[major=SE | course_id=DCD301 | syllabus_id=13782 | semester=7 | combo=SE_COM11 | title=Digital Circuit Design]
Course ID: DCD301
Title EN: Digital Circuit Design
Title VI: Thiết kế vi mạch số
Credits: 3.0
Prerequisites: ECI101
Description: This course provides students with a solid and comprehensive foundation in digital circuit design. It begins with essential concepts such as number systems, logic gates, Boolean algebra, and logic function simplification. Students then advance to designing and implementing combinational and sequential logic circuits, including multiplexers, arithmetic circuits, flip-flops, shift registers, counters, and memory elements.
The course also introduces hardware description languages (VHDL/Verilog), FPGA-based implementation, and fundamental principles of digital signal and data processing. Through these topics, students learn how hardware is described at the Register-Transfer Level (RTL) and how it is verified using testbenches and simulation.
In addition, the course provides an overview of the Digital IC Design Flow, including:
- Specification and Functional Requirements
- RTL Design using HDL
- Functional Verification and Testbench Development
- Logic Synthesis to Gate-Level Netlist
- Timing Analysis and Optimization
- Implementation on FPGA or placement & routing (for ASIC)
- Post-synthesis simulation and sign-off checks
The module emphasizes not only technical competence but also professional ethics, social responsibility, and the development of creativity and problem-solving skills. Students apply theoretical knowledge through laboratory exercises, hands-on projects, and real-world design practices.
Student tasks: - Students must attend at least 80% of contact slots in order to be accepted to the final examination.
- Student is responsible to do all exercises, assignments and labs given by instructor in class or at home and submit on time
- Use laptop in class only for learning purpose
- Promptly access to the FU FLM at https://flm.fpt.edu.vn/ for up-to-date course information
Tools: Specific Tools:
1) Simulation software
- Cadence - https://www.cadence.com/en_US/home/tools.html
- Tinkercad.com
2) Lab equipments/ Training Kits
- Tool: Oscilloscope and Function generator, multimeter
- Kit for the lab: List of components in the sheet "Electronics component list
Course type: traditional
Decision: 1318/QĐ-ĐHFPT dated 11/27/2025
Approved date: 2025-11-27
CLO1: Explain number systems, conversions, codes, and binary arithmetic.
[1] category=Assignments 1; type=on-going; weight=5.0; duration=At home; question_type=CLO1 - CLO4; grading_guide=Chapters 1–4; completion_criteria=; clos=>0
[2] category=Assignments 2; type=on-going; weight=5.0; duration=At home; question_type=CLO5 - CLO8; grading_guide=Chapters 5–8; completion_criteria=; clos=>0
[3] category=Lab1; type=on-going; weight=10.0; duration=135'; question_type=CLO1 - CLO4; grading_guide=Ch.1–3 (number systems, Boolean, K-map);; completion_criteria=; clos=>0
[4] category=Lab2; type=on-going; weight=10.0; duration=135'; question_type=CLO3, CLO5, CLO8; grading_guide=Ch.4–6 (combinational & sequential design, RTL); completion_criteria=; clos=>0
[5] category=Lab3; type=on-going; weight=10.0; duration=225'; question_type=CLO6, CLO7, CLO8; grading_guide=ch.8,9,10; completion_criteria=; clos=>0
[6] category=Progress Tests 1; type=on-going; weight=10.0; duration=30'; question_type=CLO1–CLO3; grading_guide=Chapters 1–3; completion_criteria=; clos=>0
[7] category=Progress Tests 2; type=on-going; weight=10.0; duration=30'; question_type=CLO4–CLO6; grading_guide=Chapters 4–6; completion_criteria=; clos=>0
[8] category=Final Exam; type=Final; weight=40.0; duration=60’; question_type=All CLOs; grading_guide=All chapters (Ch.1–10); both theoretical and practical aspects; completion_criteria=; clos=4
[1] desc=Digital Design with an Introduction to the Verilog HDL; author=M. Morris Mano and Michael D. Ciletti; publisher=Pearson; edition=6 th; isbn=978-0-13-454989-7; main=True; online=; note=
[2] desc=Fundamentals of Digital Logic with VHDL Design; author=Stephen Brown and Zvonko Vranesic; publisher=Mc Graw Hill; edition=4 th; isbn=978-1-260-59778-3; main=; online=; note=
[3] desc=Digital Fundamentals; author=Thomas L. Floyd; publisher=Pearson; edition=11 th; isbn=978-1-292-07598-3; main=; online=; note=
[4] desc=CMOS VLSI Design: A Circuits and Systems Perspective; author=Neil H. E. Weste, David Money Harris; publisher=Pearson; edition=4th; isbn=978-0-321-54774-3; main=; online=; note=
Session 1: Course Introduction
Chapter 1: Digital Systems and Binary Numbers
1.1 Digital Systems
1.2 Binary Numbers
1.3 Number - Base Conversions
1.4 Octal and Hexadecimal Numbers
1.5 Complements
Topic: Offline; Teaching type: CLO1; LO: IT
ITU: Textbook: Digital Design, slides, EduNext
Materials: DCD301
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 2: Chapter 1: Digital Systems and Binary Numbers (cont)
1.6 Signed Binary Numbers
1.7 Binary Codes
1.8 Binary Storage and Registers
1.9 Binary Logic
Topic: Offline; Teaching type: CLO1; LO: T
ITU: Textbook: Digital Design, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 3: Chapter 1: Digital Systems and Binary Numbers (cont)
Exercise: Conversion drills
Topic: Offline; Teaching type: CLO1–CLO6; LO: TU
ITU: Worksheet, exercises
Download: Solve problems, submit answers

Session 4: Chapter 2: Boolean Algebra and logic Gates
2.1 Introduction
2.2 Basic Definitions
2.3 Axiomatic Definition
Topic: Offline; Teaching type: CLO2; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice
CLO2: Apply Boolean algebra and minimization to design logic circuits.
Session 1: Chapter 2: Boolean Algebra and logic Gates (cont)
2.4 Theorems
2.5 Boolean Functions
2.6 Canonical and Standard Forms
Topic: Offline; Teaching type: CLO2; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 2: Chapter 2: Boolean Algebra and logic Gates (cont)
2.7 Other Logic Operations
2.8 Digital Logic Gates
2.9 Integrated Circuits
Topic: Offline; Teaching type: CLO2; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 3: Chapter 2: Boolean Algebra and logic Gates (cont)
Exercise: Boolean simplification 1
Topic: Offline; Teaching type: CLO1–CLO6; LO: TU
ITU: Worksheet, exercises
Download: Solve problems, submit answers

Session 4: Chapter 2: Boolean Algebra and logic Gates (cont)
Exercise: Boolean simplification 2
Topic: Offline; Teaching type: CLO1–CLO6; LO: TU
ITU: Worksheet, exercises
Download: Solve problems, submit answers
CLO3: Design and analyze combinational logic circuits.
Session 1: Chapter 3: Gate-Level Minimization(cont)
3.7 Other Two-Level Implementations
3.8 XOR
3.9 HDL
3.10 Truth Tables in HDL
Topic: Offline; Teaching type: CLO2; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 2: Chapter 3: Gate-Level Minimization(cont)
Exercise: Minimization practice
Topic: Offline; Teaching type: CLO1–CLO6; LO: IT
ITU: Worksheet, exercises
Download: Solve problems, submit answers

Session 3: Chapter 3: Gate-Level Minimization(cont)
Exercise: HDL practice
Topic: Offline; Teaching type: CLO1–CLO6; LO: T
ITU: Worksheet, exercises
Download: Solve problems, submit answers

Session 4: Review (Ch.1–3)
Topic: Offline; Teaching type: CLO1–CLO8; LO: T
ITU: Notes, textbook, slides
Download: Revise, ask questions
CLO4: Model and verify logic circuits using HDL.
Session 1: Progress Test 1 (Ch.1–3)
Topic: Offline; Teaching type: CLO1–CLO2; LO: TU
ITU: Exam paper
Download: Answer under exam conditions

Session 2: Lab 1.1: Number Systems
Topic: Offline; Teaching type: CLO1,CLO2; LO: TU
ITU: Lab guide, FPGA board, software
Download: Perform lab tasks, write report

Session 3: Lab 1.2: Boolean Simplification
Topic: Offline; Teaching type: CLO1,CLO2; LO: TU
ITU: Lab guide, FPGA board, software
Download: Perform lab tasks, write report

Session 4: Lab 1.3: K-map Practice
Topic: Offline; Teaching type: CLO1,CLO2; LO: TU
ITU: Lab guide, FPGA board, software
Download: Perform lab tasks, write report
CLO5: Analyze and design sequential circuits using FSMs.
Session 1: Chapter 4: Combinational logic
4.3 Analysis of Combinational Circuits
4.4 Design Procedure
4.5 Binary Adder - Subtractor
Topic: Offline; Teaching type: CLO3,CLO4; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 2: Chapter 4: Combinational logic (cont)
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
Topic: Offline; Teaching type: CLO3,CLO4; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 3: Chapter 4: Combinational logic (cont)
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
Topic: Offline; Teaching type: CLO3,CLO4; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 4: Chapter 4: Combinational logic (cont)
Exercise: Combinational circuits
4.12 HDL Models of Combinational Circuits
4.13 Behavioral Modeling
Topic: Offline; Teaching type: CLO1–CLO6; LO: T
ITU: Worksheet, exercises
Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Solve problems, submit answersRead/review and practice
CLO6: Design and implement registers and counters.
Session 1: 4.14 Writing a Simple Testbench
4.15 Logic Simulation
Topic: Offline; Teaching type: CLO3,CLO4; LO: TU
ITU: Exam paper
Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Answer under exam conditionsRead/review and practice

Session 2: Chapter 4: Combinational logic (cont)
Exercise: HDL for Combinational Logic
Topic: Offline; Teaching type: CLO3,CLO4; LO: TU
ITU: Worksheet, exercises
Download: Solve problems, submit answers

Session 3: Chapter 5: Synchronous Sequential Logic
5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
Topic: Offline; Teaching type: CLO5; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 4: Chapter 5: Synchronous Sequential Logic (cont)
5.5 Analysis of Clocked Sequential Circuits
5.6 Synthesizable HDL Models of Sequential Circuits
5.7 State Reduction and Assignment
Topic: Offline; Teaching type: CLO5; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice
CLO7: Describe memory and PLDs including FPGA resources.
Session 1: Assignment 1
Topic: Offline; Teaching type: CLO1, CLO2, CLO3, CLO4, CLO6; LO: IT
ITU: Slides:Instructional Guide
for Assignment 1
Download: Assign work to team members
Proceed to do the Assignment
Answer Edunext questions

Session 2: Chapter 5: Synchronous Sequential Logic (cont)
5.8 FSM Design Procedure
Exercise: FSM examples
Exercise: FSM practice
Topic: Offline; Teaching type: CLO1–CLO6; LO: TU
ITU: Textbook, slides, EduNext
Worksheet, exercises
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practiceSolve problems, submit answers

Session 3: Chapter 6: Registers and Counters
6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
Topic: Offline; Teaching type: CLO6; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 4: Chapter 6: Registers and Counters (cont)
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL Models
Topic: Offline; Teaching type: CLO6; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice
CLO8: Apply RTL design and HDL coding for digital systems.
Session 1: Chapter 6: Registers and Counters (cont)
Exercise: Counters practice
Topic: Offline; Teaching type: CLO1–CLO6; LO: T
ITU: Worksheet, exercises
Download: Solve problems, submit answers

Session 2: Chapter 7: Memory and Programmable logic
7.1 Introduction
7.2 RAM
7.3 Memory Decoding
7.4 Error Detection & Correction
Topic: Offline; Teaching type: CLO7; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 3: Chapter 7: Memory and Programmable logic (cont)
Exercise: Error Detection & Correction
Topic: Offline; Teaching type: CLO7; LO: TU
ITU: Worksheet, exercises
Download: Solve problems, submit answers

Session 4: Chapter 7: Memory and Programmable logic (cont)
7.5 ROM
7.6 PLA
7.7 PAL
7.8 Sequential PLDs
Topic: Offline; Teaching type: CLO7; LO: TU
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice
Session 1: Chapter 8: Design at the Register
Transfer Level
8.1 Introduction
8.2 RTL Notation
8.3 RTL Descriptions
Topic: Offline; Teaching type: CLO8; LO: TU
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 2: Chapter 8: Design at the Register (cont)
8.4 ASMs
8.5 ASMD Chart Example
8.6 HDL Example
Topic: Offline; Teaching type: CLO8; LO: TU
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 3: Chapter 8: Design at the Register (cont)
8.7 Sequential Binary Multiplier
8.8 Control Logic
8.9 HDL Description
Topic: Offline; Teaching type: CLO8; LO: TU
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 4: Chapter 8: Design at the Register (cont)
8.10 Design with Multiplexers
8.11 Race-Free Design
8.12 Latch-Free Design
8.13 System Verilog Intro
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice
Session 1: Chapter 8: Design at the Register (cont)
Exercise: RTL Modeling and ASM-Based Control Design in Digital Systems
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 2: Chapter 8: Design at the Register (cont)
Exercise: HDL Implementation and Optimization of a Sequential Binary Multiplier
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 3: Chapter 9: Asynchronous Sequential logic
9.1 Introduction
9.2 Analysis Procedure
9.3 Circuits with latches
9.4 Design Procedure
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 4: Chapter 9: Asynchronous Sequential logic (cont)
9.5 Reduction of Stateand FlowTables
9.6 Race - Free StateAssignment
9.7 Hazards
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice
Session 1: Chapter 9: Asynchronous Sequential logic (cont)
9.8 Design Example 1
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: Solve problems, submit answers

Session 2: Chapter 9: Asynchronous Sequential logic (cont)
9.8 Design Example 2
Topic: Offline; Teaching type: CLO8; LO: TU
ITU: Textbook, slides, EduNext
Download: Solve problems, submit answers

Session 3: View Assignment 1
Topic: Offline; Teaching type: CLO5, CLO6; LO: U
ITU: Slides:Instructional Guide for Assignment 1
Download: https://flm.fpt.edu.vn/gui/role/student/Students present their report and demonstrate the product.

Session 4: Assignment 2
Topic: Offline; Teaching type: CLO5, CLO6, CLO7, CLO8; LO: IT
ITU: Slides:Instructional Guide
for Assignment 2
Download: Assign work to team members
Proceed to do the Assignment
Answer Edunext questions
Session 1: Chapter 10: Digital Integrated Circuits
10.1 Introduction
10.2 Special Characteristics
10.3 Bipolar - Transistor Characteristics
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 2: Chapter 10: Digital Integrated Circuits (cont)
10.4 RTl and DTL Circuits
10.5 Transistor-Transistor Logic
10.6 Emitter - Coupled Logic
10.7 Metal - Oxide Semiconductor
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 3: Chapter 10: Digital Integrated Circuits (cont)
10.8 Complementary MOS
10.9 CMOS Transmission Gate Circuits
10.10 Switch - Level Modeling with HDL
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: https://flm.fpt.edu.vn/gui/role/student/Read/review and practice

Session 4: Chapter 10: Digital Integrated Circuits (cont)
Exercise: Mixed - Logic Design and Analysis Using RTL, TTL, and CMOS Technologies
Topic: Offline; Teaching type: CLO8; LO: T
ITU: Textbook, slides, EduNext
Download: Solve problems, submit answers
Session 1: View Assignment 2
Topic: Offline; Teaching type: CLO5, CLO6, CLO7, CLO8; LO: U
ITU: Slides:Instructional Guide for Assignment 2
Download: https://flm.fpt.edu.vn/gui/role/student/Students present their report and demonstrate the product.

Session 2: Lab 2
Lab 2.1: Combinational Circuits on FPGA
Topic: Offline; Teaching type: CLO3, CLO5, CLO7, CLO8; LO: TU
ITU: Lab guide, FPGA board, software
Download: Perform lab tasks, write report

Session 3: Lab 2.2: Sequential Circuits on FPGA
Topic: Offline; Teaching type: CLO3, CLO5, CLO7, CLO8; LO: TU
ITU: Lab guide, FPGA board, software
Download: Perform lab tasks, write report

Session 4: Lab 2.3: RTL Design Project
Topic: Offline; Teaching type: CLO3, CLO5, CLO7, CLO8; LO: TU
ITU: Lab guide, FPGA board, software
Download: Perform lab tasks, write report
Session 1: Lab 3: CMOS AND Gate design
lab 3.1 Set up the Cadence environment
Topic: Offline; Teaching type: CLO5, CLO6, CLO7, CLO8; LO: TU
ITU: Lab guide, Cedance software
Download: Perform lab tasks, write report

Session 2: Lab 3: CMOS AND Gate design
lab 3.2 Part A: Schematic design (Transistor-Level)
Topic: Offline; Teaching type: CLO5, CLO6, CLO7, CLO8; LO: TU
ITU: Lab guide, Cedance software
Download: Perform lab tasks, write report

Session 3: Lab 3: CMOS AND Gate design
lab 3.3 Part B: Simulation (ADE / Specter)
Topic: Offline; Teaching type: CLO5, CLO6, CLO7, CLO8; LO: TU
ITU: Lab guide, Cedance software
Download: Perform lab tasks, write report

Session 4: Lab 3: CMOS AND Gate design
lab 3.4 Part C: Layout Design (Layout Editor)
Topic: Offline; Teaching type: CLO5, CLO6, CLO7, CLO8; LO: TU
ITU: Lab guide, Cedance software
Download: Perform lab tasks, write report
Session 1: Lab 3: CMOS AND Gate design
lab 3.5 Part D: LVS & Extraction (Layout vs Schematic & Parasitic Extraction)
Topic: Offline; Teaching type: CLO5, CLO6, CLO7, CLO8; LO: TU
ITU: Lab guide, Cedance software
Download: Perform lab tasks, write report

Session 2: Review
Topic: Offline; Teaching type: CLO3–CLO6; LO: U
ITU: Notes, textbook, slides
Download: Revise, ask questions

Session 3: Progress Test 2 (Ch.4–8)
Topic: Offline; Teaching type: CLO3–CLO6; LO: U
ITU: Exam paper
Download: Answer under exam conditions

Session 4: Final Review & Wrap-up
Topic: Offline; Teaching type: CLO1–CLO8; LO: U
ITU: Notes, textbook, slides
Download: Revise, ask questions