Computer Organization and Architecture (CEA201)
Vietnamese title: Tổ chức và Kiến trúc máy tính
Credits: 3

Description:
This course in an introduction to computer architecture and organization. It will cover topics in both the physical design of the computer (organization) and the logical design of the computer (architecture). The main contents include the organization of a simple stored-program computer: CPU, busses and memory; Instruction sets, machine code, and assembly language; Conventions for assembly language generated by compilers; Floating-point number representation; Hardware organization of simple processors; Address translation and virtual memory; Very introductory examples of input/output devices, interrupt handling and multi-tasking systems.
Chapter covered: Computer Evolution and Performance; A Top-Level View of Computer Function and Interconnection; Cache Memory; Internal Memory; External Memory; Input/Output; Operating System Support; Instruction Sets: Characteristics and Functions; Processor Structure and Function; Reduced Instruction Set Computers; Instruction-Level Parallelism and Superscalar Processors; Parallel Processing; Multicore Computers.

Learning outcomes:
Explain the general functions and structure of a digital computer
Using AI tools and simulator tools to futher explore the main concepts
Present an overview of the evolution of computer technology from early digital computers to the latest microprocessors.
Understand the key performance issues that relate to computer design
Describe in detail the essential elements of computer organisation including internal bus, memory, Input/Output ( I/O) organisations and interfacing standards and discuss how these elements function;
Summarize, at a top level, the key functions of an operating system (OS).
Be able to apply Boolean algebra and digital logic to design and interpret complex digital circuits;
Present various types of addressing modes common in instruction sets, an essential characteristics of machine instructions, types of operands supported by typical machine instruction sets
Explain processor structure and function in details, the operations of Reduced Instruction Set Computers
Investigate, evaluate and communicate general trends in computing technologies such as Instruction-Level Parallelism and Superscalar Processors

Student tasks:
- Students must attend at least 80% of contact sessions in order to be accepted to the final examination.
- Student is responsible to do all exercises and practical given by instructor in class or at home and submit on time. Do quizzes during class.

Tools:
- Intenet
- Textbook
- AI Tools and Simulator software

Materials:
description: Computer Organization and Architecture: Design for Performance
author: William Stallings
publisher: Prentice Hall
published_date: 2012
edition: 9th (or 10th)
isbn: 978-0132936330 (9th), 978-0134101613 (10th)
description: Computer architecture : A quantitative approach
author: John L. Hennessy, David A Patterson
publisher: Morgan Kaufmann
description: http://williamstallings.com/ComputerOrganization/COA9e-Instructor/
description: http://williamstallings.com/ComputerOrganization/COA9e-student/
description: - AI Notes:https://www.https://notegpt.io/ or another AI.
- Other AI tools: ChatGPT/Copilot/Gamma
description: MARIE simulator
description: ParaCacheSimulator

Assessments:
category: Assignment
type: on-going
weight: 20.0
duration: At home
question_type: All CLOs
no_question: Option 1: Write a report, or developing assemly program
Option 2: Follow lecturer's proposal
knowledge_and_skill: Option 1: build a simple vitrual PC/other suilable activities and a report. Or Develop assemly program
Option 2: Follow lecturer's proposal
grading_guide: Basic computer components/Basic programs
note: Teachers assess their works on report
category: Exercices
type: on-going
weight: 40.0
duration: Do at home
Present in class
question_type: All CLOs
no_question: Apply AI to answer and explore the content of the subject based on the lecturer's questions and submit the result to Edunext
knowledge_and_skill: Follow lecturer's proposal on chapters
grading_guide: Studied chapters; knowledge and skills
note: Teachers assess their works on report
category: Final exam
type: Final exam
weight: 40.0
duration: 60'
no_question: Multiple choice
knowledge_and_skill: 50
grading_guide: All chapters; knowledge and skills of digital system;
note: by Exam board

Schedule:
session: - Introduction to the course.
- Chapter 1: Introduction
1.1 Organization and Architecture
learning_outcomes: IT
materials: CEA201
session: - Chapter 1: Introduction
1.2 Structure and Function
learning_outcomes: T
materials: CEA201
session: - Chapter 2: Computer Evolution and Performance
2.1 A Brief History of Computers
learning_outcomes: T
session: - Assessing exercises of chapter 1
- Chapter 2: Computer Evolution and Performance
2.2 Designing for Performance
learning_outcomes: TU
session: - Chapter 2: Computer Evolution and Performance
2.3 Multicore, MICs, and GPGPUs
learning_outcomes: T
session: - Chapter 2: Computer Evolution and Performance
2.6 Performance Assessment
learning_outcomes: T
session: - Assessing exercises of chapter 2
- Chapter 3: A Top-Level View of Computer Function and Interconnection
3.1 Computer Components
learning_outcomes: TU
session: - Chapter 3: A Top-Level View of Computer Function and Interconnection
3.2 Computer Function
learning_outcomes: T
session: - Chapter 3: A Top-Level View of Computer Function and Interconnection
3.3 Interconnection Structures
learning_outcomes: T
session: - Chapter 3: A Top-Level View of Computer Function and Interconnection
3.4 Bus Interconnection
learning_outcomes: T
session: - Assessing exercises of chapter 3
'- Chapter 4: Cache Memory
4.1 Computer Memory System Overview
learning_outcomes: TU
session: - Chapter 4: Cache Memory
4.2 Cache Memory Principles
learning_outcomes: T
session: - Chapter 4: Cache Memory
4.3 Elements of Cache Design
learning_outcomes: T
session: - Chapter 4: Cache Memory
4.3 Elements of Cache Design (cont.)
learning_outcomes: T
session: - Chapter 5: Internal Memory
5.1 Semiconductor Main Memory
learning_outcomes: T
session: - Assessing exercises of chapter 4
'- Chapter 5: Internal Memory
5.2 Error Correction
learning_outcomes: TU
session: - Chapter 5: Internal Memory
5.3 Advanced Dram Organization
learning_outcomes: T
session: - Chapter 5: Internal Memory
5.3 Advanced Dram Organization (cont)
learning_outcomes: T
session: - Assessing exercises of chapter 5
- Chapter 6: External Memory
6.1 Magnetic Disk
learning_outcomes: TU
session: - Chapter 6: External Memory
6.2 Raid
learning_outcomes: T
session: - Chapter 6: External Memory
6.2 Raid (cont)
learning_outcomes: T
session: - Chapter 6: External Memory
6.3 Solid State Drives
learning_outcomes: T
session: - Chapter 7: Input/Output
7.1 External Devices
7.2 I/O Modules
learning_outcomes: T
session: - Chapter 7 Input/Output
7.3 Programmed I/O
learning_outcomes: T
session: - Assessing exercises of chapter 6
- Chapter 7 Input/Output
7.4 Interrupt-Driven I/O
learning_outcomes: TU
session: - Chapter 7: Input/Output
7.6 I/O Channels and Processors
learning_outcomes: T
session: Chapter 8: Operating System Support
8.1 Operating System Overview
learning_outcomes: T
session: - Assessing exercises of chapter 7
- Chapter 8: Operating System Support
8.1 Operating System Overview (cont)
learning_outcomes: TU
session: - Chapter 8: Operating System Support
8.2 Scheduling
learning_outcomes: T
session: - Chapter 8: Operating System Support
8.3 Memory Management
learning_outcomes: T
session: - Assessing exercises of chapter 8
- Chapter 11: Digital Logic
11.1 Boolean Algebra
11.2 Gates
learning_outcomes: TU
session: - Chapter 11: Digital Logic
11.3 Combinational Circuit
learning_outcomes: T
session: - Chapter 12: Instruction Sets: Characteristics and Functions
12.1 Machine Instruction Characteristics
learning_outcomes: T
session: - Assessing exercises of chapter 11
- Chapter 12: Instruction Sets: Characteristics and Functions
12.2 Types of Operands
learning_outcomes: TU
session: - Chapter 12: Instruction Sets: Characteristics and Functions cont.
12.4 Types of Operations
learning_outcomes: T
session: - Chapter 12: Instruction Sets: Characteristics and Functions cont.
12.4 Types of Operations
learning_outcomes: T
session: - Assessing exercises of chapter 12
- Chapter 13: Instruction Sets: Addressing Modes and Formats
13.1 Addressing Modes
learning_outcomes: TU
session: - Chapter 13: Instruction Sets: Addressing Modes and Formats
13.3 Instruction Formats
13.5 Assembly Language
learning_outcomes: T
session: Practical Assembly Laguage
learning_outcomes: U
session: Practical Assembly Laguage
learning_outcomes: U
session: Practical Assembly Laguage
learning_outcomes: U
session: Practical Assembly Laguage
learning_outcomes: U
session: Practical Assembly Laguage
learning_outcomes: U
session: Practical Assembly Laguage
learning_outcomes: U
session: Assignments introduction
learning_outcomes: TU
session: - Assessing exercises of chapter 13
- Chapter 14: Processor Structure and Function
14.1 Processor Organization
learning_outcomes: TU
session: - Chapter 14: Processor Structure and Function
14.2 Register Organization
learning_outcomes: T
session: - Chapter 14: Processor Structure and Function
14.3 Instruction Cycle
learning_outcomes: T
session: - Chapter 14: Processor Structure and Function
14.4 Instruction Pipelining
learning_outcomes: T
session: - Chapter 15: Reduced Instruction Set Computers
15.1 Instruction Execution Characteristics
15.2 The Use of a Large Register File
learning_outcomes: T
session: - Chapter 15: Reduced Instruction Set Computers
15.3 Compiler-Based Register Optimization
15.4 Reduced Instruction Set Architecture
learning_outcomes: T
session: - Assessing exercises of chapter 14 & 15
learning_outcomes: TU
session: - Chapter 16: Instruction-Level Parallelism and Superscalar Processors
16.1 Overview
16.2 Design Issues
learning_outcomes: T
session: - Chapter 17: Parallel Processing
17.1 Multiple Processor Organizations
17.2 Symmetric Multiprocessors
learning_outcomes: T
session: - Assessing exercises of chapter 16
- Chapter 17: Parallel Processing
17.3 Cache Coherence and the MESI Protocol
17.4 Multithreading and Chip Multiprocessors
learning_outcomes: TU
session: - Chapter 18: Multicore Computers
18.1 Hardware Performance Issues
18.2 Software Performance Issues
learning_outcomes: T
session: - Chapter 18: Multicore Computers
18.3 Multicore Organization
learning_outcomes: T
session: - Assessing exercises of chapter 17 & 18
learning_outcomes: TU
session: - Assessing assigments
Review 1
learning_outcomes: U
session: - Assessing assigments
Review 2
learning_outcomes: U