Digital Circuit Design (DCD301)
Vietnamese title: Thiết kế vi mạch số
Credits: 3
Prerequisites: ECI101

Description:
This course provides students with a solid and comprehensive foundation in digital circuit design. It begins with essential concepts such as number systems, logic gates, Boolean algebra, and logic function simplification. Students then advance to designing and implementing combinational and sequential logic circuits, including multiplexers, arithmetic circuits, flip-flops, shift registers, counters, and memory elements.
The course also introduces hardware description languages (VHDL/Verilog), FPGA-based implementation, and fundamental principles of digital signal and data processing. Through these topics, students learn how hardware is described at the Register-Transfer Level (RTL) and how it is verified using testbenches and simulation.
In addition, the course provides an overview of the Digital IC Design Flow, including:
- Specification and Functional Requirements
- RTL Design using HDL
- Functional Verification and Testbench Development
- Logic Synthesis to Gate-Level Netlist
- Timing Analysis and Optimization
- Implementation on FPGA or placement & routing (for ASIC)
- Post-synthesis simulation and sign-off checks
The module emphasizes not only technical competence but also professional ethics, social responsibility, and the development of creativity and problem-solving skills. Students apply theoretical knowledge through laboratory exercises, hands-on projects, and real-world design practices.

Learning outcomes:
Explain number systems, conversions, codes, and binary arithmetic.
Apply Boolean algebra and minimization to design logic circuits.
Design and analyze combinational logic circuits.
Model and verify logic circuits using HDL.
Analyze and design sequential circuits using FSMs.
Design and implement registers and counters.
Describe memory and PLDs including FPGA resources.
Apply RTL design and HDL coding for digital systems.

Student tasks:
- Students must attend at least 80% of contact slots in order to be accepted to the final examination.
- Student is responsible to do all exercises, assignments and labs given by instructor in class or at home and submit on time
- Use laptop in class only for learning purpose
- Promptly access to the FU FLM at https://flm.fpt.edu.vn/ for up-to-date course information

Tools:
Specific Tools:
1) Simulation software
- Cadence - https://www.cadence.com/en_US/home/tools.html
- Tinkercad.com
2) Lab equipments/ Training Kits
- Tool: Oscilloscope and Function generator, multimeter
- Kit for the lab: List of components in the sheet "Electronics component list

Materials:
description: Digital Design with an Introduction to the Verilog HDL
author: M. Morris Mano and Michael D. Ciletti
publisher: Pearson
published_date: 2018
edition: 6 th
isbn: 978-0-13-454989-7
description: Fundamentals of Digital Logic with VHDL Design
author: Stephen Brown and Zvonko Vranesic
publisher: Mc Graw Hill
published_date: 2023
edition: 4 th
isbn: 978-1-260-59778-3
description: Digital Fundamentals
author: Thomas L. Floyd
publisher: Pearson
published_date: 2015
edition: 11 th
isbn: 978-1-292-07598-3
description: CMOS VLSI Design: A Circuits and Systems Perspective
author: Neil H. E. Weste, David Money Harris
publisher: Pearson
published_date: 2011
edition: 4th
isbn: 978-0-321-54774-3

Assessments:
category: Assignments 1
type: on-going
weight: 5.0
duration: At home
question_type: CLO1 - CLO4
no_question: Homework, mini-projects, and optionally the constructivist approach as proposed by the lecturer.
knowledge_and_skill: by instructor
grading_guide: Chapters 1–4
note: Individual or team work, guided by instructor, submission by a given deadline
category: Assignments 2
type: on-going
weight: 5.0
duration: At home
question_type: CLO5 - CLO8
no_question: Homework, mini-projects, and optionally the constructivist approach as proposed by the lecturer.
knowledge_and_skill: by instructor
grading_guide: Chapters 5–8
note: Individual or team work, guided by instructor, submission by a given deadline
category: Lab1
type: on-going
weight: 10.0
duration: 135'
question_type: CLO1 - CLO4
no_question: Electronic Circuit Design, Analysis and Implementation
knowledge_and_skill: by instructor
grading_guide: Ch.1–3 (number systems, Boolean, K-map);
note: Supervised by instructor
category: Lab2
type: on-going
weight: 10.0
duration: 135'
question_type: CLO3, CLO5, CLO8
no_question: Electronic Circuit Design, Analysis and Implementation
knowledge_and_skill: by instructor
grading_guide: Ch.4–6 (combinational & sequential design, RTL)
note: Supervised by instructor
category: Lab3
type: on-going
weight: 10.0
duration: 225'
question_type: CLO6, CLO7, CLO8
no_question: Electronic Circuit Design, Analysis and Implementation
knowledge_and_skill: by instructor
grading_guide: ch.8,9,10
note: Individual or team work, guided by instructor, report submission
category: Progress Tests 1
type: on-going
weight: 10.0
duration: 30'
question_type: CLO1–CLO3
no_question: Multiple choice + short answer
knowledge_and_skill: 20
grading_guide: Chapters 1–3
note: in class, by instructor
category: Progress Tests 2
type: on-going
weight: 10.0
duration: 30'
question_type: CLO4–CLO6
no_question: Multiple choice + short answer
knowledge_and_skill: 20
grading_guide: Chapters 4–6
note: in class, by instructor
category: Final Exam
type: Final
weight: 40.0
duration: 60’
question_type: All CLOs
no_question: Multiple choices
Marked by Computer
knowledge_and_skill: 50
grading_guide: All chapters (Ch.1–10); both theoretical and practical aspects
note: By Exam board

Schedule:
session: Course Introduction
Chapter 1: Digital Systems and Binary Numbers
1.1 Digital Systems
1.2 Binary Numbers
1.3 Number - Base Conversions
1.4 Octal and Hexadecimal Numbers
1.5 Complements
learning_outcomes: IT
materials: DCD301
session: Chapter 1: Digital Systems and Binary Numbers (cont)
1.6 Signed Binary Numbers
1.7 Binary Codes
1.8 Binary Storage and Registers
1.9 Binary Logic
learning_outcomes: T
session: Chapter 1: Digital Systems and Binary Numbers (cont)
Exercise: Conversion drills
learning_outcomes: TU
session: Chapter 2: Boolean Algebra and logic Gates
2.1 Introduction
2.2 Basic Definitions
2.3 Axiomatic Definition
learning_outcomes: T
session: Chapter 2: Boolean Algebra and logic Gates (cont)
2.4 Theorems
2.5 Boolean Functions
2.6 Canonical and Standard Forms
learning_outcomes: T
session: Chapter 2: Boolean Algebra and logic Gates (cont)
2.7 Other Logic Operations
2.8 Digital Logic Gates
2.9 Integrated Circuits
learning_outcomes: T
session: Chapter 2: Boolean Algebra and logic Gates (cont)
Exercise: Boolean simplification 1
learning_outcomes: TU
session: Chapter 2: Boolean Algebra and logic Gates (cont)
Exercise: Boolean simplification 2
learning_outcomes: TU
session: Chapter 3: Gate-Level Minimization(cont)
3.7 Other Two-Level Implementations
3.8 XOR
3.9 HDL
3.10 Truth Tables in HDL
learning_outcomes: T
session: Chapter 3: Gate-Level Minimization(cont)
Exercise: Minimization practice
learning_outcomes: IT
session: Chapter 3: Gate-Level Minimization(cont)
Exercise: HDL practice
learning_outcomes: T
session: Review (Ch.1–3)
learning_outcomes: T
session: Progress Test 1 (Ch.1–3)
learning_outcomes: TU
session: Lab 1.1: Number Systems
learning_outcomes: TU
session: Lab 1.2: Boolean Simplification
learning_outcomes: TU
session: Lab 1.3: K-map Practice
learning_outcomes: TU
session: Chapter 4: Combinational logic
4.3 Analysis of Combinational Circuits
4.4 Design Procedure
4.5 Binary Adder - Subtractor
learning_outcomes: T
session: Chapter 4: Combinational logic (cont)
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
learning_outcomes: T
session: Chapter 4: Combinational logic (cont)
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
learning_outcomes: T
session: Chapter 4: Combinational logic (cont)
Exercise: Combinational circuits
4.12 HDL Models of Combinational Circuits
4.13 Behavioral Modeling
learning_outcomes: T
session: 4.14 Writing a Simple Testbench
4.15 Logic Simulation
learning_outcomes: TU
session: Chapter 4: Combinational logic (cont)
Exercise: HDL for Combinational Logic
learning_outcomes: TU
session: Chapter 5: Synchronous Sequential Logic
5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
learning_outcomes: T
session: Chapter 5: Synchronous Sequential Logic (cont)
5.5 Analysis of Clocked Sequential Circuits
5.6 Synthesizable HDL Models of Sequential Circuits
5.7 State Reduction and Assignment
learning_outcomes: T
session: Assignment 1
learning_outcomes: IT
session: Chapter 5: Synchronous Sequential Logic (cont)
5.8 FSM Design Procedure
Exercise: FSM examples
Exercise: FSM practice
learning_outcomes: TU
session: Chapter 6: Registers and Counters
6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
learning_outcomes: T
session: Chapter 6: Registers and Counters (cont)
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL Models
learning_outcomes: T
session: Chapter 6: Registers and Counters (cont)
Exercise: Counters practice
learning_outcomes: T
session: Chapter 7: Memory and Programmable logic
7.1 Introduction
7.2 RAM
7.3 Memory Decoding
7.4 Error Detection & Correction
learning_outcomes: T
session: Chapter 7: Memory and Programmable logic (cont)
Exercise: Error Detection & Correction
learning_outcomes: TU
session: Chapter 7: Memory and Programmable logic (cont)
7.5 ROM
7.6 PLA
7.7 PAL
7.8 Sequential PLDs
learning_outcomes: TU
session: Chapter 8: Design at the Register
Transfer Level
8.1 Introduction
8.2 RTL Notation
8.3 RTL Descriptions
learning_outcomes: TU
session: Chapter 8: Design at the Register (cont)
8.4 ASMs
8.5 ASMD Chart Example
8.6 HDL Example
learning_outcomes: TU
session: Chapter 8: Design at the Register (cont)
8.7 Sequential Binary Multiplier
8.8 Control Logic
8.9 HDL Description
learning_outcomes: TU
session: Chapter 8: Design at the Register (cont)
8.10 Design with Multiplexers
8.11 Race-Free Design
8.12 Latch-Free Design
8.13 System Verilog Intro
learning_outcomes: T
session: Chapter 8: Design at the Register (cont)
Exercise: RTL Modeling and ASM-Based Control Design in Digital Systems
learning_outcomes: T
session: Chapter 8: Design at the Register (cont)
Exercise: HDL Implementation and Optimization of a Sequential Binary Multiplier
learning_outcomes: T
session: Chapter 9: Asynchronous Sequential logic
9.1 Introduction
9.2 Analysis Procedure
9.3 Circuits with latches
9.4 Design Procedure
learning_outcomes: T
session: Chapter 9: Asynchronous Sequential logic (cont)
9.5 Reduction of Stateand FlowTables
9.6 Race - Free StateAssignment
9.7 Hazards
learning_outcomes: T
session: Chapter 9: Asynchronous Sequential logic (cont)
9.8 Design Example 1
learning_outcomes: T
session: Chapter 9: Asynchronous Sequential logic (cont)
9.8 Design Example 2
learning_outcomes: TU
session: View Assignment 1
learning_outcomes: U
session: Assignment 2
learning_outcomes: IT
session: Chapter 10: Digital Integrated Circuits
10.1 Introduction
10.2 Special Characteristics
10.3 Bipolar - Transistor Characteristics
learning_outcomes: T
session: Chapter 10: Digital Integrated Circuits (cont)
10.4 RTl and DTL Circuits
10.5 Transistor-Transistor Logic
10.6 Emitter - Coupled Logic
10.7 Metal - Oxide Semiconductor
learning_outcomes: T
session: Chapter 10: Digital Integrated Circuits (cont)
10.8 Complementary MOS
10.9 CMOS Transmission Gate Circuits
10.10 Switch - Level Modeling with HDL
learning_outcomes: T
session: Chapter 10: Digital Integrated Circuits (cont)
Exercise: Mixed - Logic Design and Analysis Using RTL, TTL, and CMOS Technologies
learning_outcomes: T
session: View Assignment 2
learning_outcomes: U
session: Lab 2
Lab 2.1: Combinational Circuits on FPGA
learning_outcomes: TU
session: Lab 2.2: Sequential Circuits on FPGA
learning_outcomes: TU
session: Lab 2.3: RTL Design Project
learning_outcomes: TU
session: Lab 3: CMOS AND Gate design
lab 3.1 Set up the Cadence environment
learning_outcomes: TU
session: Lab 3: CMOS AND Gate design
lab 3.2 Part A: Schematic design (Transistor-Level)
learning_outcomes: TU
session: Lab 3: CMOS AND Gate design
lab 3.3 Part B: Simulation (ADE / Specter)
learning_outcomes: TU
session: Lab 3: CMOS AND Gate design
lab 3.4 Part C: Layout Design (Layout Editor)
learning_outcomes: TU
session: Lab 3: CMOS AND Gate design
lab 3.5 Part D: LVS & Extraction (Layout vs Schematic & Parasitic Extraction)
learning_outcomes: TU
session: Review
learning_outcomes: U
session: Progress Test 2 (Ch.4–8)
learning_outcomes: U
session: Final Review & Wrap-up
learning_outcomes: U