CVE-2022-31169 (Rust, published 2022-07-22T04:15Z)
Description: value: Wasmtime is a standalone runtime for WebAssembly. There is a bug in Wasmtime's code generator, Cranelift, for AArch64 targets where constant divisors can result in incorrect division results at runtime. This affects Wasmtime prior to version 0.38.2 and Cranelift prior to 0.85.2. This issue only affects the AArch64 platform. Other platforms are not affected. The translation rules for constants did not take into account whether sign or zero-extension should happen which resulted in an incorrect value being placed into a register when a division was encountered. The impact of this bug is that programs executing within the WebAssembly sandbox would not behave according to the WebAssembly specification. This means that it is hypothetically possible for execution within the sandbox to go awry and WebAssembly programs could produce unexpected results. This should not impact hosts executing WebAssembly but does affect the correctness of guest programs. This bug has been patched in Wasmtime version 0.38.2 and cranelift-codegen 0.85.2. There are no known workarounds.
Severity: nan (CVSS v3 base score: 7.5)
Weakness: CWE-682 \u2014 Incorrect Calculation
The product performs a calculation that generates incorrect or unintended results that are later used in security-critical decisions or resource management.
Repository: https://github.com/bytecodealliance/wasmtime
Files changed:
cranelift/codegen/src/isa/aarch64/inst.isle
cranelift/codegen/src/isa/aarch64/inst/imms.rs
cranelift/codegen/src/isa/aarch64/lower.isle
cranelift/codegen/src/isa/aarch64/lower/isle.rs
cranelift/filetests/filetests/isa/aarch64/arithmetic.clif
cranelift/filetests/filetests/runtests/arithmetic.clif
Commit message: Merge pull request from GHSA-7f6x-jwh5-m9r4

Copyright (c) 2022, Arm Limited.

Vulnerable code:
(decl move_wide_const_from_u64 (MoveWideConst) u64)
(extern extractor move_wide_const_from_u64 move_wide_const_from_u64)

(decl move_wide_const_from_negated_u64 (MoveWideConst) u64)
(extern extractor move_wide_const_from_negated_u64 move_wide_const_from_negated_u64)

(decl imm (Type u64) Reg)

;; 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVZ
(rule (imm (integral_ty _ty) (move_wide_const_from_u64 n))
      (movz n (OperandSize.Size64)))

;; 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVN
(rule (imm (integral_ty _ty) (move_wide_const_from_negated_u64 n))
      (movn n (OperandSize.Size64)))

;; Weird logical-instruction immediate in ORI using zero register
(rule (imm (integral_ty _ty) k)
      (if-let n (imm_logic_from_u64 $I64 k))
      (orr_imm $I64 (zero_reg) n))

(decl load_constant64_full (u64) Reg)
;; Fallback for integral 64-bit constants that uses lots of `movk`
(rule (imm (integral_ty _ty) n)
      (load_constant64_full n))
      (imm ty n))
      (imm ty 0))
      (imm ty 1))
      (imm ty 0))
      (imm ty n))
      (a64_sdiv $I64 (put_in_reg_sext64 x) (imm ty y)))
      (imm ty n))
      (value_regs (put_in_reg_zext64 x) (imm $I64 0)))
      (value_regs (mov_from_vec (put_in_reg vec) lane (vector_size in)) (imm $I64 0)))
            (neg_amt Reg (sub $I64 (imm $I64 128) amt))
            (neg_amt Reg (sub $I64 (imm $I64 128) amt))
        (value_regs (madd $I64 lo_clz tmp hi_clz) (imm $I64 0))))
        (value_regs (add $I64 maybe_lo hi_cls) (imm $I64 0))))
            (dst_hi Reg (imm $I64 0)))
        (value_regs (mov_from_vec added 0 (VectorSize.Size8x16)) (imm $I64 0))))
    fn move_wide_const_from_u64(&mut self, n: u64) -> Option<MoveWideConst> {
        MoveWideConst::maybe_from_u64(n)
    }

    fn move_wide_const_from_negated_u64(&mut self, n: u64) -> Option<MoveWideConst> {
        MoveWideConst::maybe_from_u64(!n)
    }

        let ty = if ty.bits() < 32 { I32 } else { ty };
    fn load_constant64_full(&mut self, value: u64) -> Reg {
        let rd = self.temp_writable_reg(I64);

;   orr x3, xzr, #2
;   orr x5, xzr, #2
;   orr x5, xzr, #2
;   orr x3, xzr, #2

Fixed code:
;; Type of extension performed by an immediate helper
(type ImmExtend
  (enum
    (Sign)
    (Zero)))

;; Arguments:
;; * Immediate type
;; * Way to extend the immediate value to the full width of the destination
;;   register
;; * Immediate value - only the bits that fit within the type are used and
;;   extended, while the rest are ignored
;;
;; Note that, unlike the convention in the AArch64 backend, this helper leaves
;; all bits in the destination register in a defined state, i.e. smaller types
;; such as `I8` are either sign- or zero-extended.
(decl imm (Type ImmExtend u64) Reg)

;; Weird logical-instruction immediate in ORI using zero register; to simplify,
;; we only match when we are zero-extending the value.
(rule (imm (integral_ty ty) (ImmExtend.Zero) k)
      (if-let n (imm_logic_from_u64 ty k))
      (orr_imm ty (zero_reg) n))

(decl load_constant64_full (Type ImmExtend u64) Reg)
;; Fallback for integral 64-bit constants
(rule (imm (integral_ty ty) extend n)
      (load_constant64_full ty extend n))

    pub fn zero() -> MoveWideConst {
        MoveWideConst { bits: 0, shift: 0 }
    }
      (imm ty (ImmExtend.Zero) n))
      (imm ty (ImmExtend.Zero) 0))
      (imm ty (ImmExtend.Zero) 1))
      (imm ty (ImmExtend.Zero) 0))
      (imm ty (ImmExtend.Zero) n))
      (a64_sdiv $I64 (put_in_reg_sext64 x) (imm ty (ImmExtend.Sign) y)))
      (imm ty (ImmExtend.Sign) n))
      (value_regs (put_in_reg_zext64 x) (imm $I64 (ImmExtend.Zero) 0)))
      (value_regs (mov_from_vec (put_in_reg vec) lane (vector_size in)) (imm $I64 (ImmExtend.Zero) 0)))
            (neg_amt Reg (sub $I64 (imm $I64 (ImmExtend.Zero) 128) amt))
            (neg_amt Reg (sub $I64 (imm $I64 (ImmExtend.Zero) 128) amt))
        (value_regs (madd $I64 lo_clz tmp hi_clz) (imm $I64 (ImmExtend.Zero) 0))))
        (value_regs (add $I64 maybe_lo hi_cls) (imm $I64 (ImmExtend.Zero) 0))))
            (dst_hi Reg (imm $I64 (ImmExtend.Zero) 0)))
        (value_regs (mov_from_vec added 0 (VectorSize.Size8x16)) (imm $I64 (ImmExtend.Zero) 0))))
        let ty = if ty.bits() < 32 { I32 } else { ty };
    fn load_constant64_full(
        &mut self,
        ty: Type,
        extend: &generated_code::ImmExtend,
        value: u64,
    ) -> Reg {
        let bits = ty.bits();
        let value = if bits < 64 {
            if *extend == generated_code::ImmExtend::Sign {
                let shift = 64 - bits;
                let value = value as i64;

                ((value << shift) >> shift) as u64
            } else {
                value & !(u64::MAX << bits)
            }
        } else {
            value
        };
        let rd = self.temp_writable_reg(I64);

        if value == 0 {
            self.emit(&MInst::MovWide {
                op: MoveWideOp::MovZ,
                rd,
                imm: MoveWideConst::zero(),
                size: OperandSize::Size64,
            });
            return rd.to_reg();
        } else if value == u64::MAX {
            self.emit(&MInst::MovWide {
                op: MoveWideOp::MovN,
                rd,
                imm: MoveWideConst::zero(),
                size: OperandSize::Size64,
            });
            return rd.to_reg();
        };

;   movz w3, #2
;   movz w5, #2
;   orr w5, wzr, #2
;   movz w3, #2
function %sdiv_i64_const(i64) -> i64 {
block0(v0: i64):
    v1 = iconst.i64 -2
    v2 = sdiv v0, v1
    return v2
}
; run: %sdiv_i64_const(0) == 0
; run: %sdiv_i64_const(-1) == 0
; run: %sdiv_i64_const(0xFFFFFFFF_FFFFFFFE) == 1

function %sdiv_i32_const(i32) -> i32 {
block0(v0: i32):
    v1 = iconst.i32 -2
    v2 = sdiv v0, v1
    return v2
}
; run: %sdiv_i32_const(0) == 0
; run: %sdiv_i32_const(-1) == 0
; run: %sdiv_i32_const(0xFFFFFFFE) == 1

function %sdiv_i16_const(i16) -> i16 {
block0(v0: i16):
    v1 = iconst.i16 -2
    v2 = sdiv v0, v1
    return v2
}
; run: %sdiv_i16_const(0) == 0
; run: %sdiv_i16_const(-1) == 0
; run: %sdiv_i16_const(0xFFFE) == 1

function %sdiv_i8_const(i8) -> i8 {
block0(v0: i8):
    v1 = iconst.i8 -2
    v2 = sdiv v0, v1
    return v2
}
; run: %sdiv_i8_const(0) == 0
; run: %sdiv_i8_const(-1) == 0
; run: %sdiv_i8_const(0xFE) == 1
function %udiv_i64_const(i64) -> i64 {
block0(v0: i64):
    v1 = iconst.i64 -2
    v2 = udiv v0, v1
    return v2
}
; run: %udiv_i64_const(0) == 0
; run: %udiv_i64_const(-1) == 1
; run: %udiv_i64_const(0xFFFFFFFF_FFFFFFFE) == 1

function %udiv_i32_const(i32) -> i32 {
block0(v0: i32):
    v1 = iconst.i32 -2
    v2 = udiv v0, v1
    return v2
}
; run: %udiv_i32_const(0) == 0
; run: %udiv_i32_const(-1) == 1
; run: %udiv_i32_const(0xFFFFFFFE) == 1

function %udiv_i16_const(i16) -> i16 {
block0(v0: i16):
    v1 = iconst.i16 -2
    v2 = udiv v0, v1
    return v2
}
; run: %udiv_i16_const(0) == 0
; run: %udiv_i16_const(-1) == 1
; run: %udiv_i16_const(0xFFFE) == 1


function %udiv_i8_const(i8) -> i8 {
block0(v0: i8):
    v1 = iconst.i8 -2
    v2 = udiv v0, v1
    return v2
}
; run: %udiv_i8_const(0) == 0
; run: %udiv_i8_const(-1) == 1
; run: %udiv_i8_const(0xFE) == 1