Repository: nodejs/node
Pull request: deps: V8: cherry-pick 2abc61361dd4

Original commit message:

    Fix scratch registers passed to mtvsrdd

    `ra` cannot be r0 as it will be interpreted as Operand(0)

    Change-Id: Idce58191f9d3578dc91dc4aa3872a0bf2939d8b3
    Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/6936113
    Commit-Queue: Milad Farazmand <mfarazma@ibm.com>
    Reviewed-by: Junliang Yan <junyan1@ibm.com>
    Cr-Commit-Position: refs/heads/main@{#102388}

Refs: https://github.com/v8/v8/commit/2abc61361dd4452f25de96b9d1241ed9f51bd202
Refs: https://github.com/nodejs/node/pull/59605#issuecomment-3266587252
Refs: https://github.com/nodejs/undici/pull/4530

---

It turned out that https://github.com/nodejs/llparse/pull/73 / undici 7.15.0 uncovered a bug on Power which has been addressed by this cherry-pick. It will unblock re-enabling SIMD in undici on Power (i.e. partially undoing https://github.com/nodejs/undici/pull/4530).

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Changed files:
filename: common.gypi
patch: @@ -38,7 +38,7 @@
 
     # Reset this number to 0 on major V8 upgrades.
     # Increment by one for each non-official patch applied to deps/v8.
-    'v8_embedder_string': '-node.8',
+    'v8_embedder_string': '-node.9',
 
     ##### V8 defaults for Node.js #####
 

filename: deps/v8/src/codegen/ppc/macro-assembler-ppc.cc
patch: @@ -3981,6 +3981,7 @@ void MacroAssembler::I64x2Mul(Simd128Register dst, Simd128Register src1,
   if (CpuFeatures::IsSupported(PPC_10_PLUS)) {
     vmulld(dst, src1, src2);
   } else {
+    DCHECK(scratch1 != r0);
     Register scratch_1 = scratch1;
     Register scratch_2 = scratch2;
     for (int i = 0; i < 2; i++) {
@@ -4333,6 +4334,7 @@ void MacroAssembler::I8x16BitMask(Register dst, Simd128Register src,
   if (CpuFeatures::IsSupported(PPC_10_PLUS)) {
     vextractbm(dst, src);
   } else {
+    DCHECK(scratch1 != r0);
     mov(scratch1, Operand(0x8101820283038));
     mov(scratch2, Operand(0x4048505860687078));
     mtvsrdd(scratch3, scratch1, scratch2);
@@ -4385,6 +4387,7 @@ void MacroAssembler::I8x16Shuffle(Simd128Register dst, Simd128Register src1,
                                   Simd128Register src2, uint64_t high,
                                   uint64_t low, Register scratch1,
                                   Register scratch2, Simd128Register scratch3) {
+  DCHECK(scratch2 != r0);
   mov(scratch1, Operand(low));
   mov(scratch2, Operand(high));
   mtvsrdd(scratch3, scratch2, scratch1);
@@ -4673,6 +4676,7 @@ void MacroAssembler::S128Not(Simd128Register dst, Simd128Register src) {
 
 void MacroAssembler::S128Const(Simd128Register dst, uint64_t high, uint64_t low,
                                Register scratch1, Register scratch2) {
+  DCHECK(scratch2 != r0);
   mov(scratch1, Operand(low));
   mov(scratch2, Operand(high));
   mtvsrdd(dst, scratch2, scratch1);

filename: deps/v8/src/compiler/backend/ppc/code-generator-ppc.cc
patch: @@ -2743,7 +2743,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     }
     case kPPC_I8x16BitMask: {
-      __ I8x16BitMask(i.OutputRegister(), i.InputSimd128Register(0), r0, ip,
+      __ I8x16BitMask(i.OutputRegister(), i.InputSimd128Register(0), ip, r0,
                       kScratchSimd128Reg);
       break;
     }

filename: deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc-inl.h
patch: @@ -2861,7 +2861,7 @@ void LiftoffAssembler::emit_v128_anytrue(LiftoffRegister dst,
 
 void LiftoffAssembler::emit_i8x16_bitmask(LiftoffRegister dst,
                                           LiftoffRegister src) {
-  I8x16BitMask(dst.gp(), src.fp().toSimd(), r0, ip, kScratchSimd128Reg);
+  I8x16BitMask(dst.gp(), src.fp().toSimd(), ip, r0, kScratchSimd128Reg);
 }
 
 void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,