-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Expr.lean
theorem go_denote_eq (aig : AIG BVBit) (expr : BVExpr w) (assign : Assignment) :
    ∀ (idx : Nat) (hidx : idx < w),
        ⟦(go aig expr).val.aig, (go aig expr).val.vec.get idx hidx, assign.toAIGAssignment⟧
          =
        (expr.eval assign).getLsbD idx

Proof state:
case signExtend.inl
w : Nat
assign : Assignment
originalWidth v : Nat
inner : BVExpr originalWidth
ih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < originalWidth),
    ⟦assign.toAIGAssignment, { aig := (go aig inner).val.aig, ref := (go aig inner).val.vec.get idx hidx }⟧ =
      (eval assign inner).getLsbD idx
aig : AIG BVBit
idx : Nat
hidx : idx < v
res : RefVecEntry BVBit v
hgo : blastZeroExtend (go aig inner).1.aig { w := originalWidth, vec := (go aig inner).1.vec } = res
this : 0 ≤ originalWidth
heq : 0 = originalWidth
⊢ ⟦assign.toAIGAssignment,
      { aig := (blastZeroExtend (go aig inner).1.aig { w := originalWidth, vec := (go aig inner).1.vec }).aig,
        ref :=
          (blastZeroExtend (go aig inner).1.aig { w := originalWidth, vec := (go aig inner).1.vec }).vec.get idx
            hidx }⟧ =
    (BitVec.signExtend v (eval assign inner)).getLsbD idx

Tactic:
rw [BitVec.signExtend_eq_setWidth_of_msb_false]

Result:
case signExtend.inl
w : Nat
assign : Assignment
originalWidth v : Nat
inner : BVExpr originalWidth
ih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < originalWidth),
    ⟦assign.toAIGAssignment, { aig := (go aig inner).val.aig, ref := (go aig inner).val.vec.get idx hidx }⟧ =
      (eval assign inner).getLsbD idx
aig : AIG BVBit
idx : Nat
hidx : idx < v
res : RefVecEntry BVBit v
hgo : blastZeroExtend (go aig inner).1.aig { w := originalWidth, vec := (go aig inner).1.vec } = res
this : 0 ≤ originalWidth
heq : 0 = originalWidth
⊢ ⟦assign.toAIGAssignment,
      { aig := (blastZeroExtend (go aig inner).1.aig { w := originalWidth, vec := (go aig inner).1.vec }).aig,
        ref :=
          (blastZeroExtend (go aig inner).1.aig { w := originalWidth, vec := (go aig inner).1.vec }).vec.get idx
            hidx }⟧ =
    (BitVec.setWidth v (eval assign inner)).getLsbD idx

case signExtend.inl
w : Nat
assign : Assignment
originalWidth v : Nat
inner : BVExpr originalWidth
ih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < originalWidth),
    ⟦assign.toAIGAssignment, { aig := (go aig inner).val.aig, ref := (go aig inner).val.vec.get idx hidx }⟧ =
      (eval assign inner).getLsbD idx
aig : AIG BVBit
idx : Nat
hidx : idx < v
res : RefVecEntry BVBit v
hgo : blastZeroExtend (go aig inner).1.aig { w := originalWidth, vec := (go aig inner).1.vec } = res
this : 0 ≤ originalWidth
heq : 0 = originalWidth
⊢ (eval assign inner).msb = false

Proof state:
case bin.mul
w : Nat
assign : Assignment
w✝ : Nat
lhs rhs : BVExpr w✝
lih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := (go aig lhs).val.aig, ref := (go aig lhs).val.vec.get idx hidx }⟧ =
      (eval assign lhs).getLsbD idx
rih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := (go aig rhs).val.aig, ref := (go aig rhs).val.vec.get idx hidx }⟧ =
      (eval assign rhs).getLsbD idx
aig : AIG BVBit
idx : Nat
hidx : idx < w✝
⊢ ⟦assign.toAIGAssignment,
      {
        aig :=
          (blastMul (go (go aig lhs).1.aig rhs).1.aig
              { lhs := (go aig lhs).1.vec.cast ⋯, rhs := (go (go aig lhs).1.aig rhs).1.vec }).aig,
        ref :=
          (blastMul (go (go aig lhs).1.aig rhs).1.aig
                  { lhs := (go aig lhs).1.vec.cast ⋯, rhs := (go (go aig lhs).1.aig rhs).1.vec }).vec.get
            idx hidx }⟧ =
    (eval assign lhs * eval assign rhs).getLsbD idx

Tactic:
apply denote_blastMul

Result:
case bin.mul.hleft
w : Nat
assign : Assignment
w✝ : Nat
lhs rhs : BVExpr w✝
lih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := (go aig lhs).val.aig, ref := (go aig lhs).val.vec.get idx hidx }⟧ =
      (eval assign lhs).getLsbD idx
rih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := (go aig rhs).val.aig, ref := (go aig rhs).val.vec.get idx hidx }⟧ =
      (eval assign rhs).getLsbD idx
aig : AIG BVBit
idx : Nat
hidx : idx < w✝
⊢ ∀ (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment,
        { aig := (go (go aig lhs).1.aig rhs).1.aig,
          ref := { lhs := (go aig lhs).1.vec.cast ⋯, rhs := (go (go aig lhs).1.aig rhs).1.vec }.lhs.get idx hidx }⟧ =
      (eval assign lhs).getLsbD idx

case bin.mul.hright
w : Nat
assign : Assignment
w✝ : Nat
lhs rhs : BVExpr w✝
lih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := (go aig lhs).val.aig, ref := (go aig lhs).val.vec.get idx hidx }⟧ =
      (eval assign lhs).getLsbD idx
rih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := (go aig rhs).val.aig, ref := (go aig rhs).val.vec.get idx hidx }⟧ =
      (eval assign rhs).getLsbD idx
aig : AIG BVBit
idx : Nat
hidx : idx < w✝
⊢ ∀ (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment,
        { aig := (go (go aig lhs).1.aig rhs).1.aig,
          ref := { lhs := (go aig lhs).1.vec.cast ⋯, rhs := (go (go aig lhs).1.aig rhs).1.vec }.rhs.get idx hidx }⟧ =
      (eval assign rhs).getLsbD idx

Proof state:
case bin.mul.hleft
w : Nat
assign : Assignment
w✝ : Nat
lhs rhs : BVExpr w✝
lih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := (go aig lhs).val.aig, ref := (go aig lhs).val.vec.get idx hidx }⟧ =
      (eval assign lhs).getLsbD idx
rih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := (go aig rhs).val.aig, ref := (go aig rhs).val.vec.get idx hidx }⟧ =
      (eval assign rhs).getLsbD idx
aig : AIG BVBit
idx : Nat
hidx : idx < w✝
idx✝ : Nat
hidx✝ : idx✝ < w✝
⊢ ⟦assign.toAIGAssignment,
      { aig := (go aig lhs).1.aig,
        ref := { gate := (((go aig lhs).1.vec.cast ⋯).get idx✝ hidx✝).gate, hgate := ?bin.mul.hleft.hstart } }⟧ =
    ⟦assign.toAIGAssignment, { aig := (go aig lhs).val.aig, ref := (go aig lhs).val.vec.get idx✝ ?bin.mul.hleft.hidx }⟧

Tactic:
simp

Result:
no goals

Proof state:
case signExtend.inr.isTrue
w : Nat
assign : Assignment
originalWidth v : Nat
inner : BVExpr originalWidth
ih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < originalWidth),
    ⟦assign.toAIGAssignment, { aig := (go aig inner).val.aig, ref := (go aig inner).val.vec.get idx hidx }⟧ =
      (eval assign inner).getLsbD idx
aig : AIG BVBit
idx : Nat
hidx : idx < v
res : RefVecEntry BVBit v
hgo : blastSignExtend (go aig inner).1.aig { w := originalWidth, vec := (go aig inner).1.vec } = res
this : 0 ≤ originalWidth
hlt : 0 < originalWidth
h✝ : idx < originalWidth
⊢ ⟦assign.toAIGAssignment, { aig := (go aig inner).1.aig, ref := (go aig inner).1.vec.get idx ⋯ }⟧ =
    (eval assign inner).getLsbD idx

Tactic:
rw [ih]

Result:
no goals

Proof state:
case un.rotateLeft
w : Nat
assign : Assignment
w✝ : Nat
expr : BVExpr w✝
ih :
  ∀ (aig : AIG BVBit) (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := (go aig expr).val.aig, ref := (go aig expr).val.vec.get idx hidx }⟧ =
      (eval assign expr).getLsbD idx
aig : AIG BVBit
idx : Nat
hidx : idx < w✝
n✝ : Nat
⊢ ⟦assign.toAIGAssignment,
      { aig := (go aig (un (BVUnOp.rotateLeft n✝) expr)).val.aig,
        ref := (go aig (un (BVUnOp.rotateLeft n✝) expr)).val.vec.get idx hidx }⟧ =
    (eval assign (un (BVUnOp.rotateLeft n✝) expr)).getLsbD idx

Tactic:
simp [go, ih, hidx]

Result:
no goals