-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations/Udiv.lean
theorem denote_blastShiftConcat (aig : AIG α) (target : ShiftConcatInput aig w)
  (assign : α → Bool) :
  ∀ (idx : Nat) (hidx : idx < w),
      ⟦(blastShiftConcat aig target).aig, (blastShiftConcat aig target).vec.get idx hidx, assign⟧
        =
      if idx = 0 then
        ⟦aig, target.bit, assign⟧
      else
        ⟦aig, target.lhs.get (idx - 1) (by omega), assign⟧

Proof state:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
target : ShiftConcatInput aig w
assign : α → Bool
idx : Nat
hidx : idx < w
⊢ ⟦assign, { aig := (blastShiftConcat aig target).aig, ref := (blastShiftConcat aig target).vec.get idx hidx }⟧ =
    if idx = 0 then ⟦assign, { aig := aig, ref := target.bit }⟧
    else ⟦assign, { aig := aig, ref := target.lhs.get (idx - 1) ⋯ }⟧

Tactic:
unfold blastShiftConcat

Result:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
target : ShiftConcatInput aig w
assign : α → Bool
idx : Nat
hidx : idx < w
⊢ ⟦assign,
      {
        aig :=
          (match target with
            | { lhs := lhs, bit := bit } =>
              let bit := RefVec.empty.push bit;
              let new := bit.append lhs;
              blastZeroExtend aig { w := 0 + 1 + w, vec := new }).aig,
        ref :=
          (match target with
                | { lhs := lhs, bit := bit } =>
                  let bit := RefVec.empty.push bit;
                  let new := bit.append lhs;
                  blastZeroExtend aig { w := 0 + 1 + w, vec := new }).vec.get
            idx hidx }⟧ =
    if idx = 0 then ⟦assign, { aig := aig, ref := target.bit }⟧
    else ⟦assign, { aig := aig, ref := target.lhs.get (idx - 1) ⋯ }⟧

Proof state:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
target : ShiftConcatInput aig w
assign : α → Bool
idx : Nat
hidx : idx < w
⊢ idx - 1 < w

Tactic:
omega

Result:
no goals

Proof state:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
target : ShiftConcatInput aig w
assign : α → Bool
idx : Nat
hidx : idx < w
⊢ ⟦assign,
      {
        aig :=
          (match target with
            | { lhs := lhs, bit := bit } =>
              let bit := RefVec.empty.push bit;
              let new := bit.append lhs;
              blastZeroExtend aig { w := 0 + 1 + w, vec := new }).aig,
        ref :=
          (match target with
                | { lhs := lhs, bit := bit } =>
                  let bit := RefVec.empty.push bit;
                  let new := bit.append lhs;
                  blastZeroExtend aig { w := 0 + 1 + w, vec := new }).vec.get
            idx hidx }⟧ =
    if idx = 0 then ⟦assign, { aig := aig, ref := target.bit }⟧
    else ⟦assign, { aig := aig, ref := target.lhs.get (idx - 1) ⋯ }⟧

Tactic:
have hidx_lt : idx < 1 + w := by omega

Result:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
target : ShiftConcatInput aig w
assign : α → Bool
idx : Nat
hidx : idx < w
hidx_lt : idx < 1 + w
⊢ ⟦assign,
      {
        aig :=
          (match target with
            | { lhs := lhs, bit := bit } =>
              let bit := RefVec.empty.push bit;
              let new := bit.append lhs;
              blastZeroExtend aig { w := 0 + 1 + w, vec := new }).aig,
        ref :=
          (match target with
                | { lhs := lhs, bit := bit } =>
                  let bit := RefVec.empty.push bit;
                  let new := bit.append lhs;
                  blastZeroExtend aig { w := 0 + 1 + w, vec := new }).vec.get
            idx hidx }⟧ =
    if idx = 0 then ⟦assign, { aig := aig, ref := target.bit }⟧
    else ⟦assign, { aig := aig, ref := target.lhs.get (idx - 1) ⋯ }⟧

Proof state:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
target : ShiftConcatInput aig w
assign : α → Bool
idx : Nat
hidx : idx < w
⊢ idx < 1 + w

Tactic:
omega

Result:
no goals

Proof state:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
target : ShiftConcatInput aig w
assign : α → Bool
idx : Nat
hidx : idx < w
hidx_lt : idx < 1 + w
⊢ ⟦assign,
      {
        aig :=
          (match target with
            | { lhs := lhs, bit := bit } =>
              let bit := RefVec.empty.push bit;
              let new := bit.append lhs;
              blastZeroExtend aig { w := 0 + 1 + w, vec := new }).aig,
        ref :=
          (match target with
                | { lhs := lhs, bit := bit } =>
                  let bit := RefVec.empty.push bit;
                  let new := bit.append lhs;
                  blastZeroExtend aig { w := 0 + 1 + w, vec := new }).vec.get
            idx hidx }⟧ =
    if idx = 0 then ⟦assign, { aig := aig, ref := target.bit }⟧
    else ⟦assign, { aig := aig, ref := target.lhs.get (idx - 1) ⋯ }⟧

Tactic:
by_cases hidx_eq : idx = 0 <;> simp_arith [hidx_lt, hidx_eq, RefVec.get_append]

Result:
no goals

Proof state:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
target : ShiftConcatInput aig w
assign : α → Bool
⊢ ∀ (idx : Nat) (hidx : idx < w),
    ⟦assign, { aig := (blastShiftConcat aig target).aig, ref := (blastShiftConcat aig target).vec.get idx hidx }⟧ =
      if idx = 0 then ⟦assign, { aig := aig, ref := target.bit }⟧
      else ⟦assign, { aig := aig, ref := target.lhs.get (idx - 1) ⋯ }⟧

Tactic:
intro idx hidx

Result:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
target : ShiftConcatInput aig w
assign : α → Bool
idx : Nat
hidx : idx < w
⊢ ⟦assign, { aig := (blastShiftConcat aig target).aig, ref := (blastShiftConcat aig target).vec.get idx hidx }⟧ =
    if idx = 0 then ⟦assign, { aig := aig, ref := target.bit }⟧
    else ⟦assign, { aig := aig, ref := target.lhs.get (idx - 1) ⋯ }⟧