-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations/Mul.lean
theorem denote_blast (aig : AIG BVBit) (lhs rhs : BitVec w) (assign : Assignment)
      (input : BinaryRefVec aig w)
      (hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, input.lhs.get idx hidx, assign.toAIGAssignment⟧ = lhs.getLsbD idx)
      (hright : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, input.rhs.get idx hidx, assign.toAIGAssignment⟧ = rhs.getLsbD idx) :
      ∀ (idx : Nat) (hidx : idx < w),
        ⟦(blast aig input).aig, (blast aig input).vec.get idx hidx, assign.toAIGAssignment⟧
          =
        (lhs * rhs).getLsbD idx

Proof state:
case intro
w✝ : Nat
aig : AIG BVBit
lhs rhs : BitVec w✝
assign : Assignment
input : aig.BinaryRefVec w✝
hleft :
  ∀ (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.lhs.get idx hidx }⟧ = lhs.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w✝),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.rhs.get idx hidx }⟧ = rhs.getLsbD idx
idx : Nat
hidx : idx < w✝
res : RefVecEntry BVBit w✝
hne : ¬w✝ = 0
hb :
  go
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).aig
      ((input.cast ⋯).lhs.cast ⋯) ((input.cast ⋯).rhs.cast ⋯) 1
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).vec =
    res
w : Nat
hw : w✝ = w.succ
⊢ ⟦assign.toAIGAssignment, { aig := res.aig, ref := res.vec.get idx hidx }⟧ = (lhs.mulRec rhs w✝).getLsbD idx

Tactic:
subst hw

Result:
case intro
aig : AIG BVBit
assign : Assignment
idx w : Nat
lhs rhs : BitVec w.succ
input : aig.BinaryRefVec w.succ
hleft :
  ∀ (idx : Nat) (hidx : idx < w.succ),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.lhs.get idx hidx }⟧ = lhs.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w.succ),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.rhs.get idx hidx }⟧ = rhs.getLsbD idx
hidx : idx < w.succ
res : RefVecEntry BVBit w.succ
hne : ¬w.succ = 0
hb :
  go
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).aig
      ((input.cast ⋯).lhs.cast ⋯) ((input.cast ⋯).rhs.cast ⋯) 1
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).vec =
    res
⊢ ⟦assign.toAIGAssignment, { aig := res.aig, ref := res.vec.get idx hidx }⟧ = (lhs.mulRec rhs w.succ).getLsbD idx

Proof state:
w : Nat
aig : AIG BVBit
lhs rhs : BitVec w
assign : Assignment
input : aig.BinaryRefVec w
hleft :
  ∀ (idx : Nat) (hidx : idx < w),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.lhs.get idx hidx }⟧ = lhs.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.rhs.get idx hidx }⟧ = rhs.getLsbD idx
idx : Nat
hidx : idx < w
⊢ ⟦assign.toAIGAssignment, { aig := (blast aig input).aig, ref := (blast aig input).vec.get idx hidx }⟧ =
    (lhs.mulRec rhs w).getLsbD idx

Tactic:
generalize hb : blast aig input = res

Result:
w : Nat
aig : AIG BVBit
lhs rhs : BitVec w
assign : Assignment
input : aig.BinaryRefVec w
hleft :
  ∀ (idx : Nat) (hidx : idx < w),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.lhs.get idx hidx }⟧ = lhs.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.rhs.get idx hidx }⟧ = rhs.getLsbD idx
idx : Nat
hidx : idx < w
res : RefVecEntry BVBit w
hb : blast aig input = res
⊢ ⟦assign.toAIGAssignment, { aig := res.aig, ref := res.vec.get idx hidx }⟧ = (lhs.mulRec rhs w).getLsbD idx

Proof state:
case intro.hacc
aig : AIG BVBit
assign : Assignment
idx✝ w : Nat
lhs rhs : BitVec w.succ
input : aig.BinaryRefVec w.succ
hleft :
  ∀ (idx : Nat) (hidx : idx < w.succ),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.lhs.get idx hidx }⟧ = lhs.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w.succ),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.rhs.get idx hidx }⟧ = rhs.getLsbD idx
hidx✝ : idx✝ < w.succ
res : RefVecEntry BVBit w.succ
hne : ¬w.succ = 0
hb :
  go
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).aig
      ((input.cast ⋯).lhs.cast ⋯) ((input.cast ⋯).rhs.cast ⋯) 1
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).vec =
    res
idx : Nat
hidx : idx < w.succ
⊢ ⟦assign.toAIGAssignment,
      {
        aig :=
          (RefVec.ite (blastConst aig 0).aig
              { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).aig,
        ref :=
          (RefVec.ite (blastConst aig 0).aig
                  { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs,
                    rhs := (blastConst aig 0).vec }).vec.get
            idx hidx }⟧ =
    (if rhs.getLsbD 0 = true then lhs else 0).getLsbD idx

Tactic:
simp only [Nat.succ_eq_add_one, RefVec.denote_ite, BinaryRefVec.rhs_get_cast,
  Ref.gate_cast, BinaryRefVec.lhs_get_cast, denote_blastConst,
  BitVec.ofNat_eq_ofNat, eval_const, BitVec.getLsbD_zero, Bool.if_false_right,
  Bool.decide_eq_true]

Result:
case intro.hacc
aig : AIG BVBit
assign : Assignment
idx✝ w : Nat
lhs rhs : BitVec w.succ
input : aig.BinaryRefVec w.succ
hleft :
  ∀ (idx : Nat) (hidx : idx < w.succ),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.lhs.get idx hidx }⟧ = lhs.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w.succ),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.rhs.get idx hidx }⟧ = rhs.getLsbD idx
hidx✝ : idx✝ < w.succ
res : RefVecEntry BVBit w.succ
hne : ¬w.succ = 0
hb :
  go
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).aig
      ((input.cast ⋯).lhs.cast ⋯) ((input.cast ⋯).rhs.cast ⋯) 1
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).vec =
    res
idx : Nat
hidx : idx < w.succ
⊢ (⟦assign.toAIGAssignment, { aig := (blastConst aig 0#(w + 1)).aig, ref := (input.rhs.get 0 ⋯).cast ⋯ }⟧ &&
      ⟦assign.toAIGAssignment, { aig := (blastConst aig 0#(w + 1)).aig, ref := (input.lhs.get idx hidx).cast ⋯ }⟧) =
    (if rhs.getLsbD 0 = true then lhs else 0#(w + 1)).getLsbD idx

Proof state:
aig : AIG BVBit
assign : Assignment
idx✝ w : Nat
lhs rhs : BitVec w.succ
input : aig.BinaryRefVec w.succ
hleft :
  ∀ (idx : Nat) (hidx : idx < w.succ),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.lhs.get idx hidx }⟧ = lhs.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w.succ),
    ⟦assign.toAIGAssignment, { aig := aig, ref := input.rhs.get idx hidx }⟧ = rhs.getLsbD idx
hidx✝ : idx✝ < w.succ
res : RefVecEntry BVBit w.succ
hne : ¬w.succ = 0
hb :
  go
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).aig
      ((input.cast ⋯).lhs.cast ⋯) ((input.cast ⋯).rhs.cast ⋯) 1
      (RefVec.ite (blastConst aig 0).aig
          { discr := (input.cast ⋯).rhs.get 0 ⋯, lhs := (input.cast ⋯).lhs, rhs := (blastConst aig 0).vec }).vec =
    res
idx : Nat
hidx : idx < w.succ
heq✝ : rhs.getLsbD 0 = true
heq : ⟦assign.toAIGAssignment, { aig := aig, ref := input.rhs.get 0 ?hidx }⟧ = true
⊢ (⟦assign.toAIGAssignment, { aig := aig, ref := { gate := ((input.rhs.get 0 ⋯).cast ⋯).gate, hgate := ?m.34715 } }⟧ &&
      ⟦assign.toAIGAssignment,
        { aig := aig, ref := { gate := ((input.lhs.get idx hidx).cast ⋯).gate, hgate := ?m.35283 } }⟧) =
    lhs.getLsbD idx

Tactic:
simp [heq, hleft]

Result:
no goals