-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Impl/Operations/ZeroExtend.lean
theorem go_decl_eq (aig : AIG α) (w : Nat) (input : AIG.RefVec aig w) (newWidth curr : Nat)
    (hcurr : curr ≤ newWidth) (s : AIG.RefVec aig curr) :
    ∀ (idx : Nat) (h1) (h2),
       (go aig w input newWidth curr hcurr s).aig.decls[idx]'h2 = aig.decls[idx]'h1

Proof state:
case isTrue
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝ : curr < newWidth
hgo :
  (if hcurr2 : curr < w then
      let s := s.push (input.get curr hcurr2);
      go aig w input newWidth (curr + 1) ⋯ s
    else
      let res := aig.mkConstCached false;
      let aig_1 := res.aig;
      let zeroRef := res.ref;
      let_fun hcast := ⋯;
      let input := input.cast hcast;
      let s := s.cast hcast;
      let s := s.push zeroRef;
      go aig_1 w input newWidth (curr + 1) ⋯ s) =
    res
⊢ ∀ (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < res.aig.decls.size), res.aig.decls[idx] = aig.decls[idx]

Tactic:
dsimp only at hgo

Result:
case isTrue
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝ : curr < newWidth
hgo :
  (if hcurr2 : curr < w then go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr hcurr2))
    else
      go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
        ((s.cast ⋯).push (aig.mkConstCached false).ref)) =
    res
⊢ ∀ (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < res.aig.decls.size), res.aig.decls[idx] = aig.decls[idx]

Proof state:
case isFalse
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝ : ¬curr < newWidth
hgo :
  (let_fun hcurr := ⋯;
    { aig := aig, vec := hcurr ▸ s }) =
    res
⊢ ∀ (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < res.aig.decls.size), res.aig.decls[idx] = aig.decls[idx]

Tactic:
simp [← hgo]

Result:
no goals

Proof state:
case isTrue.isFalse
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝¹ : curr < newWidth
h✝ : ¬curr < w
hgo :
  go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
      ((s.cast ⋯).push (aig.mkConstCached false).ref) =
    res
⊢ ∀ (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < res.aig.decls.size), res.aig.decls[idx] = aig.decls[idx]

Tactic:
rw [← hgo]

Result:
case isTrue.isFalse
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝¹ : curr < newWidth
h✝ : ¬curr < w
hgo :
  go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
      ((s.cast ⋯).push (aig.mkConstCached false).ref) =
    res
⊢ ∀ (idx : Nat) (h1 : idx < aig.decls.size)
    (h2 :
      idx <
        (go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
                ((s.cast ⋯).push (aig.mkConstCached false).ref)).aig.decls.size),
    (go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
              ((s.cast ⋯).push (aig.mkConstCached false).ref)).aig.decls[idx] =
      aig.decls[idx]

Proof state:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
⊢ ∀ (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < (go aig w input newWidth curr hcurr s).aig.decls.size),
    (go aig w input newWidth curr hcurr s).aig.decls[idx] = aig.decls[idx]

Tactic:
generalize hgo : go aig w input newWidth curr hcurr s = res

Result:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
hgo : go aig w input newWidth curr hcurr s = res
⊢ ∀ (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < res.aig.decls.size), res.aig.decls[idx] = aig.decls[idx]

Proof state:
case isTrue.isFalse
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝¹ : curr < newWidth
h✝ : ¬curr < w
hgo :
  go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
      ((s.cast ⋯).push (aig.mkConstCached false).ref) =
    res
⊢ ∀ (idx : Nat) (h1 : idx < aig.decls.size)
    (h2 :
      idx <
        (go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
                ((s.cast ⋯).push (aig.mkConstCached false).ref)).aig.decls.size),
    (go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
              ((s.cast ⋯).push (aig.mkConstCached false).ref)).aig.decls[idx] =
      aig.decls[idx]

Tactic:
intro idx h1 h2

Result:
case isTrue.isFalse
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝¹ : curr < newWidth
h✝ : ¬curr < w
hgo :
  go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
      ((s.cast ⋯).push (aig.mkConstCached false).ref) =
    res
idx : Nat
h1 : idx < aig.decls.size
h2 :
  idx <
    (go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
            ((s.cast ⋯).push (aig.mkConstCached false).ref)).aig.decls.size
⊢ (go (aig.mkConstCached false).aig w (input.cast ⋯) newWidth (curr + 1) ⋯
            ((s.cast ⋯).push (aig.mkConstCached false).ref)).aig.decls[idx] =
    aig.decls[idx]

Proof state:
case isTrue.isTrue
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝¹ : curr < newWidth
h✝ : curr < w
hgo : go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr h✝)) = res
⊢ ∀ (idx : Nat) (h1 : idx < aig.decls.size)
    (h2 : idx < (go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr h✝))).aig.decls.size),
    (go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr h✝))).aig.decls[idx] = aig.decls[idx]

Tactic:
intro idx h1 h2

Result:
case isTrue.isTrue
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝¹ : curr < newWidth
h✝ : curr < w
hgo : go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr h✝)) = res
idx : Nat
h1 : idx < aig.decls.size
h2 : idx < (go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr h✝))).aig.decls.size
⊢ (go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr h✝))).aig.decls[idx] = aig.decls[idx]

Proof state:
case isTrue.isTrue
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
aig : AIG α
w : Nat
input : aig.RefVec w
newWidth curr : Nat
hcurr : curr ≤ newWidth
s : aig.RefVec curr
res : AIG.RefVecEntry α newWidth
h✝¹ : curr < newWidth
h✝ : curr < w
hgo : go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr h✝)) = res
idx : Nat
h1 : idx < aig.decls.size
h2 : idx < (go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr h✝))).aig.decls.size
⊢ (go aig w input newWidth (curr + 1) ⋯ (s.push (input.get curr h✝))).aig.decls[idx] = aig.decls[idx]

Tactic:
rw [go_decl_eq]

Result:
no goals