-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations/Mul.lean
theorem go_denote_eq {w : Nat} (aig : AIG BVBit) (curr : Nat) (hcurr : curr + 1 ≤ w)
    (acc : AIG.RefVec aig w) (lhs rhs : AIG.RefVec aig w) (lexpr rexpr : BitVec w) (assign : Assignment)
    (hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, lhs.get idx hidx, assign.toAIGAssignment⟧ = lexpr.getLsbD idx)
    (hright : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, rhs.get idx hidx, assign.toAIGAssignment⟧ = rexpr.getLsbD idx)
    (hacc : ∀ (idx : Nat) (hidx : idx < w),
                ⟦aig, acc.get idx hidx, assign.toAIGAssignment⟧
                  =
                (BitVec.mulRec lexpr rexpr curr).getLsbD idx) :
    ∀ (idx : Nat) (hidx : idx < w),
        ⟦
          (go aig lhs rhs (curr + 1) acc).aig,
          (go aig lhs rhs (curr + 1) acc).vec.get idx hidx,
          assign.toAIGAssignment
        ⟧
          =
        (BitVec.mulRec lexpr rexpr w).getLsbD idx

Proof state:
case isFalse
w : Nat
aig : AIG BVBit
curr : Nat
hcurr : curr + 1 ≤ w
acc lhs rhs : aig.RefVec w
lexpr rexpr : BitVec w
assign : Assignment
hleft :
  ∀ (idx : Nat) (hidx : idx < w), ⟦assign.toAIGAssignment, { aig := aig, ref := lhs.get idx hidx }⟧ = lexpr.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w), ⟦assign.toAIGAssignment, { aig := aig, ref := rhs.get idx hidx }⟧ = rexpr.getLsbD idx
hacc :
  ∀ (idx : Nat) (hidx : idx < w),
    ⟦assign.toAIGAssignment, { aig := aig, ref := acc.get idx hidx }⟧ = (lexpr.mulRec rexpr curr).getLsbD idx
idx : Nat
hidx : idx < w
res : RefVecEntry BVBit w
h✝ : ¬curr + 1 < w
hgo : { aig := aig, vec := acc } = res
⊢ ⟦assign.toAIGAssignment, { aig := res.aig, ref := res.vec.get idx hidx }⟧ = (lexpr.mulRec rexpr w).getLsbD idx

Tactic:
have : curr + 1 = w := by omega

Result:
case isFalse
w : Nat
aig : AIG BVBit
curr : Nat
hcurr : curr + 1 ≤ w
acc lhs rhs : aig.RefVec w
lexpr rexpr : BitVec w
assign : Assignment
hleft :
  ∀ (idx : Nat) (hidx : idx < w), ⟦assign.toAIGAssignment, { aig := aig, ref := lhs.get idx hidx }⟧ = lexpr.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w), ⟦assign.toAIGAssignment, { aig := aig, ref := rhs.get idx hidx }⟧ = rexpr.getLsbD idx
hacc :
  ∀ (idx : Nat) (hidx : idx < w),
    ⟦assign.toAIGAssignment, { aig := aig, ref := acc.get idx hidx }⟧ = (lexpr.mulRec rexpr curr).getLsbD idx
idx : Nat
hidx : idx < w
res : RefVecEntry BVBit w
h✝ : ¬curr + 1 < w
hgo : { aig := aig, vec := acc } = res
this : curr + 1 = w
⊢ ⟦assign.toAIGAssignment, { aig := res.aig, ref := res.vec.get idx hidx }⟧ = (lexpr.mulRec rexpr w).getLsbD idx

Proof state:
aig : AIG BVBit
curr : Nat
assign : Assignment
idx : Nat
hcurr : curr + 1 ≤ curr + 1
acc lhs rhs : aig.RefVec (curr + 1)
lexpr rexpr : BitVec (curr + 1)
hleft :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := lhs.get idx hidx }⟧ = lexpr.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := rhs.get idx hidx }⟧ = rexpr.getLsbD idx
hacc :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := acc.get idx hidx }⟧ = (lexpr.mulRec rexpr curr).getLsbD idx
hidx : idx < curr + 1
res : RefVecEntry BVBit (curr + 1)
h✝ : ¬curr + 1 < curr + 1
hgo : { aig := aig, vec := acc } = res
⊢ rexpr.getLsbD (curr + 1) = false

Tactic:
apply BitVec.getLsbD_ge

Result:
case ge
aig : AIG BVBit
curr : Nat
assign : Assignment
idx : Nat
hcurr : curr + 1 ≤ curr + 1
acc lhs rhs : aig.RefVec (curr + 1)
lexpr rexpr : BitVec (curr + 1)
hleft :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := lhs.get idx hidx }⟧ = lexpr.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := rhs.get idx hidx }⟧ = rexpr.getLsbD idx
hacc :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := acc.get idx hidx }⟧ = (lexpr.mulRec rexpr curr).getLsbD idx
hidx : idx < curr + 1
res : RefVecEntry BVBit (curr + 1)
h✝ : ¬curr + 1 < curr + 1
hgo : { aig := aig, vec := acc } = res
⊢ curr + 1 ≤ curr + 1

Proof state:
w : Nat
aig : AIG BVBit
curr : Nat
hcurr : curr + 1 ≤ w
acc lhs rhs : aig.RefVec w
lexpr rexpr : BitVec w
assign : Assignment
hleft :
  ∀ (idx : Nat) (hidx : idx < w), ⟦assign.toAIGAssignment, { aig := aig, ref := lhs.get idx hidx }⟧ = lexpr.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w), ⟦assign.toAIGAssignment, { aig := aig, ref := rhs.get idx hidx }⟧ = rexpr.getLsbD idx
hacc :
  ∀ (idx : Nat) (hidx : idx < w),
    ⟦assign.toAIGAssignment, { aig := aig, ref := acc.get idx hidx }⟧ = (lexpr.mulRec rexpr curr).getLsbD idx
idx✝¹ : Nat
hidx✝¹ : idx✝¹ < w
res : RefVecEntry BVBit w
h✝¹ : curr + 1 < w
h✝ : ¬aig.isConstant (rhs.get (curr + 1) h✝¹) false = true
hgo :
  go
      (RefVec.ite
          (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
              { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).aig
          { discr := ((rhs.cast ⋯).cast ⋯).get (curr + 1) h✝¹,
            lhs :=
              (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
                  { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).vec,
            rhs := (acc.cast ⋯).cast ⋯ }).aig
      (((lhs.cast ⋯).cast ⋯).cast ⋯) (((rhs.cast ⋯).cast ⋯).cast ⋯) (curr + 1 + 1)
      (RefVec.ite
          (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
              { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).aig
          { discr := ((rhs.cast ⋯).cast ⋯).get (curr + 1) h✝¹,
            lhs :=
              (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
                  { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).vec,
            rhs := (acc.cast ⋯).cast ⋯ }).vec =
    res
idx : Nat
hidx : idx < w
hdiscr✝ :
  ⟦assign.toAIGAssignment,
      {
        aig :=
          (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
              { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).aig,
        ref := { gate := (rhs.get (curr + 1) h✝¹).gate, hgate := ⋯ } }⟧ =
    true
this : rexpr.getLsbD (curr + 1) = true
idx✝ : Nat
hidx✝ : idx✝ < w
hdiscr : idx✝ < curr + 1
⊢ false = (decide (idx✝ < w) && !decide (idx✝ < curr + 1) && lexpr.getLsbD (idx✝ - (curr + 1)))

Tactic:
simp [hdiscr]

Result:
no goals