-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations/Umod.lean
theorem denote_go_eq_divRec_r (aig : AIG α) (assign : α → Bool) (curr : Nat) (lhs rhs rbv qbv : BitVec w)
    (falseRef trueRef : AIG.Ref aig) (n d q r : AIG.RefVec aig w) (wn wr : Nat)
    (hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, n.get idx hidx, assign⟧ = lhs.getLsbD idx)
    (hright : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, d.get idx hidx, assign⟧ = rhs.getLsbD idx)
    (hq : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, q.get idx hidx, assign⟧ = qbv.getLsbD idx)
    (hr : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, r.get idx hidx, assign⟧ = rbv.getLsbD idx)
    (hfalse : ⟦aig, falseRef, assign⟧ = false)
    (htrue : ⟦aig, trueRef, assign⟧ = true)
      :
    ∀ (idx : Nat) (hidx : idx < w),
      ⟦
        (go aig curr falseRef trueRef n d wn wr q r).aig,
        (go aig curr falseRef trueRef n d wn wr q r).r.get idx hidx,
        assign
      ⟧
        =
      (BitVec.divRec curr { n := lhs, d := rhs} { wn, wr, q := qbv, r := rbv }).r.getLsbD idx

Proof state:
case hq
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
assign : α → Bool
lhs rhs : BitVec w
curr : Nat
ih :
  ∀ (aig : AIG α) (rbv qbv : BitVec w) (falseRef trueRef : aig.Ref) (n d q r : aig.RefVec w) (wn wr : Nat),
    (∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := n.get idx hidx }⟧ = lhs.getLsbD idx) →
      (∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := d.get idx hidx }⟧ = rhs.getLsbD idx) →
        (∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := q.get idx hidx }⟧ = qbv.getLsbD idx) →
          (∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := r.get idx hidx }⟧ = rbv.getLsbD idx) →
            ⟦assign, { aig := aig, ref := falseRef }⟧ = false →
              ⟦assign, { aig := aig, ref := trueRef }⟧ = true →
                ∀ (idx : Nat) (hidx : idx < w),
                  ⟦assign,
                      { aig := (go aig curr falseRef trueRef n d wn wr q r).aig,
                        ref := (go aig curr falseRef trueRef n d wn wr q r).r.get idx hidx }⟧ =
                    (BitVec.divRec curr { n := lhs, d := rhs } { wn := wn, wr := wr, q := qbv, r := rbv }).r.getLsbD idx
aig : AIG α
rbv qbv : BitVec w
falseRef trueRef : aig.Ref
n d q r : aig.RefVec w
wn wr : Nat
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := n.get idx hidx }⟧ = lhs.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := d.get idx hidx }⟧ = rhs.getLsbD idx
hq : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := q.get idx hidx }⟧ = qbv.getLsbD idx
hr : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := r.get idx hidx }⟧ = rbv.getLsbD idx
hfalse : ⟦assign, { aig := aig, ref := falseRef }⟧ = false
htrue : ⟦assign, { aig := aig, ref := trueRef }⟧ = true
idx✝ : Nat
hidx✝ : idx✝ < w
hdiscr :
  { wn := wn, wr := wr, q := qbv, r := rbv }.r.shiftConcat
      (lhs.getLsbD ({ wn := wn, wr := wr, q := qbv, r := rbv }.wn - 1)) <
    rhs
idx : Nat
hidx : idx < w
⊢ (if
              { wn := wn, wr := wr, q := qbv, r := rbv }.r.shiftConcat
                  (lhs.getLsbD ({ wn := wn, wr := wr, q := qbv, r := rbv }.wn - 1)) <
                rhs then
            { wn := { wn := wn, wr := wr, q := qbv, r := rbv }.wn - 1,
              wr := { wn := wn, wr := wr, q := qbv, r := rbv }.wr + 1,
              q := { wn := wn, wr := wr, q := qbv, r := rbv }.q.shiftConcat false,
              r :=
                { wn := wn, wr := wr, q := qbv, r := rbv }.r.shiftConcat
                  (lhs.getLsbD ({ wn := wn, wr := wr, q := qbv, r := rbv }.wn - 1)) }
          else
            { wn := { wn := wn, wr := wr, q := qbv, r := rbv }.wn - 1,
              wr := { wn := wn, wr := wr, q := qbv, r := rbv }.wr + 1,
              q := { wn := wn, wr := wr, q := qbv, r := rbv }.q.shiftConcat true,
              r :=
                { wn := wn, wr := wr, q := qbv, r := rbv }.r.shiftConcat
                    (lhs.getLsbD ({ wn := wn, wr := wr, q := qbv, r := rbv }.wn - 1)) -
                  rhs }).q.getLsbD
      idx =
    ({ wn := wn, wr := wr, q := qbv, r := rbv }.q.shiftConcat false).getLsbD idx

Tactic:
simp [hdiscr]

Result:
no goals