-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations/Mul.lean
theorem go_denote_eq {w : Nat} (aig : AIG BVBit) (curr : Nat) (hcurr : curr + 1 ≤ w)
    (acc : AIG.RefVec aig w) (lhs rhs : AIG.RefVec aig w) (lexpr rexpr : BitVec w) (assign : Assignment)
    (hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, lhs.get idx hidx, assign.toAIGAssignment⟧ = lexpr.getLsbD idx)
    (hright : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, rhs.get idx hidx, assign.toAIGAssignment⟧ = rexpr.getLsbD idx)
    (hacc : ∀ (idx : Nat) (hidx : idx < w),
                ⟦aig, acc.get idx hidx, assign.toAIGAssignment⟧
                  =
                (BitVec.mulRec lexpr rexpr curr).getLsbD idx) :
    ∀ (idx : Nat) (hidx : idx < w),
        ⟦
          (go aig lhs rhs (curr + 1) acc).aig,
          (go aig lhs rhs (curr + 1) acc).vec.get idx hidx,
          assign.toAIGAssignment
        ⟧
          =
        (BitVec.mulRec lexpr rexpr w).getLsbD idx

Proof state:
case isFalse
aig : AIG BVBit
curr : Nat
assign : Assignment
idx : Nat
hcurr : curr + 1 ≤ curr + 1
acc lhs rhs : aig.RefVec (curr + 1)
lexpr rexpr : BitVec (curr + 1)
hleft :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := lhs.get idx hidx }⟧ = lexpr.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := rhs.get idx hidx }⟧ = rexpr.getLsbD idx
hacc :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := acc.get idx hidx }⟧ = (lexpr.mulRec rexpr curr).getLsbD idx
hidx : idx < curr + 1
res : RefVecEntry BVBit (curr + 1)
h✝ : ¬curr + 1 < curr + 1
hgo : { aig := aig, vec := acc } = res
⊢ (lexpr.mulRec rexpr curr).getLsbD idx =
    (lexpr.mulRec rexpr curr + if rexpr.getLsbD (curr + 1) = true then lexpr <<< (curr + 1) else 0).getLsbD idx

Tactic:
have : rexpr.getLsbD (curr + 1) = false := by
  apply BitVec.getLsbD_ge
  omega

Result:
case isFalse
aig : AIG BVBit
curr : Nat
assign : Assignment
idx : Nat
hcurr : curr + 1 ≤ curr + 1
acc lhs rhs : aig.RefVec (curr + 1)
lexpr rexpr : BitVec (curr + 1)
hleft :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := lhs.get idx hidx }⟧ = lexpr.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := rhs.get idx hidx }⟧ = rexpr.getLsbD idx
hacc :
  ∀ (idx : Nat) (hidx : idx < curr + 1),
    ⟦assign.toAIGAssignment, { aig := aig, ref := acc.get idx hidx }⟧ = (lexpr.mulRec rexpr curr).getLsbD idx
hidx : idx < curr + 1
res : RefVecEntry BVBit (curr + 1)
h✝ : ¬curr + 1 < curr + 1
hgo : { aig := aig, vec := acc } = res
this : rexpr.getLsbD (curr + 1) = false
⊢ (lexpr.mulRec rexpr curr).getLsbD idx =
    (lexpr.mulRec rexpr curr + if rexpr.getLsbD (curr + 1) = true then lexpr <<< (curr + 1) else 0).getLsbD idx

Proof state:
case isTrue.isFalse.hacc.isFalse
w : Nat
aig : AIG BVBit
curr : Nat
hcurr : curr + 1 ≤ w
acc lhs rhs : aig.RefVec w
lexpr rexpr : BitVec w
assign : Assignment
hleft :
  ∀ (idx : Nat) (hidx : idx < w), ⟦assign.toAIGAssignment, { aig := aig, ref := lhs.get idx hidx }⟧ = lexpr.getLsbD idx
hright :
  ∀ (idx : Nat) (hidx : idx < w), ⟦assign.toAIGAssignment, { aig := aig, ref := rhs.get idx hidx }⟧ = rexpr.getLsbD idx
hacc :
  ∀ (idx : Nat) (hidx : idx < w),
    ⟦assign.toAIGAssignment, { aig := aig, ref := acc.get idx hidx }⟧ = (lexpr.mulRec rexpr curr).getLsbD idx
idx✝ : Nat
hidx✝ : idx✝ < w
res : RefVecEntry BVBit w
h✝² : curr + 1 < w
h✝¹ : ¬aig.isConstant (rhs.get (curr + 1) h✝²) false = true
hgo :
  go
      (RefVec.ite
          (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
              { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).aig
          { discr := ((rhs.cast ⋯).cast ⋯).get (curr + 1) h✝²,
            lhs :=
              (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
                  { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).vec,
            rhs := (acc.cast ⋯).cast ⋯ }).aig
      (((lhs.cast ⋯).cast ⋯).cast ⋯) (((rhs.cast ⋯).cast ⋯).cast ⋯) (curr + 1 + 1)
      (RefVec.ite
          (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
              { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).aig
          { discr := ((rhs.cast ⋯).cast ⋯).get (curr + 1) h✝²,
            lhs :=
              (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
                  { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).vec,
            rhs := (acc.cast ⋯).cast ⋯ }).vec =
    res
idx : Nat
hidx : idx < w
h✝ :
  ¬⟦assign.toAIGAssignment,
        {
          aig :=
            (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
                { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).aig,
          ref := { gate := (rhs.get (curr + 1) h✝²).gate, hgate := ⋯ } }⟧ =
      true
⊢ ⟦assign.toAIGAssignment,
      {
        aig :=
          (blastAdd (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).aig
              { lhs := acc.cast ⋯, rhs := (blastShiftLeftConst aig { vec := lhs, distance := curr + 1 }).vec }).aig,
        ref := { gate := (acc.get idx hidx).gate, hgate := ⋯ } }⟧ =
    (lexpr.mulRec rexpr curr + if rexpr.getLsbD (curr + 1) = true then lexpr <<< (curr + 1) else 0#w).getLsbD idx

Tactic:
next hdiscr =>
have : rexpr.getLsbD (curr + 1) = false := by
  rw [AIG.LawfulVecOperator.denote_mem_prefix (f := blastAdd)] at hdiscr
  rw [AIG.LawfulVecOperator.denote_mem_prefix (f := blastShiftLeftConst)] at hdiscr
  rw [hright] at hdiscr
  simp [hdiscr]
simp only [this, Bool.false_eq_true, ↓reduceIte, BitVec.add_zero]
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := blastAdd)]
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := blastShiftLeftConst)]
rw [hacc]

Result:
no goals