-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Carry.lean
theorem go_eq_carry (aig : AIG α) (curr : Nat) (hcurr : curr ≤ w) (cin : Ref aig) (origCin : Ref aig)
    (lhs rhs : RefVec aig w) (lhsExpr rhsExpr : BitVec w) (assign : α → Bool)
    (hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, lhs.get idx hidx, assign⟧ = lhsExpr.getLsbD idx)
    (hright : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, rhs.get idx hidx, assign⟧ = rhsExpr.getLsbD idx)
    (hcin : ⟦aig, cin, assign⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦aig, origCin, assign⟧) :
    ⟦go aig lhs rhs curr cin, assign⟧
      =
    BitVec.carry w lhsExpr rhsExpr ⟦aig, origCin, assign⟧

Proof state:
case isTrue.hright
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefVec w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦assign, { aig := aig, ref := origCin }⟧
h✝ : curr < w
idx✝ : Nat
hidx✝ : idx✝ < w
⊢ ⟦assign, { aig := aig, ref := { gate := ((rhs.cast ⋯).get idx✝ hidx✝).gate, hgate := ?isTrue.hright } }⟧ =
    rhsExpr.getLsbD idx✝

Tactic:
simp [hright]

Result:
no goals

Proof state:
case isTrue.hcin
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefVec w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦assign, { aig := aig, ref := origCin }⟧
h✝ : curr < w
⊢ ⟦assign,
      { aig := (mkFullAdderCarry aig { lhs := lhs.get curr h✝, rhs := rhs.get curr h✝, cin := cin }).aig,
        ref := (mkFullAdderCarry aig { lhs := lhs.get curr h✝, rhs := rhs.get curr h✝, cin := cin }).ref }⟧ =
    BitVec.carry (curr + 1) lhsExpr rhsExpr
      ⟦assign,
        { aig := (mkFullAdderCarry aig { lhs := lhs.get curr h✝, rhs := rhs.get curr h✝, cin := cin }).aig,
          ref := { gate := origCin.gate, hgate := ⋯ } }⟧

Tactic:
simp only [denote_projected_entry, blastAdd.denote_mkFullAdderCarry, BitVec.carry_succ]

Result:
case isTrue.hcin
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefVec w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦assign, { aig := aig, ref := origCin }⟧
h✝ : curr < w
⊢ ((⟦assign, { aig := aig, ref := lhs.get curr h✝ }⟧ ^^ ⟦assign, { aig := aig, ref := rhs.get curr h✝ }⟧) &&
        ⟦assign, { aig := aig, ref := cin }⟧ ||
      ⟦assign, { aig := aig, ref := lhs.get curr h✝ }⟧ && ⟦assign, { aig := aig, ref := rhs.get curr h✝ }⟧) =
    (lhsExpr.getLsbD curr).atLeastTwo (rhsExpr.getLsbD curr)
      (BitVec.carry curr lhsExpr rhsExpr
        ⟦assign,
          { aig := (mkFullAdderCarry aig { lhs := lhs.get curr h✝, rhs := rhs.get curr h✝, cin := cin }).aig,
            ref := { gate := origCin.gate, hgate := ⋯ } }⟧)

Proof state:
case isTrue.e_c
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefVec w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦assign, { aig := aig, ref := origCin }⟧
h✝ : curr < w
⊢ ⟦assign,
      { aig := (mkFullAdderCarry aig { lhs := lhs.get curr h✝, rhs := rhs.get curr h✝, cin := cin }).aig,
        ref := ?isTrue.origCin }⟧ =
    ⟦assign, { aig := aig, ref := origCin }⟧

Tactic:
rw [AIG.LawfulOperator.denote_mem_prefix (f := mkFullAdderCarry)]

Result:
no goals

Proof state:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefVec w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦assign, { aig := aig, ref := origCin }⟧
⊢ ⟦assign,
      if hidx : curr < w then
        let lin := lhs.get curr hidx;
        let rin := rhs.get curr hidx;
        let res := mkFullAdderCarry aig { lhs := lin, rhs := rin, cin := cin };
        let_fun this := ⋯;
        let aig_1 := res.aig;
        let carryRef := res.ref;
        let lhs := lhs.cast this;
        let rhs := rhs.cast this;
        go aig_1 lhs rhs (curr + 1) carryRef
      else { aig := aig, ref := cin }⟧ =
    BitVec.carry w lhsExpr rhsExpr ⟦assign, { aig := aig, ref := origCin }⟧

Tactic:
dsimp only

Result:
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefVec w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦assign, { aig := aig, ref := origCin }⟧
⊢ ⟦assign,
      if hidx : curr < w then
        go (mkFullAdderCarry aig { lhs := lhs.get curr hidx, rhs := rhs.get curr hidx, cin := cin }).aig (lhs.cast ⋯)
          (rhs.cast ⋯) (curr + 1)
          (mkFullAdderCarry aig { lhs := lhs.get curr hidx, rhs := rhs.get curr hidx, cin := cin }).ref
      else { aig := aig, ref := cin }⟧ =
    BitVec.carry w lhsExpr rhsExpr ⟦assign, { aig := aig, ref := origCin }⟧

Proof state:
case isTrue.hleft
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin origCin : aig.Ref
lhs rhs : aig.RefVec w
lhsExpr rhsExpr : BitVec w
assign : α → Bool
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr ⟦assign, { aig := aig, ref := origCin }⟧
h✝ : curr < w
idx✝ : Nat
hidx✝ : idx✝ < w
⊢ ((lhs.cast ⋯).get idx✝ hidx✝).gate < aig.decls.size

Tactic:
simp [Ref.hgate]

Result:
no goals