-- Mathlib/.lake/packages/lean4/src/lean/Std/Sat/AIG/If.lean
theorem denote_go {w : Nat} (aig : AIG α) (curr : Nat) (hcurr : curr ≤ w) (discr : Ref aig)
    (lhs rhs : RefVec aig w) (s : RefVec aig curr) :
    ∀ (idx : Nat) (hidx1 : idx < w),
      curr ≤ idx
        →
      ⟦
        (go aig curr hcurr discr lhs rhs s).aig,
        (go aig curr hcurr discr lhs rhs s).vec.get idx hidx1,
        assign
      ⟧
        =
      if ⟦aig, discr, assign⟧ then
        ⟦aig, lhs.get idx hidx1, assign⟧
      else
        ⟦aig, rhs.get idx hidx1, assign⟧

Proof state:
case isTrue.inr
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefVec w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig (curr + 1) ⋯ (discr.cast ⋯)
      (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).push (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).ref) =
    res
heq : curr < idx
⊢ (if ⟦assign, { aig := aig, ref := { gate := (discr.cast ⋯).gate, hgate := ?isTrue.inr } }⟧ = true then
      ⟦assign, { aig := aig, ref := { gate := ((lhs.cast ⋯).get idx hidx1).gate, hgate := ?isTrue.inr } }⟧
    else
      ⟦assign,
        { aig := (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig,
          ref := (rhs.cast ⋯).get idx hidx1 }⟧) =
    if ⟦assign, { aig := aig, ref := discr }⟧ = true then ⟦assign, { aig := aig, ref := lhs.get idx hidx1 }⟧
    else ⟦assign, { aig := aig, ref := rhs.get idx hidx1 }⟧

case isTrue.inr
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefVec w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig (curr + 1) ⋯ (discr.cast ⋯)
      (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).push (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).ref) =
    res
heq : curr < idx
⊢ ((lhs.cast ⋯).get idx hidx1).gate < aig.decls.size

case isTrue.inr
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefVec w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig (curr + 1) ⋯ (discr.cast ⋯)
      (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).push (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).ref) =
    res
heq : curr < idx
⊢ (discr.cast ⋯).gate < aig.decls.size

Tactic:
rw [LawfulOperator.denote_mem_prefix (f := mkIfCached)]

Result:
case isTrue.inr
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefVec w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig (curr + 1) ⋯ (discr.cast ⋯)
      (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).push (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).ref) =
    res
heq : curr < idx
⊢ (if ⟦assign, { aig := aig, ref := { gate := (discr.cast ⋯).gate, hgate := ?isTrue.inr } }⟧ = true then
      ⟦assign, { aig := aig, ref := { gate := ((lhs.cast ⋯).get idx hidx1).gate, hgate := ?isTrue.inr } }⟧
    else ⟦assign, { aig := aig, ref := { gate := ((rhs.cast ⋯).get idx hidx1).gate, hgate := ?isTrue.inr } }⟧) =
    if ⟦assign, { aig := aig, ref := discr }⟧ = true then ⟦assign, { aig := aig, ref := lhs.get idx hidx1 }⟧
    else ⟦assign, { aig := aig, ref := rhs.get idx hidx1 }⟧

case isTrue.inr
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefVec w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig (curr + 1) ⋯ (discr.cast ⋯)
      (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).push (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).ref) =
    res
heq : curr < idx
⊢ ((rhs.cast ⋯).get idx hidx1).gate < aig.decls.size

case isTrue.inr
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefVec w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig (curr + 1) ⋯ (discr.cast ⋯)
      (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).push (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).ref) =
    res
heq : curr < idx
⊢ ((lhs.cast ⋯).get idx hidx1).gate < aig.decls.size

case isTrue.inr
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefVec w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig (curr + 1) ⋯ (discr.cast ⋯)
      (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).push (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).ref) =
    res
heq : curr < idx
⊢ (discr.cast ⋯).gate < aig.decls.size

Proof state:
case isTrue.inl
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
assign : α → Bool
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
discr : aig.Ref
lhs rhs : aig.RefVec w
s : aig.RefVec curr
res : RefVecEntry α w
h✝ : curr < w
hgo :
  go (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig (curr + 1) ⋯ (discr.cast ⋯)
      (lhs.cast ⋯) (rhs.cast ⋯)
      ((s.cast ⋯).push (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).ref) =
    res
hidx1 : curr < w
hidx2 : curr ≤ curr
⊢ ⟦assign,
      { aig := (aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).aig,
        ref :=
          {
            gate :=
              ((aig.mkIfCached { discr := discr, lhs := lhs.get curr h✝, rhs := rhs.get curr h✝ }).ref.cast ⋯).gate,
            hgate := ?isTrue.inl.hstart } }⟧ =
    if ⟦assign, { aig := aig, ref := discr }⟧ = true then ⟦assign, { aig := aig, ref := lhs.get curr hidx1 }⟧
    else ⟦assign, { aig := aig, ref := rhs.get curr hidx1 }⟧

Tactic:
simp

Result:
no goals