-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Var.lean
theorem go_denote_eq (aig : AIG BVBit) (a : Nat) (assign : Assignment) (curr : Nat)
    (hcurr : curr ≤ w) (s : AIG.RefVec aig curr) :
    ∀ (idx : Nat) (hidx1 : idx < w),
        curr ≤ idx
          →
        ⟦
          (go aig w a curr s hcurr).aig,
          (go aig w a curr s hcurr).vec.get idx hidx1,
          assign.toAIGAssignment
        ⟧
          =
        ((BVExpr.var (w := w) a).eval assign).getLsbD idx

Proof state:
case isFalse
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
h✝ : ¬curr < w
hgo :
  (let_fun hcurr := ⋯;
    { aig := aig, vec := hcurr ▸ s }) =
    res
⊢ ⟦assign.toAIGAssignment, { aig := res.aig, ref := res.vec.get idx hidx1 }⟧ = (eval assign (var a)).getLsbD idx

Tactic:
omega

Result:
no goals

Proof state:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
⊢ ⟦assign.toAIGAssignment,
      { aig := (go aig w a curr s hcurr).aig, ref := (go aig w a curr s hcurr).vec.get idx hidx1 }⟧ =
    (eval assign (var a)).getLsbD idx

Tactic:
generalize hgo : go aig w a curr s hcurr = res

Result:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hgo : go aig w a curr s hcurr = res
⊢ ⟦assign.toAIGAssignment, { aig := res.aig, ref := res.vec.get idx hidx1 }⟧ = (eval assign (var a)).getLsbD idx

Proof state:
case inl.hidx
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hlt : curr < w
hgo :
  go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
      ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯ =
    res
heq : curr = idx
⊢ idx = curr

Tactic:
rw [heq]

Result:
no goals

Proof state:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hgo : go aig w a curr s hcurr = res
⊢ ⟦assign.toAIGAssignment, { aig := res.aig, ref := res.vec.get idx hidx1 }⟧ = (eval assign (var a)).getLsbD idx

Tactic:
unfold go at hgo

Result:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hgo :
  (if hcurr : curr < w then
      let res := aig.mkAtomCached (BVBit.mk a ⟨curr, hcurr⟩);
      let aig_1 := res.aig;
      let bitRef := res.ref;
      let s := s.cast ⋯;
      let s := s.push bitRef;
      go aig_1 w a (curr + 1) s ⋯
    else
      let_fun hcurr := ⋯;
      { aig := aig, vec := hcurr ▸ s }) =
    res
⊢ ⟦assign.toAIGAssignment, { aig := res.aig, ref := res.vec.get idx hidx1 }⟧ = (eval assign (var a)).getLsbD idx

Proof state:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hlt : curr < w
hgo :
  go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
      ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯ =
    res
heq : curr = idx
⊢ ⟦assign.toAIGAssignment,
      {
        aig :=
          (go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
              ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯).aig,
        ref :=
          (go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
                  ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯).vec.get
            idx hidx1 }⟧ =
    (eval assign (var a)).getLsbD idx

Tactic:
rw [go_get]

Result:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hlt : curr < w
hgo :
  go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
      ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯ =
    res
heq : curr = idx
⊢ ⟦assign.toAIGAssignment,
      {
        aig :=
          (go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
              ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯).aig,
        ref := (((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref).get idx ?inl.hidx).cast ⋯ }⟧ =
    (eval assign (var a)).getLsbD idx

case inl.hidx
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hlt : curr < w
hgo :
  go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
      ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯ =
    res
heq : curr = idx
⊢ idx < curr + 1

Proof state:
case inl.hstart
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hlt : curr < w
hgo :
  go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
      ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯ =
    res
heq : curr = idx
⊢ ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate <
    (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig.decls.size

Tactic:
simp [Ref.hgate]

Result:
no goals

Proof state:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hlt : curr < w
hgo :
  go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
      ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯ =
    res
heq : curr = idx
⊢ ⟦assign.toAIGAssignment,
      {
        aig :=
          (go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
              ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯).aig,
        ref := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯ }⟧ =
    (eval assign (var a)).getLsbD curr

Tactic:
rw [go_denote_mem_prefix]

Result:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hlt : curr < w
hgo :
  go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
      ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯ =
    res
heq : curr = idx
⊢ ⟦assign.toAIGAssignment,
      { aig := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig,
        ref := { gate := ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate, hgate := ?inl.hstart } }⟧ =
    (eval assign (var a)).getLsbD curr

case inl.hstart
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefVec curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry BVBit w
hlt : curr < w
hgo :
  go (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig w a (curr + 1)
      ((s.cast ⋯).push (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) ⋯ =
    res
heq : curr = idx
⊢ ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate <
    (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig.decls.size