-- Mathlib/.lake/packages/lean4/src/lean/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations/Add.lean
theorem go_denote_eq (aig : AIG α) (curr : Nat) (hcurr : curr ≤ w) (cin : Ref aig)
    (s : AIG.RefVec aig curr) (lhs rhs : AIG.RefVec aig w) (assign : α → Bool)
    (lhsExpr rhsExpr : BitVec w)
    (hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, lhs.get idx hidx, assign⟧ = lhsExpr.getLsbD idx)
    (hright : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, rhs.get idx hidx, assign⟧ = rhsExpr.getLsbD idx)
    (hcin : ⟦aig, cin, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false) :
    ∀ (idx : Nat) (hidx1 : idx < w),
        curr ≤ idx
          →
        ⟦
          (go aig lhs rhs curr hcurr cin s).aig,
          (go aig lhs rhs curr hcurr cin s).vec.get idx hidx1,
          assign
        ⟧
          =
        ⟦aig, lhs.get idx hidx1, assign⟧.xor
          (⟦aig, rhs.get idx hidx1, assign⟧.xor
            (BitVec.carry idx lhsExpr rhsExpr false))

Proof state:
case inr.hcin
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefVec curr
lhs rhs : aig.RefVec w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
hlt✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig (lhs.cast ⋯) (rhs.cast ⋯)
      (curr + 1) ⋯ (mkFullAdder aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).cout
      ((s.cast ⋯).push (mkFullAdder aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).out) =
    res
hlt : curr < idx
⊢ ((⟦assign,
            { aig := (mkFullAdderOut aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig,
              ref := { gate := (lhs.get curr hlt✝).gate, hgate := ⋯ } }⟧ ^^
          ⟦assign,
            { aig := (mkFullAdderOut aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig,
              ref := { gate := (rhs.get curr hlt✝).gate, hgate := ⋯ } }⟧) &&
        ⟦assign,
          { aig := (mkFullAdderOut aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig,
            ref := { gate := cin.gate, hgate := ⋯ } }⟧ ||
      ⟦assign,
          { aig := (mkFullAdderOut aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig,
            ref := { gate := (lhs.get curr hlt✝).gate, hgate := ⋯ } }⟧ &&
        ⟦assign,
          { aig := (mkFullAdderOut aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig,
            ref := { gate := (rhs.get curr hlt✝).gate, hgate := ⋯ } }⟧) =
    (lhsExpr.getLsbD curr).atLeastTwo (rhsExpr.getLsbD curr) (BitVec.carry curr lhsExpr rhsExpr false)

Tactic:
rw [AIG.LawfulOperator.denote_mem_prefix (f := mkFullAdderOut)]

Result:
case inr.hcin
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefVec curr
lhs rhs : aig.RefVec w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
hlt✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig (lhs.cast ⋯) (rhs.cast ⋯)
      (curr + 1) ⋯ (mkFullAdder aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).cout
      ((s.cast ⋯).push (mkFullAdder aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).out) =
    res
hlt : curr < idx
⊢ ((⟦assign, { aig := aig, ref := { gate := (lhs.get curr hlt✝).gate, hgate := ?inr.hcin } }⟧ ^^
          ⟦assign,
            { aig := (mkFullAdderOut aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig,
              ref := { gate := (rhs.get curr hlt✝).gate, hgate := ⋯ } }⟧) &&
        ⟦assign,
          { aig := (mkFullAdderOut aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig,
            ref := { gate := cin.gate, hgate := ⋯ } }⟧ ||
      ⟦assign, { aig := aig, ref := { gate := (lhs.get curr hlt✝).gate, hgate := ?inr.hcin } }⟧ &&
        ⟦assign,
          { aig := (mkFullAdderOut aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig,
            ref := { gate := (rhs.get curr hlt✝).gate, hgate := ⋯ } }⟧) =
    (lhsExpr.getLsbD curr).atLeastTwo (rhsExpr.getLsbD curr) (BitVec.carry curr lhsExpr rhsExpr false)

case inr.hcin
α : Type
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefVec curr
lhs rhs : aig.RefVec w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := lhs.get idx hidx }⟧ = lhsExpr.getLsbD idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦assign, { aig := aig, ref := rhs.get idx hidx }⟧ = rhsExpr.getLsbD idx
hcin : ⟦assign, { aig := aig, ref := cin }⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefVecEntry α w
hlt✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).aig (lhs.cast ⋯) (rhs.cast ⋯)
      (curr + 1) ⋯ (mkFullAdder aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).cout
      ((s.cast ⋯).push (mkFullAdder aig { lhs := lhs.get curr hlt✝, rhs := rhs.get curr hlt✝, cin := cin }).out) =
    res
hlt : curr < idx
⊢ (lhs.get curr hlt✝).gate < aig.decls.size