Yüksek hızlı baskı devre kartlarında sinyal bütünlüğünün incelenmesi
Investigation of signal integrity in high speed printed circuit boards
Yazar: KÜBRA AÇELYA PEHLİVAN
Danışman: DOÇ. DR. MUSTAFA BERKE YELTEN
İstanbul Teknik Üniversitesi / Lisansüstü Eğitim Enstitüsü / Elektronik ve Haberleşme Mühendisliği Ana Bilim Dalı / Elektronik Mühendisliği Bilim Dalı
Derece: Yüksek Lisans, 2023
Konu: Elektrik ve Elektronik Mühendisliği = Electrical and Electronics Engineering
Dizin: Devre kartları = Circuit boards ; Haberleşme sistemleri =   ; Karakteristik empedans = Characteristic impedance ; Simülasyon =   ; Sinyal =

Özet:
Modern elektronik cihazlarda sinyal hızlarının oldukça artması ile yüksek hızlı iletim hatlarının olduğu PCBlerin tasarımı daha çok dikkat gerektiren hale gelmiştir. Dijital haberleşme sistemlerinde sinyal bütünlüğü ve elektromanyetik uyumluluğun sağlanması daha da önem kazanmıştır. Bu PCBlerin tasarımında farklı tasarım teknikleri ve parametreleri kullanılması gerekmektedir. Yüksek hızlı iletim hatları çizilirken bu tasarım parametrelerine dikkat edilmesi gerekmekte, aksi durumda kartta sinyal kayıpları ve hataları oluşabilmektedir.
Aynı zamanda bu PCBlerin doğru bir şekilde analiz edilmesi ve simüle edilmeleri, sinyal bütünlüğünün sağlanması ile oluşabilecek hataların önceden görülebilmesini ve düzeltilebilmesini, ayrıca üretim maliyetinin düşürülmesini sağlar. 
Sinyal bütünlüğü problemleri, yansıma ve iletim kayıpları kaynaklı sinyal zayıflaması ve sinyaller arasında oluşan çapraz karışma kaynaklıdır. Bu problemleri en aza indirmede değişik tasarım parametreleri ve yaklaşımları etkili olmaktadır. Bu parametreler PCB için stack-up, yerleşim, iletim hattının geometrisi, kullanılan bağlantı ve terminasyon elemanları olarak belirtilebilir.
Bu tez kapsamında yukarıda açıklanan tasarım parametreleri ve sinyal bütünlüğü konusu literatür araştırması yapılarak kapsamlı olarak ele alınmıştır. Daha sonra bu parametrelerden bazıları belirlenerek simülasyonlar gerçekleştirilmiş ve bu parametrelerin iletim hattının sinyal bütünlüğü üzerindeki etkileri incelenmiş ve yüksek hızlı iletim hatlarının bulunduğu PCBler için bir tasarım modeli oluşturmak hedeflenmiştir. Kullanılan parametreler stack-up ve malzeme seçimi, seri komponentlerin etkisi, via türü ve yapısıdır. Simülasyonlarda çok katlı PCB'lerde sinyal bütünlüğü için önemli bir tasarım parametresi olan vialar üzerinde yoğunlaşılmıştır. Via geometrisinin sinyal bütünlüğüne etkisi via ped çapı, delik çapı, diferansiyel vialarda vialar arası mesafe, antiped çapı, paylaşımlı via anti-ped yapısı, fonksiyonel olmayan via pedleri, via yüksekliği ve via kalıntıları çerçevesinde incelenmiştir. Bu parametreler ile sinyal bütünlüğü sonuçları karakteristik empedans ölçümü, yansıma ve iletim kayıpları kapsamında karşılaştırılmıştır ve bu parametrelerin sinyal bütünlüğü üzerindeki etkisi gösterilmiştir. Simülasyon sayıları artırılarak bu parametrelerden hangilerinin sinyal bütünlüğüne daha baskın olarak etki ettiği ve via optimizasyonu için nasıl bir yol izlenebileceği araştırılmıştır. Aynı zamanda teorik olarak bilinen etkilerin seviyesi simülasyon ile belirlenerek fayda-zarar analizinin yapılmasının kolaylaştırılması amaçlanmıştır.
Karakteristik empedansın hesaplanması ve stack-up oluşturulması için Saturn PCB Design ve Advanced Design System (ADS) programları kullanılmıştır. Hatların şematik ve PCB çizimleri için Altium Designer Programı, simülasyonlar için ise 3 boyutlu tam dalga elektromanyetik alan simülatörü eklentisi bulunan ADS programı kullanılmıştır.

Abstract:
With the increase in signal speeds in modern electronic devices, the design of Printed Circuit Boards with high-speed transmission lines has become a more important issue.  For example, digital communication systems such as Ethernet and PCIE reach speeds of up to 64 GT/s on a single lane. In addition, the density and complexity of the boards increases. Ensuring signal integrity and electromagnetic compatibility in digital communication systems has become even more important. Different design techniques and parameters should be used in the design of these high speed PCBs. These design parameters and techniques should be considered and verified when designing high-speed transmission lines, otherwise, signal losses and errors may be occured on the board.
The design should be supported and validated by simulations in pre-layout and post-layout stages. Correct analysis and simulation of high speed PCBs ensures that the errors that may occur by ensuring signal integrity can be predicted and corrected. Simulation reduces production cost as it enables nonconformities to be understood before production. 
Signal integrity problems are caused by signal attenuation due to reflection and transmission losses and noise due to crosstalk between signals. Impedance discontinuity and the relationship between propagation delay with rise time are fundamental issues in signal integrity. Different design parameters and approaches are effective in minimizing signal integrity problems. These parameters can be specified as stack-up and PCB material selection, layout, trace geometry of the transmission lines and via geometry. Moreover, the connection and termination components are important parameters for high speed signal integrity. At the same time, the suitability of these parameter selections for production and cost effectiveness are also important and other challenging issue.
Within the scope of this thesis, the design parameters and signal integrity explained above have been comprehensively discussed by literature research. Some of these parameters were selected and simulations were carried out and the effects of these parameters on the signal integrity of the transmission lines were examined and it was aimed to create a design model for PCBs with high-speed transmission lines.
The parameters used are stack-up and material selection, serial component effect, via type and structure. The simulations focused on vias, which is an important design parameter for signal integrity in multilayer PCBs. The effect of via geometry on signal integrity was investigated in terms of via pad diameter, drill diameter, distance between vias in differential vias, antipad diameter, shared via anti-pad structure, non-functional via pads, via height and via stubs. These parameters and signal integrity results were compared within the scope of characteristic impedance, reflection and transmission losses, and the effect of these parameters on signal integrity was shown. At the same time, it is aimed to facilitate the benefit-harm analysis by determining the level of theoretically known effects by simulation.
Saturn PCB Design and Advanced Design System (ADS) programs were used to calculate the characteristic impedance and create a stack-up. Altium Designer Program was used for the schematic and PCB drawings of the transmission lines, and ADS program with a 3D full-wave electromagnetic field simulator plug-in was used for simulations.
An 8-layer 1.6 mm board stack-up with 4 signal layers and 4 reference planes is used in simulations. Another 2 mm stack-up was used to observe the via stub effect. The differential characteristic impedance of the differential lines was chosen as 100 Ohm and the lines were drawn accordingly. In the simulations, high frequency TDR, reflection loss and transmission loss graphs of the signals were obtained and signal integrity was examined.
The effects of via pad diameter, distance between vias in differential vias, antipad diameter, shared antipad structure, whether non-functional pads are removed or not, via height and via stubs on TDR response and accordingly reflection loss and transmission loss were investigated. It has been observed that via pad diameter, drill diameter, via height increase and the presence of non-functional pads increase the via capacitance and cause a decrease in the differential characteristic impedance. On the other hand, it was observed that the increase in the distance between the differential vias and the diameter of the via antipad caused an increase in the differential characteristic impedance.
Via stub effect was found to be more effective in reflection loss and transmission loss than other parameter changes. The positive effects of special via types and processes that reduce via stub effect on signal integrity were investigated. The effect of the use of extra vias, which can be used to reduce the via stub effect, on the signal integrity has been investigated and it has been observed that it gives positive results compared to the situation where special via types are not used.
In addition, since the capacitive and inductive effects of the specified parameters are different, it has been seen that they should be considered and examined as a parameter set. For the optimization of via geometric parameters, the number of simulations has been increased and the dominance of the effect of these parameters on the TDR response has been examined and it has been suggested that the optimization process be applied with this dominance order. The parameters examined for optimization are pad diameter, drill diameter, distance between differantial vias, antipad diameter with and without antipads combined, and distance of ground stitching vias. When the simulation results were graphed in the Matlab program, it was seen that the most dominant parameter was the pad diameter and drill diameter, and the least dominant parameter was the distance of the ground stitching vias. It has been observed that the distance between the vias and the antipad diameters in the shared and non-shared cases have similar effect.
In addition, the effect of leaving a cutout region in the planes under the series components such as AC coupling capacitors and thus providing compensation in differential characteristic impedance on signal integrity at high frequencies was investigated.
The last parameter whose effect on the signal integrity is examined is the effect of the loss tangent of the dielectric material used. The effect of low loss dielectric material and standard FR-4 dielectric material on transmission loss at high frequencies was investigated and compared.