Yüksek çözünürlüklü, direnç dizesi tipli sayısaldan analoğa dönüştürücülerde dinamik hata mekanizmalarının incelenmesi
Investigating dynamic error mechanisms of high resolution resistor string D/A converters
Yazar: EMRE TOPÇU
Danışman: YRD. DOÇ. DR. TÜRKER KÜYEL
İstanbul Teknik Üniversitesi / Fen Bilimleri Enstitüsü / Elektronik ve Haberleşme Mühendisliği Ana Bilim Dalı
Derece: Yüksek Lisans, 2012
Konu: Elektrik ve Elektronik Mühendisliği = Electrical and Electronics Engineering

Özet:
Sayısal  analog dönüştürücüler (Digital-to-Analog Converters / DAC) sayısal düzlemdeki işaretleri analog düzleme çevirirken, analog  sayısal dönüştürücüler (Analog-to-Digital Converters / ADC) analog düzlemdeki işaretleri sayısal düzleme çevirirler.Direnç dizesi gerilim çıkışlı DAC mimarisi genel olarak her bir sayısal girişe karşılık direnç dizesinin farklı bir noktasından gerilim seçer ve çıkıştaki yük bir çıkış tamponuyla sürülür. Bu mimariler monoton ve oldukça hassas yerleşme karakteristiklerine sahipken çözünürlük ve hız problemleri vardır. Yüksek hızlı direnç dizesi ve ara değer bulan OPAMP (operational amplifier) mimarilerinin bulunmasıyla yüksek hız ve çözünürlükte direnç dizesi gerilim çıkışlı DAC tasarımları yapılabilmiştir. Üretim sırasında meydana gelen statik hatalar ve uyumsuzluklar, lazer kırpma ve sayısal kalibrasyon teknikleriyle çözüm bulmuş olsa da bu mimarilerin dinamik hata mekanizmaları henüz çözüm bulmamıştır.Bu tez çalışmasında direnç dizesi gerilim çıkışlı DAC mimarisinin dinamik hata mekanizmaları incelenecektir. Analizler için test düzenekleri Cadence platformunda, BSIM 3.3 modelleri ve 0.15um 1.8V-3.3V CMOS teknolojisi kullanılarak oluşturulmuştur. Test düzenekleri sadece tek bir hata mekanizması devrede olacak şekilde tasarlanmıştır. Bu amaç için birçok bloğun ideal modelleri kullanılarak analog-sayısal birlikte olacak şekilde benzetimler yapılmıştır. Bu analizler sırasında bir C kodu yardımıyla saf sinüs verisi üretilerek DAC girişine verilmiş ve analog çıkışın DFT'si alınarak SFDR (Spurious Free Dynamic Range) hesaplanmıştır.Yapılan analizler sonucu RC zaman sabitinin koda bağlı değişmesinin direnç dizesi DAC mimarisinde en baskın dinamik hata mekanizması olduğu görülmüştür. Bu tez çalışmasında 8 temel hata mekanizması bulunmuş ve bu hata mekanizmaları için çeşitli mimariler önerilmiştir.İlk olarak OPAMP giriş kapasitesinin koda bağlı değişiminin DAC'ın dinamik doğrusallığını bozan baskın bir hata mekanizması olduğu görülmüştür. Sadece bu hata mekanizması bile diğer bütün bloklar ideal modelleriyle kullanıldığı durumunda 1 MHz'deki SFDR'ı 75 dB'ye düşürmektedir. Bu hata mekanizmasının çözümü için işlevsiz OPAMP girişi sisteme dahil edilerek ve çoklayıcı anahtarları ters yönde anahtarlanarak kod bağımsız OPAMP giriş kapasitesi elde edilmiş ve diğer herşey ideal olduğunda 1 MHz'deki SFDR 106 dB'lere çıkarılmıştır.İkinci hata mekanizması, direnç dizesinden görülen koda bağlı eş değer dirençtir. Her kod için bu dizeden görülen eş değer direncin farklı olması koda bağlı RC zaman sabiti oluşturur ve tek başına oldukça baskın bir dinamik hata mekanizmasıdır. Bütün diğer bloklar için ideal modelleri kullanıldığı durumda bile SFDR performansı 1 MHz'de 66 dB'dir. Bu hata mekanizması direnç dizesine her kod için farklı değerde seri birer direnç koyularak çözülmüştür ve herşey ideal olduğunda 1 MHz'deki SFDR performansı 66 dB'den 104 dB'ye çıkartılmıştır.Direnç dizesinden gerilim seçen anahtarların koda bağlı olarak VGS geriliminin değişmesi ve buna bağlı olarak da iletim dirençlerinin değişmesi RC zaman sabitinin koda bağlı değişmesine sebep olur ve yeni bir hata mekanizmasını oluşturur. Koda bağlı iletim direncini sabit tutabilmek için uzun yıllardır kullanılan sabit VGS yapısına ek olarak iki farklı sabit VBS yapısı önerilmiştir. Bu mimarilerde temel olarak her kod için iletimde olacak anahtarın VBS gerilimi sabit tutularak, kod bağımsız VTH, dolayısıyla da kod bağımsız iletim direnci elde edilmeye çalışılmıştır.Kapalı transistorlerin overlap kapasitelerinin VGD gerilimine bağlı değiştiği ve bunun kod bağımlı RC zaman sabitine yol açtığı gösterilmiştir. Bu dinamik hata mekanizmasının çözümü içinse kapalı transistorlerin geçitlerini çıkış geriliminin belirli bir miktar aşağısına sürecek, sabit VGD yapısı önerilmiştir.Anahtarlama sırasında meydana gelen yük enjeksiyonu ve saat geçiş beslemesi (clock feedthrough) problemlerinin de baskın bir hata mekanizması oluşturduğu gösterilmiştir. Sabit VGD yapısının yük enjeksiyonu hata mekanizmasının etkisini iki katına çıkardığı gösterilmiş ve sabit VGD yapısı gerçeklemesi yapılmamıştır.Bu tez çalışmasında şimdiye kadar tasarlanmış dinamik doğrusallığı en yüksek olan direnç dizesi gerilim çıkışlı DAC mimarisi referans olarak alınmıştır. Bu mimarinin SFDR performansı 1 MHz'de 54 dB, 200 KHz'de 64 dB'dir. Bulunan bütün hata mekanizmaları ve önerilen mimariler dikkate alınarak yapılan tasarımında SFDR performansı 1MHz'de 72 dB, 200KHz'de 90 dB olacak şekilde iyileştirilmiştir.

Abstract:
Digital-to-analog converters (DACs) convert digital signals to the analog domain while analog-to-digital converters (ADCs) convert signals from the analog to the digital domain. In this work, resistor string voltage output DAC architectures will be taken into consideration.In order to drive time varying loads with good linearity and precision settling, a digital to analog converter with an output buffer is needed. The buffered current steering DAC architecture is fast, but it is non-monotonic and it has sub-par precision settling characteristics. The settling problem is due to voltage and temperature coefficients of the feedback resistor of the output buffer implemented as an I-to-V converter. On the other hand, a buffered resistor string DAC is monotonic, settles to a precision voltage, but it has the disadvantages of speed and resolution.For resistor string DACs, a novel segmentation architecture solved the resolution problem and a series of 16-bit monotonic resistor string CMOS DACs recently gained popularity in the industry for low power, low bandwidth applications. A roadmap to 18-bits and above is foreseeable in the near future. DC nonlinearities of these 16-bit DACs can be digitally calibrated; however, the dynamic issues remain mostly unsolved, and these DACs are rarely used for waveform generation applications. The purpose of this study is to help extend the applications of high-resolution resistor string DACs to waveform generation applications from DC to 1 MHz of output frequency.A very important performance metric for waveform generation applications is the spurious free dynamic range (SFDR). SFDR is the distance (in dB) between the fundamental frequency and the highest spur in the power spectrum. When SFDR improves, total harmonic distortion (THD) and intermodulation distortion (IMD) also improve. For this reason, we chose SFDR as the performance benchmark metric.This study is based on simulation alone, and no actual hardware is built or tested in a laboratory environment. To run the simulations, Spectre, a SPICE-like circuit solver, is used on Cadence software platform. BSIM 3.3 models of a 015µ 1.8V ? 3.3V CMOS process are used in our simulations. Dynamic behavior of the output amplifier is beyond the scope of this work and the focus is on the DAC. Considering the best available class AB CMOS amplifiers give 81 dB SFDR at 1 MHz output frequency, it is our intent to improve the DAC performance to a level that, the opamp, not the DAC, is the limiting factor on the SFDR.First, a simulation test-bench is formed to measure the SFDR of the 16-bit DAC. The test-bench generates segment-driving waveforms and evaluates a coherent fast Fourier transform (FFT) of the DAC output based on the desired sampling rate and the desired output frequency. An ideal, behavioral DAC is constructed to test the performance of digital inputs and switch driving waveforms. Every time an actual transistor based DAC simulation is run, it is verified that the ideal behavioral DAC?s SFDR performance under the same setting is well over 100 dB. The test-benches are designed in the analog-mixed-signal (AMS) environment of the Cadence software platform to be able to use ideal models for most blocks while investigating each error mechanisms for the non-ideal blocks one at a time. This methodology helps eliminate the interactions between multiple error mechanisms.In this work, 8 different dynamic error mechanisms are identified and various design techniques are suggested to help reduce the errors associated with these error mecahnisms. Simulations show that the dominant effect on SFDR is code-dependent RC time constant.The first mechanism for code dependent time constant is due to the input capacitance of the interpolating amplifier. The 6 LSBs of the binary coded digital input code get converted to thermometer code, and the 63 thermometer code outputs and their complements drive 63 pairs of NMOS switches in a complementary fashion. Each switch pair has their sources connected to the positive input of a single PMOS differential pair structure that belongs to the OPAMP, and their drains connected to vhi and vlo respectively. One differential pair is constantly tied to vlo, making a total of 64 differential pairs. Under digital control, when two consecutive tap voltages from the string vhi and vlo are duplicated M times and 64-M times for the interpolation amplifier, vhi will be connected to M differential pair positive inputs, whereas vlo will be connected to 64-M differential pair positive inputs. Due to the gate capacitance of the differential pair positive inputs, there will be a different amount of capacitance connected to vhi and vlo nodes, depending on the state of 6 least significant digital inputs. This causes code dependent capacitance differences between vhi and vlo.As a solution, we propose a complementary switching structure and a secondary interpolating amplifier input stage so that Vhi and Vlo are duplicated 64-M times and M times respectively. This way, Vhi and Vlo will be connected to a total of 64 differential pairs each. For a single ended implementation, this structure has to be a dummy structure; however, for a differential implementation, this structure will be utilized as the negative input of an amplifier used in an instrumentation amplifier type setting. This constant capacitive load improvement causes the SFDR to jump from 75 dB to 106 dB at 1MHz, when everything else is ideal.Even if the code dependent capacitance problem is solved, a code dependent resistance problem remains. The second mechanism causing code dependent time constant is the code dependent AC resistance of the string. Depending on the tap point selected, resistors of two different values will be connected in parallel and this will cause a code dependent resistance seen at each tap point. This is an effect driven by the most significant bits of the digital DAC input, as the 10 MSB bits drive a 32x32, 1-out-of-1024 type row-column decoder to select the string tap voltage. The effective resistance is the lowest at the lowest and highest tap points, and highest at the mid tap point.This error mechanism can be eliminated if a series calibration resistor is placed at each tap point. The values of these series resistors are mathematically computed so that the impedance at each switch source is held constant. That is, higher series resistances are added at the top and bottom portions of the string and lower series resistances are added at the mid sections. The addition of series resistors slows down the string, but the settling time of the string becomes the same across all tap points. If the switches are ideal, the addition of series resistance to the string combined with the constant-C amplifier improves the performance from 66 dB to 104 dB.Resistor string switches have code-dependent VGS voltages, so code-dependent on resistances. This causes code-dependent RC time constant and deteriorates dynamic linearity. Bootstrapping the switch is known and has being used for many years. An additional resistor ladder is used to generate the bootstrap voltages. This technique provides a certain degree of code independent on resistance; however, from the simulation of a dummy series switch, it becomes obvious that to get good SFDR, eliminating the body effect is also necessary. Creating a VBS connection on the switches to reduce the body effect does not work because it turns on the reverse biased diodes on some of the OFF switches. Therefore, it becomes obvious that the VBS connection is needed only for the ON switch, resulting in a selective VBS bootstrap switch structure, where VBS connection depends whether the switch is ON or OFF. Another alternative to have constant VBS is to shift R-String operating region to have a higher voltage range and to bias bodies of the switch to incrementally increasing voltages, which are generated by an auxilliary resistor string. For instance, the operating region of the R-String can be set 1.0V-0.5V instead of 1.0V-0V and the bodies can be biased between 0.5V-0V. In this case, the reverse biased diodes problem does not exist. Constant Vgs implementation for tap switches are effectively used in the final architecture, but constant Vbs implementation is found to be not as significant.Overlap capacitance is known to be constant when the transistor is either in saturation or in triode; however, it is highly nonlinear when the transistor is in cutoff, due to depletion of the source and drain diffusion surfaces. In the resistor string structure, for each transistor that is ON, there are 31 transistors that are OFF. For this reason, the effects of the gate drain capacitance of the OFF transistors are very significant and they unfortunately present a nonlinear (voltage dependent) capacitance at the string tap point. This nonlinear gate drain capacitance is much more significant than the reverse biased junction capacitances of the switches. To reduce the gate-drain nonlinear overlap capacitance effect, the gate-drain voltage of the OFF switches must be held constant. The drain voltage of all the OFF switches must be at the output voltage of the ON switch. Given this constraint, the gate voltages of the OFF switches must be taken from an auxiliary resistor string such that VGD is constant. Since constant VGD approach increases effect of charge injection, it is not implemented in the final architecture.In this work, it is shown that charge injection is the next dominant error mechanism on SFDR. It is found that the string switches are responsible for the majority of the charge injection mechanism, and it is also found that charge injected on the amplifier, not on the string, causes the SFDR problem. SFDR caused by charge injection is predominantly a second order distortion, which could be reduced by a differential architecture. Clock feedthrough effect is found to be not as significant as the charge injection effectA high-speed, high resolution, 16-bit R-String DAC product (DAC8580) is taken as a comparison benchmark. From its datasheet, it is obvious that the SFDR performance of this product is dominated by dynamic effects. The DC calibrated SFDR performance of the DAC8580 is 102dB at 1 KHz and 62 dB at 200 KHz. The SFDR of our proposed DAC shows 90 dB at 200 KHz. However, one must keep in mind that our work is based on SPICE simulations on a faster CMOS process, using an ideal behavioral amplifier.