Paralel işaret işleme sistemi ve bir uygulama
A Parallel signal processing system and an application
Yazar: FATİH KURUGÖLLÜ
Danışman: PROF. DR. A. EMRE HARMANCI
İstanbul Teknik Üniversitesi / Fen Bilimleri Enstitüsü / Kontrol ve Otomasyon Mühendisliği Ana Bilim Dalı
Derece: Yüksek Lisans, 1994
Konu: Bilgisayar Mühendisliği Bilimleri-Bilgisayar ve Kontrol = Computer Engineering and Computer Science and Control
Dizin: İşaret işleme = Signal processing ; İşlemciler = Processors

Özet:
Bu çalışmada TMS320C25' lerden oluşmuş paralel bir sayısal işaret işleme sistemi sunulmuştur. Sistem donanımı iki ana işlemci kartı, işlemciler arası haberleşmede kullanılan biryardımcı kartı ve işlemcilerle kullanıcı arasında arayüz sağlayan bir IBM-PC bilgisayarı içerir. Sayısal işaret işlemci olarak TMS320C25 seçilmiştir. İşlemcilerin birbirleri ilevePCileolan haberleşmesinde çift kapılı RAM belleklerden ve kesme işaretlerinden yararlanılmıştır. Donanım üzerinde paralel programlama geliştirilmesine imkan vermek üzere, bir paralel hata ayıklayıcı programı da gerçekleştirilmiştir. Bu program kullanıcıya; yaptığı programı program belleklerine veri yükleme ve geri alma, veri belleklerine yükleme ve geri alma, program/veri belleklerini gözleme ve değiştirme, işlemci saklayıcılarını gözleme ve değiştirme, adım adım program yürütme, durak noktası koyarak program yürütme imkanı verir. Gerçeklenen sistem üzerinde, uygulama olarak DES veri şifreleme algoritmasının paralelleştirilmesi gerçekleştirilmiş vesırasal yazılan algoritmaya göre 1.54 oranında hızlanma sağlanmıştır. VI-

Abstract:
Signal processing is an important subject of electronicengineering. Typically, there exist two ways of processing signals depending on the type of the processing devices used. While the first generally uses analogue devices such resistors, capacitor, inductors and active elements and is called analogue signal processing, the second which is called digital signal processing uses digital techniques and digital computers. Digital signal processing encompasses a broad spectrum of applications ranging from digital filtering, speech vocoding, image processing, fast Fourier transforms and digital audio. These applications and those considered digital signal processing applications have several characteristic in common: - they involve mathematically intensive algorithms - they seek real-time applications - they use sampled data implementation - they provide system flexibility Over the past several decades, digital signal processing machines have taken on several evolutions in order to incorporate these characteristics. Large mainframe computers were initially used to process signals in the digital domain. Typically, because of the state-of-the art limitations, this processing was done in nonreal time. As the state-of-the art advanced, array processors were added to the processing task. Because of their flexibility and speed, array processors have become the accepted solution for research laboratory, and have been extended to end applications in many instances. However, as the integrated circuit technology has matured, thus allowing the design of faster microprocessors and microcomputers, many digital signal processing applications have migrated from array processors to microprocessor systems to single chip integrated circuit solutions. A recent development in DSP technology is the single chip DSP such as the TMS320familiy of processors. These processorsgivethedesignera DSP solution with its performance attainable only by the array processors a few decades ago. Speed and power of these devices have increased dramatically with each generation of processors and DSP-based devices can now be used in a range of applications that include graphics, control, telecommunication, defense electronicand scientific number crunching. However, the increasing power and speed of DSP devices either do not usually meet the demand of the used or the devices which meet the demand of the user are very expensive. In this case, multiple DSP systems can provide an appropriate solution to the demand for additional computing power to support complex operations. A primary design objective of a multiple DSP system is the enhancement of the system performance, throughput and real time application. -vn-In this thesis, a PC-based multiple DSP system using two TMS320C25 devices is proposed. There are some advantages of using a PC clone as a host computer. One of them is thatthe prototype hardware and software can be ported to embedded applications with little or no modification. Also, PC-based DSP boards are easy to learn thus allowing the userto begin developping and evaluating algorithms in ashort times (i.e., fewweeks). The communication between DSP and PC or between DSP and DSP can be the most critical factor in the system is often the primary bottleneck to throughput. Since real time signal processing systems generally have a high throughput of data then the choice of a particular type of data transfer mode is an important decision to be made. There are several possible memory and input/output (I/O) communication strategies which include I/O port, dual access memory, dual bank-memory, dual port memory, direct memory access (DMA) and serial interfaces. Preliminary analysis has found that the dual port memory interface scheme has the best ratio of performance/cost and as such has been chosen in the present work for as the interface technique for communication between DSP and PC, and between DSP and DSP. The system designed uses a modular methodology using two mother boards and one daughter board. The mother board which is an IBM-PC add-on card consists of a TMS320C25 DSP device and its peripherials and a dual port memory for communicating with the PC clone and two parallel ports for communication with the second motherboard and other peripherials. The daughter board which is used forcommunication with the two DSP modules consists of a dual port memory. The following is the specifications of the motherboards: -TMS320C25 16-bit DSP - 32Kx1 6 EPROM for use as program memory - 8Kx1 6 RAM for use as program memory - 8Kx1 6 RAM for use as data memory - 2Kx1 6 dual port memory for communication with PC clone - A wait state generator for slow memories - Interrupt logic circuitry for use in DSP and PC clone The address of the dual port memory for the PC clone is selectable thus providing modularity. That means the each board can be used as a single processing unit oras a part of the parallel system using the two modules. Interrupt circuits, which are also selectable through jumpers, are used via I/O ports from the PC clone to the DSP devices and vice versa. This is achieved via a dedicated piece of software where the PC uses INT1 pin of theTMS320C25 module. The two motherboards can then communicate to each other as these parts are directly connected to the daughterboard via the dual port memory where each DSP device uses its interrupt and general purpose input and output pins to stroke each other. The INTO pin of the DSPs are connected reciprocally through an I/O port. On the other hand, the XF flag of aDSP isconnectedto INT2orBI0pinoftheotherDSPviaasetofjumpers. The block diagram of the parallel system is shown as figure I. The design of a software development tools is very important task in any hardware system design. The debugging is of paramount of importance in such system design. Therefore, a parallel processing system must have a parallel debuggerenvironment. Such environment generally consists of two sections. One of these sections called high level debugger runs on the host computer and supervises other section which runs on the system1 s processors and called low level debugger. -vm-TMS3EOCE5 I/O PORT F : oo : oo 5 0 i- _INT0 £- I N B T S 2 0 3£ H D -R-.5- DUAL PORT RAM ^~ jJ2 -fit D R 5t DAUGHTER BOARD îMOTHER :board :#1 I/O PORT I H 01 2 5fl 1- F )lNT0 TMS32BC25 MOTHER BOARD #2 Figure I Block diagram of the parallel system In this thesis, a parallel debugger program has been developed and it allows the userwith the following facilities: - program download/upload - data download/upload - inspect and modify program and data memory - inspect and modify processor registers - set breakpoints in user program - single step through user program - run user program to a breakpoint ParDeb communicates with the host via dual port ram. Whenever the host (PC) sends to the processor (or processors) a command, it writes the command code to the first address of communication ram. Then data deals with the commands is written to communication ram if the command has data. Finally, the host signalsthe target processor/processors by interrupt (INTO) line. The processor enters the interrupt service routine wheneverii receives intteruptfrom the host. Then it interprets the command comes from the host and performs the desired task. The host accesses the registers of the processor via processor4 s area in the dual port ram. If updating the registers requires, writing the update values to the processor's register area by the host is enough. The host does not notify the processor for updating the registers. Wheneverthe processor gets an execution command ( Run or Run-to-breakpoint) from the host, it loads its registers from values the processor' s register area. After execution the command isfinished, the EX-processorwrites the current register values to corresponding dual port ram area. Then it signals the host. Finally, The host uses these updating values. The parallel debugger (ParDeb) has been developed without any additional hardware cost. Therefore, there are some restrictions for user programs. User programs which run in DSPs can communicate viaXF-INT2 1 ine to each other. Other DSP interrupt lines are used by the parallel debugger program which runs on the system EPROM and uses some portions of program RAM and some of PC-DSP communication RAM. Therefore, the user programs must not access these memory portions. Furthermore, the user can not use the DINT command in his/her program as this command causes the breakdown of the debugger. The programming of the parallel digital processing system has been achieved by using a data encryption algorithm as it is widely used in many signal processing application such as modem and speech transmission. Most encryption sschemes that are any good are highly secret. An encryption, issued by the U.S. National Bureau of Standarts(NBS). The DES has an open structure. Inthiswork, therefore, the DES algorithm has been chosen as encryption method. The DES consists of almost entirely bit-level permutations, substitutions, shifts and shuffling. It is designed for hardware implementation on a single VLSI chip; such chips are available commercially. But high-level programming of the DES algorithm is possible and is necessary since the encryption step is integrated to many computer and communication systems. The basic DES is substitution chiper which takes block of 64 bits of input to a unique block of 64 bits to output, underthe control of a 64 bit key, which is known only to the system intended to read the message ( The actually key size is 56 bits, the remaining 8 being predictable parity checks). As long as the key is held fixed, the same 64 bits of input will always produce the same 64 bits of output. The mapping of inputto output is one-to-one and invertible, so that the message can be decrypted. The DES has three distinguishable components. First there is the key shedule. This is simply a certain presciption for taking the 56 active bits in the key and shuffling them into 1 6 diffirent configurations, each 48 bits long. The shuffling procedure is complicated, but straightforward; bits are never combined with other bits, ormoditled, but only moved around from place to place. Inotherwords.thekey schedule makes 16 "subkeys" out of a "master key". This need be done only whenever the key is changed, not every time an input block is enciphered. Second, as the heart of the DES, there is a cipherfunction. This is a fixed, highly non-linearfunction which combines 32 bits of input (a half-word of the total block being encrypted ) with 48 bits of subkey to produce 32 bits of highly random output. The procedure in detail is to expand the 32 bits to 48 bits by a permutation that repeats some bits twice, then to add the expanded input to the 48-bit subkey ( bit by bit modulo 2 ). Then, most important, the 48 bits are reduced down to 32 bits of output by atablelook-upwhich maps every sequential bits into4bits. Thistable, which is called the S-box, is the soul of the algorithm. It is a point of controversy that the theory behind the design of the S-boxhas never been fully revealed. Finally in the chiperfunction, a bitwise permutation of the 32 output bits is performed. Third, the original 64 bits of input are putthrough afixed initial permutation and then divided into two half-words of 32 bits each. Now 1 6 stages of the following procedure are performed: One half-word is passed on to the next stage, untouched. That same half-word is also sent, with one of the 16 subkey keys, to the cipher function, producing a 32 bit random configuration. The half-word which has not yet -X-been used is now encrypted by adding it ( bitwise modulo 2 ) to this random configuration and then passed on to the next stage. Between each stage, the half- words are exchanged, so that the one passed on unchanged is notthe one thatwas passed on unchanged in the previous transition. After all 1 6 stages are complete, the two half-words are recombined through a specified bitwise permutation into the output 64-bit block. The main drawback of the DES algorithm is its key size (56 bits). This short key allows the breaking of the DES cryptosystem in about 1 2 hours of computation if an exhaustive cryptanalytic attack is carried out on the system [Diffie 1 977]. However, some techniques are used to increase the complexity of the DES and one of them is achieved by changing the key with each block. Such a system is essentially a one-time pad and is known to be secure against any cryptanalytic attack. However, the process of changing the key with every plaintext decreases the performance of the system dramatically as the management of the key and the subkey generation of the DES algorithm is a very time consuming operation which can take up as much as that of the main DES body. Oneway of solving this problem can be achieved by the use of a dual DSP system. In such a system, one of the DSP modules generates the subkeys and the other executes the encryption steps. This scheme has been adopted in this thesis and a speed-up factor of about 1.54 has been achieved. XI-