Polisilisyum tabaka üzerine fotolitografi yöntemi 0,3 mikron şekillendirme prosesinin optimizasyonu
Optimization of 0,3 µm photolithography process parameters over polysilicon layer
Yazar: ZELİHA ÖZDOĞAN
Danışman: PROF. DR. HÜSNÜ ATAKÜL
İstanbul Teknik Üniversitesi / Fen Bilimleri Enstitüsü / Malzeme Bilimi ve Mühendisliği Ana Bilim Dalı / Malzeme Bilimi ve Mühendisliği Bilim Dalı
Derece: Yüksek Lisans, 2014
Konu: Mühendislik Bilimleri = Engineering Sciences

Özet:
Yarı iletken teknolojisi haberleşme, bilişim ve otomasyon sistemlerinde yaygın olarak kullanılır ve bu alanlardaki gelişmeler aynı zamanda yarı iletken teknolojisinin gelişimine bağlıdır. Yarı iletken teknolojisi temel olarak; optik yöntemler ve ince film kaplama teknolojileri (litografi) kullanılarak, kritik boyutun nanometre seviyesine inmesiyle birlikte gelişmektedir. Litografi prosesinin gelişimi sayesinde boyutların küçülerek birçok devrenin aynı anda üretilmesi, elektronik devrelerin ucuz ve az güç harcayan yapılar haline gelmesini sağlanmıştır. Yarıiletken teknolojisinde, teknolojik seviyeyi belirleyen en önemli kriter tümdevredeki en küçük boyuttur ve kritik boyut olarak tanımlanır. Kritik boyutun küçülmesi daha hızlı çalışan devrelerin üretilmesini, iş kabiliyetinin artmasını, maliyetin düşmesini ve güç tüketiminin azalmasını sağlar ve kritik boyut küçüldükçe de litografi teknolojisindeki gelişmeler kaçınılmaz olmuştur. 
1950'li yıllarından sonra yarıiletken üretim süreçlerinde çoğunlukla fotolitografi (optik litografi) kullanılmaya başlanmıştır ve tümdevre üretim basamakları arasında önemli bir yere sahiptir. Günümüzde fotolitografi işlemi için tercih edilen yöntemlerden biri UV-litografidir. Belirli bir dalga boyundaki UV ışık bir maske üzerinden, bu dalga boyundaki ışığa duyarlı, silisyum pul üzerine serilmiş olan fotoreziste (ışığa duyarlı polimer) iletilir. Maskenin üzerinde bulunan mikro ya da nano boyutlu şekiller, birbirini takip eden bir takım kimyasal işlemler sonunda yarı iletken üzerine transfer edilmiş olur.
Kritik boyut, şekillendirme yapılan dalga boyu ve 'k' sabiti ile doğru orantılı, lensin sayısal açıklığı (NA) ile de ters orantılıdır. Dalga boyu ve sayısal açıklık, şekillendirme cihazı (stepper) ve ışık kaynağı' nın özellikleri olduğu için kullanılan teknolojiye ait değerlerdir. Bu nedenle 'k' sabitinin standart proses şartlarında aldığı değer (0,75) çeşitli yöntemlerle düşürülerek, dalga boyundan daha küçük şekillendirmeleri gerçekleştirmek mümkün olur. Bu yöntemlerden en pratik ve ekonomik olanı, termal ve kimyasal proseslerden oluşan litografi prosesinin adımlarını optimize etmek ve şekil bozukluklarında en büyük paydaya sahip olan ince film ve yansıtıcı alt yüzey etkisini azaltmaktır. Şekillendirilecek boyut küçüldükçe, yüzey topografisi düzgün olmayan ve yansıtıcı olan pul yüzeyinde kritik boyut kontrolünü sağlamak ve ince film etkisini ortadan kaldırmak en kritik problemlerdir, çünkü ışığın istenmeyen bölgelere yansıması şekil bozukluklarına ve ince film etkisi de kritik boyut farklılıklarına neden olur. 
Bu çalışmadaki amaç da SiGeC HBT BiCMOS Teknolojisi için 0,3 mikron şekillendirme prosesini 365 nm dalga boyunda gerçekleştirebilmek için litografi prosesinin tüm adımlarını optimize etmek ve düzgün yüzey topografisine sahip olmayan yansıtıcı pul yüzeyinin negatif etkisini en aza indirmektir Standart koşullarda 365 nm (UV) dalga boyundaki ışık kaynağı ile şekillenebilecek en küçük kritik boyut 0,35 µm'dir. 
Litografi prosesinin tüm adımlarının sonuç değişkenleri ile bunları etkileyen faktörler ve seviyeleri, literatür ve kullanılan cihazların özellikleri dikkate alınarak belirlenmiştir. Fotorezist ve yansıma önleyici kaplamanın pul yüzeyine serilmesi ve son adım olan sertleştirme prosesi için faktörlerin optimum seviyeleri, deneysel tasarım metotlarından biri olan Taguchi yöntemi kullanılarak tespit edilmiştir. Yarı iletken üretimi hem maliyetli hem de üretimi etkileyen çok fazla parametre olduğu için deneysel tasarım metotlarının, özellikle de Taguchi yönteminin sıklıkla kullanıldığı bir sektördür. Fotolitografi işlemi tespit edilen optimum parametre seviyelerinde gerçekleştirilerek düzgün bir profile sahip olan 0,3 mikron şekillendirme gerçekleştirilmiştir. Yapılan şekillendirme işlemi de 'k' sabitinin standart olan 0,75 değerinden 0,5 mertebesine düştüğünü göstermektedir. Bu süreçte en önemli adımlar; yansıma önleyici kaplamanın seçimi ve şekillendirme ile kuru aşındırma prosesleri dikkate alınarak, optimum fotorezist kalınlığının belirlenmesi olmuştur. Hem krtik boyut kontrolünü sağlamak ve hem de alt tabandaki topografiden dolayı şekillerde oluşacak bozulmayı önlemek için en etkili yöntemin alt taban üzerine uygulanan yansıma önleyici kaplama olduğu sonucuna varılmıştır.
Yapılan deneylerin sonuçları özetlenirse; 

•	Şekillerin profilini bozmadan kritik boyutu sağlayabilmek için fotorezist kalınlığının aşındırma prosesine dayanacak şekilde incelmesi gerekmektedir. Fotorezist kalınlığı 0,6 mikrona indirildiğinde kritik boyut sağlanmış ve fotorezist dibe kadar açılarak profil bozulmamıştır. 

•	Fotorezist kalınlığı üzerinde en etkili olan faktör serme işlemi sırasındaki son döndürme hızıdır ve 600 nanometre fotorezist kalınlığı için optimum seviye 5000 devir/dk' dır. Pulun yüzeyini tamamen kaplamak için gerekli olan rezist akıtma süresi 3 sn. (3 ml/sn) olarak bulunmuştur. 

•	Pul yüzeyindeki yansımayı ve yansıma değişimini minimum seviyeye düşürmek için serme prosesi parametrelerinin optimum seviyeleri, yansıma önleyici kaplama miktarı için 2 ml, ilk döndürme hızı için 500 devir/dk ve son döndürme hızı için 2500 devir/dk olarak bulunmuştur. Bu proses parametreleri kullanılarak pul yüzeyindeki yansıma düz silisyum pula göre %6 seviyesine düşürülmüştür. 

•	Işıklandırma sonrası yapılan kürleme işlemi 110 Cº' de gerçekleştirildiğinde, hem kritik boyutun sağlandığı hem de profil açısının 90º'ye daha yakın olduğu görülmüştür. Sıcaklık yükseldikçe profil bozulmuştur. 

•	Pul yüzeyindeki ışıklanmış ve ışıklanmamış alanların yansıma farkı karşılaştırılarak optimum banyo süresinin 60 saniye olduğu görülmüştür. 

•	Litografi prosesinin son adımı olan fotorezistin sertleştirme işlemine etki eden parametreler (son pişirme süresi, son sıcaklık ve yükselme eğimi), kuru aşındırma prosesine karşı pozitif fotorezistin direnci ve kritik boyuttaki değişim göz önünde bulundurularak değerlendirilmiştir. Son pişirme süresi ve yükselme eğiminin optimum seviyeleri 10 saniye ve 1,5 Cº/saniye 'dir. Sadece aşınma direnci dikkate alındığında son sıcaklığın optimum seviyesi 170 Cº  olarak bulunmuş, fakat bu seviye 60 nm kritik boyut değişimine neden olduğu için, her iki sonuç değişken de dikkate alınarak optimum seviye 150 Cº olarak belirlenmiştir.

Abstract:
Integrated Circuit (IC),  is a collection of electronic components, fabricated as a single unit, in which active devices (transistors, diodes, etc.) and passive devices (capacitors, resistors, etc.) and their interconnections are formed on a thin substrate of semiconductor material (typically silicon). They have an important role in the semiconductor technology. In the production of integrated circuits, five main processes are applied to silicon wafers in many times repeatedly. These are thermal processes, ion implantation, lithography, etching and deposition of layers. First of all, the layout of the circuit paths and electronic elements of a chip is created, after the design of the IC is completed. Lithography is used to transfer this layout; consists of sets of geometric shapes; onto surface of wafer.
A semiconductor process technology is generally described by the critical dimension (CD); which is the smallest feature that needs to be patterned on the wafer surface. The continuous reduction of the critical dimension is almost like a law; which is determined by the co-founder of Intel, Gordon Moore in 1965. Moore's Law states that the number of transistors per square centimeter roughly doubles every 18 months without increase in cost; which is possible by shrinkage of the CD. Critical dimension is patterned by the lithographic process and it is the most important characteristic in the manufacture of integrated circuits. Making the critical dimension smaller is the primary focus of improving semiconductor technology; because this dramatically increases the number of devices per unit area and this increase goes with the square of the CD. Also making the CD smaller of a device will make a smaller chip. This means that the number of chips per wafer increases dramatically, and since costs are related with the number of wafers and not the number of chips to a wafer, costs will be notably reduced.  The most important point is that; making the CD smaller makes devices more faster.  Therefore, improvements in lithography technology means that; better, faster and more complex circuits will be at lower cost. So lithography is one of the most important process in the production of integrated circuits.
Photolithography; also termed optical lithography, uses light to transfer a geometric pattern from a reticle to a light sensitive chemical (photoresist) on the wafer. Photolithography combines several steps in sequence; that are surface preparation and HMDS application; photoresist coating; soft baking; exposure and post exposure baking;  development; and finally hard-baking. The wafer is initially put into the oven and heated to a temperature sufficient to dehumidify of the wafer surface. In the same oven a gaseous adhesion promoter ("hexamethyldisilazane", HMDS), is applied to promote adhesion of the photoresist to the wafer. Then, a light sensitive photoresist is spun onto the wafer forming a thin layer on the surface.  In order to blow the excess photoresist solvent, the coated wafer is baked on a hotplate. The resist is then selectively exposed by the stepper through a mask (reticle) which contains the pattern information. The mask contains clear and opaque features that define the pattern to be created in the PR layer; in which areas exposed to the light are made either soluble or insoluble in a specific solvent known as a developer. In the case when the exposed regions are soluble, a positive image of the mask is produced in the resist ( positive resist). If the nonexposed regions are dissolved by the developer, a negative image results. (negative resist). Finally hard-bake process is made via heat and UV energy in order to prevent deformation of photoresist patterns by other thermal processes used in semiconductor production.

Both negative and positive photoresists are used in the photolithography process; but usually the positive one is chosen because of the higher resolution capabilities. Positive photoresist composed of three main ingredients; which are the matrix material (resin), photoactive compound (PAC) and the solvent. The matrix material serves as a binder and establishes the mechanical properties of the film. It is usually inert to the incident UV radiation but provides the resist film with its adhesion and etch resistance. PAC converted into the acid under the exposure and that makes the resin soluble in the developer, on the other hand unexposed PAC is not soluble in the developer. So exposed areas on the wafer are solved during development process. The solvent keeps the resist in the liquid state until it is applied to the wafer.  

Exposure systems; which  produce an image on the wafer using a mask;  may be classified by the optics that transfer the image from the mask to the wafer. The contact printer; which is the simplest one, puts a photomask in direct contact with the wafer and exposes it to a uniform light. Because contact printing can damage the surfaces of both the mask and the wafer; proximity and projection printing systems could be used in the production of integrated circuits. In proximity printing, the mask is brought in very close proximity to the wafer, not contacting with the wafer during exposure, thus preventing damage to the mask. But diffraction effects, because of the gap between the wafer and mask, limit accuracy of pattern transfer. Therefore the resolution obtained with the proximity printing is lower than the contact one. Finally; the most complicated one is projection printing; which uses a dual-lens system to project the pattern on the mask to the wafer by the de-magnification ratio between 1/4 and 1/10. They have an step and repeat mechanical sytstem; so the wafer stage takes a step by the die (chip) size and the illumination is repeated. Therefore they are called as stepper. The number of dies on the wafer is related to the chip size. Also they provide higher resolution than others. The resolution is highly related with the the wavelength of the light source. With the KrF (248 nm) source, the CD could be decreased to the 150 nm. Because of these reasons, they are given preference in the IC production today.

The aim of this thesis is to achieve 0,3 micron photolithography process; which is a production step in the SiGeC HBT BiCMOS technology; with the i-line (365 nm) stepper. At standart conditions the smallest critical dimension, which could be patterned by the 365 nm light source ( Hg lamp), is 0,35 µm. At the beginning of the study a research about  techniques to realize subwavelength lithography was made. The most economical and effective one was applied in order to pattern 0,3 micron wide holes on the polysilicon and oxide deposited wafer. All of the experimental studies were made in the Tübitak-UEKAE Semiconductor Technologies Research Laboratory (YITAL). 
Critical dimension is a positive fuction of the wavelength and k1 costant, but a negative function of the numerical aperture. Wavelength is directly related with the light source and NA with focusing optics of the illumination system. So these are the specifications of the stepper; which is used.  The value of the k1 constant is around 0,75 for the standart normal illumination. By using super illumination mode; which is related with the input lens of the stepper; the value of the k1 could be reduced. Also using some reticle techniques such as phase shift mask (PSM) or optical proximity correction (OPC) lead to a reduction of the k1 value. Finally the other way to decrease of the k1 value is optimisation of the lithography process parameters and applying anti reflective coating during the lithography process in order to reduce reflective notching caused by light reflected into unwanted areas and thin film interference effects. From these techniques, the last one is chosen; because it is most practical and economic one. As critical dimensions in current semiconductor manufacturing are into the submicron range, thin film interference effects and substrate reflectivity play a very important role in linewidth control. Linewidth variation and reflective notching are results of the reflective substrate. Also small resist thickness differences across dies are induced by underlying topography and lead to changes in absorbed energy from optical projection steppers. These variations in resist absorbed energy are characterized by the "swing curve", which shows the periodic swing from a maximum dose to clear to a minimum dose to clear as a function of film thickness. If swing ratio could be reduced to near zero, the resist process is able to tolerate changes in optical phase due to resist coating variations, topography and deposited film thickness non-uniformity. 
The swing ratio could be reduced by decreasing substrate reflectivity via bottom layer anti-reflection coating (BARC) or decreasing resist surface reflectivity via top layer anti-reflection coating (TAR). In this study organic BARC was chosen; because it provides both the largest reduction in swing amplitude and reflective notching. BARC can reduce negative effects of topography and deposited film thickness non-uniformity by improved planarization and reduced reflectivity of the substrate. TAR  requires not added etching process like organic BARC; because they are soluble in water. But TAR does not eliminate reflective notching from topographical features and is not effective to reduce swing amplitude as BARC. 
Before starting to experimental works, all of the photolithography process steps have been analysed one by one and process parameters and response variables defined by taking into account literature search and capabilities of process equipments; which are used in the experiments. Deposited layers on monocrystalline silicon wafers with diameter of 100 mm (4 inch) ; which were used in the experiments; are 500-600 Å thermal oxide, 1000 Å polysilicon and 1000 Å oxide  respectively. Deposition system of polysilicon and oxide layers is low pressure chemical vapour deposition (LPCVD). Chemicals used in experiments are OİR 38A9 & OİR 620-09 as positive photoresists, OPD 262 (2,38% TMAH) as developer and I-CON 16 & I-CON 7 as BARC. Two types of photoresist and BARC were used in order to see effects of coating thickness on the pattern dimension and profile. Canon FPA - 3000 i4 stepper was used during exposure of BARC and photoresist coated wafers. The NA value of the stepper is 0,63 and the wavelength of the ligt source (Hg lamp) is 365 nm. Quartz masks for the exposure system are imported in YITAL as chrome and photoresist coated; which are ready to pattern generation. For this study only one patterned mask is used. Therefore the mask was not a variable factor on the pattern dimension and profile. CEE 200X model spinner from Brewer Science was used for photoresist and BARC coating. Photoresist is poured automatically on the center of wafer from the cartridge dispensing system; but BARC is poured manually with a pipette. The developer used is from the same firm as spinner and model number is CEE 200XD. 
At the end of the photolithography process, hard-baking is made with heat or heat and UV exposure in order to prevent deformation of photoresist patterns by other thermal processes used in semiconductor production. In this study, this process step was made with heat and UV exposure via Fusion System's 200 PCU photostabilizer. The lamp system of this tool includes a high powered, microvawe operated UV source and reflective optics to provide a uniform UV irradiance on the wafer surface. 
Reflection on the wafer after BARC coating and photoresist thickness were measured with the NanoSpec210 model film thickness measurement system from Nanometrics. Photoresist thickness measurement was made on bare silicon wafers; because nonuniformities of deposited layers could cause inaccurate measurements. On the other hand; oxide and  polysilicon deposited wafers have been used for BARC coating process optimization, because reflection on the substrate is changing with type and thickness of deposited layers. Vistec INS 3000 model microscope was used for measurements of pattern dimensions. This microscope gets images of patterns with UV or DUV light source and is capable of taking measurements of so small patterns (0,3 µm). FIB (focused ion beam) tool was used to take profile images of patterns at the end of the photoresist process. 
In the experiments, optimization of process parameters has been realized for each process step respectively. Although coating of BARC on the substrate is the first step of this lithography process, optimization of photoresist (PR) coating parameters has been done initially by considering PR thickness mean and uniformity of thickness. Because PR thickness measurement has been done on bare silicon wafers without BARC coating. Taguchi method and analysis of variance (ANOVA) have been used ın order to find optimum levels of parameters and the most significant factors in both thickness mean and the uniformity of thickness. Taguchi method provides an economical and systematic method for determining the optimum levels of process parameters. Depending on the objective, there are three different mean square deviations for the signal–noise ratios that can be defined including nominal-the-better, larger-the-better, and smaller-the-better. For this study, lower thickness and thickness nonuniformity on the wafer surface during the PR coating process is preferred. Therefore, the smaller-the-better S/N ratio formula was chosen for PR process. After determining optimum levels of parameters, value of response variable is calculated at the point of optimum levels and this calculated value is compared by making experiment at the same point for the verification of the Taguchi method. For PR coating process, OİR 620-09 coded PR gives the minimum thickness and the calculated value at optimum levels of parameters is 5650 Å. By making experiment, the thickness was measured as 5850 Å. Also nonuniformity of thickness was calculated as 1,2% and measured as 0,92%. As a result, measurement results are reasonable with calculated ones. Thikness measurement has been done after soft bake process; because it causes to diffuse of excess solvent in the PR and effects the thickness. Soft bake process parameters (temperature & time) were determined by taking into account the literature and the degradation temperature of photoactive compound in the PR; which is 100 C°. The temperature was determined as 90 C° and time as 60 sec. 
In the second step of experiments; the most suitable BARC was selected for this study by considering reflection values on the wafer after BARC coating, the effect of exposure dose on the critical dimension and depth of focus values. The main difference between these two types of coating material is their kinematic viscosities and thus thickness on the substrate with same coating parameters. Kinematic viscosity of I-Con 7 is smaller than I-Con 16 and thus thinner coating could be done by using I-Con 7. Initially, Taguchi method was applied in order to find optimum levels of BARC coating parameters. Lower reflection and reflection nonuniformity on the wafer surface is preferred certainly. So, the smaller-the-better S/N ratio formula was chosen for BARC coating process. Three parameters (used chemical volume, first spinning rate and second spinning rate) and three levels for each parameter has been defined for this process step and L9 design of Taguchi's arrays was used by considering the number of parameters and levels. According to results of experiments, the minimum reflection value on the wafer with I-Con 7 is 3% and with I-Con 16 is 15%. In order to minimize both reflection and reflection nonuniformity values, optimum levels of parameters has been defined via Taguchi method. The calculated value at the optimum point is 5,68% for the reflection and 12,5% for the nonuniformity. Also experiment was done with optimum levels of parameters and the reflection was mesaured as 6% and the nonuniformity as 10,5%. Measurement results have been found reasonable with calculated ones. Then, the effect of exposue dose (J/m2 ) on the critical dimension has been determined by measuring the critical dimension change by 100 J/m2 increment. It has been found as 2% for the thinner material and  5% for the other. Depth of focus values are 1,2 µm for the thinner material and  0,6 µm for the other. These results show that; we get smaller swing ratio by using thinner BARC material; because it decreases the reflectivity on the wafer more than the other. Also; we do not need thicker BARC coating for this substrate because of its uniformity of topography. In the third step of experiments, exposure dose and focus values have been determined for both of BARC coating matertial. Exposure dose for I-con 7 coated wafer was found higher than other; because the exposure dose increases as reflection decreases. 
Aim of fourth step of experiments is defining the post exposure bake temperature and duration; that the wafer surface should be subjected to developer solution. Three samples  have been prepared by making post bake step at different temperatures (95°C, 110°C and 125°C). Microscope images of these three samples show that; dissolution rate of exposed PR is decreasing with increasing temperature and this effects pattern profiles negatively. The sample at 110°C gives the best result in terms of CD and pattern profile. For the develop time, six samples have been prepared by increasing time from 30 sec to 80 sec by 10 sec steps. After development process; the reflection on the exposed and non-exposed regions of the same wafer have been measured for six samples and differences between these two values have been calculated. 60 sec development time gives the highest difference of reflection. This result and FIB images show that; optimum development time is 60 sec. At the last step of experiments, optimization of hard-baking process parameters was made via Taguchi method. The optimum data set for the resistance of PR to etching goal is, 170 °C as final temperature, 1,5 °C /sec as ramp rate and 10 sec as post-bake time; which is realized at the final temperature without UV energy. But the final temperature was decreased to 150 °C by taking into consideration of CD change because of thermal process. 
As a result of experiments, 0,3 µm photolithography process has been achieved by a stepper; whose NA is 0,63 and light source wavelength is 365 nm. This shows that; k1 value was decreased from 0,75 to around 0,5 by decreasing the reflection on the subtrate and making photolithography process at optimum levels of process parameters.