The very reason why there are only  bits used for addressing in PAE mode is that the very first  processor using segmentation to address physical memory where segment register such as CS is bit but referring bit long segments after shifting  bits to the left Keeping this schema if there were bit real mode then  bits used for referring segments   bits base address   bits for logical addresses But this is not the truth but just a guide to draw the reason why In Intel and IA Architectures Software Developers Manual it says M is an abbreviation for MAXPHYADDR which is at most  where M is used in PDE PTE and PPDE without further explanation But I dont believe for AMD architecture that would be the extreme limit for the physical addressing If further AMD processor gets rid of legacy mode completely then there would potentially bits for addressing physical memory rather than bits like it in Itanium architecture That might be wrong but just put a stop to end this topic