Question: MERSI protocol was used by the computer that was a fourth generation of what type of processors?

full_context: Document 1: Power Macintosh 6100: The Power Macintosh 6100 is a personal computer designed, manufactured and sold by Apple Computer from March 1994 to March 1996 as part of the Power Macintosh line. It is first computer to use the new PowerPC processor created by IBM and Motorola. The low-profile ("pizza box") case was inherited from the Centris/Quadra 610 and 660AV models, and replaced the Macintosh Quadra series that used the Motorola 68040 processor, Apple's previous high end workstation line. It was the earliest Macintosh model able to run Mac OS 9.
Document 2: Mortgage Electronic Registration Systems: Mortgage Electronic Registration Systems, Inc. (MERS) is an American privately held corporation. MERS is a separate and distinct corporation that serves as a nominee on mortgages after the turn of the century and is owned by holding company MERSCORP Holdings, Inc., which owns and operates an electronic registry known as the "MERS system", which is designed to track servicing rights and ownership of mortgages in the United States.
Document 3: Apple A5: The Apple A5 is a 32-bit system-on-a-chip designed by Apple Inc. and manufactured by Samsung and is the successor to the Apple A4. The A5 commercially debuted with the release of Apple's iPad 2 tablet, and also powers the iPhone 4S, iPod Touch fifth generation, Apple TV third generation, and the iPad mini. This is consistent with how Apple debuted the A4 chip: first in the original iPad, followed by the iPhone 4, and then the iPod Touch (fourth generation). Apple claims that compared to its predecessor, the A4, the A5 CPU "can do twice the work" and the GPU has "up to nine times the graphics performance".
Document 4: MERSI protocol: The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4. The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I). The M, E, S and I states are the same as in the MESI protocol. The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system. Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state. In both the MESI and MERSI protocols, the transition from the E to M is silent.
Document 5: Power Macintosh 9500: The Power Macintosh 9500 (sold as Power Macintosh 9515 in Europe and Asia) is a personal computer designed, manufactured and sold by Apple Computer as part of the Power Macintosh line from May 1995 until February 1997. It is powered by a PowerPC 604 processor, a second-generation PowerPC chip which was faster than the PowerPC 601 chip used in the Power Macintosh 8100. The 180MP and 200 MHz models, introduced August 1996, use the enhanced PowerPC 604e processor.
Document 6: Philips 68070: The SCC68070 is a Philips Semiconductors-branded, Motorola 68000-based 16/32-bit processor produced under license. While marketed externally as a high-performance microcontroller, it has been almost exclusively used combined with the Philips SCC66470 VSC (Video- and Systems Controller) in the Philips CD-i interactive entertainment product line.
Document 7: Stimulus protocol: In telephony, a stimulus protocol is a type of protocol that is used to carry event notifications between end points. Such a protocol is used to control the operation of devices at each end of the link. However a stimulus protocol is not sensitive to the system state. In a typical application such a protocol will carry keystroke information from a telephone set to a central call control. It may also carry control information for simple types of text displays. MiNET from Mitel is a typical protocol of this sort.
Document 8: Two-phase commit protocol: In transaction processing, databases, and computer networking, the two-phase commit protocol (2PC) is a type of atomic commitment protocol (ACP). It is a distributed algorithm that coordinates all the processes that participate in a distributed atomic transaction on whether to "commit" or "abort" ("roll back") the transaction (it is a specialized type of consensus protocol). The protocol achieves its goal even in many cases of temporary system failure (involving either process, network node, communication, etc. failures), and is thus widely used.
Document 9: Apple A4: The Apple A4 is a 32-bit package on package (PoP) system-on-a-chip (SoC) designed by Apple Inc. and manufactured by Samsung. It combines an ARM Cortex-A8 CPU with a PowerVR GPU, and emphasizes power efficiency. The chip commercially debuted with the release of Apple's iPad tablet; followed shortly by the iPhone 4 smartphone, the iPod Touch (4th generation), and the Apple TV (2nd generation). It was superseded by the Apple A5 processor used in the iPad 2 released the following year, which was then subsequently replaced by the Apple A5X processor in the iPad (3rd generation).
Document 10: Stanford DASH: Stanford DASH was a cache coherent multiprocessor developed in the late 1980s by a group led by Anoop Gupta, John L. Hennessy, Mark Horowitz, and Monica S. Lam at Stanford University. It was based on adding a pair of directory boards designed at Stanford to up to 16 SGI IRIS 4D Power Series machines and then cabling the systems in a mesh topology using a Stanford-modified version of the Torus Routing Chip. The boards designed at Stanford implemented a directory-based cache coherence protocol allowing Stanford DASH to support distributed shared memory for up to 64 processors. Stanford DASH was also notable for both supporting and helping to formalize weak memory consistency models, including release consistency. Because Stanford DASH was the first operational machine to include scalable cache coherence, it influenced subsequent computer science research as well as the commercially available SGI Origin 2000. Stanford DASH is included in the 25th anniversary retrospective of selected papers from the International Symposium on Computer Architecture and several computer science books, has been simulated by the University of Edinburgh, and is used as a case study in contemporary computer science classes.
Document 11: Dragon write-back update protocol: The Dragon Protocol is an update based cache coherence protocol used in multi-processor systems. Write propagation is performed by directly updating all the cached values across multiple processors. Update based protocols such as the Dragon protocol perform efficiently when a write to a cache block is followed by several reads made by other processors, since the updated cache block is readily available across caches associated with all the processors.
Document 12: Protocol (science): Formal protocol is the general rule in fields of applied science, such as environmental and medical studies that require the coordinated, standardized work of many participants. Such predefined protocols are an essential component of Good Laboratory Practice (GLP) and Good Clinical Practice (GCP) regulations. Protocols written for use by a specific laboratory may incorporate or reference standard operating procedures (SOP) governing general practices required by the laboratory. A protocol may also reference applicable laws and regulations that are applicable to the procedures described. Formal protocols typically require approval by a laboratory official before they are implemented for general use.
Document 13: PowerPC G4: PowerPC G4 is a designation used by Apple Computer and Eyetech to describe a "fourth generation" of 32-bit PowerPC microprocessors. Apple has applied this name to various (though closely related) processor models from Freescale, a former part of Motorola. Motorola and Freescale's proper name of this family of processors is PowerPC 74xx.
Document 14: I.MX: The i.MX range is a family of Freescale Semiconductor (now part of NXP) proprietary microcontrollers for multimedia applications based on the ARM architecture and focused on low-power consumption. The i.MX application processors are SoCs (System-on-Chip), that integrate many processing units into one die, like the main CPU, a video processing unit and a graphics processing unit for instance. The i.MX products are qualified for automotive, industrial and consumer markets. Most of them are guaranteed for a production lifetime of 10 to 15 years.Many devices use i.MX processors, such as Ford Sync, Kobo_eReader, Amazon Kindle, Sony Reader, Onyx Boox readers/tablets, SolidRun SOM's (including CuBox), some Logitech Harmony remote controls and Squeezebox radio, some Toshiba Gigabeat mp4 players. The i.MX range was previously known as the "DragonBall MX" family, the fifth generation of DragonBall microcontrollers. i.MX originally stood for "innovative Multimedia eXtension".
Document 15: Power Mac G4: The Power Mac G4 is a series of personal computers designed, manufactured, and sold by Apple Computer, Inc. from 1999 to 2004 as part of the Power Macintosh line. Built around the PowerPC G4 series of microprocessors, the Power Mac G4 was marketed by Apple as the first "personal supercomputers", reaching speeds of 4 to 20 gigaFLOPS. This was the first existing Macintosh product to be officially shortened as "Mac", and is the last Mac able to boot into classic Mac OS.
ground_truth: 32-bit PowerPC