# Buggy code
def _get_image_depth(self):
    """Get depth information for the circuit.

    Returns:
        int: number of columns in the circuit
        int: total size of columns in the circuit
    """

    max_column_widths = []
    # Determine row spacing before image depth
    for layer in self.ops:
        for op in layer:
            # useful information for determining row spacing
            boxed_gates = [
                "u0",
                "u1",
                "u2",
                "u3",
                "x",
                "y",
                "z",
                "h",
                "s",
                "sdg",
                "t",
                "tdg",
                "rx",
                "ry",
                "rz",
                "ch",
                "cy",
                "crz",
                "cu3",
                "id",
            ]
            target_gates = ["cx", "ccx"]
            if op.name in boxed_gates:
                self.has_box = True
            if op.name in target_gates:
                self.has_target = True
            if isinstance(op.op, ControlledGate):
                self.has_target = True

    for layer in self.ops:
        # store the max width for the layer
        current_max = 0

        for op in layer:
            # update current op width
            arg_str_len = 0

            # the wide gates
            for arg in op.op.params:
                arg_str = re.sub(r"[-+]?\d*\.\d{2,}|\d{2,}", _truncate_float, str(arg))
                arg_str_len += len(arg_str)

            # the width of the column is the max of all the gates in the column
            current_max = max(arg_str_len, current_max)

        max_column_widths.append(current_max)

    # wires in the beginning and end
    columns = 2

    # add extra column if needed
    if self.cregbundle and self.ops[0][0].name == "measure":
        columns += 1

    # all gates take up 1 column except from those with labels (ie cu1)
    # which take 2 columns
    for layer in self.ops:
        column_width = 1
        for nd in layer:
            if nd.name in ["cu1", "rzz"]:
                column_width = 2
        columns += column_width

    # every 3 characters is roughly one extra 'unit' of width in the cell
    # the gate name is 1 extra 'unit'
    # the qubit/cbit labels plus initial states is 2 more
    # the wires poking out at the ends is 2 more
    sum_column_widths = sum(1 + v / 3 for v in max_column_widths)

    max_reg_name = 3
    for reg in self.ordered_regs:
        max_reg_name = max(max_reg_name, len(reg.register.name))
    sum_column_widths += 5 + max_reg_name / 3

    # could be a fraction so ceil
    return columns, math.ceil(sum_column_widths)


# Traceback (IndexError)
Traceback (most recent call last):
File "test_latex_creg.py", line 6, in <module>
c = qc.draw(output='latex_source', cregbundle=True)
File "/home/ed/qiskit/qiskit-terra/qiskit/circuit/quantumcircuit.py", line 994, in draw
return circuit_drawer(self, scale=scale,
File "/home/ed/qiskit/qiskit-terra/qiskit/visualization/circuit_visualization.py", line 306, in circuit_drawer
return _generate_latex_source(circuit,
File "/home/ed/qiskit/qiskit-terra/qiskit/visualization/circuit_visualization.py", line 605, in _generate_latex_source
latex = qcimg.latex()
File "/home/ed/qiskit/qiskit-terra/qiskit/visualization/latex.py", line 149, in latex
self._build_latex_array(aliases)
File "/home/ed/qiskit/qiskit-terra/qiskit/visualization/latex.py", line 561, in _build_latex_array
self._latex[pos_2 + i][column] = \
IndexError: list index out of range

# Fixed code
def _get_image_depth(self):
    """Get depth information for the circuit.

    Returns:
        int: number of columns in the circuit
        int: total size of columns in the circuit
    """

    max_column_widths = []
    # Determine row spacing before image depth
    for layer in self.ops:
        for op in layer:
            # useful information for determining row spacing
            boxed_gates = [
                "u0",
                "u1",
                "u2",
                "u3",
                "x",
                "y",
                "z",
                "h",
                "s",
                "sdg",
                "t",
                "tdg",
                "rx",
                "ry",
                "rz",
                "ch",
                "cy",
                "crz",
                "cu3",
                "id",
            ]
            target_gates = ["cx", "ccx"]
            if op.name in boxed_gates:
                self.has_box = True
            if op.name in target_gates:
                self.has_target = True
            if isinstance(op.op, ControlledGate):
                self.has_target = True

    for layer in self.ops:
        # store the max width for the layer
        current_max = 0

        for op in layer:
            # update current op width
            arg_str_len = 0

            # the wide gates
            for arg in op.op.params:
                arg_str = re.sub(r"[-+]?\d*\.\d{2,}|\d{2,}", _truncate_float, str(arg))
                arg_str_len += len(arg_str)

            # the width of the column is the max of all the gates in the column
            current_max = max(arg_str_len, current_max)

        max_column_widths.append(current_max)

    # wires in the beginning and end
    columns = 2

    # add extra column if needed
    if self.cregbundle and (
        self.ops[0][0].name == "measure" or self.ops[0][0].condition
    ):
        columns += 1

    # all gates take up 1 column except from those with labels (ie cu1)
    # which take 2 columns
    for layer in self.ops:
        column_width = 1
        for nd in layer:
            if nd.name in ["cu1", "rzz"]:
                column_width = 2
        columns += column_width

    # every 3 characters is roughly one extra 'unit' of width in the cell
    # the gate name is 1 extra 'unit'
    # the qubit/cbit labels plus initial states is 2 more
    # the wires poking out at the ends is 2 more
    sum_column_widths = sum(1 + v / 3 for v in max_column_widths)

    max_reg_name = 3
    for reg in self.ordered_regs:
        max_reg_name = max(max_reg_name, len(reg.register.name))
    sum_column_widths += 5 + max_reg_name / 3

    # could be a fraction so ceil
    return columns, math.ceil(sum_column_widths)