#NEWLINE# def _translate_lsl( self , tb , instruction ) : #NEWLINE# #INDENT# if ( ( len ( instruction . operands ) == 3 ) and isinstance ( instruction . operands [ 1 ] , ArmRegisterOperand ) ) : #NEWLINE# #INDENT# sh_op = ArmShiftedRegisterOperand ( instruction . operands [ 1 ] , 'lsl' , instruction . operands [ 2 ] , instruction . operands [ 1 ] . size ) #NEWLINE# disp = tb . _compute_shifted_register ( sh_op ) #NEWLINE# tb . write ( instruction . operands [ 0 ] , disp ) #NEWLINE# return #NEWLINE# #UNINDENT# if ( ( len ( instruction . operands ) == 2 ) and isinstance ( instruction . operands [ 1 ] , ArmShiftedRegisterOperand ) ) : #NEWLINE# #INDENT# instruction . operands . append ( instruction . operands [ 1 ] . _shift_amount ) #NEWLINE# instruction . operands [ 1 ] = instruction . operands [ 1 ] . _base_reg #NEWLINE# #UNINDENT# oprnd1 = tb . read ( instruction . operands [ 1 ] ) #NEWLINE# oprnd2 = tb . read ( instruction . operands [ 2 ] ) #NEWLINE# result = tb . temporal ( oprnd1 . size ) #NEWLINE# tb . add ( self . _builder . gen_bsh ( oprnd1 , oprnd2 , result ) ) #NEWLINE# tb . write ( instruction . operands [ 0 ] , result ) #NEWLINE# if instruction . update_flags : #NEWLINE# #INDENT# self . _update_zf ( tb , oprnd1 , oprnd2 , result ) #NEWLINE# self . _update_nf ( tb , oprnd1 , oprnd2 , result ) #NEWLINE# if ( oprnd2 . immediate == 0 ) : #NEWLINE# #INDENT# return #NEWLINE# #UNINDENT# else : #NEWLINE# #INDENT# shift_carry_out = tb . _extract_bit ( oprnd1 , ( 32 - oprnd2 . immediate ) ) #NEWLINE# tb . add ( self . _builder . gen_str ( shift_carry_out , self . _flags [ 'cf' ] ) )