#NEWLINE# def elaborate_logic( s ) : #NEWLINE# #INDENT# s . wen_reg = Reg ( 1 ) #NEWLINE# s . connect ( s . wen_reg . in_ , s . wen ) #NEWLINE# s . wben_reg = Reg ( s . num_nbytes ) #NEWLINE# s . connect ( s . wben_reg . in_ , s . wben ) #NEWLINE# s . addr_reg = Reg ( s . addr_nbits ) #NEWLINE# s . connect ( s . addr_reg . in_ , s . addr ) #NEWLINE# s . wdata_reg = Reg ( s . data_nbits ) #NEWLINE# s . connect ( s . wdata_reg . in_ , s . wdata ) #NEWLINE# s . SRAM = m = SRAMBytesComb_rst_1rw ( s . num_entries , m . num_nbytes , reset_value = s . reset_value ) #NEWLINE# s . connect_dict ( { #NEWLINE# #INDENT# m . wen : s . wen_reg . out , #NEWLINE# m . wben : s . wben_reg . out , #NEWLINE# m . addr : s . addr_reg . out , #NEWLINE# m . wdata : s . wdata_reg . out , #NEWLINE# m . rdata : s . rdata , #NEWLINE# #UNINDENT# } )