#NEWLINE# def test_RegisterWrappedChain( setup_sim ) : #NEWLINE# #INDENT# model = RegisterWrappedChain ( 16 ) #NEWLINE# ( model , sim ) = setup_sim ( model ) #NEWLINE# transl = ( not hasattr ( model , 'reg0' ) ) #NEWLINE# sim . reset ( ) #NEWLINE# model . in_ . value = 8 #NEWLINE# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg0 . out . v == 0 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg1 . out . v == 0 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg2 . out . v == 0 ) #NEWLINE# #UNINDENT# assert ( model . out . v == 0 ) #NEWLINE# sim . cycle ( ) #NEWLINE# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg0 . out . v == 8 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg1 . out . v == 0 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg2 . out . v == 0 ) #NEWLINE# #UNINDENT# assert ( model . out . v == 0 ) #NEWLINE# model . in_ . value = 9 #NEWLINE# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg0 . out . v == 8 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg1 . out . v == 0 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg2 . out . v == 0 ) #NEWLINE# #UNINDENT# assert ( model . out . v == 0 ) #NEWLINE# model . in_ . value = 10 #NEWLINE# sim . cycle ( ) #NEWLINE# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg0 . out . v == 10 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg1 . out . v == 8 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg2 . out . v == 0 ) #NEWLINE# #UNINDENT# assert ( model . out . v == 0 ) #NEWLINE# sim . cycle ( ) #NEWLINE# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg0 . out . v == 10 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg1 . out . v == 10 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg2 . out . v == 8 ) #NEWLINE# #UNINDENT# assert ( model . out . v == 8 ) #NEWLINE# sim . cycle ( ) #NEWLINE# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg0 . out . v == 10 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg1 . out . v == 10 ) #NEWLINE# #UNINDENT# if ( not transl ) : #NEWLINE# #INDENT# assert ( model . reg2 . out . v == 10 ) #NEWLINE# #UNINDENT# assert ( model . out . v == 10 )