#NEWLINE# def test_portbundle_queue_sim( dump_vcd ) : #NEWLINE# #INDENT# test_vectors = [ [ 1 , 1 , 1 , 0 , 1 , '?' ] , [ 0 , 0 , 0 , 1 , 1 , 1 ] , [ 0 , 1 , 0 , 0 , 0 , '?' ] , [ 1 , 1 , 2 , 0 , 0 , '?' ] , [ 1 , 0 , 3 , 1 , 0 , 2 ] , [ 0 , 0 , 3 , 1 , 0 , 2 ] , [ 1 , 0 , 3 , 1 , 1 , 2 ] , [ 1 , 1 , 3 , 0 , 1 , '?' ] , [ 1 , 0 , 4 , 1 , 1 , 3 ] , [ 1 , 1 , 4 , 0 , 1 , '?' ] , [ 0 , 0 , 4 , 1 , 1 , 4 ] , [ 0 , 1 , 4 , 0 , 1 , '?' ] ] #NEWLINE# model = PortBundleQueue ( 16 ) #NEWLINE# model . vcd_file = dump_vcd #NEWLINE# model . elaborate ( ) #NEWLINE# def tv_in( model , test_vector ) : #NEWLINE# #INDENT# model . enq . val . v = test_vector [ 0 ] #NEWLINE# model . enq . msg . v = test_vector [ 2 ] #NEWLINE# model . deq . rdy . v = test_vector [ 4 ] #NEWLINE# #UNINDENT# def tv_out( model , test_vector ) : #NEWLINE# #INDENT# assert ( model . enq . rdy . v == test_vector [ 1 ] ) #NEWLINE# assert ( model . deq . val . v == test_vector [ 3 ] ) #NEWLINE# if ( not ( test_vector [ 5 ] == '?' ) ) : #NEWLINE# #INDENT# assert ( model . deq . msg . v == test_vector [ 5 ] ) #NEWLINE# #UNINDENT# #UNINDENT# sim = TestVectorSimulator ( model , test_vectors , tv_in , tv_out ) #NEWLINE# sim . run_test ( )