#NEWLINE# def test( ) : #NEWLINE# #INDENT# ( test_module , test_bench ) = read_verilog_module_initial . mkLedTest ( ) #NEWLINE# code = '' . join ( [ test_bench . to_verilog ( ) , test_module . to_verilog ( ) ] ) #NEWLINE# from pyverilog.vparser.parser import VerilogParser #NEWLINE# from pyverilog.ast_code_generator.codegen import ASTCodeGenerator #NEWLINE# parser = VerilogParser ( ) #NEWLINE# expected_ast = parser . parse ( expected_verilog ) #NEWLINE# codegen = ASTCodeGenerator ( ) #NEWLINE# expected_code = codegen . visit ( expected_ast ) #NEWLINE# assert ( expected_code == code )