#NEWLINE# def test( ) : #NEWLINE# #INDENT# filelist = [ ( codedir + 'ptr_clock_reset.v' ) ] #NEWLINE# topmodule = 'TOP' #NEWLINE# noreorder = False #NEWLINE# nobind = False #NEWLINE# include = None #NEWLINE# define = None #NEWLINE# analyzer = VerilogDataflowAnalyzer ( filelist , topmodule , noreorder = noreorder , nobind = nobind , preprocess_include = include , preprocess_define = define ) #NEWLINE# analyzer . generate ( ) #NEWLINE# directives = analyzer . get_directives ( ) #NEWLINE# instances = analyzer . getInstances ( ) #NEWLINE# terms = analyzer . getTerms ( ) #NEWLINE# binddict = analyzer . getBinddict ( ) #NEWLINE# output = [ ] #NEWLINE# output . append ( list ( binddict . values ( ) ) [ 0 ] [ 0 ] . tostr ( ) ) #NEWLINE# output . append ( '\n' ) #NEWLINE# rslt = '' . join ( output ) #NEWLINE# print ( rslt ) #NEWLINE# assert ( rslt == expected ) #NEWLINE# assert ( list ( binddict . values ( ) ) [ 0 ] [ 0 ] . getClockBit ( ) == 2 ) #NEWLINE# assert ( list ( binddict . values ( ) ) [ 0 ] [ 0 ] . getResetBit ( ) == 0 )