#NEWLINE# def pymtl_wrapper_from_ports( in_ports , out_ports , model_name , filename_w , vobj_name , xobj_name , cdefs ) : #NEWLINE# #INDENT# port_defs = [ ] #NEWLINE# for ( ports , port_type ) in [ ( in_ports , 'InPort' ) , ( out_ports , 'OutPort' ) ] : #NEWLINE# #INDENT# ports = [ ( name . replace ( '_M_' , '.' ) , nbits ) for ( name , nbits ) in ports ] #NEWLINE# lists = [ ] #NEWLINE# for ( port_name , bitwidth ) in ports : #NEWLINE# #INDENT# if ( '$' in port_name ) : #NEWLINE# #INDENT# pfx = port_name . split ( '$' ) [ 0 ] #NEWLINE# if ( pfx not in lists ) : #NEWLINE# #INDENT# lists . append ( pfx ) #NEWLINE# port_defs . append ( 's.{} = []' . format ( pfx ) ) #NEWLINE# #UNINDENT# port_defs . append ( 's.{port_list}.append( {port_type}( {bitwidth} ) )' . format ( port_list = pfx , port_type = port_type , bitwidth = bitwidth ) ) #NEWLINE# #UNINDENT# else : #NEWLINE# #INDENT# port_defs . append ( 's.{port_name} = {port_type}( {bitwidth} )' . format ( port_name = port_name , port_type = port_type , bitwidth = bitwidth ) ) #NEWLINE# #UNINDENT# #UNINDENT# #UNINDENT# set_inputs = [ ] #NEWLINE# for ( v_name , bitwidth ) in in_ports : #NEWLINE# #INDENT# py_name = v_name . replace ( '_M_' , '.' ) #NEWLINE# if ( '$' in py_name ) : #NEWLINE# #INDENT# ( name , idx ) = py_name . split ( '$' ) #NEWLINE# py_name = '{name}[{idx}]' . format ( name = name , idx = int ( idx ) ) #NEWLINE# #UNINDENT# v_name = verilator_mangle ( v_name ) #NEWLINE# set_inputs . append ( 's._model.{v_name}[0] = s.{py_name}' . format ( v_name = v_name , py_name = py_name ) ) #NEWLINE# #UNINDENT# set_comb = [ ] #NEWLINE# for ( v_name , bitwidth ) in out_ports : #NEWLINE# #INDENT# py_name = v_name . replace ( '_M_' , '.' ) #NEWLINE# if ( '$' in py_name ) : #NEWLINE# #INDENT# ( name , idx ) = py_name . split ( '$' ) #NEWLINE# py_name = '{name}[{idx}]' . format ( name = name , idx = int ( idx ) ) #NEWLINE# #UNINDENT# v_name = verilator_mangle ( v_name ) #NEWLINE# set_comb . append ( 's.{py_name}.value = s._model.{v_name}[0]' . format ( v_name = v_name , py_name = py_name ) ) #NEWLINE# #UNINDENT# set_next = [ ] #NEWLINE# for ( v_name , bitwidth ) in out_ports : #NEWLINE# #INDENT# py_name = v_name . replace ( '_M_' , '.' ) #NEWLINE# if ( '$' in py_name ) : #NEWLINE# #INDENT# ( name , idx ) = py_name . split ( '$' ) #NEWLINE# py_name = '{name}[{idx}]' . format ( name = name , idx = int ( idx ) ) #NEWLINE# #UNINDENT# v_name = verilator_mangle ( v_name ) #NEWLINE# set_next . append ( 's.{py_name}.next = s._model.{v_name}[0]' . format ( v_name = v_name , py_name = py_name ) ) #NEWLINE# #UNINDENT# with open ( template_filename , 'r' ) as template , open ( wrapper_filename , 'w' ) as output : #NEWLINE# #INDENT# py_src = template . read ( ) #NEWLINE# py_src = py_src . format ( model_name = model_name , port_decls = cdefs , port_defs = '\n    ' . join ( port_defs ) , set_inputs = '\n      ' . join ( set_inputs ) , set_comb = '\n      ' . join ( set_comb ) , set_next = '\n      ' . join ( set_next ) ) #NEWLINE# output . write ( py_src )