Inefficient code generated - does not use 256b registers
Labels: triaged, oncall: pt2, module: cpu inductor

### 🐛 Describe the bug

Followup on a discussion in #106219. cc: @jgong5 

The following code gets generated by torch.compile (all scalar code relying on GCC vectorization?):

```
#include "ci5uspp363v3ky6jkccllm3bxudy2fkdpqinkqhmpehfihejs7ko.h"
extern "C" void kernel(float* in_out_ptr0,
                       const float* in_ptr0,
                       const float* in_ptr1,
                       const float* in_ptr2,
                       const float* in_ptr3,
                       const float* in_ptr4,
                       const float* in_ptr5,
                       const float* in_ptr6,
                       const float* in_ptr7,
                       const float* in_ptr8,
                       float* out_ptr0,
                       float* out_ptr1,
                       float* out_ptr2,
                       float* out_ptr3,
                       float* out_ptr4,
                       float* out_ptr5)
{
    auto out_ptr6 = in_out_ptr0;
    {
        {
            float tmp_acc0 = 0;
            float tmp_acc1 = 0;
            float tmp_acc2 = 0;
            for(long i0=static_cast<long>(0L); i0<static_cast<long>(40L); i0+=static_cast<long>(1L))
            {
                auto tmp0 = in_ptr0[static_cast<long>(i0)];
                auto tmp1 = in_ptr1[static_cast<long>(i0)];
                auto tmp4 = in_ptr2[static_cast<long>(i0)];
                auto tmp5 = in_ptr3[static_cast<long>(i0)];
                auto tmp7 = in_ptr4[static_cast<long>(i0)];
                auto tmp2 = decltype(tmp0)(tmp0 * tmp1);
                auto tmp6 = tmp4 + tmp5;
                auto tmp8 = decltype(tmp6)(tmp6 * tmp7);
                auto tmp9 = std::numeric_limits<float>::infinity();
                auto tmp10 = tmp8 == tmp9;
                auto tmp11 = -std::numeric_limits<float>::infinity();
                auto tmp12 = tmp8 == tmp11;
                auto tmp13 = std::isnan(tmp8);
                auto tmp14 = static_cast<float>(0.0);
                auto tmp15 = tmp13 ? tmp14 : tmp8;
                auto tmp16 = static_cast<float>(-3.4028234663852886e+38);
                auto tmp17 = tmp12 ? tmp16 : tmp15;
                auto tmp18 = static_cast<float>(3.4028234663852886e+38);
                auto tmp19 = tmp10 ? tmp18 : tmp17;
                auto tmp20 = static_cast<float>(-10.0);
                auto tmp21 = max_propagate_nan(tmp19, tmp20);
                auto tmp22 = static_cast<float>(10.0);
                auto tmp23 = min_propagate_nan(tmp21, tmp22);
                auto tmp24 = decltype(tmp0)(tmp0 * tmp23);
                auto tmp26 = decltype(tmp1)(tmp1 * tmp23);
                tmp_acc0 = tmp_acc0 + tmp2;
                tmp_acc1 = tmp_acc1 + tmp24;
                tmp_acc2 = tmp_acc2 + tmp26;
            }
            auto tmp3 = tmp_acc0;
            out_ptr0[static_cast<long>(0L)] = tmp3;
            auto tmp25 = tmp_acc1;
            out_ptr1[static_cast<long>(0L)] = tmp25;
            auto tmp27 = tmp_acc2;
            out_ptr2[static_cast<long>(0L)] = tmp27;
        }
    }
    {
        auto tmp0 = out_ptr0[static_cast<long>(0L)];
        out_ptr3[static_cast<long>(0L)] = tmp0;
    }
    {
        auto tmp0 = out_ptr1[static_cast<long>(0L)];
        out_ptr4[static_cast<long>(0L)] = tmp0;
    }
    {
        auto tmp0 = out_ptr2[static_cast<long>(0L)];
        out_ptr5[static_cast<long>(0L)] = tmp0;
    }
    {
        {
            float tmp_acc0 = 0;
            for(long i0=static_cast<long>(0L); i0<static_cast<long>(3L); i0+=static_cast<long>(1L))
            {
                auto tmp0 = in_ptr5[static_cast<long>(i0)];
                auto tmp1 = in_ptr6[static_cast<long>(i0)];
                auto tmp2 = decltype(tmp0)(tmp0 * tmp1);
                tmp_acc0 = tmp_acc0 + tmp2;
            }
            auto tmp3 = tmp_acc0;
            out_ptr6[static_cast<long>(0L)] = tmp3;
        }
    }
    {
        auto tmp0 = in_ptr7[static_cast<long>(0L)];
        auto tmp1 = out_ptr6[static_cast<long>(0L)];
        auto tmp3 = in_ptr8[static_cast<long>(0L)];
        auto tmp2 = tmp0 + tmp1;
        auto tmp4 = tmp2 + tmp3;
        auto tmp5 = decltype(tmp4)(1) / (decltype(tmp4)(1) + std::exp(-tmp4));
        in_out_ptr0[static_cast<long>(0L)] = tmp5;
    }
}
```

Host properties for test:

processor	: xx
vendor_id	: GenuineIntel
cpu family	: 6
model		: 85
model name	: Intel(R) Xeon(R) Platinum 8339HC CPU @ 1.80GHz
[...]
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single intel_ppin ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local avx512_bf16 dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku ospke avx512_vnni md_clear flush_l1d arch_capabilities
vmx flags	: vnmi preemption_timer posted_intr invvpid ept_x_only ept_ad ept_1gb flexpriority apicv tsc_offset vtpr mtf vapic ept vpid unrestricted_guest vapic_reg vid ple shadow_vmcs pml ept_mode_based_exec tsc_scaling
bugs		: spectre_v1 spectre_v2 spec_store_bypass swapgs
[...]

### Error logs

Generated code uses only 128b xmm registers when built with GCC:

```
0000000000001650 <kernel>:
    1650:	41 54                	push   %r12
    1652:	66 0f ef ed          	pxor   %xmm5,%xmm5
    1656:	44 0f 28 0d c2 09 00 	movaps 0x9c2(%rip),%xmm9        # 2020 <_fini+0x7b0>
    165d:	00 
    165e:	31 c0                	xor    %eax,%eax
    1660:	55                   	push   %rbp
    1661:	44 0f 28 05 c7 09 00 	movaps 0x9c7(%rip),%xmm8        # 2030 <_fini+0x7c0>
    1668:	00 
    1669:	0f 28 e5             	movaps %xmm5,%xmm4
    166c:	0f 28 dd             	movaps %xmm5,%xmm3
    166f:	0f 28 3d ca 09 00 00 	movaps 0x9ca(%rip),%xmm7        # 2040 <_fini+0x7d0>
    1676:	0f 28 35 d3 09 00 00 	movaps 0x9d3(%rip),%xmm6        # 2050 <_fini+0x7e0>
    167d:	53                   	push   %rbx
    167e:	48 89 fb             	mov    %rdi,%rbx
    1681:	4c 8b 54 24 20       	mov    0x20(%rsp),%r10
    1686:	48 89 f7             	mov    %rsi,%rdi
    1689:	4c 8b 64 24 40       	mov    0x40(%rsp),%r12
    168e:	48 89 d6             	mov    %rdx,%rsi
    1691:	48 8b 6c 24 48       	mov    0x48(%rsp),%rbp
    1696:	48 89 ca             	mov    %rcx,%rdx
    1699:	4c 8b 5c 24 50       	mov    0x50(%rsp),%r11
    169e:	48 8b 4c 24 28       	mov    0x28(%rsp),%rcx
    16a3:	0f 1f 44 00 00       	nopl   0x0(%rax,%rax,1)
    16a8:	0f 10 14 06          	movups (%rsi,%rax,1),%xmm2
    16ac:	44 0f 10 14 07       	movups (%rdi,%rax,1),%xmm10
    16b1:	44 0f 28 ee          	movaps %xmm6,%xmm13
    16b5:	0f 10 0c 02          	movups (%rdx,%rax,1),%xmm1
    16b9:	44 0f 59 d2          	mulps  %xmm2,%xmm10
    16bd:	41 0f 10 14 00       	movups (%r8,%rax,1),%xmm2
    16c2:	0f 58 ca             	addps  %xmm2,%xmm1
    16c5:	41 0f 10 14 01       	movups (%r9,%rax,1),%xmm2
    16ca:	0f 59 ca             	mulps  %xmm2,%xmm1
    16cd:	41 0f 58 da          	addps  %xmm10,%xmm3
    16d1:	0f 28 d1             	movaps %xmm1,%xmm2
    16d4:	44 0f c2 e9 05       	cmpnltps %xmm1,%xmm13
    16d9:	0f 28 c1             	movaps %xmm1,%xmm0
    16dc:	0f c2 d1 07          	cmpordps %xmm1,%xmm2
    16e0:	41 0f c2 c1 05       	cmpnltps %xmm9,%xmm0
    16e5:	0f 54 d1             	andps  %xmm1,%xmm2
    16e8:	0f 54 d0             	andps  %xmm0,%xmm2
    16eb:	41 0f 55 c1          	andnps %xmm9,%xmm0
    16ef:	0f 56 c2             	orps   %xmm2,%xmm0
    16f2:	41 0f 28 d0          	movaps %xmm8,%xmm2
    16f6:	44 0f 28 d8          	movaps %xmm0,%xmm11
    16fa:	0f c2 d0 01          	cmpltps %xmm0,%xmm2
    16fe:	44 0f 28 e0          	movaps %xmm0,%xmm12
    1702:	44 0f c2 d8 03       	cmpunordps %xmm0,%xmm11
    1707:	44 0f c2 e7 01       	cmpltps %xmm7,%xmm12
    170c:	66 41 0f eb d3       	por    %xmm11,%xmm2
    1711:	66 45 0f eb e3       	por    %xmm11,%xmm12
    1716:	66 44 0f 6f f2       	movdqa %xmm2,%xmm14
    171b:	66 45 0f 6f dc       	movdqa %xmm12,%xmm11
    1720:	66 41 0f df d5       	pandn  %xmm13,%xmm2
    1725:	66 45 0f db f5       	pand   %xmm13,%xmm14
    172a:	66 45 0f db de       	pand   %xmm14,%xmm11
    172f:	66 45 0f df e6       	pandn  %xmm14,%xmm12
    1734:	44 0f 28 f6          	movaps %xmm6,%xmm14
    1738:	44 0f c2 f1 01       	cmpltps %xmm1,%xmm14
    173d:	66 0f 6f ca          	movdqa %xmm2,%xmm1
    1741:	41 0f 28 d0          	movaps %xmm8,%xmm2
    1745:	0f 54 d1             	andps  %xmm1,%xmm2
    1748:	0f 55 c8             	andnps %xmm0,%xmm1
    174b:	41 0f 54 c3          	andps  %xmm11,%xmm0
    174f:	0f 56 ca             	orps   %xmm2,%xmm1
    1752:	0f 10 14 06          	movups (%rsi,%rax,1),%xmm2
    1756:	66 45 0f eb e6       	por    %xmm14,%xmm12
    175b:	44 0f 55 d9          	andnps %xmm1,%xmm11
    175f:	0f 28 cf             	movaps %xmm7,%xmm1
    1762:	44 0f 56 d8          	orps   %xmm0,%xmm11
    1766:	41 0f 28 c4          	movaps %xmm12,%xmm0
    176a:	41 0f 54 cc          	andps  %xmm12,%xmm1
    176e:	41 0f 55 c3          	andnps %xmm11,%xmm0
    1772:	0f 56 c1             	orps   %xmm1,%xmm0
    1775:	0f 10 0c 07          	movups (%rdi,%rax,1),%xmm1
    1779:	48 83 c0 10          	add    $0x10,%rax
    177d:	0f 59 c8             	mulps  %xmm0,%xmm1
    1780:	0f 59 c2             	mulps  %xmm2,%xmm0
    1783:	0f 58 e1             	addps  %xmm1,%xmm4
    1786:	0f 58 e8             	addps  %xmm0,%xmm5
    1789:	48 3d a0 00 00 00    	cmp    $0xa0,%rax
    178f:	0f 85 13 ff ff ff    	jne    16a8 <kernel+0x58>
    1795:	0f 28 c5             	movaps %xmm5,%xmm0
    1798:	48 8b 44 24 58       	mov    0x58(%rsp),%rax
    179d:	0f 12 c5             	movhlps %xmm5,%xmm0
    17a0:	0f 58 c5             	addps  %xmm5,%xmm0
    17a3:	0f 28 c8             	movaps %xmm0,%xmm1
    17a6:	0f c6 c8 55          	shufps $0x55,%xmm0,%xmm1
    17aa:	0f 58 c8             	addps  %xmm0,%xmm1
    17ad:	0f 28 c4             	movaps %xmm4,%xmm0
    17b0:	0f 12 c4             	movhlps %xmm4,%xmm0
    17b3:	0f 58 c4             	addps  %xmm4,%xmm0
    17b6:	0f 28 d0             	movaps %xmm0,%xmm2
    17b9:	0f c6 d0 55          	shufps $0x55,%xmm0,%xmm2
    17bd:	0f 58 d0             	addps  %xmm0,%xmm2
    17c0:	0f 28 c3             	movaps %xmm3,%xmm0
    17c3:	0f 12 c3             	movhlps %xmm3,%xmm0
    17c6:	0f 58 c3             	addps  %xmm3,%xmm0
    17c9:	0f 28 d8             	movaps %xmm0,%xmm3
    17cc:	0f c6 d8 55          	shufps $0x55,%xmm0,%xmm3
    17d0:	0f 58 c3             	addps  %xmm3,%xmm0
    17d3:	f3 41 0f 11 04 24    	movss  %xmm0,(%r12)
    17d9:	f3 0f 11 55 00       	movss  %xmm2,0x0(%rbp)
    17de:	f3 41 0f 11 0b       	movss  %xmm1,(%r11)
    17e3:	f3 41 0f 10 04 24    	movss  (%r12),%xmm0
    17e9:	f3 0f 11 00          	movss  %xmm0,(%rax)
    17ed:	48 8b 44 24 60       	mov    0x60(%rsp),%rax
    17f2:	f3 0f 10 45 00       	movss  0x0(%rbp),%xmm0
    17f7:	f3 0f 11 00          	movss  %xmm0,(%rax)
    17fb:	48 8b 44 24 68       	mov    0x68(%rsp),%rax
    1800:	f3 41 0f 10 03       	movss  (%r11),%xmm0
    1805:	f3 0f 11 00          	movss  %xmm0,(%rax)
    1809:	f3 0f 7e 09          	movq   (%rcx),%xmm1
    180d:	f3 41 0f 7e 02       	movq   (%r10),%xmm0
    1812:	48 8b 44 24 30       	mov    0x30(%rsp),%rax
    1817:	0f 59 c1             	mulps  %xmm1,%xmm0
    181a:	f3 41 0f 10 4a 08    	movss  0x8(%r10),%xmm1
    1820:	f3 0f 59 49 08       	mulss  0x8(%rcx),%xmm1
    1825:	0f 28 d0             	movaps %xmm0,%xmm2
    1828:	0f c6 c0 e5          	shufps $0xe5,%xmm0,%xmm0
    182c:	f3 0f 58 c2          	addss  %xmm2,%xmm0
    1830:	f3 0f 58 c8          	addss  %xmm0,%xmm1
    1834:	f3 0f 11 0b          	movss  %xmm1,(%rbx)
    1838:	f3 0f 10 00          	movss  (%rax),%xmm0
    183c:	48 8b 44 24 38       	mov    0x38(%rsp),%rax
    1841:	f3 0f 58 00          	addss  (%rax),%xmm0
    1845:	f3 0f 58 c1          	addss  %xmm1,%xmm0
    1849:	0f 57 05 10 08 00 00 	xorps  0x810(%rip),%xmm0        # 2060 <_fini+0x7f0>
    1850:	e8 db f7 ff ff       	call   1030 <expf@plt>
    1855:	f3 0f 10 0d a7 07 00 	movss  0x7a7(%rip),%xmm1        # 2004 <_fini+0x794>
    185c:	00 
    185d:	f3 0f 58 c1          	addss  %xmm1,%xmm0
    1861:	f3 0f 5e c8          	divss  %xmm0,%xmm1
    1865:	f3 0f 11 0b          	movss  %xmm1,(%rbx)
    1869:	5b                   	pop    %rbx
    186a:	5d                   	pop    %rbp
    186b:	41 5c                	pop    %r12
    186d:	c3                   	ret    
Disassembly of section .fini:
0000000000001870 <_fini>:
    1870:	f3 0f 1e fa          	endbr64 
    1874:	48 83 ec 08          	sub    $0x8,%rsp
    1878:	48 83 c4 08          	add    $0x8,%rsp
    187c:	c3                   	ret    
```

### Minified repro

n/a

### Versions

fbcode

cc @ezyang @msaroufim @wconstab @bdhirsh @anijain2305