giseldo/neodataset huggingface dataset:
wishlist: make 'value' and 'reference' more accessible for quick edits (lp:#1102168)

[Original report](https://bugs.launchpad.net/bugs/1102168) created by **madworm (madworm-de-inkscape)**
```
Currently it takes quite a lot of clicks through various menus and submenus
to edit the parameters (invisible, orientation, size...) - that gets
tedious pretty quickly.

It would be useful to have all footprint fields on a single page (i.e. not
having to press Edit for each one of them). Some basic settings should also
be available in the context menu right away, and a hotkey for 'invisible'
would be great.
```

Story points: 10.0
auto-create footprint archive in project (so it can be shared) (lp:#1098563)

[Original report](https://bugs.launchpad.net/bugs/1098563) created by **madworm (madworm-de-inkscape)**
```
Distribution of design files would benefit from a footprint cache, just
like the symbol cache.

If you want to publish design files so other people can use and modify them
easily, you have to modify your local project, create the footprint archive
manually and manually add that to the list of libraries. All of this is
done automatically for the schematic editor, so why not for the pcb editor
too?
```

Story points: 10.0
Eeschema - Pin graphics too large? (lp:#1095245)

[Original report](https://bugs.launchpad.net/bugs/1095245) created by **Kerusey Karyu (keruseykaryu-deactivatedaccount)**
```
I think the graphics describing the functions of pins, especially the dot,
might be slightly smaller in size.
Currently, this implies the use of a fairly long pins that graphics do not
overlaps pin numbers, and even themselves symbols must stand be large in
order to preserve a reasonable scale.
```
Original tags: eeschema graphics libedit

Story points: 12.0
Placing multiple labels (lp:#1095113)

[Original report](https://bugs.launchpad.net/bugs/1095113) created by **Johann Glaser (johann-glaser)**
```
This is a wishlist report.

It is tedious to place multiple labels in Eeschema to nets (e.g. TDI, TDO,
TMS, TCK). Therefore I ask you to implement the following feature: If the
label edit line in the Label Properties dialog contains spaces, then place
one label for each such word, one after another.

Example: Press [L] to add labels, the "Label Properties" dialog pops up.
Then enter the string "TDI TDO TMS TCK" (without the quotes but with the
spaces) in the "Text:" edit line. After pressing [Enter] or clicking the
[OK] button, the label "TDI" is at the mouse cursors tip. Click on the
according net to place this label. Immediately after this, the next word
"TDO" is at the mouse cursors tip. Click on the next according net, and so
on.

BTW: I found this feature very convenient in Cadence Allegro Design Entry
Schematic Capture.

Thanks!
```
Original tags: eeschema label

Story points: 18.0
Allow keepout zones in footprints (lp:#1081846)

[Original report](https://bugs.launchpad.net/bugs/1081846) created by **pablo pareja (parejaobregon)**
```
When using fill zones with some particular components, it would be a very
usefull option to be able to create a component footprint with some sort of
anti-copper or "cutout area" layer. In this way, you should be able to
place that component footprint anywhere inside a fill-zone and avoid (that
fill-zone) to fill in the designed geometry.

For example, when designing a PCB with SMD parts, it is sometimes neccesary
to avoid copper fills below the component to simplify soldering. Although
this can be achieved with a "cutout area", if you have to repeat the
procedure many times (say for example lots of SMD resistors) having a
footprint with the "cutout area" or "anti-copper option" included is very
usefull.

Regards,
Pablo
```
Original tags: feature.request pcbnew

Story points: 106.0
pcbnew: disable locked items in selection clarification list (lp:#1066220)

[Original report](https://bugs.launchpad.net/bugs/1066220) created by **Martin Errenst (imp-d)**
```
Problem: some items on the board are locked (like footprints). Trying to
move those, will result in an popup telling you it's a locked part (which
is fine).
If one tries to move those parts via the hotkey, imho, nothing should
happen (actual result: the mentioned popup, slowing down the workflow).
If there's more then one part under the cursor, the "Selection
Clarification" dialogue pops up (also ok), but locked items are selectable
to move (which will result in the first mentioned popup).

An easy option to avoid selecting items which are locked, is to disable
those entries in the list.
Sadly it's not possible to get any information inside the
PCB_BASE_FRAME::PcbGeneralLocateAndDisplay ( int aHotKeyCode ) method
(passing any argument to it will result in a segfault, also there's not a
single place in the code, passing anything to it).
The main problem with the attached (ugly) quickfix to disable the locked
entries is, you cannot tell what kind of action called the function (move,
rotate and flip are forbidden for locked parts, but editing the properties
for the part is ok - so one can disable the lock again).

The patch disables the "first level access" to the part, but selecting a
pad from the part and then choosing the part from the pads menu still
works. I don't really recommend using the patch ;).

Also it would be nice to number the entries inside the selection
clarification menu (or all the other menus you can trigger with hotkeys)
and assign some kind of context sensitive  hotkeys, to access the right
entry (like pressing '1' for the first entry and so on).

Version:
testing, 3762.
```
Original tags: lock move part pcbnew

Story points: 40.0
Project manager multiple selection options (lp:#1016464)

[Original report](https://bugs.launchpad.net/bugs/1016464) created by **szymon (szymon123)**
```
Seen under windows. Currently under project manager in file tree there is
no possibility to select multiple files. I know at least one option which
could be usefull on many files, delete selected files. Maybe in future
there will be more options.
```
Original tags: feature.request starter ui

Story points: 16.0
Enhanced export from Eeschema to SVG (including grouping) (lp:#1011754)

[Original report](https://bugs.launchpad.net/bugs/1011754) created by **GeBu (gebucz)**
```
It should be good to improve SVG export from Eeschema.
Now there are separated lines / objects. It should be more useful if there
be symbols (transistor etc.) and nets (GND, +5V,...) gruped or as one
object (I do not know).
It is good for editing in Inkscape for example if you want to prepare
schematic for wikipedia. It is way of Eagle script
eagle2svg-1.2.ulp: http://www.cadsoftusa.com/downloads/ulps
```
Original tags: eeschema export svg

Story points: 22.0
DRC and netclasses : clearance rules between nets of different potential (lp:#983230)

[Original report](https://bugs.launchpad.net/bugs/983230) created by **Vesa Solonen (vesa-solonen)**
```
Flexible automatic design rules would need "differential net classes" that
means different rules for a net depending on surrounding nets.

As an example I'll explain the problem of a traditional power electronics
half bridge circuit:

HV----            [400V     10A]
     |
Gh--|<            [0-415V    1A]        [0 < V(Gh)-V(Sh) < 15]
     |
Sh-------> Out    [0-400V   10A]
     |
Gl--|<            [0-15V     1A]
     |
GND------>        [0V       10A]

HV net needs "power" class clearance and width towards all nets as does
Out. Sh needs "power" class clearance towards all nets, but Gh and width
according to "control" class. Gh needs the same, but "control" clearance
towards Sh. Gl needs "control" class clearance and width.

Curently this system is unrealisable using KiCad DRC. I propose adding a
"potential class" description to net class design rules to address this
problem. Needed data stuctures for file format support and implementation
need to be discussed and designed. Interested parties are encouraged to
comment here and aim for a production ready blueprint.
```
Original tags: drc pcbnew

Story points: 156.0
No support for technology files in PCBnew (lp:#961533)

[Original report](https://bugs.launchpad.net/bugs/961533) created by **Andrew Zonenberg (azonenberg)**
```
Many other EDA tools allow a "technology file" to be created containing
standardized design rules for a specific fab process which can be imported
into a project rather than being typed in one at a time in a slow and
error-prone fashion. As far as I can tell kicad does not support anything
of the sort.

Basic workflow:
* Create PCBnew file and configure design rules
* File | Export technology file, specify file name
* Create new PCBnew file for a future project
* File | Import technology file, choose file name

The specific things that should be included in a tech file are:
* Global minimum trace size / spacing design rules
* Minimum via size design rules
* Soldermask clearance
* List of predefined trace and via sizes

This doesn't look like it'll be too hard to implement and I intend to
submit a patch in a week or two with a first-draft implementation.
```

Story points: 70.0
Assign a zone fill to multiple layers (lp:#954848)

[Original report](https://bugs.launchpad.net/bugs/954848) created by **Kalle Hyvönen (scorper)**
```
I think it would be very handy to be able to assign a zone fill to multiple
layers at the same time. It is tedious to draw and separately move separate
zone fills on multiple layers that still occupy the same physical area
(like groundfills over the whole board on more than one layer for example).
Should be a pretty simple addition.
```
Original tags: pcbnew

Story points: 26.0
Add symbol from library browser in eeschema (lp:#920380)

[Original report](https://bugs.launchpad.net/bugs/920380) created by **Kalle Hyvönen (scorper)**
```
If I'm making a schematic in eeschema, and I go to library browser, it is
not possible to add a component to the schematic. Which seems a bit
backwards since Place -> component -> library browser opens an identical
library browser, the only difference is that this time it has the "Insert
component in schematic" -button.

I have version:

Application: Eeschema
Version: (2012-01-17 BZR 3368)-testing
Build: wxWidgets 2.8.11 (no debug,Unicode,compiler with C++ ABI 1002,GCC
4.6.1,wx containers,compatible with 2.6)
Platform: Linux 3.0.0-14-generic x86_64, 64 bit, Little endian, wxGTK
Options: USE_PNG_BITMAPS=ON
         KICAD_GOST=OFF
         USE_WX_GRAPHICS_CONTEXT=OFF
         USE_WX_OVERLAY=OFF
         USE_BOOST_POLYGON_LIBRARY
```
Original tags: eeschema

Story points: 46.0
Add option for small toolbar icons (lp:#903258)

[Original report](https://bugs.launchpad.net/bugs/903258) created by **sdaau (sd-imi)**
```
I've just tried 0.0.201112101853+3290~10~natty1 - and I can notice some new
icons, and I actually like them :)

However, since I'm working on a netbook, the new large icons take up
valueable space; I'd like to have an option (maybe in Kicad/Preferences?)
so I can revert to a small version of the icons (like they used to be in,
say, 0.0.20101024-1).

Thanks!
```
Original tags: gui

Story points: 20.0
Copy block in component editor broken (lp:#893323)

[Original report](https://bugs.launchpad.net/bugs/893323) created by **Rick Jenkins (rick-hartmantech)**
```
In the eeschema component editor,  a block copy operation copies the block
on top of itself, with no ability to move the block before copying. This
results in multiple superimposed copies of, for instance, pins, which are
very confusing.

Application: Eeschema
Version: (2011-oct-27)-testing
Build: wxWidgets 2.8.11 (no debug,Unicode,compiler with C++ ABI 1002,GCC
4.5.3,wx containers,compatible with 2.6)
Platform: Linux 3.0.6-gentoo i686, 32 bit, Little endian, wxGTK
Options: USE_PNG_BITMAPS=ON
         KICAD_GOST=OFF
         USE_WX_GRAPHICS_CONTEXT=OFF
         USE_WX_OVERLAY=OFF
         USE_BOOST_POLYGON_LIBRARY
```
Original tags: eeschema inconsistency ui

Story points: 12.0
random annotation in complex hierarchy  (lp:#864122)

[Original report](https://bugs.launchpad.net/bugs/864122) created by **Ivica Kvasina (kvasina)**
```

i am presently using BZR 3044 on windows.
issue i have recently discovered is with annotation being random when using
hierarchical sheets.

one CAN influence annotation order in ONE sheet but unfortunately, this
does not work with multiple sheets.
Annotating by hand is just not practical for anything using more than few
components.

for example in top level sheet i created 12 instances to another sheet
(instances are same file, but have unique sheet names). they are arranged
in simple pattern:
1  4  7  10
2  5  8  11
3  6  9  12

unfortunately KiCad does not annotate according to selected options and so
far it seem to be random.

for example if i choose:
- reset existing annotation
- sort components by X (top to bottom, left to right)
- start to (sheet number)*100 and use first free number

i expect that components annotation is like

100  400  700 1000
200  500  800 1100
300  600  900 1200

but what i get is something like:

1300 1000  200  400
1200  800   300  700
1100  900   500  600

It neither uses sheet number, nor order in which sheets are created.

regards,

Ivica Kvasina
```
Original tags: annotation eeschema

Story points: 16.0
Graphical arc should support start/end in degrees + radius (lp:#848205)

[Original report](https://bugs.launchpad.net/bugs/848205) created by **madworm (madworm-de-inkscape)**
```
I'm trying to add routing arcs for a panelized design.

I can change the center in Cartesian coordinates, which is good. But I'm
required to enter the start/end points of the arc in Cartesian coordinates
as well. That is very cumbersome and needs a calculator.

It would be a great simplification for the user if one could enter these
values directly:

* center point (DONE)
* radius
* start in degrees
* end in degrees

I think that is a must.
```
Original tags: cern

Story points: 38.0
Improve hidden pin behavior? (lp:#807608)

[Original report](https://bugs.launchpad.net/bugs/807608) created by **Special LIU (liuns)**
```
System : scientific linux 6.0, X86_64
KiCAD version : (1) Pre-build rpm from EPEL, 2011-01-28 BZR 2765 stable
                          (2) 2011-0708 BZR-3044 -stable, build from source
code

Both version generate same wrong result.

While system use multi-voltage for digital component, annotate and netlist
writer generate
wrong result, the ERC will failure and wrong netlist generated.

How to re-produce:
      (1) open eeschema with a new design.
      (2) make Show Hidden Pin ON to see hidden power pin
      (3) place two 7404 gate from 74xx library,
      (4) 7404 gate 1, vcc connect to Power A (+5V, for example)
      (5) 7404 gate 2, vcc connect to Power B (+3.3V for example)
      (6) make annotate, 7404 gate 1 & 7404 gate 2 gets same U1
      (7) run ERC(with default option) got "Conflict problem bewteen pins
(power)"
      (8) Annotate error, because two 7404 gate from different power should
generate U1 & U2 , not only U1
      (9) So, the netlist will be wrong, beacause two different power
source connected togeger, and only one power net shows on netlist file.
      (10) if on step 6, we manual annotate 7404 gate 1 as U1, 7404 gate 2
as U2, run ERC and netlist also wrong

When use KiCAD to design signle-power system, everything works fine, but
when we design a multi-voltage system, the eeschema generate wrong netlist.

Both error (annotate & netlist writer) should be same bug in eeschema, and
should be modify with following:

When Annotate:
   (1) if hidden power pin manual connected to other net then go step 2,
else original eeschema work
   (2) checked power pin connected net name, same net name will be same
device else was different device

When Write Netlist:
   (1) if hidden power pin manual connected to other net name (+5V, for
examples), then net name change to the name connected not the original
name.

Work Around:
   Currently, we create ourself library for multi-voltage design, for
examples : 74XX with power name VCC, 74XX_3V3 with power name 3V3 .
```
Original tags: eeschema

Story points: 40.0
wishlist: snap to object (lp:#806260)

[Original report](https://bugs.launchpad.net/bugs/806260) created by **Berwyn Hoyt (berwyn)**
```
I'm an ex-user of Circad.  It has a super function called 'snap-to'.  Very
simply, it is a hotkey that moves the cursor to the centre of the nearest
object, whether that be a track end, a component pad, a line end, or
whatever.

Once you press the hotkey, the mouse cannot move the cursor for 2 seconds.
This gives you enough time to place whatever you want to place at that
point.

This feature also provides an easy way to place something to be an exact
space away from something else using the keyboard.  So if you want two
tracks spearated by exactly 2mm, then you snap to one end of the first
track, then use your keyboard to move the cursor exactly 2mm to the right
and hotkey-place the second track.  Very accurate and easy.  (Mind you,
Circad also had a nice feature which let you move 10x and 100x grid spacing
with the cursor keys by pressing Shift & Ctrl while arrowing -- that was
handy, too).

An example of when this snap-to is needed.  Trying to place a 2:1 rectangle
on the PCB_Edges layer.  I can start in top left corner, place a line to
the bottom, then a line to the right, then back up to the top, but how do I
know how far up to the top to go so that I'll meet the original starting
point exactly?  Use snap-to.
```

Story points: 62.0
wishlist: Hotkey for all functions (lp:#806259)

[Original report](https://bugs.launchpad.net/bugs/806259) created by **Berwyn Hoyt (berwyn)**
```
It would be most helpful if we could assign a hotkey to every toolbar
function in KiCad.  I propose the following mechanism:
 - have a command name associated with each toolbar function.  When you
hover or right-click the toolbar button it shows you the function name.
 - either allow that function name in the hotkeys file.  And make a way to
auto-load a hotkeys file
 - or allow an arbitrary function name to be entered in the hotkeys editor

I'm suggesting this because it is awkward to access certain functions with
the mouse when your mouse is already right where you want it to be.

(This would also provide access to all these functions to define them onto
special multi-key sequences or special mouse button combinations or even
gestures with auto-hotkey)
```
Original tags: hotkey

Story points: 42.0
wishlist: user accessible commands (lp:#795806)

[Original report](https://bugs.launchpad.net/bugs/795806) created by **sugeng anto (anthos1984)**
```
suggestion for UI :
1. Every commands must user viewable. For example : "reset local
coordinate" can only accessed by hot key. I suggest something like "zero
location" tool
2. drag tool : user don't need for right click. Currently, this tool can
only accessed by right click. First time user may don't realize that kicad
has this tool.
3. bulk copy tool : one time copy and many paste until the tool ends.
Currently it only has "copy" tool to copy and the tool end after the parts
has been placed.
4. Alternate grid select: helps most for pcbNew to switch to finer grid by
pressing hotkey (or modifier). If you can switch units, why you can switch
between finer and coarser grid?

using BZR2986-WinXP binary, run on win7 64-bit

thanks
```
Original tags: command tool ui

Story points: 14.0
pcbnew option to print net names/pin numbers (lp:#736666)

[Original report](https://bugs.launchpad.net/bugs/736666) created by **sdaau (sd-imi)**
```
I'm using kicad from ppa, bzr2898~lucid-1 currently.

For some more complicated schematics, I'd like to be able to choose to
print out net names as well, so I can have an image of 'pinouts'.
Currently, there is no such option if one chooses "Print" or "Print SVG" in
pcbnew; so currently I have to zoom in until net names show up, and grab a
screenshot (see attachment image).

While the sizes of the eventual net name objects may be a problem to solve
in the printout, they can just as well be exported in 'real size' as the
zoom shows them; and although unreadable on paper, if they are present in
the output SVG (or PS/PDF, if we print to file), then they can always be
edited (resized) afterwards in a vector graphics software like Inkscape
(personally, that's all I'd need) :)

Thanks for a great software - and cheers!
```
Original tags: export svg

Story points: 10.0
DRC doesn't check for overlapping drill holes. (lp:#684067)

[Original report](https://bugs.launchpad.net/bugs/684067) created by **Agent24 (tda7000)**
```
Running KiCad v 2010-05-05 BZR 2356 -stable

Managed to create a via that was overlapping a pad, without error message.

I have attached the board file. The problem is next to R3 (by the PLCC32
socket)
```
Original tags: drilling holes pads pcbnew via

Story points: 30.0
Antipad area should not exclude spokes (lp:#602176)

[Original report](https://bugs.launchpad.net/bugs/602176) created by **Stephen Eaton (seaton)**
```
Version: nightly build kicad-20100629-r2407-windows.tar.gz
Platform: Windows7

Problem:
(files attached)

Zone on top Copper Layer fails to attach/connect two adjoining pins (25 &
26) that are connected to net GND on component U2.  Other pins on the
component on the same net attach to the zone ok.
```
Original tags: pcbnew zones

Story points: 30.0
Allow thermal reliefs for via/zone connections (lp:#593916)

[Original report](https://bugs.launchpad.net/bugs/593916) created by **nobody (nobody-users)**
```
I have a problem with "Add zones" function. Problem is: When i add zone GND
all track and vias on the tracks have  a good antipad size and thermal
relife. But i have zones GND on the top and on the bottom side and i want
to compensate potentianl on the bord. I do it  throught vias. I trace the
GND track to the vias ( see include file) I dont have thrmal relief.
Exclude pads  in this case also don`t work.
I highlight the GND net. and display Zones option. Mayby i have
bad/incorect settings
```
Original tags: via zones

Story points: 22.0
Hierarchical sheet resize from any corner (lp:#593886)

[Original report](https://bugs.launchpad.net/bugs/593886) created by **lomarcan (lomarcan-users)**
```
An option to resize the sheet from the top could be useful. Otherwise you
need to move all the pinsheet down to make space for the new ones.
```
Original tags: eeschema starter

Story points: 32.0
CVPCB context menu (lp:#594102)

[Original report](https://bugs.launchpad.net/bugs/594102) created by **paulgittings (paulgittings)**
```
It would be useful to have a context menu in CVPCB, with an option to view
footprint (personal thing I dislike toolbars for common actions much prefer
right click context menus).
```

Story points: 16.0
Clearance track-to-track, track-to-via, via-to-via, track-to-pad, etc. (lp:#594062)

[Original report](https://bugs.launchpad.net/bugs/594062) created by **reshpe63 (reshpe63)**
```
Kicad (version 20090216) in the "Dimensions->Tracks and Vias" menu, has
only one Clearance type for the ERC; is it possible to have the following
clearance types: track-to-track, track-to-via, track-to-pad, via-to-via,
via-to-pad, pad-to-pad?
```
Original tags: drc pcbnew

Story points: 34.0
Line To Arc (lp:#594060)

[Original report](https://bugs.launchpad.net/bugs/594060) created by **cfdev (cfdev)**
```
hi,

is it possible to transforme an Line(2pts) in Arc(3pts), Like ORCAD
software.
it's an very good feature when we don't know the center of arc.
see attach file.

thanks a lot
Cyril

++
```

Story points: 10.0