protected int roxl_byte_imm(int opcode)
	{
		//  the state of the X cflag BEFORE each shift is moved into the lsb after each shift. Also, check for 0 count rotate if roxr reg (and not imm)
		//  also if roxl reg, the shift count is mod 64 not 32 finally, cond code reg is set directly here
		int shift = (opcode >> 9) & 0x07;
		if(shift == 0)
			shift = 8;

		int reg = (opcode & 0x07);
		int d = cpu.getDataRegisterByte(reg);

		int last_out;
		boolean xflag=cpu.isFlagSet(Cpu.X_FLAG);        // state of the X flag
		int maskFlags;                                  // there is no 0 rotate count here
		for(int s= 0; s < shift; s++)
		{
			last_out = d & 0x80;                    // bit rotated out before ths shift
			d <<= 1;
			if (xflag)
				d |= 1;                             // if xflag was set before the shift, set LSB
			if(last_out != 0)                       // bit goes to xflag
				xflag=true;
			else
				xflag=false;
		}
		d &= 0xff;
		cpu.setDataRegisterByte(reg, d);
		if (xflag)
			maskFlags=Cpu.X_FLAG+Cpu.C_FLAG;        // if last bit was 1, set flags accordingly
		else
			maskFlags=0;                            // these flags aren't set
		if (d==0)
			maskFlags+=Cpu.Z_FLAG;                  // Z flag set if result is 0
		if((d & 0x80)!=0)
			maskFlags+=Cpu.N_FLAG;                  // N flag for result (the V flag is always 0)
		cpu.setCCRegister(maskFlags);
		return 6 + shift + shift;
	}