Flexfet: A Low-Cost, Rad-Hard, Independent-Double-Gate SOI CMOS Technology with Flexible, Dynamic Reconfigurability (2005)

A variety of double-gate (DG) MOSFET transistor structures are being developed to permit CMOS scaling to the sub-50nm regime. However, flexible dynamic threshold voltage control is urgently needed for ultra-low-power digital circuits, novel analog/RF circuits, and dynamically reconfigurable integrated circuits. Independently double gated (IDG) FinFETs have recently been reported to have highly-controllable threshold voltage. However, a lithographically-defined fin width of less than 10nm is required to achieve this. Other recently reported planar IDG MOSFETs typically have oversized, non-self-aligned bottom gates and/or require epitaxial channel growth. This paper will present the new, low-cost, inherently rad-hard Flexfettrade silicon-on-insulator CMOS technology, with a damascene metal topgate and an implanted JFET bottomgate that are self-aligned in a gate trench. This new technology is highly scalable, due to its sub-lithographic undoped channel, non-implanted ultrashallow source/drain extensions (SDE), non-epitaxial raised source/drains, and "gate-last" flow. Most damascene gate processes use a dummy gate and implanted SDE junctions. Flexfet utilizes a spacer-lined gate trench that is etched through implanted SD regions to self-align its implanted JFET bottomgate with its TiN topgate. The top and bottomgates are connected at opposite edges of the device by a damascene local interconnect (LI) that is embedded in the STI regions between devices, resulting in high layout density. Effectively "raised" SDs are achieved without using selective epi. Sidewall spacers narrow the gate trench opening, resulting in <180nm channel lengths, even using low-cost relaxed 350nm lithography. The bottom gate effectively blocks radiation-induced trapped charge in the buried oxide (BOX) from creating a source-drain leakage path. Also, the edges of the channel are not conventionally isolated, but instead are passivated by thin, oxide/nitride sidewall spacers. Therefore, all surfaces of the channel are either gated or directly contacted, resulting in total ionizing dose (TID) hardness in excess of 1Mrad, as measured in recent AFRL X-ray tests. This device has low resistance metal contacts to all four terminals, and notably permits several different top/bottom gate connection configurations for circuit design flexibility. In addition, the bottom gate can be used as a dynamic threshold DTMOS device or as a sub-volt, super-GHz second input signal. Flexfet is very scalable since it is planar, source/drain symmetrical, and since neither the channel thickness, threshold voltage, nor its TID hardness are coupled to the thickness of the SOI film. The SOI film may be made thicker to further reduce source/drain resistance. The Flexfet device also provides the opportunity to use the bottom gate for dynamic configurability for ultra-low-power operation and in-space reconfiguration. This feature may also be used to continuously compensate for TID effects, as well as other wearout effects such as hot-carrier degradation. Therefore, this technology permits the design of dynamically "self-repairing" circuits, which are tolerant of large total doses of radiation, SEE, and cryogenic temperature effects. The new Flexfet technology from American Semiconductor is promising for advanced system-on-chip (SOC) solutions for space and missile applications operating in extreme radiation and temperature environments