Thermal analysis of high power led arrays (2009)

LEDs are being developed as the next generation lighting source due to their high\nefficiency and long life time, with a potential to save $15 billion per year in energy cost\nby 2020. State of the art LEDs are capable of emitting light at ~115 lm/W and have\nlifetime over 50,000 hours. It has already surpassed the efficiency of incandescent light\nsources, and is even comparable to that of fluorescent lamps. Since the total luminous\nflux generated by a single LED is considerably lower than other light sources, to be\ncompetitive the total light output must be increased with higher forward currents and\npackages of multiple LEDs. However, both of these solutions would increase the\njunction temperature, which degrades the performance of the LED--as the operating\ntemperature goes up, the light intensity decreases, the lifetime is reduced, and the light\ncolor changes. The word "junction" refers to the p-n junction within the LED-chips.\nCritical to the temperature rise in high powered LED sources is the very large heat flux at\nthe die level (100-500 W/cm2) which must be addressed in order to lower the operating\ntemperature in the die. It is possible to address the spreading requirements of high\npowered LED die through the use of power electronic substrates for efficient heat\ndissipation, especially when the die are directly mounted to the power substrate in a chipon-\nboard (COB) architecture. COB is a very attractive technology for packaging power\nLEDs which can lead improved price competiveness, package integration and thermal\nperformance.\nIn our work high power LED-chips (>1W/die) implementing COB architectures\nwere designed and studied. Substrates for these packaging configurations include two\ntypes of power electronic substrates; insulated-metal-substrates (IMS) and direct-bonded-copper (DBC). To lower the operating temperature both the thermal impedance of the\ndielectric layer and the heat spreading in the copper circuit layers must be studied. In the\nanalysis of our architectures, several lead free solders and thermal interface materials\nwere considered. We start with the analysis of single-chip LED package and extend the\nresult to the multi-chip arrays. The thermal resistance of the system is only a function of\ngeometry and thermal conductivity if temperature-independent properties are used. Thus\nthrough finite element analysis (ANSYS) the effect of geometry and thermal conductivity\non the thermal resistance was investigated. The drawback of finite element analysis is\nthat many simulations must be conducted whenever the geometry or the thermal\nconductivity is changed. To bypass same of the computational load, a thermal resistance\nnetwork was developed. We developed analytical expressions of the thermal resistance,\nespecially focusing on the heat spreading effect at the substrate level. Finally, multi-chip\nLED arrays were analyzed through finite element analysis and an analytical analysis;\nwhere die-spacing is another important factor to determine the junction temperature.\nWith this thermal analysis, critical design considerations were investigated in order to\nminimize device temperatures and thereby maximizing light output while also\nmaximizing device reliability.