A Compact X-Band Bi-Directional Phased-Array T/R Chipset in 0.13 $\mu{\hbox {m}}$ CMOS Technology (2012)

This paper presents an X-band bi-directional T/R chipset in 0.13 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS. The T/R chipset consists of a bi-directional gain amplifier (BDGA), a 5-bit digital step attenuator with two BDGAs for compensating the switch losses, and a 6-bit phase shifter using DPDT switches. The phase and attenuation coverage is 360 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}$</tex></formula> with the LSB of 5.625 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}$</tex> </formula> , and 31 dB with the LSB of 1 dB, respectively. The circuit has a reference state gain of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${> 3.5}~{\hbox {db}}$</tex></formula> , and the return losses of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${> 11}~{\hbox {db}}$</tex></formula> at 8.5–10.5 GHz. The T/R chipset has a phase shift accuracy with the RMS phase error of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${< 4.3}^{\circ}$</tex></formula> , while the RMS amplitude error is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${< 0.8}~{\hbox {db}}$</tex></formula> at 8.5–10.5 GHz. The attenuation accuracy is measured to be <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${< 0.33}~{\hbox {db}}$</tex></formula> , while the RMS phase error is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${< 7.4}^{\circ}$</tex></formula> at 8.5–10.5 GHz. The output P1dB of the T/R chipset is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${> 6.5}~{\hbox {dBm}}$</tex></formula> and the noise figure is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${< 7.5}~{\hbox {db}}$</tex></formula> at 8.5–10 GHz. The chip size is 2.06 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 0.58 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm mm}^{2}$</tex></formula> including pads, and the DC power consumption is 154 mW only in the BDGAs. To authors' knowledge, this is the X-band CMOS T/R chipset with the competitive RF performance compared to other device technologies, which has the smallest size and the lowest power consumption to-date.