Understanding Linear-Mode Robustness in Low-Voltage Trench Power MOSFETs (2009)

The high-temperature electrothermal stability and linear-mode robustness of low-voltage discrete power trench MOSFETs are assessed. The linear-mode robustness is shown to be dependent on the positive temperature coefficient of the subthreshold diffusion current and the MOSFET gain factor. The datasheet threshold voltage temperature coefficient ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC) of a power MOSFET is important because it correlates with the linear-mode robustness and the zero-temperature-coefficient (ZTC) point of the device. The impact of the MOSFET active area and the cell pitch on the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC is experimentally assessed on fabricated devices. It is shown that the magnitude of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC increases as the MOSFET active area increases, whereas it reduces as the cell pitch increases. The drain voltage at the onset of thermal runaway is shown to increase as the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC reduces for the same active area, thereby making the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC an indicator of linear-mode robustness. Although the gate voltage at the ZTC point and the magnitude of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSTX</sub> TC increase with the MOSFET active area, the reduced thermal resistance improves the linear-mode robustness. The implication is that improved device performance in terms of lower specific on-state resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SPEC</sub> in ohm-square millimeter) is at the expense of linear-mode robustness of the power MOSFET since lower <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SPEC</sub> devices have higher gain factors and higher currents are delivered at weaker inversion levels (and therefore contain higher proportions of subthreshold diffusion currents). In designing power MOSFETs, these parameters must be taken into consideration so as to minimize high-temperature instability and improve linear-mode robustness.