94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone (2018)

In power-management integrated circuits (PMIC) for smart phones, cascaded buck and low-dropout (LDO) regulators with N-type power MOSFETs are commonly utilized for high conversion efficiency, power quality and high-density integration as shown in Fig. 27.8.1 [1]. Long paths on printed-circuit board (PCB) from the PMIC to the following applications result in obvious parasitic effects of large L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PCB</sub> and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PCB</sub> , and multilayer ceramic capacitors (MLCC) placed near the application side are necessary. Complex and unpredictable PCB networks induce unexpected poles and zeros in the LDO loop so that an LDO with wide bandwidth (BW) and fast transient response is difficult to design. Furthermore, flash memory, such as universal flash storage (UFS) and embedded-multimedia cards (eMMC), has short-period heavy-to-light-to-heavy (H-L-H) load transients which makes LDO design more challenging. In the waveform shown in Fig. 27.8.1, the gate voltage of the power MOSFET (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> ) is pulled toward 0V when overshoot of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> is caused by a heavy-to-light load transient. Once the light-to-heavy load transient occurs at moment t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> overshoot, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> then suffers from large undershoot because the N-type power MOSFET has a driving dead zone. The driving dead zone is defined as the region of gate voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> lower than the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> level and the power MOSFET delivers no current. The power MOSFET and compensation capacitance forms a heavy capacitance load so that transient performance is degraded. In prior art, the amplifier (amp) and buffer stage consume large quiescent current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</sub> ) for easier stability compensation and higher slew rate (SR). In addition, dummy load current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dummyload</sub> ) at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> or a complex clamping function at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> are utilized for the short-period H-L-H load transient of flash memory. However, the efficiency and circuit complexity are sacrificed as a result.