Top‐Gate Organic Field‐Effect Transistors with High Environmental and Operational Stability (2011)

Top-gate organic field-effect transistors are demonstrated using a bilayer gate dielectric to propose a new compensation mechanism which leads to high operational stability. Neither changes in mobility nor threshold voltage changes are observed after 20 000 cycles of the transfer characteristics or after 24 hours under constant direct-current bias stress. We also demonstrate that these OFETs are air stable up to 210 days. Over the past several years, great progress has been made in the development of organic field-effect transistors (OFETs). Prototypes of electronic devices such as drivers for flat-panel displays,1 complementary circuits,2, 3 radio-frequency identification tags,4 and chemical or biological sensors5, 6 have already been demonstrated. While charge-carrier mobility values have improved2, 3, 7-9 with comparable values for both n- and p-channel transistors, long-term environmental and operational stability remain two major issues that need to be resolved before OFETs can realize their full commercial potential. Recently, much effort has been devoted to improve the stability of OFETs.10-18 For instance, to improve the environmental stability of OFETs, air-stable organic semiconductors have been synthesized10, 11 or encapsulation layers have been developed.12, 13 On the other hand, achieving operational stability is still a major challenge faced by OFETs as well as other field-effect transistor (FET) technologies, such as those based on a-Si:H, poly-Si, and metal-oxide semiconductors. The operational stability of a FET is in general related to dipolar orientation and charge trapping/de-trapping events at all its critical interfaces and in the bulk of the semiconductor and gate dielectric.14-18 The degradation of the performance of a FET during operation is reflected by changes of its current-voltage characteristics that result from changes of mobility (μ), of threshold voltage (Vth), or variations of the capacitance density (Cin) of the gate dielectric. The dynamics of the physical and/or chemical mechanisms producing these changes, intrinsic or extrinsic, affect the performance of a FET on different time scales.14 The stability of a FET is determined by the total effects produced by several physical and/or chemical processes, but in general, one tends to dominate over the others. This has caused current approaches to improve the stability to focus on mitigating individual processes.15-18 Furthermore, the stability of OFETs has been primarily evaluated in devices with a bottom-gate geometry. OFETs with a top-gate geometry are relatively rare because the choice of gate dielectric material is limited since its deposition can potentially damage the organic semiconductor layer underneath. The use of an amorphous fluoropolymer, CYTOP, has provided an attractive strategy for the realization of top-gate OFETs. This is because CYTOP has an excellent chemical stability, is highly hydrophobic, and dissolves in fluorinated solvents that are orthogonal to most organic semiconductor materials.8, 16, 19-22 However, CYTOP-based OFETs usually operate at high voltages because of its low dielectric constant and it is difficult to reliably reduce its thickness while maintaining a high device yield.23 Hence, there is a need for high capacitance density gate insulators that have good stability and simultaneously lead to low-voltage operation. Here, we propose the use of a top-gate bilayer gate insulator comprised of CYTOP and a high-k metal-oxide layer fabricated by atomic layer deposition (ALD) in OFETs employing 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) and poly(triarylamine) (PTAA) blends as the organic semiconductor. The use of a CYTOP/Al2O3 bilayer gate dielectric allows low-voltage operation with remarkable long-term environmental and operational stability. A key aspect arising from the use of this bilayer structure is that the changes of Vth observed during the continuous operation of an OFET, can be compensated with a counter acting mechanism that produces Vth shifts in the opposite direction. Figure 1a shows a schematic cross-sectional view of the OFET structures used for this study. In these OFETs, with different gate dielectric layers, a TIPS-pentacene and PTAA blend, spin-coated on poly-4-vinylphenol (PVP)-coated glass substrates, was used as a hole-transporting semiconducting channel. After deposition, the blended films of TIPS-pentacene and PTAA were annealed to induce vertical-phase segregation. The PVP-coated glass substrate was found to lead to OFETs with better performance; further details are described in Figure S1 of the Supporting Information (SI). In all OFETs, gold and aluminum were used as bottom-contact source/drain electrodes and top-gate electrodes, respectively. Prior to the deposition of the semiconductor layer, the surface of the gold electrodes was treated with a self-assembled monolayer of pentafluorobenzenethiol (PFBT) to improve contact between the metal and organic interface. a) Schematic cross-sectional view of OFETs. b) Capacitance-electric field (C-E) characteristics. c) Current density-electric field (J-E) characteristics. Figures 1b and 1c show the capacitance-electric field (C-E) and current density-electric field (J-E) characteristics of Al2O3 (100 nm), CYTOP (780 nm), and CYTOP (40 nm)/Al2O3 (50 nm) films, respectively. The dielectric properties were characterized using a parallel-plate capacitor geometry of gold (100 nm)/dielectric/indium tin oxide (ITO) coated glass with various areas ranging from 3.1 × 10−4 cm2 to 2.4 × 10−1 cm2. The measured Cin of the Al2O3 and CYTOP films at a frequency of 1 kHz were 78.6 and 2.3 nF/cm2, respectively. The extracted dielectric constant values were 2.0 for CYTOP and 8.9 for Al2O3, similar to previously reported values.8, 24 The CYTOP/Al2O3 bilayer exhibited a Cin of 34.8 nF/cm2 at a frequency of 1 kHz, which is close to the theoretical value (34.6 nF/cm2) estimated from a series-connected capacitor of CYTOP and Al2O3. As shown in Figure 1c, the leakage current densities of the Al2O3 and CYTOP/Al2O3 films remained below 3 × 10−7 A/cm2 at applied fields with a magnitude up to 3 MV/cm. In contrast, the leakage current of a 780 nm-thick CYTOP film reached a value of 2 × 10−7 A/cm2 at an applied field of 1.2 MV/cm. The thickness of the single CYTOP layer would have to be reduced around 50 nm to get a Cin value comparable with that of the bilayer. As we (see Figure S2 in the SI) and others23 have found, this is extremely challenging. Figure 2a–f show the transfer and output characteristics of the best devices, measured from pristine devices under a N2 atmosphere, of OFETs (W/L = 2550 μm/180 μm) using Al2O3, CYTOP, and CYTOP/Al2O3 gate dielectrics. Figure 2a shows that OFETs with an Al2O3 gate dielectric operate below 8 V due to its high Cin value. However, its current-voltage characteristics show strong hysteresis due to the presence of highly polar Al(OH)3 groups that may remain during the device fabrication. Based on the sub-threshold slope (SS) value of 0.45 ± 0.08 V/decade measured in these OFETs, we estimate a maximum trap density value of 3 × 1012 cm−2.25 Average values of μ = 5.5 (±2.0) × 10−3 cm2/Vs, Vth = -2.1 ± 0.4 V and on/off current ratio (Ion/Ioff) of 2 × 103 were calculated for all 7 devices. On the other hand, OFETs with the CYTOP gate dielectric exhibited no hysteresis but operate at high voltages of up to 50 V due to its low Cin value. Average values (7 devices) of μ = 0.39 ± 0.16 cm2/Vs, Vth = -24.3 ± 0.8 V, Ion/Ioff = 5 × 104 and SS = 2.20 ± 0.79 V/decade were measured in these devices. In contrast to Al2O3-based OFETs, the maximium interfacial trap density in devices with a CYTOP gate insulator was estimated to be only 5 × 1011 cm−2. Similarly, OFETs using the CYTOP/Al2O3 gate dielectric showed no hysteresis and achieved a maximum value of μ = 0.6 cm2/Vs at 8 V due to the relatively high Cin value of the bilayer gate dielectric. Average values (8 devices) of μ = 0.46 ± 0.08 cm2/Vs, Vth = -2.4 ± 0.1 V, Ion/Ioff = 105, SS = 0.20 ± 0.06 V/decade and a maximium interfacial trap density of 5 × 1011 cm−2 were measured in these devices. Representative transfer and output characteristics of TIPS-pentacene and PTAA blend OFETs with a) and b) Al2O3 single-layer, c) and d) CYTOP single-layer, and e) and f) CYTOP/Al2O3 bilayer dielectrics. To study their environmental stability, all OFETs were exposed to a normal ambient condition with a relative humidity between 30 and 50%. Variations of μ and Vth were monitored at discrete intervals. At each interval, each substrate was briefly transferred back into a N2-filled glove box for electrical measurements and operational stability tests. Tables that summarize the different conditions of environmental exposure and electrical stress tests and the measured values of μ and Vth for all devices are presented in Figure S3 and Tables S1–S3 of the SI. Figure 3a shows that in all OFETs no significant change in μ was observed after up to 31 days of exposure to air. The good air stability of TIPS-pentacene26-28 also contributes to the environmental stability of these OFETs. In OFETs with the Al2O3 gate dielectric, a gradual increase of the average value of μ from 5.5 (± 2.0) × 10−3 cm2/V up to 1.1 (±0.4) × 10−2 cm2/Vs was observed. In the other OFETs, after an initial increase within the first 11 days of exposure to air, μ remained unchanged with average values of 0.60 ± 0.20 cm2/Vs for CYTOP-based OFETs and 0.52 ± 0.09 cm2/Vs for CYTOP/Al2O3-based OFETs. The variations of Vth for the devices with different gate dielectrics are shown in Figure 3b. In OFETs with the Al2O3 gate dielectric, the average value of Vth, measured from sweeps of VGS from off-to-on regime, varied from -2.4 ± 0.3 V to -2.8 ± 0.3 V after 31 days in air, but large device-to-device variations of Vth were observed, as shown in Table S1. In contrast, in hysteresis-free OFETs with the CYTOP gate dielectric, a large positive shift in Vth from -24.3 ± 0.8 V to -4.0 ± 0.7 V was observed after 11 days of exposure to air. After this initial variation, no serious shift in Vth was observed, reaching a value of -3.7 ± 0.3 V after 31 days in air. The initial shift in Vth can be attributed to O2 diffusion and doping of the TIPS-pentacene layer.12, 13, 26, 29 Similar changes, albeit of a smaller magnitude, were observed in hysteresis-free OFETs with the CYTOP/Al2O3 bilayer. After 31 days in air, only a minor shift in Vth from -2.5 ± 0.1 V to -1.4 ± 0.1 V was observed. The encapsulation properties of the dielectrics used in the top-gate OFETs were further tested, after 31 days in air, by exposing them to O2 plasma for 5 min at a power of 750 W, a more severe condition than air exposure. In the OFETs with the CYTOP gate dielectric Ioff increased from 10−10 to 10−8 A. This increase is due to an increased leakage current attributed to damage of the CYTOP layer. On the other hand, Al2O3 acts as a protective layer to the energetic O2 plasma, so no significant changes in the Ion/Ioff ratios were observed in the devices with Al2O3 and CYTOP/Al2O3 gate dielectrics. As shown in Figure 3a,b, after O2 plasma treatment, the electrical properties of the OFETs with a CYTOP/Al2O3 bilayer have been tested after an accumulated air exposure up to 210 days (7 months) and μ and Vth remained practically unchanged. The other OFETs were not measured in one case because the CYTOP gate dielectric was permanently damaged by the O2 plasma and in OFETs with the Al2O3 gate dielectric because they showed strong hysteresis characteristics and significant variations of the electrical parameters. Further details on environmental stability are described in Figure S3–S7 of the SI. Variations of the averaged a) mobility and b) threshold voltage as a function of air exposure. Operational stability during multiple scans of the transfer characteristics measured in OFETs c) before and d) after air exposure for 31 days. In addition to the environmental stability, the operational stability is of critical importance for circuit design and overall device lifetime. The mechanisms of degradation under continuous operation are related to the dynamics of dipolar groups and to charge trapping and de-trapping events at all of the critical interfaces in an OFET and in the bulk of the semiconductor and gate dielectric.15-18 The operational stability was evaluated in two ways: 1) by multiple continuous scans of the transfer characteristic and 2) by applying a constant direct current (dc) bias stress. The transfer curves were measured in all OFETs during multiple continuous scans from the “off” to the “on” region, before (Figure 3c) and after air exposure (Figure 3d) for 31 days (details in Figure S3 and Tables S1–S3 of the SI). The OFET with an Al2O3 gate dielectric suffered a strong negative shift in Vth after the first 100 scans. After that, smaller changes in Vth were observed up to the 1000th scans. The same general behavior was observed before and after air exposure. In contrast, negligible changes in the transfer characteristics, during the first 1000 scans, were observed in OFETs with CYTOP and CYTOP/Al2O3 gate dielectrics, as shown in the insets of Figure 3c. To further test the operational stability of these devices before exposing them to air, both OFETs were subjected to an additional 20,000 scans. Figure 3c shows that even under such conditions, negligible changes were observed. Figure 3d shows that the operational stability of these devices was preserved after being exposed for 31 days in air. Before exposing the OFETs to air and after 1,000 scans, all OFETs were subjected to 3,600 s (1 h) of dc bias stress.Figure 4a shows the temporal evolution of the drain current (IDS) measured in all OFETs normalized to the initial value. In the OFET with the Al2O3 gate dielectric the normalized IDS dropped to a final value of 0.77 after 1 h. During the same interval, the normalized IDS dropped to 0.9 in a CYTOP device. However, the evolution of the CYTOP/Al2O3 bilayer device is different in that the normalized IDS slightly increased to 1.04 after 1 h. Figure 4b shows the evolution of the normalized IDS measured after OFETs were exposed to air for 31 days. Qualitatively, all OFETs showed a similar behavior before and after exposure. The transfer and output characteristics measured after operational stability tests are shown in Figure S8 and S9 of the SI. The operational stability of OFETs with the bilayer gate dielectric was further tested, after O2 plasma treatment, by monitoring IDS changes over 24 h of dc bias stress. Figure 4c shows that these changes remain below 4% its original value. As shown in the inset of Figure 4c, this remarkable stability results in negligible changes of the transfer characteristics. Despite device-to-device variations, OFETs with the bilayer gate dielectric showed a very similar behavior and overall changes in IDS remained below 7% regardless of their history of air exposure or prior stability tests (see Figure S10, S11 and S12 in the SI). Operational stability during continuous dc electrical bias stress. Temporal evolution of the normalized drain current during dc bias for: a) 1 h before; b) 1 h after air exposure for 31 days; and c) 24 h dc stress after O2 plasma, inset shows the transfer characteristics measured before (filled symbol) and after (open symbol) bias stress test. d) Temporal evolution of the normalized drain current in OFETs with bilayer gate dielectrics with different CYTOP/Al2O3 ratios during dc bias for 1 h. e) Simulation of CYTOP/Al2O3 bilayer local voltage distribution as a function of CYTOP thickness. f) Schematics of the temporal evolution of the two different contributions giving rise to the compensating mechanism. A decrease in IDS during dc electrical stress is commonly related to charge carrier trapping at the interface of semiconductor and gate dielectric or in the bulk of semiconductor or gate dielectric.15, 17, 18 On the other hand, an increase of IDS is commonly associated with the presence of dipoles that can be oriented at the gate dielectric or charge injection from the gate electrode.17, 18 In this context it is clear that the reduction of IDS observed in OFETs with the single Al2O3 and CYTOP layers is dominated by a trapping mechanism at the semiconductor/gate dielectric interface. The introduction of a bilayer structure allows to independently compensate the effects of these trapping mechanisms with an independent mechanism, in this case, a change in the polarizability of the Al2O3 layer which can be related to the presence of highly dipolar groups, Al(OH)3, remnant from the deposition of Al2O3. In OFETs with a single Al2O3 layer, these groups could create both shallow traps, responsible for the strong hysteresis characteristics, and deep traps causing the strong decrease in IDS during continuous electrical bias. However, in OFETs using the bilayer gate dielectric, these groups act as dipoles that can be oriented at the Al2O3/CYTOP interface or at the Al2O3 bulk and, therefore, do not contribute to the formation of shallow traps. Despite the very small leakage currents, around 10−10 A, observed in bilayer devices, charge injection and trapping in the dielectric may not be ruled out entirely. The remarkable stability of OFETs with the bilayer under electrical bias hence is attributed to compensating effects: 1) a decrease in IDS caused by intrinsic deep traps at the CYTOP/TIPS-pentacene interface and 2) an increase in IDS caused by dipoles that can be oriented at the CYTOP/Al2O3 interface or at the Al2O3 bulk and/or by charge injection and trapping at the gate dielectric. The strength of the effects of these compensating mechanisms should then be strongly dependent on the thickness of the CYTOP layer and independent of the OFET geometry. To test these hypotheses, we fabricated a new batch of OFETs using bilayer gate dielectrics with different CYTOP/Al2O3 ratios: 40 nm/50 nm and 530 nm/50 nm, respectively. The changes of IDS during dc stress were monitored for 1 h using -8 and -25 V, respectively, to achieve similar IDS values (see Figure S13 in the SI). Figure 4d shows the dynamical changes of IDS for three devices per CYTOP/Al2O3 ratio. As expected, in OFETs with the 530 nm/50 nm CYTOP/Al2O3 ratio, the normalized IDS steadily decreases as in OFETs with a single CYTOP layer. However, the opposite behavior is observed in OFETs with the 40 nm/50 nm CYTOP/Al2O3 ratio. The effect of dielectric thickness on the performance can be based on the local voltage distribution the Figure shows the voltage distribution within the bilayer as a function of the CYTOP thickness. the thickness of CYTOP is comparable to that of the Al2O3 layer, the voltage both layers is comparable and the for dipolar orientation is Hence, small changes in the polarizability of the Al2O3 layer can have a significant over the charge density in the channel. As the thickness of CYTOP is the voltage the Al2O3 layer decreases while the CYTOP layer most of the gate This the for dipolar orientation within the Al2O3 layer and also the charge density within the to variations within the Al2O3 layer. The of this compensation mechanism was by and bottom-gate pentacene transistors with a nm) bilayer. and bottom-gate pentacene OFETs show performance after 1 h dc bias stress Figure in the SI). by the compensation mechanism in Figure we that this a new for the realization of air-stable OFETs, and FET in In we fabricated and characterized TIPS-pentacene and PTAA blend based OFETs with Al2O3, CYTOP, and CYTOP/Al2O3 top-gate dielectrics. OFETs with the CYTOP/Al2O3 bilayer gate insulator show hysteresis-free high performance at low voltages due to their high capacitance density and excellent interfacial We demonstrated that OFETs using the bilayer gate dielectric show long-term environmental stability with no significant changes in mobility or threshold voltage after 210 days (7 months) of air O2 plasma A remarkable long-term operational stability of OFETs with the CYTOP/Al2O3 bilayer was also demonstrated under multiple continuous scans, up to and under a constant dc bias up to 24 h. This operational stability was achieved because this bilayer with the thickness ratio, allows the compensation of effects arising from of deep traps and simultaneously dipolar orientation at the CYTOP/Al2O3 interface and/or charge injection from the gate We demonstrated the of this effect by also both and bottom-gate OFETs with pentacene that show performance to the TIPS-pentacene OFETs dc bias stress (see Supporting Hence, we that the use of compensating mechanisms in bilayer gate dielectrics, in with top-gate lead to OFETs with operational and environmental stability which could be used in the need of In it is that this have an over other transistor OFETs with a bottom-contact and top-gate structure were fabricated on glass layers were from 2 of 20 and as a in which were by at for 40 s and at on a for 1 h in a N2-filled glove (50 nm) bottom-contact source/drain electrodes were by a A self-assembled monolayer of pentafluorobenzenethiol (PFBT) was on the electrodes by in a in for min in a N2-filled with and The TIPS-pentacene and PTAA blend was as TIPS-pentacene and PTAA were in for a of 30 and the two individual were to a ratio of TIPS-pentacene and PTAA blend layers were by at for s and at for 20 were annealed at 40 for h and at 100 for min in a N2-filled Al2O3 (100 nm), CYTOP (780 nm), and CYTOP (40 nm)/Al2O3 (50 nm) layers were used as top-gate dielectrics. A from was used to Al2O3 dielectric films at the Al2O3 films by are described CYTOP was from with a of This CYTOP was used to 780 nm-thick layers at for To the 40 nm-thick CYTOP layers, the original was with a to have a 2 of The 40 nm-thick CYTOP layers were by at for The CYTOP (780 and 40 nm) films were annealed at 100 for 20 and were out in a N2-filled nm) gate electrodes were by a of the OFETs was out in a N2-filled glove box 0.1 Capacitance-electric field (C-E) measurements were out with a capacitance (1 at characteristics of OFETs were measured with an Supporting Information is from the or from the This material is based in by by the of and by the of the under of importance to are as are but not or are made as by the The is not responsible for the or of by the than should be to the for the