Bisramgen: a silicon complier for built-in self-repairable random-access memories (1997)

This research focuses on a CAD tool, BISRAMGEN, that synthesizes layout geometries of built-in self-testable and built-in self-repairable single-port static and dynamic RAM modules with flexible, user-specified geometry parameters and CMOS design rules. Such a tool is of great importance in commercial microelectronics industry because it allows CAD designers to generate fault-tolerant RAM layouts very efficiently. Built-in self-repair (BISR) is an extremely cost-effective technique to enhance the manufacturing yield and field survivability of state-of-the-art integrated circuits employing deep submicron CMOS fabrication technology. BISR circuits not only increase the manufacturing yield and fault-tolerance of RAMs, but also allow them to be used in mission-critical field applications where diagnosing faults and performing replacements are too costly or impossible (such as space, avionic and oceanic applications). Furthermore, hard failures in embedded RAMs used in high-density microprocessors and ASICs cannot be repaired by other means due to the difficulty of accessing the internal nodes of the circuit.
Currently, the task of incorporating such circuitry within embedded memories can be performed only manually or using semi-custom design techniques by the designer, and is thereby a major bottleneck in the design cycle. BISRAMGEN takes only about 10 minutes of CPU time on a DEC 3100 to build a 1 Mb static RAM array with 8 spare rows and the BIST/BISR circuitry.
BISRAMGEN takes as input a high-level specification of the RAM parameters and the CMOS geometrical design rules, and builds an efficient built-in self-repairable RAM layout that is both drc and lvs-correct for the given ruleset (i.e., the layout satisfies the design rules for the chosen process and topologically agrees with the circuit schematic). BISRAMGEN uses a novel BIST approach based on the Inductive Fault Analysis (IFA) technique which guarantees a high physical defect coverage for CMOS RAMs. BISRAMGEN is design-rule independent; it can be used with a wide range of submicron CMOS processes developed by commercial microelectronics companies. It has been tested for processes supporting at least three layers of metal, with $\lambda$, the minimum feature size, ranging from 0.5 $\mu$m to 2.0 $\mu$m, and found to produce correct and efficient layouts. BISRAMGEN achieves a modest area overhead (typically less than 7%) for BIST, BISR and redundant elements combined, for a range of 10 representative CMOS processes with $\lambda$ varying from 0.5 $\mu$m to 2.0 $\mu$m. The area overhead achieved by BISRAMGEN is found to be comparable with or better than published results obtained using full-custom layout design. BISRAMGEN achieves a high yield of more than 95% with 10 spot defects scattered in the layout and a reliability of above 96% through 2 years of chip use. Furthermore, BISRAMGEN uses an innovative circuit technique for BISR (US patent pending) that guarantees effective zero delay overhead on RAM access time during normal operation. Existing BIST and BISR techniques are either associated with delay overhead (9) or use expensive circuit techniques that cause extra processing steps or more area overhead (54). (Abstract shortened by UMI.)