Single-Electron Charging Phenomena in Nano/Polycrystalline Silicon Point Contact Transistors (2003)

This paper gives a review of our recent work investigating the physics of single-electron charging phenomena in nano/polycrystalline silicon nanostructures. We first provide a short overview on the research of silicon-based single-electron devices from the last decade. Various single-electron transistor structures are compared in terms of control of electron islands and tunnel barriers. We then study the single-electron charging phenomena in nano/polycrystalline silicon nanostructures. A novel point-contact transistor is introduced, which features an extremely short and narrow nano/poly-Si nanowire as the transistor’s channel. This structure is suitable for studying how a grain smaller than 10 nm in size and a discrete grain boundary work as a charging island and a tunnel barrier, respectively. The relationships between structural and electrical parameters of grains/grain-boundaries and the resulting Coulomb blockade characteristics for the point contact transistors are investigated by applying various passivation processes. Finally, optimisation of grain and grain-boundary structures is discussed for improving the Coulomb blockade characteristics and realizing nano/poly-Si single-electron transistors operating at room temperature. Introduction Over the last few decades, the performance of VLSI circuits has been improved steadily by scaling down device dimensions. In dynamic random access memories (DRAMs), for instance, the amount of charge stored per memory cell has been decreased with reduction of the cell area. After the 1 Mbit generation, however, it has become increasingly difficult to keep up such a continuous decrease in the stored charge per bit because the signal becomes less immune to leakage current, internal noise, and soft errors. In microprocessors, power consumption per one MOS transistor has also been reduced due both to miniaturisation and to improved operation conditions. Nevertheless, the total power consumption per microprocessor has gradually been increasing as the number of MOS transistors per chip increases, and the number of electrons used to switch one MOS transistor on and off needs to be reduced further to counter this trend. However, when the number of electrons becomes less than 1000, inherent charge fluctuations cause unacceptable statistical variations in the subthreshold characteristics of the MOS transistors. For both memory and logic applications, how to guarantee future ‘scalability’ of the devices is a key issue, along with a reduction of the number of electrons. Singleand few-electron devices are expected to overcome these issues by introducing the Coulomb blockade (CB) effect [1],[2] as a new principle for the controlled transfer of a small number of electrons. A key building block for singleand fewelectron devices are the double tunnel junction (DTJ) and multiple tunnel junction (MTJ) structures shown in Figs. 1(a) and (b), which are composed of a series of islands with tunnel barriers between them. When a single electron enters onto the island, the charging energy EC of the island increases, and the transfer of even one electron is strongly suppressed (Coulomb blockade) if the charging energy is higher than the thermal energy kBT. From the device-engineering point of view, the MTJ is more preferable than the simple DTJ since it reduces co-tunnelling [3], which generally leads to unfavourable leakage current. Also the MTJ structure is robust against offset charge effects [4][5], which vary the Coulomb gap and even may break the CB. In general, the tunnel junction (TJ) should meet the following two requirements to show the CB effects at a temperature T: (a) (b) conductor island Fig.1: (a) Double tunnel junction and (b) multiple tunnel junction. Rt ≫ RQ = h/e = 25.6 kΩ (1) EC = e/2CΣ ≫ kBT (2) to avoid quantum and thermal smearing of the electronic states confined in the islands. In Eqs. (1) and (2) RQ is the quantum resistance (≡ h/e), and Rt and CΣ are the total tunnel resistance of the TJ and total capacitance of the electron islands, respectively. A number of fabrication methods for DTJs and MTJs have been reported. These structures may be classified into two groups in terms of the manner of formation of nanoscale electron islands: patterned electron islands and naturally formed ones. A silicon-based patterned island structure has been realized by using a pattern-dependent oxidation (PADOX) technique [6]. This technique utilizes faster oxidation caused by stress at the pattern edge, and a DTJ is formed at the both ends of a Si nanowire (NW). This technique has achieved a single electron island with a lateral size of less than 10 nm. An alternative approach is to use an AFM-based oxidation technique [7]. A NbO2 DTJ was defined on a Nb NW resulting in a Nb single island with a lateral dimension of a few nm. A step edge cut off (SECO) technique [8] has also been reported to form a metallic MTJ structure. Table Naturally formed structures exploit various kinds of local disorder in nanometer-scale structures to form the DTJ or MTJ. In a heavily doped Si NW [9] with a few tens of nanometers in width, randomly distributed dopant atoms cause potential fluctuations, and a linear chain of electron islands are formed when a negative gate bias is applied to a gate electrode placed adjacent to the NW [10]. This is a fairly simple structure and has often been used for making CB memory [11][12] and logic [13] devices. However, the CB oscillation can usually be observed Naturally-formed Patterned Controllability of dot size Controllability of dot position Controllability of tunnel barrier thickness Compatibility with Si-ULSI Controllability of tunnel barrier height Random dopant induced Roughness induced Defect induced