Impact of electrical and thermal stresses on TSV radiofrequency performance (2016)

This paper presents a study of the propagation parameters (impedance and propagation constant) for interconnection structures implementing interconnection lines (wafer front and backside) combined with Through Silicon Via (TSV). Lifetime acceleration experiments are conducted on these structures and indicate a significant variation of the propagation parameters across lifespan. The underlying physical mechanism is demonstrated and an activation model for the prediction of the line parameter variation is proposed. TSV-last processes have been considered by industry for the implementation of 3D interconnects into various kind of silicon substrates already functionalized on the front side. This is possible thanks to a TSV process with a low temperature budget (&amp;lt;200°C), guaranteeing the compatibility with most of the pre-existing MOS and passive technologies. IPDiA is offering this type of TSV technology in combination with the PICS passive platform (Passive Integrated Connecting Substrate). Several test vehicles have been implemented and excellent performances have been observed in the small signal/RF domains; electrical models have been extracted from test silicon and are showing a good agreement with simulation results and earlier literature. Application domains with permanent bias have also been considered and non-linear effects related to the semiconductor nature of the substrate have been reported (i.e. drift-diffusion). However, the effect of electrical and thermal stress that might arise from severe applications or long lifespan, and their impacts on TSV electrical stability, have not yet been reported in the literature. This works concentrates on the study of the instability modes that are related to the TSV dielectric aging under permanent bias accelerated by temperature. To avoid effects from other mechanisms (like, for example, copper diffusion in the oxide) under the selected acceleration conditions (Efield&amp;lt;10MV/cm, temperature &amp;lt;100°C), specific test structures (planar CPW) are designed. It consists of an AlSi (0.5%) metallization, which is isolated from the P type HR (High Resistivity) substrate by TSV isolation dielectric. Four different flavors of dielectric are proposed: PECVD oxide deposited at 150°C/200°C combined/not with a thermal oxide liner. When implemented, the liner is intended to enhance the dielectric/silicon interface, thus allowing to differentiate the effects of fixed charges, mobile charges, and interface states density. A strong correlation is found between charge density within the dielectric and the CPW loss and characteristic impedance. While line loss increases with charge density, the opposite behavior is observed for the characteristic impedance. Furthermore, under CVS (constant voltage stress) at 7.5 MV/cm under 100°C, a displacement of mobile charges into the dielectric is observed, that correlates to the variation of the CPW performances. FTIR analysis indicates that the mobile charges are related to the presence of silanol/hydroxide ions resulting from moisture absorption in the oxide. Similar effects are observed on real 3D TSV structures. An activation model is derived from previous results, which allows predicting the evolution of the CPW characteristics as a function of thermos-electrical stress.