NCFET: Opportunities & challenges for advanced technology nodes (2017)

In ten years since the concept of negative capacitance (NC) was first postulated [1] there have been numerous experimental demonstrations of the effect [2, 3]. In addition, circuit simulations show that NCFET can provide one generation performance boost [4, 5]. But advanced technology nodes present new challenges for NCFET. In scaled fin pitch we have to find room for the interfacial layers (IL), ferroelectrics (FE), work function (WF) metal, and gate metal (Fig. 1). During FE layer formation process we need 10nm thick metal layer to enable uniform crystallization. That means that we have to either scale down the FE layer thickness or the WF metal. It seems that the scaling will necessitate thinner FE layer, which needs to be crystalized at higher temperature and it is much more prone to leakage. Resulting FE capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> ) is too large in magnitude and hence there will barely be any NC effects (Fig. 2). To achieve steeper subthreshold slopes (SS), we have to use thicker FE and we are forced to reengineer the metal gate stack. Since the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> of NCFET is determined by capacitance matching, it is more difficult to get a wide range for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (Fig. 3). The voltage gain in an NCFET depends on both gate and drain bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) [4]. Because of the drain to gate coupling, the voltage at the internal gate node (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INT</sub> ) becomes less than the applied voltage at the external gate node (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) in the sub-threshold regime (Fig. 4(a)). In fact, for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> <;<; V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> , V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INT</sub> becomes negative (Fig. 4(a)) [considering, no shift in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> occurs through gate WF mismatch]. Therefore, despite having lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> , the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> in NCFET can be lower than the control device (Fig. 4 (b)) [4]. On the other hand, for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> > V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> , V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INT</sub> is enhanced beyond V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , as NC of the FE provides amplification. That accounts for the boost in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> (Fig. 4 (b)).