Editorial (2015)

Over the past 50 years, computing devices have rapidly improved in performance and function density enabled by the continuous shrinking of semiconductor manufacturing geometries. Device sizes of 10–20nm have now approached atomic scales. Clock speeds of digital systems have increased from a few hundred kilohertz to the gigahertz regime and the number of transistors per die has increased from about a thousand to up to 6 billion, while die sizes have only doubled (or tripled at best), indicating a more than 1000-fold increase in device density. A consequence of fabricating transistors that small, even with advanced processes, is structural irregularities at the atomic scale, e.g. the presence or absence of single doping atoms affect device characteristics in a random manner. While noise and device mismatch have always been present and have been posing major design challenges in electronic systems, three new challenges are coming together in modern electronic devices and systems: (a) the stochastic nature of the variations at the nanoscale, (b) the drastic increase in the number of individual devices on a chip necessitating ever smaller per-device failure probabilities, and (c) aging and wear-out becoming more rapid. The result is that failure rates increase significantly and fabrication yield decreases, and the impact of these low-level effects propagates from device level all the way up to the system level. Therefore, variability needs to be addressed at all stages of the design flow: during design, physical implementation, system assembly and post-fabrication. At the design stage, the availability of good quality/accuracy statistically enhanced device models is essential in order to be able to predict the effects of stochastic variations on a design and to take appropriate counter-measures. In the case of CMOS transistor designs, optimising device sizes and selecting appropriate topologies are methods used to tackle variability. The greatest workload and responsibility remains to date with chip manufacturers, who continuously improve fabrication facilities and feed-back according to design rules for creating the physical layout to the designers in order to ensure high yield figures. Despite such carefully defined design rules and a number of existing circuit design and layout techniques to reduce device mismatch, the results are never perfect even with considerable design efforts made. Moreover, new devices and technologies are continuously being developed and refined in order to further advance technology. These include, for instance, Silicon-on-Insulator and FinFET transistors, which work with un-doped channels thereby eliminating one major cause of variability. There are also certain post-fabrication measures that can improve the performance of a device or at least make it usable with reduced performance, for instance, altering power-supply voltages, slowing down clock-speed or disabling (redundant) parts. Nevertheless, satisfying timing-constraints and optimising speed/power requirements while achieving robust operation becomes a more and more difficult feat, since analogue circuits – the fundamental building blocks of any electronic circuit – are directly affected by device variability because of sensitive parameters like device matching, gains, thresholds or reference potentials. Other approaches exploring entirely different materials, such as graphene, carbon nano tubes, spintronics and even molecules are becoming more and more viable and established. Despite great efforts and advances in these areas – be it refined silicon technology or novel materials – the laws of physics and chemistry will always apply and intrinsic variability, device mismatch and noise have been and will always be present at all levels of any system albeit perhaps in different shape, form and magnitude. As a result, large complex systems need to be designed while taking certain levels of ‘uncertainty’ at lower abstraction levels into consideration. In turn, when assembling larger entities from smaller components, a certain amount of ‘uncertainty’ in behaviour needs to be expected. In this vein, it is as much about understanding, modelling and predicting variability and noise, as it is about thinking about ways to ‘embrace intrinsic variations’ and build systems that can robustly function despite these effects. This Special Issue addresses these fundamental problems from a number of viewpoints. Papers have been solicited on their potential for future developments successfully tackling some of the fundamental issues related to “Designing with Uncertainty”. The scene is set by two position papers from industry, one addressing the device level and one addressing the system level. The device-level paper “Mastering CMOS Variability Is the Key to Success” highlights random variability as the maker or breaker of designing with advanced CMOS technology and suggests that understanding, controlling and mastering variability in order to accurately factor it into the design process is the key to success. Juxtaposed is the paper “Defect Avoidance in Programmable Devices”, which discusses the use of programmable logic devices as a new way to practice yield improvement through exploiting redundancy at configuration time. It is argued that by doing so, the overheads of traditional redundancy such as explicit spares, replacement logic and on-chip non-volatile memory can be avoided. In the same vein follow six technical papers on theoretical and practical aspects of designing with uncertainty. An approach to low-level post-fabrication optimisation using fine-grained reconfiguration is introduced in “Fighting Stochastic Variability in a D-type Flip-Flop with Transistor-Level Reconfiguration”. Complement to that is the work on “An Algebra of Switching Networks”, which bridges the ‘language barrier’ between circuit structure and circuit functionality thereby providing a formal methodology to keep both descriptions synchronised. This enables exploration of structural redundancy to improve robustness while ensuring that functionality remains unchanged. Turning towards long-term effects of variability, the paper “Extending Standard Cell Library for Aging Mitigation” addresses transistor aging due to bias temperature instability (BTI), which is one of the major sources of unreliability in nano-scale technology nodes and causes circuit delays to increase and eventually lead to shortened circuit lifetimes. The work presented in “A Probabilistic Model for Nanocell Reliability Evaluation in Presence of Transient Errors” shifts the focus to modelling the reliability of nanocell devices which consist of conducting nanoparticles connected through a randomly formed self-assembled monolayer of molecules. Moving up in the design hierarchy, the paper “Yield-Driven Design-Time Task Scheduling Techniques for Multi-Processor Systems-on-Chip (MPSoCs) under Process Variation” provides a comparative study of current variation-aware design-time task and communication scheduling techniques targeted at embedded MPSoCs. Finally, in “Reliable Computation with Unreliable Computers” a holistic viewpoint is taken on running a real-world system of a million processor cores. In such a system, it is unrealistic to expect 100% functionality on power-up and operational availability degrades over time. It is argued that, therefore, built-in autonomous fault-tolerance strategies are paramount. It is our pleasure and satisfaction to present to you this range of high-quality papers covering both in breadth and depth a number of approaches to tackle current electronic design challenges when “Designing with Uncertainty” aka. “Making Sure a Design Works Reliably in the Real World Using Cutting-Edge Technology”. Sani R. Nassif received his Bachelor's degree from the American University of Beirut in 1980, and his Master's and PhD degrees from Carnegie-Mellon University in 1981 and 1986 respectively. He worked at Bell Laboratories until 1996, then joined the IBM Austin Research Laboratory where he had various technical and management positions. In 2014, he formed the company Radyalis which is focused on applying EDA techniques to the area of Cancer Radiation Therapy. He has authored one book and numerous conference and journal publications, received many Best Paper awards (IEEE Trans. CAD, ICCAD, DAC, ISQED, ICCD, SEMICON) and given keynote and plenary presentations at SASIMI, ESSCIRC, BMAS, SISPAD, SEMICON, PATMOS, VLSI-SOC, GLVLSI, ASAP and ASPDAC. He is an IEEE Fellow (since 2008), president of IEEE-CEDA, was a member of the IBM Academy of Technology, a member of the ACM and AAAS, and is an IBM Master Inventor with more than 70 patents. Martin A. Trefzer is an Anniversary Research Lecturer in the Department of Electronics at the University of York. He has received his Degree in Physics from the Technical University Berlin in 2001 and his PhD from the University of Heidelberg in 2006. His research interests include variability aware analogue and digital hardware design, biologically motivated models of hardware design, evolutionary computation, and autonomous fault-tolerance. His current focus is on using bio-inspired techniques to create adaptive, self-healing multi-reconfigurable architectures to tackle nano-scale CMOS design challenges. He is a co-investigator on three currently running EPSRC projects: Bio-inspired Adaptive Architectures and Systems (Platform Grant), Graceful and PAnDA. He is a senior member of the IEEE, a member of the DPG, co-chair of the International Conference of Evolvable Systems (ICES), and vice chair of the IEEE Task Force on Evolvable Hardware.