(Invited) Device Scalability of InGaZnO TFTs for Next-Generation Displays (2020)

Amorphous oxide semiconductor thin-film transistors (TFTs) are used as the backplane for large-screen, high-resolution OLED and LCD displays. Amorphous InGaZnO (a-IGZO) TFTs are widely used in commercialized TVs, tablets, and wearable displays for its good device performance, stability, and process controllability. Also, due to its extremely low off-current, a-IGZO TFTs are used for low refresh rate and low-power displays. Furthermore, a-IGZO TFTs have a low process temperature, enabling fabrication on various substrates (including flexible films), and also hybrid integration with other backplane technologies, such as LTPS or Si CMOS. By taking advantage of the low off-current and low process temperature, a-IGZO can be monolithically integrated in the back-end of Si CMOS for low-power applications, as well as embedded memories for long retention and non-volatile operation. There are many incentives to shorten the channel length of IGZO TFTs. First, shorter channels can boost the current without incorporating high-mobility oxides, which usually suffer from reliability issues and small process margin. When gate drivers are integrated directly onto the panel, larger currents allow smaller device footprint, thinner bezel width, and less dead space. Second, transistors with sub-micron pitch are desired to bridge the pixel gap between smartphone displays and micro-displays, and to be used for consumer AR/VR displays with &gt; 1000 ppi. Third, reduced device length is necessary for fine-grained integration with nanoscale CMOS. However, short-channel TFTs suffer from short-channel effects (SCE). For example, threshold voltage (V t ) roll-off, where the V t reduces for short channel lengths, causes device variability and hence, worse process tolerance. Therefore understanding and control of SCE is critical for designing and fabricating short-channel TFTs. In this paper, we study the device scalability of short-channel IGZO TFTs down to 1μm. The electrical channel length (L eff ) is not the same as the gate length (L g ), and is determined by the carrier profile at the gate edges. L eff ( = L g - ΔL) is obtained by the transmission line method (TLM), or shift-and-ratio method. Accurate ΔL extraction is important in determining the exact device mobility. Since scalability is related to the carrier concentration profile, it is strongly dependent on the process, where oxygen and hydrogen content varies with process conditions, and profiles change during thermal treatments. Devices with higher carrier concentration generally result in larger ΔL and worse SCE. Device simulations using TCAD shows the dependence on overlap (L ov ), slope of carrier Gaussian decay (X c ), channel carrier concentration (N ch ) on the L eff and SCE. TCAD simulation results are matched with experimental measurements for verification of the simulation models and parameters used. We define a critical carrier concentration (N crit ) which defines the L eff . Changing the carrier profile while maintaining N crit results in little difference in ΔL. For devices with an underlap, similar ΔL values result in similar SCE. However, for devices with an overlap, even with the similar ΔL values, SCE is more sensitive to carrier profile at the channel edges. This study shows that SCE may be controlled through shaping of the carrier concentration profile through optimization of the device structure and process conditions allowing fabrication of short-channel TFTs with good scalability.