High Performance Switches and Routers (2006)

PREFACE. ACKNOWLEDGMENTS. 1 INTRODUCTION. 1.1 Architecture of the Internet: Present and Future. 1.2 Router Architectures. 1.3 Commercial Core Router Examples. 1.4 Design of Core Routers. 1.5 IP Network Management. 1.6 Outline of the Book. 2 IP ADDRESS LOOKUP. 2.1 Overview. 2.2 Trie-Based Algorithms. 2.3 Hardware-Based Schemes. 2.4 IPv6 Lookup. 2.5 Comparison. 3 PACKET CLASSIFICATION. 3.1 Introduction. 3.2 Trie-Based Classifications. 3.3 Geometric Algorithms. 3.4 Heuristic Algorithms. 3.5 TCAM-Based Algorithms. 4 TRAFFIC MANAGEMENT. 4.1 Quality of Service. 4.2 Integrated Services. 4.3 Differentiated Services. 4.4 Traffic Policing and Shaping. 4.5 Packet Scheduling. 4.6 Buffer Management. 5 BASICS OF PACKET SWITCHING. 5.1 Fundamental Switching Concept. 5.2 Switch Fabric Classification. 5.3 Buffering Strategy in Switching Fabrics. 5.4 Multiplane Switching and Multistage Switching. 5.5 Performance of Basic Switches. 6 SHARED-MEMORY SWITCHES. 6.1 Linked List Approach. 6.2 Content Addressable Memory Approach. 6.3 Space-Time-Space Approach. 6.4 Scaling the Shared-Memory Switches. 6.5 Multicast Shared-Memory Switches. 7 INPUT-BUFFERED SWITCHES. 7.1 Scheduling in VOQ-Based Switches. 7.2 Maximum Matching. 7.3 Maximal Matching. 7.4 Randomized Matching Algorithms. 7.5 Frame-based Matching. 7.6 Stable Matching with Speedup. 8 BANYAN-BASED SWITCHES. 8.1 Banyan Networks. 8.2 Batcher-Sorting Network. 8.3 Output Contention Resolution Algorithms. 8.4 The Sunshine Switch. 8.5 Deflection Routing. 8.6 Multicast Copy Networks. 9 KNOCKOUT-BASED SWITCHES. 9.1 Single-Stage Knockout Switch. 9.2 Channel Grouping Principle. 9.3 Two-Stage Multicast Output-Buffered ATM Switch (MOBAS). 9.4 Appendix. 10 THE ABACUS SWITCH. 10.1 Basic Architecture. 10.2 Multicast Contention Resolution Algorithm. 10.3 Implementation of Input Port Controller. 10.4 Performance. 10.5 ATM Routing and Concentration (ARC) Chip. 10.6 Enhanced Abacus Switch. 10.7 Abacus Switch for Packet Switching. 11 CROSSPOINT BUFFERED SWITCHES. 11.1 Combined Input and Crosspoint Buffered Switches. 11.2 Combined Input and Crosspoint Buffered Switches with VOQ. 11.3 OCF-OCF: Oldest Cell First Scheduling. 11.4 LQF-RR: Longest Queue First and Round-Robin Scheduling in CIXB-1. 11.5 MCBF: Most Critical Buffer First Scheduling. 12 CLOS-NETWORK SWITCHES. 12.1 Routing Property of Clos Network Switches. 12.2 Looping Algorithm. 12.3 m-Matching Algorithm. 12.4 Euler Partition Algorithm. 12.5 Karol's Algorithm. 12.6 Frame-Based Matching Algorithm for Clos Network (f-MAC). 12.7 Concurrent Matching Algorithm for Clos Network (c-MAC). 12.8 Dual-Level Matching Algorithm for Clos Network (d-MAC). 12.9 The ATLANTA Switch. 12.10 Concurrent Round-Robin Dispatching (CRRD) Scheme. 12.11 The Path Switch. 13 MULTI-PLANE MULTI-STAGE BUFFERED SWITCH. 13.1 TrueWay Switch Architecture. 13.2 Packet Scheduling. 13.3 Stage-To-Stage Flow Control. 13.4 Port-To-Port Flow Control. 13.5 Performance Analysis. 13.6 Prototype. 14 LOAD-BALANCED SWITCHES. 14.1 Birkhoff-Von Neumann Switch. 14.2 Load-Balanced Birkhoff-von Neumann Switches. 14.3 Load-Balanced Birkhoff-von Neumann SwitchesWith FIFO Service. 15 OPTICAL PACKET SWITCHES. 15.1 Opto-Electronic Packet Switches. 15.2 Optoelectronic Packet Switch Case Study I. 15.3 Optoelectronic Packet Switch Case Study II. 15.4 All Optical Packet Switches. 15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case. 15.6 All Optical Packet Switch with Shared Fiber Delay Lines - Three Stage Case. 16 HIGH-SPEED ROUTER CHIP SET. 16.1 Network Processors (NPs). 16.2 Co-Processors for Packet Classification. 16.3 Traffic Management Chips. 16.4 Switching Fabric Chips. INDEX.