SiGe MODFETS: Overview and issues for sub-100 nm gate-length scaling (2004)

Introduction. SiGe MODFETs are attractive devices for future rf and mixed-signal communications applications, due to their greatly enhanced mobility compared to Si MOSFETs. However, MODFETs have been slow to keep pace with the tremendous advances in scaling technology that have allowed Si MOSFETs to maintain performance leadership, both for digital and analog applications. In order to fulfill their promise for enhanced performance, MODFETs must also be aggressively scaled, both laterally and vertically (1). In this paper, I will give an overview of SiGe MODFET technology and describe the materials issues for the future scalability of these devices. MODFET overview. Tensile-strained Si on relaxed SiGe n-MODFETs produce electron mobilities about 4x higher than Si/SiO2 inversion layers at a given carrier density, while compressive-strained Si0.2Ge0.8-channel (Ge-channel) p-MODFETs have mobility enhancements of ~ 6 (10). Recent demonstrations by IBM include 100 nm gate-length Ge-channel p-MODFETs with transconductance, gm, of 488 mS/mm (2), and Si0.2Ge0.8channel p-MODFETs with gm = 377 mS/mm and fmax = 116 GHz (3). More recently, we have fabricated laterallyscaled Si/ Si0.7Ge0.3 n-MODFETs with Lg = 80 nm and source-to-drain spacing of only 300 nm. These devices have record fmax of 210 GHz (4), as shown in Fig. 1. However, gate-length scaling below 80 nm results in reduced voltage gain and higher off-state leakage current, indicating the need for improved scalability. Challenges for MODFET scaling. Numerical simulations of scaled MODFET geometries indicate that quantum well depths < 10 nm, as well as p-well doping and a buried insulator layer are necessary for effective scaling below Lg = 50 nm. For vertical scaling, we have developed a low-temperature UHV-CVD growth process to increase the transient incorporation rate of phosphorous in the supply layer (5). Using this process, Si/Si0.7Ge0.3 layer structures have been grown with quantum well depths of 10 nm and electron mobility and sheet density of 1800 cm/Vs and 2.1 x 10 cm, respectively. For pwell doping, implantation through the quantum well cannot be used as it results in dopant incorporation within the channel that can degrade the mobility. Therefore, we have developed a process where the SiGe buffer layer is implanted with boron, and then the n-MODFET layer structure is regrown on top. As shown in Fig. 2., devices using this improved design have reduced output conductance and off-state leakage compared to devices with no p-well doping (6). We have also demonstrated the growth of MODFET layers structures on thin SGOI substrates. One such layer structure, shown in Fig. 3, has total thickness of only 74 nm, while maintaining room temperature mobility of 1700 cm/Vs. Acknowledgement. This work was supported by DARPA under SPAWAR contract N66001-00-C-8086. References 1. Q. C. Ouyang et al., SISPAD, 2002. 2. S. J. Koester et al., IEEE Elect. Dev. Lett. 21, 110 (2000). 3. S. J. Koester et al., IEEE Elect. Dev. Lett. 22, 92 (2001). 4. S. J. Koester et al., ISTDM, 2004. 5. J. O. Chu et al, Spring MRS, 2004. 6. S. J. Koester et al., to be published. 1 10 100 0 10 20 30 40