All‐Digital Frequency Synthesizer in Deep‐Submicron CMOS (2005)

PREFACE. 1 INTRODUCTION. 1.1 Frequency Synthesis. 1.1.1 Noise in Oscillators. 1.1.2 Frequency Synthesis Techniques. 1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver. 1.2.1 Transmitter. 1.2.2 Receiver. 1.2.3 Toward Direct Transmitter Modulation. 1.3 Frequency Synthesizers for Mobile Communications. 1.3.1 Integer-N PLL Architecture. 1.3.2 Fractional-N PLL Architecture. 1.3.3 Toward an All-Digital PLL Approach. 1.4 Implementation of an RF Synthesizer. 1.4.1 CMOS vs. Traditional RF Process Technologies. 1.4.2 Deep-Submicron CMOS. 1.4.3 Digitally Intensive Approach. 1.4.4 System Integration. 1.4.5 System Integration Challenges for Deep-Submicron CMOS. 2 DIGITALLY CONTROLLED OSCILLATOR. 2.1 Varactor in a Deep-Submicron CMOS Process. 2.2 Fully Digital Control of Oscillating Frequency. 2.3 LC Tank. 2.4 Oscillator Core. 2.5 Open-Loop Narrowband Digital-to-Frequency Conversion. 2.6 Example Implementation. 2.7 Time-Domain Mathematical Model of a DCO. 2.8 Summary. 3 NORMALIZED DCO. 3.1 Oscillator Transfer Function and Gain. 3.2 DCO Gain Estimation. 3.3 DCO Gain Normalization. 3.4 Principle of Synchronously Optimal DCO Tuning Word Retiming. 3.5 Time Dithering of DCO Tuning Input. 3.5.1 Oscillator Tune Time Dithering Principle. 3.5.2 Direct Time Dithering of Tuning Input. 3.5.3 Update Clock Dithering Scheme. 3.6 Implementation of PVT and Acquisition DCO Bits. 3.7 Implementation of Tracking DCO Bits 3.7.1 High-Speed Dithering of Fractional Varactors. 3.7.2 Dynamic Element Matching of Varactors. 3.7.3 DCO Varactor Rearrangement. 3.8 Time-Domain Model. 3.9 Summary. 4 ALL-DIGITAL PHASE-LOCKED LOOP. 4.1 Phase-Domain Operation. 4.2 Reference Clock Retiming. 4.3 Phase Detection. 4.3.1 Difference Mode of ADPLL Operation. 4.3.2 Integer-Domain Operation. 4.4 Modulo Arithmetic of the Reference and Variable Phases. 4.4.1 Variable-Phase Accumulator (PV Block). 4.5 Time-to-Digital Converter. 4.5.1 Frequency Reference Edge Estimation. 4.6 Fractional Error Estimator. 4.6.1 Fractional-Division Ratio Compensation. 4.6.2 TDC Resolution Effect on Estimated Frequency Resolution. 4.6.3 Active Removal of Fractional Spurs Through TDC (Optional). 4.7 Frequency Reference Retiming by a DCO Clock. 4.7.1 Sense Amplifier-Based Flip-Flop. 4.7.2 General Idea of Clock Retiming. 4.7.3 Implementation. 4.7.4 Time-Deferred Calculation of the Variable Phase (Optional). 4.8 Loop Gain Factor. 4.8.1 Phase-Error Dynamic Range. 4.9 Phase-Domain ADPLL Architecture. 4.9.1 Close-in Spurs Due to Injection Pulling. 4.10 PLL Frequency Response. 4.10.1 Conversion Between the s- and z-Domains. 4.11 Noise and Error Sources. 4.11.1 TDC Resolution Effect on Phase Noise. 4.11.2 Phase Noise Due to DCO SD Dithering. 4.12 Type II ADPLL. 4.12.1 PLL Frequency Response of a Type II Loop. 4.13 Higher-Order ADPLL. 4.13.1 PLL Stability Analysis. 4.14 Nonlinear Differential Term of an ADPLL. 4.14.1 Quality Monitoring of an RF Clock. 4.15 DCO Gain Estimation Using a PLL. 4.16 Gear Shifting of PLL Gain. 4.16.1 Autonomous Gear-Shifting Mechanism. 4.16.2 Extended Gear-Shifting Scheme with Zero-Phase Restart. 4.17 Edge Skipping Dithering Scheme (Optional). 4.18 Summary. 5 APPLICATION: ADPLL-BASED TRANSMITTER. 5.1 Direct Frequency Modulation of a DCO. 5.1.1 Discrete-Time Frequency Modulation. 5.1.2 Hybrid of Predictive/Closed PLL Operation. 5.1.3 Effect of FREF/CKR Clock Misalignment. 5.2 Just-in-Time DCO Gain Calculation. 5.3 GFSK Pulse Shaping of Transmitter Data. 5.3.1 Interpolative Filter Operation. 5.4 Power Amplifier. 5.5 Digital Amplitude Modulation. 5.5.1 Discrete Pulse-Slimming Control. 5.5.2 Regulation of Transmitting Power. 5.5.3 Tuning Word Adjustment. 5.5.4 Fully Digital Amplitude Control. 5.6 Going Forward: Polar Transmitter. 5.6.1 Generic Modulator. 5.6.2 Polar TX Realization. 5.7 Summary. 6 BEHAVIORAL MODELING AND SIMULATION. 6.1 Simulation Methodology. 6.2 Digital Blocks. 6.3 Support of Digital Stream Processing. 6.4 Random Number Generator. 6.5 Time-Domain Modeling of DCO Phase Noise. 6.5.1 Modeling Oscillator Jitter. 6.5.2 Modeling Oscillator Wander. 6.5.3 Modeling Oscillator Flicker (1/f ) Noise. 6.5.4 Clock Edge Divider Effects. 6.5.5 VHDL Model Realization of a DCO. 6.5.6 Support of Physical KDCO. 6.6 Modeling Metastability in Flip-Flops. 6.7 Simulation Results. 6.7.1 Time-Domain Simulations. 6.7.2 Frequency-Deviation Simulations. 6.7.3 Phase-Domain Simulations of Transmitters. 6.7.4 Synthesizer Phase-Noise Simulations. 6.8 Summary. 7 IMPLEMENTATION AND EXPERIMENTAL RESULTS. 7.1 DSP and Its RF Interface to DRP. 7.2 Transmitter Core Implementation. 7.3 IC Chip. 7.4 Evaluation Board. 7.5 Measurement Equipment. 7.6 GFSK Transmitter Performance. 7.7 Synthesizer Performance. 7.8 Synthesizer Switching Transients. 7.9 DSP-Driven Modulation. 7.10 Performance Summary. 7.11 Summary. APPENDIX A: SPURS DUE TO DCO SWITCHING. A.1 Spurs Due to DCO Modulation. APPENDIX B: GAUSSIAN PULSE-SHAPING FILTER. APPENDIX C: VHDL SOURCE CODE. C.1 DCO Level 2. C.2 Period-Controlled Oscillator. C.3 Tactical Flip-Flop. C.4 TDC Pseudo-Thermometer Output Decoder. REFERENCES. INDEX.