(Invited) Charge Trapping Type SOI-FinFET Flash Memory (2014)

Y. X. Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, and M. Masahara National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba Central 2, 1-1-1 Umezono, Tsukuba-shi, Ibaraki 305-8568, Japan. Tel: +81-29-861-3417, Fax: +81-29-861-5170, E-mail: yx-liu@aist.go.jp Three-dimensional (3D) fin-channel devices provide excellent short-channel effect (SCE) immunity thanks to the strong controllability of channel potential by the multiple gates. Therefore, the scaled charge trapping (CT) type FinFET flash memories have actively been developed in the past few years (1-3). Very recently, we have also developed floating gate (FG) type SOI-FinFET flash memories with different gate structures (4, 5), and experimentally confirmed that tri-gate (TG) structure shows the better SCE immunity and a larger memory window than double-gate (DG) structure. As a further study, in this work, we fabricate CT type TG-structured SOI-FinFET flash memories with different gate materials and different blocking layer materials, and comparatively investigate their electrical characteristics. 1. Device Fabrication In the device fabrication, we used (110)-oriented SOI wafers, and the Si-fin channels were fabricated by using orientation dependent wet etching (6). To fabricate TG structure, the SiO 2 fin hard-mask layer was removed by RIE. Then, a 4.3-nm-thick tunnel oxide was formed by thermal oxidation, followed by the deposition of a 10-nm-thick nitride (Si 3 N 4 ) layer by LPCVD. As the blocking layer, a 10-nm-thick Al 2 O 3 layer or a 9-nm-thick SiO 2 layer was deposited on the different sample wafers. As the different gate materials, we used n + -poly-Si and PVD-TiN metal. Figure 1(a) shows the SEM image of the fabricated FinFET flash memory with a scaled gate length (L g ) of 26 nm. The cross-sectional STEM images of the fabricated n + -poly-Si gate SONOS, PVD-TiN metal gate MONOS and MANOS with a high-k Al 2 O 3 blocking layer are shown in Figs. 1(b), 1(c) and 1(d), respectively. It is clear that uniform and ultrathin Si-fin channels are successfully fabricated thanks to the orientation dependent wet etching. 2. Gate Material Dependent of Memory Property At first, we measured the initial I d -V g characteristics of the fabricated SONOS and MONOS type FinFET flash memories, and the threshold voltage (V t ) values were evaluated at a constant drain current of I d = 1 mA. It was experimentally found that almost the same sV t is obtained in the SONOS and MONOS devices. This result indicates that V t variation is independent of gate material. Then, we measured P/E characteristics of the fabricated SONOS and MONOS devices. It was found that a larger memory window is obtained in the MONOS devices than the SONOS ones due to the higher work function of PVD-TiN gate than the n + -poly-Si gate as shown in Fig. 2. The higher gate work function is effective to the suppression of electron back tunneling during erase operation [7]. 3. Blocking Layer Dependent of Memory Property To investigate blocking layer material dependence on the electrical characteristics of the CT type FinFET flash memories, we fabricated MONOS and MANOS type devices with different blocking layers of SiO 2 and Al 2 O 3 as mentioned before. The initial I d -V g characteristics of the fabricated MONOS and MANOS type FinFET flash memories with different L g values from 26 to 103 nm were measured and the SCE immunity was systematically evaluated. It was found that the smaller V t roll-off and the better subthreshold slope (S-slope) are observed in the MANOS devices as compared to the MONOS ones due to the high-k effect of Al 2 O 3 in MANOS devices. The P/E characteristics of the fabricated MONOS and MANOS devices were also comparatively investigated. It was found that a significant memory window increment is obtained by introducing an Al 2 O 3 blocking layer instead of the SiO 2 one as shown in Fig. 3. This result is reasonable because a high-k Al 2 O 3 blocking layer is effective to enhance the electric field across the tunnel oxide layer and to reduce the electric field across itself. Therefore, electron back tunneling from the gate to nitride layer is effectively suppressed during erase operation. As a result, a deep erase and a large memory window are obtained in the MANOS devices than the MONOS ones. It was also confirmed that the fabricated MONOS and MANOS devices can operate over 100 k cycles, and can maintain a reasonable memory window after 10 years. In summary, we have investigated the gate material and blocking layer material dependences on the electrical characteristics of the fabricated CT type FinFET flash memories. It was experimentally found that a high work function metal gate and a high-k blocking layer are very useful to the enhancement of memory window. Acknowledgment: This work was supported in part by the Nanotechnology Project of NEDO, Japan. [1] P. Xuan et al., IEDM Tech. Dig., 609 (2003). [2] M. Spechi et al., IEDM Tech. Dig., 1083 (2004). [3] S-K. Sung et al., Symp. VLSI Tech. Dig., 106 (2006). [4] Y. X. Liu et al., Ext. Abstract, SSDM, 985 (2011). [5] T. Kamei et al., IEEE EDL 33 345 (2012). [6] Y. X. Liu et al., IEEE EDL 24 484 (2003). [7] C. H. Lee et al., IEDM Tech. Dig., 613 (2003).