Differential Current-Mode Clock Distribution - eScholarship (2015)

Differential Current-Mode Clock Distribution Riadul Islam, Hany Fahmy, Ping-Yao Lin, Matthew R. Guthaus Department of CE, University of California Santa Cruz, Santa Cruz, CA 95064 {rislam, hfahmy, plin11, mrg}@ucsc.edu Abstract—In this paper, we present a differential current-mode pulsed flip-flop (DCMPFF) for low-power clock distribution using a representative 45nm CMOS technology. Experimental results show that the DCMPFF has 47% faster clock-to-output (CLK- Q) delay than a traditional voltage-mode (VM) pulsed flip-flop. When the DCMPFF is integrated with a differential current- mode clock distribution, the differential technique saves 62% and 17% power compared to a conventional VM and a previous current-mode (CM) clock network, respectively. I. I NTRODUCTION The clock distribution network (CDN) is the most crucial network in synchronous VLSI design, as it is the basic signaling network for every synchronous block and seriously affects overall system power and performance. In terms of signaling type, clocking can be either voltage-mode (VM) or current-mode (CM). Although VM clocking is widely used due to the compatibility with standard VM logic networks, CM clocking can play an important role in low-power systems. CM signaling offers many potential advantages such as higher operating speed [1], low voltage operation [2], and ease of processing [3] compared to VM techniques. Global interconnect power and latency are increasing in tra- ditional VM signaling schemes [4]. Systems-on-chips (SOCs) add more functionality which means chip sizes are roughly constant while wire length increases relative to its planar dimensions. Because of this, the latency of RC lines grow linearly with wire length [4] despite using properly sized repeaters. An immediate solution is to use wide wires, but this results in higher energy per bit because of the large rail- to-rail voltage swing. An alternative signaling scheme such as CM, however, can eliminate transmission line repeaters in addition decreasing necessary voltage swing to significantly reduce power [5]–[8]. We can categorize signaling as differential or non- differential (single-ended). Differential clocks use two wires to send a pair of complementary clock signals. Differential signaling has higher reliability to electromagnetic interference, supply voltage fluctuations, and other sources of common- mode noise compared to single-ended signaling. Differential CM (DCM) signaling has better noise immunity compared to a single-ended CM scheme [7], [9]. However, this comes at the cost of double wiring resources and increase wiring complexity. In this paper, we extend the de novo CM clocking con- cept [5] to implement and analyze the first DCM clock distribution and a new DCM pulsed D-type FF. The clock (CLK) input to the FF is a CM receiver and the data input (D) and output (Q) are VM. In particular, the key contributions of this paper are: • The first demonstration of a differential current-mode clocked FF. • The first demonstration of a symmetric H-tree differential current-mode CDN. • The effective integration of the DCM FF with VM CMOS logic. The rest of the paper is organized as follows: Section II gives a brief overview of some existing signaling schemes. Section III and Section IV propose our DCM FF and CDN, respectively. Section V compares our new FF and CDN with existing schemes. Section VI investigates the noise and reliability of the proposed system. Finally, Section VII concludes the paper. II. O VERVIEW OF E XISTING S IGNALING S CHEMES Unlike traditional buffer-based interconnect signaling, DCM signaling uses a differential CM transmitter (Tx) that sends complementary current pulses at a very low-voltage swing into a pair of interconnect wires. The interconnect is held at roughly the same voltage and is unbuffered. At the receiving end, a differential CM receiver (Rx) senses the two comple- mentary currents and ideally converts them into two differen- tial voltages or a single-ended, full-swing output voltage. A typical non-clock differential CM signaling scheme is shown in Figure 1 [7]. This scheme uses a self-level-converted driver circuit that limits the output voltage swing. Finally, two diode- connected transistor pairs drive the interconnect. However, this kind of driver does not provide sufficient driving capability for large loads and is highly sensitive to noise [10]. This scheme uses a low-swing differential CM Rx circuit [7]. In order to increase the robustness of the design, the Rx uses both a common-gate and a common-source amplifier configuration. However, the Rx consumes a significant amount of static power due to double current-mirror stages. Another previous work used differential current-sensing for the interconnect signaling based on a modified clamped bit-line sense amplifier (MCBLSA) Rx [9]. It utilized the traditional “fanout of four” (FO4) sizing rule for a CMOS buffer chain to design the driver. However, there is no real guideline to design the Tx for different sized interconnects. Moreover, the Tx drives static current into the interconnect while the current is useful during only a fraction of the cycle which results in additional power consumption. The Rx circuit requires an equalizing signal that creates a metastable phase, while the differential input currents break this metastability and help the Rx to produce two complementary outputs.