Investigation of negative capacitance and junctionless MOSFETs for CMOS scaling (2018)

The progress of state-of-art electronics requires CMOS technology to be more powerful and power efficient. CMOS scaling is the way to achieve the goals in the past decades. However, the scaling tends to end. 3D stacking lateral and vertical nanowire MOSFETs have been proposed for further increasing the transistor density. Junctionless nanowire MOSFETs (JNT) are suited for the 3D integration because its source, drain and channel are uniformly doped which eliminates the complex process for junction formation. However, it is difficult to reduce power through the 3D integration. To reduce the power supply voltage, negative capacitance (NC) MOSFETs were proposed to improve the subthreshold swing (SS). In a NC MOSFET, NC effect is utilized to internally amplify the gate voltage, while the NC effect comes from the ferroelectric gate oxide in the device. With the motivations we investigated NC MOSFETs and JNTs, and present the results in the thesis. The fabrication of NC MOSFETs requires CMOS compatible ferroelectrics. We explored different alloys of hafnium oxides with elementary substances. HfY0.03Ox was found to show better ferroelectricity than HfGd0.05Ox and Hf0.5Zr0.5Ox. Besides, Pulsed Laser Deposition (PLD) deposited HfGd0.05Ox was found to show a self-rectifying low current resistive switching. To explore NC MOSFETs, MFMIS (metal-ferroelectric-metal-insulator-semiconductor) MOSFETs with Hf0.5Zr0.5Ox and HfGd0.05Ox ferroelectrics, and MFIS (metal-ferroelectric-insulator-semiconductor) MOSFETs with HfY0.03Ox ferroelectric were fabricated and characterized. In MFMIS MOSFETs, effect of pulse charging of the floating gate was observed instead of the NC effect. The low current resistive switching of the HfGd0.05Ox layer causes a sudden injection of free charge into the floating gate, which improves SS. The ferroelectric polarization switching of the Hf0.5Zr0.5Ox layer quickly induced more charge in the floating gate, which also improves SS. The pulse charging effect was clarified by developing a modified formula of SS. In MFIS MOSFETs, sub-thermal SS was observed in the reverse sweep following a high gate voltage application. The sub-thermal SS extends for 2.5 decades with average SS of 30 mV/dec and minimum SS of 8 mV/dec. The influence of trap charging on the stability of sub-thermal SS was investigated. Based on our analysis the sub-thermal SS was attributed to the transient NC effect. JNTs with the gate length of 80~120 nm and nanowire width of 10 nm were fabricated and characterized. Geometries of gated source drain (GSD), where the gate overlaps with the source drain pads, and source drain extension (SDE), where the gate underlaps with the nanowires, were designed. GSD JNTs show improved on current, SS, DIBL (drain induced barrier lowering) and variability than SDE JNTs. However, GSD JNTs also show larger capacitance. To characterize the tradeoff between capacitance and on current, cutoff frequency (f_t) of the JNTs were characterized. The GSD JNT shows a f_t of 30 GHz compared to the 11 GHz of the SDE JNT. The results indicate that GSD JNT is a competitive alternative to the future MOSFET.