Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al<inf>2</inf>O<inf>3</inf> gate dielectric (2011)

GaN-based HFETs offer a combination of high breakdown field, high current densities, and low on-resistance, making them well-suited for power-switching applications. Normally-off FETs are preferred in power switching applications for circuit simplicity and safety. Recently, a new type of normally-off GaN device has been reported: the hybrid metal-oxide-semiconductor (MOS)- or metal-insulator-semiconductor (MIS)-HFET, consisting of an MOS-type structure under the gate for normally-off operation and an HFET-like structure in the access regions for low on-resistance. Optimization of the insulator-epi interface and insulator quality is critical for this type of device, since the electrons under gate electrode are in direct contact with the gate insulator. Previous reports of hybrid MOS-HFETs used SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or SiN gate dielectrics deposited by plasma-enhanced chemical vapor deposition (PECVD). However, alternative deposition methods such as atomic layer deposition (ALD) have been shown to result in superior thickness control, uniformity, conformality, and film quality, while ALD high-k gate dielectrics such as Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> have generated significant interest for GaN HFETs due to excellent GaN interface quality. In this work, we fabricated normally-off AlGaN/GaN hybrid MOS-HFETs on (111) Si substrates using gate recess etching combined with an ALD Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric for low gate leakage, low on-resistance, and high breakdown voltage. The gate fabrication process was optimized to reduce the trap density associated with the dielectric and eliminate threshold voltage hysteresis, which can result from slow traps in the dielectric or at the dielectric-epi interface. A three-terminal breakdown voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> ) of 1370V was measured at a gate bias of 0 V on a device with a 20 mm gate periphery and a low specific on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) of 9.0 mΩ-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The resulting V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> figure of merit of 208 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is among the highest values reported to-date for normally-off GaN-on-Si HFETs.