Current-Mode Clock Distribution - eScholarship (2014)

Current-Mode Clock Distribution Riadul Islam, Matthew R. Guthaus Department of CE, University of California Santa Cruz, Santa Cruz, CA 95064 {rislam,mrg}@ucsc.edu Abstract—We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip- flop (CMPFF) using a representative 45nm CMOS technology. When the CMPFF is combined with a CM transmitter, the first CM clock distribution network exhibits 45.2% lower average power compared to traditional voltage mode clocks. I. I NTRODUCTION Portable electronic devices require long battery lifetimes which can only be obtained by utilizing low-power compo- nents. Recently, low-power design has become quite critical in synchronous Application Specific Integrated Circuits (ASICs) and System-on-Chips (SOCs) because interconnect in scaled technologies is consuming an increasingly significant amount of power. Researchers have demonstrated that the major consumers of this power are global buses, clock distribution networks (CDNs), and synchronous signals in general [1]. In addition to power, interconnect delay poses a major ob- stacle to high-frequency operation. Technology scaling reduces transistor and local interconnect delay while increasing global interconnect delay [2]. Moreover, conventional CDN structures are becoming increasingly difficult for multi-GHz ICs because skew, jitter, and variability are often proportional to large latencies [3]. Prior to and in early CMOS technologies, current-mode (CM) logic was an attractive high-speed signaling scheme [4]. CM logic, however, consumes significant static power to offer these high speeds. Because of this, standard CMOS voltage- mode (VM) signaling has been the de facto standard logic family for several decades. Low-swing and current-mode signaling, however, are highly attractive solutions to help address the interconnect power and variability problems [1], [2], [5], [6]. Static power is typically more significant than dynamic power in CM sig- naling. However, this static power is often significantly less than VM dynamic power in global CM interconnects while latency is also improved. CM signaling schemes can also offer higher reliability since they are less susceptible to single-event transient upsets due to the absence of buffers with source/drain diffusion areas that can be hit by high-energy particles. Previous CM schemes have been used for long global wires or, more commonly, off-chip signals. Standard logic signals, however, have remained VM to benefit from the low static power of CMOS logic. In our proposed scheme, it is not 978-1-4799-3432-4/14/$31.00 ©2014 IEEE practical to make each individual point-to-point segment of the CDN CM, but the clock signal should still benefit from the power and reliability of CM signaling. Instead, the power savings is maximized by creating a high-fanout symmetric (H- tree) distribution that feeds many CM flip-flop (FF) receivers. Logic signals on the FF receivers retain VM compatibility with low-power CMOS logic in the remainder of the chip. In this paper, we present the first true CM CDN and a new CM pulsed D-type FF where the clock (CLK) input is a CM receiver and the data input (D) and output (Q) are VM. In particular, the key contributions of this paper are: • The first demonstration of a CM clocked FF. • The first demonstration of a symmetric H-tree CM CDN using the CM FF. • The effective integration of the CM FF with VM CMOS logic. The rest of the paper is organized as follows: Section II gives a brief overview of some existing CM signaling schemes. Section III proposes our CM FF and CDN. Section IV com- pares our new FF and CDN with existing schemes. Finally, Section V concludes the paper. II. O VERVIEW OF E XISTING CM S IGNALING S CHEMES In a CM signaling scheme, a transmitter (Tx) utilizes a VM input signal to transmit a current with minimal voltage swing into an interconnect (transmission line), while a receiver (Rx) converts current-to-voltage providing a full swing output volt- age. The representative CM scheme in Figure 1 uses a CMOS inverter as the Tx while the Rx is based on a transimpedance amp [7]. This scheme provides delay improvement over VM schemes, but the Rx voltage swings around a common-mode voltage (V CM ) and any V CM shift would cause a large CDN skew [8]. vdd vdd M3 M1 In M6 vdd M4 X M8 vdd M5 M10 Out M7 M2 vdd M11 M9 Transmitter Interconnect Model Receiver Fig. 1. Previous CM schemes used an expensive transimpedance amp Rx which could result in significant skew due to V CM shift if applied to CDNs [7].