TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches (2018)

As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$Spin$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq1-2875439.gif"/></alternatives></inline-formula></i> - <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$Transfer\; Torque\; Magnetic\; RAM$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq2-2875439.gif"/></alternatives></inline-formula></i> (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, high error rate in STT-MRAM cells due to <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$retention\; failure$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq3-2875439.gif"/></alternatives></inline-formula></i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$write\; failure$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq4-2875439.gif"/></alternatives></inline-formula></i> , and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$read\; disturbance$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq5-2875439.gif"/></alternatives></inline-formula></i> threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly increased in higher temperature, which further affects the reliability of STT-MRAM-based cache memories. The major source of heat generation and temperature increase in STT-MRAM cache memories is write operations, which are managed by cache <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$replacement\; policy$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq6-2875439.gif"/></alternatives></inline-formula></i> . To the best of our knowledge, none of previous studies have attempted to mitigate heat generation and high temperature of STT-MRAM cache memories using replacement policy. In this paper, we first analyze the cache behavior in conventional <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$Least$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq7-2875439.gif"/></alternatives></inline-formula></i> - <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$Recently\; Used$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq8-2875439.gif"/></alternatives></inline-formula></i> (LRU) replacement policy and demonstrate that the majority of consecutive write operations (more than 66 percent) are committed to adjacent cache blocks. These adjacent write operations cause accumulated heat and increased temperature, which significantly increase the cache error rate. To eliminate heat accumulation and the adjacency of consecutive writes, we propose a cache replacement policy, named <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$Thermal$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq9-2875439.gif"/></alternatives></inline-formula></i> - <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$Aware\; Least$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq10-2875439.gif"/></alternatives></inline-formula></i> - <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$Recently\; Written$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq11-2875439.gif"/></alternatives></inline-formula></i> (TA-LRW), to smoothly distribute the generated heat by conducting consecutive write operations in distant cache blocks. TA-LRW guarantees the distance of at least three blocks for each two consecutive write operations in an 8-way associative cache. This distant write scheme reduces the temperature-induced error rate by 94.8 percent, on average, compared with the conventional LRU policy, which results in 6.9x reduction in cache error rate. The implementation cost and complexity of TA-LRW is as low as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$First$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq12-2875439.gif"/></alternatives></inline-formula></i> - <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$In,\; First$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq13-2875439.gif"/></alternatives></inline-formula></i> - <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><inline-formula><tex-math notation="LaTeX">$Out$</tex-math><alternatives><inline-graphic xlink:href="asadi-ieq14-2875439.gif"/></alternatives></inline-formula></i> (FIFO) policy while providing a near-LRU performance, having the advantages of both replacement policies. The significantly reduced error rate is achieved by imposing only 2.3 percent performance overhead compared with the LRU policy.