Verilog HDL: a guide to digital design and synthesis (1996)

PART I. BASIC VERILOG TOPICS. 1. Overview of Digital Design with Verilog HDL. Evolution of Computer Aided Digital Design. Emergence of HDLs. Typical Design Flow. Importance of HDLs. Popularity of Verilog HDL. Trends in HDLs. 2. Hierarchical Modeling Concepts. Design Methodologies. 4-bit Ripple Carry Counter. Modules. Instances. Components of a Simulation. Example. Design Block. Stimulus Block. Summary. Exercises. 3. Basic Concepts. Lexical Conventions. Whitespace. Comments. Operators. Number Specification. Sized numbers. Unsized numbers. X or Z values. Negative numbers. Underscore characters and question marks. Strings. Identifiers and Keywords. Escaped Identifiers. Data Types. Value Set. Nets. Registers. Vectors. Integer , Real, and Time Register Data Types. Integer. Real Time. Arrays. Memories. Parameters. Strings. System Tasks and Compiler Directives. System Tasks. Displaying information. Monitoring information. Stopping and finishing in a simulation. Compiler Directives. 'define. 'include. Summary. Exercises. 4. Modules and Ports. Modules. Ports. List of Ports. Port Declaration. Port Connection Rules. Inputs. Outputs. Inouts. Width matching. Unconnected ports. Example of illegal port connection. Connecting Ports to External Signals. Connecting by ordered list. Connecting ports by name. Hierarchical Names. Summary. Exercises. 5. Gate-Level Modeling. Gate Types. And/Or Gates. Buf/Not Gates. Bufif/notif. Examples. Gate-level multiplexer. 4-bit full adder. Gate Delays. Rise, Fall, and Turn-off Delays. Rise delay. Fall delay. Turn-off delay. Min/Typ/Max Values. Min value. Typ val. Max value. Delay Example. Summary. Exercises. 6. Dataflow Modeling. Continuous Assignments. Implicit Continuous Assignment. Delays. Regular Assignment Delay. Implicit Continuous Assignment Delay. Net Declaration Delay. Expressions, Operators, and Operands. Expressions. Operands. Operators. Operator Types. Arithmetic Operators. Binary operators. Unary operators. Logical Operators. Relational Operators. Equality Operators. Bitwise Operators. Reduction Operators. Shift Operators. Concatenation Operator. Replication Operator. Conditional Operator. Operator Precedence. Examples. 4-to-1 Multiplexer. Method 1: logic equation. Method 2: conditional operator. 4-bit Full Adder. Method 1: dataflow operators. Method 2: full adder with carry lookahead. Ripple Counter. Summary. Exercises. 7. Behavioral Modeling. Structured Procedures. Initial Statement. Always Statement. Procedural Assignments. Blocking assignments. Nonblocking Assignments. Application of nonblocking assignments. Timing Controls. Delay-Based Timing Control. Regular delay control. Intra-assignment delay control. Zero delay control. Event-Based Timing Control. Regular event control. Named event control. Event OR control. Level-Sensitive Timing Control. Conditional Statements. Multiway Branching. Case Statement. Casex, casez Keywords. Loops. While Loop. For Loop. Repeat Loop. Forever loop. Sequential and Parallel Blocks. Block Types. Sequential blocks. Parallel blocks. Special Features of Blocks. Nested blocks. Named blocks. Disabling named blocks. Examples. 4-to-1 Multiplexer. 4-bit Counter. Traffic Signal Controller. Specification. Stimulus. Summary. Exercises. 8. Tasks and Functions. Differences Between Tasks and Functions. Tasks. Task Declaration and Invocation. Task Examples. Use of Input and Output Arguments. Asymmetric Sequence Generator. Functions. Function Declaration and Invocation. Function Examples. Parity calculation. Left/right shifter. Summary. Exercises. 9. Useful Modeling Techniques. Procedural Continuous Assignments. Assign and deassign. Force and release. Force and release on registers. Force and release on nets. Overriding Parameters. Defparam Statement. Module_Instance Parameter Values. Conditional Compilation and Execution. Conditional Compilation. Conditional Execution. Time Scales. Useful System Tasks. File Output. Opening a file. Writing to files. Closing files. Displaying Hierarchy. Strobing. Random Number Generation. Initializing Memory from File. Value Change Dump File. Summary. Exercises. PART II. ADVANCED VERILOG TOPICS. 10. Timing and Delays. Types of Delay Models. Distributed Delay. Lumped Delay. Pin-to-Pin Delays. Path Delay Modeling. Specify Blocks. Inside Specify Blocks. Parallel Connection. Full Connection. Specparam Statements. Conditional Path Delays. Rise, fall, and turn-off delays. Min, max, and typical delays. Handling x transitions. Timing Checks. $setup and $hold checks. $setup task. $hold task. $width Check. Delay Back-Annotation. Summary. Exercises. 11. Switch-Level Modeling. Switch-Modeling Elements. MOS Switches. CMOS Switches. Directional Switches. Power and Ground. Resistive Switches. Delay Specification on Switches. MOS and CMOS switches. Bidirectional pass switches. Specify blocks. Examples. CMOS Nor Gate. 2-to-1 Multiplexer. Simple CMOS Flip-Flop. Summary. Exercises. 12. User-Defined Primitives. UDP Basics. Parts of UDP Definition. UDP Rules. Combinational UDPs. Combinational UDP Definition. State Table Entries. Shorthand Notation for Don't Cares. Instantiating UDP Primitives. Example of a Combinational UDP. Sequential UDPs. Level-Sensitive Sequential UDPs. Edge-Sensitive Sequential UDPs. Example of a Sequential UDP. UDP Table Shorthand Symbols. Guidelines for UDP Design. Summary. Exercises. 13. Programming Language Interface. Uses of PLI. Linking and Invocation of PLI Tasks. Linking PLI Tasks. Linking PLI in Verilog-XL. Linking in VCS. Invoking PLI Tasks. General Flow of PLI Task Addition and Invocation. Internal Data Representation. PLI Library Routines. Access Routines. Mechanics of Access Routines. Types of Access Routines. Examples of Access Routines. Utility Routines. Mechanics of Utility Routines. Types of Utility Routines. Example of Utility Routines. Summary. Exercises. 14. Logic Synthesis with Verilog HDL. What Is Logic Synthesis? Impact of Logic Synthesis. Verilog HDL Synthesis. Verilog Constructs. Verilog Operators. Interpretation of a Few Verilog Constructs. The Assign statement. The if-else statement. The case statement for loops. The Function Statement. Synthesis Design Flow. RTL to Gates. RTL Description. Translation. Unoptimized Intermediate Representation. Logic Optimization. Technology Mapping and Optimization. Technology library. Design constraints. Optimized gate-level description. An Example of RTL-to-Gates. Design Sspecification. RTL description. Technology library. Design constraints. Logic synthesis. Final, Optimized, Gate-Level Description. IC Fabrication. Verification of Gate-Level Netlist. Functional Verification. Timing Verification. Modeling Tips for Logic Synthesis. Verilog Coding Style. Use meaningful names for signals and variables. Avoid mixing positive and negative edge-triggered flip-flops. Use basic building blocks vs. Use continuous assign statements. Instantiate multiplexers vs. Use if-else or case statements. Use parentheses to optimize logic structure. Use arithmetic operators *, /, and % vs. Design building blocks. Be careful with multiple assignments to the same variable. Define if-else or case statements explicitly. Design Partitioning. Horizontal partitioning. Vertical Partitioning. Parallelizing design structure. Design Constraint Specification. Example of Sequential Circuit Synthesis. Design Specification. Circuit Requirements. Finite State Machine (FSM). Verilog Description. Technology Library. Design Constraints. Logic Synthesis. Optimized Gate-Level Netlist. Verification. Summary. Exercises. PART III: APPENDICES. A. Strength Modeling and Advanced Net Definitions. B. List of PLI Routines. C. List of Keywords, System Tasks, and Compiler Directives. D. Formal Syntax Definition. E. Verilog Tidbits. F. Verilog Examples. Index.