Design of a supply- and temperature-invariant capacitive sensor interface for low power applications (2015)

Capacitive sensing systems are widely used for measuring variables such as pressure, humidity, and displacement. Zero static current consumption, as well as the small size of MEMS (Micro-Electro-Mechanical-Systems) capacitive sensors, make them highly suitable for emerging applications such as a biomedical implant or a sensor node. To further increase the level of integration, reduce system size and ease biocompatible packaging, monolithically integrating the capacitive sensor on the same die as the readout circuits is a possible approach. Such sensors are typically fabricated by post-processing the metal layers in a CMOS stack. Monolithic sensors for applications such as absolute pressure sensing are commonly realized in a singe-ended structure to keep the fabrication steps simple. Capacitance-to-digital converters (CDCs) interfacing such sensors need to meet stringent performance specifications. Most importantly, the CDC should operate in an ultra-low power regime. Since the full-scale capacitance change of practical capacitive sensors is limited, the CDC has to achieve sensing resolutions of several femto-farads. In applications such as sensor nodes for automobiles or environmental monitoring, ambient operating conditions such as supply voltage or temperature could vary between individual nodes. As a result, besides the above, such sensor systems also require very low sensitivity to supply and temperature variations to achieve high sensing accuracy. Finally, the overall area of the readout circuit should be as small as possible to reduce the cost. Several existing high-resolution and low-power capacitive sensing systems require assisting circuit blocks such as clock sources, decimation filters and supply regulation/temperature compensation circuits for their operation. Such circuit blocks might either be strictly needed for converting the sensor signal to a digital code or for achieving desirable properties such as supply and temperature insensitivity. In either case, such additional circuit blocks increase the system die area as well as power consumption and hence the cost. Minimizing the need for such redundant blocks is hence another important design objective in chronic sensing systems such as a biomedical implant.&#13;\n &#13;\n This thesis examines the relative strengths of previously proposed capacitance-to-digital conversion schemes in the light of their suitability in a biomedical implant or a sensor node. A time-based architecture that can inherently achieve supply and temperature insensitivity utilizing a ratiometric transfer function is proposed. This architecture is suitable for interfacing a monolithically integrated single-ended capacitive sensor that has matched supply and temperature characteristics with another on-chip fixed reference capacitor. The proposed CDC uses two matched relaxation oscillators converting each capacitance to an equivalent time-period. A programmable-digital-converter evaluates a digital code equivalent to a scaled ratio between the capacitors. The proposed CDC is suitable for a stand-alone operation requiring no redundant circuit blocks such as regulation/reference circuits. Being a mostly digital architecture, the proposed CDC can operate in an ultra-low supply voltage. Due to the time-based architecture, the sensing resolution could be easily traded off with measurement time. Given the possibility of duty-cycling, this could be translated to system-level energy savings. Although the proposed CDC is best suited for interfacing monolithic sensors, the concept is shown using two matched external programmable capacitors as sensor and reference capacitors. In capacitive sensing systems, RC relaxation oscillators act as front-end circuits that convert the capacitances to equivalent time periods. As the performance of a sensor interface is limited by that of the front-end circuit, high-performance relaxation oscillators are particularly important. In particular, the jitter performance of such relaxation oscillators determines the sensing resolution of the CDC. This thesis investigates methods to minimize the jitter and proposes a relaxation oscillator architecture with the lowest period jitter among previously proposed relaxation oscillators. The period jitter of a relaxation oscillator is directly proportional to the input referred noise of its comparator and inversely proportional to the slope of the timing waveform at the instant of threshold crossing. The proposed oscillator employs a swing-boosting technique to increase the swing of the timing capacitance voltage to twice the supply voltage level. Furthermore, the proposed relaxation oscillator uses an inverter based comparator that consumes only dynamic current when the inputs reach the vicinity of the threshold voltages. Such a comparator helps in minimizing the noise while optimizing the power consumption of the comparator. Furthermore, the comparator uses a replica biasing scheme to make the inverter thresholds more resilient to changes arising from process variation. The proposed oscillator achieves the best figure-of-merit among previously proposed relaxation oscillators. The oscillator is presented as a differential topology. However, a single ended version of the proposed oscillator could be used for the purpose of interfacing a single ended capacitive sensor as a part of the overall ratiometric CDC presented.