Verification of Single-Pulse Avalanche Failure Mechanism for Double-Trench SiC Power MOSFETs (2020)

The failure mechanism of double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under single-pulse avalanche stress is verified. Instead of the widely reported burning out failure mechanism for planar-gate devices, double-trench SiC power MOSFETs suffer from a totally different failure mechanism, as they can only endure a much lower maximum single-pulse avalanche energy (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">as</sub> ). It is found that during the avalanche process, obvious gate leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) appears, which is resulted from the high impact ionization rate and high electric field along the gate trench bottom oxide interface, especially the trench corners. The I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> continuously grows along with the increase in the peak load current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> peak</sub> ), eventually leading to the breakdown of the trench bottom gate oxide under avalanche status. By increasing the value of gate resistor (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> raises the gate-source voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> gs</sub> ) during the avalanche process, forcing the channel region in an inversion state. Part of the avalanche current is then diverted into the forward conductive current, changing the failure mode from breakdown of the gate oxide to burning out of the entire device. Moreover, the influence of different avalanche stress conditions, including the di/dt and the ambient temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> ), on the single-pulse avalanche endurance capability of double-trench SiC power MOSFETs is investigated. All the samples express a similar failure phenomenon. The higher the di/dt is, the shorter the avalanche time the device can endure. This is because the higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">peak</sub> results in a higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> during the avalanche process, leading to early failure of the gate oxide. However, the T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> rarely influences the E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> as</sub> of the device, indicating that the single-pulse avalanche-induced failure of double-trench SiC power MOSFETs has little business with the melting of the lattice or package, demonstrating the correctness of the failure mechanism proposed in this article.