A 3.5ns, 2Kx9 Self Timed SRAM (1990)

A self-timed SRAM of 18K bits density has been developed which has several value added features for specialty computer CPU applications. The part was developed on the National BiCMOS 111 process, that has been previously 1 described . This part has an access time of 3.5ns and a cycle time of less than access. All inputs are registered with respect to the clock positive edge, read and write operations are internally self timed. The output latch self loads internally, thus insuring that data is valid for the entire cycle. The external timing facilitates system usage. The part is formed using a self-timed synchronous architecture. An innovative circuit method called (patent pending) that allows a CMOS technology to achieve gate delays roughly equivalent with ECL gate delays was employed. Gate delays of 105 ps have been observed versus 145 ps for a regular CMOS Inverter. SUMMARY The part has been organized as a 2Kx9, an attractive organization for Cache, Tag, and other CPU board level RAMS. Figure 1 shows the block diagram for the part. The cycle begins with clock input (CLK) going high and complementary clock input (CLKB) going low. All of the other inputs are registered from these edges, thus dramatically easing the system designers' constraints. CLK & CLKB, are buffered up through an all nchannel amplifier, (figure 2, transistors M1 - M6). It functions as a level translator, high gain and high common mode rejection amplifier with minimum delay. The amplified signal is then converted to CMOS levels (M7 - M10). The CMOS signal is then fed into a pulse generator (Mil - M20). This signal is further amplified to create the lnlat signal (latch input registers) and set the cycle in motion. The ECL Address, Data, and Control signals are brought in, registered and buffered up to CMOS levels by the Input Buffer (figure 3). Transistors Q1 and Q2 serve to translate the input signal down from the Vcc rail and to isolate the input pin from the internal latch. Current sources I1 and 12 serve to establish the voltage levels. The internal latch is comprised of transistors M3 - M6. Transistors M7 and M8 respond to the lnlat signal from the clock circuit to set the internal latch. Transistors M9 - M12 serve as another level of gain before the signal is fed to M 13 - M 16 for driving to the predecoders. The address buffer output signals are then fed to the predecoders, 1 of 4 (or 1 of 2) followed by a 1 of 16 (or a 1 of 8). These circuits are designed in post-charge logic to give them minimum delay. Post-charge logic is described as a one shot, resetting itself in preparation for the next cycle. The basic postcharge decoder will be explained later in this paper. The predecoded signals are then sent to the row decoder which drives 1 of 128 rows. The column predecode circuits are identical to those of the row decoder. The output of the 1 of 16 drives a gain stage which drives the column decoder, 9 of 144 columns are selected for output. The bit lines are normally tied hard to Vcc by transistors M5-M7 and are released for sensing by signal ColSel (figure 4). The bit is sensed by a regenerative, clocked sense amplifier made up of transistors M12-Ml4 and latched by the SenSel signal derived from the ColSel signal. The gain stages beyond the senseamp are post-charge logic stages. The output driver converts the CMOS level signals DO and DOB back to an ECL signal for driving the outside world, (figure 5). Transistors (33-06 form a voltage reference circuit that set VOH and VOL. Depending on the state of DO and DOB, one CH2885-2/90/0000- 0049 $1 .OO 01 990 IEEE