A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration (2014)

A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> ) of 1.8V, and a leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LK</sub> ) below 1 fA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively, with their corresponding I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LK</sub> below 0.48, 0.19 and 0.09 fAmp/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Process reliability related defect density (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> ) of the interposer HK-MiM is as low as 0.095% cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> as judged by a 10 years lifetime breakdown voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bd</sub> ) criterion at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> =3.2V. This low D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> within the Si interposer. Moreover, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bd</sub> tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LK</sub> & V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bd</sub> tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.