8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range (2015)

System-on-chip (SoC) processor cores experience high-frequency supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) droops when the current in the power delivery network abruptly changes in response to workload variations, thus degrading performance and energy efficiency. Previous adaptive circuit techniques aim to reduce the effects of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> droops by sensing the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> variation with an on-die monitor and adjusting the clock frequency (F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> ) [1-2] or by directly modulating the phase-locked loop (PLL) clock output with changes in the core V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> to implicitly adapt F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> [3]. The adaptive response time and complex analog circuits limit the benefits of these techniques for a wide range of F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> operating conditions. The adaptive clock distribution (ACD) [4-5] exploits the path clock-data delay compensation during a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> droop to enable a sufficient response time to proactively adapt F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> . Although the ACD mitigates the impact of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> droops on performance and energy efficiency, the previous designs require extensive post-silicon tester calibration of the dynamic variation monitor (DVM) to accurately detect the onset of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> droop. Since SoC cores operate across a wide range of F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> , V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , temperature, and process conditions, the DVM requires a unique calibration for each operating point, thus resulting in prohibitively expensive test time for high-volume products. This paper describes an ACD design in a 16nm [6] test chip with an auto-calibration circuit to enable in-field, low-latency tuning of the DVM across a wide range of operating conditions to maximize the ACD benefits, while eliminating the costly overhead from tester calibration.