Analysis of Thermal Degradation in Oxide Thin Film Transistors (2014)

Amorphous InGaZnO (IGZO) thin-film has attracted considerable attention as a transparent amorphous oxide semiconductor (TAOS), which enables the fabrication of a thin-film transistor (TFT) with high electrical properties on a large-scale substrate at very low temperature. TAOS TFT is expected for a driver element as active matrix organic light emitting diode and liquid crystal displays with a flexibility of display designs, such as system on panel and transparent display. To realize these displays, reliability is one of the most important issues. Recently, many researchers have focused on stability under electrical stress, illumination and atmospheric condition. However, Joule heating effect of the TFTs might be a significant problem because they are fabricated on low-thermal-conductivity substrates observed similarly to low-temperature-processed polycrystalline silicon TFTs. However, the degradation phenomenon induced by Joule heating of oxide TFT has not been investigated compared with that of Si TFTs. To analyze the degradation mechanism, various gate and drain voltages were applied to ITZO TFTs as electric stress. The surface temperature of a TFT under operation was analyzed using a thermal imaging system using an InSb infrared detector with a 256 × 256 pixel CCD. The detector was sensitive to wavelengths of 3 - 5 μm. The sample stage was kept at 50°C to compensate for the effect of various materials of different emissivities. This compensation enables us to measure the temperature of the sample in the range of 50 – 250°C with an accuracy of 0.1 K. The spatial resolution depends on the magnification and decreases to approximately 3 μm. We studied the thermal distribution depending on channel scale and bias voltages. Asymmetrical local heating at drain edge was observed at higher drain voltage. Furthermore, under accelerated bias voltage stress to detect self-heating effect with V DS = V GS = 20 V for 10000 s, change of electrical properties and heating temperature was observed with a passage of stress time. In the early period, the threshold voltage ( V th ) shifted to the positive direction and heating temperature decreased. Meanwhile, the positive shift was saturated in a short stress time, subsequently the negative shift and temperature increase were observed. In this study, we discuss the degradation mechanism focusing on impact ionization and carrier trapping phenomena at interface by heating effect. Further study is required to demonstrate the effectiveness of the model. In order to validate that model, we performed additional experiment and device simulation ATLAS. To analyze the above result theoretically, we performed device simulation focusing on electric filed and Joule heating distributions. By using this output curve obtained by the simulation, distribution of electric field and Joule heating effect were analyzed for the bias condition used for electric stress test. At higher drain voltage, Joule heating was observed clearly, which corresponds well to the experimental result. Furthermore, we found that vertically high electric field was observed at drain edge under V DS = 30 V. To discuss the relationship between Joule heating and high electric field, we investigated the band structure. B oth conduction and valence band bend very rapidly close to the drain edge. These band bending suggest the possibility of impact ionization. In particular, band bending is sharp under V DS = 30 V, so that higher impact ionization can be estimated. Therefore, we consider that the cause of degradation observed in stress test attributed to the generation of electron and hole pair and their carrier trapping due to impact ionization.