Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits (1978)

Modern large-scale-integrated (LSI) digital circuit design philosophy is approaching a technological crossroad. Improvements in photomasking and surface processing technologies have significantly improved the yield on very large (>40,000 mil2, >5,000 devices) chips. But even with these contributions, a majority of LSI chip designs are limited in their complexity by the number of metal signal lines that must be interconnected on the semi-conductor surface, not by the number of devices. Will intensive efforts in device minimization and processing techniques provide significant returns in terms of increased circuit complexity? Or should alternatives in the coding and processing of digital electrical signals be explored? Much theoretical work has been done on multivalued threshold logic (e.g. [1-4]), and until recently few LSI circuit oriented realizations of these ideas have been reported [5-8]. Multivalued logic provides the attractive feature of an additional one, two or more logical values that each switching variable may assume. Standard binary signals assume only logical values ZERO and ONE, while four-valued logic may assume values ZERO, ONE TWO or THREE. Thus, use of four-valued logic may double the amount of information carried by each signal line. In a metal limited design, this savings could be extremely important. Four-valued threshold logic circuits can provide a 50% reduction in the device count in some digital signal processing applications.Four-valued threshold logic circuit realizations are most easily accomplished in either a current-steering logic similar to emitter-coupled logic (ECL) or with the current steering capabilities of integrated injection logic (I2L). Logical variables are developed as integer multiples of an easily duplicated reference amount of current. These currents are summed, differences, and duplicated to produce the desired logical results. In the ECL related technique, ECL compatible outputs are generated, while TTL compatible outputs can be generated in the I2L approach.One important signal processing application for four-valued threshold logic is in digital counters and adders. A binary parallel counter is a multiple input circuit that counts the number of its inputs that are in a given state. This function can be performed with four-valued threshold logic full adder (QFA) circuits . A QFA accepts two base-four inputs A and B, and a binary carry input Ci and produces a two-quaternary-digit, base-four, output word CS, where C is the most significant digit. The table below summarizes implementations of binary parallel counters with binary full adders and QFA's. In general, 50% fewer intermediate signal lines (excludes binary inputs and outputs) and 50% fewer transistors and resistors are required.Most applications of parallel counters are within the framework of another function; e.g. parallel multipliers. A parallel counter is important in the development of an LSI digital output correlator, e.g. [9]. This correlator compared bit-by-bit two binary words and produces a binary count of the number of bits in agreement. Use of a QFA parallel counter in this application would reduce the total device count and chip area by about 14% and 18%, respectively.