Simulation with 3K time points of the waveforms inside a Phase and Frequency Detector of the bang-bang type. The detector is driven by one clock (input +) at 1 GHz and by a clock (input -) at 1GHz-398 ppm. After 1850 simulation samples, the input clock becomes noisy with the addition of a sinusoidal phase jitter of 0.3 rad of amplitude and of 10e+10 rad/sec of angular frequency. Note the typical pattern of the slips of the two Phase Detectors driven by I(lead) and Q(lag) that are orthogonal square waves. The wave of the Q(lag) detector seems to lead the other: this is because the frequency difference is negative. The PFD is wired so that its output is low if the negative input receives a lower frequency than the positive input, and viceversa.