Butt joint in top layer for low loss waveguides A. Volpini,1,2 A. Millan-Mejia,2 S. Klein,2 L. Augustin2 1Universidade de Vigo, Dep. of Telecom Eng, 36310 Vigo, Pontevedra, España 2 Smart Photonics, R&D department, Horsten 1, 5612 AX Eindhoven We present a new integration scheme for the InP based platform to monolithically integrated low-loss passive waveguides in the SMART photonics integrated circuits (PICs) platform. This method consists of performing a butt joint in the top layer of our wafers. This allows to have two different top claddings on the same wafer, one heavily doped optimized for active and one undoped optimized for passive elements. In PICs doping is necessary to allow electrical contacting of active components such as lasers, photodetectors and modulators. The dopant elements are known to cause intraband optical absorption with optical losses of more than 3dB/cm being common. Our simulations suggest losses as low as 0.6 dB/cm with the optimized top claddings. We have experimentally verified the differences in losses between the different layerstacks. We fabricated four wafers and measured the losses: one wafer has a standard layerstack, two wafers the new integration scheme and a reference wafer with no top cladding doping. We measured losses associated to three different widths of deep waveguides. We discuss the results and propose improvements. Introduction Low losses waveguides are necessary for a variety of applications such as sensing [1], delay lines [2] and many others. Usually, when extremely low optical loss values are necessary, silicon nitride (SiN) based platforms are the one performing better with losses as low as 0.03dB/cm [3]. However, they present a main drawback: active components such as lasers, amplifiers, detectors and electro-optical modulators are not available in such platforms, limiting their potential. InP based platform is an alternative, it is a direct bandgap semiconductor which allows the monolithic integration of active and passive components on the same chip. This eliminates the requirement for an external light source making the final product potentially lighter, smaller and cheaper. Compared to SiN however, losses are in the range of 2-4 dB/cm [4]. In this platform we can identify three major sources of optical loss: intrinsic losses, surface roughness and doping loss. Intrinsic loss[5] are connected to the refractive index of InP, not much can be done to control this contribution, but it is important to have a defect free material to avoid to make this losses even higher. With different lithography and etching techniques, waveguide wall roughness can be made smooth (or even removed with wet etch techniques) thus reducing roughness as source of loss. The third source is the presence of doped material. This mechanism is analyzed below and it is the main source of losses we focus on this paper. Smart Platform Starting from a InP substrate, different layers of InP, InGaAsP and InGaAs are grown. These layers have different optoelectronic properties and form the so called layerstack [4]. Trough different fabrication steps, optical elements such as laser, detectors, modulators and waveguides are pattered in the chip creating a PIC. We can identify three main layers: the substrate, the core and the top layer. The core layer is where the optical mode propagates and it is made of the quaternary alloy InGaAsP. The concentration ratio of the four elements controls the semiconductor bandgap and refractive index and allows for light generation and guiding at chip level. The top layer serves has a spacer between metal connections and the core layer that would otherwise suffer from high loss. A trade off in the layerstack is needed to make all the components available, mostly between active and passive devices. One of the most important is the dopant concentration in the cladding layers. In the next section we explain how this doping is necessary for good electrical