ECCS # 2203625: CDS&E: Machine-Learning-Driven Methods for Multiobjective and Inverse Design of van-der-Waals-Material-Based Devices PI: Jing Guo (email:guoj@ufl.edu) Department of ECE, University of Florida, Gainesville, FL, 32611 This work was supported by National Science Foundation Award # 2203625 Introduction Simulation of vdW-Material-Based FTJ Simulate Ferroelectric Tunnel Junction for Memory Simulation Tool Development & Deployment Conclusion Multi-Objective Design Results Background: Why van der Waals (vdW) Semiconductors for Electronic Devices? • Ultrathin thickness ductors preferred for excellent device scalability • A wide range of material choices with desired properties for device applications • Vertical vdW stacking to flexibly form heterojunctions (HJs) • Good carrier transport, optoelectronic, and mechanical properties • New device functionalities derived from unique material and HJ properties Acknowledgement • Machine learning methods explored for nanoscale transistor and memory device simulations. • ML assisted approach speeds up quantum transpot simulation of ferroelectric tunnel junction devices (for memory applications) • vdW heterojunction based FTJ can promise extradinarily large ON-OFF ratio • Tellurium NW array FETs promises significantly reduced leakage compared to CNT array FETs, which suffers from ambipolar transport • Multi-objective design optimizes multiple design targets, including speed, power, and device variations simultaneously and automatically. • Online simulation tools on nanoscale transistors based on 2D semiconductors deployed. ML TB Simlauton of Transistors based on vdW Materials Multi-Objective Design of vdW 2D FETs Device Performance Assessment https://nanohub.org/resources/2dfets 2DFET Tool - 2DFET is an online toll simulating the device characteristics of field-effect transistors based on 2D materials. - Model nanoscale transistors based on a wide variety of vdW 2D semiconductors by using a semi-analytical model. - Supporting >1,100 users since its depolymnet on nanoHub . Nanosheet FET Tool https://nanohub.org/resources/nanosheetfet This tool performs rigorous self-consistent quantum transport device simulations of vdW nanosheet FETs Desai et al., Science, 354, 99 (2016) 1nm-Gate-Length Transistor Memory Device: Ultrahigh On-OFF Ratio Wu et al. Nature Electronics, 3, 466 (2020) Objective 1 Objective 2 Optimal Pareto Front Design Target Objectiv e Domain Pareto front Parameter 1 Parameter 2 Design Parameter Space Two methods explored: • Non-dominated Sorting Genetic Algorithm (NSGA) • Pareto Active Learning (PAL) Simulation/evaluation Generation of new designs by using ML algorithms: • ML-Guided method automatically identifies the Pareto surface for three design targets (delay, leakage power, and variation • The method renders the distribution of the optimal device design parameters. • Pareto active learning (PAL) and non-dominated sorting genetic algorithms (NSGA) can achieve comparable results to identify the Pareto front. • PAL significantly faster than NSGA. Two design objectives: Delay and Dynamic Power: Three design objectives: Leakage, Variability, and Delay: T. Wu and J. Guo, IEEE Trans. Electron Devices, 68, 5476 (2021) Devlelop Machine Learning Methods for 2D-Material-Based Device, to: • Speed up demanding quantum transport device simulations • Develop multi-objective device design capacbilites • Delop an inverse device design framework Design goals of ferroelectric tunnel junction (FTJ) for non-volatile memory - Large tunneling resistance ratio between two states. - Large on-state current Metal 2 HZO or other FE Metal 1 Conventional FTJ: - limited barrier modulation - Scalability of tunnel layer 2D-material FTJ: - Graphene contact - 2D FE tunnel layer N. Yang, …, H. Wang, J. Guo, IEDM, p. 55 (2020) § FTJ devices show I-V characteristics in agreement with experiment § Unprecedently large tunnel electroresistance (TER) ratio >6×107 1 2010 2015 2020 10 0 10 1 10 2 10 3 10 4