Mercury Target Neutrinos 24m Baseline Iron Shielding Proton Beam π+ μ+νμ μ+ e+νμ νe K+ μ+νμ 17 Tons GdLS 30 Tons LS Veto IBD νe+p → e++n n+Gd → Gd+γ Prompt Delayed,𝜏≈28μs 96 inward looking 24 outward looking 120 10-inch PMTS J A N U S J A N U S J A N U S J A N U S J A N U S F O N T U S Large PMT Pulse Single PE PMT Pulse Custom Analog Proto-board TI ADS54J66 ADC Eval Board Analog & ADC Proto-board Xilinx Kintex Ultrascale Dev Board JANUS PCB design is complete JANUS : 32 Channel DAQ Board ... ... ATCA Backplane Global Bus PMT Data (Ethernet) Energy Sum (Serial 10Gbps) SFP+ Global Trigger Energy Sum (Serial 10Gbps) SFP+ PMT Data (Ethernet) Process Data and Triggers Digital (Serial) FPGA 1 Xilinx Kintex Ultrascale JESD204B FPGA 0 Xilinx Kintex Ultrascale 32 PMT Channels Analog Differential Signals Condition the PMT Signals Digitize the Waveforms ADC 7 500 MHz, 14-bit ADC 0 500 MHz, 14-bit ADC 3 500 MHz, 14-bit Frontend Analog Transceiver Transceiver Global Clock ADC 4 500 MHz, 14-bit FONTUS : Trigger Board FPGA Xilinx Kintex Ultrascale ATCA Backplane Energy Sum (Serial 10Gbps) Clock Front Panel Beam Signal External Triggers Global Trigger Global Bus Trigger Info (Ethernet) J A N U S J A N U S J A N U S J A N U S J A N U S F O N T U S 104 105 106 107 Neutrino Flux (Arb.) µ π K -600 -400 -200 0 200 400 600 800 1000 Time (ns) 0 20 Current (A) ×25Hz Beam Pulses Process Trigger Data to Produce Triggers Proto-board that can emulate both JANUS & FONTUS functionality is being produced. Pending testing and production of the final JANUS & FONTUS PCBs commissioning of the DAQ will begin Fall 2020. Once this design has been sucessfully deployed for JSNS2 we hope to demonstrate this as a "one size fits all" DAQ solution for medium- scale liquid scintillator detectors. The 14-bit resolution & large dynamic range provides sensitivity to high energy neutrinos, e.g. KDAR neutrinos, without losing single- PE sensitivity. The upgrade DAQ will be hosted within an ATCA shelf with 5 DAQ boards (JANUS) and one trigger board (FONTUS). Design can be expanded to fit possible future needs. Tests of the analog circuitry have demonstrated its ability to produce a differential copy of the input with excellent signal integrity. The FPGA based trigger allows event selection based on known event timing relations and the flexibility to design trigger logic specific to the physics of interest. Expected data readout rate is 1 Gbps per FPGA. The electronics will need to trigger based upon timing signals from the beam facility as well as event energy and timing conditions. Our system will leverage modern FPGA and telecom electronics to meet these requirements. The J-PARC Sterile Neutrino Search at the J-PARC Spallation Neutron Source (JSNS2) began taking data with DAQ electronics donated by the Double Chooz experiment. The Double Chooz electronics, however, were not designed for a beam based experiment and are not sensitive across the entire energy range of interest for JSNS2. I have been working, as part of a team, to develop upgrade electronics that will be better suited to JSNS2's energy and timing requirements. The upgrade electronics will enhance our physics capabilities by providing a excellent efficiency and resolution over a large energy range. Firmware testing and development underway using commercial and custom bench-top electronics. Beam Neutrino Production: Spectrum & Timing JSNS2 Detector & Primary Physics Interactions The Benefit of 14-bit Resolution The Design and Development of the JSNS2 DAQ Upgrade Eric Marzec (marzece@umich.edu) For the JSNS2 Collaboration JSNS2 Design Development