Elements: Software Infrastructure for Programming and Architectural Exploration of Neuromorphic Computing Systems PI: Naga Kandasamy, Co-PI: Anup Das Award #: 2209745 Computing platforms currently used to run machine-learning tasks have high carbon footprint. Neuromorphic computing systems, which mimic biological neurons and synapses can implement these tasks in a highly energy-efficient fashion. Major challenges for neuromorphic computing lie in its adoption by users and from a system developer's perspective, to cope with faster time-to-market pressure for new neuromorphic chip designs. Our project develops a software infrastructure called NeuroXplorer, which allows for Spiking Neural Networks (SNNs) to be mapped onto neuromorphic hardware in the most efficient way possible. It provides: • Compiler backends to generate executable code for neuromorphic chips from a high-level specification of the machine-learning task. • Mapping and synthesis tools to execute machine-learning tasks on novel neuromorphic architectures built using FPGA. • High-performance software for hardware/software design-space exploration of new neuromorphic architectures. Project Motivation NeuroXplorer Infrastructure • Design optimization engine that can incorporate hardware design metrics such as energy, latency, throughput, and reliability, as well as SNN-oriented metrics such as ISI distortion and spike disorder. • System software stack that facilitates mapping of SNN-based applications to different neuromorphic platforms. • Cycle-accurate model of neuromorphic hardware utilizing a generalized template, which can be configured with hardware- and technology-specific details from manufacturers of neuromorphic systems. • Design-space exploration using data-flow models to represent machine- learning tasks executing on neuromorphic hardware which allows key performance metrics such as accuracy and power consumption cost to be estimated early during the design process. • Analysis of different technological alternatives for neuron and synapse circuits, and impact of scaling on neuromorphic hardware, facilitating optimization of key system-level design metrics. FPGAs can serve as accelerators for SNNs, for rapid prototyping, and as the deployment platform. QUANTISENC, a quantized spike-enabled neural core design software in Verilog, enables design and synthesis of SNNs on FPGAs. SONIC: Software-Designed Hardware Methodology SONIC (SOftware-defined NeuromorphIC) is an open-source software-defined hardware design methodology to make neuromorphic computing more accessible. Enables the user to define and train an SNN model using a high-level language such as Python, generate the corresponding register transfer level (RTL) description of the hardware, and create the hardware-software interface to improve programmability when the RTL is prototyped on FPGA and ASIC. • Neuromorphic hardware is configurable via software. • Modular System Verilog testbench to verify QUANTISENC for different learning tasks and datasets. • SONIC is available at github.com/drexel-DISCO/SONIC.git under the MIT license. Contact Information Naga Kandasamy kandasamy@drexel.edu Anup Das anup.das@drexel.edu QUANTISENC: Modular Neuromorphic Hardware Design We have started to integrate SONIC into existing courses to teach neuromorphic computing. • User specifies values for various hyperparameters in the SNN: number of layers, number of spiking neurons per layer, neuronal weights, and internal parameters of the neuron (resting membrane potential, threshold potential, and refractory period). • QUANTISENC allows setting separate quantization and precision policies for synaptic weights and internal state variables to co-optimize area, power, latency, and throughput to achieve a target performance. • Python script generates configuration file for design synthesis along with testbench to simulate/verify functionality of the FPGA design. • Available at github.com/drexel-DISCO/quantisenc-public.git under