## 3 Candidate Generation in Parallel Decoding of Rate-1 Nodes
### Candidate Generation Based on Partially Ordered Candidate Sets
Simulations of the post-PAR netlists are executed for verification and the generation of the stimuli for power estimation. Power numbers are calculated with back-annotated wiring data at an SNR of \(E_{b}/N_{0}=4\) dB. A constraint of 64 Gbit/s coded throughput was set for all designs. A quantization of 6 bit is used for channel values and internal LLRs, PMs are quantized with 8 bit. Table 2 shows the post-PAR results of decoder implementations with \(N=128\), \(R=1/2\) and \(L\in\{2,4,8\}\). ExPOS-Fast-SSCL and PO-Fast-SSCL decoder implementations are presented in comparison with the implementations of [12]. As described in Section 4.1, for \(L=2\), PO- and ExPOS-based candidate generation is equal. Thus, only one decoder implementation with \(L=2\) is listed as a ExPOS-Fast-SSCL decoder in Table 2. The parameters \(S_{\text{Rate-1}}\) and \(k_{c}\) for the ExPOS-Fast-SSCL decoders were determined according to Algorithm 2. The values for \(S_{\text{Rate-1}}\) in the columns of PO-Fast-SSCL decoders and [12] equal \(L-1\), related to (4). The PO-Fast-SSCL and ExPOS-Fast-SSCL decoder architectures with \(L\in\{2,4\}\) correspond exactly to the ones presented in [12], where the sub-architectures of the Rate-1 nodes with their dedicated sorters were replaced. For the ExPOS-Fast-SSCL decoders with \(L=8\), the restriction \(N_{v,\text{Rate-1 max}}=4\) for Rate-1 nodes from [12] can be dropped, since the number of generated candidates is bounded to \(L_{\text{out}}=15\) (see (35) and Table 1). Thus, the effect of enhanced tree pruning additionally improves the implementation results. This also holds for the PO-Fast-SSCL decoder implementation with \(L=8\), which exhibits a maximal \(L_{\text{out}}=59\) for Rate-1 nodes according to (30). It can be observed that PO-Fast-SSCL and ExPOS-Fast-SSCL decoding improve the area efficiency and energy efficiency of the decoder implementations. With increasing list size, the impact increases. Since ExPOS-Fast-SSCL decoding exhibits the largest improvements with a negligible error-correction performance loss, we focus on these decoders. The area efficiency for \(L\in\{2,4,8\}\) increases by \(\{4.2\%,10.6\%,158.8\%\}\), respectively. The according energy efficiency values are improved by \(\{9.0\%,11.1\%,62.5\%\}\). \begin{table}
\begin{tabular}{c c c c c c c c c c c c} \hline \hline \multirow{2}{*}{\(L\)} & \multirow{2}{*}{\(S_{\text{Rate-1}}\)} & \multirow{2}{*}{\(k_{c}\)} & \multirow{2}{*}{\( \begin{array}{c}\textbf{Number}\\ \textbf{of Paths}\end{array} \)} & \multicolumn{3}{c}{\( \begin{array}{c}\textbf{Reduction}\\ \textbf{of Paths}\end{array} \)} & \multicolumn{3}{c}{\( \begin{array}{c}\textbf{Number of}\\ \textbf{Conparators}\end{array} \)} & \multicolumn{3}{c}{\( \begin{array}{c}\textbf{Reduction of}\\ \textbf{Conparators}\end{array} \)} \\  & & & & & & & & & & & & & & & & \\ \cline{2-12}  & & & & & & & & & & & & & &



The layouts of the three decoders with \(L=8\) presented in Table 2 are shown in Figure 12. The scaling of the figures corresponds to the area values of the decoders. The coloring is consistent for all three layouts: Computational kernels (f-, g- and h-functions, Rate-0, REP and SPC nodes, their dedicated sorters) are represented by different colors. The delay line memory and CRC update functions are colored in black and white, respectively. Rate-1 nodes and their dedicated sorters are highlighted in dark-red and orange-red, respectively. The number of Rate-1 nodes and their dedicated sorters decreases comparing the implementation of [12] (Figure 12a) with PO-Fast-SSCL and ExPOS-Fast-SSCL (Figure 12b,c) decoder implementations. This is due to enhanced tree pruning, enabled by being able to drop the restrictions on \(N_{\text{$\mathrm{\mathrm{\mathrm{\mathrm{\mathrm{\mathrm{\mathrm{\mathrm{\mathrm{\mathrm{ missing



## 5 Conclusions

In this work, we have proven that the upper bound for the number of candidates in the decoding of Rate-1 nodes required to preserve error-correction performance in Fast-SSCL decoders can be decreased.