# A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process
## 1 Introduction  
Driven by the rapid development of the information age, the demand for systems such as data acquisition, future mobile communication systems, and instrumentation is growing rapidly [1; 2; 3; 4]. As the core devices of these systems, high-speed and high-precision ADCs with a resolution exceeding 10-bit and a sampling rate higher than 1-GS/s have become a research hotspot [5; 6; 7]. However, at a high sampling rate, too short a settling time makes the settling of the residual amplifier (RA) insufficient, resulting in a decrease in ADC performance. The output-settling time of the operational amplifier is affected not only by the performance of the operational amplifier but also by the other modules such as comparators, switch capacitors, clocks, etc. In recent years, there have been several solutions to the problem of insufficient settling time of op-amps. Firstly, the ring amplifier, due to its simple topology and low power consumption, replaces the traditional operational amplifier [8; 9]. A ring amplifier combined with a high-pass filter can improve the settling time [8]. Second, the effective settling time of the residual amplifier is limited by the resolving time of the sub-ADC, so there are numerous studies on improving the performance comparators [10]. For example, an improved high-speed dynamic comparator is adopted, which aims to optimize the comparator's regeneration time and reset time [11]. Thirdly, choosing a reasonable switch resistance to create a critically damped system can reduce the multiplication time of the digital-to-analog converter (MDAC) [12]. In addition, an optimized MDAC was introduced to eliminate the effects of insufficient settlement between adjacent samples in conventional MDACs [13]. In general, great progress has been made in the improvementin settling time; however, optimization in timing from a timing perspective, which directly allocates more time to op-amps, has not been adequately studied. To address the issue, this paper proposes a reasonable and improved working timing called pre-quantization timing (PQT). Different from traditional timing that includes the sampling phase and the amplification phase, the PQT is divided into three stages: sampling, pre-quantization, and amplification, which brings obvious advantages as follows. First of all, PQT solves the problem of not allocating enough time for quantization in traditional timing. Second, a small cost is sacrificed to allow for more time for the op-amps to settle. Third, the bit error rate of the chip can be considerably reduced when employing a high-speed comparator, and the bit error rate is near \(10^{-15}\) in the final testing and verification. However, the main difficulties of the above timing applications are as follows: On the one hand, the clock generation circuit has difficulty in generating an accurate and stable timing of 25% duty cycle. Traditional pipelined ADCs using this timing typically operate in time-domain interleaved mode, as shown in the article [14; 15]. On the other hand, the external 2-GHz input clock mentioned by previous studies on pipelined ADCs increases the application difficulty of the system [16]. Therefore, this ADC uses a delay lock loop (DLL)-dependent clock circuit to generate the above timing, which can provide a non-50% duty cycle clock phase without an additional master clock. On the other hand, although PQT makes the design of the input buffer more challenging, it is less difficult than the design of the closed-loop op-amp of the MDACs, so this design is feasible and desirable. In addition to the PQT mentioned above, the performance of the modules in ADC core should also be carefully designed. Firstly, DLL is mainly used to generate a precise time delay, which does not change with external conditions such as temperature and voltage [17]. The variable delay line (VDL) is used to configure different sampling rates to provide a stable and reliable comparator clock.