# Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection
## 5 Bandwidth Extension Techniques
### Inductive Peaking
By placing an additional inductor (\(L3\)) over the shunt and series peaking, better isolation of the capacitors can be obtained; hence, the circuit bandwidth can be further enhanced [103]. However, this technique requires three inductors, thus occupying extensive silicon area. A T-coil network shown in Figure 30c resolves this challenge [97; 101; 103]. The negative coupling between the two inductors (\(L1\) and \(L2\)) affects the initial boost in the current flow to \(C2\), which indicates that \(C2\) is effectively connected in series with the negative mutual inductance element of the T-coil [102]. In other words, the T-coil network is equivalent to the shunt and double series peaking in Figure 30b, where three inductors form a 'T' shape. That is why this technique is called a 'T-coil' network. With the T-coil network, the number of inductors is reduced to two. Moreover, the two inductors or the transformer can be implemented in silicon IC while occupying lesser area than the two inductors without magnetic coupling, by using novel winding techniques for T-coils [102; 103]. The achievable BWER of T-coil network is approximately 4.0 with a reasonable \(C1\) over \(C2\) ratio and gain peaking, and the detailed quantitative values of BWER of the T-coil network are provided in [102]. From now on, the inductive peaking techniques employed in the TIAs are introduced. In 2000, a Stanford group introduced the shunt inductive peaking into their TIA based on a resistive feedback  
Figure 29: Circuit diagrams of (**a**) CS stage without inductive peaking, (**b**) CS stage with shunt peaking, (**c**) and CS stage with series peaking. CS stage as shown in Figure 31[95]. A CG stage is placed between the shunt-peaked CS stage and the PD for decoupling the PD capacitance and the main stage and for introducing an additional flexibility to optimize the shunt inductor. With the proposed technique, they achieved BWER of 1.40 using an on-chip inductor of 20 nH. Moreover, it was verified that their TIA achieves a bandwidth of 1.2 GHz when fabricated in 0.5-\(\upmu\)m CMOS technology. To the best of the authors' knowledge, the first introduction of the series inductive peaking into high-speed photodetections was performed by a Caltech research group in 2004 [80]. Their TIA, which was fabricated in 0.18-\(\upmu\)m CMOS, consists of three gain stages in order to achieve sufficient transimpedance gain and includes four series inductors. As shown in Figure 32, each series inductor separates the adjacent capacitors as follows: (1) \(L1\): the PD capacitance and the TIA input capacitance, (2) \(L2\) and \(L3\): the junction capacitances of cascode transistors, and (3) \(L4\): the output parasitic capacitance/bonding pad capacitance. The four series inductors achieve an overall BWER of 2.4, and each contribution of the inductors is summarized in Figure 32. The 3-dB bandwidth of the TIA is 9.2 GHz and the eye-diagram at 10 Gb/s is verified. In addition to using series inductors between cascode transistors, a UCSD group also added series inductors between the cascaded gain stages [98]. Two series inductors, \(L2\) and \(L3\), are placed between the cascaded amplifiers for further bandwidth extension while adopting a similar structure with [80], as shown in Figure 33. Moreover, it is notable that the authors of [98] did not overlook the degradation of phase linearity owing to the increased BWER. They evaluated the group delay response of the TIA as well as the BWER; thus, a group delay variation of 16 ps was achieved for their TIA whereas that of the TIA in [80] exceeds 50 ps. As a result, while fabricated in 0.13-\(\upmu\)m CMOS, the TIA opens the eye diagram at 40 Gb/s and achieves better eye opening compared to [80]. In 2012, the same group proposed to combine the series peaking technique with the inverter-based TIA, which is more appropriate for use in deep sub-micron CMOS SOI technology and with a lower supply voltage [69]. With a 1.0-V supply voltage, the TIA achieves 3-dB bandwidth of 30 GHz while dissipating 9 mW.