# Efficient Layered Parallel Architecture and Application for Large Matrix LDPC Decoder
## 3 Design and Implementation
### Partially Block-Parallel  
A compromise between serial-layered decoding and parallel-layered decoding is considered--more blocks are processed per cycle, but multiple cycles are still required to process a sublayer. Since more blocks are processed per cycle, but the blocks of each layer will not be processed in one cycle and are not fully parallelized, it is called partially block-parallel (PBP). Compared with the serial design, the hardware implementation of partially block-parallel hierarchical decoding consumes more hardware resources than the serial decoder but takes more throughput compared with the parallel design, lowering complexity and making the implementation of the long-code decoder possible. In this design, the decoder is able to process 3 blocks at the same time. In the decoder proposed in [15], the VM only stores amplitude information, and the sign of the VN information is obtained by reading the SM. In the reordered algorithm, the update of VN information requires 2 read and 1 write operation for SM; so, they use a memory bank design, dividing the base matrix into 3 blocks so that the decoder designed in their work can access the SM simultaneously without conflict. The path of VN sign during the operation of the decoder is shown in Figure 3a: (1) It is extracted from memory to recover VN information and CN information. (2) Then, sign is extracted again to recover CN information. (3) Finally, after computing the updated VN information, its sign part is stored in the SM. In the PBP decoder, memory access operations increase by several times; in this design, they need to be increased by 3 times. Therefore, the sign memory needs to be accessed 9 times per cycle (\(3*3=9\)). However, dividing the base matrix into 9 blocks will introduce a large number of bubbles, which will significantly reduce the throughput. This paper tries to reduce the read/write access number to 2 for each block, then dual-port memory in combination with dividing the base matrix into 3 blocks allows for 6 read/write accesses per cycle. First, assuming that sign is stored in both sign memory and VN memory, the movement of variable symbol information is shown in Figure 3b: (1) VN information is directly obtained from VM, and sign part is used to restore the CN information. (2) Sign extracted from SM is used to recover CN information. (3) After the update is completed, the sign  
Figure 3: Path of VN sign. (**a**) When the variable memory only stores the copy information, the moving path of the variable node symbol information; (**b**) When variable memory stores symbol information, the moving path of variable node symbol information; (**c**) This paper presents a new method to eliminate duplicate storage. part of the updated VN information needs to be written into both VM and SM. Obviously, using this method, each block update only requires one read/write access. However, since the storage share in [15] is abandoned, the symbol part of VN information in VM is duplicated in sign memory; so, the decoder needs to increase memory bits by one code length (17,664 bits). By analyzing Figure 3b, it can be observed that the sign in SM is only used to recover the second CN information \(R_{mn}\). The sign part written into the VM is used to compose the VN information and restore the first CN information \(R_{m^{\prime}n}\) at the same time. Consider a method for re-eliminating duplicate storage as follows: After completing block updates, the sign part of the updated variable node VN is firstly stored in VM, and when it is read out from VM, it is written into SM. Finally, when the sign is needed, it is read out from SM, and the data flow can be summarized as shown in Figure 3c. The sign read-write process is as follows: Assuming that the degree of a column is \(n\), it is obvious that \(n\) signs need to be stored. The 1 st is stored in VM, and the remaining \(n-1\) signs are stored in SM.