# An Embedded Sensor Node Microcontroller with Crypto-Processors
## 4 Implementation and Verification  
The TNODE5 chip is implemented using the standard design flow of the IHP's 250 nm BiCMOS technology. The logic synthesis is performed with Synopsys Design Compiler for a target frequency of 20 MHz. The total cell area of the synthesized chip excluding IO pads is estimated to 13.33 mm\({}^{2}\). Table 3 presents synthesis results for the cell area of different TNODE5 components. The results show that the analog and memory components (SRAM, Flash, DCO, and ADC) consume 71.8% of the total cell area. The remaining 38.2% is taken by the logic components. The crypto cores take 15.6% and the baseband core takes around 3.9% of the total cell area. This results in an area overhead due to the crypto and communication cores of nearly 20%.  
The layout of the chip is designed with the Cadence SoC Encounter tool. The size of the final chip is 23.96 mm\({}^{2}\), which is twice the size of the estimated cell area. The difference between the  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Chip Component** & **Cell Area (mm\({}^{2}\))** & **Percent (\%)** \\ \hline Flash & 5 & 37.6 \\ RAM & 3.3 & 24.8 \\ ECC & 1.45 & 10.9 \\ ADC & 1.23 & 9.2 \\ Baseband & 0.53 & 3.9 \\ Uart1 + Uart2 & 0.4 & 3 \\ SHA-1 & 0.37 & 2.8 \\ CPU & 0.3 & 2.3 \\ AES & 0.25 & 1.9 \\ Flash Controller & 0.12 & 0.9 \\ Timer (32 bit) & 0.11 & 0.8 \\ Timer (16 bit) & 0.075 & 0.6 \\ SPI + SPI2 & 0.048 & 0.4 \\ P1 + P2 & 0.048 & 0.4 \\ P3 + P4 & 0.022 & 0.2 \\ DCO & 0.024 & 0.2 \\ Bus Control & 0.018 & 0.1 \\
**TNODE5** & **13.33** & **100** \\ \hline \hline \end{tabular}
\end{table}
Table 3: Cell area of TNODE5 components estimated after synthesis.  
estimated and the final chip size is mainly reasoned by the additional area required by IO pads, the power supply network and the routing constraints. The photo of the TNODE5 layout is given in Figure 4. The TNODE5 has only 64 IO pads (39 digital, 13 analog, and 12 power/ground), which makes it possible to package the chip in a small 64-pin quad-flat-no-leads package (QFN). Furthermore, a very small ball grid array (BGA) package can be used as well. Further miniaturzations are possible with a PCB direct bonding and the flip chip technology. While a direct bonding is possible with the current chip version the flip chip technology requires special design rule, which are planned to use in future versions. Any miniaturization makes the chip more robust against tampering and improves its usability in sensor node applications.  
The verification process of the TNODE5 chip includes functional verification during the design process and the verification of the fabricated chips. The functional verification during the design stage includes the simulation of digital and analog parts and the simulation of the whole system. The simulation tests were designed to cover the functionality of the overall system and each peripheral in particular. The production tests on the fabricated chips had to confirm the functional correctness and the compliance to the specified electrical and system parameters, e.g., power consumption and maximal clock rate. The final evaluation of the chip has been done on a dedicated hardware evaluation platform.