## 3 Results
### Verification of Scheduler Operation  
To validate the proper operation of our scheduler, we monitored the state changes of specific pins on the Feather M0 microcontroller board by toggling them between LOW and HIGH states. At the start of each task--namely, sensor reading, packet assembly, and data transmission--the corresponding pin was set to HIGH, reverting to LOW upon task completion. Each task was assigned a dedicated pin, allowing simultaneous measurement of all pins using an oscilloscope. It is important to note again that in all measurements, the data formatting task was incorporated into the packet assembly task. A _Single-Sample Mode_, where each streamed packet contains a single sensor sample, is presented in Figure 5. It illustrates four sensor sampling intervals of the system operating at a sampling frequency of 100 Hz (one sample per packet). The graph displays sampling intervals, with a measured period \(\Delta X\) of 10 milliseconds between the vertical dotted lines. This results in a sampling frequency of \(1/\Delta X=100\) Hz, confirming the correct timing set by the scheduler's timer interrupt. The oscilloscope traces show the signals at the three monitored pins: the lower trace (pin D4) corresponds to the sensor reading task that occurs at each sensor sampling period, the middle trace (pin D1) corresponds to the packet assembly task, and the upper trace (pin D3) corresponds to the packet sending task. The traces demonstrate that tasks are executed sequentially without time gaps and that all tasks are executed within one sampling period. This particular configuration also provides the microcontroller with sufficient time to perform additional tasks between the end of a sending task and the start of the next reading task, if required. A _Multi-Sample Mode_, where each streamed packet contains multiple sensor samples, is shown in Figure 6. In this case, the system operates at a sampling frequency of 1750 Hz and with 26 samples per packet. It can be seen from the traces that the tasks of packet assembly (pin D3) and sending (pin D4) span several sampling periods (pin D1). Without our scheduler, executing these tasks within the short sampling period of 0.571 ms, which corresponds to the sampling frequency of 1750 Hz, would not be feasible. However, the figure confirms the correct operation of the system in multi-sample streaming mode. It is worth noting that between two consecutive packet assembly tasks (pin D3), there are 26 sensor reading tasks (pin D1 transitions), so the sampling frequency can be calculated based on the time interval and the number of reads. The main difference between the single- and multi-sample streaming modes (shown in Figures 5 and 6) is that, in the first case, all the required tasks are performed within one sampling period, while in the second case, they span several sampling periods, and the scheduler must ensure correct sensor sampling throughout. While Figures 5 and 6 graphically verify the operation of our scheduler, further validation can be performed by analysing the measured times for reading the sensors, assembling the packets, and sending the packets, which are given as results in the following sections. For example, if device D operates at a sampling frequency of 1750 Hz, contains 26 samples per packet, and uses the bit-shifted hexadecimal representation, the time to read a single sample is 0.317 ms (see Table 1), the time to assemble 26 samples into a packet is 2.300 ms, and the time to send the packet is 12.060 ms (what is explained later in Section 3.3 and presented in Table 2). The total time of the above tasks is 14.677 ms, which is shorter than the cumulative duration of 26 sampling periods at 1750 Hz, which is 14.857 ms. This confirms that the system operates within the required time constraints. Figure 5: Oscilloscope traces of four sensor sampling intervals at a 100 Hz sampling frequency with one sample per packet.