## 4 Results and Discussion
### Scenario III: Unbalanced and Distorted Source Voltage
Owing to severe distortion at the source side and unbalanced issue of the connected load, the ADALINE module alone is not sufficient to provide a ripple-free mean value, as clearly illustrated in Figure 7, Figure 12, and Figure 17. However, a ripple-free mean value of fundamental load current is highly crucial to improve accuracy of the generated reference current. Hence, in this work, an additional averaging function was integrated to remove any unwanted ripples and at the same time it improves the accuracy of the mean value. Second, in terms of harmonics mitigation performance, the findings revealed that SAPF controlled by the enhanced-ADALINE algorithm performs better in all the three scenarios as compared to the SAPF controlled by the STF-dq0 algorithm. This is supported by the smaller THD values recorded in Tables 2-4. Hence, the enhanced-ADALINE algorithm can potentially serve as an alternative to manage operation of SAPF in a three-phase four-wire system rather than just depending on the typical SRF and PQ theory techniques. Third, in the context of dc-link voltage regulation and voltage balancing, the findings revealed that the utilization of the enhanced-ADALINE algorithm does not degrade the ability of SAPF in regulating its overall dc-link and maintain its voltage balance. In other words, the enhanced-ADALINE algorithm can be integrated properly with the two PI techniques applied respectively for regulating the dc-link voltage and ensuring voltage balance of the two split dc-link capacitors. Therefore, in this work, it can be confirmed that the enhanced-ADALINE algorithm is able to correctly manage operation of SAPF in a three-phase four-wire system even if the connected grid is non-ideal and loads are unbalanced. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Performance** & \multicolumn{3}{c}{**Load A**} & \multicolumn{3}{c}{**Load B**} \\ \cline{2-7}
**Parameter** & **Phase _a_** & **Phase _b_** & **Phase _c_** & **Phase _a_** & **Phase _b_** & **Phase _c_** \\ \hline \multicolumn{7}{c}{Before installing SAPF} \\ THD (\(\%\)) & 27.74 & 18.56 & 53.32 & 33.79 & 129.01 & 27.13 \\ Phase difference (\({}^{\circ}\)) & 9.80 & 13.50 & 5.80 & 11.20 & 10.10 & 11.90 \\ PF & 0.949 & 0.956 & 0.877 & 0.929 & 0.603 & 0.944 \\ \multicolumn{7}{c}{After installing SAPF (controlled by enhanced-ADALINE algorithm)} \\ THD (\(\%\)) & 1.45 & 0.98 & 1.87 & 1.73 & 2.13 & 1.53 \\ Phase difference (\({}^{\circ}\)) & 0.10 & 0.60 & 0.40 & 1.00 & 0.30 & 0.80 \\ PF & 0.999 & 0.999 & 0.999 & 0.999 & 0.999 & 0.999 \\ \multicolumn{7}{c}{After installing SAPF (controlled by STF-dq0 algorithm) [22]} \\ THD (\(\%\)) & 1.91 & 1.66 & 2.34 & 2.20 & 2.92 & 2.05 \\ Phase difference (\({}^{\circ}\)) & 0.10 & 0.80 & 0.60 & 1.10 & 0.40 & 0.90 \\ PF & 0.999 & 0.999 & 0.999 & 0.999 & 0.999 & 0.999 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Summary of performance parameters demonstrated by the enhanced-ADALINE and STF-dq0 algorithms under Scenario III. Figure 19: Simulation result obtained under Scenario III for Load A, showing the overall dc-link voltage \(V_{dc}\), and individual voltage of each split capacitor \(V_{dc1}\) and \(V_{dc2}\), demonstrated by SAPF while applying the enhanced-ADALINE algorithm. Figure 18: Simulation results obtained under Scenario III for Load A, showing source voltage \(v_{\text{Sale}}\), load current \(i_{\text{L}abc}\), injection current \(i_{\text{in}jabc}\), source current \(i_{\text{Sale}}\), and neutral current before and after mitigation, demonstrated by SAPF while applying the (**a**) enhanced-ADALINE and (**b**) STF-dq0 algorithms. Figure 21: Simulation result obtained under Scenario III for Load B, showing the overall dc-link voltage \(V_{dc}\), and individual voltage of each split capacitor \(V_{dc1}\) and \(V_{dc2}\), demonstrated by SAPF while applying the enhanced-ADALINE algorithm.