## 4 LDPC Decoder Architecture Design  
LDPC codes are known to nearly achieve the Shannon limit when the block of data is very large (\(N\rightarrow\infty\)) [10]. However, in WSN applications the amount of bits exchanged by nodes is limited, leading to small \(N\) values. Nevertheless, in [28, 29] it is shown that LDPC codes can achieve excellent performance even when \(N\) is small. In this work, we analyze the minimum \(N\) LDPC code from the IEEE 802.16e standard [30], which corresponds to \(N=576\) coded bits and \(K=R\cdot N=288\) uncoded bits (\(R=0.5\)). Moreover, we considered the two best performing regular codes with \(N=96\) and \(N=204\) (\(K=48\), \(K=102\)) respectively, taken from MacKay database [31] and referred to as 96.33.966 and 204.33.484 (\(R=0.5\) for both). In order to size the LDPC decoder architecture, finite precision analysis ought to be performed. Given that \(p_{S}\) and \(p_{R}\) are the number of bits to represent \(S_{j}\) and \(R_{mj}\) metrics respectively, as in Equations (1-6), simulations have been carried out for \(p_{S}\in\{5,6\}\) and \(p_{R}\in\{3,4\}\); normalized-min-sum approximation with \(\sigma=0.875\) has been employed. The performance of the three considered codes are shown in Figures 1-3 both in the floating point and fixed point cases together with the performance of the corresponding uncoded system. Furthermore, it has been observed that targeting a BER of \(10^{-4}\) as in [3, 9] and imposing a maximum of ten iterations (\(I=10\)), the performance loss is negligible. Figure 1: BER performance of the \(N=96\) LDPC code. Figure 2: BER performance of the \(N=204\) LDPC code. Due to the low throughput required, we assume that a fully serial processor architecture, which executes the decoding algorithm on one CN at the time, is a reasonable solution. In this case the throughput sustained by the architecture, defined as the number of decoded bits over the decoding time, is  
\[T=\frac{K\cdot f_{clk}}{M\cdot I\cdot d_{c}^{\max}+D}=\frac{K\cdot f_{clk}}{ \frac{1-R}{R}\cdot K\cdot I\cdot d_{c}^{\max}+D} \tag{13}\]  
where \(f_{clk}\) is the decoder clock frequency, \(I\) is the maximum number of iterations, \(d_{c}^{\max}\) is the maximum degree of a CN, _i.e._, the maximum number of edges on a CN and \(D\) is the latency of the architecture. It is worth noting that Equation (13) can be adapted to parallel and partially parallel architectures by substituting \(M\) with \(M/W\) where \(W\) is the number of rows (in **H**) processed in one clock cycle. The latency \(D\) in Equation (13) can be minimized avoiding idle cycles between iterations, so that \(D=d_{c}^{\max}\). Thus, the throughput can be approximated as  
\[T=\frac{K\cdot f_{clk}}{\left(\frac{1-R}{R}\cdot K\cdot I+1\right)\cdot d_{c} ^{\max}}\approx\frac{R\cdot f_{clk}}{(1-R)\cdot I\cdot d_{c}^{\max}} \tag{14}\]  
As it can be observed, the throughput increases with \(R\) so low-rate codes are a conservative choice to achieve the target throughput. Moreover, if we fix \(N\) we observe that increasing the rate has the effect of reducing the BER performance of the code. Thus, we considered the \(N=204\), \(R=0.5\) code and tried to increase both \(N\) and \(R\). From MacKay database [31] we considered the following two high-rate codes where \(N>204\): \(N=273\), \(R=0.7\) and \(N=495\), \(R=0.87\) referred to as 273.82.3.353 and 495.62.3.2915 respectively. As shown in Figure 4 the BER performance of both codes  
Figure 3: BER performance of the \(N=576\) LDPC code. is lower than the one obtained for \(N=204\), \(R=0.5\). Furthermore, codes with \(N>204\) require a larger amount of memory than the \(N=204\), \(R=0.5\) code. From this analysis we infer that for the most complex code among the ones considered in this work, _i.e._, \(d_{c}^{\max}=7\) for the IEEE 802.16e \(N=576\), \(R=0.5\) code, and given the target throughput \(T=250\) kb/s and \(I=10\), Equation (14) leads to \(f_{clk}\geq 17.5\) MHz. In this work we fix \(f_{clk}=20\) MHz as a conservative value.