# Design and Control of a Battery Charger/Discharger Based on the Flyback Topology
## 6 Simulation Results
### Comparison with a Classical Control System  
An additional evaluation was carried out by contrasting the performance of the proposed SMC with a classical solution based on PI controllers. The first step to design this classical controller solution is to obtain a linearized model depending on the duty cycle \(d\) of the converter. This process starts with the averaged model presented in Section 2.2, which is evaluated at the steady-state conditions defined in Section 2.3 using the values given in Tables 1 and 2 (Vitec HFT). The resulting linear model is given in expressions (50) and (51), which describe the small-signal models of both the bus voltage and magnetizing current depending on the duty cycle. \[\frac{\hat{v_{dc}}}{\hat{d}}=\frac{-3.471\times 10^{4}\cdot s+2.222 \times 10^{9}}{s^{2}+1.131\times 10^{7}} \tag{50}\] \[\frac{\hat{v_{m}}}{\hat{d}}=\frac{1.041\times 10^{6}\cdot s+1.839 \times 10^{8}}{s^{2}+1.131\times 10^{7}} \tag{51}\]  
Analyzing the small-signal model of the bus voltage, given in (50), shows that the system exhibits a non-minimum phase behavior due to the positive zero of the transfer function, thus it will be almost impossible to regulate the bus voltage with a single PI controller. This type of system is commonly controlled using a cascade structure [24; 26], where an inner controller regulates another state variable to reduce the order of the system. In this case, the other state variable available is the magnetizing current, which small-signal model (51) has a negative zero, thus it has a minimum phase behavior that can be regulated with a single PI controller. Then, the current control loop reported in (52) was designed, using the pole-placement technique [46], to provide a settling time of the magnetizing current. Figure 15: Transition between battery discharge, battery charge, and battery in stand-by. current (\(i_{m}\)) equal to 0.2 ms and a closed-loop bandwidth of 8 kHz, which is below the switching frequency imposed by the PWM driving the Mosfets (\(F_{sw}=30\) kHz). \[\text{Current control loop}\ \ \ \Rightarrow\ \ \hat{d}=\frac{0.037\cdot(s+1.442 \times 10^{4})}{s}\cdot\big{(}\hat{i_{r}}-\hat{i_{m}}\big{)} \tag{52}\]  
Since the settling time of \(i_{m}\) is five times smaller than the settling time defined in Table 1 for the bus voltage (\(t_{s}=1.0\) ms), the cascade voltage controller is designed by considering a correct control of the magnetizing current, thus \(\hat{i_{m}}\approx\hat{i_{r}}\) where \(\hat{i_{r}}\) is the small-signal reference for the magnetizing current. Therefore, the dc bus voltage model is simplified by assuming \(\hat{i_{m}}\approx\hat{i_{r}}\) to obtain the reduced-order model reported in (53), which describes the behavior of the bus voltage to changes on the magnetizing current. Finally, a voltage control loop is designed to provide the current reference \(\hat{i_{r}}\) to the current control loop; such a voltage control loop, reported in (54), was designed using the pole-placement technique to provide the desired settling time and maximum voltage deviation defined in Table 1.  
\[\frac{\hat{v_{dc}}}{\hat{i_{m}}}=\frac{0.5761}{0.00027\cdot s}\ \ \ \ \text{where}\ \ \ \hat{i_{m}}\approx\hat{i_{r}} \tag{53}\] \[\text{Voltage control loop}\ \ \Rightarrow\ \ \hat{i_{r}}=\frac{5.568\cdot(s+3960)}{s}\cdot(v_{r}-\hat{v_{dc}}) \tag{54}\]  
The output of the inner (current) control loop is the duty cycle, thus a PWM is used to impose that duty cycle to the Mosfets with a fixed switching frequency \(F_{sw}=30\) kHz. Figure 16 presents the comparison between the performance of the proposed SMC solution and the classical cascade PI structure presented in this subsection. The main perturbation of the charger/discharger is the bus current which exhibits changes with the amplitude defined in Table 1: it is observed that the proposed SMC ensures both the desired settling time and maximum voltage deviation, while the PI structure only fulfills the settling time since the voltage deviation is higher than the limit \(\Delta v_{dc}\).