## 4 Design of the Enhanced Fault Current Limiting Circuit
### Parametric Design  
Before the EFCLC is inserted in the fault circuit loop, the fault current is only limited via the smoothing reactor, which decides the maximum increase in the fault current rate. The minimum smoothing reactor can be obtained using Equation (9) considering the limitations in the DCCB withstanding fault current change rate (4.5 kA). The theoretical minimum smoothing reactor is 41.2 mH. However, the simulation result provides 43 mH with 4.2% error. The reason may be attributed to the consideration of DC line current under the normal states. The smoothing reactor \(L_{dc}\) is set to 50 mH considering the margin. The EFCLC will be inserted to limit fault current rising speed and amplitude after detecting a fault. Thus, the fault current rising speed is less than the fault detection time; thus, Constraint (39) is satisfied by properly selecting a smoothing reactor. An initial test with the EFCLC has been performed. The energy dissipation resistance \(R_{FCL}\) is set to 50 \(\Omega\), and the FCL reactor \(L_{FCL}\) is set to 100 mH. The simulation conditions \"af\" and \"ah,\" as listed in Table 2, are compared here. The red dashed line in Figure 17 indicates that a fault occurs at 1.2 s and takes 1 ms to detect fault [37]. Furthermore, the delay in the IGBT of the EFCLC is disregarded here. The fault current change rate during \(\Delta t_{1}\) is approximately 4 kA/ms, which is expectedly limited under the maximum current change rate of the hybrid DCCB. The EFCLC is inserted in the fault current circuit at 1.201 s, and the fault current experiences a sharp decrease \(\Delta I_{1}\) because a part of the electrical energy is stored in \(L_{FCL}\). The fault current rising speed is lower during \(\Delta t_{2}\) than during \(\Delta t_{1}\). Therefore, the fault current at 1.203 s (the main breaker opens) is limited to approximately 6.6 kA, which is far below the maximum breaking current of the DCCB. Moreover, \(L_{FCL}\) is bypassed by the thyristor while the main breaker opens, and the fault current extinguishment can be accelerated. The initial simulation result suggests that Constraint (41) leads to the minimum value of \(L_{FCL}\) and \(R_{FCL}\). Therefore, the controlled match of \(L_{FCL}\) and \(R_{FCL}\) must be investigated. The fault current at 1.201 s is consistently 4 kA given the unchanged fault circuit parameter. Therefore, Figure 17 presents that  
\[4 kA-\Delta I_{1}+\Delta I_{2}<9 kA \tag{44}\]  
In comparison with the blue dashed-dotted line illustrated in Figure 17, two current curves share nearly the same part during \(\Delta t_{2}\). Thus, \(\Delta I_{1}\) can be obtained with a difference between the current values of the two discharging conditions. In accordance with Equation (9), \(\Delta I_{1}\) is expressed as Equation (45). \[\Delta I_{1}=\left.i_{dis\_af}(t)\right|_{t=1 ms}-\left.i_{dis\_ah}(t)\right|_{ t=1 ms} \tag{45}\]  
Moreover, Equations (44) and (38) can be simplified as Equation (46), because the two current curves depicted in Figure 17 have nearly the same value at 1.203 s.  
\[i_{dis\_ah}(t)\right|_{t=3 ms}<9 kA \tag{46}\]  
The equivalent resistance \(R_{qq\_ah}\) and equivalent inductance \(L_{rq\_ah}\) are acquired as Equations (47) and (48), respectively. Thus, on the basis of Equation (9), the fault current \(i_{dis\_ah}\) at 1.203 s can be calculated. If \(R_{FCL}=20\)\(\Omega\), then \(L_{FCL}\) must be larger than 46.4 mH to limit the fault current at 1.203 s under 9 kA. The minimum \(L_{FCL}\) matched with \(R_{FCL}=20\)\(\Omega\) has been verified via a controlled simulation (Figure 18). The simulation results of the EFCLC with controlled \(R_{FCL}\) and different \(L_{FCL}\) are compared (Figure 18). The fault current with the EFCLC (calculated \(L_{FCL\_min}=46.4\) mH with \(R_{FCL\_min}=20\)\(\Omega\)reaches 9106 A at 1.203 s. Thus, the error rate of the theoretical calculation is approximately 1.2% within a reasonable range, and the minimum \(L_{FCL}\) can be set to 47 mH.