# Dynamic Single-Electron Transistor Modeling for High-Frequency Capacitance Characterization
## 3 Simulation Results
### Characteristics of the SET-Based Amplifier  
Figure 7a shows the circuit diagram of the SET-based inverting amplifier with a constant-current load, and Figure 7b describes the operation point in the Coulomb diamond (CD) plot. The operation point is set at the center of the descending side in the input-output (\(V_{\rm ds}\)-\(V_{\rm gs}\)) characteristics for the \(I_{\rm d}=\pm 26.7\) pA [=(\(V_{\rm ds}/4\ R_{\rm t}\))/10 with \(V_{\rm ds}=e/C_{\rm\Sigma}/2\)]. Figure 6: SET input capacitance \(C_{\rm gg}\) as a function of temperature at drain voltages \(V_{\rm ds}=0.534\) mV [0.01] and 26.7 mV [0.5], and gate voltages \(V_{\rm gs}=80.1\) mV [0.5] and 93.5 mV [0.6], respectively. Figure 7: (**a**) A circuit diagram of the SET-based inverting amplifier with constant-current load, and (**b**) Coulomb diamond (CD) plot with \(V_{\rm ds}\)-\(V_{\rm gs}\) curves for \(I_{\rm d}=\pm 26.7\) pA at \(T=15.5\) K [0.05]. The operation point of the amplifier is set at the center of the descending side. To evaluate the frequency response of the amplifier, small sinusoidal fluctuation with amplitude \(\Delta V_{\rm gs}\) (=\(e/C_{\rm g}/1000\)) is added to the gate bias \(V_{\rm gs}\), and the fluctuation in \(V_{\rm out}\) is observed by the simulation. Figure 8 depicts the frequency response of the SET-based amplifier. At low frequencies, the voltage gain close to the slope of the descending side of the CD (=\(C_{\rm g}/C_{\rm d}\)) is obtained, and the phase is inverted. At high frequencies, the transistor action is lifted, the gain becomes that of passive capacitive divider consisting of the \(C_{\rm g}\) and \(C_{\rm s}\), and the output is in phase with the input. Interestingly, the gain and phase start to change at higher frequency compared to the case in Figure 5 probably due to the high-impedance condition at the output terminal. The input capacitance \(C_{\rm gg}\) is also simulated as a function of the gate voltage \(V_{\rm gs}\) at three different frequencies and shown in Figure 9.  
As can be seen in the figure at the low frequency (10 kHz), the \(C_{\rm gg}\) shows a high peak at \(V_{\rm gs}\) = 0.5 \(e/C_{\rm g}\) due to the small \(V_{\rm ds}\) and resultant abrupt change in the island charge. At the cutoff frequency (1 GHz), the peak height is reduced largely, and at the high frequency (100 GHz), the \(C_{\rm gg}\) levels off to the baseline value that corresponds to the series connection of \(C_{\rm g}\) and \(C_{\rm s}\) as shown in the expression in the legend. Such behavior again verifies that the SET behaves like a passive circuit of capacitors at high frequencies. Another interesting finding in Figure 9 is that the Miller effect [6] is not conspicuous in the SET-based amplifier as the \(C_{\rm gg}\) at the operation point (\(V_{\rm gs}\) = 0.33 \(e/C_{\rm g}\)) is almost the same as that in Figure 4a because the feedback capacitance \(C_{\rm gd}\) is negligibly small as shown  
Figure 8: Frequency response of the SET inverting amplifier operating at a drain current \(I_{\rm d}\) = 26.4 pA, gate voltage \(V_{\rm gs}\) = 53.4 mV [0.33] (center of the descending side of the CD) and \(T\) = 15.5 K [0.05]. Figure 9: SET input capacitance \(C_{\rm gg}\) as a function of the gate voltage \(V_{\rm gs}\) for a drain current \(I_{\rm d}\) = 26.7 pA at \(T\) = 15.5 K [0.05]. in Figure 4b, suggesting that it is only necessary to take care of the parasitic capacitance when we discuss the Miller effect in the SET-based amplifier. We have focused on the intrinsic SET characteristics so far. In reality, lead lines connected to the terminals are always accompanied by parasitic components such as capacitance, inductance, resistance, etc. As an example of a real circuit, an inverting amplifier with a load capacitance \(C_{\text{L}}\) is analyzed (Figure 10).