# Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication
## 3 Combined Min-Sum Algorithm
Hence, the decompression unit DECOM aims at converting this compressed version of LLRs into \(d_{c}=19\)_decompressed_ extrinsic LLRs by using \(d_{c}\) equalizers, MUXs and sign-magnitude to two's complement conversion units (SMTCs) as shown in Figure 5.

### Check Node Units

The proposed decoder consists of \(Z=56\) CNUs, which implement the check node update step shown in Algorithm 1. A minimum-finder (19-FMVG) and sign processor unit (SPU) are exploited in this step. In this section, we focus on the computation of the first two minima \(min1\), \(min2\), and index of the first minimum \(indx\) since the signs of output messages can be simply calculated by XORing the adequate signs of input messages. The structure of the minimum-finder is based on the tree structure (TS) architecture proposed by [PERSON] [34]. However, it is further modified in our proposed architecture so as to compute only the value and the index of the first minimum in the first clock cycle. The second minimum value is decided in the second clock cycle by re-utilizing the same hardware architecture. The detailed architecture of a low complexity CNU is shown in Figure 7. As can be observed, the proposed CNU architecture consists of \(d_{c}=19\) sign-magnitude conversion (SMC) units, a 19 inputs-first minimum value generator unit (19-FMVG), sign processor unit (19-FMVG), sign



unit, and the compare and select (CS) unit for generating control signals. Initially, each CNU takes \(d_{c}\) inputs with bit-width \(w=4\) of \(L_{m,n}^{i}[l]\) value from the VNU. The 4-bit LLRs in the two's complement format are converted into sign and magnitude format with the aid of sign-magnitude conversion (SMC) units. The \(sel\) control signal is set to either 0 or 1 to indicate the operation mode of the CNU. When \(sel\) is set to 0, i.e., the first clock cycle, the CNU is carried out to generate the first minimum \(min1\) and index of the first minimum \(indx\). When \(sel\) is set to 1, i.e., the second clock cycle, the CNU is re-executed in order to calculate the second minimum value \(min2\). When CNU in the second clock cycle, the maximum value of bit-width \(w\) is substituted for the input value at index \(indx\) instead of straightforwardly passed all input values to the 19-FMVG units. Moreover, depending upon the clock cycle being processed, the \(en\) control signal is set to pass the corresponding minimum value to the output. The architecture of the FMVG for \(d_{c}=19\) inputs is also presented in Figure 7. Since \(d_{c}=19\) can be decomposed into the sum of 16 and 3, the result of \(d_{c}\)-FMVG block is realized by combining corresponding blocks as described in [34]. The index generator block in Figure 7 is deployed to create the index of the first minimum value. The architecture of 3-FMVG is shown in Figure 8a. Moreover, the \(2^{k}\)-FMVG block, which computes the value and the index of the first minimum among the \(2^{k}\) input messages of bit-width \(w\), can be constructed by cascading multiple 2-FMVGs as shown in Figure 8c. The 2-FMVG unit, as detailed in Figure 8b, is exploited for the comparisons discussed earlier. The comparison signal and output value of the 2-FMVG are defined as follows:

Figure 7: Proposed check node unit (CNU) architecture. \[ \begin{split} min&=in_{1}\quad\text{and}\quad cp=0, \quad\quad\text{if}\quad in_{1}\leq in_{2}\\ min&=in_{2}\quad\text{and}\quad cp=1,\quad\quad \text{if}\quad in_{1}>in_{2}\end{split}  \tag{5}\]

For the 19-FMVG block, an input word contains \(w-1\) bits, then the comparator and MUX also require \(w-1\) bits. In this section, we denote MUX as 1-bit 2-to-1 multiplexer, and MUX\({}_{\text{ir-1}}\) as a \((w-1)\)-bit 2-to-1 multiplexer. Table 4 summarizes the number of components required for the proposed minimum-finder based on FMVG and the conventional method, which determines both \(min1\) and \(min2\) values, denoted as two minimum values generator (TMVG). Results show that the proposed FMVG approach requires a much smaller number of comparisons and MUXs than the conventional method TMVG.