# Enhanced Control Strategy for Three-Level T-Type Converters in Hybrid Power-to-X Systems
## 4 Proposed Control Design
### Output Voltage Outer Control Loop  
The plant transfer function of the capacitor/output voltage, \(v_{O}\), to the inverter side inductor current, \(i_{L1}\), can be defined by the following:  
\[P_{V_{O}(s)/L_{L_{L}ref}(s)}(s)=\frac{1}{sC} \tag{21}\]  
which is resolved by the following dynamic equation:  
\[i_{L1}(t)=C\frac{dv_{O}(t)}{dt}+i_{L2}(t) \tag{22}\]  
i.e., the desired reference current of the inverter side inductor current, is set by the capacitor voltage control loop as shown in Figure 6. Then, voltage controller \(C_{2}(s)\) is defined as (11) with the plant defined in (21) and different time constant \(\omega_{CV}\) as follows:  
\[C_{2}(s)=\frac{sC\big{(}2\omega_{CV}s+\omega_{CV}^{2}\big{)}}{s^{2}+2\xi \omega_{0}s+\omega_{0}^{2}} \tag{23}\]  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameter** & **Value** & **Units** \\ \hline Switching and sampling frequency, \(T_{s}{}^{-1}\) & 50 & kHz \\ Filter inductors, \(L_{1x}\) & 340 & \(\mu\)H \\ AC side inductors, \(L_{2x}\) & 9.43 & \(\mu\)H \\ Filter capacitors, \(C_{x}\) & 10 & \(\mu\)F \\ DC link capacitors, \(C_{1}\), \(C_{2}\) & 460 & \(\mu\)F \\ Fundamental frequency, \(f_{0}\) & 50 & Hz \\ Fundamental frequency, \(\omega_{0}\) & 100\(\pi\) & rad/s \\ DC voltage, \(V_{DC}\) & 800 & V \\ Damping factor, \(\zeta\) & 0.001 & \\ Proportional gain, \(k_{C}\) & 0.06 & \\ \hline \hline \end{tabular}
\end{table}
Table 1: System Parameters.  
Figure 7: (**a**) Open-loop and (**b**) closed-loop Bode diagrams of the current loop.  
The bandwidth frequency of the voltage control loop is then defined as follows:  
\[\omega_{BV}\approx\frac{0.5\pi-PM}{T_{d2}}. \tag{24}\]  
In order to obtain the maximum crossover frequency of the capacitor voltage loop, the delay \(T_{d2}\) caused by the inner loop must be determined. Figure 8 shows the equivalent capacitor voltage loop diagram according to (21) and (22). It can be shown that the voltage loop actuator delay is the closed loop transfer function of the current loop (Equations (8) and (9)) [39] as in the following:  
\[CL_{I}(s)=\frac{I_{LInf}(s)}{I_{L1}(s)}=\frac{2\omega_{CI}s+\omega_{CI}^{2}}{ \left(s+\omega_{CI}\right)^{2}+\omega_{0}^{2}}. \tag{25}\]  
Combining (25) and (13), considering the switching and sampling delay and the damping factor, results in the following transfer function:  
\[CL_{I}(s)=\frac{2\omega_{CI}s+\omega_{CI}^{2}}{(s^{2}+2\zeta\omega_{0}s+\omega _{0}^{2})e^{I\sigma s}+2\omega_{CI}s+\omega_{CI}^{2}}. \tag{26}\]  
then, the corresponding loop gain is defined as follows:  
\[LG_{V}(s)=C_{V}(s)CL_{I}(s)P_{V_{O}/I_{LInf}}(s)=\frac{2\omega_{C}s+\omega_{C }^{2}}{(s^{2}+2\zeta\omega_{0}s+\omega_{0}^{2})e^{I\sigma s}+2\omega_{C}s+ \omega_{C}^{2}}\cdot\frac{1}{sC} \tag{27}\]  
The Bode diagram of the current closed-loop \(CL_{I}(s)\) (Equation (26)) transfer function is shown in Figure 7b. It can be seen from the bode diagram that \(CL_{I}(s)\) act as an actuator delay, setting the voltage loop bandwidth. Then, \(T_{d2}\) can be found according to Figure 7b and is twice that of \(T_{d}\). Then, the maximum crossover frequency of the capacitor voltage loop may be defined as the following:  
\[\omega_{BV}\approx\frac{0.5\pi-PM}{2T_{d}}. \tag{28}\]  
where the transient response frequency \(\omega_{CV}\) is derived as follows:  
\[\omega_{CV}=\frac{1.33-PM}{4T_{d}}. \tag{29}\]  
The design process of the outer loop adheres to the following steps:  
* Specify the target phase margin \(PM\) of the voltage loop;
* Determine the delay value \(T_{d}\) according to the Bode diagram of a current closed loop;
* Set the value of crossover frequency \(\omega_{BV}\) according to (28) and (29);
* Set the value of \(\xi\) to be between 0.01-0.001;
* Shape the controller and loop gain according to (23) and (27), respectively.  
Figure 8: Equivalent block diagram of the voltage loop.