## 3 Proposed FFT Kernel Architecture
### Architecture Modules
#### 3.2.3 Module 3  
Module 3 (CMU) performed intermediate W\({}_{128}\) and W\({}_{64}\) multiplications for the radix-2/8/8 algorithm. According to the \(\pi\)/4 symmetry of twiddle factors [32], W\({}_{64}\) multiplications could be calculated using only eight factors of \(W_{64}^{p^{\prime}}=\exp(-j2\pi p^{\prime}/64)\) and \(p^{\prime}=1,2,\,\ldots,8\), in cooperation with sweeping and sign controls [24; 25]. Considering the six eight-cycle TSs (i.e., TS1-TS6) executed by the second BF8 in Figure 12, the CMU/W\({}_{64}\) multiplication for each cycle within a single TS period could be performed using the eight-path \(W_{64}^{p^{\prime}}\) factors, which is shown using \(p^{\prime}\) parameters in Table 2. The appropriate rescheduling of cycles 2, 4, and 6 (the red arrow in Table 2) could be used to reduce conflict in \(W_{64}^{p^{\prime}}\) multiplication in order to minimize the number of required \(W_{64}^{p^{\prime}}\) constant multipliers. Additional multiplexer controls and registers were introduced to Module 2 to enable rescheduling. For W\({}_{128}\) multiplication, \(\pi\)/4-symmetry check increased the required number of \(W_{128}^{p^{\prime}}\) factors to sixteen (\(p^{\prime}=1,2,\ldots,16\)) compared with \(W_{64}^{p^{\prime}}\). However, the scheme in [33] can be employed to decompose \(W_{128}^{p^{\prime}}\) into a form as Equations (6) and (7) if \(p^{\prime}\) parameter is even or odd. Because \(W_{64}^{k\times 1}\) could be obtained using one of the original \(W_{64}^{p^{\prime}}\) factors, thus, \(W_{128}^{p^{\prime}}\) could be derived as a combined calculation of \(W_{128}^{10\pi 3}\) and \(W_{64}^{p^{\prime}}\). Therefore, only \(W_{128}^{10\pi 3}\) constant multipliers were required to perform W\({}_{128}\) multiplication with the existing \(W_{64}^{p^{\prime}}\) constant multipliers.  
\[W_{128}^{p^{\prime}}=W_{128}^{2k}=W_{64}^{k},\textit{when}\,p^{\prime}\,\textit{ is even} \tag{6}\]  
\[W_{128}^{p^{\prime}}=W_{128}^{2k+1} =W_{128}^{1}W_{64}^{k}=W_{128}^{-1}W_{64}^{k+1} \tag{7}\] \[=W_{128}^{3}W_{64}^{k-1}=W_{128}^{-3}W_{64}^{k+1},\textit{when}\,p ^{\prime}\,\textit{is odd}\]  
As mentioned previously (Figures 9 and 10), six streams of data were accessed between Modules 1 and 3 for W\({}_{128}\) multiplications. To avoid conflict operations associated with access to identical six-stream W\({}_{128}\) factors in the same cycle, a one-sample shift was sequentially applied to the six paths of the CMU-related data accesses of the RAM banks (from Module 1, Figure 9). Figure 13 shows that the architecture of Module 3 allows access to six streams of data from Module 1 for multiplications involving W\({}_{128}\) factors, and eight data paths from Module 2 for multiplications involving W\({}_{64}\) factors (two arrow lines in Figure 13). Several duplicated \(W_{128}^{3}\) and \(W_{64}^{4}\) constant multipliers were used to manage residual conflicting W\({}_{128}\) and W\({}_{64}\) multiplications, such as cycle 4 in Table 2, to perform \(W_{64}^{4}\) multiplication twice. On the basis of our evaluation, the overall CMU (Module 3) covered an area  
Figure 12: Details of operations in TS0-TS9 (Figure 8) for Module 2 (sorting buffer).  
equivalent to 4.18 complex multipliers (structured as four real multipliers and two adders). This process was more area-efficient than the direct approach by using six/eight complex multipliers for six-stream or eight-path operations.