## 1 Introduction  
The ever-growing demand for high-power on/off-grid bidirectional AC-DC converters underscores their pivotal role in modern power and energy systems. As a result, multi-level converters have emerged as a preferred choice across various applications, owing to their superior performance characteristics [1]. These converters offer notable advantages such as enhanced efficiency, reduced \(dv/dt\) stress, and lower output voltage total harmonic distortion, making them indispensable in meeting stringent grid standards [2]. In addition, these converters are often required to operate with non-unity power factors, either to supply (absorb) reactive power to (from) the grid or accommodate loads operating with varying power factor [3]. Multi-level converters are known to be crucial in dual-stage power conversion systems that utilize an intermediate DC voltage link [4, 5, 6, 7, 8, 9]. In such multi-level conversion systems, the DC link is usually implemented using multiple split capacitors [10, 11]. The topology allows power decoupling between conversion stages and permits self-governing converter operation while employing diverse pulse width modulation (PWM) techniques [12, 13, 14, 15, 16, 17, 18]. In fact, 10-100 kVA rated multilevel AC-DCand DC-AC converters have become increasingly prominent across diverse industrial applications [19]. Dual-stage AC-DC and DC-AC converters usually include a short-term energy storage unit (typically realized by a capacitor bank) on the DC side to manage pulsating power components [20], maintain stable operation during power mismatches occurring during transients [21], and comply with hold-up requirements [22]. On the other hand, the capacitance of the DC link is a bottleneck in terms of physical size and reliability [23; 24; 25]. The DC link capacitance value is typically imposed by the hold-up time constraint. In applications where temporary loss-of-mains is tolerable, hold-up time constraint is absent, and it is possible to reduce the value of required DC link capacitance. Numerous approaches for DC link capacitance reduction have been suggested in the literature, e.g., active capacitance reduction [26; 27; 28], AC-side current distortion (up to minimum allowed power quality merit) [29; 30], permitting DC link voltage ripple increase [31; 32], etc. Minimum attainable values of DC link capacitance under active power decoupling, AC-side current distortion, notch-based DC link voltage control, and increased DC link voltage ripple were derived in [33; 34; 32], respectively. A methodology for establishing a baseline for determining split DC link voltages behavior for a family of three-level, three-phase AC-DC and DC-AC power converters was revealed in [35]. The approach is based on the assumption of the third-harmonic-dominated nature of split DC link voltages ripple. The revealed approach focused on converters operating with a unity power factor and a constrained-to-DC zero-sequence component. A subsequent study [36] utilized the outcomes of [35] to derive the lowest feasible values of split DC link capacitance for the above-mentioned family of converters. The impact of operation with arbitrary power factor on the behavior of split DC link voltages was recently explored in [37]. It was shown that operation under non-unity power factor gives rise to significant high-order harmonic content, which aggregates split DC link voltage ripple magnitudes and displaces them relative to mains voltages. Consequently, the assumption of third-harmonic-only content (shown to be accurate in case of unity power factor operation in [35]) does not hold anymore. As a result, the derivation of corresponding analytical expressions is nearly unmanageable. In order to tackle this gap, a numerical solution was adopted in [37] for the derivation of a general expression for normalized split DC link ripple energy and the angle between split DC link voltages and AC-side voltages as a function of the power factor.