# A Review of Cell Operation Algorithm for 3D NAND Flash Memory
## 2 Program Algorithm
### Cell Variation Improvement  
In a 3D NAND flash memory, a gate electrode and an insulator are alternately stacked through a single etching process. Therefore, there is an advantage in that this process increases the manufacturing efficiency and enables continuous bit capacity increase. However, there are disadvantages in that the process causes a difference in the size of the channel hole critical dimensions (CD) between the upper and lower WLs and causes a variation between the hole CDs in the lower WL due to the limitations of the physical etching process [41]. Furthermore, as the number of WL stacks increases, it is necessary to reduce the physical height of the entire total stack to perform the hole etching process at once; thereby, pitch shrinking of gate electrode and insulating layer also become unavoidable engineering processes [10]. When the pitch of the WL layer is decreased, the resistance of individual WLs increases and the upper and lower WL-to-WL capacitances continuously increase [42]. In addition, the fringing field of adjacent WLs increases and the initial Vt is decreased, reducing the program speed [43]. Furthermore, since the charge trap layer is connected over the entire WLs, and because the distance between cells gets closer, the trap layer becomes more vulnerable to retention loss [5]. To solve the above cell variation problem caused by the geometry and process integration of 3D NAND, various programming improvement methods have been proposed. First, to improve the size variation of hole CDs between WLs, different programming pulse widths are applied according to individual WLs [44], as shown in Figure 5. Due to the etching process, the resistance component increases toward the lower WL and the channel capacitance between the gate and the poly-silicon channel tends to decrease as well [42]. This difference between WLs causes loading variation between WLs, and the effective programming pulse width can fluctuate during a given pulse period. As it drops from the upper WL to the lower WL, a longer programming pulse is applied to keep the programming speed uniform among WLs. A WL overdrive scheme was also proposed to overcome the WL RC delay variation caused by non-uniformity of the plug CD [45, 46]. Considering WL RC Loading variation, delivering a verify pulse signal to the target Vt level within a given time is very challenging. The time and voltage offset can be controlled independently for each WL group; however, since too many degrees of freedom burden the entire circuit area of the chip, it may be a good idea to contain WLs in several grouping units considering the location of cells. Due to the increased resistance of individual WLs and WL-WL capacitances by pitch shrink of stacked WLs, it is difficult to increase the programming voltage to the target Vt level, and power consumption increase. To solve this problem, [PERSON] et al. suggested a method of applying the programming pulse by dividing it into two periods [47]. For the first period, selected and unselected WLs are raised to intermediate potential levels below their target levels. Then, the potential of the selected WL is increased by capacitive coupling to adjacent WLs that are also increased to their target level at the same time. Meanwhile, boosting a single WL's potential aided by adjacent WLs can cause a large glitch in the neighboring WLs as well as in the selected WL, and can result in an unintended program disturbance [48]. To resolve this problem, a glitch-canceling discharge scheme and a pre-offset control scheme have been proposed as methods to avoid capacitive coupling [49]. When the selected WL is programmed, the glitch can be generated in the adjacent WLn + 1, which can additionally cause the cell's programed Vt variation. Thus, it is shown that the pass voltage of adjacent WL can be kept constant by preemptively lowering the target pass voltage level of the adjacent unselected WL. As a similar concept to utilize the capacitive coupling, as shown in Figure 6, [PERSON] et al.