## 5 Proposed Quadrature Bandpass Continuous-Time Delta-Sigma ADC
### Quadrature Bandpass Continuous-Time Delta-Sigma ADC Circuit Design
#### 5.2.3 Four-Bit Quantizer  
A delta modulator quantizes the difference between the current input data and the previous output data with a specific feedback gain, which is accomplished by an SAR-based quantizer through analog subtraction during the sampling phase. Conventional SAR-based quantizers are limited to unity feedback gain, as they share reference voltages between the sampling and conversion phases. Implementing non-unity feedback traditionally requires additional voltage references, which increases circuit complexity, area requirements, and static power consumption [33]. The proposed SAR-based quantizer design implements non-unity feedback gain through a capacitive digital-to-analog converter (CDAC) approach. This design achieves its functionality while maintaining a simple architecture and low power consumption by modifying the ratio of two CDACs during the sampling and conversion phases. The system's operation is divided into two distinct phases: sampling and conversion. During the sampling phase, the behavior of the circuit varies depending on the desired feedback gain (\(\alpha\)). When the feedback gain needs to be less than unity, the CDAC used in the sampling phase is designed to be smaller than the one used in the conversion phase, as illustrated in Figure 10(a). In this configuration, the feedback gain is calculated using Equation (5). \[\alpha=\frac{CDAC1}{CDAC1+CDAC2}, \tag{5}\]  
which ensures the gain remains less than one. Conversely, when a feedback gain greater than unity is required, the sampling phase CDAC is designed to be larger than the conversion phase CDAC, as shown in Figure 10(b). For this configuration, the feedback gain is calculated using Equation (6). \[\alpha=\frac{CDAC1+CDAC2}{CDAC1}\quad, \tag{6}\]  
which yields a value greater than one. Both CDACs utilize binary-weighted capacitor arrays with values of 8C, 4C, 2C, and C to achieve precise digital-to-analog conversion. A crucial aspect of the design is the handling of reference voltages. The positive reference voltage (VREFP) must be scaled to \(\alpha\) times larger than that of a conventional SAR-based quantizer to maintain consistent quantization step size. This scaling is accomplished through an adjustable voltage reference generator, which works in conjunction with the CDAC structure. The overall architecture demonstrates an elegant solution to achieving variable feedback gains without requiring complex analog circuitry. By utilizing capacitor ratio modifications and an adjustable reference voltage generator, the design maintains high performance while keeping power consumption low. The binary-weighted capacitor arrays in both CDACs ensure precise conversion, while the flexible feedback gain adjustment through CDAC ratios provides versatility in application. This approach to implementing non-unity feedback gain represents a significant advancement in SAR-based quantizer design, offering a power-efficient solution that maintains performance without sacrificing simplicity. The design's ability to accommodate both greater-than-unity and less-than-unity feedback gains through the same basic architecture demonstrates its versatility and efficiency. The layout in Figure 12a shows a binary-weighted capacitor array design for the CDAC that incorporates an important design principle: the use of identical unit capacitors (C\({}_{\text{U}}\)) as building blocks. Unlike traditional binary-weighted implementations that vary the physical capacitor sizes, this design achieves binary weighting through parallel combinations of identical unit capacitors. Specifically, segments are created by connecting multiple identical C\({}_{\text{U}}\)s in parallel to achieve binary scaling (8C\({}_{\text{U}}\), 4C\({}_{\text{U}}\), 2C\({}_{\text{U}}\), and C\({}_{\text{U}}\)). This implementation approach preserves the area efficiency of binary weighting while borrowing the matching advantages typically associated with thermometer coding.