## 2 Materials and Methods  
For integrating with other GaN-based components and interconnects [14], Cr/Cu/Ti/Au, Cr/Cu/Ni/Au, Cr/Cu/Cr and Cr/Al/Ti/Au were investigated to fabricate on-chip spiral inductors on sapphire substrate in this work. Details about these metallization systems are listed in Table 1.  
In these metal multilayers, Cu and Al were chosen as conductor layers. However, they were apt to be oxidized during the water rinse or exposing to moist air. In addition to increasing the resistance of the metals, the formed Cu oxides would cause degradation in reliability due to the weakened adhesion at the Cu interface, and tended to flake off. For that matter, an inert film of Au as a protective cap layer was covered on the conductor layer to reduce the oxidation. Cr was also interposed as a top overcoating layer in Cr/Cu/Cr multilayer relying on the insulating film formed from the oxidization of chromium. Further, to avoid the interdiffusion of Cu (or Al) with Au, which forms alloys that deteriorate electrical properties, a barrier layer of Ti or Ni was essential. The fabrication process of the inductors is shown in Figure 1a. The process started with cleaning the sapphire wafers in a 3:1 mixture of sulfuric acid (H\({}_{2}\)SO\({}_{4}\)) and hydrogen peroxide (H\({}_{2}\)O\({}_{2}\)), following with a deionized water cleaning. After that, ground-signal-ground (GSG) RF test patterns and underpass lead metal lines were fabricated by a combination of standard photolithography, metallization and lift-off processes. In this step, 70/40/200 nm Cr/Pt/Au (labeled as M1) was deposited by an E-beam evaporator. Then, a 600 nm SiO\({}_{2}\) insulation layer was deposited by plasma-enhanced chemical vapor deposition (PECVD), and the SiO\({}_{2}\) film off the underpass lead line was removed after photolithography and re \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**Metal Multilayers**} & \multicolumn{6}{c}{**Material and Thickness (nm)**} & \\ \cline{2-9}  & **Adhesive Layer** & **Conductor Layer** & **Barrier Layer** & **Protecting Layer** & **PVD Technique** \\ \cline{2-9}  & **Cr** & **Cu** & **Al** & **Ni** & **Ti** & **Au** & **Cr** & \\ \hline Cr/Cu/Ti/Au & 50 & 1700 & — & — & 200 & 50 & — & \multirow{2}{*}{\
\begin{tabular}{c} Sputtering followed \\ by evaporation \\ Evaporation \\ Evaporation \\ Evaporation \\ (three-step method) \\ \end{tabular} } \\ \cline{2-9}  & **Cr/Al/Ti/Au** & 50 & — & 1700 & — & 200 & 50 & — &
\begin{tabular}{c} Sputtering followed \\ by evaporation \\ Evaporation \\ Evaporation \\ (three-step method) \\ \end{tabular} \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Details about materials, thickness and deposition techniques of metal multilayers. active ion etching (RIE). Finally, the second metal multilayer (labeled as M2) was fabricated as spiral coils. For Cu-based spiral coils, a bilayer of Cr/Cu was sputtered initially. Sequentially, Ni/Au, Ti/Au or Cr layers were evaporated to protect the sidewalls of the underlying pattern [15]. For Al-based spiral coils, Cr/Al/Ti/Au was evaporated in sequence. Figure 1b shows the optical and microscope images of spiral inductors, respectively. A series of inductors were fabricated with various layout parameters including number of turns (\(N\)), spiral metal line width (\(W\)), spacing between turns (\(S\)), inner radius (\(R_{in}\)), total thickness of metal multilayer (\(t_{mc}\)), and thickness of silicon dioxide insulation layer (\(t_{ox}\)). Analysis on these parameters lays a foundation for establishing corresponding model library and provides an insight into the design and optimization of the inductors on sapphire.