## 3 Results and Discussion
### Real-World Device Tests
The mean values of the voltages and their standard deviations for each transistor pair are shown in Table 3.  
Figures 12-14 show the measurements of \(U_{DC}\) at R0 during active operation of the amplifier for an input signal frequency of 1 kHz--for the output power at an R0 of 1, 10, and 15 W, respectively. The mean values of the voltages and their standard deviations for these cases are shown in Table 4.  
The higher values of \(U_{DC}\) in comparison with those from the simulation studies can be explained, among other things, by the IRFP transistors not being paired in terms of electrical parameters but only being matched in physical complementary pairs. IRFP transistors are voltage-controlled transistors. The different gate opening voltages of IRFP transistors translate directly into differences in the pair's resting currents. Consequently, the complementary pair is unable to develop the ideal symmetrical voltage to power itself. In the case in question, the two resistances controlled by the gate-opening voltage cyclically seek to deposit exactly half of the asymmetrical voltage on each other, which is only possible in an ideal scenario. Furthermore, the processing path is affected by interference and component noise, which further increases the value of \(U_{DC}\) at R0. However, it should be noted that in none of the cases tested did the modulus of voltage \(U_{DC}\) exceed 2.5 mV. Figure 11: Voltage \(U_{DC}\) measured at load R0 with input capacitors C7 and C8 shorted to ground for: (a) \(140/9140\); (b) \(140/9240\); (c) \(240/9140\); and (d) \(240/9240\) transistor pairs. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Parameter of \(U_{DC}\)** & **140/9140** & **140/9240** & **240/9140** & **240/9240** \\ \hline mean value (V) & \(-9.04\times 10^{-6}\) & \(-6.15\times 10^{-8}\) & \(9.04\times 10^{-6}\) & \(8.68\times 10^{-6}\) \\ standard deviation (V) & \(2.64\times 10^{-5}\) & \(2.33\times 10^{-5}\) & \(2.26\times 10^{-5}\) & \(3.21\times 10^{-5}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Numerical data for Figure 11.  
Figure 12: Voltage \(U_{DC}\) measured for 1 W of output power at load R0: **(a)** 140/9140; **(b)** 140/9240; **(c)** 240/9140; and **(d)** 240/9240 transistor pair. Figure 13: Voltage \(U_{DC}\) measured for 10 W of output power at load R0: **(a)** 140/9140; **(b)** 140/9240; **(c)** 240/9140; and **(d)** 240/9240 transistor pair. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Working** & & & & & \\
**Conditions** & **Parameter of \(U_{DC}\)** & **140/9140** & **140/9240** & **240/9140** & **240/9240** \\ \hline
1.6 V/1 kHz/1 W & mean value (V) & \(2.14\times 10^{-4}\) & \(1.92\times 10^{-4}\) & \(2.05\times 10^{-4}\) & \(2.66\times 10^{-4}\) \\  & standard deviation (V) & \(2.26\times 10^{-5}\) & \(2.59\times 10^{-5}\) & \(2.67\times 10^{-5}\) & \(2.47\times 10^{-5}\) \\ \hline
5.0 V/1 kHz/10 W & mean value (V) & \(7.33\times 10^{-4}\) & \(8.60\times 10^{-4}\) & \(7.55\times 10^{-4}\) & \(8.62\times 10^{-4}\) \\  & standard deviation (V) & \(2.76\times 10^{-5}\) & \(5.78\times 10^{-5}\) & \(2.61\times 10^{-5}\) & \(2.61\times 10^{-5}\) \\ \hline
6.3 V/1 kHz/15 W & mean value (V) & \(1.79\times 10^{-3}\) & \(2.23\times 10^{-3}\) & \(1.91\times 10^{-3}\) & \(2.36\times 10^{-3}\) \\  & standard deviation (V) & \(3.21\times 10^{-5}\) & \(5.07\times 10^{-5}\) & \(2.97\times 10^{-5}\) & \(3.63\times 10^{-5}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Numerical data for Figures 12–14. An important assumed property of the LF amplifier being tested is its self-balancing capability, which is defined as the ability to (a) bring the value of \(U_{DC}\) at R0 to a minimum and to (b) maintain the minimum value of \(U_{DC}\) during changes in the DC operating conditions of the system caused by changes in supply voltage. Sudden changes in supply voltage result in changes in the resting currents of the BJT and MOSFET transistors within the circuit.