## 3 Parallel ARIA Implementation
### Parallel ARIA Implementation on GPU
```
1//ExtendedSboxcodeusingsharedmemory
2 constantuint32_ts1[256]={...};
3...
4__global_Aria_device(in,out,dev_s1,...){
5__shared_uint32_tshared_s1[256][N];
6...
7 for(inti=threadIdx.x;i<256;i+=blockDim.x){
8 for(intj=0;j<N;j++){
9 shared_s1[threadIdx.x][j]=dev_s1[i];
10...
11}
12}
13...
14}
15__host_Aria_host(in,out,key){
16 roudnkey_gen(key,rk);
17...
18 cudaMalloc(&dev_s1,sizeof(uint32_t)*256);
19...
20 cudaMencpy(s1,dev_s1,sizeof(uint32_t)*256);
21
22 Aria_device<<block,thread>>>(in,out,dev_s1,...);
23...
24}
```

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The performance difference from previous studies clearly shows the large difference due to the difference in processors. Compared to the reference C implementation, which is not an assembly-optimized implementation, the difference is about 60\(\times\). This means that hardware differences lead to large performance differences. In 4-plaintext of our implementation, the performance was 1.73 cpb, which was 2.76\(\times\) higher than that of reference implementation. The 16-plaintext showed a performance of 0.57 cpb, and 8.73\(\times\) improved performance compared to reference implementation. It also showed 3.04\(\times\) better performance compared to 4-plaintext. The result shows that the highly optimized ARIA block cipher in a parallel way can achieve much higher throughput than that of sequential implementation. In addition, the same ARMv8 architecture was used, but the effect of the operating frequency was investigated by measuring the performance in an environment with different operating frequencies. Performance was measured on an Apple IPad Air (3 rd) with an A12 Bionic chip. The operating frequency speed of Apple M1 is 3.2 Ghz, whereas in A12 it is 2.49 GHz. As a result, it shows 1.6\(\times\) and 1.25\(\times\) higher performance in M1 with high operating frequency. From this, it can be seen that the higher the operating frequency, the better the performance. ### Evaluation on GPU Implementation

In this section, we show the performance of ARIA block cipher implementations depending on various types of memory in the GPU. As with the ARMv8 performance evaluation, the difference in key length is only the number of rounds, so we measured performance based on 128-bit key length. Factors that affect GPU implementation performance include number of threads and number of blocks. Performance measurements were taken while correcting for these factors. The Nvidia GeForce GTX 3060 laptop GPU was used for the testing. It was implemented in the Visual Studio, and the CUDA 11.8 Runtime template was used. Performance is presented in several tables for more convenient performance comparison. The size of the input data for each implementation is (number of blocks \(\times\) number of threads \(\times\) block size). That is, if the number of blocks is 1024 and the number of threads is 32, the size of the input data is 0.5 MB (1024 \(\times\) 32 \(\times\) 16). The input data are used as a random value. Our goal is to find the optimal implementation environment (e.g., type of memory, number of threads, number of blocks). The Roundkey was used by storing it in the GPU's constant memory. When all threads refer to the same memory, the Roundkey is stored in constant memory because it is better for performance to use constant memory. First, for performance comparison according to memory types, the number of blocks was fixed to 1024 \(\times\) 32 and the number of threads to 256 to show the implementation performance according to the type of memory. Shared[256] is an implementation of Listing 2 that uses Sbox tables copied to shared memory. Shared[4][256] and Shared[256][4] are an implementation of Listing 3 that uses Sbox tables copied to shared memory. The performance results are shown in Table 3.