## 5 Digital Modulation and Demodulation Circuits
### Receiver
#### 5.3.2 BPSK Demodulator Core  
The essential element of the receiver is the BPSK demodulator core shown in Figure 12, which demodulates the rectangular wave input signal based on a compact digital circuit. It therefore replaces analog circuits such as mixers and baseband filters, which can barely be realized with a small form factor and low power consumption using discrete components, while their digital counterparts can be synthesized for a small-scale and low-power FPGA. Furthermore, it differs from fully digital receivers in the sense that it does not sample the analog signal with a multi-bit, but just a single-bit analog-to-digital converter, omitting another classical and energy intensive component of a receiver circuit. In brief, it can be categorized as a direct-RF sampling receiver with a single-bit ADC and without the demodulation path of the quadrature component [33]. Prior to down-conversion, the local carrier provided to the mixing stage must be synchronized to the incoming carrier. The initial carrier burst phase of a packet will be used for this purpose, which is processed by the carrier synchronizer stage of Figure 12. A sample clock of 108.48 MHz, i.e., eight times the carrier frequency of 13.56 MHz, acquires the input RF signal _rf_in_ into a two-stage shift register in order to detect rising edges of the signal. Upon detection, a three-bit time step counter will be synchronized so that an output counter value of 0 coincides with the sampling clock period in which the rising edge of _rf_in_ occurs. A decision stage maps the time step counter values 0 to 3 to a logic '1' of the synchronized clock signal and 4 to 7 to a logic '0'. If the rising edge of the incoming RF signal and the anticipated period of a rising edge fall together, _rf_in_ and the local carrier are synchronized for the given period. An additional circuit block counts the number of subsequent synchronized carrier periods; after more than five such cycles in series, the local carrier is considered to be synchronized and further resynchronization is suppressed until the reception is interrupted (completed packet transfer or loss of RF input signal). Figure 12: Schematic diagram of the BSPK demodulator core with sub-elements to perform carrier synchronization, down-conversion (mixing and filtering) as well as symbol mapping (comparator). The mixing process of incoming RF signal and local carrier is generally supposed to result in a large output signal of the mixer if both are in phase, while a 180\({}^{\circ}\) phase shift shall result in a small output signal. Considering the rectangular wave, the output signal shall be increased if both signals share the same logic level, which is implemented by an XNOR operation (with the logical negation \(\
eg\) and the XOR operator \(\oplus\)):  
\[s_{\text{m}}(t)=\
eg(s_{\text{rf\_in}}(t)\oplus s_{\text{carrier}}(t)), \tag{27}\]  
As this signal can show a significant amount of transient toggling during one period, its time-averaged (low-pass filtered) version should be considered as a measure of the phase difference \(\phi_{\text{data}}\) of the mixed signals:  
\[s_{\text{o}}(t)=\frac{1}{T_{0}}\int_{0}^{T_{0}}s_{\text{m}}(t)dt=1-\left|\frac {\phi_{\text{data}}}{\pi}\right|. \tag{28}\]  
In a discrete-time implementation, this translates to  
\[s_{\text{o}}[n] =\sum_{i=0}^{7}s_{\text{m}}[n-i] \tag{29}\] \[=s_{\text{o}}[n-1]+s_{\text{m}}[n]-s_{\text{m}}[n-8], \tag{30}\]  
where the constant \(1/T_{0}\) was omitted and where the equation was transformed to yield a recursive moving average filter. In the implementation, this low-pass filter is realized by a 9-bit shift register and a counter, which either increments its register value if the incoming bit \(s_{\text{m}}[n]\) is '1' and the bit being removed from the filter \(s_{\text{m}}[n-8]\) is '0', decrements for the opposite case and stays constant for all other cases.