## 2 Materials and Methods
### CAN Peripheral Interrupt Synchronization  
Two different converter synchronization techniques have been tried in this work. The first one relies on the response of the CAN communication peripheral to a specific converter start-up message issued by the master controller. Robustness and versatility of the CAN protocol coexist with a big limitation in applications with very strong real time constraints, like in parallelization of VSCs without filters, where precise initial synchronization is needed to ensure the system integrity. CAN ensures a synchronization process at level 1 of the ISO/OSI stack that is used to compensate for the natural drift of local oscillators. This resynchronization process can lengthen or shorten the bit time at fixed steps determined by peripheral clock frequency, that in most cases is much lower than the system clock frequency. The CAN controller used in these tests, for example, can work at 45 MHz maximum frequency so that, with the limitation of phase segments length, bit time can be shortened or lengthened by 22 ns. In many cases due to noisy environment, the peripheral cannot work at this maximum speed so, the sampling process of bits in the CAN packet, improves uncertainty at lower speed like as demonstrated in this test.  
The on board CAN peripheral (bxCAN) offers an hardware HLP (Higher Layer Protocol) at the data link level of the ISO/OSI stack managing:  
* Transmission and reception of incoming messages;
* Construction of bit time (Time Quanta, Sync and Phase segments);
* Interrupt management registers;
* Diagnostic information.  
The reception can be done using an input filter to store particular message IDs (in this case the converter start-up message) in particular FIFO stacks of the CAN peripheral. The presence of a message in a FIFO can cause a message pending (MP) interrupt, signaling the MCU that an incoming message should be read and causing a jump to the appropriate interrupt service routine (ISR). The ISR, in turn, starts the PWM, configured to generate a 100 us period.  
The master unit periodically sends a starting message so that repeated tests of residual delay on first rising PWM edges can be done.  
Due to the bit stuffing property of the CAN protocol, a valid message cannot have more than five consecutive bits with the same logical value except for the end of frame (EOF) field, which is composed by seven recessive bits. This makes it easy to recognize the acknowledge (ACK) that can be used as a common synchronization point for the PWM generation. The time period between the last rising edge of the CAN packet (ACK) (Figure 3) and the first rising edge of the PWM can be divided into four different subperiods:  
1. Validation;
2. Peripheral FIFO register signaling;
3. Interrupt management (ends with first instruction of ISR);
4. PWM starting sequence.  
It is clear that the first subperiod is bit-rate-dependent, because the message is valid for the receivers, if there is no error until the last but one bit of the EOF [23]. The last two subperiods are inserted by the MCU that is peripheral-frequency-independent, so it is logical to consider the sum of these periods fixed and deterministic because all units are subjected to the same calculation load.  
\begin{table}
\begin{tabular}{c c c c c c} \hline
**Units under** & **N (Number** & **Average [s]** & **Std. Dev.** & **Minimum** & **Maximum** \\
**Test** & **of Tests)** & **Average [s]** & **Std. Dev.** & **[s]** & **Maximum** \\ \hline
2 \(\longrightarrow 1\) & 303 & 20.61 & 395.3 & 19.28 & 21.15 \\
3 \(\longrightarrow 1\) & 338 & 7.79 & 161.5 & 7.49 & 8.24 \\
3 \(\longrightarrow 2\) & 314 & 5.59 & 79.91 & 5.39 & 5.78 \\ \hline \end{tabular}
\end{table}
Table 1: Alignment test results.