# Configurable Hardware Core for IoT Object Detection
## 5 Results
### FPGA Resource Utilization  
To illustrate the configurability of the accelerator, we implemented several designs with a different number of cores and determined the occupation of FPGA resources (see results in Table 5).  
The configurations with more lines of cores were more expensive since each line adds an output buffer. For example, configurations \(8\times 4\) and \(4\times 8\) have the same number of cores, but the former needs more BRAMs and LUTs.  
All configurations assume the same size for the on-chip memories to store IFMs and weights. If memory is available, these can be increased, which may improve the execution time. So, the occupation of BRAMs in Table 5 represents a minimum, assuming 32 KBytes of memory for each IFM buffer and 8 KBytes of memory for each weight memory.  
The last two configurations (\(4\times 8\) and \(4\times 4\)) could be implemented, for example, in a smaller ZYNOQ7010 SoC FPGA, which shows the scalability of the architecture to lower-density FPGAs.  
The configuration with 13 lines of cores is usually preferred since the size of the feature maps considered by YOLO are multiples of 13. The other configurations can be used, but there will be a degradation in performance efficiency since in some iterations of the algorithm, some cores are not used. For example, running a feature map of size 26 in the architecture configured with eight lines of cores would need four iterations, and in the last iteration only two lines of cores would be running.  
The accelerator was mapped into the ZYNOQ7020 FPGA with quantizations of 8- and 16-bit. The 16-bit configuration was mainly considered for state-of-the-art comparison. Table 6 presents FPGA resource utilization of the accelerator for both configurations.  
In the low-cost ZYNOQ7020 FPGA, the design is mainly constrained by the number of DSPs and BRAMs. The high utilization ratio of these hardware modules influences the operating frequency due to routing. Since a single DSP can implement two \(8\times 8\) multiplications, the 8-bit solution doubles the number of MACs. It is possible to reduce  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Resource** & \multicolumn{2}{c}{**ZYNOQ7020**} \\ \hline \hline Datapath & 16 & 8 \\ \hline LUTs & 27,454 & 33,346 \\ \hline
36 kB BRAMs & 120 & 120 \\ \hline DSPs & 208 & 208 \\ \hline \hline \end{tabular}
\end{table}
Table 6: Resource utilization in a ZYNOQ7020 FPGA.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Cores** & **LUTs** & **BRAMs** & **DSPs** \\ \hline \hline \(13\times 8\) & 33,346 & 120 & 208 \\ \hline \hline \(13\times 4\) & 20,356 & 112 & 104 \\ \hline \(13\times 2\) & 13,656 & 108 & 52 \\ \hline \(8\times 8\) & 20,746 & 80 & 128 \\ \hline \(8\times 4\) & 12,698 & 72 & 64 \\ \hline \(4\times 8\) & 10,588 & 48 & 64 \\ \hline \(4\times 4\) & 6528 & 40 & 32 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Resource utilization of the accelerator for 8-bit datawidth, four MACs per core, and different numbers of cores.  
the number of BRAMs of the 8-bit solution, but a higher number of BRAMs increases the number of layers that can benefit from the ping-pong technique of memories. Therefore, both solutions use the same number of memories.