## 4 Results and Discussion
### Synthesis Results
However, the array multiplier can be efficiently optimized, as shown in [10; 33], for large multiplications, as required in floating-point multipliers. Owing to the hierarchically designed structure shown in Figure 4, the Wallace tree multiplier is faster than the array multiplier because of the parallel reduction in bits in the PP layers by HAs and FAs. However, physical design implementation becomes more complex as the word length of the multiplier increases. This can be attributed to the interconnection wires and logic levels used, as listed in Table 4. In addition, by analyzing its architecture, the number of FAs and HAs used in the initial stage of PP tree reduction did not reduce the number of PPs. Several authors have attempted to improve the performance of Wallace multipliers [32; 34]. \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Size**} & \multicolumn{2}{c}{**Size of Final Adder**} & \multicolumn{2}{c}{**Logic Levels**} \\ \cline{2-5}  & **Wallace Tree** & **Radix-4 Booth** & **Wallace Tree** & **Radix-4 Booth** \\ \hline
11 & 16 & 18 & 5 & 4 \\
16 & 25 & 27 & 6 & 5 \\
24 & 40 & 42 & 7 & 6 \\
32 & 55 & 58 & 8 & 6 \\
53 & 96 & 99 & 9 & 7 \\
64 & 117 & 120 & 10 & 8 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Synthesis results from Alliance based on 350 nm CMOS technology. Figure 7: Delay of different multipliers based on Alliance 350 nm CMOS technology. Because the radix-4 Booth algorithm can reduce the number of PPs by half, as shown in Figure 5, it is another type of fast multiplier with low area consumption. Moreover, the Booth multiplier can be implemented in 26 distinct configurations, including radix-2, radix-4, and radix-8, among others. However, these higher radix configurations necessitate additional logic to implement Booth encoding. Radix-4 Booth is widely used to improve the performance of multipliers [7; 8]. However, this is the most complex architecture for implementation in VLSI design. Alliance EDA tools lack tools for estimating the power consumption of VLSI designs. The overall power consumption of an integrated circuit can be defined as  
\[P=\alpha{C_{L}}{V_{DD}}^{2}f+V_{DD}I_{l_{eakage}} \tag{2}\]  
where the first and second terms represent the dynamic and static power consumption, respectively. \(\alpha\) is the switching activity parameter, \(C_{L}\) is the total capacitance load, \(V_{DD}\) is the supply voltage, \(f\) is the operating frequency, and \(I_{leakage}\) is the leakage current. According to (2), dynamic power consumption can be reduced by minimizing the switching activity. As shown in Table 3, the array multiplier is anticipated to have significant power consumption due to its large number of transistors and extended critical path. By contrast, the Wallace multiplier is expected to consume less power than the array multiplier. Most of the power dissipation in the Wallace tree multiplier occurs during PP tree reduction. However, the number of transistors and transitions is reduced because of the accelerated PP reduction in smaller multipliers [17; 18]. As the word length increases, power consumption may increase significantly because of the increased glitching from complex wiring routing [12]. The radix-4 Booth algorithm involves operations for the coefficient \(b_{k}\) of Equation (1) with values of \(\pm 1\) and \(\pm 2\), which are generated by the encoders, as shown in Figure 5. This complexity is expected to result in the highest power consumption [7; 17].