# Scalable Photonic Digital-to-Analog Converters
## 2 The Proposed Parallel PDAC Architecture  
A schematic diagram of the proposed architecture is shown in Figure 2. The system comprises ring resonator-based modulators, phase shifters (PS), and multimode interference couplers (MMIs). The MRMs process digital input signals by performing amplitude modulation on the continuous-wave (CW) carrier optical signal. This modulation is achieved by utilizing the change in the refractive index due to carrier depletion, allowing fast and efficient modulation while occupying a small footprint on the photonic integrated circuit (PIC). In the chip layout design, MRMs are directly sourced from the Advanced Micro Foundry (AMF) process design kit (PDK) library [25]. Low-speed thermo-optic phase shifters are employed to ensure constructive interference for the coherent coupling of modulated optical signals. The MMIs function as 3-dB splitters for the input CW optical signal (weighting scheme) and subsequent combiners for the modulated coherent optical signals. The weighting scheme relies on each 3-dB MMI splitter allocating 50% of its input intensity to the connected MRM and phase shifter (PS) branch, with the remainder directed to the next splitter for lower-order bits. This way, the monotone carrier signal from a single CW light source is exponentially distributed among the modulator branches, starting from the most significant bit (MSB) on the left and successively towards the least significant bit (LSB) on the right. In this topology, the PDAC output is given by the interference happening at the summation of the branches. The dynamic range is the same as the dynamic range of an individual MRM (all MRMs are designed to be identical). Under the idealized assumption of MRM having infinite ER, the PDAC output is linear in field and quadratic in intensity [18]. By reducing the MRM ER, the PDAC output intensity becomes more and more linear, but at the cost of reduced dynamic range. To operate efficiently at a designated carrier frequency, it is imperative to synchronize all resonances of the ring modulator. However, the inherent sensitivity of ring resonators to fabrication imperfections, such as variations in waveguide width and thickness, and mismatches in the ring-bus gap, poses a challenge. These imperfections result in disparate resonance wavelengths among the ring modulators. To overcome this challenge, each MRM incorporates an electrical heater, facilitating the tuning of resonance frequencies to align with the desired carrier frequency. One of the advantageous features of this PDAC topology is its modular design, allowing seamless accommodation of any desired number of parallel bits, with the pragmatic limit that the least significant bit remains distinguishable, assuming the photodiode in use is sufficiently sensitive. This scalability is achieved by the straightforward addition of an extra module (marked by a dotted box in Figure 2: a branch consisting of two MMIs, an MRM, and a PS), requiring no change to the earlier branches. Thus, the maximum number of bits that can be accommodated is constrained by factors such as the signal-to-noise ratio or the bit error rate. Several sources contribute to the noise in this system, including resonance drift caused by temperature fluctuations, amplifier noise in the modulating RF signal, and the photonic shot noise originating from the photodiode. As the optical signal intensity decreases for subsequent bits, there comes a point where the signal power in the LSB branch becomes comparable to the noise level. This phenomenon imposes limitations on the scalability of the proposed PDAC architecture. Assuming that a commercial VCSEL is used as the CW light source that emits 10 dBm optical power at the operating temperature, 1 dB insertion loss can be considered for a standard edge coupling or photonic wire bonding to the PDAC chip.