## 6 Various Criteria for Assessing the Power Quality and Efficiency of the Studied System
### Energy Efficiency: Power Losses  
Generally, there are two types of losses in PWM power electronics converters: conduction losses \((P_{cond})\) and switching losses \((P_{swi})\), with switching losses occurring during the transitions from \(t_{swi,on}\) to switch-on and from \(t_{swi,off}\) to switch-off. These losses are expressed as follows [75]:  
\[P_{cond,Sij}=\frac{V_{on,Sij}l_{on}l_{on}}{T_{s}} \tag{22}\]  
\[P_{swi}=\left[\frac{1}{2}v_{swi}i_{swi}\left(t_{swi,on}+t_{swi,off}\right) \right]\times f_{swi} \tag{23}\]  
where \(i_{swi}=l_{on}\) is the instantaneous phase current, \(v_{swi}\) is the switch-off voltage, \(t_{swi,on}\) and \(t_{swi,off}\) are the switch-on and switch-off times, \(V_{on,Sij}\) is the voltage drop, \(t_{on}\) is the on-time, and \(f_{swi}\) is the switching frequency.  
It is well established that, in power semiconductor devices, power losses due to switching are directly proportional to the switching frequency. These switching-related losses occur during the turn-on and turn-off phases of the device and are mainly influenced by the time over which the switching voltage and current rise and fall, respectively [165]. In other words, as the switching frequency increases, the power losses generated by switching also increase. These losses are primarily determined by the variations in voltage and current during these phases.  
\begin{table}
\begin{tabular}{c c As an example, Figure 22 illustrates phase A of an inverter arm. In this diagram, components \(S_{ij}^{+}\) and \(S_{ij}^{-}\) represent the upper and lower switches of the arm, while \(D_{A}^{+}\) and \(D_{A}^{-}\) are the associated antiparallel diodes. Furthermore, Figure 23 shows the voltage across the switch and the antiparallel diode, as well as the current flowing through them and the resulting power losses, particularly when \(I_{a}>0\).  
However, the introduction of DTLIs into a system can negatively impact its overall efficiency, primarily due to the increased power losses they generate. In the context of our configuration, it is important to highlight that total switching losses are significantly higher, potentially reaching up to twice the levels observed in conventional systems [97].  
* Power loss reduction  
To increase the efficiency of DTLI systems, various modulation strategies have been explored in the literature. In references [91; 151; 152; 166], the sub-hexagonal center PWM (SHCPWM) modulation scheme, based on PWM pulse shifting, has been developed to mitigate switching losses. This method involves sequential switching of the two inverters, effectively halving switching losses compared to conventional DTLI configurations. Additionally, SHCPWM avoids the generation of unwanted bearing currents [91]. However, it is limited by a restricted set of switching states and requires complex PWM pulse reordering, which can be computationally intensive [91; 151; 166; 152].  
Another approach to minimizing switching losses is discontinuous pulse width modulation (DPWM), as described in [118; 167; 168]. DPWM holds certain power semiconductors in the ON or OFF position over specific intervals. This technique is more efficient than space vector PWM (SVPWM) for high-power, high-frequency switching applications [59]. Furthermore, different DPWM variants, such as DPWM 30\({}^{\circ}\), 60\({}^{\circ}\), and 120\({}^{\circ}\), have been developed, which reduce switching losses by an average of 33% by avoiding switching  
Figure 23: Current through inverter switches and voltage drop between them in phase branch A.  
Figure 22: Phase A of the inverter branch.  
transitions near phase current peaks [169]. DPWM also accounts for the phase difference between current and voltage, even when the power factor is considered [170].