# Transformer: An OS-Supported Reconfigurable Hybrid Memory Architecture
## 3 Design and Implementation
### Architecture Dynamic Conversion  
Transformer organizes both NVM and DRAM in a parallel architecture physically. The NVM and DRAM are both visible to the operating system as main memory. Transformer also supports the hierarchical hybrid memory architecture logically via maintaining a DRAM-to-NVM address mapping in the OS. It can dynamically convert one architecture into another architecture according to the memory hotness. To construct the hierarchical architecture, the DRAM-to-NVM address mapping is essential maintained by a hash table. The key and value of the hash table entry are the physical address of the DRAM page and the corresponding NVM page. The mapping table entry uses a flag field to distinguish whether the entry is valid or not. To describe the reconfiguration function more clearly, We list key notations and programming APIs in Table 1. Transformer is a parallel memory architecture by default. At first, the _total_pages_, _hot_pages_ and _type_ are initialized as 0. When the kernel thread starts the monitoring, it not only records the number of page accesses, but also calculates the proportion of hot pages. Transformer dynamically reconstructs the hybrid memory architecture according to the proportion of _hot_pages_. When the \"access\" or \"dirty\" bits of a page is set during a period of sampling, the _total_pages_ increases by 1. If the number of access counts exceeds the threshold of hotness, the _hot_pages_ will increase by 1. When _total_pages_ increases, the ratio between _hot_pages_ and the _total_pages_ is still lower than the threshold of hierarchical architecture; this implies that the monitored process accesses memory pages roughly uniformly. The architecture should behave as the parallel architecture. It will check the _type_ and do nothing if it is just a parallel architecture. Otherwise, it will shift from the hierarchical architecture to the parallel architecture. The DRAM-to-NVM mappings should be removed in the hash table, and dirty pages that have been cached in the DRAM should be written back to NVM. In contrast, it establishes a hash table for storing the physical address mapping between NVM and DRAM pages when the parallel hierarchical architecture is converted into the hierarchical architecture. Transformer keeps monitoring the _hot_pages_ ratio and dynamically converts itself into an appropriate architecture for applications. The pseudo-code of architecture dynamic conversion is shown in Algorithm 1. \begin{table}
\begin{tabular}{l l} \hline _Total_Pages_ & The Total Number of Memory Pages Accessed during the Program’s Execution \\ _hot_pages_ & The number of pages whose access counts exceed the hotness threshold \\ _T\({}_{hierarchy}\)_ & The threshold for converting the memory architecture \\ _type_ & Current memory architecture: 0 and 1 denote parallel and hierarchical, respectively \\ _nvmPage_Free()_ & API for releasing NVM pages \\ _mapLink_Create()_ & API for creating a mapping between NVM and DRAM pages \\ _mapLink_Free()_ & API for releasing the mapping between NVM and DRAM pages \\ _mapTable_Create()_ & API for creating the address mapping table \\ _mapTable_Free()_ & API for releasing the address mapping table \\ _tag_Modify()_ & API for updating tags in the mapping table \\ \hline \end{tabular}
\end{table} 
Table 1: Notations and APIs.