## 3 Optimized Dual-Channel Data Storage and Access Method
### De-Cross Access and Caching Method
#### 3.3.2 Azimuth Data Access and Caching  
In the azimuth access mode, azimuth lines are accessed one by one according to the order in the SAR data matrix. As the burst length is eight, each burst transmission can obtain the data of four azimuth lines. Since a sub-matrix datum with a size of \(N_{a}\times N_{r}\) is mapped to a row of DDR3, \(N_{r}\) data in each row of DDR3 are on the same azimuth line, and the data of four adjacent azimuth lines are cross-stored in DDR3. When reading the data, read the \(4N_{r}\) data in one row of DDR3 (the \(4N_{r}\) data belong to the four consecutive azimuth lines in the SAR data matrix), and then jump to the next row to read the remaining data on these four azimuth lines until all data on these four lines have been read, as shown in Figure 11. The distance between the addresses of the two adjacent burst transmissions of the same azimuth line is \(2N_{a}\) columns. After reading a row, jump to the corresponding row to read the remaining data in this azimuth direction until the data of these four azimuth lines have been read. When the azimuth data are written back to DDR3 after being processed by the computing unit, the same address jump method is used.  
Since the four adjacent azimuth lines are cross- stored in DDR3, among the eight data obtained by each burst transmission, each pair of adjacent data belongs to a different azimuth line. When performing data caching, data needs to be  
Figure 11: Data access address change method in azimuth direction. (**a**) The four azimuth lines to be accessed in the SAR data matrix; (**b**) the physical addresses of the four azimuth lines to be accessed in DDR3 (each cell represents eight burst transmission data in DDR3; the red dotted line represents the data access sequence in DDR3).  
Figure 10: De-cross access and caching in range direction.  
RAM1, RAM2 and RAM3, as shown in Figure 12. Therefore, that the data storage order in the cache RAMs is consistent with the SAR data matrix, which is convenient for the processing engine.  
Taking a 16,384 \(\times\) 16,384 SAR matrix as an example, the size of the sub-matrix is 32 \(\times\) 32. According to the above method, 128 data must be read in each row for range data access mode or for azimuth data access mode in DDR3. Thus, each row needs to complete 16 burst data transmissions, before proceeding to the next row. As the matrix block three-dimensional mapping method proposed in Section 3.1 uses the priority access feature of cross-bank data in DDR3, there is no interval between the precharge command and the next active command, so there is no \(t_{RP}\) in the efficiency calculation equations. The reading and writing efficiency when using the access method proposed in range access mode or in azimuth access mode can be calculated as follows:  
\[\eta_{WRITE\_range\_3D}=\frac{16\times 4t_{ck}}{t_{RCD}+t_{CWL}+16\times 4t_{ck}+t_{ WR}}=67\% \tag{9}\]  
\[\eta_{READ\_range\_3D}=\frac{16\times 4t_{ck}}{t_{RCD}+t_{RP}+16\times 4t_{ck}}=82\% \tag{10}\]  
From the comparison results in Table 2, the method proposed can achieve complete equilibrium in terms of the two-dimensional data bandwidth. Although the range data efficiency is slightly reduced, the azimuth data reading efficiency and writing efficiency are increased to more than 6.7 and 7.8 times, respectively compared with the conventional method. Thus, the azimuthal data access bandwidth is not a bottleneck restricting the real-time performance of the spaceborne SAR system in the proposed method.