# Review of Task-Scheduling Methods for Heterogeneous Chips
## 5 Research Status of Experiment
### Evaluation Metric  
This section introduces the common evaluation methods of the seven categories of task-scheduling methods for evaluating heterogeneous chips, as shown in Table 6. The following is a detailed analysis of how the different scheduling methods are compared against these evaluation methods:  
* Complexity: Complexity measures the cost of the algorithm in terms of computing resources, time, space, etc. The commonly used evaluation indicators include execution time and maximum completion time (makespan). Execution time is required by the task-scheduling algorithm to generate scheduling for a given application graph [27]. Makespan [53] refers to the total time required to complete a series of tasks or assignments with the formula shown below. \[\mathit{makespan}=\max\{\mathit{AFT}(v,\mathrm{exit})\},\] (1) where \(\mathit{AFT}(v,\mathrm{exit})\) is the actual completion time of the DAG exit task. * Performance awareness: Performance-aware requirements refer to the scheduling algorithm that needs to take into account the maximization of the overall performance of the system when making decisions. The commonly used evaluation index has an acceleration ratio [54]. The speedup refers to the ratio of the task order execution time to the worst response time. The situation of the acceleration of the current algorithm for a task schedule can be obtained. The formula is shown below. \[\mathit{speedup}=\frac{\mathit{vol}}{\mathit{makespan}},\] (2) where \(\mathit{vol}\) represents the time overhead of task sequential execution. To prevent contingency, multiple datasets are averaged. * Optimality: Optimality evaluates whether the scheduling algorithm can determine the optimal or near-optimal solution scheduling task for heterogeneous chips under given constraints. One of the common evaluation indicators is the scheduling length  
Figure 8: Common hardware-in-loop, such as the Xilinx Zynq UltraScale + ZCU102 FPGA (**a**) and Odroid-XU 3 board (**b**). ratio (scheduling length ratio, SLR). SLR refers to the ratio [55] of makespan to the theoretical optimal scheduling length. The formula is defined as follows: \[SLR=\frac{makespan}{\sum_{o_{i}\in CP_{MIN}}\min_{p_{i}\in P}(w_{i,j})},\] (3) where the denominator is the sum of the minimum computational cost of the task belonging to the critical path called \(CP_{MN}\). * Power awareness: The power awareness monitors and manages the immediate energy consumption of the device. It is designed to reduce the peak power demand of the device during operation [53]. The goal of this metric is to minimize the overall parameters such as energy [56] or the energy-delay product (EDP) [57]. The EDP provides a compromise measure by considering the energy consumption and execution time. The EDP formula is defined as follows: \[EDP=\sum E_{P_{j}}\times systemTime,\] (4) where \(\sum E_{P_{j}}\) represents the total energy consumption of the whole system and _systemTime_ is the total execution time of the whole cluster system. * Energy awareness: The energy awareness focuses on the total energy consumption of heterogeneous chips over a period of time. The goal of this approach is to reduce long-term energy consumption and reduce overall energy costs [56] by improving energy efficiency. In task scheduling, resource allocation or the system design strategy, how to minimize energy consumption while completing the necessary calculation tasks is an important consideration. The commonly used indicators are average power consumption, total energy consumption, and real energy consumption \(RE(i,j)\)[29]. The real energy consumption \(RE(i,j)\) of a task \(i\) on processor \(j\) can be defined as \[RE(i,j)=\sum_{k=1}^{s}x_{i,j,k}\times EE(i,j),\] (5) where \(x_{i,j,k}\) is a binary variables and denotes whether task \(i\) execute in processing unit \(j\). \(EE(i,j)\) is used to represent the energy consumption of task \(i\) on the processing unit \(j\).