# A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications
## 4 The Proposed Fully Digital BPSK Demodulator
### Current-Starved Gated Ring Oscillator (CSGRO)  
The oscillator chosen for the proposed design, see Figure 6, is a current-starved ring oscillator that is turned ON/OFF by means of the signal \(V_{P2}\). It is also known as the _Gated Ring-Oscillator_, since its structure is similar to the ones adopted for time-to-digital converters (TDCs) in Digital-PLL design [39; 40]. The scheme shown in Figure 10 exploits a biasing current reference, \(I_{REF}=325\,\) nA, that is mirrored by the current mirror system made up of transistors \(M_{1}\)-\(M_{9}\). Analyzing the working principle of this circuit, when the signal \(V_{P2}\) is low, the last inverter is practically disabled because no mirrored current flows through \(M_{6}\) and the inverter chain of the ring oscillator results in being electrically open. Contrariwise, when the enabled signal becomes high, the \(M_{6}\) transistor starts to mirror the reference current, and the oscillation begins.  
Figure 8: Non-overlapping phases generator circuit.  
All the transistors involved worked in the sub-threshold region, and the oscillation frequency was fixed by exploiting the following equations [38]:  
\[C_{TOT}=C_{par,int}+C_{i}+C_{wire}\approx C_{par,int}+C_{i}\simeq 30\,\mathrm{fF} \tag{6}\]  
\[f_{OSC}=\frac{I_{REF}}{NV_{DD}\mathrm{C}_{TOT}}=\frac{325\,\mathrm{nA}}{3\, \times\,0.9\,\mathrm{V}\,\times\,30\,\mathrm{fF}}\simeq 4.0\,\mathrm{MHz} \tag{7}\]  
where \(N\) is the number of inverting stages, \(C_{TOT}\) is the overall capacitance associated to the output node of each inverter, \(C_{par,int}\) is the parasitic intrinsic contribution due to transistors, and \(C_{i}\) is the load capacitance added to each output stage. The wiring parasitic contribution, \(C_{wire}\), was neglected. Added capacitors \(C_{i}\) were implemented using NMOS-Cap and their dimensions are reported in Table 1. Their value was around 25 fF and chosen  
Figure 10: Schematic of the proposed current starved gated ring oscillator (CSGRO).  
Figure 9: Transient simulation of the non-overlapping phase generator with zoom on the \(\Delta\varphi\sim 4\,\mathrm{ns}\).  
to be higher than the parasitic capacitance of the inverter transistors, in order to make the latter negligible and better stabilize the oscillation frequency, \(f_{OSC}=4.0\,\mathrm{MHz}\). In this way, the oscillator will produce just one pulse when no modulation occurs on the enabling phase, \(V_{P2}\), with an on-time \(T_{ON,\mathrm{\varnothing}sc}=125\,\mathrm{ns}\). Then, when the phase modulation occurs, it will generate two output pulses with the same duration described above and shown in Figure 11.  
Corner simulations were carried out at \(T=37\)\({}^{\circ}\)C, being the circuit to be implanted inside human bodies. Both the oscillation frequency, \(f_{OSC}\), and the average power consumption, \(P_{DD}\), of the CSGRO are reported in Table 2.  
\begin{table}
\begin{tabular}{c c} \hline
**Transistor** & **Aspect Ratio [\(\mathrm{\SIUnitSymbolMicro m}\)/\(\mathrm{\SIUnitSymbolMicro m}\)]** \\ \hline \(M_{1}\)–\(M_{9}\) & 4.8/0.9 \\ \(M_{N1}\)–\(M_{N3}\)* & 0.32/0.6 \\ \(M_{P1}\)–\(M_{P3}\)* & 0.96/0.6 \\ \(M_{N4}\)* & 0.32/0.6 \\ \(M_{P4}\)* & 0.96/0.6 \\ \(M_{N5}\)* & 0.64/0.6 \\ \(M_{P5}\)* & 1.92/0.6 \\ \(M_{C_{i}}\)* & 9 \(\times\) 1.0/0.4 \\ \hline \end{tabular}  
* Dimensions of transistors inside the three-stage inverters of the core of the CSGRO in green in Figure 10;  
* dimensions of the output CMOS buffer in Figure 10;  
* dimensions of the NMOS-Cap used as an output inverter stage external load indicated with \(C_{i}\) in Figure 10.  
\end{table}
Table 1: Transistor aspect ratios of CSGRO.  
Figure 11: Transient simulation of signals \(V_{P2}\) and \(V_{pulse}\). At time instant \(t=75\,\mathrm{\SIUnitSymbolMicro s}\) the phase modulation starts.