# A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
## 3 Experimental Results
### Implementation with Stratix III FPGA  
All Cyclone IV E FPGA have a resolution greater than 10 ps, which is similar to the transmission delay lines DTCs. To pursue higher resolution, the higher working frequency and smaller frequency step size are expected. The surface of the expected resolution for a given working frequency and a given frequency step size is shown in Figure 10. It can be seen that the resolution of both the proposed 3D Vernier DTC and 2D scales up when the working frequency increases and the frequency step size decreases. Moreover, the proposed 3D Vernier DTC improved the resolution even more with a high working frequency and small frequency step size. Therefore, the Altera Stratix III EP3 SL150F1152C2 FPGA is adopted for performance improvement. The block diagram of PLLs in the Stratix III FPGA is similar to those in Cyclone IV E FPGA. However, in contrast to Cyclone IV E FPGA, the working frequency of Stratix III FPGA can be synthesized much higher. Thus, the resolution can be designed much finer than the Cyclone IV E version. The best resolution is obtained by setting the input frequency to 50 MHz (crystal frequency in DE3-150 system), D to 10, N to 126/127/128, C to 1 (the post scale counter is setting to 2 following VCO included in PLL).  
Figure 8: The post-simulated and measured differential nonlinearity (DNL) of the proposed DTC implemented with Cyclone IV E FPGA.  
Figure 9: The post-simulated and measured integral nonlinearity (INL) of the proposed DTC implemented with Cyclone IV E FPGA.  
The post-simulated resolution is 203 fs. The post-simulated DNL and INL performance are depicted in Figures 11 and 12, respectively. They are \(-0.56\)LSB-\(0.88\)LSB and \(-3.8\)LSB-\(4.4\)LSB as shown in these two figures. The credibility of post-synthesis simulated results has been demonstrated with Cyclone IV E FPGA. The DNL and INL are mainly determined by the mismatch delay time between different transmission paths with different input values. Since the DTCs implemented with two FPGAs have the same topological structure, the INL results display a similar shape. To obtain a lower non-linearity, we should place and route the elements manually with the expenses of interoperability. Moreover, the effective operation range of the proposed DTC can be easily extended by adding input bits. A 54 seconds operation range can be obtained with 48 input bits. The proposed DTC utilizes 448 slice adaptive look-up-tables (ALUTs), 237 registers and 3 PLLs when realized on the Stratix III E FPGA. The specifications for Cyclone IV and Stratix III FPGA DTCs are summarized in Table 2.  
Figure 11: The post-simulated DNL of the proposed DTC implemented with Stratix III FPGA.  
Figure 10: The time resolution of 2D and 3D Vernier DTC with different working frequency and frequency step size.  
Additionally, the phase noise and jitter of PLLs can transmit to the output signal START and STOP. However, the largest jitter on PLL outputs is smaller than 10 ps and it follows a Gaussian distribution with zero mean value. Thus, the jitter of PLL does not impact the accuracy of the average arithmetic mean measurement.  
\[\left\{\begin{array}{l}T_{F}=\frac{1}{50+10\times 128 MHz}=1.562500 ns\\ T_{M}=\frac{1}{50+10\times 127 MHz}\approx 1.574803 ns\\ T_{S}=\frac{1}{50+10\times 126 MHz}\approx 1.587302 ns\\ \Delta T=T_{F}+T_{S}-2T_{M}\approx 195 fs\\ \end{array}\right. \tag{12}\]