# RHLP-18T: A Radiation-Hardened 18T SRAM with Enhanced Read Stability and Low Power Consumption
## 2 Proposed RMLP-18T Cell and Its Operations
### Radiation-Hardened SEU Recovery Analysis  
When a high-energy particle strikes an NMOS, a negative current is generated. This can induce a 0-to-0 or 1-to-0 upset. In the case of a PMOS, a positive current is generated, which can induce a 1-to-1 or 0-to-1 upset. When the RHLP-18T cell stored at logic 1, nodes Q, QB, and S0 are considered sensitive nodes because a 1-to-0 upset or 0-to-1 upset can occur as shown in Figure 1. The RHLP-18T cell includes mechanisms to recover from single-node upsets caused by particle strikes hitting sensitive nodes.  
1. When a high-energy particle strike momentarily flips node Q from '1' down to '0', this turns on transistors P1 and P2, and it turns off N3, causing node QB's voltage to rise. Crucially, transistor P3 is designed with significantly more pull-up strength than P1 (approximately three times greater). This difference ensures that node Q is quickly pulled back up to logic '1' before the related nodes (S0 and S1) can fully change state. This rapid restoration prevents the upset from corrupting stored data.
2. When a high-energy particle strike flips node QB from '0' up to '1', this turns off P5, P6, and P9, and turns on N4. Node S0 briefly enters a high-impedance state but effectively stays at logic '0'. As a result, N2 remains off, shielding primary storage node Q from the disturbance. The transient upset at QB does not manage to flip Q.  
Afterward, QB is pulled back down to logic '0' through the path provided by N1 and N3 (which are on because Q = 1).
3. When a high-energy particle strike flips node S0 from '0' to '1', transistors P4 and P8 turn off, while N2 turns on. As a result, node S1 floats, and node Q also temporarily floats because N4 is off. Despite these transient disruptions, the main latch (Q/QB) does not flip its state. Node S0 is then pulled back to logic '0' by transistor P9, which connects it to QB (normally at logic '0').
4. When a single event strike simultaneously flips node Q from '1' to '0' and node QB from '0' to '1', the design ensures that the restoring pull-up strength of P3 (driving Q high) overcomes the combined pull-down strength attempting to keep Q low. This pull-down involves N2 and N4, depending on the transient states of S0 and S1. Because the pull-up is stronger, node Q recovers to logic '1' before the secondary nodes S0 and S1 fully invert, successfully restoring the original state.
5. When a high-energy particle simultaneously strikes the sensitive nodes Q-S0 or QB-S0, an upset occurs from 1-0 to 0-1 in Q-S0, and from 0-0 to 1-1 in QB-S0. This turns on P1, P2, P4, P8, N4 and turns off P3, P7, P5, P6, N3. In this case, all storage nodes change and are unrecoverable. According to [7], to prevent the charge-sharing effect, the distance between transistors (PMOS to PMOS and PMOS to NMOS) connected to the sensitive nodes must be at least 0.6 um. Accordingly, the layout was designed with a distance of 0.85 um between P1 and P2, and a distance of 3.71 um between P7 and N2, as shown in Figure 2.  
Figure 3: Waveforms of the memory operation of proposed RHLP-18T cell.  
In summary, the RHLP-18T cell has three main sensitive nodes (Q, QB, S0). The design inherently recovers from SEUs at all these nodes and Single Event Double Node Upset (SEDNU) at Q-QB nodes, as shown in Figure 4. The layout design prevents SEDNU at Q-S0 and QB-S0 nodes.