# FPGA Implementation of a Higher SFDR Upper DDFS Based on Non-Uniform Piecewise Linear Approximation
## 4 Experimental Result
### Performance Evaluation of Single-Core DDFS  
We have implemented six sets of DDFS under different MAEs, and the spectrum images of the output signals are shown in Figure 7. The FCW and clock frequency of DDFS in these images are the same, FCW = 200, clock frequency is 200 MHz. But the bits of output signal are different under different precision. The bit number of output signal in Figure 7a-c is 16 bits, and that in Figure 7d-f are 17 bits, 19 bits, 20 bits respectively. From the spectrum images, we can discover that the SFDR of DDFS increases and the noise floor reduces with the increase of the approximate accuracy, which means our idea of improving the SFDR by minimizing the MAE is feasible. Next we discuss the relationship between the number of linear segments s and the SFDR. We implemented six sets of DDFS with different MAE corresponding to different numbers of linear segments, and the specific number of segments and SFDR are shown in Table 3. Each set of DDFS generate three signals at low frequency (FCW = 200), medium frequency (FCW = 1000) and high frequency (FCW = 1800), and their SFDR is measured separately and averaged. As introduced in Section 1, in [21; 22], [PERSON] and [PERSON] derived theoretically the upper bound of SFDR for DDFS using uniform segmented linear approximation, respectively, whose upper bound of SFDR is shown in Equation (2) and can be expressed in Equation (15) after converting to decibels. \[SFDR=20\log(16s^{2}+1)\approx 20\log(16s^{2})=24+40\log s \tag{15}\]  
This equation is derived through Fourier transform. During the derivation process, an important prerequisite is uniform segmentation, which means that the segmentation points can be represented using the number of segments \(s\). In our proposed non-uniform PWL method, this prerequisite is not valid and mathematical derivation is not feasible. Therefore, we directly tested SFDR under different segmentation numbers through experiments. Figure 6: The Hardware architecture of multi-core DDFS. Setting \(s\) to the power of 2, the equation is plotted as an image as shown in the blue curve in Figure 8. And the red curve in the figure shows the relationship between the number of segments and the SFDR of the DDFS using PWLMMAE segmentation method. This experimental result shows that the DDFS based on our method has a higher upper bound of SFDR than the DDFS based on the uniform segmentation linear approximation method in [21; 22]. Explaining from the perspective of MAE, for a fixed interval, the more the number of segments, the higher the accuracy of the approximation and the smaller the MAE. Our proposed PWLMMAE method has a higher approximation precision with the same segments. In the following, we comprehensively evaluate the performance and resource consumption of DDFS. For performance we mainly consider SFDR and maximum clock frequency, because SFDR reflects the quality of the output signal, and maximum clock frequency reflects the highest frequency of the output signal. The resources used include LUT, Flip Flop (FF), and DSP. As can be seen in Figure 9, as the MAE decreases, the SFDR of DDFS will increase, but the hardware resources required will also be more, and the maximum clock frequency also tends to decrease, which is mainly caused by the increase in the number of segments. Table 4 shows the performance of this work compared to other FPGA-based DDFSs. the DDFS with MAE = 0.00001 uses 399 LUTs, 66 FFs and 3 DSPs and is able to achieve a SFDR of 114.04 dB with a maximum clock frequency of 244 MHz. SFDR is the most important indicator, reflecting the quality of the DDFS output signal. Except for [14], our DDFS is leading in SFDR without significant increase or even decrease in resources. Compared to the latest work [6] to the best of our knowledge, our work achieves a 4 dB higher SFDR. We use 67 more LUTs and three more DSPs, while we use 150 fewer FFs. The SFDR of this work is 41.84 dB higher than [9], but uses significantly 99 less LUTs and 140 FFs.