## 5 Conclusions and Future Work  
In this paper, we have defined the accelerator concept, which is connected to the core peripheral bus, MA. In addition, we propose a MAIL framework that can perform an acceleration profile of MA inserted TinyML applications. MAIL is a coupled architecture of system emulators and RTL simulators designed to handle the complex register configuration flows required for embedded software and neural computational acceleration using MA. The MAIL framework offers practical value by enabling cost-effective and comprehensive evaluation prior to integrating accelerators into MCUs designed for edge AI and IoT applications. The MAIL framework addresses hardware area and delay for accelerators connected via MMIO. However, in resource-constrained systems like MCUs, energy consumption is also a critical factor, necessitating evaluation in this dimension. In future work, we plan to develop an energy consumption model for the MAIL framework to provide energy profiling for accelerators utilized in MCUs. We profiled performance and ADP by inserting MA into various neural computations of TinyML applications, and verified the effectiveness of MAIL, which makes TinyML software combined with MA evaluation accessible.  
Entire core architecture designing and performing the numerical analysis, J.K.; corresponding author, D.P. All authors have read and agreed to the published version of the manuscript.  
This work was supported in part by the Brain Korea 21 4 th Generation (BK21 FOUR) Project 4199990113966, in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (10%, 10%, respectively) under Grant NRF-2018R1A6A1A03025109, and Grant NRF-2022R11A3069260, in part by the Institute of Information and Communications Technology Planning and Evaluation (IITP) funded by Korean Government [Ministry of Science and Information Communication Technology (MSIT)] through the Processing-in-Memory Computing (PIM) Semiconductor Design Research Center (30%) under Grant 2022-0-01170, in part by the Development of Flexible Software-Hardware (SW-HW) Conjunctive Solution for On-Edge Self-Supervised Learning (50%) under Grant RS-2023-00228970.  
Not applicable.  
The original data presented in the study are openly available in tflite-micro at [[https://github.com/tensorflow/tflite-micro.git](https://github.com/tensorflow/tflite-micro.git)]([https://github.com/tensorflow/tflite-micro.git](https://github.com/tensorflow/tflite-micro.git)) (accessed on 21 November 2024).  
The authors declare no conflict of interest. The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, and in the decision to publish the results.  
\begin{table}
\begin{tabular}{l c c c c} \hline  & \multirow{2}{*}{**Gemmini [21]**} & \multicolumn{2}{c}{**SCALE-Sim [22]**} & \multicolumn{2}{c}{**MAIL (Ours)**} \\ \cline{3-5}  & & **TinyConv** & **Gesture** & **TinyConv** & **Gesture** \\ \hline Target System & RISC-V SoC & \multicolumn{2}{c}{N/_A_1} & \multicolumn{2}{c}{**Arm SoC**} \\ Abstraction-level & Low (RTL) & High (Functional Model) & \multicolumn{2}{c}{**Mixed**} \\ DRAM Usage & ✓ & ✓ & \multicolumn{2}{c}{✗} \\ RTL Simulator & Verilator & \multicolumn{2}{c}{N/_A_2} & \multicolumn{2}{c}{**Cadence NCVerilog**} \\ Workload & MatMul 3  & Conv + FC & Conv + FC & Conv + FC \\ Model Architecture & \((16,16)\times(16,16)\) & Figure 5(a) & Figure 5(b) & Figure 5(a) & Figure 5(a) \\ Systolic Array Size & \((16,16)\) & \multicolumn{2}{c}{\((16,16)\)} & \multicolumn{2}{c}{\((16,16)\)} \\ Elapsed Time (s) 4  & 130.53 & 2.54 & 0.89 & **23.74** & **20.64** \\ \hline \end{tabular}
\end{table}
Table 3: Comparison of other state-of-the-art accelerator prototyping frameworks with MAIL.