## 4 FPGA Realization of the Chaotic Dynamical System with a Butterfly-Like Curve of Balance Points
Figure 13: The 2-D signal plot of the discrete-time chaotic system (9) using Forward Euler finite-difference scheme in the \((x,z)\) plane. The Adder, Subtractor, and Multiplier blocks are sequential blocks with both clock (clk) and reset (rst) signals. The Single Constant Multiplier (SCM) performs a multiplication of the input by a constant with the use of only adders, subtractors, and shift operations. The Multiplexer (MUX) block chooses one of the inputs depending on the control signal  
Figure 16: Basic blocks for the three sub-circuits of the discrete-time chaotic system (9). Figure 14: Top-level hardware design of the discretized chaotic oscillator system (9). Figure 15: 32-bit fixed-point representation in a digital computer. (ctrl) and passes it to the output. In Figure 16, all inputs and outputs of the hardware blocks have a bus width of 32-bits. In our hardware design, MUX is used to implement the absolute value function required for the state variables y and z. Hence, Equation (9) should be modified to use the multiplexer (MUX). In the discrete equation of state variable \(y\), the absolute value function \(|y|\) is used, which is defined in Equation (11). Equation (10) shows the state variable y after including MUX. \[\left\{ \begin{array}{l}y[n+1]=y[n]-hz[n]((a+b)y[n]+cx[n]\cdot z[n])\text{ if }y \geq 0\\ y[n+1]=y[n]-hz[n]((a-b)y[n]+cx[n]\cdot z[n])\text{ if }y<0\end{array} \right. \tag{11}\]  
In the discrete equation of state variable \(z\), two absolute functions are used, _viz._\(|x|\) and \(|y|\). If both state variables have the same sign, then their multiplication is positive. Otherwise, it is negative. To check if the two state variables have the same sign, we need to XOR the sign bit of the state variable \(x(S_{x})\) with the sign bit of the state variable \(y(S_{y})\), i.e., \(S_{x}\) XOR \(S_{y}\). Equation (12) shows the state variable \(z\) after including MUX. \[\left\{ \begin{array}{l}z[n+1]=z[n]+h\big{(}x^{4}[n]+y^{4}[n]-x[n]\cdot y[n]- x^{2}[n]\big{)}\text{ if }S_{x}\text{ XOR }S_{y}=0\\ z[n+1]=z[n]+h\big{(}x^{4}[n]+y^{4}[n]+x[n]\cdot y[n]-x^{2}[n]\big{)}\text{ if }S_{x}\text{ XOR }S_{y}=1\end{array} \right. \tag{12}\]  
To implement the sub-system \(X\), the discrete equation of the signal \(x\) in (9) is realized as represented in Figure 17. It uses SCM to multiply the signal \(z\) by the constant \(h\) and then adds the result to the signal \(x\) to get the output \(x=x+hz\). To implement the sub-system \(Y\), the discrete equations of the signal \(y\) in (11) are realized as represented in Figure 18. It uses four SCM modules, two multipliers, two adders, one subtractor, and one multiplexer. The SCM modules multiplies the input signals with a constant. The output signals are forwarded to the next modules. The multiplexer receives two signals produced by the adders \((a+b)y+cxz,(a-b)y+cxz\) and passes one of them according to the signal \(y\). To implement the sub-system \(Z\), the discrete equations of the signal \(z\) in (12) are realized as represented in Figure 19. This sub-system is the most complex one. It includes seven multipliers, three adders, two subtractors, one SCM, and one multiplexer. The signal \(y4\) or \(x4\) is produced using three multipliers in two stages. The multiplexer receives two signals produced by an adder \(x4+y4-x2+xy\) and a subtractor \(x4+y4-x2-xy\). It passes one of them according to the result of \(S_{x}\) XOR \(S_{y}\). The output of the multiplexer is multiplied by \(h\) and added to the signal \(z\) to produce the final output. Our FPGA realization was carried out with the Zed-Board FPGA prototyping board from Xilinx. The system specifications of the board can be listed as Zynq-7000 all programmable SoC FPGA, 512 MB DDR3 Memory, and some other peripherals. We synthesized the generated VHDL codes using Xilinx Vivado design suite and executed on the FPGA prototyping board. Figure 17: Realization of the sub-system \(X\) on FPGA. Table 2 lists the FPGA resources use for each sub-system and for the complete chaotic oscillator system.