## 1 Introduction  
Artificial neural network (ANN) has become a core technology that leads the modern artificial intelligence (AI) industry, thus it has been utilized in various fields such as image recognition, natural language processing, autonomous vehicles, and so on [1, 2, 3]. Given that the operation of ANN is based on vector-matrix multiplication (VMM), which is basically parallel calculation, the conventional computing system (called von Neumann architecture) where central processing units (CPUs) and memory are connected in series is not suitable for ANN [4, 5]. In recent years, a neuromorphic computing system has been considered as a potential candidate for future computing architecture to overcome the limitation of von Neumann architecture [6, 7, 8]. The basic components consisting of the neuromorphic system are synapses and neurons, which are connected in parallel. An integrate-and-fire (I&F) neuron circuit receives pre-synaptic inputs and spatiotemporally integrates them into a membrane. When the membrane potential exceeds a threshold of the neuron, a spike is generated, and it is transmitted to the next neurons. Conventional I&F neuron circuits have been fabricated by the complementary metal-oxide-semiconductor process with a membrane capacitor [9, 10]; however, in recent years, there have been some research about I&F neurons based on memristors such as resistive random-access memory (RRAM), phase-change random-access memory (PRAM), and magnetic random-accessmemory (MRAM), which have advantages in energy and area [11; 12]. A synapse adjusts the strength of the connection between neurons, which is called a synaptic weight. As synaptic devices, non-volatile memories, such as flash memory, memristors, etc., have been actively studied [13; 14; 15; 16]. Conductance of the synaptic device changes according to its program (PGM) and erase (ERS) states, thus that the strength of the signal transmitted to the neuron (the weight) can be adjusted. When implementing a hardware-based spiking neural network (SNN) using I&F neuron circuits and synaptic devices, there are two methods to train the network: Online and offline learning [17]. Online learning is capable of self-learning in hardware without the help of software through biologically plausible learning algorithms such as spike-timing-dependent plasticity (STDP). STDP is a Hebbian learning algorithm, which has been widely used for unsupervised learning, and supervised learning based on STDP has also been actively studied [18; 19; 20]; however, its performance has not yet reached state-of-the-art performance. Therefore, offline learning where weights are trained by a gradient descent algorithm in software-based ANN and transferred to the hardware-based SNN has attracted a lot of attention [21; 22; 23]. In order to use the hardware-based SNN as an inference system, it is important to precisely map trained weights to synaptic devices. When transferring the weights, two main issues should be taken into consideration. First of all, 32-bit full precision floating point numbers are generally used for trained weights by software-based ANN, but it is difficult to implement synaptic devices having multi-level conductance comparable to software-based weights. Moreover, it must be possible to access an individual synaptic device and be capable of mapping target weights by repeatedly applying PGM/ERS pulses. However, as the scale of the neural network increases, the number of synapses increases, thus it can be time-consuming to transfer all the weights. In this paper, we propose a scheme for transferring quantized synaptic weights to hardware-based SNN through STDP. Firstly, we train a network for the Modified National Institute of Standards and Technology (MNIST) pattern recognition using a software-based learning algorithm and try to quantize the trained weights thus that they can fit in the characteristic of the synaptic device. STDP is generally used as a learning algorithm, but it is employed as a method for weight transfer.