## 5 Hardware Implementation and Experimental Results
### Discussion
Figure 41: Mean SNR values of options 1, 2, and 3 in (**a–c**), respectively, after the simulation of the DFE with the orthogonal frequency division multiplexing (OFDM) receiver model. A multitude of literatures deal with the DFE, including [2; 3; 4; 5; 6; 7; 8; 9; 11; 12; 13; 17; 27; 28; 29; 30], and many of them are based on the CIC filter, Farrow interpolator, and the FIR filter. However, most of them address only the simulated results and few of them explain the ASIC or FPGA implementation in detail. The proposed DFE architecture in this paper was implemented in FPGA and ASIC in a rigorous manner such that the critical path delays were analyzed and the requirements of ten frequency modes (or cases) for LTE-A CA were all met. The parameters of all the building blocks in the proposed DFE were chosen after an extensive 3 GPP specification study. The spectral-domain view is also shown for each building block of the DFE. The FPGA implementation results and the ASIC synthesis results of the proposed DFE were also analyzed in terms of timing margin, speed, area, and resource usage. The proposed DFE was constructed from a systematic design methodology based on abstraction levels from Matlab and C++ functional models through C++ cycle-accurate and bit-accurate models to RTL models, while the ADC model and the OFDM receiver model were also taken into account to give an overall receiver performance in terms of the mean SNR. A special class (fixedDT) was developed to methodically convert the cycle-accurate model to the bit-accurate model, so that the RTL model performance was guaranteed to be in line with the functional model, providing a more robust design implementation. Not only the overall DFE architecture was proposed to be compliant with the LTE-A CA, but also its building blocks, especially Farrow interpolator and the digital mixer, were refined and proposed to serve their purposes relevantly. Namely, the integrate-and-dump circuitry of Farrow interpolator was refined via a condition signal to provide appropriate  
Figure 42: No. of (FIR5 + FIR4) filter taps for options 1 and 2 in (**a,b**), respectively. timing for the output. Moreover, a digital mixer with an LUT, aided by the periodic reset functionality, was proposed to overcome the problem of phase error accumulation, which was demonstrated experimentally. Another point that distinguishes our approach from others was that the OFDM receiver output was taken as the reference output, not the ADC input or output, in order to optimize the overall receiver system. The distortion that appears at the ADC input or output might be cancelled while it passes through the OFDM 1-tap equalizer. Prospective research of the proposed DFE will be directed toward incorporating more functions into the DFE architecture, such as DC offset cancellation, \(I/Q\) estimation and compensation, and antidooping filtering, as a means to digitally correct radio frequency impairments. Additionally the DFE chain for the radio transmitter, consisting of an antidooping filter, root raised cosine filter, and interpolation chain, will be included in the future research as an extension to the proposed DFE for the radio receiver.