# Balancing the Leakage Currents in Nanometer CMOS Logic--A Challenging Goal
## 3 Bspl
### Imbalance through Gate Leakage  
As an example, consider the BSPL NAND gate depicted in Figure 3. For any combination of inputs, there is a parallel connection of 3 \(\times\) PMOS and 1 \(\times\) NMOS which are switched off and not bridged (Bridged means that its source and drain terminal are connected by a low resistance path (e.g., by another transistor which is conducting) and therefore no significant potential exists between them). All remaining transistors are either switched on, or they are bridged. BSPL considers only the four transistors which are off and not bridged for its balancing concept, since neither on-transistors nor bridged ones are relevant contributors to drain-source leakage (Transistors which are on are supposed to conduct current between drain and source and therefore do not _leak_ current between these terminals. Transistors which are bridged have no significant potential between drain and source and therefore do not leak a significant current between these terminals). However, gate leakage also occurs in transistors which are switched on or bridged, due to the potential between the gate terminal and the source (or drain) terminal. To illustrate the fact that BSPL neglects the gate leakage in its balancing strategy we consider the BSPL NAND gate in Figure 3 again. For inputs AB \(=\) 00 (Figure 3b) it can be seen that in addition to the 3 \(\times\) PMOS (M7, M8, M9) and 1 \(\times\) NMOS (M5) which are switched off and not bridged, there are 3 \(\times\) PMOS which are on (M1, M2, M4) and 2 \(\times\) NMOS (M3, M6) which are switched off, but bridged. In contrast, when considering the same gate for inputs AB \(=\) 11 (Figure 3e), it can be seen that again 3 \(\times\) PMOS (M1, M2, M4) and 1 \(\times\) NMOS (M6) are switched off and not bridged, while 2 \(\times\) NMOS are on (M3, M5) and 3 \(\times\) PMOS (M7, M8, M9) are switched off, but bridged. Clearly, only one of the three groups, namely switched off but not bridged, is properly balanced for all input combinations. Although the other two groups do not need to be considered when analyzing drain-source currents exclusively, they certainly play a role in determining the total gate leakage of the cell. We have determined the different transistor states for all possible inputs to the BSPL NAND gate and listed them in Table 1.  
Figure 6: BSPL XOR gate, and the status of the transistors for different input values (inverters to generate \(\overline{\text{A}}\) and \(\overline{\text{B}}\) are not shown).  
Interestingly, we noticed that primarily leakage currents through the gate insulator of switched on transistors are responsible for the remaining data-dependent leakage of BSPL gates in 40 nm and 65 nm technology. We analyzed the situation for all BSPL gates (NOT, NAND, NOR, XOR) in both technologies and found that the group of on transistors is responsible for 85-92% of the remaining data dependency of the leakage currents, while the group of bridged transistors is responsible for only 8-15%. Hence, we conclude that it is not a viable balancing strategy in sub-100 nm technologies to only consider drain-source currents. Leakage currents through the gate insulator, particularly in switched on transistors, need to be considered in balancing approaches as well. This observation also shows that it is a misconception, although a common one, to consider leakage currents only for those transistors in a circuit which are switched off.