## 6 Experimental Results
The benchmarks have the level C3 \(18<R1+L\leq 24\). The level C3 determines big FSMs. The benchmarks have the level C4 if \(R1+L>24\). The level C4 determines very big FSMs. The results of experiments are shown in Table 7 (the LUT counts), Table 8 (the minimum cycle times), Table 9 (the maximum operating frequencies), and Table 10 (the consumed power). There is a similar organization for each of these tables. Benchmark names are in the table rows. The investigated methods are shown in the table columns. The complexity of a particular benchmark is shown in the last column. The row \"Sum\" includes results of summation for corresponding columns. In the row \"Percentage\", we show the percentage of the summarized characteristics of various FSM circuits with respect to \(P_{2T}Y\)-based FSMs. From Table 7, we can find that, compared to other investigated methods, the circuits of \(P_{2T}Y\)-based FSMs consume a minimum number of LUTs. The proposed approach provides the following gain: 1. 48.97% regarding the Auto-based FSMs; 2. 69.98% regarding the One-Hot-based FSMs; 3. 26.33% regarding the JEDI-based FSMs; and 4. 9.44% regarding the \(P_{T}Y\)-based FSMs. In our opinion, this gain is associated with a decrease in the amount of transformed state codes compared to \(P_{T}Y\)-based FSMs. Due to this, the LUT count in \(LUTeASV\) is less than 1 for the code transformer of equivalent \(P_{T}Y\)-based FSMs. Additionally, the gain can be achieved due to reducing the cardinality number of the partition of states. The fulfillment of the condition \((J+1)<K\) provides a decrease in the required number of LUT inputs for elements of \(LUTeFA\) compared to that of the LUTs of \(LUTePF\). This phenomenon can lead to a decrease in the LUT count. The following phenomenon is clear from Table 7: if an FSM has the complexity C0, then there are the same LUT counts for equivalent FSMs based on collection encoding. Moreover, in this case, other FSMs have better values of LUT counts than \(P_{T}Y\)- and \(P_{2T}Y\)-based FSMs. We can explain this in the following way. If an FSM has the complexity C0, then the condition (4) takes place. In this case, each SOP (2) and (3) is implemented by a single LUT. Therefore, in this case, there is no need to use various structural decomposition methods. However, regardless of the validity of condition (4), the encoding of output collections is executed for both \(P_{T}Y\)- and \(P_{2T}Y\)-based FSMs. As a result of this, the block \(LUTeOF\) is used. This block consumes additional LUTs compared to other researched methods. Dueto validity of (4), there are no partial functions for FSMs having the complexity C0. As a result, there is no need to assemble blocks (_LUTerFA_ and _LUTerPF_). This means that both \(P_{T}Y\) and \(P_{2T}Y\) FSMs degenerate into equivalent \(PY\) FSMs. Now, let us analyze the temporal characteristics of FSM circuits. They are represented in Table 8 (the cycle time measured in nanoseconds) and Table 9 (the maximum operating frequency measured in megahertz). Analysis of Table 8 shows that JEDI-based FSMs are the fastest. It also shows that \(P_{T}Y\)-based FSMs are marginally slower than circuits of \(P_{2T}Y\)-based FSMs (the average loss is 0.56%). At the same time, the proposed approach generates circuits with worse time characteristics than the circuits of \(P\) FSMs. The Auto-based FSMs are 0.09% faster than the \(P_{2T}Y\)-based FSMs. The One-Hot-based FSMs are 0.73% faster than the \(P_{2T}Y\)-based FSMs. Finally, JEDI-based FSMs are 5.93% faster than \(P_{2T}Y\)-based FSMs. If the FSM complexity exceeds C0, then both \(P_{T}Y\)- and \(P_{2T}Y\)-based FSMs have three-level circuits. At the same time, it is difficult to estimate a priori the number of logic levels in circuits of \(P\) FSMs. It all depends on the number of literals in the implemented sum-of-products. As follows from Table 8, if FSM complexity is equal to C0, then cycle times are the same for equivalent \(P_{2T}Y\)- and \(P_{T}Y\)-based FSMs.