# A CMOS Multiplied Input Differential Difference Amplifier: A New Active Device and Its Applications
## 2 A Multiplied Input Differential Difference Amplifier
The multiplying constant \(k\) was obtained from the detailed analysis of the MLT subpart. The first term of (1) represents the contribution of auxiliary linearization and attenuation blocks (components including M\({}_{\text{X1,2}}\) and M\({}_{\text{Y1,2}}\) with resistors \(R_{a}\) and \(R_{b}\), as visible from Figure 2). The second term of (1) covers the effect of differential pairs of the multiplying core (transistors M\({}_{\text{1-4}}\) and M\({}_{\text{5-6}}\) and their aspect ratios), and the conversion of the output current of these transistors, to the differential output voltage of the \(R_{\text{L}}\) resistors. The last term (right side of (1)) includes the contribution of boosting the output transconductance amplifier (aspect ratio of M\({}_{7,8}\) and 4\(I_{bias1}\), derived from \(I_{bias1}\) through biasing current mirrors, see Figure 2). Constant 5 represents the effect of the current gain of internal mirrors on the boosting transconductance amplifier. Note that a hand calculation of \(k\) yields a value of about \(-2\) mA/V\({}^{2}\), whereas a simulation provides a value of about \(-1.8\) mA/V\({}^{2}\) (note that the multiplier is inverting in basic configuration). This mismatch is caused by several inaccuracies in the ideal calculation: (a) a non-equal bulk and source voltage \(V_{\text{BS}}\
eq 0\) V for some transistors (differential pairs where bulk terminals are connected to \(V_{\text{DD}}\) or \(V_{\text{SS}}\)), which impacts the \(V_{\text{th}}\) and transconductance of partial specific transistors; (b) the rounding of resistor values (exact value supposes multiplication of 0.975 k\(\Omega\)/square); (c) a process and temperature dependence of \(K_{P(n,p)}\), as well as partial transconductances of CMOS transistors in proposed topology. The real experimental value of the \(k\) parameter equal to \(-1.3\) mA/V\({}^{2}\), falls into the range of the predicted values from Monte Carlo and corner analyses. The CMOS structure of the MIDDA element, including W/L aspect ratios of all the transistors, values of passive elements, and biasing sources, are shown in Figure 2. Note that not all ESD precautions and bulk connections (NMOS to \(V_{\text{SS}}\), PMOS to \(V_{\text{DD}}\)) are included in Figure 2, because of simplicity. The linear ranges of DC transfer characteristics of the real MLT section are limited up to \(\pm 500\) mV for inputs \(X\) and \(Y\), and up to \(\pm 350\)\(\upmu\)A for the auxiliary terminal \(z\). The examples of measured DC transfer characteristics between input voltage (\(V_{Y}\)) and output current (\(I_{Z}\)), are shown in Figure 3a; \(V_{X}\) serves as the DC constant, driving overall transconductance (in accordance to \(g_{\text{m}}\cong 1.3\times 10^{-3}\)\(V_{X}\)). The gain bandwidth (GBW) of the real prototype overcomes 48 MHz for the MLT subpart of the MIDDA (Figure 3b). The sweep of voltage \(V_{X}\) between \(\pm 0.05\) and \(\pm 0.5\) V, causes a change in \(g_{\text{m}}\) between \(\pm 60\)\(\upmu\)S and \(\pm 660\)\(\upmu\)S (both polarities of \(g_{\text{m}}\) are available by the DC control voltage, in comparison to a standard operational transconductance amplifier [1]), as illustrated by a graph shown in Figure 4. The DC input and output linear range of VDDB reaches approximately \(\pm 700\) mV (range is valid for inputs \(z\), \(n\), \(p\), and output \(o\)), as shown in Figure 5a. The bandwidth (3 dB) of the VDDB part is 45.1 MHz  
The examples of simple linear and nonlinear operations of the MIDDA are shown in Figure 6. Figure 6 presents the typical DC response of the MLT subpart, producing an output current \(I_{z}\) as a nonlinear parabolic function of the input voltages \(V_{X}=V_{Y}=V_{inp}\). This behaviour can be confirmed in the time domain (Figure 6b), where sine wave excitation creates output current with single polarity (negative due to negative \(k\)) and double frequency. Figure 6c,d provide an overview of the linear operation in time domain.