# O-Band and C/L-Band III-V Quantum Dot Lasers Monolithically Grown on Ge and Si Substrate
## 2 O-Band and C/L-Band III-V Quantum Dot Devices via III-V/IV Hybrid Growth
### O-Band and C/L-Band InAs/GaAs Quantum Dots on (111)-Faceted Si Hollow Substrate  
Most reported studies of III-V QD lasers were grown on 2-6\({}^{\circ}\) offcut Ge or Si towards [110] substrates to prevent the formation of APDs [36; 37; 38; 39; 40; 41; 42; 43; 45; 46; 66; 67]. Unfortunately, offcut Ge or Si substrates are not fully compatible with standard CMOS processing foundries, and it may hinder the viability of InAs QD lasers as light emitters for silicon photonics. In addition, it would be more attractive to realize a laser in which the intermediate germanium layer is not required. Because the germanium layer restricts the application range of silicon circuits and due to the large optical absorption coefficient at the telecommunications window, it is difficult to realize the light coupling between  
Figure 1: **(a)** The STEM image of C/L-band InAs quantum dots structure on Ge substrate. The white arrow: The growth direction of the epitaxial layers. **(b)** Bright field TEM image of GaAs/Ge interface. **(c)** High magnification STEM image of InAs QDs. The red-marked region: The cross section of a top-flattened InAs QD. All images are taken along [110] direction. germanium with silicon waveguide. Therefore, a high-performance III-V laser directly grown on a silicon substrate is considered a more promising solution for silicon photonic-electronic integration. To date, various approaches have been carried out to tackle the challenges associated with material incompatibility, including the large mismatch of lattice constants and thermal expansion coefficients and the polar-nonpolar nature of the III-V/IV semiconductor system. The novel epitaxy approach to integrate GaAs on silicon relies on aspect ratio trapping (ART) of defects in narrow oxide trenches to suppress the threading dislocations. The misfit strain by the formation of twinned stacking faults (SFs) is relaxed through using the V-groove structure [49; 50; 51; 60; 64; 71; 72]. This method stands out for its capability in defect trapping, good controllability and high compatibility with the Si CMOS process. Recently, [PERSON] et al., found out that III-V materials including QD lasers and in-plane GaAs nanowires can be monolithically grown by MBE upon GaAs-on-V-groove patterned Si substrates which are prepared by metal oxide chemical vapor deposition (MOCVD) [49; 60; 71]. Although APDs are avoided by the grooves and most dislocations are confined to the interface, there is still no way to release the thermal mismatch. In addition, 1550 nm quantum dot diode lasers have been realized on CMOS-standard (001) silicon substrate, but with a very thick GaAs intermediate buffer layer of 2.2 um[64]. Therefore, a novel method is strongly demanded to improve the laser structure for the reduction of thermal mismatch, for less TDs and better laser performance. Recently, by using U-shaped patterned Si (001) substrates, we obtained (111)-faceted-sawtooth Si hollow structures by homo-epitaxy [69]. The in-situ hybrid epitaxy of InAs/GaAs on such Si substrates can be realized to achieve highly efficient 1300 nm and 1550 nm emission by using a dual chamber MBE. As shown in Figure 2a, the U-shaped patterns are fabricated by a standard process on standard 8-inch on-axis Si (001) substrate, by using a SiO\({}_{2}\) hard mask, deep ultraviolet (DUV) lithography, dry etch, and removal of SiO\({}_{2}\) in diluted hydrofluoric acid (HF) solution. The U-shaped patterns have a period of 360 nm with a ridge width of 140 nm and a depth of approximately 500 nm. After cleaving into 32 mm \(\times\) 32 mm dies and ex-situ chemical cleaning, the samples are loaded into the SiGe MBE chamber for growth. After 550 nm Si growth, the (111)-faceted sawtooth hollow structures are obtained, as shown in Figure 2b, which can be used for a subsequent in-situ GaAs buffer layer and III-V QD laser structure growth. The formation of the hollow structure in Si can partially reduce the thermal mismatch between the epitaxial GaAs layer and Si substrate.