## 4 SI/PI Co-Design in the High-Speed Interconnect Using the Proposed Method  
In this section, the proposed method is applied for SI/PI co-design in the high-speed interconnect, targeting an HBM interposer channel. HBMs are assembled on a silicon interposer to form a 2.5-dimensional system for high system performance with a small form factor. The silicon interposer plays an important role in TB/sec bandwidth, as in the interposer, ultra-fine signal, power, and ground interconnects can be designed and fabricated in small dimensions. Due to complex design and fine dimensions, the PDN of the interposer is resistive and inductive, resulting in a high hierarchical PDN impedance. The PDN impedance affects power/ground noise property, resulting in SI/PI degradation. At the early design stage, each design iteration requires SI/PI analysis. Thus, an efficient analysis method is extremely important these days. In Figure 12a, a conceptual image describing a target high-speed channel to be designed and analyzed is shown. Various design parameters affecting the SI/PI are depicted. In Figure 12b, an equivalent circuit model of the hierarchical PDN and buffers, which generate power/ground noise, is shown. In one sub-block of the HBM, there exist 32 buffers, therefore, 31 aggressors generate SSO noise and power/ground noise. As can be seen from the HBM ball map [1; 2; 3], power/ground interconnects in chip and interposer PDNs shield most of the power/ground noise coupling from adjacent sub-blocks. For the hierarchical PDN shown in the Figure 12a,b, actual PDN designs of HBM interposer, package, PCB and chip are considered based on reference [1] and related previous works [2; 3; 5; 24; 25]. However, if the PDN is modeled based on the S-parameter matrix extracted from electromagnetic (EM) simulator, ground interconnect will be added up to the power interconnect, this will result in inaccurate ground noise. Therefore, power/ground resistance and inductance are extracted from the hierarchical PDN impedance. In Figure 13, hierarchical PDN impedance seen from the HBM is shown. As shown in Figure 12b, on-chip, interposer, package, and PCB PDNs are considered with decoupling capacitors in each PDN. Due to high inductance and resistance of the package and interposer PDN, hierarchical PDN impedance remains high at most of the frequency ranges with anti-resonance peaks. Proper decoupling capacitors should be placed in the PDN to reduce the hierarchical PDN impedance to solve SI/PI problems. When a proper decoupling capacitor scheme is adopted in the PDN, hierarchical PDN impedance is lowered in most of the frequency ranges with anti-resonance peaks removed. With a frequency range over 5 GHz, the impedance profile remains almost the same, even though decoupling capacitors are included. This can be solved by placing more on-chip decoupling capacitors in the on-chip PDN with smaller values. However, since the data rate of buffers in this case is 1-2 Gb/s, which is 0.5-1 GHz, current hierarchical PDN design is sufficient. In Figure 14, estimate statistical eye-diagrams of the target HBM interposer channel based on proposed method are shown and compared. As can be seen from Figure 14a, without a proper decoupling capacitor scheme in the hierarchical PDN, increased power/ground noise due to the SSO buffers associated with high PDN impedance severely degrades the SI of the HBM interposer channel. It is apparent that designs related to PI must be considered simultaneously with SI analysis. The PDN design and optimal decoupling capacitor schemes affect both SI/PI of the high-speed interconnect. Figure 14b shows the changes in the statistical eye-diagram when the proper decoupling capacitor scheme is adopted in the hierarchical PDN. As shown in Figure 13, reduced hierarchical PDN impedance in wide frequency bands also suppressed power/ground noise, resulting in an improved eye-diagram. Figure 14c shows further improvement in the eye-diagram by adopting the DBI coding.