## 4 Evaluation
### Results Analysis
#### 4.3.1 Results Analysis for Section 1  
This section contains a total of 22 questions, covering basic syntax, such as simple wire connections, data-type differences such as wire and reg, design levels, including gate-level, dataflow, and behavioral, and the differences between combinational logic and sequential logic. Finally, there is a test comparing the differences between each design level. The test results for Section 1 obtained by Group 1 are presented in Figure 8, where the x-axis represents the question numbers and the y-axis indicates the average number of attempts per question, as well as the average accuracy rates. In this figure, the gray bar depicts the average number of submissions for each question, the blue line represents the average submission time, and the red line indicates the average accuracy of the last submission. It is evident that, for most questions, students achieved a first-attempt accuracy exceeding 80%, demonstrating that the instructional explanations provided with the questions significantly supported students' comprehension. Additionally, Questions 2 to 4 and 16 to 18 constituted sets of similar question types. As observed in the figure, the average number of submissions for these grouped questions consistently decreased, while the first-attempt accuracy gradually increased across the sequence. This suggests that the design and sequencing of these question sets effectively facilitate students' rapid mastery of related concepts. An analysis of the overall test results reveals that questions with lower first-attempt accuracy primarily include the following. Question 14 requires students to determine whether a circuit was synchronous or asynchronous. We infer that many students struggled to effectively distinguish between these two types of circuits, as the concepts of synchrony and asynchrony can be particularly challenging for beginners. Questions 16, 17, and 18 assess students' understanding of _Verilog_ variable types for wire and reg and their differences, which are also closely related to the concepts of synchronous and asynchronous circuits. This may account for the lower accuracy rates observed. However, with repeated practice on similar question sets, the first-attempt accuracy improved from 78.55% on question 16 to 92.73% on question 18, indicating that such targeted exercises significantly enhance conceptual understanding and highlight the effectiveness of the learning system. Question 20 requires students to identify three different design levels in _Verilog_. We speculate that students had less exposure to gate-level representations compared to the other, more commonly encountered design levels, leading to a relatively lower accuracy rate for this question. Overall, the first-attempt correct rate was higher than 85% for most questions, and the final correct rate was close to 100%, indicating that the difficulty of this test was moderate and students had a solid foundation in terms of the basic concepts. Individual Student Performance in Group 1  
In Figure 9, the x-axis represents student IDs, while the y-axis shows each student's average number of submissions and accuracy rate. The orange line in the figure indicates that students' final accuracy is highly consistent, with the vast majority achieving or approaching 100%, demonstrating that repeated practice enabled most students to reach excellent learning outcomes. For the majority of students, the first-attempt accuracy exceeded 80%, indicating a strong initial understanding of the material. A small subset of students, for example ID 43 and ID 47, exhibited notably higher average submission counts and comparatively lower first-attempt accuracies. This suggests that, although these students were initially unfamiliar with _Verilog_, the iterative practice and explanatory support of the proposal ultimately enabled them to master the section's content and achieve successful learning results. Overall, Group 1 students demonstrated a strong foundational understanding of this section.