## 2 The 3D NAND Flash Endurance Reliability Case Study  
### Experimental Setup and Measurement Protocol  
The modeling activities in this work are based on the endurance reliability electrical characterization results performed on commercial 3D NAND flash devices integrated with the triple level cell (TLC) storage paradigm. The considered technology is a sub-100 layers (\(\geq\)72) generation considering the block device structure and the \(V_{\mathrm{T}}\) distribution coding using all the TLC pages [32] (i.e., the lower page is the lower significant bit--LSB, the middle page is the central significant bit--CSB, and the upper page is the most significant bit--MSB), as described in Figure 1. The electrical measurements required to characterize the memory devices were performed using custom-developed automated test equipment (ATE), allowing the topological extraction of the FBC after a read operation for every single location of a memory block (see Figure 2). The system is constituted by a laptop that controls the test flow running on a field programmable gate array (FPGA) device using a custom software interface that sets the proper voltages to drive the 3D NAND flash under test (i.e., \(V_{\mathrm{CC,Q}}\) chip power supply and \(V_{\mathrm{CC,IO}}\) to supply the bus interface for memory data I/O and commands), and the chip temperature with a heater/cooler element. Both \(V_{\mathrm{CC,Q}}\) and \(V_{\mathrm{CC,IO}}\) are taken as the typical values provided by the memory vendor in the datasheet. The connection between the tester unit, supplied with 12-48 V, and the laptop is achieved via an Ethernet 1 Gbps link.  
The characterization of the 3D NAND flash lifetime concerning the achievable endurance must follow the JEDEC standards provided in [33; 34]. In particular, the memory device needs to be exercised with consecutive program/erase (P/E) operations in 500 h at a 70 \({}^{\circ}\)C temperature until the rated endurance by the vendor, also called the end-of-life (EoL), is reached. Samples were programmed with a random pattern. All the endurance characterizations were performed on two different and independent memory blocks and multiple dies of the same 3D NAND flash test chip ensuring inclusion of manufacturing variability (although not considering the lot-to-lot one) in the results. The experiment protocol is summarized in Figure 2.  
Figure 3 shows the results of an endurance characterization performed on a 3D NAND flash block up to EoL. In the plot, we report the FBC per TLC memory page as a function of the achieved \(N_{P/E}\) operations. As expected from previous studies [35; 36; 37], the number of errors is page-dependent and grows as a function of the memory wear status. The average trend in the errors is fitted with the following exponential law:  
\[FBC(N_{P/E})=10.74\times exp^{(0.0001\times N_{P/E})} \tag{1}\]  
Our modeling attempts target a fresh device (\(N_{P/E}\) = 0) and the EoL point as the most critical situation for memory reliability, although the methodology described in the following sections of the work can be applied without lack of generality to every \(N_{P/E}\).  
Figure 1: TLC 3D-NAND Flash architecture considered in this work (**left**) and definition of fail bits according to their \(V_{T}\) distribution coding (**right**). Reprinted from [32] under Creative Commons License (CC BY 4.0).  
Figure 2: A Schematic of the ATE used in this work for the electrical characterization of the 3D NAND flash endurance (**top**). Cycling protocol used for extracting the FBC at defined readout steps until reaching EoL (**bottom**).