## 3 FPGA-Based Real-Time Simulator Architecture  
Figure 2 shows a schematic diagram of the FPGA-based real-time simulator. The core of the simulator is the computational engine. The computational engine is designed to provide the following main operational characteristics:  
* speed, _i.e._, a computation time in the range of tens to few hundreds of nanoseconds, and  
Figure 1: (**a**) Actual PWM generated by the controller; (**b**) PWM input considered by the simulator. * scalability, _i.e._, can be expanded to accommodate larger systems without impacting the simulation timestep. The design philosophy of the computational engine, to fulfill the aforementioned design requirements, is to:  
* exploit all possible levels of parallelism inherent to the solution algorithm of the system model, and
* design a customized hardware architecture that closely maps both the solution algorithm and dataflow. The solution algorithm adopted in this work is a variation of the generalized algorithm of [27,28]. The main difference is that the backward Euler method instead of the trapezoidal method is used. The backward Euler method provides damping to numerical oscillations that arise due to discontinuities, e.g., switchings, unlike the trapezoidal method which introduces sustained numerical oscillations due to switching events [29]. The solution algorithm is based on representing each circuit component by its companion circuit model. As such, the original system is transformed into a system of resistive elements and current sources. Nodal analysis is then used to solve for the node voltages at each timestep [27,30]. The nodal equation is given by  
\[Yv(t)=i(t)-I \tag{1}\]  
where \(Y\) is the nodal admittance matrix, \(v(t)\) is the vector of the node voltages, \(i(t)\) is the vector of current sources, and \(I\) is the vector of history current sources. Typically, the value of a given history current source \(h\) is computed by  
\[h(t)=\gamma v(t)+\kappa h(t-\Delta t) \tag{2}\]  
where \(\gamma\) and \(\kappa\) are constants and calculated from the components parameters and the timestep. Figure 2: Schematic of the FPGA-based real-time simulator in HIL testing arrangement. It has to be noted that, for a fixed simulation timestep, the right hand side of Equation (1) is updated in each simulation timestep, whereas the nodal admittance matrix \(Y\) remains constant. The associated discrete circuit (ADC) modeling approach extend the companion modeling approach to power electronic switches. The ADC approach represents a power electronic switch with a current source in parallel with a conductance \(G_{S}\) (Figure 3) [31; 32; 33; 34; 35]. In this approach, the conductance \(G_{S}\) is fixed irrespective of the switch ON/OFF state. The switch ON/OFF state is only accounted for by the value of the shunt current source. Thus, the ADC approach maintains the admittance matrix constant irrespective of the ON/OFF state of each switch [31; 32]. It is clear from the aforementioned discussion that the overall mathematical model of the system boils down to two sets of equations:  
1. the nodal equation of Equation (1). This is a set of \(M\) linear equations, where \(M\) is the number of nodes of the system, and
2. the set of history current sources equations. This is a set of \(N\) equations in the form of Equation (2), where \(N\) is the number of history current sources. The solution of the nodal Equation (1) is essentially the solution of the classical linear problem \(Ax=b\). Since the entries of the admittance matrix of the system are kept unchanged, the solution of \(Ax=b\) can be obtained by pre-calculating the inverse of \(A\) at the software level, _i.e._, before hardware implementation on the FPGA. Thus, there is no need to perform matrix inversions on the FPGA to solve Equation (1) and the solution of Equation (1) is converted to the matrix-vector multiplication of Equation (3)  
\[x=A^{-1}b \tag{3}\]  
Mathematically, a matrix-vector multiplication is the dot-product of each row of the multiplier matrix by the multiplicand vector.