# Design of Low-Power ECG Sampling and Compression Circuit
## 4 Results and Discussion
### Circuit Implementation  
In a 55 nm CMOS process, the physical layout of the proposed circuit is realized. The area of ADC is 0.011 mm\({}^{2}\) (85 \(\upmu\)m \(\times\) 134 \(\upmu\)m), and the power consumption is 0.214 \(\upmu\)W at the sampling frequency of 10 kHz. The traditional CS module with accurate calculation and register storage has an area of 0.046 mm\({}^{2}\) (215 \(\upmu\)m \(\times\) 214 \(\upmu\)m) and a power consumption of 1.409 \(\upmu\)W. In contrast, the optimized CS module based on approximate calculation and latch storage has an area of 0.037 mm\({}^{2}\) (193 \(\upmu\)m \(\times\) 192 \(\upmu\)m) and a power consumption of 0.963 \(\upmu\)W. The area and power consumption of the proposed CS module are reduced by 19.5% and 31.7%, respectively, affording a remarkable optimization effect.  
Figure 11: The functional simulation of the sampling and compression circuit.  
Figure 10: The Monte-Carlo simulation of the SAR ADC.  
The sampling and compression circuit is designed based on the optimized ADC and CS module. As illustrated in Figure 12, the circuit area is 0.325 mm\({}^{2}\) (570 \(\upmu\)m \(\times\) 570 \(\upmu\)m), limited by IO, and the core area is 0.048 mm\({}^{2}\) (220 \(\upmu\)m \(\times\) 220 \(\upmu\)m).  
The power consumption of the sampling and compression circuit is shown in Table 3. The total power consumption is 2.951 \(\upmu\)W, where the IO power consumption is 1.612 \(\upmu\)W, accounting for 54.6%, and the remaining 1.339 \(\upmu\)W is the core power consumption.  
We compare the proposed circuit against current solutions with the results reported in Table 4. A Figure of Merit (FOM) is used for fairness of the comparison under different processes, as shown in Equation (9):  
\[\text{FOM}=\frac{\text{Power}\times\text{Area}\times\upgamma}{2^{\text{ENOB}} \times\text{Frequency}},\ \upgamma=\left(\frac{55}{\text{process}}\right)^{2} \tag{9}\]  
References [10; 11] only mention the hardware consumption of the CS module, while references [12; 13] present the sampling and compression circuit results. Our work provides results for both the CS module and sampling and compression circuit, and Table 4 shows the hardware consumption of the sampling and compression circuit. Our 12-bit SAR ADC has a higher accuracy than the others, which is beneficial for data compression and reconstruction. References [10; 11] adopt a relatively advanced low supply of 0.6 V compared with the 1.2 V used in this paper, but our CS module has obvious advantages with its area of 0.037 mm\({}^{2}\) and power consumption of 0.963 \(\upmu\)W. Compared with References [12; 13], the proposed sampling and compression circuit has significant advantages in hardware consumption.  
Figure 12: The layout of the sampling and compression circuit.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline
**Module** & **ADC** & \multicolumn{3}{c}{**CS Module**} & **IO** & **Total** \\ \hline  & matrix & compression & data & & & \\  & generator & and storage & transmission & control & & \\ Power (\(\upmu\)W) & 0.214 & 0.041 & 1.027 & 0.023 & 0.034 & 1.612 & 2.951 \\ \hline \end{tabular}
\end{table}
Table 3: The power consumption of the sampling and compression circuit.  
The accurate accumulation sum of the high part and the approximate accumulation sum of the low part are added to the remote server to obtain the compressed data for signal reconstruction. Figure 13 presents the results of reconstructing the compressed data. Since the reconstructed signal is almost identical to the original signal, we offset the original signal upward by 0.2 V for clarity. The measured PRD is 1.513%, which is consistent with the simulation results of the CS algorithm.