## 3 Power Converters Modelling
### Boost Converter Average Model  
Each PV array has an interface boost converter before the connection with the corresponding bus. In this DCMG, boost converter preserves the traditional topology, but an input capacitor has been included to avoid PV array output voltage variations and a thermistor previous to the mentioned capacitor to limit the inrush current at the initial charge (see Figure 2).  
\begin{table}
\begin{tabular}{c c c c c} \hline
**Length** & **AWG 14** & **AWG 12** & **AWG 10** & **AWG 8** \\
**(Meter)** & **(\(\mu\)H; m\(\Omega\))** & **(\(\mu\)H; m\(\Omega\))** & **(\(\mu\)H; m\(\Omega\))** & **(\(\mu\)H; m\(\Omega\))** \\ \hline
5 & 4.53; 1.71 & 4.29; 1.62 & 4.06; 1.53 & 3.83; 1.44 \\
10 & 9.06; 3.41 & 8.58; 3.23 & 8.12; 3.06 & 7.66; 2.89 \\
15 & 13.59; 5.12 & 12.87; 4.85 & 12.18; 4.59 & 11.49; 4.33 \\
20 & 18.12; 6.83 & 17.16; 6.47 & 16.25; 6.12 & 15.32; 5.77 \\
25 & 22.65; 8.53 & 21.45; 8.08 & 20.31; 7.65 & 19.15; 7.22 \\ \hline \end{tabular}
\end{table}
Table 2: Line impedance values for different wire gauges and lenghts.  
Figure 1: Multibus multivoltage DCMG architecture proposed.  
\begin{table}
\begin{tabular}{c c} \hline
**Parameter** & **Value** \\ \hline Maximum power \(P_{max}\) & 250 W \\ Current at maximum power \(I_{mp}\) & 8.31 A \\ Voltage at maximum power \(V_{mp}\) & 30.1 V \\ Short circuit current \(I_{SC}\) & 8.83 A \\ Open circuit voltage \(V_{OC}\) & 37.4 V \\ \hline \end{tabular}
\end{table}
Table 3: Solar panel model parameters.  
In Figure 2, boost converter scheme has two power devices, a MOSFET (\(Q\)) and a diode (\(D\)); then, a switching function is defined for each in order to obtain the average model for the converter. In this way, \(S_{1}\) and \(S_{2}\) are switching functions for \(Q\) and \(D\), respectively. If \(S_{1}=1\), \(Q\) is in conduction state, else, if \(S_{1}=0\), \(Q\) is not conducting. Same logic is used for \(S_{2}\) and \(D\), but \(S_{1}\) and \(S_{2}\) perform in complementary mode, so the two power devices operate in a complementary way. The following combinations are not allowed \(S_{1}=1\) and \(S_{2}=1\); \(S_{1}=0\) and \(S_{2}=0\). In order to have an improved resultant model of this converter, the conduction resistances for the switching devices have been included: \(R_{D1}\) for the MOSFET and \(R_{D2}\) for the diode. The Kirchhoff Voltage Law (KVL) is applied to inductor loop and Kirchhoff Current Law (KCL) is used in capacitors nodes in order to obtain the state equations for the switching model. The average of the switching function, \(\overline{S}(t)\), corresponds to modulator signal duty cycle, \(u(t)\), in this case, \(\overline{S}(t)=u(t)\). Taking this deduction into account, it is possible to go from the switching model to the averaged model, which is given by:  
\[\frac{dv_{\rm C1}}{dt} =-\frac{1}{R_{t}C_{1}}v_{\rm C1}-\frac{1}{C_{1}}i_{L}+\frac{1}{R_ {t}C_{1}}V_{PV}\] \[\frac{di_{L}}{dt} =\frac{1}{L}v_{\rm C1}-\frac{[(R_{D1}-R_{D2})u+R_{D2}]}{L}i_{L}- \frac{(1-u)}{L}v_{\rm C2}\] \[\frac{dv_{\rm C2}}{dt} =\frac{(1-u)}{C_{2}}i_{L}-\frac{1}{R_{O}C_{2}}v_{\rm C2} \tag{1}\]  
As mentioned before, the architecture of the DCMG has two main buses in different voltage level, so the model obtained can be used for both versions, the three 380 V boost converters linked to the primary bus and the 190 V boost converter in the secondary bus.