## 2 Methodology
### PVTC-Based Analysis for Multi-Gate Circuits  
Transient fault analysis for single gates is clearly not sufficient. Digital logic circuits typically consist of hundreds of gates, and there is complex logic dependency between them, meaning that the  
Figure 5: Three-dimensional SVTC curves for multi-input gates. (**a**) SVTC of NAND gate; (**b**) SVTC of NOR gate. Figure 6: Transient fault rate calculation for an inverter with input “one”. pdf of the output of one gate is the pdf of the input of another gate. The pdf calculation result for the single gate obtained in Section 2.1 is a series of discrete points, which is not suitable for estimating the pdf for gates in the next stage. Therefore, some approximation procedures are required, and the Riemann sum \(p(V_{in})dV_{in}\) is applied to substitute for the integration \(\left\{p(V_{in})dV_{in}\right.\) in Equations (3) and (4). We then obtain the modified pdf calculation equation for single- and multi-input gates in Equations (6) and (7), respectively. \[p\left(V_{out}\right)\cdot dV_{out}\cong P\left(V_{out2}<V_{out}\leqslant V_{ out1}\right)\cong\sum\limits_{i}p\left(V_{in,i}\right)dV_{in} \tag{6}\]  
\[p\left(V_{out}\right)\cdot dV_{out}\cong P\left(V_{out2}<V_{out}<V_{ out1}\right)\cong\sum\limits_{i}p\left(V_{out,i}\right)\cong\sum\limits_{i}p \left(V_{int1,i}\right)dV_{in1}p\left(V_{in2,i}\right)dV_{in2} \tag{7}\]  
where \(\left(V_{in,i},V_{out,i}\right)\) or \(\left(V_{in1,i},V_{in2,i},V_{out,i}\right)\) is the \(ith\) point on the SVTC curve with \(V_{out2}<V_{out,i}\leqslant V_{out1}\). However, the functional complexity of actual circuits usually results in re-convergent fan-out characteristics, which causes different input ports of one gate to be interdependent. The full adder in Figure 7 is an illustration of re-convergent fan-out characteristics. As shown in Figure 7, the output signal \(C\) for the full adder circuit is determined by the inputs of gate \(G_{5}\), \(N_{1}\) and \(N_{2}\). Port \(N_{1}\) is the output of NAND gate \(G_{3}\) and is determined by the root input signals \(A\), \(B\), and \(D\). Port \(N_{2}\) is the output of NAND gate \(G_{4}\) and is determined by \(A\) and \(B\). Therefore, the two input ports of gate \(G_{5}\) are not independent. Thus, in the pdf calculation of the output signal \(C\) of \(G_{5}\), the correlation between input ports \(N_{1}\) and \(N_{2}\) must be considered, as the calculation may otherwise lead to inaccurate results. To solve this problem, the pdf calculation formula Equation (7) is adapted by considering the dependence between \(N_{1}\) and \(N_{2}\) because these two signals are both related to root inputs \(A\) and \(B\). The total probability formula Equation (8) is applied to estimate the pdf of the output signal \(C\), which considers conditional probability of input ports \(N_{1}\) and \(N_{2}\) of gate \(G_{5}\) on the root input signals \(V_{A}\) and \(V_{B}\). \[ \begin{array}{c}p\left(V_{\text{C}}\right)\cdot dV_{C}\cong P\left(V_{\text {C2}}<V_{\text{C}}\leqslant V_{\text{C1}}\right)\cong\sum\limits_{i}P\left(V _{\text{C},i}\right)\\ \cong\sum\limits_{V_{A,i},V_{B,i}}\sum\limits_{i}p\left(V_{N1,i}|V_{A}=V_{A,i},V_{B}=V_{B,j}\right)dV_{N1}\cdot p\left(V_{N2,i}|V_{A}=V_{A,i},V_{B}=V_{B,j} \right)dV_{N2}\end{array}  \tag{8}\]  
In Equation (8), point \(\left(V_{N1,i},V_{N2,i},V_{\text{C},i}\right)\) is the \(ith\) point on the SVTC curve of gate \(G_{5}\) with \(V_{C2}<V_{C,i}\leqslant V_{\text{C1}}\). \(\left(V_{A,j},V_{B,j}\right)\) is each input voltage pair of the discrete three-dimensional SVTC curve acquired by SPICE DC analysis, as shown in Figure 5. The conditional probability \(p(V_{N2,i}\,|\,V_{A}=V_{A,j},V_{B}=V_{B,j})\) can be calculated directly because \(V_{N2}\) is determined by \(V_{A}\) and \(V_{B}\) only, whereas \(V_{N1}\) is determined by \(D\) and \(N_{0}\), and the pdf estimate of the conditional probability \(p(V_{N0,i}\,|\,V_{A}=V_{A,j},V_{B}=V_{B,j})\) can be acquired by a similar method to that of \(N_{2}\).