# Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency
## 4 Optimal Encoding Schedules in Partially Parallel Encoding
### Partially Parallel Processing in 5G NR LDPC Encoding
Instead of shifting one bit group at a time, this schedule requires that all information bits, and later core parity bits, are available in registers. Consequently, it is often required to wait for information bits to be written to registers from the serial input stream [35]. However, assuming that the double buffering is available at the data input, this stall time can be avoided. The GF(2) sum of shifted vectors should be calculated using XOR gates placed in a tree-like structure. The required number of clock cycles for one codeword encoding is at least 46 (\(m_{b,\text{BG1}}\)) for BG1 codes and at least 42 (\(m_{b,\text{BG2}}\)) for BG2 codes, which is significantly higher when compared with the column-based parallel encoding. However, the required number of CSs is reduced: 26 for BG1 codes and 14 for BG2 codes [35]. Again, it is necessary to use the larger of these two numbers because of the flexibility. The encoder information throughput can be calculated as follows:  
\[Thr=\frac{k_{b}Zf_{CLK}}{N_{CPC}}. \tag{32}\]  
where \(f_{CLK}\) is the encoder's operating frequency, and \(N_{CPC}\) is the number of clock cycles necessary for a single codeword encoding -clocks per codeword. Since CSs take the largest amount of logic resources, hardware usage can be approximately expressed in the number  
Figure 4: Encoding schedule for BG1 codes when processing the entire base graph matrix row at the same time. Numbers represent the ordinal of the clock cycle in which the corresponding CPM is processed. Figure 3: Encoding schedule for BG1 codes when processing the entire base graph matrix column at the same time. Numbers represent the ordinal of the clock cycle in which the corresponding CPM is processed. of CSs. For a better comparison of approximate hardware usage efficiencies for described encoding schedules, a circular shifter's efficiency is defined as follows:  
\[Eff_{CS}=\frac{Thr}{N_{CS}}, \tag{33}\]  
where \(N_{CS}\) is the number of used CSs. This parameter values calculated for the longest codewords (\(k_{max,\text{BG1}}=k_{b,\text{BG1}}Z_{max}=8448\), and \(k_{max,\text{BG2}}=k_{b,\text{BG2}}Z_{max}=3840\)) are summarized in Table 1. As can be inferred from the results, the most efficient schedule is serial processing, although it gives the lowest throughput. Highly parallel encoding schedules are less efficient because a large number of shifters are unused, which is a consequence of the fact that the base graph matrix's rows and columns are not fully filled. For the reasons of efficiency, in this paper, serial CPM processing is implemented for codes with high lifting size (\(Z>192\)). Only one CS is used. However, the CS is designed in such a way that it can be reconfigured to reuse logic resources and to work as two or more independent CSs if codes with lower lifting size values are used. The CS design and the entire encoder architecture are described in detail in Section 5. Since more than one CS is available for shorter codes, the serial encoding schedule can be then parallelized to increase the HUE. The proposed encoding schedule processes more than one row at a time. Its example of a situation when four shifters are available is shown in Figure 5. The encoder takes information bit groups, shifts each of them, and calculates intermediate results for all \(\lambda\) vectors. During the next four rows processing, core parity bits are calculated and prepared for calculation of additional parity bits. Using the described multirow serial schedule with four CSs, the encoding time can be reduced to 180 clock cycles for BG1 codes and 94 clock cycles for BG2 codes. However, during encoding, even three out of four available CSs are frequently idle due to the PCM's structure. This is easily noticeable in Figure 5 for all rows used in additional parity bits calculation. The reason for such PCM design is an attempt to avoid pipeline conflicts