## 1 Introduction  
Time-to-digital converters (TDCs) are core components of timing-related systems and are used to convert a time interval into a digital one with sub-nanosecond accuracy. Initially, TDC technology was investigated in high-energy nuclear science experiments to measure charged-particle time-of-flight (ToF) [1]. Then, momentum and trajectory data were obtained to determine the particle type [2, 3]. TDC is often used in other fields, such as positron emission tomography (PET) [4], laser radar [5], and all-digital phase-locked loops [6]. Currently, TDCs are primarily implemented on either application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Although ASIC-based TDCs can achieve picosecond-level precision [7], the unique reconfigurability of FPGA technology makes its design extraordinarily flexible. Additionally, with the continuous development of FPGA technology, cost performance has been continuously improved so that FPGAs are excellent for low development cost and fast prototyping [8]. Therefore, FPGA-based TDCs have become more and more popular in the past decade [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]. A typical FPGA-based TDC structure contains a coarse counter and a time interpolation module. The former provides a more extended measurement range, which runs at the system clock rate, and the latter yields a sub-clock period resolution. Then, the coarse timestamp (given by the coarse counter) and the fine timestamp (given by the time interpolation module) are combined to obtain the timestamp representing the moment when a hit signal arrives. The time interpolation method of FPGA-based TDCs is mainly focused on the tapped delay line (TDL) [9, 10, 11, 12, 13, 14, 15, 16, 17], which exploits the fast carry-chain resources inside the FPGA as a delay unit to form a long delay line, covering one system clock cycle. However, ultra-wide bins, which are natural TDL and TDC bottlenecks, inevitably deteriorate the time resolution, differential nonlinearity (DNL) error, and integral nonlinearity (INL) error. To extend the resolution beyond its intrinsic cell delay, researchers have been investigating WU-A and WU-B methods proposed by [PERSON] in 2008 [10], as the accuracy could be enhanced to less than 10 ps [13; 15]. However, its DNL is more than two least significant bits (LSBs). In addition, to achieve a desirable resolution, relatively long delay lines (including more than 100 delay units) must be built, which would consume a lot of the FPGA's internal resources. Therefore, TDL-based TDCs are not the best choice due to the performance of DNL and resource cost. It is necessary to find a TDC structure that would be well balanced in terms of resolution, dead time, and resource consumption for medium performance requirements. From a structural point of view, there are mainly two resource-saving time interpolation methods of FPGA-based TDCs. Firstly, the multi-phase clock TDC samples the hit signal simultaneously via a few phase-shifted clocks. The result indicates the fine timestamp of the hit signal. Since multi-phase clocks are easy to implement in FPGA and are almost insensitive to changes in temperature and supply voltage, this method has a short dead time and better DNL performance. However, because the setup time is challenging for high-frequency systems, a relatively poor resolution (between 80-100 ps) is obtained, limiting the range of applications [18; 19; 20]. Secondly, the ring oscillator (RO) method follows the Vernier principle and saves resources by folding the TDL's long carry-chains into a looped structure. Its resolution is the period difference between two ROs working in Vernier mode. Smaller DNL and INL (less than one LSB) will be obtained due to the disappearance of the ultra-wide bins. This method could have potentially achieved a resolution of lower than 10 ps.