## 4 Evaluation
Figure 6: Model architecture of the TinyML applications used in the evaluation: (**a**) TinyConv for speech recognition, (**b**) gesture recognition. As a result of comparing the clock latency in each layer, the CNN layer decreased the clock latency up to 94.25%. These MAIL framework results help determine the MAs configuration used in TinyML. Table 2 shows the combined cycle latency across layers compared to other existing libraries. Despite the cycle latency overhead in the FC layer, the reduction in the CNN layer was dominant, decreasing by \(-\)84.32% and \(-\)61.32% in the first and second cases, respectively. In the FC layer with input and output nodes, the delay due to iterative MA enable varies according to the area size that supports the input vector and weight matrix product. Hardware accelerators inherently exhibit a trade-off between performance and resource utilization. Therefore, when evaluating MA, it is essential to consider both performance, represented by delay, and resource utilization, such as hardware area, simultaneously. To address this, we decided to use the area-delay product (ADP) metric, calculated as the product of hardware area and delay. The designer utilizing MAIL can rapidly conduct design exploration based on the prototype's ADP. Figure 8 shows the ADP results with the \begin{table}
\begin{tabular}{c c c} \hline \hline \multirow{2}{*}{**Model**} & \multicolumn{2}{c}{**Total Latency (Cycle)**} \\ \cline{2-3}  & **Speech Recognition** & **Gesture Recognition** \\ \hline Baremetal & 53,099,517 & 9,298,534 \\ X-Cube-AI & 3,677,731 & 1,151,904 \\ TFLM & 3,959,653 & 895,776 \\ MA (ours) & **576,399 (\(-\)84.32\%)** & **346,534 (\(-\)61.32\%)** \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Measurement of the neural network total cycle latency when using baremetal firmware, existing inference libraries implemented for TinyML application, and MA inserted TinyML firmware. Total cycle latency reduction was compared to the smallest value, e.g., X-Cube-AI selected in speech recognition application to comparison. Figure 7: MAIL framework cycle latency measurement for each neural architecture layer of the MA inserted TinyML applications: (**a**) speech recognition; (**b**) gesture recognition. area and cycle latency of the generated MA RTL for the MA coverage size sweep of the FC layer computation. We used Synopsys Design Compiler as the synthesis tool to measure the area of the MA RTL. The first case has \(4000\times 4\) size FC layer fc, and we generated a size of MA that divides input nodes into 1, 5, 10, 50, 100, 250, 500 times. When these MA replaced into the TinyML software, we measured the clock latency at MAIL due to repeated calls, and calculated the ADP between the synthesized area from generated MA RTL. Second case has \(224\times 16\) size FC layer fc\({}_{1}\). We varied the divide values to 1, 7, 8, 14, 28 and measured ADP by MA. The results show that iteratively using smaller-sized MAs to accumulate the output achieves better ADP than increasing the area based on the acceptable size of the input vector and weight matrix. Table 3 compares the state-of-the-art accelerator prototyping frameworks with the proposed MAIL framework. Ref. [21] targets RISC-V SoC and controls accelerators via MMIO or custom ISA, while [22] is designed for functional profiling of standalone CNN accelerators. Unlike other frameworks that provide only one approach--either RTL simulation or function modeling--based on their abstraction level, MAIL offers a mixed level of abstraction. Unlike the other two frameworks, MAIL targets MCUs and therefore does not utilize DRAM. The workload in [21] replaces neural network models with matrix multiplication due to the substantial time required for full RTL simulation. In the evaluation, all cases used a 16 \(\times\) 16 systolic array.