## 2 Computational Simulation Models
### Smart Transformer
#### 2.1.3 Low Voltage Inverter  
An overall representation of the ST's LV inverter model and associated control structure is shown in Figure 5. This inverter is in charge of forming the LV AC network to which other resources are to be connected. The power stage of the LV inverter is modeled in the _AC/DC Inverter_ block. The LV inverter operates in grid-forming mode, controlling the magnitude and phase of the voltages applied to the LV AC network. For that reason, the interface of the LV inverter with the LV AC network was modeled using controlled voltage sources. According to the DAM approach, the modulation mechanisms (e.g., PWM, SPWM or others) can be neglected without relevant impacts in the dynamics of the controller of the LV inverter [34]. The interface with the LV DC bus is implemented using a controlled current source. The power transference between the LV network and the LV DC bus is determined by Equation (12), where \(IDC_{LVinv}\) is the DC current in the controlled current source interfacing the LV DC bus, \(PLV_{Inv}\) is the active power in the LV inverter, \(VDC_{LV}\) is the DC voltage in the LV DC bus, \(Va_{LV},Vb_{LV},Vc_{LV}\) are the LV AC voltages in each phase and \(Ia_{LV},1b_{LV},Ic_{LV}\) are the AC currents in each phase. \[IDC_{LVinv}=\frac{PLV_{Inv}}{VDC_{LV}}=\frac{1}{VDC_{LV}}(Va_{LV}\cdot Ia_{LV }+Vb_{LV}\cdot Ib_{LV}+Vc_{LV}\cdot Ic_{LV}) \tag{12}\]  
Regarding the voltage in the LV DC bus, it is determined according to Equations (13) and (14), where \(C_{LV}\) is the capacitance of the LV DC bus, \(ILV_{cap}\) is the current flowing to \(C_{LV}\), \(IDAB_{LV}\) is the DC current in the secondary stage of the isolated DC/DC converter, \(IDC_{LVinv}\) is the DC current in the LV inverter, \(IDC_{LVinv}\) is the current exchanged between the LV DC bus and the LV DC network and \(I_{ESS}\) is the current in the local ESS. \[VDC_{LV}=\frac{1}{C_{LV}}\int\,ILV_{cap}dt \tag{13}\]  
\[ILV_{cap}=IDAB_{LV}+IDC_{LVinv}+IDC_{LVg}+I_{ESS} \tag{14}\]  
Figure 4: DC-DC converter stage model. Figure 5: Block diagram of the ST’s Low Voltage inverter. Given that a fixed transformation ratio \(N\) was chosen for the isolated DC/DC converter, the ST's MV inverter is also responsible for regulating the voltage in the LV DC bus. Such a relationship is expressed by Equation (15), which can be obtained combining Equations (2), (3), (11), (13) and (14). Equation (15) shows that \(VDC_{LV}\) is regulated only through \(IDC_{MVinv}\), given that the remaining current variables will vary according the existing load/generation in the hybrid distribution network and the local ESS power set-point. \[\mathbf{VDC_{LV}}=\frac{1}{C_{LV}-N^{2}C_{MV}}\int\left(IDC_{LVinv}+IDC_{LVg}+I_{ ESS}-N\left(\mathbf{IDC_{MVinv}}+IDC_{MVg}\right)\right)dt \tag{15}\]  
Similarly to the MV inverter stage, a coupling LC filter used to connect the LV inverter to the LV AC network was also considered in the modeling approach, since it affects the main dynamics of the LV inverter stage. The LC filter was dimensioned according to Equations (4) and (5). \(Z_{0}\) is given by Equation (16), where \(VDC_{LVn}\) is the nominal voltage of the LV DC bus and \(ILVmax_{p}\) is the maximum AC current peak value of the LV inverter. A \(f_{c}\) value of 2 kHz was considered for the LC filter to connect to the LV inverter, according to the considerations already made for the LC filter connected to the MV inverter stage. \[Z_{0}=\frac{VDC_{LVn}}{ILVmax_{p}} \tag{16}\]  
Regarding the control structure, the _Voltage Control_ generates a three-phase AC voltage (\(VAC_{LVinv}\)) from the references for frequency (\(f_{LV}\)) and magnitude (\(|VAC_{LVinv}|\)) according to Equation (17). \[VAC_{LVinv}= \begin{bmatrix}V_{a}\\ V_{b}\\ V_{c}\end{bmatrix} =|VAC_{LVinv}|\cdot \begin{bmatrix}sin\left(\int f_{LV}\mathrm{ d}t\right)\\ sin\left(\frac{-2\pi}{3}+\int f_{LV}\mathrm{d}t\right)\\ sin\left(\frac{2\pi}{3}+\int f_{LV}\mathrm{d}t\right)\end{bmatrix}