## 1 Introduction and Problem Formulation
### Transformation of the Petri Net-Based Description into Verilog HDL Code  
In order to implement the Petri net-based system within an FPGA, the model ought to be transformed from the graphical notion into the hardware description language. There exist several techniques that allow for such a transformation. In this paper, we follow the technique shown in previous authors' works [13; 41; 43], while as a hardware language, Verilog HDL is applied. Note that such a description is essential for further functional reduction (described in the next subsection). In general, the method is based on the description of the behavior of the system. The Verilog model consists of three main blocks. The first one refers to the transitions; the second represents the states (concurrently marked places); while the remaining one is related to the binary outputs of the Petri net-based concurrent control system. Let us describe each of them in detail. The behavior of transitions is described by logical equations. Each equation is formulated as a logical conjunction of input places and conditions of a particular transition. From the technical point of view, continuous assignments (_assign_ statements) are applied. Listing 1 shows the equations for the concurrent control system specified by \(\mathcal{N}_{1}\). There  
Figure 2: An exemplary concurrent control system modeled by an interpreted Petri net \(\mathcal{N}_{1}\). are ten transitions in the presented interpreted Petri net. Each assignment corresponds to the logical condition that enables a particular transition. For example, the first line continuously assigns a logical expression: p[1]&s to transition \(t_{1}\). This means that transition \(t_{1}\) is enabled if two conditions are fulfilled: (1) \(p_{1}\) is marked (contains a token), and (2) the input signal \(s\) is active (high value). Another line (3) assigns a logical condition p[2]&p[3]&p[4] to to[3], which means that transition \(t_{3}\) is enabled when all three of its input places (\(p_{2}\), \(p_{3}\), \(p_{4}\)) contain tokens. ```
01:assign t[1]=p[1]&s; 02:assign t[2]=p[5]&e[1]; 03:assign t[3]=p[2]&p[3]&p[4]; 04:assign t[4]=p[6]&e[2]; 05:assign t[5]=p[7]&x[1]&x[2]&x[3]; 06:assign t[6]=p[7]&x[1]&x[2]&x[3]; 07:assign t[7]=p[7]&x[1]&x[2]&x[3]; 08:assign t[8]=p[8]&x[3]; 09:assign t[9]=p[9]&x[2]; 10:assign t[10]=p[10]&x[1];
```  
Listing 1: Transition equations for the concurrent control system modeled by \(\mathcal{N}_{1}\). States (markings) of the system are represented by the procedural assignments, within the _always_ block. Such a description involves equations for places of the interpreted Petri net. In the proposed solution, each place is represented by a single register. Therefore, markings simply refer to the set of active registers (places), in exactly the same manner as in the case of the Petri net-based model. The switching of markings depends on the active transitions (that are fired); thus, the equation for each place includes a function of its input transitions. The Verilog description of states (places) for the concurrent control system specified by \(\mathcal{N}_{1}\) is shown in Listing 2. It is assumed that the system is oscillated by a clock signal (denoted as _clk_). Moreover, there is an asynchronous _reset_ signal that zeroes the system (that is, resets to the initial marking). There are ten places in the presented interpreted Petri net. The first statement (line 3) in the presented listing refers to zeroing the system to the initial state. Simply, if the _reset_ signal is active, the binary value 0010110000 corresponding to the initial marking is assigned to the vector p. Note that _reset_ is asynchronous, therefore it is activated despite the clock signal. Otherwise (that is, _if reset_ is not active), each entry of the vector p is assigned by an equation according to the token distribution in particular places.