## 1 Introduction  
NAND flash memory has played an important role in realizing various innovative digital products such as digital cameras, smart-phones, and ultra-high-capacity SSDs [1, 2]. Especially since the late 2000's, 3D vertical-NAND (VNAND) flash memory [3, 4, 5, 6] has been a key technology for sustaining a continuous capacity growth in flash-based storage systems by overcoming various technical challenges in scaling 2D NAND flash memory [7, 8]. For example, 2D NAND flash memory technologies had encountered the fundamental limits to scale below the 10 nm process technology [6] because of the low device reliability (due to severe cell-to-cell interference and the reduced number of stored charges in a flash cell (a flash cell is the basic unit that stores charge, i.e., bit information)) and high manufacturing complexity (e.g., EUV lithography equipment). However, by increasing the number of vertical stack layers, 3D VNAND flash memory has successfully contributed to sustaining the 50% per year growth rate in the NAND flash capacity [9], which established flash-based storage systems as de facto standards from mobile systems to high-performance enterprise environments. Although 3D process technology successfully enabled us to break through the scaling-down limit of conventional 2D planar NAND flash memory, 3D VNAND flash memory has encountered new challenges due to its unique 3D architecture and new flash cell structure [10, 11, 12, 13, 14, 15, 16, 17, 18, 19]. For example, due to the three-dimensional (like cubic structure) block organization of the 3D VNAND device, there is a strong variability in electrical characteristics between flash cells depending on their vertical locations within a block,which was not shown in 2D planar NAND device [10, 11, 12, 14, 16]. (In NAND flash memory, a _page_ is the unit of read and write operations, and hundreds of pages (e.g., 576 pages [20]) compose a _block_, the unit of erase operations.) Furthermore, most commercial 3D VNAND flash memories adopt cylindrical charge trap (CT)-type cell structures (e.g., TCAT [5], p-BICs [21] and SMArT [22]). The 2D planar NAND flash memory stores charges in a conductor called _the floating gate_, whereas the 3D VNAND flash memory stores bit information in a non-conductive (i.e., dielectric) layer within a CT-type cell called the _SiN trap layer_. The different cell structure of 3D VNAND flash memory causes new reliability issues such as early charge loss [15, 17, 18] or lateral charge spreading [13, 14, 19], which did not need to be considered in 2D planar NAND flash memory (more details are described in Section 2). Although many researchers have attempted to improve the performance or reliability of the 3D NAND device based on the understanding of its electrical and physical characteristics, there are few studies to optimize the manufacturing process for the successful mass production of this new device. As explained before, since the overall organization and basic cell structure of 3D NAND flash memory are considerably different from those of 2D NAND flash memory, its failure mechanisms are also quite different from those of the 2D planar device. For example, the process of stacking layers can introduce a variety of new failure sources along the vertical direction. Moreover, the vertical etching process can cause severe attacks on flash cells, which is fatal to the quality of flash memory. Therefore, to efficiently guarantee the quality of 3D NAND flash memory with a high yield and low cost, it is necessary to revisit the test methodology suitable for the new 3D VNAND device. Unlike the existing 2D planar device, each flash cell in the 3D VNAND device is serially connected along the \"channel hole\" manufactured using a _vertically successive_ etching process from the topmost layer to the bottom layer.