# Design of Low-Power ECG Sampling and Compression Circuit
###### Abstract  
Compressed Sensing (CS) has been applied to electrocardiogram monitoring in wireless sensor networks, but existing sampling and compression circuits consume too much hardware. This paper proposes a low-power and small-area sampling and compression circuit with an Analog-to-Digital Converter (ADC) and a CS module. The ADC adopts split capacitors to reduce hardware consumption and uses a calibration technique to decrease offset voltage. The CS module uses an approximate addition calculation for compression and stores the compressed data in pulsed latches. The proposed addition completes the accurate calculation of the high part and the approximate calculation of the low part. In a 55 nm CMOS process, the ADC has an area of 0.011 mm\({}^{2}\) and a power consumption of 0.214 uW at 10 kHz. Compared with traditional design, the area and power consumption of the proposed CS module are reduced by 19.5% and 31.7%, respectively. The sampling and compression circuit area is 0.325 mm\({}^{2}\), and the power consumption is 2.951 uW at 1.2 V and 100 kHz. The compressed data are reconstructed with a percentage root mean square difference of less than 2%. The results indicate that the proposed circuit has performance advantages of hardware consumption and reconstruction quality. compressed sensing; electrocardiogram; wireless sensor networks; analog-to-digital converter; approximation calculation +
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data after the ADC converts the ECG signal. [PERSON] et al. [10] proposed a general sampling and compression architecture and evaluated the performance of two implementation modes. The results highlighted that the digital circuit implementation had significant power consumption advantages. [PERSON] et al. [11] implemented a pipeline architecture for a sampling and compression circuit that processed data at high speed and bypassed the computation of unimportant input samples by a wake-up call, reducing the power consumption of the hardware. [PERSON] et al. [12] adopted a new method to deal with the saturation problem during the CS compression calculation, where the corresponding circuit adapted the energy distribution of the input signal to maximize the information contained in the measurement. [PERSON] et al. [13] presented a novel sampling and compression circuit that could simultaneously compress and encrypt data. The circuit had high compression efficiency while guaranteeing reconstruction quality, and the Compression Factor (CF) ranged from 2 to 16. In the existing ECG sampling and compression circuits, two problems lead to excessive hardware consumption. One is that the power consumption of ADC is relatively high, and some circuits employ external ADC causing unnecessary waste of resources due to functional redundancy. The other is that matrix compression adopts accurate calculation, and the compressed data are stored in registers imposing significant area and power consumption. Since CS is a lossy algorithm and considering an ECG signal, as long as the Percentage Root Mean Square Difference (PRD) of the reconstructed data is less than 9%, it can be used for medical diagnosis [14]. This paper proposes an ECG sampling and compression circuit consisting of a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for sampling and a CS module for compression. The CS module performs accurate and approximate calculations for the high and low parts of the ECG signal, respectively, based on the designed approximate addition calculation. Additionally, pulsed latches are used to store compressed data by optimizing the timing of the circuit. This paper is structured as follows. In Section 2, the CS algorithm and the sampling and compression circuit are introduced and reviewed, and the problem of excessive hardware consumption in the existing circuits is pointed out. Section 3 presents the proposed scheme, and the sampling and compression circuit is designed based on the optimized ADC and CS module. The simulation results and circuit implementation are reported and discussed in Section 4.