# Latency-Aware Accelerator of SIMECK Lightweight Block Cipher
## 1 Introduction
### Existing Crypto Accelerators for Securing Low-Resource Embedded Devices  
As we mentioned earlier, the embedded devices determine the applications (such as RFID, WSNs, WBANs, and IoTs) that require efficient implementations of the cryptographic primitives for secure communication along with limited resources and power consumption. Concerning [23; 24; 25], it is essential here to mention that the sensor nodes are the building block that governs communication between several embedded devices/applications. To provide several security services in wireless sensor nodes, the hardware accelerators of various cryptographic algorithms (including symmetric and asymmetric) are published in [2; 6; 7; 8; 9; 15; 20; 26; 27; 28; 29; 30; 31]. The more insight particulars are highlighted in the text that follows. Some ASIC (application-specific-integrated-circuits) and FPGA (field-programmable-gate-array) demonstrations of many lightweight block ciphers for securing wireless sensor nodes are presented in [2; 6; 7; 8; 9; 15; 20; 26; 27; 28; 29; 30; 31]. Under UMC55 (United Microelectronics Corporation) process technology, a lightweight RECTANGLE algorithm is implemented as hardware accelerator for data encryption and decryption on wireless sensor nodes in [2]. The hardware area is reported without the consideration of consumed power. A reconfigurable crypto hardware accelerator of elliptic-curve cryptography (ECC) on wireless sensor nodes is implemented in [6]. A lightweight encryption and decryption protocol from Advanced Encryption Standard (AES) algorithm is described in [7] for securing wireless sensor nodes. Similar to [2], the area results are only reported on FPGA without the consideration of consumed power. The evaluations of hardware (on 180 nm and 90 nm process technologies), software (on microcontrollers), and co-design implementation of AES encryption algorithm are performed in [8] for wireless sensor nodes. In [9], the security of IEEE (Institute of Electrical and Electronics Engineering) 802.15.4 suite [32] is investigated for wireless sensor nodes by providing a compact implementation of the prime and binary elliptic-curves. In [15], a SIMON block cipher is implemented on FPGA for low-resource embedded devices with an emphasis on energy and power parameters. Scalar and pipelined implementation approaches were examined. The implementation results demonstrate that the former require 39% less hardware resources and consume 45% less power. The latter result in 12 times the throughput and consume 31% less energy. Error detection schemes for lightweight block cipher, i.e., KLEIN, is presented in [26]. The proposed fault diagnosis architectures are for linear and nonlinear components of this cipher. They also presented the notion of fault space transformation for lightweight cryptography and provided its potential complications. In [27], the construction of hardware for the lightweight cryptographic block cipher QARMA including error detection mechanisms is presented. The family of lightweight tweakable block ciphers, which is targeted towards the applications such as key hash function construction for low-resource embedded devices and memory construction, is named QARMA. An efficient architecture for LED block cipher is described in [28]. The implementation results are given on Spartan-3 FPGA. Their design utilizes 114 slices and achieves an operational frequency of 167.34 MHz. Recently, a hardware design of an area efficient high-speed crypto processor is presented in [29] for 4G LTE (Long Term Evolution or System Architecture Evolution). Their design contains four ciphers including from stream and block variants. The implemented algorithms are: (i) KASUMI, (ii) SNOW-3G, (iii) MILENAGE, and (iv) ZUC. The implementation results are given on 90 nm ASIC (application-specific-integrated-circuit) technology. In [20], a hardware implementation of a SIMECK32/64 block cipher is provided for the transceiver of IEEE 802.15.4.