## 5 Results
### Simulation Results
Specifically, the undershoot is limited to 3%, and the settling time is reduced to 4 ms. However, due to parasitic impedances, the system still shows a slight steady-state error, with the output voltage settling at 59 V instead of the targeted 60 V. In hardware tests, this error can be even more significant due to inaccuracies in the prediction model or discrepancies between the real parameters and those used for calculating the reference current (Equation (7)). The proposed method combines the advantages of immediate inductor current control using Equation (7) with the steady-state stability provided by the PI controller used for the fine-tuning of the reference current, ensuring accurate and fast reference current adjustments. The IRC block ensures that the power input equals the power output under ideal conditions, while the PI regulator addresses any deviations caused by non-ideal components and external factors. The simulation results, as depicted in Figure 9, demonstrate that the proposed method is faster than the one presented in [18; 19; 20]. The system effectively mitigates the non-minimum phase problem inherent in FCS-MPC applications. It maintains the desired output voltage of 60 V without deviation and quick recovery from load changes. Specifically, the system shows a settling time of 2 ms and an undershoot of 3.2%. Additionally, there is no offset error, and the method remains fast, as the PI controller is only involved for offset correction, not in the reference current calculation block. The presence of sub-harmonic oscillations in the results can be attributed to the low temporal resolution associated with a sampling step of 5 \(\mu\)s. Future work will explore the potential for improvement by reducing the sampling step. In addition to the load resistor change results, two further simulations were conducted to validate the feasibility and robustness of the proposed converter under different dynamic conditions. The first simulation focuses on the startup behavior of the converter. As shown in Figure 10, the inductor current quickly increases to charge the capacitor to the desired voltage level of 60 V. The output voltage reaches its reference value within 3.5 ms with a small overshoot, demonstrating the effectiveness of the proposed control strategy in managing the initial charging process and achieving fast settling with minimal transient effects. Figure 8: Performance under step change in load with immediate reference current update based on (7), where the IRC block is employed directly without the involvement of the PI controller. The second simulation illustrates the system's response to an output voltage reference change, as depicted in Figure 11. At t = 0.1 s, a step-up change is applied to the output voltage reference, increasing it from 60 V to 80 V. Initially, the output voltage briefly decreases due to the non-minimum phase characteristic of the system, before it increases to reach the new reference value. The inductor current responds to the step change much faster, as seen in the simulation results. However, the dynamics of the boost converter cause the output voltage to respond more slowly. Despite this, the transition occurs without any significant overshoot, and the transient lasts for about 5 ms. This behavior demonstrates the ability of the proposed dual control strategy to handle non-minimum phase behavior while maintaining stable and accurate voltage regulation. Figure 10: Startup of the boost converter using the proposed method, showing the inductor current charging the capacitor to reach the 60 V output. Figure 9: Proposed FCS-MPC method under a step change in load from R1 = 45 \(\Omega\) to R2 = 22.5 \(\Omega\). It is important to note that while the FCS-MPC algorithm can operate in both CCM and DCM, it faces specific challenges in DCM. This is because the cost function tends to favor maintaining the zero-current state, particularly under light load conditions, which can lead to the system remaining in this state longer than desired.