## 6 Conclusions  
In this paper, two new implemented solutions for reducing the high power envelope fluctuations of the OFDM signal in vehicular communications are introduced. The first is in the time-domain to reduce the power fluctuations while the second is carried out in the frequency-domain in order to keep the demodulation slicer intact. To minimize the complexity of the second solution starting from the theoretical design of [11], we reduced the number of NNs by leveraging on the symmetry of the problem. Indeed, in the case of a QPSK modulation, this number has been reduced from 8 to 2, whereas, in the case of a DCM modulation, this number is narrowed from 24 to 6. Some other optimizations have also been developed to reduce size, increase bandwidth and speed up the computations.  
The models have been implemented on FPGA circuits and some clues are drawn for future designs. To validate them, we used the cubic metric, the BER and resources' consumption.  
Concerning the cubic metric, a slight error of 0.002 dB is observed in the case of Xilinx and 0.003 dB in the case of Altera with respect to simulations. This is justified by the residual error of the fixed-point calculation adopted by each of these constructors.  
To ensure that our implementations do not affect the performance of an OFDM communication system, we have plotted the BER in a real ECMA-368 standard, and, as it has been shown, it fits specifications perfectly.  
We compared the proposed solutions with those provided by Xilinx and Altera and we were able to conclude that the time-domain NN allowed a minimum consumption of resources and a higher maximum frequency regardless of the type of modulation. Finally, we have developed and implemented two versions of our algorithms in realistic architectures suitable for vehicular networks, and several guidelines are drawn for future implementations and optimizations in such networks approaching the implementation of OFDM on FPGA for vehicular communications.  
[PERSON] conducted FPGA simulations, design, implementation, optimization and writing. [PERSON] participates in the design, FPGA simulations, implementation, optimization, writing and algorithms. [PERSON] participates in the simulations, algorithms and the writing. [PERSON] participates in the algorithms and writing.  
This work has been partly funded by projects TERESA-ADA (TEC2017-90093-C3-2-R) (MINECO/AEI/FEDER, UE) and ELISA (TEC2014-59255-C3-3-R).  
The authors declare no conflict of interest. The funding sponsors had no role in the design of this research, in the analyses, interpretation data and decision to publish the results.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Solutions** & **FPGA Chips** & **RAM Blocks** & **DSP Blocks** & **LUTs** & **Max. Freq. (MHz)** \\ \hline Altera CFR & & 6 & 12 & 2801 & 95 \\ Time-domain NN (QPSK) & & 0 & 16 & 334 & 311 \\ Time-domain NN (DCM) & Cyclone III & 0 & 16 & 334 & 311 \\ Frequency-domain NN (QPSK) & & 0 & 24 & 617 & 106 \\ Frequency-domain NN (DCM) & & 0 & 46 & 3103 & 67 \\ \hline Altera CFR & & 6 & 20 & 1922 & 111 \\ Time-domain NN (QPSK) & & 0 & 16 & 334 & 311 \\ Time-domain NN (DCM) & Stratix II & 0 & 16 & 334 & 311 \\ Frequency-domain NN (QPSK) & & 0 & 24 & 499 & 106 \\ Frequency-domain NN (DCM) & & 0 & 40 & 1462 & 67 \\ \hline Altera CFR & & 6 & 24 & 1922 & 111 \\ Time-domain NN (QPSK) & & 0 & 16 & 334 & 421 \\ Time-domain NN (DCM) & Stratix III & 0 & 16 & 334 & 421 \\ Frequency-domain NN (QPSK) & & 0 & 24 & 499 & 143 \\ Frequency-domain NN (DCM) & & 0 & 60 & 1462 & 90 \\ \hline \hline \end{tabular}
\end{table}
Table 6: Resource consumption in the case of Altera FPGAs.