## 1 Introduction  
The digital front-end (DFE) of a radio receiver is used to convert the sample rate of the analog-to-digital converter (ADC) and filter out the remaining interference after the radio frequency (RF) front-end filters serve the role of initial band and channel selection. The channel with the desired signal is sharply filtered by a chain of digital filters in the DFE and the required signal-to-noise ratio (SNR) is achieved by sufficiently rejecting various types of blockers. The filtered signal channel from the DFE in the radio chip is typically passed over to the digital baseband processor or modern chip and at the same time the sample rate is reduced from the high ADC sample rate to acceptable rates for the baseband processor by means of downsampling in the DFE circuitry. This is in contrast to what is accomplished in the radio transmitter where upsampling or sample rate multiplication is carried out in the interpolation chain. The DFE in the radio receiver is a decimation chain and a cascade of digital filters are used in the DFE to attain the desired output SNR in an effective manner, namely, rather than using one digital filter with an extraordinarily large number of filter taps, a series of multistage digital filters are employed to attain the required SNR in a successive manner, reducing the total number of taps [1]. A host of literature deals with the digital front-ends in the radio receivers for wireless communication. A multirate subsampling front-end incorporates programmable digital decimation stages to accommodate variable bit rates in a software radio receiver in [2]. The front-end consists of digital down-converters or down-conversion mixers, comb-type channel select filters with decimation, and accumulators. Direct digital frequency synthesizers control the channel select filters and the accumulators. An integer-factor sample-rate converter for software-defined radio receivers is simulated in [3]. Implementation efficiency is emphasized in the front stages by using a decimate-by-16 multiplier-free cascaded integrator comb filter while high performance is emphasized in the back stages by using a 3-stage decimator. In addition, an increasing hardware effort is needed as the sample rate (and thus the oversampling ratio) decreases down the decimation chain, favoring placing a fractional sample-rate converter in the front stages of the chain [4]. The importance of decimation filters will continue to expand, as the high-speed data from a fast analog-to-digital converter need to be downsampled prior to ingestion by a processor [5]. As another software-defined radio receiver, the implementation in [6] takes a discrete-time approach at the analog baseband prior to the analog-to-digital converter. A programmable fractional rate-change digital front-end for software-defined radio is designed in [7], which comprises cascaded integrator comb filters, half-band filters (for decimation by 2), finite-impulse-response (FIR) filters, and polyphaser filters with numerically controlled oscillators (for decimation by variable factors). A fractional sample-rate conversion filter for a software radio receiver is implemented in a field-programmable gate array in [8]. It is composed of numerically controlled oscillators (based on phase accumulators and coordinate rotation digital computers or CORDICs), mixers (based on CORDICs), cascaded integrator comb (CIC) filters, and Farrow filters. The digital front-end in [9] uses several decimation and interpolation stages, which are implemented as polyphase filters. A channelizer that is well-suited to extracting multiple radio channels from a wideband input signal is simulated in [10] based on a reconfigurable filter bank. The filter bank is in turn based on decimation and interpolation. A tunable narrow-band digital front-end for delta-sigma ADCs is simulated in [11], which starts with a quadrature mixer followed by a complex mixer (with a tunable frequency) and a cascaded integrator comb decimator in between.