# Grating-Assisted Fiber to Chip Coupling for SOI Photonic Circuits
## 1 Introduction  
Silicon photonics platform has emerged as a key driver for building the next generation of low cost on chip optical interconnects. This has been necessitated by an ever increasing need for multichannel high performance computing as well as large capacity data storage servers along with the requirement of low energy per unit bit power consumption. Several groups have now reported significant breakthroughs in demonstrating passive and active silicon (Si) based on chip photonic components [1; 2; 3; 4; 5]. Primarily, three reasons are attributed to the preference of Si in integrated optics over other material platforms. The first being SOI architecture, characterized by the high index contrast of silicon compared to its oxide that allows for sub-micron scale single mode wire waveguides. The second being a bandgap that enables wideband transparency window over the communication channel (1.3-1.6 \(\upmu\)m). Finally, the availability of a mature silicon complementary metal oxide semiconductor (CMOS) microfabrication infrastructure which not only allows for implementing structures of nanoscale dimensions with high accuracy and repeatability, but also integrates them at a low cost, thereby allowing for large scale commercialization of photonic integrated circuits (PICs).  
A major issue facing silicon photonic chips is efficient coupling of light to and from optical fibers. The fundamental fiber mode is Gaussian in shape with a mode field diameter (MFD) of 10-11 \(\upmu\)m while the Si single mode waveguide is about 220 \(\times\) 500 nm in cross section. The huge mismatch ensures that when placed across from each other, only a tiny fraction of power can realistically couple. Fiber to chip coupling can be accomplished both in-plane and out of plane ways. The former is typically done through edge coupling by means of an adiabatic spot size converter [6; 7; 8]. It essentially involves a lensed fiber placed at the end facet of a chip with an inverse tapered Si spot size waveguide embedded in an overlay medium that matches the fiber cross section (see Figure 1). As light propagates throughthe wire waveguide (which converges to a spot), the mode expands adiabatically in the overlay resulting in a near perfect overlap with the fiber mode at the spot end. Inverse tapers have been found to yield losses as low as -0.36 dB/facet [8]. In addition, edge couplers tend to have a low polarization sensitivity and exhibit a broadband response of 200-300 nm. However, significant technological constraints arise while considering mass market deploying of edge coupling solutions. For one, the end facet has to be properly cleaved, polished and taper spot sizes of about 100 nm are required. Apart from that, only fiber-chip alignment accuracies of micrometer scale are tolerated. This makes wafer level testing and hence cost per chip extremely prohibitive. Another alternative is to employ out-of-plane techniques like surface grating couplers. It involves mounting a fiber vertically over the part of the chip containing grating features. Depending on the phase matching, the gratings will then channel light into the corresponding propagating mode in the Si wire waveguide. The number of grating lines and its lateral width is designed to match the fiber mode cross section. Since fibers can be placed at multiple locations on chip, non contact optical probing at waferscale is feasible, which is a key requirement for packaging low cost photonic circuits. However, the coupling performance of surface couplers is limited in terms of insertion loss as well as operational bandwidth when compared to edge couplers. In this review, we explore various kinds of high performance grating couplers that have been demonstrated on SOI, their design considerations and state of art. In addition, a brief overview of fiber to chip coupler device packaging solutions and wafer-scale testing from an industry perspective is provided.