# Stability of Single Electron Devices: Charge Offset Drift
## 2 Experimental Observations of Charge Offset Drift
### Silicon-Based Devices  
While metal-based devices show a large amount of drift and the transient relaxation phenomenon, all-silicon devices show neither effect. Silicon-based devices are usually fabricated through gate oxidation and etching of one or more layers of doped polySi gates to both form tunnel barriers in the silicon and provide carriers. A typical charge offset drift curve for an all-silicon device is shown in Figure 6[45]. Here, the device exhibits \(\Delta Q_{0}\approx 0.01e\) over the course of 15 days when the temperature is stable (middle panel and left side of lower panel). These data were measured in a device with electrostatically tunable tunnel barriers defined by a set of gates and their voltages (see Figure 1b). The same level of drift is seen in devices with fixed tunnel barriers prepared through a pattern dependent oxidation technique (PADOX) [31]. This remarkable difference between silicon-only devices and metallic devices will be explained below. Figure 6 does show some non-idealities in the device performance when all the experimental factors are not held fixed. Vertical red dashed lines represent temperature changes and black dashed  
Figure 6: Typical charge offset drift for an all silicon SED with electrostatically generated barriers. A very small amount of drift is observed. Note the vertical axis range in the middle plot. These data were taken while the temperature (indicated at the top of each panel for a range of data indicated by the double arrow) was stepped (each step is indicated by vertical red dashed lines) which shows the insensitivity of the silicon SED to temperature excursions. **Black** dashed lines represent liquid helium transfers into the cryostat and thus a mechanical disturbance. Reproduced with permission from reference [45], Copyright 2007, American Institute of Physics. lines represent liquid helium transfers and, therefore, a mechanical disturbance to the device. There is very little, if any, change in \(Q_{0}\) as a result of the mechanical disturbances for this device. However, abrupt changes in temperature can produce a measurable change in \(Q_{0}\). Figure 7 depicts the drift measured in another device from [45]. Here, the temperature was held between 20 to 40 mK during the entirety of the measurement. Black lines here also represent the mechanical disturbance of helium transfers. These data are plotted on a similar \(y\)-scale to that of the middle panel of Figure 6 and do exhibit some sensitivity to helium transfers. Though these devices are very stable, from the above data, it seems clear that all-silicon devices with electrostatic barriers are somewhat sensitive to temperature excursions and/or mechanical disturbances. In fact, these devices are also more sensitive than fixed-barrier PADOX devices [31]. This is probably a result of the increased number of gate voltages which are required to remain stable through mechanical or electrical disturbances in the tunable devices. However, this may depend on the details of fabrication since remarkable reproducibility has also been observed even after thermal cycling to room temperature [46] (see Figure 8 inset) or with months between measurements [30]. Thus, measurements of charge offset drift in the time domain reveal all-silicon devices (PADOX or electrostatic barrier devices) to be much more stable than metal devices. These results are summarized in Table 1.  
Figure 7: Charge offset drift measured in an Si/SiO\({}_{2}\) device with electrostatic barriers where the temperature was held constant between 20 to 40 mK. In general, very small drift is observed. Vertical dashed lines represent helium transfers and mechanical disturbances of the system where some change in \(Q_{0}\) is seen. Note the \(y\)-scale is quite magnified. Reproduced with permission from reference [45], Copyright 2007, American Institute of Physics.