## 5 Results
### Experimental Results in FPGA  
To validate the effectiveness of the proposed control strategy in a practical setting, FPGA-based experimental tests are conducted using the same parameters as in the simulation section. The experimental setup is illustrated in Figure 12, showing the Arty Z7 FPGA board connected to a PC for data acquisition and control implementation. The FPGA is programmed using HDL code generated from MATLAB HDL Coder. The FPGA implementation includes an Integrated Logic Analyzer (ILA) block to monitor internal signals, facilitating debugging and the validation of the control strategy. Notably, the tests utilize hardware-in-the-loop (HIL) techniques, with the entire system implemented within a single FPGA. This approach mitigates communication issues between the controller and converter model, and prevents clock mismatch problems, simplifying the hardware setup and reducing overall system complexity and cost. The experimental results obtained using the Integrated Logic Analyzer (ILA) are depicted in Figure 13, illustrating the controller's performance. In this test, the performance of the controller is evaluated by implementing a real-time model of the boost converter in the same FPGA. It is notable that the ILA records signals in integer form, necessitating that each signal amplitude be divided by \(2^{F}\), where \(F\) represents the number of fractional bits defined in MATLAB HDL Coder. Additionally, each sample in the ILA corresponds to 8 ns, reflecting the internal clock period of the Arty Z7 FPGA board. Figure 11: Response of the boost converter with the proposed method to an output voltage step from 60 V to 80 V at t = 0.1 s.  
Due to the difficulty in discerning the details of the signals directly from the ILA, the data are extracted in.csv format and subsequently plotted in MATLAB, providing a clearer visualization of the results, as seen in Figure 13. Figure 13 demonstrates that the output voltage closely reaches the target of 60 V, exhibiting no deviation and a stable response. The ripple in the output voltage can be decreased by reducing the sampling step of the controller, depending on the practical limitations of the converter and the power rate. Figure 12: The Arty Z7 FPGA board used for experimental testing of the controller. Figure 13: Steady-state performance maintaining 60 V output, obtained from experimental tests in the FPGA, represented by ILA. Additionally, the inductor current is maintained around 2 A, ensuring adequate power to sustain the output voltage at the desired 60 V. This precise current control enables the system to effectively adapt to the initial load of 45 \(\Omega\). Despite the clarity of steady-state performance, this figure does not capture the dynamic behavior of the controller, as it emphasizes steady-state rather than transient responses. Figure 14 illustrates the performance of the controller under a step change in load resistance, where the load resistance is varied from 45 \(\Omega\) to 22.5 \(\Omega\). This step change test further validates the proposed method's capability to handle dynamic load variations. The output voltage remains stable at 60 V, with the inductor current adapting smoothly to the new load conditions. Notably, the undershoot in the voltage is about 3.3% similar to the simulation test, and the output voltage is restored to around 60 V in less than 4 ms. These experimental results closely match the simulation results shown in Figure 9, demonstrating the effectiveness of the controller in minimizing transient deviations and quickly stabilizing the output during sudden changes in load. As shown in this section, the system response is consistent with simulation results, exhibiting a negligible undershoot and rapid settling time. This approach shows great potential for applications requiring precise voltage regulation and adaptability to changing load conditions. Moreover, it can be applied to any topology where the non-minimum phase issue makes it difficult to use horizon one FCS-MPC, enhancing control performance and stability.