# Energy-Aware Wireless Sensor Networks for Smart Buildings: A Review
## 3 Hardware Layer
### The Hardware Platform (Microcontroller and CPU)  
The hardware platforms (boards) are of two types: CPU-based and microcontroller-based [7]. First, the CPU-based platforms contain the following elements: CPU, RAM, ROM, Timer, and I/O ports, while Microcontroller-based hardware platforms include the same components as the CPU-based ones but on a single ship [8]. The Analog-to-Digital Converter (A/D) [9] receives the signal from the sensing module, converts it, and then transmits it to the processing unit, which can be either part of the hardware platform or part of the sensing module itself. Currently, most platforms used in a WSN are microcontroller based. Energy optimization at the hardware level can be achieved through the computer system architecture and the CPU architecture. In the computer system architecture, Harvard architecture [10] is a computer architecture that physically separates storage and signal pathways for instructions and data. In such architecture, instructions of a program can be stored in read-only memory, while data memory generally requires read-write memory. Because there might be more instruction memory than data memory, instruction addresses are wider than data addresses. Harvard has taken an application-driven approach by including hardware acceleration to optimize typical operations in WSN applications [11]. The Harvard event-driven system for WSN uses three techniques to reduce energy consumption [12]. Figure 1: WSN deployment criteria. Figure 2: WSN node Architecture’s layers. Lightweight event handling in hardware: For handling incoming interrupts, a specialized Event Processor is given responsibility for doing so. As a result, it removes the software overhead that provides event handling on a general-purpose processor. Hardware acceleration for typical WSN tasks: Modular hardware accelerators are included to complete regular application tasks such as data filtering and message routing. Application-controlled fine-grained VDD-gating: Addressing leakage current with architecture support for VDD-gating enables accelerator blocks to be powered off when unused. The most used CPU architecture in WSN nodes is the Reduced Instruction Set Computer architecture (RISC) [13]. This architecture is the one used in ARM CPUs that are energy efficient [14]. The RISC is an instruction set architecture (ISA) [15] that has a set of attributes that allows it to have lower cycles per instruction (CPI) than a complex instruction set computer (CISC). Most RISC architectures have fixed-length instructions (commonly 32 bits) and a simple encoding. One drawback of 32-bit instructions is reduced code density, which is more adverse, characteristic in embedded systems where RISC architectures were originally designed to serve. The architecture incorporates fewer clocks per Instruction. In contrast, the CISC processors use a higher clock rate to speed up processing, and that is why RISC architecture leads to consuming less energy. Here we present three types of microcontrollers [16]. First, PIC microcontrollers (Peripheral Interface Controller) [17] can operate over a wide frequency and voltage range, making frequency scaling possible. PIC16 microcontrollers have only one sleep mode, which was placed on the processor core. The PIC18 series have two sleep modes. The core is shut off if the peripherals are running, and vice versa for the second sleep mode. Second, The AVR microcontroller [18] follows the Harvard architecture. ATMega128 microcontroller, which belongs to the AVR family, is widely used in sensor nodes. CPU, Flash, EEPROM, and SRAM are single integrated chips. It has six power modes: Idle, ADC noise reduction, power-save, power-down, standby, and extended standby. Third, the MSP430 Microcontroller can be used for low-powered embedded devices [19]. The MSP430 also uses six different low-power modes, which can disable unneeded clocks and CPU. Table 1 illustrates the most used Microcontroller in WSN nodes. The input voltage provided in the table above is the maximum possible for each Microcontroller.