## 5 Proposed Quadrature Bandpass Continuous-Time Delta-Sigma ADC
### Quadrature Bandpass Continuous-Time Delta-Sigma ADC Circuit Design
#### 5.2.3 Four-Bit Quantizer
By constructing all capacitive elements from identical C\({}_{\text{U}}\)s rather than physically scaling capacitor dimensions, the layout achieves better matching and improved linearity. This technique minimizes the effects of process variations since all capacitive elements use identical building blocks, providing similar matching advantages as seen in thermometer-coded designs while maintaining binary-weighted functionality. The layout employs a sophisticated common-centroid technique where these identical unit capacitors are distributed symmetrically around a central point. This arrangement helps cancel out systematic process gradients and temperature variations across the array. The common-centroid pattern is clearly visible in the zoomed-in view of the unit capacitor structure, showing the careful placement and orientation of the identical elements. The structure features a top metal line serving as a common connection point, while individual bottom metal lines connect to the binary-weighted segments composed of the unit capacitors. The reference voltages V\({}_{\text{REFN}}\) and V\({}_{\text{REFP}}\) are routed through switches to each segment, enabling the binary-weighted switching operation during the conversion process. Figure 11: SAR-based quantizer operation for feedback gains of (**a**) <1 and (**b**) >1. The StrongARM comparator is shown in Figure 12b [34]. When the clock is low, all internal nodes are precharged to VDD through reset transistors, which minimizes memory effects. When the clock transitions to a high state, the evaluation phase begins as the tail current transistor activates and the reset transistors turn off. This allows the differential input pair to create an initial voltage imbalance at the internal nodes. This imbalance is then amplified by cross-coupled PMOS and NMOS pairs through positive feedback, which drives the outputs rapidly to opposite rails based on the input voltage difference. The StrongARM comparator achieves high speed and energy efficiency due to this regenerative positive feedback mechanism. This characteristic makes it particularly suitable for high-speed ADC applications where fast decision-making is crucial. The design of the comparator requires careful consideration of transistor sizing and layout symmetry to minimize offset and ensure reliable operation across variations in process, voltage, and temperature. Figure 13 illustrates the complete operation of the SAR-based quantizer through two interconnected flow charts. The first flow chart (a) demonstrates the high-level quantizer operation with feedback gain control, while the second flow chart (b) details the SAR logic implementation. In flow chart (a), the operation begins by evaluating the feedback gain \(\alpha\). When \(\alpha\) is greater than 1, the system enters a path where CDAC1 + CDAC2 is used during the sampling phase, followed by CDAC1 during the conversion phase. Conversely, when \(\alpha\) is less than or equal to 1, the system takes an alternate path where CDAC1 alone is used for sampling, followed by CDAC1 + CDAC2 for conversion. Both paths ultimately converge to the SAR operation before completion, ensuring proper quantization regardless of the feedback gain configuration. Flow chart (b) details the SAR logic implementation, beginning with an initialization phase where all bits are cleared. The conversion process starts from the Most Significant Bit (MSB) and proceeds through a systematic comparison loop. During each iteration, the input voltage (VIN) is compared with the DAC output voltage (VDAC). If VIN exceeds VDAC, the current bit is set; otherwise, it is cleared. This process continues with each successive bit until the Least Significant Bit (LSB) is reached. After processing the LSB, the conversion is complete, and the system signals the end of operation. Figure 12: **(a)** Layout view of capacitor array of CDAC and (**b**) StrongARM comparator.