# Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World
## 4 Example of a Many-Core Low-Power Processor: PULP  
In this section, a practical ultra-low power many-core architecture is presented as an example of all the topics discussed above. The device under examination is the so-called Parallel-processing Ultra-Low Power Platform (PULP) [128] developed by the Department of Electrical, Electronic and Information Engineering of University of Bologna and the Integrated System Laboratory of ETH Zurich. Figure 11 shows the internal structure of the system, including peripherals, several bus types, memory hierarchy and computational logic. The structure is defined as a System on Chip (SoC) composed by clusters of cores featuring a lot of different functionalities. Each core represents a single Processing Element (PE) of the cluster.  
In order to avoid cache coherency problems, no local data storage is included in the single PE, instead, a tightly coupled data memory (TCDM) is included in the cluster and connected to all cores by means of multiple parallel ports. The TDCM is split in banks, providing concurrent access through as many ports as the number of banks. A DMA allows to move data from L2 memory to TDCM with minimal energy cost and in the meantime, it is on charge of bridging with other clusters or peripherals.  
Outside of cluster domains, an L2 memory provides processing data to clusters and peripherals allowing the SoC to interface with the rest of the world. As exposed by [PERSON] et al. in [128], PULP can operate in two different modes: stand-alone or slave. In the former mode, a flash memory can be connected on the SPI interface allowing the SoC to draw data from it, or from the L2 storage otherwise. In the second mode, instead, PULP is seen as an accelerator that must be coupled with an external processor that is on charge of loading data in the L2 by means of the SPI and synchronize the elaboration by means of dedicated signals directly mapped in the memory. As highlighted in Figure 11, in order to improve the power management, SoC domain and cluster domain are exposed to different clock and voltage signals. Each cluster and the SoC itself are equipped with clock dividers, so it is possible to fine-tune the frequency of each different part. Moreover, each core can be clock-gated to further reduce the power consumption. This allows to better allocate hardware resources to different workloads.  
Since different workloads can require different computational power, a multiplexer denominated BBMUX allows for choosing the back bias for each cluster, thus implementing a dynamic body bias. Transitioning from a back bias value to another is possible to pass from a normal mode to a boost one, improving the speed elaboration capability. In order to manage those transitions and make them transparent to the final user, a Power Management Unit (PMU) is introduced. This is in charge of producing all the control signals needed to control the clock gating and the BBMUX selection.  
Figure 11: PULP SoC architecture.  
PULP is composed of cores based on OpenRISC and RISC-V ISA with a parallelism that can vary from 32 to 64 bits. Being synthesized exploiting a 28 nm UTBB FD-SOI technology provided by STMicroelectronics, PULP can reach 211 GOPS/W that makes him one of the most interesting open source ultra-low power core suitable for several tasks, included convolutional networks and image processing.