# Low Power FPGA Implementation of a Smart Building Free Space Optical Communication System
## 3 Implementation
When considering power amplification abilities and the fact that the optical signal required a highly powered-up gain to traverse the requisite distance between the transmitter and the receiver, there was a significant performance enhancement. A mirror reflects the laser beam at half the distance (D/2) back to the photo-detector to achieve a distance D of 12 m between the transmitter and the receiver. The existence of the mirror was used to verify the system's compatibility in outdoor settings between adherent buildings or in the design of multipath signals employing smart building mirror glazed architecture. Double the setup distance is achieved by practically inducing the mirror to reflect the signal at half the distance D/2. Figure 6 shows the practical system setup for complete hardware testing. The use of building walls as transmission points between one another with the concept of numerous signal reflections is emphasized by the fact that smart buildings present the idea of glazed exterior layers. Hence, adapting multi-node FSO networks can be installed. Figure 7 shows the schematic and amplification of a 100 mV input signal via a common emitter amplifier circuit using TIP31C. The output voltage has shown an increase to around 270 mV amplitude with the use of the TIP31C transistor, as shown in Figure 8. Figure 9 also shows the o/p collector current against time for the given sample circuit. This has demonstrated the dependability of using the TIP31C transistor as the driver and photo-detection circuit's building block. It was also demonstrated in the hardware deployment that the increase in gain allowed the optical signal to be more illuminated and travel the required distance. Figure 6: Proposed System Setup. Figure 7: Initial testing driver circuit for TIP31C. The power levels were properly adjusted to meet the targeted four laser intensities in the VHDL part, as shown in Table 3, using a trial testing of the amplitude of the voltage for optimum detection of the received bits. The levels are initialized in a hexadecimal form. Figure 10 shows the simulation results on ModelSim. The pulse width of the waveform represents the percentage of power for each illumination level. Figure 8: Output Voltage Signal for TIP31C Transistor. Figure 10: ModelSim Simulation Waveform. \begin{table}
\begin{tabular}{c c} \hline \hline
**Amplitude Level in Hexadecimal** & **Power Percentage** \\ \hline
00 & 0\% \\
65 & 33\% \\
72 & 66\% \\ FF & 100\% \\ \hline \hline \end{tabular}
\end{table} 
Table 3: PWM Levels. Figure 9: Output Current Signal for TIP31C Transistor. The laser light intensity varies along with the distinction of the data being transmitted, and the beam is carried in free space from the transmitting to the receiving point. At the receiver terminal, the BPW34 Photodetector catches the optical signal where it is reverted to an electrical one. BPW34 is a silicon-based high sensitivity photodiode packaged in a plastic capsule with a water-clear epoxy surface texture. It can detect visible and infrared radiations. Its detecting area is considered relatively high (A = 7.5 mm\({}^{2}\)) with a wide varying viewing angle (\(\varphi_{\mathrm{s}}=\pm 65^{\circ}\)). The reverted electrical signal is then passed to a comparative Analog to Digital Conversion (ADC) demodulating circuit, as shown in Figure 11, to interpret the four voltage levels into logical ones to be read by the receiver USB port from the FPGA into the computer via the GPIO input pin. The circuit is constructed using the concept of the differential pairing of TIP31C BJT. Here, a combination of four comparative differential pairs is used to measure the difference between the reference voltage and input laser voltage for a maximum value of 3.7 V. If the input voltage is greater than the reference voltage, the output voltage will be 3.7 V (Logic \"1\"), as shown in Figure 12. There are four reference voltages for each comparator so the output will be divided into four logical levels according to the input analog voltage.