## 3 Algorithms for Microcontroller
These timers are normally used as carrier signals to implement pulse-width modulation (PWM) when controlling a power electronic converter. In this case, the timers are synchronized with the falling and rising edges of the input optical control  
Figure 2: Timing diagrams of the optical communication signals (blue—input; red—feedback): (**a**) input signal; (**b**) normal operation feedback; (**c**) no gate current or gate voltage exceeding fault feedback; (**d**) short-circuit or overload current protection feedback; and (**e**) power supply failure feedback. signal. The operation of the substate functions can be interrupted by corresponding events. When the microcontroller detects the falling or rising edge of the input control signal, an interrupt function (XINT) is triggered. The XINT interrupt function determines the program's \"on\" or \"off\" state in the finite-state machine and forces the finite-state machine into the initial condition substate because the switching of the transistor occurs (substate #1 in Figure 3). To monitor the collector voltage, as mentioned above, two analog circuits are provided (circuit #2 and circuit #3 in Figure 1). The purpose of circuit #2 is to measure the collector voltage over the entire range. It is used to detect the appearance of a short circuit if the transistor is not turned on completely. To detect a short circuit, one of the spare microcontroller hardware timers is assigned for short-circuit detection. The short-circuit timer is triggered by the rising edge of the control signal and counts the duration of the collector voltage transient process, as shown in Figure 4. The moment at which the end of this period is detected by the timer corresponds to the expected end of the transient process in the collector voltage, which is equal to 4 us. At this point, the digitation of the analog signal is triggered, and the ADC converts the collector voltage four times in a row. After the conversion is completed, an ADC interrupt occurs once. The result is averaged and compared with the referenced level, which is equal to 51 V.  
If the acceptable value is exceeded, the control signal is blocked, and a feedback pulse with a duration of 9 us is generated, as shown in Figure 2d. If the voltage value is within acceptable limits, then initial substate #1 of the finite-state machine is changed into substate #2 of the \"on\" state, as shown in Figures 3 and 4. The purpose of substate #2 is to verify the collector voltage measured by analog circuit #3 (see Figure 1) with a reduced range of 0 V  
Figure 3: States and substates of the finite-state machine (green—turned on state; red—turned off state; blue—occurs in both states). to +15 V. This analog circuit is used when the transient process of the collector voltage is finished and the IGBT is switched on completely. Circuit #3 is used to monitor the overload current in the collector-emitter circuit. According to the I-V characteristic of the IGBT, if the collector current increases, the collector voltage increases as well. Using this circuit, the collector voltage value is converted by the ADC and validated by the algorithm of the finite-state machine approximately every 3 us in the infinite loop of the finite-state machine. If the result of the conversion exceeds the reference level of 4 V, the IGBT control signal is blocked, and a pulse with a duration of 9 us is generated (see Figure 2d). The driver's algorithm implements the monitoring of the gate voltage by analog circuit #4 (see Figure 1) after the transistor is turned on completely. The gate voltage analysis time is determined by the period measured by the spare hardware timer assigned for gate monitoring. This timer counts the end of the gate voltage transient process and is triggered by the rising edge of the control signal. The gate monitoring timer counter is shown in blue in Figure 4. The timer period corresponds to the maximum possible duration of the transient process in the gate voltage of the IGBT.