## 3 Analysis of Program and Erase Window  
### Program Window Effect  
Figure 2a shows the value of the programmed Vth read after applying the same program voltage to each structure. Additionally, the initial Vth value, measured by a simple read operation without additional program or erase operations, is simultaneously represented. Even though the overall ON pitch length is the same, the reduction rate of Vth varies significantly in each structure of Lg scaling, Ls scaling, and both Lg/Ls scaling. To separate the Vth reduction effect caused by the short channel effect (SCE) due to a reduction in the device size and the Vth variability effect caused by the distribution of trapped electrons in the charge trap layer (CTL) after the program operation, two Vth values were compared simultaneously. As shown in Figure 2a, the Vth reduction effect after programming was more noticeable in all three scaling cases compared to the Vth reduction effect due to the initial read operation. This is because the conduction change in the poly-Si channel that occurs as electrons are trapped within the CTL is added along with the Vth reduction phenomenon due to the SCE that occurs as the devices become smaller. The results indicate that the programmed Vth decrease is the largest during Lg scaling in both the initial read operation and the Vth change amount after the program operation. Therefore, to compare only the amount of change in Vth caused by the charge stored in the cell after programming, a graph of the initial Vth subtracted from the programmed Vth is shown in Figure 2b. This clearly confirms that the Vth reduction due to program operation deteriorates by more than four times during Lg scaling compared to Ls scaling. \begin{table}
\begin{tabular}{c c c c} \hline \hline  & **Program** & **Erase** & **Read** \\ \hline Selected cell & 17–18 V & 0 V & \(-\)5 V–5 V \\ Unselected cell & 5.5 V & 0 V & 5.5 V \\ BL & 0 V & 20 V & 0.5 V \\ DSL & 3.3 V & Floating & 3.3 V \\ SSL & 0 V & Floating & 3.3 V \\ SL & 2 V & 20 V & 0 V \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Simulated voltage condition. Figure 2: (**a**) Initial Vth and programmed Vth of selected WL under various Lg and Ls scaling conditions. (**b**) Difference between programmed Vth and initial Vth under various Lg and Ls scaling conditions. To analyze the cause of Vth reduction after programming, Figure 3a-d show the e-trapped charge distribution within the CTL when the selected WL of the proposed 3D NAND device was programmed to 17 V. As the dimensions of each device change, the electric field applied to the gate dielectric and poly-Si channel is formed differently, resulting in varying amounts of charge being trapped in each structure. Obviously, the amount of charge trapped in the entire CTL tends to increase as the gate area increases. Therefore, to check in more detail the concentration of electrons trapped in the CTL compared to the gate area, the e-trapped charge of the reference and Lg scaling structures of the CTL are shown in Figure 3e. A quantitative comparison was made by cutting the a-a' area. The results indicate that the length of the selected WL decreased by 40% from 25 nm to 15 nm during Lg scaling compared to the reference, while the length of the region where the e-trapped charge in the CTL was more than 5 \(\times\) 10\({}^{19}\) C/cm\({}^{-3}\) decreased by 54%. This suggests that the decrease in the concentration of e-trapped charges in the gate edge area during Lg scaling is the main cause of the decrease in the programmed Vth. The effect of reducing the electron concentration in the gate edge area when Lg is reduced is explained by the reduction in capacitive coupling on the WL to the poly-Si channel substrate [12]. When a program voltage is applied to the selected WL, there is no metal electrode in the space area, so a direct voltage is applied to the lower area of the gate. Still, other voltages due to the fringing field are distributed and applied to the space area.