## 3 Hybrid Computing Architecture of MSD Algorithm
### The Symbol Decision Pipeline Design  
For the process of symbol decision, this study adopts a binary computing scheme. In the correlation calculation stage, the SC is utilized to reduce the resource consumption of hardware circuits, primarily due to the consideration that binary computing requires extensive hardware resources for complex multiplication. Nonetheless, a notable concern regarding SC is that the results of SC exhibit certain statistical errors. If the entire MSD algorithm relies solely on SC, the calculation errors will accumulate at each stage of computational unit, thereby necessitating a longer computation time to ensure the convergence of results. Furthermore, a significant reason for employing binary computing in the symbol decision process lies in the fact that the first step involves computing the modulus of a complex signal. In binary computing, this solely necessitates the complex number itself. Conversely, the multiplier in the SC demands two uncorrelated random sequences. In the correlation calculation based on SC in the previous stage, only one random sequence can be generated. To sustain the use of SC for computing the modulus, an additional random sequence with the same probability value is necessary. When regenerating a new sequence based on an existing sequence, this may result in a certain correlation between the two sequences, thereby diminishing the computational accuracy. Figure 7: Correlation circuit based on SC. Considering the challenges associated with symbol decision based on SC, reconsidering the adoption of binary computing is advisable. In comparison to SC, binary computing exhibits distinctive advantages. The errors in binary computing mainly arise from data truncation during bit quantization, and its computational accuracy is significantly higher than that of SC. Moreover, when calculating the magnitude of a signal, binary data only require self-multiplication, thereby avoiding the sequence regeneration issues encountered in SC. Although the resource overhead of binary computing is higher than that of SC, some strategies can be employed to reduce its hardware resource utilization. It should be noted that the hardware resources in binary computing are intrinsically related to the real-time requirements of data processing. When the demand for the data processing rate is relatively low, binary computing approaches can be designed using a serial pipeline architecture, which does not incur high resource consumption. Recalling the characteristics of SC, it exhibits low hardware overhead but requires a long computation time, resulting in a relatively low update rate for correlation results. When binary computing is employed for symbol decision, its hardware resource consumption can be significantly reduced through reasonable pipeline design. Figure 8 illustrates the pipeline architecture for symbol decision based on binary computing. The entire pipeline comprises a multiplier, an adder, a comparator, a register, and a subtractor. The multiplier is utilized to compute the moduli of complex numbers. Given the relatively low update rate of the correlation results, this study employs a single multiplier to sequentially calculate the squares of the real and imaginary parts of the complex numbers. These values are then summed using an adder to yield the squared modulus of the complex number. Subsequently, a comparator is used to serially compare each output of the adder. Upon identifying a larger result, it is stored in the register. Once the maximum value among all correlation results corresponding to symbol 0 has been recorded, the register is reset and reused to record the maximum value among all correlation results corresponding to symbol 1. Finally, a subtractor is employed to compute the difference between these two maximum values, thereby producing the definitive symbol decision outcome.