## 2 Related Work  
### ICN Hierarchical Caching Architecture  
The feasibility of ICN in-network caching systems largely depends on whether routers can be equipped with large caches that have sufficient storage capacity and support line-speed operations. However, existing storage technologies struggle to simultaneously meet the demands of storage capacity and high I/O throughput [8]. To address this technical bottleneck, researchers have begun exploring hierarchical cache architectures that integrate multiple types of storage media to leverage the advantages of heterogeneous storage systems, enabling more efficient cache management. Ref. [9] proposed a multi-level caching system that predicts subsequent requests based on the temporal correlation between requests and proactively prefetches data blocks from SSDs to DRAM. This approach decouples the low-speed I/O operations of SSDs from the high-speed data forwarding of network components in terms of time scale. The scheme expands the capacity of ICN caches to the multi-terabyte level while maintaining line-speed data processing performance at a multi-Gbps rate. Further, ref. [11] implemented a prototype system based on a DPDK (Data Plane Development Kit) on off-the-shelf hardware, which separates high-latency SSD access operations from the forwarding process using multi-core processing technology. With a configuration of tens of gigabytes of DRAM and hundreds of gigabytes of SSD, the system achieved a throughput of over 10 Gbps. Ref. [13] proposed using block storage devices to extend the cache capacity of network elements to the terabyte level. The authors introduced an innovative split architecture, dividing network devices into a \"forwarding end\" and a \"storage end\", each handling data packet forwarding and caching operations, respectively, thereby addressing the speed mismatch between high-speed data packet forwarding and low-speed block I/O operations on switches. HCaching [17] uses DRAM as the primary cache and SRAM (Static Random-Access Memory) as a cache for DRAM, forming a high-speed, large-capacity hierarchical scheme, and optimizes DRAM cache throughput through a bulk data block prefetching mechanism. The commonality among these works lies in decoupling the high-latency access operations of lower-level large-capacity caches from the high-speed data forwarding operations in terms of time, and using small, high-speed caches to hide the latency of the lower-level caches. While these works address the integration of persistent storage into cache systems, they do not provide effective support for multi-level cache management strategies. Some studies explored the design issues of cache systems from the perspective of performance analysis. For example, ref. [18] identified bottlenecks in NDN (Named Data Networking) software routers based on COTS (Commercial Off-The-Shelf) computers and suggested that storage design schemes should be adjusted according to computational resources to ensure efficient caching and name-based forwarding. Refs. [19; 12] analyzed the CPU instruction pipeline and identified DRAM access latency as the bottleneck in NDN software switches, proposing a prefetching algorithm for NDN data structures to hide this latency. In contrast to the aforementioned works, NB-Cache [20] identified the Content Store (CS) as the main bottleneck in content routers and effectively mitigated local CS congestion through a global load balancing strategy. When a packet arrived at a router with a full CS, NB-Cache forwarded it directly to the next-hop router, avoiding local queuing delays. This method optimized resource allocation from a global perspective, decoupled fast data packet forwarding from slower content retrieval, and significantly reduced the reliance of the CS on expensive memory. In addition, some studies have explored the replica management problem in the context of distributed multi-layer cache/storage systems. For example, ref.