# K/Ka-Band Very High Data-Rate Receivers: A Viable Solution for Future Moon Exploration Missions
## 5 Results  
In order to verify the proposed concept, a receiver breadboard was realized exploiting COTS and evaluation boards (EVBs) as illustrated in Figure 6. The receiver prototype is based on two subsystems: i) the Ka-band front-end assembly, ii) the SDR and FPGA-based modem assembly. The Silicon Infusion Zaltys DVB-S2 modulator and demodulator IP cores realize the digital baseband section of the high performance DVB-S2 compliant modem. The cores are implemented directly in hardware and require minimal software interaction. The modem receive engine delivers excellent demodulation performance and includes LDPC, Bose-Chaudhuri-Hocquenghem (BHC) codes for soft decision and forward error correction (FEC) decoding to fully recover the transmitted Baseband Frames (BBFRAMES). Futhermore, the DVB-S2 standard includes a frame header that can be used to estimate carrier offset due to a Doppler shift. The Zaltys DVB-S2 Demodulator supports automatic handling of carrier offsets during acquisition of up to \(\pm 10\%\) of the symbol rate. Two frequency bands are considered in the present study, namely the K-band from 22.55 to 23.15 GHz and the Ka-band from 27.5 to 30 GHz. The front-end breadboard operates in the Ka-band with the purpose to determine the system performance in the most critical case, i.e., at high frequencies. The first IF signal (3.7 GHz) is obtained by means of a sub-harmonically pumped mixer, although fundamental mixers could, in principle, be used [27]. Indeed a sub-harmonically (\(\times 2\)) mixer requires an half-frequency LO in the range between 11.90 to 13.15 GHz and, such a signal, is easily generated by a PLL synthesizer. The front-end prototype uses a commercial image reject filter implemented in rectangular waveguide, featuring a 28.65 GHz center frequency with a 300 MHz bandwidth. Such an approach, however, cannot be adopted neither in the engineering model, nor in the flight model since it is too bulky and expensive. The technology selected for the final application is based on SIW approach. With this method, a waveguide-like filter can be realized in the very same receiver PCB; the cavities being defined by the top and bottom metal layers and, laterally, by a series of carefully designed via-holes. With respect to microstrip or coplanar-waveguide (CPW) filters, the SIW technology allows for high Q-factor cavities and do not require any additional shielding, i.e., it leads to self shielding circuits. An image reject SIW filter is implemented in a low cost RO4350 material (thickness \(h=0.25\) mm, relative permittivity \(e_{R}=3.48\), loss factor \(\tan\delta=0.004\)) as a proof-of-concept. The filter is designed according to the methodology proposed in [28] and is centered at 29.1 GHz. Figure 7a shows the fabricated circuit prototype: it uses four iris-coupled cavities and it is fed by two 50 \(\Omega\) grounded CPW transmission lines. The PCB is 28 mm long and two coaxial-to-CPW launchers are used for measurement purposes. The measured frequency response of the filter is illustrated in Figure 7b: The filter insertion loss is of about 3.6 dB, including the feeding lines and the two launchers, whereas the return loss is around \(-20\) dB at center frequency. The half-power bandwidth is equal to 2.5 GHz. In order to verify the repeatability of the fabrication process, three different circuits from the same lot have been tested: The frequency responses are very close (i.e., \(|S(2,1)|\) within \(\pm 0.2\) dB in the pass band), as testified by Figure 7b. It is worth to note here that, in order to speed-up the SIW filter design, an automatic layout generation similar to that reported in [29] could be adopted, along with full-wave electromagnetixc solvers [30; 31]. The measurement of the receiver front-end noise floor is reported in Figure 8a. In this case the RF input is terminated on a matched load at ambient temperature. The spectral noise density at the 3.7 GHz  
Figure 6: Prototypes.