# An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA
## 1 Introduction
The research outlined in reference [12] strives to improve the MS algorithm for decoding fixed-point 5G-LDPC codes. While the \"improved adapted MS (IAMS)\" algorithm showcased promising results in the study, the conducted decoding simulation (utilizing BG1 with R = 2/3 and Z = 104) suffered from alarming latency issues, requiring an excessive number of 15 iterations to achieve satisfactory decoding. In their research paper [14], the authors introduced a sequential check node design to estimate the second smallest value in the MS algorithm by incorporating a variable weight parameter to the first minimum value. This design approach reduces hardware complexity by eliminating the need to calculate the second minimum value. However, the decoding process using this check node structure still poses challenges in terms of flexibility and latency, requiring up to 20 iterations. Furthermore, attaining the ideal level of parallelism becomes challenging due to the partially parallel architecture implemented in both the [12; 14] designs. To the best of our knowledge, despite extensive research on LDPC decoding, no prior investigations have succeeded in developing a single module for 5G-LDPC decoding that seamlessly combine reduced complexity, decreased latency, and superior performance, thus highlighting the novelty and significance of our study. This article aims to revolutionize 5G  
Figure 1: 5G-NR data transmission blocks. LDPC decoding by introducing a ground-breaking decoder tailored explicitly for extended codeword lengths, emphasizing flexibility and reduced latency as its core objectives. Due to the 5G base graphs' smaller number of rows compared to the columns, the read and write networks are built using Mp:1 and 1:Mp multiplexers (based on rows) to alleviate the interconnection blocks. The shifting amounts specified as base graph entries can be utilized as inputs of the decoder thanks to the flexible shifting block design proposed in our architecture. Moreover, our architecture empowers the model to seamlessly adapt to diverse structures of the first base graph (BG1), liberating the decoder from the confines of a singular application and rendering it invaluable across a multitude of assorted applications. An optimal low-latency method [15] is included in the control node processing block with very satisfactory results in terms of decoder latency. We have modified this approach and applied it to our 5G-NR decoder for the first time. Following the simulation of this architecture, our decoder achieves a remarkable feat by accomplishing the error correction process in a remarkably low number of iterations--a mere six. The discussed performance is substantiated through extensive simulations conducted across a range of iterations and code rates, affirming the exceptional efficiency and effectiveness of our design. The rest of the article is structured as follows. Preliminaries for LDPC codes in the 5G-NR standards are presented in Section 3. Next, a digital representation of the internal blocks of the proposed architecture is given in Section 4. We discuss the results and related analyses in Sections 5 and 6. Finally, the article concludes in Section 7.