## 3 Results and Discussion
### Measurements without Sensor  
To verify the analogue shaper together with the ADC and further digital processing, the digital output of all channels was measured as a function of the baseline trim DACs, as shown in Figure 11. To remove noise each point is calculated as an average of several thousand values. It is seen that the trim DACs work correctly in the whole range and their trim range is wide enough to correct the baseline spread. Although the trim DAC signal is static, this plot proves that the whole readout chain, starting from the shaper and ending at  
Figure 10: Block diagram of the DAQ used for SALT validation. the serialiser, works correctly. A deeper look at the Figure 11 reveals small steps in the trim curves. This effect is caused by the higher resolution of the trim DACs over the ADCs. The noise distribution for all channels is shown in the histogram in Figure 12, which was created from the same amount of data, but for a single trim DACs value of 128. For each channel, the ADC output value is nearly constant and the noise Root Mean Square (RMS) is significantly below one Least Significant Bit (LSB). Figure 12 also shows that the baseline spread is purely random. The noise before and after common mode subtraction is presented in Figure 13. The values are calculated from the raw data used to build the histogram described above. Raw noise is calculated from the RMS of the values. To obtain the MCM noise the pedestals and then the MCM are subtracted before RMS computation. Figure 11: Baseline trim Digital-to-Analog Converters (DACs) scan for 128 channels before sensor connection. Figure 12: Baseline noise histogram for all trim DACs set to the default value 128; colour indicates bin height; sensor not connected. From the plot, it is seen that the measured noise RMS varies channel to channel from very low values up to half of LSB. For a uniform multi-channel ASIC one expects almost the same noise for each channel. However, this is not the real analogue noise but the result after digitisation. If the real noise is much smaller than the LSB of the ADC, then the RMS result after digitisation strongly depends on the position of the analogue channel baseline versus the closest ADC levels. If the baseline is exactly in the middle between two ADC levels the RMS should be half of LSB. On the contrary, if the baseline sits on ADC level, then the noise should be close to zero. Such behaviour is actually seen in Figure 13. In the SALT, it is possible to obtain uniform noise distribution from channel to channel by setting the baselines of all channels to the same level, applying the trim DAC correction (and assuming that the trim DAC precision is much better than the ADC one). This was also verified in measurements. To check the whole analogue front-end (including preamplifier) behaviour, measurements with the input pulse, generated internally by the calibration circuitry, were performed. Although in the presented architecture direct observation of the pulse shape is impossible, it may be reconstructed from a series of measurements done with different ADC sampling phases. The result is shown in Figure 14. The internal DLL is used to shift the sampling phase within a clock period (25 ns) in 0.4 ns steps while the digital delay is used to extend the range to several clock cycles. The plot shows responses of all channels to the injected charge equivalent to about 1 Minimum Ionising Particle (MIP) in a 250 \(\upmu\)m thick silicon sensor. With such measurements the ADC sampling phase can be aligned to obtain a maximum pulse amplitude. Good symmetry of the pulse shape with a short tail, fulfilling the specification (about 5% of amplitude after twice the peaking time), may be observed. After alignment of the ADC sampling phase, measurements were performed for the whole range of the internal input charge generator. The circuit was found linear for both input signal polarities between about \(-\)40 ke and 40 ke of input charge.