# A 60 GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers
## 3 Linearity Calibration Feedback Loop  
In this section, we present a calibration loop that is suitable for a PAM-8 receiver. The PAM-8 receiver model used is represented in Figure 5. The transmitter, the channel (IEEE '802.3 ck Ch2M - lim_3 ck_01_0319_c2m_Channels' with 30 dB loss at 30 GHz), and the AFE transfer functions were modeled with the channel symbol. Their combined s parameters matrix (\(s_{ch}\)) filters the transmitted symbols and then feeds them to the two stages TH. In the analytical discussion of the model, the input-output characteristics that reflect the buffers' static distortions were modeled using a Taylor polynomial [8, 11, 12], which depended on \(v_{corr}\) in the second stage. For validation, the actual circuit was used. Before the signal was sampled by the ADC, the thermal noise was inserted. Then, the ISI introduced by the channel was reduced using a Feed-Forward Equalizer (FFE). The slicer converted soft decisions into hard decisions, and by proper digital processing of this information, the optimum value of \(v_{corr}\) was obtained. We used an ideal model to implement the DAC and ADC. The typical analog-to-digital converter can have a spurious free dynamic range (SFDR) of the order of 56 dB [16], which is negligible compared to  
Figure 4: The \(\epsilon_{r}\) with the varying of the large-signal differential input for various bias voltages \(v_{corr}\)[8]. Figure 5: PAM-8 RX using the calibration loop with the transistor level components in blue and the Verilog-A model in green. the THD of the TI-TH circuit. The digital-to-analog converter only requires a monotone input-output characteristic due to the loop's high gain capable of absorbing the small error derived from its nonlinearities. To better explain the mathematical operations, we take for granted that the circuit samples the signal on the optimum phase; hence, we assume the system works in a discrete time domain, and the channel was modeled with its impulsive response. The signal sent by the transmitter \(u(k)\) was convoluted with the channel impulse response obtaining \(x(k)=G_{ch}u(k)\otimes h_{ch}(k)\), where \(h_{ch}\) is the equivalent impulse response of \(s_{ch}\), and \(G_{ch}\) is the equivalent channel gain. After the distortion introduced by the TH circuit, we have:  
\[z(k)=x(k)+a_{3}x^{3}(k)+a_{5}x^{5}(k)+a_{7}x^{7}(k) \tag{2}\]  
with \(a_{i}\) being the Taylor coefficients of the overall analog front end, assuming the nonlinearities can be described with a Taylor expansion of the input-output characteristics. If we assume the FFE is optimal and we neglect the residual ISI, \(d(k)\) can be written as:  
\[d(k)=u(k)+G_{nor}[a_{3}x^{3}(k)+a_{5}x^{5}(k)+a_{7}x^{7}(k)+n(k)]\otimes h_{FFE }(k) \tag{3}\]  
with \(n(k)\) being the equivalent analog circuit noise with zero mean value and with \(G_{nor}=\dfrac{1}{G_{ch}}\) being the digital gain, which normalizes the signal. The error at the slicer input \(d(k)-q(k)\) can be multiplied by the hard decision \(q(k)\), and assuming the slicer takes the correct decision \(q(k)=u(k)\), (with the MATLAB model of the system in [8], it was verified this can be considered true for SER lower than around \(15\times 10^{-3}\)) we can write:  
\[w(k)=u(k)[d(k)-u(k)]=u(k)G_{nor}\{a_{3}x^{3}(k)+a_{5}x^{5}(k)+a_{7}x^{7}(k)+n( k)\}\otimes h_{FFE}(k). \tag{4}\]  
\(w(k)\) then multiplies the loop gain \(G\), which is of the order of \(10^{6}\), and the result is filtered by a digital low-pass filter (it could also be implemented with an RC filter) and sent to a DAC with seven bits generating \(v_{corr}(k)=E\{Gw(k)\}\).