# Efficient Layered Parallel Architecture and Application for Large Matrix LDPC Decoder
## 1 Introduction  
Low-density parity-check (LDPC) code was first proposed by [PERSON] in his PhD thesis in 1962 [1]. Since [PERSON] discovered the decoding performance of LDPC code close to [PERSON]'s limit in 1997 [2], various papers and research on LDPC codes have come out one after another, and they have also been applied commercially according to various standards. Currently, LDPC code has been used as a channel error correction code in communication standards such as WiMax, 10 CBASE-T and 5G. Since the decoder module in a channel codec is the key module that affects the data transmission rate, it is generally inclined to adopt the design method of improving performance, which needs to use a large number of logic computing devices and memory devices, and its hardware resource consumption is often large. Obviously, the channel codec module occupies a large part of the power consumption and area in the whole communication baseband processing chip, so the area power consumption performance of the designed channel codec module will directly affect the baseband chip area power consumption. Naturally, it is very important to study the technical means and design methods of high-performance decoders to improve area efficiency and power efficiency. In 1999, [PERSON] et al. proposed a sum-product algorithm that can handle Gallager codes and MN (Mackay-Neal) codes. The sum-product algorithm (SPA) [3], also known as the two-phase message passing (TPMP) algorithm, is actually a probabilistic domain belief-propagation (BP) algorithm. In order to reduce the amount of operations when decoding, the SPA algorithm in the logarithmic domain [4] emerged, which enables the replacement of multiplication with addition. Subsequently, the min-sum algorithm (MSA) [5; 6] wasproposed by further approximating the check notes (CN) computation with the minimum of the set of input nodes. Further, the offset min-sum algorithm (OMS) [7] and the normalized min-sum algorithm (NMS) [8] were introduced to compensate for the loss of decoding performance of MSA. In terms of decoder hardware design, the turbo-like decoding message passing (TDMP) algorithm proposed by [PERSON] in 2003 significantly increased the iterative decoding speed of the decoder, allowing the corresponding hardware implementation to increase the throughput without sacrificing the decoding performance [9]. TDMP is actually a typical horizontal layered algorithm [10; 11], which divides the check nodes into several layers, and the update results of the last layer can be utilized in the subsequent layers, thus speeding up the update process. In contrast, [PERSON] published a paper on the vertical-layered algorithm [12], where the checksum matrix is divided vertically. Moreover, it has been shown that both horizontal- and vertical-layered updates can theoretically achieve twice the decoding convergence speed of TPMP [13]. In addition, the residue-based layered algorithm proposed by researchers can further improve decoding convergence speed [14]. For long codes, the traditional LDPC decoder generally adopts the hierarchical update method, which divides the update of all nodes into multiple layers. However, the throughput of the hierarchical decoder is smaller than that of full parallel decoding because of fewer processing units. However, the fully parallel decoder hardware scale will increase with the increase in code length, and it is not suitable for long codes. In order to improve the throughput and area efficiency of the decoder at the same time, this paper considers updating the two kinds of nodes at the same time and, at the same time, increasing the parallelism of node processing and selecting a partial block parallel scheme. In the partial block parallel decoder, the computation and memory/write need to be increased several times. Too many partition times of the basis matrix will introduce a large number of bubbles, which will cause a great negative impact on the throughput of the decoder.