# Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor
## 4 Decimal Multiplier
### Partial Product Generator--Method 1  
Considering a multiplicand, A, and a multiplier B, one partial product is the result of the multiplication of a multiplier digit, \(b_{i}\), by the multiplicand. Since a digit varies between 0 and 9, the partial product corresponds to a multiple of \(A\) in the set {0, 1A, 2A,..., 8A, 9A}. To obtain these multiples, two subsets of multiples are considered: \(S_{1}\) = {0, 5A, 10A} and \(S_{2}\) = {0, A, 2A}. The advantage of these subsets of multiples is that they can be easily generated without carry propagation, as will be shown later. From these, any multiple of the set {0, A, 2A,..., 8A, 9A} can be obtained from the addition or subtraction between multiples of each set as shown in Table 3.  
The hardware design of the partial product generator includes one multiplexer to select the multiple from the subset \(S_{1}\), another multiplexer to select the second multiple from \(S_{2}\) and one decimal adder/subtractor (see Figure 1). Selectors \(S_{a}\) and \(S_{b}\) of the multiplexers, and operand selector \(op\) are functions of the 4-bit multiplier digit, \(b_{i}=b_{i}[3]b_{i}[2]b_{i}[1]b_{i}[0]\), as described in Table 4.  
Figure 1: Partial product generator for a single multiplier digit using subsets \(S_{1}\) = {0, 5A, 10A} and \(S_{2}\) = {0, A, 2A}. The decimal adder/subtractor of the partial product generator is implemented as explained in Section 3.3 with multiples represented in excess-3. Therefore, propagate signals of the adder/subtractor are functions of three variables. Considering that the circuit is to be implemented in FPGAs with 6-input LUTs, there are three unused inputs in each LUT implementation of a propagate signal. So, the implementation of the partial product generator can be further optimized by merging the multiplexer of the subset {0, A, 2A} with the adder/subtractor (see Figure 2). Block \(Sel-Add/Sub\) sums (\(op=0\)) or subtracts (\(op=1\)) the output of the multiplexer with one multiple in the set {0, A, 2A}, determined by selector {\(S_{b}\)}. Considering the propagate and generate expressions of the BCD/excess-6 adder/subtractor with operands represented in excess-3, the expressions of the propagate and generate signals for a single digit of block \(Sel-Add/Sub\) are as follows:  
\[p[3] =op\oplus m_{a}[3]\oplus(S_{b}[0]\ \overline{S_{b}[1]}\ ae3[3]+ \overline{S_{b}[0]}\ S_{b}[1]\ 2 ae3[3]) \tag{15}\] \[p[2] =op\oplus m_{a}[2]\oplus(S_{b}[0]\ \overline{S_{b}[1]}\ ae3[2]+ \overline{S_{b}[0]}\ S_{b}[1]\ 2 ae3[2])\] \[p[1] =op\oplus m_{a}[1]\oplus(S_{b}[0]\ \overline{S_{b}[1]}\ ae3[1]+ \overline{S_{b}[0]}\ S_{b}[1]\ 2 ae3[1])\] \[p[0] =op\oplus m_{a}[0]\oplus(S_{b}[0]\ \overline{S_{b}[1]}\ ae3[0]+ \overline{S_{b}[0]}\ S_{b}[1]\ 2 ae3[0])\] \[g[3] =m_{a}[3]\] \[g[2] =m_{a}[2]\] \[g[1] =m_{a}[1]\] Table 4.0  
where \(m_{a}\) is a digit from the output of the multiplexer, \(M_{a}\). \(ae3\) and \(2 ae3\) are digits from multiples Ae3 and 2 Ae3, respectively. \begin{table}
\begin{tabular}{l l l l l l} \hline \hline \(b_{i}[3]b_{i}[2]b_{i}[1]b_{i}[0]\) & **Multiple** & **Operation** & \(S_{a}\) & \(S_{b}\) & **op** \\ \hline “0000” & 0 & 0 + 0 & “00” & “00” & 0 \\ “0001” & A & 0 + A & “00” & “01” & 0 \\ “0010” & 2A & 0 + 2A & “00” & “10” & 0 \\ “0011” & 3A & 5A – 2A & “01” & “10” & 1 \\ “0100” & 4A & 5A – A & “01” & “01” & 1 \\ “0101” & 5A & 5A + 0 & “01” & “00” & 0 \\ “0110” & 6A & 5A + A & “01” & “01” & 0 \\ “0111” & 7A & 5A + 2A & “01” & “10” & 0 \\ “1000” & 8A & 10A – 2A & “10” & “10” & 1 \\ “1001” & 9A & 10A – A & “10” & “01” & 1 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Generation of selectors in method 1. Figure 2: Partial product generator for a single multiplier digit. Connecting these propagate and generate signals with a carry chain provides the circuit for a single digit of block \(Sel-Add/Sub\) with a carry-in and a carry-out (see the implementation of a single digit in Figure 3). The complete partial product is obtained with a chain of these single-digit blocks. The generated partial products are in BCD/excess-6 format.