# A Crypto Accelerator of Binary Edward Curves for Securing Low-Resource Embedded Devices
## 5 Results and Comparison
### Performance Metrics and Evaluation  
To design more efficient systems, it is crucial to consider various performance metrics. These metrics include throughput/area, slices, LUTs, and time, which provide valuable insights into the efficiency and effectiveness of a design in terms of hardware resources and computation speed. Throughput/area is a particularly useful metric that quantifies the number of computations performed per slice. It is calculated using Equation (7) and provides a measure of how efficiently a design utilizes hardware resources. By minimizing the number of slices used, we can increase the number of computations that can be performed per unit of hardware, improving the overall efficiency. Slices and LUTs are essential metrics that indicate the number of hardware resources utilized by a design. Reducing the number of slices and LUTs employed can result in a more cost-effective system, optimizing resource utilization and improving efficiency. Time is a critical metric for measuring the speed of computation, typically measured in microseconds. By optimizing the time required for a single point multiplication (PM) operation, we can enhance the overall efficiency of the system and reduce the time needed to complete the complex computations. Considering these performance metrics allows for the evaluation and optimization of designs, enabling the development of more efficient systems in terms of hardware utilization and computation speed:  
\[\frac{throughput}{area}=\frac{throughput\left(Q\,=\,k.p\,in\,\mu s\right)}{ slices} \tag{7}\]  
Equation (7) is expressed in a simplified form as shown in Equation (8). \[\frac{throughput}{area}=\frac{\frac{10^{6}}{\widetilde{time\left(or\right)latency \left(Q\,=\,k.p\,in\,s\right)}}}{ slices} \tag{8}\]  
Equation (8) provides a definition of throughput as the reciprocal of the time required to compute one point multiplication (PM), denoted as \(Q=k.p\) in seconds. The term \"slices\" refers to the area utilized on the chosen FPGA device. The binary elliptic curve (BEC) is represented by two points, \(P\) and \(Q\), which correspond to its initial and final points, respectively. The scalar multiplier is denoted as \(k\). In Equation (8), the factor \(10^{6}\) is used to convert the time from microseconds to seconds, simplifying the calculation of throughput as given in Equation (7). To compute the latency or time required for one point multiplication (PM) operation, Equation (9) is used. The resulting latency values are listed in column 6 of Table 6. Optimizing these values helps improve the system efficiency and reduce the computation time. By considering these equations and optimizing the corresponding values, we can improve the overall efficiency of the system, reducing the time required for computations and maximizing the throughput:  
\[time\left(or\right)latency=\frac{required\ \left(CCs\right)}{operational\ clock\ frequency} \tag{9}\]  
Equation (9) specifies the computation of the necessary clock cycles (CCs) for a single point multiplication (PM) operation. The corresponding CC values are displayed in Table 4, while the operational clock frequency, measured in MHz, can be found in column 3 of Table 6. Taking into account metrics such as throughput, slices, latency, clock cycles, and operational clock frequency allows for the design of more efficient and effective systems. This optimization enables the optimal utilization of hardware resources and facilitates faster computations. The resulting improvements in performance and efficiency make our designs more competitive and impactful in their respective domains.