# HAIPO: Hybrid AI Algorithm-Based Post-Fabrication Optimization for Modern 3D NAND Flash Memory
## 2 Background
### Overview of NAND Flash Memory
Please note that if we can prevent the page buffer from reading the data in a flash cell or inhibit the data in the page buffer from transferring out of the flash chip via a data-out path, its effect will be equivalent to destroying the stored page in the selected WL. **Multi-level Cell Technology. ** Since the mid-2000s, multi-level cell techniques have been widely used to continuously increase the capacity of NAND flash memory. Multi-level cell technology aims to store multi-bit information in a single flash cell. Figure 2 illustrates \(V_{th}\) distributions for \(2^{m}\)-state NAND flash memory, which stores \(m\) bits within a single flash cell using \(2^{m}\) distinct \(V_{th}\) states. For example, \(m\) is 2 for MLC (i.e., storing 2 bits per cell), \(m\) is 3 for TLC, and \(m\) is 4 for QLC NAND flash memory, respectively [8; 9; 10; 11]. Figure 2: \(V_{th}\)distributions of \(2^{m}\)-state NAND flash memory. As \(m\) increases to store more bits within a flash cell, more \(V_{th}\) states should be put into the limited \(V_{th}\) window, which makes a \(V_{th}\) margin (i.e., a gap between two neighboring \(V_{th}\) states calculated as \(W_{\text{Total}}-\sum_{i=0}^{k}W_{\text{Pr}}\)) inevitably narrower. Since narrow \(V_{th}\) margin makes NAND flash memory more vulnerable to various noise effects, in turn, significantly degrades the flash reliability, more careful management is required for multi-level cell NAND flash memory to form finer \(V_{th}\) states, as \(m\) increases [12; 13]. Shaping a narrow \(V_{th}\) state can be achieved by reducing ISPP step voltage, but it directly degrades the flash performance (e.g., program latency) [14; 15] (More details are in Section 3). In higher \(m\)-bit multi-level cell NAND flash memory, such a trade-off between performance and reliability of NAND flash memory makes flash optimization more complex and difficult. Therefore, to meet various requirements of a storage system (e.g., performance, requirement, and yield), it is essential to efficiently optimize NAND flash memory by precisely tuning internal NAND operating parameters. **3D Cell Stacking Technology. ** Figure 3 illustrates an organizational difference in a NAND block between 2D NAND flash and 3D NAND flash memory. Although the architecture of 3D NAND flash memory is conceptually described as if multiple 2D NAND flash layers are stacked in a vertical direction [16], the inner organization of 3D NAND flash memory is quite different from this logical explanation. In the example shown in Figure 3, the 2D NAND flash memory has a 2\(D\)_matrix_ structure in which four WLs and three bitlines (BLs) intersect at 90 degrees. On the contrary, the 3D NAND flash memory has a _cube-like_ structure. The 3D NAND flash block consists of four vertical layers (v-layers) on the y-axis, where each v-layer has four vertically stacked WLs separated by select-line (SSL) transistors. As shown in Figure 3, when the 2D NAND flash block is rotated by 90 \({}^{\circ}\) in counterclockwise direction using the x-axis as an axis of rotation (i.e., if the WLs are set vertically), it corresponds to a single v-layer. Similarly, the 3D NAND flash block can be described as having four horizontal layers (h-layers) stacked along the z-axis, and each horizontal layer consists of four WLs. To increase the capacity of a 3D flash chip, the most effective approach is to increase the number of h-layers in 3D NAND flash memory (i.e., stacking more h-layers along the z-axis). As the number of h-layers increases, the block size increases as well. For example, the advanced 3D NAND flash memory has more than 200 layers, and the capacity of one flash chip reaches 1 Tb [17]. The stacked flash cells are vertically connected through _cylindrical_ channel holes. The channel holes are formed at the early stage of 3D NAND flash manufacturing by an etching process [18].