# Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation
## The Implementation of Chip Results and Measurement  
### Data Comparison with FPGA Approach  
FPGA is used as a circuit function verification before tape-out. This design was implemented in the function in FPGA Cyclone IV. In addition, comparing FPGA of Xilinx  
Figure 8: VLSI architecture of the predicted state module. Figure 9: VLSI architecture of the input table module. and Altera in different literature respectively. Table 3 expresses the comparison results with register, LUT (Look-Up Table), and IOB (Input/Output Block) resources. Between the two previous approaches and the proposed approach, Table 3 presented the comparison results on the hardware resource utilization of the FPGA resources applied. According to the results in Table 3, compared with [20], the proposed approach has significantly decreased in register utilization. Compared with [37], though the proposed approach is little more in register utilization, the timing of hardware still has a huge advantage. Tables 3 and 4 present the logic element using by number of LUT inputs, total registers, total I/O pins, and embedded multiplier 9-bit elements, as compared with [18; 19], not only has lower resource usage, but also has a huge advantage in processing time. Furthermore. Compared with the processing time in Tables 3 and 5, the results present that the proposed approach gets apparently advantage over the software implementation. In other words, based on obtains explanations, the coefficients were obtained of the \(\alpha\)-\(\beta\) tracker which rely on the state and measurement noise covariance of the KF tracking approach. Namely, for the proposed approach, it is obvious  
hardware platform of Altera DE2-115, the proposed design was verified in Modelsim and implemented on FPGA. The simulation is a critical step for designing FPGAs, and it allows us to stimulate the proposed approach. Therefore, Modelsim is a program applied to simulate VHDL and Verilog designs. The simulation in Modelsim illustrates that the filter satisfies real-time of the system. In addition, Figure 10 shows the simulation path in this article. The path is performed for 15 turns, 120 points per turn, and a total of 1800 points are simulated. In addition, random noise adds to the true trajectory, which is the observed trajectory, and then restored through the proposed approach. The results show that the proposed filtering approach can track the trajectory and speed of MD effectively, and there are different coefficient parameters for \(\alpha\) and \(\beta\) to make CDF (cumulative distribution function) plots for the comparison. Furthermore, Figure 11 reveals the comparison of the proposed approaches between the KF and the proposed tracking algorithms. Table 7 illustrates the results of the proposed localization approaches. The location accuracy corresponds to the different fixed values of \(\alpha\) and \(\beta\) coefficients, where the different fixed coefficients of \(\alpha\) and \(\beta\) are tuning constants between number 0 and number 1. On the basis of the results, the location accuracy of the proposed \(\alpha\)-\(\beta\) training-tracking method based on the coefficients of the KG is almost the same as the location accuracy of the KF tracking approach. Therefore, to use the coefficients of the KG obtained from the proposed approaches has a considered effect on the performance of the \(\alpha\)-\(\beta\) training-tracking algorithm. Namely, in terms of the results, the location accuracy of the proposed tracking approach is nearly the same as the KF tracking approach. Figure 12 shows the simulation of the nonlinear path with software, implemented on the FPGA, and then the restored position is a substitute to the software for verification. Therefore, using the coefficients of the KG from training mode done in FPGA implementation has a considered effect on the performance of the proposed approach. Furthermore, for the proposed approach, the fewer resources in terms of parallelism are used to improve the execution time.