# Scalable Photonic Digital-to-Analog Converters
## 4 Experimental Setup  
For the PDAC conversion rate evaluation, an RF experimental testbed was prepared for a 2-bit PDAC instance (DUT), as demonstrated in Figure 5. A C-band tunable laser provides a CW optical signal passing through a polarization controller and a fiber array coupling the signal to the on-chip vertical grating couplers. The insertion loss (IL) of the light coupling to the chip is approximately 5 dB. The CW laser optical power output is set to 4.6 mW, which is the maximum output power of the laser in use. The DUT receives approximately 1.5 mW optical power at the input to the first 3 dB MMI splitter. While the relative intensity noise (RIN) of the laser can contribute to the bit error rate by lowering the allocated optical power to the least significant bit below the system noise level [16], higher input power would certainly improve SNR, enabling a higher conversion rate. The DC biases to the ring heaters are provided using a multi-contact wedge (MCW) probe, which serves for the thermal tuning of the ring modulators, ensuring the alignment of the resonance dips. The MCW is also used to tune the phase shifters responsible for the coherent coupling of the modulated signals from different branches. A GSGSG RF probe is landed on the contact pads of the ring modulators, corresponding to the MSB and the LSB of the 2-bit PDAC DUT. The DC bias voltages and the RF digital signals are combined using the bias tees and sent through the RF probes. From the pseudorandom pattern generator (PPG), two independent but coherent pseudorandom bit sequences (PRBS)-15 NRZ 4 Gbps data from data channels are used as the electrical data signals for the analog conversion. The MRMs are biased at 3.5 V reverse bias. As the maximum peak-to-peak voltage (Vpp) of the PPG data channels is 1.8 V, two RF amplifiers are used to amplify the digital electrical signals to achieve 6 V peak-to-peak OOK signals. With small dynamic range and low input optical power, the data rate is limited to 4 Gbps for one channel. For a 2-bit PDAC, the data rate sums up to 8 Gbps (4 GBaud), enabling a sampling (conversion) rate of 4 Gsample/s. The amplitude-modulated optical signals are combined coherently using an MMI to obtain the optical analog signal, which is equivalent to a four-level pulse amplitude modulation (PAM-4) signal. In addition to this RF measurement, a straightforward continuous wave (CW) measurement testbed is deployed for the experimental validation of the 4-bit PDAC operation while the four MRMs are switched in a stationary manner.  
Figure 5: The schematic diagram of the RF experimental setup (**a**). PC: polarization controller, PPG: pseudorandom pattern generator, DUT: device under test, EDFA: Erbium-doped fiber amplifier, OF: optical filter, PD: photodiode, DCA: digital communication analyzer. On the right-hand side, (**b**) a photograph of the experimental setup showing the chip mount stage with a multi-contact wedge DC probe, RF probe (GSGSG), and fiber array unit (FAU), along with a micrograph from the top view of the chip surface area (**c**) containing the 2-bit PDAC, the tip of the RF probe hovering over the contact pads, while the tip of the FAU is positioned on the DUT’s grating couplers, are presented.