# A 13.44-Bit Low-Power SAR ADC for Brain-Computer Interface Applications
## 3 Layout Implementation and Post-Layout Simulation Results  
The proposed SAR ADC was designed using 180 nm CMOS technology, achieving a compact core area of 0.2475 mm\({}^{2}\) through meticulous layout optimization. Figure 16 illustrates the symmetrical floorplan with capacitor arrays distributed across the left-right repireries, while the central placement of critical analog modules--including bootstrapped  
Figure 14: Circuit of proposed dynamic logic unit. Figure 15: SAR dynamic logic unit timing operation. switches, dynamic comparators, and unity-gain buffers--minimizes interconnected parasities. The SAR logic block is strategically positioned adjacent to the capacitive DAC array to reduce switching noise coupling. Analog signal routing employs current-density optimized traces (4 mA/\(\upmu\)m width) with differential symmetric paths, maintaining a!5% length mismatch through careful metal layer planning. Proximity grouping of the comparator, sampling switches, and CDAC array achieves effective mitigation of RC delay variations. As illustrated in Table 3, the SAR ADC developed in this study exhibits remarkable performance metrics tailored for BCI applications, demonstrating superior precision and energy efficiency, as well as dynamic characteristics essential for high-fidelity acquisition of weak biological signals. The design achieves an ENOB of 13.44 bits, surpassing traditional SAR ADCs (e.g., 11.12 bits in [18]) and CT-DSM architectures (9.62 bits), thereby minimizing quantization-induced distortion. Under coherent sampling conditions (Fin = 9.6875 kHz, Fs = 320 kS/s), the ADC demonstrates a SINAD of 82.67 dB and an SFDR of 89.62 dB, as illustrated in Figure 17. The performance sweep results of ENOB and SNR as they vary with input frequency are shown in Figure 18, and the results of SNR and SINAD as they vary with input amplitude are shown in Figure 19, further validating SAR ADC's capability to maintain high signal integrity and suppress harmonic distortion in real-world operating scenarios. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & [18] & [19] & [20] & [21] & **This Work** \\ \hline Topology & IADC2-1 & SAR & SAR & SAR & SAR \\ Process (nm) & 180 & 90 & 180 & 180 & 180 \\ Sampling frequency (Hz) & 768 k & 20 M & 1 k & 1 M & 320 k \\ Supply (V) & 5 & 1.8 & 0.5/1 & 1.8 & 1.8 \\ Power (W) & 2.95 m & 31.6 \(\upmu\) & 35.9 \(\upmu\) & 40.5 \(\upmu\) & 27.9 \(\upmu\) \\ Peak input (V) & - & 500 m & 1 & - & 1 \\ Bandwidth (Hz) & 0.5 k & 1.25 M & 5 k & 50 k & 10 k \\ Resolution (bits) & 32 & 5 & 12 & 8 & 14 \\ ENOB (bits) & 18.16 & 4.53 & 11.12 & _7.7_ & 13.44 \\ SINAD (dB) & 111.1 & 29 & 68.7 & 48.15 & 82.67 \\ SFDR (dBc) & - & - & 83 & 55.52 & 89.62 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Simulation performance summary and comparison with state-of-the-art systems. Figure 16: Layout of designed circuit. From a power efficiency perspective, the proposed SAR ADC consumes only 27.9 uW, significantly less than comparable designs (e.g., 40.5 uW in [19]), and is substantially more efficient than IADC2-1 (2.95 mW) [20]. Detailed power analysis reveals that the  
Figure 19: SNR vs. input amplitude and SINAD vs. input amplitude. Figure 17: FFT analysis results of post-layout circuit simulation. Figure 18: ENOB vs. frequency. comparator dominates power consumption at 8.982 uW (32.1% of the total), followed by CDAC switching at 8.946 uW (32.0%), clock distribution at 9.0936 uW (32.5%), and SAR logic at 0.936 uW (3.3%). This optimized power distribution ensures efficient energy utilization, which is critical for extending the operational lifetime of implantable devices and meeting the stringent energy constraints of long-term BCI monitoring. Additionally, the ADC's bandwidth of 10 kHz accommodates the full spectrum of neural signals (0.5-5 kHz) while supporting higher-frequency signal acquisition, such as electromyographic data or motion artifact monitoring, thereby enhancing system versatility.