## 5 Experimental Verification  
The simulated dc microgrid and proposed fault detection algorithm were implemented and tested in an experimental prototype in order to validate the feasibility of the proposed protection approach. A laboratory-scale experimental setup in 20:1 scale from the simulation circuit was built to verify the conceivability of the proposed SDRE observer method using actual hardware. Due to overwhelming and consecutive disturbances, as well as practical limitations, implementation of the SDRE controller in this section has been neglected and the performance of SDRE observer scheme is analyzed. In the simulations, four disturbances, including severe variations in the output voltages of the PV system, BESS, and the capacitor bank, as well as load variations are considered as disturbances. In the lab test setup, the PV system, the BESS, and the capacitor bank are modeled and implemented by means of the power supply system as _MASTECH HY3005-2_ two-channel, 30-V 3-A power supply and _MASTECH HY3005-1_ one-channel, 30-V 3-A power supply. Inside these sources, there is a protective element that causes the power supply to be tripped if there are overwhelming and consecutive variations in the power supply currents. As a result, it is not possible to produce large disturbances in the power supply outputs. Further, a 10 \(\Omega\)-30 W wire-wound resistor has been used to implement the dc load. In order to apply load variations, it is necessary to use variable wire-wound resistance, which was not accessible for us. The prototype test-bed including a dc source, dc load, and insulated-gate bipolar transistor (IGBT) solid-state circuit breaker, but only with a positive line to simulate a line-to-ground (LG) fault. The employed equipment, the characteristics and their corresponding descriptions are given in Table 2. It should be noted that, apart from the implementation of the fault detection based on the SDRE observer method, the differential fault detection method proposed in [15] is also implemented to provide a comparison of the fault detection times between the two schemes. In addition, in the implementation, dc-dc converters modeling is ignored and the BESS and bank capacitor are modeled as a simple ideal source. Figure 17: Non-zero residual current of the \(C_{1}\) for disturbance and fault occurrence. The amount of threshold for the differential fault detection was assumed as 20% of the quantity of the simulation in [15]. In this test, the measured current analog-digital (A/D) transformation is fulfilled in a 50-\(\upmu\)s interval. The use of a microcontroller, IGBTs gate drivers and a schematic diagram of the prototype experimental test bed implementation are shown in Figures 18 and 19. The red light of light emitting diodes (LEDs) of current measurement modules indicate the link between the current sensor and the microcontroller. An LG fault was practically examined and applied at 1s. The power supply feeds 20W (20 V, 1 A) to the load in the steady-state utilization. It is remarkable that the power supply could supply a near 20 A-peak transient fault current for 100 ms until every channel attains a 3 A rated current amount. Figure 20 shows the residual current comparison of \(C_{1}\) capacitors during the fault occurrence without protection, with differential protection, and with SDRE observer protection. It is apparent, the transient three A fault current passes through the circuit without protection. While, by investigation of the SDRE-observer and the differential method figures, it can be deduced that the proposed SDRE observer protection detects the fault incidence more quickly. Obviously, the current value attains zero after the trip of IGBTs. Figure 21 shows the voltage of dc demand and the freewheeling current without protection, with differential, and SDRE observer protection modes.