# Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications
## 1 Introduction  
The complexity of multi-processor systems-on-chip (MPSoC) computing systems is continuously increasing [1; 2; 3]. Implementing multiple on-chip processing cores, and relevant memories, the bottleneck of the computing system becomes the inter-processor communication. To solve the inter-tile communication issue, the state-of-the-art has been characterized by the evolution from standard circuit-switched bus communications, e.g., SoC based on AMBA (Advanced Microcontroller Bus Architecture) bus as in [4], to packet-switched Network-on-Chip (NoC). This is the case of both homogeneous and heterogeneous MPSoCs [5; 6]. In Homogeneous MPSoCs [7; 8; 9; 10], all the interconnected tiles are of the same type; for example, eight MagicDSP tiles, each integrating an ARM(tm) core plus a VIW (Very Long Instruction Word) processor, are interconnected through a NoC in [8]. Instead, multiple ARM Cortex cores are integrated on-chip in [10] to implement cloud sever-on-chip solutions. Other examples of homogeneous NoCs are in Ref. [7; 9]. In heterogeneous MPSoCs, the tiles are different, see examples in [11; 12; 13; 14; 15; 16]. Particularly in multimedia applications, programmable general-purpose cores can be integrated with memories and with co-processors for computing intensive applications. The co-processors are usually integrated as synthetizable IP (Intellectual Property) macrocells for computing intensive tasks such as video coding, motion estimation/compensation, noise removal or image enhancement, and multi-dimensional transforms [17; 18; 19; 20; 21; 22]. The NoC is organized as a conventional ISO/OSI (International Standard Organization/Open Systems Interconnection) stack of layers. Indeed, a NoC aims at bringing on-chip the technologies already developed for computer and telecommunication networks [2; 23; 24; 25; 26; 27; 28; 29; 30; 31; 32; 33; 34; 35; 36]. The key building blocks of a NoC are routers [23; 24; 25; 26; 27], network interfaces (NI) [28], and links [29; 30; 31; 32; 33]. This paper will focus on links. Particularly, at the bottom of the stack, in the physical layer, conventional metal-wired links are characterized by the following limits:poor scalability;
* increased delay when transferring high data rates--at several Gb/s--among cores and/or memories placed at distances greater than 1 cm;
* increased power consumption to switch--at continuously increasing frequencies--the large capacitance offered by long metal wires. In the recent literature, optical [31; 34; 35] or wireless [25; 27; 31; 37; 38; 39; 40; 41; 42; 43; 44] links are investigated as an alternative solution to classic metal wires to reduce latency and power consumption issues. Wireless NoC (WiNoC) links are easier to integrate on-chip with respect to silicon photonic solutions that, instead, are not yet mature enough to represent a reliable on-chip networking technology. One of the main technology bottlenecks for WiNoC is printing the antenna on-chip, e.g., using top metal layers. As a matter of fact, using scaled CMOS (Complementary Metal Oxide Semiconductor) technologies, there are several works published in literature, operating from a few GHz to mm-waves, which already integrate on-chip the transmitter and the receiver, see Ref. [45; 46; 47; 48; 49; 50; 51; 52; 53; 54; 55]. Also, for the Analog-Digital converter [45; 55] and for the building blocks of a NoC (e.g., NI, Router, Link in [23; 24; 25; 26; 27; 28; 29; 30; 31; 32; 33]) there are many works proposing on-chip integrated solutions. Instead, for the antenna, there are still open issues on optimizing the trade-off between area, gain and bandwidth. For example, the survey work [56] also declares that the on-chip antenna is still one of the most difficult components to integrate on-chip.