## 6 Conclusions  
This study proposed a novel hardware framework for the MSD algorithm based on a hybrid SC approach. For the correlation calculation in the MSD algorithm, the SC scheme is employed to reduce the hardware resource overhead. In the SC-based correlation calculation, a flexible and scalable stochastic adder was developed and integrated to achieve summation operations using different scaling factors. For the binary computing-based symbol decision, a pipeline structure was proposed to execute the entire process serially, thus reducing the resource overhead by leveraging the low update rate of the SC-based correlation results. The hardware architecture based on hybrid SC for three-, five-, and seven-symbol MSD algorithm variants was successfully constructed on an FPGA platform. Experimental evaluations revealed that the BER performance of the hybrid SC is comparable to that when using traditional binary computing methods, while simultaneously achieving a substantial reduction in hardware resource utilization. However, the hardware architecture based on hybrid SC also has some drawbacks. Its energy cost increases slightly, and computational latency is relatively high. Despite the drawbacks, the introduction of SC still has significant advantages in reducing resource overhead. In future work, it is advisable to consider applying it to other algorithms with high computational complexity. \begin{table}
\begin{tabular}{l l l l l} \hline \hline \multirow{2}{*}{**MSD**} & \multirow{2}{*}{**Computing Scheme**} & \multirow{2}{*}{\
\begin{tabular}{c} **Power** \\ **Consumption** \\ \end{tabular} } & \multirow{2}{*}{
\begin{tabular}{c} **Computational** \\ **Latency** \\ \end{tabular} } \\ \cline{4-5}  & & & length = 500 & 0.76 W (76\%) & 2.08 \(\upmu\)s (2600\%) \\ \cline{3-5}  & & length = 1000 & 1.41 W (141\%) & 4.08 \(\upmu\)s (5100\%) \\ \cline{2-5}  & & length = 1500 & 1.99 W (199\%) & 6.08 \(\upmu\)s (7600\%) \\ \cline{2-5}
3-symbol & & 8-bit & 0.99 W (100\%) & 0.08 \(\upmu\)s (100\%) \\ \cline{2-5}  & & 9-bit & 1.30 W (131\%) & 0.08 \(\upmu\)s (100\%) \\ \hline \multirow{5}{*}{5-symbol} & \multirow{2}{*}{\
\begin{tabular}{c} **hybrid SC** \\ \end{tabular} } & length = 500 & 3.98 W (72\%) & 2.27 \(\upmu\)s (2838\%) \\ \cline{2-5}  & & length = 1000 & 7.73 W (139\%) & 4.27 \(\upmu\)s (5388\%) \\ \cline{2-5}  & & length = 1500 & 11.90 W (215\%) & 6.27 \(\upmu\)s (7388\%) \\ \cline{2-5}  & & 8-bit & 5.55 W (100\%) & 0.08 \(\upmu\)s (100\%) \\ \cline{2-5}  & & 9-bit & 7.12 W (128\%) & 0.09 \(\upmu\)s (113\%) \\ \hline \multirow{5}{*}{7-symbol} & \multirow{2}{*}{
\begin{tabular}{c} **hybrid SC** \\ \end{tabular} } & length = 500 & 20.85 W (69\%) & 3.04 \(\upmu\)s (3378\%) \\ \cline{2-5}  & & length = 1000 & 32.23 W (107\%) & 5.04 \(\upmu\)s (5600\%) \\ \cline{2-5}  & & length = 1500 & 51.83 W (172\%) & 7.04 \(\upmu\)s (7822\%) \\ \cline{2-5}  & & 8-bit & 30.11 W (100\%) & 0.09 \(\upmu\)s (100\%) \\ \cline{2-5}  & & 9-bit & 38.61 W (128\%) & 0.10 \(\upmu\)s (111\%) \\ \hline \hline \end{tabular}
\end{table} 
Table 9: Power consumption and computational latency of different computing paradigms. **Author Contributions:** Conceptualization, Y.L., R.L., and L.Z. ; methodology, Y.L. ; software, Y.L. ; validation, Y.L. ; formal analysis, Y.L., K.T., and Z.L. ; investigation, Y.L., K.T., and Z.L. ; resources, Y.L. ; data curation, Y.L. ; writing--original draft preparation, Y.L. ; writing--review and editing, R.L., K.T., Z.L., and L.Z. ; visualization, Y.L. ; supervision, R.L. ; project administration, R.L. and L.Z. ; funding acquisition, R.L. All authors have read and agreed to the published version of the manuscript. **Funding:** This work was supported in part by Shenzhen Fundamental Research Project under Grant JCYJ20220818103413029, in part by Guangdong Basic and Applied Basic Research Foundation 2023B1515120093, and in part by Shenzhen Science and Technology R&D Funds under Grant JSGC20220831100602005. **Data Availability Statement:** The original contributions presented in this study are included in the article.