## 6 Results and Discussion
### Experimental Results  
For our design, we used Xilinx Virtex UltraScale+ FPGA VCU118 Evaluation Board (XCVU 9P) as the implementation platform. The throughput of a decoder is often a crucial performance metric, and it can be calculated using the following formula:  
\[T_{\text{max}}=\frac{r\times l\times f}{n\times c}, \tag{10}\]  
where \(r\) is the code's rate, \(l\) is the code's length, \(f\) is the frequency of the decoder, \(n\) is the number of iterations, and \(c\) is the number of clocks per iteration [40]. For our optimized decoder designed for overlap, we can finish a single iteration in 18 clocks. Suppose we use a clock frequency of 156.25 MHz and perform eight iterations, which is a common choice for high-performance LDPC decoders. The code we use has a rate of 0.875, a length of 8176 and, thus, the throughput of the decoder can be calculated as follows:  
\[T_{\text{max}}=\frac{0.875\times 8176\times 156.25\text{ MHz}}{8\times 18}=7.76\text{ Gbps}. \tag{11}\]  
Therefore, our optimized decoder can achieve a throughput of 7.76 Gbps, which is quite high and suitable for high-speed systems. If overlap control is not used under the same decoder, one iteration takes 114 clocks, resulting in a throughput of 4.08 Gbps. In other words, overlap decoding scheme doubles throughput while maintaining unchanged resources and performance. The utilization of the FPGA is presented in Table 1. From the table, we can find that we only need 31 LUTs per CNU and consume only 20 LUTs per VNU, which is minimal for accomplishing the comparison of 32 elements as well as the transformation and summation processing of five elements. The key to this is that we implement functions such as comparison, addition, and mapping of data through combinatorial logic, and simplify the logical relationships as much as possible. It is important to note that RAMs are not considered in this calculation, as they are not used in the shift-register-based memory scheme employed in our implementation. The permutation net, including storage, requires a total of 73,718 LUTs and 142,504 registers. Overall, our decoder utilizes only 10% of the total resources on our board. This low resource usage is a testament to the efficiency of our implementation, and demonstrates its practical feasibility for real-world applications. Furthermore, a comparison of the implementation and performance of the proposed low-complexity high-throughput decoder with various other LDPC decoders with high HUE or similar PCM is presented in Table 2.  
The findings detailed in Table 2 underscore the commendable performance of the proposed decoder in comparison to other reported decoding techniques. This achievement is particularly notable in terms of achieving a high throughput while operating at a lower working frequency. Noteworthy metrics such as Mbps/kLUT, Mbps/kFF, and Mbps/36 kb BRAM are employed for comprehensive comparison, highlighting the different HUE aspects. Our Mbps/kLUT ratio emerges as highly competitive, showcasing the efficiency of our design. However, the Mbps/kFF ratio does not distinctly favor our approach, mainly due to our utilization of shift-register-based memory as opposed to BRAMs. The \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Computation Unit** & **LUT** & **Register** & **RAM** & **DSP** \\ \hline CNU & \(31\times 2\times 57=3534\) & \(26\times 2\times 57=2964\) & 0 & 0 \\ VNU & \(20\times 16\times 57=18,240\) & \(28\times 16\times 57=25,536\) & 0 & 0 \\ Permutation Net & 51,944 & 114,004 & 0 & 0 \\ Total & 73,718 & 142,504 & 0 & 0 \\ Available & 1,182,240 & 236,4480 & 2160 & 6840 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Hardware utilization. high throughput is mainly achieved by relying on deep overlap with the proposed LDPC. Simultaneously, the achievement of high HUE is supported by the adoption of the 2-bit MSA and the utilization of combinational logic-based CNUs and VNUs. Evidently, the implementation results elucidate the efficacy of the design methodology proposed in this study.