# CUDA-Optimized GPU Acceleration of 3 GPP 3D Channel Model Simulations for 5G Network Planning
## 5 Channel Emulator Acceleration on GPU
It can be inferred from Figure 7 that the GPU implementation greatly reduces the simulation time and enables the network planners to simulation more complex propagation scenarios with higher Doppler shift and even more antenna elements. To analyze the effect of both transferring larger amounts of data (64 bits vs. 32 bits per value) and performing computations with greater precision, the accelerators were designed for both double-precision (DP) and SP on both acceleration platforms. Figure 6: MIMO antenna configuration in CDL-D profile for LOS clusters. Table 4 reports the achieved performance and energy consumption for FPGA and GPU acceleration platforms for CDL-B delay profile. Overall, the optimizations result in a large speedup of **240x** in comparison to the baseline CPU implementation. The achievable performance is memory bound due to the limited on-chip shared memory of the GPU, hence the need to repeatedly read large amounts of data from the DRAM rather than storing it on-chip as was performed on the FPGA. For power analysis, CPU results are calculated based on its thermal design power (TDP) because we have no way to measure its power consumption in real time. Energy consumption is very high due to high execution latency on CPU platform. The energy consumption of the FPGA is lower than that of the GPU because the data are copied only \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Platform** & \begin{tabular}{c} **Latency** \\ **(s)** \\ \end{tabular} & \begin{tabular}{c} **Speedup** \\ **(Times)** \\ \end{tabular} & \
\begin{tabular}{c} **Power** \\ **(W)** \\ \end{tabular} &
\begin{tabular}{c} **Energy** \\ **(Q)** \\ \end{tabular} \\ \hline CPU & 5.01 & N/A & 105 & 526.0 \\ \hline FPGA (DP) & 0.03 & 172 & 31.1 & 0.96 \\ FPGA (SP) & 0.03 & 172 & 29.3 & 0.79 \\ \hline GPU (DP) & 0.08 & 60 & 52.0 & 4.37 \\ GPU (SP) & 0.02 & _240_ & 40.5 & 0.85 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Accelerated kernel latency and energy consumption. \begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline \multirow{2}{*}{
\begin{tabular}{c} **Link** \\ **Type** \\ \end{tabular} } & \multirow{2}{*}{**Kernel**} & \multicolumn{8}{c}{**Execution Latency**} \\  & & \multicolumn{8}{c}{**Downlink (\(\mathbf{R_{x}}\times\mathbf{T_{x}}\))**} & \multicolumn{8}{c}{**Uplink (\(\mathbf{T_{x}}\times\mathbf{R_{x}}\))**} \\ \cline{3-10}  & & \(\mathbf{2\times 2}\) & \(\mathbf{4\times 4}\) & \(\mathbf{4\times 8}\) & \(\mathbf{8\times 8}\) & \(\mathbf{8\times 16}\) & \(\mathbf{16\times 16}\) & \(\mathbf{2\times 32}\) & \(\mathbf{4\times 32}\) \\ \hline \multirow{2}{*}{**Downlink**} & calcCIR (\(\mathrm{\SIUnitSymbolMicro}\)) & 5.43 & 8.22 & 8.29 & 10.94 & 12.93 & 20.16 & 9.25 & 12.67 \\  & applyFIR (\(\mathrm{\SIUnitSymbolMicro}\)) & 1.72 & 5.95 & 11.23 & 22.04 & 43.12 & 85.42 & 22.12 & 43.06 \\ \hline \multirow{2}{*}{**Uplink**} & calcCIR (\(\mathrm{\SIUnitSymbolMicro}\)) & 5.43 & 8.00 & 8.35 & 11.10 & 12.58 & 19.46 & 8.86 & 11.23 \\  & applyFIR (\(\mathrm{\SIUnitSymbolMicro}\)) & 1.72 & 5.93 & 11.78 & 22.13 & 43.88 & 85.32 & 24.93 & 45.50 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Kernel latency for a combination of MIMO elements in CDL-B NLOS.