# A Software-Defined Radio for Future Wireless Communication Systems at 60 GHz
## 2 5G Testbed Overview
### ADC/DAC Integration with FPGA  
The integration of ADC/DAC with VC707 board required hardware fine tuning to achieve the desirable data rates. Thus, this section addresses thoroughly the steps taken to achieve such integration. It is important to mention that 4 DSP already offers a VC707 reference design to serve as basis, but multiple iterations were necessary to achieve the proposed mmWave SDR testbed. Firstly, the reference design FMC slots were changed to have both boards working simultaneously using the same FPGA. Secondly, since both boards use FPGA Ethernet as an initialization and data interface, a physical connection had to be considered onto the proposed SDR testbed. Thirdly, sampling rate adjustments were performed, because both ADC/DAC had different default values which, in the end, would lead to loss of samples. Lastly, both DAC and ADC data path were changed to be transmitted in real-time rather than using the default memory architecture, which temporarily allocates data in memories before transmission. As mentioned above, 4 DSP reference firmwares target Ethernet communication as the protocol to perform the initialization of both devices and to transmit/receive data. Consequently, such architecture demands a host PC to be always connected to the FPGA, which is impractical in a wireless communication transceiver. Therefore, Ethernet connection must be replaced by a new VHDL entity capable to play back initialization commands that were previously sent by the MAC engine to the FMC board entities (_stars_). This approach is highlighted in the block diagram illustrated in Figure 4, where all the connections in red are the ones that must be removed from the original FMC230 and FMC126 reference designs. With such changes, the MAC engine _star_ is now just considered to generate clock and reset signals to the others _stars_ and, due to this fact, it has been decided not to be removed. In this work, the aforementioned new entity is a processor engine, which allows the configuration commands of both converters to be sent (in real-time) from the FPGA to either ADC or DAC. Nevertheless, the design and implementation of a processor hardware engine architecture is not a straightforward task. It is usually composed of a _microBlaze_ processor, peripherals, reset, clocking and debugging blocks, which are connected together using an AXI4-Stream protocol [21]. Since the _microBlaze_ is a soft-core processor with 32-bit RISC architecture and AXI interfaces, the developed entity had AXI in mind for easy, direct access to fabric and hardware acceleration [22]. It is worth noting that this interface/protocol is not a bus, and thus a custom user block was necessary to convert the AXI data coming from the processor engine to the bus format given in Figure 4.  
The VC707 board has two instances of the FMC HPC VITA 57.1 mentioned in Section 2.1. However, the VC707's HPC2 connector is not fully populated, e.g., it has a reduced pin-out in comparison with the standard HPC connector. Consequently, the FMC230 placed on such connector would only have one out of its two DAC channels available. On the other hand, if FMC126 would be connected to it, only three out of its four ADC channels could be available. Considering that most relevant modern digital modulation techniques employ I/Q modulations to achieve higher spectral efficiency, two channels are required in both DAC/ADC boards. Therefore, FMC230 and FMC126 have been connected to the FMC1 and FMC2 slots of the VC707 board, respectively, as can be seen in Figure 3.  
Figure 5 depicts the final firmware that shows how the configuration commands are exchanged among the top level board entity (_stars_) from both DAC/ADC boards. The FMC126 board includes not only the Quad ADC IC core itself, but also other peripherals, such as a clock tree IC circuit and a I2C communication for ADC control purposes and temperature monitoring [16]. Since the FMC126 reference design foresee  
Figure 4: Block diagram of the adopted modifications common to both FMC126/FMC230.