## 8 Conclusions  
In this paper, the proposed SoC design, based on a 32-bit VexRiscv processor and cryptographic accelerator cores for PRINCE and PRESENT-80, two lightweight block ciphers, ChaCha, a lightweight stream cipher, and SHA3-512, a hash function, was successfully deployed with fewer implementation clock cycles in the Nexys4 DDR FPGA development board. In addition to the lightweight cryptographic accelerator cores, the VexRiscv SoC's functionality was validated and demonstrated to be stable, functional, and to possess high throughput. The number of utilized resources by the system in an FPGA was also relatively low, 11,830 LUTs and 9552 FFs, meaning it is eligible for compact Internet of Things application systems, with the advantage of significantly reducing the execution time resulting in low latency of lightweight cryptographic algorithms. Specifically, the PRINCE core requires 31 cycles, PRESENT-80 requires 97 cycles, Chacha20 needs 58 cycles, and SHA-3 takes 34 cycles to be implemented in the proposed SoC. Low latency enables the system to process with minimal delay and improves system performance.  
In conclusion, this work has introduced a highly customizable platform using an RISC-V processor. The highlighted contribution was the usage of the simple peripheral bus  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline  & **This Work** & [31] & [32] & [26] \\ \hline
**Device** & **Artix-7 XC/A100T** & Artix-7 XC/A100T & FE310-G00 SoC & Spartan-3E \\
**Processor core** & **VexRiscv** & VexRiscv & SiFive E31 & MicroBlaze \\
**Operation frequency** & **75 MHz** & - & - & 50 MHz \\
**Implementation type** & **SoC Accelerator** & HW instructions & SW instructions & SoC accelerator \\ \hline \hline \multicolumn{5}{c}{**Algorithm performance (cycles)**} \\ \hline PRINCE & **31** & 35 \({}^{1}\) & - & - \\
**ChaCha20** & **58** & - & 1787 \({}^{2}\) & - \\
**SHA3-512 (Keccak)** & **34** & - & 13,774 & - \\
**PRESENT-80** & **97** & 160 \({}^{1}\) & - & 514 \({}^{3}\) \\ \hline \hline \end{tabular}  
\({}^{1}\) The work of [31] reported the results as the number of instructions. \({}^{2}\) The estimated result of [32] for processing 64 bytes originally reported processing 4096 bytes. \({}^{3}\) The estimated average result for [26] originally reported 100 processing iterations.  
\end{table}
Table 8: Comparison to other relevant system implementations.  
in LiteX, based on a register-controlled interface, and the Configuration/Status Register to connect customized and optimized cores, such as PRINCE, PRESENT-80, ChaCha, and SHA-3, with VexRiscv to construct a high-performance SoC with low-implementation clock cycles and low-logic resources. This allows not only cryptographic accelerators but also various hardware cores to be integrated, forming a simple and custom SoC. The proposed SoC can be applied in small and medium systems such as Internet of Things systems, customized security IoTs devices, compact root-of-trust systems, etc. It can also be used to deploy and develop more customized and complicated systems.  
Writing--original draft preparation, methodology, software, K.-M.M.; conceptualization, validation, supervision, research administration, D.-H.L.; review, C.-K.P.; data analysis, review and editing, T.-T.H. All authors have read and agreed to the published version of the manuscript.  
This research was funded by the University of Science, VNU-HCM, under grant number DT-VT 2023-01.  
Not applicable.  
Data availability Statement: Data are contained within the article.  
The authors declare no conflict of interest.