## 3 Optical Buffering and TSI with Integrated Delay Lines
### Experimental Setup and Results for Optical TSI  
The TSI experimental setup is illustrated in Figure 10a. The setup shares the main building blocks used in the variable optical delay line buffering scheme, using, however, a different Delay Stage where two fiber pieces and the longest integrated SOI-spiral waveguide comprise the three delay branches. The two fiber-based arms correspond to delay values of 0 and \(\Delta\tau\) to accommodate non-delayed direct (Direct) transit and single packet-slot delay needs, respectively, while the integrated SOI delay corresponds to a 2\(\Delta\tau\) delay offering dual packet-slot delay. By properly synchronizing the incoming optical envelopes at the WC1 input, the TSI operation was validated for two possible packet re-arrangement scenarios, allowed by a single-stage TSI with three delay lines, as depicted in Figure 10b. Considering an input packet order of (I)-(II)-(III), Scenario 1 refers to the case where a (II)-(I)-(III) packet order is obtained at the output, while Scenario 2 results to a (I)-(III)-(II) packet stream. In order to allow for all possible packet re-arrangement scenarios in a three packet stream, our design should be scaled utilizing either more wavelengths and delay lines or, alternatively, utilizing the same three-delay-line structure in a multi-stage setup, as has been analytically studied in [23] and presented in [49].  
Figure 9: (a) Initial three data packets (b–d) packet (I) after being delayed on the three integrated Si-spiral (e) BER measurements.  
Figure 11 depicts the oscilloscope traces obtained when operating in Scenario 1 configuration, with Figure 11a showing the incoming data packets. Packet I was then converted to \(\lambda_{1}\) at WC1 to get a delay of \(2\Delta\tau\), packet III was converted to \(\lambda_{2}\) and delayed then by \(\Delta\tau\), while packet II was converted to \(\lambda_{3}\) acquiring a zero-time slot delay. The resulting (II)-(I)-(III) ordered packet stream obtained at the Delay Stage output is depicted in Figure 11b, validating correct packet re-arrangement. The output traces of every individual packet at WC2 output are shown in Figure 11c-e, with respective zoomed-in versions shown in Figure 11f-h for each output packet, revealing the regenerative properties of the WC2 stage.  
Figure 12 depicts the oscilloscope traces obtained to validate the TSI operation for Scenario 2, with Figure 12a depicting the incoming packet signal. In this case, packet (II) was converted to \(\lambda_{1}\) to acquire a \(2\Delta\tau\) delay, packet (I) was converted to \(\lambda_{2}\) and delayed then by \(\Delta\tau\), while packet (III) was converted to \(\lambda_{3}\) for direct transit. In this way, the resulting optical stream at the Delay Stage output had a packet order of (I)-(III)-(II) as shown in Figure 12b. The individual packets obtained at WC2 output are presented in Figure 12c-e with their respective zoomed-in versions illustrated in Figure 12f-h.  
Figure 11: (a) TSI Input (b) TSI Output (c,f) Packet II at WC2 Out (d,g) Packet I at WC2 Out (e,h) Packet III at WC2 Out.  
Figure 10: (a) Experimental Setup of the TSI (b) Scenarios of packet re-arrangement for three packet input stream.  
BER measurements were performed for every output packet in both TSI scenarios and are illustrated in Figure 13 along with the corresponding eye diagrams. Error-free operation at \(10^{-9}\) was obtained for all packets with an average power penalty of 3 dB for the packets traversing the fiber-based delay lines and 5 dB for the packets traversing the integrated SOI-spiral waveguide. This higher power penalty is due to the noise that originates from the SOA amplification prior to chip coupling and is subsequently amplified in the EDFA.