## 4 SI/PI Co-Design in the High-Speed Interconnect Using the Proposed Method
When the buffers are coded, cases generating large power/ground noise and crosstalk are eliminated. Compared to Figure 14b, the eye-diagram is further improved in Figure 14c. By adopting the proposed method, impacts of various factors affecting SI/PI on the target high-speed interconnect are clearly visible. It is shown that the hierarchical PDN impedance improvement also ensured SI of the target high-speed interconnect. By adopting the coding, SI is further improved and impacts are clear. Figure 12: (**a**) Conceptual image describing a target high-speed channel to be designed and analyzed considering the parameters affecting the SI/PI of the high-speed channel. (**b**) An equivalent circuit model of target hierarchical PDN and buffers in the HBM interposer. The BER eye-diagram can be obtained by calculating the BER at every receiver sampling time and reference voltage offset as shown in Equation (11), where the \(b_{\text{m}}\) represents the correct digital state, '1' or '0'. \[\text{BER}(V_{\text{ref}})=\frac{1}{2}\text{P}(V_{\text{out}}<V_{\text{ref}}|b_{ \text{m}}=1)+\frac{1}{2}\text{P}(V_{\text{out}}>V_{\text{ref}}|b_{\text{m}}=0) \tag{11}\]  
In Figure 15, derived BER eye-diagrams are compared without and with DBI coding. By applying the DBI coding, the opening of the BER eye-diagram is increased. Note that the BER scale is different in Figure 15a,b. To derive the BER, (11) is calculated at every quantized sample voltage and time. Lastly, the timing and voltage bathtub curves are obtained from the derived BER eye-diagrams. The timing bathtub curves are compared at the threshold voltage (\(V_{\text{th}}\)) in Figure 16a. In Figure 16b, the voltage bathtub curves at the sampling time are plotted and compared. The impacts of the hierarchical PDN impedance and data coding on both the timing and voltage bathtub curves are clearly shown in Figure 16. Proper SI/PI co-design ensures reliable timing and voltage analysis as well. Figure 14: Estimate statistical eye-diagrams of the HBM interposer channel based on the proposed method. (**a**) Case without proper decoupling capacitor scheme in the hierarchical PDN. (**b**) With decoupling capacitor scheme. (**c**) When the DBI coding is adopted. Figure 13: Hierarchical PDN impedances seen from the HBM are plotted without and with decoupling capacitor schemes. In the hierarchical PDN, on-chip, interposer, package and PCB PDNs are considered with decoupling capacitors in each PDN. By applying the proposed method, the target HBM channel affected by various noise factors can be easily and efficiently derived. Simultaneous comparison of the hierarchical PDN impedance and eye-diagram of the target interconnect is possible. From the derived statistical eye-diagram, further indicators such as BER eye-diagrams and timing/voltage bathtub curves can be formulated for an SI/PI co-design and co-analysis. Figure 16: (**a**) Timing bathtub curves are compared at the threshold voltage (\(V_{\text{th}}\)). (**b**) Bathtub curves comparison at the sampling time. Figure 15: (**a**) The BER eye-diagram of the HBM channel is derived from the estimated statistical eye-diagram shown in Figure 14b. (**b**) The BER eye-diagram of the HBM channel is derived from the estimated statistical eye-diagram shown in Figure 14c. Note that scales are different.