## 6 System Verification and Experiment Results
### Experiment Results
The results of (I) and (II) show that DycSe contains 0.421 w, nearly 3.6% less power than [7]. According to the observation, the muxes and demuxes' power consumption is relatively lower than PEs'. From the primitive's point of view, [PERSON] et al. [7] contain more DSP resources, which consume more power. As shown in Table 4, an individual single-direction PE in DycSe and [7] consumes 0.001 w, while a bi-directional PE's power consumption is between 0.001 and 0.002 w. Although DycSe contains bi-directional PEs requiring more power, DycSe's total PE amount is less and balances the PEs and reconfiguration circuits well. Although DycSe has extra reconfigurable circuits, such as muxes, demuxes, and adder modules, the total on-chip power consumption is still less. Furthermore, thanks to the column streaming architecture, fewer PEs do not affect the processing cycles significantly. However, Table 4 also shows DycSe's bottleneck of power consumption, which is at the adder module and should progress in the future. The result of (III) shows each work's convolution engine (PEs and adders) and whole accelerator system power consumption under their package technology. For a fair comparison, (IV) discloses each ASIC works' equivalent system power consumption to 40 nm. Finally, (V) gives out the power consumption of all the ASIC works at 150 GOPs. From the result, we observe that the power consumption of each work is consistent, which is between 100-200 s mW. Hence, cross-reference [7], also utilizing streaming architecture, is convincible and qualified to represent the low-power edge AI accelerators for being compared to DycSe on the FPGA platform. \begin{table}
\begin{tabular}{l l l l l l l l} \hline \multicolumn{1}{c}{**Power Categories**} & \multicolumn{4}{c}{**DyeSe (This Paper)**} & \multicolumn{1}{c}{**[PERSON] et al. [7]**} & \multicolumn{1}{c}{**Sparsity-Aware [11]**} & \multicolumn{1}{c}{**SOFTBRAIN [3]**} & \multicolumn{1}{c}{**CARLA [22]**} & \multicolumn{1}{c}{**ISCA [9]**} \\ \hline Power evaluation technology & FPCA & FPCA & ASIC @ 65 nm & ASIC @ 40 nm & ASIC @ 55 nm & ASIC @ 65 nm & ASIC @ 55 nm \\ \hline \multicolumn{1}{c}{Single direction:} & & & & & & & \\ A PE (W) & 0.001 & & & & & & \\  & 8-direction: & & & & & & \\  & [0.001, 0.002] & & & & & & \\ \hline \multicolumn{1}{c}{Adder module (W)} & 0.008 & \textless{}0.001 & – & – & – & – & – \\ \hline PE amounts & 121 & 144 & 144 & 128 & 160 & 196 & 168 \\ \hline Bus2 (W) & 0.001 & – & & – & – & – & – \\ \hline \multicolumn{1}{c}{Total PE and adder module (W)} & 0.180 & 0.195 & – & – & – & \\ \hline \multicolumn{1}{c}{\multirow{2}{*}{Total on-chip power (W)}} & \multicolumn{1}{c}{} & & & & & \\  & & 0.027 (4.84\%) & 0.011 (2.70\%) & & & & \\ \hline \multicolumn{1}{c}{\multirow{2}{*}{Total on-chip power (W)}} & \multicolumn{1}{c}{} & & & & & \\  & & 0.111 (3.67\%) & 0.138 (31.95\%) & 0.35 @ 65 nm & & & \\ \hline \multicolumn{1}{c}{\multirow{2}{*}{Total on-chip power (W)}} & \multicolumn{1}{c}{} & & & & & \\  & & 0.421 (100\%) & 0.46 (100\%) & & & & \\ \hline \multicolumn{1}{c}{\multirow{2}{*}{Ratio (FPCA)}} & \multicolumn{1}{c}{} & & & & & \\ \hline Power (W) @ 40 nm [8, 26, 27, 28] & – & – & 0.175 & [0.124, 0.154] & 0.553 & 0.124 & 0.067 \\ \hline \multicolumn{1}{c}{\multirow{2}{*}{Power (W) @ 13 COCPs 1}} & \multicolumn{1}{c}{} & & & & & \\ \hline \multicolumn{1}{c}{\multirow{2}{*}{\({}^{*}\) Normalize the technology to 40 nm according to the reference. \({}^{*}\) Each accelerator’s power consumption when normalizing the computation ability to 150 COPs.} & & & & \\ \end{tabular}
\end{table} 
Table 4: Power consumption comparisons.