## 5 Hardware Implementation and Experimental Results  
### FIR1 (CIC Filter)  
Word lengths of the integrator in the CIC filter were implemented as in Figure 20a, which shows the structure of the integrator. The output of the ADC, out_ADC, was set to vary such that \(-2\leq\) out_ADC \(<+2\) since the output may not be expressed with only one  
Figure 19: Mean SNR of the DFE Matlab model and the C++ model for ten frequency modes or cases.  
Figure 18: Conversion from cycle-accurate model to bit-accurate model.  
integer bit for some interference scenarios. After the signal from the ADC passed through the flip-flop (FF), the signal was sign-extended to 14 bits in the integer part (instead of the original 2 bits at out_ADC), since the maximum value of the sum of the impulse responses over all the cases was turned out to be 4096 or 212, as shown in Figure 20b. By means of this internal 12-bit word length increment (rather than using a scaling factor by 1/4096 prior to FIR1), overflow was obviated.  
Footnote 12: [[https://www.cds.org/](https://www.cds.org/)]([https://www.cds.org/](https://www.cds.org/))  
The comb filter was designed and implemented, whose structure and word lengths are displayed in Figure 21a. As with the integrator, it only consists of the addition operations. At the last stage of it, a right-shift-by-x operation was used to return the bitwidth above the decimal point back to 2 as in the input of the CIC filter. The right-shift values \(x\) were 7, 7, 4, 8, 8, 12, 4, 4, 4, and 4 for cases 1, 2, 3, 4, 5, 6, 10, 11, 12, and 13, respectively, according to the sum of the impulse responses. The decimator can be simply implemented by using a counter. The decimation factor of each case is listed in Figure 21b.  
Figure 21: (**a**) Comb filter structure and word lengths and (**b**) decimation factors for 10 cases.  
Figure 20: (**a**) Integrator structure and word lengths and (**b**) scale factors of the integrator.  
The output of FIR1 was set to quantize 16 bits in total, instead of 26 bits, in consideration of the speed of FIR3 (Farrow interpolator). In summary, the CIC filter including scaling dispenses with any internal multiplication operation and the quantization error is output only once at the end. Critical path delays are different for different implementation methods, namely, the ASIC synthesis and the FPGA placement and routing (P&R). The critical path delay for the ASIC synthesis in a 180 nm CMOS technology was 1.72 ns that consisted of the 0.66 ns delay from the (26-bit + 26-bit) adder and the remaining path delay, highlighted in red in Figure 20a, whereas the critical path delay for the FPGA P&R was 2.42 ns that consisted of the 1.674 ns adder delay and the remaining path delay, highlighted in green in Figure 20a. The critical paths seem different with ASIC and FPGA but as the procedure is the same in each stage, they may be regarded as being identical. The reason that the ASIC is faster than the FPGA is attributed to the ASIC synthesis targeting speed at the cost of area while the FPGA P&R could not attain the same goal. The ASIC synthesis results are summarized in Figure 22, where the required delay of 3.205 ns or 1/312 MHz is denoted in red. Area was expressed in 2-input NAND gate equivalent (GE) gate count. The actual delay was placed to the left of the red line and hence the CIC filter operated in compliance with the specification.