## 2 Impact of Process Variations (PV) on Different Operation Modes
### Impact of PV on Physical Unclonable Function (PUF) Quality
#### 2.1.1 Mismatch of INV-1 and INV-2  
The reliability of a PUF is a measure of the reproducibility of its response to the same challenge at different times and conditions [1]. It is the complement of the bit error rate (BER) of its responses, which can be measured by calculating the intra-chip Hamming distance of the responses generated from a single PUF chip with the same challenge. Ideally, BER should be 0% and reliability should be 100%. The reliability of the start-up state of an SRAM cell is highly dependent on the degree of mismatch between INV-1 and INV-2. The mismatch is dominated by the intra-die variation where the variation of \(V_{th}\) is the most prevalent. During power-up process, a small deviation of \(V_{th}\), denoted as \(\Delta V_{th}\), between the transistors of INV-1 and INV-2 may change the drive currents and shift the intersection of their voltage transfer curves (VTC) [9], causing asymmetric output sensitivity to external stress. The magnitude of \(\Delta V_{th}\) is primarily determined by \(\sigma_{V_{th}}\), which has been proven empirically to be related to the transistor geometry as follows [10]:  
\[\sigma_{V_{th}}=\frac{\Lambda\cdot\sigma_{V_{th,\max}}}{\sqrt{(W\cdot L)}}, \tag{1}\]  
where \(\Lambda\) is a technology-dependent parameter and \(\sigma_{V_{th,\max}}\) is the maximum value of \(\sigma_{V_{th}}\).  
Based on Equation (1), \(\sigma_{V_{th}}\) can be reduced by sizing up the transistors in an SRAM cell (see Figure 4a). Depending on the transistor sizes, the mismatch between the inverters of a cell may be reduced to an extent that its output state becomes highly susceptible to variations of external condition or in the worst case, completely determined by the noise present in the SPUF. This can be explained in Figure 5. Based on the propensity of the output to settle at one of the two states upon power-up, SRAM cells can generally be categorized as 1-skewed, 0-skewed or neutral cells [2]. Highly 1-skewed (0-skewed) cells have larger mismatches between its two inverters and have a high tendency to power up to \"1\" (\"0\"). Neutral cells have equal probability to power up to either \"1\" or \"0\", depending on the noise.  
Figure 4: (**a**) Changes in \(\sigma_{V_{th}}\) with transistor effective channel length [10]; (**b**) relationship between the percentage of unreliable bits and the scaling factor of SRAM cell template, where the widths of pull-down, pull-up and access transistors of a unit-size SRAM cell are \(W_{M1}=180\) nm, \(W_{M2}=90\) nm and \(W_{M3}=135\) nm, respectively, and all transistors have \(L=45\) nm.  
Figure 4b depicts the simulation results of the response bits generated by powering up the same SRAM cell 10 times in the presence of noise, whose parameters are set as \(f_{min}=10^{6}\) and \(f_{max}=10^{11}\), where \(f_{min}\) and \(f_{max}\) are, respectively, the base and maximum frequencies used for modeling frequency dependent noise sources [11]. An SRAM cell that does not generate the same start-up value, i.e., \"1\" or \"0\", is consistently regarded as unreliable. The percentage of unreliable bits obtained from 500 cells of an SRAM array is plotted against the size of SRAM cell. The data points can be fitted by a second order polynomial, which indicates that the percentage of unreliable bits increases almost linearly with the transistor size.