# FPGA-Based Pulse Compressor for Ultra Low Latency Visible Light Communications
## 4 FPGA Implementation
### The Transmitter  
The architecture of the transmitter is sketched in Figure 5. It is composed by several processing blocks connected through an Avalon(r) streaming bus [26]. Data, moved by the bus, cross all the blocks serially. The data flow is regulated through the backpressure technique implemented in the Avalon(r) bus: each block, when it is not ready to sink data, rises a 'busy flag' that stalls the data flow from the previous block. On the other hand, the processing chain is designed so that each block grants the availability of data as soon as the successive block is ready to accept them. This way, the rate of the data flow along the chain is imposed by the last block, which is the \"Modulator\". This architecture grants a constant and uninterrupted data flow at sample rate towards the Digital-to-Analog Converter (DAC) and the LED. Figure 4: The received signal (top) is correlated to the chirp to obtain the compressed signal (bottom). The bitstream is recovered by detecting the peaks through a threshold (red dashed line). In this example, the 24-bit packet “1111010111010011100100” is detected. Figure 5: Architecture of the transmitter. Data words to be transmitted are buffered in a First-In-First-Out (FIFO) memory. The FIFO separates the clock domains of the FPGA core that operates at 125 MHz from the transmitter domain that operates at the lower frequency of \(1/T_{TC}\). The 16-bit payload is moved from the FIFO to the next block that formats the 24-bit packet. This block calculates the CRC and builds the packet by adding the CRC and the preamble. The 16-bit input words and 24-bit output words flow at the rate of one word for every 24 bits transmitted, i.e., \(24/T_{B}=3/T_{TC}\). Thus, the block has three clock cycles to process each word. This is a simple block, and no further details are here provided. The next block is the Serializer, which sinks the 24-bit word in parallel and outputs it serially, providing the bitstream for the modulator. The output rate is \(1/T_{B}\). Similarly to the previous block, no further details are necessary for this simple step. The modulator is by far the most complex part of the transmitter and deserves more attention. Its internal architecture is detailed in Figure 6.  
The modulator is fed by the bitstream prepared by the previous blocks and produces in outputs the samples of the signal that, once converted in current, are transferred to the LED. It works with the clock CK at rate \(1/T_{TC}\), and thus every 8 CK cycles it accepts in input and processes a new bit. On the other hand, every CK cycle a new sample of \(RF_{tx}(n)\) is produced in output. Although the architecture of the modulator is the same, its complexity scales with the chirp length. In fact, the number, \(Nc\), of chirps to be added for each output sample rises with the chirp length, like stated by (6). The modulator should basically add the \(Nc\) chirps, suitably phased and masked by the corresponding data bit. This task is achieved by employing \(Nc\) identical look-up tables that store: the samples of the chirp; \(Nc\) 'AND' gates used for zeroing the corresponding look-up output; a \(Nc\)-input adder; and a sequencer block that generates the look-up addresses, the gates masking inputs, and the circuit timing. The sequencer generates the addresses to the chirp look-up tables through the counter ADD_cnt followed by a chain of adders. The n-th address in the chain, ADDn (\(0\leq n\leq Nc\)-1), is obtained by summing the value \(8\cdot n\), so that the chirp n is delayed by 8 samples with respect to the chirp n-1. The sums are modulo \(N_{S}\), where \(N_{S}\) is the number of chirp samples. Every CK cycle, the ADD_cnt is incremented. When the ADDn output is pushed back to 0 (because it reached \(N_{S}-1\)), the corresponding bit BITn is loaded with the next bit in the input bitstream. This bit feeds an input of the AND gate, so if the bit is zero, the chirp samples are zeroed; otherwise, the samples reach the adder unaffected. Finally, the adder  
Figure 6: Architecture of the modulator.