# A Wideband Power Amplifier in 65 nm CMOS Covering 25.8 GHz-36.9 GHz by Staggering Tuned MCRs
## 4 Results and Discussion  
A wideband power amplifier is designed in 65 nm CMOS technology and the layout is shown in Figure 24a. The area of the chip core is about 0.686 mm*1.933 mm. Figure 24b presents the simulated S-parameters of the designed power amplifier. The peak small-signal gain is 25.87 dB at 35.5 GHz, with a 3 dB bandwidth of 11.1 GHz from 25.8 GHz to 36.9 GHz. The output reflection coefficient is lower than \(-10\) dB from 22 GHz to 43.5 GHz while the worst input reflection coefficient is only lower than \(-3\) dB as the design goal is to broaden the bandwidth of the gain rather than wideband input matching at the input. Benefiting from the multiple-neutralization-stage design, the reverse isolation is better than \(-100\) dB from 20 GHz to 40 GHz, as shown in Figure 25a. The stability factor Kf is greater  
Figure 23: **(a)** The Gmax and stability of the 128 \(\upmu\)m transistor used in the output differential pair versus the values of neutralization capacitance (Cneu) at 32 GHz and (**b**) the Gmax and Kf at different frequencies when shunt resistors are added to the output stage pair. than 1000 for all the frequencies. The large-signal performance versus input power (Pin) at 28/31/32 GHz is shown in Figure 25b. Biased at 1.1 V supply voltages for all the three stages, the power amplifier achieves a \(P_{sat}\) of 17.57 dBm/17.84 dBm/17.81 dBm, a \(PAE_{max}\) of 24.37%/23.59%/23.12%, a \(OP_{1 dB}\) of 13.92 dBm/14.09 dBm/14.04 dBm, and a \(PAE_{P1 dB}\) of 10.24%/10.53%/10.38% at 28/31/32 GHz, respectively. Also, as shown in Figure 26a, at the frequency edge of interest, i.e., 26 GHz and 36 GHz, a \(P_{sat}\) of 17.04 dBm/17.04 dBm, an \(OP_{1 dB}\) of 13.54 dBm/13.47 dBm, a \(PAE_{max}\) of 23%/20.81%, and a \(PAE_{P1 dB}\) of 9.45%/9.27% are achieved, respectively. To check the wideband large-signal performance of the designed power amplifier, Figure 26b presents the \(P_{sat}\), \(OP_{1 dB}\), \(PAE_{max}\), and \(PAE_{P1 dB}\) from 26 GHz to 36 GHz. The designed power amplifier achieves a \(P_{sat}\) of \(17.44\pm 0.4\) dBm with a \(PAE_{max}\) of \(22.59\pm 1.78\%\), and an \(OP_{1 dB}\) of \(13.78\pm 0.31\) dBm under the 1.1 V supply voltage. Compared with the results of the only power stage with ideal LC input matching in Figure 11b, the average \(P_{sat}\) and \(OP_{1 dB}\) deteriorate from 17.66 dBm and 14.21 dBm to 17.52 dBm and 13.85 dBm from 26 GHz to 36 GHz, respectively. The average \(PAE_{max}\) decreases from 29.46% to 23.04%. The results prove that the designed power amplifier achieves wideband performances in both small- and large-signal performance using the wideband output symmetrical MCR and the staggered MCRs between stages. Table 1 summarizes the performance of the designed wideband power amplifier and compares it with other state-of-the-art PAs in the Ka-band. Our power amplifier demonstrates the highest gain compared with the previous work in Table 1 despite the use of staggering. Both the small- and large-signal bandwidths are competitive among the references in Table 1 besides the FD-SOI power amplifier in reference [29]. With a 1.1 V VDD supply and the power combining method, the \(P_{sat}\) and \(OP_{1 dB}\) of our power amplifier are impressive besides the work with a 3.3 V/2.2 V supply in references [23; 38], respectively. Figures 27 and 28 present the S-parameters and large-signal performance at the ff corner and ss corner, respectively. At both the ff corner and ss corner, the DC bias current of all the stages is adjusted by changing the gate bias voltage to make it nearly the same as that at the tt corner. At the ff corner, the 3 dB small-signal bandwidth is 12.13 GHz, with a peak gain of 23.9 dB, as shown in Figure 27a. It achieves a flat \(P_{sat}\) of 16.91-17.74 dBm, a flat \(OP_{1 dB}\) of 13.51-14.17 dBm, and a \(PAE_{max}\) of 20.57-23.76%, between 26 GHz and 36 GHz, at the ff corner. At the ss corner, the 3 dB small-signal bandwidth is 10.29 GHz, with a peak gain of 27.57 dB, as shown in Figure 28a.