# Online Signature Verification Systems on a Low-Cost FPGA
## 3 Hardware Implementations
### Hardware Accelerator  
The second approach attaches a hardware accelerator, named FPBA (Floating-Point Biometric Accelerator) [23], to the embedded system. The FPBA is a programmable acceler  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Data format**} & **Average** & **Standard** & **Variance** & **Median** \\  & **Error** & **Deviation** & & \\ \hline Single-precision & \(1.292\times 10^{-3}\) & \(7.768\times 10^{-3}\) & \(6.034\times 10^{-5}\) & \(2.272\times 10^{-4}\) \\ \hline Fixed-point & \(3.353\times 10^{-4}\) & \(7.229\times 10^{-4}\) & \(5.227\times 10^{-7}\) & \(9.541\times 10^{-5}\) \\ \hline \hline \end{tabular}
\end{table}
Table 1: Statistical analysis of data formats.  
Figure 4: Overview of the embedded system.  
ator designed to speed up operations on floating-point vectors, commonly used in several biometric algorithms. MicroBlaze configures the FPBA at runtime, setting pointer registers to the vectors stored on external memory and the floating-point instructions that must be executed. Then, the FPBA launches the instructions, automatically retrieving/writing vectors from/to memory when required through memory channels, independent of MicroBlaze. Starting from the first approach, the implementation of the algorithm is also reduced to a programming problem but replacing the C code that must be accelerated by FPBA instructions on floating-point vectors.  
The FPBA is basically a programmable processor that controls a pipelined FPU attached to memory channels, improving the execution time of biometric algorithms on floating-point vectors. A vector is a set of sequentially ordered data, which is stored in the memory. Vector lengths are configurable, launching a set of FPBA instructions repeatedly in hardware-controlled loops. Partial results of a vector computation can be temporarily stored in the internal registers and can be retrieved when needed. Any FPBA instruction defines the operation type (MIN, ADD, SQRT, etc.) on the involved source and destination operators, which can be vectors (V0 to V7), registers (R0 to R15) or scalars (S0 to S7).  
Figure 5 depicts an overview of the architecture, which is mainly focused on the fast execution of single-precision operations on vectors, commonly used in biometrics. Firstly, the pipelined FPU increases the throughput to one instruction per clock cycle of the most frequently used operations (as the maximum, addition/subtraction and multiplication). The throughput of more complex operations, such as the square root and exponential, is greatly decremented to one instruction per 28 clock cycles. Secondly, a register file temporarily stores partial results of operations that form a computation over vectorized data. Finally, the double control unit (CU0 and CU1) permits two sets of instructions virtually executed in parallel, multiplexing on time the driving of signals for the FPU and registers through an arbiter. The CU0 can continuously launch those instructions with the faster throughput; meanwhile, CU1 is waiting for the result from instructions with a slower throughput.  
FPBA instructions should be properly ordered and grouped, reducing latencies due to operand dependencies. Moreover, instructions can also be separated to take profit of the double control unit, enhancing the execution time. This approach improves the execution time when compared with the previous embedded system, maintaining the flexibility of the hardware reusability for other biometrics. Nonetheless, it requires a deep knowledge of the FPBA architecture and timing details, and, therefore, a higher development effort when compared with the first approach.  
Figure 5: Overview of the FPBA architecture.