# FPGA Applied to Latency Reduction for the Tactile Internet
## 6 Implementation Description
### Inverse Kinematics (IK-HSD)  
The hardware associated with the slave device (HSD) implements the inverse kinematics through the IK-HSD module, as shown in Figure 4. The IK-HSD FPGA-implemented circuit is designed to work with three input signals \(x^{HSD}[F32](n)\), \(y^{HSD}[F32](n)\) and \(z^{HSD}[F32](n)\) and three output signals \(\theta_{1}^{HSD}[F32](n)\), \(\theta_{2}^{HSD}[F32](n)\) and \(\theta_{3}^{HSD}[F32](n)\). However, to calculate \(\theta_{2}^{HSD}[F32](n)\) (Equation (24)) and \(\theta_{3}^{HSD}[F32](n)\) (Equation (25)) it is first necessary to perform intermediate calculations to obtain the values of \(R[F32](n)\), \(r[F32](n)\), \(\beta[F32](n)\), \(\gamma[F32](n)\) and \(\alpha[F32](n)\)  
Based on Equations (18), (24) and (25), algorithms for calculating \(\theta_{1}^{HSD}[F32](n)\), \(\theta_{2}^{HSD}[F32](n)\) and \(\theta_{3}^{HSD}[F32](n)\) were implemented in FPGA through the generic circuits illustrated in Figures 9-11 respectively. Figure 8: Proposed forward kinematics circuit for obtaining the \(z[F32](n)\) spatial coordinate (Equation (17))—FK-HMD and FK-HSD. Figure 10: Proposed inverse kinematics circuit for obtaining the \(\theta_{2}^{HSD}[F32](n)\) angular position (Equation (24))—IK-HSD. Figure 9: Proposed inverse kinematics circuit for obtaining the \(\theta_{1}^{HSD}[F32](n)\) angular position (Equation (18))—IK-HSD. As already described, and according to the illustrations shown in Figures 10 and 11, to perform the calculations of \(\theta_{2}^{HSD}[F32](n)\) and \(\theta_{3}^{HSD}[F32](n)\) it is first necessary to perform the intermediate calculations of \(\gamma[F32](n)\) (Equation (21)), \(\beta[F32](n)\) (Equation (22)) and \(\alpha[F32](n)\) (Equation (23)). However, these calculations depend on the calculation of \(R[F32](n)\) and \(r[F32](n)\). Then, when the IK-HSD module receives the input signals at every \(n\)-th instant the circuit shown in Figure 9 performs the calculation of \(\theta_{1}^{HSD}[F32](n)\) in parallel with the generic circuits illustrated in Figures 12 and 13 which were implemented in FPGA to perform the calculation of \(R[F32](n)\) and \(r[F32](n)\) based on Equations (19) and (20). The circuit shown in Figure 12 used to obtain \(R[F32](n)\), is designed to work with two input signals \(x^{HSD}[F32](n)\) and \(z^{HSD}[F32](n)\) and one output signal. This design contains two multipliers, two adders, the \(L_{4}\) constant and a sub-circuit called Sqrt, which was implemented in hardware to calculate the square root. The \(r[F32](n)\) calculation is performed the circuit shown in Figure 13. This circuit is designed to work with three input signals \(x^{HSD}[F32](n)\), \(y^{HSD}[F32](n)\) and \(z^{HSD}[F32](n)\) and one output signal. The circuit consists of three multipliers, four adders, one inverter, the constants \(L_{3}\) and \(L_{4}\), and, again, the \(Sqrt\) sub-circuit. After the parallel processing of \(\theta_{1}^{HSD}[F32](n)\), \(R[F32](n)\) and \(r[F32](n)\), the circuits responsible for calculating \(\gamma[F32](n)\), \(\beta[F32](n)\) and \(\alpha[F32](n)\) are also executed in parallel through the FPGA implementations of the generic circuits illustrated in Figures 14-16. Figure 11: Proposed inverse kinematics circuit for obtaining the \(\theta_{3}^{HSD}[F32](n)\) angular position (Equation (25))—IK-HSD. Figure 12: Proposed circuit to perform the calculation of \(R[F32](n)\) (Equation (19))—IK-HSD. Figure 13: Proposed circuit to perform the calculation of \(r[F32](n)\) (Equation (20))—IK-HSD. The value of \(\gamma[F32](n)\) is obtained through the circuit shown in Figure 14 which is based on Equation (21). The circuit is designed to work with an input signal \(r[F32](n)\) and one output signal. It consists of five multipliers, two adder, one divisor, one TFB sub-circuit to calculate the arccosine and the constants \(L_{1}\) and \(L_{2}\). The circuit for obtaining \(\beta[F32](n)\) illustrated in Figure 15 is based on Equation (22) and is designed to work with two input signals \(y^{HSD}[F32](n)\) and \(R[F32](n)\) and one output signal.