# An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios
## 4 Results and Discussion
Additionally, the modulator redesign in [19] to support new modes of operation was strictly confined to the available FPGA resources, as no hardware virtualization techniques were employed. Another relevant aspect is cost-effectiveness. Using an FPGA device with a larger chip area, it would be possible to implement a wide range of baseband modulator modes with relaxed resource availability constraints. However, a larger chip area is more expensive and typically consumes more power. In the proposed architecture, the use of more hardware resources than those available on the \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Resource**} & \multicolumn{3}{c}{**Mode 1**} & \multicolumn{3}{c}{**Mode 2**} \\ \cline{2-7}  & **OFDM** & **FBMC** & **UFMC** & **OFDM** & **FBMC** & **UFMC** \\ \hline Slice & 994 & 1575 & 2301 & 1139 & 2210 & 3103 \\ LUT & 2940 & 5103 & 8210 & 3395 & 7876 & 11,780 \\ FF & 2107 & 2307 & 6279 & 2170 & 2284 & 9912 \\ BRAM & 7 & 19 & 11.5 & 10.5 & 40 & 11.5 \\ DSP & 14 & 21 & 18 & 14 & 21 & 18 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Resource utilization for the implemented baseband modulator cores and comparison with other related works. FPGA device is possible. This enables the system implementation on a small form, cost-optimized device with immediate benefits regarding cost and power consumption compared to larger devices [5]. The clock frequency adaptation through DFS will affect dynamic power consumption. Power estimates for baseband processing were obtained using the Xilinx Vivado 2015.2 Power Analysis tool. To increase the estimates' confidence level, post-place-and-route power analysis with node activity derived from simulation files was performed. For each modulator variant, dynamic power was estimated considering the clock frequency modes defined for DFS (Table 6). Modulator variants with higher resource utilization are likely to induce more node activity and consequently have a higher dynamic power consumption. This justifies the higher power consumption of UFMC modes compared to FBMC and OFDM. The different node activity for each modulator is also the reason why power does not downscale linearly with frequency in every case. Without DFS support, the clock frequency for baseband processing would be fixed to cover the most demanding throughput scenario, even when a lower throughput would be enough. In our design and considering low-throughput scenarios satisfied by a 16.7 MHz clock frequency, DFS allows for power reductions between 99 mW (OFDM Mode 1) and 194 mW (UFMC Mode 2) compared with the operation at 100 MHz. These values represent relative reductions of 88% and 83%, respectively. Comparing operation at 16.7 MHz and 33.3 MHz, we observe power differences from 20 mW (59% reduction in OFDM Mode 1) to 38 mW (49% reduction in UFMC Mode 2). Thus, in our architecture, DFS not only allows for run-time processing throughput adaptation, but also improves the baseband processing power efficiency. Changing the functionality of an RP or the clock frequency used for baseband processing does not occur instantaneously. In real-time systems, it is important to measure and evaluate the impact of reconfiguration latency. With a 100 MHz input reference input clock, a DFS procedure takes on average 47 us to modify and lock the baseband processing clock frequency. DPR latency was measured for each RP, and the worst-case scenarios are displayed in Table 7. To reduce partial bitstream sizes, they were compressed. As expected, the RP with larger area--RP3--had a longer reconfiguration latency associated. Still, the reconfiguration of an RP always took less than a millisecond. In all experiments, the reconfiguration speed was at least 790 MB/s, which is around 99% of the maximum theoretical throughput for the ICAP, considering 32-bit data transfers at 200 MHz. Reconfiguring the communication mode of operation would typically be carried out at the control plane.