# Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World
## 3 Ultra-Low Power MCU Architectures
### Non-Volatile Memories  
A big problem in edge computing is data retention during the idle mode. Current technologies do not cope well with the low voltages used during power gating and voltage scaling as the memories used are usually volatile, like Dynamic and Static RAM (DRAM and SRAM) and internal Flip-Flops (FFs) or Latch-based registers. These traditional technologies can work at high speed and are relatively easy to manufacture and integrate, but they have the disadvantage that information is lost under a certain supply voltage value. Actually, DRAM cells tend to lose the information even when fully powered due to the leakage through the cell capacitance, thus requiring cell refresh mechanism which is energy and time consuming. Even though non-volatile integrated memories exist, like Erasable Programmable ROM (EPROM) and Flash memories, these technologies are usually slow, especially during the writing stage. This can be a serious problem, indeed, with volatile memories, part of the computation core cannot be shut down as the information has to be retained. This bottleneck is driving a lot of research towards new non-volatile memories, which have to be easily integrable, fast, small, reliable and cheap. The main new technological approaches are:  
* Resistive RAMs (ReRAMs) [57; 58; 59; 60; 61; 62; 63], which store the information as the variation of resistivity of a thin oxide film. A current is injected in the oxide to change its structure and to modify its resistance value. It is possible to program one cell to high or low resistance and so to assign a logic value to each of these two states. This technology is compatible with the current (CMOS) process. Moreover, it can achieve switching speeds of up to 10 ns and it features multilevel capability. However, the current required to reset the oxide state is high, usually being difficult to integrate in the circuit. * Ferroelectric RAMs (FeRAMs) [64; 65; 66], which work like Dynamic RAMs but store the information in a ferroelectric layer instead of a dielectric one. The technology can be compatible with DRAM process, but it is usually built on old processes (350 to 130 nm). In addition, this type of memory consumes power only to read or write the memory cell, which drastically lowers the consumption with respect to DRAMs. The technology is intrinsically fast, it takes about 1 ns to modify the state of the layer, indeed. Usually, the bottleneck is the electronic control, which is rather complex, like in DRAMs. * Phase-Changing RAMs (PCRAMs) [67; 68; 69; 70; 71; 72], in which a chalcogenide glass can change phase from amorphous to crystalline. Moreover, chalcogenide glass can also hold an intermediate state, allowing for multilevel storage. However, the cells are difficult to program, so their use is still limited. These devices are faster than Flash-based memories, in particular for writing operations as PCRAMs that feature the possibility to modify each cell individually. The drawbacks are that the cells are prone to aging (even if they are better than Flash memories) and they are susceptible to temperature variations. * Magnetic RAMs (MRAMs) [73; 74; 75; 76; 77; 78; 79; 80; 81], which use electron spin to store information. Currently, MRAMs look a very promising solution and several researchers envision that they might replace both the main memory and the storage memory in future architectures. When reading an MRAM, a current is forced to flow near the magnetic material, and the reading operation is accomplished by sensing the polarization of the magnetic field. When writing, an external current needs to overcome the stored field to impose a new value. As a consequence, writing requires more power consumption than reading. This technology can compete with Static RAM cells speed, while presenting a much lower area utilization.