## 2 Stacked Power Amplifiers  
In CMOS SOI technology, the transistor body is not tied to a substrate but instead can be connected to a preferred node or left floating. The proposed stacking PA structure utilizes this feature. The devices are stacked; i.e., they are electrically floating on top of each other [20]. This enables a higher VDD and thus higher output power as the devices in the stack do not exceed the breakdown voltages if bias points are selected correctly. The schematic of the design is shown in Figure 1. The design is constructed by stacking four devices; in this case, by stacking 40 nm floating body devices. Based on the design manual, VDD can be increased from a nominal 1 V up to 1.1 V and still maintain its reliability. Thus, by stacking four transistors, we can increase the VDD up to 4.6 V taking into account the inductor and routing losses. As a result, the maximum output power that can be transferred to a 50 \(\Omega\) load is above 20 dBm or \(>\)6.3 V peak-to-peak signal. The gates of the transistors in the stacked PA are not RF grounded, but the inter-stage matching and voltage swing of M\({}_{2}\)-M\({}_{4}\) are controlled by dimensioning the gate capacitors C\({}_{2}\)-C\({}_{4}\) correctly. In order to avoid breakdown, the transistors source node waveforms are kept synchronous and progressively increased. Note also that each stage in the stack increases the delay and parasitics (which is a problem especially at mmWave frequencies), and thus it is impractical to increase the number of stacked devices excessively [21]. The simulated voltage swings at the drain nodes of the proposed design with an input power of 0 dBm are presented in Figure 2. It can be seen that the amplitude roughly doubles after each stage, but also a small amount of delay can be observed after each stage. In \begin{table}
\begin{tabular}{c c} \hline \hline
**Modulation Scheme** & **Required EVM (\%)** \\ \hline QPSK & 17.5 \\
16 QAM & 12.5 \\
64 QAM & 8 \\
256 QAM & 3.5 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: EVM requirements for 3 GPP NR carrier [17]. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Carrier BW (MHz)** & **FR2 Frequency Range** & **ACPR Limit** \\ \hline
50, 100, 200, 400 & 24.25–33.4 GHz & 28 dB \\
50, 100, 200, 400 & 37–52.6 GHz & 26 dB \\ \hline \hline \end{tabular}
\end{table} 
Table 2: ACPR requirements for 3 GPP NR carrier [17]. fact, with the gate capacitors, we also minimize the delay and provide a linear increase in the voltage swing in the stack. In addition, a direct match to a 50 \(\Omega\) load is enabled by optimizing the device size and gate capacitors. As a result, an additional output impedance matching network is not needed, which simplifies the design and minimizes the parasitics, losses and area. The PA core (highlighted with red dashed line in Figure 1) consists of four current combined power cells. The schematic of one power cell is shown in Figure 3. Each stage consists of three parallel devices. The total width of each device is 21 \(\upmu\)m with a minimum length to maximize the speed. Thus, the total width of M1-M4 (three devices in one cell and four cells in parallel) is 258 \(\upmu\)m each. The transistor size is optimized in terms of power, linearity and efficiency. The layout of the PA core is illustrated in Figure 4. Power cells are connected symmetrically, the input is connected from both sides of the power cells to minimize the gate resistance, and the drain nodes of M4 are combined as currents instead of power and thus connected directly to the output. As can be seen in Figures 3 and 4, each gate capacitor is distributed in eight small metal oxide metal (MOM) capacitors. This is due to the fact that small capacitors (in a range of 6 \(\times\) 6 \(\upmu\)m\({}^{2}\)) can be placed close to the transistor cells with fewer parasitics. The total value of the gate capacitors decreases higher in the stack. C2 = 330 fF is the largest capacitor, while C4 = 208 fF is the smallest capacitor.