## 3 Case Study: Design and Implementation of the Photovoltaic Control System
### Transformation of the Petri Net-Based Description into Verilog HDL Code  
The transformation of the modeled photovoltaic system to the Verilog code was performed strictly according to the rules presented in Section 2.2. Listing 4 shows the declaration of the main module and input/output signals of the system.  
```
1:module photovoltaic_system(
2:outputreg[3:0]status,
3:outputreg[3:0]status_p,
4:outputreg[3:0]status_t,
5:inputel,e2,e3,e4,e5,e6,e7,e8;
6:inputpw1,pw2,pw3,pw4,pw5,pw6,pw7,pw8;
7:inputtpl,tp2,tp3,tp4,tp5,tw6,tp7,tp8;
8:inputclk,reset
9:);

\begin{table}
\begin{tabular}{c c c} \hline \hline
**Output Signal/Variable** & **Place** & **Description** \\ \hline \([3:0]status_{e}\) & \(p_{18}\) & Number of enabled modules counted \\ \([3:0]status_{p}\) & \(p_{19}\) & Number of panels with correct power \\ \([3:0]status_{t}\) & \(p_{20}\) & Number of panels with correct temperature \\ \hline \hline \end{tabular}
\end{table}
Table 2: Association between output signals and places of the interpreted Petri net.

Figure 10: Specification of a single (1 st) module (a part of the system).

There are 12 registered outputs that strictly refer to the output signals described in the previous section. Moreover, there are 26 input signals in total, and 24 of them correspond to the input signals associated with photovoltaic modules, while the 2 remaining refer to the clock and reset signals. Listing 5 shows the sample equations for transitions and places. According to the rules described in Section 2.2, transitions are declared as wires and utilize continuous assignments, while places are declared as registers and involve procedural assignments. Since the system is synchronous, the states (markings) are changed with the rising edge of the clock signal. Furthermore, the asynchronous reset signal zeroes the system by returning to the initial marking. It can be noticed that there are equations that include six input variables and more. For example, the equation for transition _t2_ (line 04) involves eight input signals (logical conjunction of eight variables). According to the discussion shown in Section 3.3, such equations can be a good basis for the functional decomposition and reduction in the FPGA resources. However, in the presented photovoltaic system, other equations are going to be optimized.
``` //Declaration of transitions: 01: wire [1:108] t; //Declaration of places: 02: reg [1:109] p; //Equations of transitions: 03: assign t[1]=p[1]; 04: assign t[2]=p[10]@[11]&p[12]&p[13]&p[14]&p[15]&p[16]&p[17];... 05: assign t[5]=p[2]&e1; //Equations of places: 06: always@(posedge clk or posedge reset  
```
01:always@(posedge clk or posedge reset)
02:begin
03:if(reset)
04:status_e <= 4'b0;
05:status_p <= 4'b0;
06:status_t <= 4'b0;
07:else begin
08:if(p[18])begin
09:status_e[0]=(e1&e2&e>e3&e4&e-e5&e-e6&e-e7&e-e8)|
10:(e1&e-e2&e-e3&e-e4&e-e5&e6&e-e7&e-e8)|
11:(e1&e2&e>e3&e4&e-e5&e6&e-e7&e-e8)|
12:...
13:status_e[1]=(e1&e2&e-e3&e-e4&e-e5&e6&e-e7&e-e8)|
14:(e1&e-e2&e-e3&e4&e-e5&e-e6&e-e7&e-e8)|
15:...
16:status_e[2]=(e1&e2&e-e3&e4&e-e5&e6&e-e7&e-e8)|
17:(e1&e-e2&e-e3&e4&e-e5&e6&e7&e-e8)|
18:...
19:status_e[3]=(e1&e2&e3&e4&e5&e6&e7&e8);
20:end
21:if(p[19])begin
22:status_p[0]=(pw1&-pw2&-pw3&-pw4&-pw5&-pw6&-pw7&-pw8)|
23:(pw1&-pw2&-pw3&-pw4&-pw5&pw6&-pw7&-pw8)|
24:...
25:end
26:if(p[20])begin
27:status_t[0]=(tp1&-tp2&-tp3&-tp4&-tp5&-tp6&-tp7&-tp8)|
28:(-tp1&-tp2&-tp3&-tp4&-tp5&tp6&-tp7&-tp8)|
29:...
30:end
31:end
32:end
```  
Listing 6: Equations for outputs.