# FPGA Applied to Latency Reduction for the Tactile Internet
## 1 Introduction  
Tactile internet is conceptually defined as the new generation of internet connectivity which will combine very low latency with extremely high availability, reliability and security [1, 2]. Another feature that has been pointed out is that this new generation will be centered around applications that use human-machine communications (H2M) alongside devices that are compatible with tactile sensations [3, 4, 5]. Currently, the IEEE 1918.1 standard [6] defines characteristics of the tactile internet, where both the structure and description of application scenarios and definitions are presented. A tactile internet environment is basically composed of a local device (known as a master) and a remote device (known as a slave), where the master device is responsible for controlling the slave device over the internet through a two-way data communication network [7, 8]. Bidirectional communication is needed to simulate the physical laws of action and reaction, where action can be represented as sending operational commands and reaction can be represented as the forces resulting from that action. In tactile internet applications, the desired time delay for device communication is characterized by an ultra-low latency. In bilateral communication, the required round trip latency ranges from 1 ms up to 10 ms depending on the application requirements [9, 10, 11, 12]. According to [13], it can be noticed that in a tactile internet application, 30% of the total system latency is generated by the master and slave devices. These devices demand high processing speeds as repeated execution of a variety of computationally expensive algorithms and techniques are required. These algorithms involve the use of arithmeticoperations and calculations of linear and nonlinear equations that need to be computed at high sampling rates in order to maintain application fidelity. The remaining 70% of the latency is caused by the communication network, which makes them unsuitable for such latency constraints [14]. To address this problem, some research groups have been studying communication networks in the context of tactile internet. The works [15; 16; 17] shows some types of techniques that can be used to reduce network latency. Other groups have been studying prediction techniques, where many algorithms have been studied and proposals using artificial intelligence (AI) have proved to be effective [18]. On the other hand, the implementation of complex AI-based prediction methods can further increase the latency of the computer systems present in master and slave devices. Alternatively, new approaches such as using field-programmable gate arrays (FPGAs) can improve the performance of master and slave devices in a tactile system environment. The FPGAs enables the creation of customizable hardware which allow algorithms to be parallelized and optimized at the logical gate level to speed up their operations. Literature results show that computationally expensive algorithms can achieve speedups of up to \(1000\times\) over software implementations when custom-implemented in FPGAs [19; 20; 21; 22; 23; 24; 25]. In this context, this paper has, with motivation, a hardware proposed implementation to target reducing the 30% of the total latency related to tactile devices. The project uses FPGA devices to minimize the execution time of algorithms associated with master and slave devices. FPGAs allow the parallelization of algorithms and latency reduction compared to software systems embedded in traditional architectures with general purpose processors and microcontrollers. In an effort to validate the proposed strategy, this paper presents a discrete reference model that can be adjusted for different types of master and slave devices in a tactile internet system. Validation results, throughput, and post-synthesis figures obtained for the proposed hardware implementation using FPGA devices are presented. Comparisons with other works in the literature show that using FPGA can significantly accelerate the processing speed in tactile devices.