# Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers
## 3 Related Works
### Parallel Implementation of CTR Mode of Operation on the NEON Engine
#### 4.2.2 HIGHT-CTR Optimization
The result of Our Work 2 shows faster performance than the previous study [9] and Our Work 1. ### Parallel Implementation of HIGHT-CTR and Revised CHAM-CTR Mode on the NEON Engine

Table 6 shows the performance comparison of HIGHT and revised CHAM parallel implementations. [PERSON] et al. [10] presented the secure and fast implementation for HIGHT and revised CHAM using the NEON engine in the ARMv8 platform. In fast implementation, task and data parallelism was applied to compute multiple operations and data simultaneously. In addition, utilizing all the vector registers, 24 encryptions in HIGHT, 16 encryptions in revised CHAM-64/128, 10 encryptions in revised CHAM-128/128, and 8 encryptions in revised CHAM-128/256 were processed simultaneously. In the secure implementation, [PERSON] et al. [10] optimized random-shuffling, the core operation of fault attack countermeasures, using the NEON engine. Our Work 1 in HIGHT is a parallel implementation with efficient transpose operation and proposed parallel implementation. In addition, Our Work 1 in HIGHT processed 48 encryptions, with more encryptions than before, simultaneously by scheduling all vector registers more efficiently than previous work [10]. Through the above advantages, Our Work 1 in HIGHT achieved about 5.26% performance improvement over the existing fast implementation for HIGHT [10]. Our Work 2 in HIGHT is a parallel implementation of the HIGHT-CTR mode, and, like Our Work 1, 48 encryptions are simultaneously processed. Furthermore, by applying the CTR mode optimization, the computation overheads are reduced by efficiently pre-computing some round operations up to five rounds. Through proposed parallel techniques and optimization of CTR mode, it shows 8.62% performance improvement over previous work [10]. Our Work 1 of revised CHAM is our proposed parallel implementation. Through efficient vector register scheduling, we processed more 48, 24, and 24 encryptions simultaneously, which is more than the number of previous encryptions, in revised CHAM-64/128, CHAM-128/128, and CHAM-128/256, respectively, and likewise applied the transpose operation without additional costs when loading data from memory to four vector registers and storing four vector registers into memory. Through the proposed optimization techniques, Our Work 1 of a revised CHAM family shows an improvement of 9.52%, 1.52%, and 4.02% compared to the previous work [10]. Finally, Our Work 2 of revised CHAM is a parallel implementation of the CTR mode optimization. Our Work 2 of the revised CHAM processes the same number of encryptions simultaneously as Our Work 1 of revised CHAM. In addition, through CTR mode optimization, some round operations up to the initial eight rounds are pre-computed to reduce the computational overheads of the round functions. As a result, performance improvements of 15.87%, 2.94%, and 5.36% in revised CHAM-64/128, CHAM-128/128, and CHAM-128/256, respectively, were achieved compared to previous work [10]. Our Work 2 shows the results of the fastest CTR mode in ARMv8 architecture. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Work** & **Suggested Structure** & **\#Data Parallelism** & **Cpb** & **Improvement** \\ \hline \hline LEA-128 [9] & ECB mode & 24 & 3.88 & - \\ \hline LEA-192 [9] & ECB mode & 24 & 4.69 & - \\ \hline LEA-256 [9] & ECB mode & 24 & 5.32 & - \\ \hline LEA-128 (Our Work 1) & ECB mode & 24 & 3.76 & 3.09\% \\ \hline LEA-192 (Our Work 1) & ECB mode & 24 & 4.56 & 2.77\% \\ \hline LEA-256 (Our Work 1) & ECB mode & 24 & 5.18 & 2.63\% \\ \hline LEA-128 (Our Work 2) & CTR mode (Our Work) & 24 & 3.54 & 8.76\% \\ \hline LEA-192 (Our Work 2) & CTR mode (Our Work) & 24 & 4.39 & 6.39\% \\ \hline LEA-256 (Our Work 2) & CTR mode (Our Work) & 24 & 5.01 & 5.82\% \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Running time comparison of LEA implementation in ARMv8 architecture.