## 3 Results  
The simulation results were generated using the Cadence Virtuoso program using 0.18 \(\upmu\)m CMOS technology from TSMC. The transistor aspect ratio of the CMOS structure of the CDTA is shown in Table 2. The bias current for the CCII (\(I_{B}\)) was 50 nA, and the bias voltage for the TA (\(V_{B}\)) was \(-\)50 mV. The voltage supply was 450 mV (\(\pm\)225 mV), and the power consumption of the CDTA shown in Figure 3, with \(I_{set}\) = 10 nA, was 328 nW. Figure 5 shows the CDU DC characteristics of the \(I_{z}\) versus \(I_{p}\) and \(I_{z}\) versus \(I_{n}\) of the CDTA for \(V_{z}\) = 0. It is evident that the circuit can process signals up to 50 nA, which is equal to the bias current of the CCII. Figure 6 demonstrates the TA DC characteristics of the \(I_{x+}\) versus \(V_{z}\) with various \(I_{set}\) of the TA. The circuit is capable of processing input voltages in the range of \(\pm\)200 mV while the voltage supply is \(\pm\)225 mV, confirming the circuit's ability \begin{table}
\begin{tabular}{c c c c} \hline \hline
**CCII** & **W/L (\(\upmu\)m/\(\upmu\)m)** & **TA** & **W/L (\(\upmu\)m/\(\upmu\)m)** \\ \hline M\({}_{1}\), M\({}_{2}\) & 40/3 & M\({}_{1}\), M\({}_{2}\) & 2 \(\times\) 15/1 \\ \hline M\({}_{3}\), M\({}_{6}\), M\({}_{8}\), & 50/3 & M\({}_{5}\)–M\({}_{11}\) & 2 \(\times\) 10/1 \\ M\({}_{9}\)–M\({}_{11}\) & & & \\ \hline M\({}_{9}\), M\({}_{4}\), M\({}_{5}\), M\({}_{7}\), & 30/3 & M\({}_{3}\), M\({}_{4}\) & 15/1 \\ M\({}_{12}\)–M\({}_{15}\) & & & \\ \hline  & & M\({}_{5c}\)–M\({}_{11c}\) & 10/1 \\ \hline  & & M\({}_{12}\)–M\({}_{19}\) & 2 \(\times\) 15/1 \\ \hline  & & M\({}_{12c}\)–M\({}_{19c}\) & 15/1 \\ \hline \multicolumn{3}{c}{Capacitor: C\({}_{C}\) = 5 pF} \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Transistor aspect ratios of the CDTA. to operate under low supply voltages. The overall performance of the proposed CDTA is summarized in Table 3. Compared with the previous CDTAs in [21; 22; 23; 24; 25], the proposed structure provides a low supply voltage and low power consumption. For the filter application in Figure 4, the capacitance values were chosen as \(C_{1}=C_{2}=20\) pF. With \(I_{set}=60\) nA, the frequency response of the filter is shown in Figure 7,  
Figure 5: DC characteristics of the \(I_{2}\) versus \(I_{p}\) and \(I_{2}\) versus \(I_{n}\) of the CDTA for V\({}_{x}=0\). Figure 6: DC characteristics of the \(I_{x+}\) versus \(V_{z}\) with various \(I_{set}\) of the TA. \begin{table}
\begin{tabular}{c c} \hline
**Parameters** & **Value** \\ \hline Supply voltage & 0.45 V \\ \hline Bias current I\({}_{B}\) & 50 nA \\ \hline Technology & 0.18 \(\mu\)m \\ \hline DC current swings: \(I_{p}\), \(I_{n}\) & \(\pm\)50 nA \\ \hline Current gains: \(I_{z}/I_{p}\), \(I_{z}/I_{n}\) & 0.988, 0.999 \\ \hline Offset current \(I_{z}\) (\(I_{p}\) = \(I_{n}\) = 0) & 0.3 nA \\ \hline \(-\)3 dB bandwidth: \(I_{z}/I_{p}\), \(I_{z}/I_{n}\) & [135, 124] kHz \\ \hline \(-\)3 dB bandwidth of \(g_{m}\) (\(I_{set}\) = 10 nA) & 76 kHz \\ \hline \(z_{p}\), \(z_{n}\) & 19 k\(\Omega\) \\ \hline \(z_{z}\) & 62.27 M\(\Omega\) \\ \hline \(z_{x+}\), \(z_{x-}\) & [861, 792] M\(\Omega\) \\ \hline \(g_{m}\)(\(I_{set}\) = [5, 10, 15, 20] nA) & [34.5, 67.5, 99.5, 130.6] nS \\ \hline Power dissipation(\(I_{setwhere the simulated cut-off frequency was 2.66 kHz, the quality factor was \(\cong\)1, and the power consumption of the filter was 1.098 \(\upmu\)W.  
Figure 8 demonstrates the electronic tuning capability of the filter using different values of \(I_{set}\) = (30, 60, and 90) nA. The corresponding cut-off frequencies were (1.47, 2.66, and 3.58) kHz, respectively. Figure 8: Frequency responses of the CM filter with different \(I_{set}\) for (**a**) LFE, (**b**) HPF, (**c**) BPF, (**d**) BSF, and (**e**) APF. Figure 7: Frequency responses of the CM filter with \(I_{set}\) = 60 nA. To confirm the stability and robustness of the filter design, both Monte Carlo (MC) analysis and process, voltage, temperature (PVT) corner analysis were performed.