# A 28-nm CMOS Low-Power/Low-Voltage 60-GHz LNA for High-Speed Communication
## 5 Conclusions: Main Achievements, Pioneering Research and Future Directions  
This paper presented the design of a wideband, low-power/voltage 60 GHz LNA in 28 nm bulk CMOS technology, specifically tailored for high-speed mm-wave wireless communication systems. The proposed LNA includes a pseudo-differential two-stage amplifier followed by an output buffer stage, optimized using the PE-SNIM strategy. This  
Figure 11: MC-simulated results for main LNA performance parameters. \begin{table}
\begin{tabular}{l c c c c c c c} \hline \hline
**Parameters** & **[20], 2024** & **[21], 2020** & **[22], 2022** & **[23], 2022** & **[24], 2020** & **[19], 2012** & **This Work** \\  & **(M)** & **(M)** & **(M)** & **(P)** & **(M)** & **(M)** & **(P)** \\ \hline No. stages/topology & 1 CAS-2 CS & 3 CS & 2 CS & 2 CS & 1 CAS & 2 CAS & 1 CAS-2 CS \\ \hline Differential (d)/single-ended (s) & s & d & d & d & s & s & d \\ \hline ESD protection/HBM level [kV] & NO & NO & NO & NO & NO & 3 & 2 \\ \hline Center frequency [GHz] & 60 & 60 & 60 & 58 & 60 & 60 & 60 \\ \hline _NF @_ center freq. [dB] & 4.4 & 5 & 7.1 (S) & 4.4 & 4.6 & 8.6 & 8.4 \\ \hline Power gain (\(S_{21}\)) @ center freq. [dB] & 16.8 & 25 & 16.1 & 22.7 & 14.1 & 10.2 & 13.5 \\ \hline _BW\({}_{\text{3 dB}}\)_ [GHz] & 16.4 & 7.5 & 15 & 9 & 6 & 10 & 7 \\  & (50.6–67) & (53.5–61) & (52–67) & (54–63) & (57–63) & (55–65) & (57.3–64.3) \\ \hline _IP\({}_{\text{1 dB}}\)_ [dBm] & \(-13\) & \(-22\) & \(-10\) & \(-16.1\) & \(-13.5\) & \(-11\) & \(-15\) \\ \hline Voltage supply [V] & 1.2 & 1.3 & 1.2 & - & 2.5 & 1 & 0.9 \\ \hline Current consumption [mA] & 27.5 & 36.5 & 58.3 & - & 9.6 & 30 & 11.6 \\ \hline Power consumption, \(P_{\text{DC}}\) [mW] & 33 & 47 & 70 & 29.9 & 24 & 30 & 10.4 \\ \hline CMOS process [nm] & 40 & 65 & 90 & 40 & 130 & 65 & 28 \\ \hline FoM [14] & 2.46 & 1 & 0.57 & 2.01 & 0.98 & 0.45 & 1.10 \\ \hline _FoM\({}_{1}\)_ [15] & 0.29 & 0.25 & 0.06 & 0.43 & 0.31 & 0.05 & 0.20 \\ \hline _FoM\({}_{2}\)_ [16] & 4.76 & 1.84 & 0.84 & 3.90 & 1.87 & 0.54 & 1.38 \\ \hline _FoM\({}_{3}\)_ [17] & 0.87 & 0.09 & 0.33 & 0.62 & 0.84 & 0.26 & 0.37 \\ \hline _FoM\({}_{4}\)_ [18] & 238.54 & 11.64 & 83.56 & 95.61 & 83.57 & 43.25 & 43.53 \\ \hline \hline \end{tabular}
\begin{tabular}{l c c c c c c} \hline \hline
**(S)**: simulations; (M)**: measurements; (P)**: post-layout simulations. [14] _FoM = (Gain [dB] - BW\({}_{\text{3 dB}}\)_ [GHz])_//(_NF [dB] - 1) \(\cdot\)\(P_{DC}\) [_mW]. [15] _FoM\({}_{1}\) = Gain [dB]_//(_P\({}_{DC}\) [mW] - (\(F-1\))). [16] _FoM\({}_{2}\) = (Gain [dB] - BW\({}_{\text{3 dB}}\) [GHz])_//(_\(F-1\) - \(P_{DC}\) [mW]). [18] _FoM\({}_{4}\) = (Gain [dB] - IP\({}_{\text{1 dB}}\) [mW])_//_BW\({}_{\text{3 dB}}\)_ [MHz]_//(_\(F-1\) - \(P_{DC}\) [mW]); \(F\) is the noise factor.  
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Table 2: LNA performance and comparison with the state of the art. technique enables differential operation with ultra-low power consumption, traditionally a challenge in nanoscale CMOS, while maintaining impedance/noise matching. A key innovation of this work is the integration of customized LC resonant networks, made up of stacked coils and differential MIM capacitive structures, which were properly co-designed to obtain compact low-loss on-chip matching, ensuring broadband gain performance. Furthermore, input/output transformers also serve as an intrinsic path for ESD protection, achieving up to 2-kV HBM robustness, an often overlooked yet essential feature in mm-wave designs. Post-layout EM simulations confirm the effectiveness of the proposed design, showing a power gain of 13.5 dB, a 7-GHz \(BW_{\text{3 dB}}\) centered at 60 GHz, an \(N\!F\) of 8.4 dB and an \(IP_{\text{1 dB}}\) of \(-15\) dBm, with a total power consumption of just 10.4 mW from a 0.9-V supply voltage. The LNA meets the stringent requirements of high-speed, low-power OOK-based mm-wave receivers and compares favorably with recent state-of-the-art solutions.