## 3 Simulation Results  
The proposed DDCCTA and mixed-mode universal filter was simulated in SPICE using 0.18 \(\upmu\)m CMOS technology to show its performance. The aspect ratios of MOS transistors and capacitance values are shown in Table 3. The power supplies were given as \(V_{DD}=-V_{SS}=0.5\) V, \(I_{B}=5\)\(\upmu\)A, \(V_{B}=-0.3\) V.  
The performance of the proposed DDCCTA was investigated. Figure 4 shows the DC transfer characteristics when the input voltage \(V_{y}\) was varied and the output voltage \(V_{x}\) is investigated. Figure 4a,b show, respectively, the input voltage swings between \(V_{y+}\) and \(V_{x}\) and its voltage error, and between \(V_{y-}\) and \(V_{x}\) and its voltage error. Thanks to the BD-MOST technique, the rail-to-rail input voltage swings were achieved for a supply voltage of only \(\pm 0.5\) V.  
The transconductance characteristic with different setting currents, Iset, is shown in Figure 5. Figure 5a,b show, respectively, the DC and AC characteristics, when Iset was changed to [2,4,6,8,10,12,14] uA. Figure 6 shows the simulated impedances at the x-, z-, and o-terminals of the DDCCTA. From this result, the resistances at the x-, z-, and o-terminals were, respectively, 1.5 k\(\Omega\), 900 k\(\Omega\), and 4.71 M\(\Omega\), whereas the parasitic capacitances at the o- and z-terminals were 0.197 pF and 0.297 pF, respectively. Figure 4: DC transfer characteristics: (**a**) V\({}_{\rm x}\) against V\({}_{\rm y+}\) and its error, (**b**) V\({}_{\rm x}\) against V\({}_{\rm y-}\) and its error. Figure 5: Simulated transconductance characteristic with different setting currents: (**a**) DC characteristic, (**b**) AC characteristic. \begin{table}
\begin{tabular}{l c c c} \hline
**DDCC** & **W/L (\(\mu\)m/\(\mu\)m)** & **TA** & **W/L (\(\mu\)m/\(\mu\)m)** \\ \hline M\({}_{1}\), M\({}_{2}\) & 30/0.5 & M\({}_{1}\), M\({}_{2}\) & 60/1 \\ M\({}_{3}\) & 13/0.3 & M\({}_{3}\), M\({}_{4}\) & 15/1 \\ M\({}_{4}\), M\({}_{5}\), M\({}_{b}\) & 12/3 & M\({}_{5}\)–M\({}_{11}\) & 20/1 \\ M\({}_{6}\)–M\({}_{11}\) & 50/2 & M\({}_{5}\)–M\({}_{11c}\) & 10/1 \\ M\({}_{9}\)–M\({}_{16}\) & 24/3 & M\({}_{12}\)–M\({}_{19}\) & 30/1 \\ M\({}_{\rm R}\) & 4/5 & M\({}_{12c}\)–M\({}_{19c}\) & 15/1 \\ Capacitor: C\({}_{\rm C1}\) = C\({}_{\rm C2}\) = 2.6 pF, C\({}_{\rm B}\) = 0.5 pF & & \\ \hline \end{tabular}
\end{table} 
Table 3: Transistor aspect ratios and capacitance values of the DDCCTA. The proposed mixed-mode universal filter was designed and simulated. The capacitance values of C\({}_{1}\) and C\({}_{2}\) were 0.26 nF. In the first case, the setting currents I\({}_{\text{set}\,1,2,3}\) were set to 5 uA. Figure 7a shows the simulated frequency magnitude responses of LPF, HPF, BPF, and BSF, and Figure 7b shows the simulated frequency magnitude and phase responses of the APF of the VM filter. The filter consumes 374 uW of power and provides 10 kHz of the natural frequency. Figures 8a, 9a and 10a show, respectively, the simulated frequency magnitude responses (LPF, HPF, BPF, and BSF) of CM, TAM, and TIM, while Figures 8b, 9b and 10b show, respectively, the simulated frequency magnitude and phase responses of CM, TAM, and TIM for APF. Figures 7-10 confirm that the proposed circuit can work as a mixed-mode universal filter. Figure 8: The simulated magnitude and phase frequency responses of CM for: (**a**) LPF, HPF, BPF, BSP, (**b**) APF. Figure 10: The simulated magnitude and phase frequency responses of TIM for: (**a**) LPF, HPF, BPF, BSP, (**b**) APF. The proposed mixed-mode universal filter performance was tested in the case of the process, supply voltage, and temperature variations. In this case, a BPF of both VM and CM was selected for testing. Figure 12 shows the Monte-Carlo analysis using 200 runs of the frequency magnitude responses with 5% variations of the transistor threshold voltage. The selected frequency magnitude responses of VM, and CM are shown in Figure 12a,b, respectively.