## 5 Synthesis Example
The block _LUTerASV_ transforms the full codes \(FC(s_{m})\) into the partial state codes \(\overline{PC(s_{m})}\). This transformation is not executed for the states \(s_{m}\in S^{0}\). The table of _LUTerASV_ includes the following columns: \(s_{m}\), \(FC(s_{m})\), \(PC(s_{m})\), and \(AV_{m}\). The last column includes the symbols of additional variables equal to 1 in the codes \(PC(s_{m})\). In the discussed case, the full state codes are taken from Figure 7; the partial state codes are taken from Figure 9. Using these codes, we can create Table 6. \begin{table}
\begin{tabular}{c c c c} \hline \hline \multirow{2}{*}{**Function**} & \multirow{2}{*}{_CoreFC_} & \multicolumn{3}{c}{_CorePC_} \\ \cline{3-4}  & & \(\$^{1}\) & \(\$^{2}\) \\ \hline \(D_{1}\) & 1 & 1 & 1 \\ \(D_{2}\) & 1 & 1 & 1 \\ \(D_{3}\) & 1 & 1 & 1 \\ \(D_{4}\) & 1 & 1 & 1 \\ \(a_{1}\) & 1 & 0 & 0 \\ \(a_{2}\) & 0 & 1 & 1 \\ \(a_{3}\) & 1 & 1 & 1 \\ \(a_{4}\) & 1 & 1 & 1 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Table of _LUTerFA_. Obviously, using Table 6 gives us the perfect SOPs [17] of SBF (12). To minimize the number of interconnections between the blocks _LUTerFA_ and _LUTerASV_, we transform Table 6 into a multi-functional Kamaugh map (Figure 10). Figure 10 is based on Figure 7. This transformation is done in an obvious way. We have simply replaced the symbols of states from Figure 7 with symbols of corresponding additional variables. Additionally, the codes of states \(s_{m}\in S^{0}\) are \"do not care\" code combinations. Using Figure 10 gives us the following SBF:  
\[ \begin{split} v_{1}&=T_{2}T_{4}\lor T_{2}T_{3};\\ v_{2}&=T_{2}\overline{T_{4}};\\ v_{3}&=T_{1}T_{4}\lor T_{1}T_{3};\\ v_{4}&=T_{1}\overline{T_{4}}.\end{split}  \tag{34}\]  
There are 10 literals in SBF (34). If each function from (12) is represented by its perfect SOP, then these SOPs have \(R1*R4=16\) literals. Therefore, using the multi-functional Kamaugh map allows for reducing the number of interconnections by 1.6 times. As shown in [31], the fewer interconnections a circuit has, the less power it consumes. Step 12. During this step, various technology mapping procedures should be executed [45; 46]. If the FPGA chip used is produced by AMD Xilinx, then their CAD tool Vivado [47] should be applied for implementing an FSM circuit. In the next section, we show some results based on using this CAD package to implement FSM circuits. Experiments allow us to compare the effectiveness of the proposed method in relation to some known methods. At the end of this section, we will show how to estimate the hardware amount in the circuits of FSMs \(P_{2T}Y(A1)\) and \(P_{T}Y(A1)\). We start from FSM \(P_{2T}Y(A1)\). To find the LUT counts for circuits of _CoreFC_, _CorePC_ (the first logic level), and _LUTerFA_ (the second logic level), it is necessary to analyze Table 5 (the table of _LUTerFA_). Each symbol \"1\" in this table corresponds to a LUT from the first logic level. In the table, there are 21 \"1\" symbols. Therefore, the first-level circuits consist of 21 LUTs. If a row of the table includes more than a single 1, then this row corresponds to a LUT from the second logic level. There are \begin{table}
\begin{tabular}{c c c c} \hline \hline \(S_{m}\) & \(FC(S_{m})\) & \(PC(S_{m})\) & \(AV_{m}\) \\ \hline \(s_{2}\) & 0100 & 0100 & \(v_{2}\) \\ \(s_{5}\) & 0101 & 1000 & \(v_{1}\) \\ \(s_{6}\) & 1000 & 0001 & \(v_{4}\) \\ \(s_{7}\) & 0110 & 1100 & \(v_{1}v_{2}\) \\ \(s_{8}\) & 1001 & 0010 & \(v_{3}\) \\ \(s_{9}\) & 1010 & 0011 & \(v_{3}v_{4}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Table of _LUTerASV_. Figure 10: Karnaugh map for SBF _ASV2(SV)_. 7 LUTs in the circuit of _LUTerFA_. This can be found from Table 5. To find the LUT counts for blocks _LUTerOF_ and _LUTerASV_ creating the third logic level, we should analyze SOPs (29) and (34), respectively. If an SOP includes at least two literals, then it determines a LUT of the third logic level. As follows from (29), there are 6 such SOPs. The analysis of (34) shows that the system includes 4 such SOPs.