## 3 Proposed SQRD Algorithm with a Novel Modified RVD
### Proposed Modified RVD
In the SCGR procedure, after the process of sorting#2 is done, PUC#1 and PUA#3 in PE#2 stay idle at the first clock cycle of the processing cycles and process the three columns of the current input \(3\times 3\) matrix in the other three clock cycles; PUa#4 in PE#3 is in an idle state for the first half of every processing cycle and processes the two columns of the current input \(2\times 2\) matrix in the second half; then, PUC#2 in PE#4 processes the remaining \(\mathbf{H}_{4,4}\) at the last clock cycle of the processing cycles and stays idle for the other three clock cycles. In the procedure of RGR, the elimination of \(\mathbf{S}_{3,2}\) in the first \(\mathbf{S}\) performed by PUC#3 in PE#3 in vectoring mode starts at the 41 st clock cycle when \(\mathbf{S}_{3,2}\), i.e., \(r_{1,2}^{l}\), and \(\mathbf{S}_{2,2}\), i.e., \(r_{2,2}\), are obtained after the processing in sorting#3; PUC#4 in PE#4 will eliminate \(\mathbf{S}_{7,6}\) in vectoring mode at the 55 th clock cycle after \(\mathbf{S}_{6,6}\), i.e., \(r_{4,4}\), is obtained from the process of PUC#2. With a time-sharing Givens rotation structure, part of the rotation operations of PUC#3 and PUC#4 performed on the subsequent elements shown in Figure 4 are reasonably assigned to the suitable processing units in an idle state. As illustrated in Figure 9, the rotation operations of \((r_{2,4}^{R},r_{1,4}^{I})\), i.e., \((\mathbf{S}_{2,6},\mathbf{S}_{3,6})\), and \((-r_{2,4}^{I},r_{1,4}^{R})\), i.e., \((\mathbf{S}_{2,8},\mathbf{S}_{3,8})\), are separately assigned to the two CORDIC modules in PEb#2 because PEb#2 is just idle when \(r_{1,4}\) and \(r_{2,4}\) are generated. For a similar reason, the rotation operations of \((-r_{2,3}^{I},r_{1,3}^{R})\), i.e., \((\mathbf{S}_{2,7},\mathbf{S}_{3,7})\), \((0,r_{1,1})\), i.e., \((\mathbf{S}_{2,3},\mathbf{S}_{3,3})\), and \((0,r_{3,4}^{R})\), i.e., \((\mathbf{S}_{6,8},\mathbf{S}_{7,8})\), are assigned to PUC#2, PUC#4, and PUC#3, respectively. If no time-sharing Givens rotation is adopted, as shown in Figure 10, an additional PUC#5 must be used for helping PUC#3 with the rotation operations to match the processing rate of SCGR because it will take seven clock cycles for PUC#3 alone to finish the Givens rotation of the seven paired elements of \(\mathbf{S}_{2,3,\cdot}\), which exceeds the processing cycles of SCGR. Furthermore, it will cost more delay buffers (DBs) for the aligning of the relevant elements for modified RVD, because the process is extended with only three processing units (PUC#3, PUC#4, and PUC#5). Therefore, with time-sharing Givens rotation structure, one CORDIC module and eight DBs (a DB contains \(N_{bw}\) bit registers; \(N_{bw}\) is the adopted bit-width) are saved and the hardware efficiency of the entire SQRD is improved. Figure 10: Processing flow of time-sharing Givens rotation structure. Figure 9: Deeply pipelined processing flow of the proposed SQRD processor with time-sharing Givens rotation structure. ### CORDIC Architecture

Figures 11 and 12 illustrate the detailed CORDIC architecture adopted in our design. The CORDIC module has eight micro-rotation stages and four pipelined stages. In the normal CORDIC module shown in Figure 11a, the rotation direction calculated by \(y_{i}>0:-1:1\) is used and stored in VM; and in RM, the rotation direction is retrieved. In the CORDIC module used for the time-sharing Givens rotation structure shown in Figure 11b, a time-sharing mode (TSM) is added to process the shared rotation operation using the rotation direction from the corresponding processing unit. The scale factor of CORDIC with eight micro-rotations is \(\prod_{i=0}^{7}\bigl{(}1/\sqrt{1+2^{-2i}}\bigr{)}=0.607259\). In our design, we approximate this number to \(2^{-1}+2^{-3}-2^{-6}-2^{-9}=0.607421875\) and the corresponding hardware architecture is presented in Figure 12.

### Sorting

The iterative sorting procedure of the proposed SQRD processor is performed with norm calculator and sorting#1-3. Figure 13 shows the architectures of these modules.