# A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process
## 3 Circuit Implementation and Calibration
### Four-Port Comparator in Sub-ADCs  
The comparator is one of the most commonly used modules in the sub-ADCs. As shown in Figure 6, a four-port comparator consists of pre-amplifier, latch, buffer, and calibration circuit. In this design, the pre-amplifier isolates the kick-back noise generated by the strong-arm latch. The strong-arm latch with cross-coupled pairs is used to directly produce the rail-to-rail outputs for the output signal of the pre-amplifier [26]. Based on the mentioned clocks \(\phi_{3}\) and \(\phi_{3e}\) in Section 2, the timing of comparator is divided into two phases. In the first phase of \(\phi_{3e}\), \(\phi_{3}\) is at a low level. Transistor M9 and M10 are off, while transistors M11-M14 as switches are on. Then, the output terminals VOP and VON are pulled up to DVDD. The process of resetting the comparator is finished. At the same time, the MOSFETs do not work, so there is no static power consumption. In the second phase of \(\phi_{3}\), \(\phi_{3}\) is at a high level. VIP and VIN are the two differential signal inputs, coming from the output of the pre-amplifier. The input signals realize signal conversion through the cross-coupled pairs, which can quickly increase the current of the circuit and cause VOP and VON to become high- or low-voltage.  
The offset of the comparator mainly comes from differential pairs M1-M4 and M9-M10, which cannot go beyond 1/2 LSB of this sub-ADC, otherwise the residual will exceed the quantification range of the next stage. In this design, the equivalent input offset voltage (V\({}_{\text{OS}}\)) of the comparator is about \(\pm\)53 mV within the 3-sigma interval of the Monte Carlo simulation. The offset contributed by the pre-amplifier is about \(\pm\)36 mV, more than the offset of the latch. To decrease the offset, the sizes of M1 and M2 are increased to match better, and the overdrive voltage of the input MOSFET is reduced to 105 mV.  
To correct the offset, a 3-bit calibration circuit is added in the pre-amplifier to correct the offset of the comparator by controlling OS_P<2:0>and OS_N<2:0> in Figure 7a. A detailed calibration process for offset is mentioned in Section 3.5.1. Figure 7b is the equivalent circuit of Figure 7a.  
As is shown in Figure 7a, the offset and output common mode are changed when \(\Delta\)I is introduced. When ignoring channel length modulation effect and \(\Delta\)I \(\
eq\) 0, the relationship between V\({}_{\text{OS}}\) and \(\Delta\)I is as Equation (1):  
\[\text{V}_{\text{OS}}=\sqrt{\frac{2\text{I}-\Delta\text{I}}{\text{u}_{\text{n} }\text{C}_{\text{ox}}\frac{\text{W}}{\text{L}}}}-\sqrt{\frac{2\text{I}+\Delta \text{I}}{\text{u}_{\text{n}}\text{C}_{\text{ox}}\frac{\text{W}}{\text{L}}}} \tag{1}\]  
Figure 5: Delay lock loop. (**a**) Delay lock loop schematic; (**b**) Delay line schematic; (**c**) timing of delay line.  
As is shown in Figure 7b, an additional \(\mathrm{V_{OS}}\) is caused by \(\Delta\mathrm{I}\) at the input. VTP\({}^{\prime}\) and VTN\({}^{\prime}\) are the output ports. When \(\Delta\mathrm{I}\
eq 0\), the output common mode is increased as in Equation (2):  
\[\mathrm{VTP}^{\prime}-\mathrm{VTP}=\mathrm{VTN}^{\prime}-\mathrm{VTN}=\frac{ \Delta\mathrm{I}}{2}\times\mathrm{R} \tag{2}\]