## 2 Materials and Methods
### Design and Implementation of swHPFM
#### 2.2.4 Vectorization  
In the SW26010 processor, each CPE has a 256-bit-wide SIMD floating-point unit, whose instruction pipeline is fixed to up to 8 stages. To analyze its main cost, an aligned vectorized and nonvectorized test set was designed, in which 512-cycle addition, subtraction, multiplication, and division operations were compared. The results demonstrate that, for the aligned SIMD vectorized program, the computing performance can be accelerated by as much as 3.956x, compared to the scalar operation, as listed in Table 2.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Instruction** & **Non-Vectorized (Cycles)** & **Vectorized (Cycles)** & **Speedup** \\ \hline vaddd & 3342 & 846 & 3.950 \\ vsubd & 3417 & 917 & 3.726 \\ vmult & 3417 & 846 & 4.039 \\ vdivd & 18169 & 4436 & 4.096 \\ vmad & 6159 & 1551 & 3.971 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Aligned vectorization performance.  
However, to use simd_load/simd_store for vectorization, it is necessary to ensure that the standard-type variable is 32-byte-aligned (for floatv4, only 16-byte-aligned). The compiler can only guarantee that the head address of the array is aligned. The remainder of the data address is required for a programming guarantee. If unaligned memory access is executed, the MPE automatically degenerates into unaligned access, executed by simd_load/simd_storeu extension functions. However, a higher price will be paid. However, the CPEs will directly output the \"Unaligned Exception\" error.  
In the CPEs, it is necessary to explicitly use the simd_load/simd_storeu extension functions or the vldd_ul/vldd_uh/ vstd_ul/vstd_uh instructions to execute the unaligned operation. Comparing the unaligned vectorized and nonvectorized 512-cycle addition, subtraction, multiplication and division operations, the results demonstrate that the unaligned SIMD vectorized program only realizes an average speedup of 1.822\(\times\), compared to the scalar operation, as listed in Table 3.  
Comparing Tables 2 and 3, the unaligned SPM access severely degraded the vectorization performance. The absolute latency of the unaligned access was even higher. In addition, the latency of the vectorization operation, which includes the arithmetic and permutation operations [22], is listed in Table 4.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Category** & **Instruction** & **Absolute Latency (Cycles)** & **Pipeline Latency (Cycles)** \\ \hline \multirow{4}{*}{Arithmetic} & vaddd, vadds, vsubd, & \multirow{2}{*}{7} & \multirow{2}{*}{1} \\ \cline{3-3} \cline{5-5}  & vsubs, vmad, vmas & & \\ \cline{2-3} \cline{2-3} \cline{5-5}  & vsqrtd/vsqrts & 32/18 & 28/14 \\ \cline{2-3} \cline{5-5}  & vdivd/vdivs & 34/19 & 30/15 \\ \hline \multirow{2}{*}{Permutation} & vinsw, vinsf, vextw, & \multirow{2}{*}{1} & \multirow{2}{*}{1} \\  & vextf, vshift, vshiftw & & \\ \hline \hline \end{tabular}
\end{table}
Table 4: Absolute and pipeline latencies of the SIMD instructions.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Instruction** & **Non-Vectorized (Cycles)** & **Vectorized (Cycles)** & **Speedup** \\ \hline vaddd & 3405 & 2315 & 1.471 \\ vsubd & 3407 & 2316 & 1.471 \\ vmult & 3408 & 2317 & 1.471 \\ vdivd & 17895 & 5819 & 3.075 \\ vmad & 6154 & 3794 & 1.622 \\ \hline \hline \end{tabular}
\end{table}
Table 3: Unaligned vectorization performance.  
The instruction prefix 'v' stands for the vector operations. The instruction suffixes 'd'/'s' and 'w'/'f' represent double/single-precision and word/ floating-point vectors, respectively. The permutation instructions 'ins'/\"ext\"/\"shf\" correspond to insertion/ extraction/shuffle operations. Therefore, to fully utilize the SW26010 vectorization, the kernel array was converted from an array of structures (AOS) into a structure of arrays (SOA) to facilitate the alignment operation in the CPE. In addition, since the shuffling operation has a lower latency than unaligned access, a fine-grained shuffling operation is used to generate data to reduce the number of unaligned loadu/stroeu operations.