# Efficient Implementation of Matrix-Based Image Processing Algorithms for IoT Applications
## 2 The Algorithm Description
Some adaptations of the algorithm were made to reduce the execution time: for S = 15, the method of determining set S has been changed (considering that the number of possible combinations is 16, all the possible combinations will be considered and there is no need to randomly choose), and the number of iterations in the CS-RANSAC algorithm is limited to a maximum of 16 iterations. VSDP++ library functions were used for all matrix and vector operations [22; 23]: matrix multiplication--_matmmllf_, matrix addition and subtraction--_matsadd_, _matssub_, matrix transpose--_transpm_, maximum and minimum element in a vector--_vecmax_, _vecmin_, location of maximum and minimum element in a vector, _vecmaxloc_, _vecminloc_. The code uses a 32-bit representation for floating point algorithm variables and computations (multiplications and additions) [23]. This approach will cause a slight decrease in precision and, therefore,the quality of the reconstructed image, but the use of a 32-bit fixed-point representation would excessively increase the execution time. The use of fixed-point representation keeps the processing time at reasonable values with an acceptable decrease in performance. The execution time was measured, in processor cycles, using the IDEs' code profiler. ## 5 The Performance Using 32-Bit Fixed-Point Microcontrollers

This section describes the results obtained using the 32-bit processor. The execution time and the effect of finite precision are shown in Figures 5-7. One can observe, in these figures, that the performance is good. For low and medium levels of mixed noise, the CS-RANSAC algorithm has a PSNR greater with up to 4 dB and a SSIM greater up to 80%. The SSIM obtained with CS-RANSAC is better than that of DCT even the differences in PSNR are not so high for high levels of mixed noise. The CS-RANSAC algorithm responds better for impulsive noise, as is shown in Figure 7. In Figures 5-7, the noised image characteristics (PSNR, SSIM, noise type) are the same as noised images characteristics from Figures 2-4. Figure 5: Performance evaluation for low noise (microcontrollers implementation). Table 2 summarizes the performances, and Table 3 compares the implementation in MATLAB with Blackfin implementation. Table 4 illustrate the execution time considering a Blackfin processor at 750 MHz. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multicolumn{1}{c}{**Noised Image**} & \multicolumn{2}{c}{**DCT Reconstructed Image**} & \multicolumn{2}{c}{\
\begin{tabular}{c} **CS-RANSAC** \\ **Reconstructed Image** \\ \end{tabular} } & \multicolumn{2}{c}{
\begin{tabular}{c} **Execution Time** \\ **CS-RANSAC** \\ \end{tabular} } \\ \hline
**PSNR** & **SSIM** & **PSNR** & **SSIM** & **PSNR** & **SSIM** & **Cycles** & **Time** \\ \hline
20.48 & 0.36 & 23.92 & 0.46 & 26.04 & 0.59 & 4,675,862,063 & 6.23 \\ \hline
17.14 & 0.21 & 20.8 & 0.29 & 24.18 & 0.54 & 5,662,802,735 & 7.55 \\ \hline
14.29 & 0.15 & 17.87 & 0.21 & 22.21 & 0.62 & 8,728,624,005 & 11.64 \\ \hline
15.04 & 0.18 & 18.04 & 0.25 & 19.47 & 0.42 & 7,584,207,993 & 10.11 \\ \hline
19.6 & 0.38 & 22.45 & 0.46 & 23.45 & 0.57 & 4,520,337,537 & 6.03 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Performance comparison (32-bit fixed-point implementation). Figure 6: Performance evaluation for large noise (microcontrollers implementation). An improved implementation using MAX7800x (with ARM core at 100 MHz, RISC V core at 60 MHz and CNN accelerator with 64 cores at 50 MHz) will be described in the next sections.