_Article_  
Design and Implementation of Ternary Logic  
Integrated Circuits by Using Novel  
Two-Dimensional Materials [PERSON] 1, [PERSON] 1, [PERSON] 1, [PERSON] 1,2 and [PERSON] 1,* 1 CNRS-International-NTU-THALES-Research-Alliance (CINTRA), Nanyang Technological University,  
Singapore 639798, Singapore; [EMAIL_ADDRESS] (M.H. ); [EMAIL_ADDRESS] (X.W. );  
[PERSON]DDRESS] (G.Z. ); [PERSON]_ADDRESS] (P.C.) Institut of Electronique, de Microelectronic de Nanotechnologie (IEMN),  
CNRS UMR 8520-Universite de Lille, 59650 Villeenve  
and less devices are required for a given data length. For instance, a ternary system with a digit size = 19 can represent a data size about 319-1 G. Meanwhile, that of a binary system is only 219-0.5 M.  
Ternary logic has been widely studied for decades, but is still severely blocked by the fact that the designs of ternary are much more complex than those of binary. In the 1980s, the design of silicon CMOS ternary occurred as a moderate breakthrough, where one p-MOSFET, two resistors and one n-MOSFET were in-series connected [4; 5]. Such circuits simplified the design, but it required two passive resistive resistors, and increased the production complexity. More seriously, it largely increased the static power consumption because of the two resistors with relative low resistance. In the 1990s, the carbon nanotube field effect transistor (CNTFET) showed itself to be promising for its ballistic transport, high mobility and low off-current properties [7; 8]. And it was then found that the threshold voltage of CNTFET could be well determined by its diameter, which was quite suitable for the ternary threshold logic design [9; 10]. Based upon that, many groups have focused their attention on the demonstration of ternary logic gates using multi-threshold CNTFETs [11; 12; 13; 14; 15]. In their designs, no passive resistive components were needed, but the simplest ternary NOT gate still needed six CNTFETs, which was much more complicated than that of a classical CMOS binary NOT gate (two FETs). Therefore, both the silicon ternary and CNT ternary are not cost-efficient enough to establish a practical ternary application: It needs four transistors in silicon ternary and six transistors in CNT ternary to process one trit (which equals 1.58 bits) of information. Meanwhile, one can use the same four (or six) transistors to process two (or three) bits of information in binary logic circuits. A recent breakthrough on ternary logic is the demonstration of a ternary NOT gate by using the commercial CMOS processes [16]. But it suffers from the low operation frequency due to the ultra-low current, and the other types of ternary logic functions are still undiscovered. Recently, the emerging two-dimensional (2D) semiconducting materials, such as graphene, transitional metal dichalcogenides (TMDs) and black phosphorus (BP), have attracted enormous attention due to their excellent electronic properties [17; 18; 19; 20; 21; 22; 23], and this also opens up new possibilities in logic circuits in terms of both CMOS binary [24; 25] and ternary logic design [26; 27; 28; 29; 30; 31]. For example, [PERSON] et al. [26] presented the first 2D-materials-based standard ternary inverter in 2016. [PERSON] et al. [28] designed and fabricated the novel tunable MoS\({}_{2}\)/BP-based ternary devices (tuned by the electric field and device channel length). [PERSON] et al. [29] demonstrated the graphene/WSe\({}_{2}\)-based light triggered ternary device. However, all of these previous works are mainly focused on the demonstration of a standard ternary inverter (STI). To accomplish simplicity in circuit design and increase the data density in practical integrated circuits, further research on ternary logic devices, circuits and algorithms needs to be explored. In this work, we propose to perform a systematical study on the 2D-based ternary logic from individual ternary logic gates to large scale ternary integrated circuits.