## 2 Fine-Timestamp Maker Design
### Ring Oscillator Design  
The TDC's ultimate resolution is determined by the frequency difference between the ring oscillator and the system clock, clk_0. Since the frequency of clk_0 is constant, the oscillation frequency must be controlled accurately to achieve an ideal resolution of TDC. Therefore, the RO plays an essential role in the Vernier-measuring module. The traditional structure of an RO is shown in Figure 6[21; 22; 23]. Its elemental compositions are the cascaded delay units connected in a looped structure through a NAND gate, where the delay units are the dedicated fast carry-chains in the FPGA. Each delay unit is connected to the \(n\)-input multiplexer so that the ring delay line's actual length could be selected conveniently by changing the four-bit control word (_Sel_ in Figure 6) via the PC. Due to the fast propagation attribute of the delay unit, the frequency of the ROs can be controlled finely. However, the addition of multiplexers incurs a more complex layout and routing of the RO, introducing variable delay fluctuations when they are implemented in different locations on the FPGA. Figure 5: Schematic diagram of the coincidence circuit. Figure 6: Schematic diagram of the traditional ring oscillator. The most commonly used oscillation frequency adjustment method is via a multiplexer; in this paper, we conduct the comparison test using both this method and RO-IP. As shown in Figure 7, the PC is used to adjust the parameters of both ring oscillators to be tested via USB. The frequency of oscillation output by RO-IP and the traditional method can be observed using a high-bandwidth (1.5 GHz) oscilloscope (Tektronix MSO46 made in U.S.A.). The oscillation period statistics of the conventional method are depicted in the red curve in Figure 8. The Figure 8 indicates many unreasonable situations have occurred, such as the oscillation period generated by the RO with more delay units is smaller than those with fewer delay units. It means that there is a non-negligible difference in the delay between the delay units and the multiplexer when different _Sel_ values are selected. Although the period of oscillation is mainly trending upward as the _Sel_ value increases, its actual delay value fluctuates wildly when adjusting it. To make the oscillation period more insensitive to the different implementation locations in FPGA, we should use simpler peripheral circuits as much as possible. Based on this principle, we propose a new delay unit cascading structure called \"DU-IP\", consisting of only 16 cascaded delay units as shown in Figure 9. Instead of using the multiplexer, we adjust the length of the ring delay line through the engineering change order (ECO) tool in the Xilinx Vivado design suite without the process of re-layout. Figure 8: Oscillation period statistics. Figure 7: Diagram of experimental block. In addition, to ensure that the delay units cascaded inside the DU-IP remain in the same relative position with a different layout, we use a relatively paced macro (RPM) tool in Vivado. In this work, we position each delay unit in the DU-IP next to each other (as shown in Figure 10) so that the delay between them is almost consistent, allowing the oscillation period to be adjusted more linearly. Then, we package these relative position constraints of the delay units to form an IP core (intellectual property core). The end users only need to instantiate this IP core when they use it. The absolute position of the DU-IP in the FPGA must then be determined. The delay units can only be cascaded upwards, but there is a larger gap for every 25 configurable logic blocks (CLBs) in each clock region's CLB columns. We adopt the manual routing method (setting the P block constraint) during the instantiation process of the DU-IP to ensure that the starting position of the cascaded delay units is implemented as far from the bottom of the clock region as possible.