# Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors
## 2 Results
### Scheme of a Trigger Adder Modulo a Quasi-Mersenne Number
\begin{array}{c}0\leq z<4\\ z=4\\ 4<z\leq 7\end{array} \right. \tag{20}\]  
In the cases corresponding to the first line of Formula (19), the second line of adders does not perform any actions. Integers lying in the range \(0\leq z<2^{k}\) do not require reduction to a value modulo \(2^{k+1}\). In this case, the variable formed at the output of the adder (\(2_{k+1}\)) is zero. It is non-zero in the cases corresponding to the second and third lines of Formula (5). The difference between these cases is that the number \(z=2^{k}\) does not require reduction modulo \(2^{k+1}\), and the numbers corresponding to the range \(2^{k}<z\leq 2^{k+1}-1\)--vice versa. Reducing a number in the above range \(2^{k}<z\leq 2^{k+1}-1\) to a number modulo \(2^{k+1}\) means that the number \(2^{k+1}\) should be subtracted from the given number and, as in the case considered above, adding a number that in binary representation contains exactly \(k\) ones, i.e., adding the number \(q=2^{k+1}-2^{k}-1\). Let us emphasize once again that for the binary representation of the number \(2^{k+1}\), \(k+2\) binary digits are required. For example, the number 8 in binary representation is 1000. The second line of adders in the circuit in Figure 3 contains \(k+1\) single-digit adders. This means that the number \(2^{k+1}\) will be automatically subtracted when it is used, even when a logical one is formed at the output of the carry bit of the adder with the number \(k+1\). The addition of the number \(q=2^{k+1}-2^{k}-1\), composed in binary representation from \(k\) ones, according to the circuit in Figure 3 is carried out in a manner similar to that discussed above. The carry-out output of the single-digit adder (\(2_{k+1}\)) is connected by feedback to adders (\(2_{i}\)), \(i=1,2..,k\) via the \"logical AND\" element (4). Consequently, the number \(q\), given by Formula (16), will be added to the result of the primary summation (the first line of adders) if a logical one is formed at the output of the adder (\(2_{k+1}\)) or at the output of the generator (5). The above feedback forms an analog of a trigger. Namely, if the result of the summation lies in the range \(2^{k}<z\leq 2^{k+1}-1\), then the circuit can be in two stable states. Indeed, adding the number \(q\) results in the formation of a logical one at the carry-out output of the adder (\(2_{k+1}\)), which supports summation with the above number \(q\). This represents one of the two stable states. The second stable state occurs when a logical zero is formed at the output of the adder carry bit (\(2_{k+1}\)). In this case, the number \(q\) is not added to the result of the primary summation. The generator (5) ensures switching between the two specified stable states. It transfers the circuit to the state \"add the number \(q\) to the primary summation result\". This reduces the result of the primary summation to the sum modulo \(2^{k}+1\). An exception arises when the result of the primary summation corresponds to Formula (16) or the second line in Formula (19). In these cases, it should also remain unchanged (for example, the number 4 does not require reduction modulo 5). This is also ensured by the circuit in Figure 3. To prove this, consider the following summation result  
\[\underbrace{100\ldots 0}_{k}+\underbrace{011\ldots 1}_{k}=\underbrace{111 \ldots 1}_{k} \tag{21}\]This result does not lead to the formation of a logical unit at the input of the adder bit carry (\(2_{k+1}\)). Therefore, after switching off the generator (5), a return to the initial state corresponding to the number \(100\underbrace{\ldots 0}_{k}\) will be performed. Thus, in all three cases corresponding to Formula (19), the proposed circuit actually provides summation modulo \(2^{k}+1\). Let us consider the results of testing the proposed circuit. It should also be noted that the circuit in Figure 3 clearly demonstrates the advantages of using quasi-Mersenne numbers, as well as the possibility of generalizing the proposed approach to summation modulo other numbers.