## 2 Proposed Current-Mirror-Based Potentiostat Readout Circuit  
A block diagram of the proposed potentiostat readout circuit is shown in Figure 2. The proposed circuit consists of potentiostat biasing, current mirror, and TIA stages. In the potentiostat biasing stage, the voltage potential between the WE and RE is maintained by the feedback loop. In the current mirror stage, the current from the CE is copied by the low-noise and mismatch-tolerant current mirror. In the TIA stage, the current from the current mirror stage is converted to a voltage signal. This voltage signal can be converted to a digital code using an analog-to-digital converter (ADC). The top architecture of the proposed current-mirror-based potentiostat readout circuit is shown in Figure 3. The input stage of the readout circuit consists of a sensor and CA. The CA generates a feedback loop with an \(M_{5}\). It maintains a constant \(V_{REF}\) between RE and WE. The \(V_{REF}\) is calculated as  
\[V_{REF}=V_{WE}-V_{RE}=V_{DD}-V_{B1} \tag{1}\]  
The current from the CE is mirrored by the gain-boosted cascode current mirror stage. The mirrored current is converted to the voltage through the TIA stage. Here, the transimpedance gain is programmable to adjust the gain. The low-pass filter (LPF) filters out the unwanted high-frequency components, and also acts as an antialasing filter before a 12-bit successive approximation register (SAR) ADC. The internal operating parameters,  
Figure 3: Top architecture of proposed current mirror based potentiostat readout circuit. Figure 2: Block diagram of the proposed potentiostat readout circuit. including the clock timing, transimpedance gain, \(V_{B1}\) voltage, and chopper frequency are programmable, through a serial peripheral interface (SPI). The architecture of the proposed current mirror is shown in Figure 4a. The current input, \(I_{IN}\), is mirrored to the output current, \(I_{OUT}\). To increase the output resistance of the current mirror and to reduce the number of errors due to the channel-length modulation, a gain-boosted cascade scheme is adopted. The W/L ratio between \(M_{a}\) and \(M_{b}\) determines the current ratio between \(I_{IN}\) and \(I_{OUT}\). Thus, the mismatch derived from the process variation between \(M_{a}\) and \(M_{b}\) directly affects the accuracy of the current mirror. The \(I_{IN}\) is converted to the gate voltage by the diode-connection between the drain of \(M_{c}\) and the gate of \(M_{a}\), and the gate voltage is converted to the \(I_{OUT}\) by the transconductance of \(M_{b}\); thus, the flicker noises from \(M_{a}\) and \(M_{b}\) largely contribute to the overall noise. In addition, the flicker noise from the gain-boosting amplifier acts as the main noise contributor. In this design, these mismatches and low-frequency noise components can be cancelled by the four-phase combinations of the chopper and DEM. In Figure 4b, the current mirror is operated in four phases as a combination of three switching signals, \(CLK\) 1, \(CLK\) 2, and \(CLK\) 5. The connections between the mirror transistors and amplifier are altered periodically as \(P_{1}\), \(P_{2}\), \(P_{3}\), and \(P_{4}\). The mismatches between the elements can be averaged out. In this current mirror, the chopper operation and dynamic element matching operation are merged into four phases. The low-frequency noise of the current mirror and amplifier are up-modulated by the chopper operation. The mismatch between the transistors in the current mirror and the amplifier is averaged, and thus a highly accurate current mirror operation with low noise is achieved. The circuit configuration of the proposed current mirror as the phases of the combined chopper and DEM operations are illustrated in Figure 5. At the point of the connection around \(M_{3}\), in Phase 1, the source of \(M_{3}\) is connected to the drain of \(M_{2}\), and the gate of \(M_{3}\) is connected to the negative output of the amplifier.