## 2 SRAM PUFs  
SRAMs are one of the most common blocks in digital integrated circuits. In addition, they are usually designed with transistor sizes close to the minimum allowed by technology [15]. This fact, together with the aggressive scaling of CMOS technologies, make SRAMs particularly sensitive to parameter variations and external noise. This, in turn, can threaten SRAM stability and data integrity particularly in nanometer technologies [16; 17]. Nevertheless, parameter variations are the basis for SRAM PUF generation, as it was introduced in the previous section, and as it will be further discussed in this section. The most common SRAM cell types are formed by either six or eight transistors [18; 19; 20; 21]. In this work, we focus on the six-transistor cell, the so-called 6T cell. The schematic of the 6T cell is depicted in Figure 1a and it is composed of two cross coupled inverters that form a latch (transistors N\({}_{1}\), N\({}_{2}\), P\({}_{1}\), P\({}_{2}\)), and two pass transistors (N\({}_{X1}\), N\({}_{X2}\)) which allow reading and writing data. The cell has two nodes (Q and QB in Figure 1a), and once the cell is stable, one of them is at V\({}_{\text{DD}}\) ('1' logic state), whereas the other is at 0 V ('0' logic state), so the cell has two stable states: (V\({}_{\text{DD}}\), 0) and (0, V\({}_{\text{DD}}\)). Which node is '0' and which one is '1' determines the bit that the SRAM cell is storing. Furthermore, pass transistors are used to write new data to the cell and to read its content. These two tasks are performed through the bit-lines (BL and BLB). When the cell is off (V\({}_{\text{BIAS}}\) = 0 V), both nodes Q and QB are at 0 V. When the cell is powered on, V\({}_{\text{BIAS}}\) is raised from 0 to nominal supply voltage (V\({}_{\text{DD}}\)). After a transient time, one of the two nodes will end up at 0 V, while the other will end up at V\({}_{\text{DD}}\). This means that the cell will start up either at logic '0' or at logic '1'. If the two cross-coupled inverters were identical and perfectly balanced, a single cell would start up at logic '0' or at logic '1' randomly. In this hypothetical situation, the only factors which could tip the scale to one of the two states will be non-deterministic influences like external or internal noise, small temperature imbalances or other factors that can be considered random in time. However, this scenario is not realistic, since there are always differences in the transistor parameters that result in an imbalance in the cross-coupled inverters of each cell. The relative differences between the inverters of each bit-cell make each individual cell more likely to start up either at logic '0' or logic '1' [22]. Highly mismatched cells will be more prone to start up to a given value each time they are powered up. These cells are highly biased to one of the two states, and they will always start to the same state, or at least be more prone to start to one given state because they will be less affected by external factors. By contrast, cells with near perfectly matched inverters will behave more randomly because, since they do not have an inherent bias towards any estate, they will be more affected by random factors like noise or temperature. Highly mismatched bit-cells are those that are useful for PUFs because their start-up value will be more consistent between start-ups. These cells are usually called \"reliable cells\" from a PUF point of view. Conversely, well balanced cells are not suitable for PUFs because its response will be more unpredictable, and thus unreliable to be used as PUF. Nevertheless, unreliable cells can be used for random number generation [1; 23; 24]. SRAM cells designed to be used as memory storage are usually manufactured aiming to be as well balanced as possible to maximize their stability and dependability when storing data, when being read or when being written. This is in conflict with SRAMs working also as PUFs, since, as discussed above, the best SRAMs for PUFs are those which are more unbalanced.