# A 13.44-Bit Low-Power SAR ADC for Brain-Computer Interface Applications
## 2 Circuit Topology
### Bootstrapped Sampling Switch Design  
As depicted in Figure 4, the charge-pump bootstrapped sampling circuit incorporates dynamic gate biasing technology. Compared to conventional transmission gate switches, the primary advantage of this architecture lies in its constant on-resistance (R\({}_{\text{on}}\)): by stabilizing the gate-to-source voltage (V\({}_{\text{GS}}\)), it maintains a uniform Ron regardless of input  
Figure 3: System architecture of proposed SAR ADC. \(\Phi_{2}\) (Sampling Phase):  
The circuit enters a pumped state, where the source terminal of the switch transistor connects to the bottom plate of the bootstrap capacitor and the gate terminal connects to the top plate of the bootstrap capacitor. Consequently, the gate-to-source voltage (V\({}_{\text{GS}}\)) is pumped to (V\({}_{\text{in}}+\) V\({}_{\text{DD}}\)), ensuring V\({}_{\text{GS}}\) = V\({}_{\text{DD}}\) (independent of input voltage). This implementation eliminates the inherent nonlinear Ron variation of standard CMOS switches, with its on-resistance expressed as follows:  
\[R_{\text{on,bootstrap}}=\frac{1}{\mu_{\text{n}}C_{\text{ox}}\frac{W_{\text{N }}}{L_{\text{N}}}\left(V_{\text{DD}}-V_{\text{THN}}\right)}, \tag{1}\]  
where \(\mu_{\text{n}}\) represents electron mobility (a process-dependent parameter), C\({}_{\text{ox}}\) denotes the gate oxide capacitance per unit area, W\({}_{\text{N}}\) and L\({}_{\text{N}}\) correspond to the width and length of the NMOS switch transistor, V\({}_{\text{GS}}\) is the gate-to-source voltage, where V\({}_{\text{GS}}\) equals V\({}_{\text{DD}}\), and V\({}_{\text{THN}}\) is the threshold voltage. The critical term (V\({}_{\text{DD}}-\) V\({}_{\text{THN}}\)) remains stabilized through the bootstrapping mechanism, ensuring immunity to input signal fluctuations. For bootstrapped gate-voltage switch circuits, the primary sources of nonlinearity include the following:  
1. The charge injection effect in switch transistors manifests when the device turns off, as the inversion layer channel charge redistributes through the source/drain terminals, inducing an error voltage \(\Delta\)V on the sampled-and-held signal. 2. Clock Feedthrough Effect: when the clock signal transitions, it couples onto the sampling capacitor through the gate-drain overlap capacitance (C\({}_{\text{gd}}\)) or gate-source overlap capacitance (C\({}_{\text{gs}}\)) of the switch transistor, introducing nonlinear perturbations at the sampled output. 3. Body Effect (Substrate Bias Effect): in n-well processes, the body effect in NMOS switch transistors must be rigorously considered, as the threshold voltage (V\({}_{\text{TH}}\)) exhibits a nonlinear dependence on the input signal (V\({}_{\text{in}}\)), directly contributing to sampling nonlinearity. In addition to the aforementioned nonlinearity sources, sampling clock jitter also introduces signal distortion, as visually demonstrated in Figure 7.  
\(\delta\)(nT) denotes the temporal deviation between actual and ideal sampling instants at the time nT, representing clock jitter in the time domain. \(\Delta\)(nT) quantifies the voltage error between the measured sample value and the ideal value at nT. The polarity of \(\Delta\)(nT) is determined by the signs of \(\delta\)(nT) and the input signal's slope, where for a sinusoidal input signal x(t) = Asin(\(\omega\)int), the sampling error caused by clock jitter is expressed as follows:  
\[\Delta x(nT)=A\omega_{\text{in}}\delta(nT)\cos(\omega_{\text{in}}nT). \tag{2}\]  
Figure 7: Sampling under clock jitter conditions.