# Enhanced Linearity in Intracranial Pressure Monitoring System Through Sample Isolation Bridge ROIC
## 3 ROIC Implementation Details
### Sample-Data Isolation Based SAR ADC  
Figure 7 depicts the architecture and timing sequence of the 10-bit SAR ADC. This design features a dynamic comparator with two stages, coupled with a set of bootstrapped switches, a dual split-capacitor digital-to-analog converter (CDAC), and SAR logic. In a manner similar to a traditional monotonic SAR ADC, the ADC samples the input signal from the top plates of the capacitor arrays, while the bottom plates are linked to a reference voltage, VCM, or ground via the switch control of the DAC. The capacitor array in a standard 10-bit SAR ADC necessitates 29 capacitance units [44; 45; 46; 47]. As shown in Figure 7, this capacitor array is categorized into two sections, parted by a bridge capacitor, which is configured as a single unit capacitor cell. A Metal-Insulator-Metal (MIM) capacitor is employed, featuring a unit capacitance of 25.12/F. The two sections are referred to as the Lower side (L-side) and Higher side (H-side), as illustrated in Figure 7. On the L-side, base capacitors are arranged with a capacitance ratio of 1:2:4, while on the H-side, they are arranged with a ratio of 1:2:4:8:16:32:64. Utilizing this capacitor array configuration can lead to significant power savings. Figure 8 illustrates the schematic of the proposed bootstrapped switch. It consists of five key modules: (1) a charge-discharge module, (2) a bootstrapped module, (3) a sampling switch module, (4) a virtual switch module, and (5) a sampling isolation module. Figure 6: The schematic of the telescopic cascade amplifier. Figure 7: The 10b SAR ADC architecture and time sequence. Conventional bootstrapped switches have several limitations, such as high power consumption, switching speed limitations, insufficient drive capability, etc., which will become more obvious when high linearity is required for sampling switches in high-precision ADCs. The proposed scheme addresses these challenges by incorporating an additional transistor \(M_{10}\) to prevent unwanted charge leakage and thus protect the switching transistors. A pair of voltage followers are used to isolate the sampling switch from the front-stage low-power analog amplifier. In the sampling switch module, transistor \(M_{2}\) employs a linear bias cancellation technique to effectively reduce the parasitic capacitance and the required sampling capacitance. Besides that, this method also helps to alleviate the body effect. The sampling isolation module further enhances the circuit by isolating the ADC input from the charge injection effects on the output of the front-stage low-power analog amplifier, thereby improving the linearity of the entire sampling switching circuit. A two-stage dynamic comparator, comprising a preamplifier and a latch, sees widespread application in SAR ADCs. Illustrated in Figure 9 is the schematic of a fully dynamic two-stage comparator employed in both the initial and subsequent stages to streamline the design process while optimizing the respective transistor sizes for varying levels of accuracy and speed. Given the minimal voltage difference at the comparator's input, a preamplifier is essential to ensure the latch switches appropriately. During the reset phase, when _Clks_ is low and _ClksB_ is high, the tail current transistor \(M_{5}\) is disabled, allowing \(M_{1}\) and \(M_{2}\) to pull the nodes \(VP\) and \(VN\) to \(VDD\), respectively. Concurrently, the comparator outputs, \(OP\) and \(ON\), are reset to ground. As _Clks_ rises during the regeneration phase, \(M_{5}\) is activated, and the input differential pairs \(M_{3}\) and \(M_{4}\) begin to charge the nodes \(VP\) and \(VN\) at a rate dictated by the input signal difference. As soon as either node approaches the threshold voltage of the latch stage's input transistor, latch regeneration triggers, driving one output high while the other is lowered. With the rising output voltage, a positive feedback mechanism is initiated, ultimately yielding inter-rail outputs.