# InP-Based Foundry PICs for Optical Interconnects
## 3 Building Blocks targeting Hybrid-Integration Applications
### Etched Facets  
The etched-facet building block that is being introduced into our generic-foundry process has already been employed successfully in the realization of a 4-channel scalable optical switch consisting of an InP-based PIC containing an array of SOAs flipped onto a Si/SiNx-based PIC containing the passive switch fabric [22; 23]. Figure 8a shows the schematic implementation of the generic-foundry process, including the etched facets, and Figure 8b shows an SEM photograph of a waveguide with an etched-facet termination near a cleaved facet. Etched facets provide many benefits over cleaved-waveguide facets:  
* They fix the I/O interface positions L\({}_{\text{InP}}\) of the PIC down to sub-micron accuracy, as opposed to cleaved facets, which practically have an accuracy \(\Delta\)x\({}_{\text{cleave,InP}}\) of around +/-10 \(\upmu\)m (see Figure 8c)
* Reduction of back reflection at the facets by setting the angle \(\alpha\) of the etched facet with respect to the waveguide (see Figure 8d)
* They set the desired output angle of the light (angle \(\theta\) as shown in Figure 8d) independently from the angle \(\alpha\) of the etched facet that affects the back reflection
* Possibility of applying optical coatings to the etched facets on-wafer and in a single coating process before cleaving or dicin  
Figure 7: Illustration of four of the most common approaches for hybrid integration of InP PICs with PICs from other technologies. (**a**): edge-coupling method through active alignment between the PICs (**b**) edge-coupling approach employing flip-chip alignment (**c**): surface-coupling approach with grating couplers (**d**): surface-coupling approach using 45\({}^{\circ}\) vertical mirrors. In the work reported in previous studies [22; 23], we were able to achieve an SOA gain of 22-23 dB with the etched facets compared to a gain of 27-28 dB for SOAs with cleaved facets, resulting in an additional loss of \(\sim\)2.5 dB introduced by the etched facets. In this case, the mode size of the waveguide at the etched facets was around \(2.5\times 2.5~{}\upmu\)m\({}^{2}\), resulting in an increased loss and reflectivity (compared to that of a cleaved-facet SOA) due to the roughness from etching of the facet. When transferring this process to the generic foundry run, the etching process for the etched facets will be further optimized for lower roughness and lower etched-facet losses. In addition, the etched facets can also be etched on the diluted waveguides (see Figure 2a), where the mode size is much larger (\(\sim\)10 \(\times\) 7 \(\upmu\)m\({}^{2}\)), reducing the effect of the etched-facet roughness even further. The noise figure of the etched-facet SOAs reported in [22; 23] was around 5-6 dB, and the length accuracy of the etched-facet SOAs was below \(\pm\)0.5 \(\upmu\)m (compared to \(\pm\)3.5 \(\upmu\)m for the cleaved SOAs). Etched facets are advantageous for both edge-coupling concepts shown in Figure 7a,b, however it is important that the optical signal can propagate from one PIC to another (and, of course, also to optical fibers) without much beam divergence (i.e., large mode sizes) so that the light does not bounce off the pedestal that is introduced. As is shown in Figure 8a, a major advantage of our generic-foundry process is that it allows for the realization of SSCs with an MFD of 10 \(\upmu\)m by 7 \(\upmu\)m, resulting in a small beam divergence angle. This, in turn, allows for a rather large pedestal length (\(>\)10 \(\upmu\)m) before a significant portion of the light hits the pedestal. The etched facets are formed on-wafer (before cleaving) by a chemically-assisted ion-beam-etch (CAIBE) process. After structuring of the waveguides, a SiNx hard mask is deposited over the whole wafer. Then, the opening for the etching of the facet is defined by lithography followed by selective etching of the SiNx mask in a reactive-ion etcher.