# Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication
## 3 Combined Min-Sum Algorithm
### A Posteriori Information Update Units

The proposed decoder consists of \(Z=56\) APUs, which implement the operations in a posteriori information update step shown in Algorithm 1. The detailed architecture of a low-complexity APU with only one adder array is shown in Figure 9. Each APU takes \(d_{c}\) inputs at bit-width \(w\)\(P_{n}^{i}[l-2]\) and two values from check-to-variable node memory RMEM, i.e., \(R_{m,l}^{i-1}[l-1]\) and \(R_{m,l}^{i}[l-1]\). Similarly, the _sel_ control signal in the VNU is set to either 0 or 1 to indicate the operation mode. When _sel_ is set to 0, i.e., the first clock cycle, the APU is carried out to calculate the sum of \(P_{n}^{i}[l-2]\) and \(-R_{m,l}^{i-1}[l-1]\). When _sel_ is set to 1, i.e., the second clock cycle, the APU is re-executed in order to calculate \begin{table}
\begin{tabular}{c c c} \hline \hline  & **19-FMVG** & **19-TMVG** \\ \hline No. of Comparators & 18 & 35 \\ \hline No. of MUX\({}_{w-1}\) & 27 & 53 \\ \hline No. of MUX & 0 & 11 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Components required for the minimum finders of \(d_{c}=19\) inputs of bit-width \((w-1)\). Figure 8: Architecture of \(2^{k}\)-first minimum value generator (FMVG) unit using the TS approach [34]. \(P_{n}^{i}[l-1]\) by adding \(R_{m,n}^{i}[l-1]\) into the output from previous clock cycle. At the input, two MUXs are utilized to appropriately select the input data according to the clock cycle being processed. In addition, a deMUX is allocated at the output to indicate the truth output value of APU. Moreover, depending upon the clock cycle being processed, the \(en\) control signal is sufficiently set to pass the computation result from the adder array to the output or feedback to the input multiplexer. All outputs from APUs are given to input multiplexers to start the processing of the next layer, as shown in Figure 4. As in the case of VNU architecture, the proposed APU uses two decompression units DECOM to convert the compressed LLRs taken from RMEM into \(d_{c}=19\) decompressed extrinsic LLRs. ### Controller Block

This block generates control signals, such as \(data\_sel\) to indicate the step being processed; \(cnt\_layer\_cnu\) and \(cnt\_layer\_cnu\) to indicate the layer being processed by CNUs, VNUs, and APUs; and \(mem\_en\), to enable write access to the check-to-variable node memory RMEM. ## 5 Implementation Results and Comparisons

The simulation of proposed low-complexity high-throughput pipelined layered QC-LDPC decoder architecture for 5G NR wireless standard was carried out using BPSK modulation in an AWGN channel environment. Figure 10 illustrates the FER performance of the proposed QC-LDPC decoders on the \(N=3808\), \(R=1/3\) for BG1 base matrix of 5G NR wireless standard. The results indicate that the proposed QC-LDPC decoder architecture scheme with bit-width \(w=4\) and ten decoding iterations deliver a FER of \(10^{-5}\) at 2.75 dB. It can be observed that the CMS decoding provides a better error correction performance compared with the original MS and OMS algorithms. Figure 9: Proposed a posteriori information update unit architecture. The major advantage to be realized from our proposed design comes at the decoder complexity reduction. It should be noted that more clock cycles are required to finish a decoding iteration compared to the conventional design. By applying the hardware reuse approach, the critical path is reduced, and, therefore, the operating frequency is enhanced. Hence, the throughput would remain the same in the case of an ideal clock frequency. The reported throughput is given by Equation (6), where \(f_{max}\) denotes the maximum operating frequency, and \(I_{max}\) is the maximum number of iterations to decode one codeword. Based on the pipeline chart in Figure 11, the number of clock cycles per decoding iteration is \(2\times L\) in which two clock cycles are required to decode each layer. The proposed decoder consumes a total of \((2\times L\times I_{max}+2)\) clock cycles.