## 2 The Proposed SAR ADC
### The Proposed Switching Scheme  
The operational rules of the proposed switching strategy are explained using a 5-bit SAR ADC. The operation consists of a sampling phase and five comparison phases, as shown in Figure 3, where the 4 th comparison phase can be repeated up to N-1 times. Figure 1: The proposed architecture of the N-bit SAR ADC. Figure 2: The sequence chart of the N-bit SAR ADC. Figure 3: Switching stage of the proposed 5-bit SAR ADC. First comparison: The reference voltage of one of the capacitors of the subarray and the maximum capacitor of the main array is GND in the initial state, and the reference voltage of the remaining capacitors is V\({}_{\rm ref}\). The input signal is sampled to the top plate of the capacitor array through a sampling switch. When sampling is complete, the sampling switch is turned off. The comparator can then directly perform the first comparison and output the comparison result (D\({}_{\rm I}\)) without consuming switching energy (E\({}_{\rm I}\) = 0). The voltage at the time of comparison is  
\[\left\{ \begin{array}{c}\rm V_{P}(1)=V_{\rm IP}\\ \rm V_{N}(1)=V_{\rm IN}\end{array} \right. \tag{1}\]  
Second comparison: If D\({}_{\rm I}\) = 1, in the negative-conversion capacitor array, the reference voltage of the maximum capacitor in the main array is switched from GND to V\({}_{\rm ref}\); moreover, the reference voltage of the other capacitors remains constant. If D\({}_{\rm I}\) = 0, in the positive-conversion capacitor array, the reference voltage of the maximum capacitor in the main array is switched from GND to V\({}_{\rm ref}\), and the reference voltage of the other capacitors remains unchanged. Consequently, the low-side voltage increases (V\({}_{\rm ref}\)/2), and the high-side voltage remains unchanged. The second comparison is performed, and the comparator outputs the result of the second comparison (D\({}_{\rm 2}\)). The second comparison does not consume switching energy either (E\({}_{\rm 2}\) = 0). The voltage of the 2 nd comparison is  
\[\left\{ \begin{array}{c}\rm V_{P}(2)=V_{\rm IP}+[1-D_{\rm I}]\times\frac{V_{ \rm ref}}{2}\\ \rm V_{N}(2)=V_{\rm IN}+D_{\rm I}\times\frac{V_{\rm ref}}{2}\end{array} \right. \tag{2}\]  
Third comparison: If D\({}_{\rm I}\)D\({}_{\rm 2}\) = 11 or 0, in the subarray on the higher-voltage side, the reference voltage of capacitors is switched from V\({}_{\rm ref}\) to GND, and in the subarray on the lower-voltage side, the reference voltage of capacitors is switched from GND to V\({}_{\rm ref}\); then, closing the bridge switch between the main array and subarray allows the capacitor array to undergo charge redistribution. If D\({}_{\rm I}\)D\({}_{\rm 2}\) = 10 or 01, the bridge switches are closed directly. As a result, the high-side voltage decreases (V\({}_{\rm ref}\)/4) and the low-side voltage does not change. In the third comparison, the capacitor array switching energy is  
\[\rm E_{3}=2^{N-6}CV_{\rm ref}^{2} \tag{3}\]  
The voltage of the 3 rd comparison is  
\[\left\{ \begin{array}{c}\rm V_{P}(3)=V_{\rm IN}+[1-D_{\rm I}]\times\frac{V_{ \rm ref}}{2}-D_{\rm 2}\times\frac{V_{\rm ref}}{4}\\ \rm V_{N}(3)=V_{\rm IN}+D_{\rm I}\times\frac{V_{\rm ref}}{2}-[1-D_{\rm 2}]\times \frac{V_{\rm ref}}{4}\end{array} \right. \tag{4}\]  
Fourth-to-(N-1)\({}^{\rm th}\) comparisons: Based on the output of the previous step, on the higher-voltage side of the main array, the reference voltage of the corresponding capacitor is switched from V\({}_{\rm ref}\) to GND, while the reference voltage of the other capacitors remains constant; then, the comparator performs the comparison and outputs the comparison results. The ADC repeats the process until (N-1) comparisons are completed. The switching energy for each comparison, from the 4 th to the (N-1)\({}^{\rm th}\), is computed as follows:  
\[\rm E_{i}=\left[ \begin{array}{c}2^{N-1-i}+\sum_{j=4}^{i-1}(D_{i}+D_{j-1}-2D_ {\rm I}D_{j-1})\times 2^{N-1-j}\\ +(3D_{i-1}+(1-2D_{i-1})\times(2D_{\rm I}+D_{\rm 2}))\times 2^{N-4}\end{array}