# Prediction of a Two-Transistor Vertical QNOT Gate
## 3 Results and Discussion
While it was known that such a behavior is fundamentally associated with a high-barrier contact (which is the case here), our data additionally prove that the pinch-off is more accentuated when there is no sufficient gate-source overlap to attract the injected charge carriers toward the channel surface. More importantly, it justifies the presence and absence of the two intermediate voltage levels, since such strong pinching-off at the no-overlap circuit dictates the stable establishment of the constant resistance regime between the complete turning-on and off. Figure 2d,e simply deliver the same message, based on the electron pinch-off at the no-overlap NFET (here the ground is the source) that forms the intermediate state between its full on-off switching. Figure 2: (**a**) Simulation results showing the direct impact of the gate-electrode length on VTC. (**b,c**) Hole concentration inside the PFET at \(V_{\text{in}}=2\) V (level “2”) under no and full overlap conditions. (**d,e**) Electron concentration inside the NFET at \(V_{\text{in}}=3\) V (level “1”) under no and full overlap conditions. Now, we return to the base structure (\(E_{b}=0.6\) eV, no electrode overlap) and demonstrate the possibilities of VTC engineering. Firstly, the parameter \(t_{\text{osc}}\) was found to have a significant impact on the level formation, as illustrated in the simulation results of Figure 3a upon changing \(t_{\text{osc}}\) from 50 to 200 nm. The four output data levels, \"3\", \"2\", \"1\", and \"0\", were extracted at \(V_{\text{in}}=0\), 2, 3, and 5 V, respectively, from each VTC. As shown in Figure 3b-e, the semiconductor thickness significantly influences the two intermediate data voltages, with a clearly monotonous trend, meaning that a desired value can eventually be obtained through fine tuning of the layer thickness. Meanwhile, little or no impact of \(t_{\text{osc}}\) was seen on the two extreme levels. This interesting phenomenon can be explained as follows. Since the QNOT behavior in our system originates from the \(E_{b}\) and the contact resistance thereof [13], an enlarged out-of-plane bulk film resistance at a thicker film can significantly modulate the VTC characteristics [14]. More specifically, the FET contact resistance becomes larger with a higher \(t_{\text{osc}}\) in this staggered electrode architecture [21; 22], affecting the establishment of the pinch-off region (see Figure 2b,d), thus pushing the \"2\" and \"1\" levels toward \(V_{\text{DD}}\)/2 at the same time. Secondly, the vertical positioning of the gate electrode was another efficient controlling factor. In fact, separately changing the PFET and NFET gate dielectric thicknesses is a traditional approach in a complementary metal-oxide-semiconductor (CMOS) binary inverter to relatively tune the strength of the transistors [23]. In our simulation, the total thickness of the common dielectric (\(t_{\text{diel}}\)) was fixed as 100 nm, yet the three in-dielectric positions of the gate electrode (center, high, and low) were compared as graphically illustrated in Figure 4a. The high or low position was made by moving the electrode from the center position by 25-nm upwardly or downwardly, respectively. Figure 4b shows that a systematic horizontal movement of the level \"2\" to \"1\" transition point was observed by changing the vertical gate position. This is understood as the outcome of the increase in the PFET strength (for the high position) or the NFET strength (for the low position) that redistributes the supplied \(V_{\text{DD}}\) at different ratios, thus modulating the mid-transition \(V_{\text{in}}\) point. These results also re-confirm the contact-dominated QNOT mechanism, as evidenced by no practical change in the four data levels and the extreme transitions points, because these properties are mostly determined by the depleted source regions rather than the capacitively modulated channel regions [19]. Figure 3: (**a**) Change of VTC according to the variation of \(t_{\text{osc}}\).