# A Novel ASIC Implementation of Two-Dimensional Image Compression Using Improved B.G. Lee Algorithm
## 4 Results and Discussion
### Image Metric Comparison of the Proposed DCT/IDCT Architectures  
The simulation used four test images, Cameraman, Apple, Bird, and Lena, to evaluate the proposed DCT algorithm's performance. The size of each image was 256 \(\times\) 256, with unsigned 8 bits denoting each pixel. The block size of each image segment was 8 \(\times\) 8, resulting in a total of 1024 blocks for evaluating the input image. The Peak Signal-to-Noise Ratio (PSNR) [28] is used as the evaluation metric to assess the algorithm's performance on the processed image quality. The computation of the Mean Square Error (MSE) is the first step to calculating the PSNR and estimating the variation of the two image's pixel values. The PSNR and MSE are calculated according to Equations (7) and (8). \[\text{PSNR}=10\ log_{10}\frac{(2^{n}-1)^{2}}{\text{MSE}} \tag{7}\]  
\[\text{MSE}=\frac{1}{mn}\ \sum_{x=0}^{m-1}\sum_{y=0}^{n-1}\left[I_{a}(x,y)-I_{e}( x,y)\right]^{2} \tag{8}\]  
The PSNR of the images reconstructed using the [PERSON] algorithm is represented in Table 8. In image processing applications involving digital images, the widely used figure of merit is PSNR. A higher PSNR is preferred as it indicates less distortion and noise in the image. PSNR values greater than 30 are usually preferred for image processing applications. The proposed architecture's accuracy was verified by comparing the reconstructed image quality with other hardware architectures [9; 25; 26]. The comparison results of the PSNR of different methods are listed in Table 8. The reconstructed images using the proposed implementation are illustrated in Figure 10, where a, c, e, and g represent the input images, and the reconstructed images are denoted by b, d, f, and h. The PSNR of the proposed design was higher by 14.61%, 5.85%, and 4.55% than the PSNR of the architectures listed in [9; 25; 26]. The Innovus tool of Cadence was used to perform place and route. Figure 11 depicts the physical layout of the proposed design that was used for the image compression. The layout comprises a single polysilicon layer (Poly1) and nine distinct metal layers (M1 to M9). Post routing, to account for constant Process-Voltage-Temperature (PVT) change, power and static timing analysis was performed. The total negative slack (TNS) obtained from the analysis was zero. \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multicolumn{5}{c}{**Technology: 90 nm**} \\ \hline
**Architecture** & **Power (mW)** & **Delay (nS)** & **Area (mm\({}^{2}\))** & **PDP (pJ)** \\ \hline CSD Met [27] & 12.21 & 22.9 & 20.40 & 287.301 \\ EF Method [27] & 12.31 & 23.53 & 21.05 & 289.654 \\ Imp. Loeffler [25] & 15.19 & 18.97 & 37.63 & 288.154 \\ Proposed & 10.48 & 21.69 & 33.05 & 227.311 \\ \hline \hline \end{tabular}
\end{table} 
Table 6: _Cont._ \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multicolumn{5}{c}{**Technology: 45 nm**} \\ \hline
**Architecture** & **Power (mW)** & **Delay (nS)** & **Area (mm\({}^{2}\))** & **PDP (pJ)** \\ \hline Loeffler [6] & 25.97 & 31.81 & 22.76 & 826.105 \\ Shen’s Method [9] & 13.51 & 28.32 & 11.73 & 382.603 \\ [PERSON] [22] & 27.18 & 35.22 & 20.63 & 957.279 \\ HEVC [26] & 11.96 & 32.86 & 23.78 & 393.005 \\ CSD Met [27] & 11.78 & 26.51 & 10.20 & 312.287 \\ EF Method [27] & 11.48 & 28.65 & 11.04 & 328.902 \\ [PERSON] [25] & 13.54 & 23.65 & 18.81 & 320.221 \\ Proposed & 9.72 & 26.48 & 17.69 & 257.38 \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Analysis of power, delay and area for different DCT/IDCT structures using 45 nm. Figure 10: Original and reconstructed images along with PSNRs using the proposed method. (**a**,**c**,**e**,**g**) Original Image. (**b**,**d**,**f**,**h**) Reconstructed images of (**a**,**c**,**e**,**g**) respectively using the proposed method.