## 2 Materials and Methods
### Digital Phase-Sensitive Demodulation Technique  
Without considering environmental interference and noise effects, the sine excitation signal output by the data acquisition system may change in amplitude and phase when passing through the measured field domain, while the frequency and waveform remain unchanged. Therefore, the basic form of the discrete signal of \(V_{m}(i)\) that represents the magnitude of voltage received by FPGA can be expressed as  
\[V_{m}(i)=A\sin(2\pi i/N+\theta) \tag{4}\]  
where \(A\) is the amplitude of the sine wave, and \(N\) represents the number of sampling points of the AD converter within one excitation signal cycle. Obviously, such a digital signal sequence requires processing to obtain the sine wave amplitude required for image reconstruction. Taking the maximum value point \(V_{max}\) in a cycle as the value of \(A\) is a simple and effective method. However, this method will result in extremely low noise immunity, and any noise that causes a change in the maximum value will have a significant impact on the results. Another method is to directly transmit the amplitude of these discrete signals to the upper computer, which utilizes its powerful data processing function for calculation. However, this requires transmitting \(N\) data per cycle, which is very detrimental to the real-time performance of the system.  
To address the above issues, digital phase-sensitive demodulation technology is adopted, which converts the discrete signal into a sine wave amplitude through multiplication accumulation and coordinate conversion in FPGA and then transmits it to the upper computer. This method has good anti-interference performance. Due to the parallel execution of instructions in FPGA and the need to transmit only one data to the upper computer, it has almost no impact on the real-time performance of the system.  
In Equation (4), \(V_{m}\) represents the voltage to be measured. Assuming \(V_{re}\) represents the real part of \(V_{m}\) and \(V_{im}\) represents the imaginary part of \(V_{m}\), they can be represented as  
\[V_{re}=\frac{2}{N}\sum_{i=0}^{N-1}V_{m}(i)\times\sin\frac{2\pi i}{N}=A\cos\theta \tag{5}\]  
\[V_{im}=\frac{2}{N}\sum_{i=0}^{N-1}V_{m}(i)\times\cos\frac{2\pi i}{N}=A\sin\theta \tag{6}\]  
Therefore, the amplitude of \(V_{m}(i)\) can be expressed as  
\[A=\sqrt{V_{re}^{2}+V_{im}^{2}} \tag{7}\]  
According to the above formula, digital phase-sensitive demodulation is achieved using the Multiply Accumulate (MAC) and Coordinate Rotation Digital Computer (CORDIC) modules in FPGA. The designed module block diagram is shown in Figure 10.  
Figure 9: Read and write state machine.  
\(V_{m}\left(n\right)\) represents the discrete voltage value to be measured after AD conversion. Two MACs are used to perform cross-correlation operations with the reference signals \(\sin(n)\) and \(\cos(n)\), respectively, to obtain the real and imaginary values. Take the output of MAC as the input of CORDIC and perform modulus calculation to obtain the amplitude of the signal to be tested. Using digital phase-sensitive demodulation technology effectively ensures the real-time performance of the system and improves the data acquisition speed.