## 1 Introduction  
The Internet of Things (IoT) has emerged as a transformative paradigm, revolutionizing how we interact with our environment. As IoT devices grow exponentially, there is increasing demand for low-power, cost-effective wireless communication solutions [1, 2]. This proliferation of interconnected smart devices necessitates innovative receiver designs that meet stringent IoT requirements while maintaining energy efficiency and compact form factors. In IoT receiver design, the low-IF (intermediate frequency) architecture has gained traction by balancing power efficiency and performance. This architecture offers advantages over traditional direct conversion (zero-IF) receivers, including improved DC offset and flicker noise performance. However, low-IF faces image rejection challenges crucial for maintaining signal integrity amid interference. To address this, complex continuous-time sigma-delta analog-to-digital converters (ADCs) provide an effective solution. These ADCs perform both analog-to-digital conversion and image rejection, simplifying receiver architecture while maintaining high performance. Their continuous-time implementation provides inherent antialasing filtering, reducing analog filtering requirements before the ADC stage. The 2.4 GHz ISM (Industrial, Scientific, and Medical) band has become popular for IoT applications due to its global availability and support for protocols like Bluetooth LowEnergy (BLE) [2] and Zigbee [3], as shown in Figure 1. These protocols suit short-range communication and offer low power consumption, making them ideal for battery-powered IoT devices. IoT receiver design faces several critical challenges. Power consumption is paramount, as IoT devices must operate long-term on battery power or energy harvesting. This demands ultra-low-power circuits and architectures that maintain performance while minimizing energy use. The evolving IoT ecosystem requires flexible receivers supporting multiple communication protocols, with adaptable modulation schemes and data rates at low power consumption. Integration presents another challenge. Single-chip solutions must incorporate complex functionalities while reducing system cost and size for space-constrained IoT devices. This necessitates innovative circuit topologies and system architectures that achieve high integration without performance compromise. The analog-to-digital converter design significantly impacts overall receiver performance [4; 5]. ADCs must handle wide dynamic ranges and maintain resolution across varied signal conditions while consuming minimal power. Continuous-time sigma-delta ADCs offer an effective balance between performance and power efficiency for these requirements [6]. This paper presents a low-power CMOS receiver for 2.4 GHz ISM band IoT applications, compatible with the BLE protocol. The design combines low-IF architecture with a complex continuous-time sigma-delta ADC for efficient image rejection and high-performance analog-to-digital conversion. Our integrated approach creates a power-efficient, compact receiver that meets modern IoT requirements. The design emphasizes minimal power consumption while maintaining BLE performance standards. The complex continuous-time sigma-delta ADC serves dual purposes: bandpass filtering for image rejection in low-IF receivers and simplified architecture for reduced power consumption and improved signal quality. The subsequent sections provide a detailed examination of the system architecture, focusing on three key aspects: First, we present the design considerations for implementing a quadrature bandpass continuous-time delta-sigma ADC optimized for BLE applications. Second, we analyze the circuit-level implementations, including the 4-bit feedback DAC, active-RC integrator, and SAR-based quantizer designs. Finally, we evaluate the system's performance through comprehensive measurements of the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), image rejection ratio (IRR), and power consumption.