## 1 Introduction  
Recently, multimedia contents have been changed to serve immersive experiences to users with evolutionary interfacing devices. Among the various types of emerging devices, virtual reality (VR) components, such as head-mounted display (HMD) devices, have been continuously developed to provide a seamless user experience with high-resolution video streams [1; 2; 3; 4]. As such, a system usually requires a huge amount of data transmissions; however, the conventional VR HMD is in general inconvenient due to the connection cables between the media host and HMDs [5], limiting the impact of VR applications. Therefore, wireless VR becomes a promising solution to provide the next-level experience by transferring at least 4 K video streams through RF circuits.  
If we directly adopt the high-speed near-field communication standards [6; 7; 8], however, it is inefficient to give the immersive user-level experience due to the long transmission latency caused by the iterative error recovery algorithms associated with complex interleaving schemes [9; 10; 11; 12]. Supporting the transmission rate of over 6 Gbps, for example, the recent WiGig standard uses a number of baseband operations including the scrambler, the FFT-based processing, the high-speed analog-to-digital conversion, and the iterative low-density parity-check (LDPC) error-correction code (ECC), requiring the transmission delay of more than 5 ms [13]. In addition, the complicated baseband steps, in general, necessitate a large amount of energy, potentially increasing the size of the battery for mobile HMD devices. Considering the practical channel condition for wireless VR applications, therefore, it is necessary to utilize only the essential baseband steps for achieving the required transmission quality, accordingly reducing the baseband latency as well as the energy consumption.  
Adding to our previous 60 GHz transceiver RF integrated circuits (RFICs) [14], in this work, we newly introduce a compact but effective baseband architecture for wireless VR applications. By observing the channel conditions of practical use cases, for the first time, we analyze erroneous patterns in wireless VR applications. To correct a massive number of consecutive errors caused by the misaligned beamforming from head-rotating motions, we design an advanced error-correction code (ECC) associated with the simple but efficient block-level interleaving scheme. As the proposed interleaver successfully scatters the burst errors into different short-length component codes (CCs), our baseband system can tolerate up to 1080 consecutive errors among 106,920 bits, which is sufficient to tolerate the practical misaligned problem. As a prototype design, integrating the proposed digital baseband architecture and the high-speed analog interfaces connecting the external devices, a fully-integrated baseband architecture for the wireless VR system is implemented in 65 nm CMOS technology. Adopting the massive-parallel structures for digital baseband processing, we can achieve a transfer rate of 12.8 Gbps while consuming only 525 mW including all the high-speed analog interfaces. As the proposed baseband processing uses non-iterative ECC with hard-decision inputs, we can also achieve the transfer latency of 1 ms, which is superior to other near-field wireless systems, leading to zero-latency wireless VR solutions.  
The rest of this paper is organized as follows. Section 2 explains the overall architecture of our wireless VR system. Section 3 presents the proposed baseband processing using the block-level interleaving with short-length component ECC codes. The implementation results are shown and compared to the other related works in Section 4. The concluding remarks are finally made in Section 5.