# SNR Enhancement of an Electrically Small Antenna Using a Non-Foster Matching Circuit
## 2 Non-Foster Circuit Design
### Non-Foster Circuit Design  
Figure 3 shows the schematic of the proposed non-Foster circuit to provide negative capacitance. Two transistors are cross-coupled to produce a 180-degree inverted phase from the input along the feedback loop [5]. The transistors used were Avago ATF-53189 [14], which are field effect transistors with wideband operation bandwidths of 50 MHz-6.5 GHz. With these basic schematics and selected transistors, the other components were optimized to satisfy the stability condition described in Section 2.3. A high frequency circuit simulator, Keysight Technologies Advanced Design System (ADS) [15], was used for the optimization. Table 1 lists the optimized values of other components. The reference impedance (Z\({}_{\text{ref}}\)) of the NFC was set to 6 pF considering the monopole's capacitance. The values of inductors (L\({}_{\text{G}}\), L\({}_{\text{D}}\), L\({}_{\text{S}}\)) and resistors (R\({}_{\text{G}}\), R\({}_{\text{D}}\), R\({}_{\text{s}}\)) connected to the gate, drain, and source of the transistors should be carefully chosen to ensure the wideband stability criterion. As the value of the inductor increases, its self-resonant frequency (SRF) decreases, adversely affecting the NFC stability [16]. The resistor values are also important since the wrong selection can lead to a generation-negative resistance that goes against the stability condition [17]. To reduce the loop gain of the transistors for stability, R\({}_{\text{Stab}}\) and C\({}_{\text{Stab}}\) are set as 51 \(\Omega\), 1 pF, respectively. The gate voltage (V\({}_{\text{GG}}\)), drain voltage (V\({}_{\text{DD}}\)), and drain current of the designed circuit are 1.8 V, 5.7 V, and 4 mA, respectively.  
Figure 2: The impedance of a short monopole antenna as a load: (**a**) resistance and (**b**) reactance.  
Figure 4 shows the simulated results of the NFC in the frequency range from 50 MHz to 500 MHz. According to the Smith chart of the reflection coefficient (S\({}_{11}\)) in Figure 4a, the locus winds in a counterclockwise manner as the frequency increases from 50 MHz to 500 MHz. This contradicts the [PERSON]'s reactance theorem, denoting that the negative capacitance has been successfully generated. Figure 4b plots the capacitance versus the frequencies. As can be seen, a negative capacitance ranging from 11 pF to 7.5 pF, and approximately 8 pF at 300 MHz, is generated.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameter** & **Value** & **Parameter** & **Value** \\ \hline \(Z_{\text{ref}}\) & 6 pF & R\({}_{\text{S}}\) & 600 \(\Omega\) \\ L\({}_{\text{G}}\) & 1 uH & R\({}_{\text{Stab}}\) & 51 \(\Omega\) \\ L\({}_{\text{D}}\) & 1 uH & C\({}_{\text{Stab}}\) & 1 pF \\ L\({}_{\text{S}}\) & 4.7 uH & C\({}_{\text{G}}\) & 510 pF \\ R\({}_{\text{G}}\) & 1.1 K\(\Omega\) & C\({}_{\text{in}}\) & 100 pF \\ R\({}_{\text{D}}\) & 1.1 K\(\Omega\) & C\({}_{\text{out}}\) & 510 pF \\ \hline \hline \end{tabular}
\end{table}
Table 1: Optimized values of passive components in Figure 3.  
Figure 4: Simulation results of the non-Foster circuit: (**a**) Smith chart of the reflection coefficient. (**b**) Negative capacitance versus frequency.  
Figure 3: A schematic of the proposed non-Foster circuit.