# Review of Ka-Band Power Amplifier
## 3 Topologies
### Cascade  
The cascode structure is the most widely used circuit structure in amplifier circuit design, and it is an improvement of the common base amplifier circuit. Its simple circuit schematic diagram is shown in Figure 8.  
The most important characteristic of the cascode structure is that it greatly increases the input impedance on the basis of maintaining the excellent frequency characteristics of the common base amplifier circuit, which is very effective for improving the small signal gain. In addition, the application of the cascode structure in PA design can increase the maximum output voltage by about 1.5 times, effectively reduce the requirements of the amplification stage for the maximum output current, reduce the size of the transistor, and improve the output efficiency. Compared with the common source structure, the input and output ports of the cascode power amplifier structure have a better isolation effect and better stability. In 2004, [PERSON] and [PERSON] presented a fully integrated 2-stage cascode power amplifier in 180 nm CMOS [48]. A shielded-substrate coplanar waveguide structure was designed in the amplifier to reduce the substrate-induced losses. Experimental results for the power amplifier demonstrate up to 14.5 dBm output power and gain of 7 dB at 24 GHz. In Ref. [49], a high linearity PA with ultra-wide video bandwidth for 5G wireless communication was proposed. With the increase in operating frequency, the output power, efficiency and linearity of Pas decrease sharply because of the sideband asymmetry of Pas caused by the memory effect [50]. Since third-order intermodulation distortion (IMD3) is generated by the mixing of fundamental wave and envelope nonlinear term, when the impedance at the envelope frequency is not zero, there is a large IMD3 on one side of the signal, resulting in an asymmetric IMD3 sideband [51]. To suppress the memory effect, an efficient low drop out (LDO) regulator is proposed. The fast load regulating LDO guarantees that the output impedance at the envelope frequency is less than 5 \(\Omega\) in \begin{table}
\begin{tabular}{c c c c c c c c} \hline
**Ref.** & **Tech** & **Frequency** & **Gain** & **Psat** & **P1 dB** & **PAEpeak** & **Area** & **Topology** \\ \hline
[45] & 180 nm CMOS & 24 & 14.5 & 14 & / & 13.2 & 0.84 & 3-stage CS \\ \hline
[46] & 65 nm CMOS & 24/28 & 9.1/8.1 & 14.7/14.4 & 13.9/13.6 & 42.6/40.1 & 0.11 & 1-stage CS \\ \hline
[47] & 90 nm CMOS & 28 & 21.3 & 17.7 & 16.7 & 23.6 & 0.49 & 3-stage CS \\ \hline \end{tabular}
\end{table} 
Table 1: Comparison of the measurement results with the CS PA.  
Figure 8: Cascade amplifier circuit schematic diagram. the frequency range up to 1 GHz. The output impedance is low enough to eliminate the envelope voltage component and suppress the memory effect. The 3-stage CS cascode PA in 65 nm CMOS achieved the gain of 22 dB, P\({}_{\text{sat}}\) of 14 dBm, the linear output power is 9.5 dBm with the IMD3 of \(-\)30 dBc and peak PAE of 21.8% at 28 GHz. The presented PA and LDO are shown in Figure 9a. The core area of PA is 0.19 mm\({}^{2}\) and LDO is 0.34 mm\({}^{2}\). In order to improve the efficiency of Pas, a dual-mode switched capacitor PA was reported [52]. The PA can operate in both high- and low-power modes by controlling the switching capacitance to modulate the output impedance. The measured results demonstrate 25.8% peak PAE at 19.9 dBm P\({}_{\text{sat}}\) in high-power mode and 22.8% peak PAE at 17 dBm P\({}_{\text{sat}}\) in low-power mode. In addition to the memory effect, the nonlinear capacitance gate-to-drain capacitances (\(C_{GD}\)) and drain-to-source capacitances (\(C_{DS}\)) of power transistors is also one of the reasons for the poor linearity of RF CMOS PA [53]. For further improving linearity, [PERSON] et al. proposed a simple but effective resistive body network, reducing the gate capacitance changes of the power transistor [54] (see Figure 9b). As a result, the presented PA, composed of 2-stage differential cascode, achieves linearity PAE of 25% at output power of 20.25 dBm at 28 GHz.