# Scalable Photonic Digital-to-Analog Converters
Cascaded asymmetric directional couplers provide intensity weighting of the input monotone optical signal to be further switched by EOMs according to the digital input signal. Unlike incoherent parallel PDACs, the technical challenge of the coherent scenario is that the phase mismatch between the paths deteriorates stable intensity summation, degrading the signal-to-noise ratio that can lead to scalability limitations. Hence, a phase shifter is deployed on each signal path to support the in-phase coherence of signals before being summed up by the Y-junction combiners. The proof-of-principle design reported in [18] in the silicon-on-insulator (SOI) platform demonstrated the switching of each signal path in a passive manner without utilizing actual EOMs and hence deployed a simulation methodology to calculate the performance metrics of the design. In addition, the fabrication sensitivity of the deployed asymmetric directional couplers and Y-junctions significantly deteriorates a desirable yield in terms of the linearity performance of the PDAC. In comparison, the authors of [19] proposed using a nested MZM configuration employing symmetric splitters/combiners for both intensity weighting and output combining. The actual chip is fabricated on a 300 mm-CMOS platform to be able to accommodate a large footprint of MZMs. Recently, the work of [20] introduced a novel architecture combining both serial and parallel schemes by employing a segmented MZM configuration in conjunction with 90\({}^{\circ}\) phase shifters specifically designed for applications in quadrature amplitude modulation (QAM) and pulse-amplitude modulation (PAM) schemes. Despite the potential conceptual advancement, the practical implementation of this architecture remains unexplored, not to mention the relatively huge footprint requirements of MZMs hindering the resolution scalability of such topology. By comparing the serial and parallel schemes, it is evident that the conversion rate of the parallel scheme is \(N\) times larger than the serial scenario at the same modulator speed and bandwidth (\(N\) being the resolution). Furthermore, it is important to note that almost all of the state-of-the-art serial and parallel incoherent PDAC topologies, unlike coherent ones,rely on photodetectors to generate the desired analog intensity, thereby limiting the scope of their application. These applications, such as photonic parallel processing, all-optical machine learning, and optical telecommunication, to name a few, necessarily require the analog signal to be in the optical domain. This is also suitable for high-speed operations as it does not involve the conversion latency of the photodiodes, and the speed is mainly determined by the modulator bandwidth. On the other hand, the inherent challenge of coherent topologies is that all modulated signals of the parallel channels must be added coherently. This can be addressed by the deployment of additional phase shifters, while not affecting the overall power efficiency when the optical path length difference is minimized by the design. In this work, we propose and experimentally demonstrate a parallel coherent PDAC architecture utilizing symmetric multimode interference couplers (MMIs) and ring resonator-based modulators. MMIs enable a balanced weighting and combining scheme that is more robust to fabrication process variation compared to state-of-the-art architectures [18; 19]. Switching each signal path by MRMs provides an ultra-compact and power-efficient solution compared to the related work based on MZMs [19]. We discuss the deployed tuning strategy to realize coherent summation functionality. The experimental testbed enabling dynamic digital-to-analog conversion with 2-bit resolution is also provided. Different from the approach in [18], this work experimentally implements the modulation functionality using MRMs. Further simulation results support the potential of this approach for realizing higher conversion rates.