# Balancing the Leakage Currents in Nanometer CMOS Logic--A Challenging Goal
## 5 Analysis Results
Such a security evaluation has been used to assess the robustness of DPA-resistant logic styles in [32]. We have conducted this type of analysis on our new logic gates and compare them to BSPL and classic logic. The result is shown in Figures 9 and 10 for all gates in both 40 nm and 65 nm technology. To compare the results, it is important to observe which mutual information curve drops at a lower amount of noise, identifying the more robust countermeasure [31; 32]. It is obvious that the iBSPL gates require the least amount of noise to hide the data dependency which indicates the highest protection against attacks. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Gate** & **Technology** & **BSPL** & **iBSPL** \\ \hline \multirow{2}{*}{NAND} & 40 nm & +162\% & +85\% \\  & 65 nm & +160\% & +60\% \\ \hline \multirow{2}{*}{NOR} & 40 nm & +87\% & +76\% \\  & 65 nm & +87\% & +66\% \\ \hline \multirow{2}{*}{XOR} & 40 nm & \(\pm\)0\% & +21\% \\  & 65 nm & \(\pm\)0\% & +85\% \\ \hline \multirow{2}{*}{NOT} & 40 nm & +100\% & +56\% \\  & 65 nm & +100\% & +31\% \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Area overhead (transistor-only) of BSPL and iBSPL logic gates compared to regular CMOS standard cells. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Family** & **Technology** & **Power (\(\mu\)W)** \\ \hline \multirow{2}{*}{Classic} & 40 nm & 2.00 \\  & 65 nm & 2.92 \\ \hline \multirow{2}{*}{BSPL} & 40 nm & 2.80 \\  & 65 nm & 3.26 \\ \hline \multirow{2}{*}{iBSPL} & 40 nm & 2.40 \\  & 65 nm & 2.96 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Average power consumption for one clock cycle. Although in the dynamic area, load capacitances dominate the current consumption and consequently information leakage, in the case of static leakage, the leakage current is dominated by subthreshold, and gate leakages, which are also a function of various parameters such as threshold voltage, oxide thickness, transistors dimensions, supply voltage [33; 34; 35]. Naturally, process variations and layout imbalances affect any equalization countermeasures. Furthermore, layout and RC-extraction through the post-layout analysis improve the accuracy of simulations [36; 37]. Ignoring such post-layout and post-production can mitigate the leakages. However, the mitigation level is undoubtedly reduced in reality (post-production), and the benefit of the countermeasure will not entirely vanish. Hence, here we just consider the impact of process variations on the ability of a worst-case (i.e., strongest possible) adversary to extract information. In this regard we have used Monte Carlo simulations to model intra-die process variations of severity levels of 1%, 3%, 5% and 10%. For every SBox circuit and every possible input value, we carried out 500 Monte Carlo simulations, performed the information theoretic analysis for a noise standard deviation \(\sigma\), and took the maximum mutual information value as the representative value for the given noise level. Although the margin between iBSPL and BSPL/Classic is clearly reduced when process variations are considered, our newly developed logic cells still provide the highest level of protection against information extraction across all levels of process variations. Table 6 compares the energy (static and dynamic) and latency overhead associated with the BSPL and iBSPL versions of the PRESENT SBox. Clearly, iBSPL does not only provide the better protection, it also comes at a lower overhead in terms of energy and latency. As a final comparison between classic logic, BSPL and iBSPL we consider static power and dynamic power analysis attacks on the synthesized SBox circuits. For that purpose, we have simulated the leakage current of each SBox circuit 5000 times for random inputs while adding Gaussian-distributed noise. In fact, we have repeated that process 500 times to model the influence of process variations corresponding to the given severity level.