## 3 HD-VLL for Hybrid DS/FH Spread Spectrum Signals
### Hd-Vll
Accumulator 1 in the jerk compensation module accumulates the filtered jerk value \(\hat{\hat{a}}\) at each system clock, and the output \(s_{1i}\) at the \(i\)th sampling point can be written as follows:  
\[s_{1i}=\sum_{i=1}^{i}\hat{\hat{a}}T_{s}=\hat{\hat{a}}\cdot iT_{s}. \tag{12}\]  
Figure 4: Structure of second-order VLL loop filter. The output of Accumulator 1 and the filtered acceleration value \(\hat{a}\) are added and sent to the acceleration compensation module. Accumulator 2 in the acceleration compensation module accumulates \(\hat{a}+\hat{\hat{a}iT_{s}}\) at each system clock, and the output \(s_{2i}\) at the \(i\)th sampling point can be written as follows:  
\[s_{2i}=\sum_{l=1}^{i}\left(\hat{a}+\hat{\hat{a}lT_{s}}\right)\cdot T_{s}=\hat{a }\cdot iT_{s}+\hat{\hat{a}T_{s}}^{2}\cdot\frac{i(i+1)}{2}\approx\hat{a}\cdot iT _{s}+\frac{1}{2}\hat{\hat{a}}\cdot(iT_{s})^{2}, \tag{13}\]  
where (13) is an approximation valid for \(\hat{\hat{a}T_{s}}\ll\hat{a}\). The output of Accumulator 2 and the filtered velocity value \(\hat{v}_{dk}\) are added together as the final output \(s_{3i}\), which can be expressed as follows:  
\[s_{3i}=\hat{v}_{dk}+\hat{a}\cdot iT_{s}+\frac{1}{2}\hat{\hat{a}}\cdot(iT_{s}) ^{2}. \tag{14}\]  
The output \(s_{3i}\) of the HD-VLL filter and the acquisition velocity \(v_{acq}\) are summed and converted to Doppler frequency according to the carrier frequency of the current frequency hopping time slot, which is accumulated by the multi-carrier NCO to produce the local instantaneous phase, and the result is given in (15). \[ \begin{array}{l}\phi_{ki}=\phi_{0k}+\frac{2\pi f_{ij}}{c}\sum_{l=1}^{i} \left(v_{acq}+\hat{v}_{dk}+\hat{a}lT_{s}+\frac{1}{2}\hat{a}l^{2}T_{s}^{2} \right)\cdot T_{s}\\ =\phi_{0k}+\frac{2\pi f_{ij}}{c}(v_{acq}+\phi_{dk})\cdot iT_{s}+\frac{\pi f_{ ij}}{c}\hat{a}\cdot(iT_{s})^{2}+\frac{\pi f_{ij}}{3c}\hat{a}\cdot(iT_{s})^{3}\\ =\phi_{0k}+\frac{2\pi f_{ij}}{c}\hat{v}_{d}\cdot iT_{s}+\frac{\pi f_{ij}}{c} \hat{a}\cdot(iT_{s})^{2}+\frac{\pi f_{ij}}{3c}\hat{a}\cdot(iT_{s})^{3},\;i=0, 1,2,\ldots,M-1.\end{array}  \tag{15}\]  
Compared to the local instantaneous phase produced by the second-order VLL in (6), which only contains the phase generated by velocity, the local instantaneous phase produced by the HD-VLL in (15) contains the phase generated by velocity, acceleration, and jerk. Hence, (15) better fits the instantaneous phase of the received signal in (8), which reduces the dynamic impact on the loop. A structure diagram of the HD-VLL is shown in Figure 5.  
As shown in Figure 5, the structure of a multi-carrier NCO is displayed in the dashed box above, where \(K_{o}\) is the gain of the multi-carrier NCO; the structure of the HD-VLL loop filter is displayed in the dashed box below, where the second-order VLL loop filter structure is shown in the gray area, the jerk compensation module is shown in the purple area, and the acceleration compensation module is shown in the red area. The workflow of the HD-VLL to generate local phase is summarized in Algorithm 1. ```
1:Input: velocity error \(v_{dis}\), sampling period \(T_{s}\), loop update interval \(T\), total number of loop update periods \(L\), total number of sampling points in a loop update period \(M\), carrier frequency of the current frequency hopping time slot \(f_{ij}\), acquisition velocity \(v_{acq}\), loop bandwidth \(B_{o}\). 2:Initialization : \(k=1,\;i=1\). 3:for\(k=1,2,\ldots,L\) do
4: Velocity error discriminator module updates the velocity error \(v_{dis}\). 5: Update \(\hat{a}\), \(\hat{a}\) and \(\hat{v}_{dk}\) by formula (10), formula (11) and formula (9). 6:for\(i=0,1,\ldots,M-1\) do
7: Update \(s_{1i}\) by formula (12). 8: Update \(s_{2i}\) by formula (13). 9: Update \(s_{3i}\) by formula (14). 10: Update \(\phi_{ki}\) by formula (15). 11:end for
12:end for
13:Output : \(\phi_{ki}\). ```  
**Algorithm 1**Workflow of HD-VLL to Generate Local Phase