## 3 Candidate Generation in Parallel Decoding of Rate-1 Nodes
### Candidate Generation Based on Partially Ordered Candidate Sets
Therefore, we evaluate the total number of considered paths \(L_{\text{out}}\) within the decoding of a Rate-1 node with \(N_{v}>S_{\text{Rate-1}}\) and the number of comparators needed for sorting the considered paths. For [20], \(L_{\text{out}}\) is calculated according to (5) with \(P=S_{\text{Rate-1}}\) according to (31). Since the decoding of a Rate-1 node proceeds serially in [20], \(P\) intermediate sorting steps are involved to reduce the number of paths from \(2L\) to \(L\). Under the assumption that the whole decoding process is unrolled for high-throughput decoders, \(P\) sorting units need to be instantiated in a Rate-1 node. Then, the number of comparators in all the \(P\) sorters is

\[P=\min(N_{v},S_{\text{Rate-1}}). \tag{31}\]3

For a fair comparison with [15], we need to adopt the threshold \(S_{\text{Rate-1}}\) to their MC set-based candidate generation scheme. For \(L\in\{2,4,8\}\), they provide details about the MC sets \(\mathcal{C}_{L}\) that represent the indices combinations to generate the candidates in parallel by flipping the corresponding bits. The cardinality of the sets \(|\mathcal{C}_{L}|\) is the number of candidates of each input path. These sets, restated in our candidate denomination, are \(\mathcal{C}_{L=2}=\{0,1,2,3\}\) with \(|\mathcal{C}_{2}|=4\), \(\mathcal{C}_{L=4}=\{0,1,2,3,4\}\) with \(|\mathcal{C}_{4}|=5\) and \(\mathcal{C}_{L=8}=\{0,1,2,3,4,5,6,8,9,7,16,32,64\}\) with \(|\mathcal{C}_{8}|=13\). Adopting \(S_{\text{Rate-1}}\) to these sets corresponds to eliminating all values that have a 1 in positions \(\geq S_{\text{Rate-1}}\) of their binary expansion. Considering \(S_{\text{Rate-1}}=1\) as an example, we obtain \(C_{S=1,L=2}=\{0,1\}\) with \(|\mathcal{C}_{1,2}|=2\). Consequently, for [15] with threshold adoption, we obtain

\[P=\min(N_{v},S_{\text{Rate-1}}). \tag{31}\]4

In the parallel implementation of this work, the number of considered paths in Rate-1 nodes in ExPOS-Fast-SSCL decoding, analog to (19) and (30), is

\[L_{\text{out,ExPOS}}=\sum_{i=0}^{L-1}\sum_{ \begin{subarray}{c}j=0\\ m_{ij}<\delta_{j}\end{subarray} }^{p-1}1. \tag{35}\]

Due to the parallel processing in [15] and in this work, only one bigger sorter is needed, whose number of comparators is

\[\binom{L_{\text{out}}}{2}, \tag{36}\]

where \(L_{\text{out}}\) is set to \(L_{\text{out,MC}}\) and \(L_{\text{out,ExPOS}}\), respectively. Table 1 presents the calculated values of the number of paths according to (5), (34) and (35), and the values of the number of comparators according to (33) and (36). For the comparison, we selected different combinations of \(L\), \(S_{\text{Rate-1}}\) and \(k_{c}\), for which the error-correction performance is close to the one of original SCL decoding as shown in Section 4.1. We observe reductions in the number of visited paths from 14.6 % to 53.1 % compared to [20] and 25.0 % to 56.3 % compared to [15] with threshold. In terms of the number of comparators, the savings range from 17.3 % to 72.6 % and 46.4 % to 81.7 %, compared to [20] and [15] with threshold, respectively. ### Implementation Results

Unrolled and fully pipelined SCL decoder Application-Specific Integrated Circuit (ASIC) implementations achieve high throughput [12]. Therefore, the depth first traversal of the PFT is implemented in an unrolled manner. Each vector function, executed by a node of the PFT, corresponds to an instantiated computational kernel. Register balancingreduces the amount of required memory in such decoders and, thus, improves area and energy efficiency. The architectures of the decoders presented in this section are automatically generated by the framework presented in [12] and implemented in a 28 nm FD-SOI CMOS technology under worst case Process, Voltage and Temperature (PVT) conditions (125 \({}^{\circ}\)C, 0.9 V for timing, 1.0 V for power). Synthesis is performed with the Synopsys Design Compiler, and Placement and Routing (PAR) is carried out with the Synopsys IC-Compiler.