# Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices
## 3 Electronic Packaging
### Vertical Integration  
Monolithic integration of photonic and electronic functionalities onto a single chip is often promoted as the ultimate goal for large-scale Si photonics [4]. However, at low-to-medium volumes (10\({}^{4}\)-10\({}^{5}\) chips per year), the vertical integration of the electronic and photonic functionalities onto two separate Si chips can bring an economic-advantage, because it allows for the mixing of different CMOS technology nodes. Specifically, the fabrication tolerances of PICs can be satisfied by the 45 nm node on relatively low-cost 200 mm wafers, while high-performance cost-effective electronic-ICs (EIC) may need the 14 nm node on 300 mm wafers. The footprint of a PIC (10-30 mm\({}^{2}\)) is usually quite large compared to a typical EIC, because of large photonic components (AWGs, delay-lines, etc.) and the space reserved for Fiber-to-PIC coupling, so not 'wasting' this space on the more expensive CMOS node can bring a significant reduction in overall cost. The vertical integration of an EIC on a PIC can be made using either solder-ball-bump (SBBs) or copper-pillar-bump (CPBs) interconnects, which provide an electrical, mechanical, and thermal interface between the two chips [46; 47]. In particular, vertical integration improves the high-speed electronic interface to the PIC, because it acts to replace long (100-500 \(\upmu\)m) possibly curved, wire-bonds with short (\(\approx\)10 \(\upmu\)m) SBB or CPB interconnects, which minimizes parasitic induction effects [48; 49; 50]--see Figure 12. In addition to high-speed, high-density electronic integration, the mechanical connection offered by SBBs and CPBs also allows for the bridging of different functional technologies, such as MEMS (micro-electro-mechanical systems), III-V, non-CMOS ASIC (application-specific integrated circuit), etc. [3]. Figure 12: Vertical integration of an electronic integrated circuit (EIC) driver-chip on top of a Si-PIC; (**a**) Image of an EIC integrated on a PIC, with RF (radio frequency) and DC (direct current) signals routed from the front-end electronics on the PCB across the surface of the PIC; (**b**) Microscope image of the EIC integrated onto the PIC using several hundred discrete copper-pillar-bumps (CPBs); (**c**) Further zoomed-in microscope image of the CPB interconnects between the EIC and PIC. Solder reflow bonding with a “no clean” flux allows for very well aligned CPB interconnects with minimal “solder squeezing”. CPBs typically have a diameter of 20-30 \(\upmu\)m, and are formed by Cu electro-plating of under-bump metal-pads on the PIC and EIC, followed by the deposition of a (lead-free) Sn-Ag-Cu solder-cap. The PIC and EIC are vertically integrated by aligning the matching pairs of CPBs on both chips using the beam-splitter camera of a flip-chip system; bringing the two chips into contact; and then applying a thermo-compression or solder-reflow cycle to fuse together the paired solder-caps. These solder-caps will be coated by a native-oxide layer that must be removed to ensure a good electrical and mechanical interconnect is formed [51]. The traditional solder-fluxes used in electronic packaging are generally not applicable in photonic packaging, because they can leave chemical residue that contaminates the optical interfaces for Fiber-to-PIC coupling. This can lead to increased insertion losses and also a weakening of the mechanical Fiber-to-PIC bond. Instead, a 'no clean' flux should be used during the solder-reflow bonding. This flux is VOC-free (volatile organic compounds) and activates and evaporates at the melting-point of the solder [52], so it does not require a post-bonding solvent-rinse that can contaminate the PIC [53; 54]. After the alignment of the EIC and PIC in a flip-chip system, and applying a 'no clean' flux solder-reflow cycle (typically 250 \({}^{\circ}\)C for 30 s), it is possible to achieve an excellent bond between the top- and bottom-side CPBs.