## 3 Proposed SQRD Algorithm with a Novel Modified RVD
### Proposed Modified RVD
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Items** & **This Study** & **[9]** & **[20]** & **[3]** & **[8]** & **[19]** \\ \hline Antennas & 4 \(\times\) 4 & 4 \(\times\) 4 & 4 \(\times\) 4 & 4 \(\times\) 4 & 4 \(\times\) 4 \\ Algorithm & GR & GR & GR & GR & GR \\ Technology & 55 nm & 65 nm & 0.18 \(\upmu\)m & 65 nm & 0.13 \(\upmu\)m & 90 nm \\ \(f_{\text{max}}\) (Hz) & 250 M & 243.9 M & 116.3 M & 550 M & 200 M & 220 M \\ Gate count & 176.5 K & 278 K & 437.5 K & 468 K & 299 K & 375.1 K \\ Processing latency (ns) & 236 & 266.5 & - & 625.5 & 685-775 & 654.5 \\ SQRD Processing cycles & 4 & 5 & 4 & 8 & 8 & 5 \\ SQRD throughput (SQRD/s) & 62.5 M & 48.8 M & 29 M & 68.75 M & 25 M & 44 M \\ SQRD NHE 1 & 0.354 & 0.207 & 0.217 & 0.177 & 0.198 & 0.192 \\ \(\mathbf{Q}^{H}\mathbf{y}\) Processing cycles & 1 & 1.25 & 4 & - & - & 5 \\ \(\mathbf{Q}^{H}\mathbf{y}\) throughput (\(\mathbf{Q}^{H}\mathbf{y}\)/s) & 250 M & 195 M & 29 M & - & - & 44 M \\ \(\mathbf{Q}^{H}\mathbf{y}\) NHE & 1.416 & 0.829 & 0.217 & - & - & 0.192 \\ MIMO data throughput 2  & 6 Gbps & 4.7 Gbps & 696 Mbps & - & - & 1 Gbps \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Implementation results and performance comparisons. Figure 13: Architecture of the modules of the iterative sorting procedure: (**a**) norm calculator; (**b**) sorting#1–3. ## 6 Conclusions

In this article, we designed an SQRD processor with reduced complexity and high throughput for MIMO detectors. An efficient SQRD algorithm based on a novel modified RVD was proposed, which could significantly reduce the computational complexity compared to the latest studies. According to the proposed algorithm, we designed the corresponding SQRD hardware architecture with CORDIC-based Givens rotation. In the hardware design, a time-sharing Givens rotation structure was adopted to take advantage of the CORDIC processor in an idle state as far as possible. In this way, hardware complexity was further decreased and hardware efficiency was improved. We also implemented the SQRD processor with SMIC 55-nm COMS technology. The implementation results show that our design surpasses other related studies in normalized hardware efficiency and achieves a MIMO data throughput of 6 Gbps, which can support current high-speed wireless MIMO systems. Conceptualization, L.S. and B.W. ; methodology, L.S. ; software, L.S. ; validation, L.S., B.W., and T.Y; writing--original draft preparation, L.S. ; writing--review and editing, L.S. and B.W. ; funding acquisition, T.Y. All authors have read and agreed to the published version of the manuscript. This research is supported by the National Science and Technology Major Project of China under Grant 2014 ZX03001011-002. The authors declare no conflict of interest. ## Appendix A

Since \(\mathbf{y}\) is normally distributed which is \(\mathbf{y}\sim\mathcal{N}\big{(}\mathbf{Hs},\delta^{2}\mathbf{I}_{NN}\big{)}\)[14], the likelihood to estimate \(\mathbf{s}\) can be given by

\[ \begin{array}{ll}p(\mathbf{y};\mathbf{s})&=\prod_{i=1}^{N}\big{(}\sqrt{2\pi }\sigma\big{)}^{-1}\exp\!\left(-(\mathbf{y}_{i}-\mathbf{H}_{i;}\mathbf{s})^{ 2}/2\sigma^{2}\right)\\ &=\left(\prod_{i=1}^{N}\!\left(\sqrt{2\pi}\sigma\right)^{-1}\right)\cdot\exp \!\left(-\!\sum\limits_{i=1}^{N}\left(\mathbf{y}_{i}-\mathbf{H}_{i;}\mathbf{s} \right)^{2}/2\sigma^{2}\right)\\ &=\left(\prod_{i=1}^{N}\!\left(\sqrt{2\pi}\sigma\right)^{-1}\right)\cdot\exp \!\left(-\|\mathbf{y}-\mathbf{H}\mathbf{s}\|^{2}/2\sigma^{2}\right)\end{array}  \tag{1}\]

Note that to maximize likelihood, \(p(\mathbf{y};\mathbf{s})\) is equivalent to minimize \(\|\mathbf{y}-\mathbf{H}\mathbf{s}\|^{2}\). Therefore, the ML solution of \(\mathbf{s}\) is given by \(\overset{\mathbf{s}}{\mathbf{s}}_{ML}=\underset{\mathbf{s}\in\Omega}{\mathrm{ argmin}}\|\mathbf{y}-\mathbf{H}\mathbf{s}\|^{2}\). ## Appendix B

The number of CORDIC operations needed in SCGR is the summation of the CORDIC operations needed in every column elimination process.