## 6 Applications of Chaos to Encryption
### Applications of Chaos in the Hardware Implementation of Encryption Systems  
Different technologies have been recently exploited for implementing cryptographic systems in hardware. For example, in [18], at first, a novel hyperchaotic map has been presented by taking a one-dimensional infinite collapse model as seed. Successively, since the conceived map highlights a wide hyperchaotic range, high sensitivity, good ergodicity and extreme complexity performance, a secure communication system has been designed and implemented in hardware [18]. The input message (that can be an image, a text, or a sound) is processed via a delta modulator and then encrypted by exploiting the conceived hyperchaotic map. At the receiver side, the map and a delta demodulator are employed to retrieve the original message. Experimental measurements have shown both efficiency and simplicity of the secure communication system when the information signal is transmitted over an optical channel [18].  
In [19], a very simple chaotic system showing both odd and even symmetries is presented, along with an experimental set-up based on FPGA platforms. In particular, a chaos-based speech encryption scheme is designed and implemented on an FPGA using Verilog HDL [19]. The security of the encryption scheme is assessed, with the aim to show the effectiveness of the conceived approach [19]. Moreover, by virtue of good use of the hardware resources, the encrypted scheme is able to guarantee a throughput of 1.3 Gbit/sec via a Xilinx Kintex 7.  
In [20], the FPGA implementation of a sound encryption system based on a fractional-order chaotic system is illustrated. A number of techniques are exploited to enhance the throughput as well as to reduce the hardware utilization. Security analysis techniques (including basic statistical aspects, the NIST tests, mean square error and key sensitivity) are carried out to highlight the robustness of the conceived approach [20].  
In [21], a novel stream cipher based on a chaotic skew tent map is illustrated and realized in a 0.18 \(\upmu\)m CMOS technology. The conceived ciphering algorithm exploits a linear feedback shift register, which modifies the chaotic trajectories produced by the skew tent map dynamics. This enables the randomness of the generated sequences to be improved [21]. The implemented stream cipher is able to achieve encryption speeds of 1 Gbps with power consumption as low as 24.1 mW. A security analysis of the cipher is carefully carried out [21]. In particular, the generated keystreams are analysed via NIST randomness tests, showing that they are undistinguishable from truly random sequences. Key sensitivity and key space size are analysed, with the aim to highlight the security of the conceived cipher [21].  
In [22], a chaotic system without equilibrium points (i.e., with hidden attractors) is at first introduced and implemented in a real electronic circuit. Then, S-boxes are realized and employed in a new image encryption algorithm [22]. In particular, some S-boxes with good cryptographic properties are exploited for sub-byte operations. The performances of both S-boxes and encryption procedures are analysed to highlight the capabilities of the method [22].  
By virtue of their complex dynamic behaviours, chaotic systems with coexisting attractors [23; 24; 25] represent an interesting topic in view of their practical application to encryption. For example, in [26] an extended Lu system with coexisting attractors is at first introduced, along with analyses of bifurcation diagrams and phase portraits. Then, a hardware implementation of the conceived system is illustrated, along with an efficient chaotic image encryption algorithm [26].