# Electromagnetic Analysis of Vertical Resistive Memory with a Sub-nm Thick Electrode
## 3 Results and Discussion  
Figure 1a,b shows the schematic of the fabricated VRRAM with conventional metal (Pt) and graphene plane electrodes. The active memory layer is sandwiched between the pillar and edge plane electrodes, satisfying the vertical structure. It should be noted that specified layouts demonstrate the structure of the single cell of the vertical resistive switching memory with built-in metal contacts for electrical characterization. The probes contacting metal pads and pillar electrodes in both devices are configured to perform SET programming operations. Figure 1: The structure of the single device RRAM in 3D vertical architecture. (**a,b**) The schematic of the VRRAM with conventional metal (Pt) and 2D graphene edge electrodes, respectively. The probes are configured for SET programming operations; (**c**) high-resolution TEM image of the cross-sectional view of the graphene-based VRRAM (Scale bar: 10 nm); (**d**) current response of the sole monolayer graphene sheet with no active memory layer; (**e,f**) microscopic image (top view) of the Pt- and graphene-based VRAMs (Scale bar: 20 \(\upmu\)m). The thickness of the Pt electrode of the control device is 5 nm, whereas the graphene monolayer is known to be 3 A thin [20; 23; 24]. For reference, in this study, the pillar (TiN) and plane (Pt or graphene) electrodes are presented as top and bottom electrodes, unless otherwise stated. Figure 1c depicts a high-resolution TEM image of the cross-sectional view of the VRRAM with the graphene electrode. Here, a graphene sheet was accurately transferred on top of the adhesion layer (see Materials and Methods section). Moreover, given the proper etching aspect ratio that is practiced by the industries, the resulted trench is expected to be principally abrupt. It is known that graphene has exclusive thermal and electrical properties suitable for electronic applications [25]. Therefore, the current response of the memory-free VRRAM is as shown in Figure 1d, indicating the expedient conductivity of the graphene material, including specific semi-metal/metal contact. Microscopic images of the fabricated VRRAMs with metal (control sample) and graphene electrodes are shown in Figure 1e,f. The experimentally obtained _I-V_ response of multiple cycles of the VRRAM with Pt and graphene electrodes are depicted in Figure 2a,b. Blue represents the SET operation region, i.e., transition from high (HRS) to low (LRS) resistance states, whereas gray reflects the RESET region, switching from LRS to HRS. It is important to note that programming voltages is substantially smaller in the graphene-based VRRAM (V\({}_{\text{SET}}\) = \(-\)0.2 V; V\({}_{\text{RESET}}\) = 0.2 V) when compared to the memory with the Pt electrode (V\({}_{\text{SET}}\) = 1.4 V; V\({}_{\text{RESET}}\) = \(-\)2.3 V), providing ultra-low power switching. In addition, resistive switching occurs in different polarities of the voltage sweep. This implies that in conventional VRRAMs, the SET is obtained by biasing the pillar electrode with positive amplitude voltage and grounding the metal plane electrode (Figure 1a). In contrast, for the graphene-based VRRAM, one can expect the SET by applying a positive voltage on the graphene plane and grounding pillar electrodes. Furthermore, the switching current for the conventional metal-based VRRAM is 30 \(\upmu\)A for SET and 100 \(\upmu\)A (self-compliance) for RESET. Integrating the graphene as a plane electrode will provide 5 \(\upmu\)A for both programming configurations. Initially, the current compliance of 5 \(\upmu\)A, similar to the one utilized in the programming operations in graphene-based memory, was used during the forming process. In the case of the VRRAM with a metal electrode, the impact of the current compliance levels, including 30 \(\upmu\)A used during the experimental forming/measurements, on the resistance distribution will be discussed later in this study.