## 2 Related Work
The block diagram of the modified Booth-based modulo 65 (\(2^{n}+1\)) multiplier [2], with \(n\) set to 8 is shown in Figure 3. Here, the Booth encoder, Booth selector, half adder, and full adder in the hardware structure are abbreviated as BE, BS, HA, and FA, respectively. In this work [2], the multiplicand \(A\) and multiplier \(B\) are expressed in binary as \(A=a_{n}\,a_{n-1}\,a_{n-2}\ldots a_{0}\) and \(\rm{B}=b_{n}\,b_{n-1}\,b_{n-2}\ldots\,b_{0}\). The final result Q [2] can be expressed as Equation (3):  
\[Q=\left|\sum_{i=0}^{\frac{n}{2}-1}\left|(A_{n-1:0}+1)2^{2i}b_{i}^{MB}\right|_{ 2^{n}+1}-a_{n}B-B\right|_{2^{n}+1} \tag{3}\]  
Figure 2: (**a**) Hardware structure of the modulo (\(2^{8}-1\)) (63, \(n=8\)) multiplier [1]. (**b**) Circuit of the Booth encoder [1] and (**c**) Circuit of the Booth selector [1]. \[\text{where }b_{i}^{MB}=b_{2i-1}+b_{2i}+b_{2i+1}\text{, }\left|(A_{n-1:0}+1)2^{2i}b_{i}^{MB} \right|_{2^{n}+1}=PP_{i}+1+z_{2i}2^{2i}.\]  
According to Equation (3), the BE and BS are shown in Figure 4a,b. Equation (3) can be deduced and calculated according to [2] and, finally, Equations (4) and (5) can be obtained:  
\[Q=\left|C+S+1\right|_{2^{n}+1} \tag{4}\]  
\[\left|C+S\right|_{2^{n}+1}=\left|\sum_{i=0}^{\frac{n}{2}-1}pp_{i}+{pp_{1}}^{*} +{Z_{n}}^{*}+\overline{B_{L}}+\frac{n}{2}\right|_{2^{n}+1} \tag{5}\]  
In these equations, \(C\) is carry, \(S\) is sum, \({Z_{n}}^{*}\) and \(\vec{B_{L}}\) are the compensation values of the weighting circuit used to obtain accurate output values, and \(pp_{1}\)* is taken by the inverter of \(pp_{i,0-2i-1}\) (for \(i>0\)). Finally, Equations (4) and (5) are summed using the inverted end-around-carry (IEAC) carry-save adder (CSA) tree to obtain the final output value Q. From the above descriptions of the modified Booth-encoding modulo (\(2^{n}-1\)) multiplier and modulo (\(2^{n}+1\)) multiplexer, it is clear that the two architectures have many similar circuits. The similar parts of the two architectures can be leveraged as a basis for common use. A certain method can be used to distinguish the different operations so that a circuit with a slightly larger hardware can be used to complete the two kinds of modulus operations. [PERSON] and [PERSON] [8] also adopted the modified Booth-coded 1 complement  
\[B=\sum_{i=0}^{n-1}2^{2i}(b_{2i-1}+b_{2i}-2b_{2i+1}) \tag{1}\]0 Hardware structure of the modulo (\(2^{8}+1\)) (\(65\), \(n=8\)) multiplier [2]. modulo (\(2^{n}-1\)) multiplier [1] and modified Booth-encoding-based modulo (\(2^{n}+1\)) multiplier [18] and combined them into the multifunction modulo (\(2^{n}\pm 1\)) multiplier using the same hardware. However, their hardware structure still has room for improvement in terms of power consumption, delay time, hardware area, and operation range. The architecture of the radix-4 Booth-encoding-based multifunction modulo (\(2^{n}\pm 1\)) multiplier proposed in this paper can achieve significant improvements in power consumption, latency, and hardware area. Moreover, the structure of the proposed low-power, area-saving, and fast modulo (\(2^{n}\pm 1\)) multiplier can operate the modulo (\(2^{n}+1\)) and modulo (\(2^{n}-1\)) multipliers with only one control signal sharing the same hardware structure. Meanwhile, the operation ranges of the multiplicand and multiplier of the proposed modulo (\(2^{n}+1\)) and modulo (\(2^{n}-1\)) multipliers are [0, \(2^{n}+1\)) and [0, \(2^{n}\)], respectively. These ranges are wider than those of the hardware structure reported by [PERSON] and [PERSON] [8]. The system architecture of the proposed FPGA implementation of multifunction modulo (\(2^{n}\pm 1\)) multiplier based on radix-4 Booth encoding will be presented in the following section.