## 3 Results  
There are four transistors presented in this study, including two FinFET W120L160 and W120L2000 transistors (Manufactured in National Chip Implementation Center, Hsinchu city, Taiwan, fin width = 120 nm, channel length = 160 nm, 2000 nm), and two planar MOSFET L180 nm and L90 nm transistors (TSMC, Hsinchu city, Taiwan, channel length = 180 nm, 90 nm). According to the algorithm as described in Section 2.3, the measured data were deliberately fitted with a conventional model formula with a significant modification like that shown in Equations (1) and (2). Parameters at various Gate biases were then determined for fitting the as-measured characteristic curves and these are listed in Tables 1-4. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Gate Bias** & \(\mathbf{k_{N}}\) **(A/V\({}^{2}\))** & **Vth (V)** & \(\boldsymbol{\lambda}\) & \(\boldsymbol{\alpha(A)}\) & \(\boldsymbol{\beta(V^{-2})}\) & \(\boldsymbol{\chi(V)}\) \\ \hline \(\mathrm{V_{GS}}\) = 0.80 V & \(5.000\times 10^{-4}\) & 0.3772 & 0.0280 & \(2.40\times 10^{-6}\) & 16.0 & 0.40 \\ \hline \(\mathrm{V_{GS}}\) = 1.00 V & \(4.530\times 10^{-4}\) & 0.3980 & 0.0220 & \(3.22\times 10^{-6}\) & 11.0 & 0.56 \\ \hline \(\mathrm{V_{GS}}\) = 1.20 V & \(3.950\times 10^{-4}\) & 0.3905 & 0.0184 & \(3.90\times 10^{-6}\) & 11.0 & 0.74 \\ \hline \(\mathrm{V_{GS}}\) = 1.50 V & \(3.150\times 10^{-4}\) & 0.3215 & 0.0155 & \(5.13\times 10^{-6}\) & 6.0 & 1.04 \\ \hline \(\mathrm{V_{GS}}\) = 1.80 V & \(2.400\times 10^{-4}\) & 0.1345 & 0.0140 & \(6.53\times 10^{-6}\) & 4.0 & 1.40 \\ \hline \(\mathrm{V_{GS}}\) = 2.00 V & \(2.000\times 10^{-4}\) & \(-0.0630\) & 0.0145 & \(8.76\times 10^{-6}\) & 1.4 & 1.60 \\ \hline \(\mathrm{V_{GS}}\) = 2.20 V & \(1.680\times 10^{-4}\) & \(-0.1700\) & 0.0270 & \(1.20\times 10^{-5}\) & 1.4 & 1.78 \\ \hline \end{tabular}
\end{table} 
Table 4: Determined parameters of MOSFET L90 (length = 90 nm). \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Gate Bias** & \(\mathbf{k_{N}}\) **(A/V\({}^{2}\))** & **Vth (V)** & \(\boldsymbol{\lambda}\) & \(\boldsymbol{\alpha(A)}\) & \(\boldsymbol{\beta(V^{-2})}\) & \(\boldsymbol{\chi(V)}\) \\ \hline \(\mathrm{V_{GS}}\) = 0.25 V & \(1.71\times 10^{-4}\) & \(-0.140\) & 0.105 & \(4.60\times 10^{-7}\) & 105.0 & 0.34 \\ \hline \(\mathrm{V_{GS}}\) = 0.50 V & \(1.66\times 10^{-4}\) & \(-0.165\) & 0.080 & \(1.40\times 10^{-6}\) & 7.0 & 0.36 \\ \hline \(\mathrm{V_{GS}}\) = 0.75 V & \(1.46\times 10^{-4}\) & \(-0.132\) & 0.163 & \(1.88\times 10^{-6}\) & 16.0 & 0.25 \\ \hline \(\mathrm{V_{GS}}\) = 1.00 V & \(1.29\times 10^{-4}\) & \(-0.101\) & 0.154 & \(2.24\times 10^{-6}\) & 19.0 & 0.29 \\ \hline \end{tabular}
\end{table} 
Table 1: Determined parameters of FinFET W120L160 (fin Width = 120 nm, Length = 160 nm), where \(\delta\) = \(2.58\times 10^{-7}\) A with kink modification and \(\delta\) = \(1.17\times 10^{-6}\) A without kink modification at V\({}_{\mathrm{GS}}\) = 1.00 V.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Gate Bias** & \(\mathbf{k_{N}}\) **(A/V\({}^{2}\))** & **Vth (V)** & \(\boldsymbol{\lambda}\) & \(\boldsymbol{\alpha(A)}\) & \(\boldsymbol{\beta(V^{-2})}\) & \(\boldsymbol{\chi(V)}\) \\ \hline \(\mathrm{V_{GS}}\) = 0.80 V & \(0.228\) & \(0.556\) & \(0.170\) & \(7.78\times 10^{-4}\) & 46.0 & 0.22 \\ \hline \(\mathrm{V_{GS}}\) = 1.00 V & \(0.240\) & \(0.654\) & \(0.120\)while only monopoles are found in planar MOSFET, as shown in Figures 3b and 4b. Kinks were set to the peak coordinates (\(\chi\), \(\alpha\))\({}_{\text{peak}}\), where \(\chi\) is the V\({}_{\text{DS}}\) value of the peak (such as in Figure 3b) or somewhere between the twin peaks (such as in Figure 2b). The parameters (\(\chi\), \(\alpha\)) were determined by observing the peaks. The beta (\(\beta\)) was varied to find the minimum \(\delta\) deviation depending on the peak width and this resulted in (c), (d), and (e) in Figures 1-4. Actually, carriers received thermal agitations from the kinks, which may cause lower I\({}_{\text{DS}}\) current flow.