# Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL
## 6 Experimental Results
### Roofline Performance Model  
To evaluate the achieved performance, the roofline model [17] can be used. This model relates the operational intensity to the achieved performance. In the guided image filter, the operational intensity, however, depends on the value of _radius_. A larger _radius_ results in more operations to be performed for an equal amount of data that is read, and therefore a higher operational intensity. The number of operations per pixel is given by \(ops_{px}(r)=3(32r^{2}+32r+22)\), e.g., \(ops_{px}(3)=1218\) and \(ops_{px}(6)=4098\). The maximum radius for a floating-point implementation of the guided image filter algorithm is \(r=3\). For higher values, the synthesized hardware does not fit in the FPGA anymore. Therefore, a fixed-point implementation was used, which could go up to a radius \begin{table}
\begin{tabular}{c c} \hline \hline
**Memory Operation** & **OpenCL Cache Hit Rate** \\ \hline Filtering input & 81.5 \% \\ Guidance Input & 95.4 \% \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Cache hit rates in the OpenCL generated cache. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Profile** & **Execution Time** & **GOPS** & **Frames/s** \\ \hline SVM & 22.06 ms & 114 & 45 \\ Memory Buffer & 32.72 ms & 77 & 30 \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Execution times of the guided filter on HARP with and without shared virtual memory. \(r=6\). Both the floating-point and fixed-point implementations of the guided image filter were executed for the possible values for radius. This results in the measured performance depicted in Figure 9. In this figure, the performance of the kernels for the different operational intensities is shown. The fixed-point kernel performance is indicated by the blue dots, while the floating-point kernel performance measurements are shown in red. Moreover, the roofline model of the HARP platform is shown as well. As peak-memory bandwidth, the bandwidth of 16 GB/s is used. The peak floating-point performance of the Arria 10 FPGA equals 1366 GFLOPS. This should be interpreted in the following way. The Arria 10 FPGA consists of 1518 DSPs. Each of these DSPs can perform 2 FLOP/clock cycle, which results in 3036 FLOP/clock cycle for all DSPs. At a rate of 450 MHz, this results in 3036 FLOP/clock cycle \(\times\) 450 MHz = 1366 GFLOPS [18]. Please note that for the fixed-point kernel, the performance should be expressed in OPerations per Second (OPS), instead of FLOPS. As can be seen in Figure 9, the implementation definitely benefits from using the fixed-point implementation. While the maximum achievable performance of the floating-point kernel is 135 GFLOPS, the fixed-point kernel achieves a top performance of 430 GOPS. For radii that both the floating-point and the fixed-point kernel can implement, on the other hand, no significant difference in performance can be observed. In this case, using the floating-point implementation is advantageous due to the specific issues of the fixed-point implementation, such as under- and overflow. Furthermore, it can be seen in Figure 9 that for larger operational intensities, a higher performance is obtained. Therefore, the larger computational demands do not hamper the performance and the kernel is only limited by the achieved bandwidth. It can, however, be seen that the maximum performance of the floating-point kernel, 135 GFLOPS, is smaller than the compute limit of 1366 GFLOPS. This can be explained as follows. The number of floating-point operations for radius 3 is 1218 per cycle. The clock frequency for the design is 237.5 MHz. The occupancy of the requested bandwidth is 48.6%. This gives a performance estimation of \(1218\times 237.5\times 10^{6}\times 0.486\) operations per second or 140.6 GFLOPS, which is 4% above the measured value. Up until this point, one pixel, consisting of three different color channels, was processed in parallel. It is, however, possible to process two or four pixels simultaneously, resulting in either six or 12 parallel calculations.