## 4 Implementation of the Proposed Solution  
There are in the market several platforms for implementing embedded systems [21]. In our case, two different platforms have been used and compared, namely Nutaq (SFF-SDR) and Altera (Stratix II EP2S180). The two platforms integrate FPGAs of Xilinx and Altera, respectively. We used an FPGA instead of a DSP for the benefits it offers. Indeed, an FPGA allows a higher frequency, supporting higher bit rates and providing real-time processing.  
The training process of time and frequency-domain NN is done in an offline way; therefore, only their layers will be implemented on an FPGA circuit (without the learning algorithm). Figures 8 and 9 illustrate the architecture of a NN as well as the activation function implemented during our development, respectively.  
It is worth noting that the real and imaginary parts of the signal are separately processed; thus, this architecture will be duplicated in the case of the time-domain solution and multiplied by the number of constellation areas treated in the case of the frequency-domain solution.  
We first test the implementation of our proposed solution on OFDM signals with different numbers of subcarriers for QPSK and 16-QAM modulations. In order to represent each OFDM sample, we adopted signed fixed-point representation that provides a compromise between the traditional and the floating-point representations. Indeed, it allows higher computational speeds and minimal resource consumption. Following a statistical study carried out on the proposed NN regarding the minimum and maximum values of signals, we found that each sample can be represented with 16 bits: a sign bit, five bits for the integer part and finally 10 for the fractional part. In contrast to the time-domain NN, the frequency-domain NN does not allow the reduction of the power fluctuations present in an OFDM signal; on the other hand, it retains the triangular shape of the modulation constellation imposed by the ACE-AGP algorithm. Recall that, in the case of QPSK modulation, the number of frequency-domain NN is two, whereas, for a 16-QAM modulation, this number is six. Figure 10 illustrates the implementation of the frequency-domain NN for 16-QAM modulation.  
The implemented architecture in the case of 16-QAM is subdivided into three different stages as shown in Figure 10. The first stage allows for determining the belonging of a point to a quadrant of the constellation and adapting it to frequency-domain NN. The second stage consists of three blocks, each one grouping two NNs allowing a different treatment of the real and imaginary parts to ensure a proper expansion. The last stage allows for recovering the original position of the constellation point. In case of QPSK modulation, the same stages will be used, with the difference that the second one will contain one block instead of three.  
For comparing the achieved performance with that obtained by simulation, we choose a JTAG (joint test action group) hardware co-simulation [22]. This feature allows for simulating the whole or part of a design implemented directly on an FPGA platform. This approach also makes it possible to accelerate the simulation of a complex design and to verify its correct functioning in the hardware. The reason behind the use of a hardware co-simulation is to minimize the development time while avoiding implementing the entire OFDM transmission and reception system on an FPGA platform. In fact, only the proposed NN will be implemented on a hardware platform while the rest will be emulated by software. At each clock cycle, the software sends a data frame to the hardware for  
Figure 10: Implemented frequency-domain NN using a Xilinx system generator.  
processing. The communication between the software and the hardware is carried out either by a JTAG or Ethernet cable for more speed (Figure 11).