## 2 Related Work
The percent of packet loss was reported to be about 2.5% in the worst-case scenario. [PERSON] and [PERSON], in 2023, proposed a hybrid hardware/software firewall based on an FPGA for the mitigation of distributed denial of service (DDoS) attacks [34]. The system was implemented on a NetFPGA SUME development board that features a Xilinx Virtex-7 690T FPGA, four 10 Gb/s SFP+ interfaces, static and dynamic RAM and other peripherals. The packet processing is implemented in hardware with the FPGA programmable logic and the packet data are forwarded to a software filter after some metadata have been appended. The results showed how the proposed architecture that distributes the workload between hardware and software components can achieve a very good performance and is effective in the mitigation of DDoS attacks. A more advanced type of firewall is the one referred to as a stateful firewall, which checks the network packets, tracking the state of connections based on knowledge of the protocols used in the network connection. [PERSON] et al., in 2016, proposed Open Packet Processor, a programmable architecture for platform-independent stateful in-network processing [35]. The system was implemented on the development board NetFPGA SUME, with a clock of 156.25 MHz and a 64-bit data path from the Ethernet ports, corresponding to a 10 Gb/s data throughput for each port. The authors reported a data throughput between \(10^{7}\) and \(8\cdot 10^{7}\) packets/s. [PERSON] et al., in 2019, presented FlowBlaze, a firewall based on Extended Finite State Machines (EFSMs) that can support a wide range of complex network functions and can make stateful packet inspection [36]. The proposed device was implemented on the NetFPGA SUME SmartNIC, an x8 Gen3 PCIe adapter card containing a Xilinx Virtex-7 690T FPGA and four SFP+ transceivers providing four 10 Gb/s Ethernet links. Experimental measurements of the FlowBlaze performance showed that the device is characterized by a latency of a few microseconds and a maximum data throughput of \(14.88\cdot 10^{6}\) packets/s in the case of packet sizes of 64 bytes, but the authors state that, in principle, a maximum data throughput of 40 Gb/s is possible. Research activities were recently carried out on the exploitation of machine-learning algorithms to detect potential security threats in network communication. [PERSON] et al., in 2017, designed a heterogeneous anomaly-based intrusion detection system (HA-IDS) which is built on an FPGA and a Graphics Processing Unit (GPU) [37]. The system uses the FPGA (Xilinx Virtex-5 XC5 VTX240T) to collect the network data and extract the packets' information, while the GPU (Gigabyte GeForce GTX 1080) is used to implement a back-propagation neural network to detect anomalies in the network data. Experimental results from studies carried out on a 2 GB dataset (consisting of regular packets as well as DDoS attack packets) show that the system can achieve an accuracy of 80.42% with a data throughput of 200 Mb/s. [PERSON] et al., in 2021, presented an intrusion detection system on an FPGA based on deep learning [38]. The system was implemented on a PYNQ-Z2 development board with a Xilinx ZYNQ XCZ020-1 CLG400C FPGA on board and achieved an accuracy of 99.41% with a data throughput of 90 Mb/s. [PERSON] and [PERSON], in 2021, proposed a binary neural network (BNN) on an FPGA to design an intrusion detection system [39]. Different single hidden layer BNNs were implemented on a Xilinx Kintex Ultrascale+ FPGA (XCKU3P) and trained with two different datasets (NSL-KDD and UNSW-NB15). The results showed that the designed system can achieve an accuracy between 77.77% and 98.96%, it is very efficient in resource usage (8606 to 17,990 lookup tables) and features a very low classification latency (from 16 ns to 19 ns). A different type of firewall deals with the security of bus transactions of microprocessors-based embedded systems from potential attackers.