## 6 Experimental Results  
The proposed receiver was fabricated in a 28 nm CMOS process, as shown in Figure 14. The chip layout features an RF front-end area of 0.375 mm\({}^{2}\) and a QBP-CT\(\Sigma\)AM ADC area of 0.145 mm\({}^{2}\). In BLE-mode operation, the receiver achieves a sensitivity of \(-95\) dBm at a \(10^{3}\)-bit error rate while consuming 4.08 mW from a 1.0 V supply. Figure 14 shows the layout view of the QBP-CT\(\Sigma\)AM ADC that draws 0.81 mW including power consumption from the bias circuit for current distribution to active blocks, input/output drivers, and clock distribution circuitry. SNR measurements were conducted using a peak low-IF signal at 1.5 MHz with a 100 Hz resolution, as illustrated in Figure 15. The feedforward architecture results in minimal harmonic distortion at the output. The design achieves a peak SFDR of 79.8 dBc, with an impressive image rejection ratio of 54.2 dBc during measurements. Figure 14: (a) Chip microphotograph and (b) layout view of QBP-CT\(\Sigma\)AM ADC. Figure 13: Flow charts of (a) SAR-based quantizer and (b) SAR logic. The measured SNDR and SNR across different input signal levels are plotted in Figure 16. The ADC demonstrates peak performance with an SNDR of 67.5 dB at \(-2\) dB relative to full scale (dBFS) and a peak SNR of 68.9 dB at \(-1\) dBFS. For reference, the full-scale signal (0 dBFS) corresponds to a differential peak-to-peak voltage (V\({}_{\text{P-P}}\)) of 1 V. The ADC achieves a dynamic range of 70.3 dB across its 2 MHz signal BW. Figure 17 shows the performance stability of the ADC's SNDR under varying operating conditions. The voltage variation demonstrates that the SNDR responds to supply voltage changes from \(-10\%\) to \(+10\%\). Without RC calibration, the SNDR significantly degrades by \(-16\) dBc at \(10\%\) voltage variation. With calibration enabled, the variation is contained within \(\pm 2\) dBc. The temperature variation shows SNDR performance from 0 \({}^{\circ}\)C to 100 \({}^{\circ}\)C. The uncalibrated system's SNDR degrades by \(-8\) dBc at 100 \({}^{\circ}\)C, while the calibrated system maintains performance within \(\pm 2\) dBc across the temperature range. These results validate the effectiveness of the RC calibration scheme in maintaining stable ADC performance across both voltage and temperature variations, which is essential for reliable operation in IoT applications. Figure 16: Measured SNR and SNDR for various input voltages. Figure 15: Output spectrum of the RX output with a low-IF signal at 1.5 MHz. Intermodulation testing was performed to characterize the QBP-CT\(\Sigma\)AM ADC's linearity. When presented with two strong input signals at \(-15\) dBFS at frequencies of 1.3 GHz and 1.7 GHz, the resultant intermodulation products measure 58.7 dBc below the fundamental tones, as shown in Figure 18.  
Table 1 presents a performance comparison between the proposed receiver and previously reported IoT receivers with \(\Sigma\)AM [35; 36; 37; 38; 39; 40; 41]. Our design implements a low-IF architecture for BLE standards with an intermediate frequency (IF) of 1.5 MHz. The CT-Q\(\Sigma\)AM ADC achieves an effective number of bits (ENOB) of 10.9, operates at a sampling frequency of 32 MHz, and provides a BW of 2 MHz. To enable fair comparison, we evaluate the ADC performance using two established figures of merit: \(\text{FOM}_{\text{S}}\)[42] and \(\text{FOM}_{\text{W}}\)[43]. The \(\text{FOM}_{\text{S}}\) metric emphasizes resolution and dynamic range improvements, with higher values indicating better performance. Conversely, \(\text{FOM}_{\text{W}}\) focuses on energy efficiency, where lower values represent better performance. The proposed CT-QBP \(\Delta\Sigma\)M ADC achieves an \(\text{FOM}_{\text{S}}\) of 164.3 dB. While this figure is lower than some IoT sensor applications [35; 36; 40; 41], due to our higher intermediate frequencies, our design demonstrates superior energy efficiency with the best \(\text{FOM}_{\text{W}}\) among state-of-the-art implementations [35; 36; 37; 38; 39; 40; 41].