# FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs
## 5 Performance Efficiency of FPGA-QNN
The information derived from this analysis provides a foundation for developing strategies aimed at improving the efficient utilization of resources in FPGA hardware design processes. The final part of the performance evaluation includes the power consumption of all models in both simulation and practice. The power analysis of the designed accelerators was conducted using the power estimation tool in the Xilinx Vivado 2021.2 software. Figure 18 presents the power consumption of the models from practical measurements and Vivado tool. The power consumption of accelerators is divided into two groups, dynamic and static, according to the type of consumption, and dynamic consumption is further partitioned into five components. The first four of these components represent the resources consumed by the accelerator: clock, signals, logic elements, and memory units. The last one is the power consumed by the operating system. Static consumption remained at a low level of 0.138-0.189 W in all three accelerators. In dynamic power consumption, approximately 82% of the total power consumption is consumed by the operating system that controls the Pynq Z1 card. Analyses based on different quantization levels show that increasing the quantization level results in enhanced total power consumption. The W2A2 model with the highest power expenditure consumes 2.85 W, which can be treated as a very small value in comparison to hardware such as CPU or GPU. It can be noted that the actual power consumption is 0.5 W higher than Vivado estimates due to the limited calculation of Vivado with FPGA and the operating system. However, the PYNQ Z1 card has extra input and output hardware components other in addition to FPGA. The performance comparisons of resource utilization in FPGA-QNN over a set of state-of-the-art accelerators were carried out and are presented in Table 6 for the FashionMNIST dataset. The main rationale behind the selection of the comparing schemes was to make a fair comparison, as these schemes are built on the same DL model and dataset. The experimental results verified the MNIST dataset as easily learnable, which makes MLP feasible. Comparisons for the FashionMNIST dataset required models with convolution layers for better operation. The best performance in terms of FPS criterion was attained at the W1A1 quantization level and the H-folding level for the MLP delivering 723 KFPS  
Figure 17: FPGA source consumption by model, precision, and folding. and the LeNet reaching 6.9 KFPS. In the original work on FINN, an LFC model with three full-connection layers was developed and the classification of the MNIST dataset was accomplished with a 1-bit quantization model. The proposed model operates with a clock frequency of 200 MHz and consumes 22.6 W energy. Our MLP model, consisting of two full-connection layers, consumes only 2.05 W energy while operating at a clock frequency of 100 MHz. Additionally, the LFC accelerator used approximately eight times more logic resources than our work. The proposed MLP model had a performance of 1018 GOPs, while FINN achieved the highest processing capability, with a performance of 8265 GOPs. This is because FINN used a more powerful FPGA card and performed a lot of processing. A conclusion from comparing these two studies clearly proves that the proposed MLP has better efficiency in terms of power efficiency (GOPs/W). The FP-BNN is the second top accelerator in GOPs, depleting resources at a high volume. The power consumption and resource utilization of the FP-BNN faces the maximum level. FCA-BNN is reported to have a processing speed of 1.9 GOPs, with a clock frequency of 166 MHz using 1.3 K BRAM and 152 K LUT. Although the FCA-BNN is two times better in terms of processing speed, it is 15 times higher in memory usage and eight times higher in logic element usage. LeNet has impractical GOP performance due to the bottleneck in the convolution operations and pooling layers.