## 4. Jitter Generation Method
Therefore, the minimum resolution of the jitter generation is 2 ps. There is a design example of jitter generation, which generates a rectangular period jitter with a frequency of 10 Mega-Hertz (MHz) and an amplitude of 20 picoseconds. First, we need to control the phase-locked loop through FPGA to generate a 200 MHz sampling clock, and then, using this sampling clock, to generate addresses and read the jitter data in ROM by generated addresses, where the data model of rectangular period jitter in ROM is generated by formulas (7) and (8). Finally, the data are calculated by the amplitude factor generated by the amplitude control in Figure 3 to obtain the final delay control. The timing diagram of this design example is shown in Figure 5. We assume that ROM_data has 20 data in Figure 5, the ROM_data is sent by a 200 MHz sampling clock, and the jitter frequency obtained is 10 MHz. Because the amplitude of rectangular period jitter in ROM_data is 1 in Figure 5, and the digital step of the programmable delay controlled by Delay_ctl is 10 picoseconds, we need that the amplitude factor is 2 if the amplitude of the jitter generated is 20 picoseconds. Delay_ctl is the output of the FPGA and the input of the programmable delay. Figure 4: Jitter generation circuit. Different from the deterministic jitter generation, the generation of a random jitter data stream is special. The random jitter data stream is generated by MATLAB, and the Gaussian white noise function _randn_, the constant function, and the signal-to-noise ratio (SNR) of the signal are required. It can also be generated by other algorithms, such as the Box-Muller algorithm, and the central limit theorem (CLT) method. [27; 28]  
The definition of SNR is as follows:  
\[SNR=10\log\frac{P_{s}}{P_{n}} \tag{11}\]  
where \(P_{s}\) is the power of the signal and \(P_{n}\) is the power of the noise. According to the definition of Gaussian white noise, \(P_{n}\) is also the variance of Gaussian white noise [29]. We can generate the original signal via the constant function; Gaussian white noise via the randn function; calculate \(P_{s}\), \(P_{n}\), and SNR; and, finally, get the relationship between the variance and other known quantities, as shown in Equation (12). The specific process of generating a random jitter data stream is shown in the Figure 6.  
\[\sigma^{2}=P_{n}=\frac{P_{s}}{\frac{1/105 NR}{10}}=\frac{P_{s}}{SNR} \tag{12}\]  
Assuming that the Gaussian noise signal sent to ROM is \(y_{i}(i=0,1,2,\ldots,1023)\), the mean is \(\mu_{0}\), and the root mean square is \(\sigma_{0}\); then, the final output \(\sigma\) through jitter generation circuit is  
\[\sigma=\sqrt{\frac{\left(Ny_{i}-N\mu_{0}\right)^{2}}{1024}}=N\sigma_{0} \tag{13}\]  
where \(N\) is the amplitude factor generated by the amplitude processing in Figure 4. When the random jitter is generated, the random jitter data stream in ROM is read by the sampling clock that is generated by the PLL, and it is sent to the amplitude processing and multiplied by the amplitude factor. Finally, the result is used as a control word of the programmable delay line to generate a controllable random jitter. The delay compensation is used to compensate the phase deviation to ensure that the phase of the data pattern and the jitter clock are the same when the jitter is synthesized [4]. The compensation can use the FPGA count delay or the delay chip. Because the FPGA count delay is limited by the counter operating frequency, the resolution of the count delay is generally of nanoscale order. At the same time, considering the phase compensation calibration, the programmable delay chip is used in this design for delay phase compensation and improves the resolution of delay. Figure 5: Timing diagram of jitter generation. The jitter synthesis in this design example is implemented by high-speed D flip-flop, and its principle is a relative delay by using the clock side and D side of the D flip-flop, as shown in Figure 7, and the data pattern and the jittery clock are, respectively, connected to the D side and the clock side.