# Design of a Digital Array Signal Processing System with Full Array Element
## 3 Implementation and Verification of the DBF Algorithm
### Hardware Implementation of the MIMO Phased Array DBF Algorithm  
For hardware implementation, the operating band range is 11-12 GHz, with a bandwidth of 1 GHz. The baseband signals of each subarray are orthogonal to each other and can be either LFM signals or single-frequency signals. The hardware implementation of the MIMO phased array digital multibeam formation algorithm consists of the following parts: DBF weight calculation IP core, multiplier, baseband signal ROM, multi-stage flow accumulation module, and IF signal ROM module. The implementation process includes two clock domains: fast and slow. To ensure hardware timing convergence, DBF weight calculations, including multiplication, addition, and other computational operations, are performed in the slow clock domain, while the high-speed and broadband IF signal emission is realized in the fast clock domain. Of these, the DBF weight calculation IP is designed and generated by the XILINX HLS tool [27]; however, the specific design process is not the focus of this paper and will not be described. The flow chart of the hardware implementation of the MIMO phased array DBF algorithm is shown in Figure 18.  
Figure 17: Directional map simulation. Figure 18: Hardware implementation of the algorithm. The four parallel DBF weight calculation IP cores in Figure 18 calculate the one-dimensional DBF weights of each subarray based on the beam pointing angle and carrier frequency from the master control module. A two-dimensional full overlap emission beamforming matrix \(\mathbf{W}\) is constructed based on the DBF weights of the four subarrays as follows:  
\[\mathbf{W}= \begin{pmatrix}w_{1,1}&0&\dots&0\\ \dots&w_{2,1}&\dots&0\\ w_{1,8}&\dots&\dots&w_{4,1}\\ 0&w_{2,8}&\dots&\dots\\ 0&0&\dots&w_{4,8}\end{pmatrix} = \begin{bmatrix}W_{1}&W_{2}&W_{3}&W_{4}\end{bmatrix} . \tag{8}\]  
where \(w_{n,m}\) is the weight corresponding to the \(n\)'th array element of the \(m\)'th subarray. At the same time, the master module passes the mutually orthogonal baseband IQ signals \(\phi_{n}(t)\) required for the \(n\)'th subarray to the transceiver module and stores them in the ROMs of the baseband signal. During beamforming, the transceiver module reads the baseband signals in each ROM and constructs the input signal matrix \(\mathbf{\phi}\). \[\mathbf{\phi}=\left[ \begin{array}{c}\phi_{1}(t)\\ \phi_{2}(t)\\ \phi_{3}(t)\\ \phi_{4}(t)\end{array} \right]. \tag{9}\]  
The multiplication of the full-overlap transmit beamforming matrix with the input signal matrix is achieved using a four-channel parallel complex multiplier and a multi-stage flow accumulation module in Figure 18[26]. \[\mathbf{\psi}=\mathbf{W\phi}. \tag{10}\]  
The output signal \(\mathbf{\psi}\) of the \(11\) array elements can be obtained as shown in Equation (11). \[\mathbf{\psi}=\left[ \begin{array}{c}\psi_{1}(t)\\ \psi_{2}(t)\\ \dots\\ \psi_{11}(t)\end{array} \right]. \tag{11}\]  
When the module detects a new incoming baseband signal or a new beam pointing angle and carrier frequency, the above calculation is repeated to obtain the latest output signal matrix. Finally, the output signal of each array element is output to the IF signal cache ROM, and a higher frequency clock is used in the fast clock domain to transmit the IF signal from the ROM cache to realize the hardware implementation of the simultaneous multibeam algorithm. The DBF results were tested in a microwave darkroom; the test environment is shown in Figure 19. Corresponding to the system hardware architecture in Section 2.1.1, 1 in Figure 19 is the system transmit antenna array, 2 is the system RF front-end, 3 is the system digital array signal processor and 4 is the receiving antenna turntable, which can be rotated in any azimuth angle. The receiving antenna is connected to the spectrum analyzer and vector network analyzer to test the transmit signal. Four beams pointing at \(-45^{\circ}\), \(-15^{\circ}\), \(15^{\circ}\), and \(45^{\circ}\) are generated simultaneously, with carrier frequencies of 8.1 G, 8.2 G, 8.3 G, and 8.4 G, respectively.