## 3 Preliminaries
### Fault Self-Repairing Based on Checkpoint-Rollback Scheme
#### 3.2.1 Object and Time Selections for Checkpoint Backup  
As the name checkpoint-rollback recovery suggests, checkpoint backup and checkpoint rollback are two independent operations for the fault self-repairing module (FSRM); therefore, the backup object and the backup time are two critical parameters for establishing effective checkpoints. In the traditional checkpoint backup scheme, the embedded systems need to back up all the data belonging to the architectural memory components (registers and memories) for the next checkpoint-rollback [28]. This procedure requires continuously accessing various registers for replicating stored elements.  
However, this type backup approach will not only occupy a large number of on-chip storage spaces but also result in a high time overhead on checkpoint backup operation to the real-time embedded system. Generally, the registers in a processor can be categorized into instruction set registers and temporary registers according to their function types, where we define the instruction set registers of OpenRISC as special meaning registers with a small number of control registers, such as the instruction register (IR), program counter (PC), general purpose registers (GPR), special purpose registers (SPR), and status registers (SR). In addition, temporary registers are defined as buffer registers during instruction execution, where the results will be saved into the instruction set registers after operation and will not affect the continuation of program.  
In the five-stage execution pipeline of the CPU, the sequence of instructions of each BB enters the processor for orderly execution. The timing diagram of the BB instructions executed in the five-stage pipeline processor is shown in Figure 3. In the P1 clock cycle, when the jump instruction enters the ID stage, the instruction (Instr. 3) in front of the jump instruction enters the EX stage, and its regular operation, such as logical comparison or data operation begins to execute.  
Then, in the P2 clock cycle, the instruction (Instr. 3) execution stage has completed, its operation results are stored into the instruction set registers, and the temporary registers associated with it will no longer affect the execution of subsequent instructions. The jump instruction enters the EX stage, and some relevant registers will be updated. Finally, in the P3 clock cycle, the instruction monitor will detect a delay slot instruction, which indicates the end of the current BB, and if the relevant registers for the jump instruction execution have completed updates, the integrity signature of the current BB will be verified as early as at this time.  
As all the operation results were updated to the instruction set registers in the P3 clock cycle, and the values of all the temporary registers do not affect next BB program execution; we only need to back up the values of the instruction set registers to meet the checkpoint-rollback operation. Therefore, the end of P3 is the best time for the checkpoint backup.  
Figure 3: The timing diagram of BB instructions being executed in the five-stage pipeline processor.