## 3 Design and Development
### The FPGA Implementation Detail
In this system, the modulus calculation uses circular rotation mode. The adjustable precision feature of the CORDIC algorithm allows flexible configuration based on different application scenarios, further optimizing the overall system performance. In the FFT results, whichever of the real or imaginary parts has a larger absolute value is taken as the X input after taking the absolute value, thereby skipping the first iteration of CORDIC. The modulus calculation using CORDIC performs a total of 2-4 steps, totaling three iterations. After completing the iterations, the data are multiplied by the CORDIC scaling factor and sent to the buffer. The entire process from input data to buffer write is carried out in a pipelined manner, fully leveraging the parallel processing capabilities of the FPGA to ensure computational real-time performance and high efficiency. The energy normalization calculation part uses two DSPs to calculate the cumulative energy of the resampled FFT results, allowing the use of more bits for calculations to ensure precision. After all outputs are accumulated, a hyperbolic rotation mode CORDIC performs the square root operation. The CORDIC relies on the previously used DSPs to iterate four times, followed by multiplication with a scaling factor that includes the reciprocal of the CORDIC gain and the reciprocal of the reference signal energy square root, to obtain the energy normalization result. After completing the energy normalization, the logarithm of the energy is calculated, followed by calculating the relative entropy with a preset value and scaling the final result again using the ratio of sampled energy to preset energy before comparing it to a preset threshold to obtain the judgment result. For division operations and logarithmic computations involved in the system, since these operations typically consume significant resources and have high computational latency in hardware implementations, this paper opts to use a lookup table (LUT) method. This method precomputes and stores commonly used division and logarithmic values, allowing rapid retrieval of results through table lookup when needed, thereby significantly reducing computational latency [37; 38]. Specifically, for division operations, the lookup table is designed based on the range and precision requirements of the dividend, storing the reciprocal of the dividend in discrete form to allow approximate division values to be obtained directly through multiplication during actual computations. Similarly, for logarithmic operations, the method maps the fractional part of the input signal to precomputed logarithmic value tables. This lookup method not only reduces hardware resource consumption but also improves computation speed, ensuring system efficiency in real-time signal processing. The pipelined architecture was applied in the overall system design to further enhance computational efficiency and reduce latency [39; 40]. Pipeline architecture breaks down complex computational tasks into multiple subtasks processed in parallel stages, achieving multi-level parallel computation. By breaking down a single complex combinational logic into simpler combinational logic handled in multiple stages and applying pipeline processing, data processing within a single clock cycle can be performed with lower latency, allowing the system to operate at higher clock frequencies [41; 42]. This is achieved at the cost of increased overall processing delay and resource consumption, thereby significantly improving maximum throughput. In this fault detection module, pipeline application is reflected in the parallel processing of multiple computational steps, such as data acquisition, preprocessing, FFT computation, energy normalization, logarithmic computation, and result determination. This design not only increases system throughput but also reduces the waiting time between each computational step.