# A 4.1 W/mm\({}^{2}\) Hybrid Inductive/Capacitive Converter for 2-140 mA-DVS Load under Inductor +
## 2 Architecture  
Figure 2 provides the motivation for combining the two converters to achieve higher efficiency across a wide output power range. Here, to maintain high power efficiency, shown on the Y-axis, capacitive converters are used at low powers and inductive converters are used at high powers. We note that by changing the voltage conversion ratio of capacitive converter, higher efficiency at low power operation can be performed. But the increase in capacitance value for higher power outputs puts practical limitations on capacitive converters for higher loads in DVS based systems. On the other hand inductive converters are able to support higher loads. Thus a hybrid of both these converters can achieve a wide output power range.  
The details of the hybrid converter are provided later (Figure 14). However, both converters are connected in parallel but only one is switched on at any one time. The switching between the converters is done when the efficiency achieved by one exceeds that achieved by the other. The switching between the converters is done on the basis of voltage sensing to optimize efficiency. This transition voltage can be estimated for a given load condition and is modeled in the following analysis. The switch-over point between the two converters can be decided by considering when the efficiencies of both converters are equal.  
We know that at the time of switching \(V_{out,cap}=V_{out,ind}\) thus the ratio of converter efficiencies, \(\alpha\), is given by Equation (2).  
\[\alpha=\frac{\eta_{ind}}{\eta_{cap}}=\frac{\left[\frac{V_{out,ind}\times V_{ out,ind}}{V_{in,ind}\times V_{in,ind}}\right]}{\frac{V_{out,cap}\times V_{out,cap}}{V_{in, cap}\times V_{in,cap}}}=\frac{I_{in,cap}}{I_{in,ind}} \tag{2}\]  
Figure 3: 3-D depiction of inductor over digital load.  
Figure 2: Desired efficiency profile for each DVS system.  
The switch over from capacitive to inductive converter is done when the ratio \(\alpha\) is greater than one and from inductive to capacitive when it is less than one. We can identify the transition voltage, \(V_{sw}\), if we plug in the values of the two converter currents [3,23] in Equation (2), we get  
\[\alpha=\frac{\frac{1}{k}\cdot\frac{V_{max}-V_{out}}{R_{out}}}{\frac{V_{out}!-I_{ out}}{V_{in}}+\frac{1}{\frac{I_{out}^{2}\cdot(R_{L}+R_{switch})}{V_{in}}}} \tag{3}\]  
where \(V_{max}\) is the no load output voltage of the capacitive converter, \(R_{L}\) is the series parasitic resistance of the integrated inductor, \(R_{switch}\) is the on-resistance of the MOS switches.  
The above relation can be used to estimate \(V_{sw}\) for any kind of load. Figure 4 shows the variation of \(\alpha=\eta_{ind}/\eta_{cap}\) with output voltage for our design for a 10 \(\Omega\) load on the left (blue line) and a digital load (DVS 25 [EMAIL_ADDRESS] V) on the right (red line). The dotted line corresponds to \(\alpha=1\). The transition voltage for the digital load in this plot is 0.5 V and the transition voltage for the 10 \(\Omega\) resistive load is 0.44 V. Increasing the resistive load current or the digital load current would move the optimal transition voltage to a lower value as indicated in the figure.  
To avoid limit cycling between the two converters it is necessary to add some hysteresis margin to the transitions between the two converters. Increasing this hysteresis margin reduces the probability of limit cycles but unfortunately also reduces the overall conversion efficiency as the less efficient converter is allowed to operate for a longer period. However, making this hysteresis margin too small would result in \"hunting\". In particular, the hysteresis margin should be made larger than the sum of the ripple voltage and the noise at the decision point. For our prototype design the ideal transition voltage is 0.55 V and the measured ripple voltage is 35 mV around the transition point. Using a little bit of a safety margin we operate the capacitive converter from 0.4 V to 0.55 V and operate the inductive from 0.9 V to 0.5 V, i.e., we use a 50 mV hysteresis margin.