## 3 Proposed SQRD Algorithm with a Novel Modified RVD
### Proposed Modified RVD
In addition, as the size of the channel matrix increases, the reduction will be further expanded and gradually approach 50%. To evaluate the BER performance of the proposed SQRD algorithm in MIMO detection, it is simulated with a K-best detector and a maximum likelihood (ML) detector in an uncoded \(4\times 4\) 64-QAM MIMO system along with the SQRD algorithm in reference [9]. Figure 2b shows that the proposed SQRD algorithm achieves similar BER performance with the one in reference [9]. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Algorithm** & **Number of CORDIC Operations** & **If N=4** \\ \hline
[9] & \(2N^{3}+(1/2)N^{2}-(1/2)N\) & 134 \\ \hline The proposed & \(N^{3}+(1/2)N^{2}+(1/2)N\) & 74 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Complexity of different Givens rotation (GR)-based QR decomposition schemes. Figure 2: Performance comparisons with the design in reference [9]: (**a**) complexity performance for different matrix sizes; (**b**) uncoded bit error rate (BER) performance in \(4\times 4\) 64-QAM multiple-input multiple-output (MIMO) system. ## 4 Proposed SQRD VLSI Architecture

### Overview of the Proposed SQRD Hardware Architecture

According to Algorithm 1, we designed the corresponding high-speed and low-complexity SQRD hardware architecture for a \(4\times 4\) MIMO system. To match the high throughput of current wireless communication systems, the proposed SQRD architecture is deeply pipelined and highly parallel, which can decompose one \(4\times 4\) channel matrix in four clock cycles and process one \(\mathbf{Q}^{H}\mathbf{y}\) per clock cycle. In other words, the processing cycles of SQRD (clock cycles needed for decomposing one \(\mathbf{H}\)) and \(\mathbf{Q}^{H}\mathbf{y}\) (clock cycles needed for processing one \(\mathbf{Q}^{H}\mathbf{y}\)) are four clock cycles and one clock cycle, respectively, which are both decreased by 20% compared to the design of reference [9]. As \(\text{throughput}=\)clock \(\text{frequency}/\text{processing cycles}\), both the SQRD and \(\mathbf{Q}^{H}\mathbf{y}\) throughput of the proposed SQRD will be improved by 25% compared to the design of reference [9]. In addition, the time-sharing GR structure is designed to take advantages of the idle state of CORDIC modules caused by iterative sorting, which can further reduce the hardware overhead and improve hardware efficiency. The proposed SQRD hardware architecture is basically comprised of one norm calculator, three sorting modules, and four processing engines. Norm calculator and sorting modules are used for iterative sorting; processing engines with CORDIC-based Givens rotation structure are used for decomposing the channel matrix and processing \(\mathbf{Q}^{H}\mathbf{y}\). Figure 3 presents the dataflow of the proposed SQRD design for the \(4\times 4\) MIMO system. Sorted complex Givens rotation (SCGR) is performed on the \(4\times 4\) complex channel matrix \(\mathbf{H}\) and \(4\times 1\) complex receive signal vector \(\mathbf{y}\) with



Then, RGR performed with processing engine#3-4 eliminates the two non-zero elements below the diagonal of \(\mathbf{S}\), as shown in Figure 4. It can be suggested that the elements of the upper two rows of \(\mathbf{R}^{c}\) are obtained after the processing in sorting#3 because the elimination of the first two columns of \([\mathbf{H}\left|\,\mathbf{y}\right|\) have been completed. As the upper four rows of \(\mathbf{S}\) are derived from the upper two rows of \(\mathbf{R}^{c}\) according to Equation (10), they can be obtained immediately after the process of sorting#3 is done. Therefore, the elimination processes of the non-zero element \(\mathbf{S}_{3,2}\) (i.e., \(I_{1,2}^{I}\)) in RGR and the third column of \(\mathbf{R}^{c}\) in SCGR are performed with processing engine#3 at the same time when the relevant elements are output from sorting#3. This will improve the parallelism of the SQRD hardware architecture and shorten the processing latency.