# Balancing the Leakage Currents in Nanometer CMOS Logic--A Challenging Goal
## 2 Background  
CMOS logic is the de-facto standard for integrated circuit design since its introduction in 1963 [28]. It has replaced former logic families such as NMOS logic due to its smaller static power dissipation. This trait is achieved by ensuring that in all CMOS logic gates at least one switched off transistor is present in any path between VDD and GND for each combination of input signals. As an example, consider the classical CMOS NAND gate depicted in Figure 1. For any value of its input signals A and B, at least one cut-off transistor, marked by a dotted line, is responsible for breaking the conductive path and preventing uncontrolled current flow between VDD and GND. At the time CMOS logic was invented, this design strategy was sufficient to produce cells with a negligible power consumption in stable states, as leakage currents in individual transistors were almost not present [28]. However, as technology scaling advanced into nanometer dimensions, these leakage currents kept growing and became a serious problem for device applications that require a low standby power.  
Another problem is caused by the fact that the magnitude of the current flowing through a CMOS cell with stable inputs is severely data-dependent. One of the dominant sources of static power consumption in transistors is drain-source leakage. With that in mind, we consider again the NAND gate in Figure 1. It is to be expected that two NMOS transistors in series, both in the off-state (AB = 00), conduct a smaller current than a single cut-off NMOS (AB = 01 and AB = 10). Similarly, two off-state PMOS in parallel connection (AB = 11) should conduct more current than the two off-state NMOS in series. This setting leads to a fundamentally data-dependent static power consumption of CMOS cells which can be exploited as a side channel [15].  
Usually, an adversary requires full control over the clock signal of the device under test (DUT) to perform such attacks. During any desired part of the cryptographic operation the clock is stopped and all I/O signals of the DUT are kept stable [14]. Then, the static power consumption, i.e., the current still flowing through the DUT, is measured for an arbitrary period of time. The length of this period can be adjusted to reduce the noise included in the measurements exponentially until a noise floor, caused by the algorithmic noise, is hit [14]. This is the main reason masking schemes can only provide reasonable resistance to such attacks when it is guaranteed that the algorithmic noise is sufficiently larger than the exploitable signal [11; 12; 16]. In [16] it is demonstrated that SPSCA attacks can even  
Figure 1: Classic NAND gate, and the status of the transistors for different input values.  
be performed without control over the clock signal when the designer of the DUT fails to ensure that all sensitive data are removed from the circuit's state before entering a temporary idle state.  
To perform practical SPSCA attacks, a special measurement setup is required. The main differences between measuring the static power and the dynamic power consumption of circuits are the DC nature of the static power, its comparably small magnitude, and its strong dependency on environmental influences [14]. In [14] a setup based on a conventional oscilloscope is described. It is also shown that controlling the voltage and the temperature can make devices orders of magnitude more susceptible to SPSCA [14, 16].