## 4 Quantum Exchange Lock Parallel Scheduler
### Quantum Circuit Hierarchical Strategy Based on Qelps
The first two layers involve six quantum bits and four CNOT gates, with \(Q(1)^{2}=36\) and \(Q(1)_{max}=64\), leading to \(Q_{norm}=0.58\) according to Formula (6). Through extensive experiments, \(\lambda=0.63\) is obtained, and Formula (4) results in \(Cost(1,2,0)=-0.0007\). Since the cost function is less than zero, optimization continues. When the number of optimizations is \(i=2\), the number of optimized layers increases to \(l=3\), while the current optimization starts from \(e=0\). In this case, all CNOT gates in the \(l_{2}\) layer satisfy the mapping constraints. As a result, \(\Delta S(2,3,0)=\Delta S(1,2,0)\). The first three layers collectively utilize 10 quantum bits and 6 CNOT gates, with \(Q(2)^{3}=1000\) and \(Q(2)_{max}=1728\). Using Formula (6), we obtain \(Q_{norm}=0.56\), and applying Formula (4) results in \(Cost(2,3,0)=0.0067\). Since the cost function value is greater than zero, the optimization process terminates. For \(i=3\), the number of optimized layers is \(l=2\), and the current optimization begins from \(e=2\). In this case, all quantum gates in both the \(l_{2}\) and \(l_{3}\) layers satisfy the mapping constraints, leading to \(\Delta S(3,2,3)=0\). These two layers involve a total of 4 quantum bits, 2 CNOT gates, and 1 Hadamard (H) gate. With \(Q(3)^{2}=16\) and \(Q(3)_{max}=25\), Formula (6) yields \(Q_{norm}=0.64\), while Formula (4) computes \(Cost(3,2,2)=0.2368\). Since the cost function remains positive, the optimization process is again halted. The FJOSA algorithm effectively minimizes the number of inserted SWAP gates while significantly reducing the overall circuit depth. Additionally, it enhances the mapping layout of quantum bits to a certain extent. When combined with a quantum gate parallel execution strategy, FJOSA can further decrease SWAP gate insertions while ensuring CNOT constraints are met. This ultimately leads to a more efficient and stable execution of quantum circuits, improving both computational accuracy and hardware resource utilization. ## 6 Experimental Evaluation

### Evaluation Metrics

The experiments in this paper utilize the benchmark circuit library [66; 67; 68; 69; 70; 71; 72], which is widely adopted for evaluating quantum circuit scheduling. All circuits consist of Clifford+T gates, with CNOT gates as the only two-qubit operations. The number of quantum bits in

Figure 6: Quantum circuit after optimization with \(n_{1}=0\): (**a**) Original hardware architecture with \(n_{1}=0\); (**b**) Original logic circuit diagram with \(n_{1}=0\). the circuits ranges from 4 to 16. To comprehensively analyze the execution performance and optimization effectiveness, IBM's Qiskit compiler [73] is integrated with superconducting quantum hardware [74]. All algorithms presented in this paper are implemented using Python 3.9, and all compilation tasks are performed on a laptop equipped with an AMD Ryzen 7 processor (3.20 GHz, 16 GB RAM). To further validate the effectiveness of the proposed method, the 2 QAN (Quantum Annealing Network) algorithm [75] is used as a comparative benchmark. The 2 QAN algorithm optimizes quantum bit connectivity through quantum annealing techniques to minimize the number of SWAP gate insertions. By comparing our method with 2 QAN, we provide a comprehensive evaluation of different optimization approaches in quantum circuits, particularly regarding their adaptability and optimization performance under complex hardware topologies. This analysis offers valuable insights for future quantum circuit optimization strategies. ### Model Evaluation

We evaluate the performance of three quantum circuit scheduling and optimization algorithms--2 QAN, QELPS, and FJOSA--in terms of compilation overhead through experiments on 30 benchmark circuits. As shown in Table 1, all three algorithms effectively optimize the number of extra gates in quantum circuits, significantly reducing their count. However, their optimization effects vary. Compared with the benchmark circuit, the 2 QAN algorithm achieves an optimization rate of 57.10%.