## 3 Entropy Feature-Based LNMS LDPC Decoding Optimization
### Generalized LNMS Decoding Algorithm  
This section provides a detailed description of the iterative LNMS LDPC decoding process utilized in the receiver of the flash storage system. As shown in Figure 2, the system architecture includes several key components: detector, LPU, CN, VN, and decision. The detector is mainly responsible for extracting data from the flash channel output and calculating the LLR information from the channel. This LLR information serves as the key input to the iterative decoding process and provides the necessary signal quality indicators for the subsequent steps. In iterative decoding, the LPU plays a key role. Each LPU is responsible for processing a single row of the check matrix. For example, the \(i\)-th LPU mainly performs the calculation and transmission tasks of information between the \(i\)-th CN and the VN connected to it. At the \(l\)-th decoding iteration, the operation of the LPU starts by receiving external information from adjacent VNs in combination with the information transmitted to the VN by the CN in the previous round of iteration (\(CI_{ij}^{(l-1)}\)), where the initial value of the information transmitted by the CN to the VN (\(CI_{ij}^{(0)}\)) is set to zero. Then, the LPU integrates the information of all neighboring VNs and calculates and feeds back update information to the VN (\(VI_{ij}^{(l)}\)), thereby changing the information of the VN. In addition, the LPU is also responsible for calculating the posterior probability information of each bit and performing error detection and correction. The result of each iteration will determine the final decoding output by calculating the posterior information (\(\textbf{v}^{(l)}\)) and combining it with the decision logic. This series of iterative operations is crucial to improving the efficiency and accuracy of decoding, which continue until the preset stop condition is met or the maximum number of iterations is reached. One can observe that, based on the principle of iterative decoding, it is obviously critical to reduce the average number of LPUs in each iteration, which directly reduces the latency of the decoding process. In addition, the optimization of resource allocation and scheduling plays a vital role in improving the operating efficiency of flash storage systems. These optimization strategies not only enhance the response speed of decoding but also improve the system's ability to adapt to changing operating conditions, thereby promoting more efficient data processing and storage operations. Subsequently, we briefly describe the LNMS algorithm presented in [20; 29]. Let \(\textbf{c}=\left\{c_{1},c_{2},\ldots,c_{j},\ldots,c_{n}\right\}\) be the received codeword from the flash-memory channel, where \(c_{j}\) represents the \(j\)-th bit of the codeword and \(n\) is the length of the codeword. Let \(M(i)\) represent the set of VNs that are participated in the \(i\)-th CN (\(i=1,2,\ldots,m\)). Let \(CI_{ij}^{(l)}\) (\(i=1,2,\ldots,m,\textbf{j}=1,2,\ldots,\textbf{n}\)) denote the check-to-variable information at the \(l\)-th iteration. Let \(VI_{ij}^{(l)}\) (\(i=1,2,\ldots,m,\textbf{j}=1,2,\ldots,\textbf{n}\)) denote the variable-to-check information at \(l\)-th iteration. Let \(v_{j}^{(l)}\) (\(j=1,2,\ldots,n\)) denote the posterior information at the \(l\)-th iteration. Let \(c_{j}^{(l)}\) denote the \(j\)-th bit of the codeword after the \(l\)-th decoding iteration. _(1) Initialization:_  
Initialize the posterior information of the \(j\)-th bit to \(LLR_{\text{ch},j}\), i.e., \(v_{j}^{(0)}=LLR_{\text{ch},j}\). Clear the check-to-variable information, i.e., \(CI_{ij}^{(0)}=0\).