# A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds
## 4 8-Transistor PUF Performance Measurements  
To assess the PUF performance, 5G transient noise, including thermal noise, flicker noise, shot noise, etc., was added to the post-layout Monte Carlo simulations because all 8T PUF cells and 6T-SRAM PUF cells were stable in nominal conditions without any external noise. For the two-phase power gating _SUPPLY_ transistors, an 80 nm width was chosen for phase I, and 4 um was chosen for phase II. Meanwhile, the 6T-SRAM PUF was examined under the same conditions for comparison. In addition to nominal conditions, the design was evaluated under different PVT corners, i.e., temperatures from \(-\)40 \({}^{\circ}\)C to 85 \({}^{\circ}\)C and supply voltages from 0.8 V to 1.6 V, and the process corners included _Slow-Slow (SS)_, _Fast-Fast (FF)_ etc. For quantitative evaluation, clusters of 2048 PUF cells were read out for 100 power on-off cycles of 60 ns. This resembles 100 times the same _Challenge_. The 100 2048-bit read-out strings are the PUF _Resposes_. Furthermore, the PUF clusters imitate different PUF devices. With a thorough reset, these PUF characteristics are able to be assessed with post-layout simulations. The intensive multiple simulations here aim to examine the PUF properties to prepare for prototype chip fabrication, so the extracted data were then processed with Matlab to acquire PUF robustness, uniqueness, randomness, etc.  
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline  & **HOST** & **DFT** & **ESSCIRC** & **DFT** & **DATE** & **This** & **This** \\  & **2012 [6]** & **2012 [55]** & **2014 [10]** & **2016 [20]** & **2023 [56]** & **Work** & **Work** \\ \hline \multirow{2}{*}{**Design**} & 6T- & 6T- & \multirow{2}{*}{Hybrid} & \multirow{2}{*}{DFF} & 6T- & 6T- & \multirow{2}{*}{8T PUF} \\  & SRAM & SRAM & & & SRAM & & SRAM \\
**Technology** & 65 nm & 45 nm & 22 nm & 45 nm & 90 nm & 65 nm & 65 nm \\
**Reset Time** & 1 ms & 1 s & 1 s & 50 us & 5 us & 120 us & 1 ns \\ \hline \hline \end{tabular}
\end{table}
Table 1: Reset periods in comparison.  
Figure 8: Transient noise simulation with a 120 us reset period.  
The results were compared with some prior work in Table 2. It is worth noting that the works [8; 9; 25; 58; 59; 60; 61] are ASIC-based measurements, and only [62] and this work include simulation-based evaluations. In fact, post-layout simulations are very resource and time consuming, so only a few works, e.g., [62], can extract data from schematic-based simulations.  
By comparing this work with state-of-the-art designs, it is shown to satisfy the basic PUF requirements and can be evaluated as a PUF. From Table 2, it can be seen that some of the latest designs [44; 59; 60; 61] improve the native stability of PUFs and achieve the native BER very close to 0%. Ref. [44] realises a 0% stabilised BER with relatively high mask ratios and energy consumption per bit, while [59; 60; 61] utilises a novel circuit implementation. This work tries to reach the same level of performance with high-frequency evaluations enabled by the power-gated 8T PUF structure. Since the post-layout simulation is extremely time and resource consuming, there are only a few previous works that attain the same level of results by simulation, e.g., the results of [62] are extracted from schematic-based simulations. The main achievement of the proposed design and structure is the speed, which saves time and hence conserves the total power consumption, etc.