# Microarchitectural Characterization on a Mobile Workload
## 7 Results
### Ipc  
IPC is a critical performance metric in common microprocessors. It analyzes execution time as a product of instruction count. It evaluates the level of instruction-level parallelism. Without instruction-level parallelism, a processor can only issue less than one instruction per clock cycle (IPC \(<\) 1) [11].  
\begin{table}
\begin{tabular}{l c c c c} \hline \hline \multicolumn{1}{c}{**Workloads**} & \multicolumn{1}{c}{**Crypto \%**} & \multicolumn{1}{c}{**Integer \%**} & \multicolumn{1}{c}{**Float \%**} & \multicolumn{1}{c}{**LD/ST \%**} \\ \hline AES-XTS & 20.26\% & 24.66\% & 33.98\% & 21.10\% \\ \hline Text Compression & 0.00\% & 82.62\% & 0.02\% & 17.35\% \\ Image Compression & 0.00\% & 74.29\% & 9.21\% & 16.50\% \\ Navigation & 0.00\% & 59.18\% & 1.10\% & 39.72\% \\ HTML5 & 0.00\% & 65.24\% & 1.87\% & 32.89\% \\ SQLite & 0.00\% & 67.36\% & 0.65\% & 31.99\% \\ PDF Rendering & 0.00\% & 70.51\% & 3.82\% & 25.67\% \\ Text Rendering & 0.00\% & 65.00\% & 1.82\% & 33.19\% \\ Clang & 0.00\% & 72.84\% & 0.44\% & 26.72\% \\ Camera & 0.02\% & 49.96\% & 26.64\% & 23.39\% \\ \hline N-Body Physics & 0.00\% & 28.56\% & 34.38\% & 37.06\% \\ Rigid Body Physics & 0.00\% & 36.79\% & 39.56\% & 23.65\% \\ Gaussian Blur & 0.00\% & 14.55\% & 52.59\% & 32.86\% \\ Face Detection & 0.00\% & 49.96\% & 28.16\% & 21.88\% \\ Horizon Detection & 0.00\% & 59.60\% & 20.55\% & 19.84\% \\ Image Inpainting & 0.00\% & 44.21\% & 33.76\% & 22.03\% \\ HDR & 0.00\% & 66.64\% & 16.23\% & 17.12\% \\ Ray Tracing & 0.00\% & 35.42\% & 39.35\% & 25.23\% \\ Structure From motion & 0.00\% & 46.29\% & 30.82\% & 22.89\% \\ Speech Recognition & 0.00\% & 66.62\% & 13.30\% & 20.08\% \\ Machine Learning & 0.00\% & 28.60\% & 56.15\% & 15.25\% \\ \hline \hline \end{tabular}
\end{table}
Table 6: Instruction mix in Geekbench 5.  
Figure 2 is the IPC for Geekbench workloads. In general, a CPU-centric benchmark's IPC number tends to bigger than one. Similarly, Geekbench 5 shows an average of 2.0 IPC. In Figure 2, the highest number is 3.4 IPC on high dynamic range (HDR). It means that HDR runtime seems to be highly optimized. To have a high IPC number, key microarchitecture performances are required to be good, including cache and branch. HDR's L1 D-cache miss rate is less than 1.2% and the misses per kilo-instruction (MPKI) number is only 2.5. Additionally, there is minimum branch performance impact. Branch MPKI is about 0.1.  
There are four workloads (text compression, navigation, N-body physics, and speech recognition) that have IPC lower than 1. These workloads are memory subsystem dependent. It implies that cache performance is critical to maximizing the benchmark score. In our study, N-body physics occupies 37% of memory operations from the entire execution. The L1 D-cache miss ratio is up to 13% in the experiment. There was no such behavior in the previous CPU benchmark study [12]. This experiment implies that the size of input data contributes to the performance score significantly due to cache efficiency. If benchmark vendors ignore the impact of cache sensitivity on CPU benchmarks, a specific architecture may be favored (e.g., large cache architecture CPU).