## 4 Results and Discussion
### Synthesis Results  
Table 3 presents a comparative analysis of the synthesis results regarding the transistor count, area, and delay for various designed multipliers. The array multiplier showed the highest transistor count. Using Alliance tools, a 64-bit array multiplier was successfully synthesized, surpassing the 875,000 transistors employed in the industrial-scale project of a static control superscalar microprocessor, which was synthesized using the same tools [20]. Both Wallace and radix-4 Booth multipliers effectively reduce the number of transistors. Figure 6 depicts the area of each multiplier, which was normalized relative to the array multiplier. As expected, the findings in Figure 6 and Table 3 reveal a significant increase in area with increasing size of the array multiplier [26]. The Wallace multiplier consistently exhibited the smallest area across all multiplier lengths, with this reduction being more  
pronounced for shorter lengths. As the multiplier size increases, the area of the Wallace multiplier converges to that of the radix-4 Booth multiplier. Alliance tools employ various cells to optimize the delay in each design. The synthesis was performed using standard cells from the SXLIB library. Consequently, different cells were selected to optimize the delay in each design due to their distinct architectures and final adder sizes. The substantial area observed in the designs can thus be attributed to the use of larger standard cells to meet the minimum delay constraint as well as the limitation in utilizing the most advanced features owing to the symbolic layout employed. Figure 7 shows the normalized delay for each multiplier. The delay measurement is performed along the critical path, where the slowest signal must propagate. [PERSON] provided the lowest latency for the 11-, 16-, and 24-bit multipliers, consistent with the findings of the 8-bit and 16-bit multiplier designs in [17; 31], respectively. For the 32-, 53- and 64- bit multipliers, [PERSON] experienced a delay nearly identical to that of the radix-4 Booth multiplier, aligning with the findings of the 32-bit multiplier design using 350 CMOS technology [15]. Wallace offers fast speed because instead of linear dependency, as in the array multiplier, the total delay is proportional to the logarithm of the multiplier operand's word length [32]. In Table 3, the logarithmic behavior of the delay for the Wallace multiplier can be corroborated by increasing the word length, whereas the array multiplier exhibited linear delay increments. \begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline \multirow{2}{*}{**Length**} & \multicolumn{3}{c}{**Transistor Count**} & \multicolumn{3}{c}{**Area (mm\({}^{2}\))**} & \multicolumn{3}{c}{**Delay (ns)**} \\ \cline{2-10}  & **Array** & **Wallace Tree** & **Radix-4 Booth** & **Array** & **Wallace Tree** & **Radix-4 Booth** & **Array** & **Wallace Tree** & **Radix-4 Booth** \\ \hline
11 & 14,776 & 4950 & 6180 & 0.258 & 0.085 & 0.11 & 26.5 & 15.6 & 18.7 \\
16 & 35,558 & 10,572 & 12,152 & 0.623 & 0.179 & 0.23 & 36.3 & 19.6 &  
The size of the final CLA adder and logic levels required for the Wallace tree and radix-4 Booth multipliers are listed in Table 4. The Wallace tree multiplier had the smallest final adder. Radix-4 Booth and Wallace require almost the same number of logic levels to implement the final adder, which explains why they have almost the same delay in the 32-, 53-, and 64-bit multipliers (see Figure 7). The results shown in Figures 6 and 7 and Table 3 indicate that the most important advantage of an array multiplier is its high degree of uniformity. Thus, to perform small multiplications, an array multiplier is preferable owing to its simplicity and structural regularity. However, it was shown that the delay and area become very large for large word lengths in an array multiplier [25; 26; 33]. Therefore, for large multiplications, such as the multiplication of floating-point numbers, a high-speed multiplier such as Wallace or radix-4 Booth may be used.