# Silicon Integrated Nanophotonic Devices for On-Chip Multi-Mode Interconnets
## 2 Silicon Multi-Dimensional (De)Multiplexers
### Silicon Hybrid (De)Multiplexers
We give a summary of the reported silicon wavelength/mode hybrid (de)multiplexers in Table 2. It can be seen that, for most of the reported structures, the wavelength channels still outnumber the mode channels, which gives rise to the system cost and layout complexity. Hence, it is necessary to reduce the wavelength channels further by introducing TE/TM polarizations as a third dimension. Furthermore, coarse wavelength-division multiplexing (CWDM) with a larger channel spacing (\(>\) 20 nm) could also be helpful to enhance the stability and lower the cost [93; 113; 114; 115; 116; 117]. The polarization/mode hybrid (de)multiplexers are able to handle multiple mode channels with dual polarizations. One straightforward scheme is to directly cascade the two groups of ADCs designed for TE and TM modes, respectively, as illustrated in Figure 7a. In [96], an eight-channel polarization/mode hybrid (de)multiplexer was demonstrated on silicon with the first four TE/TM modes (i.e., TE\({}_{0-3}\) and TM\({}_{0-3}\)). The higher-order modes (i.e., TE\({}_{1-3}\) and TM\({}_{1-3}\)) are excited by using the cascaded ADCs, while TE\({}_{0}\) and TM\({}_{0}\) modes are coupled into the multi-mode bus waveguide by using a polarization beam splitter (PBS). The experimental results exhibit insertion losses of IL \(\approx\) 2 dB and crosstalk of XT \(\approx-10\) dB over a 30-nm bandwidth. For such polarization/mode hybrid (de)multiplexers,  
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Ref**} & \multirow{2}{*}{**Year**} & \multirow{2}{*}{**Size (mm)**} & \multicolumn{2}{c}{**Capacity**} & \multirow{2}{*}{**\(\Delta\lambda\) (mm)**} & \multirow{2}{*}{**IL**} & \multirow{2}{*}{**XT**} \\ \cline{3-3} \cline{5-7}  & & & **W** & & & & \\ \hline
[86] & 2014 & 1.2 & 3 & 2 & 8\(\sim\)10 & / & \(-\)30 \\
[89] & 2014 & \(\approx\)0.2 & 2 & 3 & 0.4 & 1.5 & \(-\)22\(\sim\)\(-\)12 \\
[91] & 2014 & \(\approx\)3 \(\times\) 2 & 16 & 4 & 3.2 & 7 & \(-\)10 \\the measured crosstalk is much higher compared with the conventional mode (de)multiplexers working on a single polarization [77]. Such a phenomenon is mainly due to the undesired inter-polarization crosstalk (IPC) at the receiver terminal. Here, we show a design example to illustrate this effect. We calculate the effective indices for TE\({}_{0}\) and TE\({}_{2}\) modes in the 220-nm-thick SOI with SiO\({}_{2}\) cladding, as shown in Figure 8a. The waveguide widths are chosen to be w\({}_{\text{wg,0}}\) = 400 nm and w\({}_{\text{wg,1}}\) = 1.27 \(\upmu\)m to meet the phase-matching condition between TE\({}_{0}\) and TE\({}_{2}\) at a 1.55-\(\upmu\)m wavelength. The gap width is chosen to be w\({}_{\text{gap}}\) = 150 nm. The coupling length is then optimized to be 15.5 \(\upmu\)m to achieve critical coupling. Thus, the input TE\({}_{2}\) mode can be completely demultiplexed from the multi-mode bus waveguide with negligible residual power, as shown in Figure 8c. Unfortunately, for these optimal parameters, the effective indices are also quite close between TM\({}_{0}\) and TM\({}_{1}\) (see the dashed lines in Figure 8a). As a result, part of the input TM\({}_{1}\) mode will also be extracted by the ADC optimized for TE\({}_{0}\)-TE\({}_{2}\) conversion (see Figure 8c), leading to the significant IPC. The IPC could be reduced by optimizing the structural parameters to achieve a polarization-selective mode coupling [96; 97; 98]. However, this methodology always leads to a relatively narrow working bandwidth and a significant parametric sensitivity. Another possible solution is to cascade the polarizers to filter out the undesired polarizations [99], but polarization filtering will give rise to the total insertion losses [118; 119; 120; 121; 122; 123; 124; 125; 126; 127; 128]. Figure 7: The schematics for the silicon polarization/mode hybrid (de)multiplexers based on (**a**) cascaded ADCs [96] and (**b**) cascaded adiabatic ADCs [100]. The IPC problem can be addressed by exploiting the cascaded adiabatic ADCs, as shown in Figure 7b.