# Dynamic Weighted CNN-LSTM with Sliding Window Fusion for RFFE Final Test Yield Prediction
## 1 Introduction
[PERSON] [20] proposed a deep-learning-based wafer map yield prediction model that leverages spatial relationships between chip positions and chip-level yield variations on the wafer, significantly improving prediction accuracy even without process parameters. [PERSON] [21] introduced a novel wafer yield prediction model that utilizes spatial clustering information from functional testing. It extracts spatial distribution variables of defect clusters using the Least Absolute Shrinkage and Selection Operator (LASSO) method and combines them with logistic regression to predict the final yield. Experimental results showed that this model, by considering defect cluster features, significantly outperformed existing methods. [PERSON] [22] proposed a discrete spatial model based on defect data, using a Bayesian framework and hierarchical generalized linear mixed models to analyze and predict wafer yield at different chip locations, effectively enhancing the fit to spatially correlated wafer map data and improving yield analysis precision. [PERSON] [23] introduced a new framework for final test (FT) yield optimization and reverse design of WAT parameters using multiobjective optimization algorithms, applying widely used algorithms such as the Nondominated Sorting Genetic Algorithm II (NSGA-II), the Speed-constrained Multiobjective Particle Swarm Optimization (SMPSO), and the Generalized Differential Evolution 3 (GDE3), proving effective in improving yield and accurately identifying optimal WAT parameter combinations. [PERSON] [24] proposed an AI-based wafer yield prediction framework, exploring the potential and challenges of using virtual metrology in semiconductor manufacturing. In the realm of semiconductor manufacturing, yield prediction and enhancement are pivotal for improving production efficiency and reducing costs. [PERSON] [25] utilized manufacturing process features to predict yield across different designs, employing Bayesian model fusion techniques to integrate data from both new and old equipment for accurate yield prediction. Through comparative experiments with averaging methods, early learning methods, and data mixing methods, the results demonstrated that Bayesian model fusion achieved smaller prediction errors on small sample sets. [PERSON] [26] proposed a scalable yield prediction framework for semiconductor manufacturing using explainable artificial intelligence (XAI). By incorporating a scalable framework based on input data to account for divergence factors in predictions and adopting XAI to address this challenge, the AI leverages model explanations to modify manufacturing conditions. This framework improved prediction accuracy and utilized Shapley additive explanations to elucidate the relationship between yield and features. Furthermore, [PERSON] [27] proposed an explainable method with adaptive modeling for yield enhancement in semiconductor smart manufacturing. This study introduces a domain-specific explainable automated machine learning approach (termed xAutoML) designed to self-learn optimal models for yield prediction, offering a degree of explainability and providing insights into key diagnostic factors. [PERSON] [28] proposed a backend final test yield prediction method based on Gaussian Mixture Model (GMM) ensemble regression, leveraging front-end WAT parameters to predict final test yield during the wafer manufacturing stage. This approach enabled early detection of low-yield issues, significantly enhancing prediction performance. The CNN-LSTM model, with its short-term memory network, is widely applied in language signal recognition and prediction. Building on this, researchers have explored multimodal fusion to optimize this model and conduct studies in related prediction domains. [PERSON] [29] proposed a novel wafer yield prediction method combining Improved Genetic Algorithm (IGA), High-Dimensional Alternating Feature Selection (HAFS), and Support Vector Machine (SVM), effectively addressing data imbalance and overfitting in wafer manufacturing.