## 3 Results and Discussion  
### Tests with Two Modules with 24-bit Sigma-Delta Converters and Two Chassis  
For the Sigma-Delta converters, the single-phase mains voltage was used. The input for both modules was a single-phase voltage at 50 Hz and Vrms = 230 V.  
Firstly, a test was performed to determine the phase error of each of the modules under testing. The phase difference between two consecutive channels of the same module was measured. Secondly, a test was carried out to determine the phase error between two channels of modules A and B. The phase shifts Channel-A0 and Channel-B0 were measured. The two modules were inserted into the same cDAQ-9185 chassis and placed in two consecutive slots. In a third test, captures were made with different cDAQ-9185s. Modules A and B were connected in slot 1 and the two chassis were synchronised with the TSN standard. The test allowed for verifying the synchronism for simultaneous single-phase voltage sampling. The tests were repeated with 2 m and 10 m Ethernet cables. Figure 5 shows that almost all the time series data were below 100 ns and Figure 6 shows that the distribution type of the TSN synchronous tests had a higher dispersion than the two reference tests on the same chassis, but the central position of the distributions (medians) were below 60 ns. Figure 5: Time series of the four Sigma-Delta converter tests. Table 3 shows the statistical results for the four trials. On the one hand, the accuracy was observed with a median of Me = 9.5 ns and a very low variance of \(\sigma^{2}\) = 7.7 ns for the Sigma-Delta channels integrated into the same module A was seen. When they are in different modules of A and B, the average errors of Me = 28.31 ns and the variance of \(\sigma^{2}\) = 14.9 ns were obtained. With a 2 m cable, a median Me = 17.7 ns was obtained, which was very close to the best reference of Me = 9.52 ns, but with a very high dispersion identified with a variance of \(\sigma^{2}\) = 250.6 ns. For a 10 m cable, the median was Me = 54.3 ns but with a somewhat smaller variance. These results with NI-9242 modules and 24-bit Sigma-Delta converters represent the highest level of quality available with the current technology and serve as a reference for estimating the quality of 16-bit SAR converters. In a first assessment, it can be said that the phase errors for simultaneous captures and TSN synchronism comply with the specifications established in the IEEE 802.1 AS-2011 standard. This is a technology that manages to maintain synchronisation 10 times higher than that indicated as optimal by the standard, which is 1 us. Conversely, it is necessary to estimate the uncertainty of the method based on the results obtained. The box-and-whiskers diagram allows for comparing the results of the four types of tests, as well as for estimating the uncertainty of the instrumentation system that integrates the TSN synchronism. It is necessary to remember that in a box plot, the black lines mark the upper value and lower value positions where 95% of the samples were concentrated. Therefore, the upper end, identified with a black arrow, marks an uncertainty level with a 5% error in the phase measurements for each of the cases. The red lines represent the position of the median for the whole time series, while the blue box marks the lower and upper quartile limits. Figure 7 shows the box plots for the Sigma-Delta converter tests. \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{3}{*}{**Statistics (ns)**} & \multicolumn{4}{c}{**Test: 50 Hz, 230 Vrms, and Sampling Fs = 50 kS/s**} \\ \cline{2-5}  & \multicolumn{4}{c}{**24-bit Sigma-Delta Converters**} \\ \cline{2-5}  & **Slot 1** & **Slot: 1–2** & **Chassis: 1–2** & **Chassis: 1–2** \\  & **A0–A1** & **A0–B0** & **Cable 2 m** & **Cable 10 m** \\ \hline Median (Me) & 9.52 & 28.31 & 17.76 & 54.35 \\ \hline Mode & 9.61 & 27.01 & 15.11 & 48.78 \\ \hline Variance (\(\sigma^{2}\)) & 7.69 & 14.92 & 250.66 & 168.92 \\ \hline Standard Deviation (\(\sigma\)) & 2.77 & 3.86 & 15.83 & 13.00 \\ \hline \hline \end{tabular}
\end{table}