# A Novel Cross-Latch Shift Register Scheme for Low Power Applications
## 3 Analysis of Layout Area and Power Consumption of the Proposed CLSR Design  
To accomplish the goals of achieving low integrated circuitry layout area and low power consumption, the proposed flip-flop is designed with cross-latch architecture. Since the conventional master-slave (MS) latch transmission gate flip-flop (TGFF) is the most widely used flip-flop, it is necessary to make a comparison between this proposed CLSR scheme and the traditional MS latch flip-flop. The proposed CLSR scheme was implemented in TSMC-40 nm CMOS process standard technology [33]. Figure 7 shows the post-simulation results of the proposed 256-bit CLSR design under the process of 1 GHz/TT corner frequency at a supply voltage of 0.9 V. The output QN is generated by shifting the input data according to the clock signal. When the clock is triggered positively 16 times, the data are shifted by 16-bit, and the signal of Q15 is generated. When the clock is triggered positively 256 times, the data are shifted by 256-bit, and the signal of Q255 is generated. It can be seen that after adding a delay clock circuit (Figure 6c), the above-mentioned glitch issue is clearly wiped out. Figure 7: Post layout simulation of 256-bit shift register design based on the proposed CLSR design. Figure 8 shows the layout comparison between a 256-bit shift register that was constructed based on this proposed CLSR scheme and the conventional master-slave latch architecture. The number of transistors in the conventional MS latches shift register design is 6144, and the number in the proposed CLSR scheme design is 3174. Compared with the conventional MS latches shift register, the number of transistors in the proposed CLSR scheme can be reduced by 48.33%. To show the advantages of the proposed design in terms of average power consumption, we performed simulations for different conditions. Figure 9a shows the power consumption of the proposed CLSR scheme design in different switching activities (0-100%) at 0.9 V/250 MHz. Because the required number of transistors is decreased dramatically, the proposed CLSR scheme reduces the average power consumption by 36% compared with the conventional MS latch design. Additionally, the gates capacitances are reduced, and the dynamic power dissipation is suppressed as well. Figure 9b shows a comparison of leakage powers under different word lengths between MS latch and CLSR architectures. The leakage current of an MS latch shift register is mainly contributed by the inverters and is proportional to the numbers of inverters. In the proposed CLSR scheme, the number of inverters is reduced significantly. Thus, the proposed 256-bit CLSR scheme design saves 60.53% leakage current as compared with the conventional design. Figure 8: 256-bit shift register, proposed CLSR scheme and the conventional master–slave latch architecture layout. Figure 9: Power consumption performance. (**a**) Different data switching activity. (**b**) Leakage power. (**c**) Different operation frequency. (**d**) Different supply voltage. Figure 9c shows the power consumption at different operating frequencies (1 MHz\(-\)1 GHz). From the results, the proposed CLSR scheme achieves an average power saving of 35% as compared with the conventional MS latch design. Figure 9d shows the power consumption of the proposed CLSR scheme design under different voltages. To ensure both designs can operate normally, the operating frequency is set at 25 MHz. From the post-layout simulation results, we find that when the proposed CLSR scheme operates from 0.4 V to 0.9 V, it can save 31% power consumption on average compared with the traditional design. Figure 10 shows its optimal power delay product (PDP) performance. The PDP was employed as a composite performance index in this work. For each supply voltage, the CQ delay was scanned to obtain the best PDP number. Both shift register designs were determined to function properly under process variations. The proposed CLSR scheme works well in any kind of simulation trials.