## 3 Results and Discussion
More improvements of the thermal dissipation were accomplished by additional embedding of the TiO\({}_{2}\) NS-monolayer, lowering the GPU chipset's temperature by 1-7 \({}^{\circ}\)C. Note that only the TiO\({}_{2}\) NS-monolayer embedded in PDMS exhibited similar thermal dissipation effects compared with the 30 wt% TiO\({}_{2}\) NS-filler. Moreover, 30 wt% TiO\({}_{2}\) NS-filler/monolayer embedded in PDMS exhibited almost the same heat dissipation characteristics as the 40 wt% TiO\({}_{2}\) NS-filler. It is noteworthy that the loading fraction of the TiO\({}_{2}\) in NS-monolayers is only 0.314 wt%. These results indicate that the TiO\({}_{2}\) NS-monolayer not only effectively enhances the thermal conductivity of TIM but is also a cost-effective way to achieve a high thermal conductivity of TIM without additional filler loading. Figure 5c shows the working time-dependent temperature variation of the GPU chipset from 0 to 500 s with the fabricated TIMs attached. In all samples, there were abrupt increases in temperature during the initial stages, which then became saturated about 140 s later. In addition, the maximum measured temperatures of the GPU chipset decreased as the loading fraction of the TiO\({}_{2}\) NS-filler in the PDMS increased, with a tendency to decrease further in the presence of the TiO\({}_{2}\) NS-monolayer. To theoretically investigate the thermal conductivity enhancement of TIMs by a TiO\({}_{2}\) NS-monolayer, a computer simulation was used with COMSOL Multiphysics 5.6. The simulations were conducted on the premise that the lowest saturation temperature model has the highest thermal conductivity. The quantity of heat applied to the chipset and the air flow speed applied to the heat sink were fixed considering typical cooling fan speeds (\(\varOmega\)150 mm, 1200 rpm) and detailed values are described in the materials and methods Section 2.3. For more accurate analysis, the thermal resistances between the PDMS, TiO\({}_{2}\) NSs, chipset, and heat sink should be considered based on the contact interface conditions [24]. The thermal resistances between the chipset and TIM and the TIM and heat sink were set to relatively high values of 2 \(\times\) 10\({}^{-5}\) Km\({}^{2}\)W\({}^{-1}\) because they have solid-solid contact interfaces with air gaps due to the surface roughness [25, 26]. TiO\({}_{2}\) NSs and PDMS form relatively stable interfaces because they are mixed and hardened in a liquid state [27]. Thus, the thermal resistance between TiO\({}_{2}\) NSs and PDMS was 10\({}^{-7}\) Km\({}^{2}\)W\({}^{-1}\), a relatively low value [28]. Figure 6a shows the heat conduction characteristics of TIMs with bare PDMS, 20 wt% TiO\({}_{2}\) NS-filler in PDMS, and 20 wt% TiO\({}_{2}\) NS-filler/monolayer in PDMS at  
Figure 5: (**a**) Optical photographs of the GPU chipset and heatsink set with the fabricated TiO\({}_{2}\) NS-based TIM. (**b**) The saturation temperature and (**c**) time-dependent temperature variations of the GPU chipset according to the concentration of TiO\({}_{2}\) NS-filler with and without the TiO\({}_{2}\) NS-monolayer in PDMS matrix as the TIM. (Insets in Figure 5b are optical photographs of the fabricated TiO\({}_{2}\) NS-based TIMs.). the same temperature scale. The heat conduction enhancement due to the NS-monolayer was clearly observed by comparing the average temperatures of the chipset and TIM. The ratio of the temperature difference between the two substances forming an interface can be described as follows:  
\[\text{Temperature difference ratio}=\frac{\text{T}_{\text{heat source}}-\text{T}_{\text{TIM}}}{\text{T}_{\text{TIM}}}\times 100\;[\%], \tag{1}\]  
where \(\text{T}_{\text{heat source}}\) and \(\text{T}_{\text{TIM}}\) are the steady-state temperature of the heat source (chipset) and TIM, respectively. The large temperature difference indicates that there is a large contact resistance, which can impede heat conductions between the chipset and TIM, causing heat to be trapped in the heat source.