# A Low-Complexity Start-Stop True Random Number Generator for FPGAs
## 3 The Quality of Bit Streams Produced by the Proposed Generator
\begin{table}
\begin{tabular}{l c c c c c c c c} \hline \hline \multirow{2}{*}{**Test**} & \multicolumn{6}{c}{**Raw Data**} & \multicolumn{6}{c}{**Raw Data + SHA1**} \\ \cline{2-10}  & **WT2** & **WT3** & **WT4** & **WT2D** & **WT2** & **WT3** & **WT4** & **WT2D** \\ \hline
1. Frequency & — & — & — & Y & Y & Y & Y & Y \\
2. Block frequency & — & — & — & — & Y & Y & Y & Y \\
3. Cumulative sums & — & — & — & Y & Y & Y & Y & Y \\
4. Runs & — & — & — & — & Y & Y & Y & Y \\
5. Longest run & — & — & — & — & — & — & Y & Y & Y \\
6. Rank & — & — & — & — & — & — & Y & Y & Y \\
7. DFT & — & — & — & — & — & — & — & Y & Y \\
8. Nonoverlapping template & — & — & — & — & — & — & — & ✓ & ✓ \\
9. Overlapping template & — & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
10. Universal & — & — & — & — & ✓ & ✓ & ✓ & ✓ & ✓ \\
11. Approximate entropy & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
12. Random excursions & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
13. Random excursions variants & — & — & — & ✓ & ✓ & ✓ & ✓ & ✓ \\
14. Serial & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
15. Linear complexity & Y & Y & Y & Y & Y & Y & Y & ✓ \\ \hline \hline \end{tabular}
\end{table} 
Table 4: The final results of statistical tests described in SP 800-22, \(f_{L}\) = 5 MHz. \begin{table}
\begin{tabular}{l c c c c c c c} \hline \hline \multirow{2}{*}{**Test**} & \multicolumn{6}{c}{**Raw Data**} & \multicolumn{6}{c}{**Raw Data + SHA1**} \\ \cline{2-7}  & **WT2** & **WT3** & **WT4** & **WT2D** & **WT2** & **WT3** & **WT4** & **WT2D** \\ \hline
1. Frequency & — & — & — & — & Y & Y & Y & Y \\
2. Block frequency & — & — & — & — & Y & Y & Y & Y \\
3. Cumulative sums & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
4. Runs & — & — & — & — & — & ✓ & ✓ & ✓ \\
5. Longest run & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
6. Rank & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
7. DFT & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
8. Nonoverlapping template & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
9. Overlapping template & — & — & — & — & ✓ & ✓ & ✓ & ✓ \\
10. Universal & — & — & — & ✓ & ✓ & ✓ & ✓ & ✓ \\
11. Approximate entropy & — & — & — & ✓ & ✓ & ✓ & ✓ & ✓ \\
12. Random excursions & — & — & — & ✓ & ✓ & ✓ & ✓ & ✓ \\
13. Random excursions variants & — & — & — & ✓ & ✓ & ✓ & ✓ \\
14. Serial & — & — & — & ✓ & ✓ & ✓ & ✓ & ✓ \\
15. Linear complexity & Y & Y & Y & Y & Y & Y & Y \\ \hline \hline \end{tabular}
\end{table} 
Table 3: The final results of statistical tests described in SP 800-22, \(f_{L}\) = 10 MHz. The proposed generator yields IID bit sequences that pass the restart tests specified in NIST 800-90B and, following the application of SHA1, all tests outlined in SP800-22. For the generator depicted in Figure 2, achieving the same outcome requires combining at least seven-bit streams using the XOR function, each produced in the circuit shown in Figure 1. This conclusion holds under the condition that the sampling frequency \(f_{L}\) does not exceed 10 MHz and the outcome remains consistent across different FPGA technologies. Table 6 presents the proportion \(R_{\beta}\) and the values of \(P_{T}\) for raw data and after processing for WT7 and WT2D implemented in Virtex 5 XC5 LVX50T. Reliable comparison of existing proposals of TRNGs is very difficult, and the result depends strongly on the assumed criteria. For comparison, TRNGs that meet the following conditions were selected:  
1. The generator can be integrated into the same FPGA alongside a digital system that employs random sequences. 2. The authors declare that the generator produces IID sequences and that the restart tests described in the SP800-90B are performed.