## 1 Introduction
A look-up table based numerically controlled oscillator is coupled with the mixers. The final stages are polyphase decimation filters. One of the structures that incorporate a tunable rate change factor in polyphase filters is the Farrow structure [4], which is amenable to time interpolation. A digital front-end for direct-sampling receivers is implemented in [12], where digital mixers, cascaded integrator comb filters, Taylor-series polynomial interpolation filters (based on resampling for fractional decimation), and decimation-by-2 filters are employed. In [13], a digital down-converter with polyphase cascaded integrator comb filters is simulated to validate its compatibility with the time interleaved analog-to-digital converter. Parallel processing is employed in the channelization for an IEEE 802.11 ac receiver in [14], which is implemented in software on a graphics processing unit. A lower-error Farrow structured variable fractional delay interpolation is described and simulated in [15]. In this paper, a digital front-end decimation chain in radio receivers with fractional sample-rate conversion is proposed, simulated, designed, and implemented, which can fulfill carrier aggregation in the long-term evolution (LTE) and LTE-advanced (LTE-A) standards while accommodating multiple frequency bands. Fractional sample-rate conversion (FSRC) is realized by means of a Farrow interpolator and the output of the DFE is fed to the orthogonal frequency division multiplexing (OFDM) baseband processor. A methodic design methodology is taken to guarantee the register transfer level (RTL) performance relative to higher abstraction level performances and to accomplish the design goals on an overall OFDM receiver system basis. The proposed DFE architecture is fully compliant with the LTE-A CA specification and it is synthesized in an application-specific integratedcircuit (ASIC) and also implemented in a field-programmable gate array (FPGA), which are also analyzed in depth in terms of performance and hardware complexity. Prior to giving a more detailed look at the DFE architecture in Section 2, we first sketched the overall structure of the proposed DFE for LTE and LTE-A in Figure 1. The cascaded integrator comb (CIC) filter received the ADC output signal and converted the sampling rate by a factor of \(1/N\) where \(N\) is an integer. FSRC is capable of converting the sample rate by a factor of L/M where L/M is a rational number, not only an integer number. The digital mixer (DM) removed the intermediate frequency (IF) of the component carriers in carrier aggregation (CA) for LTE-A and increased or decreased each carrier frequency. Subsequently, carrier aggregation filters (CAF1 and CAF2) adjusted the sample rate or sampling frequency to the output frequency of the LTE DFE receiver by a last-step conversion and eliminate unwanted frequency-domain interference arising from CA. Lastly, the channel selection filter (CSF) got rid of the residual interference while sustaining the desired signal. The paper is organized as follows. The design flow and the overall DFE architecture are described in Section 2. The building blocks of the overall DFE architecture are elaborated on in terms of basic concept and theory in Section 3, which is subdivided into the explanation of CIC, FSRC, digital mixer, carrier aggregation filter, and channel selection filter. Simulated results of the overall DFE architecture is detailed in Section 4. The detailed hardware implementation and the experimental results of the proposed DFE in both an ASIC and an FPGA are demonstrated in Section 5, together with some discussion, which are followed by the conclusion.