# FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs
## 1 Introduction  
Recent innovations and advancements in the computational capability of new-generation processors have paved the way for an efficient and fast implementation of deep learning (DL)-based models [1, 2, 3]. This mobility essentially enhances the development of such models for a plethora of applications in the era of artificial intelligence (AI) [4, 5, 6, 7]. A critical emphasis has been placed on accelerating DL-based approaches operating on floating-point operations. Therefore, when executing a typical DL approach, satisfying the requirement of accuracy is of paramount significance. The distinctive feature of DL is itsmechanism of learning the attributes and weights of the networks from large datasets [8]. To ensure a robust level of accuracy, complex models have been employed with success, but at the expense of a large computational load and memory budget. Convolutional neural networks (CNNs) inspired by biological processes, as one of the most popular DL techniques, have become an increasingly popular choice for implementation in embedded devices [9; 10]. Existing CNN algorithms often require a huge amount of multiplication and accumulation (MAC) operations [11; 12]. Recent studies have attempted to boost the applicability of CNN algorithms for devices with constrained resources [13]. This can be, of course, achieved by diminishing the computational complexity and memory requirements of CNNs. One way to speed up the implementation of CNNs is to exploit several graphic processing units (GPUs) that are capable of floating point arithmetic operations [14]. Due to the high power consumption of GPUs, they may easily suffer from large energy costs, which cannot be handled by embedded devices powered by limited batteries [15]. FPGAs as an embedded device have been a popular way to accelerate CNNs, with lower energy consumption than GPUs in real-time embedded applications [16; 17]. A spectacular advantage of FPGAs is their resilience in arranging functionality to perform any task. Due to the superiorities of FPGAs, such as reconfigurability, customization, energy efficiency, and flexible architecture design, there have been several research attempts focusing largely on the application of FPGA-based CNN hardware accelerators [18; 19]. Nevertheless, FPGAs are equipped with on-chip limited resources, which limit the practicality of CNNs in dealing with the issue of MAC operations and the great amount of weights. This requires the efficient utilization of the restricted resources in real-time processing platforms. A promising solution to this challenge is to quantize the models, which can reduce the floating-point precision to a fixed-point scalar form with a lower bit-width [20; 21]. In the context of machine learning, QNNs have been introduced to convert MAC operations into bit-wise operations with extremely low precision [22]. By performing this quantization, the computation and storage load can be remarkably alleviated, subject to data loss as a result of quantization errors. This article studies the potential of FPGA-QNN, a QNN accelerating structure for FPGAs using the FINN framework [23]. The FPGA-QNN constructs 12 QNN networks with respect to changing quantization and folding grades. The folding part contains the parallelization process, which determines the resource usage and acceleration level of the network. A customized approach is introduced to multi-bit quantization and folding levels, tailored to optimize resource utilization and performance trade-offs on the PYNQ 21 platform. Unlike in previous works, our folding levels are experimentally tuned to achieve a balance between throughput and energy efficiency. The paper evaluates the proposed framework using three quantization levels (W1A1, W1A2, and W2A2), showcasing the impact of precision on performance metrics such as resource utilization and accuracy. This detailed analysis has not been comprehensively addressed in previous studies.