## 4 Simulation and Experimental Results  
The simulation model of the circuit topology and two-loop control was developed on software package PSIM 11 and was run to capture waveforms and observe transient performance of the converter under load-current variations. Simulation results are illustrated in Figures 13 and 14. Figure 12: Bode plot of the compensated voltage control loop system: PM = 60\({}^{\circ}\) at 3150 rad/s (500 Hz). Figure 13: Simulation waveforms for \(V_{in}=12\) V with step change in load from 50% load to rated full load; (**a**) \(V_{o}\) is output voltage, \(I_{o}\) is output current, (**b**) \(I_{L1}\) and \(I_{L2}\) are input inductor currents, and (**c**) \(V_{s1}\) and \(V_{s3}\) are voltages across the switches \(S_{1}\) and \(S_{3}\), respectively. The load is changed from 50% load to rated load (Figure 13) and from full load to 50% load (Figure 14). It should be observed that the overshoot or undershoot in output voltage for both step changes is 2V, which demonstrates the excellent stability of control. Load current and the two input inductor currents smoothly change to the next steady-state value. The settling time of the inductors' current and load voltage is nearly 25 ms. The voltage across the primary switches (VS1) is clamped at the reflected output voltage, and the voltage across the secondary devices (VS3) is clamped at the output voltage V\({}_{\text{o}}\) without any overshoot during the load transients, ensuring safe operation of the converter. Figure 14d (zoomed waveform in transient period) shows voltage across the primary side devices is clamped at the reflected output voltage, while voltage on the secondary side devices is always clamped at output voltage. Figure 14e,f shows steady-state (zoomed) waveforms at rated load and half load, respectively. It should be noted that primary side devices maintain ZCS, and secondary side devices maintain ZVS under both conditions. Figure 14: Simulation waveforms for \(V_{in}=12\) V with step change in load from rated load to half load with identical nomenclature. (**a**) \(V_{o}\) is output voltage, \(I_{o}\) is output current, (**b**) \(I_{L1}\) and \(I_{L2}\) are input inductor currents, and (**c**) \(V_{s1}\) and \(V_{s3}\) are voltages across the switches \(S_{1}\) and \(S_{3}\), respectively, (**d**) zoomed waveform of \(V_{s1}\) and \(V_{s3}\), (**e**). \(I_{Ls}\) is the transformer primary current and \(I_{S1}\) and \(I_{S2}\) are the current through the switches \(S_{1}\) and \(S_{3}\), respectively at full-load steady-state and (**f**) \(I_{Ls}\) is the transformer primary current and \(I_{S1}\) and \(I_{S2}\) are the current through the switches \(S_{1}\) and \(S_{3}\), respectively at half-load steady-state. Figure 15 shows the experimental prototype of the converter. It is operated by the designed controller, which has been tested in the laboratory for the step changes in load for a fixed 12 V input voltage. Table 2 shows the details of the components used in the hardware prototype. Gating signals for the semiconductor devices are generated by Texas Instruments (TI) digital signal processor (DSP) TMS320F28335. Experimental waveforms for the step change in load are shown in Figures 16 and 17. Figure 16 demonstrates the experimental waveforms of inductor current \(i_{L}\), voltage \(V_{AB}\), and output voltage \(V_{o}\) with respect to time for the step change in load from rated load to 50% load. The similar waveforms for step change in load from 50% to rated load are manifested in Figure 17. Overshoot and undershoot in the output voltage are negligible during load transients. Further, output voltage \(V_{o}\) is maintained at the constant value. The variations in inductor current \(I_{L}\) and \(V_{AB}\) (transformer primary voltage, that is, the sum of voltage across the two primary switches S\({}_{1}\) and S\({}_{2}\)) are within safe limiting values. Therefore, the switches do not experience any voltage spike during transition, which ensures safe and normal operation of the converter.