# Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices
## 2 Materials and Methods
### Designed System  
The system described before has been simulated in Simulink. Figure 3 is an example of a model-based system designed for \(N=2\).  
In this case, the impedance lines, Z1 and Z2, are equal with a resistive part of 1 m\(\Omega\) and an inductive part of 250 nH. They represent the non-ideality of the cables used to  
Figure 3: Simulink model of the system with two inverters.  
connect the inverters to the load, while Z0 is the load impedance composed of a resistive part of 1 m\(\Omega\) and an inductive part of 1 mH. The subsystems, FPGA1 and FPGA2, contain the core of the simulation model: the FSM that controls the PWM and its reset logical rules. The subsystems, BRIDGE1 and BRIDGE2, are the modules dedicated to converting the FPGA signal (0-3.3 V) to the output voltage (\(\pm\)300 V). Indeed, the inverter module is composed of a logical section (FPGA device), with a power supply of 3.3 V, and a power section that provides the \(\pm\)300 V output voltage. A load current operating point of 10 A has been imposed, that means a current of 5 A in each module for the two-inverters system.  
To take into account crystal oscillator tolerance or possible non-perfect synchronization in the switch on of the inverters, which could lead to the generation of circulating currents, different phase and frequency clocks have been considered. As an example, in the two parallel-connected inverters system depicted in Figure 3, the clock of the first inverter was imposed to 100 MHz, while in the second inverter a clock frequency 0.1% greater and a 5 ns clock phase delay were forced. Crystal oscillator datasheets that are generally used in FPGA applications are reported in [39; 40]. The frequency variation estimated is around 10 ppm and 100 ppm. Hence, to demonstrate the validity of the approach and to take into account the ageing of the crystal oscillator, a tolerance of 1000 ppm (corresponding to 0.1%) has been considered.  
In Figure 4, the subsystems BRIDGE is presented. All the subsystems deployed in the main model-based schematic with the same function are perfectly identical.  
The subsystem BRIDGE aims to convert the FPGA-output control signals into power system signals. In this paper, the internal architecture of the inverter has not been studied because the effort has been concentrated on its control regardless of its internal structure. The Simulink model represents the BRIDGE inverter controlled by a 0-3.3 V signal. The low-pass filter, employed to convert the square wave into the output sine wave, which is normally required after the inverter, has not been considered, since it does not affect the simulation results. \(V_{DC}\) is the constant DC-link equal to 600 V. The conversion is achieved with the simple Equation (6):  
\[\mathrm{V_{out}}=\frac{V_{DC}}{3.3}-\frac{V_{DC}}{2} \tag{6}\]  
where \(V_{\mathrm{out}}\) is the output voltage of the BRIDGE and \(V_{DC}\) is the voltage of the system DC-link, both expressed in Volt.  
The FPGA subsystem includes the model-based design of the proposed new control method that is described in detail in the following paragraph.