## 3 Results and Discussion
### NBTI-Aware PVTC Method Analysis  
To explore how the NBTI effect can affect the transient fault rate of digital circuits, we add the NBTI model to the PVTC analysis framework. Table 2 presents the transient fault estimation results for NAND and NOR gates and the full adder circuit when the circuit is in a fresh state and after three years of NBTI degradation. We also calculate the change rate before and after degradation, which is defined as follows: (Degraded-Fresh)/Fresh.  
As shown in Table 2, the NBTI effect causes a significant transient fault rate change for different parts of the VLSI circuit during its lifetime. Moreover, as the feature size, supply voltage and threshold voltage continue to decrease, this change will become more severe in the future. These results also illustrate that the transient fault rate will increase for certain gates with a certain input pattern, but the opposite situation is observed for other gates with the same input pattern combination (Table 2). A detailed illustration of the fault rate change for the NAND and NOR gates with the same input pattern, in a fresh state and degraded state, respectively, is provided in Figure 14.  
As shown in Figure 14a, the gate will be more sensitive to transient faults after degradation when the input pattern of the NAND gate is \"01\"; in contrast, the same pattern \"01\" results in a transient fault rate decrease for the NOR gate, as shown in Figure 14b. This result is mainly due to the different functions of the logic gates. When the threshold voltage of the pMOS increases, an input of \"0\" will be more likely to be recognized as \"1\"; thus, the transient fault rate will be more likely to increase with an input of \"00\", whereas the transient fault rate will be more likely to decrease with an input of \"11\" for both the NAND and NOR gates. If the input is \"01\", the NOR gate is more likely to logically mask the error, whereas the NAND gate is not, which creates the different trends in the change rate. Thus, during the entire lifetime of a VLSI circuit, we can provide more accurate fault rate estimation results if NBTI effect is considered.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Logic Circuit**} & \multirow{2}{*}{**Input**} & \multicolumn{2}{c}{**Transient Fault Rate (\%)**} & \multirow{2}{*}{**Error (\%)**} & \multicolumn{2}{c}{**Runtime (s)**} \\ \cline{3-6}  & & **MC** & & **PVTC** & & **MC** & **PVTC** \\ \hline \multirow{3}{*}{NAND Gate} & 00 & 0.81 & 0.88 & 8.6 & \multirow{3}{*}{220} & \multirow{3}{*}{0.41} \\  & 01 & 8.98 & 9.11 & 1.4 & & \\  & 11 & 7.52 & 7.46 & \(-\)0.8 & & \\ \hline \multirow{3}{*}{NOR Gate} & 00 & 15.47 & 14.80 & \(-\)4.3 & \multirow{3}{*}{230} & \multirow{3}{*}{0.39} \\  & 01 & 4.77 & 4.41 & \(-\)7.5 & & \\ \cline{1-1}  & 11 & 0.23 & 0.21 & \(-\)8.7 & & \\ \hline FA Sum & 000 & 22.71 & 22.88 & 0.7 & 452 & 1.0 \\ \hline FA Carry & 000 & 2.57 & 2.55 & \(-\)0.8 & 452 & 1.8 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Comparison of the results of the probability voltage transfer characteristics (PVTC) method and Monte Carlo (MC) simulation.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Logic Circuit**} & \multirow{2}{*}{**Input**} & \multicolumn{2}{c}{**Transient Fault Rate (\%)**} & \multirow{2}{*}{**Change Rate (\%)**} \\ \cline{3-4}  & & **Fresh** & & **Degraded** \\ \hline \multirow{3}{*}{NAND Gate} & 00 & 0.88 & 1.03 & +17.1 \\  & 01 & 9.11 & 10.11 & +11.0 \\  & 11 & 7.46 & 6.51 & \(-\)12.7 \\ \hline \multirow{3}{*}{NOR Gate} & 00 & 14.80 & 16.89 & +14.1 \\  & 01 & 4.41 & 3.78 & \(-\)14.3 \\ \cline{1-1}  & 11 & 0.21 & 0.16 & \(-\)23.8 \\ \hline FA Sum & 000 & 22.88 & 25.11 & +9.8 \\ \hline FA Carry & 000 & 2.55 & 3.22 & +26.3 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Comparison of the transient fault rate before and after negative bias temperature instability (NBTI) degradation.