# Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication
## 3 Combined Min-Sum Algorithm
For QC-LDPC codes, the parity-check matrix \(H\) of size \(M\times N\) (where \(M=m_{b}\times Z\); \(N=n_{b}\times Z\)) is partitioned into \(L\) horizontal decoding block layers. Each decoding block layer contains \(m_{b}/L\) consecutive block rows of \(H\), such that any variable node is connected at most once to any block layer. We denote \(\mathcal{M}_{l}\) as the set of consecutive block rows of \(H\) corresponding to block layer \(l\in\{1,...,L\}\). For the sake of simplicity, each decoding block layer \(L\) in this work is assumed to contain only one block row, i.e., \(L=m_{b}\). In addition,  
Figure 3: Schematic representation of base matrix base graph (BG)1 defined by 5G NR standard for generating a QC-LDPC code of code length \(N=3808\) bits, code rate \(R=1/3\), and \(Z=56\). \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**No. of Rows**} & \multicolumn{8}{c}{**Check Node Degree \(d_{c}\)**} \\ \cline{2-9}  & **3** & **4** & **5** & **6** & **7** & **8** & **9** & **10** & **19** \\ \hline in BG1 & 1 & 5 & 18 & 8 & 5 & 2 & 2 & 1 & 4 \\ \hline in BG2 & 6 & 20 & 9 & 3 & 0 & 2 & 0 & 2 & 0 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Check node degree \(d_{c}\) distribution for 5G NR LDPC codes. \(R_{m,n}\) denotes the check-to-variable message conveyed from check \(m\) of \(l\)th layer to variable node \(n\). \(L_{m,n}\) represents the variable-to-check message from variable node \(n\) to check node \(m\). In the \(i\)th iteration, the LLRs message from layer \((l-2)\) to next layer \(l\) for variable node \(v\) is represented by \(P_{n}^{i}[l-2]\). The CMS decoding based on pipelined layered scheduling algorithm can be summarized in Algorithm 1. ``` Input: \(y=(y_{1},y_{2},...,y_{N})\in\mathcal{Y}^{N}\)\(\triangleright\) Received word Output: \(\hat{x}=(\hat{x}_{1},\hat{x}_{2},...,\hat{x}_{N})\in\{0,1\}^{N}\)\(\triangleright\



The overall decoder architecture is shown in Figure 4. First, the input MUX network aims at selecting between channel intrinsic messages (input LLRs) and LLR messages from the previous layer. It should be noted that intrinsic messages are used only at the initialization stage. Then, the input LLRs of \(w=4\) bits quantization is buffered in the input register memory banks, named by PMEM. The specific configuration of PMEM is presented in a later subsection. There are \(n_{b}=68\) output ports of PMEM and each one represents \(Z=56\) LLR values of \(w=4\) bits (i.e., \(Z\times w=224\) bits). Consecutively, these 68 outputs are fed to the switch network, which performs a circular shift to the LLR data read from PMEM to align variable nodes with appropriate check nodes based on \(H\)-matrix value. A decomposition unit (DCPU) is used for converting the \(d_{c}=19\) LLR outputs of 224 bits from the switch network into \(Z=56\) LLR combinations of \(d_{c}\times w=76\) bits. Then, these 56 LLR combinations of 76 bits and the output data fetched from check to variable messages (RMEM) are passed to \(Z=56\) check node-based processors. After performing check node and variable node processing, each of these \(Z=56\) check node-based processors (CNBPs) produces 76 bits updated LLR messages \(P_{n}\) and \(2(w-1)+\lceil log2d_{c}\rceil+d_{c}=30\) bits extrinsic check-to-variable messages \(R_{m,n}\) represented in compressed mode. The CNBP sends \(P_{n}\) messages to the combination unit (CMBU) for the next decoding layer and the compressed \(R_{m,n}\) messages to check-to-variable node memory RMEM for the next iteration. The CMBU performs the reverse operation of DCPU that converses \(Z=56\) updated LLR combinations of 76 bits into \(d_{c}=19\) LLR outputs of 224 bits. It should be noted that the compressed \(R_{m,n}\) messages from RMEM are fed back to CNBP units through the decompress units (DECOM). Various blocks in the decoder architecture are explained in detail in the following subsections.