## 1 Introduction  
In the semiconductor manufacturing industry, chip testing directly affects the quality and reliability of final products [1]. Each chip must pass through rigorous electrical characteristics tests, including probe testing and functional testing [2], in order to ensure the chip meets the predetermined performance standards before entering the market. In addition to traditional testing methods, the semiconductor testing field has begun to adopt cutting-edge technologies such as quantum dot testing and electromagnetic characteristic analysis [3]. These technologies aim to explore the micro-level electrical characteristics and failure modes of chips. The development of Automatic Test Equipment (ATE) [4] has significantly facilitated the implementation of large-scale chip testing, which continues to expand its operation spheres to include higher speeds, larger ranges, and lower costs. This implementation has moved at superhigh speeds, increasing testing efficiency and coverage, and decreasing the false negatives and false positives. At the same time, the application of artificial intelligence and machine learning has enhanced the optimization of testing processes and the precision of defect detection [5]. The establishment and implementation of international standards such as IEEE 1149.1 (JTAG) [6] have provided a uniform and standardized framework for global chip testing practices. With the emergence of technologies like IoT, 5G communications, and AI, chip testing has welcomed new opportunities and challenges, leading to innovative developments in testing technologies that improve and ensure quality assurance in chip design and manufacturing [7]. Chip testing not only helps to identify and eliminate defective chips but also provides the basis for chip grading [8]. Although chips that have passed basic quality control still pose a failure risk, this risk is often related to the chip's performance stability under different working conditions [9; 10]. Through refined grading, manufacturers can optimize resource allocation by using high-performance chips for applications with stringent requirements and assigning lower-performance chips to other applications which are sensitive to cost [11]. This strategy not only optimizes resource use and enhances the market competitiveness of product lines [12], but it also reduces potential safety issues caused by chip failures. Chip grading serves not only advancing technology but also controlling costs [13; 14], thereby impacting competitiveness. With the pace of development within the industry, it has become overwhelmed with chip design and manufacturing, with rising demands for grading and quality control. Traditional chip grading methods rely on static testing and electrical measurements [15], which are increasingly inefficient in rapidly changing production lines, often resulting in the inaccurate characterization of minute performance differences. This ultimately leads to incorrect grading, raising the cost of high-density integrated circuits and high-performance chips [16]. Additionally, traditional testing equipment is physically limited in sensitivity and accuracy, so it cannot catch the very subtle instances of incorrect grading, which in turn negatively influences the accuracy and trustworthiness of the grading [17]. As a result, unified testing standards can no longer meet the needs of modern high-performance, high-reliability integrated circuits [18; 19]. To accommodate the increasingly complex designs and production demands of integrated circuits, manufacturers and research institutions are adopting a variety of cutting-edge technologies and methods to improve the accuracy and efficiency with which chips can be graded [20]. Dynamic testing technologies enable more comprehensive performance evaluations under simulated real-world conditions [21], examining basic electrical characteristics, analyzing long-term variability, and investigating failure modes.