## 5 Hardware Implementation and Experimental Results
### Discussion  
The overall design process of the proposed DFE is shown in Figure 38, composed of three stages, namely, calculation of the filter specification, calculation of the filter coefficients, and simulation of the DFE together with the OFDM receiver model. From the chosen decimation ratio of each filter, the filter specification was calculated, followed by the calculation of the FIR filter coefficients. Subsequently, with the calculated filter coefficients and the data bitwidths (set by the fixedDT class), the DFE together with the OFDM receiver model was simulated to draw the mean SNR performance (and the area, which is typically proportional to the no. of filter coefficients). If the SNR is not met or if more than enough margin is left for the filter specification, this process is repeated to explore the design space and to optimize the overall system through manual tweaking of the decimation ratio, the filter specification, and the bitwidths, in this order. This design process was more specified with a simple example for each stage of the design process in Figure 38. The first stage of the design process in Figure 38 was the calculation of the filter specification. To explain the first stage, three design options are illustrated in Figure 39, differing in the respective decimation ratios across the CIC filter, the FSRC filter, and the FIR4 filter. The decimation ratio of each filter determines the sampling rate or frequency \(f_{s}\) of the filter. On the other hand, various blocker and adjacent channel selectivity requirements (coming from the standard spec itself) determines \(f_{pass}\), \(f_{stop}\), \(\Delta f=f_{stop}-f_{pass}\), \(\delta_{s}\), and \(\delta_{p}\), where \(f_{pass}\) is the passband frequency, \(f_{stop}\) is the stopband frequency, \(\Delta f\) is the transition width, \(\delta_{s}\) is the stopband attenuation or suppression, and \(\delta_{p}\) is the passband ripple, respectively. Next, from the computed filter specification, the no. of filter coefficients was calculated in the way illustrated in Figure 40 [25]. If, for instance, \(f_{s}\) equals 30.72 MHz, \(f_{pass}\) equals 9 MHz, and \(f_{stop}\) equals 10 MHz, then the no. of filter coefficients, \(N\), is readily calculated from Figure 40. The filter coefficients themselves were obtained on the basis of Parks-McClellan optimal FIR filter algorithm [26]. Finally,  
Figure 36: Breakdown for digital signal processor (DSP) slice use. Figure 37: P&R timing report of the proposed DFE. corresponding to the third stage of the design process in Figure 38, the overall DFE with the OFDM receiver model was simulated after the filter coefficients of all the filters are obtained. Figure 41 illustrates the mean SNR values of options 1, 2, and 3 in (a), (b), and (c), respectively. The design space of the overall DFE system was explored for, for example, the three design options or candidates. From the worst case standpoint, the mean SNR values of option 1, across the six cases or frequency modes, leave higher margins above the required SNR of 40 dB, when compared with those of options 2 and 3, and hence option 1 will be chosen in this case. Figure 42 illustrates the sum of the no. of filter taps of the FIR4 and FIR5 filters. Up to case number 6 (i.e., without CA), option 1 served better in terms of the area. If all the cases are considered (including cases 7, 8, and 9 with CA), option 2 is in practice tantamount to option 1. Similar to the aforementioned example design options 1, 2, and 3, various candidates in the architecture design space were evaluated before the final DFE architecture was proposed. Figure 39: Example design options 1, 2, and 3 in (**a-c**), respectively, in terms of the partitioning of the overall decimation ratio 8. Figure 40: Parameters of the filter specification and the number of filter coefficients, assuming frequency mode 1 and 20 MHz bandwidth (BW).