## 5 Performance Evaluation
### Computation Overhead
Table 4 also presents the measurement results of the EC operations, the hash function, and basic operations on big numbers used in the proposed protocol. The measurement was conducted on two different Rocket cores with two configurations: RV32I and RV32 IMAC. \begin{table}
\begin{tabular}{l l c c} \hline \hline
**Notation** & **Description** & **RV32-IMAC \#Cycle** & **RV32-I \#Cycle** \\ \hline \(T_{h}\) & Hash function & 13,943 \(\pm\) 10 & 14,178 \(\pm\) 7 \\ \(T_{sm}\) & ECC scalar multiplication & 129,821,421 \(\pm\) 26,894 & 136,189,184 \(\pm\) 17,860 \\ \(T_{a}\) & ECC point addition & 266,589 \(\pm\) 32 & 274,658 \(\pm\) 13 \\ \hline \(T_{r}\)* & Random number generation & 80,649 \(\pm\) 20 & 82,349 \(\pm\) 9 \\ \(T_{puf}\)* & PUF function & 135,810 \(\pm\) 14 & 137,442 \(\pm\) 28 \\ \(T_{mod}\) & Modulo & 23,711 \(\pm\) 4 & 25,160 \(\pm\) 18 \\ \(T_{ba}\) & Big number addition & 698 \(\pm\) 2 & 838 \(\pm\) 1 \\ \(T_{bm}\) & Big number multiplication & 5009 \(\pm\) 5 & 5075 \(\pm\) 6 \\ \hline \hline \end{tabular}
* Timing varied depending on the design and system implementation of the primitives.  
\end{table} 
Table 4: Computation notation and timing of elliptic curve computations. Figure 3: A 32-bit IMAC RISC-V system. \begin{table}
\begin{tabular}{l c c} \hline \hline
**Protocol** & **Sensor Node** & **Sever** \\ \hline Ours—level 2 & \(4T_{sm}+2T_{a}+T_{h}\) & \(3T_{sm}+T_{a}+3T_{h}\) \\ Ours—level 1 & \(2T_{sm}+T_{a}+2T_{h}\) & \(2T_{sm}+2T_{h}\) \\ [14] & \(2T_{sm}+3T_{h}\) & \(2T_{sm}+3T_{h}\) \\ [28] & \(4T_{sm}+3T_{h}\) & \(5T_{sm}+5T_{h}\) \\ [29]—Protocol 1 & \(11T_{sm}+3T_{a}+10T_{h}\) & \(4T_{sm}+T_{a}+8T_{h}\) \\ [29]—Protocol 2 & \(5T_{sm}+2T_{a}+7T_{h}\) & \(3T_{sm}+T_{a}+7T_{h}\) \\ [30] & \(5T_{sm}+T_{a}+16T_{h}+T_{f}^{*}\) & \(4T_{sm}+T_{a}+8T_{h}\) \\ \hline \hline \end{tabular}  
* \(T_{f}^{*}\): fuzzy extractor.  
\end{table} 
Table 5: Computation cost comparison. The notations I and IMAC describe the extension of the instruction set architecture used to design the Rocket core. The extension I is the base integer instruction set that can support various operating environments. The extension M contains instructions that support multiplication and division. By default, the RV32I can emulate any extension; however, this experiment aimed to test the significance of other extensions on computing the proposed protocol. The measurement exposed the core operations of each computation to reduce the increase in the cycle count of branching and other operations of the program. It was expected that the ECC scalar multiplication required the most computing effort. The measurement results show that the RV32 IMAC with more instruction extensions and hardware cost could achieve a lower cycle count when processing the computations, however the performance improvement was insignificant. In specific, the ECC scalar multiplication could achieve only a 5% increase in performance. We conducted another timing measurement to assess the execution of the proposed protocol on the Rocket RV32 IMAC. The operation of the RISC-V system was expected to be the same as if it was operating at a sensor node. The computations of the protocol were broken down into smaller steps. The timing measurement was conducted to wrap around a function that computed all of the operations in a single step. Table 6 shows the cycle count and execution time of the system running at a 50 MHz clock supply. Based on the experimental results, the RISC-V Rocket core with extra extensions and hardware cost could not deliver a noticeable increase in computing efficiency compared with the default ISA. Therefore, the base configuration Rocket RV32I is suitable as the central processing unit for resource-constrained sensor nodes. To further improve the performance of computing the EC operations, an accelerator designed specifically for EC multiplication attached to the Rocket core as a RoCC, an accelerator connected directly to the Rocket core, is a direct and cost-effective solution.