# Stability of Single Electron Devices: Charge Offset Drift
## 2 Experimental Observations of Charge Offset Drift
### Mixed Devices  
The observations of charge offset drift which have been enumerated so far paint a striking dichotomy between metal-based devices and silicon-based devices. This drives a measurement of charge offset drift on a device where the SED quantum dot is formed in silicon with Al gates [48]. Devices based on this architecture have been extremely successful as quantum information devices and have recently been used to demonstrate the first two-qubit gate in silicon [24]. Earlier, the same group fabricated SEDs within 100 nm of each other to use one as a sensor of charge transitions on the other [35]. To be sensitive, the sensor SED has to remain on the steep portion of the SED curve at low bias shown schematically in Figure 1. To combat the charge offset drift induced excursions in the operating point of the sensor, the authors implemented a computer-controlled feedback loop to return the sensor to the appropriate place on the sensor control curve.  
A similar device which contained only one SED was examined in reference [48]. The device is shown in an SEM micrograph in Figure 10 along with the measurement circuit. It consists of two barrier gates labeled B1 and B2. Two \"lead gates\" (labeled L1 and L2) provide carriers out to the heavily-doped source and drain without inducing a large number of electrons on the island. The island potential is modulated with the plunger gate labeled as P. The corresponding charge offset drift data appears in Figure 11. The size of the drift, \(\Delta Q_{0}\approx 0.15e\), is a value intermediate between that of silicon based devices and that of metal based devices. This is a powerful result. One might  
Figure 9: Power spectral density of an Si/SiO\({}_{2}\) device measured at two different gate voltages and over the course of two months including several thermal cycles. The upper cluster of curves at \(V_{G}=3.475\) V, indicates that a single two-level system (TLS) dominates at this gate voltage. Orders of magnitude less noise is obtained at \(V_{G}=3.25\) V. The black curve is a fit to a Lorentzian. Reproduced with permission from reference [30], Copyright 2008, American Institute of Physics.  
expect that since the dot is formed in the silicon away from the Al gates and the tunnel barriers are created electrostatically, that the charge offset drift would be similar to an all-silicon device. The fact that it is not similar lends strong support to the discussion of glassy relaxation. A hint as to why this is the case is shown in Figure 10b. It shows a TEM micrograph taken from a slice of the device along the line from source to drain under gate P, the dot plunger gate. As is clear from the micrograph, the deposited Al and SiO\({}_{2}\) layer react to form a non-deliberate AlO\({}_{x}\) layer at the upper interface of the SiO\({}_{2}\) gate dielectric. This is an important fabrication feature in determining the level of charge offset drift in the device.  
Figure 11: Charge offset drift in the same device as in Figure 10. The size of the drift is \(\Delta\)\(Q_{0}\approx 0.15\)e, intermediate between all-silicon devices and Al/AlO\({}_{x}\) devices. The inset shows the Coulomb blockade oscillations which were used to extract the \(\Delta Q_{0}\) values. Data were obtained at a temperature of 2.2 K. Reproduced with permission from reference [48], Copyright 2014, Institute of Physics.  
Figure 10: SED made in silicon with Al gates. (**a**) micrograph of the device and the measurement circuit used for the charge offset drift measurement; (**b**) TEM micrograph of the device along the source to drain direction directly under the plunger gate, P. The micrograph shows that a non-deliberate AlO\({}_{x}\) layer forms at the interface between the SiO\({}_{2}\) gate oxide and the Al gates. Reproduced with permission from reference [48], Copyright 2014, Institute of Physics.