# A Multilevel Switched Capacitor Inverter with Reduced Components and Self-Balance
## 2 Design of Proposed SCMLI
### Operating Mode  
The proposed topology possesses a 13-level output and fourteen operating modes. The different switching modes and output levels are shown in Table 1, where \"0\" and \"1\" indicate the \"off\" and \"on\" statuses of the switches, respectively. The working conditions of capacitors are presented by \"C\", \"D\", and \"-\", which denote the charging, discharging, and idle states. A total of five complementary switch pairs are employed to prevent the capacitors from being short-circuited. Moreover, capacitors \(C_{1}\) and \(C_{2}\) have the same state and a high charging frequency, which is beneficial to diminish the capacitor voltage ripple and improve the waveform quality of the output voltage.  
Figure 3 shows the positive conducting paths in each operating state. Note that the lines highlighted in green represent the charging circuit of the capacitors, and that the lines highlighted in red represent the paths of the synthetic voltage level. In addition, the proposed 13-level topology can integrate the inductive load, because there is a reverse current path composed of capacitors and anti-parallel diodes. For the simplicity of analysis, the assumption is that all devices are ideal and that the voltages of capacitors \(C_{1}\) and \(C_{2}\) are  
\begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline \multirow{2}{*}{**Nodes**} & \multirow{2}{*}{**Output Voltage**} & \multicolumn{6}{c}{**Switches**} & \multicolumn{6}{c}{**Capacitors**} \\ \cline{3-10}  & & \(S_{1,2}\) & \(S_{3,4}\) & \(S_{5,6}\) & \(S_{78,9}\) & \(S_{10,11}\) & \(S_{12}\) & \(C_{1}\) & \(C_{2}\) & \(C_{3}\) \\ \hline
1 & +6 \(V_{\rm dc}\) & 01 & 10 & 10 & 01 & 01 & 0 & D & D & D \\
2 & +5 \(V_{\rm dc}\) & 01 & 10 & 10 & 10 & 01 & 0 & D & D & D \\
3 & +4 \(V_{\rm dc}\) & 01 & 10 & 01 & 10 & 01 & 0 & C & C & D \\
4 & +3 \(V_{\rm dc}\) & 01 & 10 & 10 & 01 & 10 & 1 & D & D & C \\
5 & +2 \(V_{\rm dc}\) & 01 & 10 & 10 & 10 & 10 & 0 & D & D & – \\
6 & +\(V_{\rm dc}\) & 01 & 10 & 01 & 10 & 10 & 0 & C & C & – \\
7 & 01 & 01 & 10 & 01 & 10 & 1 & D & D & C \\
8 & 0 & 10 & 10 & 10 & 01 & 10 & 1 & D & D & C \\
9 & \(-V_{\rm dc}\) & 10 & 01 & 01 & 10 & 10 & 0 & C & C & – \\
10 & \(-2\)\(V_{\rm dc}\) & 10 & 01 & 10 & 10 & 10 & 0 & D & D & – \\
11 & \(-3\)\(V_{\rm dc}\) & 10 & 01 & 10 & 01 & 10 & 1 & D & D & C \\
12 & \(-4\)\(V_{\rm dc}\) & 10 & 01 & 01 & 10 & 01 & 0 & C & C & D \\
13 & \(-5\)\(V_{\rm dc}\) & 10 & 01 & 10 & 10 & 01 & 0 & D & D & D \\
14 & \(-6\)\(V_{\rm dc}\) & 10 & 01 & 10 & 01 & 0 & D & D & D \\ \hline \hline \end{tabular}
\end{table}
Table 1: Operating modes of the proposed MLI.  
Figure 1: Proposed 13–level SC inverter.  
Figure 2: Working states of switched capacitors. (**a**) Charging of \(C_{1}\) and \(C_{2}\) in parallel. (**b**,**c**) Discharging of \(C_{1}\) and \(C_{2}\) in parallel/series.  
constant at \(V_{\rm dc}\), while the voltage of capacitor \(C_{3}\) is constant at \(3~{}V_{\rm dc}\). The positive polarity voltage is generated when switches \(S_{2}\) and \(S_{3}\) are turned on, and the negative polarity voltage is generated when the switches S\({}_{1}\) and S\({}_{4}\) are turned on.