## 3 Implementation and Measurement  
### Experimental Setup Testbed  
The experimental setup considers the acquisition of real-valued data from several run tests to calculate CFR, PAPR, and ACPR signal measurements considering the DUT. Figure 5 shows the developed SDR testbed used to obtain the experimental results, it consists of a radio frequency system-on-chip with a \(2\times 2\) board dual channels of the I and Q reception quadrature signals, these pass through a type finite impulse response (FIR) filtering stage to be handled by an adjustable internal sampling rate to produce a 12-bit output signal up to 122.88 MS/s according to the signal bandwidth requirements. The DUT considers a ZK60-5619 MA+ amplifier with 50 ohms output impedance, which is used with  
Figure 4: LTE 5-MHZ and 10–MHz signal PAPR vs. output power level with and without CFR applied. Figure 3: (a) LTE-5 and (b) 10–MHz actual signal vs. CFR signal for time samples. 5 V bias with a typical gain of 17.27 dB for 2 GHz band applications. A libiiio library is run on this embedded Linux to provide a full-duplex communication between the data from MATLAB and the FPGA hardware modules. For the RF transceiver board AD9361; MATLAB sends the data to the FPGA; the data link is made over Ethernet between the ADI Hardware system connected to the FPGA-SoC platform that runs on ADI Linux. The RF transceiver performance provides a narrow range from 2.4-2.5 GHz to support signals up to 56-MHz using a dual 12-bit DACs with a synchronization clock set at 245.76 MHz. The up-conversion path uses an I/Q modulator driven by an internal local oscillator (LO) operating at the frequency of 2.40 GHz to generate the RF signal. The LO is provided internal and operates from 47 MHz to 6.0 GHz. To perform the test and evaluation of the proposed methods, separate experiments are carried out. The first measurement tests are conducted with the identification of CFR, ACPR, and PAPR, to estimate the values in a feedback iterative procedure. The measurement system includes the FPGA, RF transceiver dual-channel sub-6 GHz, wideband amplifier ZX60-5916 MA-S+ that feature a typical gain \(\approx\) 17.33 dB biasing with 5 V. At the feedback path, a receiver is used to digitize the down-converted signal using an I/Q demodulator operated at a sampling rate of 245.76 MHz, while an interpolation filter is applied as data rate is set for a given bandwidth. Here OFDM symbols and subcarrier EVM (%) against subcarriers in the frequency domain and symbols in the time domain are described. In this case, the EVMs are calculated for each carrier within a frame and the peak values are displayed in the 3D graphic, the EVMs for each carrier are shown for 64-QAM using frequency division duplex (FDD). In this implementation, the EVM performance is evaluated based on a reference measurement channel (RMC) for a downlink test. The digitally modeled signal to measure the peak and root mean square (RMS) EVM average of the input signal frames. For the output DUT amplifier measurement, a SIGLENT SSA3032X was carried out for analysis in the frequency domain. In this case, the setup for the analysis of EVM, PAPR, and ACPR are developed in MATLAB through the LTE toolbox and the RF Blockset models for Analog Devices RF Transceivers. The data input is sent from the host computer, and the ARRadio card setting tests operates with an AD9361 RF transceiver using a carrier  
Figure 5: Experimental testbed photograph. Relevant instruments depicted as follows. (**A**): Altera Cyclone V FPGA SoC-Kit. (**B**): AD9361 RF Agile Transceiver working at 2.40 GHz center frequency. (**C**): High isolation amplifier Mini-Circuits ZX60-5916 MA+. (**D**): Power Supply GW INSTEK GPS-3303. (**E**): Display HOST PC-MATLAB. (**F**): Spectrum Analyzer SIGLENT SSA3032X. frequency 2.40 GHz and an LTE 10-MHz with a sampling rate of 245.76 MHz and 122.88 for the LTE 5-MHz and performed for a IFFT size of 1048.