# Parasitic-Based Active Gate Driver Improving the Turn-On Process of 1.7 kV SiC Power MOSFET
## 3 Simulation Study  
The proposed AGD circuit in the DPT configuration is presented in Figure 3. The chosen device is a half-bridge module (CAS300M17 BM2), so the AGD is controlling only transistor \(T_{2}\) (see Figure 3) during the DPT. \(T_{2}\)'s gate current \(i_{\text{G}}\) is actively controlled by the AGD with the previously described method and \(T_{1}\)'s gate is connected constantly to \(-5\) V (in reference to its source). In this particular case, \(L_{S}\) is equal to 15 nH based on the datasheet. Simulation verification of the proposed AGD multi-level gate voltage method based on the parasitic inductance voltage measurement was conducted in Saber RD software. The CAS300M17 BM2 module simulation model was provided by the producer of the device. The first steps of the research were to observe the waveforms of \(V_{\text{Ls}}\) with CGD and, basing on this, conclude if the method can be used in all SiC MOSFETs. The purpose of the simulation study was to verify the assumptions about the decrease in the turn-on time and energy in the chosen method. Finally, the main aim of the simulation was to measure power losses of the CGD at the turn-on cycle and compare them with the AGD. In simulations, the SiC MOSFET half-bridge module was connected in the DPT setup (Figure 3). Transistor \(T_{1}\) was turned off and \(T_{2}\) was the DUT. The gate resistance \(R_{\text{G}}\) of both the AGD and CGD was set to a fixed value of 20 \(\Omega\). The main assumption of the similar value of the \(R_{\text{G}}\) in tests  
Figure 3: The AGD in DPT setup with half-bridge module 1.7 kV/325 A SiC MOSFET CAS300M17 BM2. of the AGD and CGD was to obtain the same \(di_{\rm D}/dt\) ratio at the turn-on of the device for both cases. \(T_{1}\) was connected in parallel to the inductor \(L=110\)\(\mu\)H. The CGD gate voltage \(V_{\rm GG}\) was fixed at a value of 15 V at the turn-on (according to datasheet recommendations). The AGD gate voltage \(V_{\rm GG}\) (Figure 2) had a variable value of either 15 or 30 V. The AGD simulation was conducted using the feedback signal from \(V_{\rm Ls}\), which was connected to the Saber RD logical and electrical elements to provide the active control of the \(V_{\rm GG}\) voltage. Delays of the components were not considered in that stage of the research. The DPT was conducted for four operating conditions at the turn-on cycle for the \(V_{\rm DD}\) voltages of 700 or 900 V and \(I_{0}\) currents of 170 or 270 A. However, the observations of the response of the AGD on the increasing \(I_{0}\) current had smaller step of change to verify that this solution is independent from the variation in the drain current. The turn-on cycle using the CGD for \(V_{\rm DD}=700\) V, \(I_{0}=\)270 A is shown in Figure 4. In comparison, the turn-on cycle with the AGD for the very same conditions is shown in Figure 5, where the difference in the voltage falling time is visible. The \(vds/dt\) ratio increased without any serious oscillations of \(i_{\rm D}\), thus shortening the turn-on cycle of the device. Notice that in Figures 4 and 5, the \(i_{\rm D}\) rising time is marked, and in both simulated cases, the \(di_{\rm D}/dt\) ratio was the same (1 kA/us) due to identical \(R_{\rm G}\) values and \(V_{\rm GG}\) levels in \(\Delta t_{21}\) (see Figure 2). Additionally, the simulations show that the AGD compensates the delay between the rising of the \(v_{\rm GS}\) voltage and the moment when the device starts to conduct the drain current. Table 1 presents the results of the previously mentioned simulation. The turn-on energy mostly decreased for \(V_{\rm DD}=900\) V, \(I_{0}=270\) A. The turn-on energy settled at 65.5 mJ for the CGD, whereas for the AGD, it reached just 45.9 mJ, resulting in a difference of roughly 30%. The smallest percentage disparity was measured for \(V_{\rm DD}=900\) V, \(I_{0}=170\) A, and it was equal to 15%.