# A 4.1 W/mm\({}^{2}\) Hybrid Inductive/Capacitive Converter for 2-140 mA-DVS Load under Inductor +
## 2 Architecture
### Capacitive Converter  
Switched capacitor (SC) or capacitive DC-DC converters have gained popularity in recent years due to ease of implementation and fairly high efficiencies. These capacitive converters use only capacitance to achieve the desired voltage conversion. The capacitive converter consists of bucket capacitors which transfer the charge from the input supply to the tank capacitor by a periodic switching action. The tank capacitor filter the current to the load. In a typical closed loop scenario whenever the output voltage drops below the reference voltage (desired output voltage), transfer of charge from the input to output is initiated by a hysteresis based controller. Figure 6 shows functional description of a pair of 2:1 converters (in IPO-OPG topology) [25] connected in parallel where the no-load output voltage of each copy is equal to \(V_{in}/2\). The efficiency of capacitive converter is given by \(V_{out}/V_{max}\) where \(V_{max}\) is the maximum output voltage that can be achieved by the converter under no-load condition i.e., \(V_{in}/2\). The maximum load current supplied by the above mode is given by \(I_{out}=4 nC_{bucket}f(V_{in}/2-V_{out})\) where \(f\) is the frequency of switching, \(C_{bucket}\) is the size of each bucket capacitor and n is the number of bucket capacitors connected in parallel. Figure 7 shows the transformer model for the capacitive converter as discussed in detail in [25]. Through Figure 7 it can be inferred that the converter achieves maximum efficiency at no-load voltage(\(V_{max}\)) but losses the capability to deliver any power to the output. So, there his a tradeoff between the maximum current transferred and efficiency achieved for a given capacitive converter.  
Figure 5: (a) Signal coupling to the inductor from digital circuits underneath (b) Signal coupling from the inductor to digital circuits underneath.  
Figure 6: Block diagram for a two phase interleaved IPO-OPG capacitive converter.  
Figure 6 shows a two phase interleaved converter where there are exactly two copies of similar converters switching with a phase shift of 180 degrees. This implementation reduces the output voltage ripple by effectively doubling the operating frequency. Figure 8 shows the actual circuit level implementation of capacitive converter part of the hybrid converter. PMOS and NMOS devices are used as switches and deep trench capacitors are used as bucket capacitors. This implementation is designed to operate when the output voltage ranges from 0.4-0.55 V at an input of 1.2 V.  
For our DVS load the switched capacitive converter is enabled by a state machine when the reference voltage is lower than 0.55 V which is based on the calculations of Equation (5). In this prototype a single mode (IPO-OPG) [23] capacitive converter which is 2-phase interleaved  
Figure 8: Complete circuit implementation for the capacitive converter including the control loop.  
Figure 7: Transformer model for the capacitive converter and the corresponding output load line characteristics [25].  
has been implemented. The IPO-OPG configuration achieves a maximum conversion ratio of 2:1 (Vout = Vin/2). The complete capacitive converter configuration that was implemented is shown in Figure 8. A single bound hysteretic controller achieves the regulation. In this type of control the output voltage is compared with the reference voltage and when the output voltage dips below the reference voltage a switching action is initiated to transfer a quanta of charge from the supply to the output. In this implementation, single capacitive converter mode has been implemented but multiple modes can be easily implemented and the appropriate mode selected by the state machine based on the reference voltage.