## 3 The Proposed Circuits
### Complexity Estimation for the Proposed Circuits  
Table 7 shows a comparison with the reference design [2]. The QCA implementation for the proposed FG gate for the QCA parameters, such as area, delay, and number of consumed cells had 0.010 \(\upmu\)m\({}^{2}\) consumption area, 0.25 delay clock, and 11 QCA cells, respectively. For the proposed TR gate, it had 0.073 \(\upmu\)m\({}^{2}\) consumption area, 1.5 delay clock, and 64 QCA cells, respectively. The QCA circuit for the proposed 1-bit reversible comparator also had 0.237 \(\upmu\)m\({}^{2}\) consumption area, 3.0 delay clock, and 165 QCA cells, respectively.  
On the other hand, considering the design of complex gates and circuits, determining the best way to design the wires crossovers, in order to reduce the cost, is very important [6]. In the design of wires crossovers, the design of coplanar crossovers using non-adjacent clock phases, in addition to being implemented and designed in a single layer, has a lower implementation cost and is the best type, compared to other types of wires crossover implementations. As a result, as compared in the table, all our designs are implemented on a single layer and as a coplanar design. Additionally, the power delay product evaluation criterion (PDP), based on [16], using the QCADesignerE software, is illustrated in Table 7. A frequency of 1 THz was considered to calculate PDP. As can be seen in Table 7, the powers of the proposed FG gate, TR gate, and 1-bit comparator circuit were 11.47 \(\times\) 10\({}^{-10}\)  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Proposed Reversible Circuits** & **Circuit Cost** & **Quantum Cost** \\ \hline FG & 1\(\alpha\) & 1 \\ TR gate & 2\(\alpha+1\beta+1\gamma\) & 4 \\
1-bit comparator & 5\(\alpha+2\beta+3\gamma\) & 9 \\ \hline \hline \end{tabular}
\end{table}
Table 6: Quantum cost for QCA layout the proposed reversible circuits.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Proposed Reversible Circuits** & **Area Cost** & **Delay Cost (Power (W) (Power \(\times\) Latency))** & **Crossover Type** \\ \hline FG [2] & 0.023 & 37 & 0.75 & 0.013 & 23.23 \(\times\) 10\({}^{-10}\) & 17.42 \(\times\) 10\({}^{-22}\) & Multi-Layer \\ \hline TR gate [2] & 0.090 & 122 & 1.0 & 0.090 & 73.86 \(\times\) 10\({}^{-10}\) & 73.86 \(\times\) 10\({}^{-22}\) & Multi-Layer \\ \hline
1-bit comparator [2] & 0.343 & 319 & 3.0 & 3.087 & 161.8 \(\times\) 10\({}^{-10}\) & 485.4 \(\times\) 10\({}^{-22}\) & Multi-Layer \\ \hline Proposed FG & 0.010 & 11 & 0.25 & 0.0006 & 11.47 \(\times\) 10\({}^{-10}\) & 2.867 \(\times\) 10\({}^{-22}\) & Coplanar \\ \hline Proposed TR gate & 0.073 & 64 & 1.5 & 0.164 & 27.56 \(\times\) 10\({}^{-10}\) & 41.34 \(\times\) 10\({}^{-22}\) & Coplanar \\ \hline Proposed 1-bit comparator & 0.237 & 165 & 3.0 & 2.133 & 58.32 \(\times\) 10\({}^{-10}\) & 174.96 \(\times\) 10\({}^{-22}\) & Coplanar \\ \hline \hline \end{tabular}
\end{table}
Table 7: Comparison for the proposed QCA reversible circuits of previous works.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Proposed Reversible Circuits** & **Area Cost** & **Latency Cost** \\ \hline FG & 0.010 & 0.25 & 0.0006 \\ TR gate & 0.073 & 1.50 & 0.164 \\
1-bit comparator & 0.237 & 3.0 & 2.133 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Quantum cost for the proposed reversible circuits.  
27.56 \(\times\) 10\({}^{-10}\), and 58.32 \(\times\) 10\({}^{-10}\) (W), respectively. The proposed FG gate, TR gate, and 1-bit comparator showed improvements of 50.62%, 62.69%, and 63.95%, respectively, in comparison to the power parameter compared to the design [2]. Additionally, the PDP parameters for the proposed FG gate, TR gate, and 1-bit comparator circuit were 2.867 \(\times\) 10\({}^{-22}\), 41.34 \(\times\) 10\({}^{-22}\), and 174.96 \(\times\) 10\({}^{-22}\) (Ws), respectively. As a result, in terms of the PDP parameter, the proposed FG gate, TR gate, and 1-bit comparator circuit, compared to [2], were superior at about 83.54%, 44.03%, and 63.95%, respectively.