## 5 Implementations
### The System-on-Chip  
In this paper, LiteX [44] was used as an SoC building framework, interconnecting components and invoking suitable toolchains to synthesize and deploy the design in an FPGA. The VexRiscv processor core with the Wishbone bus configuration was the first component to be initialized in the system, along with other peripherals, forming a basic SoC. All accelerator core designs in Verilog HDL were added later in the process. LiteX also  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Name** & **Address** & **Description** \\ \hline Reset & 0x00 & Set and reset input \\ Input & 0x01 & 32-bit input register \\ Byte Number & 0x02 & Set index of last byte \\ Input Last & 0x03 & Set the last input and start \\ Status & 0x09 & Accelerator status bit \\ Hash Output & 0x10–0x1F & 512-bit hash output registers \\ \hline \hline \end{tabular}
\end{table}
Table 4: Internal register address mapping for the SHA3-512 core.  
Figure 10: The SHA3-512 accelerator architecture with bus interface.  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Name** & **Address** & **Description** \\ \hline Key Input & 0x10–0x17 & 256-bit key input registers \\ Nonce Input & 0x20–0x21 & 64-bit number-use-once registers \\ Data Input & 0x40–0x4F & Optional 512-bit message input registers \\ Data Output & 0x80–0x8F & 512-bit keystream output registers \\ Control & 0x08 & Accelerator control bit \\ Status & 0x09 & Accelerator status bit \\ Configuration & 0x30 & Accelerator configuration bit \\ \hline \hline \end{tabular}
\end{table}
Table 3: Internal register address mapping for the ChaCha accelerator.  
supports generating essential project files and constraints for the respective FPGA platform toolchain, which was Vivado in this work.  
Utilizing Migen, a Python-based fragmented hardware description language, the LiteX framework enables hardware cores and SoC systems to be designed with ease, experimenting with various digital design architectures and implementing them in various FPGA hardware platforms. By using the framework alongside the hardware cores library provided by the LiteX open-source community, including VexRiscv, a more-accessible building process of large and complex SoCs can be made, improving the portability and flexibility of the design process.  
The SoC was generated with the following configuration after calling the SpinalHDL generation process for the VexRiscv processor; the framework then started to compile and elaborate the system design based on the building script, and then started the FPGA synthesizing process, building the bitstream.  
* Single-core 32-bit VexRiscv processor (RV32 IM), 32-bit Wishbone Bus with 4 GB address space, 8 KB L1 cache (4 KB data cache and 4 KB instruction cache), and 8 KB L2 cache.
* Peripherals: UART, SPI, GPIO.
* Custom cryptographic accelerator cores for PRINCE, PRESENT-80, ChaCha, and SHA3-512.  
The proposed SoC architecture composed of a VexRiscv processor and lightweight cryptographic cores is presented in Figure 11. As briefly mentioned for the PRINCE accelerator core in Section 4.1, the Configuration/Status Register bus in LiteX is a mechanism for reading and writing values for the configuration registers of various intellectual property (IP) cores within the FPGA. It should not be conflated with CSRs as defined by the RISC-V ISA. This bus is used to control and monitor the behavior of the IP cores, such as setting up clock frequencies, enabling or disabling features, and reading status information. The CSR bus is an important feature in the LiteX SoC builder tool in building the proposed SoC, as it allows for a simple and flexible interface with the IP cores, making it easy to configure and control various components, including all of the lightweight cryptographic accelerator cores.