## 2 Materials and Methods
### Digital Signal Processing (DSP)  
The digital part of the SALT is clocked directly by the 40 MHz experimental clock, so its phase is different from the ADC sampling clock phase. Hence, before any data processing, the samples from ADC have to be handed over to the DSP clock domain. The common solution in such a situation, an asynchronous FIFO queue, is not a good choice for the SALT ASIC. First, although the relation between ADC and digital clocks may vary, they are not asynchronous since the phase shift is known (defined in the chip configuration). Second, in the radiation environment, some ADCs may incidentally receive an additional sampling pulse (because of SEE) permanently destroying data coherence (some FIFOs would be shifted). Therefore, a simple circuit consisting of two flip-flops connected in parallel, sampling data on a positive and negative clock edge, respectively, is used. At least one of the flip-flops samples ADC data correctly for any phase relation. For most cases both work correctly but the optimal one should be chosen taking into account timing margins. This solution makes the data coherence immune to SEEs. The ADC samples are encoded as 6-bit two's complement numbers. Signed numbers are necessary to cover both sensor polarities. The negative values are obtained for \(p^{+}\)-in-\(n\) sensors and merely for such samples an arithmetic inversion is performed. Thereby, the rest of the DSP chain, shown in the central part of Figure 5, was designed based on the assumption that all samples are positive. The first DSP operation is the masking of a noisy or dead channel. Such channels are completely removed from further data processing. In the next processing step, the pedestals, uploaded previously to the configuration registers, are subtracted. Therefore, in channels without a signal from the sensor (without a hit), the expected pedestal-subtracted value is zero. A common-mode disturbance could shift all channels coherently up or down. To remove this common-mode shift, a mean common mode MCM offset is computed, and subtracted. Only those channels with amplitude below a pre-defined MCM threshold contribute to the average. The choice of MCM threshold is a trade-off between the largest rejected disturbance and the smallest signal which may be detected. Both subtractions in pedestals and MCM are fragile operations since they may easily overflow their 6-bit representation. Hence, the saturation arithmetic is utilised here, i.e., the result is limited to the range between a minimum and maximum value of 6-bit two's complement number. The following step is the ZS, which eliminates all signals smaller than or equal to a non-negative ZS threshold (roughly 3-4 times the expected noise). At this stage, the ADC values are rounded to 5-bit precision because the negative part is no longer needed. According to simulations, the occupancy is about 1% or less, and therefore the ZS provides a very large reduction in the data that needs to be processed and transmitted. Data from the ZS block are sent directly to the packet builder (PCK), which creates data packets with the format specified in Table 2. The packets are stored in design-specific memory (MEM) in advance of their serialisation. During normal operation, the ASIC  
Figure 5: Data processing in the SALT; vertical lines separate clock domains; FE—analogue front-end, ADC—Analog-to-Digital Converter, Ped—Pedestal Subtraction, MCM—Mean Common Mode, ZS—Zero Suppression, PCK—Packet Builder, MEM—data memory, IDL—Idle Packets Generator, Ser—Serialiser, PLL—Phase-Locked Loop, DLL—Delay-Locked Loop. generates mostly packets with data compressed in the ZS block (Normal packets). However, for diagnostic and testing purposes, it is important that the chip can also transmit packets without compression, called NZS (Non-Zero Suppressed) packets, in response to a fast TFC command. The NZS packet contains raw ADC values or partially processed data (see alternative input of PCK block in Figure 5). Moreover, it includes the values calculated by the MCM algorithm, i.e.