## 2 Materials and Methods
### Adaptation Mechanism  
The structure of the proposed adaptation mechanism in general corresponds to the adaptation process described above and expressed by Equation (4). For each clock cycle, following components of the \(X\) pattern and the vector of neuron weights are provided to the inputs of this block. The final outcome is then computed in an asynchronous fashion. This results from the fact that particular components of this mechanism (Multi-bit full adder (MBFA), Multi-bit full subtractor (MBFS), and multiplier) are asynchronous circuits, leading to a very small delay. This allows obtaining a very high data rate. A first operation performed by the adaptation system is the subtraction of the \(X\) and the \(W\) signal (in following pairs \(x_{i}-w_{i,j}\)). The result of this operation can be positive or negative. In the second case, if the buffer length is too small (4 bits in this example case), then in two's complement code the result is incorrect. This problem propagates into the subsequent multiplication operation. For example, let us consider an example case in which \(x_{i}=3\) and \(w_{i,j}=13\). The subtraction result in this case equals \(-10\). In the two's complement code, assuming the buffer length of 4 bits, we get \"0100\". Multiplying this number by \(\eta=8/16\) leads (after the shift by 4 bits, required in this case) to the value of \"0010\", which corresponds to the number of 2. To avoid this problem, after the subtraction operation, the absolute value (abs) of the \(x_{i}(k)-w_{ij}(k)\) factor is determined. The sign of this factor is stored in a memory cell. As a result, the multiplication may always be performed with positive numbers. The result of the multiplication operation, \(P_{i,j}(k)\cdot|x_{i}(k)-w_{i,j}(k)|\), depending on the stored sign is then changed accordingly. In the case when the sign stored in memory is negative, the sign of the overall result is changed, which is carried out by subtracting the calculated result from the 0 number. In the situation, in which the sign is positive, the result remains unchanged. The EXOR gates used in the circuit are responsible for a proper interpretation of the signs and to ensure a proper operation of the overall adaptation mechanism. It is worth noting that, for \((x_{i}(k)-w_{i,j}(k))<0\), the EXOR gates behave as typical NOT gates. This allows easily performing either the addition or the subtraction operation, depending on the situation. The \(\eta(k)\cdot G()\cdot(x_{i}(k)-w_{i,j}(k))\) signal is, in the last step of the adaptation process, added to a given \(w_{i,j}(k)\) weight of a given neuron. The resultant \(w_{i,j}(k+1)\) substitutes then, in the memory, the previous \(w_{i,j}(k)\) value. Storing the new value into the memory takes place at the falling edge of the clock signal. Particular \(x_{i}\) and \(w_{i,j}\) signals are supplied sequentially to the described adaptation block (in each neuron). In this case, the use of a fully parallel approach would be ineffective, as it would require a very large number of external pads of the chip. For example, for ten \(x\) input signals and 16-bit resolution, it would be necessary to use 160 pads. Programmable Multi-Phase Clock Generator  
The proposed multi-phase clock generator has been implemented inside the chip, to reduce the number of external pins of the chip. Circuits of this type are usually implemented using a chain of D-flip flops (DFFs) [27; 28; 29; 30; 31; 32]. The advantage of such approach is the high immunity of the parameters of the clock to external conditions. However, there are also some disadvantages of such solutions. A typical DFF is composed of 26 transistors (six logic NAND gates). Two of these gates are switched over, even if there is no change at the D input of the DFF. These gates are switches over twice, i.e., during the raising and the falling edges of the controlling clock signal. In a typical multiphase clock generator, the input of only one DFF equals \"1\", however the power is dissipated by all DFFs in the chain.