# An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA
## 3 LDPC Codes in 5G-NR  
LDPC codes have been adopted by 5G standards because of their remarkable error correction performance for high codeword lengths and built-in parallelism for hardware implementation [16]. They specify a sparse M \(\times\) N Parity-Check Matrix (PCM) H that contains a much smaller number of 1s compared to 0 s [17]. For Hi, j represents the i-th column and j-th row of H, with N \(-\) M = K information bits and M parity bits, where the code rate is denoted as R = K/N. Furthermore, N and M represent the number of variable nodes (VNs) and check nodes (CNs), respectively. The j-th column represents the j-th VN (vi), and the i-th row represents the i-th CN (ci) [18]. Considering C = [x1, x2,..., xN], where xi \(\in\) [0, 1], C is a codeword if and only if  
\[\text{H}\cdot\text{C}^{\text{T}}=1 \tag{1}\]  
The weight (dci, dvi) is defined as the number of 1s within the rows and columns, respectively. The LDPC codes are classified into two categories; a regular code is when both dci and dvi are constant, otherwise, it is characterized as an irregular code [19]. During each iteration, the sum-product algorithm (SPA) [20] computes the extrinsic information of each node using the data received from their connected nodes. \[\text{l}_{\text{n}}=\log(\text{P}_{\text{r}}(\text{x}_{\text{i}}=0/\text{r}_{ \text{i}})/\text{P}_{\text{r}}(\text{x}_{\text{i}}=1/\text{r}_{\text{i}}))=2 \text{Y}_{\text{n}}/\sigma^{2} \tag{2}\]The a priori data (Y\({}_{\rm n}\)) refer to the received information (r\({}_{\rm i}\)) that represents the decoder input. The a posteriori (I\({}_{\rm n}\)) is the updated information, based on belief propagation according to the probabilities of the Log-Likelihood Ratio (LLRs) [11; 21]. Next, the CN units compute the new soft information based on the following equation:  
\[\rm f(x)=log\tanh(\,\rm{1}\,x\,\rm{1}\,/\,2) \tag{3}\]  
The VN units update the LLRs coming from the corresponding CNs as follows:  
\[\rm VN(Y_{\rm i})=Y_{\rm i,1}+Y_{\rm i,2}+\ldots+Y_{\rm i,n} \tag{4}\]  
Then, each VN sends the computed messages again to the corresponding CNs for the next iteration. The min-sum algorithm (MSA) simplifies the complexity of the sum-product [22; 23] by approximating the SPA function (Equation (3)) within the CN process into the minimum function:  
\[\rm CN(Y_{\rm i})=\Pi(sgn(Y_{\rm i})\cdot min(\,\rm{1}\,Y_{\rm i}\,\rm{1})) \tag{5}\]  
There have been numerous updates made to the MS algorithm, including Offset MS (OMS) and Adapted MS (AMS). The enhanced MS algorithms diminish the overestimation of message magnitudes [11; 12]. The LDPC codes in conformity with 5G standards recognize a significant breakthrough relating to decoding performances and the length of transmitted data [24; 25]. They constitute a family of QC-LDPC codes, which can be described by the use of protograph codes [26; 27]. A protograph code is defined by its matrix Hp = Mp \(\times\) Np and its expansion factor Z [28; 29; 30]. The values of the lifting size (Z) fall within an integer range (\(2\leq Z\leq 384\)). The entries (Hp(i,j)) of the matrix Hp would be from \(-1\) to Z \(-1\). Each entry of the matrix is expanded as zeros Z \(\times\) Z binary submatrix for (Hp(i,j)) = \(-1\), and the identity Z \(\times\) Z matrix is shifted by (Hp(i,j)) for positive values [31; 32]. Following the expansion of Hp, the LDPC matrix becomes H = M (Mp \(\times\) Z) \(\times\) N (Np \(\times\) Z) [33; 34]. The 5G standards indicate two base graphs:  
BG1 = 46 \(\times\) 68, used in scenarios requiring high throughput [24; 35]. BG2 = 42 \(\times\) 52, which is used for applications with lower throughput [12; 35]. The structures of the two base matrices are presented (see Figure 2). For both base graphs, the block \"A\" corresponds to the information (message) bits, while \"B\" has the double diagonal structure that assigns the encoding process, and \"C\" is an all-zeros matrix. The extension matrices \"D\" (message bits) and \"E\" (parity bits) support incremental redundancy requests [36; 37].