# High-Efficiency, Low-Power, Fully Integrated Neural Electrical Stimulation Circuit
## 3 Circuit Design
### High-Voltage-Generation Circuit Design
The operation of the negative-voltage-generation circuit can be divided into two states: capacitor charging state (shown by the red dashed line in Figure 5a) and voltage generation state (shown by the blue dashed line in Figure 5a). When CLK is low, the negative-voltage module charges capacitor C0, Mp1 and Mn3 conduct, and Mn1 and Mn2 are disconnected. Figure 4: Structure of the series–parallel charge pump circuit. Figure 3: Conventional series–parallel charge pump architecture. During this period, the C0\(-\) end of the capacitor is connected to the input voltage of 1.65 V, the C0+ end is connected to GND, and the voltage difference between the upper and lower plates of capacitor C0 is 1.65 V. VDD/2 is chosen as the input charging voltage to make sure that the voltage stored on the capacitors is within VDD, and this VDD/2 voltage is provided by the voltage generation circuit of the stimulation system. When CLK is high, Mn1 and Mn2 conduct, and Mp1 and Mn3 are disconnected. During this period, C0\(-\) is connected to GND. Since the voltage at both ends of the capacitor does not change abruptly, the voltage at C0+ is pulled down to \(-\)1.65 V. In order to prevent the parasitic diode in Mn2 from turning on when the voltage at C0+ is \(-\)1.65 V, Mn2 adopts a deep N-well (DNW) device. In addition, considering that vp is a negative voltage and CLKB is a low voltage, Mn3 generates leakage current. A diode Mp6 is added between C0+ and Mn3 to prevent leakage current in Mn3. The series-parallel charge pump operates in two phases: charging and discharging. When CLK is high, the capacitor is charged, and its path is shown by the blue dotted line in Figure 5b. Mn4-Mn11 are on, Mp2- Mp5 are off, and the negative-voltage outputs are connected to Mn4, Mn6, Mn8 and Mn10. Take capacitor C1 as an example. At this time, C1\(-\) is connected to \(-\)1.65 V, C1\(+\) is connected to 1.65 V, capacitor C1 is charged, and the capacitor voltage difference between the upper and lower plates is 3.3 V. When CLK is low, the capacitor series discharge, as shown by the red dotted line in Figure 5b. During this period, Mn4-Mn11 are disconnected, and Mp2- Mp5 are on. Taking capacitor C1 as an example, the voltage at the C1\(-\) end is 1.65 V. Since the voltage at both ends of the capacitor does not change abruptly, the voltage at the C1+ end becomes 4.95 V (1.65 + 3.3 V), i.e., Vout1 = 4.95 V. Similarly, Vout2 = 8.25 V (4.95 V + 3.30 V), Vout3 = 11.55 V (8.25 V + 3.30 V) and Vout4 = 14.85 V (8.25 V + 3.30 V). The capacitor size was determined based on the maximum stimulation current and the maximum stimulation pulse width of the stimulator. With a stimulation current of 1 mA and pulse width of 1 ms, the stimulation charge would be Qload = 1 \(\mu\)C, calculated by Q = I \(\times\) T. Assuming that the load consumes 40% of the charge stored on the capacitors, the total charge of the series-parallel charge pump system would be Qtotal = 2.5 \(\mu\)C, which is also equal to the charge stored on a single capacitor Qsingle = 2.5 \(\mu\)C. From Q = C \(\times\) V, we get the value of the single-stage capacitor Csingle = 0.76 \(\mu\)F when V = 3.3 V.  
Figure 5: Charge pump processes: (**a**) negative-voltage circuit; (**b**) series–parallel charge pump. For the negative-voltage module, assuming the charge transfer efficiency is at 40%, then the negative-voltage module needs to store a charge of \(\text{Qneg\_total}=6.25\) uC. According to the charging voltage difference of its storage capacitance of 1.65 V and C = Q/V, the capacitance value required is \(\text{Cneg}=3.8\) uF. This calculation is universal, and the load charge can be recalculated when the stimulus current or the pulse width is changed, and the capacitance value of the various levels of storage capacitance can be solved. A bootstrap circuit, as shown in Figure 6, is used to control the gate of transistor Mn2 to make sure the gate-source voltage difference of Mn2 does not exceed the device limit.