# An All-Digital Optical Phase-Locked Loop Suitable for Satellite Downlinks +
## 2 Coherent Optical Receiver
### All-Digital OPLL Description  
Figure 3 illustrates the block diagram of the implemented coherent optical receiver used in the OGS of Figure 1. In the coherent receiver, the trans-impedance amplifier (TIA) is used for loss compensation. In addition, a different approach is used to implement the local oscillator \(LO\), known as an optical voltage-controlled oscillator (OVCO), for fine-tuning the optical signal [15]. It consists of a system formed by the laser, the dual-parallel Mach-Zehnder modulator (DPMZM), the 90\({}^{\circ}\) RF hybrid, and the electrical VCO. Due to the RF signals in quadrature, generating a single-side sub-carrier modulation is possible, thereby removing a stronger sub-carrier. The interface between a continuous-time system and a discrete-time is provided by an analog-to-digital converter (ADC), and the reverse conversion is performed by a digital-to-analog converter (DAC). The first-order active filter transfer function is a basis for the OPLL loop filter (LF). The combination with the VCO transfer function, an integrator, results in a second-order system. The LF transfer function is given by:  
\[F(z)=K_{1}+\frac{K_{2}}{1-z^{-1}} \tag{8}\]  
where \(K_{1}\), and \(K_{2}\) are the loop filter gains, and \(z^{-1}\) is a symbol for a one-sample time delay in the z-domain. They can be found using the bilinear transformation, or Tustin's Rule, in the discrete-time system theory [16]. A signal-to-noise ratio (SNR) estimator was also implemented to determine noise variations on the demodulated signal and the OPLL. The second and fourth-order moments estimator, M2M4, is the basis of the SNR algorithm [17]. The phase detector's block diagram is shown in Figure 3, inside the green dashed block. It provides information on phase error from a tracked carrier signal. However, as digital modulation suppresses the carrier, it has no carrier to be tracked. Therefore, based on the modulation scheme, a circuit removes the signal's modulation, resulting in an unmodulated carrier to track when using an analog phase detector. For the modulation format used in this study, a circuit multiplied by four should be used to generate an error signal. The block diagram of this type of circuit used in QPSK modulation is shown in Figure 4.  
The resulting error signal from the scheme shown in Figure 4 can be written as:  
\[v_{e}(t) =[(I(t)+Q(t))\cdot(I(t)-Q(t))]\cdot(I(t)\cdot Q(t))\] \[=K_{D}\sin{(4\theta_{n}(t))},\quad\text{where}\quad K_{D}=\frac{G_ {TIA}^{4}R^{4}P_{S}^{2}P_{LO}^{2}}{4} \tag{9}\]  
where \(G_{TIA}\) is the trans-impedance gain, \(R\) is the responsivity, \(P_{S}\) is the modulated signal power, and \(P_{LO}\) is the power of the \(LO\). These \(I(t)\) and \(Q(t)\) signals are the output of an optical coherent detector using a trans-impedance amplifier [18]. In the case of a discrete system, taking the imaginary part (\(\mathfrak{Im}\)) of the fourth power (QPSK) of the sample \(I/Q\) signals removes the modulation and recovers the phase-error signal. This operation results in the same gain as a circuit multiplication, where:  
\[\mathfrak{Im}[X(k)^{M}]=\frac{\mathfrak{Im}[(I(k)+iQ(k))^{M}]}{M}=K_{D}\sin(M \theta) \tag{10}\]  
Figure 4: QPSK phase discriminator used in analog phase detector. The output error is proportional to \(K_{D}\sin{4\theta}\), where \(K_{D}\) is the phase detector gain and \(\theta\) is the error signal [18]. Figure 3: Block diagram of the implemented all-digital OPLL. The laser, the dual-parallel Mach-Zehnder modulator (DPMZM), the RF hybrid, and the VCO form an optical voltage-controlled oscillator (OVCO) shown inside the blue dashed block. The proposed digital discriminator is shown inside the green dashed block. where \(X(k)=(I(k)+iQ(k))\) are the sampled \(I/Q\) signals written in a complex notation. For example, for QPSK, \(M=2^{b}=4\), where \(M\) represents the modulation order, and \(b\) is the number of bits/symbols. This technique was proposed for a discrete-time decision-directed loop for OPLL synchronism [19].