# A Multilevel Switched Capacitor Inverter with Reduced Components and Self-Balance
## 5 Simulation and Experimental Analysis
### Experimental Result  
To validate the effectiveness of the proposed topology, a 13-level switched capacitor inverter test prototype has been built, as shown in Figure 10. Table 6 gives the specific experiment parameters. The carrier frequency is set to 3 kHz and the output frequency is set to 50 Hz. The steady-state and dynamic performance of the proposed multilevel topology are experimentally analyzed. The strain capacity of the SCMLI was tested under complicated working states by changing the experimental parameters, such as the change of the input voltage, load, modulation ratio, and frequency. Figure 11a gives the steady-state wave of output voltage and current when the modulation ratio \(M=0.9\). The switched capacitor inverter can output 13-level voltage and achieve a six-fold voltage gain, which is in line with the theoretical analysis. In addition, the output current is close to the sine wave, indicating that the proposed topology has a reverse current loop to carry out the inductive load. Figure 11b shows the waves of the capacitors voltage, which slightly fluctuates within the allowable range. \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameters** & **Values** \\ \hline Input voltage (\(V_{\mathrm{dc}}\)) & 25 V \\ Output frequency (\(f_{\mathrm{o}}\)) & 50 Hz \\ Triangle carrier frequency & 3 kHz \\ Capacitors \(C_{1}/C_{2}/C_{3}\) & 2200 μF \\ Modulation index (\(M\)) & 0.9 \\ Load & 80 \(\Omega/80\)\(\Omega+15\) mH \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Simulation parameters. Figure 8: Simulation waveforms. (**a**) Output voltage and current under resistive–inductive load. (**b**) Output voltage and current under resistive load. (**c**) Voltage waves of \(C_{1}\), \(C_{2}\), and \(C_{3}\). Figure 9: THD of the output voltage. Figure 12 shows the waves of the output voltage and current under input voltage changes between 25 V and 15 V. It is apparent that the voltage levels and boost factor of the inverter remain unchanged during the sudden change in input voltage, and the output voltage and load current can alter synchronously and stably with the input voltage. \begin{table}
\begin{tabular}{c c} \hline \hline
**Components** & **Specifications** \\ \hline Input voltage (\(V_{\text{dc}}\)) & 25 V \\ Output frequency (\(f_{o}\)) & 50 Hz/25 Hz/100 Hz \\ Carrier frequency & 3 kHz \\ Capacitors C\({}_{1}\)/C\({}_{2}\)/C\({}_{3}\) & 2200 \(\mu\)F \\ Resistive-inductive load & 80/160 \(\Omega\) + 15 mH \\ Switches (\(S_{1}\)-\(S_{12}\)) & SPP20N60C3 \\ Dode & MBR2020 CTG \\ Optocouplers & TLP250 \\ Current probe & Tektronix A622 \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Experimental parameters. Figure 11: Experimental results at the steady-state. (**a**) Output voltage and current. (**b**) Voltages of \(C_{1}\), \(C_{2}\), and \(C_{3}\). Figure 12: Waves of the output voltage and current under the mutation of input voltage changes. Figure 10: Experimental prototype and schematic. Figure 13 presents waves of the capacitors' voltage under the input voltage of the topology changes between 25 V and 15 V. It is apparent that the capacitor voltage is relatively rapid and reaches the steady state after a short transition. Figure 14 gives the output voltage and current waveform under the mutation of the load (unloaded to 80 \(\Omega\) + 15 mH and 80 \(\Omega\) + 15 mH to 160 \(\Omega\) + 15 mH). It is apparent that the output voltage remains stable during the sudden change in load, and that the current quickly changes from 0 to the working state before decreasing as the load increases. Figure 15 presents the experimental waveforms of the proposed SCMLI under the mutation of the modulation index \(M\). It is apparent that the voltage levels decrease from 13 to 9 when \(M\) alters from 0.9 to 0.6, and the voltage gain is reduced to 4, whilst voltage levels decrease from 9 to 7 when \(M\) is altered from 0.6 to 0.4, and the voltage gain is reduced to 3, which is consistent with the analysis in Table 2.  
Figure 14: Waves of output voltage and current under the mutation of load.