# A 13.44-Bit Low-Power SAR ADC for Brain-Computer Interface Applications
## 2 Circuit Topology
### Capacitive DAC Array Design  
The CDAC architecture proposed in this design is shown in Figure 9. The capacitance values in the MSB (most significant bit) section are 32 C\({}_{\text{u}}\), 16 C\({}_{\text{u}}\), 8 C\({}_{\text{u}}\), 4 C\({}_{\text{u}}\), 4 C\({}_{\text{u}}\), 2 C\({}_{\text{u}}\), and 1 C\({}_{\text{u}}\); those in the LSB (least significant bit) section are 32 C\({}_{\text{u}}\), 16 C\({}_{\text{u}}\), 8 C\({}_{\text{u}}\), 8 C\({}_{\text{u}}\), 4 C\({}_{\text{u}}\), 2 C\({}_{\text{u}}\), and 1 C\({}_{\text{u}}\). Here, C\({}_{\text{u}}\) represents the unit capacitor. In the schematic, V\({\rm 0}\) to V\({\rm 1}\)\({\rm 3}\) denote the outputs of each stage in the preceding bootstrapped sampling switch, and N\({\rm 1}\)\({\rm 1}\)\({\rm 3}\)\({\rm 0}\) and P\({\rm 1}\)\({\rm 3}\) to P\({\rm 0}\) are signals fed back by the SAR logic array. The CDAC architecture synergistically integrates three innovative techniques: bottom-plate sampling with a V\({}_{\text{CM}}\) reference switching protocol for charge injection cancellation, a segmented binary-weighted structure employing bridge capacitors for area-efficient impedance matching, and strategic insertion of redundant bits in both MSB and LSB sections for error correction. This optimized system architecture achieves a remarkable 87% switching energy reduction and 98.3% area savings compared to conventional implementations through novel charge redistribution pathways and switched-capacitor network optimizations. The bottom-plate sampling technique ensures that the total charge on the capacitor's top plate node remains constant after switch disconnection, effectively isolating the critical sampling node from charge injection and charge absorption effects during switch transitions while maintaining invariant charge conditions on the upper plate that protect comparator input pair MOSFETs from disturbance, thereby enabling the ADC to achieve a superior linearity performance through this charge-conserving architecture. The V\({}_{\text{CM}}\)-based switching scheme incorporates an additional reference voltage at V\({}_{\text{CM}}\) = 1/2V\({}_{\text{DD}}\) = 900 mV where, during sampling, all capacitor bottom plates connect to V\({}_{\text{CM}}\) before the SAR logic array, upon completing comparison, drives each capacitor's bottom plate to either V\({}_{\text{DD}}\) or GND based on the conversion results [14]. This methodology ensures that each capacitor switches only once per conversion cycle while maintaining a constant input common-mode voltage at the comparator through simultaneous differential capacitor  
Figure 8: Frequency characteristics of bootstrap switching circuits. Figure 9: Circuit of proposed CDAC. switching, thereby achieving the dual advantages of power reduction during capacitor switching and a simplified comparator design by eliminating common-mode transients that would otherwise require complex auto-zeroing or offset cancellation circuitry. The high-precision SAR ADC typically adopts a segmented capacitor array structure, as illustrated in Figure 10, where this partitioning architecture effectively reduces the number of unit capacitors needed to optimize the chip area while simultaneously lowering the performance requirements for sampling switches and accelerating the CDAC settling time through the reduced capacitive load.