# HAIPO: Hybrid AI Algorithm-Based Post-Fabrication Optimization for Modern 3D NAND Flash Memory
## 2 Background
### Overview of NAND Flash Memory  
**NAND Flash Organization. ** The NAND flash memory consists of flash cells, which store data, and peripheral circuits, which support flash commands such as read and write. Flash cells are grouped into a page, and multiple pages form a block. Figure 1 illustrates the hierarchical organization of a NAND flash chip. A set of flash cells form a NAND string that is connected to a bitline (BL), and NAND strings of different BLs compose a block. The control gate of each flash cell at the same vertical location in a block is connected to a wordline (WL), so all the cells at the same WL (i.e., sharing WL) concurrently operate. Thousands of blocks constitute a plane while sharing all the BLs in the plane. There are typically two or four planes in a single NAND flash chip (or die). **Data Storage Mechanism. ** A flash cell stores bit data as a function of its threshold voltage (\(V_{th}\)) level that highly depends on the amount of charge in the cell's charge trap layer; the more electrons in the charge trap layer, the higher the cell's \(V_{th}\) level. Depending on the number of electrons in the cell's charge trap layer, the flash cell works as an off switch or an on switch under a given control gate voltage (i.e., WL gate voltage), thus effectively storing bit data. For example, we can assign a '0' state when the flash cell has a high \(V_{th}\) and a '1' state when the flash cell has a low \(V_{th}\). Since the flash cell is surrounded by dielectric materials, electrons in the charge trap layer are electrically insulated. This cell organization gives NAND flash memory a non-volatile characteristic so that the electrons trapped in the flash cell do not leak even after the power is off. Figure 1: An organizational overview of NAND flash memory. **NAND Flash Operations. ** There are three basic operations to access or modify the data stored in NAND flash memory: (_i_) program, (_ii_) read, and (_iii_) erase operations. The program operation, which increases \(V_{th}\) of selected flash cells, injects electrons from the substrate into the charge trap layer of the selected flash cells using FN tunneling [7] by applying a high voltage (>20 V) to WL gates (i.e., changing the state of the flash cell from '1' state to '0' state). On the other hand, to erase programmed cells (i.e., change the state of the flash cell from '0' state to '1' state), a high voltage (>20 V) is applied to the substrate (while WL gates are set to 0 V) to remove electrons from the charge trap layer, which decreases the \(V_{th}\) of the flash cells. Since the program operation can change the bit value of a flash cell only from '1' to '0', all the flash cells of a page should be erased to program data on the page (_erase-before-program_ property). The erase operation works in block granularity because the high voltage is applied to the entire substrate that underlies the whole block, while the program operation is performed in page granularity. To read the stored data from flash cells, the \(V_{th}\) levels of the flash cells on the selected WL are probed using a read reference voltage \(V_{ref}\). In Figure 1, when WL\({}_{k}\) is selected for read, since other WLs (e.g., WL\({}_{k+1}\) or WL\({}_{k-1}\)) should not affect the read operation of WL\({}_{k}\), all the flash cells in other WLs should behave like pass transistors. Therefore, their gate voltage is set to \(V_{READ}\) (>6 V), which is much higher than the highest \(V_{th}\) value of a flash cell. If \(V_{th}\) of the \(i\)-th flash cell in WL\({}_{k}\) is higher than VREF, the \(i\)-th flash cell turns off, so the cell current of BL\({}_{i}\) is blocked (i.e., the flash cell is identified as '0'). On the other hand, if the \(V_{th}\) of the \(i\)-th flash cell is lower than VREF, the \(i\)-th flash cell turns on, so the cell current can flow through BL\({}_{i}\) (i.e., the flash cell is identified as '1'). By sensing BL\({}_{i}\)'s from the selected WL\({}_{k}\), the stored data are read out to the page buffer.