## 5 Implementation and Power Estimation  
The design is coded in verilog HDL. Once pre-synthesis simulations are successful, RTL is synthesized for ASIC and FPGA implementation. The power estimation and comparison is done for ASIC implementation and design validation is done on FPGA platform. For power estimation, it is synthesized in \(130\)-nm UMC CMOS process for maximum sampling frequency of \(30\) Msps using Synopsys Design Compiler. The power estimation is done once post synthesis simulation is successful. Synopsys Prime Power is used for estimating dynamic power. Input to Prime Power is the VCD (Value Change Dump) file generated from verilog simulation and the synthesized netlist. The VCD file contains all signal transition that occurred during the simulation. For generating VCD file, input to the simulator are the synthesized netlist, test vectors generated in MATLAB and SDF (Standard Delay Format) file used for synthesis. Figure 13: Word length (\(Q_{dig}\)) control, multi-bit to 1-bit control, on signal level and word level. Figure 13 shows a quantizer in hardware. For an input with word length N, quantizer shifts the input to right by \(N-Q_{dig}\) with sign of the word preserved as shown in Figure 13 for \(Q_{dig}\) equal to one. By doing this, higher order bits do not see lot of switching when they are processed further in the receiver. There will be activity in the lower order bits of the word. Hence with smaller \(Q_{dig}\), there is saving in dynamic power. Table 1 shows the estimated power for various \(Q_{dig}\) and \(f_{s}\) combinations for a given \(\widehat{\text{SNR}}_{FE}\) under different conditions of interference. Case-I corresponds to the case when there is no interference and only noise is present in the system. Case-II corresponds to the case when there is no interference on the alternate channels and only adjacent interference is present with noise. Case-III is the case where adjacent channels are absent, whereas, alternate channels and noise are present in the channel. In case-IV all interferences are present along with noise. Every \(Q_{dig}\) and \(f_{s}\) combination in the table satisfies the required BER. The estimated power is also shown for all combinations. The combination of \(Q_{dig}\) and \(f_{s}\) that consumes lowest power for a particular interference and \(\widehat{\text{SNR}}_{FE}\) condition is put into the LUT. Such entries are listed under gray shading. The power is estimated for maximum length packet. Average power (\(P_{avg}\)) is calculated as follows:  
\[P_{avg} = \frac{P_{synch}\times T_{synch}+P_{data}\times T_{data}}{T_{total}} \tag{12}\] \[\text{where, }\ T_{total} = T_{synch}+T_{data} \tag{13}\]  
\(P_{synch}\) is the average power consumption during preamble and SFD. \(P_{data}\) is the average power during data. As shown in Figure 4, \(T_{synch}\) is preamble and SFD duration. It is \(10\) symbol long and data is \(256\) symbols long. The power spent during synchronization is fixed (\(P_{synch}\) = \(10\) mW) and depends on \(Q_{dig}\) and \(f_{s}\) settings for the data duration. In order to have a simple clock generator, the operating sampling frequency (\(f_{opr}\)) for the design are integer division of \(30\) Msps. They are \(30\), \(15\), \(10\), \(6\), \(5\), \(3\), \(2\), and \(1\) Msps respectively. As shown in Table 1, the sampling frequencies are quantized to the next higher operating sampling frequency. For, e.g., sampling frequency of \(13\) Msps is raised to \(15\) Msps. We can see from the table, maximum power consumed by the design is \(3.3\) mW. The lowest power consumed by the design as can be seen from the table is \(0.49\) mW, when \(f_{s}\) is \(2\) Msps and \(Q_{dig}\) is \(1\)-bit. At this sampling  
Figure 13: Cont. frequency, there is only one multiplier active in the FIR filter. \(f_{s}\) of 2 Msps means the signal with IF of 3 MHz is under-sampled. In spite of under-sampling and coarsely quantizing (1-bit) the signal, specified BER is achieved when \(\widehat{\text{SNR}}_{FE}\) is high.