# Design of a Broadband and High-Isolation CMOS Active Quasi-Circulator
## 2 Circuit Design and Implementation
For the purpose of efficiently reducing the influence of the S31 transmitting path while still preserving the quasi-circulator characteristic, a phase cancellation method has been created. In order to travel down an additional signal with antiphase at port 3, a CS FET M3 is placed in parallel to ports 1 and 3. This is performed in order to take advantage of the intrinsic phase inversion capability of the CS FET, which allows it to have the ability to cancel out phase cancellation. Under the assumption that all other scattering parameters are zero, the quasi-circulator is defined by the constraint that both S21 and S32 must equal 1. The phase cancellation path is depicted in Figure 2, and it consists of a second CS FET that is linked in parallel to ports 1 and 3. The phase inversion feature is followed by this transmission path, which is similar to the S21 path of the active balun. Modifying the settings of the circuit allows for exact control of the phase difference between the output port of the phase cancellation path and port 3 of the CS FET. This difference can be carefully regulated to be 180 degrees. Taking everything into account, the quasi-circulator is able to achieve a greater degree of isolation from the S31 by combining the two output ports. Because of the cascading stage of the active balun, a signal that is transmitted to port 2 may ultimately result in a combination of reverse traveling waves at port 3. This is in reference to the transmission path known as S32. In addition, due to the one-sided nature of the FET, the incoming signal is unable to flow via port 1. Furthermore, while accounting for the same characteristics, the recommended circuit structure permits the accomplishment of very low magnitudes of \(|\)S121, \(|\)S131, and \(|\)S231. A straightforward unilateral CS FET model, which is depicted in Figure 3a, has been incorporated into the study of the suggested quasi-circulator. Gate-to-source capacitance (Cgs) and drain-to-source capacitance (Cds) are the corresponding forms of capacitance. In order to provide coupling between the gate and the drain, the transconductance \(g_{m}\) is utilized. Furthermore, the analysis of the six-port chain matrix is carried out with the help of the equivalent network of the suggested quasi-circulator, which is shown in Figure 3b [15]. Figure 2: Flow chart of the proposed broadband and high-isolation quasi-circulator. Cgs1 + Cgs3, Cds1 + Cgs2, and Cds2 + Cds3 are the equations that are used to calculate the parasitic capacitance as C1, C2, and C3, respectively. It is possible to express the six-port chain matrix using the code shown in Figure 3b. \[T_{AQC}= \begin{bmatrix}1&0&0&0&0&0\\ 0&1&0&0&0&0\\ 0&0&1&0&0&0\\ j\omega C_{1}&0&0&1&0&0\\ g_{m1}&j\omega C_{2}&0&0&1&0\\ g_{m3}&g_{m2}&j\omega C_{3}&0&0&1\end{bmatrix} \]  
In contrast to the quasi-circulator that has been proposed, ports 2, 3, and 5 should be ended by an open circuit. For this reason, it can be deduced that the Z matrix is the most suitable candidate for matrix reduction. Through the process of converting the Z matrix to the S matrix, the eventual scattering parameters of the suggested quasi-circulator can be determined as follows:  
\[S_{ii}^{AQC}=\frac{2}{j\omega C_{1}Z_{0}+1}-1\ \ \ i=1,2\text{and}3\]  
\[S_{12}^{AQC}=S_{23}^{AQC}=S_{13}^{AQC}=0\]  
\[S_{21}^{AQC}=\frac{-2g_{m1}Z_{0}}{(j\omega C_{1}Z_{0}+1)(j\omega C_{2}Z_{0}+1)} \tag{1}\]  
\[S_{32}^{AQC}=\frac{-2g_{m2}Z_{0}}{(j\omega C_{3}Z_{0}+1)(j\omega C_{2}Z_{0}+1)} \tag{2}\]  
\[S_{31}^{AQC}=\frac{-2Z_{0}[(j\omega C_{2}Z_{0}+1)g_{m3}-g_{m1}g_{m2}Z_{0}]}{( j\omega C_{1}Z_{0}+1)(j\omega C_{2}Z_{0}+1)(j\omega C_{3}Z_{0}+1)} \tag{3}\]  
In this design, equal power transmission for \(\mid\)S21 \(\mid\) and \(\mid\)S32 \(\mid\) is required.