## 6 Conclusions and Further Work  
In this paper, the authors presented some considerations and practical experiments concerning the recently proposed multitasking architecture for a real-time system [2]. Some switching techniques that allowed efficiently handling the available resources and reducing the power consumed by the system were tested. These proposals were compared with a classical solution in a safety system based on the scheme of one dedicated processor per a single task (STP). The first technique was based on the introduction of a clock-gating mechanism to the classical STP architecture and it gave the best results--the greatest energy savings. Next, a series of experiments were conducted with a multitasking architecture based on pipelined processing with task interleaving (MTP). This structure was modified by adding memory-resource switching (RAM gating). This modification also yielded a radical reduction of power. However, in the case of the scenario consisting of simple cores, wherein each core executed only a single task (STP), there were limitations. First of all, as the number of concurrently and independently working cores grew, the reliability of the system decreased. This problem became more evident when different tasks needed to cooperate with one  
Figure 18: Comparison of the total dynamic power consumed by mixed structures for a different number of cores and various configurations of cores (all cases for \(SP=150\)). \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Method** & \begin{tabular}{c} **Resources Utilization Related to Non-Gated Solution [\%]** \\ **Slice LUTs** \\ \end{tabular} & \begin{tabular}{c} **Dynamic Power Reduction Related** \\ **Slice Registers** \\ \end{tabular} & \
\begin{tabular}{c} **Slice Registers** \\ \end{tabular} &
\begin{tabular}{c} **to the Non-Gated Solution [\%]** \\ \end{tabular} \\ \hline STP CG & 100 & 101.9 & 59.6 \\ MTP RG & 100.8 & 100 & 7.8 \\
[26] & 138.7 & 116.9 & 4.0 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Comparison of the results obtained for STP CG and MTP RG with [26]. another. Moreover, the capacity of the structure was limited and when the number of different tasks was too great it was impossible to use the STP architecture. In the authors' opinion, the main contributions of the paper are:  
* the development of an original, energy-efficient, multicore architecture and its flexible models;
* the extension of the developed multitasking structure with mechanisms and modules controlling the gating procedures;
* the proposing of a set of metrics for analyzing the basic properties of real-time systems; and
* having conducted a series of experiments, analyses of the obtained results, and the formulation of design guidelines that allowed selecting the optimal system configuration (scenario). The research presented in the paper concerned mainly independent tasks. Different configurations (scenarios) of the system, which investigated the impact of two mechanisms on dynamic power reduction, were analyzed. However, there were many issues not addressed in this paper, e.g., cooperating tasks that need to exchange data, synchronization of tasks, complex memory operations, buses with energy-efficient protocols, cyclic execution of tasks, and the further gating of idle resources. In the literature, an additional power optimization technique was published, power gating [27; 28; 29]. However, the authors decided to neglect this problem in this research. The main reason was that the paper dealt with FPGA structures, in which this technique is not common. Admittedly, in the structure of the chip on which the experiments were conducted, a Virtex 7, Xilinx, introduced the possibility of power gating [33], but the application of this technique for real-time systems is debatable. Problems with state retention and additional delays are not acceptable for time-predictable systems. Yet another idea for future consideration is a mixed system, consisting of STP CG cores and MTP RG processors.