## 3 Circuit Design
### Analog Front-End
#### 3.2. Analog to Digital Converter  
The multiplexed and amplified signal is then converted into a digital form by an \(8\) bit SAR ADC (see Figure 1). This topology is well-suited for low power and small-area applications since it requires a minimal amount of analog circuitry. To save area, analog multiplexing of input signals, requiring only one AD converter, was employed even though it resulted in a small power penalty with respect to the use of one converter per each amplifier and digital multiplexing of data [16]. The number of the converter bits was chosen taking into account the following considerations:  
* The maximum amplitude for an extra cellular action potential is \(\sim 1\) mV [17] while the minimum signal is about \(10\)\(\mu\)V, the latter being determined by the typical input noise due to neural background activity and electrode impedance [18]. Therefore, the ratio between the Full Scale Range (FSR) and the ADC least significant bit, _i.e._, the dynamic range of the converter, should be better than \(1\) mV/\(10\)\(\mu\)V \(\approx 100\). This results in a converter resolution larger than \(6.35\) bit. * The ADC quantization noise has to be kept much lower than the minimum detectable signal, _i.e._, the rms input noise. This requirements translates into: \[\frac{FSR}{2^{n}G\sqrt{12}}<10\)\(\mu\)V (16)where \(G\) is the amplifier gain and \(n\) is the number of converter bits. The worst-case condition occurs for the minimum gain of the amplification chain, which is set by the ratio between the FSR and the maximum amplitude of the input signal, \(A_{max}\): \[G_{min}<\frac{FSR}{A_{max}}\cong\frac{3\ \textrm{V}}{1\ \textrm{mV}}=3000\] (17) In the present design we set \(G_{min}\ \cong 2000\) and thus: \[n>log_{2}\bigg{[}\frac{FSR}{\sqrt{12}\cdot 10\mu V\cdot G_{min}}\bigg{]}\cong 5.4\] (18)  
In practice, taking into account that the effective number of bit (ENOB) is always lower than the nominal figure, the use of an \(8\) bit ADC will provide a safe margin for the design. A higher resolution is useless and harmful since it would increase the ADC power consumption. The ADC consists of three main parts: the capacitor array, the comparator and the logic block performing the successive-approximation algorithm. The capacitor array, which acts as sampling capacitance during the sampling interval and as charge-sharing DAC during the conversion period, has been implemented as a binary array. The value of the unit capacitance, \(C_{LSB}\), was chosen considering two requirements:  
* The noise in the sampling phase has to be significantly smaller than the quantization noise. Thus, the total capacitance of the array, \(C_{TOT}\), must satisfy the condition: \[\frac{KT}{C_{TOT}}<\frac{\left(V_{REF}\right)^{2}}{12}\] (19) which clearly is not a limit factor, resulting in \(C_{TOT}\) much larger than about \(1\) fF. * The LSB capacitance has to be sufficiently accurate and it has to fulfill the following requirement [19]: \[2\frac{\Delta C_{LSB}}{C_{LSB}}\cdot\sqrt{2^{N-1}}=2\frac{K_{c}}{\sqrt{A_{c}} }\cdot\sqrt{2^{N-1}}<0.5\] (20) where \(K_{c}=0.5\%\cdot\mu\)m and \(A_{c}\) are the Pelgrom mismatch parameter and the least significant bit (\(LSB\)) capacitor area, respectively. ?From Equation (20) \(A_{c}\) has to be larger than \((4.5\ \mu\)m\()^{2}\), which implies \(C_{LSB}>19.5\) fF, considering a specific capacitance of \(1\) fF/\(\mu\)m\({}^{2}\). Taking into account also the effect of parasitic capacitance that can degrade the achievable accuracy, \(C_{LSB}=80\) fF was employed as unit capacitor, resulting in a total capacitance of \(2^{N}\cdot C_{LSB}=20.48\) pF. The comparator was implemented as a classical two-stage topology, as depicted in Figure 4. A \(20\) dB gain preamplifier is followed by a PMOS latch stage and a couple of inverters are connected at the latch outputs to regenerate the signals. The two-stage architecture was preferred to a dynamic latch in order to avoid kickback noise and metastability [20, 21].