## 2 Circuit Description
### Proposed 0.3 V CDBA
All conveyors used in the design of the CDBA, with the additional voltage buffer, are identical and are identically biased. The current gain of both conveyors, which is equal to the current gains from the \(p\) to \(n\) and from the \(n\) to \(z\) terminals of the CDBA, as determined at shorted outputs, are given in the following equation:  
\[A_{i}=\frac{g_{m3A}\frac{g_{m1}}{g_{m3A}}}{g_{m3A}\frac{g_{m1}}{g_{m1}}+g_{o2}} \tag{2}\]  
In this expression, \(g_{o1}=g_{ds1}+g_{ds5}\) and \(g_{o2}=g_{ds3}+g_{ds7}\), where \(g_{m}\), \(g_{mb}\), and \(g_{ds}\) denote the transconductance, bulk transconductance, and output conductance of the MOS transistor, respectively. Thus, the current gain error of the current mirror M3-M4 is reduced \(g_{mb1}/g_{o1}\) times, compared to a simple MOS current mirror, i.e., by the number equal to the voltage gain of the input differential stage M1-M2. Assuming \(g_{m1}/g_{mb1}=g_{m2}/g_{mb2}\), the dc voltage gain of the voltage follower \(z-w\), and other followers in the structure, can be expressed as follows [48]:  
\[A_{vo}=\frac{\frac{g_{mb1}}{g_{o1}}\frac{g_{m3}}{g_{o1}}\frac{g_{m3}}{g_{m3}+g _{dm3}+g_{o2}}}{1+\frac{g_{mb1}}{g_{o1}}\frac{g_{m3}}{g_{o2}}\frac{g_{m3}+g_{o2 }}{g_{m3}+g_{m3}+g_{o2}}} \tag{3}\]  
It should be noted that its gain error is lower than that calculated from the formula \(A_{o}/(1+A_{o})\), where \(A_{o}\) is the open loop voltage gain of the internal OTA, and can easily be lowered much below 1%, even with open loop gain in the range of 30 dB, thus providing a very good accuracy in a simple structure. The above property is achieved thanks to the connection between the bulk and drain terminals of M\({}_{3}\), which provide equal \(V_{BS}\) voltages for M\({}_{2}\) and M\({}_{3}\), improving accuracy, even if it lowers the voltage gain of the internal OTA. The output resistance at the output of the voltage follower, which is equal to the resistances seen at the \(p\), \(n\), and \(w\) terminals of the CDBA, is given as follows:  
\[r_{p}=r_{n}=r_{w}\cong\frac{1}{g_{m3}\frac{g_{mb1}}{g_{o1}}} \tag{4}\]  
Thus, it is a reciprocal of \(g_{m3}\), which is multiplied by the voltage gain of the first stage. The output resistance at the \(z\) terminal of the CDBA is given as follows:  
\[r_{z}=\frac{1}{g_{ds4}+g_{ds8}} \tag{5}\]  
and its value is rather small, due to the lack of cascode connections in the output stage. The ratio of resistances is as follows:  
\[\frac{r_{p,n,w}}{r_{z}}\cong\frac{g_{m3A}}{g_{ds4}+g_{ds8}}.\frac{g_{mb1}}{g_{ o1}} \tag{6}\]  
This is, however, of the order of \(10^{3}\)\(\Omega/\Omega\), which is sufficient for the proposed application. The 3 dB bandwidth of the voltage follower is approximately equal to its gain-bandwidth product (\(GBW\)), which can be approximated as follows:  
\[GBW\approx\frac{g_{mb1}}{C_{gd3}} \tag{7}\]This is typically much lower than the 3 dB frequency of the current gains of the conveyors and the CDBA. It is worth pointing out that the parasitic pole associated with the drain/gate node of M\({}_{2}\) and equal to \(g_{m2}/C_{\Sigma}\), where \(C_{\Sigma}\) is the total parasitic capacitance associated with this node, should be located much above the GBW of the voltage follower. The minimum supply voltage of the CDBA is given by \(V_{DDmin}=\max(V_{S52}+V_{SDsat6}\); \(V_{S53,4}+V_{SDsat5})\), where \(V_{SDsat}\) is the saturation voltage of an MOS transistor. Assuming that \(V_{S62,3,4}~{}\approx~{}V_{DSsat}\), which holds in the weak inversion region, the minimum \(V_{DDmin}\) can be as low as \(2V_{SDsat}\) (ca. 200 mV) [47].