## 3 Analysis of Program and Erase Window
### Erase Window Effect  
Figure 6a shows the initial Vth and erased Vth values for each proposed ON pitch structure. As in the program analysis, the erased Vth and initial Vth values are shown in Figure 6b to check only the Vth change pattern due to the hole-trapped charge stored in the CTL, excluding the Vth reduction phenomenon due to the read operation caused by the SCE. The results indicate that in Ls scaling, the Vth decreases and the erase window improves, while in Lg scaling, the Vth increases and the erase window deteriorates. The decrease in Vth during Ls scaling is interpreted as an increase in the fr  
Figure 5: (**a**) E-trapped charge distribution when program voltage is 17 V in reference and Ls scaling. (**b**) Comparison of e-trapped charge in CTL by cutting a-a’ area in (**a**,**b**). (**c**) Comparison of electric field in gate stacks by cutting b-b’ area in (**a**,**b**). (**d**) Programmed Vth as function of program voltage in reference and Ls scaling structure. (**e**) E-trapped charge distribution when program voltage is 22 V in reference and Ls scaling. (**f**) Electron density of poly-Si channel during read operation when programmed Vth is high (4.4 V) and low (0 V). To clarify this, the hole-trapped charge in the CTL after the erase operation was examined, as shown in Figure 7a-c. The results confirm that during Ls scaling, compared to the reference, a high hole concentration occurs not only in the selected WL but also in the space area due to the strengthening of the fringing field with the adjacent WL. A quantitative comparison of the hole concentration trapped in the CTL for each structure was made by cutting the a-a' direction in Figure 7a-c. Figure 7d shows that during Ls scaling, compared to the reference, a very high hole concentration is confirmed in the selected WL and space area. However, during Lg scaling, a hole concentration at only 50% of the reference is quantitatively confirmed below the selected WL. This phenomenon can be explained similarly to the program operation, as seen earlier, due to the reduction in the hole tunneling current through the tunneling oxide caused by a lack of capacitive coupling resulting from a decrease in the gate area. Meanwhile, another issue that can arise during Lg scaling is erase saturation [12]. Unlike program operations, erase operations must consider the mutual injection of holes and electrons. If the amount of electron back tunneling current through the blocking oxide on the gate side is relatively large compared to the decrease in the hole current from the substrate during Lg scaling, the effect of reducing the erase window can be significantly deepened. Therefore, to secure effective erase window characteristics during excessive Lg scaling, it is crucial to consider the charge dynamics of electron and hole injection in the erase operation and  
Figure 6: (**a**) Initial Vth and erased Vth of selected WL under various Lg and Ls scaling conditions. (**b**) Difference between erased Vth and initial Vth under various Lg and Ls scaling conditions. Figure 7: Hole-trapped charge distribution in CTL during erase operation in (**a**) reference, (**b**) Ls scaling, and (**c**) Lg scaling. (**d**) Comparison of h-trapped charge in CTL by cutting a-a’ area in (**a–c**). simultaneously improve the back tunneling current. This can be achieved by appropriately introducing high-work function materials or improving the blocking oxide quality. Figure 8 plots the programmed Vth and erased Vth analyzed so far. From the PE window perspective, it can be seen that allocating a slightly larger portion to Ls scaling compared to Lg scaling is advantageous for securing larger memory window characteristics. However, the cell's distribution margin formed by the final ISPP must be evaluated by comprehensively considering the reliability characteristics according to the distribution of electrons and holes within the CTL and deterioration due to \(Z\)-interference.