# A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow
## 1 Introduction  
The growing diffusion of the Internet of Things (IoT) [1; 2] involves the embedding of integrated circuits (ICs) into objects to acquire, process, and exchange useful information. This requires the development of mixed-signal ICs that typically integrate a sensor, analog front-end, analog-to-digital converter (ADC), digital processing, and a simple wireless transceiver [3; 4; 5; 6]. Together with area minimization and reconfigurability, one of the strongest constraints is on power consumption: these systems often have to operate for years from tiny batteries or by harvesting energy from the environment; thus, an extremely low power consumption is required. Since in many applications IoT sensor nodes have to be energy autonomous, they have to scavenge energy from the environment by means of photovoltaic cells, thermoelectric generators, and vibration sensors. Operating with this kind of energy harvesting system requires the minimization of the supply voltage, and circuits operating with supply voltages as low as 0.3 V are suitable to properly operate with such harvesting sources [7; 8; 9]. The operational transconductance amplifier (OTA) is a fundamental building block to design analog front-ends, allowing for the implementation of amplification and filtering functions needed in IoT and biomedical applications. In this regard, several OTAs have been proposed in recent work, which allow for the attainment of good performance working with supply voltages as low as 0.3 V [10; 11; 12; 13; 14; 15; 16; 17; 18; 19]. These solutions are almost all based on body-driven (BD) input stages which, at such low supply voltage, allow them to reach rail-to-rail input common mode range (ICMR) and exploit gate-biased techniques in orderto assure well-defined dc bias point and good robustness against process, supply voltage, and temperature (PVT) variations. In addition, due to the aggressive supply voltage scaling and due to the effectiveness of the deep sub-threshold region in which the most of these architectures work, the performance of recent ultra-low voltage (ULV) OTAs can be considered state-of-the-art in terms of gain bandwidth product and slew rate normalized to the power consumption. However, such OTA topologies rely on a full custom design approach and, even if the analog part is often only a small fraction of the whole system, it requires a large design effort, with a negative impact on design times and costs, which are very important aspects in the context of IoT nodes development. This is because both the schematic and the layout design phases are typically carried out manually, iterating each step repeatedly until specifications are met with good robustness under PVT variations and mismatches. To overcome this problem and reduce both costs and time-to-market, a design methodology for analog circuits defined as synthesizable analog design has been introduced in [20]. In this design approach, all circuit building blocks are implemented through standard-cells taken from the digital library and coded in a hardware description language, which can then be synthesized from commercial standard-cell libraries and automatically placed and routed using electronic design automation (EDA) tools. Compared to conventional analog implementations, standard-cell-based analog implementations significantly shorten the design time and cost [20; 21; 22; 23; 24; 25; 26; 27; 28; 29; 30; 31; 32]. In the context of the design of standard-cell-based amplifiers, researchers have recently focused on automatic place-and-route strategies for standard-cell-based circuits, typically adopted in the digital design flow, to implement fully-synthesizable analog circuits and drastically reduce the area usage of analog building blocks [33]. Research studies are investigating both the use of a digital approach to implement analog functions [20; 34] and the design of analog blocks exploiting digital standard-cells [22; 25; 35; 36].