# High-Reliability Wireless Pressure Measurement System Based on FEC Algorithm
## 4 Key Control Logic Design
### Wireless Module Logic Design  
The wireless part of the front-end memory is responsible for receiving and identifying the instructions from the back-end, modulating the real-time monitoring or read-back data into LoRa RF signals and transmitting them into the air; the wireless part of the back-end test bench is responsible for sending the instructions issued by the host computer, completing the reception and demodulation of the LoRa RF signals returned by the front-end memory, and transmitting them to the main control chip and the host computer for information display. Taking the wireless front-end memory module as an example, Figure 9 shows the logic flow chart of the wireless module. First, start the wireless module and complete its initialization process. After initialization, the system needs to wait for the wireless module to complete the internal reset process. Using different level combinations of the DIO pins, configure the module to enter the required configuration mode through the MODE_CTL signal. In the configuration mode, the baud rate of the serial communication is set to 9600 bps, with a data format of 8 data bits, no parity bit, and 1 stop bit. After the parameters are written, the system switches the wireless module from the configuration mode to the transmission mode to start the data sending and receiving tasks. For the wireless receiving module, its operation logic is similar to that of the sending module, also requiring steps such as initialization, reset, mode configuration, and parameter setting.  
After inserting the FEC encoding logic into the FPGA, the data transmission timing of the SPI interface is controlled through a state machine to ensure the stable transmission of encoded data packets. The encoding and decoding logic is controlled by a finite state machine, and the implementation of the encoding and decoding logic is shown in Figure 10.  
Figure 9: Logic flow chart of the wireless module.  
In the encoding logic, the lookup table method is used to implement multiplication operations. The coefficients of the generator polynomial are calculated and stored in the BRAM of the FPGA. The lookup table method transforms complex real-time multiplication operations into address index lookups, significantly reducing the complexity of real-time calculations and being suitable for the parallel processing characteristics of FPGA. The generation of parity bits is achieved through a linear feedback shift register. The input data enter the shift register in byte streams and undergoes iterative operations using the following polynomial:  
\[G(X)=\prod_{i=0}^{31}\left(x-\alpha^{i}\right) \tag{1}\]  
Finally, a 32-byte check code is generated. The original data and the check code are combined into an FEC-encoded data packet. The maximum transmission unit of the LoRa module is adjusted to ensure the complete transmission of the encoded data packet.  
The decoding state machine is responsible for receiving FEC encoded data packets and detecting and correcting errors. It waits for data reception in the IDLE state and initializes decoding parameters. When the data_received signal is high, it enters the RECEIVE state to receive 255 bytes of encoded data and then calculates the syndrome of the data through a shift register and determines whether there are any errors. If syndrome_zero = 1, it enters the CORRECT state; otherwise, it enters the SOLVE_ERROR state, using the Berlekamp-Massey algorithm to calculate the error location polynomial. In the CORRECT state, it calculates the error values, corrects the received data, and finally sends the corrected data to the flash storage module.