# Research on an Intelligent Test Method for Interconnect Resources in an FPGA  
[PERSON]  
1 School of Automation Engineer, University of Electronic and Technology of China, Chengdu 611731, China; [EMAIL_ADDRESS]  
[PERSON]  
2 Shenzhen Institute for Advanced Study, University of Electronic and Technology of China, Shenzhen 518110, China; wenjing11 [EMAIL_ADDRESS]  
[PERSON]  
3 The 58 th Research Institute of China Electronics Technology Group Corporation, Wuxi 214072, China; [EMAIL_ADDRESS]  
[PERSON]  
1 School of Automation Engineer, University of Electronic and Technology of China, Chengdu 611731, China; [EMAIL_ADDRESS]  
Footnote 1: [[https://www.mdpi.com/journal/applsci](https://www.mdpi.com/journal/applsci)]([https://www.mdpi.com/journal/applsci](https://www.mdpi.com/journal/applsci))  
Footnote 2: [[https://www.mdpi.com/journals/pdf/](https://www.mdpi.com/journals/pdf/)]([https://www.mdpi.com/journals/pdf/](https://www.mdpi.com/journals/pdf/))  
of the test. Therefore, the key to efficient FPGA testing lies in generating the least number of configurations necessary to achieve full coverage.  
While earlier research on interconnect resources testing within FPGAs focused mainly on testing the configurable logic blocks (CLBs) and random access memory (RAM) [3; 4], as well as developing testing methods for these components, such methods are no longer sufficient for testing today's larger and more complex FPGAs. In recent years, research has emerged that focused on testing interconnect resources, utilizing modeling methods based on directed graph theory, wiring algorithms, and built-in self-tests (BISTs) [4; 5; 6]. These studies abstract the metal interconnects and switch matrices into directed graph models, using path search algorithms based on directed graphs such as network maximum flow algorithms, depth-first search algorithms, and breadth-first search algorithms to achieve automatic testing of the switch matrices [7; 8].  
However, most of this research has yet to establish a general testing model, and there are few effective methods for determining and locating fault types. While machine learning methods have been employed in some testing studies, these approaches require a large number of training sets and can be hindered by long code running times and uncontrollable test costs. Therefore, we utilized an improved depth-first algorithm to validate the Kintex-7 FPGA. After nine configurations, we achieved coverage of 100%.  
Before testing an FPGA, it needs to be configured, which involves interconnecting resources to generate test paths. Manually configuring FPGA is time-consuming and increases testing costs due to the vast and complex interconnect resources. Therefore, in this paper, we propose an improved depth-first algorithm for wire routing search. Figure 1 is a structure diagram of the FPGA interconnect resource test process. Prior to the search, we need to extract and process the interconnect resources of the FPGA and convert them into models. Once the routing configuration file is generated, it is loaded onto the DUT (device under test) FPGA using an ATE (Automated Test Equipment) to complete the configuration. Then, the testing phase begins with the ATE applying stimuli to the DUT FPGA and collecting the corresponding responses to compare them with the expected results. By analyzing the comparison results, we can determine if the DUT FPGA has any faults. In this paper, the resource extraction and modeling process will be introduced in Section 3, the automatic wire routing search will be discussed in Section 4, and the utilization of ATE for configuration and testing will be explained in Section 5. Table 1 provides the abbreviations used in this paper along with their respective explanations.  
Figure 1: FPGA interconnect resource testing process.