# A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
## 1 Introduction  
A digital-to-time converter (DTC) is used to generate a time signal with a width that is proportional to the programmable input digital value. It has been widely used in the fields of automatic test equipment (ATE) or measurement instruments [1; 2; 3; 4; 5; 6; 7; 8; 9; 10; 11; 12]. High resolution is the most critical consideration in DTC design, which means high precision and high performance of ATE and measurement instruments. In terms of implementing methods, the DTCs can be classified as application specific integrated circuit (ASIC) DTC [1; 2; 3; 4; 5; 6; 7; 8] and field programmable gate arrays FPGA-DTC [6; 8; 11]. The resolution of ASIC-DTCs can be better than 1 ps, which is realized with the capacitor charging circuit. But the ASIC-DTCs are limited by small dynamic range, high cost and long development time. The DTCs also can be classified with absolute [1; 2; 3; 4; 5; 6; 7; 8; 9; 10; 11] or relative [8; 9; 10; 11] time generation due to different operations. The absolute time generations have wide dynamic ranges but poor resolution performance. They are also sensitive to process, voltage and temperature (PVT) variations. On the contrary, the relative time generations have much finer resolution and are robust to PVT. However, the relative methods are hampered by path or element mismatches.  
Since a digitally-implemented DTC is usually realized by logic gates or delay lines, FPGAs which inherently include logic gates and phase locked loops (PLLs) attract research interest on DTC implementation. Moreover, the lower cost and shorter time-to-market also motivate the development of FPGA-DTCs. Nowadays, FPGA-DTCs which are realized by phase-shifting can obtain about 8 ps resolution [6; 9]. To increase the resolution, a DTC based on the Vernier principle was proposed in [11]. It achieved a 1.58 ps resolution using two integrated PLLs with Altera Stratix-III FPGA. Similarly, thequantified phase shift resolution (QPSR) DTC proposed in [8] obtained a 3.93 ps resolution with Xilinx Virtex-6 FPGA. However, the high resolution of these methods is achieved with advanced FPGAs. The Vernier DTC and QPSR DTC realized with Xilinx Virtex-5 FPGA only obtained 35.27 ps and 27.1 ps resolution, respectively. Therefore, a high resolution and low-cost FPGA-DTC is not only valuable for practical applications, but also very challenging for researchers.  
In this paper, a novel DTC realized with the three delay lines Vernier principle (3D Vernier DTC) is proposed and evaluated. The resolution of the proposed DTC is 203 fs implemented with Altera Stratix-III FPGAs. The theoretical resolution of 3D Vernier DTC can be tenfold higher than traditional Vernier DTCs and QPSR DTCs implemented with the same FPGAs. Moreover, the DTC obtains 13.5 ps resolution even with the cheapest Altera Cyclone-IV E FPGAs. The high-resolution performance of the proposed DTC benefits from the high, medium and slow Vernier delay line constructed by PLLs, which ensures fine resolution and robustness to PVT variation.  
This paper is organized as follows. Section 2 describes the principle and structure of the proposed DTC. Section 3 presents the realization and experimental results of the proposed DTC system. Sections 4 and 5 discusses the results and concludes the paper, respectively.