# A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow
## 4 The Proposed Inverter-Based D2S Converter with Enhanced Common Mode Rejection  
Inverter-based OTAs require a differential-to-single-ended (D2S) converter that determines the overall common mode rejection ratio (CMRR) and input common mode range (ICMR) of the amplifier. In the context of inverter-based OTAs, the conventional approach to implement the D2S converter exploits an inverter that drives another inverter whose input and output terminals are connected to each other, thus obtaining a voltage gain approximately equal to \(-1\)[59]. However, due to the poor matching and the low intrinsic gain of the inverters, this approach results in poor CMRR performance and high sensitivity to PVT variations if the bias point is not properly stabilized. Recently, a novel topology of an inverter-based D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier, and a local feedback loop, was presented by the authors in [33]. The D2S in [33] exhibits higher CMRR, improved ICMR, and better robustness with respect to PVT variations than the conventional inverter-based D2S.  
In this paper, to further improve the CMRR and robustness to PVT variations, we propose an enhanced version (\(D2S_{E}\)) of the D2S in [33], whose schematic is depicted in Figure 4. In particular, the proposed \(D2S_{E}\) exploits the two-stage standard-cell-based error amplifier reported in Figure 5 to boost the gain of the feedback loop with respect to the previous version. As further modifications, we have also added the inverters \(I_{7}\) and \(I_{8}\) to accurately set the output static voltage of the \(D2S_{E}\) and to provide a low-output impedance as discussed in Sections 2 and 3. The factor \(h\) in the inverters \(I_{3,4,5,6}\) in Figure 4 denotes the number of reference inverters in parallel used to implement each one of the inverters \(I_{3,4,5,6}\), whereas, referring to Figure 5, the factor \(g\) in the inverters \(I_{o,2,1,2,3,5}\) denotes the number of reference inverters in parallel used to implement each one of the inverters \(I_{e0,e1,e2,e3,5}\).  
Figure 4: Standard-cell D2S converter with enhanced common mode rejection.  
The gain of the proposed improved error amplifier can be computed as:  
\[Av_{err}(s)\approx\frac{gm_{e_{0}}}{gds_{e_{0}}+gds_{e_{3}}+gds_{e_{4} }+gm_{e_{4}}}\cdot\frac{gm_{e_{5}}}{gds_{e_{5}}+gds_{e_{6}}+gm_{e_{6}}}\cdot \frac{gm_{e_{7}}}{gds_{e_{7}}}\cdot\\ \cdot 1\bigg{/}\bigg{(}1+s\frac{Cgs_{e_{4}}+Cgd_{e_{0}}+Cgd_{e_{3}}} {gm_{e_{4}}}\bigg{)}\cdot 1\bigg{/}\bigg{(}1+s\frac{Cgs_{e_{6}}+Cgd_{e_{5}}+Av_{e_{7}}Cgd_{e_ {7}}}{gm_{e_{6}}}\bigg{)}\\ \cdot 1\bigg{/}\bigg{(}1+s\frac{C_{L}+Cgd_{e_{7}}}{gds_{e_{7}}} \bigg{)} \tag{16}\]  
and, considering the definition of \(g\), it can be rewritten as:  
\[Av_{err}(0)=\bigg{(}\frac{g}{1+(2+g)/Av_{inv}}\bigg{)}^{2}Av_{inv}. \tag{17}\]  
It has to be remarked that the proposed two-stage error amplifier does not require any internal compensation if its load capacitance (i.e., the sum of the input capacitances of \(I_{5}\) and \(I_{6}\) in Figure 4) is high enough to guarantee a good phase-margin in the range of operation of the OTA.  
The frequency response of the proposed \(D2S_{E}\) converter can be derived as follows:  
\[Av(s)=\frac{gm_{4}}{gm_{7}+gds_{7}+gds_{4}+gds_{8}+dsg_{6}}\cdot\frac{1}{1+s \frac{Cgs^{2}+Cgd_{6}+Cgd_{6}+C_{L}}{g^{m_{7}}+gds_{7}+gds_{4}+gds_{8}+gds_{6}}} \tag{18}\]  
and, remembering the definition of the factor \(h\), the dc differential gain can be simplified as:  
\[Av(0)=h\cdot\frac{gm}{gm+(3+h)gds}=\frac{h}{1+(3+h)/Av_{inv}}. \tag{19}\]  
By following the same aprroach reported in [33], the CMRR of the proposed \(D2S_{E}\) can be derived as:  
\[CMRR=\bigg{(}\frac{g}{1+(2+g)/Av_{inv}}\bigg{)}^{2}\cdot\frac{Av_{inv}^{2}}{2}. \tag{20}\]