# FPGA Implementation of a Higher SFDR Upper DDFS Based on Non-Uniform Piecewise Linear Approximation
## 3 Hardware Architecture of DDFS
### Single-Core DDFS  
Before introducing the overall architecture of DDFS, we discuss the hardware implementation of the PWL approximation. Suppose we obtain the \(s\) linear segments of the sin function by executing the PWLMMAE algorithm introduced in the previous section in MATLAB, and the start point, end point, slope \(a\), and intercept \(b\) of each segment are \begin{table}
\begin{tabular}{c c c c} \hline \hline
**i** & **a** & **b** & **End Point** \\ \hline
1 & 1.54503497834031 & 0.000990880661757787 & 0.2001953125 \\
2 & 1.43612208005773 & 0.0227876190983088 & 0.326171875 \\
3 & 1.2977670692432 & 0.0679214996797700 & 0.43359375 \\
4 & 1.14069314244100 & 0.1363041900189 & 0.5302734375 \\
5 & 0.97032027885993 & 0.226383524844325 & 0.62109375 \\
6 & 0.79035884163542 & 0.338143580690051 & 0.70703125 \\
7 & 0.604027272905406 & 0.469880462191978 & 0.7900390625 \\
8 & 0.412863639934916 & 0.620903909462291 & 0.87109375 \\
9 & 0.218415511777311 & 0.790288325648528 & 0.951171875 \\
10 & 0.0602097594473886 & 0.940157596611038 & 1 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Segmentation results of the first quadrant of the sin function. Figure 3: PWL approximation of the sin function. also obtained. We store the \(a\) and \(b\) of each segment in two separate LUTs. The hardware implementation architecture of the PWLMMAE algorithm is shown in Figure 4. In order to compute the approximate function value of the input \(x\), the first step is to determine in which interval segment the input \(x\) is located before indexing to the corresponding \(a\) and \(b\). The independent variables in the first quadrant of the \(\sin\) function are all positive, and both the interval endpoints and the input can be expressed as unsigned numbers, so we use \(s-1\) parallel comparators and a multiplexer to implement segment indexing instead of using a subtractor as in [30]. Comparison of unsigned numbers is obviously more efficient than subtraction, and it is sufficient to start comparing from the high significant bits. The input \(x\) is compared with the first \(s-1\) interval endpoints at the same time, if \(x\geq x(END_{i})\), then \(sign_{i+1}=0\), indicating that the input \(x\) is not in the \(i\)th segment, otherwise \(sign_{i+1}=1\), which does not mean that the input \(x\) is in the \(i\)th segment, and the results of the \(s-1\) comparators can form an \(s-1\) bits vector \(\{sign_{s}:sign_{2}\}\), which will be used as the input of the multiplexer to select the segment index. The mapping of this vector to segment index is shown in Table 2, where index1, index2 and indexs represent the address or index of the slope \(a\) and intercept \(b\) of the first, second and last segment in the LUT. After getting the segment index corresponding to the input \(x\), we can go to the LUT to get the corresponding \(a\) and \(b\), and then perform the multiplication and addition operation, which requires a multiplier and an adder. Since the bit width of input \(x\) and slope \(a\) are so long that the multiplication is time consuming, it is necessary to add a register after the multiplier. In this way, the delay for the whole approximate calculation is only one clock cycle. Now, we design the entire hardware architecture of DDFS based on the hardware architecture of the PWLMMAE algorithm described above. In fact, we only need to replace the PAC in Figure 1 with the PWLMMAE hardware architecture and then add simple control logic to exploit the symmetry of the \(\sin\) function. The entire DDFS architecture is shown in Figure 5. \begin{table}
\begin{tabular}{c c} \hline \hline \(\{sign_{s}:sign_{2}\}\) & **Index** \\ \hline \(s-1\)’b111...111 & index1 \\ \(s-1\)’b111...110 & index2 \\... &... \\ \(s-1\)’b000...000 & indexs \\ \hline \hline \end{tabular}
\end{table} 
Table 2: The mapping of the vector to segment index. Figure 4: The hardware architecture of PWLMMAE algorithm.