## 1 Introduction  
Advancement in the semiconductor industry has increased the demand for nanoscale devices for analog/ radio frequency (RF) and high switching speed applications, but, power consumption and reliability issues are the major concerns in integrated circuits (ICs), so compactness in devices is an urgent problem to be solved in nanoscale systems. According to [PERSON]'s law, drastic reduction in volume and cost of the devices will occur. However, as the conventional metal oxide semiconductor field effect transistors (MOSFETs) scale down continuously, the OFF-state current dramatically increases and short channel effects (SCE) are severely aggravated, and a limitation of 60 mV/Dec subthreshold swing (SS) cannot be broken. In addition, low switch ratio (Ion/Ioff) ratio and drain induced barrier lowering (DIBL) effect are also arising. In order to avoid these issues, a lot of novel structures have been proposed and investigated in recent years, among them, tunnel field effect transistor (TFET) [1; 2] is a selective candidate for future ultra-low power applications, where carrier injection from source to channel is modulated by a gate-controlled band to band tunneling (BTBT) mechanism. The structure of a conventional TFET consists of a gated p type region/intrinsic region/n type region (p-i-n) diode operating under a reverse bias condition and the gate bias determines the quantum tunneling barrier width at the source-channel interface. Benefitting from innovation of structure and mechanism, TFETs are compatible with conventional complementary metal oxide semiconductor (CMOS) process and can break the SS limit of 60 mV/Dec. Additionally, it is not influenced by the short channel effects (SCE) and the leakage current of conventional TFETs is small under the OFF-state condition [3; 4]. However, small ON-state current and large Miller capacitance are still inherent disadvantages in TFETs. To improve the ON-state current, a lot of novel structures of TFETs are proposed, for example, the L-shaped channel TFET (LTFET) [5; 6; 7], U-shaped channel TFET (UTFET) [8; 9], symmetric TFET (S-TFET) [10; 11], U-shaped channel with dual sources TFET (DS-UTFET) [12], covered source-channel TFETs (CSC-TFETs) [13], hetero junction TFET with T-shaped gate (HTG-TFET) [14], 2D materials channel TFET and hetero-bilayer TFETs [15; 16]. As a whole, TFETs reported in recent years adopt abrupt junction at tunneling interface, which leads to a complex fabrication processes and a high thermal budget. In addition, a heavily doped concentration in the channel and active region are also challenging during the fabrication process and it is easy to be influenced by random dopant fluctuations (RDFs) [17; 18; 19; 20; 21]. To avoid complex fabrication processes and high thermal budgets in TFETs, the junctionless tunneling field effect transistor (JLTFET) [22; 23; 24; 25; 26; 27; 28; 29; 30] has been studied extensively in recent years, which uses uniformly high-doping concentration in the source, channel and drain regions so that the doping concentration and type of channel region are consistent with source region and drain region. Due to uniform doping, the JLTFET is immune to random dopant fluctuations (RDFs) and overcomes complex fabrication processes in manufacturing, meanwhile, source and drain region are formed by the charge plasma concept which further avoids high thermal budgets in the JLTFET. Whereas, low ON-state current still remains the most serious problem in junctionless TFETs due to the presence of barrier between source and channel. In this paper, a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source was proposed to improve the performance of a conventional HJLTFET [31; 32], where the corresponding heavily p type doping region / intrinsic region / heavily n type doping region (P+-I-N+)structure can be realized by the charge plasma concept with appropriate workfunction for the polar gate (PG) and control gate (CG).