## 1 Introduction  
The growth of internet traffic over the last decade has pushed data capacity and increased the processing speed demand in modern computational server based networks such as data centers. Optical interconnection between the servers of the data centers can further enhance the data processing capacity of the network by exploiting space, time, and wavelength domains [1; 2; 3]. An important challenge is to design photonic integrated circuits (PIC) with complex optical signal processing functionalities such that many of the data processing tasks can be transferred from the electrical to the optical domain. PICs using low-loss optical waveguide on Si\({}_{3}\)N\({}_{4}\)[4] platform technology are a promising solution to implement some complex optical functionalities on-chip such as generating large optical time delay (_i.e._, by using optical buffers [5]) or building high quality factor resonators [6]. Propagation losses of 2.8 \(\upmu\)m \(\times\) 80 nm cross-section area Si\({}_{3}\)N\({}_{4}\) waveguides first reported in [7] were measured to be 8 dB/m (0.5 mm bend radius), and as low as 3 dB/m for larger bends (2 mm bend radius). Large bend radius is required in the low-loss Si\({}_{3}\)N\({}_{4}\) waveguide to reduce the mode-mismatch loss at the bending regions. Therefore, in the PIC applications, where compact waveguide routing is required, high index contrast waveguides, such as silicon on insulator (SOI) waveguides are preferable to Si\({}_{3}\)N\({}_{4}\) waveguides. Standard SOI waveguides (220 nm \(\times\) 500 nm cross-section area) with propagation losses of \(\sim\)2.5 dB/cm have been demonstrated with bending radii as low as 7 \(\upmu\)m [8]. However, to design optical buffer circuits using long length delay waveguides (_i.e._, in the range of meters to introduce several _ns_ time delay [1; 5]), SOI waveguides are not suitable. For example, to design the 12.86 ns delay line demonstrated in [5], a \(\sim\)0.92 m long 220 nm \(\times\) 500 nm cross-section SOI waveguide will exhibit around \(\sim\)230 dB loss. Therefore, recently demonstrated low-loss Si\({}_{3}\)N\({}_{4}\) waveguides are investigated to build integrated long optical buffers. Using a wafer-bonded silica-on-silicon planar waveguide platform, propagation losses as low as 0.1 dB/m are reported in [9], where the waveguide thickness is set to 40 nm and the waveguide width varies from 3 \(\upmu\)m to 14 \(\upmu\)m. The low trending propagation loss of Si\({}_{3}\)N\({}_{4}\) waveguides suggests that these waveguides can be used to build all optical packet routing PICs where long optical delay lines or low-loss optical buffer circuits are required [10]. In [1], for example, we proposed an analytical model of a passive wavelength striped (PWM) circuit, where an optical serial packet stream is converted to a parallel stream to increase the bandwidth scalability of optical interconnect networks. The PWM circuit implements simultaneous optical filtering and delays each time segment of the data with respect to its adjacent channel by a specific amount of time using optical buffers or long optical delay waveguides. To design an integrated version of the PWM circuit, low-loss Si\({}_{3}\)N\({}_{4}\) waveguides can be used to build its key building blocks (_i.e._, a demultiplexer to filter the optical channels and the long delay lines to implement the time delay between the adjacent channels). A low-loss arrayed-waveguide grating (AWG) demultiplexer using Si\({}_{3}\)N\({}_{4}\) waveguide platform is proposed in [11]. An AWG based demultiplexer on Si\({}_{3}\)N\({}_{4}\) waveguide platform presented in [11] (\(<\)0.5 dB insertion loss and 40 dB cross-talk) demonstrates better performance than the MZI filter based optical demultiplexers. However, in [1] we find that the AWG approach to build the demultiplexer in a PWM circuit incurs overall greater loss and increases the footprint of the PWM device due to the individual time delay requirements for each of the channels after the AWG.