# A Multi-Channel Data Simulator Based on the Time Unification System
## 2 System Architecture of Simulator  
Figure 2 depicts the system architecture of the proposed simulator, which comprises an FPGA controller, DDR, Serial Advanced Technology Attachment (SATA) solid-state storage, a PCIe\(\times\)8 interface, a 10-gigabit Ethernet (10 GbE) interface, a PPS interface, an input interface, and an output interface. The FPGA controller controls the various modules within the simulator and processes the input and output data. The DDR caches the input  
and output data, compensating for the timing differences between the SATA solid-state storage and the input/output interfaces. The PCIe interface transfers the simulated data, stored result data, and configuring parameters. The 10 GbE interface transmits real-time output simulated data via the User Datagram Protocol (UDP) and simultaneously receives real-time result data. The PPS interface receives the PPS signal from the time reference generator, synchronizing the output timing of various output interfaces, and forwards it to the host computer via the UDP protocol for time synchronization. The input and output interfaces communicate with the target system, encompassing high-speed interfaces utilizing the TLK2711 serializer-deserializer and low-speed interfaces such as the Recommended Standard 422 (RS422), Controller Area Network (CAN), and Low-Voltage Differential Signaling (LVDS). The simulator has two working modes: the storage mode and real-time mode. In the storage mode, the simulator imports and exports simulated data and result data in large quantities with the host computer through the PCIe interface. The simulator can achieve high-speed offline data simulation and high-speed data recording and storage. By inputting the stored simulated data in advance, the simulator can output the data stably at a fixed frequency and cycle and store the result data output by the target system at the same time. The storage mode of the simulator can achieve the synchronization of time between the simulator and the target system by inputting the time reference to simulate data transmission with a fixed period and delay. The simulator guarantees the fixed timing of the simulated output data through the two-level design of SATA solid-state storage and DDR. The SATA solid-state storage has a large capacity and can continuously simulate and output different data. Meanwhile, due to the storage's non-volatile characteristics, the simulated data can still be saved after the simulator is powered off. The high-speed result data generated by the target system can also be stored in the SATA solid-state storage. The DDR ping-pong buffer design can avoid data loss due to the occupation of the SATA bus during storage. The PCIe interface can transmit data at high speed from the simulator to the host computer, saving time for the import and export of huge amounts of simulator data. In real-time mode, the simulator and the host computer transmit data in real time through the 10 GbE interface. The real-time mode can achieve the input and output of the real-time results and simulated data of the target system. The host computer calculates and outputs simulated data based on the real-time input result data and performs closed-loop simulation verification. Figure 2: The system architecture of the simulator. The real-time mode of the simulator can simulate the real working environment of the target system in a closed loop. The simulator forwards the results of the target system to the host computer, and the host computer outputs the simulated data of the next moment based on the results and the PPS. UDP network data transceiving through the 10 GbE interface can effectively improve the real-time performance in terms of data output and reduce the closed-loop control delay. The storage mode and real-time mode of the simulator work independently and in parallel. While in real-time mode, the simulator simultaneously stores the result data of the target system in the SATA solid-state storage.