# A g\({}_{m}\)/I\({}_{\rm D}\)-Based Low-Power LNA for Ka-Band Applications
## 2 Design Procedure  
The g\({}_{m}\)/I\({}_{D}\) design procedure is a powerful sizing and biasing tool for MOSFET-based circuits [11; 12]. The methodology exploits the ratio between the transconductance and the drain current as they are both width-dependent parameters to obtain a width-independent design variable. Since this ratio gives the ability of a MOSFET to generate a small-signal current gain from a DC bias current, the g\({}_{m}\)/I\({}_{D}\) ratio is often referred to as the MOSFET efficiency. The characterization of a MOSFET in terms of g\({}_{m}\)/I\({}_{D}\) ratio allows the derivation of the main performance metrics of a circuit to provide a width-independent sizing tool, allowing fast optimization and near-first-time successful design. A series of LUTs can be generated to avoid conventional SPICE iterative simulations, and designers can apply optimization algorithms to find optimal sizing and operating points or simply explore the design space more efficiently [31]. The first step consists of simulating several devices to fully characterize their behavior and build the LUTs with fundamental DC, AC, and noise parameters. These values can then be used to design LNAs given the specifications and circuit topology. The floating-body (FB) transistors of the GlobalFoundries 4 SRFSOI process design kit (PDK) are chosen to design the LNA. Since they are FB transistors, they do not possess substrate contact. To analyze their behavior, several geometries are simulated to fully characterize the behavior of the FETs in the selected kit. The total width (W) is varied from 20 to 120 um in steps of 5 um; the length (L) comes in discrete values of 32, 40, and 48 nm; and the unit finger width (w\({}_{f}\)) is varied from 0.5 to 2 um, which is the maximum range available in the PDK. In addition, the DC voltage V\({}_{\mathrm{GS}}\) is varied from 0 V to 1 V in steps of 25 mV and V\({}_{DS}\) is varied from 0 V to 1 V in steps of 25 mV, using the schematic shown in Figure 1a, which is used to simulate all the parameters analyzed in this section. The DC parameters observed include the drain current I\({}_{DS}\), the threshold voltage V\({}_{TH}\), the gate-drain current I\({}_{GD}\), and the gate-source current I\({}_{GS}\). On the other hand, the AC parameters obtained are regular transconductance g\({}_{m}\), gate-bulk transconductance g\({}_{mb}\), drain-source transconductance g\({}_{ds}\), and all FET capacitances (shown in Figure 1b, gate-source C\({}_{gs}\), gate-drain C\({}_{gd}\), source-bulk C\({}_{sb}\), drain-bulk C\({}_{db}\)). Finally, the noise of the FET is characterized using two main parameters: STH and SFL (thermal and flicker noise, respectively). To automate the sweeps and generate the LUTs efficiently, the simulations are automated using a single MATLAB script that performs the following tasks:  
* Generates DC sweeps for all corners. These corners are generated by considering all possible combinations of process, temperature, and noise variations and depend on the PDK used. In this case, the combinations include typical (T), slow (S), and fast (F) devices with \(-40\)\({}^{\circ}\)C, \(16\)\({}^{\circ}\)C, \(125\)\({}^{\circ}\)C and high-, nominal-, and low-noise corners. * Maps the FET's operating point parameters into the desired output variables to build a multidimensional MATLAB matrix from the Cadence database results. * Generates the Spectre simulation netlists with the desired geometries and sweeps. * Sequentially runs all the previously generated simulations. * Generates a.mat file with the multidimensional data for each corner as a result. The original code provided by [11; 12] is adapted to accommodate the 4 SRFSOI PDK and the mentioned sweeps. A simple _lookUp()_ function is then used to recover the desired values and plot the desired parameters. More information about this process can be found in [11; 12].