# A Review of Cell Operation Algorithm for 3D NAND Flash Memory
## 2 Program Algorithm
### Improvement of the Program Disturb  
Compared to 2D NAND, there is a possibility that the program disturbance characteristics in 3D NAND are severely deteriorated due to the following reasons. First, because there are multiple strings in one block, new program disturbance stress modes, such as Y-mode and XY-mode, are added in conjunction with X-mode disturbances existing in 2D NAND [12]. In particular, since the number of slits for block-to-block separations is reduced to increase the chip density [11], the number of strings is expected to increase continuously; thereby, Y-mode program stress will be the main cause further diminishing the memory window. Second, since 3D NAND uses poly-silicon as channel material, the on/off characteristic of the select transistor is much worse than that of 2D NAND, and the off-state leakage current flows through the select gate in boosting mode, which weaken the program disturbance [13]. Third, since it is difficult to remove electrons in the poly-silicon channel during the pre-charge operation due to the grain boundary trap [14; 15], achieving high channel potential in boosting mode is very challenging. Fourth, when large channel potential difference between adjacent WLs is applied in the end of programming loop [16], the electron/hole pair generated via the trap-assisted band-to-band tunneling (BTBT) mechanism reduces the channel boosting potential [17; 18]. Fifth, due to the floating body characteristics of 3D NAND, a negative down-coupling phenomenon occurs during the falling of the verify pulse of the selected and the unselected WLs [19], aggravating the deterioration of the hot carrier injection (HCI) program disturb [20]. In this respect, various enhancement algorithms to improve the obstacles of the above program disturb will be described. [PERSON] et al. proposed a few approaches to suppress the program disturbance: keeping higher Vt level of top select transistor and adopting the negative top select transistor bias during program operation [12]. In the Y-mode program disturbance, unselected strings hanging on the same BL in the program cell should be inhibited with the same BL bias 0 V. Therefore, both forming a high Vt level of the top select transistor and applying the negative bias in top select transistor during program operation can present better cut-off characteristics of select transistors. However, if too high a negative voltage is applied,  
Figure 1: (**a**) WL pitch scaling. Reprinted/adapted with permission from Ref. [10], 2020, IEEE. (**b**) TLC NAND scaling trends of program throughput and parallelism. Reprinted/adapted with permission from Ref. [11], 2020, IEEE. gate-induced drain leakage (GIDL) current is rapidly generated at the junction overlap region underneath the select transistor, which could make boosting level lower. To reduce the increasing Y-mode program stress, [PERSON] et al. proposed an improved pre-charging method [21], as shown in Figure 2. A block has several upper select transistors, while WLs and lower select transistors are shared within a block. The sharing of WLs allows the memory area to be reduced; however, the unselected strings are also disturbed, since the program voltage is applied through the shared WLs. To decrease program disturbance of an unselected string, a very high bit line (BL) bias is applied to the unselected string before the program operation, enhancing the initializing efficiency of the channel potentials. However, for this operation, a high BL bias must be transmitted to the channels of unselected strings, so there is a side effect of an increase in programming time. Therefore, this method is not used at the beginning of ISPP operation, but only during the last program pulse loop, when channel boosting is insufficient to minimize program disturbance degradation. On the other hand, to further improve the program disturbances caused by electrons trapped at the grain boundary of the poly silicon channel, [PERSON] et al. proposed a new pre-charge method [22].