# LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems
## 5 VLSI Implementation of Dual-Mode LDPC Decoder for 5G NR Systems
### Post-Layout Implementation Results  
Using the ASIC design flow, the decoder is synthesized and implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm complementary metal-oxide-semiconductor (CMOS) process with a working frequency of 294.1 MHz. There are three major costs located in the posterior and extrinsic memory, with a cell area of approximately 42.2%; arithmetic units with 64 parallelisms and a cell area of about 25.2%; and the network/de-network in pipelines with a cell area of approximately 22.7%. The proposed dual-mode LDPC decoder operates with two different code lengths, and the highest throughput meets the throughput requirement of the 5G NR standard, which is higher than 10 Gb/s. To evaluate the throughput of the proposed dual-mode LDPC decoder, the throughput estimation equations used for the decoder are as follows:  
\[\textit{Throughput}\ (TP)\ =\ \frac{CL\times f}{\big{(}\frac{\hat{p}}{\hat{p}}+N_{pipe }\big{)}\times N_{row}\times N_{iter}}, \tag{23}\]  
where \(CL\) and \(f\) denote the code length and frequency, respectively; \(z\) and \(P\) are the expending factor and number of parallelisms, respectively; and \(N_{pipe}\), \(N_{row}\), and \(N_{iter}\) represent the  
Figure 8: Architecture of (**a**) CNU and (**b**) Min & Index Finder using the proposed compensation scheme of group comparison. number of pipeline stages, the base row, and the maximum iterations, respectively. Without employing the early termination, the throughput reaches at least 10.86 and 5.84 Gb/s in BG 1 and BG 2, respectively. The highest throughput of the decoder in BG 1 mode can exceed the throughput requirement of 10 Gb/s for the 5G NR systems. Figure 9 illustrates the chip layout and Table 3 lists the summary of post-layout results of the proposed dual-mode LDPC decoder. Table 3 also lists a comparison of recent studies for the 5G NR systems. The studies in [23; 24] achieved post-layout and post-synthesis (pre-layout) implementations, respectively. Compared to the post-synthesis implementation, the post-layout implementation contains more hardware information, including the logic gate placements, clock tree synthesis, and wire routing. It is worth noting that the studies in [23; 24] focused on the low code-rate (high correcting ability) LDPC decoding and this study focused on the high code-rate (high transmission rate) LDPC decoding for the 5G NR systems. Thus, it is hard to compare these application-specific integrated circuits (ASICs) because their design parameters are very district. To achieve a fair evaluation of the LDPC decoder ASICs using the distinct CMOS processes, however, the normalized area efficiency (NAE) and energy efficiency (NEE) are widely used [25] and evaluated in terms of the 40 nm CMOS process in this study. The NAE denotes how many decoded bits per unit area can be achieved in the decoder. The NEE denotes how much energy per decoded bit is consumed in the decoder. In early 2021, the study in [23] proposed the LDPC decoder ASIC for the 5G NR standard using a layered combination min-sun algorithm (CMSA) decoding to achieve the features of low complexity and high throughput. It supports a low rate-1/3 BG 1 with a code length of 3808. Using the TSMC 65 nm CMOS process, it achieves a maximum throughput of 3.04 Gb/s with a NAE of 7.18 bits/mm\({}^{2}\) and a NEE of 42.48 pJ/bit. To further support the low rate-1/3 BG 1 with the maximum code length of 25,344 and low rate-1/2 BG 2 with a maximum code length of 19,200 in the 5G NR standard, the study in [24] proposed a reconfigurable LDPC decoder ASIC using a layered NMSA decoding accompanied with instruction-level reordering and data-level rescheduling. Because it achieves 33.2 Gb/s/iteration using the TSMC 28 nm CMOS process, the throughput rates are 6.64 Gb/s at average iterations of 5, and 7.92 Gb/s at average iterations of 4.92, for the rate-1/3 BG 1 and rate-1/2 BG2 LDPC decoding, respectively.