## 2 Quasi-Static Analysis Using the Proposed Equivalent Circuit Model  
The plasmon detector using a CMOS field-effect transistor (FET) was simplified with the basic configuration shown in Figure 1a. The gate node of the plasmon detector was directly coupled with the integrated antenna. The terahertz signal was received through the integrated antenna and transmitted to the gate of the detector device. The detector gate was also provided with an external gate bias voltage to control the modulation of the internal channel of the transistor [23]. The input signal \(v_{IN}\) of the plasmon detector can be expressed with a terahertz input signal \(v_{THz}\) and an external gate bias \(V_{G}\) at high frequency as follows:  
\[v_{IN}=v_{THz}+V_{G}. \tag{1}\]  
The detector input is connected to the input port of the integrated antenna and the external gate bias line through the transmission lines [24]. The transmission lines exhibit different electrical properties depending on the length of the transmission lines by the lumped-element model. The impedance of the transmission lines is modeled as the characteristic impedance considering the return loss and is modeled as constant impedance when the transmission line length is fixed. When the input port of the integrated antenna is connected to the gate of the detector device, the impedance from the integrated antenna to the point where the external gate bias line meets is expressed as \(Z_{IN}\). The impedance from the external gate bias line to the point where the input port of the integrated antenna meets corresponds to \(Z_{Bias}\). The impedance connected to the detector input from the point where the input port of the integrated antenna meets the external gate bias line corresponds to \(Z_{G}\). The source of the detector device connected to the ground is ideally virtual ground, but a few offset voltages can be generated due to the wire bonding line. The characteristics of the interconnection line from the source of the device to the ground are denoted as the impedance \(Z_{sp}\).  
The detector device is modeled as a voltage source using a small-signal method as shown in Figure 1b because the terahertz signal that is applied to the detector input is extremely small. The current flowing at the detector device is determined by the detector input signal and transconductance. The relationship between the changes in the input voltage and output current of the detector at different frequencies is assumed as a plasmonic conversion transconductance \(g_{c}\). The equivalent impedance of the detector device from the detector input corresponds to \(z_{DT}\). The impedance \(z_{DS}\) at the detector output node is represented by a parallel connection of the parasitic capacitor and load resistance and is expressed as  
\[z_{DS}=C_{DS}//R_{DS}=\frac{R_{DS}}{1+j\omega C_{DS}R_{DS}}. \tag{2}\]  
The output voltage of the detector has an AC signal that the terahertz input signal is coupled through the parasitic capacitor \(C_{GD}\) between the gate and the drain. The output node also detects DC signals based on the magnitude of the terahertz signal and generates a DC offset voltage by the structure of detector device [18]. The DC offset voltage has an effect on the output characteristics since the response to the terahertz input is shown in the DC voltage at the drain node of the detector. However, the proposed analysis neglects the DC offset voltage at the drain node, and it is assumed that the source of the detector device becomes ground.  
Figure 1: Schematic diagrams of the proposed model for the plasmon detector using the field-effect transistor (FET) at high frequency: (**a**) Basic model including the parasitic capacitances; (**b**) modified model for small-signal analysis.