# Towards Large-Scale Fast Reprogramable SOA-Based Photonic Integrated Switch Circuits
## 4 Monolithically Integrated InP 8 \(\times\) 8 Space and Wavelength Selecting Switch
At the optical plane, four different wavelength channels, \(\lambda_{0}\), \(\lambda_{1}\), \(\lambda_{2}\), and \(\lambda_{3}\), with a nominal channel separation of 400 GHz are multiplexed and modulated using a Mach-Zehnder modulator. The WDM signal is then amplified, de-multiplexed, de-correlated, and used as input to the device with 0 dBm channel power. The chip output is connected to a pre-amplified optical receiver after a 0.95 nm bandwidth filter for broadband noise rejection. An average total current per path of the order of 140 mA is used. Optical signal to noise ratios greater than 27.0 dB for 0.1 nm resolution bandwidth and a mean 13.3 dB on-chip loss are measured for each of the channels of a  
Figure 2: (**a**) Architecture and (**b**) composite image of the active-passive InP 8 \(\times\) 8 cross-connect. multiplexed channel, as evaluated at a representative path from input 0 to output 0 [27]. With the maximum number of three SOAs on a single path, no oscillation is observed. When moving to a bigger number of gates, the inclusion of isolation sections may be needed. The electrical plane comprises fast current drivers and programmable logic. A multiple current source provides DC currents to the pre-amplifying SOAs. Fast current drivers connect to the SOA selector gates of the integrated cross-connect to enable path and channel selection. The current levels for each of the SOA selector gates is separately programmed by means of digital-to-analog converters (DACs) and a central microcontroller. An Altera Stratix III field programmable gate array (FPGA) provides time-slotted control signals to the nanosecond rise-time current drivers for optical path selection. Bit-level synchronization is achieved between the routed data and the switch controller by means of a common reference clock generator between the FPGA and the bit error rate (BER) test equipment. To demonstrate simultaneous WDM multi-path data routing the wavelength multiplexed data is split into four copies using broadband splitters and launched into four input ports: 0, 1, 6, and 7 of the chip. Sixteen channels are routed within the 8 \(\times\) 8 cross-connect to output port 0. All four input paths are sequentially enabled with a round-robin scheduling and loaded with WDM input signals for dynamic multi-path WDM reconfigurability studies. The correspondent SOAs are driven by periodic 1 \(\upmu\)s pulses with 60 ns guard-bands programmed via the FPGA. Figure 4a shows the time traces of the output WDM signals. Along the x-axis the selected input port changes at each time slot as for the round-robin scheduling. The four sets of wavelengths are selected using external optical filters and are displayed as four separate graphs. The time traces appear to be clean and well resolved. The optical power is levelled for each wavelength to within 2 dB, as the current values have been optimized for equalized output power from time-slot to time-slot. Figure 4b also shows the fall and rise time for the output signal when moving from one time slot to the next one: The switching occurs within 5 ns [34]. Power penalty is expected to be dominated by amplified spontaneous emission from the transmitter side amplifier and the cross-connect. For higher input powers and number of wavelengths per channels, new optical amplifier concepts based on low-overlap between the mode and the gain area may prevent unwanted cross-gain modulation. The requirements for reduced energy use also require the photonic components to be abstracted to enable tractable network level implementations: Multicast capability, packet-time-scale reconfigurability, power levelling irrespective of signal path, distributed signal quality monitoring,  
Figure 3: Setup for wavelength division multiplexing (WDM) single and multi-port simultaneous routing. FPGA: field programmable gate array. and data rate transparency have been implemented at the chip level in order to enable an abstracted digital control plane [34; 35; 36].