###### Abstract  
Interconnects are significant elements in integrated circuits (ICs), as they connect individual components of the circuit into a functioning whole. To form a void-free interconnect, a thin and uniform copper seed layer must be deposited as a basis for electroplating. In this paper, process parameters of sputtering including incident energy, incident angle, substrate temperature, and deposition rate were studied to form a uniform copper seed layer. Different liner/barrier materials and properties including crystal planes were also studied to enhance the quality of the copper seed layer. The study was carried out by molecular dynamics simulation. It revealed that increasing the incident energy and substrate temperature during the sputtering process increases their diffusivity but results in poorer uniformity and larger alloy percentage. By decreasing the deposition rate, the Ostwald ripening effect becomes dominant and increases the uniformity. An adequate incident angle could increase necking and uniformity. Among the sputtering process parameters and material properties discussed in this study, surface diffusion barrier energy of different crystal planes is the most decisive factor, which leads to good uniformity. copper seed layer; integrated circuit; interconnect; liner/barrier; metallization; molecular dynamics simulation; physical vapor deposition; sputtering; thin film +
Footnote †: journal: Applied Sciences  
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Several techniques have been developed to overcome this shadowing effect, such as directional physical vapor deposition (PVD) and ionized PVD. Directional PVD includes long-throw deposition [1] and collimated sputter deposition [2]. [PERSON] et al. [3] presented the well-known ionized PVD technique and its application to interconnect manufacturing, which was proposed by [PERSON] [4]. Liner and barrier layers are other important topics in copper interconnect manufacturing. Generally, the liner and barrier layers comprise a bilayer of tantalum and tantalum nitride (Ta/TaN) [5] surrounded by a dielectric layer of silicon nitride (SiN). There are some alternatives to tantalum-based barrier layers, such as the titanium (Ti)-based barrier layers. However, the copper barrier efficiency of titanium is not as good as tantalum-based films. Therefore, [PERSON] et al. [6] presented a multilayer film of Ti/TiN/Ti as a copper diffusion barrier layer. TiN prevents excessive reaction between titanium and copper, which increases the resistivity of wire, while the top titanium layer provides good wetting of copper films because the copper wetting on TiN is very poor. One of the most promising liner/barrier layers discussed recently is the Co/TaN bilayer [7]. Other liner/barriers such as the Mo/MoN bilayer [8] and the W/WN bilayer [9] are also alternatives to the Ta/TaN bilayer. Simulation of the Damascene process has been carried out by the Monte Carlo method and molecular dynamics simulation. [PERSON] et al. [10] presented a study of deep submicron interconnect metallization with a modified kinetic Monte Carlo method, while [PERSON] et al. [11] studied trench filling by ionized PVD with the Monte Carlo method. [PERSON] et al. [12] and [PERSON] et al. [13] carried out the study of copper trench filling in the Damascene process by molecular dynamics. Molecular dynamics simulation describes the atomic motion of constituent particles that satisfy the law of classical mechanics at the atomic scale. The superiority of the molecular dynamics approach becomes apparent as the size of the system decreases. As features of integrated circuits scale down in size constantly, the atomic level simulation of the trench filling process would advance a deeper understanding of film growth mechanisms.