# HAIPO: Hybrid AI Algorithm-Based Post-Fabrication Optimization for Modern 3D NAND Flash Memory
## 1 Introduction  
NAND flash memory is the key memory technology in architecting modern storage systems. NAND flash-based solid-state drives (SSDs) provide various advantages over traditional hard disk drives (HDDs), such as high performance, low power consumption, and small form factor while achieving high device capacity (e.g., several tens of terabytes per SSD [1, 2, 3, 4]). However, due to the rapid expansion of the data-centric computing market, NAND flash-based solid-state drives (SSDs) are faced with new challenges that should meet various requirements simultaneously. For example, data center applications require quality of service (QoS), in which 99.99% or 99.9999% of the total read requests should be performed without delay in response time. In addition, due to the explosive increase in data generation, NAND flash memory is required to satisfy large capacity, high reliability, and high performance at the same time. To successfully implement a mass production system based on high yield while satisfying various requirements of modern applications, post-fabrication optimization. (Generally, many NAND manufacturers and storage companies have referred to tuning eFuses to improve their characteristics after manufacturing the chip as \"post-manufacturing optimization\". In our paper, we use the term \"optimization\" following such a convention.) isan essential step in the manufacturing process of modern NAND flash memory. After fabricating a chip, manufacturers configure various device parameters (e.g., the voltage/timing parameters for read/program/erase operations) that determine the chip's performance, reliability, and yield. Chip information related to device parameters is stored in special NAND flash cells. (The minimum unit for storing data in NAND flash memory is called a flash cell.) During system booting, the NAND flash chip reads the chip information stored in the special NAND flash cells according to the power-up sequence. The NAND flash chip moves it into a register-type circuit with a latch structure called an eFuse (electrical fuse) in peripheral circuits to access the chip information. All device parameters affecting the NAND flash memory characteristics (i.e., reliability and performance) are determined by the combinations of eFuse values. Post-fabrication optimization is a complex and time-consuming process that determines the best device parameters based on the optimized eFuse combinations. Traditionally, post-fabrication optimization has been manually done by experienced engineers at NAND manufacturers. However, manual-based post-fabrication optimization is no longer practical in modern high-capacity 3D NAND flash chips for three reasons. First, the number of device parameters to optimize for a single chip has significantly increased. For example, a modern triple-level cell (TLC) NAND flash chip has more than thousands of device parameters that must be carefully configured depending on the physical characteristics of target NAND flash cells. Second, there exists a complex trade-off correlation between NAND flash memory performance, reliability, and yield. For example, improving performance can lead to reliability degradation or make it difficult to secure high yields. Moreover, in modern NAND flash chips, such correlation between device characteristics shows significant variations between flash chips, flash blocks within a single chip, and even pages in a single block. (Generally, a NAND flash chip consists of thousands of blocks, and a single block comprises multiple pages.) Therefore, the difficulty of post-fabrication optimization increases exponentially as NAND flash memory technologies are advanced. Finally, post-fabrication optimization is a time-critical task. To meet the limited product turnaround time (TAT), i.e., the amount of time taken to complete the chip production since the start of development, post-fabrication optimization should be completed in quite a short time (e.g., a few days).