# Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems
## 3 Integrated Circuits
### Noise-Power Efficient Double-Gated Push-Pull Preamplifier Using Quasi-Floating Body  
In most of low-power, low-noise operational transconductance (\(g_{m}\)) amplifiers (OTAs) in the previous works, the transconductance (\(g_{m}\)) of the input transistors was maximized for high noise-power efficiency by operating them in the subthreshold region, the transconductance in the rest of the transistors was minimized by making them operate in the strong inversion region [21; 22]. Recently, a push-pull topology (often called as a current reuse topology) was adopted to double the effective \(g_{m}\) of the input transistor [23; 24; 25; 26]. In this work, we have introduced a double-gated, push-pull preamplifier where the body terminal of the input transistors is used as the second gate to further improve the noise-power efficiency. Figure 3 illustrates the double-gated PMOS transistor implemented by using a quasi-floating body. In power-on state, the source potential initially connects to the supply voltage (\(V_{DD}\) = 1 V), and the body is biased by a source-body junction diode which is weakly in forward-bias. As the potential of the body approaches to that of the source, the body is biased by a leakage current through a large parasitic resistive path (\(R_{\text{LEAK}}\approx 50\) G\(\Omega\)) from the source, making the body can work as another input gate in  
Figure 2: Photograph of the fabricated neural interface module and the flexible microelectrode array (**left**), the block diagram of integrated circuits in the module (**right**). the transistor. In the steady-state condition, the body leakage current is about 2 pA and the potential becomes ~900 mV, while maintaining a potential difference of 100 mV from the source terminal (according to our SPICE simulation). In the actual implementation, the quasi-floating bodies in the NMOS transistors are formed by using the triple wells from the given process technology. Both PMOS and NMOS transistors are isolated from rest of the transistors by using the double guard-rings in the layout. The overall schematic of the proposed preamplifier is shown in Figure 4. The effective transconductance of the OTA, \(G_{m}\), can be given by:  
\[G_{m}=\underbrace{g_{m1}+g_{m3}}_{Push-Pull~{}Stage}+\underbrace{g_{m1}+g_{m 3}}_{Quasi-Floating~{}Body}=2g_{m}(1+\eta)\approx 2.4g_{m} \tag{1}\]  
where \(\eta\) is a body transconductance ratio, \(g_{m\eta}/g_{m}\), which is approximately given as ~0.2 in 0.25 \(\upmu\)m CMOS processes. When an input signal is applied to both gate and body through capacitive coupling, \(G_{m}\) is expected to increase by a factor of 2.4 because it consists of the sum of gate transconductance (\(g_{m}\)) and body transconductance (\(g_{mb}\)). This means that we can achieve the reduction in input-referred noise (IRN) by a factor of 2.4, compared to the conventional OTAs where the input signal is applied to a single NMOS or PMOS transistor. In this topology, the closed-loop gain is determined by the capacitive ratio between \(C_{IN}\) and \(C_{F}\) (or \(C_{IN\_PN}\) and \(C_{F\_PN}\)) as given by:  
\[A_{v\_QFB}=\frac{-(g_{m}+g_{mb})r_{out}}{1+\frac{C_{F}}{C_{F}+C_{IN}}g_{m}r_{ out}+\frac{C_{F}\_{PN}}{C_{F\_PN}+C_{IN\_PN}}g_{mb}r_{out}}\approx\frac{-(g_{m}+g_{mb} )r_{out}}{1+\frac{C_{F}}{C_{F}+C_{IN}}(g_{m}+g_{mb})r_{out}}\approx-\frac{C_{ IN}}{C_{F}} \tag{2}\]  
where \(r_{out}\) is the resistance seen from the output nodes (\(V_{ON}\) or \(V_{OP}\)). To achieve a stable closed-loop gain, the cascode transistors, \(M_{\text{S1-S4}}\), are added in order to boost the output impedance. The simulation result shows that an open-loop gain of \(>\)80 dB is achieved from the single stage amplifier with an aid of cascade transistors. The values of the input and feedback capacitors are carefully chosen by considering the input impedance and the strength of \(g_{m}\) and \(g_{mb}\) in the amplifier. Assuming the high \(G_{m}\) of the given amplifier, the input impedance is roughly determined by the combination of \(C_{IN}\), \(C_{IN\_P}\), and \(C_{IN\_N}\).