# A Low-Complexity Start-Stop True Random Number Generator for FPGAs
## 3 The Quality of Bit Streams Produced by the Proposed Generator
The second criterion ensures that random sequences originate from phenomena for which non-deterministic processes prevail. The third criterion assures the high statistical integrity of the generated sequences. The fourth criterion excludes TRNGs that provide comparable security while demanding substantial resources or consuming excessive power. However, the existing literature predominantly features proposals that do not adhere to the first two conditions, which stem from the characteristics and historical development of FPGAs, along with the relatively recent NIST recommendations on entropy sources for generating random sequences [47]. Consequently, the number of proposals validated using the comprehensive methodology outlined by NIST is relatively small [28; 29; 36; 38; 39; 40; 41; 42; 52]. We refrain from discussing the efficacy of alternative methods for assessing the randomness of generated sequences here. Alternatively, evaluations can employ AIS-31 tests [53; 54], tests from the TU01 package [44], or DieHarder [45]. Some authors adopt a hybrid approach, evaluating the entropy source with NIST 800-90B tests while verifying statistical properties, using methods such as AIS-31 [37]. This choice highlights the preference for NIST's methodology despite its limited adoption in everyday research practices. Meanwhile, the proposed method by BSI remains in the draft stage [54]. Table 7 compares TRNGs that meet criteria (I)-(IV). Notably, the proposed generator achieves a throughput of up to 10 Mbit/s consistently across various FPGA manufacturing technologies, belonging to the category of generators characterized by low complexity and resource requirements. The specific resource values depend on the layout type. What sets this proposal apart from other known designs meeting criteria (I)-(IV) are its complete scalability and portability across different chips and predominant FPGA technologies. In contrast, other authors' designs (listed in Table 7) are tailored to specific chip types and may not function reliably when implemented on different FPGA technologies. The concept of scalability involves deploying multiple instances of the same TRNG within an FPGA without requiring further adjustments to their placement. For example, by integrating 32 instances of the TRNG shown in Figure 3 into a single FPGA, the bit generation rate can be substantially increased to 320 Mbit/s. However, it is crucial to consider that augmenting the number of instances also amplifies complexity, resource utilization, and power consumption due to the rapid switching of flip-flops. Therefore, while \begin{table}
\begin{tabular}{l c c c} \hline \hline \multicolumn{1}{c}{\multirow{2}{*}{**TRNG Design**}} & \multicolumn{2}{c}{**Number**} & \multicolumn{1}{c}{**Throughput**} \\
**Technique** & **LUTs** & **Flip-Flops** & **[Mbit/s]** \\ \hline Self-timed rings [28] & 56 & 19 & 100 \\ Fibonacci-Galois RO [29] & 288 & 190 & 400 \\ Metastability+jitter [36] & 4 & 3 & 0.76 \\ Metastability+jitter [38] & 36 & 0 & 12.50 \\ Multi-stage feedback ring oscillator [39] & 24 & 2 & 290 \\ RO with XOR gates [40] & 13 & 4 & 500 \\ Non-identical ROs [41] & 15 & 13 & 3.50 \\ Delay-Difference-Cell [42] & 256 & 256 & 225 \\ Metastability [52] & 14 & 6 & 25 \\ RO with XOR gates [8] & 23 & 23 & 10 \\ WTD2 (this work) & 11 & 13 & 10 \\ \hline \hline \end{tabular}
\end{table} 
Table 7: A comparison of TRNGs that meet conditions (I)–(IV). scalability offers enhanced throughput potential, the fundamental limitation remains the availability of FPGA resources required for building these TRNGs and power consumption, especially in devices such as IoT.