# Smart Energy Meters for Smart Grids, an Internet of Things Perspective
## 3 Computational Platforms  
Computing devices for the embedded domain have exploded in complexity, functionality, and versatility, resulting in the enabling of ever-growing complexity in the IoT sensing or physical layer design. From microcontrollers to single-board computers to application-specific integrated chips to programmable devices to integrated systems on chip, the computing hardware scene has exploded with complexity of choice and configuration, making it difficult to holistically review the state of the art; the task is only further complicated by the myriad of architectural requirements of modern smart metering solutions and the related intelligence. The technological evolution of embedded devices is presented in brief before delving into the specific architectural ecosystems employed. Microcontrollers are small, embedded computers finding extensive, rather unparalleled, usage in the modern technology-driven world. From the earliest x86-based architecture to the more recent ARM-centered designs, microcontrollers have grown in breadth and integration to offer a broad spectrum of design choices and performances. The current, and by no means exhaustive, list of commercial offerings includes x86, 68 HC11, PIC, STM, ARM, RISC-V, AVR, M8C, S08, Parallax propeller, MIPS, and DSP-based designs, supplemented by a range of storage, RAM, communication, and power options. The popular offerings are listed in Table 7 against the main characteristics, such as memory, architecture, instruction set, bus width, and peripherals. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Type** & **Measurement** & **Usage** \\ \hline Phase Measurement Unit & Phase and magnitude, synchro-phasor, relative phase angle difference, phasor differential & Complex power flow, tripping and inter-area oscillations, frequency change, phase unbalance \\ \hline Power Quality meter & Voltage harmonics, crest factor, total harmonic distortion, phase harmonic index, inter-harmonics, notching, etc. & Topology identification, grid state estimation, energy efficiency \\ \hline Digital Fault Recorders & Waveform snapshot in case of fault & Fault location and fault type, energy leakage \\ \hline Waveform measurement units & Relative waveform difference & Event detection and classification \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Smart grid measurements. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Hardware Type** & **Offering/Architecture** & **Characteristics** \\ \hline \multirow{8}{*}{
\begin{tabular}{c} \begin{table}
\begin{tabular}{c c c} \hline \hline
**Hardware Type** & **Offering/Architecture** & **Characteristics** \\ \hline  & & 8-bit and 32-bit RISC based AVR cores, 1.6 to 24 MHz, up to 256 Kbyte flash RAM, 64 to 16 Kbytes SRAM, 61–512 bytes EEPROM, up to 12-bit ADC, IEC, SPI, UART, CAN, USB, Ethernet \\ \hline  & RISC-V & 32-bit RISC-V based architectures, 160 MHz clock speed,16 KB to 400 KB of SRAM, 22 IO pins, Wi-Fi, Bluetooth 5(LE), SPI, UART, IEC, IEC, IEC (based on ESP32-C3 implementation) \\ \hline  & ARM & 32-bit ARM based microcontrollers, 32 MHz to 550 MHz clock speed, 128 KB to 2 MB flash storage, 20 KB to 1.4 MB RAM, up to 512 bytes EEPROM, up to 100 IO, 12-bit ADC, SPI, IEC, UART, USART, USB 2, Bluetooth (low energy), ZigBee, LoRaWAN (based on STM32 discovery platform) \\ \hline  & Virtex & 91,000–136,900 slices, 582,720–876,160 logic cells, 6938–13,275 Kbits distributed RAM, 795–1410 RAM blocks of 36 Kbit each, 650-850 single-ended or 321–408 differential inputs, 1260–2520 DSP4821 slices, PCI express (Gen2/Gen3), 36–72 gigabit transceivers (based on Virtex-7 series) \\ \hline  & Kintex & 10,250–74,650 slices, 65,600–477,760 logic cells, 838–6788 Kbits distributed RAM, 4860–34,380 Kbit RAM, 300–500 single ended or 144–192 differential inputs, 240–1920 DSP48 slices, PCI express (Gen2)), 8–32 gigabit transceivers (based on (based on (based on (based on (based on (based on ()))))))))))))))))))))}} \\\\\\\\\\\\\\\\\\\\\\\\\\ \\ \\ \\ \end{array}}\] \\ \end{array}\]  
\end{table}