# Application of a MEMS-Based TRNG in a Chaotic Stream Cipher
## 4 Implementation Results  
The proposed encryption algorithm including the transmitter and the receiver was implemented in a Xilinx Virtex 7 FPGA. In order to test the system, a part of the post-processed bitstream generated by the sensor was used as the initial values of \(x_{0},\gamma\) and \(y_{0}\). To find a good compromise between encryption speed and security, a 64-bit precision was used. Since \(\gamma\) and \(x_{0}\) are within the interval \((0,1)\) they can be implemented easily on the FPGA using a fixed-point arithmetic. The resources used by the transmitter, including the total number of lookup tables (LUTs), slice registers, and digital signal processing blocks (DSPs), as well as the throughput obtained, are shown in Table 2. Furthermore, the area, frequency, and throughput obtained by other chaotic stream ciphers implemented in similar platforms are shown for comparison purposes.  
Establishing a comparison between these systems is not straightforward since they have been implemented in different platforms and it is difficult to analyze the level of security that each one provides. For example, the cryptosystem proposed in [27] achieves a higher throughput than the STM-LFSR algorithm but it is transmitting 16 bits instead of eight after each iteration, which may result in a higher vulnerability. However, it can been seen that our system achieves higher performance area ratio (Mbps/slice) than most of the other cipher systems.  
After implementing the algorithm, we were able to encrypt and decrypt images efficiently. As an example, Figure 10 shows an original and its encrypted images, and Figure 11 shows their  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Device** & [25] & [26] & [27] & [28] & **This Work** \\ \hline Platform & Virtex 5 & Virtex 6 & Virtex 6 & Virtex II & Virtex 7 \\ Main chaotic algorithm & Logistic Map & Henon Map & Logistic Map & Lorenz System & Skew Tent Map \\ Key generation & NA & NA & NA & NA & TRNG \\ LUTs & 50 & 1600 & 643 & 2718 & 805 \\ Registers & 48 & 64 & 160 & 791 & 70 \\ Total DSPs & 9 & 16 & 16 & 40 1 & 16 \\ Freq (MHz) & 43.2 & 25.7 & 93 & 15.5 & 134 \\ Throughput (Mbps) & 43.2 & 25.7 & 1500 & 124 & 1072 \\ Slices 2 & 25 & 408 & 181 & 1755 & 210 \\ Mbps/slice & 1.728 & 0.063 & 8.287 & 0.07065 & 5.105 \\ \hline \hline \end{tabular}  
* Virtex II uses 18 \(\times\) 18 multipliers instead of DSPs;2 The number of slices has been estimated from the number of Registers and LUTs, assuming unrelated logic.  
\end{table}
Table 2: Comparison with Recent Published Chaos-Based Ciphers.  
respective histograms. The correlation between the original and the encrypted image in this case is only 0.0020, indicating that both images are almost uncorrelated.  
Moreover, in the present work, power consumption was also estimated. The FPGA manufacturer power report utilities was used for this purpose. After doing post-implementation simulations, the obtained dynamic power consumption at an operation frequency of 125 MHz (1 Gbps) was 60 mW, which resulted in 60 pJ/bit.  
This value is similar to the power consumption of other lightweight ciphers implemented in FPGA, such as [29], where power consumption per ciphered bit is 155 pJ/bit in the AES block cipher and 62 pJ/bit in the Present block cipher (It should be noticed that these ciphers were implemented in a Xilinx 6 Series FPGA that typically presents a 25%-30% higher power consumption than a Xilinx 7 Series FPGA). However, these cipher systems achieve throughputs of 116 Mbps and 37.6 Mbps, respectively, which are significantly lower than the throughput achieved by our system.