# Analysis of AC DC Four-Switch Boost-Buck Battery Charger Converter for EV Applications
## 8 Control Design  
In the design of the small-signal model for the converter, the closed-loop small-signal block diagram is illustrated in Figure 13. This section focuses on the design of the current controller \(G_{Ci}(s)\) and the voltage controller \(G_{CV}(s)\) to achieve the desired control objectives. As shown, the converter consists of two loops: the inner current loop and the outer voltage loop. Therefore, the design process begins with the inner current loop by designing \(G_{Ci}(s)\). It worth noting that \(K_{sense}\) is the voltage sensor gain for the output voltage, which equals to \(\frac{1}{V_{0}}\). To ensure a consistently high PF by reshaping the input current waveform in all operational modes, it is essential for the inner current loop to possess a wide bandwidth, facilitating fast responses. Additionally, its crossover frequency must be kept below the switching frequency \(\omega_{s}\). In terms of robustness, the phase margin of the inner current loop should be greater than \(45^{\circ}\) to guarantee stability. The inner current loop gain is a good approximation below the switching frequency and around the input voltage. This loop gain varies with the input voltage and must have sufficient stability margins for that variation. In the boost mode, the current control transfer function \(G_{Ci}(s)\) is a proportional and integral (PI) controller with a first-order low-pass filter, which has a cut-off frequency (\(\omega_{\text{C}}\)) at the switching frequency. The equation can be expressed as follows  
\[G_{Ci}(s) = \frac{s+2011}{2s}*\frac{\omega_{\text{C}}}{s+\omega_{\text{C}}}. \tag{16}\]  
Figure 13(a) illustrates the current loop gain transfer function, showing a crossover frequency occurring near \(110\) kHz, accompanied by a phase margin of \(64^{\circ}\). Figure 13: Closed-loop small-signal block diagram. The inner current loop can be closed and its transfer function for the closed-loop transfer function \(G_{igd-CL}(s)\) will be  
\[G_{igd-CL}(s) = \frac{G_{Ci}(s)}{1+G_{Ci}(s)}\frac{G_{igd-RC}(s)}{G_{igd-RC}(s)}. \tag{17}\]  
The external voltage loop, which is slower to respond, is sensitive to fluctuations in the input voltage that occur at twice the line frequency, often referred to as the double line frequency. The loop's performance as a voltage regulator is accurately approximated only at frequencies lower than this double line frequency. Consequently, to ensure stability and adequate response, the crossover frequency for this loop must be set below the double line frequency and should be paired with a phase margin exceeding 45 degrees. The design of the output voltage controller, denoted as \(G_{CV}(s)\), is formulated by employing the current reference to output voltage transfer function \(G_{vi_{ref}}(s)\), which is derived using \(G_{di_{ref}}(s)\). This approach facilitates the management of the output voltage in the face of input variations and preserves system stability across the operating range. The voltage transfer function \(G_{vi_{ref}}(s)\) can be expressed as follows  
\[G_{vi_{ref}}(s) = G_{vd-RC}(s)G_{igd-CL}(s)K_{sense}. \tag{18}\]  
The voltage control loop's transfer function, designated as \(G_{vi_{ref}}(s)G_{CV}(s)\), is tailored to achieve a phase margin of \(87^{\circ}\) at a crossover frequency of 4 Hz, as depicted in Figure 14b. This specification ensures that the system maintains stability and a timely response to changes in load or input voltage. The phase margin value of \(87^{\circ}\) provides a buffer above the minimum acceptable margin of \(45^{\circ}\), contributing to the robustness of the control loop against variations in system parameters or external disturbances. The selection of a 4 Hz crossover frequency, well below the double line frequency, allows the control loop to effectively mitigate the influence of an input voltage ripple and ensures a stable output voltage, which is essential for the reliable operation of power electronic systems.