## 2 Modeling and Simulation Procedure
The RTN amplitude differences observed between simulation and experimental results outside of the previously specified range, obviously, are due to fluctuations in the experimental samples' parameters responsible for the drain current. This is confirmed by the significant differences observed in the RTN amplitude for two different experimental samples outside of the indicated range: the jumping increase is observed for the positive gate overload higher than \(0.1\) V for the sample with width 130 nm, and for the negative gate overload lower than \(0.15\) V for the sample with a width of 90 nm. Reasonable agreement with the experimental results enables the use of this model in Junctionless FinFET and comparison with various other models, especially the conventional simple cell model. The proposed defect model was applied for simulating the RTN amplitude generated by single charges trapped at the oxide-semiconductor interface, as well as in the gate oxide layer of nanosized Junctionless (JL) Silicon on Insulator (SOI) FinFET. The RTN amplitude was calculated in steady state condition using the following expression  
\[\text{RTN}=(\text{I}_{\text{d0}}-\text{I}_{\text{d}})/\text{I}_{\text{d0}} \tag{2}\]  
where \(\text{I}_{\text{d0}}\) and \(\text{I}_{\text{d}}\) denote the drain current before and after trapping the single charge, respectively. The structure of the simulated transistor is shown in Figure 5a and the corresponding parameters are presented in Table 2. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameters** & **Designation** & **Value of the Parameters** \\ \hline The channel doping concentration & \(\text{N}_{\text{ch}}\) & \(2\times 10^{16}\) cm\({}^{-3}\) \\ Gate oxide thickness & \(\text{t}_{\text{ox}}\) & \(1.4\) nm \\ Gate width & \(\text{W}_{\text{gate}}\) & \(90\), \(130\) nm \\ Gate length & \(\text{I}_{\text{gate}}\) & \(55\) nm \\ \hline \hline \end{tabular}
\end{table} 
Table 1: The parameters of the simulated MOSFET. Figure 4: RTN amplitude dependence on the gate overload for the planar MOSFET with gate widths 130 (**a**) and 90 (**b**) nm. 3D simulations were performed in the framework by a drift-diffusion model using the TCAD Sentaurus software. The influence of trapped charge in this model is accounted by trapped charge density \(\rho_{\text{trap}}\) in the Poisson equation, which is part of the transport model used [28]:  
\[\
abla\varepsilon\
abla\varphi=-\,\text{q}(p-n+\text{N}_{\text{D}}-\text{N}_{ \text{A}}\ )-\rho_{\text{ytap}} \tag{3}\]  
where \(\varepsilon\) is the electrical permittivity, \(\text{q}\) is the elementary electronic charge, \(n\) and \(p\) are the electron and hole densities, \(\text{N}_{\text{D}}\) is the concentration of ionized donors, \(\text{N}_{\text{A}}\) is the concentration of ionized acceptors. Boundary conditions for \(\rho_{\text{trap}}\) are determined by the form of charged defect (Figure 3). In Sentaurus, \begin{table}
\begin{tabular}{c c c} \hline
**Parameters** & **Designation** & **Value of the Parameters** \\ \hline The channel doping concentration & \(\text{N}_{\text{ch}}\) & \(5\times 10^{18}\) cm\({}^{-3}\) \\ Equivalent gate oxide thickness (\(\text{HfO}_{2}\)) & \(\text{t}_{\text{eff}}\) & 1.2 nm \\ Channel thickness & \(\text{Ts}_{\text{i}}\) & 9 nm \\ Channel width & \(\text{W}_{\text{fin}}\) & 22 nm \\ Gate width & \(\text{W}_{\text{gate}}\) & 55 nm \\ Gate length & \(\text{L}_{\text{gate}}\) & 13 nm \\ \hline \end{tabular}
\end{table} 
Table 2: Parameters of the simulated SOI FinFET. Figure 5: The structure of the simulated JL MOSFET (**a**) and comparison of \(\text{I}_{\text{d}}\text{-V}_{\text{g}}\) characteristics of the transistor carried out from simulation and experiment (**b**). an area with a certain shape, size, and boundary was created in the oxide layer and at the boundary using the Sentaurus Structure Editor, which corresponds to the different single trapped charge models at stake (i.e., under consideration).