# Circulating Current Reduction in MMC-HVDC System Using Average Model
## 2 MMC-HVDC System Structure  
Figure 1a,b shows the single line diagram of the MMC-HVDC system and circuit diagram of a three-phase MMC converter (double-star configuration) as proposed in Reference [28], respectively. The HVDC system includes two MMCs working as a rectifier and inverter connected at each side of an AC system through a three-phase transformer. The sub-modules (SMs), or cells, are used to develop a half-bridge circuit. Each cell is made of a capacitor and two Insulated-gate bipolar transistors (IGBTs) switches (T\({}_{1}\), T2) connected in series. The cell output voltage (\(V_{sm}\)) is equal to the capacitor voltage (T\({}_{1}\) on state) or zero (T\({}_{1}\) off state) and is regulated by the controller. The switching states of the cells are controlled so that at any instant, \(n\) cells out of \(2n\) cells are on (\(n_{up}\) in the upper arm and  
in the lower arm) in each phase. Each arm consists of \(n\) series of connected cells and an inductor \(L_{arm}\) in series, which is used to limit the fault current. Each leg comprises two arms, which can be represented as a controllable voltage source, i.e., \(V_{up}\) and \(V_{low}\). The converter terminal voltage at the AC side in phase \(a\) can be expressed as follows:  
\[V_{C(a)}=\frac{n_{low}-n_{up}}{2n}V_{dc} \tag{1}\]  
As \(n_{up}+n_{low}=1\) and \(n_{up},n_{low}e\{0,1\ldots n\}\) based on Equation (1), \(V_{C(a)}\) will change in discrete steps from \(V_{dc}/2\) to \(-V_{dc}/2\) with a step size of \(\frac{V_{dc}}{n}\). By using the capacitor voltage balancing technique, the voltage of each cell is perfectly regulated at \(\frac{V_{dc}}{n}\). The converter will generate an ideal \((n+1)\)  
Figure 1: Modular multilevel converter-based high-voltage direct-current (MMC-HVDC) system: (**a**) single line diagram; (**b**) circuit diagram; (**c**) AC side voltage. level sinusoidal waveform for the AC side system with respect to the DC side midpoint as shown in Figure 1c [29]. In hardware implementation, the capacitor voltages of SMs are measured using large number of voltage sensors. It increases hardware complexity and also introduces errors in signal measurements, which affects the sinusoidal ideal voltage waveform [30]. The converter voltage (\(V_{up,low}\)) in phase \(a\) can be described as follows:  
\[(V_{up,low}(a))=\sum_{n=1}^{N}S_{n}V_{c} \tag{2}\]  
where  
\[S_{n}=\left\{ \begin{array}{rl}&1,\text{ if }n_{th}\text{cell is inserted}\\ &0,\text{ if }n_{th}\text{ cell is by passed}\end{array} \right.\]  
The switching signal \((s)\) finds the converter arm voltage based on \(v_{up,low}^{ref}\) for the corresponding upper and lower arms. The dynamics of converter control include the grid side current \((i_{1})\), output converter voltage at the AC side (\(V_{c}\)), DC side current \((I_{dc})\), and internal circulating current \((i_{circ})\)[31]. Using [PERSON]'s voltage law in converter phase \(a\), the following expressions are derived:  
\[\frac{V_{dc}}{2}-V_{up(a)}-L\frac{di_{1u}}{dt}=V_{g} \tag{3}\]  
\[-\frac{V_{dc}}{2}+V_{low(a)}+L\frac{di_{1l}}{dt}=V_{g} \tag{4}\]  
Adding Equations (3) and (4), the dynamics of the converter output current at AC side is given as:  
\[\frac{L}{2}\frac{di_{1}}{dt}=e_{a}-V_{g} \tag{5}\]  
where \(e_{a}=\frac{V_{up(a)}-V_{low(a)}}{2}\) is the inner generated voltage in phase \(a\), \(V_{g}\) is the grid side voltage, \(i_{1u},\ i_{1l}\) is the upper and lower arm currents, and \(L\) (\(L=L_{t}+L_{arm}/2\)) is the equivalent inductance of the transformer and converter arm.