# Balancing the Leakage Currents in Nanometer CMOS Logic--A Challenging Goal
## 5 Analysis Results  
In this section, we analyze our newly developed iBSPL logic cells and compare them to classic CMOS logic gates as well as the BSPL cells originally proposed in [27]. Our simulations are performed by HSPICE using transistor models from two commercial nanometer process technologies, 40 nm and 65 nm. To achieve balanced rise and fall times for all analyzed logic cells we have set the width of (functional) PMOS transistors significantly larger than the width of NMOS transistors, especially when stacked, to account for the difference between electron and hole mobility, while keeping the lengths identical. As a first step we analyze the area overhead associated with balancing the leakage currents in nanometer process technologies. In that regard, we put the required transistor-only area of BSPL and iBSPL cells in relation to classic CMOS logic gates. Those results can be found in Table 4. It is obvious that the overhead associated with our new iBSPL cells is consistently lower than that of BSPL cells, with the only exception being the XOR gate. We have also measured the average power consumption for a PRESENT SBox for one clock cycle. Table 5 shows that the iBSPL circuit consumes less power in comparison to BSPL. As  
Figure 8: iBSPL gates in 40 nm. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Gate** & **Technology** & **TCB\({}_{1}\)** & **TCB\({}_{2}\)** & **TCB\({}_{3}\)** & **TCB\({}_{4}\)** \\ \hline \multirow{4}{*}{NAND} & 40 nm & w = 120.00 & - & w = 397.15 & w = 160.63 \\  & 40 nm & w = 140.39 & - & \\  & 65 nm & w = 181.57 & - & w = 172.99 & - \\  & & w = 228.96 & - & & - \\ \hline \multirow{4}{*}{NOR} & 40 nm & - & - & w = 172.70 & - \\  & 40 nm & - & - & w = 291.94 & - \\  & 65 nm & - & - & w = 155.99 & w = 3 \(\times\) 360.00 \\  & & - & - & w = 127.11 & w = 1209.16 \\ \hline \multirow{2}{*}{XOR} & 40 nm & w = 2 \(\times\) 271.72 & - & w = 314.88 & - \\  & 65 nm & w = 3 \(\times\) 152.51 & w = 3 \(\times\) 509.44 & - & - \\ \hline \multirow{2}{*}{NOT} & 40 nm & w = 271.72 & - & - & - \\  & 65 nm & w = 152.51 & - & & - \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Number and size of TCBs added to each gate to achieve a balanced static power consumption. previously stated, the BSPL concept neglects the fact that the pass-transistor-based XOR is not suitable for standard cell design; in iBSPL we have used a complementary XOR gate. Hence, comparing their area overheads is not much meaningful. As a next step we analyze how much information can be extracted from the leakage of each of the balanced and unbalanced gates. In the simulation environment, the (static) power measurements are free of noise. Hence, even extremely small differences between the power consumption associated with the processing of different data values lead to successful key recovery. Therefore, the goal of a proper security evaluation in the simulation domain is to put the feasibility of attacks on the underlying circuit in relation to the noise level. In reality, the power measurements are always affected by noise originating from the measurement setup and environmental parameters. To this end, an evaluation metric based on the concept of Information Theory has been developed in [31]. It considers Gaussian-distributed noise centered to the simulated power values, and estimates the mutual information between the simulated leakage and the processed data. For a given noise standard deviation, the technique evaluates the amount of available information which can be exploited by the _worst-case_ adversary, independent of the type of relationship between leakage and processed data (e.g., specific leakage models, linear/non-linear dependency,...). Therefore, the purpose of IT analysis is to extract a curve of the mutual information over the noise standard deviation, therefore identifying the necessary noise level to fully hide the information leakage. The lower the required noise, the higher is the robustness, since the leakage can more easily (with lower noise) be hidden.