# Training and Inference of Optical Neural Networks with Noise and Low-Bits Control
## 2 Architecture  
### Neural Networks and ONNs  
A fully connected neural network consists of an input layer, hidden layers, and an output layer, as shown in Figure 1[16]. The image of the handwritten data set (MNIST [17]) is input into the network for simulation [18]. Since the handwritten data set is composed of 0-9, the output layer has 10 outputs. In our previous work [15], we designed an image classification and recognition model based on a fully connected neural network (FCNN) and mapped it to a silicon-based photonic integrated circuit, as shown in Figure 2[15]. Previous simulation experiments showed that the optical modulator enabled the chip to perform fast and high-precision classification of hand-written numbers with an accuracy greater than 97%. Speeds of up to 80 Gbps can be achieved at the currently reported rates of silicon-based modulators. Up to 80 Gbps can be achieved in the recently reported rates of silicon-based modulators. A silicon ONN chip is mainly composed of five parts. In the first part of Figure 2a, the input port can be realized by a side coupler or grating coupler. The fan-out structure can be realized by cascading 1 \(\times\) 2 multi-mode interference (MMI). The second part is the input light divided into 128 parts, with one Mach-Zehnder modulator (MZM) for every two channels. The third part consists of 256 MZMs, half of which are used to encode the target file and the other half to load the weight signal. Then, two waveguides, a silicon waveguide and a sinusoidal waveguide, are used to realize the matching structure of the target file signal and the weight signal. In the fourth part, there are 128 balance detectors, each of which multiplies the one-way target file signal with the weight signal. The final addition and activation functions can be implemented via circuits, which are composed of the fifth part. Figure 1: FCNN structure. The ONN chip is designed to recognize 10 complete (0 to 9) handwritten digital images simultaneously. We resize the digital images into 11 \(\times\) 11 grayscale matrices with 8-bit resolution and flatten them into vectors. These vectors are fed through parts one and two, and are multiplexed in the time domain. Next, in the third and fourth part, the pairing of the encoded target file and the loaded weight signal and the multiplicative accumulation operations are performed. Finally, different node/neuron outputs are obtained by sampling the results of the previous step. The final output of the ONN is represented by the intensity of the output neurons, with the highest intensity of each test image corresponding to the prediction category. The peripheral system, including signal sampling, nonlinear functions, and merging, is implemented electronically by means of digital signal processing hardware. Figure 3 shows the schematic diagram of the optoelectronic system. After being input through the input port, the signal is multiplied and added by the optical neural network chip, and output through the balance detector. Shot noise is generated in the balanced detector. The balanced detector enters the circuit through AD/DA conversion, and the computer is used to process the data in the nonlinear part. In this part, quantization of the data is required. Since the optical neural network we designed has three layers, this process needs to be cycled three times to get the final output. We will elaborate on the specific models for noise and quantization in the following sections. Figure 3: Schematic diagram of the optoelectronic system. Figure 2: Chip design (**a**) of an ONN chip structure. (**b**) Matrix multiplication concept diagram. The chip is implemented for each layer of the network structure. Matrix multiplication is performed by combining the input target signal (yellow) and the weight signal (blue) and translating them to the balance detector for detection.