# Elliptic-Curve Crypto Processor for RFID Applications
### Hardware Accelerators for RFID Applications  
The existing ECC-based state-of-the-art hardware accelerators for RFID applications are described in [14; 19; 20; 21; 22]. In [14], an ECC-based crypto processor for RFID tags over \(GF(2^{163})\) is presented. The processor architecture is capable of performing the PM and modular arithmetic operations that include additions and multiplications. These operations are required for the ECC based crypto protocols. On 0.13 \(\upmu\)m complementary metal-oxide-semiconductor (CMOS) technology, the achieved clock frequency is 1.13 MHz. The total number of required clock cycles to perform one PM operation is 275,816. Similarly, the time to compute one PM operation is 244.084 ms. The architecture utilizes 12,506 logic gates and consumes 36.63 \(\upmu\)W power.  
Another ECC-based crypto processor architecture for RFID tags over \(GF(2^{163})\) is presented in [19]. On 0.35 \(\upmu\)m CMOS technology, the achieved clock frequency is 13.56 MHz. The total number of required clock cycles to perform one PM operation is 430,654. Moreover, the time for one PM computation is 31.8 ms with a utilization of 15,094 logic gates. Similar to [14; 19], another ECC-based crypto processor architecture for RFID tags over \(GF(2^{163})\) is presented in [20]. On a 0.18 \(\upmu\)m technology, the reported clock frequency is 0.847 MHz. The total number of reported clock cycles for the computation of one PM operation is 296,964. Moreover, the time for one PM computation is 350.6 ms with a utilization of 13,200 logic gates.  
A binary Edward-curve (a special class/model of ECC) based crypto processor for extremely constrained applications is described in [21]. For area optimization, the size of the embedded register file is reduced. The power is improved by setting/enabling clock-gating during the synthesis process over the 0.13 \(\upmu\)m technology. With several area and power improvement techniques, the reported clock frequency is 0.400 MHz. Furthermore, the total number of required clock cycles for the computation of one PM operation is 219,148. Moreover, the time required to perform one PM computation is 547.87 ms with a utilization of 11,720 logic gates.  
Similarly in [22], a crypto processor is presented to implement an Elliptic-curve Digital Signature Algorithm (ECDSA) over \(GF(\mathbb{P}_{192})\) for application in RFID tags. The design objectives are to achieve low-energy, small chip area, robustness against cryptographic attacks and flexibility. On a 130 nm CMOS technology, the processor achieves 200 MHz frequency with a chip size 0.15 mm\({}^{2}\). For one signature generation, it takes 2500 us.  
In addition to RFID specific architectures, there are several other PM hardware accelerators, described in [18, 23, 24, 25, 26]. A 2-stage architecture with pipelining to reduce clock cycles and optimize clock frequency is described in [18, 24]. A low-area ECC accelerator architecture using a digit-serial multiplication method is described in [23]. Similar to [21], a low-cost and fast hardware implementations of the PM on Binary Edward-curves is presented in [25]. Moreover, a \(\frac{throughput}{area}\) architecture to optimize both throughput and area at the same time is provided in [26]. This is achieved by using a digit-serial multiplier in the datapath of the accelerator architecture.