# A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders
## 2 Materials and Methods
### Parallel RSC Encoders Hardware Architecture  
The parallel RSC encoder was implemented as VHDL intellectual property (IP) core. The architecture of the system matches the block diagram shown in Figure 3. The IP core can be exploit to generate a generic RSC encoder, which can be fixed by specifying \(g(x)\), the puncturing scheme vector, and the matrix containing the feed-forward polynomials \(h_{k}(x)\). Such vectors are necessary to generate the matrices \(A^{\prime},B^{\prime},C^{\prime},D^{\prime}\). The information contained in these matrices is important to build the data path logics. Indeed, let us pose \(Y=(c^{\prime}_{0}c^{\prime}_{1}...c^{\prime}_{k\cdot N_{0}-1})\) and let us consider as example the generation of the output \(c^{\prime}_{i}\). By isolating the contribution of the rows \(D^{\prime}_{i}\) and \(C^{\prime}_{i}\) of the matrix \(C^{\prime}\) and \(D^{\prime}\) in Equation (12), such output is calculated as shown in the system of Equation (19):  
\[\begin{cases}c^{\prime}_{i}&=c^{\prime}_{iC^{\prime}}+c^{\prime}_{iD^{\prime}} \\ c^{\prime}_{iC^{\prime}}&\triangleq C^{\prime}_{i}\cdot S[n]\\ c^{\prime}_{iD^{\prime}}&\triangleq D^{\prime}_{i}\cdot\begin{pmatrix}u[n]\\ \ldots\\ u[n+k-1]\end{pmatrix}\end{cases}\,, \tag{19}\]  
where \(c^{\prime}_{iC^{\prime}}\) and \(c^{\prime}_{iD^{\prime}}\) are respectively the contributions of the networks described by the rows \(C^{\prime}_{i}\) and \(D^{\prime}_{i}\).  
Figure 3: Block diagram of a \(k\)-parallel RSC encoder  
In particular, \(c^{\prime}_{iD^{\prime}}\) is produced by the network operating over the inputs of the RSC encoder; on the contrary, the term \(c^{\prime}_{iIC^{\prime}}\) is generated by the subsystem processing the internal flip-flop states. More specifically, only the inputs whose position corresponds to the ones of the unitary elements inside the \(D^{\prime}_{i}\) row contribute to \(c^{\prime}_{iD^{\prime}}\).  
In view of that, for each element \(c^{\prime}_{iD^{\prime}}\) a dedicated network is instantiated which sums through exclusive OR (XOR) operations the inputs specified by the unitary elements of the row \(D^{\prime}_{i}\). In particular, the architecture of the network is designed to minimize the logical path from the inputs to the output. For such aim, the various XOR gates are linked in a tree fashion. In each layer of the tree, the elements of the previous layer are grouped into couples which feed a XOR gate. In case of an odd number of layer inputs, the last element is directly linked with the successive layer. When a matrix row \(D^{\prime}_{i}\) is identically null, its contribution \(c^{\prime}_{iD^{\prime}}\) is forced to 0, which is the neutral element for the XOR gate. This means that such row is not contributing to generate the output \(c^{\prime}_{i}\).  
Figure 4 shows the tree pattern of the network for the generation of \(c^{\prime}_{iD^{\prime}}\).  
The approach described for the generation of the output bits \(c^{\prime}_{i}\) through the matrix rows \(C^{\prime}_{i}\) and \(D^{\prime}_{i}\) was also exploited to produce the inputs to the flip-flops through the rows \(A^{\prime}_{i}\) and \(B^{\prime}_{i}\). More specifically, the same network topology described for the matrix rows \(D^{\prime}_{i}\) is also exploited for all the other matrices rows.