# Conception of a System-on-Chip (SoC) Platform to Enable EMG-Guided Robotic Neurorehabilitation
## 3 System Requirements and Architecture Implementation
This flexibility enables potential adjustments for future applications or specific signal acquisition needs. Conversely, the use of 24-bit resolution provides a voltage resolution as low as 300 \(\upmu\)V, thereby enabling the detection of even minimal changes without the necessity of significantly increasing the gain of the acquisition system. A microcontroller-based system cannot handle high acquisition rates, restricting the bandwidth for capturing signals. While sufficient for low-frequency EMG signals, the system fails to capture signals with higher frequencies, as it operates at only 1 kSPS. Given that EMG signals span a bandwidth between 0.01 Hz and 10 kHz, most of this range remains unsupported. Moreover, its limited processing capacity prevents the implementation of real-time processing necessary for the exoskeleton's control loop. To address these challenges, a SoC FPGA-based system was developed. The selected device, the ZYNQ XC7Z010-1 CLG400C is manufactured by AMD-Xilinx (headquartered in San Jose, CA, USA) and integrates a high-performance dual-core ARM(r) Cortex(tm)-A9 MPCore(tm) processor with 28 nm programmable FPGA logic. This architecture combines on-chip memory, external memory interfaces, and a broad range of peripheral connectivity interfaces, offering the processing power, flexibility, and real-time capabilities required for the system. This flexibility reduces latency and enhances the integration of ROS2 nodes, ensuring modularity and scalability for the robotic subsystems. High-speed data acquisition on Zynq-7000 boards is supported by its capability to handle computationally intensive tasks without external latency. With its multi-channel processing and integrated ARM cores, the Zynq-7000 enables systems to preprocess and analyse EMG data directly on the hardware, minimizing the data bandwidth required for external transmission. Zynq-7000 platforms support ROS2 integration through tools like meta-FOrEST ([[https://meta-forest.readthedocs.io/en/latest/introduction.html](https://meta-forest.readthedocs.io/en/latest/introduction.html)]([https://meta-forest.readthedocs.io/en/latest/introduction.html](https://meta-forest.readthedocs.io/en/latest/introduction.html)), accessed on 5 November 2024), which is an automatic creation tool for nodes of ROS2 systems integrating several FPGA logics into a ROS2 system (ROS2-FPGA nodes) and enables seamless communication between the FPGA and ROS2 nodes. This facilitates the deployment of ROS2-based robotic frameworks by automating the generation of FPGA nodes, reducing programming complexity. For example, meta-FOrEST can link the FPGA processing cores directly with ROS2 middleware, enhancing performance while maintaining a flexible modular architecture for robotic subsystems [20; 21]  
The integration of the ADS1298 analog front-end and its connection to a computer for efficient signal processing are detailed below, as shown in Figure 1.  
The architecture comprises an IP block that oversees the AFE Controller (ADS SPI Controller), which is linked through a multiplexer to a buffer where data is temporarily stored before being transmitted to DDR memory, via DMA. The blocks used are as follows:  
* ADS SPI Ctrl: This custom IP block acts as the controller for SPI communication when receiving data from the AFE. It temporarily stores and manages the captured data until the DMA is ready for transmission. It includes an AXI4-Lite slave interface for interaction with the processing block, an AXI-Stream master interface for data transfer to the DMA, and an SPI communication module with a 128 \(\times\) 32 FIFO memory to ensure no data loss. Additionally, it features a clock divider that converts the system clock (50 MHz) to a 4 MHz clock for SPI communication. * ADS SPI Mux: This custom IP block functions as a multiplexer that allows switching between two SPI data streams connected to the AFE. The first stream, linked to the AXI  
Figure 1: Proposed system architecture to integrate the ADS1298R AFE and its connection to a computer.