## 4 Simulation and Experimental Results  
The set-up used to carried out the different experiments with the MACC-based two-loop digital control is shown in Figure 4. It is composed of a 400 V 1.6 kW buck-boost prototype converter with the parameters described in Table 1 and the TMS320F28377S DSC. The design of the buck-boost converter is presented in [32]. The tests were carried out changing quantization values and controller parameters, as described next. Test 1 has been done using the conventional voltage error approach shown in Figure 3 using a 12 bit ADC to take the samples of output current and voltage. The external loop compensator is designed to obtain a cross-over frequency of \(f_{c}=4\) kHz. Test 2 also corresponds to the conventional voltage error measurement approach used in Test 1 but tuning \(f_{c}=2\) kHz. In order to reduce the voltage error quantization value \(q_{v}\)Test 3 has been carried out with the proposed voltage error block shown in Figure 3, using a 16 bit ADC in differential mode and \(f_{c}=4\) kHz for the external closed loop. In Test 4, the ADC quantization level of the output current and voltage is increased, scaling ADC resolution to 8 and 11 bits respectively for the current and voltage sampled values [35], and using the conventional approach error voltage block in Figure 3. Loop gains of the external control loop for the last test are selected to obtain \(f_{c}=4\) kHz. Figure 5 shows simulated waveforms of output current reference \(i_{Lref}\), variable control \(u\), and voltage error \(e_{v}\) when the converter operates in steady-state with \(V_{g}=200\) V and \(v_{o}=300\) V.  
A summary of the tests and evaluations of the fulfillment of the stability conditions for each loop, obtained by replacing the parameters of Tables 2 and 3 in the restrictions (11) and (14), are shown in Table 4. Figure 5a shows quantization-induced perturbations (QIP) in all signals for the Test 1, when neither \(q_{DPWM}/q_{i}<K_{pi}\) for the restriction (14) of the inner current loop nor \(K_{iv}T<q_{i}/q_{v}\) of the external loop are fulfilled. In Test 2, although condition (14) is not fulfilled, QIP are reduced for the output current reference as can be seen in Figure 5b. The condition for the external loop (11) is satisfied due to the reduction of the gains \(K_{iv}\) and \(K_{pv}\), but, as the cross-over frequency depends on the proportional gain \(K_{pv}\), the loop bandwidth is reduced. The ADC quantization level of the output voltage quantization \(q_{v}\) is reduced in \begin{table}
\begin{tabular}{l l} \hline \hline
**Converter Parameters** & **Value** \\ \hline Input voltage \(V_{g}\) & 200–400 V \\ Output voltage \(V_{o}\) & 100–400 V \\ Rated power & 1.6 kW \\ Switching frequency \(f_{s}=1/T\) & 100 kHz \\ Output capacitor \(C_{o}\) & 28 μF \\ Intermediate capacitor \(C\) & 1.32 μF \\ Mutual inductance \(M=L_{m}\) & 135 μH \\ Self inductances \(L_{1}=L_{2}\) & 270 μH \\ Damping network \(R_{d}C_{d}\) & 5 \(\Omega\), 20 μF \\ Load resistor \(R_{o}\) & 200 \(\Omega\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Parameters for the buck-boost setup. Figure 4: Experimental set-up of the buck-boost voltage regulator: (**a**) coupled-inductor buck-boost power stage, (**b**) digital signal controller with output capacitor \(C_{o}=28\) μF, (**c**) oscilloscope, (**d**) constant resistive load \(R_{o}=200\)\(\Omega\) (**e**) input dc power supply, and (**f**) auxiliary power supply for DSC and MOSFET drivers. To compare the bandwidths and stability margins provided by each of the tests, the corresponding Bode plots of the voltage loop-gains for the converter operating in boost mode are provided in Figure 6, being the loop gain frequency response in a switched converter a powerful tool commonly used for the design of the controllers used in the control stage [36]. It is important to note that the results for the Test 1 have not been included in the frequency response analysis previously described.