## 1 Introduction
### Related Work  
Significant research has been conducted into the efficient application of LDPC decoding within flash memory systems. A sensing strategy to reduce the raw bit-error rate (RBER) and latency of LDPC is proposed in [10], which comprehensively considers the inter-state, intra-state and cross-layer asymmetric error characteristics of flash memory. The read voltage is optimized to reduce the RBER by utilizing the unbalanced state transition features brought on by changes in the threshold voltage distribution due to retention time and P/E cycles [11]. An optimal read voltage decision-making scheme is proposed in [12] to eliminate the read operations required for read retries, thereby reducing read latency; the scheme uses overlapping error correction codes to determine the optimal best reading voltage. In [13], the nonuniform error characteristics between different states and within the same state are comprehensively quantified, thus the sensing level and the delay can be optimized in a more targeted manner. Given the challenges posed by intra-cell unbalanced bit-error probability and data dependence, in [14], strategies such as interleaving upper and lower page bits have been proposed to enhance min-sum LDPC decoding and reduce decoding latency. A joint decoding strategy is proposed in [15] to achieve latency reduction, which optimizes soft information by exploiting the bit-granularity error rate obtained by combining two bits in a pair of shared pages. Further studies have shown that nonuniform bit-error rates across layers can be mitigated by blending data from error-prone, lower-layer units with more reliable upper-layer units, thereby diluting the concentration of errors and improving decoding speed [16]. Additionally, methods that exploit inter-state error patterns to refine the LNMS LDPC decoding process have been explored, aiming to decrease decoding latency. A bit-error-aware LDPC decoding scheme based on the bit-error characteristics of multi-level cell (MLC) NAND flash pages is proposed in [17] to reduce the number of decoding iterations. A scheme to accelerate decoding by exploiting the error patterns of 3D triple-level cell (TLC) NAND flash pages is proposed in [18], which first decodes two lower RBER pages and stores their corresponding channel LLRs and a posteriori LLRs to optimize the decoding operation of the higher RBER page. A resistance drift-aware LDPC decoding method is proposed in [19], which improves the LDPC decoding performance but also increases the writing time. An efficient LDPC coding scheme has been introduced in [20], which exploits the significant RBER difference between pages to further shorten the decoding iterations for phase-change memory. An improved sliding window decoding algorithm [21] has been proposed based on the joint source-channel coding scheme [22] for dual spatially coupled LDPC codes. Additionally, a joint-grouping shuffling scheduled decoding algorithm [23] has been introduced for the joint source-channel coding scheme in double LDPC code systems. This method considers the overall structure of the Tanner graph for both source and channel coding and applies shuffled decoding. Furthermore, an algorithm has been proposed to jointly optimize the read voltage thresholds [24] across all layers by maximizing mutual information (MMI), thereby improving soft LLR information and reducing the read latency of 3D NAND flash memory. A bilayer LDPC coding scheme [25] has been developed for MLC NAND flash memory, leveraging the inter-page asymmetry of MLC flash memory channels and storing additional parity in the lower pages.