## 2 Experimental Details and Simulation Setup  
We used Czochralski-grown phosphorus-doped n-type wafers (200 \(\upmu\)m thick with 3-5 \(\Omega\)-cm,) in this study. The removal of surface defects was the first step by applying an etching solution containing sodium hydroxide (NaOH) at 70-80 \({}^{\circ}\)C for nearly 10 min. After that, the samples were cleaned by standard RCA-1 and RCA-2 cleaning procedures to remove organic as well as metallic impurities. Finally, sample cleaning was completed using deionized water. After cleaning, the samples were immediately transferred to a thermal oxide furnace. The SiO\({}_{2}\) tunnel layer grown by the thermal furnace had an approximate thickness of 1.2 nm on both sides of the silicon wafer. The temperature used for the growth of the SiO\({}_{2}\) was set around 600 \({}^{\circ}\)C with an O\({}_{2}\) flow rate of 10 L/min for 30 min. After the growth of SiO\({}_{2}\), the samples were transferred to the PECVD chamber for the deposition of the nc-SiO\({}_{\text{x}}\). The transfer of samples was undertaken by breaking the vacuum and temporarily exposing them to the normal atmosphere. The nc-SiO\({}_{\text{x}}\) deposition with SiH\({}_{4}\), H\({}_{2}\), CO\({}_{2}\), and PH\({}_{3}\) gases was performed at a temperature of about 230 \({}^{\circ}\)C to the thickness of 30 nm. Optimized PECVD deposition parameters for the nc-SiO\({}_{\text{x}}\) layer were described in our prior paper [24]. All fabricated samples were exhibited to the post-deposition annealing (PDA) at 850, 900, and 950 \({}^{\circ}\)C for a 1-h duration. Finally, for the hydrogen passivation, forming gas annealing (FGA, 15% H\({}_{2}\) in Ar) was completed at 400 \({}^{\circ}\)C for 2 h.  
The fabricated symmetric structures are described in Figure 1a. The SiO\({}_{2}\) tunnel oxide layer and the nc-SiO\({}_{\text{x}}\) layer with a 30 nm thickness were confirmed through spectroscopic ellipsometry (VASE, [PERSON], Lincoln, NE, USA). The passivation characteristics were evaluated by employing a QSSPC measurement system (WCT Sintron, 120). The transfer length method (TLM) was applied to obtain the contact resistivity (\(\rho\)). The ultrathin SiO\({}_{2}\) tunnel oxide layer and nc-SiO\({}_{\text{x}}\) layer thickness were affirmed through transmission electron microscopy (TEM) and spectroscopic ellipsometry (VASE, [PERSON], Lincoln, NE, USA). As for simulation concerns, the AFORS-HET v.2.5 is a powerful and professional simulation program used for hetero-junction solar cells. Using this tool, various simulation-based papers have been published [25; 26]. In the present study, we examined thoroughly the solar cells displaying tunnel oxide passivated contact and attest that the rear side structure for the TOPCon solar cell is a heterojunction. Architecture for the TOPCon solar cell applied in the present study is included in terms of the following: front electrode (Ag)/SiN\({}_{\text{x}}\)/p\({}^{+}\)-Si layer/n-Si wafer absorber/SiO\({}_{\text{x}}\)/nc-SiO\({}_{\text{x}}\) layer/rear electrode (Ag). A graphic depiction as well as the energy band structure for the simulated device architecture plus the comprehensive parameters are provided within Figure 1b,c and Table 1, accordingly. In Table 1, the supposed parameters of the TOPCon devices applied for the simulation are presented. Two essential parameters of tunnel oxide, namely, pinhole density through the oxide (D\({}_{\text{ph}}\)) and the interface-states density (D\({}_{\text{it}}\)), are studied in the simulation. In this work, it is necessary to note that despite AFORS-HET being a 1D simulation tool, it can handle pinholes. This paper required categorizing the pinhole as a micro-hole or a micro-channel through tunnel oxide, because of the damage to oxide integrity by an impurity diffusion throughout the high temperature anneal [27]. Using a pinhole, the bulk carriers recombine at the interface, which decreases the solar cell performance.