# Sharp Switching Characteristics of Single Electron Transistor with Discretized Charge Input
## 2 Sample Design and Fabrication  
Figure 1a,c show scanning electron microscope (SEM) images of the samples that we designed. The corresponding circuit diagrams are shown in Figure 1b,d. In Figure 1d, areas surrounded by a dotted and a dashed lines denote the ID and the SET, respectively. Input node of the SET is capacitively coupled to the ID with a coupling capacitance \(C_{\mathrm{C}}\). For the purpose of dividing electrical charge at the island \(n_{1}\), two capacitors of \(C_{\mathrm{C}}\) and a grounded capacitance \(C_{\mathrm{B}}\) are connected to the island \(n_{1}\). Red circles indicate tunnel junctions and the inset in Figure 1c shows a close-up picture of the tunnel junction \(J_{1}\). The junction area of \(J_{1}\) is approximately 180 nm \(\times\) 40 nm.  
When the island \(n_{2}\) is connected to the ground, the electrical charge \(Q_{\rm C}\) at \(C_{\rm C}\) and the threshold voltages of the ID are expressed as follows [12]:  
\[Q_{\rm C}=\frac{C_{\rm C}(C_{I_{1}}V_{\rm g}+n_{1}e)}{C_{I_{1}}+C_{\rm B}+C_{\rm C }}, \tag{1}\]  
\[\left(n_{1}-\frac{1}{2}\right)\frac{e}{C_{\rm B}+C_{\rm C}}\leq V_{\rm g}\leq \left(n_{1}+\frac{1}{2}\right)\frac{e}{C_{\rm B}+C_{\rm C}} \tag{2}\]  
where \(C_{I_{1}}\) is the junction capacitance of \(J_{1}\) and \(e\) is the elementary charge. When \(C_{\rm C}\) is equal to \(C_{\rm B}\), the ID generates the discretized charge with a constant period of half of \(e/C_{\rm C}\) to the input voltage \(V_{\rm g}\). In addition, from Equation (1), to obtain the clear discontinuity of \(Q_{\rm C}\), \(C_{\rm C}\) is required as large as or larger than \(C_{I_{1}}\). We used an interdigitized capacitor type [15,16] as \(C_{\rm C}\) and the self-capacitor type [17] as \(C_{\rm B}\). A rectangular-like Al plate that roles the part of \(C_{\rm B}\) is shown in Figure 1c. We deliberately enlarged \(n_{2}\) in order to implement \(C_{\rm B}\) as much as \(C_{\rm C}\). The size of the flat-plate structure was about \(6.3\,\mathrm{\SIUnitSymbolMicro m}\) wide and \(5.0\,\mathrm{\SIUnitSymbolMicro m}\) long. In order to adjust the ratio of capacitance values \(C_{\rm B}/C_{\rm C}\), we designed geometories of the device utilizing the three dimensional capacitance extraction program (FFTCap) [18]. A back-gate voltage of \(V_{\rm bg}\) and a capacitance \(C_{\rm BG}\) were used for adjusting the offset charge on the island \(n_{2}\). Another sample excluding \(J_{1}\), which would work as a simple SET, was created simultaneously on the same substrate to be compared with the discontinuity of the electrical responses (see Figure 1a).  
Samples were fabricated by using the electron beam lithography and the Al shadow evaporation technique [19] on a thermally oxidized silicon substrate. In this method, the oxidized Al layer that formed between the first and the second Al layer acts as tunnel barrier. The surface of the 1 st-deposited Al layer was oxidized by adding 13 Pa of pure O\({}_{2}\) gas for 60 s into an evaporation chamber. At room temperature, the values of respective series resistance of the SETs with the ID and without the ID were 104 k\(\Omega\) and 106 k\(\Omega\).  
Figure 1: (**a**) Scanning electron microscope (SEM) image of a single electron transistor (SET) without an input discretizer (ID). Red circles indicate tunnel junctions; (**b**) The equivalent circuit of the SET without the ID; (**c**) The SEM image of the SET with the ID. The inset shows a close-up the tunnel junction of \(J_{1}\); (**d**) The equivalent circuit of the SET with the ID.