# All-Integer Quantization for Low-Complexity Min-Sum Successive Cancellation Polar Decoder
## 6 Discussion  
In our research, we designed and evaluated a low-complexity quantization technique using a CPU-based simulation because a CPU is more flexible in computation, particularly for handling high-precision floating-point arithmetic. However, unlike CPUs, FPGAs rely on fixed-point arithmetic and often require approximations to optimize performance due to hardware constraints. Our experiment is carefully designed to handle all-integer computation, ensuring compatibility with FPGA hardware while reducing the need for complex arithmetic operations. Table 3 summarizes the key differences between CPU and FPGA arithmetic, highlighting the necessary adjustments for hardware implementation. Given these differences, our proposed quantization method is expected to be FPGA-efficient due to its reduced reliance on floating-point operations, optimized bit-width representation, and minimized computational complexity. \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Decoding**} & \multicolumn{3}{c}{**Reduction Gain per Block Length (Bits)**} \\  & **256** & **1024** & **4096** & **16,384** \\ \hline Integer-quantized MS-SC & 74.06\% & 75.51\% & 76.61\% & 77.23\% \\ Fixed-point MS-SC & 34.21\% & 36.07\% & 37.83\% & 34.65\% \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Reduction gain in computational complexity relative to conventional SC decoding algorithm. Our results highlight the significant impact of all-integer quantization on the performance of the SC decoding algorithm, confirming that MS-SC decoding is well suited to this approximation method. In terms of error propagation, ambiguous results are observed, as shown in Figure 4. For 5-bit integer quantization, the BER performance does not improve over the 4-bit level at \(E_{\text{b}}/N_{0}\) values below 6 dB for QMS-SC decoding, even though their FERs are identical. This suggests that, while increasing the quantization level improves the accuracy in certain scenarios, it may not significantly enhance BER in low \(E_{\text{b}}/N_{0}\) regimes. However, such low \(E_{\text{b}}/N_{0}\) regions are not typically utilized, as their BERs are quite poor. The integer-based conventional SC decoding results show that expanding the integer range does not lead to performance improvement because integer values are poorly suited for accurately representing hyperbolic functions in SC decoding. To optimize the quantization level, the 5-bit quantization level is concluded to be optimal for operating the MS-SC decoding in the integer domain. Notably, the performance at low quantization levels, lower than the 5-bit level, closely resembles that of infinite-precision MS-SC decoding as the length and rate of polar codes increase. On fading channels, the performance of QMS-SC does not improve despite increasing the bit level from 5 bits to 8 bits, and it saturates at the 5-bit level, suggesting that increasing bit precision does not result in further performance improvements. Compared to the results of [26], which employed fixed-point quantization, our all-integer quantization approach achieves a similar BER/FER performance, as shown in Figure 7. Considering the computational complexity in Table 2, the results of this experiment confirm that our method significantly reduces computational complexity compared to fixed-point operations in FPGA implementation. In comparison, as shown in Table 4, the fixed-point calculations reported in [26] have low implementation complexity but still result in sufficient decoding performance. On the other hand, as discussed in [9], the nonuniform quantization method introduces higher implementation complexity due to its sophisticated design for optimizing quantization levels. However, it offers a superior decoding performance in specific scenarios, making it more suitable for applications where performance is prioritized over hardware constraints.