# Enhancing the SRAM PUF with an XOR Gate
## 5 Discussion
#### Future Work  
Further research is essential to investigate the effects of aging on this design and to develop potential mitigation strategies. Although our design enhances the uniqueness, randomness, and security of the SRAM PUF by employing multiple challenge-response pairs (CRPs), a critical challenge remains: the susceptibility of SRAM PUFs to aging. This phenomenon can significantly impact the stability and reproducibility of PUF outputs. Therefore, a comprehensive examination of the aging effects on this dual-SRAM architecture is necessary, as the integration of responses from two SRAM components may intensify the reliability issues typically associated with aging. Potential avenues for future research include employing accelerated aging methods [35; 36] to assess their impact on the responses generated by our design.  
Additionally, the inclusion of two SRAM components within the same architecture presents a drawback. A more effective design could involve utilizing a single SRAM that captures multiple samples per challenge. By XORing these samples together, a single-bit response can be generated that emulates the results of two SRAM reads followed by XORing, as demonstrated in this paper. While a sample size of two effectively represents the findings of this study, this approach can be scaled to accommodate any number of samples, provided that care is taken to avoid repeating challenge addresses, as repetition would negate their contribution in the XOR operation. Additionally, this design can be implemented entirely in software, facilitating an exponential increase in the potential challenges derived from the existing SRAM. Consequently, this method could enable any  
\begin{table}
\begin{tabular}{l c c c c} \hline \hline \multirow{2}{*}{**PUF Metrics**} & **SRAM XOR** & **Microcontroller** & **FPGA SRAM** & **Reconfigurable** \\  & **PUF** & **SRAM PUF [22]** & **PUF [23]** & **SRAM PUF [26]** \\ \hline Number of CRPs & \(n^{2}\) & \(n\) & \(n\) & \(n\) \\ BER or \(HD_{intra}\)1  & 0.0020 & 6.85 \(\times\) 10\({}^{-7}\)* & 0.0271 & 0.009 \\ \(HD_{inter}\) & 0.4966 & 0.4954 & 0.4806 & 0.499 \\ Entropy H(O) & 0.9999 & 0.9974 & 0.9979 & N/A \\ \hline \hline \end{tabular}
\end{table}
Table 5: PUF metrics of previously implemented SRAM PUFs compared to the new design. The term \(n\) denotes the number of SRAM cells on the device. Moreover, work in [22; 26] used fuzzy extractors, a mix of filtering fuzzy cells and error correction code, to improve reliability. The SRAM XOR PUF used fuzzy extractors by just filtering out fuzzy cells.  
currently utilized SRAM PUF hardware to adapt to a framework similar to the XOR SRAM PUF, significantly enhancing the randomness and the number of possible CRPs generated.  
[PERSON] contributed software, data collection/analysis, writing, and revising. [PERSON] contributed hardware design/creation, visualizations, and tables. [PERSON] supervised the research. All authors have read and agreed to the published version of the manuscript.  
This research received no external funding.  
Not applicable.  
Data Availability Statement: Data available in a publicly accessible repository: [[https://github.com/NAU-Cybersecurity-lab/xor-sram-data](https://github.com/NAU-Cybersecurity-lab/xor-sram-data)]([https://github.com/NAU-Cybersecurity-lab/xor-sram-data](https://github.com/NAU-Cybersecurity-lab/xor-sram-data)), accessed on 16 October 2024.  
The authors declare no conflicts of interest.  
The following abbreviations are used in this manuscript:  
\begin{tabular}{l l} AES & Advanced Encryption Standards \\ BER & Bit-error rate \\ CRP & Challenge-response pair \\ GPIO & General-Purpose Input/Output \\ SRAM & Static Random-Access Memory \\ PCB & Printed circuit board \\ PUF & Physically Unclonable Function \\ RBC & Response-Based Cryptography \\ RSA & Rivest-Shamir-Adleman \\ XOR & Exclusive-OR \\ \end{tabular}