# A Wideband Power Amplifier in 65 nm CMOS Covering 25.8 GHz-36.9 GHz by Staggering Tuned MCRs
## 3 The PA Circuit Implementation  
Figure 1 shows the architecture of the implemented wideband power amplifier. Three common-source stages are used to improve power gain and to stagger the Z21 of each MCR stage conveniently. Output power is increased by two-way current-combining. The matching networks mainly consist of transformer-based MCRs between each stage and transmission lines for the input and output. The gate biases of the transistors are supplied  
Figure 21: The Z21 of the MCR1 when the inductors and capacitors are all ideal components with a k increasing from 0.3 to 0.7.  
Figure 22: (**a**) The Z21 of MCR1 at the input of the power amplifier and (**b**) the Z21 of each MCR and the total circuit.  
Figure 20: (**a**) The lumped model of MCR1 based on TF1 for matching and (**b**) the 3D view of the input-matching network including TF1 and the power splitter.  
through the center tap of the transformers (TF1, TF2, and TF3) by series resistors (R1) of 250 \(\Omega\) to improve common mode stability [37]. Especially for the input stage, series resistors Rs of 10 \(\Omega\) are inserted between gate and the input transformer (TF1) to further suppress the common-mode oscillation. Pseudo-differential NMOS pair with neutralization capacitors has been employed to all the stages. The neutralization capacitors implemented via metal-oxide-metal are used to tackle the negative feedback and to improve reverse isolation [37]. Then, both the power gain and stability are improved. Shunt resistors are added at the gate of each stage to reduce the Q factor of the impedance, to help implement matching, and also to improve the stability of the circuit. Figure 23a presents the Gmax and stability of the 128 \(\upmu\)m transistor used in the output differential pair versus the values of neutralization capacitance (Cneu) at 32 GHz. Gmax1 and Kf1 present the condition without gate paralleled resistors, and Gmax2 and Kf2 present the condition that two 150 \(\Omega\) gate paralleled resistors (Rg for output stage) are added. It indicates that the Cneu range sustaining Kf > 1 is extended from about 23.9% to 51.7%. Also, the Gmax decreases by about 3 dB when Cneu is 37 fF. Considering that the whole circuit is composed of three cascaded circuit stages, the gain reduction induced by these shunt resistors at each stage is acceptable. Figure 23b shows the Gmax and Kf at different frequencies with shunt resistors added. It demonstrates that the Cneu ranges sustaining Kf > 1 at different frequencies are almost the same. Even at 40 GHz, the Gmax is bigger than 11.75 dB. The neutralization capacitance (Cneu) selected for the three stages are 37 fF/17 fF/9.5 fF, respectively. All the neutralization capacitors are implemented with parallel-plate metals. In this work, 2*32/1*32/1*16 fingers with a finger width of 2 \(\upmu\)m (128 \(\upmu\)m*2 for the output stage differential pair) for the output stage, driver stage 2, and driver stage 1 are used for better performance. The metal lines on transistors are simulated using a 3D EM simulator. The 1.1 V VDD supply is fed through the center tap of the transformers. The 0.6 V VGS for the power stage and driver stage 2 and 0.55 V for driver stage 1 are selected for the consideration of output power and PAE.