## 4 Conclusions  
In this paper, we propose an FPGA-based CNN accelerator for pulse waveform classification. First, we employ CNN to classify the different types of pulse waveforms. Moreover, to reduce the number of parameters and the memory used to cache intermediate results, we specially design a CNN model in accordance with experiments, which illustrates that the optimization of the CNN software algorithm has a significant effect on memory reduction. Finally, we implement the CNN algorithm on FPGA, optimize the hardware design by three optimization methods, and realize the accelerator, which costs only 0.714 W under a working frequency of 100 MHz. The hardware optimization dramatically improves the clock speed and reduces memory access latency.  
In summary, the specified CNN model and the custom RTL design help reduce resource usage, latency, and power consumption. The software and hardware co-design method helps improve the performance of the accelerator significantly. The low-power and real-time features allow the CNN classification accelerator of pulse waveform to be integrated into the portable devices, and it will play an  
\begin{table}
\begin{tabular}{c c c c c c} \hline  & [27] & [30] & [31] & [26] & **Our Work** \\ \hline CNN Model & AlexNet & VGG16 & VGG16 & AP2D-Net & Self-Design \\ Platform & Vertix-7 VX690T & Zynq XC7Z020 & Virtex-7 VX690T & Ultra96 & Artix XC7A100T \\ Clock (MHz) & 150 & 214 & 150 & 300 & 100 \\ BRAMs (36 Kb) & 2192 & 85.5 & 1220 & 162 & 53.5 \\ DSPs & 2980 & 190 & 2160 & 287 & 147 \\ Flip-flop (F/F) & 281.8 K & 35.5 K & - & 94.3 K & 30.08 K \\ Latency (ms) & - & 364 & 106.6 & 32.8 & **0.827** \\ Power (W) & 31.2 & - & 35 & 5.59 & **0.714** \\ \hline \end{tabular}
\end{table}
Table 4: Comparison with previous FPGA-based CNN implementations.  
\begin{table}
\begin{tabular}{c c c c c c} \hline
**Component (Total)** & **Solution 1** & **Solution 2** & **Solution 3** & **Solution 4-1** & **Solution 4-2** \\ \hline Clock (MHz) & 100 & 100 & 100 & 100 & 170 \\ BRAMs (36 Kb) & 26.30\% & 35.93\% & 68.52\% & 39.63\% & 39.63\% \\ DSPs & 61.25\% & 61.25\% & 61.25\% & 61.25\% & 61.25\% \\ LUT (63,400) & 37.63\% & 37.80\% & 39.92\% & 29.76\% & 29.83\% \\ LUTRAM (19,000) & 12.35\% & 12.36\% & 12.39\% & 7.42\% & 7.43\% \\ Flip-flop (F/F) (126,800) & 28.30\% & 28.66\% & 28.25\% & 23.72\% & 23.75\% \\ Latency (ms) & 19.631 & 2.499 & 1.270 & 0.827 & 0.487 \\ Power (W) & 1.63 & 1.638 & 1.645 & 0.714 & 1.089 \\ \hline \end{tabular}
\end{table}
Table 3: Resource consumption and performance of different solutions on FPGA.  
essential role in doctor diagnosis. In future work, we will further optimize and improve the accelerator's throughput by employing the data quantization method and other state-of-the-art strategies.  
Conceptualization, C.C. and Y.Z.; Data curation, C.C. and J.H.; Formal analysis, C.C. and J.H.; Funding acquisition, Z.L. and H.Z.; Investigation, C.C.; Methodology, C.C. and Z.L.; Project administration, Z.L. and H.Z.; Resources, Z.L. and Y.Z.; Software, C.C.; Supervision, C.C.; Validation, C.C., S.Z. and J.H.; Visualization, S.Z. and H.Z.; Writing-original draft, C.C.; Writing-review and editing, C.C., Z.L. and H.Z. All authors have read and agreed to the published version of the manuscript.  
This research was funded by the National Major Science and Technology Project (No. 2018 ZX01031-201, 2018 ZX09201011).  
The authors declare no conflict of interest.