# Stability of Single Electron Devices: Charge Offset Drift
## 2 Experimental Observations of Charge Offset Drift
### Silicon-Based Devices
To further the discussion of the stability of all-silicon devices, and to compare more completely to metal based devices, we can examine the power spectral density of the charge noise in these devices as well. Figure 9 shows data measured on various days and at two different gate voltages [30]. First, it is clear from the data at each gate voltage that the time dependence of the noise is quite small as the different color curves lie on top of each other for a particular gate voltage. Both the knee frequency and the absolute value of the noise remain unchanged. Secondly, one notices a difference in the character of the noise at \(V_{G}=3.475\) V (upper cluster of curves) and \(V_{G}=3.25\) V (lower cluster of curves). \(S_{Q}\) shows a Lorentzian lineshape at \(V_{G}=3.475\) V as evinced by the \(1/f^{2}\) dependence above 10 Hz and the flat value of the noise below 1 Hz. The black line in the figure denotes a fit to this form. Therefore, in this range of gate voltage, there is a single TLS present in the device which dominates the noise. At \(V_{G}=3.25\) V, \(S_{Q}\) exhibits \(1/f\) noise and has orders of magnitude smaller noise below 1 Hz. While the \(1/f\) noise form denotes that there are several TLSs active at this gate voltage, their combined effect is much smaller than the single TLS, which is active at the higher gate voltage. Finally, these data include multiple changes in gate voltage, and thermal cycling to room temperature. The implication of this data is that an individual TLS present in the Si/SiO\({}_{2}\) system was stable as a function of temperature or slow changes in the gate voltage. Thus, the remarkable stability of all-silicon SEDs is due to a lack of interactions between individual TLSs and not to the complete absence of TLSs. As mentioned earlier, all-silicon devices with fixed barriers (PADOX) are marginally more stable than those with electrostatic barriers. Given this slight dependence on architecture one might think that the overall stability of devices might be the product of some specific steps in the fabrication. This has been directly addressed in the literature, most directly in reference [47], where devices were fabricated in different foundries. It was found that the stability of all-silicon devices is a robust property of the materials. Regardless of how the devices are fabricated, even devices with relatively poor performance (gate leakage and unintentional barriers) exhibit excellent charge offset stability 100 times better than that of metal-based devices [47]. In summary, single electron devices based in the Si/SiO\({}_{2}\) material system show much smaller charge offset drift (\(\Delta Q_{0}\leq 0.01e\)) than metallic SEDs (\(\Delta Q_{0}\geq 1e\)) and much smaller sensitivity  
Figure 8: The main panel shows charge offset drift data in an all silicon device with electrostatic barriers. Very stable behavior before and after a thermal cycle to room temperature (represented by the time spanned by the **grey** bar) is observed. The inset shows the source-drain current as a function of plunger gate voltage before (**black** curve) and after (**red** curve) the thermal cycle measured with exactly the same voltages on every gate. All features in the data before the thermal cycle are reproduced in the curve taken after the thermal cycle. The curves are offset for clarity. All data were taken at a temperature of about 2.2 K. Reproduced with permission from reference [46], Copyright 2013, Institute of Electrical and Electronics Engineers. to external perturbations such as temperature, mechanical disturbance, and voltage pulses. This stability is not associated with the lack of TLSs in SiO\({}_{2}\) but rather with the degree of interaction between TLSs which are present in both AlO\({}_{x}\) and SiO\({}_{2}\). Before we discuss the TLSs in these systems within the context of glassy relaxation, we first discuss work on SEDs fabricated in the combined system of silicon dots defined with Al gates to complete the experimental picture.