## 5 Implementation of the Adaptive SMC and Detailed Circuital Simulations
### Digital Implementation of the Adaptive SMC
Figure 8 shows that \(i_{L1}\) is introduced in the CMPSS; hence, an ADC channel is not needed for \(i_{L1}\). Since the external input of the CMPSS (\(i_{L1}\)) is connected to the positive inputs of the comparators, the lower comparator correctly produces the reset signal (\(Reset\)). In contrast, the upper comparator produces an inverted version of the set signal (\(\overline{Set}=1-Set\)). The outputs of the CMPSS are logic signals, which is the main advantage of the structure given in Figure 8, since those logic signals can be captured by the second thread (Thread 2) at the full speed of the microprocessor (200 MHz); hence, the capture frequency is not limited by the conversion time of the ADC. Similarly, the control signal of the MOSFETs (\(u\) and \(\overline{u}\)) are logic signals; therefore, executing Thread 2 at 10 MHz or  
Figure 8: Digital implementation of the control algorithm. 12 MHz will provide a resolution between 1% and 1.25% of the switching period for both the rising and falling times of \(u\) (and \(\overline{u}\)). In fact, executing Thread 2 at the full speed of the F28379D Microprocessor (200 MHz) could improve the resolution of \(u\) (and \(\overline{u}\)) to 0.06% of the switching period. Algorithm 3 reports the pseudocode for Thread 1, which calculates the comparator inputs \(\Psi_{L1,Set}\) and \(\Psi_{L1,Reset}\). This algorithm considers the discrete implementation of the high-pass filter given in Equation (58), which is obtained from the analog high-pass filter previously reported in Equation (47) by performing the Tustin transformation \(\left(s=[2/T_{add}]\cdot[2-1]/[z+1]\right)\) discussed in [39], and subsequently applying the inverse \(Z\)-transformation to obtain the difference equation representation of \(i_{R(k)}\). In such an expression, \(T_{add}\) is the ADC sampling time. Therefore, Thread 1 can be executed at 264 kHz for the application example, which ensures an ADC frequency of 264 kSPS (\(T_{add}=3.8\) us). The calculations of \(\Psi_{L1,Set}\) and \(\Psi_{L1,Reset}\) show that those values are continuous; hence, those signals must be provided to the CMPSS using two DAC channels. The F28379D Microcontroller has DAC channels with minimum conversion times equal to 2 us; hence, \(T_{add}=3.8\) us can be fulfilled by the on-board DAC. Finally, the values of \(i_{R}\) and \(i_{o}\) are stored for the next iteration of the algorithm. \[i_{R(k)}=\frac{i_{o(k)}-i_{o(k-1)}-\left(\pi\cdot F_{safe}\cdot T_{add}-1 \right)\cdot i_{R(k-1)}}{\pi\cdot F_{safe}\cdot T_{add}+1} \tag{58}\]  
```
0:\(v_{R}\), \(F_{safe}\), \(\Delta\Psi\), \(T_{add}\)
1:loop
2: measure\(i_{o(k)}\), \(v_{C2(k)}\), \(v_{p(k)}\), \(i_{L2(k)}\)
3:\(i_{R(k)}\leftarrow\left\{\frac{i_{(k)}-i_{(k-1)}-\left(\pi\cdot F_{safe}\cdot T _{add}-1\right)\cdot i_{R(k-1)}}{\pi\cdot F_{safe}\cdot T_{add}+1}\right\}\)\(\triangleright\) High-Pass filter
4:\(k_{c(k)}\leftarrow\left\{\frac{v_{p(k)}}{v_{C2(k)}}\right\}\)\(\triangleright\) Calculate the adaptive current gain
5:\(k_{v(k)}\leftarrow\left\{-\frac{3.9\cdot C_{2}}{k_{c(k)}\cdot t_{o(k)}}\right\}\)\(\triangleright\) Calculate the adaptive voltage gain
6:\(\Psi_{L1,Reset(k)}\leftarrow\left\{i_{R(k)}+k_{v(k)}\cdot\left(v_{R}-v_{C2(k)} \right)+\left(k_{c(k)}-1\right)\cdot i_{L2(k)}+\Delta\Psi\right\}\)
7:\(\Psi_{L1,Set(k)}\leftarrow\left\{i_{R(k)}+k_{v(k)}\cdot\left(v_{R}-v_{C2(k)} \right)+\left(k_{c(k)}-1\right)\cdot i_{L2(k)}-\Delta\Psi\right\}\)
8:\(i_{R(k-1)}\gets i_{R(k)}\)\(\triangleright\) Store \(i_{R(k)}\) value
9:\(i_{o(k-1)}\gets i_{o(k)}\)\(\triangleright\) Store \(i_{o(k)}\) value
10:return\(\Psi_{L1,Set(k)}\), \(\Psi_{L1,Reset(k)}\)\(\triangleright\) Signals for the comparators of the CMPSS
11:endloop
```  
**Algorithm 3** Thread 1: calculation of the comparator inputs (\(\Psi_{L1,Set}\) and \(\Psi_{L1,Reset}\))  
Algorithm 4 reports the pseudocode for Thread 2, which produces the control signals for the MOSFETs (\(u\) and \(\overline{u}\)); hence, it must be executed between 80 and 100 times the maximum switching frequency.