# A Lightweight Image Cryptosystem for Cloud-Assisted Internet of Things
## 3 Materials and Methods
### Proposed Lightweight Image Cryptography Algorithm  
The proposed lightweight image cryptosystem (HXP) algorithm is a block cipher designed for low area overhead. The cipher features bit grouping, the XOR function, and bit permutation layers. The cipher accommodates a variable block size; hence, it can also be used with rich-resource IoTs, like conventional cryptography algorithms. There is no need for an S-box in the proposed image algorithm; hence, it conserves memory. The architectural design of HXP is shown in Figure 2. Figure 2a depicts the encryption module \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Author** & **Title** & **Algorithm used** & **Strength** & **Weakness** \\ \hline \multirow{3}{*}{[46]} & PRINCE—A low-latency & \multirow{3}{*}{Feistel structure} & It conserves & It is susceptible to \\  & block cipher for pervasive & & computational resources & key-related attacks and \\  & computing applications & & computational resources & requires more rounds to \\ \hline \multirow{3}{*}{[47]} & A New Family of & \multirow{3}{*}{SPN structure} & Consumes low power and & Hardware implementation \\  & Lightweight Block Ciphers & & exhibits high diffusion & is resource-intensive \\ \hline \multirow{3}{*}{[48]} & New Lightweight & \multirow{3}{*}{Feistel structure} & It uses only one S-Box & S-Box consumes memory \\  & DES Variants & & It uses only one S-Box & and requires more rounds \\ \hline \multirow{3}{*}{[49]} & mCrypton—A Lightweight & \multirow{3}{*}{Crypton architecture} & Compact implementation in & Hardware implementation \\  & Block Cipher for the Security & [50] (SPN structure) & both hardware and software & is resource-intensive \\ \cline{1-1}  & of Low-Cost RFID Tags & & & \\ \cline{1-1}  & and Sensors & & & \\ \hline \hline \end{tabular}
\end{table} 
Table 1: _Cont._ \begin{table}
\begin{tabular}{c c} \hline \hline
**Symbol** & **Description** \\ \hline XOR & Exclusive-or \\ \hline HXP & Hash, XOR, and bit permutation \\ \hline \(\bigoplus\) & Concatenation operator \\ \hline \(\otimes\) & XOR operator \\ \hline SHA\(-\)256 & Secure Hash Algorithm 256 \\ \hline \(p\) & Input image \\ \hline C & Cipher image \\ \hline \(\sigma_{p}\) & Contrast of P/standard deviation of pixels in P \\ \hline \(\mu_{p}\) & Luminance of P/mean of pixel in P \\ \hline \(\sigma_{C}\) & Contrast of C/standard deviation of pixels in C \\ \hline \(\mu_{P}\) & Luminance of C/mean of pixel in C \\ \hline \(var_{P}\) & Variance of P \\ \hline \(var_{C}\) & Variance of C \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Description of the notations used in this research paper. of HXP. The encryption module takes the permutation key and all the pixels in a single row of the image to be encrypted at a time. The array of pixels is converted into an array A of n bits. The layers making up the HXP cryptosystem are outlined as follows:  
1. Bit grouping layer: The bits in A are grouped into two equal parts, L and R, each of size (n/2) bits. \[L =A\Big{[}0\ldots\frac{n}{2}-1\Big{]}\] (1) \[R =A\Big{[}\frac{n}{2}\ldots n-1\Big{]}\] (2)
2. XOR operation layer: A bitwise XOR operation is carried out on L and R, according to Equation (3), to form an array of xorbit and the bits in R is concatenated to xorbit to form xorbitR, which has n bits. The symbol \(\bigoplus\) represents concatenation in Equation (4). \[xorbit[i]=L[i]\otimes R[i]\qquad for\ 0\leq i<\frac{n}{2}\] (3) \[xorbitR=xorbit\ \oplus R\] (4)
3. Bit permutation: This layer takes the permutation key, permkey, and xorbitR as inputs. Permkey contains an array of random integers with size n. The value of integers in permkey ranges between 0 and n - 1. Each bit of xorbitR is rewritten according to Equation (5). \[encbits[i]=xorbitR[permkey[i]]\ \ \ \ for\ 0\leq i<n\] (5) The pseudocode in Algorithm 1 outlines the design of the encryption module. Figure 2: HXP architectural design. ```
Output: enclock
1. \(START\)
2. \(L=block\left[0\ldots\frac{n}{2}-1\right]/\text{a block contains n bits}\)
3\(R=A\left[\frac{n}{2}\ldots n-1\right]\)
4.