## 3 Physical Layer Design
### Two Stage PA  
In the transmitter, power amplifier is one of the power-hungry blocks that affects the overall efficiency of the transmitter. In our design, a two-stage Common Source (CS) topology is used as it provides high frequency response and larger voltage swing compared to cascode designs. The two-stage PA proposed in this work is shown in Figure 7. It uses a CS topology with drain-to-gate transformer-feedback neutralization technique, which creates an additional signal path that neutralizes the current flow through Cgd [67]. The transformers are formed using inductors at the gate and drain terminals of M1 (Lg1 and Ld1) and M2 (Lg2 and Ld2) as shown in Figure 7 with coupling factors, k1 and k2 respectively. The values of the coupling factors are chosen such that they minimize the reverse transformation \(\mathrm{Y_{12}=\frac{I_{p}}{V_{ds}}}\mathrm{V_{in}=0\,\,}\) of the two stages of the amplifier. The inductor Ld1 and Ld2 at the drain of the transistors M1 and M2 resonates with the drain capacitance. This increases the overall gain and bandwidth at the center frequency. Transistor M1 and M2 are biased using a voltage  
Figure 6: Schematic and component values of the proposed OOK modulator with NMOS cross-coupled VCO.  
divider-based biasing circuit. The output of the power amplifier is matched with 500 hm by using L match impedance matching technique.  
Here, we present the key characteristics of the transmitter as described above. Figure 8a shows the frequency response of the VCO. From Figure 8a, it can be observed that the VCO is centered at 60 GHz. We simulated the on-off steady state gain of OOK modulator using Cadence Virtuoso analog design environment (ADE). At 60 GHz the modulator has an \"on\" and \"off\" state gain of \(-\)3.6 dB and \(-\)81.6 dB respectively as shown in Figure 8b. Therefore, the on-off steady state gain is above 78 dB for the frequency ranges from 45 GHz to 75 GHz. Figure 9 shows the S\({}_{11}\), S\({}_{22}\), and S\({}_{21}\) for the proposed PA. The S\({}_{11}\) is the ratio of reflected power to the incident power at the input port and is known as reflection coefficient or return loss. For the proposed PA design the value of reflection coefficient, S\({}_{11}\) is found to be \(-\)30.15 dB at 60 GHz. Therefore, we conclude that the input is matched well with the 500 hm antenna impedance and hence we find negligible reflections at the input at 60 GHz. Similarly, S\({}_{22}\) is the ratio of reflected power to the incident power on the output port and it is found to be \(-\)15.42 dB at 60 GHz. S\({}_{21}\) is the ratio of output power to the input power and represents the power gain for a well-matched PA. From Figure 9, S\({}_{21}\) is found to be 14.48 dB.  
The waveform shown in Figure 10 shows the amplified OOK modulated signal at the output of PA with a pseudo-random sequence of logic 0 s and 1 s at baseband signal input. As demonstrated 9 bits (00011100) are modulated between 1.06 ns and 1.59 ns indicating a data rate of nearly 17 Gbps. The output waveform indicates a 450 mVpp which translates to \(-\)3 dBm output power and is achieved with a total DC power consumption of 3.9 mW. This implies a bit energy efficiency of 0.23 pJ/bit at 17 Gbps on the transmitter side.  
Figure 8: Transmitter characterization (**a**) VCO oscillation frequency (**b**) ON-OFF state gain of modulator.  
Figure 7: Schematic and component values of the proposed power amplifier.