## 3 Proposed Serial to Parallel Converter  
A general S\({}^{2}\)P circuit should have the same number of D-flip flop (D-FF) as the number of control outputs. Because it feeds the input data serially and reads the outputs in parallel fashion as shown in Figure 2a. It means that as the number of data increases, the number of clocks for operation also increases. Therefore, it is difficult to directly apply to a system that requires a lot of control, such as a 5G system, because it has unnecessary clock consumption and increase of dc power consumption, simultaneously. To improve this problem, the proposed S\({}^{2}\)P circuit was designed with minimum D-FF applied by allocating addresses per byte as depicted in Figure 2b. Figure 2b shows the proposed 160-bit S\({}^{2}\)P architecture, and the operation flowchart is as in Figure 2c. The first D-FF group, which receives the 8-bit data signal with clock, has the  
Figure 1: (**a**) The transient frequency (\(F_{t}\)) and maximum frequency (\(F_{max}\)), \(F_{t}\) and (**b**) minimum noise figure (\(NF_{min}\)) at 8 \(\mu\)A current. Figure 2: Architecture of the conventional for 160-bit (**a**), proposed S\({}^{2}\)P converter (**b**), and flowchart for operation of proposed converter (**c**). same structure as a general 8-bit S\({}^{2}\)P converter. This D-FF has 4 input pins of data (D\({}_{1}\)), reset (R\({}_{1}\)), enable (E\({}_{1}\)) and clock, and has an output (Q\({}_{\Delta}\)). After that, 8-bit data is output to the second D-FF group input along with the enable signal. This second D-FF also has data (D\({}_{2}\)), reset (R\({}_{2}\)), enable (E\({}_{2}\)), clock, and address (A). This second D-FF outputs data to MUX-DEMUX block with one clock signal, and switches to the desired output byte according to allocated address signal. After starting, confirming the data of the reset, S\({}^{2}\)P starts operating while receiving the data and the clock signal. After that, data is transmitted to the second D-FF through the enable signal, and the input enable signal is used as the enable signal of the second D-FF. At this time, the DEMUX of the input enable signal is switched to the enable signal of the second D-FF due to an additional enable signal, which generated by combination of input address signals. And then, data is output through MUX-DEMUX to desired output. Subsequent data updates are performed quickly in each sequence. The proposed S\({}^{2}\)P converter can selectively update the desired output through the assigned address. The general converter requires 160 clock signals to update a desired output among 160-bit data. However, the proposed converter only needs 10 clocks per output byte without additional clock signal. This operation can reduce unnecessary clock operation of 150 bits, so it can be applied to a system requiring fast and low power. Figure 3 shows the post-simulation results using cadence specter simulator. After reset, data of output address second O [1,7:0] and [1] bit of O [1,7:0] is input with 8 clock signals. At the ninth clock, the output (Q\({}_{\Delta}\)) of the first D-FF waits at the second D-FF input. Thereafter, at the 10 th clock, the desired data is output and hold due to allocated address signal and enable. The design proceeded with the IC digital circuit design method. Verilog code was verified using Modelsim simulation tool, and then DC compiler tool was used for synthesis. The layout was placed and routed using the IC compiler tool, and the timing issues were simulated and verified. The verification of the design includes the results of simulating timing issues using each worst corner model provided by the process company. Figure 4 shows the chip layout in which place and routing (PNR) were performed include the process model. It was PNR using the IC compiler tool, and then layout was verified by layout and schematic comparison. The total chip was designed in an area of 990 \(\times\) 990 \(\upmu\)m\({}^{2}\), but it includes a buffer for measurement and pads for input/output pins.