## 8 Conclusions  
Modern FPGAs are widely used in the design of cyber-physical systems [13]. These chips are very powerful: a single FPGA chip is enough for implementing practically any block (either combinational or sequential) of modern CPSs [50]. The reverse side of the FPGA universality is an extremely small number of LUT inputs [21; 51]. This is a serious drawback that significantly complicates the design process. As a result, various methods of functional decomposition should be applied in the step of technology mapping. It is known that FD-based circuits are multi-level. The disadvantages of layered circuits are well known: they are slower and less energy efficient than equivalent single-level counterparts. Better results can be obtained by replacing the functional decomposition with the structural one [10]. This is proved, for example, in the work [19]. In the paper [20], the FSM circuit optimization is achieved due to using the twofold state assignment and encoding of output collections. The resulting \(P_{T}Y\) FSM circuits have better values of LUT counts than their FD-based counterparts. However, the twofold state assignment is connected with the transformation of maximum binary state codes into their extended equivalents. As a result, a code transformer should be used that consumes some additional resources of the FPGA fabric. To reduce the LUT count in the circuits of \(P_{T}Y\)-based FSMs, we propose to use two LUT-based blocks (cores). To do this, we use the main ideas from the paper [22]. Both cores generate systems of partial Boolean functions. This leads to \(P_{2T}Y\) FSMs having the following peculiarity: one of the cores uses the MBCs, whereas the second core uses the partial state codes. Our approach reduces LUT counts and slightly improves temporal characteristics as compared to equivalent \(P_{T}Y\)-based FSMs. The overhead of the proposed method is a rather insignificant increase in consumption of power (up to 1.56% on average). We hope  
Figure 14: Selection of FSM model. the proposed \(P_{2T}Y\) FSMs can function as an efficient tool for implementing FPGA-based sequential devices in modern cyber-physical systems. The conducted experiments have shown that, under certain conditions, the proposed method allows for better results than methods based entirely on either maximum binary or one-hot state codes. If some partial functions are implemented using a single LUT, then our method allows for improving the spatial, temporal, and energy characteristics of the LUT-based circuits of sequential blocks. We think that our method can be modified to take into account the use of state assignment methods other than the twofold one. In this, we see the further directions for the proposed method development. Under certain conditions, the transition from the proposed model to other models is possible (Table 11). In the most general case, the FSM architecture consists of three cores of partial functions. There are also three dual-core architectures. One of the directions of our further research is the development of synthesis methods and the study of the characteristics of LUT-based FSM circuits based on these two- and three-core models. Conceptualization, A.B., L.T. and K.K. ; methodology, A.B., L.T., K.K. and S.S.; software, A.B., L.T. and K.K. ; validation, A.B., L.T. and K.K. ; formal analysis, A.B., L.T., K.K. and S.S.; investigation, A.B., L.T. and K.K. ; writing--original draft preparation, A.B., L.T., K.K. and S.S.; supervision, A.B. All authors have read and agreed to the published version of the manuscript. This research received no external funding. Not applicable. The data presented in this study are available in the article. The authors declare no conflict of interest. The following abbreviations are used in this manuscript: