## 4 FPGA Implementation of PID Controller and BB-BC
### System Architecture  
The FPGA design consisting of the PID controller and the BB-BC algorithm is written in VHDL hardware description language and implemented in a Xilinx development platform, Zybo-7010 board, using the Xilinx ISE Design Suite 14.7 and Vivado Design Suite. Figure 8 depicts the entire system architecture including the FPGA device and the HVAC model implemented in MATLAB environment. The processing steps of the proposed architecture are shortly described below.  
1. The FPGA BB-BC module generates a set of random PID parameters (\(k_{p}\), \(k_{i}\), \(k_{d}\)), either to form the initial candidate or the new candidate around the center of mass in the next iteration cycles.
2. The FPGA PID controller module receives the values of the parameters and controls the HVAC plant.
3. The FPGA BB-BC module calculates the fitness functions for this candidate (i.e., PID parameters) using the ITAE equation and then calculates the new center of mass.
4. The HVAC model runs for a short period.
5. The evaluate function checks the system output and decides whether the BB-BC module must re-run to improve system performance, i.e., when the system has been affected by external disturbances that cause the output to exceed some predefined thresholds. Note that we use the HVAC plant as a part of the FPGA BBBC module to produce the first optimization parameters (\(k_{p}\), \(k_{i}\), \(k_{d}\)) of the PID controller for the HVAC model in the first run.  
Given that the evolutionary algorithms consume enough time to reach the optimal solution, even when the number of iterations is small, they are not suitable for latency-sensitive applications in real time. However, accelerating the evolutionary algorithm using an FPGA-based platform, as in the case of FPGA-in-the-loop (FIL) paradigm, can reduce the execution time and achieve the convergence into the optimal solution under specific timing constraints. Therefore, the FPGA-based BB-BC algorithm can be executed much faster, fact that improves confidence that the target optimization algorithm can finally satisfy the real-time requirements of an industrial application.  
The total execution time of the MATLAB/Simulink model (\(T_{MS}\)) incorporates the MATLAB processing time, the FPGA execution time and the time required for the data exchange between the host PC and the FPGA board and is given by the equation  
\[T_{MS}=T_{MP}+T_{M2F}+(T_{FPGA})+T_{F2M} \tag{14}\]  
where \(T_{MS}\) is total execution time of the MATLAB/Simulink model, \(T_{MP}\) is the MATLAB processing time, \(T_{M2F}\) is the time required for transferring data from MATLAB to FPGA platform, \(T_{FPGA}\) is the FPGA processing time, and \(T_{F2M}\) is the time required for copying data from FPGA platform to the MATLAB/Simulink environment.  
Figure 8: Proposed system architecture.  
Assuming population size \(N\) and number of iterations \(M\), the total execution time (\(T_{FPGA}\)) of the proposed FPGA BB-BC circuit is given by the equation  
\[T_{FPGA}=M\times N\times(T_{CG}+T_{FC}+T_{COM}+T_{PID+Plant}) \tag{15}\]  
where \(T_{CG},~{}T_{FC},~{}T_{COM}\) are the latencies of the FPGA BB-BC stages, i.e., candidate generation, fitness function calculation, and center of mass calculation, respectively and \(T_{PID+Plant}\) is the latency of FPGA PID controller and the plant.  
Figure 9 shows the top-level diagram of our MATLAB/Simulink model, which includes the FPGA BB-BC/PID module (using the FIL concept), the HVAC module, an analog-to-digital converter to feed the digital error value into the FPGA BB-BC module, an digital-to-analog converter to provide the PID controller output to the HVAC model, an adder to calculate the error and the set point.