# The Firmware Design and Implementation Scheme for C Form-Factor Pluggable Optical Transceiver +
## 3 CFP Firmware Design Scheme
### FPGA Design  
The detailed functionality of CFP firmware FPGA designed in this paper consists of an MDIO interface that communicates with the host, CFP standard memory configuration and access function, CFP hardware pin control function, and CFP power control function. Figure 5 shows an internal functional block diagram of the FPGA. All clock sources for FPGA operation come from the MCU. The clock speed is set to 48 MHz. The driving clock is used for the MDIO interface in the FPGA that communicates with the host, the communication between the FPGA and MCU, and information transfer between the FPGA internal blocks. The MDIO interface of the FPGA is implemented to operate as an MDIO slave. It is designed to enable data access (write/read) functions according to physical addresses set by the host. The FPGA has two main registers. The first register is the CFP register, which represents the CFP standard memory. It is implemented according to the CFP-MSA standard memory map described in Section 2, and the external host accesses the CFP register using the MDIO interface. The second register is an MCU interface register that communicates with the MCU to configure the additional memory map needed to control the CFP transceiver. The MCU monitors the access address and control request of the CFP register to the external host via the MDIO to reflect the internal CFP operation. Table 1 describes parts of the FPGA internal register memory map. Registers 0 \(\times\) 10010-0 \(\times\) 10017 are CFP hardware pin-related control registers. Register 10018 is used to control the related ICs for the power supply. Register 0 \(\times\) 1001B is used to limit the read/write of the specific register areas according to the password controls described in Section 2.2. When the host requests permission by entering a password value in the password entry address, the MCU controls the 0 \(\times\) 1001B address of the FPGA to allow access to the register in a specific area when matched against the entered value and  
Figure 5: Field Programmable Gate Array (FPGA) Block Diagram. the previously stored password. In addition, there are CFP internal IC control-related registers, but only some of them are described due to space limitations. The MCU interface block connects the FPGA and MCU, and MCU requests are processed through this interface block. An additional general register is implemented so that the MCU can monitor the MDIO access information and MDIO interface status. For memory read/write management, shadow memory is implemented in the FPGA using dual port memory for the CFP register area. Dual port memory is a structure that has read/write access from one of two ports. Because of this structure, if it is accessed from both sides simultaneously, invalid values may be used in memory and read. To solve this problem, priority is given to the host interface side. In other words, the MCU must not access the CFP register during the host access interval. The MCU as an internal controller should not be accessed while the host is accessing. The MCU monitors the access status register at 0 \(\times\) 10060-0 \(\times\) 10062 to verify that the address of the CFP register it wants to access is BUSY with the host. If the status is idle, the MCU performs the operation. However, the problem still exists. If the MCU performs the operation after verifying that the status of the access status register is IDLE, a collision occurs if the host approaches. If access is attempted by the host while the MCU is in write access, the FPGA forcibly blocks the write access of the MCU and sends the information to the MCU using register 0 \(\times\) 10062. Therefore, the MCU is able to confirm whether the current operation has been completed. Figure 6 shows the timing diagram of the collision and the blocking action.