## 2 Circuit Topology of RF-Energy-Harvesting Integrated Circuit
### Low-Voltage Low-Dropout Regulator  
Because of an input voltage with inference and input power limitation, a low-voltage and low-power LDO regulator is required for supplying a stable and clean voltage to the next stage. The designed LDO regulator was used for regulating the output variation in the over-voltage protection circuit and for providing a stable voltage \(\rm{V_{dd}}\) of 1.5 V to the charger control circuit. Figure 5 shows the proposed low-voltage LDO regulator, which includes a reference voltage, a current source, an error amplifier, a pass transistor, a feedback network, frequency compensation, and a load. A CMOS reference voltage \(\rm{V_{ref}}\) was generated and inputted to the positive terminal (+) of an error amplifier (EA). The negative terminal (-) of the EA was connected to the feedback network. A comparison between the reference voltage \(\rm{V_{ref}}\) and a feedback value indicates that the voltage difference between the positive and negative terminals was amplified as an output voltage of the EA, which was connected to a pass transistor for providing a stable supply voltage \(\rm{V_{dd}}\) by controlling the load current flow through the pass transistor [23]. Figure 6 shows the complete circuit of the adopted CMOS reference voltage [24]. The supplied voltage \(\rm V_{dc}\) could be maintained at a possible voltage of 0.7 V when all transistors operated in the subthreshold region. A compensation capacitor \(\rm C_{C}\) was added between the drain of \(\rm M_{N1}\) and ground (GND) to improve circuit stability by increasing the phase margin. Assume that \(\rm I_{2}=100\times I_{1}\), \(\rm W_{MP2}=100\times W_{MP1}\), and \(\rm W_{MN2}=100\times W_{MN1}\). The voltage of node X was equal to that of node Y (i.e., \(\rm V_{X}=V_{Y}\)). Figure 4: Proposed over-voltage protection circuit. Figure 5: Proposed low-voltage LDO regulator with a reference voltage, a current source, an error amplifier, a pass transistor, a feedback network, frequency compensation, and a load. Thus, the drain-source voltage of M\({}_{\rm P2}\) (V\({}_{\rm DS,MP2}\)) was equal to that of M\({}_{\rm P3}\) (V\({}_{\rm DS,MP3}\)). Two bias currents (I\({}_{2}\) and I\({}_{3}\)) were identical without channel length modulations of M\({}_{\rm P2}\) and M\({}_{\rm P3}\). If two NMOSFETs operated in the subthreshold region, the voltage difference across the resistor \(R_{1}\) is given as follows:  
\[V_{\rm R1}=V_{GS,MN2}-V_{GS,MN3}=nV_{T}\times\ln\frac{(W/L)_{MN3}}{(W/L)_{MN2}}, \tag{13}\]  
where \(n\) and \(V_{T}\) are the subthreshold region swing parameter and thermal voltage, respectively. The \(n\) is a constant and \(V_{T}\) is a parameter independent of the process. Thus, process variations do not influence \(V_{R1}\). \(V_{GS,\,MNi}\) and (\(W\)/\(L\))\({}_{MNi}\) are the gate-source voltage and the ratio of width to length for the transistor M\({}_{\rm Ni}\), respectively. Equation (13) indicates that a temperature coefficient (TC) is positive for the resistor's voltage \(V_{R1}\). Voltage reference \(V_{ref}\) can be written as follows:  
\[V_{ref}=V_{R2}+V_{GS,MN2}=2.01\times\frac{R_{2}}{R_{1}}\times V_{R1}+V_{GS,MN2}, \tag{14}\]  
where \(V_{R1}\) and \(V_{R2}\) are voltage differences across resistors \(R_{1}\) and \(R_{2}\), respectively, and \(V_{GS,MN2}\) is the gate-source voltage of the transistor \(M_{N2}\) with a negative TC. A positive TC was combined with a negative TC in an integrated circuit to obtain the desired reference voltage \(V_{ref}\) with zero temperature dependence [24]. The simulation result shows that the reference voltage \(V_{ref}\) varied from 499.035 mV to 502. 855 mV with respect to the supplied voltage V\({}_{\rm dc}\) from 1.7 V to 2.0 V at a quiescent current of 34 nA. Figure 7 shows the complete circuit of a low-voltage LDO regulator. The EA was a CMOS two-stage amplifier, which was designed to regulate the supplied output voltage V\({}_{\rm dc}\) of the low-voltage LDO regulator by controlling the gate voltage of the pass transistor V\({}_{\rm err}\).