# Large Field-Size Elliptic Curve Processor for Area-Constrained Applications
## 4 Implementation Results and Performance Comparison
### Results
For instance, the area for \(GF(2^{409})\) field are 0.82 (ratio of 30,561 over 36,857) times lower than \(GF(2^{571})\) field. Moreover, on 65 nm process technology, our proposed architecture can operate on a maximum 1800 MHz and 1450 MHz clock frequency over \(GF(2^{409})\) and \(GF(2^{571})\) fields, respectively. As for as the computational cost for one PM execution is concerned, our proposed architecture over \(GF(2^{409})\) and \(GF(2^{571})\) require 7.72 \(\upmu\)s and 14.17 \(\upmu\)s, respectively. This indicates that the 0.71 (ratio of 409 over 571) times increase in the field length (i.e., from \(GF(2^{409})\) to \begin{table}
\begin{tabular}{c c c c c c c c} \hline \(m\) & **Slices** & **LUTs** & **FFs** & **Clock Cycles** & **Freq (MHz)** & **Latency (\(\upmu\upmu\)s)** & **Thrpt** & **FoM** \\ \hline
409 & 4439 & 12,568 & 4129 & 13,903 & 357 & 38.94 & 25.68 kbps & 5.78 \\
571 & 5683 & 14,356 & 5961 & 20,551 & 317 & 64.82 & 15.42 kbps & 1.07 \\ \hline \end{tabular}
\end{table} 
Table 2: Implementation results on Xilinx (Virtex 7) FPGA. \begin{table}
\begin{tabular}{c c c c c c c} \hline \(m\) & **Area (\(\upmu\upmu\))** & **Clock Cycles** & **Freq (MHz)** & **Latency (\(\upmu\upmu\)s)** & **Thrpt** & **FoM** \\ \hline
409 & 30,561 & 13,903 & 1800 & 7.72 & 129.53 kbps & 4238.40 \\
571 & 36,857 & 20,551 & 1450 & 14.17 & 70.57 kbps & 1914.69 \\ \hline \end{tabular}
\end{table} 
Table 3: Synthesis results on (65 nm) ASIC. \(GF(2^{571})\)) results in 0.54 (ratio of 7.72 over 14.17) times increase in computation time. As shown in column six of Table 3, the throughput of our proposed accelerator design over \(GF(2^{409})\) and \(GF(2^{571})\) is 129.53 kbps and 70.57 kbs, respectively. When we consider the defined FoM for comparison, the last column of Table 3 shows that the proposed accelerator architecture over \(GF(2^{409})\) is more efficient than \(GF(2^{571})\) field. The reason is lower field length (i.e., 409). The lower field length utilizes lower hardware resources and takes lower computational time. Hence, the ratio of throughput over area results in a higher value for lower field length. _Comparison to FPGA and ASIC results._ As expected, the performance of our proposed architecture on ASIC is more efficient as compared to the FPGA implementations. The area comparison is not possible to provide. However, the frequency achieved on ASIC over \(GF(2^{409})\) and \(GF(2^{571})\) is 5.02 (ratio of 1800 with 357) and 4.57 (ratio of 1450 with 317) times higher as compared to FPGA. Similarly, the latency calculated for ASIC over \(GF(2^{409})\) and \(GF(2^{571})\) is 5.04 (ratio of 38.94 with 7.72) and 4.57 (ratio of 64.82 with 14.17) times lower than compared FPGA. The computational cost of our proposed architecture in latency can be reduced by using pipeline registers after each Karatsuba split, shown in Figure 2. If we consider the throughput and FoM values, Tables 2 and 3 reveal that the ASIC implementations on 65 nm technology are more efficient as compared to the modern 28 nm technology on FPGA.