# Latency-Aware Accelerator of SIMECK Lightweight Block Cipher
## 1 Introduction
### Existing Crypto Accelerators for Securing Low-Resource Embedded Devices
Four optimized architectures, i.e., (i) straightforward, (ii) two-stage, (iii) folded, and (iv) DSP-based implementation, are implemented on a 28 nm process technology (Artix-7 FPGA). There are two functional modules in implementations of straightforward designs, i.e., key expansion, and round function block, are implemented in an iterative approach. The loading operation of all four keywords requires only one clock cycle. The loading of four master keywords in parallel in a key expansion block is processed in a two-stage design implementation. The loading operation of all four keywords requires only one clock cycle. For each round of a key expansion, two keys are computed in parallel with a significant increase in hardware resources. For achieving least hardware resources, their folded design relies on their straightforward architecture where they reused the whole round function to implement the Key expansion block. Concerning the use of DSP48E1 slices, they further applied the DSP multi-pumping methodology on their two-stage architecture to further reduce the count of required DSP slices. Consequently, the implementation results are reported after logic synthesis. Therefore, these optimized architectures utilize 40 (for straightforward), 57 (for two-stage), 33 (for folded), and 43 (for DSP-based implementation) slices as an area. For these similar optimized designs, the achieved clock frequency values are 387.6, 297.7, 370.9, and 349.8 MHz. Different optimization strategies results in different clock cycle requirements: 32 (for straightforward), 16 (for two-stage), 32 (for folded). The clock cycles for the DSP-based implementation are not reported. In [30], three dedicated hardware architectures (with a 32-bit datapath) have been presented for three different lightweight cryptographic algorithms, i.e., LED 64/128, SIMON 64/128, and SIMECK 64/128. The implementation results are reported on Spartan-3, Spartan-6, and Zynq-7000 FPGA platforms in terms of hardware resources, speed, efficiency, and consumed power. On Zynq-7000 FPGA, their architectures result in high throughput up to 891.99, 838.95, and 210.13 Mbps for SIMECK 64/128, SIMON 64/128, and LED 64/128 algorithms, respectively. Based on test results and security analysis, their architectures provide efficient encryption with high performance and low area cost. Furthermore, their dedicated implementations are also secure enough against statistical attacks. The hardware implementations of LED and SIMECK block ciphers are considered in [31]. The implementation results are reported on Artix-7 FPGA. The utilized FPGA LUTs (look-up-tables), Slices, and achieved operational frequency for SIMECK64/128 block cipher is 139, 92 and 172.41 MHz, respectively. Even though some ASIC and FPGA accelerators of several cryptographic primitives for securing many wireless sensor nodes are described in [2; 6; 7; 8; 9; 15; 20; 26; 27; 28; 29; 30; 31]. Many of these designs [15; 26; 27; 30; 31] utilize higher hardware resources that are not feasible for low-resource embedded devices. With higher hardware resources, the computational cost for encryption and decryption computation is still high. For performance evaluations, only the area and computational complexity of the designs are considered without concerning the power consumption of their cryptographic circuits. We believe that the area and computational complexity of these accelerators can be improved by employing different architectural strategies, i.e., parallelism, pipelining, splitting data, and key blocks into smaller lengths, etc. To our best knowledge, we have identified only three hardware accelerators of the recently proposed SIMECK block cipher in the literature [20; 30; 31]. These implementations have not described the most critical design parameter, i.e., power, which is the fundamental requirement of the low-resource embedded devices. Consequently, power-optimized implementations of SIMECK are needed to establish a trade-off between state-of-the-art implementations of other lightweight cryptographic algorithms.