## 3 Hardware Implementation  
To achieve the real-time streaming operation, the proposed ANC system was implemented using a hardware CNN accelerator (Figure 10); it receives a differential analog signal from the reference microphone \(R\) and generates an anti-noise audio signal, through a class-D amplifier and an internal speaker in the in-ear headphone. The analog signal from \(R\) is converted to a 16-bit digital signal, at the sample rate of 46,875 S/s; the digital signal is applied to the hardware CNN accelerator, the delta-sigma modulator DAC [24] accepts the 16-bit CNN accelerator output and generates a 1-bit 6-Mbps pulse density modulation signal, which goes through a class-D amplifier, an LC low pass filter (inductance L = 220 uH, capacitance C = 470 nF, \(-\)3-dB cutoff frequency = 15.7 kHz), and the internal speaker (32 \(\Omega\)). The proposed hardware CNN accelerator was implemented in a field programmable gate array (FPGA), for the inference operation. The operations of the proposed CNN model (Figure 8) are divided into 10 one-layer operations and a 512-tap FIR operation; the one-layer operation is further divided into four steps (dilated 1-D CONV, ReLU, FC, residual/skip add). The number of input samples to the n-th layer (\(n\) = 1, 2, 3,\(\ldots\), 10), approximately, doubles as n increases by 1 (Equation (4)):  
\[2^{n-1}(kernel\ size-1)+time\ samples \tag{4}\]  
where the kernel size is 16, and the number of time samples is three; three adjacent time samples are taken from the dilated buffer (Figure 11), in a fetch cycle, and are processed, sequentially, in the one-layer operation, to achieve real-time operation, with the processing time of the CNN accelerator (Figure 12a,b) of 47.5 us (\(\sim\)2.2 samples), at clock frequency 120 MHz. For real-time streaming operation, the real-time factor should be less than 1. The CNN accelerator takes around the same time, 2.2 sample periods, to process an input unit of one or three samples. The real time factor is 2.2 and 0.74, for the input unit of one and three samples, respectively. Hence, an input unit of three samples is used in this work for the real time operation. The first layer (n = 1) fetches 18 samples L1 [1:18] from the dilated buffer, performs the four step operations, generates an output sample for L1 [1:16], and stores the one-sample output in L2 [49]; the output sample for L1 [2:17] is stored in L2 [50], and the output for L1 [3:18] is stored in L2 [51] (Figure 11). The dilated 1-D CONV operation takes 149 clock cycles to fetch 16 samples from the dilated buffer and perform the dilated 1-D CONV operation, then it stores the 16-bit output to the systolic array (SA) output buffer and repeats this procedure twice. The ReLU operation takes nine clock cycles to move data from the SA output buffer through Demux, RELU, and Mux, to the SA input buffer. The FC operation takes 93 clock cycles to move data from the SA input buffer, through the systolic array, to the SA output buffer. The residual-add and skip-add operations are performed, simultaneously, and take the same time of 14 clock cycles (Figure 12a). After the four-step operations are performed for all 10 layers, the output data of three samples are registered, as the newest data of the 514 samples in the FIR buffer. The FIR filter performs a 512-tap operation on the 512 samples of the FIR buffer, stores one sample output to the final buffer, and repeats this procedure twice (Figure 12b); this process takes 2653 clock cycles (Table 1). The total processing time of the three adjacent input samples is 5702 clock cycles (47.5 us). The clock cycles of every operation in Table 1 were  
Figure 10: The proposed ANC system, using the hardware CNN accelerator. measured by monitoring the state change at the master controller in the Verilog simulations. The system latency is eight samples (170.6 \(\upmu\)s), including the waiting delay of collecting three samples at the input buffer. The buffers require 41 kB memory, to store the data and the 3232 parameters of the CNN model.