## 5 Discussions and Conclusions  
This paper implements a new-developed phoneme pronunciation diagnostic framework for French CAPT modalities as a register-transfer level core. Classical machine learning networks are impacted by the multicollinearity problem among the predictors of the utterance sample vectors, the PLS algorithm is therefore applied in to the desired network as the feature extracting layer to suppress the collinearity. Next, the soft-margin SVM is used to perform the second network layer to enhance the classifying ability of the network. Experiments results demonstrate that this method possesses better accuracy performance than the state-of-the-art. Yet, we must claim that the performance of the DNN implementations are constrained by training data size, so the experiments of this paper cannot prove that the algorithm of this paper inevitably leads to the best performance. Considering that a classical DNN model include 5 layers at least (1 input, 3 hidden and 1 output layers), whereas the proposed one only 4 (1 input, 1 PLS feature extracting, 1 SVM classifying and 1 output layers), the latter is more suitable for the systems on chips. As far to the register-transfer level implementing of the design, we prototype it via a new-proposed VHLS SW/HW co-design flow in order to facilitate the development works and maintenances. During this work, it is found that synthesizing directly the behavior from Matlab down to RTL prevents the implementation from benefiting from the running-efficiency advantages of FPGAs, a series optimizing forms are therefore made in the loop and instrument levels. The CUEB French Phoneme Database is used to evaluate the achievements of this work. The experiments results verify the basic function of the new implementation by comparing it with its Matlab and C++ implementations. The hardware evaluation experiments demonstrate that the prototype of this paper make efficient use of the given hardware resources, and achieves a speedup of 10.89\(\times\), which making better use of the hardware resources. Despite of many benefits of development productivity and easy maintenances, it should note that high level synthesis seriously constrain the performance of FPGA implementations in the terms of hardware costs and running-efficiency comparing to the low abstract level implementations. If high performance is desired, some more bottom optimizations are still required, especially when the constraints of Placing and Routing cycle is taken into account. In the future research, we will further improve the methods of this paper. The PLS methods and hardware implementing experiences will be considered as a potential solution of sparse learning to solve the data-hungry problems, which may also benefit the embedded CAPT applications from deep learning methods. Meanwhile, there exists still some other hardware solutions worth trying, such as MicroBlaze, which may provide nice performance if well optimized. Conceptualization, Y.B. (Yanjing Bi) and C.L. ; methodology, Y.B. (Yanjing Bi), C.L., Y.B. ([PERSON]) and F.Y. ; software, C.L. ; validation, C.L. ; formal analysis, Y.B. ([PERSON]) and C.L. ; investigation, Y.B. ([PERSON]) and C.L. ; resources, Y.B. ([PERSON]), C.L., Y.B. ([PERSON]) and F.Y. ; data curation, C.L. ; writing-original draft preparation, Y.B. ([PERSON]) and C.L. ; writing-review and editing, Y.B. ([PERSON]) and F.Y. ; project administration and funding acquisition, Y.B. ([PERSON]), C.L., Y.B. ([PERSON]) and F.Y. All authors have read and agreed to the published version of the manuscript. This research was partially funded by National Natural Science Foundation of China (ID: 62171440), Chinese Academy of Sciences and Jiangxi Provincial Social Sciences \"14 th Five-Year Plan\" (2021) Fund Project (ID: 21 YY33). The study was approved by the Academic Council of School of Foreign Studies in the Capital University of Economics and Business (8 May 2023). Informed Consent Statement: Informed consent was obtained from all subjects involved in the study.