# NextGen ADS-B Software-Defined Reception with Enhanced Techniques
## 3 Methodology and Solutions
### Multiple Amplitude Samples Algorithm  
The 112-bit Mode S waveform used in the extended squitter is depicted in Figure 2. It illustrates the ADS-B message waveform. This waveform uses pulse position modulation (PPM) to modulate data. A pulse in the bit position's leading half denotes a binary ONE. A pulse representing a binary ZERO is at the trailing half-bit position. Figure 1: The high-level structure of ADS-B In signal processing. The four-pulse preamble signals signify the start of the Squitter reception. A dynamic power threshold is adjusted to 6 dB lower than the preamble level during preamble detection. The squitter reception processor will not be able to see any signals that are received below this level. The 24-bit CRC found in the parity identity (PI) field is used to identify errors after all of the bits have been received. The squitter is given to surveillance processing if no errors are found. An error correction approach is used if an error is found (implied by a non-zero value of error syndrome). One stronger overlapping Mode A/C False Replies Unsynchronized In Time (FRUIT) error can be corrected by the existing error correction procedure. This error is generated by unwanted responses by ground stations, and it leads to overlapping with the originated signal at the receiver end known as FRUIT. There are two widely used preamble detection techniques for detecting the signal's valid pulse position (VPP) [11], leading-edge position (LEP), and falling edge position (FEP) between 0 to 8 microseconds of the burst. Nonetheless, cross-correlation is one of the suggested solutions for preamble detection which is done in [21]. In our research, the preamble detection comparison between the leading-edge and cross-correlation performance is done. Following Investigation, a leading-edge position approach is deployed for preamble detection. To be more specific, if a sample has a large slope in the interval prior to it and a less than substantial slope in the interval after it, it is deemed to have a leading edge. Figure 3 flowchart explicitly illustrates the preamble detection procedure. In the initial stage, SDR needs to be configured according to ADS-B frequency, bandwidth as well as sampling rate, afterward the received data will be validated based on the leading edge in order to find out the pulse position [25]. In the second stage, when four pulses with the same spacing as the Mode S preamble are found, the preamble detection process starts to validate four pulses with timings of 0, 1.0, 3.5, and 4.5 microseconds. During preamble detection, a Reference Power Level is produced for purpose of re-triggering and demodulating the entire data block. It computes based on middle samples matching with pulse position and power of samples which are within 2 dB tolerance. In the next step, 1, 3.5, and 4.5 microseconds tests are done to detect later preamble pulses if there is any overlapped signal. For instance, a test for one microsecond is necessary to look for high power in the pulse positions 1, 2, 4.5, and 5.5 microseconds following the start to address this potential overlap issue. In addition, the preamble is put to another test to ensure its validity. This test determines whether at least two out of the four preamble pulses have power levels that are within the \(\pm\)3 dB range of the Reference Level. Otherwise, the preamble is rejected. Figure 2: ADS-B waveform and message format. DF validation is applied for each chip duration lasting 0.5 microseconds. If a Valid Pulse Position is located at, or inside \(\pm\)1 sample of, the leading-edge time for a given chip, a pulse is considered to have been detected. If each chip's peak amplitude is equal to or more than the threshold which is 6 dB lower than the preamble reference level, the detected preamble is then considered genuine. Otherwise, the preamble is discarded. As the last step, re-triggering activation will be evaluated and performed in case of finding stronger signals and later overlaps.