## 3 Results
### Devices Featuring Ni-ALD Dielectric-Ni Junctions
#### 3.2.3 Optimization of Ni-SiO\({}_{2}\)-Ni Junction Fabrication  
The optimization of Ni-based MIM SETs with SiO\({}_{2}\) PEALD dielectric was investigated using an approach that exploits the benefits and minimizes the weaknesses of both FGA and RHP treatments. We developed a process flow (referred to as FGA+RHP) where the first hydrogen-based treatment performed after barrier deposition is an FGA at 400 \({}^{\circ}\)C, because the main purpose of this step is to achieve complete reduction of the relatively thick parasitic NiO on the first Ni layer without damaging the SiO\({}_{2}\) barrier. At this stage of the fabrication, the byproduct of the process, H\({}_{2}\)O, easily diffuses through a thin dielectric layer and is removed. For the second treatment, the primary goal is mainly to anneal defects in the PEALD SiO\({}_{2}\) dielectric with a secondary objective of reducing the NiO layer on the bottom of the upper electrodes. For this purpose, we performed a study comparing double FGA with FGA+RHP treatments [48]. Using two dice originating from the same oxidized Si wafer, 50 nm-thick inlaid Ni islands are defined in the SiO\({}_{2}\) substrate using EBL, ICP, Ni evaporation, and CMP. Next, 12 layers of SiO\({}_{2}\) as the dielectric tunnel barrier are deposited by PEALD on one sample, and a stack of 10 SiO\({}_{2}\) + 2 Al\({}_{2}\)O\({}_{3}\) is deposited on the second sample. Subsequently, the samples are subjected to a 10-s O\({}_{2}\) plasma ashing step to clear any residual carbon on the deposited tunnel barrier. Next, the samples are treated with a 25 min-FGA at 400 \({}^{\circ}\)C in 5% H\({}_{2}\)-95% Ar. The source and drain leads are then defined in a second EBL, followed by an O\({}_{2}\) plasma de-scum, metal evaporation, and liftoff. After completion of the fabrication process, the devices were tested electrically at 300 K and they all exhibited very low conductance, averaging on the order of 100 pS, indicative of the additional NiO layer on the bottom of the source/drain electrodes [11]. At this stage, the dice are separated into two separate pieces for the final NiO reduction treatment: A1 and B1 with 12 layers of SiO\({}_{2}\), and A2 and B2 with a stack of 10 layers of SiO\({}_{2}\) + two layers of Al\({}_{2}\)O\({}_{3}\). Overall, more than 400 devices were fabricated in these four pieces. The A1 and A2 pieces were then used as reference samples and subjected to a second FGA for 10 min at 375 \({}^{\circ}\)C. The samples B1 and B2 were subjected to RHP (with the same conditions as described in Section 3.2.2 of this report). The average conductance at 300 K in all samples after the second treatment increased by a factor of \(\sim\)10\({}^{3}\). Figure 13: (**a**) \(G(V_{ds})\) dependence observed in (Ni-SiO\({}_{2}\)-Ni) SET fabricated with two RHP steps at a CBO peak. For \(V_{ds}\) above a threshold \(V_{Th}\approx 15\) mV, very strong noise is observed, but below this threshold the switching noise is much lower than in double FGA samples. The peaks of CBOs never reach \(G_{0}/2\) indicating that some NiO remains. (**b**) The spectral density of noise as a function of \(V_{ds}\) shows two orders of magnitude increase of noise above 15 mV (\(T=0.4\) K). Figure 14 shows the comparison of charging diagrams for devices fabricated using two FGA steps (batches A1 and A2, Figure 14a) vs. devices fabricated using FGA+RHP (batches B1 and B2, Figure 14b). Most importantly, all of the measured devices from batches B1 and B2 clearly show the disappearance of gate-independent excess noise typical of double-FGA devices from batches A1 and A2 (Figure 14a): diamonds are now clearly visible in Figure 14b.