# A Low-Phase-Noise 8 GHz Linear-Band Sub-Millimeter-Wave Phase-Locked Loop in 22 nm FD-SOI CMOS
## 2 System Architecture and Circuit Design
### PLL Divider Chain  
The I/Q VCO output frequency, being in the order of 160 GHz, is too large for the PFD, which is made of digital blocks. Therefore, a frequency division is necessary to bring the I/Q VCO output frequency down to the center frequency of 638.67 MHz, suitable for phase and frequency comparison. The divider chain is composed of two different divider types, namely the injection-locked frequency divider (ILFD) and the current-mode logic (CML) divider. First, a network of \(2\div 2\) ILFD (\(\div 4\)) was designed to convert the center frequency f\({}_{0}\) from 163.5 GHz to 40.875 GHz, followed by the CML divider network. The \(\div 2\) ILFD is depicted in Figure 3a and is based on injecting a current at f\({}_{0}\) in the middle point of the cross-coupled pair of M1 and M2. CPWG lines TL3 and TL4 are used in the resonator circuit along with the parasitic capacitances of M1, M2, and M5 instead of inductors for the first two dividers from the VCO output. This allows a wider locking range compared to the inductor-based divider.  
The sinusoidal voltage signal from the I/Q VCO buffer is fed to the gate of the transistor M5, which produces a tail current \(i_{i}=I_{inj}cos(\omega_{0}t+\varphi)+I_{0}\), where \(I_{inj}<I_{0}\). The condition \(I_{inj}<I_{0}\) is necessary to ensure that a net positive current is injected. Denoting \(Q\) as the quality factor of the LC tank, and \(\omega_{0}=2\times\frac{1}{\sqrt{LC}}\) and \(I_{osc}\) as its resonating frequency  
Figure 3: Frequency divider by 2: (**a**) injection-locked; (**b**) CML-based.  
Figure 2: I/Q VCO circuit.  
and current amplitude of oscillation, respectively, the synchronization range of the ILFD can be approximated as follows [13]:  
\[\Delta\omega_{0}\approx\frac{\omega_{0}}{2Q}\frac{4}{\pi}\frac{I_{inj}}{I_{osc}} \tag{1}\]  
As the current is injected through the PMOS transistor M5, \(I_{inj}=g_{m5}V_{inj}\), where the injected voltage \(V_{inj}\) corresponds to the output voltage of the VCO and \(g_{m5}\) is the transconductance of M5. In consequence, the synchronization range is proportional to the injected voltage amplitude \(V_{inj}\), which is the peak voltage of the preceding VCO stage. Meanwhile, the PMOS injection offers easier voltage transfer (matching) and current conversion from the VCO, as well as lower process capacitance, resulting in a wider locking range of the divider resonator. Additionally, a differential-to-single-ended buffer is employed to isolate the VCO from the first \(\div\)2 divider.  
Next, a six-stage \(\div\)2 CML divider (\(\div\)64) succeeds the ILFD network to bring the center frequency from 40.875 GHz down to 638.67 MHz. The conventional CML divider utilizes two D-latches with resistive elements in a master-slave configuration [5]. Here, a simplified input-unbalanced D-latch with no resistive load is used (as seen in Figure 3b). The divider uses two latches cross-coupling to allow clock division. The first latch is composed of transistors M1-M4, whereas the second is formed by M5-M8. The latch transistors M3-M4 and M7-M8 also provide resistive loading. The divider input is given through the current source I0, which is implemented by an NMOS transistor with W/L twice that of M1-M2 or M5-M6. The designed improved CML divider exhibits high speed and full voltage swing with large bandwidth.