## 4 Simulation and Experimental Results
Inductor current \(I_{L}\) is adjusted to their new steady-state values smoothly. The settling time is nearly 20 ms. This demonstrates stable performance over a wide load variation. It should be noticed that the experimental settling time is higher than the simulation value because the hardware experiences power loss, voltage drop, stray inductance/capacitance, system delay, and parasitic elements, which cause aberration from the ideal model. Better dynamic performance may be achieved by proper tuning of the controller parameters. \begin{table}
\begin{tabular}{c c} \hline
**Components** & **Parameters** \\ \hline Primary Switch (\(S_{1}\), \(S_{2}\)) & IRFB4127 PbF 200 V, 76 A, \(R_{ds,on}=17\) m\(\Omega\) \\ \hline Secondary Switch (\(S_{3}\), \(S_{4}\)) & IPP60R125 CP 650 V, 11 A, \(R_{ds,on}=0.125\)\(\Omega\) \\ \hline Series Inductor & TDK5901 PC40Z core, 3.9 uH \\ \hline HF transformer & 3C95 ETD49 ferrite core; \(N_{1}=5\), \(N_{2}=45\) \\ \hline Boost Inductors & 3C95 ETD49 ferrite core, \(N=42\), \(L=200\) uH \\ \hline Output Capacitor \(C_{O}\) & 220 uF, 450 V electrolytic capacitor \\  & 0.68 uF, 450 V high frequency film capacitor \\ \hline \end{tabular}
\end{table} 
Table 2: Component parameters of the hardware prototype. Figure 15: Laboratory prototype of the half-bridge converter. Figures 18 and 19 show the steady-state zoomed waveforms under half load and full load, respectively. Figures 18a and 19a show the gate-to-source \(V_{GS}\) and drain-to-source \(V_{ds}\) voltage waveforms across primary side MOSFET and transformer primary current \(i_{s}\) waveform at half load and full load, respectively. It is clearly demonstrated that the current through the switch naturally goes to zero. The negative current shows the antiparallel body diode conduction across the switch before turning off the gating signals, ensuring ZCS turn-off of the primary side semiconductor devices. Figure 16: Hardware result for step change in load from 50% load to full load: (1) voltage \(V_{AB}\) (100 V/div), (2) inductor current \(i_{L}\) (10 A/div), and (3) output voltage \(V_{o}\) (100 V/div). Figure 17: Hardware result for step change in load from full load to 50% load: (1) voltage \(V_{AB}\) (100 V/div), (2) inductor current \(i_{L}\) (10 A/div), and (3) output voltage \(V_{o}\) (100 V/div). Figure 19: _Cont._  
Figure 18: Experimental results for \(v_{int}\) = 12 V at 50% load: (**a**) gate-to-source voltage \(V_{Gs1}\) (20 \(V\)/div), current across primary-side MOSFET \(i_{s1}\) (20 A/div), and voltage \(V_{AB}\) = 50 V/div; (**b**) gate-to-source voltage \(V_{GS3}\) (20 V/div), drain-to-source voltage \(V_{ds3}\) (200 V/div), and current across secondary-side MOSFET \(i_{s3}\) (2 A/div). Voltage waveforms \(V_{GS}\) and \(V_{DS}\) across the devices clearly demonstrate the ZCS of the primary side devices and ZVS of the secondary side devices under both load conditions. The results are satisfactory during the transients that occurred due to sudden load disturbances while maintaining the steady-state performance. The steady-state performance is retained at the originally proposed in [17]. Corresponding gate-to-source \(V_{GS}\) and drain-to-source voltage \(V_{ds}\) waveforms of the secondary side devices are shown in Figures 18b and 19b. In these waveforms, gate-to-source voltage (\(V_{GS}\)) is applied when the voltage across secondary device \(V_{DS}\) is zero already, which ensures ZVS operation in secondary devices. It confirms the soft-switching of all the devices. Table 3 shows the comparison between the conventional active-clamped converter and the proposed snubberless topology. It is clear from the comparison that the snubberless operation with proposed control has several merits in terms of voltage gain, efficiency, reduced current, transformer size, and soft-switching range. Simple control has resulted in these merits with a demerit of limited duty range.