# A Novel Cross-Latch Shift Register Scheme for Low Power Applications
## 2 The Proposed Cross-Latch Shift Register (CLSR) Design
### Principle of the Proposed Circuit Architecture  
To solve the issues of high overhead layout area and high power consumption, the proposed CLSR scheme includes cross-latch architecture in optimizing the integrated circuitry layout area and lowering the power consumption. Figure 4 shows the architectures of the MS design (TGFF) and the proposed cross-latch shift register (CLSR) design. The proposed CLSR scheme consists of one cross-latch that performs the same functions as those of the master latch and slave latch of the conventional shift register. When CLK = 0, the slave latch S0 and master latch M1 store the same data. Thus, these two latches can be replaced by one cross-latch in the proposed CLSR design. When CLK = 1, the proposed CLSR uses one latch to hold the same data stored in the master latch and slave latch, respectively. In this CLSR scheme, we replaced the conventional master-slave (MS) latches (with the drawback of having two latches hold the same data at a different clock frequency) with one cross-latch.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & **TGFF** & **ACFF**[28] & **TSPCFF**[29] & **CSFF**[30] & **CLSR** \\ \hline Number of transistors & 48 & 44 & 36 & 48 & 36 \\
1-bit P/N of transistors & 12/12 & \(11/11\) & 8/10 & \(11/13\) & 9/9 \\ Floating problem & N & Y & Y & Y & N \\ Power (nW) & 300.10 & 304.00 & 700.70 & 271.10 & 163.90 \\ Area (\(\upmu\)m\({}^{2}\)) & 16.76 & 15.67 & 13.16 & 18.18 & 13.31 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Transistor-count comparison of 2-bit latch shift register.  
Figure 3: Snapshots of post-layout simulation waveforms. ACFF design: top rows. TSPCFF design: next rows. CSFF design: bottom rows.  
In the following paragraph, we use a 3-bit shift register to explain the difference between the proposed CLSR scheme and the conventional MS latch architecture. Figure 5 shows the schematic of the proposed cross-latch shift register (CLSR) design. When CLK = 1, the master and slave latches of each flip-flop (FF0, FF1, FF2) in the conventional MS latch architecture store the same data. Thus, the two latches can be replaced by one latch (green box) and still hold the necessary data. Likewise, when CLK = 0, the master and slave latches of different flip-flops store the same data so that the data can be stored by the path shown in the blue box. The data are conducted through the latch in the blue box when CLK = 0, and they are conducted through the latch in the green box when CLK = 1. The proposed CLSR scheme will not store redundant data during data transmission. Therefore, low power consumption and less integrated circuitry layout area design goals can be achieved simply because we have reduced the number of transistors dramatically.  
To implement this proposed CLSR scheme, an additional inverter is added in the flip-flop FF0 to ensure that the input data and output Q are at the same level. In the last stage, flip-flop FF2, an independent latch is adopted to ensure that static operation is maintained in the output stage. According to the above discussion, when the \(N\)-bit shift register is built, we need to copy FF1 until \(N\)-2 bit, and FF0 and FF2 stay in the first and last stages, respectively. In sum, the CLSR design fulfills the fundamental functions that the MS design has and wipes out the drawbacks that the MS design bears.