# The Eye-Opening Arbiter-PUF FPGA Implementation with Auto Error Detection
## 1 Introduction  
Security in electronic devices is a highly demanded requirement in many applications. To identify and protect intellectual property, electronic components, and systems from manipulations, counterfeiting, or other harm, physical unclonable functions (PUFs) have been proposed over the last two decades. They are memory-free low-power security primitives with the functionality to generate random but unique hardware fingerprints that can be used to identify hardware devices or for more advanced encryption applications like [1, 2]. The PUF uniqueness only depends on small manufacturing variations, which make its responses ideally unclonable and unpredictable, even by the manufacturer. Beyond many other parameters [3, 4], two important key requirements for PUFs are the stability of their response and short readout time. PUFs have been proposed in various architectures, both for implementation as integrated circuits (ICs) [5, 6, 7, 8] or on field-programmable gate arrays (FPGAs) [9, 10, 11, 12, 13]. Whereas IC-based PUFs obviously offer larger design space, FPGA-based designs offer other distinct advantages: the FPGA can be used both functionally and as source of entropy of the PUF by reprogramming, and FPGAs are intrinsically available in many state-of-the-art (SotA) electronic systems and are thus the more cost-effective solution in many applications. A well-studied SotA implementation of an FPGA-based PUF is the arbiter-PUF, as indicated in Figure 1a [10, 14]. The source of entropy is the delay difference regarding two parallel delay paths; the resulting phase shift of a triggered rising edge through thetwo paths is detected by an arbiter, effectively a D-flip-flop (D-FF) with one path entering its D-input and the other used as the clock input; the binary arbiter decision realizes a 1-bit output. The delay paths consist of switchable delay elements (SDEs), which can be swapped using multiplexers controlled by an input challenge vector. This alters the propagation delays depending on the challenge, which results in a challenge-dependent phase shift and arbiter response. Thus, a multitude of challenge-response pairs (CRPs) are generated, and this realizes a strong PUF [3]. Without the challenge and reconfiguration of the delay lines, every arbiter generates exactly one bit, and a weak PUF is realized. In [15], such a compact design was presented. Overall, the arbiter-PUF is very simple and has a fast response time, but it is very sensitive to noise as especially small phase shifts result in noisy unstable arbiter decisions. Moreover, when implemented as a strong PUF, it is also known for its easy attackability [16]. Ref. [10] reported a bit error rate (BER) of 2%, while the evaluation time is in the picoseconds range. Another SotA FPGA-based PUF is the ring oscillator (RO)-PUF, as illustrated in Figure 1b [9; 13; 17]. Herein, the source of entropy is again a chain of delay elements, which by positive feedback result in an oscillation frequency of an RO; by comparing the oscillation frequencies of two (adjacent) ROs, a response bit is obtained. In [18], guidelines for the design of efficient RO-PUFs are provided. The SDEs of the ROs can also be reconfigured upon a challenge input vector generating CRPs [19]. RO-PUFs offer much better stability compared to arbiter-PUFs as they average the noise by their longer oscillation times. Unfortunately, this comes at the cost of longer readout times [20]. For example, Ref. [19] reduced the BER to be \(<\)10\({}^{-4}\)%, while one evaluation required 20 ms. Also, they are prone to (even  
Figure 1: Different PUF architectures. (**a**,**b**) show two SotA architectures, while (**c**) shows the EoA-PUF, which uses two competing ROs, like (**b**), whose oscillation is stopped when their phase difference exceeds an adjustable deadzone, leading to fast and stable decisions by the arbiter based on (**a**). contactless) side-channel attacks due to the emission of RF spurs at their self-oscillation frequencies [20]. Another known variation of the RO-PUF is the TERO-PUF [21].