# FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
## 3 FPGA Counters Implementations
### Software-Like Counters
```
(a)  LDIN_UP CUCNT LDIN_RES RCNT LD17 PVCNT LDCNT.QU ST^OUT_UP (b) LDIN_UP STCNT.CU LDIN_RES STCNT.R LD17 PVCNT.PV CALCNT LDCNT.QU ST^OUT_UP (c) LDIN_UP CUCNT(ST+CAL) LDIN_RES RCNT(ST+CAL) LD17 PVCNT(ST+CAL) LDCNT.QU ST^OUT_UP (d) LDIN_UP STCNT.CU LDIN_RES STCNT.R LD17 PVCNT(+CAL) LDCNT.QU STOUT_UP
```

The above example uses only some of the functionalities of the counter, as it is often used in practice. The time needed to execute the above functionality for the S7-319 controller is, respectively: 1328 ns for counters compliant with the standard and 415 ns for counters realized in the Simatic standard. The S7-1516 unit--from the family of the newest and the most efficient units--need to execute the program, respectively, in: 405 ns for counters compliant with the standard and 250 ns for Simatic standard counters. So the fastest PLC, using a 16-bit classic counter, runs the presented program about 5 times longer than the slowest unit presented in this paper. In the case of the fastest unit, presented in the most left-hand side column of Table 6, this disproportion is twice as large. ## 5 Conclusions

This paper presents the idea of hardware support for IEC61131-3 compliant counter operations. The developed concept can be used in practice, whereby the counter block can work with a dedicated microprocessor/microcontroller or a general-purpose unit. The minimalistic interface between the CPU and the counter block allows building PLCs with very low latency for counter operations. The concept of bit.WORD integrated hardware/software controller is presented. One part of the microprocessor performs operations on BOOL-type variables only, while the other part enables operations on WORD-type (32-bit) variables. Such a concept enables some parallelism of the performed operations that are executed concurrently, e.g., bit and word data could be written to counter block concurrently. The presented concepts have been described in Verilog HDL language and implemented in an FPGA device with a dedicated software core CPU performing basic operations. Two types of counters are presented. The first one is a classical hardware counter built on the basis of flip-flops. The second type, software-like, is also hardware-based. However, it draws on ideas of software implemented counters in its design. It is based on memory cells on which operations are performed. Both structures are very fast and make it possible to execute the counter update operation in a single clock cycle. Nevertheless, hardware counters provide faster structures. However, they utilize flip-flops, making these structures effective for small counter blocks. Hardware counters with some small modifications can work as high-speed counters which count events regardless of the program [25]. Software-like counters are a slightly slower design (in the range of max frequency), but they are based on memory-dedicated FPGA structures. This makes even a counter block for 1024 counters not a big problem. Experimental results show the validity of the adopted solutions. Changes accompanying the fourth industrial revolution, Industry 4.0, such as large-scale communication, increased automation, improved communication, self-monitoring, and production of smart machines, have led to the need for increased performance of programmable logic controllers. The Integrated Hardware-Software PLC idea is especially suitable for that purpose. First, the control loop is relatively short in relation to classical solutions. Second, bit.WORD units can work concurrently and in the future, support for \"out of order\" technology is planned. Third, different communication modules can be easily integrated with the PLC core, so the integration in digital communication networks is possible. Conceptualization, M.C. and R.C. ; methodology, M.C., R.C. and A.M.; software, M.C., R.C. and A.M.; hardware, R.C. ; validation, M.C., R.C. and A.M.; formal analysis, M.C. ; investigation, M.C., R.C. and A.M.; writing--original draft preparation, M.C. and R.C. ; writing--review and editing, M.C., R.C.