## 2 Circuit Description  
### Proposed 0.3 V CDBA  
The electrical symbol of the CDBA is shown in Figure 1. Its operation in an ideal case is described by Equation (1). The circuit can be seen as a current differential amplifier with zero-impedance inputs \(p\) and \(n\) and infinite-impedance output \(z\). The difference in currents flowing into the \(p\) and \(n\) terminals is conveyed to the \(z\) terminal with a current gain equal to unity. In addition, there is an additional voltage buffer between the \(z\) and \(w\) terminals with a voltage gain equal to unity and a zero output impedance. \[ \begin{pmatrix}I_{z}\\ V_{w}\\ V_{p}\\ V_{n}\end{pmatrix} = \begin{pmatrix}0&0&1&-1\\ 1&0&0&0\\ 0&0&0&0\\ 0&0&0&0\end{pmatrix}\begin{pmatrix}V_{z}\\ I_{w}\\ I_{p}\\ I_{n}\end{pmatrix}  \tag{1}\]The CMOS structure of the CDBA proposed in this work is shown in Figure 2. The circuit consists of two identical non-inverting current conveyors (CCIIs), namely M1-M8 and M1c-M8c, as well as one voltage buffer M1b-M7b. The CCIIs were presented and verified experimentally in [47]. Their structure was developed from the ultra-low-voltage buffer (M1-M3, M5-M7) first proposed in [48], by adding a high-impedance output stage (M4 and M8), thus creating a \(z\) output of the conveyor. The circuit exploits bulk-driven transistors that allow for avoiding the constraints associated with threshold voltages of MOS transistors, providing a rail-to-rail signal swing even at very low supply voltages. Considering the first conveyor M1-M8, we should note that the bulk terminal of M1 corresponds to its \(Y\) input (grounded); the drain of M3 (\(p\) terminal of CDBA) corresponds to the \(X\) terminal; and the drain of M4 (\(n\) terminal of CDBA) is its \(z\) output. Thus, the current flowing into the terminal \(n\) of the CDBA is subtracted from the current flowing into its \(p\) terminal, and this difference is conveyed to the output \(z\) of the CDBA. Between \(z\) and \(w\), we have a voltage buffer with an identical structure as the one used in current conveyors. As already mentioned, the current conveyor structure consists of the \(Y-X\) voltage buffer (M1-M3, M5-M7) and the output stage M4-M8. The voltage buffer [48] can be seen as a two-stage operational transconductance amplifier (OTA) operating in a voltage follower configuration. Transistors M1 and M2 form a simple non-tailed BD differential pair, biased by the current sinks M5 and M6. The input stage is followed by the second stage of OTA, consisting of the transistor M3 biased by the current sink M7. Due to the non-tailed architecture with BD transistors, the circuit can operate with a very low supply voltage of two saturation voltages of MOS transistors in weak inversion (ca. 200 mV), while offering a rail-to-rail voltage swing. An interesting feature of the proposed structure is its high voltage gain accuracy, despite the relatively low open-loop gain of the internal OTA [48]. This improves its frequency response and eliminates the need for additional compensation capacitors, even for load capacitances on the order of several picofarads. By doubling the output stage transistors, a CCII configuration can be achieved. To obtain a CCII with a supply voltage of 0.3 V, i.e., about 60% of the threshold voltages in the used technology (0.5 V), the circuit was biased with very low currents of the order of nA. In addition, \(V_{GS}\) voltages for all transistors were around mid supply, for the assumed channel lengths of 1 \(\upmu\)m, which provides maximum headroom for the possible impact of the process, voltage and temperature (PVT) variations, and signal swing. The channel length of transistors is relatively large to increase their output resistances and consequently  
Figure 1: Electrical symbol of the CDBA. Figure 2: Proposed 0.3 V CDBAs. intrinsic voltage gains. The biasing current of the output stage is five times larger than the biasing current in each branch of the input differential amplifier, which decreases the output resistance and improves the stability margin of the internal OTA.