# Large Field-Size Elliptic Curve Processor for Area-Constrained Applications
## 1 Introduction
### Related Work  
Elliptic curve point multiplication (ECPM) is the most critical part (from a computation point of view) in elliptic curves. The EPCM further depends on the computation of two more operations. These operations are point addition (PA) and point double (PD). The PA and PD computations depend on the execution of finite field addition, square, multiplication and inverse operations. Different hardware accelerators have been described in the literature to optimize the ECPM implementation. Nevertheless, the most recent architectures are described in [15; 16; 17; 18; 19; 20; 21; 22; 23; 24; 25].  
A highly efficient architecture for ECPM computation on Koblitz curves is proposed in [15] over \(GF(2^{163})\) to \(GF(2^{571})\). The selected PM algorithm allows the parallel processing of Frobenius maps and point additions. Moreover, to minimize the computational time and improve clock frequency, the scheduling of point addition operations is performed. A pipelined multiplier accumulator unit is used. Finally, the inversion is based on efficient addition chains for the reduction of clock cycles. In [16], a GCC-6 CC (clock cycle) dual-field ECPM architecture is proposed. A Karatsuba multiplier is utilized to compute efficient polynomial multiplications. The scheduling of addition operations minimizes the total number of required cycles. The results are provided on Xilinx Virtex 5 and Virtex 7 FPGA devices.  
An efficient throughput over area ECC processor over binary elliptic curves is proposed in [17]. A segmented digit-serial finite field multiplier is utilized to reduce hardware resources. Moreover, the scheduling of addition operations reduces latency (i.e., the computational time for PM execution). The results are synthesized on Virtex 7 FPGA device over \(GF(2^{163})\) to \(GF(2^{571})\) fields. Another throughput over area efficient ECC processor is presented in [18]. The area is reduced by employing only a singular finite field multiplier. A 41-bit digit-parallel multiplier is used to compute finite field squares and multiplication operations. Throughput is optimized using a 2-stage pipelining and rescheduling of PA and PD computations. Over \(GF(2^{163})\) to \(GF(2^{571})\) fields, the implementations are provided on Virtex 7 and modern 16 nm ASIC technology.  
The authentication of IoT (Internet of Things) devices is generally performed using a Physical Unclonable Function (PUF). Therefore, the leakage of PUF responses in an authentication system reduces its privacy and security. To improve its security, an ECC-based PM algorithm with different key lengths is used in [19]. The hardware resources are reduced by reusing the underlying finite field computing units. Their circuit achieves a maximum of 135 MHz frequency on Virtex 6 device. The single ECPM computation takes 19.33, 22.36, 41.36 and 56.5 \(\upmu\) for 233, 283, 409 and 571 key lengths respectively.  
The Weierstrass model of ECC is implemented in [15; 16; 17; 18; 19]. Nevertheless, these designs are vulnerable to side-channel attacks. Consequently, in order to prevent these side-channelattacks, Edward and Huff curve-based PM architectures have been described in [20; 21; 22; 23; 24; 25]. The Edward and Huff curves (special models of ECC) provide unified PA and PD operations to execute the PM operation in ECC. On Xilinx FPGA devices, Edward curve architecture over \(GF(P)\) with \(P=256\) is implemented in [20; 21]. Similarly, the FPGA implemented Edward curve designs over \(GF(2^{233})\) is described in [22; 23]. The 4-stage pipelined architectures of Huff curves over \(GF(2^{233})\) on FPGA is implemented in [24; 25].