## 4 Separated Phase-Current Control Using IBDGs
The sampled phase voltage of the downstream IBDG (\(V_{x-down}\)) is transferred to the upstream IBDG via smart grid communication. When this voltage reaches the upstream IBDG, it is transformed into \(V_{d}\) by [PERSON]'s transformation. The switching operation of the voltage selector is dependent on a trigger signal. If the \(V_{d}\) of the upstream IBDG lies within the permissible voltage limit and the \(V_{d}\) of the downstream IBDG is over the admissible voltage limit for longer than 0.05 s, a trigger signal is produced. Then, the \(V_{d}\) of the downstream IBDG is chosen as the input of the voltage regulator of the upstream IBDG. The reactive current of the upstream IBDG increases. For the faulty phase, the current reference generator is divided into two circumstances. The first circumstance is already explained. The AND gate generates the FIM signal as it receives both the fault signal and SDG connection signal. The FIM strategy is enabled to eliminate the effects of fault current contribution from the SDG. The phase current reference is calculated by  
\[I_{x-ref}=I_{max}\cdot sin\Big{[}2\pi ft+\theta_{g-est}+\beta\Big{]}, \tag{12}\]  
where \(f\) is the grid frequency and \(\theta_{g-est}\) is the phase angle of the estimated grid current. The details of the grid and SDG current estimations will be explained in Section 6. When the estimated grid current \(\Big{(}I_{g-est}\Big{)}\) and estimated SDG current (\(I_{SDG-est}\)) are achieved, they are sent to the Fourier analysis (FA) module contained in the FIM strategy. The FA module extracts the amplitude of the estimated grid and SDG currents (\(\big{|}I_{g-est}\big{|}\) and \(\big{|}I_{SDG-est}\big{|}\)) and the phase of the estimated grid and SDG currents (\(\theta_{SDG-est}\)) (Equation (12)). The \(\beta\) angle can be calculated by using Equation (7). The current amplitude of the IBDGs (\(\big{|}I_{IBDG}\big{|}\)) connected to grid is used in the calculation. Thus, to correctly calculate the \(\beta\) angle in the case of some IBDGs being disconnected from the grid, the IBDGs should recognize the disconnection. The disconnection signal (DISC) of the IBDGs can be obtained through smart grid communication. If some IBDGs are disconnected, the disconnection signals are sent. Their current amplitudes for calculating the \(\beta\) angle are set at zero. \(N\) stands for the number of IBDGs installed in the system. As a consequence, the \(\beta\) angle calculation is still correct, although there is a disconnection for some IBDGs. On the other hand, for the second circumstance, the AND gate receives only the fault signal sent from the FD module, since the SDG is disconnected from the grid. Hence, there is no FIM signal produced by the AND gate, and the VC strategy is enabled. For the isolated phase, the islanding strategy is activated because of the tripping signal sent by the recloser. The phase current reference is set at zero in order to prevent the damages caused by out-of-phase reclosing. A control diagram of the current control for \"neutral\" connected to the fourth leg of the IBDG is shown in Figure 5. When three-phase current references are prepared, they are combined with a negative sign. This summation is set as the current reference for \"neutral\" (\(I_{n-ref}\)). Finally, in Figures 3 and 5, the three-phase current references and neutral current reference are sent to the PI current controller. In the phase current regulation, the PI controller compensates for the error between the phase current reference and phase current feedback (\(I_{x}\)). Similarly, a PI controller is also adopted for the neutral current (\(I_{n}\)) regulation. The outputs of the PI controllers for the phase and neutral currents consist of the phase voltage reference (\(V_{x-ref}\)) and neutral voltage reference (\(V_{n-ref}\)), respectively. The voltage references are applied in generating the pulse width modulation (PWM) signal. Figure 5: Control diagram of the current control for “neutral”.