# Influence of Quality of Mounting Process of RF Transistors on Their Thermal Parameters and Lifetime
## 3 Solder Process  
According to the IPC-610 [24] standard, 30% of the total area of voids cannot be exceeded, and the additional criterion is the limitation to the maximum of 8% of the individual empty space under the soldering surface of the investigated RF power transistors. In order to control both the indicators, 100% production of such modules undergoes the X-ray test [38] with the X-ray DAGE system: XD7600 NT. This test detects any errors in the SMT process, such as voids in the soldering process or short circuits. The examples of the results of such measurements are presented in Figure 3.  
The presented results are for the transistors soldered in such a way that at least one of the requirements related to the size of the void is not satisfied. In Figure 3a, the total void size is 18%, but the individual void size is as high as 12.7%. On the other hand, the largest total surface not covered with the solder is shown in Figure 3b. In this case, both the overall void area exceeds 30% and the individual largest void is 9.6%. An important observation is that the presence of voids occurred in the case of gold-plated transistors. For the other models of transistors with silver coating of the leads mounted on other PA modules no process problems were observed. For the presented examples of the process defects, a cross-section was made, also presented in Figure 3. As a result of the cross-sectional cutting of the transistor by the area of voids occurrence, 8 regions can be distinguished. Regions 1-3 are for the solder layer  
Figure 3: X-ray images of the area of the soldered joint and microscopic cross-section photos of such a joint for a big individual void (**a**) and many small voids (**b**): 1—black color means voids; 2—golden color means remnants, pollen due to the cross-section; 3—silver color—solder joint; 4—PCB layer; 5—transistor case; 6—active area of the transistor; 7—source active layer; 8—golden source electrode. of the transistor source. In the photo, there are solder voids (region 1) visible, which were previously localized by performing an X-ray test. In order to illustrate the problem of a high number of voids in the produced modules, some information about the production process is collected in Figure 4. This figure presents the qualitative results and the level of such process errors for the discussed power transistors [35; 36] installed in the described electronic modules. Figure 4 presents values of the quality index in the successive months, the yield [38], related to the level of occurrence of empty individual spaces in relation to the production level. It was compared with the yield level associated with the occurrence of short-circuits on the transistors, also appearing in the SMT assembly process. It can be noticed that regardless of the registered number of modules tested using X-ray (blue bars in Figure 4) in each month from 20 January to 21 February, the permissible value of voids was exceeded. Products with such process defects accounted for 8% to even 34% of the production batch (red line in Figure 4). This proves that the void level indicator was not sufficiently controlled in the discussed period. At the same time, for the same number of samples measured in the X-ray test, the level of short-circuits on the assembled RF power transistors was recorded. In this case, the results remained stable and indicated that less than 1% of the products made in individual batches required a rework process (black line in Figure 4). Figure 4 shows that the presence of voids that did not meet the criteria described above affected the quality of soldering much more than the occurrence of short circuits. Thus, it is the main procedural problem. At the same time, it is important to check the risk of voids for the operation of electronic modules.