## 2 Background
### Schoolbook Strategy
For an operand size of 163 \(\times\) 163, the reference design achieves a maximum frequency of 177.8 MHz, while our accelerator runs at 131 MHz. Comparatively, the reference multiplier accelerator is faster in operating frequency than our hardware accelerator. This higher circuit frequency in the reference design results in a lower computation time than our accelerator, evident in column six of Table 2. Similarly, our accelerator uses more slices than the accelerator of [14]. This might happen due to using different devices, i.e., Virtex-II in the reference design and Virtex-4 in our work. Compared to the Spartan-6 implementation of a 32 \(\times\) 32 radix-4 Booth multiplier of [17], our Kintex-7 Booth multiplier accelerator is 6.45 (ratio of 645.161 with 100) times faster in operating frequency. One reason could be the different implementation platforms. Another reason is the use of registers/buffers in our accelerator, which benefits in optimizing the frequency, while in the reference accelerator, a combinational logic is implemented. A comparison to the latency is impossible as the reference design lacks this information. Although our accelerator operates at a higher circuit frequency, on the other hand, it utilizes more area in LUTs than the reference design. Thus, there is always a trade-off between frequency and area utilization. The Kintex-7-implemented design in [18] considers 16 \(\times\) 16 operand lengths. On similar Kintex-7 devices using the same operand sizes, our design uses fewer LUTs than the reference design. The other parameters cannot be compared because the reference design lacks the corresponding details. ## 5 Conclusions

This article has presented a parameterized hardware accelerator design for the Booth polynomial multiplier. The parameterization enhances flexibility, enabling users to conduct multiplication across diverse operand lengths rather than being restricted to specific operand sizes. We have reused hardware resources to optimize the Booth accelerator efficiently, which helps minimize the design's overall area cost. Moreover, an FSM-based controller is implemented for control purposes. A detailed comparison of the results (in terms of throughput over area) of the proposed Booth multiplier design with several non-digitized bit-serial polynomial multiplication accelerators is provided. The Booth multiplier design is implemented in Verilog HDL using the Vivado IDE, and the implementation results are considered up to the post-place and route stage on the Xilinx Virtex-7 FPGA. The architecture allows various operand sizes up to 4096 bits for evaluation. Thus, our accelerator with shorter operand lengths is more convenient for various applications. This research received no external funding. **Data Availability Statement:** The work performed in this study is not available due to security reasons. **Conflicts of Interest:** The author declares no conflicts of interest. ## References

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