# The Eye-Opening Arbiter-PUF FPGA Implementation with Auto Error Detection
## 1 Introduction
Instead of using two parallel ROs, they are connected in one chain to prevent locking phenomena. In [22], a compact variant, using just two inverters and D-latches, was proposed. Another common PUF approach regarding FPGAs was exploited with SRAM-based PUFs [23; 24]. The bistable state of a non-written SRAM-cell decides on either 0 or 1 shortly after start-up. Unfortunately, the native SRAM PUF has a high error rate [23]. The bistable ring (BR)-PUF also evaluates the final state of several inverters arranged in a ring structure after release from a bistable state, like a power-up but offering a challenge input [11]. The instability in PUF responses due to noise, but also due to environmental changes like supply or temperature, has to be corrected for as, otherwise, authentication, fingerprint generation, or any cryptographic application would become impossible. Various methods are employed in the SotA to stabilize PUF responses. Bit-masking is used to store the locations of unstable bits and to blank them for reproducing the PUF response [5; 6]; disadvantageously, in an enrollment phase, the unstable bits must first be found by (factory) measurement, and the positions of unstable bits can even change upon other environmental changes, such as temperature, which makes the task complex and costly. IC-based PUFs have also used hardening techniques, e.g., in IC-based SRAM PUFs [24]; this is not applicable in arbiter-, RO-, or generally in FPGA-PUFs. For the remaining PUF errors, digital error correction can be used [25; 26]. The remaining random bit-flips of the PUF response are treated like noise in a communication channel, which are then corrected using helper data and error correction codes (ECCs). Obviously, the more errors that need to be corrected, the lower the code rate (number of useful bits for a given number of raw bits) and the more the complexity of the helper data and error correction algorithms increases. This helper data needs additional costly permanent memory, motivating a reduction in the amount of necessary data. Furthermore, the helper data can leak information about the secret PUF information to an attacker. Thus, secure schemes to store helper data have to be implemented, as investigated in [25; 26; 27]. Consequently, there is demand for more robust PUF architectures and improved PUF stabilization techniques, which ideally include the possibility to automatically detect unstable bits, to have an as ideal response of the PUF as possible before digital error correction. An idea to achieve this is the application of the so-called eye-opening arbiter (EoA)-PUF [28]. It operates as a mixture between the arbiter- and ring oscillator-PUFs and exploits phase difference integration by enabling oscillation until a predefined phase difference threshold (deadzone) is exceeded; this is illustrated in Figure 1c. Thus, it promises both fast and highly robust readouts. In this paper, we present the first actual FPGA implementation of the EoA-PUF and validate its principles by measurement. Several tuning algorithms are proposed to remove routing-based response bias, which is--in contrast to IC-based implementations--an intrinsic non-ideality in FPGA-based designs. The paper is organized as follows: Section 2 reviews the basic operation of the EoA-PUF. Section 3 describes the FPGA-specific implementation of the EoA-PUF and a tuning method to overcome routing-induced bias. The PUF uniqueness is examined in Section 4, and, in Section 5, the adjustment of the deadzone and resulting BERs are investigated. Section 6 summarizes our work, and Section 7 concludes the paper.