# A 13.44-Bit Low-Power SAR ADC for Brain-Computer Interface Applications
## 2 Circuit Topology
### Bootstrapped Sampling Switch Design
The random clock jitter can be modeled as a white noise source \(x_{\text{jitter}(t)}\) that is added to the input prior to ideal sampling, where the resulting sampling error power due to clock jitter is given by the following:  
\[x_{jitter}^{2}(t)=[A\omega_{\text{in}}\cos(\omega_{\text{in}}t)]^{2}\cdot\delta _{jitter}^{2}(t)=\frac{(2\pi f_{\text{in}}A)^{2}}{2}\delta_{jitter}^{2}(t). \tag{3}\]  
Given the input sinusoidal signal power of A\({}^{2}\)/2, the resulting signal-to-noise ratio degradation caused by sampling clock jitter is as follows:  
\[SNR_{jitter}|_{\text{dB}}=-20\text{lg}\big{[}2\pi f_{\text{in}}\delta_{ jitter}(t)\big{]}. \tag{4}\]  
The signal-to-noise ratio degradation caused by clock jitter depends not only on the jitter itself, but also on the input frequency, with empirical design practice requiring that jitter-induced noise remains below half of the quantization noise, expressed as follows:  
\[\frac{(2\pi f_{\text{in}}A)^{2}}{2}\delta_{jitter}^{2}(t)\leq\frac{1}{2\cdot 1 2}\cdot(\frac{2A}{2^{N}})^{2}, \tag{5}\]  
\[\delta_{jitter}^{2}(t)\leq\frac{1}{12\pi^{2}f_{\text{in}}^{2}2^{2N}}. \tag{6}\]  
For a 12-bit ADC operating at 320 kS/s, the RMS jitter \(\delta_{\text{jitter}}\) must be maintained at below 2.31 ns--a readily achievable specification--while the white noise introduced by clock jitter can be effectively suppressed through oversampling techniques, demonstrating how moderate-speed converters benefit from relaxed jitter requirements and noise-shaping capabilities. According to references [12; 13], the third-order harmonic distortion introduced by a constant on-resistance sampling switch is given by the following expression, indicating that linearity can be improved by reducing the on-resistance while increasing the V\({}_{\text{GS}}\) of the sampling transistor. \[|HD3|\cong\frac{1}{4}\frac{A^{2}}{(V_{\text{GS}}-V_{\text{TH}})}2\pi f_{in}RC _{L} \tag{7}\]  
where A represents the input signal amplitude, fin denotes the input frequency, R is the on-resistance, and C\({}_{\text{L}}\) signifies the sampling capacitance. The synchronous clock-controlled circuit features fixed conversion time for each bit. Through a series-connected MOSFET configuration, this design enables optimized switch transistor sizing where each bit's capacitor employs switches with tailored on-resistance--this approach minimizes the overall device area while maintaining timing precision, as illustrated in \[R_{\text{on,bootstrap}}=\frac{1}{\mu_{\text{n}}C_{\text{ox}}\frac{W_{\text{N }}}{L_{\text{N}}}\left(V_{\text{DD}}-V_{\text{THN}}\right)}, \tag{1}\]0 The ellipsis (...) in the schematic denotes replicated MOS transistors with identical configurations. Operating at a 320 kS/s sampling rate with a 9.6875 kHz input frequency that satisfies coherent sampling conditions, the dynamic performance characteristics of the least significant bit in the sampling circuit are demonstrated in \[R_{\text{on,bootstrap}}=\frac{1}{\mu_{\text{n}}C_{\text{ox}}\frac{W_{\text{N }}}{L_{\text{N}}}\left(V_{\text{DD}}-V_{\text{THN}}\right)}, \tag{1}\]1