## 4 System Simulation Analysis
### Analysis of Output Stage  
The three-phase voltage output of the NPC three-level inverter circuit was as follows:  
\[\left\{ \begin{aligned} & U_{AN}=\frac{1}{6}U_{ld2}(2S_{A}-S_{B}-S_{C})\\ & U_{BN}=\frac{1}{6}U_{ld2}(2S_{B}-S_{A}-S_{C})\\ & U_{CN}=\frac{1}{6}U_{ld2}(2S_{C}-S_{A}-S_{B})\end{aligned} \right. \tag{10}\]  
In (10), each phase switch state \(S_{Z}\) (\(Z=A\), \(B\), \(C\)) has three possible values, leading to a total of twenty-seven combinations of three-phase switch states. According to the calculation results of the switching state expression, the output phase voltages of the NPC three-level inverter circuit had a total of nine levels, which were \(-2U_{\text{dc2}}/3\), \(-U_{\text{dc2}}/2\), \(-U_{\text{dc2}}/3\), \(-U_{\text{dc2}}/6\), \(0\), \(U_{\text{dc2}}/6\), \(U_{\text{dc2}}/3\), \(U_{\text{dc2}}/2\), and \(2U_{\text{dc2}}/3\). According to the three-phase voltage expression, further simplification gave the output line voltage of the NPC three-level inverter circuit:  
\[\left\{ \begin{aligned} & U_{AB}=U_{AN}-U_{BN}=\frac{1}{1}U_{ld2}(S_{A}-S_{B})\\ & U_{BC}=U_{BN}-U_{CN}=\frac{1}{2}U_{ld2}(S_{B}-S_{C})\\ & U_{AC}=U_{AN}-U_{CN}=\frac{1}{2}U_{ld2}(S_{A}-S_{C})\end{aligned} \right. \tag{11}\]  
Similarly, each switch state \(S_{Z}\) (\(Z=A\), \(B\), \(C\)) has three possible values in (11), so each expression has nine different combination ways. The calculation results of the switching state expression revealed that the output line voltage of the NPC three-level inverter circuit comprised a total of five distinct levels, which were \(-U_{\text{dc2}}\), \(-U_{\text{dc2}}/2\), \(0\), \(U_{\text{dc2}}/2\), and \(U_{\text{dc2}}\). To validate the accuracy of the theoretical calculations for the output phase voltage and output line voltage levels of the NPC three-level inverter circuit and assess the quality of the output voltage waveforms, a simulation of the NPC three-level inverter output stage was conducted. The parameters of the simulation model are presented in Table 2 below. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameter** & **Value** & **Remark** \\ \hline \(U_{dd2}\) & 1602 V & DC bus voltage \\ \(C_{2}\), \(C_{3}\) & 1120 \(\times 10^{-6}\) F & Capacitance value \\ \(f_{c}\) & 10 kHz & Switching frequency \\ \(L_{4}\) & \(2\times 10^{-3}\) H & Filter inductance value \\ \(C_{4}\) & \(20\times 10^{-6}\) F & Filter capacitance value \\ \(R\) & 100 \(\Omega\) & Load \\ \(m\) & 0.5 & Modulation ratio \\ \(f_{0}\) & 50 Hz & Modulating waveform frequency \\ \(t\) & 0.2 s & Simulation time \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Output stage simulation model parameters. Figure 10: (a) Primary side inverter square wave \(U_{\text{h1}}\) and secondary side inverter square wave \(U_{\text{h2}}\). (b) Intermediate-level output voltage \(U_{\text{dc2}}\). The output phase voltage waveform of the NPC three-level inverter circuit is illustrated in Figure 11a, revealing a nine-step waveform. The partial expansion of the phase voltage indicated that when the DC bus voltage \(U_{\text{dc2}}\) was set to 1602 V, the voltage values of the nine levels were \(-1068\) V, \(-801\) V, \(-534\) V, \(-267\) V, \(0\) V, \(267\) V, \(534\) V, \(801\) V, and \(1068\) V, which align with the theoretical calculations previously discussed. The output line voltage waveform of the NPC three-level inverter circuit is presented in Figure 11b, illustrating a five-step waveform. The partial expansion of the line voltage indicated that when the DC bus voltage \(U_{\text{dc2}}\) was set to 1602 V, the values of the five levels were \(-1602\) V, \(-801\) V, \(0\) V, \(801\) V, and \(1602\) V, which are consistent with the previously discussed theoretical calculations. The midpoint voltage variation of the NPC three-level inverter circuit affected the stability of the output voltage.