## 4 Experiments
### Running-Time Performance  
This subsection first analyzes the operation schedules of the proposed implementation, then evaluate its running-time performance by comparing it with multiple reference implementations. For the purpose of fairness, all the references are implemented in high abstract environments, including Matlab and C++. This allows us to evaluate the implementations within the similar development productivity constraint. The optimizing depth is set as \(D\text{opt}=32\) in order to well balance the hardware consumptions and running time efficiency. For better understanding, the optimized behavior code, Algorithm 4, is divided into the following four scopes to analyze: (a) Scope 1: Line 3, (b) Scope 2: Lines 4-11, (c) Scope 3: Lines 12-17 and (d) Scope 4: Lines 18-24. The four scopes execute in sequence, so the total latency cost \(L_{\text{opt}}\) can be estimated as  
\[L_{\text{opt}}=L_{\text{s1}}+L_{\text{s2}}+L_{\text{s3}}+L_{\text{s4}} \tag{19}\]  
where \(L_{\text{s1}}\), \(L_{\text{s2}}\), \(L_{\text{s3}}\) and \(L_{\text{s4}}\) are the latency costs of the four scopes. According to the scheduling results of Vivado HLS, the first scope includes only two constant data reading accesses (\(B\) and \(ETA\)). The memory access operations cost one cycle and they are parallelly scheduled, so Scope 1 costs one cycle totally. The second scope is a perfect loop nest corresponding to the PLS regression. The scheduling results of the inner loop body is shown in Figure 8, as well as the latency cost of each operator. All the operations are scheduled as indicated in Figure 5. The latency cost of \begin{table}
\begin{tabular}{l l l l l l l l} \hline \hline \multirow{2}{*}{**Instance**} & \multirow{2}{*}{**DSP48E**} & \multirow{2}{*}{**FF**} & \multirow{2}{*}{**LUT**} & \multicolumn{6}{c}{**Quantity**} \\ \cline{5-8}  & & & & \(D_{\text{opt}}=4\) & \(D_{\text{opt}}=8\) & \(D_{\text{opt}}=16\) & \(D_{\text{opt}}=32\) \\ \hline \(fadd\) & 2 & 205 & 390 & 2 & 4 & 8 & 16 \\ \(fmul\) & 3 & 143 & 321 & 4 & 8 & 16 & 32 \\ \(dadd\) & 3 & 445 & 1149 & 1 & 1 & 1 & 1 \\ \(dexp\) & 26 & 1549 & 2599 & 1 & 1 & 1 & 1 \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Instance list. \begin{table}
\begin{tabular}{l l l l l} \hline \hline \multicolumn{1}{c}{**Implementations**} & \multicolumn{1}{c}{**BRAM\_18K**} & \multicolumn{1}{c}{**DSP48E**} & \multicolumn{1}{c}{**FF**} & \multicolumn{1}{c}{**LUT**} \\ \hline \(capt\_\)_phls\_ori & 1(\(\approx\)0\%) & 34(15\%) & 6565(6\%) & 9691(18\%) \\ \(capt\_\)_phls\_opt\_4 & 1(\(\approx\)0\%) & 45(20\%) & 7571(7\%) & 11,130(20\%) \\ \(capt\_\)_phls\_opt\_8 & 1(\(\approx\)0\%) & 61(27\%) & 9004(8\%) & 13,242(23\%) \\ \(capt\_\)_phls\_opt\_16 & 1(\(\approx\)0\%) & 93(42\%) & 11,867(11\%) & 17,456(32\%) \\ \(capt\_\)_phls\_opt\_32 & 1(\(\approx\)0\%) & 157(71\%) & 17,590(16\%) & 25,850(48\%) \\ Available & 280 & 220 & 106,400 & 53,200 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Element utilizations. the loop body is 37 cycles, and that of Scope 2 therefore is \(L_{82}=n\times m\times 37/D_{\mathrm{opt}}+n\times L_{\mathrm{interval}}^{ \mathrm{loop}}=663110\) cycles, where \(L_{\mathrm{interval}}^{\mathrm{loop}}=2\) is the interval latency of the outer loop. The third scope is a dependent loop whose iterations are pipelined. Figure 9 shows the scheduling result of the \(i\)- and \((i+1)\)-th iterations of this scope. The latency cost of a single iteration is \(11\) cycles. Because this is a dependent loop, the iteration interval latency due to the pipelining optimization is \(L_{\mathrm{interval}}^{\mathrm{PIPELINE}}=4\) cycles. Thus, its total latency cost is \(L_{83}=(n-1)\times L_{\mathrm{interval}}^{\mathrm{PIPELINE}}+11=147\) cycles. The fourth scope is a series of operations executing in sequence. They cannot be parallelized due to the data dependencies. As shown in Figure 10, the latency cost of this part is \(L_{84}=62\) cycles.