## 2 Proposed Potentiostat Readout Circuit
In the output stage, the transconductance (\(g_{m}\)) of the PMOS and NMOS can be combined to drive a larger load and can increase the power efficiency by the Monticelli class-AB output stage [14]. In the CMFB circuit, the \(R_{CM}\) and \(C_{CM}\) detect the output common mode voltage. The error amplifier consists of MN20, MN21, MN22, MP20, and MP21, which generate the control voltage \(V_{cmfb}\), which controls the bias current of the cascode stages. By using an error amplifier, common mode feedback is possible without switching noise. The fast CMFB path [15] can provide quick common mode feedback by simultaneously transmitting back through the NMOS (NM11-NM15) and PMOS (PM11-PM15). In addition, for frequency stability, a nested Miller capacitor was added to the CMFB stage and the main amplifier to ensure a stable frequency of the phase margin of 50\({}^{\circ}\). The values of the transistors and passive elements in the FDDA are listed in Tables 1 and 2. Figure 5: Potentiostat readout circuit: (**a**) top architecture and (**b**) FDDA current flow architecture. Figure 6: Schematic of the proposed chopper FDDA. The glucose concentration ranges and the equivalent resistance variation of commercial glucose strips are shown in Table 3[16]. With the resistance according to the glucose concentration of 36-450 mg/dL, it had a value of 250-2250 k\(\Omega\) when using the OneTouch Ultra(r) test strip from Johnson & Johnson. This functionality enabled it to read hypoglycemia with glucose levels lower than the normal range (80-130 mg/dL) or hyperglycemia with blood sugar levels of 180 mg/dL or more. In this paper, as shown in Figure 7, the Verilog-A equivalent voltage-controlled resistor modeling of the glucose sensor and its specifications are similar to the OneTouch Ultra(r) test strip, which was is implemented and simulated. The resistance between the \(RE\) and \(CE\) was modeled as a constant resistor at 10 k\(\Omega\). In this circuit, the \(WE\) and \(RE\) are indirectly biased to 1.2 V and 600 mV, respectively, by the virtual short between each amplifier input node. Figure 8 shows the current and differential output voltage according to the impedance change. The voltage-controlled resistance between the \(WE\) and \(RE\) varied from 250 to 2250 k\(\Omega\), as shown in Figure 7. As the resistance changes, a change in current \(I_{sense}\) occurs. As a result of simulating the resistance range of 250 to 2250 k\(\Omega\), the amount of current (\(I_{sense}\)) was 2.3995 \(\mu\)A (at 250 k\(\Omega\)) and 266.68 nA (at 2250 k\(\Omega\)). The current was converted \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Transistor** & **Size (W/L) (\(\mu\)m)** & **Transistor** & **Size (W/L) (\(\mu\)m)** \\ \hline MP1, MP2 & 60/2.5 & MN1, MN2 & 16/4 \\ \hline MP3–MP6 & 40/0.5 & MN3–MN6 & 40/0.5 \\ \hline MP7, MP8 & 20/2 & MN7, MN8 & 16/4 \\ \hline MP9, MP10 & 160/0.5 & NM9, MN10 & 80/0.5 \\ \hline MP11 & 5/2 & MN11, MN12 & 4/4 \\ \hline MP12 & 50/2 & MN13, MN14 & 20/0.5 \\ \hline MP13, MP14 & 40/0.5 & MN15 & 5/4 \\ \hline MP15 & 200/2 & MN16, MN17 & 5/4 \\ \hline MP16, MP17 & 80/2 & MP18, MP19 & 5/0.5 \\ \hline MP18, MP19 & 10/0.5 & MN20 & 4/2 \\ \hline MP20, MP21 & 12/5 & MN21, MN22 & 40/0.5 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Values of transistors in the proposed FDDA. \begin{table}
\begin{tabular}{c c} \hline \hline
**Component** & **Value** \\ \hline \(C_{F}\) & 4.8 pF \\ \hline \(C_{CM}\) & 412 fF \\ \hline \(R_{CM}\) & 562.615 k\(\Omega\) \\ \hline \(C_{E}\) & 3.2 pF \\ \hline \(R_{E}\) & 1 M\(\Omega\) \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Values of passive components in the FDDA.