# Highly Linear Loaded-Line Phase Shifter Utilizing Impedance Transformer and PIN Diode
## 4 Measurement Results and Discussion  
To demonstrate the effectiveness of the proposed concept, a one-bit loaded-line phase shifter was designed and fabricated with two added stubs. Each stub is grounded through a pair of PIN diodes, enabling controlled switching between phase states. The final dimensions of the circuit were determined using the optimization tools available in Advanced Design System (ADS). The schematic and the fabricated prototype of the one-bit phase shifter are presented in Figure 5. A detailed layout of the implemented switch, including all critical dimensions, is shown in Figure 6, with exact values summarized in Table 1. The design is fabricated on Rogers RO4534 (\(\epsilon_{r}\approx 3.4\), tan\(\delta\approx 0.0027\)) with a thickness of 60 mil (1.524 mm), ensuring both low PIM and stable dielectric performance.  
To evaluate the performance of the proposed design, the phase shift in the proposed structure was both simulated and measured, as shown in Figure 7. The target phase shift of 45 degrees was successfully achieved, as confirmed by both simulation and measurement results. Additionally, the return loss (S\({}_{11}\)) and insertion loss (S\({}_{21}\)) were analyzed for both switching states of the PIN diodes. The corresponding simulated and measured results are presented in Figure 8 for the OFF state and Figure 9 for the ON state.  
Figure 4: Highly linear loaded-line phase shifter with coupler impedance transformer.  
Figure 5: One-bit loaded-line phase shifter with enhanced linearity.  
Figure 6: Dimensions of the proposed design.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameter** & **Value (mm)** & **Parameter** & **Value (mm)** \\ \hline W1 & 1.75 & W2 & 7.2 \\ \hline L1 & 5.1 & L2 & 23.5 \\ \hline W3 & 0.8 & S & 0.2 \\ \hline W4 & 1.8 & L3 & 8.1 \\ \hline W5 & 5 & L4 & 24.1 \\ \hline W6 & 12.8 & L5 & 10.3 \\ \hline W7 & 17.3 & L6 & 10.3 \\ \hline W8 & 14 & L7 & 3.5 \\ \hline W9 & 21.3 & L8 & 11.3 \\ \hline W10 & 23 & L9 & 6.1 \\ \hline W11 & 20.35 & L10 & 6.1 \\ \hline W12 & 16 & L11 & 6.8 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Dimensions of the proposed design.  
Figure 8: Measured and simulated IL and RL of the new phase shifter with PIN diodes in the OFF-state.  
Figure 7: Measured and simulated phase shift.  
The provided results of the S-parameters show a discrepancy between simulation and measurement. During standalone measurements of the PIN diodes on a simple 50 \(\Omega\) microstrip line, we observed that different samples of the same PIN diode model exhibited slight variations in their parasitic parameters. On the other hand, slight variations in the parasitic elements of different PIN diode samples become more pronounced in our design due to the intentionally reduced impedance seen by the diodes. This effect partly explains the minor discrepancies observed between simulations and measurements.  
The linearity performance of the proposed design was evaluated under three different scenarios: (i) without PIN diodes, (ii) with PIN diodes in the ON state, and (iii) with PIN diodes in the OFF state. The corresponding simulated and measured results are presented in Figure 10. All IIP3 measurements were conducted at an input power level of 25 W.  
In the first scenario, the structure without PIN diodes exhibited a measured IIP3 of 106 dBm, primarily limited by the measurement setup. With the PIN diodes in the ON state, the simulated IIP3 was 108 dBm, while the measured value was 106 dBm--again constrained by the linearity of the test equipment. When the PIN diodes were in the OFF state, the simulated IIP3 was 101 dBm, and the measured result was 100 dBm, demonstrating  
Figure 10: Measured and simulated IIP3 of the new phase shifter with and without PIN diodes.  
Figure 9: Measured and simulated IL and RL of the new phase shifter with PIN diodes in the ON-state.  
strong agreement with simulation and confirming the effectiveness of the impedance-transformed parallel topology in improving linearity.