# Design and Simulation of Low-Orbit Satellite Broadcast Signal Receiving and Processing Terminal
## 3 Key Technologies
### Overall Machine Design  
As introduced before, according to the independence of functions of each part in the low-orbit satellite signal on-board and ground data processing processes, the system can be divided into four parts: antenna array, radio frequency unit, baseband processing board, and application processing terminal. Among them, the antenna array consists of 31 identical antenna elements. The antenna elements adopt a circular polarization method and support receiving left-hand circular polarization and right-hand circular polarization signals at the same time. The left-hand and right-hand circular polarization signals are filtered separately. After amplification, the combined signal is transmitted to the RF local oscillator board through the RF cable. The left-hand RF frequency point, which is 2860 MHz, has a close frequency with the right-hand RF frequency point, which is 2074 MHz, so the left-hand channel and the right-hand channel adopt the same design [57]. The left-handed signal is mixed in the form of LO-RF, and the right-handed signal is mixed in the form of RF-LO, which widens the frequency spacing of the left/right-hand local oscillators. The left-handed local oscillator frequency is designed to be 2860 MHz, and the corresponding left-handed intermediate frequency is 376-480 MHz, which is located in the second Nyquist zone of the ADC. The right-handed local oscillator frequency is designed to be 2074 MHz, and the corresponding right-handed intermediate frequency is 126-230 MHz, which is located in the first Nyquist zone of the ADC. Figure 12 shows the spectrum after mixing. The left/right-handed local oscillator will leak, resulting in mutual modulation. The modulated signal is 786 MHz, which can be filtered out using a low-order low-pass filter. After the intermediate frequency signal obtained after mixing is sampled by the ADC, the  
Figure 11: Decoding module flow chart. Figure 12: The spectrum after mixing. spectrum of the second Nyquist zone will be moved to the first Nyquist zone. Figure 13 shows the spectrum after ADC sampling. As can be seen from Figure 1, the sampled signal does not undergo aliasing, so it will not cause a loss in signal-to-noise ratio. The RF unit mainly consists of three circuits, namely a down-conversion and intermediate frequency amplification circuit, a local oscillator generation circuit, and a power supply circuit [44]. There are 32 down-conversion channels, corresponding to 31 antenna array elements, and the remaining 1 down-conversion channel is reserved; the baseband processing board is mainly responsible for processing the 200 MHz bandwidth intermediate frequency signal transmitted from the down-conversion board, and after AD conversion, each signal is sent to the FPGA for beamforming separately and then sent to the subsequent SoC for signal demodulation and decoding, the SoC uses the Zynq 7030 chip. The schematic diagram of data flow is shown in Figure 14. The decoded baseband data are sent to the host computer through 1 Gigabit Ethernet. The data processing terminal, that is, the host computer, is mainly responsible for receiving target detection data, radar and communication data, image slices, vector data, digital elevation maps, and satellite real-time orbit data, in the meantime issuing control and management instructions to the receiver, and interact with receiver [44]. The SoC baseband board mainly implements digital beam synthesis, anti-interference processing, signal acquisition, tracking, and decoding, and uses a board-to-board high  
Figure 14: Schematic diagram of data flow between FPGA and SoC on the baseband processing board. Figure 13: The spectrum after ADC sampling. speed connector to connect the baseband board and the multi-channel down-conversion board. The 32 channels of intermediate frequency signals are sent to the 32 channels of ADC for analog-to-digital conversion, and then the digital signals are sent to the beam steering FPGA.