# Fabrication Tolerances' Impact on an ODAC-Based PAM-4 Transmitter
## 1 Introduction  
The intense demand for high-capacity networks, driven by novel applications such as 4K/8K video streaming, 5G mobile networks, the Internet of Things (IoTs), and cloud networking has put pressure on the need for an upgrade of bandwidth-limited optoelectronic components [1]. Hence, PIC pledge to unlock higher-capacity transceivers while minimizing their losses, footprint and power consumption. As PIC maturity continues to increase, leading to wide acceptability in industries and commercial applications, the complexity of PIC has also increased due to the large number of components on a single chip [2, 3]. Examples with more than 1500 components on a single chip have been achieved and more are expected [2]. The success of PIC can be attributed to the possibility of the large-scale production of Silicon Photonics (SiP) at a reduced footprint, low component-to-component losses, low power consumption and low overall packaging cost [4]. This has allowed PIC to be used in application specific photonic integrated circuits (ASPIC), which play a role in data/ telecommunications, medical applications and bio sensing and, even more recently, in transportation applications such as LIDAR [5, 6]. Such application-specific designs require painstaking efforts, a long time and high cost to achieve results and their design cannot be transformed or used for other applications except the specific purposes they are designed for [7]. In some cases, the design may fail to meet the initial objective, which implies that the process has to be repeated and the cost of production will be increased [7]. Several factors are responsible for chip failure in SiP devices, often due to their small features of sub-micron size, which can lead to a significant performance mismatch between the supposed designed model and the actual device obtained after fabrication [8]. These factors can be categorized as fabrication variation, operational variation, system variation,random variation and high material index contrast [9; 10]. Errors arising from these variations can constitute challenges in the overall chip performance, resulting in a reduced yield in mass productions of such PIC devices after fabrication. In addition, since light is highly sensitive to slight deviation, the inaccurate estimation of passive device properties such as the waveguide height, sidewall angle and width of directional coupler can adversely alter the path of the signal, leading to coupling mismatch [11; 12]. Also, the device's position in the die in mass production and the number of repeated runs of PIC devices in a given die can also slightly vary the behaviour of each of the devices in the entire die [9; 13]. Such variations may result from ageing due to the wear and tear of lithography equipment, lithography exposure dose and chemical/mechanical polishing [9]. Several studies have been carried out in the past on the fabrication tolerances of PIC devices. [PERSON] et al. in [13] studied the linear correlation between similar components fabricated on the same chip and the variability in their wavelength mismatch. This study tried to establish how this variability can impact devices that are highly wavelength-dependent such as ring resonator modulators and optical filters in a wavelength division multiplexing (WDM) system. Therefore, several identical resonators on a 16 \(\times\) 9 mm chip were fabricated. The results established a linear relationship between the resonator wavelength deviation and distance between two identical resonators on the chip with a maximum of a 4 nm wavelength mismatch between two resonators that are 1 nm apart. Similar work in [14] presented an analytical model to study the impact of wavelength mismatches among different devices on chips due to fabrication process variation on passive Silicon Photonic devices both at the component and device levels.