# Towards Large-Scale Fast Reprogramable SOA-Based Photonic Integrated Switch Circuits
## 3 InP SOA-Based Broadband Switch Matrices  
Broadband switches are expected to enable considerable energy savings with respect to electronic switching as the line-rate increases, as the data throughput is not directly linked to the actuation energy [28]. So far, the highest connectivity SOA-gate based circuit has been a three-stage 16 \(\times\) 16 switch with a hybrid Clos-Tree structure [23]. A single active epitaxy was used to enable loss-less on-chip operation and 10 Gb/s routing between selected paths. The use of active waveguides for every component within the chip requires significant levels of current injection to overcome loss, and this in turn leads to a building up in spontaneous emission noise and a compromised optical signal to noise ratio (OSNR) of 14.5 dB/0.1 nm. In [24], we reported the first 16 \(\times\) 16 switch on a re-grown active-passive epitaxial wafer: The sparse use of SOA gain elements and low loss passive waveguide components is anticipated to allow reduced signal impairment through lower levels of amplified spontaneous emission (ASE) and distortion. Figure 1a shows the three-stage hybrid Benes-Tree architecture as implemented with 2 \(\times\) 2, 4 \(\times\) 4, and 2 \(\times\) 2 switches at the input, center, and output stages, respectively. The first and the last stage of SOAs are used as pre-amplifiers and booster amplifiers, respectively. The center stage enables path fast reconfigurability and is replicated in two planes to allow re-arrangeable non-blocking interconnection. The active SOA gates are integrated with the passive broadcast and waveguide routing circuits by \begin{table}
\begin{tabular}{c c c c c} \hline \hline  & **Input Ports \(\times\) Output Ports** & **Wavelength Paths** & **Connectivity** & **Ref.** \\ \hline SOA-based space & 16 \(\times\) 16 & 1 & 16 & [23] \\ switches & 16 \(\times\) 16 & 1 & 16 & [24] \\ \hline SOA- and & 4 \(\times\) 4 & 4 & 16 & [25] \\ AWG-based & 4 \(\times\) 16 & 4 & 16 & [26] \\ cross-connects & 8 \(\times\) 8 & 8 & 64 & [27] \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Connectivity in fast optical switch matrices for Mach-Zehnder interferometers (MZI) and semiconductor optical amplifier (SOA) gate switch matrices. AWG: arrayed waveguide grating. using an active-passive epitaxial regrown InP/InGaAsP (Indium Gallium Arsenide Phosphide) wafer The switch comprises 192,500 \(\upmu\)m long SOA gates distributed in six columns and a comparable number of splitters, combiners, and waveguide crossings within a chip area of 4.0 mm \(\times\) 13.2 mm, for a record number of 480 components on a single photonic chip [7]. To create the photonic waveguide wiring, a four-step inductively coupled plasma (ICP) etch was performed. While the central SOA electrodes are connected to fast programmable drivers for path reconfiguration, the remaining connections at the inputs and at the outputs are made via electrical patch panels to arrays of modular direct current (DC) sources. Both single and multi-path operation are assessed [29]. Polarization controllers are used as the circuit is optimized for transverse electric (TE) polarization. Initial characterization is performed to study the component level and path level operation [24]: All quoted on-chip losses come from in-situ measurements. Only thirty-two paths have been tested, due to the chip complexity: the paths from input 1 to output 1 to 32, and paths from input 32 to output 1 to 32--these paths include the shortest and the longest paths of the chip for full loss map understanding. Path yield numbers are reported in the next section for a similar area chip, fabricated on the same wafer. The use of low-loss passive waveguides in combination with high-contrast active gates leads to promising system level metrics in terms of optical signal to noise ratio with a best case value of 28 dB/0.1 nm.