# An Embedded Sensor Node Microcontroller with Crypto-Processors
## 4 Implementation and Verification
### Power and Performance  
The power dissipation of the TNODE5 design was estimated in the layout-phase and measured on the fabricated chip. The post-layout power estimation is performed with the Encounter Power System tool that is a part of the Cadence Encounter design toolset. The power estimation is done for typical operating conditions (T = 25 \({}^{\circ}\)C, V\({}_{\mathrm{core}}\) = 2.5 V, V\({}_{\mathrm{pad}}\) = 3.3 V) and for an operating frequency of 1 MHz. The dynamic power was estimated by using the activity data extracted from the post-layout simulations. Furthermore, the power dissipation was estimated for different crypto operations executed by the integrated crypto accelerators. In addition, the power dissipation is estimated during the data transmission and reception by the integrated baseband core. Finally, the power consumption during an SPI data exchange was estimated. During all tests the ADC and the Flash were active and had constant power consumption. The results of power estimation are summarized in Table 4.  
The power estimation results show that the ADC and the Flash consume 13.6 mW, which is much more than the chip logic. The ADC supports a standby mode where its power consumption drops to  
Figure 5: TNODE5 testbench: (**1**) Test execution from Flash; (**2**) Test execution via \(\mathrm{I^{2}C}\) debug port. several \(\mu\)W. The Flash component must be active as long as the processor is reading data from it. If it is not selected, the Flash component enters the standby mode automatically. As expected, the maximum power consumption in the chip logic was estimated for the ECC operations, which corresponds to the occupied cell area. The early power estimation on the fabricated chips was performed during the production tests. The TNODE5 chip includes dedicated power supplies for the core (VDDCORE), pads (VDDPAD), and analog and mixed signal parts of ADC (VDDA and VDDM). The VDDCORE source supplies the standard logic cells, Flash, and digital parts of the ADC and pads. Therefore, it was not possible to measure the power dissipation of the ADC and Flash separately. Measurement results of the node's average power dissipation for several production tests are given in Table 5. The power dissipation is estimated by measuring the current of each power source separately at the nominal supply voltage (VDDCORE = 2.5 V, VDDA = VDDM = 2.5 V, VDDPAD = 3.3 V). The operating frequency was fixed at 1 MHz. The results in Table 5 present the average power dissipation extracted from the measurements of 51 randomly selected chips. The results show a good correlation with the estimated power dissipation. The highest power dissipation of the VDDCORE source was measured during crypto tests. The power dissipated at pads is higher during the SPI and baseband tests, which correlates to the higher activity on external ports during these tests. In addition, the power of three randomly selected chips was measured at an operating frequency of 10 MHz. The results are summarized in Table 6.  
The estimated power consumption of TNODE5 is fairly high when compared to commercially available state-of-the-art TI MSP430 processors that consume up to 1 mW @ 1 MHz. However, one has to consider that the TNODE5 was fabricated in a mature 250 nm technology process with limited \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Test @ 10 MHz** & **PVDDCORE (mW)** & **PVDDPAD (mW)** & **PVDDA (mW)** & **PVDDM (mW)** & **PTotal (mW)** \\ \hline Rx & 13.5437 & 3.3492 & 1.0595 & 2.2430 & 20.1954 \\ Tx & 13.8279 & 3.2426 & 1.0635 & 2.2525 & 20.3865 \\ Crypto & 26.582 & 3.3108 & 1.0602 & 2.1442 & 33.0972 \\ SPI & 14.0432 & 4.6625 & 1.0572 & 2.2842 & 22.0471 \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Post-production power measurements of TNODE5 chip at a frequency of 1 MHz.