## 6 Experimental Results  
As a basis for comparing the efficiency of different synthesis methods, we use the benchmark FSMs from the library [42]. The library includes 48 benchmarks of varying complexity (numbers of states, inputs, outputs, output collections, and interstate transitions). The STTs of benchmark FSMs are represented using the format KISS2. These benchmarks have been used by different designers as a representative sample to compare the main characteristics of proposed and known FSM circuits [33; 34; 36]. To give an idea of the complexity of these benchmarks, we show their characteristics in [19; 42]. As a rule, in research, FSMs are considered as stand-alone units. In this case, the stability of the output signals is not one of the main design problems. However, in our current paper, we consider Mealy FSMs as some parts of digital systems. As follows, for example, from [14], Mealy FSMs are unstable. This means that input fluctuations result in output fluctuations. The output fluctuations can cause operation failure in a digital system. Output stabilization can be achieved due to using a synchronous input register (AIR) [19]. The following is a principle of interaction of an FSM and other digital system blocks (Figure 11). The system outputs are treated as FSM inputs forming the set \(I\). As long as there are transients in the digital system, the synchronization signal _Clk1_ is equal to zero. This actually disconnects the FSM from other system blocks. When system outputs are stable, they are loaded into the AIR. Due to this, fluctuations in the system outputs do not affect the FSM output values. Of course, there is some overhead connected with this approach. Obviously, AIR consumes additional resources of the FPGA fabric. It also consumes some additional power and increases the value of FSM cycle time. Therefore, we took into account this overhead in our research. Figure 11: Interaction of FSM with other system blocks. In experiments, we use the Virtex-7 VC709 Evaluation Platform (xc7 vx690 ffg1761-2) [38]. Its FPGA chip xc7 vx690 ffg1761-2, produced by AMD Xilinx, is a base for implementing FSM circuits. For LUTs of this chip, there is \(S_{L}=6\). The step of technology mapping is executed by the CAD tool Vivado v2019.1 (64-bit) [47]. To create tables with experimental results, we use data from the reports produced by Vivado. The VHDL-based FSM models are used to connect the benchmarks with Vivado. We use the CAD tool K2F [10] to create VHDL codes corresponding to initial KISS2-based benchmark files. From the Vivado reports, we have derived the following characteristics of \(P_{2T}Y\) Mealy FSM circuits: the number of LUTs (LUT count), value of cycle time, maximum operating frequency, and power consumption. As a basis for comparison, we have chosen four different FSMs. They are the following: 1. \(P\) Mealy FSMs with MBCs produced by the Auto method of Vivado; 2. \(P\) Mealy FSMs with one-hot state codes produced by the One-Hot method of Vivado; 3. JEDI-based \(P\) Mealy FSMs; and 4. \(P_{T}Y\)-based FSMs with twofold state assignment [20]. We did not compare \(P_{2T}Y\) and \(PY\) Mealy FSMs. This is because \(P_{T}Y\) FSMs have better characteristics than equivalent \(PY\) Mealy FSMs [20]. Therefore, if the proposed approach allows for improving characteristics compared to \(P_{T}Y\), then the results obtained will obviously be better than the results for equivalent \(PY\) Mealy FSMs. As follows from [19; 42], the values of LUT counts and other LUT-based FSM circuits' characteristics strongly depend on the relation between the values of \(L+R1\) and \(S_{L}\). In the discussed case, there is \(S_{L}=6\). The benchmarks used have 5 complexity levels (C0-C4). These levels are determined in the following order. The benchmarks have the level C0 if \(R1+L\leq 6\). The level C0 determines trivial FSMs. The benchmarks have the level C1 if \(6<R1+L\leq 12\). The level C1 determines simple FSMs. The benchmarks have the level C2 if \(12<R1+L\leq 18\). The level C2 determines average FSMs.