# A Novel ASIC Implementation of Two-Dimensional Image Compression Using Improved B.G. Lee Algorithm
## 3 ASIC Implementation of 2D DCT/IDCT Based on B.G Lee DCT Algorithm
### Architectural Design for [PERSON] DCT Algorithm
The pipelined architecture that performs 2D DCT using the separability property by performing 1D DCT on the rows of each 8 \(\times\) 8 image segment and on the columns is illustrated in Figure 9. The hardware architecture designed to perform 1D IDCT on the rows and columns of each 8 \(\times\) 8 image segment is the same and has been reused. A 256 \(\times\) 256 image is divided into smaller blocks of size 8 \(\times\) 8. Each 8 \(\times\) 8 image block comprises 64 pixels, containing eight rows and eight columns. All of the pixels are stored in the generated memory. Each row of image pixels of the first 8 \(\times\) 8 block is given as input to compute the 1D DCT and then each row is output per cycle after the transformation. Eight clock cycles are needed to compute the 1D DCT of the eight rows of each 8 \(\times\) 8 image block. The bit widths of the digital input and output data of the eight-point DCT and IDCT with respect to the eight-stage pipeline architecture of Figures 7 and 8 are tabulated in Table 4. The data range of the input image is \(-\)255 to 255 and the bit width is 9 bits for the first 1D DCT, where the sign bit is represented by the 9 th bit. The width of the output obtained from the first 1D DCT is 17 bits. After eight clock cycles, the transpose of the transformed coefficients is taken. The transpose of the transformed coefficients is obtained in the 9 th clock cycle. The columns of the transposed image is then subjected to 1D DCT. The input and output bit width of the data for the second 1D DCT is 17 bits. The computation of the 1D DCT on the resultant 8 \(\times\) 8 image block requires 8 clock cycles. Once the 1D DCT is carried out, the 8 \(\times\) 8 image blocks are ready for the IDCT transformation to recover the original image. The input and output bit width for the first 1D IDCT is 17 bits. In the next 8 clock cycles, the 1D IDCT is performed on the rows of the transformed image segment. The transpose of the resultant matrix is taken in the 9 th clock cycle. Eight clocks are required to perform 1D IDCT on the columns of the resultant image segment to obtain the reconstructed image. The input bit width of the final 1D IDCT is 17 bits and the output bit width is 9 bits. Each 8 \(\times\) 8 image block takes 34 clock cycles for the DCT and IDCT computation. The DCT algorithm is made more efficient by the integration of pipelining. The incorporation of error-tolerant adders in the butterfly diagram computations, the utilization of the proposed low-power fixed point multipliers and shifters for the multiplications involved, along with the application of pipelining with the efficient row-column architectural design makes the [PERSON] algorithm implementation efficient in terms of power and computational efficiency. The 2D DCT/IDCT of each 8 \(\times\) 8 image segment can be quickly processed in 34 clock cycles with a substantially reduced level of circuit complexity. \begin{table}
\begin{tabular}{c c c} \hline \hline
**1D DCT/IDCT** & **Input Bit Width** & **Output Bit Width** \\ \hline
1D DCT (Row) & 9 bits & 17 bits \\
1D DCT (Column) & 17 bits & 17 bits \\
1D IDCT (Row) & 17 bits & 17 bits \\
1D IDCT (Column) & 17 bits & 9 bits \\ \hline \hline \end{tabular}
\end{table} 
Table 4: DCT/IDCT data bit widths. Figure 9: Pipelined architecture of 8 \(\times\) 8 DCT-IDCT.