# A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures
## 3 Classical Method to Design LBIST Circuits with the STUMPS Architecture  
The previous chapter outlines reasons that prevent us from achieving high coverage of faults in CUTs that are provided with LBIST circuits with the STUMPS architecture. These problems stem from the low phase shift between binary sequences appearing at outputs of pseudo-random TPGs that are designed exclusively on the basis of a conventional LFSR structure associated with a primitive polynomial. This is why a phase shifter [3] (pp. 184-188), [54] is usually inserted between outputs of the LFSR [34; 35; 36; 37; 55] or LHCA 90/150 [12; 37; 39; 55; 56] and serial inputs of scan paths incorporated into the CUT. Such a modified STUMPS architecture is shown in Figure 6. In a later part of this study, the TPG provided with a phase shifter at its outputs shall be referred to as a test pattern generator based on LFSR or CA with Phase Shifter at the outputs and designated as LFSR + PS and CA + PS, respectively. The phase shifter itself is a network of XOR gates appropriately wired to outputs of the LFSR or CA register. Its application not only makes it possible to provide sufficient phase shift between binary sequences supplied to serial inputs of scan paths but also enables incorporation of LFSR structures of much lower size than the number of scan paths (\(n~{}\ll~{}m\) in Figure 6). For instance, in [34], the authors used LFSR registers with lengths of 24, 32, 48, 64, 80, 96, and 128 bits to produce test sequences supplied then to multiple scan paths, where the number of scan paths fed from a single TPG ranged from several dozens to more than 8000. However, the use of a phase shifter inevitably entails a delay introduced into the hardware, which is a drawback of the proposed solution. The time of signal propagation throughout the phase shifter is several times longer than the propagation time of multiplexers incorporated into scan path cells [34], and, in addition, that time is added to the propagation time of the multiplexer embedded into the first cell of a scan path. These two factors restrict the maximum operation frequency of the test facilities made up of TPG and scan paths. It eventually leads to an extended total time of test execution. In addition, when a single LFSR feeds a plurality of scan paths, things get worse due to the need to route interconnections within a sophisticated network of XOR gates incorporated into a phase shifter. Typically, the desired fan-out factor is achieved by incorporation of additional buffers (logic amplifiers) wired to the flip-flops' outputs of the LFSR and to some XOR gates outputs of the phase shifter. These two factors lead to further growth of propagation time for signals passing the phase shifter and make the engineering process for test pattern generators much more complicated. The studies referenced disclose several methods to design phase shifters with the aim to ensure the assumed value of the phase shift between output data channels. Some of these methods are based on operations on digital matrices that describe structures of linear registers and phase shifters connected to the LFSR or CA outputs [37, 57]. Other solutions employ simulation of a linear register operation, where the simulated linear register structure reflects the layout of an original linear register combined with a phase shifter. However, it is an approach that may prove time-consuming in the case of long linear registers [34, 35, 36, 39, 56]. Additionally, other methods have been developed intending to find out such structures of both an LFSR register and a phase shifter that are capable of generating the desired set of deterministic test vectors [22, 58].