## Appendix B  
**Example A2**. : _In Example A2, the set \(J=\{I_{1},J_{2},J_{3},J_{4},J_{5}\}\) of jobs is the same as in Example 1 and Example A1. The set of processors is increased from four processors in Examples 1 and Example A1 to nine processors in Example A2: \(M=\{M_{1},M_{2},\ldots,M_{9}\}\)._  
The processor \(M_{1}\) processes the operations \(V_{1}=\{v_{1},v_{7}\}\). In Figure A2, the forbidance to process the operations from the set \(V_{1}\) simultaneously on the processor \(M_{1}\) is determined by the edge \([v_{1},v_{7}]\) in the graph \((V,\varnothing,E)\). The processor \(M_{2}\) processes the operations \(V_{2}=\{v_{2},v_{4}\}\). The forbidance to process the operations from the set \(V_{2}\) simultaneously on the processor \(M_{2}\) is determined by the edge \([v_{2},v_{4}]\). Similarly, the forbidance to process operations from the set \(V_{3}=\{v_{3},v_{9}\}\) simultaneously on the processor \(M_{3}\) is determined by the edge \([v_{3},v_{9}]\). The forbidance to process this pair of operations from the set \(V_{4}=\{v_{6},v_{12}\}\) simultaneously on the processor \(M_{4}\) is determined by the edge \([v_{6},v_{12}]\) in the graph \((V,\varnothing,E)\). The forbidance to process operations from the set \(V_{5}=\{v_{5},v_{11}\}\) simultaneously on the processor \(M_{5}\) is determined by the edge \([v_{5},v_{11}]\). The forbidance to process the operations from the set \(V_{6}=\{v_{8},v_{12}\}\) simultaneously on the processor \(M_{6}\) is determined by the edge \([v_{8},v_{12}]\). The forbidance to process operations from the set \(V_{7}=\{v_{7},v_{10}\}\) simultaneously on the processor \(M_{7}\) is determined by the edge \([v_{7},v_{10}]\). The forbidance to process the operations from the set \(V_{8}=\{v_{9},v_{11}\}\) simultaneously is determined by the edge \([v_{9},v_{11}]\). The forbidance to process the operations from the set \(V_{9}=\{v_{3},v_{4}\}\) simultaneously on processor \(M_{9}\) is determined by the edge \([v_{3},v_{4}]\). The processors, which are used to process the operation \(v_{i}\in V\), are presented near the vertex \(v_{i}\) in Figure A2. The precedence constraints established between operations of different jobs are given as follows: \(v_{1}\Rightarrow v_{4}\); \(v_{1}\Rightarrow v_{8}\); \(v_{3}\Rightarrow v_{1}\); \(v_{8}\Rightarrow v_{3}\); \(v_{6}\Rightarrow v_{10}\); \(v_{10}\Rightarrow v_{12}\); \(v_{8}\to v_{4}\); \(v_{11}\to v_{8}\). These precedence constraints are represented by seven arcs \(\{(v_{1},v_{4}),\ (v_{1},v_{8}),(v_{3},v_{1}),\ (v_{8},v_{3}),(v_{6},v_{10}),\ (v_{10},v_{12}),(v_{8},v_{4})\}\subset A\) and two edges \(\{[v_{4},v_{8}],[v_{8},v_{11}]\}\subset E\). The digraph \((V,A,\varnothing)\) has one circuit \((v_{1},v_{8},v_{3},v_{1})\) and this circuit has no adjacent vertices in the graph \((V,\varnothing,E)\). Since the digraph \((V,A,\varnothing)\) has no circuit with adjacent vertices in the graph \((V,\varnothing,E)\), there exists a schedule for Example A2 of the general unit-time problem \(G_{c}MPT|t_{i}=1|C_{\max}\) that is completely determined by the mixed graph \(G\); see Theorem 4. We construct the following colouring \(c(G)\) of the mixed graph \(G=(V,A,E)\): \(c(v_{1})=2\), \(c(v_{2})=1\), \(c(v_{3})=2\), \(c(v_{4})=3\), \(c(v_{5})=4\), \(c(v_{6})=5\), \(c(v_{7})=6\), \(c(v_{8})=2\), \(c(v_{9})=3\), \(c(v_{10})=5\), \(c(v_{11})=1\), \(c(v_{12 By Theorem 5, the equality \(\chi(G)=6=C_{\max}(S)\) must hold. Note that Theorem 5 is only valid for colourable mixed graphs. For example, if the precedence constraint \(v_{12}\Rightarrow v_{9}\) is added to the input data of Example A2, we obtain the following mixed graph: \(G^{+}=(V,A\cup\{(v_{12},v_{9})\},E)\). The obtained mixed graph becomes un-colourable due to the existence of a circuit \((v_{12},v_{9},v_{10},v_{12})\) such that the vertices \(v_{9}\) and \(v_{10}\) are adjacent in the graph \((V,\varnothing,E)\), which is a subgraph of the mixed graph \(G^{+}=(V,A\cup\{(v_{12},v_{9})\},E)\); see Theorem 1.