# Scan Matching by Cross-Correlation and Differential Evolution
## 3 Background
### Experimental Setup and Embedded Data Processing  
The aim of this work is the design of a localization algorithm suitable for an autonomous mobile vehicle, for example a wheeled mini robot for exploration, surveillance and rescue operations. Hardware architecture of such vehicle was described, for example, in [46]. The mechanical construction of the vehicle was based on the RC Baja 5B SS chassis and it was equipped with all necessary electronic devices that allowed the control of its movement. The vehicle was also equipped with the SICK LMS 100 LiDAR and a set of odometry sensors.  
A novel algorithm for a specific system or device ought to be validated in terms of correctness, accuracy, reliability and robustness. In order to allow rapid prototyping and evaluation of various approaches, a model-based development using a software simulation of particular system components (i.e., Software in the Loop) was adopted to validate the scan matching algorithm. The simulation framework provides information about the true position and orientation of the device, simulates its movement in a pre-defined indoor environment and produces simulated LiDAR and odometry data. The structure of the environment is defined by a floor plan. The target processor is an Advanced RISC Machine (ARM) Cortex-M microcontroller expected to run the scan matching algorithm and to compute the estimated position and orientation of the device in the real device. This top-level design strategy is visually illustrated in Figure 1.  
An ARM Cortex-M processor supports different functionality depending on its version. Table 1 describes the basic features of several recent ARM Cortex-M versions (M0+, M3, M4 and M7) [47]. In general, the proposed approach makes use of summation, multiplication and division operations that can be implemented as integer or floating-point operations.  
Figure 1: An outline of the simulation-based design.  
The performance of a processor can be assessed from three different perspectives. An ARM Cortex-M processor can implement the von Neumann or the Harvard architecture. The Harvard architecture has a separate instruction bus connected to an internal cross-bar bus. It supports hardware parallelism by allowing simultaneous access to instructions and data. The second important property of the implemented architecture is the number of stages in the instruction pipeline. A higher number of pipeline stages can accelerate instruction execution and increase the computational power of a processor. For integer operations, the processor implements an add instruction as a standard functionality of an arithmetic logic unit (ALU). However, multiply, divide and digital signal processing (DSP) instructions are optional. ARM Cortex-M family processors can be equipped with slow (32 cycles) or fast (1 cycle) multiply instructions, 32-bit divide instructions and digital signal processing instructions (e.g., a multiply-accumulate operation) useful for input signal filtering. If the executed algorithm uses floating-point data types, then the presence of a floating-point unit (FPU) is highly recommended due to the long processing times without this mathematical co-processor. An FPU can be realized in the processor core as a single (32-bit) or a double (64-bit) precision version of a mathematical co-processor.  
The selection of a suitable processor core version depends not only on data-type implementation but there are several important algorithm parameters including the resolution of input data, grid map cell size and the type and configuration of the optimization procedure.