# Method to Predict Performances of PCB Silicone Conformal Coating under Thermal Aging
## 3 Results
### D FEA Modeling of the Stress Distribution for the Case with Chip Attached to the PCB  
When restricting the study to lateral tension stress component criteria, the simple bi-layer geometry studied before is less severe than that observed in conformal coating applications. Chips attached to the PCB and covered by the coating likely create local high-stress values. For this reason, a more complex geometry (Figure 14) is studied using a 2D FEA model.  
Because of the presence of the chip, new zones of high stress are expected at the junction between the PCB and the chip or the upper left and right corners of the chip. Therefore, a new mesh study is required to test the stability of the solution in the vicinity of the chip. Rounded corners are used for the coating covering the corners of the chips to consider either coating accumulation at the lower edges, close to the PCB, and thinner coating at the upper left and right corners of the chip. The control physics default mesh of COMSOL was used for meshing, which is based on a triangular element with a quadratic Lagrange shape function. The spatial stress distribution building in coating A when exposed to a temperature of 125 \({}^{\circ}\)C was calculated by varying the mesh density. We looked at the stress close to the lower edge of the chip because it is where larger stress builds up because of the presence of two orthogonal adhesion interfaces. The evolution of stress in the function of the number of triangular elements is summarized in Table 6, showing the rather stable mesh insensitive solution is obtained for 1748 elements.  
To provide a more accurate local stress estimate, the linear elastic assumption is removed, selecting a Neo-Hookean nonlinear model that provides a better fit of the experimental stress-strain curve for larger strain values. The Neo-Hookean model shows that its nonlinear behavior is fully defined by [PERSON]'s modulus calculated in the linear part of the measured stress-strain curve, corresponding to low strain values. The Lame parameters inputs to COMSOL are calculated using [PERSON]'s modulus and [PERSON]'s ratio. Material parameters are summarized in Table 7. Table 8 shows chip and PCB material properties used in FEA simulation. The chips are usually packaged by an epoxy molding compound; therefore, epoxy resin properties were selected for FEA simulation. While a Neo Hookean  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Number of Triangular Elements** & **Number of Cell’s Vertices** &
\begin{tabular}{c} **Maximum Von Mises Stress (MPa)** \\ \end{tabular} \\ \hline
914 & 523 & 0.15 \\
1196 & 670 & 0.19 \\
1748 & 960 & 0.21 \\
3024 & 1627 & 0.21 \\ \hline \hline \end{tabular}
\end{table}
Table 6: Evolution of the maximum value of Von Mises stress near the chip edge in contact with the PCB.  
Figure 14: Geometry of 2D FEA modeling of chip attached to PCB; x, y units are in mm.  
at rupture, while the safety margin concerning rupture is large at 125 \({}^{\circ}\)C (1.4%). In terms of coating suitability for conformal coating application, we have similar conclusions to those obtained using simpler bi-layer geometry: high temperature leads to a low local stress value compared to the value at rupture, while potential failure is possible at low temperature. The presence of the chip makes the local stress value almost equal to the threshold of stress rupture, with a high potential risk of crack initiation with time. For conformal coating B, the max. local stress value near the chip is 0.16 MPa at \(-\)40 \({}^{\circ}\)C and 0.44 MPa at 125 \({}^{\circ}\)C, respectively. As predicted by the simplified approach, the issue now is at high temperatures, for which we have higher stress. Because the max. local stress value remains below 13% of the stress leading to rupture, the risk of potential crack stays low.