# A Review of Cell Operation Algorithm for 3D NAND Flash Memory
## 2 Program Algorithm
### Cell Variation Improvement
showed that programming throughput can be improved by applying the same verify voltage to WLn + 1 to reduce capacitive coupling during the verify operation of the selected WL [50]. This is because, before WLn + 1 is programmed, it stays in the erase state and applying a lower voltage than the read pass voltage to WLn + 1 does not affect the sensing current for the verify operation of the selected WL. However, in 3D NAND, since there is no metallurgical junction among WLs, the fringing field may induce Vt variation of the selected WL at read operation, depending on the voltage previously applied to adjacent WLs. Figure 5: (**a**) WL loading variation due to channel hole CD variation. Reprinted/adapted with permission from Ref. [44], 2017, IEEE. (**b**) Variable-pulse scheme to cope with WL loading variation. Reprinted/adapted with permission from Ref. [44], 2017, IEEE. As the pitch of WLs is downward, the initial Vt of the selected WL decreases due to an increase in the fringing field of the adjacent WL during read operation, which decreases the programed Vt of the selected WL. To improve this, a method of applying a negative voltage to BL has been proposed [43]. Unlike the conventional method of applying ground to BL in the program operation, by applying a negative voltage, the voltage between the gate and the poly-silicon channel can be increased, and thus, more electrons can be programmed, widening the memory window. However, this method may also cause reliability problems, such as oxide breakdown by increasing the electric field between the gate and the channel and retention loss by trapping the excess electrons, and may burden the peripheral circuit for generating a negative voltage. In the transition from 2D to 3D NAND, another problem in terms of reliability is early retention loss. Since 3D NAND uses band-engineered tunneling oxide for hole injection during the erase operation, electrons are not only stored in the charge trap layer in the program operation, but some are trapped in the tunneling oxide, weakening vertical retention characteristics [51; 52]. Moreover, the electrons stored in the charge trap layer undergo lateral migration through silicon nitride connected over the entire WLs, intensifying retention loss [53; 54]. To improve this, a reprogram method in which program operation is performed once again in a state where retention loss has occurred right after first program operation, improving both vertical and lateral charge loss [55]. As shown in Figure 7, the negative counter pulse scheme was also suggested [48]. This scheme utilizes a counter-pulse by boosting the channel potential through a self-boosting mechanism while applying a negative gate voltage to a selected WL during verifying operation, as shown in Figure 7. The large negative field generated accelerates the de-trap process between program loops, thereby reducing the retention loss. Figure 6: Couple-capacitance-minimizing technique. Reprinted/adapted with permission from Ref. [50], 2019, IEEE. A aggressive pitch scaling of WLs also results in cell-to-cell programed Vt variation due to hole radius variation by high aspect-ratio hole etching process, which increases the number of programming loops, degrading the program throughput. To solve this problem, an adaptive pulse programming scheme is proposed [56]. Programmed Cell Vt distribution can be reduced by classifying fast cells and slow cells in advance. By applying inhibit voltage to BL to induce program inhibit operation in fast cells during the program pulse, it prevents fast cells from over programming by using shorter programming pulse width. W-C. [PERSON] et al. also proposed a pair-bitline program scheme. In the case of our single-gate vertical-channel (SGVC) 3-D NAND Flash chip, the gate edge profile causes strong discrepancy of program property between even or odd BLs. These issues are usually addressed by performing program on cells individually on even and odd BLs at the expense of program throughput.