## 5 Results and Discussion
The Figure 12a,b shows the line voltages with d-q control and SPWMDSC and SPWMPSC respectively, when one of the phases is open-circuited from time t = 1 s to t = 1.2 s at 50 Hz frequency. Figure 12c,d is the line currents with d-q control and SPWMDSC and SPWMPSC. During the faulty open-circuited operation, Figure 12e-h shows the capacitor voltages of the upper arm and lower arm of phase-a SM-1 with SPWMDSC and SPWMPSC modulation schemes, respectively. Further, the primary and secondary phase-a transformer currents, when SPWMLSC and SPWMPSC schemes are implemented, are shown, respectively, in Figure 12 ij. Similarly, Figure 13a,b shows the line voltages with d-q control and STHILSC and STHIPSC respectively, when one of the  
Figure 11: Change in current. **(a)** Line voltages of converter with d-q control and STHILSC, **(b)** line voltages of converter with d-q control and STHIPSC, **(c)** line currents of converter with d-q control and STHILSC, **(d)** line currents of converter with d-q control and STHIPSC, **(e)** STHILSC implemented upper arm phase-a SM-1 capacitor voltage, **(f)** STHILSC implemented upper arm phase-a SM-1 capacitor voltage, **(g)** STHILSC implemented lower arm phase-a SM-1 capacitor voltage, **(h)** STHIPSC implemented lower arm phase-a SM-1 capacitor voltage, **(i)** primary and secondary phase-a transformer currents when STHILSC is implemented, **(j)** primary and secondary phase-a transformer currents when STHILSC is implemented, **(k)** STHILSC implemented line voltage THD, **(l)** STHILSC implemented line current THD, **(m)** STHIPSC implemented line voltage THD, and **(n)** STHIPSC implemented line current THD. phases is open-circuited from time t = 1 s to t = 1.2 s at 50 Hz. Figure 13c,d shows the line currents with d-q control and STHILSC and STHIPSC respectively. During the faulty open circuit condition, Figure 13e-h shows the STHILSC implemented upper arm and lower arm phase-a SM-1 capacitor voltages, respectively, and STHIPSC implemented upper arm and lower arm phase-a SM-1 capacitor voltages, respectively. The primary and secondary phase-a transformer currents when implementing STHILSC STHIPSC are shown in Figure 13i,j. Further, the short circuit condition is created from time t = 1 s to t = 1.2 s. At this time interval, the converter performance is visualized, with simulation results shown in Figure 14. Figure 14a,b shows the line voltages with d-q control and SPWMLSC and SPWMLSC respectively. Furthermore, Figure 14c,d shows the line currents with d-q control and SPWMLSC and SPWMPSC respectively. During the faulty short circuit condition, Figure 14e-h shows the upper arm load lower arm phase-a SM-1 capacitor voltages with SPWMLSC schemes, respectively. Furthermore, the primary and secondary phase-a transformer currents SPWMLSC and SPWMPSC modulation schemes are shown in Figure 14i,j, respectively. Figure 12: Converter when one phase is open circuited. (**a**) Line voltages of converter with d-q control and SPWMLSC, (**b**) line voltages of converter with d-q control and SPWMPSC, (**c**) line currents of converter with d-q control and SPWMLSC, (**d**) line currents of converter with d-q control and SPWMLSC implemented upper arm phase-a SM-1 capacitor voltage, (**f**) SPWMPSC implemented upper arm phase-a SM-1 capacitor voltage, (**g**) SPWMLSC implemented lower arm phase-a SM-1 capacitor voltage, (**h**) SPWMPSC implemented lower arm phase-a SM-1 capacitor voltage, (**i**) primary and secondary phase-a transformer currents when SPWMLSC is implemented, (**j**) primary and secondary phase-a transformer currents when SPWMPSC is implemented. Figure 13: Converter when one phase is open circuited.