# Review of Ka-Band Power Amplifier
## 2 Technology
The InP HEMT device is a vertical device, which has better noise characteristics than the InP HBT device. It is often used to design low-noise amplifiers. Its profile is shown in Figure 3b.The InP HBT device is a transverse device. Compared with InP HEMT, its breakdown voltage is higher, and its power capacity is larger. It is often used to design power amplifiers. InP HBT is mainly divided into a single heterojunction bipolar transistor (SHBT) and a double heterojunction bipolar transistor (DHBT). On the one hand, the band gap of the InP DHBT collector material is greater than that of the InP SHBT collector material, so its collector has higher voltage resistance, and it is conducive to high power output; on the other hand, the collector material of InP DHBT has high thermal conductivity, so it has better heat dissipation performance and is more suitable for high-current and high-power circuit design. InP-based technology is the only technology that can provide Pas with >20 dbm output power over 200 GHz [31; 32]. DHBT 500 nm and 250 nm technology nodes provide about 330 GHz and 400 GHz f\({}_{\text{T}}\) respectively, and the latter's f\({}_{\text{MAX}}\) is up to 700 Ghz. Compared with traditional CMOS FET, the InP DHBT process has the advantages of large breakdown voltage, small parasitic capacitance and low substrate loss. The main limitation of InP is its cost because it is difficult to purchase and is a very fragile material, which makes its manufacturing and handling extremely dangerous. Figure 3: (**a**) GaN HEMT structure profile, (**b**) InP HEMT structure profile. With the increase in the operating frequency of Pas, the CMOS process node decreases to several nanometers or tens of nanometers [33]. The reduction in the MOS transistor size will reduce the breakdown voltage threshold of the gate oxide layer, and the power supply voltage will also decrease with the increase in the process nodes. Silicon has low electron mobility and poor high frequency characteristics, which limits the application of silicon technology in the higher frequency band. The lower breakdown voltage also limits the output power of the power amplifier. However, due to the extremely rich content of silicon in nature, it is easy to purify and grow a single product. The cost of silicon technology is much lower than that of III-V technologies (when mass produced). In addition, the integration of silicon technology is very high, and multi-layer metal layers can make very complex circuits. In 2021, [PERSON] proposed a 2-stage cascode PA in 60 nm CMOS. The PA achieved 17.1 dBm output power and the PAE remained above 38.2% in the area of 0.16 mm\({}^{2}\)[34]. When the performance requirements are not too strict, the silicon process can be realized in a small area, and the cost is very low. Therefore, silicon technology is one of the important processes for making the Ka-band power amplifier. With decades of development, bulk silicon CMOS technology has become more and more mature. However, with the continuous reduction in device feature size, many new problems still appear, such as the short channel effect. SOI (silicon on insulator) technology refers to the process of forming a layer of semiconductor monocrystalline silicon thin film material on the insulating material layer, and then manufacturing integrated circuits on monocrystalline silicon. The main difference between the traditional bulk CMOS process and SOI technology is that SOI CMOS have a buried oxide layer, which separates the device from the substrate [35]. Its profile is shown in Figure 4. In SOI CMOS, each device is surrounded by an oxide layer, which is completely isolated from the surrounding devices and fundamentally eliminates the latch-up effect [36]. At the same time, the buried oxygen layer also increases the thickness of the insulating layer between the interconnect and the substrate, which greatly reduces the parasitic capacitance of the interconnect [37].