## 3 Circuit Design
### DC Offset Cancellation Loop  
There are a large number of nonideal factors that can increase the output offset, such as inevitable device mismatch, large gain of the receiver, flicker noise, the sink current of the photodiode, and PVT variation. Therefore, a DCOC circuit following the VGA stage [27] was designed to eliminate the output offset. As shown in Figure 14, the schematic of the DCOC circuit consists of a lowpass filter, an error amplifier, and a sink current source. The DCOC circuit should extract the offset signal from the output of the VGA stage without data signal deterioration. Therefore, lowpass filters with large resistors are commonly implemented as the first stage in a DCOC circuit. Figure 14: A schematic of the DC offset cancellation (DCOC) circuit. Figure 12: Simulated eye diagrams of the receiver in high-power mode. (**a**) 25 Gb/s; (**b**) 28.9 Gb/s. Figure 13: Simulated eye diagrams of the receiver in low-power mode. (**a**) 25 Gb/s; (**b**) 28.9 Gb/s. The bandwidth of the lowpass filter in a DCOC loop is typically designed to be a few megahertz. The capacitance density of a nitride metal-insulator-metal (MIM) capacitor is around 0.001 mm\({}^{2}\)/pF in 0.13 \(\upmu\)m SiGe BiCMOS technology. The area of the capacitors is about 0.032 mm\({}^{2}\) to realize the typical 4 MHz bandwidth of a lowpass filter with given R1 and R2. In our design, the DCOC loop without the capacitors of the lowpass filter can also realize the function of DCOC (DC offset cancellation), and the bandwidth (\(BW\)) and the gain-bandwidth product (\(GBW\)) of the DCOC loop remain unchanged. Due to the high-swing input signal, the error amplifier in a DCOC loop would work improperly without parasitic capacitors. Finally, parasitic capacitors result in a 6% decrease in chip area by avoiding the introduction of the additional capacitors in a typical design. As shown in Figures 15 and 16, the variations of the total parasitic capacitance in the following error amplifier (the sum of \(C_{GSI}\) and \(C_{GBI}\)) which caused by differential input voltage, process and temperature are smaller than 3.8% and 1.7%, respectively. The PVT variation of the parasitic capacitors is too small to affect the DCOC loop; hence, the PVT variation of the parasitic capacitors can be considered acceptable. An error amplifier following the lowpass filter was implemented to amplify the DC offset. The effective value of C\({}_{\text{C}}\) becomes large due to the Miller effect; then the dominant pole of the error amplifier is pushed to low frequency, which avoids the data signal coupling from the VGA stage to the input TIA stage through the DCOC loop. The simulated coupling isolation is about \(-128\) dBc at 12.5 GHz. The DCOC loop shown in Figure 1 is based on feedback architecture [28], and the transfer function of the DCOC loop is given by  
\[H_{DCOC}=\frac{H_{AMP}(s)}{1+H_{AMP}(s)H_{error}(s)\frac{g_{\text{m}5}}{1+g_{ \text{m}5}R_{\text{E}5}}}, \tag{6}\]  
Figure 16: The simulated process and temperature variation of the total parasitic capacitance. Figure 15: The simulated voltage variation of the total parasitic capacitance. where \(H_{AMP}(s)\) denotes the transimpedance transfer function from the input TIA to the VGA stage, \(H_{error}(s)\) is the transfer function of the error amplifier in the DCOC circuit, and \(g_{m5}\) is the transconductance of Q\({}_{5}\). Considering that \(H_{AMP}(s)\) and \(H_{error}(s)\) are far more than 1 within the bandwidth of the DCOC loop, \(H_{DCOC}(s)<<1\), and the DC offset and flicker noise are attenuated by the feedback architecture from Equation (6). Considering the input-referred noise of the optical receiver deteriorated by the DCOC loop, the input-referred noise introduced by the error amplifier and the sink current source were analyzed.