## 4 Sensitivity Analysis
### Sensitivity Analysis  
This analysis consists of a comparison by simulation of the main characteristic parameters associated with the dynamic and steady-state response of the output variable (output voltage, \(V_{O}\)) of a simplified converter model with respect to that of the expected behaviour of the full converter model (reference model) for a step-type input signal. Due to the nature of the proposed research, it might be considered of interest to work with real converters instead of simulations. However, this would have required the construction of 24 converters. This is an unaffordable cost due to the purchase of devices, acquisition cards, controller circuits, etc. on the one hand and the enormous number of working hours involved on the other. But also, it is not considered necessary, since, as demonstrated in [17], the performance of the complete non-ideal model of the converter fits almost perfectly to the real case. In fact, the complete non-ideal model of the converter was validated against a real converter. Consequently, it is sufficient to use this model, already validated (which can be considered as a reference or benchmark), to analyse the true influence of the non-linearity not taken into account in each case of sensitivity analysis. The methodology proposed for the sensitivity analysis is based on cancelling out in each simulation of the complete non-ideal model of the converter the effect of a specific non-ideality from those defined in Section 2.2. For this purpose, the terms associated with the non-ideality under study (the one not taken into account in each case) are removed from the full reference model [17], i.e., the corresponding row or column is removed from the model, which reduces the order of (1) from 13 to minus. In this way, it is possible, by comparison with the full reference model, to isolate the effect that each non-ideality has on the converter response. To quantify this effect, it is necessary to calculate certain magnitudes of percentage errors that determine the differences between the behaviour of the output variable of each simplified model and the reference one (for each non-ideality and case study). Although the reference model is of high order (13 th order), the dynamic behaviour of the output parameters, voltage and current is mainly determined by the output low-pass filter (LC circuit). Consequently, the dynamics of the converter output variables can be expected to follow a response similar to that of a second-order system. For this reason, the errors chosen for the analysis are the usual ones in a second-order system: overshoot error, rise time error, fall time error, steady-state error and peak time error. The results of more than 330 simulations performed in a Matlab(r) Ver R2019a environment for all the cases under study, operating frequencies and topologies, buck and boost are shown in Figures 4 and 5, respectively. \begin{table}
\begin{tabular}{c c c c c} \hline \hline  & \multicolumn{2}{c}{**Buck Topology**} & \multicolumn{2}{c}{**Boost Topology**} \\ \hline
**Element** & **Model and Rated Values** & **Parameters** & **Model and Rated Values** & **Parameters** \\ \hline \multirow{4}{*}{Mosfet} & SPW47N60C3 FKSA1, & \multirow{2}{*}{\(C_{\text{ass}}:2200\) pF \(R_{\text{DS}}:70\)} & DFN420N10T, IXYS® & \multirow{2}{*}{\(C_{\text{ass}}:4390\) pF} \\  & INFINENON® & & & \\  & USA & & & 100 VDC, 420 A & \(R_{\text{DS}}:2.3\) m\(\Omega\) \\  & 650 VDC, 47 A & & & \\  & STTH20004 TV1, & & & \\  & STMicroelectronics® & \(V_{\text{y}}:1.325\) VDC & DESI30-10A, IXYS® & \(V_{\text{y}}:1.5\) VDC \\  & 400 VDC, 240 A & \(R_{D}:2\) m\(\Omega\) & 1000 VDC, 30 A & \(R_{D}:12.5\) m\(\Omega\) \\ \hline \hline \end{tabular}
\end{table} 
Table 4: _Cont._Figure 4: Conf. Figure 4: Overshod error, rise time error, setting time error, steady-state error and peak time error for buck topology in each case. Figure 5: Conf. Figure 5: Overshoot error, rise time error, settling time error, steady-state error and peak time error for boost topology in each case.