# A Reconfigurable SRAM CRP PUF with High Reliability and Randomness
## 3 Proposed SRAM CRP PUF
### Symmetrical Layout Design Technique  
In the realm of PUFs, two distinct forms of variation play a crucial role: systematic variation and random variation [24]. Systematic variation is predictable, and is caused by controlled manufacturing or environmental factors, while random variation is attributed to uncontrollable elements such as semiconductor manufacturing variations. Unlike systematic variations, random variations lack clear patterns due to their inherent unpredictability, contributing to the PUF security through entropy. To optimize randomness and reliability, the proposed PUF cell must utilize a regular layout, minimizing the systematic variations while maximizing the inherent device characteristics for enhanced local random variation. The symmetric layout of matched devices can help minimize systematic variations, and the use of small-sized devices will maximize variations in device characteristics, thereby enhancing the randomness and reliability of PUF [25].  
Figure 3 depicts the layout implementation, illustrating the PUF cell floor plan, where the symmetric placement of both the inverter arrays is crucial for dominant random output characteristics inherited from process variation. This symmetrical arrangement minimizes the systematic variation [26]. Transistors within each inverter array are symmetrically placed based on the vertical boundary (dashed line). The transistors are placed as close together as possible to minimize the effects of gradients. The first _n/4+2_ and last _n/4+2_ transistor columns constitute the parallel-coupled inverters (blue color), the challenge transistors (green color), the adjunct NMOS transistors (purple color), and \"dummy\" transistors (red color) for the left and right sides, respectively. To ensure uniformity during silicon etching, two \"dummy\" columns are added, ensuring identical geometries for the transistors. Each column comprises five transistors that are stacked vertically, with two PMOS transistors at the top and three NMOS transistors at the bottom. The two middle columns are utilized for pre-charge transistors (orange color) at the top and word-line transistors (yellow color) at the bottom. The central space is designated for cross-wiring the outputs of the two inverter arrays.  
Among the input lines connected to the left and right inverter transistors, the input signal, _PRE_, must be symmetrically connected to each array to simultaneously activate both inverters during the \"Evaluation\" mode. The input connection line of the _PRE_ transistor must be connected symmetrically along the vertical boundary line to avoid delay mismatch. Meanwhile, the input signals, _C<n-1:0>_ and _WL_, are conveniently connected to each array without the strict requirement of symmetry, because the proposed timing sets the challenge input in the \"Configuration\" mode, which does not impact PUF operation in \"Evaluation\" mode. The world-line is activated after a sufficient wait time in the proposed timing scheme, ensuring the two PUF outputs are fully polarized to opposite values.  
Figure 3: (a) Layout floor plan and (b) Layout design with 32-bit challenge input.  
The layout design for the PUF cell requires an area of 7.42 \(\upmu\)m \(\times\) 51.72 \(\upmu\)m, utilizing the 180 nm CMOS process shown in Figure 3b. The transistors are set to the minimum size, \(W/L=220\) nm/180 nm, to maximize the random variation (local mismatch) [27]. With a bit-width of \(n=32\) for the input challenge signal, the design incorporates a total of 104 transistors. The actual layout organizes transistors according to a floorplan, utilizing assigned colors to represent distinct functions.