# An Efficient Algorithm for Mapping Deep Learning Applications on the NoC Architecture
## 3 Multilevel Task Mapping for NN Applications  
In this section, the main objective is about exploring the AI-based application mapping on various NoC platforms by considering latency and energy consumption. The technique used in this article is depicted in Algorithm 1. There are multiple phases of this algorithm. In the first phase (region analysis), we select particular region(s) where the various tasks of an application can be deployed based on core availability. In the next phase, the neurons of that task are mapped onto the processor cores of the region selected in phase one, and hence the complete application is mapped onto the processor architecture. To the best of our knowledge, the task mapping of AI applications on NoC architecture is rarely studied and we shall consider a mesh-based NoC for application mapping to evaluate this solution. However, the prospective research will focus on exploring NoC architectures other than mesh-based structures. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Article** & **Mapping Technique** & **Performance Improvement** &
\begin{tabular}{c} **AI Application** \\ **Mapping** \\ \end{tabular} \\ \hline
[6] &
\begin{tabular}{c} DVFS-based \\ application mapping \\ \end{tabular} & Large power savings & ✗ \\ \hline
[8] & Multi-application mapping &
\begin{tabular}{c} 18\% reduction in latency and \\ energy consumption \\ \end{tabular} & ✗ \\ \hline
[9] & Fault-tolerant mapping &
\begin{tabular}{c} 9.5\% communication energy \\ reductions and 7.94\% \\ performance improvement \\ \end{tabular} & ✗ \\ \hline
[10] & Heuristic-based algorithm &
\begin{tabular}{c} Reduction in the maximum \\ average packet latency by 10.42\% \\ \end{tabular} & ✗ \\ \hline
[11] & \
\begin{tabular}{c} Run-time mapping for hard \\ real-time applications \\ \end{tabular} &
\begin{tabular}{c} 13\% reduction in the \\ energy consumption \\ \end{tabular} & ✗ \\ \hline
[12] & \
\begin{tabular}{c} B*tree-based \\ simulated annealing \\ algorithm/genetic algorithm \\ \end{tabular} &
\begin{tabular}{c} 23.45\% reduction in power \\ consumption and 24.42\% \\ reduction in the latency \\ \end{tabular} & ✗ \\ \hline
[34] & \
\begin{tabular}{c} Branch-bound (BB)-based exact \\ mapping (BEMAP) algorithm \\ \end{tabular} &
\begin{tabular}{c} 19.93\% reduction in energy \\ consumption and 61.10\% \\ depletion in network latency \\ \end{tabular} & ✗ \\ \hline
[35] & \
\begin{tabular}{c} Comparison of most of the \\ reported application mapping \\ techniques for NoC \\ \end{tabular} &
\begin{tabular}{c} Conclusion is provided for NoC \\ application mapping-based on \\ algorithm run-time \\ \end{tabular} & ✗ \\ \hline
[36] & \
\begin{tabular}{c} Particle swarm optimization \\ (PSO) algorithm and \\ TABU search \\ \end{tabular} &
\begin{tabular}{c} Reduction in average latency by \\ 63\% and average energy \\ consumption by 69\% \\ \end{tabular} & ✓ \\ \hline
[37] & \
\begin{tabular}{c} Combining uneven and search \\ mapping strategies \\ \end{tabular} &
\begin{tabular}{c} Up to 64\% more energy-efficient \\ in comparison with SotAs \\ \end{tabular} & ✓ \\ \hline
[38] & \
\begin{tabular}{c} Multic level genetic algorithm \\ based technique \\ \end{tabular} &
\begin{tabular}{c} Reduction in power \\ consumption and delay in \\ comparison with traditional \\ genetic algorithm \\ \end{tabular} & ✗ \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Comparison of the recent work. The algorithm first partitions the application into tasks, which are respective layers of the neural network, and selects a particular region for its mapping. It also looks into the processor cores which are available at the moment. In the second step, the neurons are mapped onto the particular cores to enhance the performance in terms of latency and energy consumption. In the following sub-sections, we discuss the two steps which are required for realizing these objectives.