## 2 Materials and Methods
### Methods  
_Solutions for the Adaptation Mechanism and Clock Generator_  
The proposed digital ANN operates in a mixed synchronous-asynchronous mode. This means that part of the operations is performed sequentially, but asynchronous processing is introduced wherever possible, which allows for significant simplification of the structure of the used circuits. The network works with multi-bit signals, which means that each input datum \(x_{i}\), as well as the corresponding neuron weight \(w_{i,j}\), is a multi-bit number (usually 16-bit) [26]. Lower resolutions, however, may be used to test the proposed solution. Providing, in parallel, a full learning pattern into the network (\(X=\{x_{1},x_{2},\dots,x_{n}\}\)) is impractical, considering various possible values of \(n\) in \(X(k)\) and \(W_{j}(k)\) signal (where \(n\) is the dimension of the learning pattern). For this reason, particular components of the \(X\) pattern are fed sequentially into the network, with all bits of a given component \(x_{i}\) provided in parallel. For example, for a ANN processing 10-element learning patterns \(X\), only 10 clock cycles are needed. Diagram of the proposed adaptation mechanism is shown in Figure 5.  
Figure 4: Measurement setup composed of PC board, designed from scratch for the verification of the realized chip prototype: (**left**) a new, printed circuit board (PCB) for the implemented integrated circuit; and (**right**) the overall measurement setup. Figure 5: Diagram of the proposed adaptation mechanism. In the first step, described above, the distances between the neuron weights and the given learning pattern \(X\) are calculated, according to the so-called Manhattan distance measure:  
\[D_{\text{L1}}(X(k),W_{j}(k))=\sum_{i=1}^{n}\big{|}x_{i}(k)-w_{i,j}(k)\big{|}, \tag{3}\]  
This means that for each pair (\(x_{i}(k)\), \(w_{i,j}(k)\)) the signal \(|x_{i}(k)-w_{i,j}(k)|\) is calculated, which is then stored in the internal memory of a given neuron. The subtraction operation is based on a multi-bit full subtractor (MBFS), in which the borrow out bit \(B_{i,j}\), at the most significant 1-bit full subtractor (1 BFS) in the MBFS indicates which of the input signals (\(\alpha\) or \(w\)) is larger. This information is also stored in the memory of a given neuron. The memory cells containing particular neuron weights \(w_{i,j}\), and the computed \(|x_{i}-w_{i,j}|\) factors are indexed with the use of the proposed programmable multiphase clock. It is worth emphasizing here that the described operations are performed in parallel in all neurons of the ANN. In other words, for an \(n\)-element learning pattern \(X\), only \(n\) clock phases are required to calculate the distances of all neurons in the network to a given \(X\). At the next stage of the learning algorithm, the winning neuron is determined. On the basis of the position of this neuron, the ANN then determines which neurons belong to its neighborhood and what is their distance to this neuron. The way the neighborhood is defined depends on the applied learning algorithm of the ANN. Based on the distance, the value of the learning rate, \(\eta\), is calculated for each neuron in the ANN. Then, based on the previously stored \(|x_{i}-w_{i,j}|\) factors, the adaptation process is carried out, as described below:  
\[w_{i,j}(k+1)=w_{i,j}(k)+(\overline{B_{i,j}}-B_{i,j})\cdot P_{i,j}(k)\cdot|x_{i }(k)-w_{i,j}(k)|, \tag{4}\]  
where \(P_{i,j}(k)\) is the product of learning rate \(\eta\) and the so-called neighborhood function, which determines the strength of the adaptation depending on the distance of a given neuron to the winning neuron. The adaptation process is also carried out in an iterative manner. The number of iterations is equal to the number of iterations from the first step described above (\(n\)). The same clock generator is used at this stage to control this process. At the hardware level, in Equation (4) very simple summing, subtraction, negation and multiplication operations are used.