# GPU@SAT DevKit: Empowering Edge Computing Development Onboard Satellites in the Space-IoT Era
## 1 Introduction
#### Edge Computing Onboard Satellites for Space-IoT
The constant exposure to cosmic rays and high-energy protons significantly increases the risk of Single Event Effects (SEEs) in these devices [37]. While some of these effects, such as Single Event Upsets (SEUs), are non-destructive soft errors, others, like Single Event Latchups (SELs), can have catastrophic consequences and are therefore unacceptable. Moreover, radiation exerts a long-term detrimental effect on hardware, notably reducing the overall lifespan of the mission. Field Programmable Gate Arrays (FPGAs) offer a viable alternative. One of their key advantages is their availability in a wide range of silicon-grade technologies, making them well suited for space applications. For instance, radiation-hardened FPGAs like the Xilinx Virtex-5 QV are immune to SELs and highly resistant to SEUs [38]. Due to their robustness, space-qualified FPGAs have been a reliable choice for space missions for many years [39], establishing themselves as a proven technology in the industry. Although they may involve higher initial costs and longer development times compared to COTS solutions, their customizable architecture allows for optimized performance and energy efficiency, making them ideal for accelerating compute-intensive tasks, such as DL algorithms [40]. In contrast, hardware platforms like Graphic Processing Units (GPUs), which dominate commercial applications for executing ML tasks, are rarely used in space due to their higher power consumption and susceptibility to SELs. Indeed, to the best of our knowledge, no space-grade GPU has yet been introduced to the market. Consequently, FPGAs are the preferred platform in space for onboard parallel computation [41]. To advance the deployment of FPGA-based technologies for edge computing algorithms on satellites, and to foster the development of the Space-IoT paradigm, this paper introduces the GPU@SAT DevKit. This innovative ecosystem is tailored to assess a versatile, high-performance accelerator (GPU@SAT) [42; 43] specifically designed for edge computing tasks, i.e., image processing, which requires handling computationally intensive operations like convolutional layers. The accelerator features a parallel architecture, comprising multiple scalable cores and compatibility with the open-source OpenCL 1.2 programming framework, resembling the functionality of a GPU. The design is well suited for executing DL algorithms through the General Purpose computing on GPU (GPGPU) paradigm, leveraging GPU processing power for versatile computations beyond traditional graphics rendering. Additionally, it is entirely VHDL-coded and optimized for FPGAs, free from third-party Intellectual Property (IP) dependencies. The remainder of this paper proceeds as follows: Section 2 explores FPGA-based solutions for accelerating DL algorithms, with a focus on the GPU@SAT architecture and its rationale for adoption. Section 3 provides an in-depth technical overview of the DevKit and illustrates the execution flow of a kernel. Section 4 presents the benchmarking utilized to validate the functionality of the DevKit, alongside initial results from the accelerator, demonstrating its promise in edge computing applications. Finally, Section 5 provides a summary of the key findings and outlines future research directions.