## 4 Hardware Security
### Physical Unclonable Functions (PUFs)
#### 4.1.4 PUFs as a Root of Trust  
A layered defense model, as shown in Figure 19, is preferred for a secure system with outermost layers managing the regular operations of the device and acting as protection barriers for inner layers. RoTs act as a fundamental source for various secure schemes enforcing access to cryptographic modules as well as security resources at the hardware level. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Article** & **PUF Type** & **Stages** & **Uniqueness [mean (std)]** & **Uniformity [mean (std)]** & **Reliability [mean (std)]** \\ \hline [234] & Lattice PUF & 1000 & 50.00\% (1.58\%) & 49.98\% (1.58\%) & 1.26\% (2.88\%) \\ \hline [236] & FLAM-PUF & 64/128 & 49.73\%/49.99\% & 49.81\%/49.85\% & 95.59\%/96.58\% \\ \hline \multirow{2}{*}{[237]} & Strong response-feedback PUF & \multirow{2}{*}{32/64/128} & 50.17 (1.41)/50.00 (0.31)/ & 49.54 (3.67)/50.05 (2.79)/ & \\  & & & 49.99 (0.21) & 49.93 (1.78) & - \\ \hline \multirow{2}{*}{[238]} & DDQ-APUF & 64/128 & 47.28\%/47.65\% & 50\%/50\% & 99.95\%/99.91\% \\ \hline \multirow{2}{*}{[246]} & \multirow{2}{*}{FOM-CDS PUF} & \multirow{2}{*}{17} & 47.38\%(RO mode)/ & 47.71\% (RO mode)/ & 3.1\% CRO-PUF/ \\  & & & 53.79\% (TERO mode)/ & 56.23\% (TERO mode)/ & 9.14\% Dual mode/ \\  & & & 50.33\% (Full mode) & 53.68\% (Full mode) & 7.91\% FOM-CDS PUF \\ \hline [247] & CRC-PUF & 128 & 49.9978\% & 50.077\% & - \\ \hline \multirow{2}{*}{[249]} & \multirow{2}{*}{RC-PUF} & \multirow{2}{*}{32} & 27.3\% (bit delay = 2 μs)/ & 50.3\% (bit delay = 2 μs)/ & 96.2\% (bit delay = 2 μs)/ \\  & & & 30.9\% (bit delay = 32 μs) & 50.3\% (bit delay = 32 μs) & 98.5\% (bit delay = 32 μs) \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Comparing the performance of PUFs. The software security built on top of hardware-based RoT provides extra layers of flexibility and protection. These hardware-based RoTs build a trusted execution environment (TEE) for running privileged software, perform cryptographic operations, and offering constant tamper protection. This design approach minimizes the attack surface area and makes inner layers easier to secure because they have fewer, highly controlled tasks. The trust-validation sequence continues moving towards inner layers up to the system core, known as the Root of Trust (RoT) [259]. Edge devices leverage RoTs in establishing a protected environment for cryptographic processes needed for data encryption and authenticating devices connected to backend systems [260]. RoT applies various code validation mechanisms before executing the code on secured CPUs and shields against physical attacks to a certain extent. Thus, a Chain of Trust is established when each component in this chain trusts the codes it runs as they are validated by the previous link, creating an unbroken line of trust back to the Root of Trust [261; 262]. The hardware RoT secures EC operations by providing the cryptographic keys in the booting process. Hardware-based RoT is typically a small, dedicated chip embedded within an IoT device leveraging upon intrinsic hardware characteristics [263]. PUFs are ideal for hardware-based RoT that hosts cryptographic functions, such as private and public key encryption [264]. The unique keys generated from the edge device's PUF and the secure boot process ensure that only authorized firmware or updates are loaded, preventing trojan or malware attacks. [PERSON] et al. proposed a hardware Root of Trust (RoT) architecture utilizing a Zynq-7000 SoC FPGA (Xilinx Inc., San Jose, CA, USA) and integrating various cryptographic components. These components include PUFs for device authentication, the Advanced Encryption Standard (AES) for data encryption, Secure Hash Algorithms (SHA-2 and SHA-3) for ensuring data integrity, and the Edwards-curve Digital Signature Algorithm (EdDSA) for digital signature verification [265]. A hardware RoT is proposed in [266], leveraging Quantum Tunneling PUFs to identify ICs digitally. In contrast to SRAM PUFs, Quantum Tunneling PUFs operate without the need for error correction.