# Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation
## 1 Introduction
Furthermore, the model of mobile devices (MDs) is a nonlinear function of the position and velocity parameters [10]. Nonlinear models in state equation assumption may lead to non-optimal solutions for linearized schemes. In terms of these services and applications, the techniques of positioning and tracking approaches have become particularly important and increased dramatically under these developments. Most of today's positioning and tracking systems are developed and implemented with software. However, software implementations often result in speed delay and cannot provide in-time positioning information for LBS applications [17; 18; 19; 20]. In order to improve the computational speed of positioning systems and accuracy, there already are lots of improved algorithms in literature [21; 22; 23; 24; 25; 26; 27; 28; 29; 30; 31; 32; 33; 34]. The calculations of the KF approach are involved in the number of matrix computations, which include addition, multiplication, and inverse operations. The approach is difficult to implement hardware in traditional devices with some practical systems, such as high performances in real-time, flexible and convenient implementation [10; 17; 18; 19; 20; 30; 31; 32]. In addition, the processors of Digital Signal Processing (DSP) adopt sequential program execution. Therefore, it cannot correspond to the require of high-speed and real-time requirements. On the contrary, an FPGA has precision accuracy and high portability, it can decrease the disadvantages of software for specific integrated circuit approaches. Actually, one possible way to increase performance is through the use of hardware acceleration using field-programmable gate arrays (FPGAs). Implementing functions as hardware have the potential to allow the use of more complex algorithms such as KF, and the approach also allows the implementation of multiple functions-as-a-chip systems on a single FPGA [16; 17; 18; 19; 20]. Each logical unit of the FPGA is determined at the time of programming, and no instructions are required. As a result, there is a significant advantage in the speed of processing operations with high accuracy and freely programmable characteristic. Namely, it can be easy to develop. Because of these advantages, FPGA is very suitable to be a verification method before tape-out. A chip has the advantage of low cost and fast processing time. Therefore, tape-out is chosen as the result. This article implements localization algorithms using high-speed hardware devices. To implement the localization algorithms, the filtering formulas are derived and simplified from the filtering models and matrix operations, and then the hardware-based approaches using FPGAs are implemented. The FPGA-based implementation of the localization algorithm can improve the traditional matrix operation approach and can be applied to practical systems. The hardware implementation has advances of high portability, low cost, high accuracy, and wide extension in scope. In addition, under a stationary environment, the coefficients of the \(\alpha\)-\(\beta\) filter are extracted from the KF algorithm, which is a degenerate form of the KF algorithm [15; 31; 32]. The proposed training and tracking scheme replaces the decision mode of the KF algorithm with an alpha-beta (\(\alpha\)-\(\beta\)) algorithm to avoid repeatedly calculating the Kalman gain (KG). In this article, an adaptive low-complexity location-estimation approach combining \(\alpha\)-\(\beta\) filtering algorithm with the KF algorithm is proposed and implemented. The proposed tracking approach is based on the \(\alpha\)-\(\beta\) filtering algorithm extracting the coefficients of the KG from the KF algorithm according to different judgments. In addition, this article proposed the hardware implementation for the proposed filtering algorithm. The concept is performed by a chip, which has the features of real-time processing and pipeline structure.