## 4 Hardware Implementation of CPU-SPU Collaborative SoC
### Hardware Implementation of the Fault Self-Repairing Module  
As previously described, the instruction fault self-repairing operation of the FSRM via the checkpoint-rollback mechanism is tightly coupled with the BB integrity checking mechanism of the instruction monitor. The overall control status diagram of the SPU real-time instruction monitoring and checkpoint-rollback operation is illustrated in Figure 7. When the instruction monitor detects a delay-slot instruction following transfer instruction into the execution of the CPU five-stage pipeline, the status of BB end triggers the  
Figure 6: The hardware implementation details of the instruction monitor connecting with the CPU. checkpoint-backup operation, which duplicates the values of instruction set registers into buffer-purpose registers. Then, the instruction monitor asserts the BB valid status when the BB integrity label verification has passed; otherwise, it asserts the BB invalid status. At the status of BB valid, a new checkpoint begins to be established, which backs up the values of buffer-purpose registers into the backup-purpose registers. After checking that the status is BB invalid, the checkpoint recovery is activated, and all the values of backup-purpose registers are restored into the instruction set registers. When the register value restoration has completed, the CPU_Stall signal will be released and the CPU resumes the first instruction execution of the current BB. This two-stage checkpoint-rollback can minimize the time consumption required for instruction fault recovery. The hardware implementation of two-stage registers for the checkpoint-rollback operation is presented in Figure 8, which also is a specific hardware implementation detail of Figure 4. We additionally configured the proposed two-stage registers for buffering and backing up all the values of the instruction set registers. In each stage, thirty-two 32-bit registers are configured to back up all the values of the instruction set registers (including the IR register). In some practical applications of the OpenRISC processor, only twenty-six instruction set registers are actually utilized in the realistic checkpoint-backup operation. Increasing register configurations of the thirty-two 32-bit registers will fully meet the requirements of future more-complicated checkpoint-rollback operations in different application platforms. For a better clarification, the implementation flow of the program execution monitoring and instruction fault self-repairing is presented in Algorithm 1. It should be considered that the CPU_Stall signal will suspend the execution pipeline of instruction when the BB's integrity is invalid, and then SoC enters the instruction fault self-repairing phase, which will make the performance overhead of FSRM impossible to be calculated by the performance indicator of Cycles-Per-Instruction (CPI). Therefore, the checkpoint-rollback operation as the post-detection technique will not be considered in the next performance overhead evaluation. Figure 7: The overall control status diagram of instruction monitoring and checkpoint-rollback. ```
1:\(ADD_{start}\), Instruction
2:Exception, BB End, BB Valid, BBInvalid
3:\(BB_{i}\leftarrow\) set of the program basic blocks, \(BB_{i}\), \(1\leq i\leq m\), where \(m\) denotes total of BBs. 4:\(Instruction_{j}\leftarrow\) set of instructions in each BB, \(Instruction_{j}\), \(1\leq j\leq n\), where \(n\) denotes total number of instructions in each BB.