# High-Efficiency, Low-Power, Fully Integrated Neural Electrical Stimulation Circuit
## 3 Circuit Design  
### High-Voltage-Generation Circuit Design  
Typically, there are two methods to realize high-voltage-generation circuits: DC-DC converters and charge pump circuits. DC-DC converters mainly consist of capacitors, inductors, diodes and transistors. However, for implantable chips, inductive components are generally bulky and impose risks for electromagnetic compatibility, making capacitor-based energy storage charge pumps the only viable option for on-chip high-voltage-generation circuits. The CW charge pump, as the earliest charge pump scheme (proposed in 1932), has the structure shown in Figure 1(a) [13]. However, the biggest problem of this scheme is that it is highly sensitive to parasitic capacitance. Subsequently, [PERSON] proposed a new charge pump design scheme, which is based on a diode and pump capacitor composition. The structure is shown in Figure 1(b). The circuit uses a number of diodes to prevent current backflow [14; 15]. With excellent performance, this design is widely adopted in mainstream high-voltage-generation circuits. However, this scheme still suffers from limitations, such as fixed gain and a large device area. Therefore, it is not suitable for systems with small area requirements. Although conventional charge pumps are easy to implement, their efficiency is relatively low due to the threshold voltage drop of diodes. To address this limitation, the conventional series-parallel charge pump replaces the diodes with CMOS switches, as shown in Figure 3. When the clock is high, all capacitors are charged by Vin, and the voltage difference between the upper and lower plates of the capacitors is 1.65 V. When the clock is low, the capacitors are connected in series, resul  
Figure 1: Block diagram of the neural stimulation. Figure 2: Switching charge pump structure: (**a**) CW charge pump; (**b**) Dickson charge pump. This paper presents a proposed series-parallel charge pump structure with a negative-voltage-generation module, as shown in Figure 4. Compared to conventional charge pump circuits, this architecture is capable of generating high voltages using a low-voltage CMOS process and reduces the number of stages required to achieve the same voltage conversion rate, thereby reducing the number of capacitors required and achieving a small area. Moreover, it enables the system to have a standby static power consumption as low as the picowatt level and to maintain high efficiency over a wide range of output currents. To achieve an output voltage above 12 V, the proposed series-parallel structure needs only four stages (N = (Vout \(-\) Vin)/3.3 V), in which 3.3 V is the voltage difference between the two plates of the capacitor in the charging stage, whereas conventional series-parallel structure needs seven stages due to lower voltage (1.65 V) stored on the capacitors. By saving three charge pump stages, the proposed charge pump saves 29% area compared to conventional structure, at the same time improving the power efficiency. The power consumption of the charge pump mainly comes from the dynamic power consumption of the switches. The larger the number of switches, the higher the dynamic power consumption. Similarly, high switching frequency leads to greater switching losses and reduced efficiency. However, high-frequency switching reduces the ripple of the output voltage. Hence, there is a trade-off to consider when deciding on the switching frequency. Besides switching losses, the efficiency of the charge pump is also affected by the on-state voltage drop of the switching devices. The increase in the number of stages may improve the voltage conversion efficiency, but each stage introduces additional losses. The negative-voltage-generation module of the high-voltage-generation circuits is shown in Figure 5a, and the series-parallel charge pump circuit is shown in Figure 5b.