# A Review of Sharp-Switching Band-Modulation Devices
## 5 Alternative Applications of Sharp Switching
### Dynamic Memory Cell: Operation as Capacitorless DRAM
With a '0'-state programmed, the deeply depleted body tends to get repopulated with carriers, due to thermal generation and parasitic current injection. By contrast, in the '1'-state the excess carrier concentration may decrease with time, due to recombination and current leakage. These two processes make the turn-on voltage shift with time and the dynamic memory window becomes narrower. When the turn-on voltages for logic '1' and '0' merge (VON-0 = VON-1), the memory effect vanishes [34]. Therefore, the carrier charge under the front gate needs to be periodically refreshed, lest the memory state is lost. In particular, the unwanted population of electrons that tends to accumulate under the gate and eventually corrupt state '0' can be eliminated by grounding the front gate. The maximum elapsed time in which it is still possible to recover the memory state without losing the information is known as the retention time. Frequent readout of the '0'-state improves retention, because the parasitic electrons are swept away by the anode pulse. Figure 17: Operation of N-type Z\({}^{2}\)–FET DRAM. (**a**) Carrier populations in ‘1’ and ‘0’ memory states. (**b**) Output characteristics in ‘1’ and ‘0’ states, showing the measured currents (adapted from [34]). The performance of the \(Z^{2}\)-FET as a 1T-DRAM cell can be briefly summarized, as follows:  
**Speed**: The \(Z^{2}\)-FET DRAM performs best when the program and readout pulses are short. The power dissipation is obviously reduced by limiting the time \(\mathrm{I_{ON}}\) flows (when reading out the '1'-state). Measurements show that with 320 ns anode pulses, the energy saving is two orders of magnitude compared with a 120 \(\mathrm{\SIUnitSymbolMicro s}\) pulse [22]. Ultra-fast operation has been demonstrated through TCAD simulations, with access times below 1 ns. The performance is enhanced for two reasons: (i) shorter anode pulses enable lower readout voltages, and (ii) shorter top-gate pulses enhance the barrier height. Besides, slow cell access times may result in the loss of the sharp-switching capability. **Retention time**: Both memory states benefit from repeated readout operation, which has a regenerative effect. Adequate control of the carrier concentration during the '0'-state hold operation is essential. After careful optimization, retention times over 500 ms have been demonstrated [38]. Trap-assisted tunneling [39] and especially carrier generation through Shockley-Read-Hall (SRH) process at the anode-body junction [40] seem to be the main limiting factors to extending the retention time. Some techniques have been explored to improve it, for example the half-ground-plane \(Z^{2}\)-FET [41] or the double ground-plane (Figure 3a). **Energy consumption**: The \(Z^{2}\)-FET DRAM current is only significant when writing or reading the '1'-state, see Figure 18. A high '1'-state read current is attractive for state discrimination. Therefore, optimization efforts have focused on the energy reduction for '1'-state programming. It has been demonstrated that it is possible to write the cell with low anode-voltage (\(\mathrm{V_{A}}\approx 0.4\) V), greatly reducing the current and practically suppressing the programming energy [42]. Energy and power consumption now occur exclusively during the readout of the '1'-state, with less than 1 pJ/bit per operation at 1 V and an even lower standby energy. Moreover, the '1'-state readout process regenerates the '1'-state condition, relaxing the need for periodic refreshing. The use of alternative materials with a narrow bandgap, such as germanium, is an attractive avenue towards reducing the operating voltage and, hence, the power consumption of \(Z^{2}\)-FET DRAM cells. This has been demonstrated through numerical simulations [43]. **Temperature dependence**: Tests under elevated temperature conditions have proven that successful operation is possible, although some minor modifications may be required.