# A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds
### Main Contributions  
Two fundamental circuits are built in this work: one is the custom 8T PUF in Figure 1a; the other is the two-phase power gating cell in Figure 1b. A single-phase power gating cell is also implemented for comparison, as shown in Figure 1c. Based on these circuits, a power-gated 8-Transistor (8T) PUF architecture presented in Figure 2 is developed to alleviate some of the aforementioned issues. This power gating structure can also be utilised with the other bistable PUFs to improve PUF performance. The main contributions are listed below:  
* **The custom 8T PUF facilitates fast statistical measurements and improves security:** The 8T PUF maximises physical mismatch and eliminates data retention swiftly for  
Figure 1: Schematics of (**a**) 8T PUF cell, (**b**) two-phase power gating cell and (**c**) single-phase power gating cell.  
Figure 2: A two kilo-bit power-gated PUF architecture.  
high-speed evaluations and countering security attacks [14; 15; 16; 17; 18]. It does not require a special process for high-density SRAM manufacturing and can be fabricated in the same process as microcontrollers (MCUs). Fast statistical measurements can be performed on this platform to extract raw PUF bits. These raw bits are then processed and marked onto a bitmap to identify the PUF cell instability. These unstable bits, which are discarded in the references, can be used for _True Random Number_ generation or as part of the PUF _Response_[19; 20; 21; 22].
* **Two-phase power gating improves PUF performance and security whilst saving energy and delaying ageing:** This newly developed power-switching process includes three stages: 1. Reset stage: The reset stage drops the virtual power supply (vddv), quickly drains the remaining current and eliminates retained data. 2. Phase I power-up stage: Phase I slowly powers up the chosen PUFs to prolong the metastability-resolving process in the hope of reducing EMI and crosstalk amongst PUF cells [23]. 3. Phase II power-up stage: Finally, phase II speeds up the voltage ramp-up process. In addition, different combinations of power gating parameters can curb the in-rush current, thus shielding it from side channel attacks, e.g., Differential Power Analysis (DPA) [14; 15]. Moreover, the 8T PUF cells are partitioned into rows, and only the chosen rows will be powered up during the reading process. Besides saving energy proportionally, PUF cells without a power supply cannot be read out and are protected from security attacks. Furthermore, power gating can delay the transistor ageing effect.
* **A new data processing method marks out most errors:** The high-speed measurements not only reduce the time needed for the enrolment phase in manufacturing but also enable multiple evaluations in the key regeneration phase. Since the positions of the unstable PUF cells drift away in different voltage or temperature corners, and extreme corners cause more unstable PUF cells, TMV plus Dark-bit masking in nominal conditions [7; 8; 9] is insufficient. We propose a new data processing method here. First, during manufacturing, Multiple TMV under nominal conditions and extreme corners are used to mark out unstable readings and flipped readings as Dark bits onto a bitmap. Then, during field usage, the Dark bits are discarded first and followed by the regeneration of Secret Keys using fast TMV. Finally, with a significantly reduced number of error bits remaining, an error correction technique with a lower hardware penalty will be applied. When the BER drop close to 0%, the hardware penalty for error correction can be reduced significantly. The stability levels of PUFs are also recorded on the bitmap. These unstable readings can be used further for True Random Number generation or as part of the PUF _Response_.