## 1 Introduction  
In this work we propose minimizing power consumption of digital receiver depending on the quality of signal received. The version of IEEE 802.15.4-2006 at \(2450\) MHz with DSSS physical layer with OQPSK modulation specifies \(65\) dB possible variation in the received signal strength. We take advantage of this large variation by designing a power scalable baseband architecture, which adapts itself to the variation in signal and interference levels. The digital section adapts the word length (\(Q_{dig}\)) and sampling frequency (\(f_{s}\)). To make the receiver adaptive and low power, various design techniques are proposed in this paper. The key features of this power scalable receiver are interference detector and SNR estimator (IDSE), variable tap and variable coefficient FIR filter, an adaptivity control unit and an adaptation procedure. Minimizing power consumption of the receiver has been done by various authors in various ways. Varying \(f_{s}\) of the receiver to minimize power requires varying number of taps in the FIR filter. Authors in [1] have proposed a variable tap FIR filter based on approximate filtering to reduce power. In doing so, authors have demonstrated power reduction by a factor of 10. Besides varying number of taps to save power, we have used minimum resolution coefficients for FIR filters to save power. Author in [2] controls the resolution of analog-to-digital converter (ADC) in receiver and digital-to-analog converter (DAC) in transmitter. The ADC resolution is controlled depending on signal-to-noise and signal-to-interference ratio and resolution of DAC is controlled based on crest factor of modulation scheme. The author has not suggested any way to measure signal-to-noise and signal-to-interference ratio. Authors in [3] have proposed reconfigurable radio for MIMO wireless systems. Authors have emphasized on optimizing number of operations, latency requirements and the architecture of signal processing elements to minimize complexity of the MIMO signal processing. Number of antennas and modulations levels are reconfigurable in the systems proposed in [3]. Adaptive word length control is used to implement an OFDM based low power wireless baseband processing system [4]. OFDM processing essentially consists of filtering, followed by an FFT engine and then an equalization block. The Error Vector Magnitude (EVM) of the received signal is continuously monitored, to adjust the word length. If EVM is above a threshold, the word length is increased to improve precision and conversely, for good EVM (low error rate), the word length is reduced. Our approach for receiver design incorporates controlling the amplitude quantization and sampling frequency depending on the SNR levels and interference presence. Our approach of scaling power by varying \(Q_{dig}\) and \(f_{s}\) applies the concepts of adaptive signal processing to minimize power. Traditionally, adaptive signal processing is well known for minimizing error of signal processing structures [5], whereas our objective is to minimize power while keeping the error criteria as a constraint in the optimization formulation. An adaptation procedure is proposed to facilitate adaptation in packetized communication. Now let us look at power consumption numbers in present day communication receivers on CMOS technologies. In [6] authors have reported IEEE 802.15.4 receiver (CC2420 chip) consuming \(20\) mA when active with \(1.8\) V power supply. Low power analog front end design for IEEE 802.15.4 has been proposed in a few papers [7,8]. In [7], authors proposed a front end design in \(0.18\)\(\mu\) CMOS technology that consumes \(4.32\) mW, whereas in a more recent paper the authors in [8] proposed a front end in 90 nm technology that consumes \(3.6\) mW when active. Authors in [9] have discussed power consumption of various wireless technology for WPAN applications. As mentioned, authors in [9] say that the power consumption of wireless devices scales with the data rate.