# Design and Simulation of Low-Orbit Satellite Broadcast Signal Receiving and Processing Terminal
## 5 Conclusions and Future Work  
This solution combines digital beamforming technology, time-frequency domain interference suppression technology, three-loop capture and tracking technology that introduces a bit synchronization loop, and RS decoding and other technologies based on FPGA digital processing board, using the JFM7K325T chip to design the FPGA, which is designed by Fudan Microelectronics and contains a large number of DSP units, which are mainly used for multi-beam digital down-conversion and phase shift processing, narrow-band anti-interference, etc. And use the JFM7K325T chip to perform simulation design of the whole low-orbit satellite broadcast signal receiving and processing terminal. The simulation results show that the beamforming gain of the whole machine reaches 14-15 dBic;  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Bit Error Rate \(\mathrm{P_{b}}\)** & **Soft Verdict Coding Gain (dB)** & **Hard Verdict Coding Gain (dB)** \\ \hline \(10^{-3}\) & 3.24 & 5.15 \\ \(10^{-4}\) & 4.17 & 6.06 \\ \(10^{-5}\) & 4.68 & 6.50 \\ Upper bound & 5.00 & 7.00 \\ \hline \hline \end{tabular}
\end{table}
Table 4: \(\mathrm{E_{B}}/\mathrm{N_{0}}\) and decision gain under several typical bit error rates.  
Figure 25: Relationship curve between bit error rate and normalized signal-to-noise ratio.  
the interference-to-signal ratio reaches 57 dB when resisting interference from a single frequency band, and the interference-to-signal ratio reaches 47 dB when resisting interference from three frequency bands; in large dynamic scenarios, the bit synchronization loop can complete bit synchronization within 60 ms, with a bit error rate of 0; the coding gain can reach 7 dB.  
The low-orbit satellite broadcast signal processing terminal designed in this scheme still has room for improvement: 1. Currently, the three channels of a single frequency point have occupied about 85% of the FPGA logic resources, which is close to saturation. In the future, the process of capture, tracking, and decoding will be considered for transplanting to the ARM part. In this case, the SoC can replace the Z7030 chip with the Z7045 chip with larger logical resources to improve the computing speed and processing capabilities of the entire machine; 2. The algorithm of the bit synchronization loop can continue to be improved, reducing the time required for bit synchronization in large dynamic scenarios.  
Literature search: [PERSON] and J.L.; Theoretical methods: [PERSON] and J.L.; Software design: [PERSON] and Z.W.; Graph creation: [PERSON] and [PERSON]; Data collection: [PERSON] and [PERSON]; Data analysis: [PERSON] and [PERSON]; Writing--original draft: [PERSON]; Writing--review & editing: [PERSON] and [PERSON]; Supervision and guidance: [PERSON]. All authors have read and agreed to the published version of the manuscript.  
This work was funded by Shandong Provincial Natural Science Foundation (ZR2021 MD127), research on multi-source information fusion and high-precision positioning technology in complex environments.  
Data Availability Statement: Data is contained within the article.  
The authors declare no conflict of interest.