## 3 Methodology
### GPU Mapping Implementation of SAR-SIFT Algorithm
The number of kernel invocations is reduced from \(S+1\) to 1, saving kernel invocation time where kernel code is copied to device memory, and streaming multiprocessors (SM) and streaming processors (SP) are initialized. Additionally, there is minimal code overhead in the combined kernel function. The scheduler optimizes processor utilization, contributing to performance improvement. Similarly, the multi-scale SAR-Harris feature response obtained based on the multi-scale ratio gradient is directly implemented in CUDA. Parallel processing is achieved by assigning a thread to each pixel of the feature response image. It can be observed that the computation kernels for each scale in the scale space are independent of each other. Thisstep also employs a combined kernel optimization, simplifying the \(S+1\) kernels into a single kernel. 2. GPU Accelerated Key Point Detection  
In this processing stage, it is necessary to detect local extrema in the feature response images at different scales within the SAR-SIFT scale space. A total of N kernels are utilized, where each thread examines the extrema of a single pixel in the feature response image. The challenge in this processing stage involves storing all detected key points. Before executing the kernels, the number of key points generated by the kernels and the order of generated points are uncertain. In most sequential implementations, using a global array in device memory to store key points and a global index variable to track the number of key points found is a common approach. However, due to synchronization issues, this method cannot be directly applied to the GPU. 3. GPU-Accelerated Key Point Orientation Assignment and Feature Description  
The key point orientation assignment and feature descriptor construction can be achieved using a single kernel function. This is because both steps require the same gradient information around key points, considering the uneven distribution of texture features in SAR images. The algorithm utilizes the gradient information of surrounding \(96\times 96\) pixels to set the main orientation and construct feature descriptors for key points. The number of thread blocks in the kernel is determined by the number of key points detected in the previous step, with each block responsible for setting the main orientation and constructing features for one key point. Each thread block is configured with \(97\times 97\) threads, where each thread computes the gradient information for one pixel. Firstly, threads within a block load the surrounding \(97\times 97\) pixels of key points into shared memory, which is implemented using a caching mechanism to reduce memory access latency, and synchronization points are used to ensure that all threads have completed loading. Secondly, the gradients of the surrounding \(96\times 96\) pixels of key points are calculated. Implementing histogram creation on the GPU is challenging due to simultaneous updates to the shared gradient direction histogram by all threads, introducing synchronization issues. In such cases, the use of atomic instructions significantly degrades performance due to a low number of bins and high conflicts between threads. A parallel histogram creation technique utilizes multiple copies of histograms updated by different parallel elements [28]. These partial histograms are then merged to form the final histogram. This study has adapted this technique for computing the orientation histogram. To determine the maximum value of the histogram, a well-known GPU reduction algorithm employing the MAX operator is employed.