## 4 A Survey on FPGA-Based Sensor Systems
### Safety and Security Applications for Sensor Nodes  
This section is composed of sensor nodes focusing on safety ([84; 85; 86]) and security implementations for sensor node architectures ([25; 26; 27; 30; 87; 88]). In [84], [PERSON] presented the design of a sensor node based on an FPGA Altera Cyclone II (EP2C5) in order to be used in surveillance of a fabrication zone of aircrafts. The node is composed of an NRF2401 transceiver (2.4 GHz) and the system is based on a Nios-II soft-core. However, the author did not provide energy consumption results. [PERSON] _et al._ presented a WSN [85] focusing on surveillance and motion detection based on two levels of nodes. First level nodes consist of a Microchip microcontroller coupled with proximity and ultrasonic sensors. The microcontroller sends the data via 433 MHz ASK radio link to the second layer of nodes. These nodes comprise a Cyclone II (EP2C3) FPGA which performs motion detection, edge detection and image compression. The authors did not provide energy consumption results. In [86], the authors presented the implementation of a people counter system accelerated on an IGLOO FPGA for WSN applications. The FPGA performs a Dijkstra-based algorithm at 10 MHz and consumes 5 mW. Several cryptographic accelerators have been proposed for sensor nodes based on FPGAs whose applications range from acceleration based on embedded resources to partial reconfigured ones. Elliptic Curve Cryptography is usually proposed as key agreement protocol in WSNs since it utilizes smaller keys, is faster and consumes less energy in comparison with other public key cryptosystems. In this respect, [PERSON] _et al._[30] presented a cryptographic accelerator for Elliptic Curve Cryptography (ECC) that supports various types of NIST curves via partial reconfiguration using the sensor node presented in Section 4. Moreover, [PERSON] _et al._ proposed the implementation of an ECC core for binary fields on an IGLOO FPGA (AGLN250V2) for a sensor node clocked at 27 MHz [89]. Besides that, [PERSON] _et al._ presented a survey of hardware implementations, ASIC and FPGA, focusing on WSN [87]. Also, [PERSON] _et al_. reviewed the state-of-the-art on AES designs focusing on sensor nodes [90]. The IEEE 802.15.4 standard [3] provides cryptographic primitives in the MAC layer in order to ensure confidentiality, authentication and replay protection. Likewise, several variations of AES [91] in counter-mode (CCM) can be utilized in ascending levels of security [92]. In this respect, several authors have proposed FPGA implementations of the IEEE 802.15.4 security suite. [PERSON] _et al_. presented a compact AES architecture in an Altera Cyclone I (EP1C4F) [28]. Clocked at 50 MHz, the core consumes 98.92 mW and can process up to 57 Mbps. The authors compared the features of the core with a software implementation of AES in an ARM966E-S microprocessor which consumes 140 mW and processes 16 Mbps, clocked at 200 MHz. Likewise, [PERSON] _et al_. [29] presented an accelerator for 802.15.4-based sensor nodes. It consists of a compact AES core coupled with a Content Address Memory (CAM) which stores the keys and addresses the nodes in the WSN. It was implemented in an Altera Stratix I (EP1S10F), clocked at 3 MHz. It has a throughput of 600 kbps and consumes 29 mW. Finally other cryptographic primitives have been proposed for sensor nodes, such as hyperchaos encryption (Spartan 3E, XC3S500E) [25], Skipjack and involutional block ciphers [27, 88]. [PERSON] _et al_. proposed to implement two involutional block ciphers (particularly KHAZAD and BSPN) in a low-cost Spartan-3 FPGA (XC3S200) [27]. Given that they are involutional, that is, using the same algorithm for encryption and decryption, the authors claimed that they are suited to be implemented in area-constrained systems. The implementations have been compared with implementations in a low-cost microcontroller, an 8-bit ATMega 128. Likewise, the BSPN algorithm consumes 20.45 mW (5.12 nJ) and KHAZAD 32.39 mW (9.60 nJ) in the FPGA _versus_ 1,373 nJ in the ATMega per block.