# Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques
## 4 Design Example: Super Class AB QFG Amplifier in a 130 nm CMOS Process
### Circuit Analysis  
Routine small-signal analysis of the circuit of Figure 8a leads to a transconductance  
\[G_{m}\approx g_{m1A}[1+g_{m3A}(R_{DS}||r_{o2B})] \tag{5}\]  
with \(g_{mi}\) and \(r_{ol}\) as the small-signal transconductance and output resistance of transistor \(\mathrm{M_{i}}\), respectively, and \(R_{DS}\) as the resistance of triode transistors \(\mathrm{M_{R1}}\) and \(\mathrm{M_{R2}}\), which is  
\[R_{DS}\approx\frac{1}{\beta_{R1,2}\left(V_{RES}-\sqrt{\frac{I_{B}}{\beta_{3B} }}-V_{SS}-2V_{TH}\right)} \tag{6}\]  
where \(\beta_{i}=\mu C_{ox}(W/L)_{i}\) is the transconductance factor of transistor \(\mathrm{M_{i}}\). The GBW is \(\mathrm{GBW}=G_{m}/(2\pi C_{L})\), with \(G_{m}\) defined in Equation (5) and \(C_{L}\) as the load capacitor. The small-signal gain is \(G_{m}\cdot R_{out}\), with \(R_{out}=g_{m8}r_{o8}r_{ol0}\) 1 \(|\left[g_{m6}r_{o6}(r_{o4A}\mid r_{o2A})\right]\) as the output resistance of the amplifier. Using the simple MOS square law, an approximate expression can be found for the SR:  
\[SR\approx\frac{\beta_{3A,AA}}{2C_{L}}\left(\sqrt{\frac{\beta_{1B,2B}}{2\beta_{ 3B,4B}}}A+\frac{R_{DS}\beta_{1B,2B}}{4}A^{2}\right)^{2} \tag{7}\]  
with \(A\) as the differential input signal amplitude. Note that \(SR\) is not limited by the bias current, as expected from a class AB amplifier. Practical values of \(SR\) are, however, lower, due to nonideal effects not considered in Equation (7).  
Regarding thermal noise and noting that \(g_{m1A}=g_{m1B}=g_{m1C}=g_{m2A}=g_{m2B}=g_{m2C}\), \(g_{m3A}=g_{m4A}\), \(g_{m3B}=g_{m4B}\) and \(g_{m9}=g_{m10}\), the input-referred noise density is  
\[\begin{array}{l}V_{n,in}^{2}=\frac{2\delta_{R2}T}{S_{m1A}}(2+\frac{S_{m4B}} {S_{m1A}}+\frac{S_{m1A}}{S_{m1A}R_{DS}}+\frac{1}{S_{m1A}g_{m3A}R_{DS}^{2}}+ \frac{g_{m9}}{g_{m1A}g_{m3A}^{2}R_{DS}^{2}}\\ \qquad\qquad\qquad\qquad\qquad\qquad+\frac{1}{g_{m3A}^{2}R_{DS}^{2}})\end{array} \tag{8}\]  
with \(k_{B}\) as the Boltzmann's constant, \(T\) as the absolute temperature, \(g_{ml}\) as the transconductance of the transistors implementing the \(I_{B}/2\) current sources and \(\delta\) as a parameter that varies from 1/2 to 2/3 from weak inversion to strong inversion. Note that transistors in the output branch have little influence on the input-referred noise, due to the large gain, according to theoretical expectations.  
Note, also, that decreasing bias voltage \(V_{RES}\) increases \(R_{DS}\) and, hence, increases gain, GBW and SR and reduces input-referred noise. Unfortunately, it also reduces phase margin, which can be approximated by  
\[PM\approx 90^{\circ}-\tan^{-1}\bigg{(}\frac{GBW}{f_{pND}}\bigg{)}\approx 90^{ \circ}-\tan^{-1}\bigg{[}g_{m1A}g_{m3A}(R_{DS}||r_{o2B})^{2}\frac{C_{X}}{C_{L}} \bigg{]} \tag{9}\]  
where \(f_{pND}\)\(\approx-1/[2\pi(R_{DS}\mid r_{o2B})C_{X}]\) is the frequency of the lowest nondominant pole, and \(C_{X}\) is the parasitic capacitance at the nodes where the gates of M\({}_{3A}\) and M\({}_{4A}\) are connected. Hence, a tradeoff between gain, GBW, SR, input-referred noise and stability exists for a given \(C_{L}\). Tuning \(V_{RES}\) allows for optimally balancing these parameters and compensating for PVT variations.