# Efficient Implementation of Matrix-Based Image Processing Algorithms for IoT Applications
## 2 The Algorithm Description
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline \multicolumn{1}{c}{**Noised Image**} & \multicolumn{2}{c}{**DCT Reconstructed Image**} & \multicolumn{2}{c}{**CS-RANSAC**} \\  & & & & **Reconstructed Image** \\ \hline
**PSNR** & **SSIM** & **PSNR** & **SSIM** & **PSNR** & **SSIM** \\ \hline
20.48 & 0.36 & 24.04 & 0.46 & 28.14 & 0.63 \\ \hline
17.14 & 0.21 & 20.91 & 0.29 & 26.92 & 0.58 \\ \hline
14.29 & 0.15 & 18.03 & 0.21 & 25.41 & 0.71 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: DCT denoising vs. CS-RANSAC denoising. Figure 4: Performance evaluation for impulsive noise (MATLAB implementation). Figure 3: Performance evaluation for large noise (MATLAB implementation). A more detailed performance evaluation that proves the comparable or better performance of CS-RANSAC compared with other existing methods (BM3D, TV-L1) is given in [13]. In our paper, we evaluate the algorithm performance, in various implementation, to give a performance comparison between these implementations and to prove the possibility to implement, with good performance, relative complex image processing algorithms using microcontrollers in IoT applications. ## 4 The Microcontrollers' Implementations

Two 32-bit fixed-point microcontroller (e.g., Blackfin BF5 xx, and MAX7800x, Analog Devices, Analog Devices Inc./Maxim Integrated, USA, Digi-Key) implementations are proposed in this section. The Blackfin architecture is designed for multimedia applications, the accessible memory is up to hundreds of Mbytes, and the processor clock frequency is up to 750 MHz. The instruction set is powerful (arithmetic instructions, multiplications with accumulation, dual and quad instructions, hardware loops, multifunction instructions) [20; 21]. The MAX7800x chip is a dual core ultra-low power microcontroller with an ARM Cortex M4 processor with FPU up to 100 MHz with a 16 KB instruction cache, 512 KB flash memory, 128 KB SRAM, and a RISC-V Coprocessor up to 60 MHz for digital signal processing instructions. There are many interfaces (general purpose IO pins--GPIO, serial ports, analog to digital convertor (10 bit, 8 channels), neural network accelerator optimized for deep convolutional neural networks (442k 8-bit weight capacity, network depth up to 64 layers with up to 1024 channels per layer), power management for battery operations, real time clock, timers, AES 128/192/256, and CRC hardware acceleration engine. The ARM Cortex-M4 with FPU processor CM4 is well suited for the neural network system control and combines high-efficiency signal processing functionality with low energy consumption. The 32-bit RISC-V coprocessor is dedicated for ultra-low power consumption signal processing. The instructions set include: four parallel 8-bit additions/subtractions, floating point single precision operations, two parallel 16-bit additions/subtractions, two parallel MACs, 32- or 64-bit accumulate, signed, unsigned, data with or without saturation. A convolutional neural network (CNN) unit is included in the MAX7800x chip. A more detailed architecture description of MAX 7800x, how the proposed implementation uses the CNN accelerator, and ARM and RISC V cores are shown in the next section. The above-presented algorithm was written in C programming language, using the integrated development environment Visual DSP ++ 5.1 and Maxim Eclipse SDK. The code was automatically optimized for speed (hardware loops, interprocedural analysis) [22]. The size \(S\) of set \(S\) influences the performance of the algorithm. The total number of combinations (randomly chosen) for RANSAC algorithm are \(C_{N}^{S}=\frac{N(N-1)...(N-S+1)}{S(S-1)...1}\). If \(S\) is small, the number of combinations is large, and the algorithm may converge in many iterations (especially for large noise). If \(S\) is large, the number of combinations is smaller, then the RANSAC algorithm has a smaller number of iterations.