# Arrayable TDC with Voltage-Controlled Ring Oscillator for dToF Image Sensors
## 3 TDC Circuit Design and Implementation
During the effective high-level phase of EN_VCO, the MN1 transistor conducts, and when the IN + voltage at the input gate terminal of the MN2 transistor is high, it conducts deeply. The OUT-voltage is quickly pulled down, and at this time, the gate voltage of the MP2 transistor synchronously decreases. The MP2 transistor opens and pulls up the OUT + node voltage to a high level. When the IN-voltage is low, the increase in OUT + voltage causes the MP1 transistor to turn off. At this time, it competes with the MN2 transistor and MP1 transistor for current at the OUT-node, accelerating the OUT-voltage to eventually stabilize at a low level. Using MN1 tubes to form a tail current source to control the charge and discharge current path can effectively suppress the effects of non-ideal factors such as process angle deviation, device misalignment, temperature offset, noise interference, and substrate coupling effects on the circuit. It can significantly improve the circuit's ability to suppress common-mode noise in power supply, and its power supply suppression bit performance is significantly improved compared to traditional structures. Specter simulation results are shown in Figure 4. The phase noise is \(-100.64~{}\mathrm{d}\mathrm{B}\mathrm{c}/\mathrm{H}\mathrm{z}\) and \(-124.88~{}\mathrm{d}\mathrm{B}\mathrm{c}/\mathrm{H}\mathrm{z}\) at 1 MHz and 10 MHz, respectively, and the split-phase clock jitter is at 3.24 ps. The VCTRL voltage provided by the PLL controls the oscillation frequency of the VCRO and thus the resolution of the TDC [19]. The variation in VCTRL voltage concerning the oscillation frequency of VCRO is scanned by simulation after the tt process angle at 25 \({}^{\circ}\mathrm{C}\). The simulation results are shown in Figure 5; according to the changing relationship between the oscillation frequency and resolution of VCRO and VCTRL voltage, the average gain of VCRO during the changing of VCTRL voltage in 0 V-1.35 V is 622 MHz/V. To obtain the VCTRL control voltage, it is necessary to provide a voltage after locking the frequency of the PLL; the PLL's oscillator structure and the TDC's VCRO keeping in line can improve the linearity of the TDC's VCRO by more than 99% linearity [20]. This control voltage given by the PLL can effectively compensate for the effect of PVT variations on the TDC resolution. By adjusting the VCTRL voltage (0 V-1.35 V), the corresponding resolution variation can be achieved in the range of 139 ps-2.3 ns. With the continuous improvement of TDC time resolution and sampling clock frequency, the problem of sampling metastability occurs, and the bit error rate also increases, seriously affecting the accuracy of TDC [10; 21]. This phenomenon is due to the random arrival of photons, and the generated STOP signal pulse is also uncertain. When the rising edge of the input signal CK does not meet the sampling conditions, it is impossible to accurately determine whether photons have arrived. The transistor level structure of the D-type flip-flop using TSPC dynamic logic structure is shown in Figure 6.  
Figure 4: Simulation results of phase noise (**a**) and split-phase clock jitter of VCRO (**b**). \[H_{delay}(s)=\frac{-A}{1+\frac{s}{\omega}} \tag{2}\]0 \(K_{VCO}\) gain curve graph. When the edge of the input signal and the edge of the sampling clock satisfy the timing competition condition, a transistor-level conflict will occur inside the D flip-flop, causing MN3 located on the same pull-down path to turn off and MN2 to turn on. Therefore, the control line S is at an uncertain intermediate potential, causing the output of the final D flip-flop to be unable to stabilize accordingly. The probability of metastable output occurrence is closely related to the process used by the trigger and the rising speed of the input edge. Usually, there is a strong positive correlation between the probability of metastable failure and the integrity of process nodes and signals.