# Error Mitigation Methods for FSM Using Triple Modular Redundancy
## 1 Introduction  
The growing complexity of digital systems and the rising demands for their flexibility (ease of reconfiguration) mean that programmable logic circuits are playing an ever more important role. The leading devices in this group are FPGAs (Field Programmable Gate Arrays). Their considerable logic resources allow the easy implementation of complex digital systems at relatively low cost. The short prototyping time for circuit solutions cannot be underestimated either. A number of advantages of FPGA devices have made them widely used in industries where fast signal processing is required. It appears that FPGAs are also applied in areas such as medicine, the military, nuclear power, and space industries, where they perform critical functions [1, 2]. In each of these areas, the reliability of the implemented system is crucial; oftentimes, as in military or space applications, mobility is also vital. Mobility in this context is understood as maximizing battery life, which is directly related to the energy efficiency of the implemented systems. Of course, reliability and energy efficiency are interrelated (reducing the amount of heat emitted by a device, especially thermal stress, reduces the probability of failure). In the applications mentioned earlier, one of the main sources of failure or malfunction is the effect of ionizing radiation. Especially in the area of space applications, the problem of radiation effects on FPGAs is extremely important [3]. Radiation affects semiconductor devices in two ways: Single Event Effects (SEEs) and dose effects. Dose effects correspond to a permanent change in selected parameters as a result of prolonged radiation exposure (prolonged exposure to ionizing radiation causes degradation of the crystal lattice, which affects the resistivity of the semiconductor; it is also possible that the material itself begins to accumulate a positive electrical charge), while SEEs are related to phenomena resulting from the effect of a particle on a logic structure and can cause a change in the value of individual bits [4]. Mitigation techniques include appropriate manufacturing processes at the physical level [5; 6] or appropriate digital circuit design (FPGA implementation) [3; 7; 8]. The primary mitigation method for configuration memory is scrubbing--memory is'refreshed' from an external source [9; 10; 11; 12]. Dynamic and partial reconfiguration can help to detect, isolate, and recover from SEU faults [13]. In case of implemented design, there are also mitigation techniques like Error Checking and Correction (ECC) [14], which most commonly uses the Hamming code [15] or the Reed-Solomon code [16]. Sometimes, elements of FPGAs are used for special purpose--BlockRAM as a sensor [17]. Redundancy is a basic, albeit costly, technique for increasing the probability of correct system operation. It involves for example duplicating selected blocks several times in order to perform exactly the same task. If the duplicated modules operate in exactly the same way at the same time (the state of their outputs is the same), this means that no SEE-induced errors have occurred in the operation of the modules. However, if the signals on their outputs are different, this means that an error must have occurred in one of the duplicated modules. Triple modular redundancy (TMR) is commonly used in practice--three identical and independent modules perform the same function. The outputs of these modules are attached to the majority voting circuit, so that the state of the module outputs can be uniquely determined during the voting process (a single fault is assumed). TMR is the subject of a number of scientific papers [18; 19; 20; 21; 22]. Fault-tolerant systems without redundancy are also designed [23]. Naturally, the use of TMR results in a significant increase in the number of logical resources used, and thus, in power dissipation.