## 1 Introduction  
Designing digital circuits to meet specific requirements is a challenging task that demands significant effort from designers. This process is often time-consuming, and achieving an optimal design is not always guaranteed. To aid designers, EDA tools are used to enhance efficiency and produce more optimised circuits [1]. Some EDA tools incorporate Machine Learning (ML) techniques [2] or other forms of artificial intelligence [3, 4] to assist in circuit design. However, current tools do not typically employ Evolutionary Algorithms (EA) to generate various circuit design solutions. EAs are search-based techniques inspired by Darwinian evolutionary principles. They apply crossover and mutation, each with a set probability, to evolve toward an optimal solution for the given problem, mimicking natural selection to gradually enhance solution quality. The concept of genetic search was introduced by [PERSON] in 1948 [PERSON] (1948). Since then, the field of EAs has grown extensively, with applications in areas such as symbolic regression ([PERSON], 2016) and circuit design ([PERSON], 2016). Prominent EA methodologies include Genetic Algorithms (GAs) ([PERSON], 2016), Genetic Programming (GP) ([PERSON], 2016), GE ([PERSON], 2016), and Evolutionary Strategies (ES) ([PERSON], 2016). Evolvable Hardware (EH) refers to using EAs to evolve electronic circuits or their components. EH can be categorised into intrinsic and extrinsic evolution. Intrinsic evolution involves using hardware, such as Field Programmable Gate Arrays (FPGAs), to evolve and test solutions directly on the hardware in real time ([PERSON], 2016). In contrast, extrinsic evolution relies on simulation tools to evolve and test circuits solely in a computer environment ([PERSON], 2016). FPGAs are used to prototype digital circuits, which are specified at design time using HDLs, such as Very High-Speed Integrated Circuit HDL (VHSIC HDL or VHDL), Verilog, and SystemVerilog (SV), to describe circuit behaviour at different levels of abstraction. These languages enable designers to define circuits at both the gate level, using Boolean equations, and at the behavioural level, which is closer to high-level programming and includes constructs like loops and conditionals. The synthesis process then translates these descriptions into a gate-level netlist, which serves as the blueprint for physical implementation. Digital sequential circuits, which differ from digital combinational circuits (detailed in Section 2) in their ability to store and manage state information, are critical in complex digital systems. These circuits are modelled using FSMs, which help represent the data flow and state transitions based on inputs. FSMs can be classified into two main types: Mealy machines and Moore machines (detailed in Section 2). In this work, we have evolved the MSD as a Mealy machine (shown in Figure 1) due to its ability to be highly responsive. Figure 1: Mealy FSM of the single-input double-output Gold MSD. To the authors' knowledge, no such MSD has been evolved in the literature using the evolutionary technique used in this work. As discussed in Section 4.1, GE is utilised to evolve this MSD and generate automatic HDL solutions. GE, a variant of GP that creates programs or expressions in virtually any syntax, uses context-free Backus-Naur Form (BNF) grammars for genotype-to-phenotype mapping. BNF is a formal notation used to describe the syntax of programming languages and data structures. It consists of production rules that define how non-terminal symbols can be expanded into sequences of terminal symbols and other non-terminals. More detail is given in Section 4.1. These grammars allow the specification of rules that guide the evolution process. GE has been highly successful in various applications, including symbolic regression [14], classification [15], and particularly in automatic circuit design, whether combinational [16] or sequential [17], making it an ideal choice for this study.