## 6 Conclusions  
In this paper, a dual-channel data storage and access method is designed and implemented for spaceborne SAR real-time processing. The method proposed ensures that the data bandwidths in the range direction and azimuth direction achieve complete equilibrium, and reduce the use of on-chip cache resources. In addition, based on the above method, a dual-channel data controller is implemented by using Xilinx XC/VX690T FPGA. The experimental results show that the read data bandwidths in the range direction and azimuth direction can both reach 10.24 GB/s, the reading efficiency is 80% which an increase of more than 6.7 times that of the conventional method. Additionally, write data bandwidths in the range direction and azimuth direction can both reach 8.45 GB/s, the writing efficiency is 66% which an increase of more than 7.8 times that of the conventional method. This paper also compares several existing FPGA-based implementations to verify the superiority of the data controller proposed. The method proposed can also be extended to other two-dimensional image real-time processing scenarios, such as FPGA-based Un-inhabited Aerial Vehicle Synthetic Aperture Radar (UAVSAR) [18, 39] and Convolutional Neural Networks (CNNs) [40, 41, 42], etc. In the future, we will conduct research on multi-channel SAR data processing, multi-mode integrated SAR processing, and new efficient algorithms that are suitable for real-time processing in order to meet new remote sensing application requirements.  
Conceptualization, G.W. and H.C.; methodology, G.W. and Y.X.; software, G.W., H.C. and Y.X.; validation, G.W.; formal analysis, G.W.; investigation, G.W. and Y.X.; resources, H.C. and Y.X.; writing--original draft preparation, G.W.; writing--review and editing, G.W., H.C. and Y.X.; supervision, Y.X.; project administration, H.C.; funding acquisition, H.C. and Y.X. All authors have read and agreed to the published version of the manuscript.  
This research was funded by the National Natural Science Foundation of China under Grant No. 91738302.  
This work was supported by the Chang Jiang Scholars Program under Grant T2012122 and the Hundred Leading Talent Project of Beijing Science and Technology under Grant Z141101001514005.  
The authors declare no conflict of interest.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline  & **Ours** & [34] & [33] & [32] & [31] & [30] \\ \hline Data Granularity & 16,384 \(\times\) 16,384 & 16,384 \(\times\) 16,384 & 16,384 \(\times\) 16,384 & 16,384 \(\times\) 16,384 & 8192 \(\times\) 8192 & 4096 \(\times\) 4096 \\ FPGA & Xilinx & Xilinx & Xilinx & Xilinx & Xilinx & Altera DE4 \\ DDR3 channel & 2 & 2 & 1 & 1 & 1 & 2 \\ Range access & 10.24 GB/s & 8.3 GB/s & 4.8 GB/s & 6.0 GB/s & - & - \\ bandwidth & 10.24 GB/s & 9.62 GB/s & 4.8 GB/s & 2.37 GB/s & - & - \\ Range access & 80\% & 69\% & 74\% & 93.75\% & - & 83\% \\ Azimuth access & 80\% & 80\% & 74\% & 74\% & - & 83\% \\ efficiency & 0.43 s & 0.45 s & 0.83 s & 1.18 s & 0.33 s & - \\ time & 4 & 4 & 4 & 8 & - & - \\ Cache RAM & 4 & 4 & 4 & 8 & - & - \\ number & Pipeline processing & & & & & \\ supported or not & Yes & No & No & No & No & No \\ \hline \end{tabular}
\end{table}
Table 6: Comparisons with previous implementations.