# A Feedback Control Method to Maintain the Amplitude of the RF Signal Applied to Ion Traps
## 3 FPGA-Based Feedback Control
### FPGA-Based Feedback Controller
#### 3.3.3 Design of the Controllers  
In Figure 5a, the step response of the unity feedback circuit of a plant is presented. We use a PI controller and lag compensator to implement an FPGA-based closed-loop control. The forms of unity feedback using a PI controller and lag compensator are presented in Figure 5b,c, respectively. To model the helical resonator, which is the plant of the feedback control, we measure the corresponding output signal, thus changing the frequency of the input of the helical resonator. The transfer function \(G(s)\) of the model is as follows:  
\[G(s)=\frac{3.117\times 10^{8}s+7.527\times 10^{15}}{s^{2}+2.244\times 10^{5}s+5. 373\times 10^{14}}=\frac{C(s)}{R(s)}, \tag{2}\]  
where \(C(s)\) and \(R(s)\) denote the output and input of the plant, respectively. The transfer function has two poles, \(s=-1.122\times 10^{5}\pm j\) 2.318 \(\times\) 10\({}^{7}\), and one zero \(s=-2.415\times 10^{7}\). The overshoot and settling time of the plant was calculated in MATLAB as 135.38% and 34.94 \(\mu\)s, respectively. By applying the step input to the plant, the steady-state error of the unity feedback can be obtained as follows:  
\[ \begin{array}{ll}e(\infty)&=\lim\limits_{s\to 0}\frac{sR(s)}{1+G(s)}\\ &=\lim\limits_{s\to 0}\frac{s(1/s)}{1+G(s)}=\frac{1}{1+\lim G(s)}=0.0666. \end{array}  \tag{3}\]  
We designed a PI controller and lag compensator that can reduce the overshoot and maintain the settling time at less than 1 s, which does not have much of an effect on the experiments with the ion traps, while at the same time having the lowest steady-state error. Figure 5: Conceptual diagrams of the unity feedback. (**a**) Unity feedback without the use of any controller. (**b**) Unity feedback using a PI controller. (**c**) Unity feedback using a lag compensator. As previously defined, a PI controller is a proportional-plus-integral controller that feeds an error (proportional) plus the integral of the error (integral) to a plant [24]. It uses a pure integrator that places the pole of the controller at the origin to reduce the error to zero. Moreover, it can be expressed as follows:  
\[U(s)=\bigg{(}K_{P}+\frac{K_{I}}{s}\bigg{)}E(s), \tag{4}\]  
where \(K_{P}\), \(K_{I}\), and \(E(s)\) denote the proportional gain of the controller, integral gain of the controller, and error signal, which is the difference between the set-point voltage and input of an ADC, respectively. Discretization is required to enable the use of the PI controller in Verilog. Using the backward Euler method, we replace \(s\) with \(\frac{1-z^{-1}}{T}\); the terms of (4) becomes:  
\[U(z)=\bigg{(}K_{P}+\frac{K_{I}T}{1-z^{-1}}\bigg{)}E(z), \tag{5}\]  
where \(T\) denotes the period of the cycle. Equation (4) can be expressed as follows:  
\[U[k]=U[k-1]+K_{P}E[k]-K_{P}E[k-1]+E[k]K_{I}T. \tag{6}\]  
When the PI controller is used, there are no gains to reduce the steady-state error and overshoot together. Further, we found the two gains that reduced the errors the most through trial and error. When the proportional gain and integral gain of the PI controller are 2.21 \(\times\) 10\({}^{-4}\) and 5.81, respectively, the overshoot and settling time are 135.41% and 34.94 \(\upmu\)s, respectively, with the least steady-state error. A lag compensator does not use a pure integrator; it places the pole near the origin [24] and takes the following form:  
\[U(s)=\bigg{(}\frac{s+z_{\mathrm{C}}}{s+p_{\mathrm{C}}}\bigg{)}E(s), \tag{7}\]  
where \(p_{\mathrm{C}}\) and \(z_{\mathrm{C}}\) denote the pole and zero of the lag compensator, respectively. Again, by applying the backward Euler method for discretization, the following can be obtained:  
\[U[k]=\frac{U[k-1]+(1+Tz_{\mathrm{C}})E[k]-E[k-1]}{1+Tp_{\mathrm{C}}}. \tag{8}\]  
\(\Big{(}\frac{s+z_{\mathrm{C}}}{s+p_{\mathrm{C}}}\Big{)}G(s)\) must be greater than 1 to achieve a greater reduction in the steady-state error when a lag compensator is added than when only the plant is used.