# A CMOS Multiplied Input Differential Difference Amplifier: A New Active Device and Its Applications
## 2 A Multiplied Input Differential Difference Amplifier  
This active device was developed because of the requirement for electronically controllable active blocks (integrators, amplifiers, etc. ), as well as the requirement for devices which provide a nonlinear operation of multiplication that is useful for analogue systems, as previously mentioned. A MIDDA partially operates as a voltage differencing differential difference amplifier (VDDDA), reported in [7; 8]. However, the multiplication of signals at the input section is a new feature which is not provided by VDDDA elements. Figure 1 explains the small-signal behaviour of a MIDDA. Figure 1a includes the block structure of a MIDDA. This topology was preserved in case of implementation using CMOS technology. The first subpart of a MIDDA, depicted in Figure 1a, is indicated by a MLT (multiplier) with a current output terminal. Note that our design was inspired by the solution presented in [9]. However, it was completely redesigned, and supplemented by an input linearization system and a boosting operational transconductance amplifier [1; 2]; this is visible in the full transistor structure, shown in Figure 2. When studying our design in detail, it is possible to observe some important differences to [9], as follows: (a) a redesign of the multiplying core, providing better dynamics and using larger bias current, allowing a wider range of the input voltage signal, as well as the speed and frequency bandwidth; (b) input linearizing attenuators, designed to improve applications with linear operations; and (c) an additional operational transconductance amplifier output section, required for the boosting of the output current and overall transconductance. The output operational transconductance amplifier was designed with cascaded current mirrors exhibiting auxiliary biasing (classical cascoded mirrors are not applicable in extremely low-voltage processes because of limited voltage space). Figure 1: Multiplied input differential difference amplifier (MIDDA) behavioural principles and subparts: (**a**) Symbol and internal sub-sections, ideal transfers; (**b**) Overview of the layout of cells (Cadence) of the fabricated prototype (0.31 mm\({}^{2}\)). A new solution, which utilizes a CMOS voltage differential difference buffer (VDDB), forming the second subpart of the MIDDA (also shown in Figure 1a), differs from the classical concept of a VDDDA [8]. As becomes obvious when studying the internal structure of the VDDB depicted in Figure 2, the CMOS circuitry is completely different, and much more complex, than the simple structures presented in [7; 8]). The key difference is that our solution is based on folded-cascode architecture, and includes both NMOS and PMOS differential pairs. The CMOS process C035 I3T25 (ON Semiconductor) 0.35 \(\upmu\)m (3.3 V) was chosen for the design and fabrication of the MIDDA prototype because it was the most suitable technology for our study. Figure 1b shows an overview of the layout of the fabricated device. Unfortunately, a microphotograph is not available due to technologically-unavoidable plating, placed above the fabricated die in I3T technologies. The MIDDA element has four voltage input terminals (\(Y\), \(X\), \(n\), \(p\)), one output terminal \(o\), and one auxiliary terminal \(z\). The operation of the device can be defined using the following simple inter-terminal relations: \(I_{z}=V_{X}\times V_{Y}\times k\), \(V_{o}=V_{z}-V_{n}+V_{p}\), where \(k\) (given by technological constants and dimensions of key transistors in internal structures) can be expressed using:  
\[k\cong\left(\frac{2R_{a}}{R_{b}}\right)^{2}\cdot\sqrt{2\frac{K_{Pn}}{2}\left( \frac{W}{L}\right)_{1,2,3,4}\frac{K_{Pp}}{2}\left(\frac{W}{L}\right)_{5,6}}R _{L}.5\sqrt{K_{Pn}4I_{bias1}\left(\frac{W}{L}\right)_{7,8}} \tag{1}\]  
Design constants are: \(K_{Pn}=136\)\(\upmu\)A/V\({}^{2}\), \(K_{Pp}=29\)\(\upmu\)A/V\({}^{2}\), \(V_{thr}=0.6\) V, and \(V_{thr}=-0.62\) V, for NMOS and PMOS in this I3T CMOS technology.