## 3 Simulation Results and Discussion  
### Analysis of Hump Behavior of Gate-Normal NWTFETs  
Figure 2 shows the simulated transfer curves of the gate-normal NWTFETs, which show clear hump behavior degrading SS and I\({}_{\text{on}}\). Two noteworthy phenomena are observed. First, hump behavior occurs and the SS is abruptly changed around V\({}_{\text{G}}\) = 0.7 V. In order to analyze the hump behavior, the electron BTBT generation rates in the gate-source overlap region are simulated at around V\({}_{\text{G}}\) = 0.7 V at V\({}_{\text{D}}\) = 0.5 V. As shown in Figure 3, gate-normal BTBT occurs at the corners earlier than at the sides, which is called the corner effect. To be specific, the area wherein BTBT occurs is extended from the corner to the side as V\({}_{\text{G}}\) increases. In addition, the electron BTBT generation rate is not constant through the NW, and is stronger at the corner. This means that different BTBT turn-on voltages exist in an NW, which induce the hump behavior. Second, as shown in Figure 2, the hump becomes more severe as V\({}_{\text{D}}\) decreases. At low V\({}_{\text{D}}\), it is vulnerable to the hump because the influence of the gate increases as the V\({}_{\text{D}}\) decreases, while the hump is more affected by the structure of the gate. The definition of the corner and side of an NW is shown in Figure 4. Because the tunneling width is determined by the epi-layer thickness (\(T_{\text{epi}}\)), gate-normal tunneling occurs mainly in the epi-layer [28]. Thus, by integrating electron BTBT generation rates over the cross-section of an NW, electron BTBT generation rates per channel length are calculated. In order to evaluate the influence of the corners on I\({}_{\text{D}}\), the electron BTBT generation rates at the corners and sides are compared with each other. Figure 5 shows that gate-normal tunneling occurs first in the corner region and then in the side region of an NW. The corner effect is dominant at a low \(V_{\text{G}}\) while it becomes less strong as \(V_{\text{G}}\) increases. Thus, it degrades the on-off transition abruptness of the total electron BTBT generation rates. Figure 6a shows the 2D contour of electrostatic potential. As shown in Figure 6b,c, the surface potential is higher at the corner than at the side in the entire range of \(V_{\text{G}}\). This is because the charge at the corner is shared by the surrounding gate. The charge sharing effect at the corner contributes to the higher surface potential compared with the side one [29; 30]. The difference in surface potentials in an NW affects the energy band diagrams of gate-normal NWTFETs. Figure 7 shows the energy band diagrams extracted,  
Figure 2: Transfer curves of the gate-normal NWTFETs for \(V_{\text{D}}\) values of 0.5 V and 0.05 V. It is shown that gate-normal NWTFETs suffer from hump behavior, which degrades \(SS\) and \(I_{\text{on}}\). at the corner and side, from the middle of the gate-source overlap region, respectively. Gate-normal tunneling, which is a main current mechanism of the gate-normal NWTFETs, occurs vertically in the gate-source overlap region, whereas the current is conducted laterally along the gate-controlled surface channel [10]. Then, in order to induce gate-normal tunneling, the band alignment in the direction perpendicular to the channel in the gate-source overlap region should be required [28]. When the \(V_{\text{G}}\) is 0.6 V, the conduction energy band edge (\(E_{\text{C}}\)) of the epi-layer is aligned with the valence energy band edge (\(E_{\text{V}}\)) of the source region at the corner, while the \(E_{\text{C}}\) of the epi-layer is not aligned with the \(E_{\text{V}}\) of the source region at the side. This is because the higher surface potential of the corner leads the energy band of the surface to shift down, which causes the gate-normal tunneling to turn on early. Thus, the corner and side of an NW have different BTBT turn-on voltages, which induce the hump behavior. Figure 4: Definition of corner and side of a nanowire (NW).