## 5 Performance Analysis of MSD Algorithm Based on Hybrid SC
### Hardware Resource Overhead of MSD Algorithm  
To assess the hardware resource overhead of the hybrid SC approach designed in this study, the entire hardware circuit was meticulously implemented on the FPGA platform. Specifically, the Xilinx Virtex UltraScale xcvu190 platform was utilized, and the synthesis and implementation tools were Vivado Synthesis 2018 and Vivado Implementation 2018, respectively. As previously mentioned, a multi-stream approach was adopted to balance hardware resource consumption and computing speed. Due to the variation in BER performance under different sequence lengths in hybrid SC, this study conducted a precise evaluation of hardware resource consumption for various sequence lengths through controlling the number of parallel-processed streams. Considering actual data processing requirements, the symbol rate of the transmitted data was set to 10 Msps, and the up-sampling factor of the receiver was set to four. For comparison, resource requirements for binary computing under 8- and 9-bit quantization were also established. Due to the up-sampling factor, a four-input adder is required to accumulate the multiplication results within each symbol. For the three-, five-, and seven-symbol MSD algorithms, this architecture necessitates three-, five-, and seven-input adders, respectively, to perform the summation of accumulated results across multiple symbols. To determine the optimal scaling factors for each adder, we conducted numerical simulations of the MSD algorithm under the constraint that the summation results must not exceed the limiting range while minimizing the scaling factor. Through numerical analysis of the MSD computational process, we established the following scaling factor assignments: two for three-input adders, two for four-input adders, three for five-input adders, and four for seven-input adders. The selection criteria aimed to balance between preventing overflow in addition operations while preserving maximum signal resolution through minimal scaling factors. Table 6 illustrates the hardware resource overhead of the three-symbol MSD algorithm under different computing paradigms. When the sequence length was 500, the hybrid SC proposed in this study exhibited a lower hardware resource consumption than that demanded by 8-bit binary computing. When the sequence length reached 1000, the hardware resource consumption of hybrid SC surpassed that of 8-bit binary computing, yet remained inferior to that of 9-bit binary computing. As the sequence length exceeded 1500, the hardware resource consumption of hybrid SC surpassed the threshold for 9-bit binary computing. Figure 17: The BER performance of the 7-symbol MSD algorithm. Table 7 illustrates the hardware resource overhead of the five-symbol MSD algorithm. In comparison to the three-symbol MSD, the hybrid SC demonstrated a hardware resource consumption that remained slightly lower than that of 8-bit binary computing, even when the sequence length reached 1000. When the sequence length increased to 1500, the hardware resource consumption of hybrid SC exceeded that of 8-bit binary computing but remained less than that of 9-bit binary computing. This is primarily due to the non-linear relationship between hardware resource consumption and computational load in SC. Even though an increase in the number of MSD symbols leads to a linear increase in computational load, the resource consumption does not increase significantly. Table 8 illustrates the hardware resource overhead of the seven-symbol MSD algorithm. When the sequence length reached 1500, the hardware resource of hybrid SC slightly exceeded that of 8-bit binary computing. Conversely, when the sequence length was reduced to 500, the hardware resource of hybrid SC was merely one-third that with 8-bit binary computing. Nonetheless, the utilization of storage resources in hybrid SC exhibited a notably higher consumption compared to binary computing.