# A Low-Phase-Noise 8 GHz Linear-Band Sub-Millimeter-Wave Phase-Locked Loop in 22 nm FD-SOI CMOS
## 3 Experimental Results  
The chip (shown in Figure 5) was realized in the 22 nm CMOS FDSOI process and has an area size of 1.25 mm \(\times\) 0.9 mm. The integrated bowtie antenna has inter-layers of  
Figure 4: Schematic of: (**a**) PFD; (**b**) CP+LPF; and (**c**) PA.  
metal fills for metal density DRC rules. This does not affect the 7 dB gain of the antenna and its efficiency. To measure the PLL, the measurement setup from Figure 6 is used. The signal from the integrated bowtie antenna is picked up by a horn antenna (Mi-Wave 261G-10/387) with 12 dB gain. Thereafter, the signal is applied to a WR5 waveguide. As the spectrum analyzer (FSW from Rhode & Schwarz) has a span of 70 GHz, the RF signal is down-converted with the FS-Z220 Rhode & Schwarz mixer. The LO signal is generated from a signal generator (MG3690C from Anritsu) using a InP multiplier (SMZ170 from Rhode & Schwarz). All the measurement devices are available at the System-on-Chip Center (SoCC) at Khalifa University. For phase noise measurements, the spectrum analyzer has the phase noise option enabled by software. The measured spectrum of the PLL is presented in Figure 7. The resolution (and view) bandwidth is 47 KHz. The measured RF signal power is \(-19.53\) dBm at 157.82 GHz. It can be observed that the worst-case scenario in-band spur for the standalone PLL is about \(-35.7\) dBc. Therefore, the power at the PLL output after the buffer is close to 2 dBm, taking into account the gain of the PA, the gain of the two antennas, and the power losses due to free-space propagation at 160 GHz. Figure 5: Chip photomicrograph (1.25 mm \(\times\) 0.9 mm). Figure 6: PLL measurement setup. To measure the tuning range of the VCO, the PLL loop is disabled by turning off the components of the loop. The linear tuning range of the VCO is measured to be from 159.5 GHz to 167.5 GHz (as illustrated in Figure 8). Nevertheless, the VCO is functional at frequencies as low as 157.5 GHz. Additionally, it can be inferred by the figure that the measured VCO tuning frequency range closely converges with the simulated results. Figure 9 shows the measured phase noise of the PLL, VCO, and reference. The measured phase noise of the PLL is \(-103\) dBc/Hz @ 11 KHz and \(-128\) dBc/Hz @ 100 KHz. The free-running VCO has a phase noise of \(-111\) dBc/Hz @ 100 KHz and \(-132\) dBc/Hz @ 1 MHz. The reference at 5 GHz has a phase noise of \(-110\) dBc/Hz @ 1 KHz and  
Figure 8: Measured versus simulated VCO tuning range. Figure 7: PLL output spectrum at 160 GHz. Furthermore, (1) predicts a linear synchronization with the injection signal level of the injection-locked divider. This is confirmed by the measurements in Figure 10. Due to the limitation of the tuning range of the VCO, the last measured point (in blue) at \(-20\) dBm input power is extrapolated from the previous measurement point. Table 1 provides the benchmark of the proposed PLL and comparisons with other relevant works. For instance, [4] is a 198-274 GHz CMOS PLL. Even though the performance in terms of bandwidth, DC power consumption, and chip area of the PLL in this work is good, the phase noise lies above \(-80\) dBc/Hz @ 100 KHz with an output power  
Figure 10: Measured synchronization range of the injection-locked divider @ 160 GHz. Figure 9: Measured PLL phase noise: closed loop (black), VCO (red), and reference (blue). of only \(-11\) dBm. Moreover, the proposed PLLs in [8] and [9] produce phase noises more than \(-90\) dBc/Hz @ 100 KHz with DC power consumptions in the range of 323-380 and 1150-1250 mW, respectively. Meanwhile, the proposed PLL in this work has a phase noise of only \(-103\) dBc/Hz @ 1 KHz and \(-128\) dBc/Hz @ 100 KHz, which is among the lowest compared to the state-of-the-art sub-mm-wave PLLs.