# Large Field-Size Elliptic Curve Processor for Area-Constrained Applications
## 4 Implementation Results and Performance Comparison
### Comparison to State of the Art  
The comparison to state-of-the-art architectures is shown in Table 4. Column one gives the reference design and publication year (in form of Ref/Year). The utilized field length \(m\) is illustrated in column two. The implementation device is presented in column three. Columns four and five show the hardware resources in FPGA slices and LUTs. The last three columns provide the timing information in clock cycles, operational frequency and latency. \begin{table}
\begin{tabular}{l l l l l l l l} \hline \hline
**Ref/Year** & \(m\) & **Device** & **Slices** & **LUTs** & **CCs** & \
\begin{tabular}{l} **Freq** \\ **(MHz)** \\ \end{tabular} &
\begin{tabular}{l} **Latency** \\ **(μs)** \\ \end{tabular} \\ \hline \multicolumn{8}{l}{**Implementations of Weierstrass model of ECC**} \\ \hline  
\hline \hline \end{tabular}
\end{table} 
Table 4: Comparison to related PM architectures. Comparison to Weierstrass model of ECC.As compared to [15], our proposed architecture utilizes 2.67 and 3.50 times lower slices on Virtex 7 FPGA device over \(GF(2^{409})\) and \(GF(2^{571})\), respectively. The cause to achieve higher resource utilization in [15] is the parallel computation of Frobenius maps and point additions while in our work, we use a non-pipelined Karatsuba multiplier. Note that the clock cycles and frequency comparison are not feasible as the particular information is not given. On the other hand, the operation rescheduling for PA and PD computations result in lower latency values (9.50 over \(GF(2^{409})\) and 18.51 over \(GF(2^{571})\)) as compared to our work (39.83 over \(GF(2^{409})\) and 66.08 over \(GF(2^{571})\)). There is always a tradeoff between hardware resources and computational time (i.e., latency). Concerning [23; 29; 31], the bit-serial and digit-serial multipliers are practical to reduce hardware resources while bit-parallel and digit-parallel multipliers are more convenient to reduce computational cost with area and power overheads. Therefore, over \(GF(2^{409})\) and \(GF(2^{571})\), the use of a segmented digit-serial multiplier in [17] results in 1.49 and 2.23 times higher FPGA slices as compared to our proposed architecture where we employed a hybrid bit-parallel Karatsuba multiplier architecture of Figure 3. The clock cycle comparison is not possible as the relevant information is not described in the work of [17]. If we compare the circuit frequency, our architecture is 1.10 and 1.24 times more efficient. The computational cost of our proposed architecture is comparatively 0.82 and 0.87 times higher. Again, we remind the reader that there is always a tradeoff between the area and processing time. On Virtex 6 FPGA, we provide the area comparison of our work in terms of LUTs with the unified architecture of [19] as the information of the FPGA slices is not reported. Comparatively, our architecture utilizes 7.97 and 6.89 times lower FPGA LUTs over \(GF(2^{409})\) and \(GF(2^{571})\). The reason for the use of lower resources in our work is that we proposed dedicated designs for \(GF(2^{409})\) and \(GF(2^{571})\) fields while in [19] a unified ECC architecture is proposed to implement binary field lengths from \(GF(2^{233})\) to \(GF(2^{571})\). As shown in Table 4, the clock cycles utilized in [19] are lower as compared to our work but we achieved higher operational frequency (210 for \(GF(2^{409})\) and 170 for \(GF(2^{571})\)). The average sum of frequency achieved for \(GF(2^{409})\) and \(GF(2^{571})\) is 190 MHz (210 MHz + 170 MHz then divided by 2). Comparatively, our average frequency of two dedicated designs is 1.40 times higher as compared to the frequency (135 MHz) achieved for the unified design of [19]. As we are utilizing the lower hardware resources but our design takes more processing time. As compared to the 6 CC-6 CC architecture of [16], our hybrid Karatsuba multiplier-based ECPM design takes 5.51 (ratio of 80,970 over 14,687) times lower FPGA LUTs.