# Classic Discrete Control Technique and 3D-SVPWM Applied to a Dual Unified Power Quality Conditioner
## 2 UPQC in Dual Topology
### Series Active Power Filter (Series APF)  
The simplified circuit in Figure 4 represents the series APF of the UPQC. Additionally to the terms defined in Section 1 for Figure 1, \(V_{\text{is}}\), \(V_{\text{ib}}\), and \(V_{\text{ia}}\) are voltages in the power grid between the series compensator and the network for phases a, b, and c, respectively; \(C_{\text{sat}}\), \(C_{\text{sb}}\), and \(C_{\text{sc}}\) are the power grid capacitance of phases a, b, and c, respectively; and \(i_{\text{sa}}\), \(i_{\text{fsb}}\), and \(i_{\text{fsc}}\) are the filtered currents supplied to the load using the series APF. Moreover, \(Q_{1}\)-\(Q_{6}\) are the duty cycles for the three-phase inverter; \(V_{d}^{*}\) is a reference for the unbalance voltage between the two DC capacitors; \(V_{\text{B}}^{*}\) is a reference for the DC link voltage; and \(i_{\text{cs}}^{*}\) is a reference for the current supplied by the series APF. From the control scheme, there are three control loops. The first control loop corresponds to the current in the source side, responsible for controlling independently the current of each phase in the source. The second control loop corresponds to the voltage in the DC bus of the inverter to keep constant the voltage. The third control loop is required because of the DC branch that divides capacitors, and it is used to maintain the same voltage values in capacitors. The block diagram in Figure 5 represents the control system of the series APF, which illustrates the three control loops previously mentioned only for phase a; this diagram is the same for phases b and c. Herein, \(V_{\text{B}}^{*}(t)\) is the required voltage in the DC bus of the power inverter applied as a reference with positive and negative values, according to the requirements in the capacitors of more or less energy drained through bi-directional inverter. Besides, the term \(Hv\) is a voltage sensor gain. Furthermore, inside the \"phase A control loop\" the term \(Hi\) represents the current sensor gain, \(Vm\) is the PWM gain,  
Figure 4: Series active power filter (series APF) for the UPQC in dual topology. \(Gi(s)\) is the current loop transfer function, and \(Ki\) is the current sensor gain (\(Ki=0.44\)). Moreover, \(Hd\) is the unbalanced voltage sensor gain, \(Gd\) represents the unbalanced voltage transfer function, \(Gv\) refers to the voltage loop transfer function, \(Kv\) is the voltage control attenuation (\(Kv=0.64\)), and \(Kd\) denotes the unbalanced voltage control attenuation (\(Kd=319\)). Finally, the output of the circuit is represented by two voltages: \(V_{d}\) that refers to the unbalance voltage between two DC capacitors and \(V_{B}\) defined as the DC link voltage. The unbalance voltage is expected to have a small value so it can be neglected. Finally, the current reference is a sinusoidal signal synchronized with the fundamental frequency of the power network, so the load in conjunction with the series APF behaves as a pure resistive load. The split capacitor configuration has several advantages. From the circuit point of view, a midpoint that allows correcting the unbalanced current of the load. From the modeling point of view, three independent single-phase inverters that allow analyzing the three-phase inverter, as this simplifies the circuit. Hence, the equivalent model of the series APF used in the UPQC is represented in Figure 6; where, Figure 6 presents the single-phase circuit; Figure 6 shows the circuit referred to the primary of the transformer; and finally, Figure 6 displays the final equivalent circuit per phase in which the switching period is much lower than the network frequency. Thus, the terms \(V_{rd}(t)\) and \(V_{0}(t)\) are constant in the switching periods. Figure 5: Series APF diagram. Figure 6: \(Cont\). The equivalent resistances and inductances in the primary and secondary of the transformer are calculated as described next.