## 2 System Components
### Puc Mli  
MLIs generate output voltages close to sinusoidal form as a result of combining different stair-case voltage levels at their outputs. Thus, a high output voltage with smaller harmonic content can be obtained depending on the number of voltage levels, without using step-up transformers. In comparison with classic two-level inverters, MLIs have improved results in terms of harmonics and efficiency for the same switching frequency. Usually, conventional MLI topologies such as CHB, FC, and NPC require more than one DC voltage source for proper switching. However, in the case of PUC MLIs, one DC source at the input can be sufficient to generate five or seven levels at the output voltage. To enable multilevel voltage generation, auxiliary capacitors are utilized in the circuit. The basic power circuit of the PUC structure is given in Figure 4. As can be seen, the circuit is U-shaped [50; 51]. There are two semiconductor switches and one DC voltage source used to build the fundamental PUC structure. By using more than one PUC structure, the voltage level at the output can be increased in the PUC-based MLI topology. The PUC circuit design originated as a consequence of merging the features of CHB and FC. Some of the distinguishing features of the PUC inverter are the use of a single isolated DC source, the need for fewer switching elements and gate drivers than other  
Figure 4: The power circuit of PUC [51]. Figure 3: The DC–DC boost converter circuit topology. MLI topologies at the same voltage level, the uncomplicated control method, the lower installation costs due to its components, the reduced \(\mathrm{d}v/\mathrm{d}t\) stress, and the lower harmonic distortion. Another advantage of the PUC is that it can perform bidirectionally, both as an inverter and a rectifier. The multilevel PUC converter operating either as an inverter or a rectifier is shown in Figure 5[52]. This topology is able to generate five or seven levels at the output depending on the selection of the ratio between the auxiliary capacitor voltage \((V_{c})\) and DC source \((V_{dc})\). However, the proposed PUC wind energy conversion model based on the PMSG MLI has shortcomings due to the size of the auxiliary capacitor, the complex technique used to stabilize its voltage, and its integration into the grid. Addressing these issues can enhance the overall reliability and availability of the wind energy conversion system. There is a relationship between the number of auxiliary capacitors used in PUC MLIs and the voltage level at the output. This relationship is given by  
\[N_{V}=2^{N_{C}+2}-1 \tag{9}\]  
where \(N_{V}\) is the level of the output voltage and \(N_{C}\) is the number of auxiliary capacitors. For example, if one capacitor is used, then seven levels at the output voltage can be attained. In this study, one capacitor is used and, in this way, five or seven voltage levels are obtained at the inverter output. Only six power semiconductor switches are necessary in the power stage in this situation. The voltage level in the PUC MLI topology changes according to the ratio between the auxiliary capacitor voltage \((V_{c})\) and the DC source voltage \((V_{dc})\). Five-level operation (PUC5) is obtained by setting the auxiliary capacitor voltage \((V_{c})\) to half of the input voltage \((V_{dc})\). On the other hand, seven-level operation (PUC7) is obtained by setting the auxiliary capacitor voltage \((V_{c})\) to one third of \((V_{dc})\)[53]. The output voltage levels and the corresponding switching states of PUC7 and PUC5 are shown, respectively, in Table 2. According to the switching cases, Figure 6(1)-(7) illustrates the circulating current for each case for both the PUC7 and PUC5 operations. The switches S4, S5, and S6 and S1, S2, and S3 are complementary to each other, respectively. Figure 5: (**a**) Multilevel PUC inverter; (**b**) multilevel PUC rectifier.