## 2 Bloom Filter Labelling for Packet Switching with Photonic Integrated Switches
### Results  
Figure 7a illustrates the oscilloscope traces obtained for two different phases (Phase#1 and #2), with every phase lasting for the duration of four data packets and corresponding to a different combination of BF-based addresses (IDs) for the four switch output ports. The first five rows in Figure 7 show the packet headers and the four output port IDs (Port_ID, Port_ID, Port_3_ID, Port_4_ID). Rows 6, \begin{table}
\begin{tabular}{c c c c c c c} \hline  & **S1** & **S2** & **S3** & **S4** & **S5** & **S6** \\ \hline
**CROSS** & 1.08 V (21 mA) & 0 V & 1.03 V (17 mA) & 0.98 V (11 mA) & 0.89 V (6 mA) & 1.18 V (36 mA) \\
**BAR** & 0.89 V (4 mA) & 1.02 V (16 mA) & 0 V & 0 V & 0 V & 0.9 V (7 mA) \\ \hline \end{tabular}
\end{table} 
Table 1: Optimum Biasing Conditions for each one of the MZIs PSs in CROSS or BAR state. Figure 6: Optical trace when light is inserted in port#3 and a 200 MHZ electrical clock signal modulates a switch in its optical path. Push -pull configuration is used. 7 and 8 illustrate the respective control signals produced by the FPGA for driving MZIs 4-6 (CTR_MZI4, CTR_MZI5 CTR_MZI6) after processing the packet header information and the port ID. During Phase#1, each of the four packets is routed to a different output port based on its header information and the respective Port ID. At the end of Phase#1, the four BFs corresponding to the respective port IDs get a new label, resembling the case of a change in the network topology and the new location of resources. This results into a different routing path for each packet even though every packet retains its header during both Phases. For example, the first packet with header '00101101' is routed to Output port 3 during Phase 1 and to Output Port 4 during Phase 2. Figure 7a indicates proper routing functionality and switch re-configurability for all packets during both phases. BER measurements were then performed, to evaluate the signal quality degradation, when optical packets are forwarded through the switch matrix utilizing the BF-labelling scheme. The 10 Gb/s packets were inserted in port 3 of the switching matrix and routed to all output ports. The BER measurements illustrated in Figure 7b revealed an error-floor at \(10^{-4}\), which mainly stems from the limitations on the maximum current drawing enforced by the Pseudo Current Mode Logic (PCML) interface of the FPGA output transmitter channels. The PCML interface constrained the current to values lower than 10 mA, which translates to 9 mW of maximum electrical power applied to each MZI. This power ensures optimal switching only for MZI#5, according to Table 1, while all other switches required higher power levels for altering their state. The PCML interface and the associated current drawing-based origin of the \(10^{-4}\) error-rate was verified by replacing the FPGA board with a PPG capable to deliver programmable patterns up to 12.5 Gb/s with voltage levels up to 2.5 Vpp and without any limitations in current draining. Two (MZI#4, MZI#6) out of the three switches in the path i1/i4 to o1/o4 were controlled by the PPG, while MZI#2 was biased with a constant DC signal. The two electrical control signals had a voltage swing of 1 V and 1.1 V, respectively, and the BER performance is presented in Figure 7b. The enhanced ER of the switches from the unlimited current draining led to error-free operation up to \(10^{-9}\), with a power penalty ranging between 1.2 dB-2.5 dB. This indicates that the use of DAC or amplification at the FPGA output can yield error-free operation at the expense of increased power consumption. The use of driving circuits to interface the FPGA with the MZIs yielding both optimal  
Figure 7: (a)Experimental packet trace results recorded with the oscilloscope for control signals and packets at output of the 4 \(\times\) 4 switch (b) Bit Error Rate (BER) measurements of the signal at the output of the switch using the FPGA and the PPG for driving the phase shifters of the MZIs. In the legend, i stands for input and o stands for output.