# Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices
## 1 Introduction  
The last decade has seen Si-photonics promoted as a platform for potentially revolutionary advances in the fields of Telecommunications, Data Communications, Medical Technology, Security, and Sensing [1; 2; 3]. The main driving force behind Si-photonics is the potential to realize small, highly integrated, photonic sub-systems that leverage off the decades of fabrication experience, technology, and scalability already developed for CMOS (complementary metal-oxide semiconductor) electronics [4]. Ultimately, the goal is the development of low-cost high-volume photonic integrated circuits (PICs) with integrated electronics, to simultaneously access the full potential of the silicon platform--i.e., Si-photonics for high-speed signaling and sensing, and CMOS-electronics for subsequent logical operations and computations [5]. An impressive array of Si-photonic elements has been demonstrated by researchers, and are now available as qualified 'building blocks' in the multi-project wafer (MPW) runs offered by several silicon foundries [6; 7; 8]. These include one-dimensional (1D) and two-dimensional (2D) grating-couplers, broadband edge-couplers, strip/rib waveguides and crossings, multi-mode-interference (MMI) splitters, echelon and arrayed waveguide (AWG) multiplexers/de-multiplexers, thermally-tunablemicro-ring resonators, high-speed Ge photodiodes, thermo-optic phase shifters, electro-absorption modulators (EAMs), etc. Literally thousands of these photonic elements, and perhaps dozens of simple Si-PIC (photonic integrated circuit) designs, can be laid-out on the single MPW 'block' (usually 10-30 mm\({}^{2}\)) that is typically used by academic researchers and small-to-medium enterprises (SMEs) as their test-bed for photonic designs. However, developing innovative PICs, and demonstrating their functionality in a laboratory environment, either on an optical-bench or in a probe-station, is only the first step towards realizing useful devices that can attract investment and generate interest and value in the market. Very often, the technical challenges associated with transferring an Si-PIC from the laboratory to a device are underestimated, or even completely overlooked at the Si-PIC design phase, leading to significant performance penalties and unnecessarily high fabrication costs in first-generation prototypes. 'Photonic Packaging' is the catch-all term used to describe the range of techniques and technical competencies needed to make the optical, electrical, thermal, mechanical (and sometimes chemical) connections between a PIC and the outside world [9; 10; 11; 12]. While Fiber-to-PIC coupling is perhaps the best-known aspect of photonic packaging, the field also includes the integration of laser-chips, micro-optics, electronic-chips, and micro-fluidics on PICs; the high-speed (25 Gbps) routing and impedance-matching of transmission-lines from external connectors to the microscopic photonic components on the PIC; and the efficient thermal cooling and thermal-stabilization needed to keep the PIC within its operational range--see Figures 1 and 2. While satisfying any one of these photonic packaging requirement can be trivial, especially with the tools and resources a laboratory environment, they can be difficult to realize in a robust, stand-alone device for prototyping in the field. This is especially the case in more advanced photonic devices, where there is the simultaneous need for several different varieties of packaging, i.e., multi-channel Fiber-to-PIC coupling, a vertically integrated driver-chip, and a high-speed connection, and a thermo-electric cooler [12]. To ensure that these devices are fully-functional when fabricated and assembled requires the adoption of packaging design rules (PDRs) up front, at the Si-PIC design stage. This article provides a review of the different optical, electrical, and thermal considerations for successful photonic packaging, as a PDR 'primer' that also highlights some current trends that are helping to scale packaging to commercial volumes of photonic devices.