# 3D Tiled Code Generation for [PERSON]'s Algorithm
## 5 Results
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline
**N** & **Serial** & **Pluto** & **ST** & **TC** & **TP** & **ByRow** & **3D Tiled** \\ \hline
1000 & 0.26 & **0.08** & 0.09 & 0.14 & 0.11 & 0.56 & 0.13 \\
2000 & 3.66 & 0.91 & **0.71** & 0.88 & 1.19 & 2.62 & 0.82 \\
3000 & 16.92 & 4.23 & 3.11 & 2,93 & 4.65 & 7.29 & **2.57** \\
4000 & 49.31 & 15.87 & 9.56 & 7,34 & 12.11 & 14.76 & **5.83** \\
5000 & 113.73 & 43.12 & 22.08 & 14.36 & 22.94 & 26.17 & **10.44** \\
6000 & 226.44 & 73.61 & 39.74 & 24.63 & 41.03 & 40.45 & **18.51** \\
7000 & 388.72 & 133.29 & 65.86 & 40.36 & 63.94 & 59.06 & **30.54** \\
8000 & 610.64 & 224.13 & 102.57 & 58.66 & 95.38 & 82.83 & **45.68** \\
9000 & 1142.03 & 501.54 & 191.91 & 106.05 & 134.94 & 114.11 & **64.51** \\
10,000 & 1521.17 & 628.74 & 244.81 & 133.33 & 182.67 & 149.88 & **96.26** \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Time in seconds for Intel i7-8700 and 12 threads (ST, TC, and TP denote the codes generated on the basis of the space-time, tile correction, and transpose approaches, respectively); best results of each row in bold. depicts how code speedup depends on the number of treads for \(N\) = 10,000; speedup is calculated on the basis of the data presented in Table 4.  
Table 5 presets execution times in seconds on Intel Xeon E5-2699 v3 and 36 threads used for code execution. The code generated with the approach presented in this article outperforms strongly the other examined codes starting from the problem size \(N=3000\). For shorter RNA strands, the transpose code demonstrates better performance because, in such a case, there is no data moving between cache and RAM. For longer sequences, the 3D tiled code accelerates over eighty times the serial code and allows us to achieve super-linear speedup (greater than 36). \begin{table}
\begin{tabular}{c c c c c c c c} \hline
**Threads** & **Serial** & **Pluto** & **ST** & **TC** & **TP** & **ByRow** & **3D Tiled** \\ \hline
1 & 1521.17 & 1564.28 & 796.16 & 437.59 & 584.25 & 486.25 & **312.38** \\
2 & & 902.88 & 453.24 & 236.73 & 310.54 & 271.70 & **217.58** \\
4 & & 657.66 & 307.04 & 165.55 & 206.75 & 160.11 & **119.01** \\
8 & & 643.33 & 255.08 & 155.50 & 198.03 & 160.13 & **100.71** \\
12 & & 628.74 & 244.81 & 133.33 & 182.67 & 149.88 & **96.26** \\ \hline \end{tabular}
\end{table} 
Table 4: Time in seconds for Intel i7-8700 and \(N\) = 10,000 (ST, TC, and TP denote the codes generated on the basis of the space-time, tile correction, and transpose approaches, respectively). Figure 3: Speedup for Intel i7-8700 and RNA sequence length, \(N\) = 10,000. Figure 2: Speedup for Intel i7-8700 and 12 threads. It is worth noting that for longer sequences, space-time tiling allows achieving higher performance on Intel Xeon than that achieved on i7-8700. On the other side, the ByRow code is not so efficient on Intel Xeon as on i7-8700. It is worth noting that for 36 threads, the parallel ByRow code does not outperform the serial ByRow code. Code speedup calculated on the basis of the data in Table 5 are presented in Figure 4.  
Table 6 and Figure 5 present times and speedup on 1, 2, 4, 8, 16, and 36 threads, respectively, for the longest RNA length, \(N=\) 10,000 under our experiments. As we can see, the performances of the serial and parallel 3D tiled codes are much greater than those achieved for the codes generated with the related approaches. The low speedup of the