## 2 Methodology
### PVTC-Based Analysis for Single Logic Gates  
In VLSI design, a combinational circuit is composed of basic logic gate cells; thus, the transient fault analysis method begins with a single logic cell. In this paper, to describe the random characteristics of noise-induced effects, we apply a voltage level probability density function (pdf) to describe the input signal and supply and propose a PVTC method to establish the relationship between the input and output voltage pdf distributions of the logic gates. The basic scheme of the PVTC modeling method for logic gates is shown in Figure 3.  
As shown in Figure 3, the function relationship between the voltage level of the input signal and output signal can be acquired by the PVTC model. Figure 4 provides an illustration of the procedure for establishing the PVTC model for an inverter gate. Figure 4a presents an SVTC curve for an inverter gate by SPICE DC analysis, and the pdf of the input signal can be modelled as a random variable following a normal distribution due to the environmental noise effects, as shown in Figure 4c. Figure 4a,c show that the probability of the input signal falling into the shaded area [\(V_{in1}\), \(V_{in2}\)] is equal to the probability of the output signal falling into the shaded area [\(V_{out1}\), \(V_{out2}\)], and this relationship can be expressed as  
\[P\left(V_{out2}<V_{out}\leqslant V_{out1}\right)=P\left(V_{in1}\leqslant V_{in }<V_{in2}\right) \tag{1}\]  
However, Figure 4b illustrates that in the practical construction of an SVTC curve, instead of a continuous curve, only a series of discrete points can be acquired because of the actual characteristics  
Figure 3: Diagram of the PVTC modeling method. Figure 2: NBTI-aware transient fault rate analysis framework based on the PVTC method. of DC analysis. Therefore, the corresponding output signal point \(V_{o}\) for any input signal point \(V_{i}\) may not be found exactly in the discrete SVTC curve, which is necessary for the probability calculation in Equation (1). Thus, a discrete pdf approximation process must be used to implement the calculation. First, the input range of the signal is divided into a sequence of equal-length intervals by DC analysis, and the length of each interval is \(dV_{in}\), which can be set in the analysis process. We assume that, for each point (\(V_{in,i}\), \(V_{out,i}\)) in the SVTC curve (e.g., point \(D\) in Figure 4b), input signals falling into area \([V_{in,i}-dV_{in}/2,V_{in,i}+dV_{in}/2]\) or the corresponding output signal of area \([V_{A},V_{C}]\) all have the same voltage \(V_{out,i}\). Furthermore, the approximation error can be tolerated because the division interval of \(dV_{in}\) is small. Then, the probability of the output voltage level being equal to \(V_{out,i}\) can be calculated as  
\[P\left(V_{out,i}\right)=\int_{V_{A}}^{V_{C}}p\left(V_{in}\right)dV_{in} \tag{2}\]  
Subsequently, to calculate the probability of the output signal falling into area \([V_{out2},V_{out1}]\), we search for all points (\(V_{in,i},V_{out,i}\)) having an output signal belonging to this area in the SVTC curve. All of the \(P(V_{out,i})\) of these points are then accumulated, and the probability of the output signal falling into the given area can be acquired. In the pdf calculation process, the gap between \(V_{out1}\) and \(V_{out2}\) is set to a small interval \(dV_{out}\); therefore, the pdf of area \(p(V_{out})\) can be estimated as  
\[p\left(V_{out}\right)\cdot dV_{out}\cong P\left(V_{out2}<V_{out}\leq V_{out1} \right)\cong\sum_{i}P\left(V_{out,i}\right)\cong\sum_{i}\int p\left(V_{in,i} \right)dV_{in} \tag{3}\]  
where (\(V_{in,i}\), \(V_{out,i}\)) is the _ith_ point on the SVTC curve with \(V_{out2}<V_{out,i}\leq V_{out1}\). PVTC analysis for gates with multiple input ports, such as NAND and NOR gates, can be modelled by a similar method. However, the SVTC curves for these gates are extended to three-dimensional curves (two or more input axes and one output axis), as shown in Figure 5.  
Figure 4: Principle of the PVTC method for an inverter gate.