# Balancing the Leakage Currents in Nanometer CMOS Logic--A Challenging Goal
###### Abstract
Although most of the previously listed works only aim at reducing the data dependency to some extent, BSPL [27], or rather _Balanced Static Power Logic_, is the first attempt to fully remove the imbalance by design. Although this succeeds up to a negligible error for a rather outdated technology node, namely 180 nm, we show in this work that the same approach fails to deliver equally promising results in smaller geometries, such as 65 nm and 40 nm. Thus, we develop and introduce an alternative approach that delivers better balance than BSPL in smaller feature sizes at a lower cost. Our Contribution. As a first step we analyze the BSPL approach presented in [27] and identify several potential issues in its design. Then we use simulations in 65 nm and 40 nm CMOS technology to investigate whether the principles behind BSPL translate to smaller geometries without suffering from a loss of balance due to the different leakage behavior. After concluding negatively in this regard, we determine the cause for such imbalances. Interestingly, we find that primarily leakage currents through the gate insulator of transistors which are switched on by their gate voltage are responsible for this observation. We argue that it is costly, in terms of area and energy, to balance all sources of data-dependent leakage in nanometer CMOS technologies via a generic cell structure. Furthermore, such an approach would suffer from the presence of process variations more severely due to its increased size per gate. Hence, we take a different path and propose an alternative to BSPL that is not generic but technology-specific and thus able to deliver better security at a lower cost. We call our new technique _improved Balanced Static Power Logic (iBSPL)_ and compare it to classic CMOS logic as well as BSPL gates. With respect to the comparison metrics we choose the same approach as [27] and present mutual information results between applied inputs and leakage currents of our custom gates. Our results confirm that a lower noise level is required to hide the data dependency exhibited by our iBSPL gates compared to BSPL and classic logic. We also analyze a cryptographic substitution box (PRESENT Sbox) synthesized either with regular CMOS gates, BSPL gates, or our technology-specific cells and demonstrate that in the ideal case as well as in the presence of intra-die process variations of different magnitudes (1%, 3%, 5%, 10%) modeled by Monte Carlo simulations, iBSPL gates are the preferable solution in all analyzed cases. Afterwards, we perform SPSCA attacks on the different Sbox circuits, which again confirm that the highest effort is required to extract the key for our new logic cells. For completeness we also analyze the success of _dynamic_ power analysis attacks on our circuits and demonstrate that unlike the BSPL approach, our new iBSPL logic gates are not any more susceptible to this kind of adversary when compared to classic gates. Although this work focuses on static leakage and introduces a power equalization technique as a countermeasure against side-channel attacks, it is worthwhile to mention that equalization schemes, e.g., iBSPL, are supposed to be combined with algorithmic masking schemes to provide security against dynamic power analysis attacks by masking and harden static power attacks by equalization.