## 1 Introduction  
With the rapid growth of semiconductor industries and innovative technologies, chip design has become an indispensable facet of technology sectors for engineers. Advances in semiconductor processes have not only enhanced the performances of consumer electronics but also exerted a profound influence on various technological fields, including artificial intelligence, the _Internet of Things_ (_IoT_), and communications. Consequently, the demand for professionals with strong digital-circuit design capabilities has emerged as a central priority in science and technology education. With the evolution of digital circuit design technologies, _hardware description languages_ (_HDLs_) have become indispensable for the design and verification of digital systems. Among the various _HDLs_, _Verilog_ stands out as one of the most widely adopted _HDLs_, finding extensive applications in developing _field-programmable gate arrays_ (_FPGAs_) and _application-specific integrated circuits_ (_ASICs_). _Verilog_ supports designs at the _behavioral level_, _register-transfer level_ (_RTL_), and _gate level_[1], which allows for precise specifications of circuit functionalities. Through the use of synthesis tools [2], the _Verilog_ descriptions can be converted into _standard-cell netlists_, culminating in complete chip designs and layouts. Despite the widespread availability of teaching resources and learning tools for software programming languages, such as _Python_ and _Java_, _HDLs_, like _Verilog_, remain relatively underserved. Although _Verilog_ is invaluable in practical digital circuit designs, its specialized syntax and limited learning pathways impose a steep learning curve for beginners. In traditional instructional settings, students can often be discouraged by a lack of hands-on experience and immediate feedback. A system to assist the self-studies of _Verilog programming_ has been strongly requested in both academia and industry. Recent studies have explored various methods to support student learning, showing promising results. Some have proposed gamified adaptive learning systems that leverage AI to personalize learning without the need for instructor intervention, effectively improving learning outcomes and self-efficacy [3; 4]. Others have integrated active learning strategies and hands-on projects into traditional courses, helping students better understand and apply complex concepts such as digital system design [5]. These approaches demonstrate the value of combining technology, interactivity, and personalization to enhance student engagement and performance, providing useful references for the design of our proposed system. Previously, we developed a web-based _Programming Learning Assistant System_ (_PLAS_) to offer a dedicated self-learning environment for novice students to learn key software programming languages, including \(C\), _Java_, _Python_, and _JavaScript_[6]. _PLAS_ provides several types of exercise problems that have different levels and learning goals for step-by-step study. For any problem, an answer from a student is marked automatically in the system, and the result is immediate feedback to the student. In this paper, we design and implement a web-based _Verilog Programming Learning Assistant System_ (_VPLAS_) by extending our work on _PLAS_ for software and programming to address the common challenges students face when learning _Verilog_. In our earlier study in [7], we proposed an initial version of _VPLAS_, focusing on providing simple exercise problems. Building upon this foundation, we enhance this _VPLAS_ by refining its instructional design and adopting a layered, progressive teaching approach. These improvements allow students to engage in effective self-directed learning and strengthen their overall learning experiences. It delivers a structured set of exercise problems coupled with automated answer evaluations, creating a highly interactive, self-directed learning environment.