# A Ku-Band GaAs Multifunction Transmitter and Receiver Chipset
## 3 Circuit Blocks of the Ku-Band Multifunction Chipset  
### 5-Bit Digital Attenuator  
The attenuator is designed in a passive type for zero DC power consumption. This is beneficial in allowing the multifunction chip to be used in a large-scale phased array system. To achieve a  
Figure 1: Block diagram of (**a**) the Ku-band multifunction transmitter and (**b**) receiver. 15.5-dB attenuation range, five-unit attenuator cells with binary-weighted attenuation are connected in cascade. The least significant bit (LSB) and the most significant bit (MSB) are 0.5 dB and 8.0 dB, respectively. In Figure 2, the topologies of the unit attenuator cells are presented. For 0.5-dB and 1.0-dB attenuation, a switched-T structure shown in Figure 2a is adopted for low insertion loss and small chip area. A \(2\times 50\)-m D-mode HEMT with on-resistance of 12.2 \(\Omega\) and off-capacitance of 27.3 fF is used for switching devices (M\({}_{\text{s}}\) and M\({}_{\text{p}}\)). As the attenuation increases, the conventional switched-T structure presents a larger phase imbalance between the reference and attenuation states. Therefore, a 2.0-dB attenuator cell is designed using the structure shown in Figure 2b. An additional capacitor, C\({}_{\text{P1}}\), compensates for the phase imbalance by adjusting the insertion phase in the attenuation state without degrading the insertion loss and matching performance in the reference state [15]. Finally, 4.0-dB and 8.0-dB attenuator cells are designed with the structure shown in Figure 2c, where a capacitor, C\({}_{\text{P2}}\), is connected in parallel with R\({}_{\text{P2}}\). This not only reduces the phase imbalance but also prevents the bandwidth reduction occurring in high attenuation cells [16; 17; 18]. Figure 3 shows a full schematic and micrograph of the 5-bit digital attenuator. The placement order of each unit attenuator cell is determined, such that the operation bandwidth is maximized. A shunt resistor (R\({}_{\text{11}}\)) provides the attenuator with DC ground. The 5-bit digital attenuator occupies an area of \(0.9\times 0.4\) mm\({}^{2}\), excluding probing pads. The parameter value of each component is presented in Table 1.  
Figure 3: Schematic and chip micrograph of the 5-bit digital attenuator. Figure 2: Topologies of the unit attenuator cells. (**a**) 0.5-dB and 1-dB attenuator cell, (**b**) 2-dB attenuator cell, (**c**) 4-dB and 8-dB attenuator cell. The measurement results of the 5-bit digital attenuator are shown in Figure 4. The insertion loss and matching performance in the reference state are depicted in Figure 4a. The insertion loss ranges from 4.9 to 6.6 dB over the entire Ku-band frequency. The input and output matching are below \(-14.2\) and \(-23.8\) dB, respectively. Figure 4b shows the measured insertion loss for all 32 attenuation states. It can be seen that the total attenuation of 13.8 to 15.5 dB is achieved with a step of 0.5 dB. Figure 4c shows the input and output matching performance for all 32 attenuation states, which are below \(-11.5\) and \(-15.6\) dB, respectively, in the entire Ku-band. The root mean square (RMS) attenuation and parasitic phase errors, shown in Figure 4d, are less than 1 dB and \(2^{\circ}\), respectively. \begin{table}
\begin{tabular}{c c c c c c} \hline
**Parameter** & **Design Value** & **Parameter** & **Design Value** & **Parameter** & **Design Value** \\ \hline M\({}_{1}\)–M\({}_{10}\) & \(2\times 50\)-\(\mu\)m & R\({}_{5}\) & \(5.1\)\(\Omega\) & R\({}_{10}\) & \(498.9\)\(\Omega\) \\ R\({}_{1}\) & \(16.4\)\(\Omega\) & R\({}_{6}\) & \(627.0\)\(\Omega\) & R\({}_{11}\), R\({}_{\rm G}\) & \(6.7\) k\(\Omega\) \\ R\({}_{2}\) & \(102.3\)\(\Omega\) & R\({}_{7}\) & \(7.6\)\(\Omega\) & C\({}_{1}\) & \(65.3\) fF \\ R\({}_{3}\) & \(31.5\)\(\Omega\) & R\({}_{8}\) & \(371.2\)\(\Omega\) & C\({}_{2}\) & \(133.9\) fF \\ R\({}_{4}\) & \(96.9\)\(\Omega\) & R\({}_{9}\) & \(18.4\)\(\Omega\) & C\({}_{3}\) & \(122.8\) fF \\ \hline \end{tabular}
\end{table} 
Table 1: Design parameters of the 5-bit digital attenuator.