## 2 Proposed Circuit  
### The Multiple-Input DDCCTA  
Figure 1a shows the CMOS implementation of the proposed DDCCTA, and Figure 2b shows its electrical symbol. The port characteristics of the ideal DDCCTA in Figure 2a can be given by  
\[ \begin{array}{c}V_{x}=V_{y+1}+V_{y+2}-V_{y-1}-V_{y-2}\\ I_{z}=I_{x}\\ I_{z\pm}=I_{x}\\ I_{0\pm}=\pm g_{m}(V_{z}-V_{1})\end{array}  \tag{1}\]  
where \(g_{m}\) is the transconductance gain of the DDCCTA. This building block can provide multiple-input differential \(y\)- terminals, multiple-output plus/minus \(y\)- and \(o\)-terminals, compared to conventional DDCCTAs [4]. The multiple inputs of the DDCCTA can be implemented using the MIBD-MOST technique, as shown in Figure 2[49]. Figure 2a shows the MIBD-MOST symbol and Figure 2b shows the implementation of the MIBD-MOST technique. In this technique, the input signal can be fed into the bulk-terminal (back-gate) of the MOS transistor. Figure 1: Proposed DDCCTA: (**a**) CMOS structure, (**b**) its electrical symbol. Figure 2: MIBD-MOST: (**a**) symbol, (**b**) implementation of MIBD-MOST, (**c**) implementation of large resistance RMOS. The MIBD-MOST can be obtained by paralleling the C\({}_{\text{B}}\)(1-N) capacitances, which are shunted by large R\({}_{\text{MOS}}\)(1-N) resistances, as shown in Figure 2b. The large resistance R\({}_{\text{MOS}}\) can be realized by antiparallel coupling of two MOSTs operating in the cut-off region, as shown in Figure 2c. The use of a parallel resistance R\({}_{\text{MOS}}\) and capacitance C\({}_{\text{B}}\) allows the MIBD-MOST to handle both DC and AC signals. The input capacitance C\({}_{\text{B}}\) and the large resistance R\({}_{\text{MOS}}\) create a high-pass filter at the input terminal with a very low cutoff frequency \(\leq\) 1 Hz, therefore, its influence on the proposed application is negligible. The MOS differential pairs M\({}_{1}\), M\({}_{2}\) in Figure 1a will be implemented using this MIBD-MOST technique. The operation of the proposed DDCCTA in Figure 1a can be explained by dividing it into two parts, DDCC and TA. The DDCC consists of transistors M\({}_{1}\)-M\({}_{16}\), M\({}_{\text{b}}\), I\({}_{\text{B}}\). Transistors M\({}_{1}\), M\({}_{2}\) form a differential MOS pair, while transistors M\({}_{1}\), M\({}_{3}\) form a flipped voltage follower to achieve a minimum supply requirement, i.e., to keep \(V_{DD}\) as low as \(V_{GS}+V_{DSsat}\), which is specially suitable for LV designs. The current sources M\({}_{4}\), M\({}_{5}\) act as loads for the input differential pair M\({}_{1}\), M\({}_{2}\) and also serve to supply the necessary quiescent current for M\({}_{1}\), M\({}_{2}\). It should be noted that the MOS differential pairs M\({}_{1}\), M\({}_{2}\) are implemented using the MIBD-MOST technique and, therefore, increasing the number of input terminals will not increase the bias current and power consumption of the input differential pair, which is the main advantage of the MIBD-MOST technique. To improve the power efficiency at the output stage, which consists of M\({}_{6}\), M\({}_{9}\), R\({}_{\text{MOS}}\), the super class-AB output stage from [50] is used. The drain voltage of M\({}_{2}\) controls the gate of M\({}_{6}\) and via capacitor C\({}_{\text{C1}}\) the gate of M\({}_{9}\). The quiescent current of M\({}_{9}\) is determined by the biasing current I\({}_{\text{B}}\), transistor M\({}_{\text{b}}\), and large resistor R\({}_{\text{MOS}}\). The large resistance R\({}_{\text{MOS}}\) can be implemented as shown in Figure 2c. The capacitance C\({}_{\text{C1}}\) and the large resistance R\({}_{\text{MOS}}\) create a high-pass filter with a cutoff frequency of about 1 Hz. For AC signals with a frequency greater than 1 Hz, the AC voltages at the gates of M\({}_{9}\) and M\({}_{6}\) are nearly identical, therefore, class AB output stage operation is achieved. To compensate for the frequency characteristic of the two-stage internal amplifier, Miller frequency compensation was applied using the capacitance C\({}_{\text{C2}}\).