# Model Predictive Control Algorithm for Converter Based on a Convolutional Neural Network
## 4 Simulation Experiment and Analysis
### System Closed-Loop Control
When the tracking control error exceeds the threshold value, the pre-trained CNN calculates the load type at this moment by inverter operation state data obtained through sampling. The system continuously samples inverter operation state data at intervals of a fixed time window \(n\) and the load type is calculated. When the load type calculated by the CNN is consistent for several consecutive times, the load type is determined to be the inverter load type for this time period. Figure 13 is the control process diagram of the transition from NL to HPFRIL. Figure 13a illustrates the tracking control error variation curve of the output voltage during this switching process. The three-phase output voltage waveforms of the inverter before load switching, after load switching, and after control model switching are shown in Figures 13b, 13c, and 13d, corresponding to the positions marked as (a) in  
Figure 11: Output voltage waveform quality comparison between the Classical and Compensated FCSMPC algorithms. (**a**) HPFRIL. (**b**) LPFRIL. (**c**) NLL. Figure 12: Output voltage waveform quality comparison between the Classical and Optimal FCSMPC algorithms. (**a**) HPFRIL. (**b**) LPFRIL. (**c**) NLL. Figure 13a, respectively. The specific experimental procedure is conducted as follows: First, the converter system is controlled using the Classical FCSMPC algorithm under NL conditions. After the system achieves stable operation, the control strategy is switched to the NNC (NL--Classical FCSMPC). At \(t=1\,\)s, the HPFRIL is connected. Due to the mismatch between the NNC (NL--Classical FCSMPC) and the actual load, the tracking control error escalates sharply, exceeding the threshold value significantly, as indicated at position 1 in Figure 13a. Concurrently, the inverter output voltage exhibits significant distortion, as shown in Figure 13b and the corresponding output current is shown in Figure 13e. When the tracking control error exceeds the threshold value for three consecutive control cycles, it immediately switches back to the Classical FCSMPC algorithm control and triggers the load-type identification program, and the system operates stably under the control of the Classical FCSMPC algorithm, with the tracking control error as shown at position 1 in Figure 13a, and the corresponding inverter output voltage waveform as shown in Figure 13c. When the CNN recognizes the load type as HPFRIL for several consecutive times, the control strategy is switched to the NNC (HPFRIL--Optimal FCSMPC) at \(t=2\,\)s, and the corresponding tracking control error is shown at position 1 in Figure 13a, in which it can be seen that after switching the neural network controller, the tracking control error of the system is significantly reduced, and the corresponding output voltage and current waveforms are shown in Figure 13d,f. The control performance is better than the Classical FCSMPC algorithm. Similar to the experimental process shown in Figure 13, Figures 14 and 15 present the control process diagrams for switching from NL to NLL and from HPFRIL to NLL,  
Figure 13: Switching from NL to HPFRIL. (**a**) Tracking control error variation curve. (**b**) Output voltage waveform corresponding to position 1. (**c**) Output voltage waveform corresponding to position 1. (**d**) Output voltage waveform corresponding to position 1. (**e**) Output current waveform corresponding to position 1. (**f**) Output current waveform corresponding to \(t=2\,\)s.  
respectively. In Figure 14, the inverter is initially operated using the Classical FCSMPC algorithm and then switched to the NNC (NL--Classical FCSMPC) model. At \(t=1\) s, the NLL is connected, causing a decline in inverter control performance, as shown in Figure 14a at position 1 and Figure 14b,e. This triggers the control model switching and load-type identification process. Subsequently, the CNN is employed to identify the load type under Classical FCSMPC control.