# Advances in Graphene Field Effect Transistors (FETs) for Annine Neurotransmitter Sensing
## 2 Problem Outline
### GFET Configurations  
Graphene has a zero bandgap and is often used as the gate channel in FET design [111; 112]. The design of GFET sensors, as shown in Figure 1a, includes several \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Neuotransmitter/Targeted Marker** & **Method** & **Catalyst/Transducer** & **LOD** & **Ref.** \\ \hline \multirow{4}{*}{\(\text{H}_{2}\text{O}_{2}\)**as a NEP Marker**} & CV & AgNP/graphene/GCE & 28 \(\upmu\)M & [83] \\  & CV & AgNP/MWCNT/AU electrode & 0.5 \(\upmu\)M & [84] \\  & CV & MnO\({}_{2}\)/GO/GCE & 0.8 \(\upmu\)M & [85] \\ \hline \multirow{4}{*}{\(\text{SER}\)} & CV & PSS/GO & 3.3 \(\upmu\)M & [86] \\  & CV & AuNP/graphene & 5 \(\upmu\)M & [87] \\  & CV & Pd/GO & 0.05 \(\upmu\)M & [88] \\ \hline \multirow{4}{*}{\(\text{ACh}\)**inhibitors**} & CV & ChO-AuNPs-GO-ITO & 100 \(\upmu\)M & [89] \\  & CV & ChO-GO-PNP-ITO & 5 \(\upmu\)M & [89] \\  & CV & MNP/Graphene & 10 \(\upmu\)M & [90] \\ \hline \multicolumn{2}{c}{**Histamine**} & DPV & MWCNTs/Ag-Ag\({}_{2}\)O/GCE & 0.18 \(\upmu\)M & [91] \\ \hline \hline \end{tabular}
\end{table} 
Table 2: _Cont._key steps: (1) graphene transfer to the substrate responsible for the electrical current and transconductance transmission of biosensing events, (2) a set of at least three electrodes to operate the transistor in a liquid environment, (3) a delivery mechanism that enables tested samples to reach the graphene layer, and (4) a layer of biorecognition elements on the graphene layer. These components enable the capture of a target analyte with the limit of detection (LOD) being based on the target's affinity constant. In FET design, the position of the gate becomes crucial for biosensing applications because it impacts the drain/source current (I\({}_{\text{DS}}\)) due to its gate capacitance [113]. Different GFET configurations are classified as back-gated, top-gated, coplanar-gated, and liquid-gated, as illustrated in Figure 1b. Si/SiO\({}_{2}\) is still the favoured substrate because of its compatibility with nanoelectronics. Other substrates for liquid-gating biosensing include glass and quartz [114,115]. In back-gated GFET design, the gate electrode is situated beneath the substrate and is isolated from the graphene channel by a dielectric layer (e.g., SiO\({}_{2}\)) [10]. The carrier  
Figure 1: (**a**) The schematic GFET biosensor design: showing a graphene sheet functionalised with biorecognition elements (purple) and immersed in a medium containing the target analyte (red) and (**b**) back-gated, top-gated, coplanar-gated, and liquid-gated GFET configurations. density in the graphene layer is affected when a voltage is applied to the back gate, creating an electric field across the dielectric. The graphene layer becomes charged because of this electric field, which modulates the number of charge carriers (electrons or holes) and, consequently, the graphene channel conductivity. On the other hand, in a top-gated GFET, the gate electrode (e.g., Ti/Au [116; 117]) is positioned above the graphene channel, with the dielectric layer acting as a barrier to ensure efficient gate control over the channel. By providing a voltage to the top gate, the electric field modifies the carrier concentration (electrons or holes) in the graphene channel, which in turn controls the current flow. When compared to back-gated devices, the proximity of the top gate to the graphene layer allows for enhanced electrostatic control over the channel because the thin dielectric layer offers more capacitance, which enables significant channel modulation at lower gate voltages. Nonetheless, the growth of an oxide on top of the graphene without breaking the carbon lattice and reducing the mobility of its free carriers remains an obstacle. The coplanar-gated configuration places the gate electrode on the same plane as the graphene channel [118], typically next to it, to avoid the growth of an oxide on top of graphene. The gate and graphene are separated by a thin dielectric layer arranged to give a high capacitance.