## 3 Circuit Description
### Tdc  
Figure 4 shows the block diagram of a two-dimensional time-to-digital converter. The time-to-digital converter (TDC) designed in this study is based on a two-dimensional Vernier architecture with a 7-bit thermometer output [20]. This design significantly reduces the length of the delay line compared to traditional linear Vernier architectures, thereby mitigating the accumulation of jitter as the reference or feedback signal passes through the delay line. By utilizing two delay lines along the X and Y axes, this architecture allows for a shorter delay line while achieving the same bit resolution, resulting in superior area efficiency due to the two-dimensional layout design. In this design, the X-axis delay line has a delay of 38.5 ps per stage, while the Y-axis delay line has a delay of 35 ps per stage, achieving a TDC resolution of 3.5 ps. This resolution is attained through the difference between the delay steps of the X and Y delay lines. The two-dimensional structure generates a Vernier plane with a higher number of quantization levels, enhancing the time range that the TDC can detect.  
A critical challenge in designing high-resolution TDCs is maintaining consistent performance across process, voltage, and temperature (PVT) variations. Traditional Vernier TDCs can exhibit significant resolution changes due to PVT variations. To address this, the designed TDC incorporates a delay-locked loop (DLL) to ensure the delay of the delay lines. Figure 5 shows the block diagram of the delay-locked loop (DLL). The calibration process includes feedforward calibration, where the DLL adjusts the supply voltage (VDD) of each delay line through a low-dropout (LDO) regulator, ensuring the X delay line consistently achieves 38.5 ps and the Y delay line consistently achieves 35 ps. This approach stabilizes the TDC resolution at 3.5 ps despite PVT variations.  
Figure 4: Block diagram of two-dimensional time-to-digital converter.  
The proposed low-power, compact wideband PLL architecture employs a ring oscillator (RO) type oscillator, which has a smaller area than an LC oscillator. However, ROs generally exhibit higher phase noise. To mitigate the out-of-band phase noise generated by the RO, the PLL's bandwidth is extended to effectively suppress out-of-band noise. This approach increases the in-band noise tolerance, necessitating a high-resolution TDC to maintain overall noise performance. The two-dimensional Vernier TDC achieves a resolution of 3.5 ps, thereby reducing in-band phase noise and enhancing the overall performance of the PLL. The implementation of the two-dimensional Vernier TDC begins with the design of a time comparator that compares signals from the X and Y delay lines using flip-flops. The output of this comparator is sequentially ordered and output as a thermometer code. The proposed two-dimensional Vernier TDC provides a compact and efficient solution for high-resolution time-to-digital conversion. By combining a two-dimensional delay line structure with a robust calibration mechanism, it ensures stable and accurate performance, making it suitable for integration into wideband PLLs with stringent area and noise requirements.