# Tunneling Current Variations in Small-Sized Devices Based on a Compact Threshold Voltage Model
## 4 Simulation Experiment
### Experimental Results  
Simulations were conducted on the gate and drain currents of an NMOSFET and a PMOSFET under certain bias conditions. The results for the NMOSFET are shown in \begin{table}
\begin{tabular}{c c} \hline
**Process Parameters** & **Parameter Value** \\ \hline \(V_{TH0}/V\) & 0.701 \\ \(K_{1}/V^{1/2}\) & 0.438 \\ \(K_{2}\) & 0.011 \\ \(K_{3}\) & 2.25 \\ \(K_{4}/V^{-1}\) & \(-\)0.018 \\ \(K_{5}\) & 2.28 \\ \(K_{6}\) & 0.53 \\ \(K_{7}\) & 0.46 \\ \(K_{8}\) & 0.069 \\ \(K_{9}/V^{-1}\) & \(-\)0.021 \\ \(K_{10}/V^{-1}\) & \(-\)0.032 \\ \hline \end{tabular}
\end{table} 
Table 1: Parameter extraction results. \begin{table}
\begin{tabular}{c c c c c c c c} \hline
**Name** & **Parameters** & \multicolumn{6}{c}{**Values**} \\ \hline Gate length & \(L_{min}\) (nm) & 90 & 75 & 65 & 53 & 45 & 40 \\ Channel length & \(L_{ch}\) (nm) & 65 & 53 & 45 & 37 & 32 & 28 \\ Overlap dimension length & \(L_{g,ave}\) (nm) & 12.5 & 11.0 & 10.0 & 8.0 & 6.5 & 6.0 \\ Oxide layer thickness & \(T_{ox}\) (nm) & 1.3 & 1.2 & 1.1 & 0.9 & 0.8 & 0.7 \\ Supply voltage & \(V_{DD}\) (V) & 1.2 & 1.1 & 1.0 & 1.0 & 0.9 & 0.9 \\ Threshold voltage & \(V_{TH}\) (V) & 0.35 & 0.33 & 0.32 & 0.30 & 0.28 & 0.27 \\ Junction depth & \(X_{j}\) (nm) & 71.5 & 58.5 & 49.5 & 36.0 & 35.5 & 31.5 \\ Substrate dopant concentration & \(N_{sub}\) (\(10^{19}\) cm\({}^{-3}\)) & 0.4 & 0.6 & 0.8 & 1.1 & 1.4 & 1.6 \\ Transition depth & \(X_{tr}\) (nm) & 35 & 29 & 25 & 18 & 18 & 16 \\ Channel dopant concentration & \(N_{ch}\) (\(10^{18}\) cm\({}^{-3}\)) & 1.15 & 1.15 & 2.0 & 2.0 & 2.0 & 3.0 \\ Gate dopant concentration & \(N_{gate}\) (\(10^{20}\) cm\({}^{-3}\)) & 0.92 & 0.92 & 1.14 & 1.5 & 1.66 & 1.66 \\ \hline \end{tabular}
\end{table} 
Table 2: Physical parameters. \begin{table}
\begin{tabular}{c c c c c c c} \hline
**AIGSD** & **BIGSD** & **CIGSD** & **AIGC** & **BIGC** & **CIGC** \\ \hline NMOSFET & 0.016 & 0.002 & 0.04 & 0.0164 & 0.0035 & 0.08 \\ PMOSFET & 0.011 & 0.001 & 0.08 & 0.011 & 0.0015 & 0.08 \\ \hline \end{tabular}
\end{table} 
Table 3: The BSIM4 model parameters. Figures 7-10, while the results for the PMOSFET are shown in Figures 11-14. Since the trend of gate tunneling current variation is similar between NMOSFETs and PMOSFETs, in this article, we only used an NMOSFET as an example to illustrate the changes in gate tunneling current for the two different gate states [17]. for devices with gate lengths ranging from 53 nm to 40 nm, the gate tunneling current exhibits an apparent exponential increase. As the gate length decreases, i.e., as the oxide layer thickness becomes thinner, the gate tunneling current increases more rapidly. With a reduction in gate oxide layer thickness, the gate tunneling current increases from \(10^{-9}\) A to \(10^{-6}\) A, approximately three orders of magnitude, for devices with gate lengths ranging from 90 nm to 40 nm. Figure 8 depicts the simulation results for an NMOSFET under another gate state, \(V_{DS.N}=0\) and \(V_{GS.N}=0\sim V_{DD}\), illustrating a similar conclusion. However, the gate tunneling current is greater at \(V_{DS.N}=0\) compared to \(V_{GS.N}=0\). Figure 11 depicts the contour plot of gate current (\(I_{G.N}\)) and drain current (\(I_{D.N}\)) or the NMOSFET biased at gate state \(V_{GS.N}=0\) and drain state \(V_{DS.N}=V_{DD}\). For all devices with oxide thickness ranging from 0.7 nm to 1.3 nm under this gate state, both the rectangular-point line representing \(I_{G.N}\) and the circular-point line describing \(I_{D.N}\) exhibit similar trends. The magnitude of the drain current \(I_{D.N}\) is approximately equal to the gate current \(I_{G.N}\). The dashed line represents the theoretical variation curve obtained from Equation (38) of the model, which matches the exponential increase observed in the simulation results. This confirms the effectiveness of the proposed model (Equation (38)).