# FPGA Applied to Latency Reduction for the Tactile Internet
## 7 Results
For the 10 ms constraint, the maximum limit is 375 \(\upmu\)s. The value \(t_{\text{hardware}}\) that is presented in Table 3 and according to Equation (71), corresponds to the sum of the latencies of the five implemented modules (Table 2), two modules are associated with the MD device (FK-HMD and KFF-HMD) and three modules are associated with the SD device (FK-HSD, IK-HSD, and FBF-HSD). Thus, the presented value of 403 ns in Table 3 corresponds to the sum of the two modules related to the master component, which has a total of 117 ns of which 47 ns come from the FK-HMD module and 70 ns from the KFF-HMD module together with the sum of the three modules referring to the slave component, which has a total of 286 ns of which 47 ns derives from the FK-HSD module, 218 ns from IK-HSD and 21 ns from the FBS-HSD module. So for the 1 ms constraint, the implementation presented a 93\(\times\) speedup relative to the 37.5 \(\upmu\)s, and for the 10 ms constraint, the speedup was 930\(\times\) relatives to the 375 \(\upmu\)s limit. The sample rates resulted from the five modules that were implemented in this work were notably fast. The values obtained contributed to the hardware meeting the time constraint limits required in a tactile internet environment. Hardware latency showed values significantly below the required constraints, as shown in Table 3. These values are well below the 30% presented in the literature and due to the fact that the communication medium demands 70% of application latency, this value can be increased as the latency of hardware devices showed to be significantly low. In other words, it can be said that the remaining latency not spent on the hardware devices can be consumed in the network. It is important to remember that in a more complex tactile internet environment, there are several others more algorithms to be implemented in hardware such as prediction algorithms, dynamic control, AI based techniques, etc. However, as the proposed implementations present low hardware resource consumption, other necessary modules, as the ones previously mentioned, could also be implemented in the same shared hardware since resources would still be available. Table 4 presents comparisons of the results obtained by the proposed implementation of this work with equivalent results found in works from the state of the art. The first column indicates the references of related works. The next two columns show the used FPGA platform and the amount of degrees of freedom of the used device. The fourth column presents the type of numerical representation used in the implementation and, finally, the last four columns present the times obtained by each reference for latency added by the forward kinematics (FK), inverse kinematics (IK), the kinesthetic force feedback (KFF) and feedback force (FBF) modules, respectively. As described in Table 4, a hardware model for calculating the forward kinematics of a 5-DoF device is presented in [30]. For the trigonometric calculations, a Taylor series expansion \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline
**Reference** & **Device** & **DoF** & **Data type** & **FK** & **IK** & **KFF** & **FBF** \\ \hline This work & Virtex 6 & 3 & Floating P. & 47 ns & 218 ns & 70 ns & 21 ns \\ \hline
[30] & Virtex 2 & 5 & Floating P. & 1240 ns & - & - & - \\ \hline
[31] & Cyclone IV & 3 & Floating P. & - & 143,000 ns & - & - \\
[32] & Unknown & 6 & Fixed P. & 3000 ns & 4500 ns & - & - \\
[33] & Cyclone IV & 10 & Fixed P. & - & 440 ns & - & - \\
[34] & Cyclone IV & 5 & Fixed P. & 680 ns & 940 ns & - & - \\
[35] & Artix 7 & 3 & Fixed P. & 200 ns & - & - \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Comparative table with state of the art works. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Time** & **Latency** & **\(t_{\text{hardware}}\)** & **Speedup** \\
**Restriction** & **Limit** & & \\ \hline
1 ms & 37.5 \(\upmu\)s & 403 ns & 93\(\times\) \\
10 ms & 375 \(\upmu\)s & 403 ns & 930\(\times\) \\ \hline \hline \end{tabular}
\end{table}