## 2 Proposed Resistive-Bridge Readout Integrated Circuit
### Circuit Implementation of a Chopper-Stabilized, Recycling Folded Cascode Instrumentation Amplifier  
Figure 6 shows the schematic of the proposed chopper-stabilized RFC IA. To reduce low-frequency noise, the choppers are added to the input stage and the folded cascode stage. For using fully differential CFIA topology, the differential difference amplifier (DDA)-style input stages are needed. The PMOS differential pairs, _MP_1-_MP_4, form the recycling folded  
Figure 4: Top block diagram of the proposed resistive-bridge microsensor readout IC. Figure 5: Simulated transfer function of the proposed CFIA. cascode input stage, and \(MP5\)-\(MP8\) forms the feedback input stage. \(MN1\)-\(MN4\) work as driving transistors, with a ratio of \(5\):\(6\), as shown in (6). \[MN2:MN1=MN3:MN4=5:6 \tag{6}\]  
The cross-over connections of these current mirrors keep the small-signal input currents added at the sources of \(MN7\) and \(MN8\), in phase. The Monticelli-style, floating class-AB control units are implemented using \(MP15\), \(MN9\), \(MP16\), and \(MN10\). By implementing class-AB output stage, \(G_{m}\) and GBW of the RFC can be increased. The compensation capacitors, \(C_{\text{F}}\)s, are connected between the output nodes and gate of the output common source stage in a Miller compensation manner to compensate for the frequency response. The \(R_{\text{CM}}\)s and \(C_{\text{CM}}\)s detect the output common-mode voltage. The error amplifier for common-mode feedback consists of \(MP19\), \(MP20\), \(MN13\), \(MN14\), and \(MN15\) to generate the control voltage _vcmfb_, which controls the bias current of the cascade stages. The \(\text{W}/\text{L}\) values of the transistors and passive components (in the proposed RFC's fully differential difference amplifier) are shown in Tables 1 and 2, respectively. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Transistor** & **Size (\(W\)/\(L\)) (\(\mu\)m)** & **Transistor** & **Size (\(W\)/\(L\)) (\(\mu\)m)** \\ \hline \(MP1\)–\(MP8\) & \(32/4\) & \(MN1\), \(MN4\) & \(0.6/10\) \\ \hline \(MP9\), \(MP10\) & \(2/1.5\) & \(MN2\), \(MN3\) & \(0.5/10\) \\ \hline \(MP11\), \(MP12\) & \(4/10\) & \(MN5\), \(MN6\) & \(8/1\) \\ \hline \(MP13\), \(MP14\) & \(4/10\) & \(MN7\), \(MN8\) & \(40/12\) \\ \hline \(MP15\), \(MP16\) & \(1/10\) & \(MN9\), \(MN10\) & \(1/18\) \\ \hline \(MP17\), \(MP18\) & \(2/10\) & \(MN11\), \(MN12\) & \(1/10\) \\ \hline \(MP19\), \(MP20\) & \(2/2\) & \(MN13\), \(MN14\) & \(1/16\) \\ \hline - & - & \(MN15\) & \(0.5/12\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Values of transistors in proposed RFC FDDA. Figure 6: Schematic of the proposed chopper-stabilized RFC. The transconductance of the 1 st-stage can be increased by \(11/5\), according to expression (1) and can be expressed as (7). The gain bandwidth can be determined by the \(G_{mRFC}\) and compensation capacitor, \(C_{F}\), as (8). \[G_{mRFC(1 st-stage)}=\frac{11}{5}g_{mP\mathrm{M1}a} \tag{7}\]  
\[GBW_{RFC}=\frac{G_{mRFC}}{2\pi C_{F}} \tag{8}\]  
The simulated input-output characteristics of the RFC CFIA are shown in Figure 7. The coefficient of the determination R\({}^{2}\) was calculated to be 0.9999, within the resistance variation (\(\Delta\)R) range of \(-380\Omega\)-\(380\Omega\). Figure 8 shows the closed-loop gain of the proposed RFC CFIA, based on corner simulation. The closed-loop gain varies from 100.0026 V/V (at the FF 125 \({}^{\circ}\)C) to 100.9353 V/V (at the TT 29 \({}^{\circ}\)C). Figure 9 shows the input-referred noise, with corner simulation results, when the chopper is enabled and disabled. The input-referred, low-frequency noise at 1 Hz is reduced from 1.49 \(\mathrm{\SIUnitSymbolMicro V}/\mathrm{\SIUnitSymbolMicro Hz}\) (when the chopper is disabled) to 80 \(\mathrm{nV}/\mathrm{\SIUnitSymbolMicro Hz}\) (TT 27 \({}^{\circ}\)C) (when the chopper is enabled). The input-referred noise is reduced to 1/18.6 times with the chopper operation.