# 3D Tiled Code Generation for [PERSON]'s Algorithm
## 5 Results  
To carry out experiments, we used two machines with a processor Intel i7-8700 (3.2 GHz, 6 cores, 12 threads, 12 MB Cache) and a processor Intel Xeon E5-2699 v3, 2.3 GHz (3.6 GHz turbo), 18 cores, 36 threads, 45 MB Cache. All examined codes were compiled by means of the Intel C++ compiler version 19 with the -O3 flag. Experiments were carried out for ten RNA randomly generated sequence lengths of the problem defined with parameter \(N\) from 1000 to 10,000. The results presented in the articles [18; 19] show that cache efficient code performance does not change based on strings themselves, but it depends on the size of a string. We compared the performance of 3D tiled code generated with the presented approach with that of:  
1. Pluto parallel tiled code (based on affine transformations) [8]. 2. Tiled code based on the space-time technique [4]. 3. Tiled code based on the correction technique [3]. 4. [PERSON] manual cache efficient implementation of [PERSON]'s RNA folding (transpose) [18]. 5. [PERSON] manual cache efficient implementation ByRow (parallel version) [19]. All source codes used for carrying out experiments as well as a program allowing us to run each parallel program for a random or real RNA strand in the FASTA format and obtain a target Nussinov table can be found at the address [[https://github.com/piotrbla/nuss3d](https://github.com/piotrbla/nuss3d)]([https://github.com/piotrbla/nuss3d](https://github.com/piotrbla/nuss3d)) (last accessed on 7 June 2022). For the Pluto code [8], the tile size 16 \(\times\) 16 \(\times\) 1 was chosen empirically (Pluto does not tile the most inner loop) as the best among many sizes examined. For the tile correction technique, the tile 1 \(\times\) 128 \(\times\) 16 was chosen as the best according to the article [21]. For the space-time tiled code, we chose the tile size 16 \(\times\) 16 \(\times\) 16 used in the experimental study whose results are presented in the article [4]. For the code generated with the presented approach, the tile size 116 \(\times\) 42 \(\times\) 54 was chosen from many different tile sizes, examined by us, as the one exposing the highest code performance. Table 3 presets examined code execution times in seconds for ten sizes of an RNA sequence on Intel i7-8700. Output codes are executed for 12 threads. We can see that the presented approach allows for obtaining cache efficient tiled code, which outperforms significantly the other examined implementations for each RNA strand with a length greater than 2000. For longer RNA strands, only the 3D tiled code speedup is super-linear (greater than 12). For shorter problem sizes, data are moved only among the different levels of cache, not to RAM, hence neither tiling approach allows for significant speedup of generated code [2]. Figure 2 depicts the speedup calculated on the basis of the times presented in Table 3. Under speedup we mean the ratio of the serial code execution time to the corresponding parallel code execution time. The second in terms of efficiency is the code generated with the correction approach implemented within the TRACO compiler. The ByRow code outperforms the codes generated with transpose and space-time tiling; the worst results are achieved for the code generated with Pluto, which is unable to tile the innermost loop nest. Table 4 shows how the code execution times depend on the number of threads (1, 2, 4, 8, and 12) for \(N\) = 10,000 on the Intel i7-8700 processor. We can observe that the presented approach allows for (i) generation of scalable code (execution time decreases with the increasing number of treads) and (ii) achieving the highest code performance for each number of threads in comparison with that of the reminding examined codes. The second in terms of performance is the code obtained with the tile correction strategy. Figure 3