# Electrical Coupling of Monolithic 3D Inverters (M3 INVs): MOSFET and Junctionless FET
## 3 DC/AC Characteristics  
Figures 2 and 3 show the drain current-gate voltage (\(I_{nds}\)-\(V_{ngs}\)) characteristics of two types of top N-type transistors (\(L_{G}\) = 20 and 50 nm) in M3 INV-MOS and M3 INV-JL at the different gate voltages (=0 and 1 V) of bottom P-type transistor, respectively. The solid lines and dotted lines indicate \(I_{nds}\)-\(V_{ngs}\) characteristics of top N-type transistors with \(L_{G}\) = 20 nm at two different gate voltages (=0 V and 1 V) of the bottom P-type transistors, respectively, and the squares and the circles \(I_{nds}\)-\(V_{ngs}\) characteristics of top N-type transistors with \(L_{G}\) = 50 nm at two different gate voltages (=0 V and 1 V) of the bottom P-type transistors, respectively. Figure 2 show \(I_{nds}\)-\(V_{ngs}\) characteristics of top N-type MOSFET in M3 INV-MOS in the case of \(T_{ILD}\) = 10 nm and 100 nm, respectively. Figure 3 show \(I_{nds}\)-\(V_{ngs}\) characteristics of top N-type JLFET in M3 INV-JL in the case of \(T_{ILD}\) = 10 nm and 100 nm, respectively. When \(T_{ILD}\) = 10 nm, it can be observed that the threshold voltage of top N-type transistors was clearly shifted due to the gate voltage of bottom P-type transistor. On the other hand, in the case of \(T_{ILD}\) = 100 nm, no threshold voltage shift of top N-type transistors occurs when the gate voltage of bottom P-type transistors changes. \begin{table}
\begin{tabular}{c c} \hline
**Symbols** & **Description** & **Value/Unit** \\ \hline \(T_{ox}\) & Gate-oxide thickness & 0.9/1/1.1 nm \\ \(T_{si}\) & Silicon-channel thickness & 6 nm \\ \(T_{sub}\) & Silicon substrate thickness & 50 nm \\ \(T_{sw}\) & Sidewall thickness & 31 nm \\ \(V_{IN}\) & Input voltage of M3 INV & V \\ \(V_{m}\) & Switching threshold voltage of the M3 INV & V \\ \(V_{ngs}\)/\(V_{ngs}\) & Gate-source voltages of top/bottom transistors & V \\ \(V_{nds}\)/\(V_{ngs}\) & Drain-source voltages of top/bottom transistors & V \\ \(V_{OUT}\) & Output voltage of M3 INV & V \\ \(V_{sub}\) & Substrate voltage & V \\ \(V_{th}\) & Threshold voltage * of the top transistor & V \\ \hline \end{tabular}  
* The threshold voltage \(V_{th}\) is defined as \(V_{ngs}\) when \(I_{nds}\) = 10\({}^{-7}\) A.  
\end{table} 
Table 1: Cont. Figure 2: Current-voltage characteristics of the top N-type metal-oxide-semiconductor field-effect transistor (MOSFET). (**a**) \(I_{nds}\)-\(V_{ngs}\) characteristics at \(V_{ngs}\) = 0 (solid lines and filed circles) and 1 V (dotted lines and empty squares) in the case of ILD = 10 nm and (**b**) \(I_{nds}\)-\(V_{ngs}\) characteristics at \(V_{ngs}\) = 0 (solid lines and filled circles) and 1 V (dotted lines and empty squares) in the case of \(T_{ILD}\) = 100 nm. The lines and symbols denote \(L_{G}\) = 20 and 50 nm, respectively. We use W/L = 0.2/0.03 μm. Figure 4 show \(\Delta V_{th}\), \(\Delta V_{gm}\), and \(\Delta V_{Cngng}\) versus \(T_{ILD}\) at different gate lengths (\(L_{G}\) = 20, 30, and 50 nm) of the top N-type transistors in both M3 INV-MOS and MOSINV-JL, respectively. The filled and empty symbols denote simulation results of the top N-type transistors in both M3 INV-MOS and M3 INV-JL, respectively, and the squares, circles, and triangles denote those at \(L_{G}\) = 20, 30, and 50 nm, respectively. As \(T_{ILD}\) decreases, \(\Delta V_{thr}\), \(\Delta V_{gm}\), and \(\Delta V_{Cngng}\) increases at both M3 INV-MOS and M3 INV-JL. When \(T_{ILD}\) is over 30 nm, \(\Delta V_{th}\), \(\Delta V_{gm}\), and \(\Delta V_{Cngng}\) are below 50 mV, the coupling between stacked transistors in both M3 INV-MOS [14] and M3 INV-JL can be ignored. As \(L_{G}\) increases in both M3 INV-MOS and M3 INV-JL, \(\Delta V_{thr}\), \(\Delta V_{gm}\), and \(\Delta V_{Cngng}\) increase.