## Materials and Methods
### Underwater Wireless Optical Communication System Construction  
* Physical Implementation  
The UWOC system consists of a transmission section, a 0.3 m water tank with sea water, and a reception section, as shown in Figure 1. In the transmission section, the FPGAboard connected to the host PC via a serial port. Since the communication between the FPGA board and the host PC was of a lower data rate than the transmission speed of the optical part, an IP core-generated FIFO was used for data flow buffering. A TLV3501 comparator was employed as the driving circuit to drive the optical transmitter, which provided sufficient driving capability suitable for different light sources. In our case, the light source was a 488 nm semiconductor laser. In the reception section, the PDs worked in a photovoltaic mode, and an OPA855 transimpedance amplifier was adopted to convert the small photocurrent signal to an amplified voltage signal. Before the demodulation, the obtained voltage analog signals were converted to digital signals using an AN9238 analog to digital converter (ADC) module. The FPGA board in the reception section demodulated the input signal and transferred the received messages to the host PC. For a comparison of the PDs with different bandgaps in optical filter-free UWOC, a commercial silicon PD (S1226-18 BK) from HAMAMATSU with a light-sensitive area (1.21 mm\({}^{2}\)) close to our device was selected, with a maximum dark current of 2 pA, a peak responsivity of 0.36 A/W at 720 nm, and a rise time of 150 ns [31]. * Working Mechanism  
The FPGA board of transmission section received instructions and messages from the host PC and then modulated the messages using an On-Off Keying (OOK) encoding method. In the following, the FPGA controlled the driving circuit of the optical emitter to modulate the optical signal intensity for data transmission that was based on the RS-232 serial data transmission standard. In this step, a state machine was used to generate transmission signals, as shown in Figure 2a. Upon receiving a transmission signal, the sending module state changed from the \"S_IDE\" to the \"S_START\" state, in which the voltage of the emitter was pulled to a low level for one symbol period. In the next moment, the sending module entered the \"S_SEND_BYTE\" state, where the data in buffer were read and the signal level was changed sequentially over eight symbol periods. When the sending process was completed, the system would enter the \"S_STOP\" state, pulling up the level for one symbol period, and then returning to \"S_IDLE\" if there were no more tasks in the sequence. In the reception section, when the optical signals reached the PD, they were first converted into small electrical signals. The transimpedance amplifier connected to the PD output amplified the small photocurrent signals to large voltage signals that were further converted into digital signals by an ADC module. The FPGA board demodulated the digital signals into messages. The obtained messages were then handled by the receiving module to send them to the host PC through a state machine, as shown in Figure 2b. After powering up, the receiver module defaulted to a receiver-enabled state that continuously read the input signal, called the \"S_IDLE\" state. When it read a falling edge of a start bit, indicating the start of transmission, the receiver module would change to the \"S_START\" state. After one symbol period, it changed to the \"S_REC_BYTE\" state and began receiving data, where eight bits of data were received over eight symbol periods. To satisfy the sampling theorem, and to receive data accurately, each data bit was sampled at the midpoint of the symbol period. Once it received the stop bit indicating completion of data reception, the receiver module would enter the \"S_STOP\" state. To avoid missing the start bit of the next byte, it waited only half a symbol period before turning to the \"S_DATA\" state, in which the  
Figure 1: The block diagram of the UWOC system.