## 5 Simulation Results and Analyses
In our scheme, 6 timing recovery iterations are simulated and compared with the ideal code performance. The bit or frame error ratio (BER/FER) of the scheme with the above parameters is shown in Figure 7.  
The performance of the LDPC coded system, which suffered from large timing errors, is within 0.1 dB of the ideal code performance (Figure 7). The LDPC coded system performs well at low SNRs (i.e., below 1 dB) without any pilot symbols. The cost is trivial, because the complexity linearly grows with the LDPC code length. In addition, incremental operations are limited. Figure 6: NMSE of the timing phase and frequency estimation with an average of 50 times for each \(E_{b}/N_{0}\). Finally, our algorithm is more stable than the algorithm in [4] because our algorithm employs soft decisions, whereas [4] uses hard decisions as code constraint feedback. Hard decisions yield false judgments when even decoded bits are reversed falsely, which involves computing the same parity check equation. In comparison, no similar case of false judgment exists in our algorithm. Therefore, our scheme shows rational complexity and excellent performance similar to [4]. However, our algorithm is more stable in timing recoveries especially at low SNRs. The complexity increment for the timing recovery scheme can be analysed in the comparison between the original scheme with traditional timing recovery and LDPC decoding, and the proposed scheme with the iterative timing recovery, the residual timing recovery and LDPC decoding. The traditional scheme performs the timing recovery and LDPC decoding separately. It has one timing tracking calculation for each sample and several LDPC decoding iterations. However, under the same condition and LDPC decoding iterations, our scheme has the same LDPC decoding computations and timing tracking calculation, including some extra calculations of iterative timing recovery. By Equations (34)-(37), and given iteration number \(N_{i}\), there are about \(N_{i}\cdot[2(2K-1)+2]\) additions and \(N_{i}\cdot(K+2)\) multiplications of additional computations in our scheme. Actually, with the gradual correction of timing errors by the proposed iterative timing scheme, the equivalent SNR is improved too. So the iteration number of LDPC decoding can be significantly reduced by sharp reduction of the decoding iterations. So it also magnificently cut down the computational complexity for the whole iterative system. However, it is difficult to illustrate this procedure analytically due to the nature of iterative process, which is closely related to the initial input signals and nonlinear iterative calculation. So the computational complexity cost of the proposed scheme is determined by initial input parameters and precision required in the joint decoding and demodulation. Thus, it can only be evaluated by numerical methods dependent on random input modulated signals. In our former work [6], it employs similar metrics from LDPC decoding to achieve timing synchronization at low signal-to-noise ratios. It obtains the accurate timing acquisition with a search window based Nelder-Mead simplex algorithm [20] to maximize the sum of the absolute values of the metrics. It obtained a little performance gain (\(\leq\)0.05 dB) than our  
Figure 7: BER/FER of the proposed method with 6 iterations. The LDPC (1944, 972) decoding is performed with maximum iterations of 20.  
new proposed algorithm. However, it may encounter the problems of local convergence of the optimization searching algorithm under limited iterations. It had to add some more additional decision module to judge and overcome the convergence problem. In our proposed method, it can achieve the same performance and overcome the deficiency of local convergence of the suggested optimization brought by the iterative BP decoding. It can be explained as follows. Due to the analyses of the influence of timing offsets on LDPC decoding, the effect of the timing error can be modeled as the decrease of SNR in the decoding procedure.