## 5 Conclusions
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Item**} & \multicolumn{2}{c}{**Merged Circuits**} & \multicolumn{2}{c}{**Modulo (\(2^{n}\pm 1\))**} & \multicolumn{2}{c}{**Proposed Work**} \\  & \multicolumn{1}{c}{**[1,2]**} & \multicolumn{2}{c}{**[8]**} & \multicolumn{2}{c}{**Proposed Work**} \\ \hline \hline \multirow{2}{*}{\(n\)} & **ADP** & **ADP** & **Saving** & **ADP** & **Saving** & **ADP** & **ADP** & **Saving** \\  & & & & & & & & \\  & & & & & & & & \\  & & & & & & & & \\  & & &modulo multiplier can be applied to communication systems, cryptography, digital filters, and digital signal processors. Conceptualization, C.-T.K. and Y.-C.W. ; Methodology, C.-T.K. and Y.-C.W. ; Software, Y.-C.W. ; Validation, C.-T.K. and Y.-C.W. ; Formal analysis, C.-T.K. ; Investigation, C.-T.K. and Y.-C.W. ; Writing--original draft, C.-T.K. ; Writing--review & editing, C.-T.K. All authors have read and agreed to the published version of the manuscript. This research received no external funding. * _[PERSON] et al. (2012)_ [PERSON]; [PERSON] Area-Power Efficient Modulo \(2^{n}-1\) and Modulo \(2^{n}+1\)Multipliers for \([2^{n}-1,2^{n},2^{n}+1]\) Based RNS. _IEEE Trans. Circuits Syst. I Regul. Pap._**2012**, _59_, 2263-2274. [CrossRef]
* _[PERSON] et al. (2020)_ [PERSON]; [PERSON]; [PERSON] Perspective and Opportunities of Modulo \(2^{n}-1\) Multipliers in Residue Number System: A Review. _J. Circuits Syst. Comput._**2020**, _29_, 2030008. [CrossRef]
* _[PERSON] et al. (2019)_ [PERSON]; [PERSON] [PERSON] Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo \(2^{n}-1\) Adder and Multiplier. _Circ. Syst. Signal Pract._**2019**, _38_, 2138-2164. [CrossRef]
* [PERSON] and [PERSON] (2021) [PERSON]; [PERSON] Efficient Tree Multiplexer Design by using Modulo \(2^{n}+1\) adder. In Proceedings of the 2021 Emerging Trends in Industry 4.0 (ETI 4.0), Raigarh, India, 19-21 May 2021. [CrossRef]
* _[PERSON] et al. (2023)_ [PERSON]; [PERSON]; [PERSON] On the modulo \(2^{n}+1\) addition and subtraction for weighted operands. _Microprocess Microsy._**2023**, _11_, 2138-2164. * [PERSON] et al. (2018) [PERSON]; [PERSON] Diminished-1 multiplier using modulo \(2^{n}+1\) adder. _Int. J. Eng. Technol._**2018**, \(7\), 31-35. [CrossRef]
* _[PERSON] et al. (2008)_ [PERSON]; [PERSON] [PERSON] VLSI design of diminished-one modulo \(2^{n}+1\) adder using circular carry selection. _IEEE Trans. Circuits Sys. II Express Briefs_**2008**, _55_, 897-901. * _[PERSON] et al. (2010)_ [PERSON]; [PERSON]; [PERSON] Improved area-efficient weighted modulo \(2^{n}+1\) adders design with simple correction schemes. _IEEE Trans. Circuits Sys. II Express Briefs_**2010**, _57_, 198-202. * _[PERSON] et al. (2013)_ [PERSON]; [PERSON] Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers. _IEEE Trans. Circuits Syst. I Regul. Pap._**2013**, _60_, 2940-2952. [CrossRef]  
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