# The Firmware Design and Implementation Scheme for C Form-Factor Pluggable Optical Transceiver +
## 2 Related Work
### CFP Register  
The space of the CFP register has hexadecimal addressing ranging from 0 \(\times\) 8000 to 0 \(\times\) FFFF and is divided into eight sections for CFP register space allocation and access control [11]. Each section is further divided into 32 tables. Eight tables are allocated to the NVR. Tables 1, 2, 3 and 4 store basic identification (ID) information, extended ID information, network channel-specific information, and host channel-specific information, respectively. Tables 5 and 6 store information needed by the CFP manufacturer, and Tables 7 and 8 allow the user to store necessary information. Table 9 with addresses from 0 \(\times\) 9000 to 0 \(\times\) 9 FFF is used for vendor private data. The remaining tables are assigned to the volatile register (VR) and configured to store CFP configuration, control, status, and DDM information. In implementation, CFP registers use fast memory to shadow the NVM and DDM data. The shadow registers decouple the host-side timing requirements from the internal processing, timing, and hardware control circuit-introduced latency of the module vendor.  
If the vendor and user data and vendor private data are unintentionally changed, the register value of the optical transceiver may be invalid or may result in unexpected behavior. Therefore, the MSA standard recommends a password control method to limit the reading/writing of memory values in specific areas. The password is entered in CFP memory in addresses 0 \(\times\) A000 and 0 \(\times\) A001, with a password value of 32 bits. Through the MDIO interface, the Host enters the password value in the password entry. If the contents of both registers match the previously stored password values, the host system can read the values for the password-protected registries. If not, all values for the addresses of the protected registers will be read as 0 \(\times\) FFFF.  
confirms that the MDIO interface and control circuit are ready for normal operation and enters a high power up state according to CFP state memory value and control signal. At this time, all circuits can be normally operated and stabilized, and then the tx-off state is entered. The tx-off state is the state in which the power of the optical transmitter using the network channel is not supplied. From here, the CFP transceiver can enter the tx-turn on state, in which the transceiver determines whether to use the channel according to the settings in the register. After that, the CFP transceiver finally transitions to the ready state and data are transmitted. Depending on the host request, the CFP may be in low power mode or perform a reboot. In the case of a low power mode request, it switches to the tx-off state, closes all channels, enters the high power down state, and then enters the low power state. Here, the CFP should power down all the circuitry to less than 2 Watts and keep only the MDIO interface function running. Finally, the fault state must remain in low-power mode to prevent permanent damage to the CFP, and the MDIO interface and DDM functions must be operating normal for recovery.  
Based on the DDM information, the status of the CFP transceiver should be updated in the fault, alarm, warning, and status (FAWS) register. The Figure 3 illustrates the mechanism of the signal source contributing to the global alarm (GLB_ALRM) and the relationship among the status, latch, and enable registers. The CFP uses GLB_ALRM to alert the host about any conditions outside the normal operating conditions. In this system, the status registers drive the latch registers on a bit-by-bit basis. The logic OR of all enabled bits in the latched registers drives GLB_ALRM. When GLB_ALRM alerts the host to a latched condition, the host may query the latched registers for the condition. The latched bits are cleared from the read line of the corresponding register. Thus, a read of all latched registers can be used to clear all latched register bits and to de-assert GLB_ALRM [11].  
Figure 2: State Transition Diagram of Optical Transceiver [11].