## 1 Introduction  
Modern electronic communication systems, such as baseband optical communication and satellite communication receivers, have growing demands for high-speed and high-resolution analog-to-digital converters (ADCs) [1, 2, 3, 4, 5]. A TIADC system composed by several slow but accurate sub-ADCs can meet the requirements of communication systems [6, 7, 8]. However, due to the offset, gain and timing mismatches among the parallel sub-ADC channels, the performance of TIADC has been limited [9, 10]. The offset and gain mismatch introduce direct current (DC) and gain product terms, and they can thus be calibrated by adders and multipliers, respectively [11]. Hence, the crucial challenge is to calibrate the timing mismatch that acts as the sample-time error, is dependent on input signal and deteriorates with an increase in input frequency [12, 13].  
In the analog domain, analog and mixed-signal calibration techniques can relieve the timing mismatch via the variable-delay line (VDL) in a direct way. However, the VDL requires an additional analog circuit and is very sensitive to process, temperature, voltage and thermal noise effects, which are detrimental to calibration performance [14, 15, 16, 17]. In contrast, fully digital calibration techniques have the advantages of high reliability and strong transplantation, while their biggest problem (i.e., digital circuit area) can be addressed by employing a more advanced technology.  
Many fully digital calibration techniques have been proposed in previous research [18; 19; 20; 21; 22; 23; 24; 25; 26]. In Ref. [18], the outputs of TIADC are modulated by the Hadamard matrix to generate the pseudo-aliasing signals. However, this approach only adapts to the TIADC with specific channel numbers, owing to the limits of Hadamard transform. Ref. [19] provides a method that exploits the correlation of the input signal and the mismatch spurs in the frequency domain to eliminate the influence of timing mismatch. Nevertheless, this requires a tremendous amount of filters and massive calculation of inverse discrete Fourier transform (IDFT), leading to an increase in hardware complexity; however, millions of sampling numbers are needed to achieve the convergence condition. In Ref. [21], based on the frequency-shifted and derived basis functions, a calibration method for time-skew errors needs the Hilbert filter to reconstruct the complex signal, resulting in the additional consumption of hardware resources. Furthermore, the feedback architecture [18; 20; 23; 24; 25; 26] is utilized to make their estimated parameters close to the actual value, but this also brings potential stability issues. To address the aforementioned concerns, we put forward a novel, fully digital calibration technique. We utilize the conjugate property of the spurious signals to avoid the generation of complex signal and reduce hardware complexity. We also propose a new feedforward algorithm to mitigate the risk of feedback-structure-induced non-convergence during the extraction of time-skew errors. It is worth noting that our calibration technique is suitable for any channel's TIADC system.  
The remainder of this manuscript is structured as follows. Section 2 presents a detailed exposition and analysis of the proposed calibration methodology. In Section 3, numerical simulations and experimental findings are portrayed. Finally, Section 4 presents a brief conclusion of the proposed method.