# A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process
## 3 Circuit Implementation and Calibration
### Flip-Around Sample and Hold Amplifier (SHA)  
The pipelined ADC can be divided into two categories: SHA-less pipelined ADC and pipelined ADC with SHA [27; 28; 29; 30]. SHA is placed ahead of MDAC in comparison to SHA-less ADC for several reasons. Firstly, because a comparator cannot compare a changing signal, SHA is used to obtain an unchanged sampled signal, especially for IF sampling applications. Secondly, although SHA brings extra power consumption and nonlinearity to some extent, the performance of sample and hold amplify (SHA) is relatively stable in the full frequency band.  
The topology of flip-around SHA is shown in Figure 8a. Compared with non-flip-around SHA, this structure has a small area, low noise, and low power consumption due to its one capacitor and large feedback coefficient. In this design, the technology of bottom-plate sampling is selected. VGSS (\(\phi_{\mathrm{1e}}\)) is turned off before VGS (\(\phi_{\mathrm{1}}\)), which reduces the influence of charge injection on the sampling MOSFETs M1 and M2. In addition, the clock feed-through of the gate-drain and gate-source flipped capacitors can be eliminated through this technique; otherwise, there will be errors in the sampling output voltage.  
Figure 6: Comparator schematic, including pre-amplifier, strong-arm latch, and buffer. \(\phi_{4}\) and \(\phi_{4e}\) are clocks for the designed comparators.  
Figure 7: (**a**) Pre-amplifier with calibration. (**b**) Equivalent circuit (**a**). \(\mathrm{V_{OS}}\) and raised output common mode caused by \(\Delta\mathrm{I}\).  
Dummy MOSFETs are also added to the symmetrical structure to reduce the impact of charge injection further. According to the conservation of charge at the sampling and hold phase phases, the transfer function of SHA can be shown as Equation (3):  
\[\text{VOUT}=\text{VOUTP}-\text{VOUTN}=-\frac{1}{1+\frac{1}{\text{A}}}(\text{ VINP}-\text{VINN}) \tag{3}\]  
Due to the gain (A) of operational amplifier being \(\infty\), the ideal the transfer function of SHA can be shown as Equation (4):  
\[\text{VOUT}_{\text{A}\rightarrow\infty}=-\text{VIN} \tag{4}\]  
Because of the limited gain (A) of the operational amplifier and the required accuracy of 12 bits, the error of VOUT under the maximum amplitude of one side (0.6 V) needs to satisfy the Equation (5):  
\[\text{VOUT}_{\text{error}}=|\text{VOUT}-\text{VOUT}_{\text{A}\rightarrow \infty}|<\frac{1}{2\times 2^{12}} \tag{5}\]  
Considering the parasitic effect of layout, the DC gain selected is 75 dB. The high-gain operational amplifier is introduced in Section 3.4.  
In Figure 8b, a bootstrapped switch is utilized for sampling, whose on-resistance is smaller than that of the MOS or CMOS switch, helping SHA obtain a higher linearity and faster speed. During the sampling phase, CLKN (red arrow) changes from DVDD to DVSS. M7, M8, and M4 turn on. The parasitic capacitance CP of the node VG results in the sampled signal generating input-related nonlinearity because the gate source voltage of M3 is less than VDD and is related to the input voltage \(\text{V}_{\text{IN}}\). The relationship between VG and \(\text{V}_{\text{IN}}\) is shown in Equation (6):  
\[\text{V}_{\text{G}}=\frac{\text{CB}}{\text{CB}+\text{CP}}\text{VDD}-\frac{\text {CB}}{\text{CB}+\text{CP}}\text{V}_{\text{IN}} \tag{6}\]  
M9 and M3 use Deep-Nwell (DNW) MOSFETs to decrease the effect of channel length modulation. M7 is applied to prevent the risk of breakdown in M5. During the hold phase (blue arrow), CLKN changes from DVSS to DVDD. M1, M2, and M6 turn on. CB begins to charge, while VG discharges to zero potential through M5 and M6.