## 3 Underwater Communication Experiment and Discussion
### Analysis of FPGA Resource Utilization  
The system is designed to support bidirectional communication, with all functional modules implemented on the FPGA's logic resources. The resource utilization after synthesis is illustrated in Figure 17a. As shown in the figure, the look-up table (LUT) utilization is 17.99%, which is relatively high compared to other resources. This is primarily attributable to the complex computational tasks involved in the system, including AXI protocol data interactions, filtering operations, RS code encoding/decoding, and other intricate logic functions. To reduce LUT resource consumption, algorithm optimization can be applied to refine computation-intensive modules, eliminating redundant logic and minimizing unnecessary LUT usage. Additionally, a pipelined architecture can be implemented to distribute LUT resource requirements more evenly, alleviating bottlenecks caused by centralized logic operations. The DSP utilization is relatively low at 4.09%, achieved by converting a significant portion of multiplication and division operations into shift-and-addition operations, thereby reducing the demand for DSP resources. The BRAM utilization is only 2.5%, contributing to the overall stability of the system. This low utilization is achieved by storing data in DDR mode, which greatly reduces the reliance on the PL-side BRAM. However, this approach shifts part of the resource burden to the PS side, leveraging the unique advantages of the ZYNQ7020 development board. Twenty percent of the system's IO resources are allocated for data interaction between the FPGA and peripherals, such as the ADC and DAC. The flexible configuration of IO resources in the FPGA ensures efficient and accurate data transfer between the digital and analog domains. Furthermore, the abundant IO resources provide scalability for future system expansion, enabling theintegration of additional peripherals for underwater environmental monitoring, such as temperature sensors and other sensing modules. The system power consumption is illustrated in Figure 17b, which comprises two primary components: dynamic and static energy consumption. The dynamic energy consumption dominates, accounting for 92% of the total, while the static energy consumption constitutes the remaining 8%. Within the dynamic energy consumption, the PS module is the largest contributor, consuming 85% of the total power. This is primarily due to data interactions between the host computer and the PS side, as well as extensive storage tasks on the DDR. The overall power consumption of the system is maintained at a low level of 1.921 W. To further reduce system power consumption, dynamic voltage and frequency scaling (DVFS) technology can be used on the PS side to dynamically adjust the operating voltage and frequency according to the load conditions, thus significantly reducing power consumption during low-activity periods, while gated clocks can be used on the PL side to apply gated clocks on the programmable logic (PL) side to deactivate unused logic modules during idle states, thus further reducing power consumption. Further comparative analysis between the optimized RS coding module and the official IP reveals significant improvements in resource efficiency (LUTs and registers) and low power consumption, while maintaining competitive throughput, as illustrated by the metrics listed in Figure 18. By converting Galois field multiplication into bitwise XOR operations, particularly during the encoding process, the hardware complexity is effectively reduced. Specifically, the proposed design achieves a 16.4% reduction in LUT usage, a 31.2% reduction in register usage, and a 35.7% reduction in power consumption, with only a 15.2% decrease in throughput, from 151 MHz to 128 MHz. However, considering the actual communication rate of the system, this design not only meets the requirements but also provides considerable redundancy margin.