## 5 Discussion  
We introduced an experimental instrumentation based on widely available COTS components for in-depth monitoring of SEEs in electronic systems. Using a case study (SRAM memory), we presented the main characteristics of the proposed approach, discussed the obtained results, and provided examples exploiting the instrumentation capabilities. As discussed, traditional SEL monitoring solutions for memories often just count overcurrent events and rarely report the correlation with other types of events. In particular, coherent timestamping is another missing capability, reducing the opportunities for in-depth analysis. Even if different test modes are employed, many setups perform the current monitoring with external circuitry, lacking the correlation between events and current spikes. The proposed instrumentation provided a solution for these limitations, enabling enhanced analysis of the observed effects. Notably, when compared to traditional or simplified approaches, some important conclusions for this study would not be possible, such as the correlation between SELs and SEFIs (error accumulation), which required precise time synchronization. This information was necessary to support the understanding of the flight behavior of the studied SRAM memories, as reported in prior work [14].  
Besides that, the proposed instrumentation has an adequate resolution on the individual SEL events with more precise current logging with high-frequency sampling and clustering capabilities. The usage of fine-grain measurements highly improves the investigation of the observed events, providing details of the induced errors using information about their current signatures and faulty behavior. The instrumentation also allowed the characterizing of other SEE cross sections, which improves the overall knowledge about the  
Figure 9: Logical bitmap of the memory address space with examples of identified SEFIs during distinct SELs. The \(x\) and \(y\) axis represent addresses in an arrangement based on the logical memory organization with arrays, rows, and columns, as specified on the datasheet [12]. For this bitmap, a partial March C- (1) run is shown, in which isolated SEUs were hidden to allow better visualization of the clusters. The highlighted groups 1, 2, and 3 represent the identified types of clusters.  
memory's response to radiation effects. Table 2 summarizes the performance and functional parameters of the developed instrumentation.  
It is worth mentioning that this instrumentation is not limited to SRAM memories since it can be used for other memory types. Only a few adaptations are required, such as addressing size, pin assignments, and specific protocols. In some cases, even the same test board could be used since the memories are often built with similar chip packages and pinouts. Since the proposed instrumentation is based on an FPGA, it has a very flexible pin assignment that supports easy integration with other memory types. Furthermore, as discussed in Section 4 with a few examples, the strategy presented in this work can be extended to other device types and more complex systems, such as microprocessors, FPGAs, and systems-on-chip. To achieve that, the test engine and error reporting should accommodate other types of tests (e.g., benchmark output checking). With this type of SEE monitoring with enhanced synchronization, it is possible to identify the current signatures of the tested device for a broad range of workloads and operational modes. Using this information, researchers can compile a dictionary with current signatures correlating operational states and SEL response that could provide more capabilities for predicting systems behavior under the target radiation environments.