# Algorithmic Design of an FPGA-Based Calculator for Fast Evaluation of Tsunami Wave Danger
## 2 Materials and Methods
### HLS-Based Algorithm Porting
Since the Verilog synthesizer does not have standard operations on floating point numbers, ready-made libraries (IP cores) were used as part of Xilinx _Vivado_. Unfortunately, the Verilog language is not sufficient to write universal parameterizable code, so part of the module had to be implemented in a fixed manner, for a kernel size equal to 3. The HLS system allows synthesis with the setting of the required maximum frequency, which allows one to adjust the maximum frequency/size ratio of the final circuit. For Verilog code, one must modify the code to increase the frequency. In fact, there are alternative options to increase the frequency. However, RTL synthesis and implementation are very limited in what they can improve within design, because structure/behavior is strictly specified. For example, they cannot increase pipeline depth automatically to achieve better timing. HLS tools, on the other hand, are free to choose how to implement the desired algorithm. In addition, using the C++ language and HLS, it is possible to easily replace the float type with half-precision or fixed-point numbers by changing exactly one line. However, we did not use this option for tsunami-related applications. The HLS code was synthesized for 148.5 MHz (1080p50 video frequency) and 400 MHz (close to the theoretical FPGA limit). The final synthesis took place for the Zynq UltraScale + (xczu7 ev) platform. All solutions were analyzed for maximum frequency using Vivado tools. Strictly speaking, the maximum frequency is not explicitly given in Vitis/Vivado timing reports. Vivado HLS can report Fmax, calculated from post-synthesis timing reports (using the \"target period-worst slack\" formula); the same was done for the Verilog design. Target frequency (specified in constraints) was the same as the target frequency for the HLS design (400 MHz and 148.5 MHz), and 148.5 MHz for Verilog, which is not a real frequency on which the implemented design can run. All of the algorithms on any platform operate on data in single-precision floating point (IEEE 754) format; no conversions to fixed points or half-precision were made. Such conversion may result in better FPGA resource utilization, but requires deep data analysis for every case, and is beyond our consideration here. The final results are presented in the table below. As can be seen from Table 1, in the example of real tasks, the amount of program code was reduced by 5-8 times, while the implementation performance (clock frequency of operation) was maintained. However, the side-effect was an increase in the number of logical blocks (LUT) and arithmetic processing blocks (DSP). The increased memory block consumption in the naive HLS example demonstrates that in order to use HLS effectively, one must know the FPGA's structure and features well. ### Tsunami Math Model and Numerical Scheme

To simulate the tsunami wave propagation, the nonlinear shallow water PDE system [9] was used. \[ \begin{split} H_{t}+\left(uH\right)_{x}+\left(vH\right)_{y}=0,\\ u_{t}+uu_{x}+vu_{y}+gH_{x}=gD_{x}\\ v_{t}+uv_{x}+vv_{y}+gH_{y}=gD_{y},\end{split}  \tag{1}\]

where \(H(x,y,t)=\eta(x,y,t)+D(x,y)\) is the distance from the sea's surface to the bottom, \(\eta\) is the sea surface displacement relative to the mean sea level (wave height), \(D(x,y)\) is the water depth (which is supposed to be known at all grid points), \(u\) and \(v\) are the water flow velocity components in the \(x\) and \(y\) directions, respectively, and \(g\) is the gravity force acceleration. Note that the lower indices \(t\), \(x\), \(y\) in (1) indicate partial derivatives with respect to time and space variables. For numerical experiments, the following finite-difference MacCormack scheme [3] was implemented: