# HAIPO: Hybrid AI Algorithm-Based Post-Fabrication Optimization for Modern 3D NAND Flash Memory
## 1 Introduction
Therefore, manually optimizing a large number of device parameters within a limited time requires significant human effort and often fails to obtain optimal results. To address the challenges in post-fabrication optimization, we introduce HAIPO (Hybrid AI Algorithm-based Post-fabrication Optimization), a new post-fabrication optimization scheme that enables optimizing modern high-density 3D NAND flash memory to better meet various performance, reliability, and yield requirements within the limited optimization TAT during NAND manufacturing. HAIPO aims to automatically search and find the optimal eFuse combinations based on deep learning (DL) [5] and evolutionary algorithm (EA) [6]. HAIPO uses (_i_) a lightweight deep-learning (DL) model to generate initial device parameters that can roughly meet the given design requirements and (_ii_) an evolutionary algorithm (EA) to automatically explore device parameters from the initial values. In addition, to more carefully yet more extensively explore the device parameter sets (i.e., populations), HAIPO introduces three key guidelines for each generation in the EA to generate device parameters. First, it ensures that each population satisfies a set of _predefined rules_ based on domain-specific knowledge from experienced engineers. If the EA generates a value that violates any rules, HAIPO chooses a random value that meets all related rules. Second, HAIPO checks that every device parameter is in a desirable value range based on the _recent populations_ (i.e., _newborns_) that provide the highest performance and reliability levels (i.e., the highest achievement score). Third, HAIPO _simulates_ the optimization level of each population based on a simple Bayesian model (trained online with real-measurement results) to select the best populations to be tested on real chips. By doing so, we can effectively evaluate a large number (e.g., \(\sim\)10\({}^{7}\)) of populations within the limited measurement times, which accelerates the entire post-optimization process. In addition, to further improve the efficiency and robustness of our HAIPO, we integrate two optimization modules with our technique. These modules enable HAIPO both to take into account chip variation due to complex 3D manufacturing processes and to improve the optimization TAT in an environment where multiple requirements must be satisfied simultaneously. To validate the effectiveness of our technique, we evaluate HAIPO using 320 real state-of-the-art 3D TLC/QLC NAND flash chips. Our results show that HAIPO improves the performance and reliability of NAND flash chips by 12% and 8.8% on average, respectively. Furthermore, HAIPO efficiently reduces the total optimization TAT up to 70% compared with the manual-based optimization. The rest of this paper is organized as follows. In Section 2, we review the overview of NAND flash memory and NAND eTuse tuning operations. Section 3 provides a key concept of NAND post-fabrication optimization. In Section 4, we present a design and implementation of our technique, HAIPO. The experimental results follow in Section 5, and the related work is summarized in Section 6. Section 7 concludes with a summary and future work.