# Design of a Broadband and High-Isolation CMOS Active Quasi-Circulator
## 2 Circuit Design and Implementation
Thus, a criterion for achieving perfect amplitude imbalance can be defined as follows:  
\[\left|\frac{S_{21}^{AQC}}{S_{32}^{AQC}}\right|=1 \tag{4}\]  
By substituting (1) and (2) into criterion (4), the relationship between \(g_{m1}\) and \(g_{m2}\) can be obtained as follows:  
\[\frac{g_{m1}}{g_{m2}}=\frac{1+(\omega C_{1}Z_{0})^{2}}{\sqrt{\left(1+\left( \omega C_{1}Z_{0}\right)^{2}\right)\left(1+\left(\omega C_{3}Z_{0}\right)^{2} \right)}} \tag{5}\]  
Figure 3: (**a**) Simplified FET model. (**b**) Equivalent network of the quasi-circulator. From (5), the quasi-circulator can exhibit a perfect amplitude imbalance by regulating the FET dimension and bias voltage. In addition, to acquire the superior \(\mid\)S31 \(\mid\) isolation, we suppose that \(\left|S_{31}^{AQC}\right|=0\). From (3), the relationship between \(g_{m3}\) and \(g_{m1}\), \(g_{m2}\) can be derived as follows:  
\[g_{m3}=\frac{g_{m1}g_{m2}Z_{0}}{1+j\omega C_{2}Z_{0}} \tag{6}\]  
The dimension of M3 FET can be explicitly defined by design criterion (6) to emerge the phase cancellation at port 3. Consequently, from design criteria (5) and (6), the proposed quasi-circulator delivers perfect amplitude imbalance and superior \(\mid\)S31 \(\mid\) isolation. In this condition, Vds1 has a higher influence on the noise figure than Vds2. Thus, a smaller bias condition is essential. Figure 4 shows the simulated S-parameters of different isolation curves between port 1 and port 3 at various widths of M1 at 5-33 GHz. The channel length is 90 nm. The notch of the curve at 10 GHz is formed by best matching parasitic capacitors of transistor M3's width at 3 \(\upmu\)m.  
Figure 5 shows the simulated insertion loss and isolation of the proposed quasi-circulator. The simulated results of insertion loss of S21 are around 4.8 to 9.8 dB, and of S32 are approximately 4.1 to 7.9 dB in Figure 5a. Figure 6 shows the simulated isolation results. A superior isolation performance of nearly 90 dB around 10 GHz of S31 can be seen in Figure 5b. All of the return losses in the range of 5 to 35 GHz are better than 10 dB over this time period, as shown in Figure 6a. The isolation of S12 and S23 is 18 to 22 dB and 46 to 51 dB separately in Figure 6b. The quasi-circulator was fabricated by TSMC 90 nm 1P9M CMOS technology. Figure 7a shows a schematic of the quasi-circulator. Table 1 provides a detailed account of the intricate circuit's specifications: The M1 assembly employed a ten-finger nMOS device with a gate width of 3 \(\upmu\)m. The twenty-finger nMOS device, with a gate width of 2 \(\upmu\)m, was used for M2. The M3 implementation involved the use of an nMOS device with forty-three fingers and a gate width of three micrometers. To maintain amplitude balance and input matching for port 1 across a wide operating bandwidth, the drain voltages (VDS1, VDS2) have been adjusted to 0.5 V and 1 V, respectively. The resistor Rb (3.5 K\(\Omega\)), the drain inductor L1 (2 nH), and the drain inductor L2 (3.6 nH) were all adjusted to ensure optimal matching. The capacitors CS1, CS2, and CS3, with capacitance values of  
Figure 4: Simulated S31 as a function of frequency at various widths of transistor M3. 0.289 pF, 0.45 pF, and 0.3 pF correspondingly, served as the DC-blocking capacitors for ports 1, 2, and 3. Figure 7b shows the photograph of the chip. The chip's dimensions are 0.64 \(\times\) 0.58 mm\({}^{2}\), including the testing pads. For the fabrication of the proposed quasi-circulator, three nMOSFETs with fT values above 142 GHz were employed. In order to achieve wideband performance and smooth gain flatness, an active balun with a cascading structure was chosen. Phase cancellation is a technique that can be used to isolate the suggested quasi-circulator. The reverse phase path is enabled by the CS FET. By employing criteria, an iterative electromagnetic simulation, and a TSMC kit, it is feasible to adjust the dimensions of the practical FET and the circuit characteristics to achieve exceptional performance.