# Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection
## 2 Silicon Photonics for High-Speed Data Communications
### Hybrid Integration  
As briefly discussed so far, silicon photonics has undergone remarkable progress, demonstrating its potential to replace the legacy copper-based interconnections. Nevertheless, some issues have yet to be addressed to prevent degradation of the performance of the EPIC. Moreover, the compatibility with a FinFET CMOS platform is unknown and should be investigated in the future. Alternatively, a hybrid integration leveraging the respective process optimizations of the EIC and the PIC would be more advantageous at present, and it has become viable owing to advanced 3-D integration techniques. In this section, several recent works based on the hybrid integration will be reviewed and compared with the monolithic integration in various aspects. The most common integration method is the use of a wire-bonding technique which has been prevalently used in EIC packages. However, wire bonding severely degrades the signal integrity as the data rate becomes higher, because the length of a wire is directly translated into an inductance. For even higher data rates, the situation degrades as the wavelength of the signal becomes comparable to the length of the wire. Due to its relatively large dimension, wire bonding also limits the maximum pin density; hence, it is not appropriate for modern system-on-chip packages where an extremely high pin density is required. Nevertheless, thanks to its distinguishably low-cost characteristic, it is still widely used for low-speed packages and chip-on-board test environments. An example of the integration of EPIC based on wire bonding is shown in Figure 13. A typical PD can be wire-bonded to a TIA chip and the output of the TIA is connected to a trace on a printed circuit board (PCB) to  
Figure 11: Schematic view of EPIC structure [51]. Figure 12: Block diagram of optical transceiver [51]. interface with high-speed end-launch connectors. Based on wire bonding, the works in [52; 53] achieve operating data rates of 25 Gb/s and 64 Gb/s, respectively. Flip-chip bonding is a more advanced technique based on face-to-face bonding, completely eliminating the bond wires. Because of a shortened chip-to-chip space (several tens of \(\upmu\)m with modern techniques), the parasitic elements can be significantly reduced, resulting in improved signal integrity at higher speeds. Figure 14 illustrates a typical flip-chip package. The PD chip and the TIA chip are flip-chip bonded on the same package substrate through which high-speed signal interconnection is made. The output of the TIA is connected to the PCB trace via the package and the solder bump. In this case, the structure of the PICs should be a back-illumination type for proper fiber coupling. With this configuration, the work in [54] presents a 4 \(\times\) 28-Gb/s optical receiver exhibiting good sensitivity. Similarly, but in a slightly different manner, the EIC and the PIC are stacked vertically using an interposer as shown in Figure 15[55], realizing a 12 \(\times\) 5 two-dimensional EPIC array in order to maximize the I/O density. The implemented transceiver chip achieves a total aggregate data rate as high as 600 Gb/s. Figure 14: Illustration of flip-chip package [54]. Figure 13: Illustration of wire-bonded EIC and PIC. Figure 15: Implementation of 2-D array of EPIC [55]. Figure 16 illustrates an improved flip-chip package that directly bonds the EIC and the PIC using micro bumps, thus obviating any redistribution layer between the high-speed regions to further reduce the parasitic components. The rest of the signals are connected to the package substrate through C4 bumps. An additional cost may be incurred by such a package technique due to the requirement of a customized substrate. Currently, the most advanced technique is shown in Figure 17. Contrary to the previous technique, it uses the PIC as a redistribution layer itself, thus simplifying the package process [40; 43; 57]. The EIC is flip-chip bonded to the macro PIC in a similar way.