# A New SEPIC-Based DC-DC Converter with Coupled Inductors Suitable for High Step-Up Applications
## 3 Semiconductor Stresses and AC Analysis of the Proposed SEPIC-Based Converter  
### Semiconductor Stresses and Ripples Calculation  
From the analysis carried out in the previous section, the semiconductor stresses are determined, neglecting the capacitor voltage ripples. These semiconductor stresses are also needed for the converter design. The maximum voltage across switch \(S\) is obtained from the second topological state, while the dc transistor current stress can be found from the first topological state. The voltage across switch \(S\) is equal to the sum of the internal capacitor voltage, \(V_{\text{C1}}\), and the output capacitor voltage, \(V_{\text{C2}}\). By replacing \(V_{\text{C1}}\) and \(V_{\text{C2}}\) from (6) and (7), the transistor voltage stress is:  
\[V_{S}=\frac{n+D}{n\times(1-D)}\times V_{g} \tag{13}\]  
The current flowing through the transistor is the sum between \(i_{LM}/n\) and \(i_{L3}\). Hence, the dc transistor current stress is: \(D\times\left(\frac{I_{LM}}{n}+I_{L3}\right)\). By replacing \(I_{LM}\) and \(I_{L3}\) from (11) and (12), the transistor current stress is:  
\[I_{S}=\frac{D^{2}\times(n+D)^{2}}{n^{2}\times(1-D)^{2}}\times\frac{V_{g}}{R} \tag{14}\]  
The voltage stress for diode \(D_{\text{I}}\) can be found from the second topological state being equal to \(\frac{V_{g}-V_{\text{C1}}-V_{\text{C2}}}{1+n}\). Using (6) and (7), it results that:  
\[V_{\text{D1}}=\frac{D}{n\times(1-D)}\times V_{g} \tag{15}\]The current through diode \(D_{1}\) is equal to \(i_{LM}/n\), and therefore the dc current through \(D_{1}\) is \(D\times\frac{I_{LM}}{n}\). With \(I_{LM}\) given by (11), one obtains:  
\[I_{D1}=\frac{D^{3}\times(n+D)\times(1+n)}{n^{2}\times(1-D)^{2}}\times\frac{V_{g }}{R} \tag{16}\]  
Similarly, the voltage stress across diode \(D_{2}\) is obtained from the first topological state, while from the second topological state, the dc current through diode \(D_{2}\) results as:  
\[V_{D2}=\frac{V_{g}}{n} \tag{17}\]  
\[I_{D2}=(1-D)\times\frac{I_{LM}}{1+n}=\frac{D^{2}\times(n+D)}{n\times(1-D)} \times\frac{V_{g}}{R} \tag{18}\]  
The voltage stress across \(D_{4}\) is the sum between \(V_{C1}\) and \(V_{C2}\). Using (6) and (7) it immediately follows that:  
\[V_{D4}=\frac{n+D}{n\times(1-D)}\times V_{g} \tag{19}\]  
As \(D_{4}\) conducts the sum of the currents \(\frac{i_{LM}}{1+n}+i_{L3}\) in the second topological state, taking (11) and (12) into account, the dc \(D_{4}\) current is found as:  
\[I_{D4}=(1-D)\times\left(\frac{I_{LM}}{1+n}+I_{L3}\right)=\frac{D\times(n+D)}{ n\times(1-D)}\times\frac{V_{g}}{R} \tag{20}\]  
Peak-to-peak inductor currents and capacitor voltages ripples are also invoked in the design equations and in the CCM operation conditions. The magnetizing peak-to-peak current ripple can be written as:  
\[\Delta I_{LM}=\frac{D\times V_{g}}{n\times L_{M}\times f_{s}} \tag{21}\]  
The peak-to-peak current ripple for the inductor \(L_{3}\) is given by:  
\[\Delta I_{L3}=\frac{D\times(n+D)\times V_{g}}{n\times L_{3}\times f_{s}} \tag{22}\]  
For the internal capacitor \(C_{1}\), the peak-to-peak voltage ripple is expressed as:  
\[I_{S}=\frac{D^{2}\times(n+D)^{2}}{n^{2}\times(1-D)^{2}}\times\frac{V_{g}}{R} \tag{14}\]0  
The output capacitor peak-to-peak voltage ripple is:  
\[I_{S}=\frac{D^{2}\times(n+D)^{2}}{n^{2}\times(1-D)^{2}}\times\frac{V_{g}}{R} \tag{14}\]1  
According to the CCM operation condition, it is necessary that the diodes be on during the whole topological state during which they are planned to conduct. This imposes the condition that the minimum diode current has to remain positive during the corresponding topological state. Taking into account that the converter includes three diodes, this will result in three CCM conditions. As the currents through \(D_{1}\) and \(D_{2}\) are equal to \(\frac{I_{LM}}{n}\) and \(\frac{I_{LM}}{1+n}\) respectively, for these diodes, the CCM condition is the same.