# A Novel ASIC Implementation of Two-Dimensional Image Compression Using Improved B.G. Lee Algorithm
###### Abstract
The design was improved further by incorporating an efficient adder and approximation-based shifter. Although the power was reduced, the critical path delay was slightly increased compared to existing architectures. A DCT technique using approximate computing was proposed by [PERSON] et al. [19] to configure the transform matrix size in accordance with the retained coefficients obtained in the scanning. The proposed technique's addition operations and energy were lesser than the existing approximate computing technique. The simulation of the proposed technique was evaluated using MATLAB and on an FPGA platform. Significant reductions in power, gate counts, implementation time, and the number of adders were observed compared to the existing approximate adders. [PERSON] et al. [20] computed an eight-point DCT using a modified Loeffler scheme where the multiplications are performed in the last stage. A new approximation algorithm using shift and add operations in place of multiplications is also incorporated into their work. A novel distributed arithmetic architecture was proposed by [PERSON] et al. [21] that focused on reducing the area and power. The newly introduced compression scheme generated a butterfly structure with lesser additions. [PERSON] et al. [22] introduced a 2m-point algorithm for DCT with almost half the multiplication operations compared to the efficient prevailing algorithms in his work. Even though the structural design of the algorithm was more straightforward than the existing algorithms, the number of additions involved was slightly higher. The algorithms mentioned above, even though fast, require floating-point multiplications resulting in complex and slow implementations. Faster computations can be accomplished by scaling and approximating the coefficients in the algorithms to substitute floating-point multiplications with fixed-point multiplications. The resulting algorithms are considerably faster than the existing designs, making them beneficial in many practical applications. These fast algorithms require a data bus of larger width to perform the fixed-point computations demanding an expensive VLSI implementation and higher power consumption. Hence, the DCT implementations using regular arithmetic computations and limited bus width is an area that attracts research. High compression rates can be attained with DCT, but with high computational complexity and energy overheads. The human eye can tolerate minor degradations in the quality of the images by including small errors. DCT computations utilizing approximate computing have been proposed and designed in this research to reduce the computations and improve performance. The input data are optimized using pipelining in the different stages of the DCT and IDCT algorithm improving the processing speed. The complexity of the arithmetic computations and power are minimized by utilizing error-tolerant adders, signed fixed-point multipliers, and shifters. Through the separability property of 2D DCT, the row-column decomposition approach is applied to compute the 2D DCT of each 8 \(\times\) 8 image block segment. Each 8 \(\times\) 8 image block's DCT and IDCT can be accomplished with an abridged circuit complexity and enhanced efficiency in 34 clock cycles. The B.G. Lee DCT algorithm design structure and the optimization of the B.G. Lee DCT algorithm using the proposed method is discussed in the methodology section. Section 3 illustrates the ASIC implementation of 2D DCT/IDCT based on the B.G. Lee algorithm and the detailed architectural design utilizing the proposed error-tolerant adders and fixed-point multipliers. The implementation of the proposed method and the performance metric comparison of the proposed and prevailing DCT/IDCT architectures is presented in Section 4. Section 5 concludes the overall research.