# A Novel Cross-Latch Shift Register Scheme for Low Power Applications
## 2 The Proposed Cross-Latch Shift Register (CLSR) Design  
Figure 1 shows the process of data transmission for a conventional shift register under different clock signals (CLK = 1 and CLK = 0). As shown in Figure 1a, for a shift register with a positive edge triggered flip-flop, when CLK = 0 at the first stage flip-flop (FF0), the master latch (M0) is opened and receives the input data while the slave latch (S0) is closed and stores the previous data. At the same time, in the second stage flip-flop (FF1), the master latch (M1) will track the data stored in the slave latch (S0) of FF0. Likewise, as shown in Figure 1b, when CLK = 1, the slave latch of each flip-flop will track the data in the master latch and send it to the output. According to a data transmission analysis, it can be observed that when CLK = 0, the slave latch (S0) of FF0 and master latch (M1) of FF1 store the same data. When CLK = 1, each flip-flop holds the same data in the master and slave latches, respectively. This situation leads to storage of redundant data in many latches. Implementing and keeping this state may consume extra electrical power and may occupy more overhead integrated circuitry layout area. Note that in addition to showing the traditional transmission gate flip-flop (TGFF), Figure 2 also includes three recently proposed low-power FF designs [28; 29; 30]. Figure 2b shows the adaptive coupling (AC) flip-flop design [28]. Unlike the traditional MS latch-based design, this design uses a differential latch structure with pass transistor logic to achieve true single-phase clock (TSPC) operation. To overcome the effects of process variation on the master latch, a pair of level recovery circuits were inserted into the cross-coupled path. In this design, the clock drives only 4 transistors, and the total number of transistors is 22. When the FF operates at lower data-switching activity, lighter clock loads and reduced circuitry in the FF design can significantly reduce dynamic power consumption. However, there are floating problems in several nodes inside this FF design, which impose limitations on the applications of the ACFF design [28]. Figure 2c shows the true single-phase clock flip-flop, named TSPCFF [29]. It is composed of a conventional dynamic TSPC-based FF design with 9 transistors colored in blue and an additional 9 transistors to ensure its static operations and sufficient output drive capability. This FF design provides better power performance compared with the traditional TGFF design. Similar to the ACFF design, it also suffers from the floating problem of internal nodes. The CSFF (charge sensing flip-flop) design incorporates an XOR logic in its master latch to compare inputs D/DN with outputs QI/QN, as shown in Figure 2d [30]. In this architecture, the input data are captured only when a discrepancy occurs. This gives a performance edge in power consumption over conventional MS latch-based FF designs when the data switching activity is low. The simulation results indicate that this design encounters a floating problem of an internal node, as shown in  
Figure 3. Referring to the simulation waveforms shown below, if input data D change when CK = 1, internal nodes CS and DN are actually in a floating state, which adversely leads to extra power consumption in following inverter. Due to this reason, these FF designs are thus excluded from the performance comparison in this paper. These circuits use a true-signal-clock phasing scheme to reduce clock load and reduce dynamic power consumption. However, some internal floating nodes exist. Figure 3 shows the simulation waveforms of these FF designs. Therefore, in these designs, the same internal floating nodes dissipate additional static power consumption. Although this issue does not affect its function, additional static power consumption is confirmed, especially at low operating speeds or standby mode.