# Improved Safety Analysis Integration in a Systems Engineering Approach
## 2 State of the Art  
This section discusses the state of the art concerning the integration of safety analysis in the systems engineering approach in order to compare the existing work with the proposed methodology. The related work is divided into two parts: the integration of the SA in the MBSE process and the automatic generation of FTA. For the integration of SA and MBSE, most of the works considered the extention of system models to enable the automatic generation of safety artifacts. In [12], [PERSON] proposed a methodology that deals with the integration of the MBSA in the MBSE process. A SysML extension is created in order to include information about safety in the system model, which gives an opportunity to the systems expert to make some decisions without the assistance of the safety expert. A Safety Analyzer program is developed in order to extract relevant information from the system model. As outputs of the developed program, a group of minimal cut sets is given for all system failure modes. [PERSON] et al. presented a methodology in [17] called MeDISIS. On one hand, it tries to generate an FMEA from structural and behavioral diagrams in SysML models. On the other hand, it aims at constructing the dysfunctional models using AltaRica language [18] to compute the reliability indicators. The methodology starts by an automatically generating a preliminary FMEA. A set of structural diagrams (Internal Block Diagram (IBD) and Block Definition Diagram (BDD)) and behavioral diagrams (activity diagram and sequence diagram) are analyzed in detail in order to give, for each component and function, a complete list of failure modes with their possible causes and effects. Then, a safety expert completes the final FMEA. The second step of MeDISIS is the mapping between SysML models and AltaRica language in order to ensure the direct assignment of reliability indicators to the failure modes generated in the first step. Concerning the generation of the fault trees from system models, we cite some works that allow the generation of the static and dynamic fault trees from system structure. The related work is divided into two categories: works that do not consider the redundancy in the generation of fault trees such as [19; 20; 21; 22; 23; 24] and others that consider the redundancy during the generation of fault trees such as [25; 26; 27; 28; 29]. [PERSON] et al. in [28] developed an algorithm that allows the generation of the Temporal Fault Trees (TFT) from state machines. A recent technique for introducing temporal logic to fault trees named Pandora is used to ensure the generation. This work considers the redundancy behaviour during the transformation from the state machine to TFT. [PERSON] and [PERSON] in [27] developed an approach which permits the dynamic fault trees generation from UML diagrams. The description of the system and the components dependencies are modeled by UML diagrams. A failure model, which gathers all components properties, is created using the system description and the failure properties of components. Then, based on the functional dependencies between components, the logical gates of FT are chosen. Finally, each logical gate is allocated to its respective nodes of the failure model. [PERSON] and [PERSON] in [26] extended the approach of [PERSON] [21] in order to generate a DFT from Architecture Analysis and Design Language (AADL). To consider the redundant components and the temporal sequences of failures in the DFT, the static fault tree generated by [PERSON] is enriched. They consider the redundancy, the dependent failures, and the reconfiguration activities during the generation of FTs. These works present some limits such as they only use the static and spare gates and they do not manipulate any of the active, standby (with and without switch), and mixed redundancies. In [29], [PERSON] proposed an approach which allows the generation of the SFT using a model transformation from UML diagrams.