## 3 Target Platforms
\begin{table}
\begin{tabular}{p{56.9 pt} p{56.9 pt} p{56.9 pt} p{56.9 pt} p{56.9 pt} p{56.9 pt}} \hline \hline
**Ref.** & **Implementation** & **Platform** & **Trace Type** & **Preprocessing** & **Classifier** \\ \hline
[36] & HW: FPGA & Virtex-II Pro & PT \({}^{1}\) & mean of consecutive samples, PCA \({}^{3}\) & visual inspection \\ \hline
[21] & HW: FPGA & Spartan-3 & PT, EMT \({}^{2}\) & sum of squared values in each clock cycle & k-means \\ \hline
[38] & HW: FPGA & Spartan 3A & EMT & PCA & EM \({}^{4}\) clustering \\ \hline
[41] & SW: simulation & 8-bit AVR microcontroller & PT & averaging over multiple traces (same point means same precomputed values) & k-means \\ \hline
[42] & SW & - & PT & SdAEN \({}^{5}\) & k-means; IDEC \({}^{6}\) \\ \hline
[44] & SW: \(\mu\)NaCI & ARM Cortex-M4 & EMT & low-pass filter, outliers replaced with median of non-outliers & k-Means, fuzzy k-means, EM clustering, SOSD \({}^{7}\), MIA \({}^{8}\) \\ \hline
[46] & HW: FPGA & Virtex-5 & EMT & k-means, DoM \({}^{10}\), covariance, variance, range as POI selection trace alignment (for SW) \\ \hline
[47] & HW: FPGA & SASEBO-CH FPGA & PT, EMT & low-pass filter, POI \({}^{11}\) selection with SOSI, trace alignment & k-means, fuzzy k-means, EM, SPA \({}^{12}\) \\ \hline
[39] & HW: FPGA & Spartan 6 & PT & sum of squared values in each clock cycle & difference to the mean and k-means \\ \hline
[18] & SW: \(\mu\)NaCI & ARM Cortex-M4 & EMT & low-pass filter, Gradient Visualization for POI selection & CLA \({}^{13}\) (k-means, fuzzy k-means, EM clustering) followed by CNN \({}^{14}\) \\ \hline
[17] & HW: FPGA, ASIC & Spartan 6 & PT, EMT & sum of squared values in each clock cycle & difference to the mean followed by SVM \({}^{15}\) \\ \hline  & & & & & followed by ANN \({}^{16}\) \\ \hline  & & \multicolumn{1}{p{56.9 pt}}{\({}^{1}\) Power Trace, \({}^{2}\) Electromagnetic Trace, \({}^{3}\) Principal Component Analysis, \({}^{4}\) Expectation Maximization, \({}^{5}\) Stacked Denoising Autoencoder, \({}^{6}\) Improved Deep Embedded Clustering, \({}^{7}\) Sum of Squared Differences, \({}^{8}\) Sum of Squared \(t\)-values, \({}^{9}\) Mutual Information Analysis, \({}^{10}\) Difference of Means, \({}^{11}\) Points of Interest, \({}^{12}\) Simple Power Analysis, \({}^{13}\) Clustering Leakage Assessment, \({}^{14}\) Convolutional Neural Network, \({}^{15}\) Support Vector Machine, \({}^{16}\) Artificial Neural Network.} \\ \hline \end{tabular}
\end{table} 
Table 1: Summary of related work. The **Controller** block governs the sequence of field operations within the design and the data flow among different blocks and chooses the specific operation to be executed in the ongoing clock cycle. Whenever the **ALU** block is active, it is responsible for carrying out either addition (utilizing bitwise XOR) or squaring operations. Meanwhile, the always-active **MULT** block, functioning as the field multiplier, computes a field product, employing the four-segment Karatsuba multiplication method iteratively. Throughout the years, we have developed different versions of the ECSM accelerator. In this work, we use the following variants of the accelerator:  
* Design_ultra is a specific instance of our ECSM design that was compiled with the Synopsys Design Compiler using the compile_ultra feature. This high-effort compilation process involves logic-level and gate-level synthesis and optimization, aiming to achieve an optimum quality of results. The compile_ultra feature leverages all DC Ultra capabilities, balancing timing and area limitations to deliver a compact circuit that meets stringent timing criteria. The exhaustive compilation enhances synthesis quality, resulting in improved performance, reduced design area, and lower power consumption. Design_ultra was manufactured into an ASIC. in the IHP 250 nm technology [51]. The compile options increased the resistance of the design against SCA attacks.