## 2 Materials and Methods
### Definition and Design of the System's Components
#### 2.2.3 Internal Interfaces to Connect FPGA/LED Driver and FPGA/PD Driver
This amplifier was manufactured by Analog Devices and bought on [[https://mouser.com/](https://mouser.com/)]([https://mouser.com/](https://mouser.com/)) (accessed on 5 September 2024). Furthermore, the amplitude of the single-ended signal was increased to 800 mV\({}_{\text{pp}}\), as illustrated in Figure 17.  
We opted for the TXO crystal oscillator to generate the clock signal, which produces a stable 40 MHz square wave. This oscillator is renowned for its stability and is frequently utilized in wireless Internet of Things (IoT) applications employing the LoRa WAN protocol [36]. The crystal oscillator is integrated into the interface and can be connected to the MAX5184 DAC via a jumper. Alternatively, the clock signal can be generated from the Xilinx Zynq 7020 FPGA [37], which is integrated into the TE0720 SoC, and connected to the MAX5184 DAC [34] by adjusting the jumper's position. Considering that the output impedance of \(OUT_{P}\) and \(OUT_{N}\) is 400 \(\Omega\)[34], the resistors \(R_{1}\) and \(R_{3}\) were set to 402 \(\Omega\), which is the closest standard value to 400 \(\Omega\). By analyzing the circuit loops depicted in Figure 17, we derived the following equations:  
\[\frac{V_{\text{{OUTPUT}}}-V_{+}}{R_{1}}=\frac{V_{+}}{R_{2}} \tag{6}\]  
\[\frac{V_{\text{{OUTPUT}}}-V_{-}}{R_{3}}=\frac{V_{-}-V_{O}}{R_{4}} \tag{7}\]  
By defining \(R_{2}=2\cdot R_{1}\) and \(R_{4}=2\cdot R_{2}\), the output voltage assumes the following value:  
\[V_{O}=2\cdot(V_{\text{{OUTPUT}}}-V_{\text{{OUTPUT}}}) \tag{8}\]  
Figure 15.0 Schematic design of the FPGA/LED driver connection. We selected \(R_{2}=1\) k\(\Omega\) and \(R_{4}=1\) k\(\Omega\). The output is connected to the input of the LED driver circuit for signal modulation. The components selected for the connection between the FPGA/LED driver are listed in Figure 15.1 The datasheets of the MAX5184 DAC, the MAX4105 amplifier, and the TXO crystal oscillator can be found in [34; 35; 36], respectively. Interface Module for PD Driver/FPGA Connection  
For the PD driver/FPGA interface, an analog-to-digital converter (ADC) is needed to transform the analog signal from the receiver into a 10-bit digital signal. The MAX148 ADC [38] was chosen for its 10-bit resolution and ability to operate with clock signals of up to 80 MHz. This ADC was manufactured by Analog Devices and bought on [[https://mouser.com/](https://mouser.com/)]([https://mouser.com/](https://mouser.com/)) (accessed on 5 September 2024). Though this design employs a 40 MHz clock signal, also used by the MAX5184 DAC [34]. The implemented design, which includes the MAX4105 high-speed amplifier [35], is depicted in Figure 15.2  
We chose the internal reference mode [38] for the operation of the MAX1448 ADC. In this mode, the highest reference (\(REF_{P}\)), lowest reference (\(REF_{N}\)), and common-mode voltage range (\(COM\)) terminals operate as outputs, with the following values:  
Figure 15.3  
Figure 15.4  
Figure 15.5  
In this context, \(V_{DD}=3\) V signifies the digital supply voltage of the ADC, and \(V_{REFIN}=2\) V represents the internal scale value for the chosen operating mode. As a result, the MAX1448 ADC [38] is configured to convert analog amplitude signals ranging between \(-1\) V and \(1\) V.  
Figure 15.6 Schematic design of the PD driver/FPGA connection. \begin{table}
\begin{tabular}{c c c c c c} \hline R\({}_{1}\) & 402 \(\Omega\) & R\({}_{2}\) & 1 k\(\Omega\) & DAC & MAX5184 \\ R\({}_{3}\) & 402 \(\Omega\) & R\({}_{4}\) & 1 k\(\Omega\) & Amplifier & MAX4105 \\  & & & Oscillator & TXO crystal 40 MHz \\ \hline \end{tabular}
\end{table} 
Table 3: Components of the FPGA/LED driver connection. Pertaining to the circuit implementation shown in Figure 18, the first stage entails a conditioning phase employing a non-inverting amplifier.