# Generating Airborne Ultrasonic Amplitude Patterns Using an Open Hardware Phased Array
## 3 Hardware Design  
SonicSurface is a phased array consisting of 256 transducers emitting at 40 kHz. The transducers are arranged in a 16 \(\times\) 16 grid and built on a single integrated printed circuit board (PCB). On one side of the PCB, ultrasonic emitters are soldered, whereas, on the other side, the field-programmable gate array (FPGA) (EP4 CE6E22C8N--ALTERA IV Core Board, Waveshare), shift registers (74 HC595, TI), drivers (MIC4127 from MT), and decoupling capacitors (ceramic 50V 0.1 \(\upmu\)F) are mounted. The signals for each emitter are generated by the FPGA. The shift registers demultiplex each digital line coming from the FPGA into eight channels, and the drivers boost the voltage of the channels from logic voltage to the supplied power voltage (up to 20 peak-to-peak voltage (Vp-p)). A block diagram can be seen in Figure 1.  
The calculation of the phases and amplitudes to be emitted is performed on an external computer and then sent to the FPGA via Serial Universal asynchronous receiver-transmitter (UART) protocol at 203,400 bauds. A double buffer has been implemented in the FPGA to generate the signals uninterruptedly [48]; one of the buffers stores emission patterns coming from the computer, whereas the second buffer is the one that is used by the FPGA to continuously generate the emission signals, a command from the computer swaps the buffers at once. This method avoids latency and waiting issues. Different versions of the firmware are available for the FPGA to support phase and amplitude control, or amplitude modulation of the 40 kHz main signal. The protocol used to communicate with the FPGA is presented in Table 1; 1 byte specifies commands or emission patterns. If the byte value is larger than 127, it is a command; otherwise, it represents an emission phase offset or amplitude, depending on the mode. By default, the FPGA has a resolution of 32 divisions per period, so numbers from 0 to 31 represent phases from 0 to 2\(\pi\), 32 represents no emission. Receiving a value of 254 indicates that new phases are going to be sent, the read pointer of the buffer is set to channel 0; afterwards, each phase sent will be assigned into the current read pointer and the pointer increased by one. The command 253 indicates swapping of the buffers. Other commands are: 252, to toggle amplitude modulation at 200 Hz for haptic feedback applications; 252 indicates that instead of phases, amplitudes are going to be sent. From 192 to 196, indicates the board number to activate (being 192 board number 1), in the case that multiple boards were chained together. The FPGA can generate 256 square-wave signals at 40 kHz. Each of the signals supports a phase delay control of 32 divisions per period or \(\pi/16\) radians, the amplitude can be modulated with up to 16 divisions. A multiplexing scheme strategy was employed for reducing the number of needed output pins and, thus, reduce the price of the FPGA. Packs of eight channels are multiplexed into one digital line. Later, this line is demultiplexed back into eight channels while using the shift registers. Figure 2 illustrates the channel multiplexation scheme from the FPGA and circuit implementation. \begin{table}
\begin{tabular}{l l l} \hline \hline
**BYTE** & **Command** & **Action** \\ \hline
0 XXXX XXX & Set phases or amplitudes & Sets the phase or amplitude for the current channel and moves the pointer to the next channel \\
1111 1110 & Start receiving phases & Sets the current channel to the first one and set that values will represent phases \\
1111 1101 & Swap buffer & Swaps the emission and read buffer \\
1111 1100 & Toggle modulation & A modulation of 200 Hz on the amplitude \\
1111 1100 & Amplitude mode & Sets the current channel to the first one and set that values will represent amplitudes \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Communication protocol commands. Figure 1: Schematic of the SonicSurface ultrasonic array.