## 2 Case Study
### Hardware  
The design process of low-end commercial appliances is often characterised by a huge focus on costs saving. Indeed, even the introduction of a single hardware component could turn out to be critical to the design of such devices: e.g., adding a costly component to the hardware needed to build the final appliance may substantially increase its consumer price and hinder its chances of commercial success. In order to reproduce as faithfully as possible the cost-saving process, in the following we adopt a hyper-constrained embedding device as the testing device to run AI techniques. More in details, throughout our experiments we leverage an OpenMV Cam H7 Plus ([[https://openmv.io/products/openmv-cam-h7-plus](https://openmv.io/products/openmv-cam-h7-plus)]([https://openmv.io/products/openmv-cam-h7-plus](https://openmv.io/products/openmv-cam-h7-plus)), accessed on 14 November 2021) microcontroller board. The selected board contains an ARM Cortex M7 processor which runs at low clock speed (480 MHz) to obtain low power consumptions, enabling deployment on edge and battery-powered devices. Moreover, the selected board stores 32 MBs of SDRAM, 1 MB of SRAM, and 2 MB of internal flash, for general purpose storage: such a small amount of memory represents the first obstacle against using the simple embedded device for AI applications. Indeed, most of the available state-of-the-art NNs have footprints greater than the memory availability of such device--see Table 1.  
Running AI techniques does not depend on memory footprint only. Indeed, another limitation for running AI on that sort of board comes from the computational power of the device. In order to measure computational power of devices, and compare it with the NNs computational requirements, the FLOPS and FLOPs metrics are commonly used. FLOPS--FLoating point Operations Per Second--refers to the number of floating point operations that a device is capable to complete in one second. FLOPs--FLoating point OPerations--on the other hand, represents the number of floating points operations required to run a single algorithm--e.g., NN inference. Knowing the number of cores of a device, its clock frequency, and the number of FLOPs per clock cycle that the device is capable to handle, it is possible to compute the theoretical FLOPS performance of a device by means of the following equation:  
\[\text{FLOPS}=\text{cores}\times\text{clock frequency}\times\frac{\text{FLOPs}}{ \text{cycle}} \tag{1}\]  
The ARM Cortex-M7 at our disposal is a single-core microprocessor, which runs at 480 MHz, and capable of one FLOP per cycle. Therefore the board used in our experiments has a theoretical performance of \(0.48\times 10^{9}\) FLOPS. This measure, when compared with the FLOPs requirements of modern NNs, clearly indicates the strong limitations of that sort of devices for AI applications. Indeed, the ARM board is _theoretically_ capable of running a single inference of a MobileNet (Table 1) in \(\text{t}=\frac{\text{FLOPs}}{\text{FLOPs}}=0.583\,\text{s}\). This would allow incoming inputs to be processed at a rate of 1.72 Frames Per Second (FPS), which is not enough for most real-time commercial solutions. Moreover, our preliminary tests--see Section 3.1--performed using standard pre-trained MobileNet do not even come close to those performances, thus increasing concerns on the applicability of AI techniques on that device. Bigger and more powerful NNs would bear even more burden to the board at hand, thus making it impossible to run close to real-time inference.