# Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques
## 4 Design Example: Super Class AB QFG Amplifier in a 130 nm CMOS Process
### Proposed Super Class AB Amplifier  
Figure 8a shows the proposed circuit, which is based on a recycling folded cascode topology [70]. The same adaptive bias circuit used in Figure 6b, formed by the FVFs M\({}_{\rm 1C}\)-M\({}_{\rm 1D}\) and M\({}_{\rm 2C}\)-M\({}_{\rm 2D}\), is employed. In quiescent conditions, M\({}_{\rm 1C}\)-M\({}_{\rm 2C}\) have the same \(V_{GS}\)\({}^{Q}\) as M\({}_{\rm 1A}\), M\({}_{\rm 1B}\), M\({}_{\rm 2A}\) and M\({}_{\rm 2B}\), and, since they have also the same size, neglecting mismatch and channel length modulation, they set a quiescent current \(I_{B}\) in M\({}_{\rm 1A}\), M\({}_{\rm 1B}\), M\({}_{\rm 2A}\), and M\({}_{\rm 2B}\). When a differential signal is applied, the largest (winning) input voltage level shifted by the \(V_{SG}\)\({}^{Q}\) of M\({}_{\rm 1C}\)-M\({}_{\rm 2C}\) appears at the common source of M\({}_{\rm 1A}\), M\({}_{\rm 1B}\), M\({}_{\rm 2A}\) and M\({}_{\rm 2B}\). Hence, currents in these transistors are not limited by \(I_{B}\), due to the large currents that can be provided by the FVFs.  
Figure 8: Proposed super class AB QFG amplifier. (**a**) Circuit diagram. (**b**) Microphotograph (layout image also included, due to the opaque die passivation layer).  
The differential current amplifier employed to transfer and scale the currents in \(\mathrm{M_{1B}}\) and \(\mathrm{M_{2B}}\) to the output is a nonlinear cascode current mirror formed by \(\mathrm{M_{3A}}\), \(\mathrm{M_{3B}}\), \(\mathrm{M_{4A}}\), \(\mathrm{M_{4B}}\), \(\mathrm{M_{3C}}\), \(\mathrm{M_{4C}}\), \(\mathrm{M_{5}}\) and \(\mathrm{M_{6}}\). It employs local common-mode feedback [69] by transistors \(\mathrm{M_{R1}}-\mathrm{M_{2B}}\) acting as tunable active resistors. When a large differential current appears in \(\mathrm{M_{1B}}-\mathrm{M_{2B}}\), a large voltage drop appears in \(\mathrm{M_{R1}}-\mathrm{M_{R2}}\), which creates a large current in either \(\mathrm{M_{3A}}\) or \(\mathrm{M_{4A}}\), which reaches the output. Hence, this nonlinear current mirror provides an additional dynamic current boosting.  
Current starving is implemented in Figure 8a by two DC current sources that subtract part of the DC input current to the NMOS current mirrors. For a fixed current mirror gain \(K\), current starving allows for decreasing the quiescent current of the current mirror output, thus increasing the amplifier output resistance and DC gain [71]. However, here, current starving is used to increase \(K\) without increasing static power. The starving factor used is 0.5, so half of the bias current (\(I_{B}/2\)) is subtracted. As a result, \(K\) can be doubled in Figure 8a for the same quiescent current consumption.  
Adaptive biasing of cascode transistors \(\mathrm{M_{5}}\), \(\mathrm{M_{6}}\), \(\mathrm{M_{7}}\) and \(\mathrm{M_{8}}\) is provided using the QFG technique of Figure 4d to avoid \(\mathrm{M_{3A}}\), \(\mathrm{M_{4A}}\), \(\mathrm{M_{9}}\) and \(\mathrm{M_{10}}\) entering triode region for large dynamic currents (which would strongly degrade SR). The simple pseudo-resistor of Figure 2a is enough, in this case.