## 7 Measurement Results  
Figure 13 shows the chip micrograph of the proposed 6-bit DSA implemented by a 0.25 \(\upmu\) GaAs process, with a core area of 0.51 mm\({}^{2}\). The chip integrates a positive voltage controller and realizes compatibility with conventional CMOS TTL control voltage.  
Figure 11: Comparison of insertion loss between the \(\pi\)-type attenuator before and after using low-pass inductive compensation structure.  
Figure 12: Schematic of the 6-bit DSA.  
To evaluate the performance of the DSA, the root mean square (RMS) amplitude/phase error is defined as follows:  
\[RMS\_Amplitude\_Error=\sqrt{\frac{1}{2^{n}-1}\sum_{i=1}^{i=2^{n}-1}(RA_{i\_ measured}-RA_{i\_ideal})^{2}} \tag{22}\]  
\[RMS\_Phase\_Error=\sqrt{\frac{1}{2^{n}-1}\sum_{i=1}^{i=2^{n}-1}(\phi_{i\_ measured}-\phi_{ref})^{2}} \tag{23}\]  
where \(RAi\_measured\) and \(RAi\_ideal\) are the relative attenuation values measured at state i and the ideal relative attenuation value of state \(i\), respectively. Similarly, \(\phi i\_measured\) and \(\phi ref\) are the additional phase shift measured at state i and the reference state, respectively.  
The electrical properties of the chip were measured on-chip using a Cascade probe station, an ACP-GSGI50 microwave probe, an Agilent 5227B vector network analyzer, a digital multi-channel power supply, and a DC bias power supply. The DC bias voltage applied to the chip, along with the truth table for the digitally controlled power supply, is detailed in Table 1, where 0 represents 0 V, and 1 represents 5 V. This configuration enables the chip to attain 64 states by changing the control voltages.  
Figure 14 shows the results for this chip. Figure 14a shows the measured relative attenuation of all 64 states, with no overlap. Figure 14b shows the measured insertion loss of \(-\)2.54 dB. This remarkably low insertion loss can be primarily ascribed to ILRTs. Figure 14c shows the measured RMS amplitude and phase errors, which are within 0.18 dB and 7\({}^{\circ}\), respectively, exhibiting the lowest amplitude error with small phase error between in 2 to 22 GHz in the GaAs process. As expected, the phase error increases when the frequency is increased. However, the additional phase shift is greatly reduced due to the use of series inductive compensation structures. Figure 14d,e show the measured return loss, and the return loss of all 64 states is better than \(-\)17 dB, indicating excellent matching performance. Figure 14f shows the measured power capacity at the reference state with the input 1 dB compression point (IP1 dB) of 29 dBm at IF 12 GHz, indicating that the DSA has a  
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Bias Voltage/V**} & \multicolumn{6}{c}{**Digitally Controlled Voltage**} & \multirow{2}{*}{**Status**} \\ \cline{2-2} \cline{4-7}  & **Vc1** & & **Vc2** & **Vc3** & **Vc4** & **Vc5** & **Vc6** \\ \hline \(-\)5 & 0 & 0 & 0 & 0 & 0 & 0 & 0 dB \\ \(-\)5 & 0 & 0 & 0 & 0 & 0 & 1 & 0.5 dB \\ \(-\)5 & 0 & 0 & 0 & 0 & 1 & 0 & 1 dB \\ \(-\)5 & 0 & 0 & 0 & 1 & 0 & 0 & 2 dB \\ \(-\)5 & 0 & 0 & 1 & 0 & 0 & 0 & 4 dB \\ \(-\)5 & 0 & 1 sufficiently high-power performance to notbe a limiting factor in the linearity of the phased array system.  
Table 2 presents the comparison of the designed DSA with the published attenuators with state-of-the-art performance. The results show that the proposed DSA shows the best performance in terms of insertion loss, RMS amplitude error, return loss, linearity, and FOM.