## 5 Column Streaming-Based Convolution Engine Architecture
### Reconfiguration Adder Module  
The adder module should be able to handle multiplication products generated by different PE groups, whose result requires adding up according to the algorithm. As shown in Section 4.3, different mapping varieties make each group of multiplications happen at the different PEs groups (e.g., Figure 7's PEs in the red rectangles), which generates a partial sum. If the products of a group of PEs are added together, we call this group a partial sum group. The examples can be observed in Figures 7-10, and their partial sum group can be grouped vertically or horizontally. To identify partial sum groups, we defined a notation system (5)-(8) to represent how the partial sum was obtained from different PEs. If the partial sum means to generate vertically, the partial sum group can be defined as \(\text{Psum}\{\text{PE}(\text{C}\text{l}\text{x},\text{R}\text{w}\text{y} \text{ }\text{  
The other partial sum group cases are the multiplication input data mapped to nonadjacent PEs. As shown in Figure 8, Psum{PE(Col0,Col8-9), PE(Col9, Row2)} are generated by the PEs(Col0, Row8-Row10), containing the output data {8\(\cdot w_{00}\),9\(\cdot w_{01}\),10\(\cdot w_{02}\)}, and the PE(Col9, Row2), containing data {11\(\cdot w_{02}\)}. To easily present the partial sum groups composed of nonadjacent PEs, the same color of rectangles is used, such as in Figure 8, to indicate the same partial group. For implementing the different summation demands, the adder module is designed to have the ability to add up the multiplication products vertically and horizontally. The adder module comprises two submodules: a column and a row adder submodule. The column adder submodule is shown in Figure 17, which is used to handle the vertical products adding up cases according to different filter sizes \(k\), Psum{PE(Col\(\cdot\), Rowy \(\sim\) Row(\(y+k-1\))}. There are 11 columns of adders in the column adder submodule. Each column in the column adder submodule consists of three seven-input adders and a set of programmable components, such as demuxes and muxes, responsible for remapping the result from the PE array. Each sub-column adder module generates the partial sum and sends the result to the accumulator module. On the other hand, partial sums from the PEs are required to be added horizontally. However, the horizontally adjacent PEs stream the input data in the different clock cycles. There is a cycle delay in some cases, such as between PE(Col4, Row7) and PE(Col5, Row7). As a result, the column adder module requires delay buffers to adjust the addition operation timing. The delay chain design in the row adder module can be observed in Figures 18 and 19. There is a total of five adder rows in the row adder submodule. When \(k=3\), the seventh row of the adder (row R7) shown in Figure 18 is utilized. When \(k=4\), the sixth and seventh rows of the adder (rows R6 and R7) shown in Figure 19 are utilized. The other name of adder row R7 is R9_left, which indicates that when \(k=3\) and \(4\), in the PE array's point of view, R7 is their row 9 and uses the left inputs AR9C_i_ in Figures 7, 17 and 19. In the same way, the other name of adder row R6 is R8_left, which means it is also utilized by PE array row 8 in the \(k=4\) case. In Figure 7, the four partial sum groups, Psum{PE(Col0\(\cdot\)3, Row8)},  
Figure 17: Programmable column adder submodule. Psum[PE(Col0-3, Row9)], Psum[PE(Col4-7, Row8)], and Psum[PE(Col4-7, Row8)], are required to be added up horizontally. Hence, in this case, R8_left and R9_left are used. Row adders R8-10 are shown in Figure 20, which are utilized by the cases of \(k=6\)\(\sim\)\(10\). Figure 20 is a condensed version of all three adder rows R8\(\sim\)\(10\), which uses the dash line rectangles to represent the three different adder rows' structure, \(r=8\)\(\sim\)\(10\). The input amount of the output mux in the figure is a variable according to how many wires are circled by the individual dash line rectangle. For example, there is a five-to-one mux utilized when \(r=9\).