# Model Predictive Control Algorithm for Converter Based on a Convolutional Neural Network
## 4 Simulation Experiment and Analysis
### System Closed-Loop Control  
This article establishes a 2L-VSI simulation model based on MATLAB/Simulink 2022a (as shown in Figure 2). Parameters of inverter: DC voltage \(v_{dc}=520\) V; filter inductor \(L=2.4\) mH; equivalent resistance \(r_{f}=0.05\) \(\Omega\); filter capacitor \(C=40\) \(\upmu\)F; simulation step \(T_{s}=40\) \(\upmu\)s; and output voltage reference voltage \(v_{ref}\) is the three-phase AC voltage with a frequency of 50 Hz and amplitude of 200 V. Parameters of load: HPFRIL with active power \(P=8500\) W and reactive power \(Q=5300\) var; LPFRIL with active power \(P=6000\) W and reactive power \(Q=8000\) var; NLL with \(R_{L}=47\) \(\Omega\) and \(C_{L}=470\) \(\upmu\)F. The simulation hardware environment is an Intel i7-11800H processor with 32 GB RAM. To evaluate the control performance of different neural network controllers, the neural network controllers of the Compensated FCSMPC and Optimal FCSMPC algorithms are implemented for closed-loop control of the 2L-VSI and compared with the control performance of the Classical FCSMPC algorithm [38]. Figures 10(a), 10(b), and 10(c), respectively, illustrate the phase-A output voltage waveform quality comparisons between the NNC (Compensated FCSMPC) control strategy and the Classical FCSMPC control strategy under three load conditions: HPFRIL, LPFRIL, and NLL. In Figure 10(a), under HPFRIL conditions, the output voltage controlled by the Classical FCSMPC algorithm has a total harmonic distortion (THD) value of 3.57% and the output voltage controlled by the NNC (HPFRIL--Compensated FCSMPC) has a THD value of 1.95%, which represents an improvement of 45.38% in the THD value. In Figure 10(b), under LPFRIL conditions, the output voltage controlled by the Classical FCSMPC algorithm has a THD value of 3.65% and the output voltage controlled by the NNC (LPFRIL--Compensated FCSMPC) has a THD value of 1.99% for a 45.48% improvement in the THD value. Under NLL conditions, Figure 10(c) demonstrates the output voltage controlled by the Classical FCSMPC algorithm with a THD value of 5.84% and the output voltage controlled by NNC (NLL--Compensated FCSMPC), with a THD value of 4.41% and an improvement of 24.49% in the THD value. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Model** & **Acc** & **Pre** & **Rec** & **F1** & \
\begin{tabular}{c} **Training** \\ **Time** \\ \end{tabular} &
\begin{tabular}{c} **Computation** \\ **Time** \\ \end{tabular} \\ \hline BP & 83.78\% & 83.33\% & 83.83\% & 83.20\% & 2 min 27 s & 1.492 ms \\ LSTM & 91.93\% & 92.48\% & 91.92\% & 91.81\% & 11 min 42 s & 6.996 ms \\ CNN & 96.42\% & 96.49\% & 96.44\% & 96.44\% & 3 min 43 s & 3.130 ms \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Comparison of experimental results of different models. Figure 10: Performance curves of different models during the training process. (**a**) The accuracy variation curves. (**b**) The loss function variation curves. Figures 12a, 12b, and 12c, respectively, present the phase-A output voltage waveform quality comparisons between the NNC (Optimal FCSMPC) control strategy and the Classical FCSMPC control strategy under three load conditions: HPFRIL, LPFRIL, and NLL. In Figure 12a, under HPFRIL conditions, the NNC (HPFRIL--Optimal FCSMPC) achieves a THD value of 1.66%, representing a 53.50% improvement. In Figure 12b, under LPFRIL conditions, the NNC (LPFRIL--Optimal FCSMPC) achieves a THD value of 1.57%, corresponding to a 56.99% improvement. In Figure 12c, under NLL conditions, the NNC (NLL--Optimal FCSMPC) attains a THD value of 3.95%, achieving a 32.36% improvement. To further validate the effectiveness of the neural network control system for converters based on CNN load-type identification as shown in Figure 4, closed-loop control experiments are conducted under conditions of varying load types of 2L-VSI. The tracking control error of the inverter output voltage, defined by Equation (2), serves as the trigger signal for control model switching and load-type identification.