# Broadband Millimeter-Wave Front-End Module Design Considerations in FD-SOI CMOS vs. GaN HEMTs
## 4 Discussion  
Equations (1) and (2) from [45] support the results attained from simulating the uniform \(N\)-element square antenna arrays generated in Cadence AWR, where the antenna array gain increases in proportion to \(N\) whereas the HPBW (\(\theta_{B}\)) reduces at half the rate of the increase in \(N\). \[Array\ Gain=10\cdot log_{10}\bigg{(}\frac{4\pi\cdot A_{e}}{\lambda^{2}}\bigg{)},\ \ \ \ \ \ A_{e}=e_{max}\cdot N\cdot\text{A}_{antenna} \tag{1}\]  
\[\theta_{B}=10\cdot log_{10}\bigg{(}\frac{0.886\lambda}{\sqrt{Nd}}\bigg{)},\ \ \ \ \ \ \text{d}=\lambda/2 \tag{2}\]  
The PAs will produce an average \(P_{OUT}\) per element (\(P_{OUT,AVE}\)/_element_) determined by the technology and devices used (i.e., Si CMOS vs. GaN HEMT) in a system where we are using one antenna element per FEM (e.g., Figure 1), so the number of elements or channels for a particular phased array system needs to be determined based on the PA's \(P_{OUT,AVE}\)/_element_ to reach the targeted Tx EIRP. The value of \(P_{OUT,AVE}\)/_element_ is calculated based on the number of antenna elements, \(N\), and since the antenna array gain and the number of FEMs will both double with \(N\), the necessary \(P_{OUT,AVE}\)/_element_ will be reduced by \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Ref.** & **Tech.** & **Tx BW** & **Tx Gain** & **Tx \(P_{OUT,SAT}\)** & **Tx \(OP_{4 IB}\)** & **Core Size** \\ \hline
[24], 2020 &
\begin{tabular}{c} 22 nm CMOS \\ FD-SOI \\ \end{tabular} & 25.5–29.3 & 30 & 17.2 & 16.0 & 0.2 \\ \hline
[25], 2020 &
\begin{tabular}{c} 45 nm CMOS SOI \\ \end{tabular} & 22.7–30.8 & 17.6 & \textgreater{}18.8 & 11.8–18.4 & 2.1 \\ \hline
[26], 2021 &
\begin{tabular}{c} 0.13 \(\upmu\)m SiGe \\ BiCMOS \\ \end{tabular} & 21–44 & 15.2–17.8 & 18.1–19 & 13–17 & 0.9 \\ \hline
[27], 2021 &
\begin{tabular}{c} 0.13 \(\upmu\)m SiGe \\ BiCMOS \\ \end{tabular} & 24–30 & 26 & \textgreater{}17.8 & \textgreater{}15.9 & 1.78 \\ \hline
[28], 2023 &
\begin{tabular}{c} 65 nm CMOS \\ \end{tabular} & 28–44 & 9.2 & 15–16 & 9–12 * & 0.19 \\ \hline
[29], 2023 &
\begin{tabular}{c} 65 nm CMOS \\ \end{tabular} & 25.4–29.6 & 26 & 15.1 & 13.5 & 0.06 \\ \hline
[30], 2020 &
\begin{tabular}{c} 65 nm CMOS \\ \end{tabular} & 24.9–30 & 21 & 15.3 & 13.3 & 0.22 \\ \hline
[31], 2021 &
\begin{tabular}{c} 90 nm CMOS \\ \end{tabular} & 30–39.2 & 18.3 & 15.1 & 13.3 & 0.21 \\ \hline
**Our Si PA +** &
\begin{tabular}{c} 22 nm CMOS \\ FD-SOI \\ \end{tabular} & 24–39 & 11.5–14.9 & 12.3–14 & 9.5–10.5 & - \\ \hline
[32], 2022 &
\begin{tabular}{c} 60/100 nm \\ GaN/Si \\ \end{tabular} & 32–36 & 25 & 35 & \textgreater{}32 * & 14 \\ \hline
[33], 2017 &
\begin{tabular}{c} 100 nm GaN/Si \\ \end{tabular} & 28–34 & 18 & 35.5 & - & 11 \\ \hline
[34], 2021 &
\begin{tabular}{c} 150 nm GaN/SiC \\ \end{tabular} & 33–37 & 14 & 29.7 & - & - \\ \hline
[35], 2020 &
\begin{tabular}{c} 150 nm GaN/SiC \\ \end{tabular} & 26–30 & 27 & 31 & \textgreater{}25 * & 20 (packaged) \\ \hline
[36], 2021 &
\begin{tabular}{c} 150 nm GaN/SiC \\ \end{tabular} & 37–40.5 & 23 & 33 & 30 * & 18 (packaged) \\ \hline
**Our Medium-Power** & \multirow{2}{*}{40 nm GaN/SiC} & \multirow{2}{*}{21–31} & \multirow{2}{*}{17.4–19.3} & \multirow{2}{*}{21.7–23.1} & \multirow{2}{*}{16.4–18.3} & \multirow{2}{*}{-} \\
**GaN PA +** & & & & & \\
**1.5 dB Switch Loss** & & & & & \\ \hline
**PEX EM Sim. Only** & \multirow{2}{*}{40 nm GaN/SiC} & \multirow{2}{*}{24–39} & \multirow{2}{*}{18.1–20} & \multirow{2}{*}{27.5–29.6} & \multirow{2}{*}{18.8–24.5} & \multirow{2}{*}{-} \\
**Our Watt-level** & & & & & & \\
**GaN PA +** & & & & & \\
**1.5 dB Switch Loss** & & & & & \\ \hline \hline \end{tabular}  
* estimated from figures.  
\end{table} 
Table 2: The literature comparison of broadband Tx Si and GaN FEMs in the 5G FR2-band. one-fourth with each doubling of \(N\), as indicated by Equation (3), which is then manipulated to show the average \(P_{OUT}\) required for \(N\) PAs (\(P_{OUT,AVE}\)/_total_) in Equation (4).