## 4 Results and Discussion  
In Figure 10, an example of measurement carried out with the 40 GSa/s Tektronix DPO7254 oscilloscope in the case of the FPGA platform is reported. Figure 10: _Cont._  
Figure 9: Flowcharts used for the C language implementation of the Forney (**a**) and Lu (**b**) methods. GPIO, general-purpose input/output. In Table 4, the performance of the Forney and Lu methods when implemented on an FPGA platform are compared. Data about cell LUTs' (look-up tables') usage refer only to the block performing Forney or Lu algorithm (excluding logic used to compute the output delay, shown in Figure 8). To better appreciate the results, the same are also represented in Figure 11.  
As can be seen, as theorized by the model presented in the literature, [PERSON]'s method performs better in terms of resources usage in respect of [PERSON]'s one. The difference between the two algorithms increases with the system complexity (i.e., increasing the \(m\) and \(t\) parameters), and it is clearly appreciable for the RS(255,223) configuration. Nevertheless, from the output delay point of view, [PERSON]'s algorithm definitely performs better: this behavior is justified by the fact that [PERSON]'s algorithm computes the result in a strong, recursive way (as can be seen, for example, in the error magnitude extraction phase). This leads to deep architectures in which the last output is strongly dependent on the previous one, negatively affecting the overall latency. From this point of view, [PERSON]'s algorithm is more efficient thanks to its parallel-prone structure, as can be seen in the RTL resulting scheme (Figure 6). Therefore, if the target application is to be implemented on an FPGA platform, [PERSON]'s should be preferred, unless the available resources in terms of area are not binding. In Table 5, the performance of the two algorithms when the implementation platform is an MCU is reported. The measurement technique can be better visualized in Figure 12, where the outputs from the Tektronix MSO 2024 oscilloscope in the case of configuration RS (255,223) are reported. The output delays obtained in the case of MCU implementation are not intended for a direct comparison with ones measured in the case of FPGA implementation. The FPGA solution outperforms the MCU one: the \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**System Configuration**} & \multicolumn{2}{c}{**Forney**} & \multicolumn{2}{c}{**Lu**} \\ \cline{2-5}  & **Cell LUTs** & **Time (ns)** & **Cell LUTs** & **Time (ns)** \\ \hline A & 56 & 6.7 & 62 & 8.3 \\ B & 163 & 10.2 & 138 & 15.2 \\ C & 263 & 11.7 & 268 & 22.5 \\ D & 828 & 20.8 & 760 & 32.8 \\ E & 7126 & 47 & 6081 & 71 \\ F & 27,100 & 72.2 & 21,082 & 136.4 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Field programmable gate array (FPGA) implementations results. LUTs, look-up tables. Figure 10: Oscilloscope measurements of the GPIO pin for the configuration F of Table 3 in the case of FPGA implementation. (**a**) Measurement of the execution time of the [PERSON] algorithm. (**b**) Measurement of the execution time of the Lu method. comparison must be made between the two methods, considering the same implementation platform and the same system configuration. As can be seen in MCU implementation, the improvements made by the method proposed by [PERSON] et al. are fully evident. In this case, as opposed to the FPGA implementation, all the operations are computed sequentially, and [PERSON]'s method can take full advantage of the minor number of operations required to produce the result. Also, in this case, the advantage grows with the system complexity: in  
Figure 11: Graphical representation of the results of Table 4. (**a**) FPGA implementations resources’ usage in terms of cell look-up tables (LUTs), (**b**) FPGA implementations’ output delay. Figure 12: Oscilloscope measurements of the GPIO pin for the configuration F of Table 3 in the case of MCU implementation.