## 2 FFT Design Considerations  
### Related Works for MIMO-OFDM FFT  
Various hardware architectures have been developed to perform the FFT algorithm. Among these architectures, the memory-based [8] and pipelined [9] architecture are the two primary categories. The memory-based FFT configuration is structured based on the employment of one or several processing elements (PEs) in cooperation with the memory modules. This memory-based structure is suitable for flexible FFT operations, which provide various FFT streams or operation points (i.e., FFT length) [10, 11, 12]. However, this approach is not appropriate for high-throughput or low-latency FFT operations when the operability of PEs or memory bandwidths is limited [13, 14, 15]. By using flexible FFT computation (length or streams), numerous memory-based FFT designs have been presented for MIMO-OFDM applications [15, 16, 17]. However, most of these approaches employ low-radix PEs (i.e., radix-\(r\), where \(r\) is \(\leq\) 16), which limits throughput performance. The pipelined FFT architecture is applied to increase operation throughput and latency by using hardware resources [9]. Moreover,  
Figure 2: Block diagram for the conventional \(M\times M\) MIMO-OFDM transmission model.  
two conventional pipelined FFT categories are multipath delay communicator (MDC) [9; 18] and single-path delay-feedback (SDF) architectures [9; 19].  
The MDC structure has the features of multipath (i.e., parallel) feedforward operations performed using switch control with first in first out (FIFO) memory. By effectively using the parallel data paths and operation units, the multipath processing feature of MDC can be applied to the FFT computation of multiple streams [20]. Therefore, several FFT designs based on MDC structures have been presented for MIMO-OFDM applications [20; 21; 22; 23]. Figure 3 shows the block diagram for the conventional \(M\)-path MDC architecture applied to MIMO-OFDM FFT of \(M\) streams, where the feedforward multipath data is processed using switch blocks, FIFOs, butterfly units and multipliers. The SDF architecture provides a feedback path for FIFOs to efficiently manage the butterfly operation data at each pipeline stage [9]. To enable parallel processing for SDF configurations, the extended multipath delay-feedback (MDF) architecture [24; 25] was proposed. Because the MDF scheme can process multiple input streams, MDF architectures have been researched for required multistream FFT operations in MIMO-OFDM systems [7; 25; 26; 27; 28; 29]. On the basis of the MDF structure using the radix-\(2^{k}\) algorithm (where \(k\) is a positive integer) [30], an \(N\)-point FFT unit has \(\log_{2}(N)\) radix-2 operation stages involving the feedback-pathed FIFO and butterfly 2 (BF2) units [9; 30]. Figure 4 shows a conventional \(M\)-path MDF FFT structure for \(M\times M\) MIMO-OFDM applications. Furthermore, some previous studies [21; 25; 28] discuss the schemes of hardware cost reduction for multipliers located at multiple paths (Figures 3 and 4). In general, these MDC or MDF approaches [20; 21; 22; 23; 24; 25; 26; 27; 28; 29] enable multipath/parallel operations associated with multiple FFT streams (i.e., the number of data paths and FFT streams is equal).