## 1 Introduction  
Multipliers are essential components in multimedia applications, digital signal processing, neural networks, image processing, and machine learning. They serve as fundamental components for tasks such as filtering, correlation, de-noising, and domain transformation [1, 2, 3, 4, 5, 6, 7]. However, they also require a quick response when using minimal area and power. These applications require revolutionary changes in the design process of very-large-scale integration (VLSI)-integrated circuits. Therefore, the development of high-performance computational hardware such as multipliers is a major concern [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13]. The design criteria for multipliers primarily focus on four aspects in order to form an efficient multiplier: speed, power consumption, area, and accuracy. The state of the art on VLSI designs focuses mainly on the reduction in the area; however, in the last decade, the priority has changed mainly to speed and power consumption. However, the high-speed requirement causes an increase in circuit complexity, demanding a greater number of transistors in the circuit and more power consumption [10, 11, 12, 13]. A similar approach was applied to field-programmable gate arrays (FPGAs), which have embedded hardware multipliers. Multiplication can also be performed using logic cells, which are occasionally preferred. This is because the number of hardware multipliers in an FPGA is limited, and their location and digit capacity are fixed [13]. [PERSON] et al. presented a performance comparison for several types of multipliers [14]. Multipliers of 4-, 8-, 16-, and 32-bit word lengths were implemented in the Verilog hardware description language and synthesized using Leonardo Spectrum(r) software for a 350 nm complementary metal-oxide-semiconductor (CMOS) technology. The VLSI design of 32-bit variants indicated that the Wallace tree scheme would be the most suitable for speed-critical applications where the area is not a priority. [PERSON] and [PERSON] presented a performance comparison of various 32-bit multiplier designs of array, Wallace, Dadda, reduced area, and radix-4 Booth multipliers with different optimization synthesis modes in the Leonardo Spectrum(r)[15]. These multiplier designs were modeled in Verilog, simulated, and synthesized using 350 nm CMOS technology. They concluded that the radix-4 Booth multiplier had the best results in terms of area performance in the three optimization modes. When delay optimization was used, the array multiplier had the longest delay, whereas the fastest speed performance was produced by the Wallace multiplier. [PERSON] et al. evaluated and compared the accuracy and circuit characteristics of the Wallace and array algorithms using 8- and 16-bit approximate multipliers [16]. The approximation was implemented by replacing accurate full adders (FAs) with approximate FAs. Cadence(r) tools were used in the VLSI design for the 65 nm CMOS technology. In terms of architecture, they found that Wallace multiplier designs tend to have lower power consumption and a smaller area than array multipliers. [PERSON] et al. presented an analysis and comparison of different types of multipliers such as Wallace, array, and Baugh Wooley [5]. The designs were implemented in the hardware description language, and the power, area, and speed were simulated using Modelsim and Xilinx(r) ISE 8.1. The principal conclusion is that the speed and power consumption of the Baugh Wooley multiplier are the lowest among the three multipliers. [PERSON] et al. presented an approach for implementing 8-bit array, Wallace, and Vedic multipliers using modified gate diffusion input (GDI) technology [17]. In a comparative analysis of the area, power, and delay, it was found that multipliers built based on GDI logic occupied less area, dissipated less power, and experienced less delay than multipliers based on CMOS logic. [PERSON] et al. improved the design of the array and Wallace multipliers using an efficient adder circuit [18].