## 2 System Architecture and Design Principles
### RS Coding Design Based on FPGA  
Afterwards, the packet data after data preprocessing is channel-coded to enhance the robustness of the system and to reduce the BER. In this study, an improved RS (255,239) coding module implemented on an FPGA platform is proposed. The module utilizes redundant information generated during the coding process for error correction. During the encoding process, a set of data to be encoded is considered as the coefficients of an information polynomial. The information polynomial is expressed as  
\[u(x)=u_{238}x^{238}+u_{237}x^{237}+\cdots+u_{1}x+u_{0}, \tag{1}\]  
where \(u_{0}\) to \(u_{238}\) are the information to be encoded. The RS (255,239) encoding in this design is defined over the Galois field \(GF\big{(}2^{8}\big{)}\), with the generator polynomial selected as  
\[g(x)=\prod\
olimits_{i=1}^{i=16}{(x+\alpha^{i})}, \tag{2}\]  
The polynomial is expanded in the Galois field to obtain the generator polynomial coefficients \(g_{0}\) to \(g_{16}\); the systematic encoding is completed through the calculation as  
\[r(x)=(u(x)x^{16})\text{mod}_{g(x)}, \tag{3}\]  
The encoding circuit is illustrated in Figure 3 [46]. The information to be encoded is sequentially input into the circuit. At the start of encoding, \"_Switch1_\" is connected to the \"_ur_\" terminal, which is responsible for inputting \(u(x)\) to participate in the subsequent Galois field operations. Meanwhile, \"_Switch2_\" is connected to the \"\(u(x)\)\" terminal, which is responsible for outputting the data to be encoded (\(d_{1}\) to \(d_{239}\)) sequentially. After the information input is completed, the two switches are toggled, and the generated parity check symbols (\(R_{0}\) to \(R_{15}\)) are appended to the last 16 bytes of the data. These parity symbols are then output sequentially along with the original information up to \(d_{255}\), completing the encoding process. Figure 2: Schematic diagram of data grouping and packing. To simplify the hardware implementation complexity, the present design employs a Python 3.8 script for data preprocessing, which implements various operations in the Galois field. Equation (2) is expanded as follows:  
\[ \begin{array}{ll}g(x)=&x^{16}+118x^{15}+52x^{14}+103x^{13}+31x^{12}\\ &+104x^{11}+126x^{10}+187x^{3}+232x^{8}\\ &+17x^{7}+56x^{6}+183x^{5}+49x^{4}\\ &+100x^{3}+81x^{2}+44x+79\end{array} , \tag{4}\]  
where \(g_{0}\) to \(g_{16}\) are the coefficients of the polynomials \(x^{0}\) to \(x^{16}\). During the encoding process, the coefficients of the generator polynomial remain unchanged. This characteristic is exploited to optimize the hardware implementation of Equation (3). Taking \(u_{0}\) as an example, the Galois field multiplication of \(u_{0}\) and the generator polynomial \(g_{0}\) can be generated using script code. The precomputed results can be expressed as  
\[y_{(8 bit)}=g_{0}\otimes u_{0}\left\{ \begin{array}{ll}y[0]&=x_{0}{}^{\wedge}x _{2}{}^{\wedge}x_{5}\\ y[1]&=x_{0}{}^{\wedge}x_{1}{}^{\wedge}x_{3}{}^{\wedge}x_{6}\\ y[2]&=x_{0}{}^{\wedge}x_{1}{}^{\wedge}x_{4}{}^{\wedge}x_{5}{}^{\wedge}x_{7}\\ y[3]&=x_{0}{}^{\wedge}x_{1}{}^{\wedge}x_{6}\\ y[4]&=x_{1}{}^{\wedge}x_{5}{}^{\wedge}x_{7}\\ y[5]&=x_{2}{}^{\wedge}x_{6}\\ y[6]&=x_{0}{}^{\wedge}x_{3}{}^{\wedge}x_{7}\\ y[7]&=x_{1}{}^{\wedge}x_{4}\end{array} ,\right. \tag{5}\]  
where \(u_{0}=\left[x_{7}\ x_{6}\ x_{5}\ x_{4}\ x_{3}\ x_{2}\ x_{1}\ x_{0}\right]\) and \(g_{0}=79=\left(01001111\right)_{2}\). When implementing the hardware circuit, the Galois field multiplication can be converted into XOR operations on the individual bits of \(u_{0}\). This approach works well to reduce the encoding resources and complexity. The RS decoding process is efficiently executed on an FPGA through a finite-state machine design, encompassing key computational steps such as syndrome computation, application of the Berlekamp-Massey (BM) algorithm, execution of the Chien search algorithm, and utilization of the Forney algorithm [47; 48; 49].