## 3 Results  
### Identification of the Circuit Model  
The IC studied in this paper belongs to the 110 nm technology node and is characterized by the parameters reported in Table 1. The emissions of the IC have been studied during a standard bit sequence defined by the IC supplier, representing a digital data transfer through the I/O pins. Specifically, three different conditions have been studied, referring to different choices of the data sequence frequency and rise time, and of the average nominal level (rms) of the currents injected into the pins (Table 2). In this paper, the overall circuit model has been implemented with the circuital simulation tool Qucs [27], see Figures 2 and 3. The time-domain waveforms for \(I_{core}\), and the values of the components in Figure 2 have been provided by the IC supplier, as the outputs of a transistor-level simulation of the IA, whereas the submodel describing the I/O buffer in Figure 2 have been imported by the IBIS library [13]. A quad-flat package has been used, with a total area of about 20 \(\times\) 20 mm. The package parasitic lumped elements have been extracted by a quasi-static field simulator (Comsol Multiphysics [28]). The values of the electrical parameters of the package and of the decays are summarized in Table 3.  
The test board has been realized with a three layer PCB (see Figure 5), with the geometrical and electrical parameters provided in Table 4 (an FR-4 dielectric has been used). The PCB traces are designed to provide controlled impedances of 50 \(\Omega\)\(\pm\) 10% (in the frequency range 1 MHz-1 GHz) and equalized delays, in order to avoid signal integrity issues related to delay mismatching.  
The PCB \(S\)-matrix has been computed by means of the FEM solver integrated into the full-wave commercial simulator CST Microwave Studio [29]. In the following, \(S_{11}\)(\(n\),\(n\)) and \(S_{12}\)(\(n\),\(n\)) represent the reflected and transmitted waves associated to the generic line \(n\), whereas \(S_{11}\)(\(n\),\(m\)) and \(S_{12}\)(\(n\),\(m\)) represent the coupling coefficients between lines \(n\) and \(m\) at ports 1 and 2 and, hence, they may be taken as a measure of the near-end and the far-end crosstalk noise, respectively. Figure 7a shows, as an example, the computed parameter \(S_{12}\)(13,13) (transmission along the trace #13), whereas Figure 7b shows the transmission from line #13 to two adjacent ones, \(S_{12}\)(13,14) and \(S_{12}\)(13,15). The behaviors shown in Figure 7 are representative of the results for all PCB traces and, thus, from Figure 7a, it is evident that the board traces are well matched to the reference impedance at least up to 1 GHz, since the transmission is almost perfect (at 1 GHz, \(S_{12}\) is still above \(-\)1 dB). From Figure 7b it results that the crosstalk noise is completely negligible, thanks to already-mentioned design guidelines adopted  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline _Die Area_ & \(V_{dd(core)}\) **(V)** & \(V_{dd(IO)}\) **(V)** & _Clock Frequency_ **(MHz)** & _Rise-Time_ **(ns)** \\ \hline
4.5 mm \(\times\) 3 mm & 3.3 & 2.5 & 60 or 70 & 0.35 or 0.58 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Dimensions and nominal values for the studied IC.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline  & \(C_{d}\) **(nF)** & \(C_{IO}\) **(uF)** & \(R\) **(fD)** & \(L\) **(nH)** \\ \hline Min & 100 & 4.7 & 0.06 & 2.7 \\ Max & 100 & 5.0 & 0.07 & 3.0 \\ \hline \hline \end{tabular}
\end{table}
Table 3: Parameters for the package.  
for the multilayered structure. After computing the \(S\)-parameters, the admittance matrix has been derived from (2) and then synthesized with a low-order approximation as in (3). The matrix entries in (3) have been implemented through the equivalent circuits in Figure 3. As an example, Table 5 shows the extracted values for the equivalent circuit elements for lines #38-40.