# Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication
## 3 Combined Min-Sum Algorithm
\[Throughput=\frac{N\times f_{max}}{I_{max}\times 2\times L+2} \tag{6}\]

In order to confirm the efficiency of our solution, we have conducted our proposed decoder on the expansion size \(Z=56\), code rate \(R=1/3\) using 5G base matrix BG1 LDPC code. The proposed LDPC decoder architecture was modeled by the Verilog hardware description language (HDL) and simulated to verify its functionality using a test pattern generated from a C simulator. After successful verification of the design functions, it was then synthesized using sufficient time and area constraints. Both simulation and synthesis steps were executed by using Synopsys design tools and TSMC 65-nm CMOS standard cell technology. The post-synthesis results are reported in Table 5. The proposed low complexity layered LDPC decoder architecture occupies an area of 1.49 mm\({}^{2}\) and achieves a throughput of 3.04 Gbps at 750 MHz. The power and energy dissipations are 259 mW and 85.20 pJ/bit, respectively. In addition, Table 5 shows the implementation and performance comparisons of the proposed low-complexity high-throughput decoder with various other LDPC decoders. It is confirmed that the proposed design helps reduce the decoder complexity. Since these designs have different implementation parameters, including code length, CMOS technology, and the quantization bits, it is necessary to apply performance normalization for a fair comparison. The normalization method in [35] is adopted. In order to keep the

Figure 11: Pipeline schedule of the proposed QC-LDPC decoder. Figure 10: Decoding performance of the QC-LDPC decoders on the \(N=3808\), \(R=1/3\) for base matrix BG1 of 5G NR. hardware performance comparison on an equal basis with respect to technology, area, and the number of iterations, it is usually evaluated by the throughput-to-area ratio (TAR) metric, which was defined by TAR = Throughput/Area (Gbps/mm\({}^{2}\)). It can be observed that the proposed architecture is found to be the most efficient in terms of area efficiency among the reported decoders, yielding a normalized throughput-to-area ratio (NTAR) value of 2.04 Gbps/mm\({}^{2}\). Specifically, the NTAR of our work is 10.3% better than that of the next most efficient decoder [36] and 38.7% better than the rest of the reported decoders. The decoder in [37], which offers the highest normalized throughput at 7.31 Gbps, occupies a very large-scale design area. Hence, its NTAR is significantly low compared to our proposed design. Specifically, the NTAR ratio of our work is about 46.08% better than that of [37]. High operating frequency usually comes at the cost of increased power consumption. Despite this, though, as shown in Table 5, the proposed enhanced decoder achieves very good results in terms of energy efficiency, very close to that of the work presented in [38]. Moreover, it can be seen that the energy efficiency of our proposed LDPC decoder yields 70.13% better than that of the next most area-efficient decoder in [36]. Based on the implementation results presented above, it is clear that the design method offers a significantly low complexity, high area efficiency, and high throughput, which is sufficient for the 5G NR wireless communication standard. However, it is very challenging to design a low error correction decoder for 5G LDPC codes since the offset factor is relatively difficult to optimize in quantized LDPC decoders. In order to improve the error correction performance as well as achieve cost efficiency and high throughput issues, further enhancements should be proposed in future research for adjusting the offset factor of the OMS decoder in the pure LDPC part. ## 6 Conclusions

Enhanced versions of CNBP architectures are proposed to improve the complexity of the LDPC decoders in this paper. First, an efficient minimum-finder for CNU architecture