## 3 Low-Complexity Decoding Algorithm
### Modified 2-Bit MSA  
In order to implement high-speed hardware for LDPC decoding, it is necessary to quantize the message values. Quantization with fewer bits can save memory and simplify the hardware structure, but it may also lead to a reduction in BER performance [31]. Based on the original MSA, [22] gave a modification only using 2-bit quantization, while retaining a good decoding performance, but greatly simplifies the computation and storage. In this algorithm, intrinsic message is quantized using 2 bits, and is represented by \(B_{s}B_{m}\)[32]. Unlike traditional quantization methods, the 2-bit MSA does not directly represent the true values of the messages, but instead represents the confidence coefficient. \(B_{s}\) represents a hard decision of the received message, while \(B_{m}\) indicates the reliability of the hard decision [33]. When \(B_{m}=0\), it represents a low confidence level but not the value of zeros, while \(B_{m}=1\) indicates a high level of confidence in the hard decision. The values of \(B_{s}\) and \(B_{m}\) can be obtained using Equations (1) and (2), where \(rx\) is the received message and \(Ty\) is a transformation threshold. The value of \(Ty\) is determined as 4/10 through simulations. \[B_{s}=\text{sign}(rx), \tag{1}\]  
\[B_{m}= \begin{cases}1,&\text{if }|rx|>T_{y},\\ 0,&\text{otherwise}\.\end{cases}  \tag{2}\]  
Figure 4: PCM of proposed (8176, 7154) LDPC codes for overlap. ```
Input: rx and PCM Initialization: \(L(q_{n})=-rx\); Decoding: while\(t\leq it_{max}\) and \(Hx^{T}\
eq 0\)do CN Update: for\(i=1:m\)do \(L(r_{mn})=\prod_{n^{\prime}\in N(m)\setminus n}\operatorname{sign}(L(q_{mn^{ \prime}}))\cdot\min_{n^{\prime}\in N(m))n}abs(L(q_{mn^{\prime}}))\);  end forVN Update: for\(j=1:n\)do \(L(q_{mn})=L(q_{n})+\sum_{n^{\prime}\in M(n)\setminus m}L(r_{m^{\prime}n})\); Posterior probability Update: \(L(P[x_{n}\mid y,S])=L(q_{j})+\sum_{m\in M(n)}L(r_{mn})\); Decoding decision: if\(L(P[x_{n}\mid y,S])>0\)then \(x_{n}=0\); else \(x_{n}=1\);  end if \(t=t+1\);  end for Output: Decoded Data \(x\)
```  
**Algorithm 2**Min-Sum Algorithm. After receiving the message \(rx\), the initialization part first transforms \(rx\) from integers into 2-bit messages according to Equation (3), where \(I_{n}\) stands the intrinsic message converted from \(rx\). \[I_{n}=B_{\mathrm{s}}B_{m}= \begin{cases}01,&\text{if }rx>T_{y},\\ 00,&\text{if }T_{y}\geq rx\geq 0,\\ 10,&\text{if }0>rx\geq-T_{y},\\ 11,&\text{if }rx<-T_{y}.\end{cases}  \tag{3}\]  
When implementing on FPGA, direct use of adders or comparators consumes more LUT resources compared to combinational logic circuits. To enhance the HUE and to adapt to the dual-port characteristics of the gate circuit, we have devised an improved algorithm that builds on these observations. To optimize the memory structure, in CNU, only 3 bits are used to store each c2v message, representing the product of sign bits, min1 and min2, instead of storing all the \(R_{mn}\) results. The values of min1 and min2, which are calculated in CNU, can be used to restore the exact \(R_{mn}\) in VNU before use [22]. Due to the fact that the magnitude part of the CNU's input is only 1 bit, finding min1 and min2 can be easily formulated as Boolean operations with AND and OR gates. For example, the expression for finding min1 and min2 for 8 bits is given by Equation (4). \[ \begin{split} a&=B_{m1}B_{m2}B_{m3}+B_{m1}B_{m2}B_{m4}+B_{m1 }B_{m3}B_{m4}+B_{m2}B_{m3}B_{m4}\\ &=B_{m1}B_{m2}(B_{m3}+B_{m4})+(B_{m1}+B_{m2})B_{m3}B_{m4},\\ b&=B_{m5}B_{m6}B_{m7}+B_{m5}B_{m6}B_{m8}+B_{m5}B_{m7}B_{m8}+B_ {m6}B_{m7}B_{m8}\\ &=B_{m5}B_{m6}(B_{m7}+B_{m8})+(B_{m5}+B_{m6})B_{m7}B_{m8},\\ c&=B_{m1}B_{m2}B_{m3}B_{m4},\\ d&=B_{m5}B_{m6}B_{m7}B_{m8},\\ min_{1}&=cd,\\ min_{2}&=abc+abd+acd+bcd=ab(c+d)+(a+b)cd.\end{split}  \tag{4}\]  
To optimize the hardware implementation of the CNUs, a pipeline operation can be performed to divide the 32 inputs into four groups. This enables the calculation of four sets of min1 and min2, which can then be cascaded to a second stage by inputting these sets.