## 1 Introduction  
Our world is characterized by the widespread distribution of various cyber-physical systems (CPSs) into all spheres of human activity [1; 2; 3]. Currently, intensive research is being carried out in the field of designing and ensuring the safety of the operation of CPSs [4; 5; 6; 7; 8; 9]. As the name suggests, these systems include digital (cybernetic) parts interacting with physical objects [10; 11; 12]. Very often, these digital parts include various sequential blocks [3; 11]. These blocks can implement, for example, various security algorithms [13]. To improve the overall quality of a cybernetic part, it is necessary to optimize characteristicsof its sequential blocks. In the current paper, we discuss a case where the sequential blocks of digital parts are represented by finite state machines (FSMs) [14]. Very often, the models of Mealy FSMs are used for the specification of sequential blocks [14; 15]. The process of FSM design requires balancing the values of the occupied chip area, the maximum operating frequency, and power consumption [16; 17]. We discuss a case where FSM circuits are designed with field-programmable gate arrays (FPGAs). The look-up table (LUT) elements are the basic elements used for implementing FSM circuits. As follows from [18; 19], the circuit area has the greatest influence on the values of other characteristics. The area can be reduced due to jointly applying various methods of structural decomposition. In our paper [20], we propose an optimization method based on jointly applying the methods of twofold state assignment (TSA) and encoding of output collections. As a result, LUT-based FSM circuits have exactly three logic levels. Let us point out that FPGAs are very popular in modern digital systems design [5; 7; 8]. In this paper, we focus our attention on FPGA chips produced by AMD Xilinx [21] because this corporation is the largest manufacturer of FPGA chips. To implement an FSM circuit, we use configurable logic blocks (CLBs) that include four main components: LUTs, programmable flip-flops, dedicated multiplexers, and fast interconnections. To obtain a multi-CLB circuit, the system of inter-CLB programmable interconnects should be used. The proposed method reduces the values of LUT counts in the multi-level circuits of Mealy FSMs. The main principle of TSA-based FSMs assumes using two types of internal state codes [20]. Each state is represented by both a maximum binary state code (MBC) and an extended state code (ESC) [20]. Such an approach allows for reducing FSM hardware compared to methods based solely on MBCs. However, the approach in [20] is connected with some overhead. Namely, an additional state transformer block should convert MBCs into ESCs. This converter consumes additional LUTs and interconnections. In this paper, we show how to reduce the noted overhead. The main contribution of this paper boils down to the following. We have proposed: (1) a novel design method aimed at reducing the LUT counts in the circuits of FPGA-based Mealy FSMs with twofold state assignment and encoding of output collections; (2) a generalized FSM architecture, including three blocks of partial Boolean functions (PBFs); (3) a method of choosing one of seven possible FSM architectures based on the generalized architecture. To reduce hardware, we propose to use at least two cores of logic [22]. The first core generates PBFs based on MBCs. The second core uses ESCs for this purpose. This approach allows for reducing hardware in the state transformer circuit because now only a part of the MBCs is transformed into ESCs. The scientific novelty of the proposed approach also includes an improvement in the known method of encoding of output collections by some additional variables. This encoding is done so that each of the cores includes some additional variables that do not occur in the second core. Thanks to this approach, the number of LUTs generating additional variables is reduced.