## 5 Conclusions  
This study improved the performance of [PERSON] and [PERSON]'s modified Booth-encoder-based multifunction modulo (\(2^{n}\pm 1\)) multiplier [8] by basing it on a radix-4 Booth encoding scheme to have a wider operation range, lower power consumption, faster operation, better area efficiency, and lower area-delay product (ADP) and power-delay product (PDP). It can support the multiplication functions of both modulo (\(2^{n}+1\)) and modulo (\(2^{n}-1\)) multiplexers in the same circuit hardware. By integrating their single modulo functions into a multifunction modulo (\(2^{n}\pm 1\)) multiplier, it can save up to 50.92% (\(n=32\)) of ADP and 50.02% (\(n=32\)) of PDP compared with merged separate circuits. This multifunction \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Item**} & \multicolumn{2}{c}{**Merged Circuits**} & \multicolumn{2}{c}{**Modulo (\(2^{n}\pm 1\))**} & \multicolumn{2}{c}{**Proposed Work**} \\  & \multicolumn{1}{c}{**[1,2]**} & \multicolumn{2}{c}{**[8]**} & \multicolumn{2}{c}{**Proposed Work**} \\ \hline \hline \multirow{2}{*}{\(n\)} & **PDP** & **PDP** & **Saving** & **PDP** & **PDP** & **PDP** \\  & **Saving** & & **Saving** & **Saving** & **PDP** & **Saving** \\ \hline
8 & 1.2291 & 0 & 0.7658 & +37.70\% & 0.7368 & +40.05\% \\ \hline
16 & 4.0743 & 0 & 2.4190 & +40.63\% & 2.2180 & +45.56\% \\ \hline
32 & 16.6939 & 0 & 10.3132 & +38.22\% & 8.3429 & +50.02\% \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Comparison of the PDP of the proposed study and other methods. \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**Item**} & \multicolumn{2}{c}{**Modulo (\(2^{n}-1\))**} & \multicolumn{2}{c}{**Modulo (\(2^{n}+1\))**} & \multicolumn{2}{c}{**Merged Circuits**} & \multicolumn{2}{c}{**Modulo (\(2^{n}\pm 1\))**} & \multicolumn{2}{c}{**Proposed Work**} \\  & \multicolumn{1}{c}{**[1]**} & \multicolumn{1}{c}{**[2]**} & \multicolumn{2}{c}{**[1,2]**} & \multicolumn{2}{c}{**[8]**} & \multicolumn{2}{c}{**Proposed Work**} \\ \hline \hline \multirow{2}{*}{\(n\)} & **Power** & **Power** & **Power** & **Power** & **Power** & **Power** & **Power** & **Power** & **Power** \\  & **(W)** & **(W)** & **(W)** & **Saving** & **(W)** & **Saving** & **(W)** & **Saving** \\ \hline
8 & 0.042 & 0.044 & 0.086 & 0 & 0.048 & +44.19\% & 0.048 & +44.19\% \\ \hline
16 & 0.105 & 0.105 & 0.21 & 0 & 0.114 & +45.71\% & 0.107 & +49.05\% \\ \hline
32 & 0.282 & 0.283 & 0.565 & 0 & 0.309 & +45.31\% & 0.289 & +48.85\% \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Comparison of the dynamic powers of the proposed method and other methods. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Item**} & \multicolumn{2}{c}{**Modulo (\(2^{n}-1\))**} & \multicolumn{2}{c}{**Modulo (\(2^{n}+1\))**} & \multicolumn{2}{c}{**Merged Circuits**} & \multicolumn{2}{c}{**Modulo (\(2^{n}\pm 1\))**} & \multicolumn{2}{c}{**Proposed Work**} \\  & \multicolumn{1}{c}{**[1]**} & \multicolumn{1}{c}{**[2]**} & \multicolumn{2}{c}{**[1,2]**} & \multicolumn{2}{c}{**[8]**} & \multicolumn{2}{c}{**Proposed Work**} \\ \hline \hline \multirow{2}{*}{\(n\)} & **Delay** & **Delay** & **Delay** & **Delay** & **Delay** & **Delay** & **Delay** & **Delay** \\  & **(ns)** & **(ns)** & **(ns)** & **Saving** & **(ns)** & **Saving** & **(ns)** & **Saving** \\ \hline
8 & 13.203 & 15.332 & 15.332 * & 0 & 15.954 & +4.06\% & 15.351 & \(-\)0.12\% \\ \hline
16 & 19.346 & 19.457 & 19.457 * & 0 & 21.219 & +9.06\% & 20.729 & \(-\)6.54\% \\ \hline
32 & 30.532 & 28.565 & 30.532 * & 0 & 33.376 & +9.31\% & 28.868 & +5.45\% \\ \hline \hline \end{tabular}  
*: Taking the worst case of delay time between [1,2].  
\end{table} 
Table 3: Comparison of the delay times of the proposed method and other methods.