## 6 System Verification and Experiment Results
### Experiment Results  
To evaluate the benefit of the trade-off between the flexibility provided and the resource used by DyCe, we implement the convolution engine structures of both DyCe and [7] on the Xilinx Vivado synthesis tool. Both structures contain a PE array, an adder module, registers, and programmable connections. Since under similar processing cycles, the PE amount used in DyCe was 121, and the PE amount of [7] requires 144, this indicates that the column streaming mapping algorithm for the PE array can reduce the PE amount by eliminating the paddings [5]. Hence, DyCe gains the spare resources for the reconfigurable connections in terms of flexibility. To move forward and form the full-size multiply-Add (MAD) modules in a complete convolution engine, an adder module is also integrated into DyCe and [7] for a fair comparison. The convolution engine implementation result of DyCe and [7] is released in this subsection. By a cross-reference from [7], we can see the DyCe's potential for integrating into a complete system of an edge AI accelerator in terms of LPUS scope. Figure 23: Partial sums generated by Col9_Adder. Figure 22: Partial sums generated by Col0_Adder. Table 3 releases the primitive usages consumed by DycSe and [7] when choosing Virtex-7 XC7 VX485T as the targeting product. To clearly show the comparison, we direct the data in Table 3 to a line chart, shown in Figure 26. In the line chart, the blue line illustrates the primitives used by DycSe, while the orange line shows the resource utilized by [7]. The result indicates that DycSe contains more resources at LUT2, LUT3, LUT6 (Look-up tables), and LDCE (Latch). Due to the demuxes utilized in the adder module to provide flexibility for the PE array in DycSe, LUT2 and LUT3 amounts of DycSe are more than [7]. Similarly, the quantity LUT6 is also larger, mainly utilized by adders. Since the adder module requires some delay chains, LDCEs are also more than [7]. Although the primitive number shows that DycSe contains more LUTs than [7], there is only a 1% overhead of utilization in DycSe compared to [7] in the total FPGA resource, as shown in Figure 27.  
Figure 24: Input features and weights data among the column adder submodule. Figure 25: Partial sums generated by row adder R9_left (R7). Figure 27: Resource utilization of the targeted FPGA. (**a**) The utilization of DycSe; (**b**) The utilization of [PERSON] et al. [7]. \begin{table}
\begin{tabular}{c c c c} \hline \hline \multirow{2}{*}{**Primitives**} & \multirow{2}{*}{**Functional Category**} & \multicolumn{2}{c}{**Primitive Count**} \\ \cline{3-4}  & & **DycSe** & **[PERSON] et al. [7]** \\ \hline LUT1 & LUT (Look-up table) & 44 & 0 \\ \hline LUT2 & LUT & 3571 & 0 \\ \hline LUT3 & LUT & 6066 & 1104 \\ \hline LUT4 & LUT & 1558 & 1040 \\ \hline LUT5 & LUT & 2064 & 2304 \\ \hline LUT6 & LUT & 2037 & 416 \\ \hline CARRY4 & Carry Logic & 548 & 256 \\ \hline LDCE & Flop \& Latch & 3344 & 2304 \\ \hline FDCE & Flop \& Latch & 2544 & 2304 \\ \hline FDE & Flop \& Latch & 0 & 16 \\ \hline DSP48E1 & Block Arithmetic & 121 & 144 \\ \hline MUXF7 & Multiplexer & 16 & 32 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Report Primitives Usage, using Xilinx Vivado to Synthesize. Figure 26: Primitives amounts of DycSe and [PERSON] et al. [7]. Regarding power consumption, since not every work utilizes the same chip technology, we use the following methods to present Table 4, which contains the separated convolution engine's power consumption along with the whole system. (I) Re-construct the cross-reference [\(\mathcal{T}\)]'s convolution engine on the Xilinx FPGA tool as DycSe does. (II) Compare their power consumption ratio while both are on the same FPGA platform. (III) Disclose the power consumption of other reference works in convolution engine form along with the whole system form. (IV) Normalize all the ASIC work to 40 nm technology according to the datasheets and references [8; 26; 27; 28]. (V) The result also shows the power consumption of each work at the same computation ability, normalized.