## 2 Split DC Link Voltages in Zero-Sequence-Restricted Three-Phase Three-Level AC-DC Converter
+m_{0}(t), \tag{5}\]  
where \(M(t)\) represents the magnitude of sinusoidal modulating signals and \(m_{0}(t)\) denotes the zero-sequence component [37]. As a result, converter-imposed AC-side voltages (cf. Figure 1) contain zero-sequence constituent \(v_{0}(t)\) imposed by \(m_{0}(t)\),  
\[\overset{\rightarrow}{v}_{ABC}(t)= \begin{pmatrix}v_{AN}(t)\\ v_{BN}(t)\\ v_{CN}(t)\end{pmatrix} \approx V_{M} \begin{pmatrix}\sin(\omega t)\\ \sin(\omega t-\theta)\\ \sin(\omega t+\theta)\end{pmatrix} +v_{0}(t). \tag{6}\]  
In general, \(m_{0}(t)\) may include both DC and high-order AC components in order to both equalize average values of the voltages across split DC link capacitors \(V_{DC1}\), \(V_{DC2}\) and reduce corresponding voltage ripples \(\Delta v_{DC1}(t)\), \(\Delta v_{DC2}(t)\)[29; 30]. In some cases, \(m_{0}(t)\) is permitted to include DC component only in steady-state, allowing to equalize split DC link voltages average values without influencing corresponding voltage ripples [35; 36; 37] (which is the case considered in this paper). It should be emphasized that under certain circumstances, \(m_{0}(t)\) must be kept zero at all time, calling for an external hardware-based equalization circuits [33]. Denoting reference values of average split capacitor voltages as \(V_{DC1}^{*}\) and \(V_{DC2}^{*}\), respectively, and assuming that  
\[V_{DC1}^{*}=V_{DC2}^{*}=0.5V_{DC}^{*},\quad C_{DC1}=C_{DC2}=C_{DC} \tag{7}\]  
with \(V_{DC}^{*}\) denoting overall DC link voltage reference value, it was shown in [37] that under the conditions (1), steady-state instantaneous split DC link voltages are given by  
\[v_{DC1,2}(t,\varphi)\approx V_{DC1,2}^{*}\mp\Delta v_{DC1,2}(t)=0.5V_{DC}^{*} \mp\Delta V(\varphi)\cos(3\omega t+\alpha(\varphi)) \tag{8}\]  
with load angle \(\varphi\)-dependent phase shift \(\alpha\) and ripple magnitude \(\Delta V\). In addition, the following dependencies were obtained in [37] for the case of \(\omega=100\pi\) rad/s base angular frequency,  
\[ \begin{array}{l}\Delta V(\varphi)\approx\frac{2S}{V_{DC}^{*}C_{DC}}E_{AC}^{ pu}[V],\\ E_{AC}^{Pu}=\left(-84.46|\cos\varphi|^{4}+116.3|\cos\varphi|^{3}-124.1|\cos \varphi|^{2}+9.197|\cos\varphi|+265.1\right)\cdot 10^{-6}\left[\frac{I}{ \Delta t}\right],\\ |\alpha(\varphi)|\approx\left(-308.1|\cos\varphi|^{4}+410.7|\cos\varphi|^{3}-1 96.7|\cos\varphi|^{2}+9.883|\cos\varphi|+86.87\right)\cdot\frac{2\pi}{360^{ \circ}}\left[rad\right].\end{array}  \tag{9}\]  
Figure 2: Generalized topology of a three-level three-phase AC-DC power converter. Unfortunately, distinction between leading and lagging power factors was not addressed in [37]. Re-examining the results, phase shift in (10) should be adopted, in general case, as  
\[\alpha(\varphi)\approx\left\{ \begin{array}{ll}|\alpha(\varphi)|,&\varphi<0\\ -|\alpha(\varphi)|&\varphi>0\end{array} \right. \tag{11}\]  
Hence, operation with lagging power factor (i.e., \(\varphi>0\)) tends to align the positive peak of the positive split DC link voltage with positive peak of AC-side phase voltage, while operation with leading power factor (i.e., \(\varphi<0\)) tends to synchronize the negative peak of the positive split DC link voltage with positive grid voltage peak, as shown in Figure 3 for different values of the power factor (PF = cos\(\varphi\)). As a result, DC link capacitance should be sized according to the worst case of AC-side power factor expected value according Figure 3.