# Arrayable TDC with Voltage-Controlled Ring Oscillator for dToF Image Sensors
## 2 Circuit Design Gated Ring Oscillator Type TDC and Principle of Operation  
The TDC, at the circuit level, uses a ring voltage-controlled oscillator-based TDC structure to quantify the time-of-flight, which is more compact and simpler compared to other types of TDCs (for example vernier type TDCs) [9; 12]. The block diagram of the gated ring oscillator type TDC module proposed in this paper is shown in Figure 1. The system mainly consists of a voltage-controlled ring oscillator (VCRO) circuit, preprocessing circuit, counter, encoder, phase arbiter circuit, and memory.  
Figure 1: Structure of gated ring oscillator type TDC system.  
The core of the TDC is a four-stage pseudo-differential voltage-controlled ring oscillator with VCRO as shown in Figure 1, which is controlled by a PLL generating a stable VCTRL voltage to obtain the desired oscillation frequency [13], thus expanding the frequency tuning range and improving the overall TDC measurement performance. Firstly, the START signal, STOP signal, and RESET signal go through a preprocessing circuit to generate the enable signals Ron, Rst, and EN_TDC to control the other modules to work. The fine resolution of the TDC is determined by the eight uniform phases (P1-P8) generated by the VCRO, and the minimum resolution is equal to the magnitude of the time of one phase difference, defined as P; the sampling circuits are used to control the frequency of the TDC at the moment when the START and the preprocessing circuit samples and holds the eight split-phase clocks at the onset of the START and STOP signals, respectively, to form an 8-bit binary code with phase position information, which is encoded by the encoder and converted into two 3-bit phase signals. The P8 phase output is followed by a 10-bit asynchronous counter for coarse counting, and the size of the coarse counting time for a cycle is equal to 8\"P. The overall system architecture of the TDC is very simple and does not require the use of an FPGA or processor to perform the time-to-digital conversion.  
In order to achieve smaller resolution, an accurate sampling of the START and STOP signals at the moment of their onset is required to correspond to partial-phase clock-phase information within the VCRO [10]. Conventional sample-and-hold circuits consist of switching devices, capacitors, and operational amplifiers. The response speed and accuracy of this circuit structure are not suitable for phase sampling of TDC [14]. The sampling circuit proposed in this paper is described in detail in Section 3. Figure 2 illustrates the timing principle of the TDC quantization process in this design. START and STOP pulse signals arrive at the time that the sampling circuit samples the eight split-phase clock phases to generate an 8-bit binary code consisting of 0 or 1. The encoder then converts this special 8-bit binary code into a 3-bit code that represents the fine resolution results. The counter is incremented by one when the VCRO cycles through eight phase changes.  
The time interval expression to be measured is as follows:  
\[\mathrm{T}=\left(\mathrm{N}\times 8-\mathrm{M}_{\mathrm{Start}}+\mathrm{M}_{ \mathrm{Stop}}\right)\times\mathrm{P} \tag{1}\]  
where N is the counter reading and is equal to the encoder 1 and encoder 2 output code corresponding to the decimal value and P product.  
Figure 2: Timing schematic of the TDC quantization process.