# Process Development of Low-Loss LPCVD Silicon Nitride Waveguides on 8-Inch Wafer
## 3 Fabrication Process  
The suggested fabrication process flow of the Si\({}_{3}\)N\({}_{4}\) waveguide on an 8-inch CMOS line is shown in Figure 7. \begin{table}
\begin{tabular}{c c} \hline
**Structural Parameters** & **Size** \\ \hline \(\mathrm{W_{taper}}\) & 0.3 \(\mathrm{\SIUnitSymbolMicro m}\) \\ \(\mathrm{W_{WG}}\) & 1.0 \(\mathrm{\SIUnitSymbolMicro m}\) \\ \(\mathrm{L_{taper}}\) & 200 \(\mathrm{\SIUnitSymbolMicro m}\) \\ \hline \end{tabular}
\end{table} 
Table 1: Structural dimensions of the inverse tapered edge coupler. Figure 5: The simulation curve of the coupling efficiency at different widths (**a**) \(\mathrm{W_{taper}}\) and (**b**) \(\mathrm{L_{taper}}\). Figure 6: The field distribution of the light transmission in the inverse tapered edge coupler at 1550 nm. Firstly, the BOX layer was split into two steps: 3 \(\upmu\)m thermal SiO\({}_{2}\) and 1 \(\upmu\)m PECVD SiO\({}_{2}\). A 3 \(\upmu\)m-thick SiO\({}_{2}\) was grown on an 8-inch bare silicon wafer using a thermal oxide process. The oxide was grown on both sides of the wafer in this process, which limited the deformation of the wafer due to stress. Following this was the deposition of 1 \(\upmu\)m SiO\({}_{2}\) via the PECVD process. We separated the BOX layer into two steps due to two considerations: 1. The texture of the SiO\({}_{2}\) film deposited by the PECVD process was looser, and thus easier to etch and reflow in the following annealing process. 2. The processing time of thermal oxide increases drastically with the increase in thickness; reducing 1 \(\upmu\)m can save much time in the thermal oxide process. In addition, the loose PECVD SiO\({}_{2}\) would harden in the following annealing process to form the property close to thermal oxide. Secondly, a layer of PECVD SiO\({}_{3}\)N\({}_{4}\) film was deposited as the hard mask (HM) layer in the etching of the waveguide layer. Then the waveguide layer was patterned and etched on the BOX layer with a depth of around 0.42 \(\upmu\)m, which balanced the loss of the BOX layer in the following chemical mechanical polishing (CMP) step. At the same time, in order to limit the stress of the silicon nitride film on the wafer, as shown in Figure 8, we added a checkerboard stress relief pattern that could make the film into a discontinuous state on the nonwaveguide position on the wafer. Because phosphoric acid (H\({}_{3}\)PO\({}_{4}\)) has a very high selectivity ratio for silicon nitride and silicon oxide, we immersed the wafer in phosphoric acid at 150 \({}^{\circ}\)C for 1500 s to completely remove the Si\({}_{3}\)N\({}_{4}\) hard mask while ensuring that it did not damage the BOX layer [29]. After removing the hard mask, the BOX layer was annealed at 1050 \({}^{\circ}\)C for 3 h to make the SiO\({}_{2}\) trench sidewalls reflow, thus reducing the roughness of the trench sidewalls and harden the PECVD SiO\({}_{2}\). Then, 430 nm Si\({}_{3}\)N\({}_{4}\) was deposited by the LPCVD process. In order to reduce the warpage of the wafer and improve the uniformity of CMP, as shown in Figure 7h, after the deposition of the core layer, we removed all the silicon nitride film in the nonwaveguide area to release the stress accumulation in the film, then planarized the wafer surface with CMP. Since the H-bond was not completely released from the film during the LPCVD deposition of the silicon nitride film [30], an annealing process with 1050 \({}^{\circ}\)C for 3 h was applied after the CMP to release the remaining H-bonds in the silicon nitride film. Finally, 2.6 \(\upmu\)m SiO\({}_{2}\) was deposited as the top cladding layer of the waveguide by the PECVD process. Some SEM images of the intermediate steps are shown in Figures 9 and 10. Figure 7: The fabrication process flow of the Si\({}_{3}\)N\({}_{4}\) waveguide.