# An FPGA-Based Four-Channel 128k-Point FFT Processor Suitable for Spaceborne SAR
## 3 Hardware Implementation of the FFT Processor
### Single Channel FFT Processor Structure  
According to the radix-\(2^{3}\) algorithm scheme, a single-channel 32k-point FFT processor contains five radix-\(2^{3}\) operation stages, that is, 32k = \(8^{5}\). The five operating stages are serially connected through four non-constant factor multipliers. The output data of the previous stage is used as the data input of the next stage through the non-constant factor multiplier, thus, forming a channel FFT structure, as shown in Figure 11. The stage unit in the figure is the same as the stage structure in Figure 8, but the size of the D unit is different; the TW_GEN unit generates the required twiddle factors in real time and provides them to the non-constant factor multiplier. It can be seen from the figure that each stage contains three processing units (PE1-PE3) and an address controller; each processing unit contains an SDF structure. In addition, PE1 contains a \(-j\) term multiplier, and PE2 contains \(-j\) and \(W_{8}^{1}\) multiplier; each SDF structure contains a RAM unit (D unit in Figure 8), a radix-2 butterfly unit (BF2) and two data selectors.  
Figure 11: Single channel structure and its sub-modules.  
Figure 10: Data word length adjustment strategy for a radix-\(2^{3}\) butterfly unit.  
The functions and implementation methods of each module are as follows:  
* The radix-2 butterfly unit (BF2) realizes a complex butterfly operation, which contains logic circuits for the addition and subtraction of complex numbers.
* The data selector is used to determine the inflow and outflow direction of data, which contain address control logic to control RAM and work with the BF2.
* The SDF module implements a pipeline to receive input data, and a pipeline to output the data after the radix-2 butterfly calculation. The SDF module contains a piece of RAM, which can be easily implemented by calling the IP core Block Memory Generator.
* The processing unit modules (PE1, PE2, and PE3) are used to rotate the data in a specific direction after the SDF structure, that is, to multiply the factors \(-j\) and \(W_{8}^{1}\).
* The address controller is used to provide the three SDF structures with the address values of the current read and write operations on the RAM in each clock cycle, and indicate the current operation of the SDF structure on the RAM (cache the newly input data or cache the BF2 settlement result). The logic of the address controller is completely based on the sequence value of the current incoming time domain data, and therefore it can also be considered a data flow controller.
* The function of the operation-stage module (stage) is to complete the processing of data at an operation stage and output the results and their corresponding addresses in a pipeline.
* The TW_GEN module is used to generate the twiddle multiplication factor required for each clock to be used as the input of the non-constant factor multiplier. In this module, the CORDIC IP core in the FPGA needs to be called. The IP core is used to generate the \(\sin(x)\) value and the \(\cos(x)\) value when the input is \(x\); the value of \(x\) can be summarized as Equation (11) using Equation (4) and Figure 4. We name the TW_GEN connected after Stage 4 as TW_GEN4, and so on. For Equation (11), the numerical change rule of each parameter in each TW_GEN module is shown in Table 5. Except for \(N\), which is a fixed value, other values change in each clock cycle with the value in Table 5 using Equation (11) as follows:  
\[x=-\frac{2\pi}{N}\cdot n_{4}\cdot(k_{1}+2k_{2}+k_{3}) \tag{11}\]