## 3 Prototype Specification  
Figure 3 shows the external of the prototype. Table 2 lists the prototype specifications. It is composed of two field programmable gate array (FPGA) boards. Radio frequency (RF) part, modem part, STPA and BAA parts are implemented on one FPGA board while the FEC part is implemented on the other board. The transmitter and receiver are mounted on a single prototype. The receiver has two input ports capable of BAA signal processing. The prototype can also output the spectrum of the received signal after BAA processing as well as the constellations of the specific subcarrier. We employed a fast Fourier transform (FFT) filter bank based multicarrier transmission system. In our first proposal in [19], FFT windowing and BAA per subcarrier were performed on the premise of ideal symbol timing extraction. In the presence of strong inter-system interference, the timing extraction may fail and hence FFT and BAA should be applied before that. In the FFT filter bank, we also utilized an overlapped FFT [23] so as to treat transmission/reception signals as continuous and we can obtain frequency domain signal in arbitrary timing at the receiver side. Filter bank multicarrier system can also keep orthogonality between subcarriers after the FFT time domain windowing function by providing guard bands. Although spectral efficiency is degraded compared to OFDM, the main contribution of this paper is to verify the effectiveness of the proposed STPA-BAA scheme. With this configuration, BAA is applied just after the FFT filter bank, and then followed by original reception process i.e., symbol timing extraction, demodulation, and FEC decoding. Figure 4 shows a block diagram of the transmitter with STPA. The relationship between the system bandwidth, subcarrier bandwidth, and their arrangement is also depicted. The system bandwidth of the prototype is 102.4 MHz wherein central 5.2 MHz (=100 kHz \(\times\) 52 subcarriers) are utilized for signal transmission. Multicarrier transmission signal is firstly generated in the frequency domain. The information bit sequence is encoded by a convolutional encoder. The encoded bits are converted to complex symbols according to the modulation level specified. The symbol rate of each subcarrier is 50 kHz wherein the minimum frequency resolution of the prototype system is 12.5 kHz; one symbol is represented by four sample points. Through a serial-to-parallel (S/P) converter, the symbols are mapped to each subcarrier with being shaped to the root raised cosine (RRC) frequency \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameters** & **Values** \\ \hline FPGA & Xilinx Vertex-4 \\ Data bus bit-width & 8 bits \\ Clock frequency & 409.6 MHz \\ Sampling rate & 102.4 MHz \\ Number of FFT point & 8192 \\ Frequency resolution & 12.5 kHz \\ Symbol rate per subcarrier & 50 kHz \\ Subcarrier spacing & 100 kHz \\ Number of subcarrier, \(N\) & 52 \\ Pulse shaping filter & Root raised cosine, Roll-off factor: 0.2 \\ IF frequency & 140 MHz \\ Resolution of D/A Converter & 16 bits \\ Resolution of A/D Converter & 12 bits \\ Receiver dynamic range & 82 dB \\ BAA algorithm & CMA/PI/PI-CMA \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Prototype specifications. FPGA: field programmable gate array; FFT: fast Fourier transform; IF: intermediate frequency; D/A: digital-to-analog; A/D: analog-to-digital; BAA: blind adaptive array; CMA: constant modulus algorithm; PI: power inversion. Figure 3: External of the prototype. RF: radio frequency; FEC: forward error correction. response. Roll-off factor of the RRC filter is 0.2 and subcarrier becomes 80 kHz bandwidth. Fifty-two subcarriers are arranged with 100 kHz spacing (i.e., eight points) without inter-carrier interference. In the STPA part, the variable digital attenuator reduces the power of low-level subcarriers to \(G\) dB. In the experiment, the total output power of all subcarriers are increased by an amplifier.