# Atomic Layer Deposition (ALD) of Metal Gates for CMOS
## 1 Introduction  
### Scaling and Issues of SiO\({}_{2}\)/poly-Si Gate Stacks  
Basic principle of FETs was proposed by [PERSON] in 1925 [1], in which, an electric field generated by a voltage applied to the gate electrode is used to control the flow of current between the drain and source electrodes. The metal-oxide-semiconductor field-effect transistor (MOSFET) was invented by [PERSON] and [PERSON] in 1959 [2], in which the device structure is obtained by growing a layer of silicon dioxide (\(\mathrm{SiO}_{2}\)) on top of a silicon substrate and depositing a layer of metal on top, as shown in Figure 1a. The gate stack is equivalent to a planar capacitor, with one of the electrodes replaced by the semiconductor substrate. When a large enough voltage is applied to the gate (gate voltage \(V_{g}>\) threshold voltage \(V_{t}\)), it modifies the distribution of charges in the doped bulk Si and form a conductive channel (inversion layer) near the \(\mathrm{SiO}_{2}\)/Si interface and a depletion region below, as shown in Figure 1b, switching the device to its \"on\" state. If the gate voltage is lower than \(V_{t}\), the transistor is switched \"off\". By using different doped Si substrates, n-type and p-type MOSFETs could be made. In 1967, [PERSON] filed his patent of CMOSFETs [3], in which the two types of the MOSFETs are connected in a way shown in Figure 2 to form an inverter. When a gate voltage generatesan \"on\" in one MOSFET, it always give the \"off\" in the other one. The gate voltage change will switch simultaneously the states of the two MOSFETs. By doing this, the output voltage of the CMOSFETs will switch between high voltage (\(V_{dd}\)) and low voltage (\(V_{ss}\)). After the switching, or at the static state, there is always one device \"off\", or no current (ideally) between the line \(V_{dd}\) and line \(V_{ss}\). Such a low standby power characteristic of CMOSFET made it an enabler of Very Large Scale Integrated Circuit (VLSI) and Ultra-Large Scale IC (ULSI). In the history of MOSFET technology development, the gate stack using SiO\({}_{2}\) as dielectric and poly-Si as gate electrode (Poly-Si/SiO\({}_{2}\)/Si) was the most successful story. SiO\({}_{2}\) dielectric was used in the first Si MOSFET technology, together with aluminum (Al) metal gate. In 1971, poly-Si gate was induced to replace Al. In 1989, the dual gate technology by doping the poly-Si was employed in 800 nm node to simplify CMOS process. The Poly-Si/SiO\({}_{2}\)/Si stack had been used for 10 generations, until 130 nm. During these years, switching performance of the devices was continuously improved, and device number per unit area increased, by scaling down the dimension of the MOSFETs. For a MOSFET with thick enough SiO\({}_{2}\), the leakage through it is negligible compared to that between the source and drain. As its thickness is reduced to nanometer level, the tunnel leakage due to quantum effect increases to large extent and finally dominates the device leakage [4]. According to the prediction of ITRS in 1999, the pure SiO\({}_{2}\) could not be used as the gate dielectric after 130 nm node. For a gate dielectric layer of SiO\({}_{2}\), the gate leakage density \(J_{g}\) could be described as  
\[J_{g}=\frac{A}{T_{ox}^{2}}\exp\{-2T_{ox}\sqrt{\frac{2m^{*}q}{\hbar^{2}}(\Phi_ {B}-\frac{V_{ox}}{2})\} \tag{1}\]  
where \(T_{ox}\) is the layer thickness, \(\Phi_{B}\) the potential barrier height between the metal and the SiO\({}_{2}\), \(V_{ox}\) the voltage drop through the SiO\({}_{2}\), \(m^{*}\) the electron effective mass in the dielectric, and \(A\) an experimental  
Figure 1: MOSFET (**a**) and its energy band structure (**b**), where \(q\) is the carrier density, \(V_{G}\) the gate voltage, \(V_{t}\) the threshold voltage, \(E_{f}\) the fermi level, \(E_{c}\) and \(E_{v}\) the conduction band and valence band edges, respectively. Figure 2: CMOSFETs, where input voltage is applied to A and output is extracted by the voltage of Q.  
constant.