# An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios
## 3 Baseband Modulator Architecture
### Baseband Modulation for 5G Waveform Candidates
The iterative nature of memory-based architectures is well adapted to this scenario where the ability for continuous data-stream processing is not a priority requirement. Second, the lower resource utilization of memory-based architectures allows for a more scalable replication of IFFT cores per sub-band branch. Third, memory-based architectures allow for the application of pruning algorithms [32]. Before starting the IFFT processing, the location of the non-zero values within the \(N^{\prime}\)-element input array are known. This can be used to prune arithmetic operations between zero values and thus reduce the transform processing time. The IFFT architecture implemented follows a Decimation-In-Frequency (DIF) Radix-2 algorithm, where the processing of an \(N^{\prime}\)-point IFFT is divided into \(\log_{2}N^{\prime}\) processing stages of \(\frac{N^{\prime}}{2}\) processing steps. The processing steps are executed by a butterfly unit that picks two input values and produces two results: (1) the sum of the two input values; and (2) the difference of the two input values multiplied by a complex twiddle factor. The memory-based IFFT architecture implemented is depicted in Figure 5, and its main constituent elements are: a control engine, a Radix-2 butterfly unit, two \(\frac{N^{\prime}}{2}\)-element memory banks (M0 and M1) and a ROM memory used to control IFFT pruning (pruning ROM). Due to the DIF algorithm employed, IFFT results are not produced in natural order. Therefore, a reordering unit is attached to deliver IFFT output results in natural order to the subsequent datapath modules. The operation of the IFFT module can be divided into two phases: load input/unload results and process transform. During the load input/unload results phase, the control engine issues read/write operations on M0 and M1 to fill the memory banks with the incoming data samples, while forwarding the results from previous transform processing to the reordering unit. The process transform phase corresponds to the execution of the processing steps of each Radix-2 IFFT processing stage. The control unit fetches values from M0 and M1 to the butterfly unit that performs a processing step. Then, the results are stored back in M0 and M1. In this architecture, the control engine uses a binary counter to generate all the signals to control the butterfly unit and memory bank addressing. We adopted the butterfly structure and address generation scheme from [33] and further extended the architecture to support IFFT pruning. The complex multiplier used for twiddle factor multiplications was implemented with three real multipliers, one adder, and two subtractors. Figure 5: Memory-based architecture for the IFFT modules used in the UFMC modulator. The profile of the IFFT input data array is known in advance: 12 subcarriers are mapped to the central bins of a 64-element array, and the remaining 52 elements are zero. Following the DIF Radix-2 algorithm, it is possible to pre-determine the processing steps that need to be executed and those that can be pruned. The pruning ROM contains information about the number of processing stages where pruning occurs--pruning stages--and for each of these stages, it provides the number of processing steps to be executed, as well as their corresponding control binary counter values to be used by the control engine. For the pruning stages, the control engine fetches the binary counter values from the pruning ROM. When the end of the pruning ROM is reached, the control engine knows that there are no more pruning stages and, thus, internally generates the binary counter values simply by incrementing it from 0 to \(\frac{N^{\prime}}{2}-1\). In our case, there are two pruning stages comprising 12 and 24 processing steps each. Therefore, the pruning ROM is made of 39 words: one to indicate the amount of pruning stages, two to indicate the amount of processing steps of each pruning stage, and the \(12+24=36\) binary counter values for each processing step.