# Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency
## 7 Conclusions  
In this paper, a novel architecture for 5G NR LDPC encoding is presented. The designed encoder can be configured to encode all LDPC codes from the 5G NR standard in runtime. The architecture is based on the serial encoding schedule that processes one CPM of the PCM per clock cycle. However, it incorporates a novel approach of reusing available hardware resources for processing multiple CPMs per clock cycle for codes with shorter codewords. This is obtained by the innovative design of the circular shifting network which can be configured to work as a single shifter for long input data vectors or as multiple independent CSs for shorter inputs. Proposed CS architecture is also applicable in other hardware designs for both encoding and decoding of LDPC codes when flexibility is a requirement.  
In addition to the architectural contributions, the paper also presented the method for offline encoding schedule optimization when multiple CPMs are processed per clock cycle. The GA-based optimization provided a great improvement in the encoding throughput (up to 183%) and latency (up to 92%). Implemented encoder provided multi-gigabit throughput and showed significant improvement in hardware usage efficiency, when compared with other architectures used for encoding of QC-LDPC codes. On average, the proposed encoder implementation has five times higher HUE, when compared to highly parallel implementations and about 22% higher HUE, when compared to the serial implementation. The obtained throughput and latency match the required specifications for all currently proposed 5G use cases. The flexibility of the proposed encoder makes it applicable in any of those scenarios.  
Some contributions described in the paper can be applied in encoders or decoders for other QC-LDPC codes. The GA-based optimization can be performed for any architecture  
Figure 14: Normalized hardware usage efficiency for various 5G NR LDPC encoder architectures depending on the lifting size.  
\begin{table}
\begin{tabular}{c c c c c c c c c c c} \hline \hline \multirow{2}{*}{**Architecture**} & \multicolumn{3}{c}{**Resources Utilization**} & \multirow{2}{*}{\(Thr_{norm,avg}\)} & \multirow{2}{*}{\(f_{max}\)} & \multirow{2}{*}{\(Thr_{avg}\)} & \multirow{2}{*}{\(Thr_{avg}\)} & \multicolumn{3}{c}{**Avg. HUE (Thr_{norm,avg}\)_Resources_**} \\ \cline{2-2} \cline{6-11}  & & & & & **36k** & & **(b/Cycle)** & **(MHz)** & **(Gbps)** & **b/Cycle/** & **b/Cycle/** & **b/Cycle/** & **Gbps/** \\ \hline Column based parallel [34] & 42,257 & 248,641 & 246,960 & 6 & 61.9 & 330 & 20.43 & 1.46 & 0.25 & 0.25 & 0.48 \\ Row based parallel [31; 35] & 26,180 & 126,986 & 131,185 & 3.5 & 30.1 & 470 & 14.15 & 1.15 & 0.24 & 0.23 & 0.54 \\ Serial & 1729 & 8712 & 9975 & 3 & 6.6 & 580 & 3.83 & 3.82 & 0.76 & 0.66 & 2.22 \\ Proposed optimized & 2215 & 11156 & 9635 & 5 & 10.3 & 580 & 5.97 & **4.65** & **0.92** & **1.07** & **2.70** \\ \hline \hline \end{tabular}
\end{table}
Table 3: Implementation results for various architectures of 5G NR LDPC encoder and average throughput and hardware usage efficiency comparison.  
that requires multiple rows processing for possible throughput increase. In addition to that, the proposed cyclic shifter design can be used in any encoder or decoder design that needs multiple shifting modes. A good example would be the encoder for WiMAX LDPC codes whose lifting sizes vary from 24 to 96.  
Conceptualization, V.L.P., D.M.E.M., and A.R.; methodology, V.L.P. and D.M.E.M.; validation, V.L.P.; formal analysis, V.L.P. and D.M.E.M.; investigation, V.L.P.; resources, A.R.; writing--original draft preparation, V.L.P., D.M.E.M., and A.R.; visualization, V.L.P.; software, V.L.P. and D.M.E.M.; supervision, A.R.; project administration, A.R.; funding acquisition, A.R. and V.L.P. All authors have read and agreed to the published version of the manuscript.  
This research received no external funding.