## 4 FPGA Realization of the Chaotic Dynamical System with a Butterfly-Like Curve of Balance Points  
Here, we realize the new chaotic dynamical system (4) using FPGA. Chaotic systems are implemented in FPGA using finite-difference numerical schemes and computer algorithms [37, 38, 39, 40]. The new dynamical system (4) with a closed butterfly-like curve of balance points can be represented in \((x,y,z)-\)coordinate system as follows:  
\[\left\{ \begin{array}{l}\dot{x}=z\\ \dot{y}=z\ (\ -ay-b|y|-cxz)\\ \dot{z}=x^{4}+y^{4}-|x||y|-x^{2}\end{array} \right. \tag{8}\]  
For FPGA implementation of the chaotic system (8), we need to discretize it first. With the help of a forward Euler integration method [45], we obtain a discrete-time representation of the chaotic system as given below. \[\left\{ \begin{array}{l}x[n+1]=x[n]+hz[n]\\ y[n+1]=y[n]+\{z[n](-ay[n]-b\ \mathrm{abs}(y[n])-c\ x[n]z[n])\}\\ z[n+1]=z[n]+h\{x^{4}[n]+y^{4}[n]-\mathrm{abs}(x[n])\mathrm{abs}(y[n])-x^{2}[n] \}\end{array} \right. \tag{9}\]  
Figure 10: Transient chaos pattern: (**a**) time series of \(v\) in the interval \([0,500]s\); (**b**) the phase portrait of the attractor in the \((v,w)\) plane; (**c**) time series of \(v\) in the interval \([0,225]s\); (**d**) the corresponding phase portrait of the attractor in the \((v,w)\) plane. In the forward Euler scheme (9), \(n\) and \(n+1\) are the current and next counters respectively, while \(h\) is the discretization step size. Also, \(\text{abs}(y)=|y|\) is the absolute value function, which is defined as follows:  
\[\text{abs}(y)=\left\{ \begin{array}{rl}y&\text{if}\quad y\geq 0\\ -y&\text{if}\quad y<0\end{array} \right. \tag{10}\]  
The chaotic behavior of the system (8) can be obtained by selecting the coefficient parameters as \((a,b,c)=(14,0.5,1.4)\) and the initial phase as \((x_{0},y_{0},z_{0})=(0.05,0.05,0.05)\). A Python code for implementing the discretized chaotic system (9) is shown in Algorithm 1. ```
Input: Initial states x0, y0, and z0. System parameters a, b, and c. Output: xn, yn, and zn  j = 1  step = 500,000  x = x0  y = y0z = z0 while j < step do  xn.insert(j, x + h * z)  yn.insert(j, y + h * (z * (-a * y - b * abs(y) - c * x * z))  zn.insert(j, z + h * (pow(x,4) + pow(y,4) -abs(x) * abs(y) - pow(x,2)))  x = xn[j]  y = yn[j]  z = zn[j]  j = j + 1 end
```  
**Algorithm 1** Python code for the new discrete-time chaotic system (9)  
Figures 11-13 represent the simulated orbits for our chaotic oscillator system (7) using the Euler method (Algorithm 1) in the \((x,y)\), \((y,z)\) and \((x,z)\) planes, respectively with \(h=0.001\). Figure 11: The 2-D signal plot of the discrete-time chaotic system (9) using Forward Euler finite-difference scheme in the \((x,y)\) plane. Figure 14 shows the top-level hardware design of the discrete-time chaotic system (8). The chaotic system (8) has three inputs for the initial phase signals \(x0\), \(y0\) and \(z0\). In addition to the clock and reset signals, the chaotic system (9) has the system parameters \(a\), \(b\) and \(c\) as the other inputs. As shown in Figure 14, the top-level block diagram contains three sub-systems, which are implemented according to Equations (9) and (10). Each state variable in any of the chaotic sub-system has 32-bits. It is described using fixed-point representation which consists of 1-bit for the sign, 7-bits for the integer part, and 24-bits for the fractional part (see Figure 15). The Hardware Description Language (VHDL) code for the top level of the chaotic system (9) is devised as in [37]. The three sub-circuits are implemented using basic mathematical operations (Adder, Subtractor, Multiplier, Multiplexer, and Single Constant Multiplier). The basic blocks of these operations are shown in Figure 16. The VHDL codes for the adder/subtractor, and multiplier are taken as represented in [37]. Figure 12: The 2-D signal plot of the discrete-time chaotic system (9) using Forward Euler finite-difference scheme in the \((y,z)\) plane.