# A Low-Band Multi-Gain LNA Design for Diversity Receive Module with 1.2 dB NF
## 2 Structure of the Designed LNA  
Figure 2 shows the structure of the designed low band LNA. To achieve a Noise Figure (NF) below 2 dB at high gains, the core LNA adopts a cascode CS with a source inductive degeneration structure. Ignoring the pad and bonding wire effects, gate-drain capacitance (CGD), etc., the NF and gain of the cascode CS LNA at an input resonance frequency can be simplified as below [4]:  
\[NF=1+g_{ml}R_{s}\gamma(\omega_{0}/\omega_{T})^{2} \tag{1}\]  
\[V_{out}/V_{in}=R_{L}/(2L_{S}\omega_{0}) \tag{2}\]  
where \(g_{ml}\) is the transconductance of the M1 transistor, \(R_{s}\) is the source impedance, \(\gamma\) is the coefficient where the value is around 2/3 to 1, and \(R_{L}\) and \(L_{S}\) are the load resistance and source inductance values, respectively. The size of M1 and M2 transistors are 100 \(\mu\)m/60 nm and 50 \(\mu\)m/60 nm, respectively. The G6, G5, and G4 gain modes are being decided in Core 1 on Figure 2, where the gain ranges are 16-19 dB, 10-13 dB, and 4-7 dB, respectively. The supply voltage which is generated by an LDO regulator, is 1 V and the design current specification values for these gain modes are 12 mA, 6 mA, and 3 mA, respectively. Therefore, to control the current in different gain modes, VB1 is being controlled. The VB1 values for G6, G5, and G4 gain modes are 420 mV, 360 mV, and 310 mV, respectively. Reduction of current and VGS-Vth simultaneously, would reduce the variation of the \(g_{m}\) of the input transistor which is necessary to keep the input matching variation small. In addition, to keep the linearity of the structure in the specification range, it is necessary that the current is not limited by transistor M2, which would cause the VDS of M1 to be reduced and consequently the linearity of the structure to be degraded. Figure 2: Structure of the designed low band LNA. For G6, the gain mode M5 transistor is off and all of the M2 transistors are on. To reduce the gain in G5 and G4 gain modes, M5 turns on and some parts of the transistors in M2, turns off. Then M5 provides some part of the current passing from M1 which helps for the gain reduction. The gain steps are decided according to the ratio of the M5 and M2 transistors [4]. R\({}_{\text{L}}\) also provides fine gain tuning for the designed structure around the gain of the interest. The low gain modes are G3 (\(-2\) to \(1\) dB), G2 (\(-8\) to \(-5\)), and G1 (\(-14\) to \(-11\)), which are decided using M3 and M4 transistors where their sizes are \(20\)\(\upmu\)m/\(60\) nm and \(20\)\(\upmu\)m/\(60\) nm, respectively. The VB2 voltage is \(420\) mV for G3, G2, and G1 gain modes. In order to improve the third-order intermodulation intercept point (IIP3), the attenuation circuit has been applied at the input part of the second path. The design specification defines the current consumption of the G3, G2, and G1 gain modes to be \(1.2\) mA. Phase discontinuity is the phase difference when there is a change in the gain modes of the structure, where it should be limited to some specific values. This can be controlled coarsely in Modem. However, for this design, we have implemented the block in such a way that this specification is achievable in analog block level with more accuracy. The reason to apply attenuation modes through active path is to keep the phase discontinuity within \(\pm 10^{\circ}\). Furthermore, the source degeneration inductance (L\({}_{\text{S}}\)) as well as the output load devices have been shared between the first and second paths, and for all of the gain modes in the same band, there will be no major output load changes (for example in the output capacitors). This keeps the phase variation for all gain modes very small. As mentioned before, this structure is meant to be applied for different frequency bands. To select the different bands, a 5 PST switch has been applied at input of the LNA.