## 1 Introduction and Problem Formulation
### Optimization of the Verilog HDL Code of the Concurrent Control System
#### 2.3.1 Optimization of the Sequential Part of the System (Redundant Sequential Logic Optimization)
Finally, both functions \(\ D_{3}=f(Q_{3},\ x_{1},\ x_{2})\) and \(\ D_{4}=f(Q_{4},\ x_{1},\ x_{2})\) have different arguments. However, due to the fact that the system is oscillated by the same clock signal, they can be transformed into the equivalent form. Let us explain this with an example. Assume that at time \(\ t=0\) both flip-flops are initialized with the same value, e.g., \(\ Q_{3}^{t=0}=Q_{4}^{t=0}=0\). Then, after inserting that into expression (2), we obtain the same functions \(\ D_{3}^{t=0}=D_{4}^{t=0}=x_{2}\). Since at the moment \(\ t=0\) the excitation functions of the flip-flops are equal, at the next moment \(\ t=1\), the Q values remain the same: \(\ Q_{3}^{t=1}=Q_{4}^{t=1}\). Furthermore, if both flip-flops are initialized by value \(\ Q_{3}^{t=0}=Q_{4}^{t=0}=1\), we obtain \(\ D_{3}^{t=0}=D_{4}^{t=0}=x_{1}\), and thus \(\ Q_{3}^{t=1}=Q_{4}^{t=1}\). By repeating the above for every time moment \(\mathrm{t}\), it can be noticed that both flip-flops are equivalent. For the general case, we formulated Theorem 1. Figure 4: Equivalence of flip-flops: (**a**) simple; (**b**) hidden; (**c**) cofactored form. **Theorem 1**. : _Two synchronous flip-flops \(D_{k}\) and \(D_{l}\) are described by Shannon expansion:_  
\[ \begin{array}{l}D_{k}=Q_{k}\ f_{1k}+\overline{Q_{k}}\ f_{0k}\\ D_{l}=Q_{l}\ f_{1l}+\overline{Q_{l}}\ f_{0l}\end{array}  \tag{4}\]  
_where \(f_{1k}=f(Q_{1},\ldots,\ Q_{k}=1,\ \ldots,Q_{n},\ x_{1},\ldots,x_{m})\) and \(f_{0k}=f(Q_{1},\ldots,\ Q_{k}=0\,\ldots,\ Q_{n},\ x_{1},\ldots,x_{m})\) are equivalent if_  
_(a) cofactor functions are equivalent, \(f_{1k}=f_{1l}\) and \(f_{0k}=f_{0l}\),_  
_(b) initial values for both flip-flops are identical \(Q_{k}^{l=0}=Q_{l}^{l=0}\)._  
Proof of Theorem 1.: We show that for any time moment \(t\), if \(Q_{k}^{t}=Q_{l}^{t}\) holds, then it implies that \(Q_{k}^{t+1}=Q_{l}^{t+1}\). Since the operation of D flip-flops can be described by \(Q_{k}^{t+1}=D_{k}^{t}\) and \(Q_{l}^{t+1}=D_{l}^{t}\), Equation (4) can be rewritten in the following form:  
\[ \begin{array}{l}Q_{k}^{t+1}=Q_{k}^{t}\ f_{1k}+\overline{Q_{k}^{t}}\ f_{0k}\\ Q_{l}^{t+1}=Q_{l}^{t}\ f_{1l}\ +\overline{Q_{l}^{t}}\ f_{0l}\end{array}  \tag{5}\]  
Inserting condition (a) \(f_{1k}=f_{1l}\) and \(f_{0k}=f_{0l}\) into Equation (5), we obtain the following:  
\[ \begin{array}{l}Q_{k}^{t+1}=Q_{k}^{t}\ f_{1l}+\overline{Q_{k}^{t}}\ f_{0l}\\ Q_{l}^{t+1}=Q_{l}^{t}\ f_{1l}\ +\overline{Q_{l}^{t}}\ f_{0l}\end{array}  \tag{6}\]  
If \(Q_{k}^{t}=Q_{l}^{t}\), we obtain \(Q_{k}^{t+1}=Q_{l}^{t}\ f_{1l}+\overline{Q_{l}^{t}}\ f_{0l}=Q_{l}^{t+1}\). Hence, if at time t = 0 (b) \(Q_{k}^{t=0}=Q_{l}^{t=0}\) holds, it implies that \(Q_{k}^{t=1}=Q_{l}^{t=1}\). Similarly, if \(Q_{k}^{t=1}=Q_{l}^{t=1}\) holds, it implies that \(Q_{k}^{t=2}=Q_{l}^{t=2}\), and so on, for every time moment \(t\). \(\square\)  
Cofactors of a function can be obtained in a very efficient way from the BDD. For the flip-flops considered in our example, the BDD cofactors of \(D_{3}\) (versus \(Q_{3}\)) and \(D_{4}\) (versus \(Q_{4}\)) are shown in Figure 3(b) (corresponding schema in Figure 4c). If the order of variables in a BDD diagram is arranged in such a way that the root of the diagram is associated with the variable \(Q\), then the child nodes constitute cofactors. To summarize, searching for equal cofactors can be conducted relatively easily with the BDD, effectively reducing the number of flip-flops. Once the sequential part of the system is optimized, the decomposition of logic functions is executed. Such a process is a perfect supplement for the redundant sequential logic optimization and may strongly influence the utilized resources of an FPGA.