# A Low-Phase-Noise 8 GHz Linear-Band Sub-Millimeter-Wave Phase-Locked Loop in 22 nm FD-SOI CMOS
## 2 System Architecture and Circuit Design
### Other PLL Blocks  
Other blocks include the phase/frequency detector (PFD), the charge pump (CP), and the loop filter (LF). The output of the frequency divider chain is applied at the DIV and \(\overline{DIV}\) inputs and the 5 GHz reference at REF and \(\overline{REF}\) inputs of the PFD. As represented in Figure 4a, the three-state PFD is composed of two D-latches and an AND gate. When the reference signal is \"high\" while the divider signal is \"low\", the outputs UP-\(\overline{UP}\) and DOWN-\(\overline{DOWN}\) of the D-flip-flops (DFF) are forced to be \"high\" and \"low\", respectively. This causes the VCO to increase its output frequency, matching the reference frequency after subsequent frequency divisions. Similarly, a \"low\" state of the reference signal will induce a decrease in the VCO/divider output in order to match the reference frequency. The \"zero\" state is created when the reference and divider signals are equal in phase and frequency, leading to a reset of the DFFs through the AND gate. Meanwhile, when the two input signals of the PFD converge, a fast reset path causes the DFFs to enter state \"zero\" before any charge is transmitted to the succeeding CP stage. This is called the \"dead-zone\" and creates spurs in the PLL output. Therefore, the minimum pulse width of the PFD is limited to the reset path delay [14]. The dead-zone may be reduced by using inverter-generated delay blocks following the AND gate [15] or by employing a NOR gate in place of the AND gate [16]. In this work, an AND gate is formed by using a symmetric NAND gate followed by an inverter, allowing the reduction of the dead-zone and resulting in a wideband PFD. The PFD outputs are applied to a differential charge pump (shown in Figure 4b). The transistors M1-M4 are driven differentially by UP-UPn and DOWN-DOWNn signals from the PFD. Therefore, the two I0 current sources from GND and VDD will be steered in transistors M1-M4 and the differential loop filter (LF) based on R1, C1 and R2, C2. The resistors R2 connected to VCM will set the common-mode voltage at the outputs of the CP to VCM. The differential architecture has several advantages, including an insensitivity to the PMOS and NMOS switch mismatches and improved speed and voltage range [17].  
Moreover, a three-stage common-source power amplifier (PA) followed by an on-chip bowtie antenna was designed to amplify the PLL output in a transmitter-antenna configuration (as seen in Figure 1). The schematic of the PA is depicted in Figure 4c. The first and second stages are composed of the duplicate transistor M1 as well as the coplanar waveguides TL2 and TL3, respectively providing voltage amplification. The last stage is formed by M2 and TL3 and performs power amplification. interstage capacitors C3 and C4 are used to suppress the DC signal from one stage to the other. The size of M2 is twice that of M1 to handle the output current of 10 mA. A common bias current of 5 mA is used to bias the class A amplifier with a DC supply voltage VDD of 1.5 V through a feeding network formed by the transistor Mb and the resistor R1. As a result, a total DC power consumption of 30 mW is generated. The high-pass network consisting of capacitors C1 and C2 and the coplanar waveguide TL1 was designed to match the input of the PA to 50 \(\Omega\). The gain of the PA ranges from 6.5 dB to 10 dB within the 159.5-167.5 GHz band. Meanwhile, the wideband bowtie antenna has a bandwidth of 32 GHz ranging from 140 GHz to 172 GHz, with a peak gain and reflection coefficient of 7 dBi and \(-\)25 dB at 160 GHz. The designed PLL is applied in a millimeter-wave transmitter to facilitate the performance measurement procedure.