# An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios
## 2 Background and Related Work
While a primary 4G/LTE system operates, secondary 5G systems exploit spectrum holes via DSA and use different waveforms (e.g., OFDM, GFDM, and UFMC) for transmission without affecting primary user communications. The first flexible hardware platform designed for multiple 5G waveform scenarios was proposed in [19]. It is a complete transmitter/receiver platform that comprises hardware and software modules for digital baseband processing, RF boards, and high-level software applications for system control and information display purposes. Baseband processing on the transmitter side is implemented ona Xilinx Zynq xc7z020 device that includes an FPGA and an embedded ARM processor on the same chip. Three 5G waveform candidates are supported--OFDM, FBMC, and UFMC--and a baseband modulator for each waveform is implemented. The high-level software application selects the type of waveform and the baseband parameters to be used. Then, a DMA controller fetches data stored on the external DDR memory and sends it to the selected waveform modulator. In turn, the modulator performs baseband processing and forwards the results to an RF front-end extension board. At the baseband processing level, the flexibility in [19] comes from multiplexing between the three baseband modulators: the static multi-mode approach. Thus, although the three modulators are always present in the system, only one can be used at the same time. This is not efficient from a resource utilization perspective and not suitable for non-contiguous CA scenarios. For each waveform, two numerologies are supported by defining the value of some baseband parameters. Therefore, the modulators have to be designed for the most demanding scenario. This static multi-mode approach is also not upgradeable. If new waveforms or numerologies have to be supported in the future, the FPGA baseband infrastructure has to be redesigned. Moreover, this approach is not scalable, as the continuing addition of new modes of operation may force design migration to a larger device, with an associated overhead in terms of cost and power consumption. OFDM popularity over the last two generations of cellular communications led to numerous works on FPGA-based implementations for OFDM baseband modulators (e.g., [20; 21]. We have also contributed with a dynamically-reconfigurable OFDM modulator for LTE downlink transmission employing DPR [22] and a parallel-pipelined architecture OFDM modulator that exploits DFS to support scalable numerologies for 5G communications [23]. Regarding FBMC and UFMC, there are few published works on hardware implementations for baseband modulators. [PERSON] et al. [24] and [PERSON] et al. [25] presented FPGA-based implementations for polyphase network FBMC modulators. Alternatively, we showed that, despite its higher computational complexity, the Frequency Spreading (FS) approach is a convenient scheme for FPGA-based FBMC designs and proposed a flexible and resource-efficient variant of an FS-FBMC baseband modulator [26]. For UFMC, [PERSON], et al. [27] presented an FPGA-based implementation for a baseband modulator that exploits the separation between sub-band and subcarrier processing and the decomposition of the UFMC symbol into prefix, core, and suffix parts. With this technique, the authors claim a significant complexity reduction compared to a baseline UFMC implementation, which can be very important when the number of allocated sub-bands for UFMC transmission increases. That work followed the numerology for LTE 5 MHz channelization and presented resource utilization results for post-synthesis (before place-and-route) design only. In turn, [PERSON] et al. [28] followed the algorithm proposed in [29] and presented an FPGA-based UFMC modulator for LTE 10 MHz channelization. Each UFMC sub-band is not processed in parallel, but using a ping-pong buffering/memory strategy, which requires clock frequencies above 300 MHz to achieve acceptable processing latencies.