## 2 Related Work
### Classifications by CPU Architecture
The selected devices were reported within the state-of-the-art applications involving real-time image processing with hardware-constrained embedded vision systems. For each device, Tables 3 and 4 address the following hardware features: CPU SoC, flash memory, Static Random Access Memory (SRAM), the CPU clock frequency, and principal applications. The CPU with RISC-V architecture is optimized for AIOT applications, including implementing real-time image processing tasks and TinyML algorithms. Conceptually, TinyML is a trend focused on executing classification and inferencing tasks through machine learning algorithms based on techniques such as support vector machine and neural networks in embedded systems with hardware-constrained [15; 44; 45]. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline \multirow{2}{*}{**Device Name**} & **Processing** & \multirow{2}{*}{**Flash**} & \multirow{2}{*}{**SRAM**} & **CPU Clock Frequency** & \multirow{2}{*}{**CV Applications**} \\  & **Hardware System** & & & & \\  & **on a Chip (SoC)** & & & & \\ \hline \multirow{3}{*}{\begin{tabular}{c} Freenove ESP32- \\ S3-WROOM CAM \\ Board \\ \end{tabular} } & 32-bit dual core & & & & Robotics, \\  & XTensa LX7 & 8 MB & 8 MB & 2 \(\times\) 240 MHz & Embedded Vision, \\  & RTSC-V & & & & Security Systems, \\  & & & & & AI App \\ \hline \multirow{3}{*}{\begin{tabular}{c} ESP32 S3-EYE \\ \end{tabular} } & 32-bit dual core & & & & Robotics, \\  & XTensa LX7 & 8 MB & 8 MB Octal & 2 \(\times\) 240 MHz & Embedded Vision, \\  & RISC-V & & & & Security Systems, \\  & & & & AI App \\ \hline \multirow{3}{*}{\begin{tabular}{c} Seeed Studio XIAO \\ ESP32S3 Sense \\ \end{tabular} } & 32-bit dual core & & & & Robotics, \\  & XTensa LX7 & 8 MB & 8 MB Octal & 2 \(\times\) 240 MHz & Embedded Vision, \\  & RISC-V & & & & Security Systems, \\  & & & & AI App \\ \hline \multirow{3}{*}{\
\begin{tabular}{c} PyAI-K210 \\ RISC- \\ \end{tabular} } & 64-bit dual-core & & & & Robotics, \\  & Kendryte K210 & 1 MB & 512 KB & 2 \(\times\) 486 MHz & Embedded Vision, \\  & RISC-V & & & & IA App \\ \hline \multirow{3}{*}{
\begin{tabular}{c} Speed MADX-II \\ M2 dock \\ \end{tabular} } & 64-bit single-core & 16 MB SPI Nor & & & Robotics, \\  & Cortex-M7 RISC-V & Flash & 8 MB SRAM & 800 MHz & Embedded Vision, \\  & & & & IA App \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Embedded systems classification for RISC-V architecture. The RISC-V architecture allows the deployment of neural-network-optimized models for predicting and inferring tasks in control and image classification systems. In robotics applications, these tasks are useful for tracking, avoiding, and detecting objects. On the other hand, the CPU with Cortex-M that incorporates RISC-V architecture allows a CPU clock frequency of over 250 MHz, which could increase the system's performance; however, this configuration increases power consumption and cost. The TinyML trend supported by classical ML theory has allowed a significant advance within the field of mobile robotics applications by making it possible for embedded systems that govern the operation of a robot to be capable of performing computer vision tasks, such as real-time image processing, as well as the control of robot actuators. In this sense, one of the most outstanding achievements since 2020 [15; 46; 47] is the implementation of a general-purpose artificial neural network (ANN) to achieve patterns classification in real-time image processing, linear regression, or value predictions expected from sample sensor signals, as well as intelligent PID controllers implemented on microcontrollers [48].