# A 4.1 W/mm\({}^{2}\) Hybrid Inductive/Capacitive Converter for 2-140 mA-DVS Load under Inductor +
## 2 Architecture
### Inductive Converter  
As discussed earlier, the capacitive converter transitions to the inductive converter when the output voltage is higher than 0.55 V up to 0.9 V. In the reverse direction the inductive converter transitions to the capacitive converter when the output voltage falls below 0.5 V. The clocks to the digital controller are enabled and the switching action resumes. The inductive converter consists of the core converter unit and the controller which regulates the output voltage to the desired value as shown in Figure 14. The digital PWM controller utilizes a time-to-digital based analog-to-digital converter to digitize the error between the reference voltage and the output voltage. The error is then digitally integrated in an accumulator, the output of which forms the code for generation of the appropriate duty-cycle pulses in the digital PWM generator. Figure 9 shows the layout details for the 2 nH inductor that is realized with the top two metallic layers so that the digital circuits can be realized underneath. The inductor is roughly 524 \(\upmu\)m \(\times\) 524 \(\upmu\)m in size. For a fully-integrated implementation of a buck converter, like the one shown in Figure 10, the physical size of the passives dominate the area occupied. On the other hand, the output ripple voltage is given by Equation (4) [3] where \(L\) and \(C\) are the inductance and filter capacitance, \(D\) is the duty cycle for generating the required output voltage and \(f_{sw}\) is the switching frequency of the buck converter. \[\Delta V=\frac{D(1-D)V_{DD}}{8 LCf_{sw}^{2}} \tag{4}\]  
Figure 9: Layout details of the 2-metal 2 nH inductor. Reducing the size of the passive filter components forces us to increase the switching frequency \(f_{sw}\) so as to meet the output ripple voltage specifications. To understand this tradeoff carefully, let us consider the different components of input power \(P_{in}\) are given by Equation (5), where \(P_{out}\) is the power supplied to the load, \(P_{sw}\) (given by Equation (6)) is the power consumed by switching the power device and its respective buffers, \(P_{cond,PMOS}\) is the conduction loss in the PMOS device and \(P_{otherloss}\) is the power loss in the rest of the circuit. The conduction loss for the NMOS device is treated separately as it does not carry the load current [3]. \[P_{in}=P_{out}+P_{sw}+P_{cond,PMOS}+P_{otherloss} \tag{5}\]  
\[P_{sw}=C_{gate}V_{DD}^{2}f_{sw} \tag{6}\]  
Here, \(C_{gate}\) is the total capacitance switched. The conductive loss in the PMOS device can be approximated by Equation (7), where \(\mu_{p}\) is the PMOS hole mobility, \(W_{p}\) is the width of the PMOS power device, \(V_{Tp}\) is the threshold voltage of the PMOS device and \(I_{PMOS}\) is the RMS current in the PMOS power device. The mean square value, \(I_{PMOS}^{2}\), is given by \(I_{PMOS}^{2}=D^{2}I_{load}{}^{2}+I_{PMOS,rms}^{2}\) where \(I_{PMOS,rms}\) is the RMS value of \(I_{PMOS,ripple}\)-\(I_{PMOS,ripple}\), in turn is given by Equation (8). \[P_{cond,PMOS}=\frac{I_{PMOS}^{2}}{\mu_{p}C_{ox}^{W_{p}}L}(V_{DD}-V_{Tp}) \tag{7}\]  
\[I_{PMOS,ripple}=-\frac{D(1-D)V_{DD}}{2 Lf_{sw}}+(t-nT)\frac{(1-D)V_{DD}}{L} \tag{8}\]  
The \(P_{otherloss}\) (shown in Equation (9)) includes the conductive loss in the NMOS power device (Equation (10)), the power lost in the inductor series resistance (Equation (11)) and the short circuit current (Equation (12)). \[P_{otherloss}=P_{cond,NMOS}+P_{cond,L}+P_{sc} \tag{9}\]  
where  
\[P_{cond,NMOS}=\frac{I_{NMOS}^{2}}{\mu_{n}C_{ox}^{W_{n}}(V_{DD}-V_{Tn})} \tag{10}\]  
Figure 10: Complete inductive convertor including control loop. AVDD is the input voltage.