## 6 CT Pre-Processing Core Implementation and Integration
### IP Block Design  
For implementing the CT pre-processing core on the Xilinx board, we used Vitis(tm) HLS, which is the Xilinx high-level synthesis tool that allows C, C++, and OpenCL(tm) functions to become hardwired onto the device logic fabric and RAM/DSP blocks. The HSL implementation results in a register transfer level (RTL) block design, also called IP block design, which can be implemented on FPGA. Moreover, by describing our hardware components with Vitis(tm) HLS, we do not have to describe the arithmetic hardware components at the logic gate level. In fact, Vitis(tm) HLS utilizes optimized arithmetic hardware components, provided by Xilinx as a library.  
The CT pre-processing core is described with C++ source code. Each stage of the dataflow architecture is encapsulated in a C++ function. The arguments of each function describe the input/output ports of the stage. In synthesis, to obtain the pipelined dataflow architecture, we use the directives \"#pragma HLS DATAFLOW\" and \"#pragma HLS PIPELINE dataflow\" provided by Vitis(tm) HLS. These directives allow to implement C++ loops and C++ functions as a pipelined dataflow RTL block design.  
Externally, the CT pre-processing core communicates via AXI4-STREAM interfaces. These are defined by using the data format \"hls::axis\" and the directive \"#pragma HLS INTERFACE axis\", which can be only used for the external interfaces of the core. As a result, for interconnecting the three internal stages of the CT pre-processing with a stream interface, the \"hls::stream\" template type and the directive \"#pragma HLS STREAM variable=_data format_\" are used.  
Furthermore, we define three primitive data formats, which allow to parameterize the core for different data formats in the three main stages of the CT pre-processing core:  
* Detector format: This format refers to the raw-sensor data that are generated by the DMS and collected by the data-flow module in the DAS. It defines the input data format of the _sensor-data conversion stage_.
* Image-processing format: This format refers to the desired data format for the pre-processing steps. It defines the output data format of the _sensor-data conversion stage_, the data format for the _image-processing stage_, and the input data format of the _reconstruction conversion stage_.
* Reconstruction format: This format refers to the reconstruction representation. It defines the output data format of the _reconstruction conversion stage_.  
The designer in Vitis(tm) HLS defines the primitive data formats as the C++ class at synthesis time.  
For DSE purposes, we configure the CT processing core with different encoding of the floating-point and fixed-point representations. For implementing these representations with the Xilinx arithmetic processing units, we use the provided libraries hls_math, hls_half, and ap_fixed. These allow us to use _double, float, single, half and ap_fixed<W,I>_ formats. In fixed format, W refers to the data width and I the integer part of the real value number. In Section 9, the implementation results of the different configurations used in the DSE are discussed.