## 1 Introduction  
The conditions required to accommodate the increasing bandwidth densities in 5G+, hyperscale data centers and high-performance computer (HPC) environments are becoming more extreme. Given the requirement that larger numbers of optical transceiver I/O ports are moved closer to the signal source chip in the system (e.g., ASIC or FPGA) in embedded or co-packaged optical assemblies, it follows that transceivers will need to be packed more tightly into very confined spaces. Consequently, transceivers will need to operate at higher ambient temperatures than those to which commercial transceivers have historically been subjected, in many cases exceeding 105 \({}^{\circ}\)C as we will outline later on. In order to be deployed in these hyperscale environments, optical transceivers will need to provide higher aggregate bandwidths, a reduced footprint and higher reliability at operating temperatures exceeding 100 \({}^{\circ}\)C. The design and performance of a silicon photonic micro-transceiver are presented, which can operate under high ambient temperature regimes exceeding 105 \({}^{\circ}\)C. The quad (4 Tx + 4 Rx) silicon photonic micro-transceiver \"IOCore\" incorporates a 1310 nm Fabry-Perot Quantum Dot laser, the output of which is modulated at data rates of 25, 32 and 50 Gbps per lane. The compact 5 \(\times\) 5 mm micro-transceiver chip features a multimode optical coupling interface and an optical redundancy circuit. Together, these enable robust, low-cost operation and connectivity at high temperatures and increase reliability by over an order of magnitude compared to non-redundant integrated laser schemes. The first generation of 100G silicon photonics micro-transceiver comprised four bidirectional channels operating at 25 Gbps [1]. AIO Core collaborated with partners of the European H2020 COSMICC project [2] to demonstrate its first generation of silicon photonics micro-transceivers on mezzanine test cards [3], which have recently been standardized by the IEC [4]. The COSMICC hyperscale optical interconnect ecosystem demonstration platform \"Aurora\" was exhibited at ECOC 2019 in Dublin in September 2019 (Figure 1). Silicon photonics-based transceivers were initially developed for data center interconnects (DCIs), where the high requisite volumes of optical transceivers enabled critical investment in new technologies. Silicon photonics has evolved over the past five years from a high-cost margin telecom technology to a commoditized datacom transceiver technology capable of transmitting bit rates of hundreds of Gbps at transmission costs of an ever decreasing fraction of a US dollar per Gbps and a power consumption of less than 15 picoloules per bit. A relevant example is the specification recently published by the Co-Packaged Optics Collaboration [8] of a 3.2 Tbit/s co-packaged transceiver module [9]. The advent of 5G has given rise to the requirement for high data rates in the fronthaul segment [10], and this trend is expected to increase with the introduction of advanced antenna systems (AAS) [11] and radio transmission in the millimeter wave range [12]. However, the interconnection speed remains lower in radio communications than in DCI: 100 Gbps links are being introduced in the current generation, with the requirement expected to increase to 400 Gbps within the next few years. A possible scenario is depicted in Figure 2.  
Two ASICs (depicted in blue in Figure 2)--for example, the ASIC used for digital baseband processing functions--are connected to each of four 400 Gbps optical modules through four 50 Gbps electrical lanes. Each optical module receives inputs from both ASICs in a dual star redundant configuration for protection and computation offload purposes. These four optical modules connect to another four modules across an optical link, the length of which can range from a few centimeters for intra-board optical interconnects to hundreds of meters for split radio equipment.