## 1 Introduction  
Parallelization of voltage source converters is becoming a widely used practice [1; 2; 3; 4; 5]. With the constantly increasing power systems size [6], parallelization becomes a landmark for feeding power systems because like the multi-levels structures, it enables the use of smaller power devices with smaller power losses, reduces the total harmonic distortion [2], and achieves higher overall efficiency because the switching frequency can be increased [7]. Other advantages are the reliability of arbitrary redundancy [1; 4; 8; 9; 10] and the standardization of power devices, because the power systems specifications are met by the number of parallel units and not by the devices themselves. In the literature, a lot of papers propose studies about parallelization of power converters. Parallel operation is used in the renewable energy conversion field, in particular [1] proposes a way to connect wind turbines to the grid by using AC-DC-AC topology with parallel operation of both rectifiers and inverters. In [11], the authors present a parallel DC-AC switched mode power converter that connects a small power generator (<1 MW) to the grid, using two smaller units connected in parallel through master-slave logic. In the automotive field, ref. [3] proposes an electric vehicle fast charger based on two parallel three-level DC-DC converters, where the parallelization is achieved through an integrated inductor at each converter output in order to minimize the circulating current and reduce the output current ripple. In case of voltage source converters (VSCs), there are different ways to deploy parallel operation in order to avoid circulating current among units, which causes undesired voltage drops, power losses and stress on the common DC link (in case of parallel input topology). This reduction can be achieved using particular modulations: the authors in [8; 12] use SVPWM (Space Vector PWM). Other researchers in [7] propose a cascade null vector control system together with a three-phase Harmonic Elimination PWM (HEPWM) modulator in order to reduce the zero sequence circulating current. Other techniques [13; 14; 15; 16; 17; 18; 19] perform synchronization at a fundamental frequency by using two different approaches: galvanic isolation using multiple winding line frequency transformers or including an impedance at the output of each VSC. This can be achieved either by using a single phase harmonic filter inductor or using magnetic coupled inductors between corresponding phases of each parallel VSC. Authors in [14] propose criteria to evaluate frequency line inductors at VSCs output in three study cases: single unit connected to the bus, two units with different DC link and two units that share the same DC link. The latter case results in significant circulating currents between units, that can be mitigated by inserting a high impedance path with common mode coils placed between corresponding phases of different VSCs. In [19], a total flux minimization control method based on Discontinuous PWM (DPWM) is presented in order to reduce the coupled inductors size. All of the works reviewed above use some filters, usually inductors, to keep any recirculating currents under control. In [20], the authors propose a novel parallelizing method acting directly at the modulation frequency level, relying only on the natural parasitic inductance and resistance of the wiring among parallel units. This would allow the complete removal of any filter, so that a complete parallel converter would be truly modular, composed only of the sum of the parallelized converters. The proposed synchronization method is based on a sequence of two stages: an initial coarse synchronization supported by a slow communication interface like CAN bus, followed by a high speed closed-loop control on each converter that compensates for slightly different clock frequencies and residual delay errors left by the initial synchronization.