## 4 Separated Phase-Current Control Using IBDGs
The dead band of the voltage regulator is in a range of 0.9 to 1.1 pu, which is the acceptable voltage limit according to EN50160 and ESKASAA18 [17]. When \(V_{d}\) is out of the dead band, the error between \(V_{d}\) and the permissible voltage limit is sent to the PI controller. The output of the PI controller is set as \(I^{\prime}_{q-ref}\). During no fault occurrence, the PF should be varied within a given range defined by the grid code. The inverter must have enough leverage for a reactive current (\(I_{q}\)), allowing for a minimum PF that complies with the grid code. Thus, the final active current reference (\(I_{d-ref}\)) is constrained by the current limiter, defined as  
\[I_{d-ref}\leq\mathrm{PF}\cdot I_{max}, \tag{8}\]  
where \(I_{max}\) is the maximum allowable current level of the inverter. To satisfy the PF requirement, the final reactive current reference (\(I_{q-ref}\)) is limited by the PF limiter, defined as  
Figure 3: Control diagram of the separated phase–current control for phase \(a\) (References [19], [20], and [26]). \[ \begin{array}{l}I_{q-ref}\leq tan(cos^{-1}\text{PF})\cdot I_{d-ref}\ ;\ \ \ \ \text{ PF}>0\\ I_{q-ref}\geq tan(cos^{-1}\text{PF})\cdot I_{d-ref}\ ;\ \ \ \ \ \text{ PF}<0.\end{array}  \tag{9}\]  
During the ground fault, the grid overvoltage probably occurs in the nonfaulty phase due to the system grounding [27]. It can also be compensated for through deployment of the voltage regulator. For example, grid overvoltage occurs in phase \(a\). If the ground fault occurring in phases \(b\) and \(c\) causes the grid overvoltage of phase \(a\), the FD module contained in the separated phase-current control of phases \(b\) and \(c\) sends the fault signal to the current reference generator of phase \(a\). At this moment, the voltage regulation is the top priority. \(I_{q-ref}\) is not limited by Equation (9), i.e., \(I_{q-ref}=I^{\prime}_{q-ref}\). Even though an overloaded distribution transformer caused by a lower PF may happen, this does not affect the lifetime of the distribution transformer. This is because the distribution transformer can normally sustain the overloading condition for half an hour [28]. However, the phase current may be greater than the current rating of the power semiconductor. To prevent damage of the inverter, the \(I_{d-ref}\) must be restricted by a current limiter, defined as  
\[I_{d-ref}\leq\sqrt{(I_{max})^{2}-(I_{q-ref})^{2}}. \tag{10}\]  
If the grid overvoltage of phase \(a\) is not caused by the ground fault occurring in phases \(b\) and \(c\), there is no fault signal from the FD module contained in the separated phase-current control of phases \(b\) and \(c\). The overvoltage that is not related to the ground fault may be longer than half an hour. To forbid long-time overload of the distribution transformer caused by a lower PF, both \(I_{d-ref}\) and \(I_{q-ref}\) are governed by Equations (8) and (9). When both \(I_{d-ref}\) and \(I_{q-ref}\) are achieved, they are transformed into the phase current reference (\(I_{x-ref}\)) by  
\[I_{x-ref}=\sqrt{(I_{d-ref})^{2}+(I_{q-ref})^{2}}\cdot sin(\theta_{x}+tan^{-1} \frac{I_{q-ref}}{I_{d-ref}}), \tag{11}\]  
where subscript \(x\) represents phases \(a\), \(b\), and \(c\). The phase voltage (\(V_{x}\)) is sent to the PLL control to calculate the voltage phase angle (\(\theta_{x}\)). Although the downstream grid voltage exceeds the acceptable voltage limit, the reactive current of the upstream IBDG may be low, because the difference between \(V_{d}\) of the upstream IBDG and the acceptable voltage limit used for computing the reactive current reference is not significant. The upstream IBDG contributes to regulating the downstream grid voltage by using the \(V_{d}\) of the downstream IBDG as the input of the voltage regulator of the upstream IBDG. The voltage selector switches the input of the voltage regulator between the \(V_{d}\) of the upstream IBDG and the \(V_{d}\) of the downstream IBDG. A control diagram of the voltage selector is shown in Figure 4.  
Figure 4: Control diagram of the voltage selector.