## 1 Introduction and Problem Formulation
The technique described above is effective (the translated system reflects the model) and relatively easy to perform (the transformation can be conducted automatically), thus it seems to be the most popular nowadays. However, there is an important drawback that refers to the relatively high utilization of hardware resources of an FPGA. As already mentioned, an FPGA consists of LUTs and flip-flops (FFs). Although a single LUT allows for the implementation of any logic function, it is limited to a relatively small number of variables (usually 5-6). This means that larger functions ought to be divided (decomposed) into subfunctions with a small number of variables [45; 46; 47; 48]. Obviously, such a decomposition heavily influences the number of logic blocks used to implement the modeled system. Therefore, the final implementation of the Petri net-based design may drastically increase. Let us now briefly overview the most popular logical function decomposition techniques of systems implemented within an FPGA. The first decomposition algorithms were developed in the 1990s and they were initially oriented on the optimization of the gate structures (with further adoption to FPGAs). These methods include the _MIS-PGA_, _ASYL_, _Chortle_, and _Xmap_ algorithms. Their essence was to optimize the multi-level implementation of logical functions. Later, as a result of the development of decomposition methods, tools such as _Demain_[49], _FGsyn_[50], and _Decomp_[51] were developed. Those techniques are based on the classical decomposition model [52], and they provide efficient solutions (in terms of the number of logic blocks or the number of layers), but their main drawback is high computational complexity. Therefore, the optimization possibilities of complex circuits were highly limited, since the long synthesis time made them difficult to use in practical approaches. In the 2000s, plenty of academic tools appeared, together with the representation of logic functions in the form of And-Inverter Graphs (AIGs). Such a graph can be found, for example, in the _ABC_[53] and _DAOmap_[54] systems. Meanwhile, the re-synthesis techniques were developed [55; 56], benefiting systems such as the Delay-Driven BDD (_DDBDD_) [57] and BDS-PGA 2.0 [58], which use Binary Decision Diagrams (BDDs) to represent logical functions. Furthermore, development of technology and the expansion of logic blocks in the programmable circuits resulted in the appearance of tools that permit the configuration of logic blocks, e.g., _ALMmap_[59]. Getting back to the current times, there is no doubt about the importance of decomposition in logical synthesis. Such a process is a subject of extensive research in the context of synthesis dedicated to FPGAs and Programmable Array Logic (PAL)-based systems [60]. Decomposition is also used in the synthesis process oriented to Complex Programmable Logic Devices (CPLDs) [61; 62; 63]. In logical synthesis algorithms, the way in which a logical function is represented is especially important. Functions can be represented in the form of a table description [52], cube description, and graph description. Nevertheless, methods that utilize BDDs [57; 64] are of great interest. The achievements of [PERSON] and [PERSON] laid the foundations for subsequent types of decomposition, but memory-inefficient decomposition tables (_Karn taught_ tables) were used to represent the logical functions. Looking from the terms of memory consumption, a much better solution is the BDD representation [57; 58; 65]. The description of logical functions in the form of BDD leads to the significant reduction in computer memory and better speed performance of operations on these functions. Moreover, a dozen standard libraries for manipulating BDDs are available. To be precise, the reduced and ordered form of BDD (ROBDD) is used. These advantages have led to the development of tools such as BDS or DDBDD and MultiDec [66] that lead to effective solutions. Good solutions are also provided by mentioned tools such as DAOmap or ABC [67], which use AIGs.