# Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices
## 4 Thermal Management of PICs  
Photonic elements, such as integrated semiconductor optical amplifiers (SOAs) and micro-ring resonators, exhibit a strong temperature-dependence that is many times greater than that of CMOS electronics. A temperature variation of 20 \({}^{\circ}\)C is often sufficient for a PIC to drift out of its operational profile [55; 56]. Global thermal stabilization of the PIC in a photonic device, usually with a thermoelectric cooler (TEC), is essential for prototypes that need to be tested in the field, where seasonal temperature swings of \(\pm\)10 \({}^{\circ}\)C are common. The added global stability from the TEC allows for more efficient and better reproducibility in the local temperature-tuning of individual photonic elements (e.g., micro-ring resonators, thermo-optic phase-shifters, etc.) on the PIC. Increasing the coefficient of performance (CoP) of the TEC in these modules is an important consideration for lowering the operational cost of deployed photonics. Figure 13: Analysis of the copper-pillar-bumps (CPBs) for vertical integration; **(a,b)** SEM images of the ‘top’ and ‘bottom’ CPBs that form the vertical interconnect between the PIC and EIC before solder-reflow bonding. The asymmetric pairing of the CPBs helps to reduce slippage during the flip-chip alignment; **(c)** Side-view image of the PIC + EIC assembly after a ‘grind and polish’ has been used to expose approximately 70 CPBs; **(d,e)** X-ray microscope images of the PIC+EIC assembly, allowing the operator to ‘see through’ the EIC, and identify the position of the CPBs. This diagnostic allows the operator to non-destructively identify missing or grossly malformed CPBs. Figure 14 shows a schematic of the typical 'thermal stack' for a module with a PIC and integrated EIC. The electrical power is delivered to the EIC, where it evolves into thermal power (\(H=dQ/dt\)) via Joule-heating, and then flows into the PIC through the SBB or CPB interconnect layer. From there, the heat conducts into a heat-spreading plate, and reaches the 'cold side' of the TEC, before reaching the baseplate of the module, where it is lost to the ambient environment, either through passive convection/conduction, or 'rack-based' forced-convection cooling. The effect of unchecked Joule-heating can be illustrated by powering-up the EIC while the TEC is powered-down, as shown in Figure 15. Here, 1.1 W of power is applied to the EIC in a Si photonic optical network unit (ONU), developed for the the EU-FP7 'FABULOUS' project [57], which results in a temperature increase of 34 \({}^{\circ}\)C and 20 \({}^{\circ}\)C for EIC and PIC, respectively. These measurements were made using a thermal microscope, which allows for accurate, non-contact temperature measurements, both of the PIC (100 \(\upmu\)m-scale) and the full photonic module (10 cm-scale). These dynamic temperature measurements provide quantitative information on both the heat-conduction and heat-capacity of the thermal stack. Broadly speaking, the 'kinks' in these dynamic measurements correspond to the time taken for the heat to 'fill' the different blocks of material in the stack, though proper modelling and data-fitting is needed to fully extract the quantitative details. In contrast, the steady-state temperature difference between the EIC and PIC (\(\Delta\)T = 13.8 \({}^{\circ}\)C) provides a very direct measure of the thermal resistance (\(R_{T}\)) of the CPB interconnect layer through, \(R_{T}=\Delta\)T/\(H\). The thermal resistance of the full CPB layer is then 12.5 K/W = 13.2 \({}^{\circ}\)C/1.1 W. Given that the interconnect layer consists of 484 individual CPBs, this implies a resistance of 6.1 \(\times\) 10\({}^{3}\) K/W per interconnect. The dynamic and steady-state information from the thermal microscopy measurements can be used to validate current thermal models, and also to show how future designs can be optimized.