## 1 Introduction  
III-V multijunction solar cells have been the most efficient photovoltaic cells by overcoming the detailed balance limit of single-junction solar cells [1, 2, 3, 4, 5]. Recently, six-junction III-V solar cells with three compositionally graded buffers have reached a 1-Sun global efficiency of 39.2% [2]. The monolithtically integrated six-junction solar cell requires high material consumption and long epitaxial growth time for the three metamorphic graded buffers that are approximately -5 um thick in total. Therefore, the high material growth time and cost can be an obstacle for the use of III-V multi-junction solar cells in various terrestrial applications, other than for space and military applications. Water-bonded III-V multi-junction solar cells are another type of high efficiency III-V technology [6, 7, 8]. Four-junction solar cells fabricated by bonding an InGaP/GaAs dual-junction solar cell to an InGaAsP/InGaAs cell showed a record-breaking conversion efficiency of 44.7% under 297-Suns [9]. Although this approach does not require lengthy and material-consuming growth of metamorphic graded buffers, it must consume two expensive III-V wafers, e.g., GaAs and InP wafers, to create one high efficiency multi-junction solar cell. Since the cost of III-V wafer accounts for more than 80% of the total manufacturing cost [10, 11], replacing expensive III-V wafers with cheaper Si wafers could be the first step toward more techno-economic and high efficiency III-V multi-junction solar cells.  
Growth of III-V materials on Si, however, creates several hurdles to overcome, such as large lattice mismatch, polar/non-polar growth, and thermal cracks [12; 13; 14; 15; 16]. The large lattice mismatch issue can be mitigated via dislocation filter layers, thermal cycle annealing, and two-step growth, while the polarity mismatch can be addressed by using an offcut Si wafer [17; 18; 19; 20; 21; 22]. The thermal cracks caused by the difference in thermal expansion coefficients during sample quenching can be avoided by restricting the total III-V layer thickness below \(\sim\)7 \(\upmu\)m at moderately low growth temperatures [23]. Decades of research on III-V growth on Si have enabled production of 18.0% efficient monolithic GaAs solar cells on Si by addressing these issues [24; 25]. However, the possibility of epitaxial lift-off of III-V solar cells grown on Si for wafer-bonded III-V multi-junction solar cells to reduce their manufacturing cost has not been explored.  
Here, we demonstrate, for the first time, a thin-film GaAs solar cell grown on an Si wafer then transferred to a polyimide film via a metal wafer bonding and epitaxial lift-off process. The 2.1 \(\upmu\)m-thick GaAs buffer was grown on a Si wafer to reduce the threading dislocation density to 1.8 \(\times\) 10\({}^{7}\) cm\({}^{-2}\), measured by electron channeling contrast imaging. An inverted GaAs solar cell structure was grown on the GaAs/Si template and revealed a 10.6% 1-Sun efficiency without anti-reflection coating, demonstrating that a wafer bonding and epitaxial lift-off process is compatible with III-V solar cells hetero-epitaxially grown on Si substrates. We believe that an optimized GaAs solar cell structure with InGaP window layer and back-surface field layer will boost the thin film GaAs solar cell performance further.