# A Reconfigurable SRAM CRP PUF with High Reliability and Randomness
## 2 Conventional SRAM CRP PUF
### Existing Issue  
In this structure, achieving a response output from the inherent random process variations depends on balancing the two cross-coupled inverter arrays within the SRAM structure. However, obtaining this balance in the layout design is challenging due to inevitable mismatches [23], particularly in the signal lines connecting the arrays, potentially producing a biased output.  
The challenge input signal serves dual roles, controlling the SRAM power-up and configuring the PUF cell. When a specific challenge input is applied, the specified challenge transistors are turned on to establish connections from the two arrays to the VDD and VSS. Power-up requires activating at least one bit among the n-bit challenges, while the configuration requires the activation of all the n-bit challenges. Disparities in parasitic components can cause the PUF cell to power up and decide its output value before all the challenge transistors are configured, causing incorrect operation during the \"Configuration & Evaluation\".  
The worst-case scenario involves activating the left PMOS challenge transistors before the right ones, and simultaneously activating all the NMOS challenge transistors, as shown in the upper part of Figure 1c. Since there is no timing difference among the NMOS transistors' activations, the two outputs of the PUF cell are solely influenced by the activation times of the PMOS challenge transistors. The voltages, _OUT_B_ and _OUT_, begin to drop from VDD simultaneously due to the current discharged to VSS when the NMOS challenge transistors are turned on. The voltage, _OUT_B_, decreases more slowly than the voltage, _OUT_, with the charge current to VDD since the left PMOS transistors are activated earlier. The instantaneous voltage difference between _OUT_B_ and _OUT_ is amplified by the positive feedback loop in the SRAM structure, and eventually, _OUT_B_ is pulled up to VDD or deviates to 1. Conversely, if the right NMOS challenge transistors are turned on earlier than the left ones, all the PMOS transistors are turned on simultaneously, as shown in the lower part of Figure 1c. The two outputs of the PUF cell are only affected by the turn-on difference of the NMOS challenge transistors. The voltage, _OUT_, will be discharged to VSS before the voltage, _OUT_B_. Similarly, under the effect of a positive feedback loop, _OUT_ is pulled down to VSS or biased towards zero. Thus, the PUF cell output depends on which challenge bit initiates the power-up earlier, rather than depending on the entire n-bit challenge input. Consequently, the PUF cell output becomes independent of the challenge input and produces a fixed response output. This can lead to a potential correlation between the response outputs corresponding to the different challenge inputs.  
Similar to the challenge input, for the input signal _PRE_, asymmetrical connections to the two inverters result in one inverter being turned on earlier when _PRE_ is set to a low level in the \"Evaluation\" mode. If any pre-charge transistor of the inverter array is turned off earlier, its output voltage will start to decrease from VDD before the other output. The positive feedback loop amplifies the instantaneous voltage difference between the two outputs, ultimately driving the output voltage of the inverter array, whose pre-charge transistor is turned off earlier, to zero. This also specifies a predetermined response output value even with distinct challenge inputs.  
Meanwhile, reading the output voltage occurs when the input signal, _WL_, is high, activating the _WL_ transistors to connect the two inverter outputs to the two bit-line outputs and altering the capacitance load value at the two inverter outputs. Turning on _WL_ too early during a conflict between two inverter arrays in the \"Evaluation\" mode can affect the response output, and the mismatch between the two load capacitors can bias the response output to a predetermined value.