## 5 Implementation of the Adaptive SMC and Detailed Circuital Simulations
### Digital Implementation of the Adaptive SMC
For the application example, 10 MHz was selected. Thread 2 starts by capturing the output signals of the CMPSS (\(Reset\) and \(\overline{Set}\)); then, Thread 2 detects if a rising edge on the \(Reset\) signal has been produced by the CMPSS. To take into account that the set \(Set\) signal produced by the CMPSS is inverted (\(\overline{Set}=1-Set\)), Thread 2 detects if a falling edge on the \(\overline{Set}\) signal has been produced. Then, the algorithm changes the MOSFET signals \(u\) and \(\overline{u}\) following the new formulation of the control law previously obtained in Equation (57); if no rising edge on \(Reset\) or falling edge on \(\overline{Set}\) occurs, then \(u\) and \(\overline{u}\) are not changed. The last steps of the algorithm store the states of \(Reset\), \(\overline{Set}\), \(u\), and \(\overline{u}\) for the next iteration. Figure 9 summarizes the digital implementation, where the processes of both threads are synthesized. In addition, the connection of both threads with the analog CMPSS module is illustrated, which occurs inside the microprocessor to generate the MOSFET control signals. Finally, the figure also illustrates the signal processing of the modified control law adopted for this digital implementation. The digital implementation of the SMC reported in Figure 9 was performed in the power electronics simulator PSIM, as follows. Thread 1 and Thread 2 algorithms were implemented using a C-code block for each thread, and the CMPSS was implemented using two comparators. Thread 1 was executed with a sampling frequency equal to 264 kHz (sampling time equal to 3.8 us), while Thread 2 was executed with a sampling frequency equal to 10 MHz (sampling time equal to 0.1 us). The simulation of this digital implementation, reported in Figure 10, evaluates the compensation of a load transient from steady state to battery charge with the maximum current derivative \(\left|\frac{d\bar{u}_{i}}{dt}\right|=70\) A/ms; hence, it reproduces the conditions considered for the  
Figure 9: Flowchart of the digital implementation. simulation of the analog implementation reported in Figure 5. The new simulation results of Figure 10a show two fast current transients between 0 A and 2 A, where the Zeta converter provides the fast current components, as expected. The stable condition \(i_{L1}=i_{L2}\) is also confirmed in this simulation, where \(i_{L1}\) is constrained by \(\Psi_{L1,Set}\) and \(\Psi_{L1,Reset}\), thus ensuring the global stability of the SMC, as given in inequality (54). In addition, the C\({}_{2}\) voltage is constrained to the \(MO_{C2}\) limit, demonstrating that the SMC's digital implementation provides the same performance of the analog implementation. Finally, the switching frequency is always below the maximum design limit (120 kHz), thus requiring the same MOSFETs used for the analog implementation of the SMC. Figure 10b shows a zoom of this simulation, which confirms that the Zeta converter provides the high-frequency component of the load current transient. The zoom also shows the detail of \(\Psi_{L1,Set}\) and \(\Psi_{L1,Reset}\), where the discretization caused by the sampling frequency of Thread 1 (264 kPS) is observed. This simulation also shows the correct operation of the modified formulation of the sliding surface given in inequality (54), and it reports both the \(Set\) and \(Reset\) signals generated by the CMPSS, where \(Set=1-\overline{Set}\). Finally, the control signal \(u\) generated by Thread 2 is also presented, which agrees with the modified control law. In summary, the simulations of both the analog and digital implementations of the SMC confirm the correct operation of the power system and the adaptive SMC for any operation condition. Therefore, the proposed solution can supply the current transients imposed by the load, thus forcing the battery to supply only low-frequency components.