# Efficient Design of Reversible Adder and Multiplier Using Peres Gates
## 6 Functionality Verification
The goal was to highlight the potential advantages of the reversible approach, especially in terms of information preservation and resource utilization. Quantum speedup potential, which is a measure of how much faster a quantum algorithm could perform a specific task compared to its classical counterpart, was explored. The inherent reversibility of the designed circuit using Peres gates positions it favorably for potential quantum speedup in certain algorithms, contributing to the broader understanding of reversible logic in quantum computation. After comparing all the reversible adders using different techniques, we can say that the ripple carry adder is best suited due to the low metric values, as mentioned in Figure 35. The smaller number of inputs, constant and garbage lines, and quantum cost requirement to design an adder circuit are advantageous to using a ripple carry adder. Figure 34: Further performance analysis of different adder configurations using Peres gates. Figure 35: Analysis of Different Adder Configurations using Peres Gates. In Table 2, various reversible logic gates used are Feynman Gate (FG), Toffoli Gate (TG), Fredkin Gate (FRG), Peres Gate (PG), New Gate (NG), TSG Gate (TSG), MKG Gate (MKG), HNG Gate (HNG), and PFAG Gate (PFAG) for comparison on the number of gates used for the construction of different reversible multiplier configurations. The first three multiplier circuits are designed as a part of research in this research article using only Toffoli and Peres gates. The other comparative circuits used other reversible gates available in the literature, as shown in the table. In Figure 36, the comparison of different multiplier circuits is made on the basis of quantum cost. The 4-bit reversible multiplier proposed in this article has a comparable quantum cost as compared to other multiplier circuits. The reduced quantum cost of 256 is the main outcome of this research as compared to a quantum cost for the same circuit design in the literature. \begin{table}
\begin{tabular}{c c c c c} \hline \multirow{2}{*}{**Multiplier Circuit**} & \multicolumn{4}{c}{**No. of Reversible Gates**} \\ \cline{2-5}  & **Peres Gates** & **Toffoli Gates** & **Feynman Gates** & **Other Gates** \\ \hline Proposed design 1-bit & 1 & - & - & - \\ \hline Proposed design 2-bit & 2 & 4 & - & - \\ \hline Proposed design 4-bit & 15 & 16 & - & - \\ \hline Proposed design 4-bit multiplier using CSA & 16 & 16 & - & - \\ \hline Multiplier design in [26] & 20 & - & - & 8 PFAG \\ \hline Multiplier design I in [27] & 11 & 9 & - & 8 PFAG- \\ \hline Multiplier design II in [27] & 11 & 9 & - & 8 HNG \\ \hline Multiplier design in [28] & 20 & - & 16 & 8 PFAG- \\ \hline Multiplier design in [29] & 16 & - & 16 & 12 MKG \\ \hline Multiplier design in [30] & - & - & 16 & 16 FRG + 13 TSG \\ \hline Multiplier design in [31] & - & 12 & 16 & 16 FRG + 12 NG \\ \hline \end{tabular}
\end{table} 
Table 2: Use of gates for different Multiplier configurations. Figure 36: Performance analysis of different multiplier configurations. Where * indicates the partial product output and not the final product of two 4-bit numbers in all the references, and hence, the quantum cost of these [26; 27] circuits will be finalized after adding further stages in these circuits, and hence the quantum cost for the final product of the 4-bit multiplier using the ripple carry adder and carry-save adder is definitely greater than 140 and 144, which is the landmark for the proposed multiplier circuit. A 10% to 48% reduction in the quantum cost is observed, referring to the above table parameters in the proposed designs. The analysis also considered potential optimization opportunities for the design. This includes exploring advanced reversible gates, circuit restructuring, or algorithmic enhancements to further improve performance metrics and address any identified limitations. The comprehensive evaluation of performance metrics provides valuable insights into the strengths and potential areas of improvement for the RCA design using Peres gates.