# Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection
## 5 Bandwidth Extension Techniques
### Equalization
After the cascaded CS stage, CTLE is used to compensate the high-frequency loss owing to the limited bandwidth of a spatially modulated PD, which is monolithically integrated in a single chip. Therefore, the work in [106] achieves 5-Gb/s data rate while the 3-dB bandwidth of the spatially modulated PD is only 700 MHz. Figure 36: (a) [PERSON] effect (b) Miller capacitance applied in a differential CS stage in [91]. In order to achieve sufficient high-frequency boosting and to overcome noise amplification of CTLE, a non-linear equalization technique of a decision feedback equalizer (DFE) has been introduced for optical receivers. The DFE technique has been widely used in electrical links to compensate for inter-symbol interference (ISI) caused by the frequency dependent loss and reflections [9; 25; 108; 109; 110]. Because a theoretical background of DFE can be found in many publications [9; 111; 112; 113; 114], only a brief introduction is provided in this paper for better clarification of the focus. Owing to the loss and reflections, a single transmitted bit cannot complete its transition within a bit period or a unit-interval (UI) so that it influences the following bit sequence. The basic concept of the DFE is that the previously received bit sequence is used when a receiver makes a decision whether the currently received bit is 'zero' or 'one', by feeding back the previously decided bit sequence to the input as shown in Figure 39. That is, the DFE uses consecutive multiple bits to distinguish a single bit because the bits interact with each other due to the ISI. The degree of compensation is closely related to the number of DFE taps, which determines the length of the previous bit sequence to be included in the decision of the current bit. However, the power consumption of DFE circuitry is proportional to the number of taps. This indicates that the DFE requires large power consumption to achieve a sufficient compensation, which renders it less attractive to adopt the DFE for optical links. In 2013, however, an IBM Research group proposed an optical receiver by employing the DFE with infinite impulse response (IIR) feedback [70]. Its most interesting feature is that the receiver uses a resistor-based TIA for \(I\)-\(V\) conversion as shown in Figure 40a. As mentioned earlier, the resistor-based TIA should sacrifice the circuit bandwidth for gain and SNR. In this approach, a large resistor is used to achieve high gain and SNR at the expense of reduced bandwidth, and the resulting ISI is compensated by DFE. Moreover, only one tap DFE is used to compensate the ISI, which arises from a nearly infinite number of preceding bits, by using IIR feedback, and therefore, the overhead of a large number of DFE taps is significantly reduced. In contrast to electrical links where the ISI is mainly caused by external components so that is difficult to predict, the RC time constant between the PD capacitance and the resistor, which is located in the IC and is truly predictable, determines the ISI in a resistor-based receiver. As a result, by making the first feedback tap experience the same RC time constant as the input signal, the feedback signal is exponentially decayed in the same manner as the currently incoming signal so that it can compensate  
Figure 37: Summary of CTLE based on source degenerated CS stage. (**a–c**) Circuit diagrams of normal CS stage, CS stage with source degeneration resistor, and CS stage with source degeneration resistor and capacitor (CTLE). (**d**) Transfer function of CTLE. Figure 38: Overall structure of [91]. infinite taps of ISI as shown in Figure 40b. With the IIR-DFE technique, the resistor-based TIA achieves a data rate of 9 Gb/s. In [115], a University of Toronto group extended the adoption of IIR-DFE to the RGC TIA structure, where the dominant pole is located at the output of the TIA. Compared with [70], the dominant pole is moved from the TIA input to the TIA output; therefore, the DFE feedback subtraction is placed at the output of the TIA in [115].