# FPGA Applied to Latency Reduction for the Tactile Internet
## 7 Results  
The entire tactile internet model infrastructure presented in Figure 4 was implemented with the purpose of validating the FPGA hardware implementation. A spatial trajectory that represents the data sent by the OP through the \(\mathbf{a}(n)\) (Equation (42)) signal was created to validate the entire developed environment. The created trajectory performs a variation in all of the three angles of the MD articulation (Figure 3). For this, it was first considered that the MD is in the initial angular position  
Figure 30: Proposed circuit to calculate the feedback force \(F_{y}^{HSD}[F32](n)\) (Equation (61))—FBF-HSD. Figure 29: Proposed circuit to calculate the feedback force \(F_{x}^{HSD}[F32](n)\) (Equation (60))—FBF-HSD. expressed as \(\theta_{1}^{MD}(0)=0\), \(\theta_{2}^{MD}(0)=0\) and \(\theta_{3}^{MD}(0)=0\), which corresponds to the spatial position \(x^{OP}(0)=0\), \(y^{OP}(0)=-0.107\) and \(z^{OP}(0)=-0.035\) of the tool as illustrated in Figure 32. Initially, the first joint is moved to \(\theta_{1}^{MD}(\mathit{nn})=pi/2\) where \(v\) represents a quantity of samples that is equal to 4 s, thus resulting in the position \(x^{OP}(\mathit{vn})=-0.132\), \(y^{OP}(\mathit{vn})=-0.107\) and \(z^{OP}(\mathit{vn})=-0.167\). Then, the second joint is moved to \(\theta_{2}^{MD}(\mathit{vn})=pi/4\) which results in the position \(x^{OP}(\mathit{vn})=-0.093\), \(y^{OP}(\mathit{vn})=-0.013\) and \(z^{OP}(\mathit{vn})=-0.167\) and, finally, the third joint moves up to \(\theta_{3}^{MD}(\mathit{vn})=pi/4\), thus resulting in the \(x^{OP}(\mathit{vn})=-0.186\), \(y^{OP}(\mathit{vn})=0.025\) and \(z^{OP}(\mathit{vn})=-0.167\) position. The path created is within the limits of the device workspace and takes a total time of \(t_{1}=12\) s of which 4 s are used to perform the movement of each joint. In an effort to validate the circuits from the implemented modules in FPGA, equivalent software models were used to compare the results of both implementations. The software models use a 32-bit floating point format while the hardware modules run a parallel implementation with a hybrid representation which uses both a 32-bit floating point and a fixed point representation in different parts of the proposed architecture, as presented in Section 6. In all scenarios, the signal sampling rate (or throughput) was \(R_{s}=\frac{1}{t_{s}}\) (samples per second), where \(t_{s}\) is the time between the \(n\)-th samples. From the experimental results, the mean square error (MSE) between the software model and the hardware implementation proposed by this work was calculated using the MSE which can be expressed as  
\[MSE=\frac{1}{Q}\sum_{n=0}^{Q-1}(M^{\text{5W}}[F32](n)-M[F32](n))^{2}, \tag{72}\]  
where \(Q\) represents the number of tested samples, \(M^{\text{5W}}[F32](n)\) corresponds to the variables of the software model and \(M[F32](n)\) corresponds to the variables of the model implemented in FPGA. The quantity of tested samples for the results presented here is \(Q=1200\), which correspond to the quantity of samples of the generated trajectory. The variables that correspond to the hardware model \(M[F32](n)\) vary according to the module in which it was implemented. In the case of forward kinematics, as the FK-HMD and FK-HSD modules have the same implementation, the values corresponding to the variables \(x[F32](n)\), \(y[F32](n)\) and \(z[F32](n)\) change according to the respective module. For the FK-HMD module, these variables correspond to \(x^{HMD}[F32](n)\), \(y^{HMD}[F32](n)\) and \(z^{HMD}[F32](n)\) and  
Figure 32: Trajectory used to validate hardware modules. for the FK-HSD module the same variables correspond to \(x^{ENV}[F32](n)\), \(y^{ENV}[F32](n)\) and \(z^{ENV}[F32](n)\) as presented in Section 6. For inverse kinematics, the variables \(M[F32](n)\) of the IK-HSD module correspond to \(\theta_{1}^{HSD}[F32](n)\), \(\theta_{2}^{HSD}[F32](n)\) and \(\theta_{3}^{HSD}[F32](n)\).