# 5G Physical Layer-Based Procedure to Support Time-Sensitive Networking
## 5 Using The 5G Physical Layer Signal for TSC Synchronization  
Using the 5G physical layer slot indication signal for TSN synchronization is the main proposal of this paper. It represents a novel approach to achieving accurate time coordination in a wireless network independently of the end terminal capacities. This method involves a SC base station, which includes a gPTP instance that guarantees the synchronization and accuracy of the 5G NR radio frame. The SC then transmits a timing signal to the UE using the 5G NR radio frame. This timing signal includes both the synchronization and reference times. The UE receives this timing signal and uses it to synchronize its local clock with the SC clock. The SC handles this synchronization process, and the UE extracts the time and synchronization from the 5G NR radio frame. Using the Physical Layer Slot Indication Signal with a Time-Locked Loop (TLL) for Enhanced Synchronization Precision  
The symbols within a slot may be configured as downlink, uplink, or flexible (i.e., uplink or downlink) symbols. A slot indicator signal may be transmitted to the UE to specify the symbol allocation within each slot using the Downlink Control Information (DCI) protocol. The slot indicator may include an indication of the periodicity of the symbols configured in a downlink-uplink pattern, several consecutive full downlink slots at the beginning of each downlink-uplink pattern, several consecutive downlink symbols at the beginning of a partially-filled slot, several consecutive full uplink slots at the end of each downlink-uplink pattern, and/or several consecutive uplink symbols at the end of a partially-filled slot. Moreover, the slot indicator may be configured following other formats to provide the UE with an indication of slot and/or symbol usage. The SC may transmit the slot indication signal such that the arrival of the slot indication signal corresponds with a flank signal of the SC clock. Figure 6 illustrates a schematic of the timing between the SC clock flank signal and subframes of the radio frame. Thus, the UE may calculate the synchronized time according to Equation (3):  
\[\tau_{\text{SynchronizedTime}}=\tau_{\text{Internal Clock}}-\tau_{\text{Timing Advance}}\pm\Delta_{\text{SlotIndication}}, \tag{3}\]  
where \(\tau_{\text{SynchronizedTime}}\) is the synchronized time in the UE, \(\tau_{\text{Internal Clock}}\) is the time kept by the internal clock of the UE, \(\tau_{\text{TimingAdvance}}\) is the timing advance value received from the SC, and \(\Delta_{\text{SlotIndication}}\) is the difference between the arrival time of the slot indication signal at the UE and the reference time. The synchronized time maintains synchronization with the reference clock between the slot indication signals. In this context, it is noteworthy to introduce the Time-Locked Loop (TLL) system, a specialized circuit designed for phase alignment and synchronization purposes, offering distinct advantages over traditional Phase-Locked Loops (PLLs). Unlike PLLs, the TLL operates in the time domain, making it ideal for applications where precise timing alignment is paramount. Thus, the TLL system can execute synchronization with the reference clock of the virtual clock domain; it effectively adjusts the internal clock of the UE to ensure synchronization with the received timing signals. Figure 7 illustrates a TLL feedback circuit, which contains the following elements:  
* Controlled Oscillator: This component generates periodic timing signals. * Real-Time Clock (Counter): This counts time based on the periodic timing signals from the controlled oscillator and produces a time-out signal. * Time Comparator: This compares the computed time-out signal with a reference time-in signal. * Loop Filter: The result of the comparison from the time comparator is filtered and then provided as feedback to the controlled oscillator.