## 3 Two-Level Control Design
### Higher-Level Inverse Dynamic Control
The internal DC bus voltage can hence be controlled by considering the power balance at the internal DC bus terminals, which, observing that the internal bus depicted in Figure 3 includes six couples of series-connected capacitors, results in:  
\[P_{g}=\frac{d}{dt}\bigg{[}\frac{1}{2}\Big{(}\frac{6C_{in}}{2}\Big{)}v_{in}{}^ {2}\bigg{]}+\frac{3}{2}\text{Re}\bigg{\{}\mathbf{v}_{3}\hat{\mathbf{i}}_{3} \bigg{\}}+\sum_{i=4}^{6}\big{(}v_{i}^{+}\cdot i_{i}^{+}+v_{i}^{-}\cdot i_{i}^ {-}\big{)}, \tag{18}\]  
where \(v_{in}=v_{in}^{+}\) - \(v_{in}^{-}\) represents the internal bus pole-to-pole voltage. By means of the same procedure used to obtain (17), the control law for the DC bus voltage is obtained from (18), resulting in:  
\[ \begin{split} P_{g}*=& v_{in}\Big{[}\hat{g}C_{in} \frac{d}{dt}v_{in}^{*}+g_{1\ in}\big{(}v_{in}^{*}-v_{in}\big{)}+g_{2\ in}\!\int \big{(}v_{in}^{*}-v_{in}\big{)}dt\Big{]}+\\ &+\text{Re}\big{\{}\mathbf{S}_{3}^{*}\big{\}}+\sum_{i=4}^{6} \big{(}P_{i}^{+*}+P_{i}^{-*}\big{)},\end{split}  \tag{19}\]  
where \(g_{1\ in}=(6/2)C_{in}/K_{1}\), \(g_{2\ in}=(6/2)C_{in}/(K_{1}K_{2})\). Note that, similar to the control of external port voltages realized by (17), (19) provides the reference power to control of the internal bus voltage with dynamics assigned by coefficients \(g_{1\ in}\), \(g_{2\ in}\), and is formally equivalent to a PI regulator with feed-forward/compensation terms. Power \(P_{g}^{*}\) must be split into ports 1 and 2 by means of a suitable logic, such as:  
\[\left\{ \begin{array}{l}P_{1}^{*}=\beta_{1}P_{g}^{*}\\ P_{2}^{*}=\beta_{2}P_{g}^{*}\end{array} ,\ \ \beta_{1}+\beta_{2}=1,\right. \tag{20}\]  
where the terms \(\beta_{i}\) can be constants, functions, or references obtained from an upper-level supervisory control. Lastly, for the considered three-wire configuration, it is necessary to introduce the equilibrator control to maintain voltage balance. Define voltage unbalance as:  
\[v_{bal}=v_{in}^{+}+v_{in}^{-}, \tag{21}\]  
and recognizing that, in the present topology, only DC ports can introduce voltage unbalances, the unbalance power is consequently defined as:  
\[P_{un}=\sum_{i=4}^{6}\big{(}P_{i}^{+*}-P_{i}^{-*}\big{)}, \tag{22}\]such that it is possible to introduce a power balance equation similar to (18) for the internal bus. Observing that the internal bus depicted in Figure 3 includes six couples of capacitors, parallel-connected with respect to voltage balancing, the desired power balance equation results in:  
\[P_{bal}=\frac{d}{dt}\left[\frac{1}{2}(12C_{in})v_{bal}^{2}\right]-P_{un}. \tag{23}\]  
Considering (23) and recognizing that \(v_{bal}\)' = 0, the reference balancing power is obtained as  
\[P_{bal}^{*}=v_{in}\left[g_{b1}v_{bal}+g_{b2}\int v_{bal}dt\right]-P_{un}, \tag{24}\]  
where gains are defined as \(g_{b1}\) = \((12C_{in})/(K_{1})\), \(g_{b2}\) = \((12C_{in})/(K_{1}K_{2})\). If more than one equilibrator is present, balancing power can be treated, similarly to (20), by means of a number of suitable, unity-sum coefficients. Lastly, current references for each port are obtained from power references as:  
\[\mathbf{i}_{i}^{*}=-\frac{2}{3}\frac{P_{i}^{*}}{\mathbf{v}_{i}}\quad i=1, \tag{25}\]  
\[i_{i}^{*}=-\frac{P_{i}^{*}}{v_{i}}\quad i=2, \tag{26}\]  
\[\mathbf{i}_{i}^{*}=\frac{2}{3}\frac{\mathbf{S}_{i}}{\mathbf{v}_{i}}\quad i=3, \tag{27}\]  
\[\left. \begin{array}{c}i_{i}^{+*}=\frac{P_{i}^{*+}}{v_{i}^{*}}\\ i_{i}^{-*}=\frac{P_{i}^{*-}}{v_{i}^{*}}\end{array} \right\}\quad i\in[4,6], \tag{28}\]  
\[i_{bal}^{*}=\frac{P_{bal}^{*}}{v_{in}^{-}}. \tag{29}\]  
Note that (25), being aimed at controlling the internal bus voltage through (19), includes active power only. Clearly, a certain reactive power can be also exchanged if necessary, resulting in a control equation similar to (27). In more general cases, (25) and (26) are valid for, respectively, AC and DC ports connected to controllable energy sources, while (27) and (28) are valid, respectively, for AC and DC ports connected to loads or non-controllable energy sources (i.e., PV plants).