# A Data-Driven Fault Tree for a Time Causality Analysis in an Aging System
## 3 The ITCA Methodology
### Phase 3: The ITCA Model Construction  
Phase 3 builds, in a sequential up-bottom structure, several connected common logic trees to depict unexplained causes through multilevel structure. Each level includes three stages: verify the common logic trees' construction, connect those trees to their corresponding causes, and generate new labelled sub-datasets that exclude the variables associated with causes already explained from the concatenated datasets. In Phase 3, each cause (i.e., condition) of the obtained common logic trees in Phase 2 is considered as a new event that needs to be explained in a lower level using a new common logic tree. This procedure is iteratively repeated to construct a multilevel tree that represent the fault causality structure over time. In such hierarchical structures, the common feasible solutions at the first level characterize the fault event using general fault indicators, while the common feasible solutions at the lower levels will use specific fault indicators to explain the last causes of the tree. * Stage 1: Verify the common logic trees' construction over the defined periods. This stage verifies the knowledge representability of the constructed logic tree for each defined period of time and decides whether the further decomposition of its involved condition is required or not. At each decomposition level, verification of the tree knowledge is characterized by the coverage of the common feasible solution, which assists in avoiding decomposing the weak information branches. Therefore, the model construction is verified to sustain the tree at a non-redundant knowledge level based on the pre-set coverage threshold. Meanwhile, the construction phase can be interpreted if there is no common tree that is able to provide sufficient knowledge representability, or if there are no more variables in the dataset for any further root cause explorations. * Stage 2: Connect the common logic trees to their corresponding causes. The applied relaxation in selecting a common feasible solution over the defined periods is very useful in constructing a common logic tree that easily demonstrates the change in the causality at a given level of decomposition in the ITCA model. However, it could happen if the time-based searching algorithm fails to form only one common logic tree that dominates all the defined periods at a certain decomposition level. This case could happen if there is a lack of extracted knowledge or a tight range in the solution tolerance selection (STS). To solve this situation, different common logic trees may be found by the algorithm, but each period is dominated by only one common feasible solution. Therefore, if such a situation rises, a time-OR gate is proposed to connect the different common logic trees to represent the change in the event causality  
Figure 4: Curve of the cut-point values of similar feasible solutions obtained over time. knowledge over all the defined periods at a given decomposition level. The time-OR gate acts as a time switch that shifts between the common logic trees according to their corresponding periods. Hence, an expert could observe the fault behaviour over time based on the proposed common similar solution trees at a certain decomposition level of the ITCA model. Figure 5 presents an example of the time-OR gate functionality in a one-level ITCA model. Two common feasible solutions, \(S_{1}\) and \(S_{2}\), are found by the time-based searching algorithm. \(S_{1}\) characterizes the fault event at only \(\Delta_{1}\) and \(\Delta_{2}\) using the OR gate (G2) between the patterns \(P_{1}\) and \(P_{2}\). While \(S_{2}\) represents the fault even only at only \(\Delta_{3}\) with one pattern, \(P_{3}\). This allows \(P_{3}\) to be connected directly to \(S_{2}\) without any need for an OR gate. The time-OR gate (G1) enables ITCA to fully demonstrate the fault event causality over the three defined periods (\(\Delta_{1}\), \(\Delta_{2}\) and \(\Delta_{3}\)).