# Comparison of Various Factors Affected TID Tolerance in FinFET and Nanowire FET
## 3 Results and Discussion  
Figure 3 shows the basic structure of the FinFET and 5 ch-NW as well as the interface hole trap after TID simulation. Figure 3a,b show that the physical thickness and EOT of the insulator were the same. Figure 3c,d show the interface hole traps of the FinFET and 5 ch-NW, respectively. The hole traps at the interface between SiO2 and HfO2 was confirmed to improve simulation accuracy. Figure 3c,d also show that the hole-trapped interface between Si and SiO2. TID is a phenomenon generated because of the accumulation of radiation irradiated to the device. When the radiation penetrates through the insulator region of a device, EHP is generated through the ionization process. Due to their difference in mobility, the generated electrons rapidly diffuse out from the dielectric region. However, some holes are captured in the insulator region trap sites, thereby increasing the leakage current and causing a negative VT shift [26; 27]. Figure 4 illustrates the TID simulation method. In Figure 4a, VG according to the transient time takes the shape of a pulse. The ID-VG curve changes depending on if the pulse is rise or down. In this figure, we can see the upsweep when the purse is rising. Additionally, we can see the downsweep when the purse is going down. The width of the pulse is related to the amount of dose. We can see the simulation results when the pulse is end. The results show the VT shift and that means the hole is trapped in the interface. Figure 3: Structure of each device and the interface hole traps after the total ionizing dose (TID) simulation. (**a**) The structure of the FinFET; (**b**) the single-stage structure of 5 ch-NW; (**c**) the interface trap of the FinFET; (**d**) the interface trap of the 5 ch-NW. Figure 5 shows the electrical characteristics of the device with the TID effects for each radiation level. We extracted the \(\mathrm{V_{T}}\) when the drain current was \(1\times 10^{-7}\) [A] using the current constant method in Figure 5. It shows that the \(\mathrm{V_{T}}\) shifted because the holes generated by the radiation were trapped in the insulator. Therefore, the shift tendency increases with the increase in the TID. In Figure 5, relatively low levels of radiation did not affect the transfer characteristics. Due to the nanoscale oxide area, the hole trap caused by the radiation was reduced. Additionally, the GAA structure increased the gate holding power and reduced the effect of the trapped charge. Figure 5c,d show the log scale of \(\mathrm{I_{D}}\)-\(\mathrm{V_{G}}\) where the off current increase phenomenon, caused by the TID effects, was confirmed. In the figure, we can see that the off current change of 5 ch-NW was less than that of FinFET. This shows that the effect of suppressing the SCE also suppressed the TID effects. Table 2 presents the \(\mathrm{V_{T}}\) value for each TID amount of both the FinFET and 5 ch-NW. Figure 5e,f show the transconductance of the FinFET and 5 ch-NW. It can be noticed that the transconductance increases with radiation, as shown in Figure 5e,f, because of the decrease of \(\mathrm{V_{T}}\) and the flow of more drain current at the same gate voltage. Figure 6 shows the details the \(\mathrm{V_{T}}\) shift for each device. In the case of FinFET, a 48 mV shift from 100 Mrad than the initial was observed. In the case of the 5 ch-NW, roughly 42 mV shift from 100 Mrad than the initial was observed. The 5 ch-NW therefore showed less \(\mathrm{V_{T}}\) shifts than the FinFET, as per the simulation results. \begin{table}
\begin{tabular}{c c c} \hline \hline \(\mathrm{V_{DD}}\) = 0.65 V & FinFET (\(\mathrm{V_{T}}\)) & 5 ch-NW (\(\mathrm{V_{T}}\)) \\ \hline Initial & 329 mV & 402 mV \\
100 k (rad) & 325 mV & 402 mV \\
1 M (rad) & 323 mV & 400 mV \\
10 M (rad) & 312 mV & 388 mV \\
100 M (rad) & 281 mV & 360 mV \\ \hline \hline \end{tabular}
\end{table} 
Table 2: \(\mathrm{V_{T}}\) data of each device according to the amount of TID. Figure 4: TID simulation method of the FinFET.