# Standalone GPS L1 C/A Receiver for Lunar Missions
## 2 The _WeakHEO_ Receiver Architecture
### GPS Acquisition
#### 2.5.2 Acquisition Hardware Implementation  
The FPGA implementation of the acquisition is shown in Figure 9. The Nios II processor is used to manage and configure the different blocks (e.g., the acquisition module is configured with parameters such as Doppler frequency, PRN code, number of integrations, _etc._), and to analyze the data provided by the acquisition module to decide if a signal has been detected. The acquisition module processes the input data using the PCS method as shown in Figure 8 and provides acquisition statistics (peak value, mean value, standard deviation, _etc._) to the Nios II processor. Since the integration time is very long (9.5 s), the amount of data to save is significant (around 39 M samples). Therefore, a DDR2 SDRAM external to the FPGA is used to save this data.  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Quantity** & **Value** \\ \hline C/N0 (dB-Hz) & 15 \\ Sampling rate (MHz) & 4.096 \\ Quantization (bit) & 4 \\ Quantization loss (dB) & 0.05 \\ Coherent integration time (ms) & 20 \\ Coherent gain (dB) & 46 \\ Frequency search step (Hz) & 25 \\ Worst case frequency mismatch loss (dB) & 0.91 \\ Code search step (chip) & 0.25 \\ Worst case code alignment loss (dB) & 1.16 \\ Data bit alignment loss (dB) & 0.92 \\ Squaring loss (dB) & 5.73 \\ Final desired SNR (dB) & 16 \\ Non-coherent gain required (dB) & 26.77 \\ Number of non-coherent integration & 475 \\ Total accumulation time (s) & 9.5 \\ Maximum tolerable Doppler rate error (Hz/s) & 2.63 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Theoretical acquisition parameters.  
Figure 8: Block scheme of the acquisition module.  
In high sensitivity acquisition, the acquisition time can be very long and the transition between the acquisition and the tracking becomes difficult. Thus, we propose to acquire the signal twice, reducing the frequency search space after the first step.  
The time spent to search one frequency bin is defined as:  
\[T_{FB}=\frac{f_{S}T_{I}}{f_{FPGA}}=\frac{4.096\times 10^{6}\times 9.5}{163.84 \times 10^{6}}=237.5\,\mathrm{ms} \tag{4}\]  
where \(f_{S}\) is the sampling rate, \(T_{I}\) is the total integration time, and \(f_{FPGA}\) is the clock frequency of the FPGA. For the first acquisition, the frequency search space considered is \(\pm\)35 kHz. With a frequency step of 25 Hz, there are \(N_{FB,1}\) = 2801 frequency bins, thus the time to search the entire frequency search space is:  
\[T_{A,1}=T_{I}+N_{FB,1}T_{FB}=9.5+2801\times 237.5\,10^{-3}=674.5\,\mathrm{s} \tag{5}\]  
According to Figure 7, the Doppler rate is less than 4 Hz/s after the initial few hours of the MTO. Therefore, during the first acquisition the frequency of the received signal may have shifted by up to 2700 Hz (4 Hz/s \(\times\) 675 s). For the second acquisition, the frequency search space is then \(\pm\)2700 Hz, which corresponds to \(N_{FB,2}\) = 217 frequency bins. The time to search the frequency search space of the second step is:  
\[T_{A,2}=T_{I}+N_{FB,2}T_{FB}=9.5+217\times 237.5\,10^{-3}\approx 61\,\mathrm{s} \tag{6}\]  
During this time, the frequency of the received signal could have shifted by up to 244 Hz, which is still too large to start correctly the tracking. However, provided we recorded the time between the two consecutive acquisitions, the Doppler rate can been estimated by looking at the evolution of the Doppler frequency, or from the evolution of the code delay. From Figure 7, we can assume the Doppler rate is constant during a short time interval and therefore it is possible to initialise the tracking from these results.  
Figure 9: Global structure of the acquisition implementation.