# A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures
## 7 Discussion and Conclusions  
This study is intended to present a new concept for the engineering of a Test Pattern Generator (TPG) capable of producing pseudo-random test vectors for scan path testing of the STUMPS architecture. The innovative structure assumes the implementation of multiple Linear Feedback Shift Registers with D-type and T-type flip-flops (DT-LFSR) with identical layouts. Such a TPG, designated herein as DT-LFSR-TPG, enables a substantial increase in phase shift between binary sequences appearing at the TPG outputs compared to phase shifters described in [34; 39]. What is also important in such TPGs is that the acceptable separation factor (phase shift) between output channels is guaranteed for any pair of the TPG outputs, quite the opposite to other solutions; for instance, the one disclosed in [13], where such an offset is guaranteed only for adjacent outputs. Moreover, with the assumption of the minimum phase shift, the DT-LFSR-TPG circuits also make it possible to wire more scan paths to the TPG outputs as compared to the numbers achieved in [34; 39]. The DT-LFSR-TPG modules also outrank the test pattern generators of the LFSR + PS type as proposed in [34] in terms of the maximum operating frequency. The divergence between operation frequencies becomes even more significant when the number of TPG output channels increases. The high generation frequency for pseudo-random test patterns, achieved for DT-LFSR-TPG solutions, enables substantial reduction of the testing time and, in consequence, reduction of expenses for testing. However, the higher hardware overhead, as compared to solutions outlined in [34], is a certain drawback of the TPGs investigated in this study. The DT-LFSR-TPG structures also prevail in higher operation frequencies as compared to two-dimensional and hierarchical CA and GLFSR registers that comprise at least two layers of XOR gates in their paths of linear feedback. On the contrary, only a single XOR gate is included in each local feedback loop (i.e., the internal loop of a T-type flip-flop) when DT-LFSR registers are used as components of test pattern generators of the DT-LFSR-TPG type. Pseudo-random pattern generators of the DT-LFSR-TPG type seem to be an attractive solution for designers who still have some redundant hardware remaining in their projects, where integrated circuits with a large number of input and output lines with quite low utilization of internal resources can serve as a good example. At least for a portion of such circuits, the overall area occupied on a silicon substrate is determined by dimensions of numerous pads for input and output lines. If so, a substantial part of silicon areas available for an internal logic of an IC still remains redundant and can be used for the needs of the LBIST structure. The DT-LFSR-TPG structures of pseudo-random test pattern generators are easy to design, which is a subsequent advantage of such solutions. The design is just reduced to selection of an appropriate D\({}^{k}\)T\({}^{t}\) structure of the DT-LFSR register (based on Tables 1 and 6) suitable for the test pattern generator. The selection must guarantee that the required separation between output channels of the DT-LFSR-TPG module is preserved while keeping the cost of the test pattern generator at the lowest possible level. The determination of content for both of the aforementioned tables is also a minor problem. As was mentioned in Section 4.3, the calculation of phase shifts between binary sequences at outputs of the DT-LFSR register with the register length up to as many as 100 bits takes not more than several seconds. In turn, the logic synthesis of all DT-LFSR registers listed in Table 6 took less than 1 min. On the contrary, the time necessary to design a test pattern generator of the LFSR + PS type with the use of methods given in [34] was sometimes as long as several hours.