## 2 Materials and Methods
### Fabrication Procedure  
The 200 mm SOI (silicon on insulator) wafers have a 220 nm thick silicon-layer, and a 2 um thick buried oxide layer, and were processed with a MPW (multi-project wafer) run at the CEA-Leti Si-photonics foundry, using standard CMOS process flows. An initial step in the wafer-processing, is the definition of the fiber grating-couplers by 193 nm DUV lithography, and a specific 120 nm partial etch of the Si-layer (with a uniformity better than 3% for the whole wafer). This partial etch is used to pattern the fiber couplers, and to define the height of the reduced-height 100 nm strip waveguides (220 nm Si-layer \(-\) 120 nm Si-etch = 100 nm Si-waveguide), used to achieve our low-loss micro-resonator filters. The realized gratings allowed the coupling of light directly from the input fiber to the Si waveguide, which was either 220-nm high or 100-nm high, according to the considered filter design.  
The other etching process used has a depth of 220 nm \(\pm\) 3% (full-etch), and a uniformity of 1.5% for the whole wafer. Both Si-etching processes are performed using ICP RIE, and dry etching equipment is used to obtain very low losses for optical waveguides. It must be noticed that this, fully CMOS-compatible, etching procedure is very different from the strategies that have been exploited in the past in order to realize height-reduced waveguides ([12] and references therein), which required steam oxidation of the Si-layer and subsequent HF stripping.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameter** & **Units** & **Racetracks** & **Rings** \\ \hline Bus waveguide (width \(\times\) height) & nm \(\times\) nm & 500 \(\times\) 220 & 500 \(\times\) 100 \\ Resonator waveguide (width \(\times\) height) & nm \(\times\) nm & 500 \(\times\) 220 & 825 \(\times\) 100 \\ Straight-leg & nm & 4745 & N.A. \\ Curve radius (@ waveguide center) & nm & 4490 & 6000 \\ Bus-to-Resonator gap & nm & 200 & 410 \\ Inter-Resonator gap & nm & 415 & 340 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Parameters used for the first fabrication of the filters.  
Figure 2: The green line shows the combination yielding the desired coupling coefficient. The red and blue lines correspond to an over and under coupling of 0.5 dB, respectively. (**a**) Contour map obtained considering a straight-coupling geometry; (**b**) Contour map obtained for curved-coupling geometry.  
A HDP (high density plasma) oxide cladding layer encapsulates the waveguide, and optically insulates the waveguide from the Ti/TiN heater, used to tune the filters. The oxide layer thickness is selected to give the best trade-off between heating efficiency and optical losses. The heater consists of a 10 nm-thick layer of Ti (used for adhesion), and of a 110 nm-thick TiN resistive layer, that is patterned to create the thermo-optic phase shifter above the waveguide. Finally, a silicon-oxide cladding layer is deposited, and a tungsten via is added, to make contact with the heater layer. This oxide layer provides optical isolations from the aluminum metallization, used for electrical routing to the contact pads. A schematic cross-section of the full device is shown in Figure 3a, with a top-view microscope image of the racetrack-based structure in Figure 3b.