# FPGA Implementation of a Higher SFDR Upper DDFS Based on Non-Uniform Piecewise Linear Approximation
## 1 Introduction  
DDFS technology can generate the ideal sinusoid signal. Because of its advantages of fast frequency switching, high frequency resolution and low phase noise, it is widely used in modern communication and radar systems. [PERSON] et al. [1] first proposed DDFS architecture in 1971, and almost all subsequent DDFS were based on this architecture. As shown in Figure 1, the architecture of DDFS mainly consists of two parts: phase accumulator and phase-amplitude converter(PAC). Finally, if an analog signal output is needed, a digital-to-analog converter (DAC) and a low-pass filter (LPF) will be added. The frequency control word (FCW) is the input to the entire DDFS and is used to control the frequency of the output signal. The phase accumulator accumulates FCW every  
Figure 1: General architecture of DDFS. clock cycle to continuously generate new phase stored in the phase register. Its essence is to sample the phase based on the clock frequency, and for each overflow of the phase register, it completes one cycle sampling of the sine signal. The phase is then converted to the corresponding amplitude value in PAC. According to the above description, the frequency of the output signal is determined by the frequency control word (FCW) and clock frequency, which can be expressed as follows:  
\[f_{out}=\frac{FCW}{N}*f_{clk} \tag{1}\]  
where \(f_{clk}\) is the clock frequency, and \(N\) is the width of the frequency control word. The core design of DDFS is the PAC, which can be implemented in many ways, the simplest way is to use a lookup table (LUT), which use the phase as address to index the corresponding amplitude value. The size of LUT increases exponentially with the increase of the bit width N of the FCW, and in order to improve the frequency resolution of the output signal, N is usually taken to a large value, which results in a very large size of LUT, even using the symmetry of the sine function. In [2; 3; 4; 5], the phase is truncated to reduce the size of LUT, but it amplifies the error of the PAC and introduces more spurious signals into the output signal. The latest LUT-based DDFS were proposed by [PERSON] et al. [6], which use multiplexer-based LUT implemented in a tree structure. In order to get rid of the limitation of LUT size, many computation-based methods have been proposed. The core idea of these methods is to optimize space complexity with computational complexity. CORDIC algorithm [7] is introduced to calculate the amplitude value in [8; 9; 10; 11; 12; 13]. This method calculates trigonometric functions by angle rotation, which can avoid memory access, but the iteration period is longer. [PERSON] et al. [14] design DDFS using a multiplier-based angle rotation algorithm and achieve impressive performance. Some work combines the two methods of angular rotation and lookup table to reduce the lookup table size as much as possible while maintaining accuracy [15; 16; 17; 18]. In addition, polynomial approximation method is also used for amplitude calculation [19; 20; 21; 22; 23; 24; 25; 26; 27; 28]. In polynomial interpolation methods, the first quadrant of the sine function is usually evenly divided into \(s\) segments, each of which is approximated separately by a polynomial, and \(s\) is usually a power of two. Among these works, [PERSON] [19] first used 16-segment linear functions to approximate the first quadrant of the sine function, and designed a correction table using ROM. In order to reduce errors, Chebyshev polynomial and Lagrange polynomial interpolation are used to reduce the MAE and mean square error (MSE) respectively, such as [20; 21]. The most important performance indicator of DDFS is SFDR. Therefore, many researchers have conducted in-depth studies on SFDR of DDFS based on polynomial interpolation. [PERSON] et al. [22] theoretically proved the SFDR upper bound of DDFS based on PWL approximation, as shown in Equation (2).