# Design of Shadow Filter Using Low-Voltage Multiple-Input Operational Transconductance Amplifiers
## 2 Proposed Circuit  
### Mi-Ota  
The electrical symbol of the MI-OTA is presented in Figure 1. The general expression for the output current of the OTA can be written as a sum of three differential input voltages multiplied by a circuit transconductance \(g_{m}\):  
\[I_{o}=g_{m}(V_{+1}+V_{+2}+V_{+3}-V_{-1}-V_{-2}-V_{-3}) \tag{1}\]  
The CMOS circuit schematic of the MI-OTA is presented in Figure 2a. This CMOS structure is a modified version of the two-input, one-output MI-OTA, which was first experimentally verified in [33]. In the proposed MI-OTA, an additional input voltage was incorporated to facilitate filter applications. This modification, which increases the number of inputs, resulted in a simplified filter topology and a reduction in the number of OTAs required. The design features a linearized bulk-driven (BD) input stage (M\({}_{1}\)-M\({}_{4}\)) coupled with a set of current mirrors (M\({}_{5}\)-M\({}_{12}\)) configured in a current mirror topology with a single output. The linearization technique employed relies on the principle of source degeneration, wherein transistors M\({}_{3}\) and M\({}_{4}\) operate in the triode region and are regulated by input signals. This approach enhances linearity and improves immunity to common-mode signals. The underlying concept was initially introduced for conventional gate-driven (GD) circuits operating in the strong inversion region [34]. In this design, a similar topology is adapted for bulk-driven (BD) devices operating in the weak inversion region, which aligns with the extremely low bias currents required for ultra-low-power applications. Additionally, the input transistors M\({}_{1}\) and M\({}_{2}\) were replaced with multiple-input devices. These devices were formed by conventional BD transistors enhanced with capacitive voltage divider/summing circuits connected to their bulk terminals, as depicted in Figure 2b. This approach, referred to as the MI-BD-MOS technique [35], streamlines the multiple-input structure and reduces overall power dissipation. Figure 1: Electrical symbol of MI-OTA. The summing circuits comprise capacitors \(\rm C_{Bi}\) in parallel with large resistances \(\rm R_{L}\), implemented using anti-parallel connections of transistors \(\rm M_{L}\) operating in the cutoff region with \(\rm V_{GS}\) = 0. For the frequency range of interest (\(\omega>>1/C_{\rm B}R_{L}\)), the summing coefficients are determined solely by the capacitor values. The large resistances \(\rm R_{L}\) ensure the proper DC biasing of the bulk terminals of \(\rm M_{1}\) and \(\rm M_{2}\). Notably, the application of the BD technique not only extends the OTA's common-mode range but also enhances its linear range. To enhance the DC voltage gain without restricting the output swing of the OTA, the current mirror transistors are implemented as composite devices using a self-cascode (SC) configuration. In this design, the transistors \(\rm M_{ic}\) (i = 5-13) operate in the triode region, functioning as source-degenerative resistors for their counterparts \(\rm M_{i}\). This configuration effectively increases the output resistance of the device, contributing to improved overall voltage gain while maintaining adequate output swing capabilities. The quasi-static I-V transfer characteristics of the OTA, corresponding to the \(i\)-th input, can be expressed for unity-gain current mirrors and under the condition \(\omega>>1/C_{\rm B}R_{L}\) as follows [33]:  
\[I_{out}=2I_{set}tanh\left(\beta_{i}\eta\frac{V_{+i}-V_{-i}}{2n_{p}U_{T}}-tanh ^{-1}\left[\frac{1}{4m+1}tanh\left(\beta_{i}\eta\frac{V_{+i}-V_{-i}}{2n_{p}U_{T }}\right)\right]\right) \tag{2}\]  
where  
* \(\eta=\left(n_{p}-1\right)=g_{mb1,2}/g_{m1,2}\) at the operating point;
* \(n_{p}\) is the subthreshold slope factor for p-channel transistors;
* \(U_{T}\) is the thermal potential;
* \(m=(\rm W_{3A}/L_{3A})/(\rm W_{1,2}/L_{1,2})\) is the relative aspect ratio of the two matched transistor pairs \(\rm M_{3A}-M_{1,2}\);
* \(\beta\) is the AC voltage gain of the input capacitive divider.