## 4 Results and Discussions
### Electrical and Photovoltaic Properties  
As the next part of characterization process, the electrical properties of the fabricated CuIC micro-Si thin film were analyzed using Hall Effect measurements. To this end, the doping concentration and carrier mobility were determined for the samples annealed at different temperatures; see Figure 10. At an annealing temperature of 550 \({}^{\circ}\)C, the hole concentration was in the order of \(10^{15}\) cm\({}^{-3}\), while the mobility parameter was extremely high. Therefore, such a micro-Si film is not suitable as the emitter layer of poly-Si solar cells, because according to [32; 33], the typical values of the hole concentration and carrier mobility for an emitter layer should be in the range of from \(10^{16}\) to \(10^{19}\) cm\({}^{-3}\) and from 1 to 100 cm\({}^{2}\)/V.s, respectively. Thermal treatment at a higher temperature, i.e., 750 \({}^{\circ}\)C, led to a considerable decrease in hole mobility, i.e., to 70 cm\({}^{2}\)/V.s, which was in an appropriate range. At the same time, the opposite trend was observed for the hole concentrations of the fabricated film after annealing at 750 \({}^{\circ}\)C, which reached to more than \(10^{18}\) cm\({}^{-3}\). When thermal annealing was conducted at 900 \({}^{\circ}\)C, the hole concentration and mobility reached 70 cm\({}^{2}\)/V.s and \(5\times 10^{19}\) cm\({}^{-3}\), respectively. This behavior confirms that Cu atoms can play the role of p-dopants more effectively with increasing the thermal budget of the CuIC process. When the material and electronic properties of the deposited thin films had been investigated, we fabricated a simple solar cell using the CuIC micro-Si thin films as the emitter layer and created  
Figure 10: Variation of the hole concentration (blue) and mobility (red) with thermal annealing temperature. Figure 9: (**a**) SEM micrograph of CuIC micro-Si thin film with (n-type C-Si wafer/p-type Si/Cu) structure after annealing at 500 \({}^{\circ}\)C, (**b**) SEM micrograph of the CuIC micro-Si thin film after annealing at 600 \({}^{\circ}\)C.  
metal electrode contacts for the thin film samples fabricated on n-type C-Si wafers. The simplified structure of this device is shown in the inset of Figure 11a. In this device, CuIC micro-Si thin films form the p-side of the solar cell junction, while an n-type C-Si wafer forms the n-side. The AZO layer acts as an interface between the micro-Si layer and metal electrode contacts, and reduces the series resistance of the final solar cell. Figure 11 shows the Rectification Ratio (RR), dynamic resistance and J-V characteristics of the solar cell made by the CuIC thin film layer which was fabricated using the optimized process. RR is defined as the ratio of the forward bias current of the p-n junction to the current at the same bias voltage but with reverse polarity. The variation of RR with temperature is shown in the blue curve of the graph in Figure 11. Under the dark condition, the created p-n junction showed good rectification behavior, with the highest \(RR=4100\) at \(\pm\) 1 V and a reverse saturation current of \(J_{0}\approx 85\) nA.cm\({}^{-2}\). Then, we calculated the dynamic resistance (\(R_{d}=\Delta V/\Delta J\)) of the p-n junction over a bias voltage of \(\pm\) 1 V in order to determine the series resistance (\(R_{S}=R_{d}|_{\text{J,cell}}=0\)) and shunt resistance (\(R_{Sh}=R_{d}|_{\text{V,cell}}=0\)) of the fabricated solar cell. As shown in Figure 11, the values of \(R_{S}=14.0\)\(\Omega\).cm\({}^{2}\) and \(R_{Sh}=63.7\)\(\Omega\).cm\({}^{2}\) were too high and too low, respectively. These results, in line with the material and morphological characteristics, imply that the quality of the fabricated thin film was not sufficient for use in photovoltaic applications. However, this represented a significant improvement in comparison to our previous results reported in [34].