# Safety-Oriented System Hardware Architecture Exploration in Compliance with ISO 26262
## 4 Safety-Oriented System Hardware Architecture Exploration Framework
### System Hardware Architecture Exploration with Safety and Hardware Overhead Consideration
#### 4.3.2. ASIL-Oriented Hardware Architecture Exploration Algorithm
The derived outcomes of safety mechanism deployment are \(SM_{\textit{CAN bus}}\) = \(SM_{\textit{HHH}}\), \(SM_{\textit{AEB\_MCU}}\) = \(SM_{\textit{HHH}}\), \(SM_{\textit{B\_SEN}}\) = \(SM_{\textit{HHH}}\), \(SM_{\textit{B\_PECU}}\) = \(SM_{\textit{MMMM}}\), \(SM_{\textit{Radar}}\) = \(SM_{\textit{HHH}}\), \(SM_{\textit{R\_ECU}}\) = \(SM_{\textit{MMMM}}\), \(SM_{\textit{S\_SEN}}\) = \(SM_{\textit{HHH}}\), \(SM_{\textit{S\_ECU}}\) = \(SM_{\textit{MMMM}}\), \(SM_{\textit{PS}}\) = \(SM_{\textit{LLM}}\) (PS stands for the power supply) and the corresponding hardware architecture metrics all comply with the target ASIL. D requirements, which are \(\text{SPFM}\) = \(99.87\%\), \(\text{LFM}\) = \(99.89\%\), and \(\text{PMHF}\) = \(8.995\times 10^{-9}\). To reach these results, there are ten design iterations executed. Next, the total hardware overhead needs to be calculated according to the hardware overhead data summarized in Table 14.

\[HO\_Total_{\textit{lite\_d}}(\%)=\frac{\sum_{e=1}^{9}HC\left(SM_{\textit{xyz }}(PT(e))\right)}{\sum_{i=1}^{17}HC\left(i\right)}=\frac{82.84}{204}=40.61\% >HO\_{\textit{Max}_{\textit{sys}}}\] \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**\begin{tabular}{c} **\(\textbf{Hardware}\)** \\ **Element** \\ \end{tabular} & **\begin{tabular}{c} **Hardware** \\ **Unit** \\ \end{tabular} & \begin{tabular}{c} \(SM_{\textit{LLL}}\) \\ \end{tabular} & \begin{tabular}{c} \(SM_{\textit{LLL}}\) \\ \end{tabular} & \begin{tabular}{c} \(SM_{\textit{MMMM}}\) \\ \end{tabular} & \
\begin{tabular}{c} \(SM_{\textit{MHM}}\) \\ \end{tabular} &
\begin{tabular}{c} \(SM_{\textit{HHH}}\) \\ \end{tabular} \\ \hline \hline Brake ECU 1-4 & 8 & – & – & – & – \\ EBM 1-4 & 4 & – & – & – & – \\ CAN bus & 16 & 8 & 10 & – & – & 100 \\ AEB MCU & 20 & 20 & 25 & 50 & 55 & 100 \\ Brake pedal & 8 & 24 & 28 & 45 & 50 & 75 \\ Sensor & 14 & 25 & 30 & 60 & 64 & 80 \\ Brake pedal ECU & 12 & 28 & 30 & 48 & 54 & 75 \\ Radar ECU & 16 & 28 & 32 & 52 & 56 & 75 \\ Speed sensor & 10 & 20 & 24 & 45 & 48 & 75 \\ Speed Meter ECU & 14 & 20 & 25 & 48 & 52 & 75 \\ Power supply & 6 & 12 & 15 & – & – & 20 \\ \hline \hline \end{tabular}
\end{table} 
Table 13: Safety mechanism deployments and their \(DC_{RF}\) and \(DC_{DPFL}\) for \(PT\). Because the current system hardware overhead does not meet the constraint, the HO-oriented hardware architecture exploration algorithm is activated to solve the hardware overhead problem. The process of performing the HO-oriented hardware architecture exploration is similar to the previous example presented in Section 4.3.3. Therefore, we do not repeat the process and directly provide the modified parts, which are summarized as follows:

* \(SM_{S\_SEN}=SM_{HHH}\to SM_{MHM}\), \(SM_{S\_ECU}=SM_{MMM}\to SM_{MHM}\) and \(SM_{PS}=SM_{LML}\)
* \(\to SM_{HHH}\). * \(HO_{\_Total_ite\_4}(\%)=\frac{\sum_{\tau=1}^{9}HC\left(SM_{\_}{\_}{\_}{\_}{ \tau=1}^{9}(PT(\epsilon))\right)}{\sum_{\_}{\_}{\tau=1}^{9}HC\left(i\right)}= \frac{81}{20\lambda}=39.71\%<HO_{\_}Max_{\_}{\_}{\_}{\_}{\tau=1}.\)
* Hardware architecture metrics, which all comply with the target ASIL D requirement are SPFM = 99.83%, LFM = 99.52%, and PMHF = 9.58 \(\times\) 10\({}^{-9}\). Thus, after a total of thirteen design iterations, including eleven iterations for the ASIL-oriented algorithm and two iterations for the HO-oriented algorithm, the resulting fault tree and the FMEDA report are obtained, as shown in Figure 9 and Table 15, respectively. Through the AEB case study, we have illustrated the proposed safety-oriented system hardware architecture exploration framework for the safety-critical automotive system design. Furthermore, the remarkable performance of the proposed framework has also