# A Novel RFID Authentication Protocol Based on Reconfigurable RRAM PUF
## 3 RRAM PUF Circuit  
The typical PUF structure based on traditional RRAM is shown in Figure 0(a),b. Unlike other PUFs that generate random output bits using subtle differences in the manufacturing process, the RRAM implements the PUF function by its discrete resistance distribution formed after erasing. Its physical mechanism is generally attributed to the formation and rupture of conductive filaments formed by oxygen vacancies between two metal electrodes. Because of the randomness of the generation and the disappearance of oxygen vacancies, the shape and size of conductive wires vary randomly in different RRAM cells or even in different periods of the same RRAM cell [11]. Then, a random resistance distribution is formed between different RRAM cells. If a suitable reference current is set, a 0 or 1 can be read out. When the PUF with the structure of Figure 0(a) is working, the PUF challenge input is used as the address of the relevant decoder and an RRAM cell is selected, and then the read current \(\mathrm{I_{R}}\) of the cell is compared with the reference current \(\mathrm{I_{REF}}\), and the sense amplifier (SA) can output a 1-bit PUF response. When a multi-bit PUF response needs to be generated, the operation needs to be repeated many times. This structure is limited by the number of RRAM units, can only generate limited challenge response pairs (CRPs), and has low work efficiency. It is a typically weak PUF and cannot be directly applied to scenarios such as identity authentication. Different from the structure in Figure 0(a), the scheme in Figure 0(b) selects two RRAM cells according to the challenge bit, and then the resistance of the two cells is compared as the output of the PUF response. Due to the difference in response calculation methods, this scheme constitutes a strong PUF circuit, but when a multi-bit response needs to be generated, the read operation must be repeated multiple times, and the work efficiency is still low. In order to improve the computational efficiency of the PUF circuit and expand the challenge response space, this paper proposes a new type of PUF circuit based on RRAM. As shown in Figure 2, the overall structure of the PUF mainly includes PUF control logic modules, 32 rows \(\times\) 32 columns of RRAM memory cells, 32 word lines (WL), 32 bit lines (BL), 32 source lines (SL), 32 sensitive amplifiers (SA), and 32 exclusive OR (XOR) gates and 32 D flip-flops, where each RRAM memory cell is composed of an N-type transistor and a resistive memory cell. Among them, the PUF control logic module receives the excitation signal of the main system (including PUF response calculation request, 32-bit PUF challenge, read/write request signal and corresponding address, etc. ), and generate the decoder control signal, address and other read/write control signals of the RRAM circuit according to the above signals, and complete RRAM configuration, read/write, PUF response calculation and other functions. The traditional memory PUF generally uses the PUF challenge as the memory address and selects the PUF unit, and then reads the stored value of the corresponding unit as the PUF response. For a multi-bit response, it needs to be read multiple times. The proposed RRAM-PUF circuit generates the address signal of the word line decoder according to the 32-bit challenge, and judges the challenge bit by bit. If challenge [k] = 1 (k = 0, 1, 2,..., 31), then control the word line decoder to select the word line WL\({}_{k}\), and then read out the values stored in all RRAM cells in the k-th row and perform an XOR calculation with the flip-flop output of the corresponding column. Save the calculation result in the trigger again. If challenge [k] = 0, no read operation is performed. By repeating the above operation 32 times, a 32-bit PUF response can be obtained.