# Onboard Processing in Satellite Communications Using AI Accelerators
## 4 AI-Capable Commercial Chipsets
\begin{table}
\begin{tabular}{c c c c} \hline \hline \multirow{2}{*}{**Device**} & \multirow{2}{*}{**Provider**} & \multicolumn{2}{c}{**Core Units**} \\ \cline{3-4}  & & **CPU** & **On-Chip Accelerator** \\ \hline \multirow{2}{*}{Myriad Family} & \multirow{2}{*}{Intel} & \multirow{2}{*}{2\(\times\) Leon 4 RISC} & Image/Video PA \\ \cline{3-4}  & & & \multicolumn{1}{c}{SHAVE} \\ \hline \multirow{2}{*}{Jetson Nano} & NVIDIA & 4\(\times\) ARM Cortex-A57 MP & 128-CUDA Maxwell \\ \hline \multirow{2}{*}{Jetson TX2 Family} & NVIDIA & 2\(\times\) Denver ARM64b & \multirow{2}{*}{256-CUDA Pascal} \\ \cline{3-4}  & & 4\(\times\) ARM Cortex-A57 MP & & \\ \hline \multirow{2}{*}{Jetson Xavier NX Family} & \multirow{2}{*}{NVIDIA} & \multirow{2}{*}{6\(\times\) Carmel ARM64b} & \multirow{2}{*}{2\(\times\) NVDLA} \\ \cline{3-4}  & & & 2\(\times\) PVA \\ \cline{3-4}  & & & 48 Tensor \\ \hline \multirow{2}{*}{Jetson AGX Xavier Family} & \multirow{2}{*}{NVIDIA} & \multirow{2}{*}{8\(\times\) Carmel ARM64b} & \multirow{2}{*}{2\(\times\) NVDLA} \\ \cline{3-4}  & & & 2\(\times\) PVA \\ \hline \multirow{2}{*}{Jetson Orin NX Family} & \multirow{2}{*}{NVIDIA} & \multirow{2}{*}{6\(\times\)/8\(\times\) ARM64b} & \multirow{2}{*}{1\(\times\)/2\(\times\) NVDLAv2} \\ \cline{3-4}  & & & 1\(\times\) PVAv2 \\ \cline{3-4}  & & & 32 Tensor \\ \hline \multirow{2}{*}{Jetson AGX Orin Family} & \multirow{2}{*}{NVIDIA} & \multirow{2}{*}{8\(\times\)/12\(\times\) ARM64b} & \multirow{2}{*}{2\(\times\) NVDLAv2} \\ \cline{3-4}  & & & 1792/2048-CUDA Ampere \\ \cline{3-4}  & & & 2\(\times\) NVDLAv2 \\ \cline{3-4}  & & & 1\(\times\) PVAv2 \\ \hline \multirow{2}{*}{Cloud AI 100 Family} & \multirow{2}{*}{Qualcomm} & Snapdragon 865 MP & \multirow{2}{*}{Cloud AI 100} \\ \cline{3-4}  & & & \multicolumn{1}{c}{Kryo 585 CPU} \\ \hline \multirow{2}{*}{Instinct MI200 Family} & \multirow{2}{*}{AMD} & \multirow{2}{*}{CDNA2} & \multirow{2}{*}{6656/14,080 Stream Proc.} \\ \cline{3-4}  & & & 104/220 \\ \cline{3-4}  & & & \multicolumn{1}{c}{Core Units} \\ \hline \multirow{2}{*}{Versal AI Edge Family} & \multirow{2}{*}{XILINX} & 2\(\times\) Cortex-A72 & 8-304 AI Engines \\ \cline{3-4}  & & & 90-1312 DSP Eng \\ \cline{3-4}  & & & 2\(\times\) Cortex-R5F2 & 43k-1139k System \\ \cline{3-4}  & & & \multicolumn{1}{c}{Logic Cells} \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Trade-off of the AI chipsets and boards under consideration: Core Units. available on January 2023 [38]). The first is suitable for embedded real-time and safety-critical systems, while the wide number of cores of the second allows the use of multiple threads in sequential parallelizable software [33; 37]. In the case of the on-chip accelerators, as their architecture differs from one developer to the other, one cannot make a proper comparison without taking into account the performance per operation, which is detailed in Table 4. The most popular AI on-chip accelerators are GPUs (CUDA Cores, Streams Processors) and AI cores (Tensor, AI Engines, and DSP Engines). Versal chips, apart of the on-chip accelerators (AI and DSP Engines), include a programmable logic (PL) chip that can be used to design time-critical parts of the algorithm, exploiting the inherent parallelism of the hardware design. Notice that some data are not reported by the developer, marked as \(NR\), and in some cases, the required information is not detailed, marked as \(x\). The most supported data type operations conducted by the chipsets are integer byte (_INT8_), half-precision floating point (_FP16_), and single-precision floating point (_FP32_) operations. Instinct MI200 and Cloud AI 100 families have the greatest operation rates in half-precision floating point, but their form factor and power consumption make them unsuitable for embedded systems applications. NVIDIA's next-generation AI processors family (Orin NX and AGX Orin) promises to