# Reviews Based on the Reconfigurable Intelligent Surface Technical Issues
## 2 Technical Considerations for RIS
### Hardware Implementation of RIS
A nearly passive RIS, as shown in Figure 16b, is a term for a reconfigurable RIS using PIN diodes, which actually includes an active circuit with a bias, but it is classified as a nearly passive RIS in that it only controls the phase without amplifying the signal. In the case of an active RIS, a power amplifier is included to amplify the signal to overcome the disadvantage of double path loss of a passive RIS; however, due to problems such as high cost, complexity, and power consumption, a hybrid RIS has been recently proposed [71], as shown in Figure 16c. A bias network is required to control the unit cell reflection characteristics of the RIS. The structure of this network depends on the reconfiguration mechanism and the desired degrees of freedom of control of the propagating signal. For example, for a 1-bit RIS structure with a PIN diode reconfiguration unit cell, the bias network can consist of columns driven by a voltage such that each PIN diode in a single column is biased either in a reverse or forward direction with respect to 0\({}^{\circ}\) and 180\({}^{\circ}\), respectively. This type of network is typically designed to be driven by an FPGA. The complexity of the bias circuit for RIS depends on factors such as the reconfiguration scheme, number of unit cells, and periodicity. Continuous tuning with a varactor, which requires a variable DC voltage between 0 and 30 V, typically relies on a digital-to-analog converter (DAC), which requires an analog-to-digital converter (ADC) channel for each unit cell to individually control the unit cell elements with an analog signal. DACs require digital control signals, such as in the form of the well-known serial communication protocols such as SPI and I2C, and associated circuitry and clock signals. The bias of a PIN diode, on the other hand, can be easily implemented to have a forward bias voltage of typically 0.7 to 1.5 volts and a typical operating current of about 1 to 10 mA. Of course, to reduce cost and size, digital circuits such as microcontroller IO ports are often used. For the bias circuit, if it is not electrically isolated from the RF emitters that make up the unit cell, it will not perform as designed. Therefore, an RF choke or optical bias circuit is required to electrically isolate it from the emitters in the unit cell. [PERSON] et al. [72] developed an optically controlled reconfigurable metasurface, which presents the concept of providing a bias voltage to a unit cell with varactor diodes through photodiodes controlled by light of varying intensity, as shown in Figure 17a. Figure 16: RIS classification based on power. (**a**) Passive RIS [70]. (**b**) Nearly passive RIS. (**c**) Active RIS. Adapted with permission from [71]. Copyright 2023 IEEE. In addition, the complexity of the reconfiguration control circuit for beam steering in RIS can be problematic for large-arean RISs [10]. Several methods have been proposed to simplify it, such as sequential loading [10] or unit cell gathering [73], as shown in Figure 17b. A method to reduce the bias network complexity through row/column control in reconfigurable reflectarray antennas was recently proposed by Artiga [74], in which the phase of each unit cell is controlled on a row-by-row basis such that additional phase shifts occur when rows and columns overlap. For an N \(\times\) M metasurface, this scheme requires only N + M analog control lines rather than N \(\times\) M. This study also proposed a 1-bit row/column control scheme that applies an XOR function to the digital unit cells, and showed that it can achieve similar gains to the individual control of 1-bit and 2-bit unit cells without increasing the sidelobe level. The complexity of the bias circuit becomes even more problematic at higher operating frequencies; to address this, the concept of a hypersurface has been proposed [73], where the impedance of each unit cell can be controlled to vary its size and phase using a very small ASIC.