###### Abstract  
With the emergence of 5G and satellite communication applications, where millimeter-wave (mm-wave) active phased arrays play an important role, the demand for a highly integrated and cost-effective method to achieve mm-wave antennas is an inevitable trend. Antenna-in-package (AiP) design is therefore becoming a hotspot. This paper presents the design procedure for a broadband silicon-based stacked patch antenna in Ka-band, which realizes a practical AiP structure for phased-array module integration requirements. A stacked-patch antenna on a high-resistivity silicon (HRS) substrate is demonstrated to effectively extend the bandwidth with the guidance of characteristic mode analysis (CMA).The proposed antenna element and its \(2\times 2\) array were designed and fabricated using silicon bulk micromachining and wafer-level bonding technology. The measured results from the fabricated antenna prototypes showed that (1) the antenna element had an impedance bandwidth of 13.8% from 26.2 to 30.1 GHz, and the peak gain was 6.1 dBi at 28.9 GHz; (2) the \(2\times 2\) array realized an impedance bandwidth of 11.4% from 27.2 to 30.5 GHz, and the peak gain was 9.3 dBi at 28.5 GHz. silicon-based; antenna-in-package (AiP); characteristic mode analysis (CMA); 5G communication; satellite communication; Ka-band 202312249831223  
to its high machining accuracy, low loss, and design flexibility. However, the high cost of this process limits its market to mm-wave applications. Therefore, manufacturers have studied low-cost HDI processes suitable for mass production. IBM has developed various AiP arrays operating in the Ka-band and W-band for mm-wave 5G communication systems based on the HDI process [5; 6; 7]. Molding compounds are materials used in the fan-out wafer-level packaging (FOWLP) process, which is known as eWLB. Several works of AiP design based on this process have been reported so far [8; 9]. Silicon substrate, as one of the most important materials for the integrated circuit industry, can be used to manufacture mm-wave antennas for a highly integrated purpose. At present, the mainstream silicon processing technologies include CMOS, SiGe, and the silicon-based 3D integration process based on bulk silicon micromachining and chip micro-assembly processes [10]. The CMOS process and SiGe process utilize the advantages of semiconductor processes and are mainly used for manufacturing antenna-on-chip (AoC) and on-chip radar systems above 60 GHz. However, the silicon substrate with low resistivity results in a poor radiation efficiency [11]. The silicon-based 3D integration process is more flexible, enabling integration solutions such as heterogeneous integration and high-precision heterogeneous integration in silicon technology. The bulk silicon micromachining process is used to etch the cavity on the silicon substrate for placing the chip and for the cover plate, to create through-silicon-vias (TSVs), and generate metal graphics. Through th micro-assembly process, a mm-wave chip is sintered into the cavity through gold wire bonding. Then, low-temperature wafer-level bonding is performed, and finally, three-dimensional integrated microsystems [12; 13] and T/R modules [14; 15] are obtained through slicing and segmentation. Therefore, a microstrip antenna manufactured through standard silicon process can be easily assembled with other active chips, providing a cost-effective solution for mm-wave AiP design. In practical application scenarios, typical requirements for antennas include sufficient bandwidth, stable antenna gain within the bandwidth, and radiation patterns, to achieve the optimal beam scanning capability for phased arrays. However, the high permittivity of substrates, which can result in a high quality factor (Q value) for antennas and trigger surface waves, hinders silicon-based antennas from achieving high performance. Aiming at the above problems, [PERSON] et al.