## 5 Research Trends in Ge Photodetectors
### Remaining Technical Issues and Future Research Trends
#### 5.5.2 Monolithic Integration of Ge Photodetectors with CMOS Integrated Circuits  
Essential for future Si EPIC is the co-integration of Ge photodetectors with functional CMOS circuits, which brings optical detection and further signal processing together. Therefore, there has been much effort in pursuing such integration. However, fabrication of high performance Ge photodetectors together with conventional CMOS devices comes with several technical issues that must be addressed, including the thermal budget issue, the cross contamination issues and the non-planarity issue due to Ge layer thickness. To avoid the high temperatures needed during two-step Ge growth and subsequent cyclic annealling for dislocation density reduction, thermal evaporation polycrystalline Ge with full compatibility with CMOS fabrication due to its deposition temperature as low as \(\sim\)300 \({}^{\circ}\)C was demonstrated [6]. However, the relatively inferior electrical quality of the Ge limits the performance of the photodetector making this technique not suitable for high-speed high efficiency Si EPIC for future data transmission. Another study [38] uses a wire-bonding technique to connect separately-manufactured Ge photodetectors and a Si CMOS amplifier (see Figure 10). While this approach reduces the process complexity and cost considerably, undesirable large parasitic capacitance from the bonding pad and inductance from the bonding wire inevitably sacrifice the speed performance. [PERSON] _et al_. [24] reported the first successful monolithic integration of a Ge photodetector with CMOS on the same wafer (Figure 11). Special attention was given to the thermal budget planning in the process design. Since high temperature is compulsory for gate oxide growth, Ge grow was inserted after the gate processing. Furthermore, to avoid damage by high temperature Ge layer epitaxy, reduced-press chemical vapor deposition (RPCVD) at 350 \({}^{\circ}\)C was used. Also, no high temperature annealling was carried out. To address the non-planarity issue normally induced by thick Ge of several microns used for efficient light absorption, a waveguided photodetector with a thin Ge layer of \(\sim\)200 nm was used. Since with low temperature Ge growth and no curing annealling, the  
Figure 10: Optical micrograph showing a Ge-on-SOI photodiode wire-bonded to a high-gain CMOS IC. High-magnification optical and SEM micrographs of the photodiode are also shown. From [38]. fabricated 25 um-long detector demonstrated large dark current of 10 \(\upmu\)A _@_\(-\)1 V and relatively low responsivity of \(\sim\)0.6 A/W at 1,554 nm. Figure 11: A four-channel, 10 Gbps monolithic optical receiver in 130 nm CMOS with integrated Ge waveguide photodetectors. From [24]. Figure 12: **(a)** Schematic showing the “electronic-first and photonic-last” integration approach for monolithically fabricating the Ge p-i-n photodetector and Si CMOS circuit on common SOI platform. **(b)** Comparable threshold voltages were observed in both n-MOS and p-MOS transistors despite the introduction of an additional thermal budget during the Ge epitaxy growth. From [75]. The impact of high temperature prebake treatment before Ge epitaxy on the monolithic integration was studied by [PERSON] _et al_. [75]. For UHVCVD Ge epitaxy, an 800 \({}^{\circ}\)C prebake before actual growth is usually necessary for removal of native oxide from Si surface to ensure Ge epitaxy quality. However, such high temperature causes thermally enhanced dopant diffusion in CMOS devices leading to possible shift in transistor's threshold voltage (V\({}_{\text{th}}\)). This concern is especially the case for short channel devices since the impact of dopant diffusion is larger. It was found that for transistors with effective channel length of \(\sim\)180 nm, the additional 800 \({}^{\circ}\)C thermal budget virtually have no apparent impact on the V\({}_{\text{th}}\) (Figure 12(b)).