## 5 Security Analysis
### Bit Error Analysis  
A bit error is a bit that flips between the binary values 0 and 1, when generating it multiple times consecutively. Such bit flips degrade both the reliability and uniqueness metrics. We have already discussed this coherence before in our reliability investigations. However, when evaluating fabricated PUFs, very often it might be useful to investigate the bit errors/flips that occur due to ambient temperature changes or supply voltage fluctuation over time. For that reason, we calculate the bit errors in percent for each PUF core that occurred during repeated response measurements. The bit error \(BE_{n}\) for PUF instance \(n\) is defined as the sum of all \(HD\)s between its reference response \(R_{ref,n}\) and \(W\) measured responses \(R^{\prime}_{n,w}\) for the same reference challenge, both of the length \(L\in\mathbb{N}\):  
\[BE_{n}=\frac{1}{W}\sum_{w=1}^{W}\frac{HD(R_{ref,n},R^{\prime}_{n,w})}{L}\times 1 00\%. \tag{11}\]  
Figure 8: PUF uniformity box plot.  
This metric can be considered as an extension of reliability and uniqueness evaluation. Hereby, bit errors can be investigated and made visible easier when analyzing PUF responses core by core.  
Even when using a differential bit generation approach as in our PUF, bit errors might still occur due to changing environmental conditions and random noise. In some cases, the comparator input voltages differ very slightly, which potentially results in bit flipping over time, directly causing degradation of the reliability and uniqueness metrics. When using PUFs for unique ID generation, i.e., in identification applications, a typically applied approach is to define a binning technique in order to distinguish between individual IDs. The higher the amount of flipped bits within an ID, the less the uniqueness. As a consequence, low uniqueness leads to enlarged bins in the binning model. For that reason, we evaluate bit errors of PUF across the ambient temperature range from \(-20\,\mathrm{\SIUnitSymbolCelsius}\) to \(80\,\mathrm{\SIUnitSymbolCelsius}\) in \(20\,\mathrm{\SIUnitSymbolCelsius}\) steps. We measured 125 responses per core by applying a fixed reference challenge (full readout) to the PUF. Figure 9 shows the bit errors in percent for 10 PUF cores measured in a climatic chamber (test cases \(P_{1}\) to \(P_{6}\)). The plot shows increased bit error values at \(-20\,\mathrm{\SIUnitSymbolCelsius}\) and \(80\,\mathrm{\SIUnitSymbolCelsius}\) for certain PUF cores, which denotes the maximum ratings in terms of operating temperature. Core 9 shows a slightly increased bit error value at \(20\,\mathrm{\SIUnitSymbolCelsius}\). This can be explained by the corresponding voltage measurements at the comparator input terminals. The voltage difference \(\Delta V_{comp}\) for bit position \(r_{12}\) differs only a little and sometimes turns from positive to negative (flipping between logical 0 and 1).  
In a second experiment, we explored the bit errors independent of the evaluation board used. Therefore, we measured 30 physical PUF core instances at nominal conditions (test case \(P_{11}\)) by utilizing two Evaluation Boards A and B, respectively. Figure 10 shows the corresponding bit error values. Core 20 shows the greatest bit errors, which we have already explained in our reliability discussion earlier in this paper. The bit errors remain almost stable if comparing the measurements for both Evaluation Boards with each other. Moreover, core 16 shows the maximum deviation between Evaluation Board A and B with \(\Delta BE_{16}=0.34\%\), which is still below 0.5% and hence negligible low.  
Figure 10: Bit errors across different PUF core instances and Evaluation Boards A and B.  
Figure 9: Bit errors over ambient temperature.