## 5 Security Analysis
### Reliability Analysis  
The reliability metric is a crucial factor in providing a robust outcome under environmental variances and disturbances, keeping a PUF response stable by minimizing the need for post-processing due to software-sided error correction [11]. The reliability \(REL_{n}\) for PUF instance \(n\) is calculated on the digital output level, as stated in Equation (4) [32]:  
\[REL_{n}=100\%-\frac{1}{T}\sum_{t=1}^{T}\frac{HD(R_{ref,n},R^{\prime}_{n,t})}{ L}\times 100\%, \tag{4}\]  
where \(R_{ref,n}\) describes the reference response at nominal conditions, meaning the nominal supply voltage and ambient temperature conditions at room temperature, whilst \(R^{\prime}_{n,t}\) describes the PUF response for \(T\) different ambient conditions and different supply voltages. The response bit width is \(L\in\mathbb{N}\) and the ideal value for reliability is 100% [32]. To decompose the response on the analog level, we look at the reliability solely based on the Hamming distance \((HD)\), as shown in Equation (5) for sub-response \(r_{k}\). Thereby, \(x_{l}\) and \(y_{l}\) define bit strings of equal length \(L=28\) that are compared bitwise against each other:  
\[HD=\sum_{l=0}^{L-1}(x_{l}\oplus y_{l}). \tag{5}\]  
Furthermore, we define states for voltages \(V_{comp,z}\) and \(V_{out,q}\) according to Equations (6) and (7), resulting in Equation (8):  
\[V_{comp,+} =V_{out,a}+V_{e,+}, \tag{6}\] \[V_{comp,-} =V_{out,b}+V_{e,-},\] (7) \[\Delta V_{comp} =V_{comp,+}-V_{comp,-}. \tag{8}\]  
The sub-response generated by the comparator is given as:  
\[r_{k}= \begin{cases}1&\text{for }V_{comp,+}>V_{comp,-},\\ 0&\text{for }V_{comp,+}<V_{comp,-}.\end{cases} \]  
\begin{table}
\begin{tabular}{c c c c c c c c c c c c} \hline \hline  & **Test** & & \multicolumn{3}{c}{**Ambient Temperature**} & \multicolumn{3}{c}{**VDDcore**} & \multicolumn{3}{c}{**Vin**} \\  & **Case** & \(-\)**20 °C** & **0 °C** & **20 °C** & **25 °C*** & **40 °C** & **60 °C** & **80 °C** & **0.9 V** & **1.0 V** & **1.1 V** & **0.9 V** & **1.1 V** \\ \hline  & \(P_{1}\) & \(\times\) & & & & &  
The maximum reliability (with \(HD=0\)) of the PUF is therefore achieved for the cases \(\tilde{r}_{k}\in\{x_{l},y_{l}\}\):  
\[\tilde{r}_{k}= \begin{cases}1&\text{for }(V_{out,a}>V_{out,b})\wedge(V_{comp,+}>V_{ comp,-}),\\ 0&\text{for }(V_{out,a}<V_{out,b})\wedge(V_{comp,+}<V_{comp,-}).\end{cases} \]  
This emphasizes the necessity of a design level co-optimization between the minimization of the readout path's error voltage \(V_{e,z}\) and its impact on the actual compared voltage at \(V_{comp,z}\) along with the maximization of \(V_{out,d}\)[9; 20; 33]. These constraints help to reduce unstable or even false detected bits already at design level. As for the error voltages, the best case would be \(\Delta V_{e}=V_{e,+}-V_{e,-}=0\) V. Nonetheless, this case remains unlikely for our system, as the comparator's input offset voltage limits the safely detectable voltage difference. However, to obtain a high similarity in each readout path for our system, resistors with equal temperature coefficients and low variation are incorporated. Moreover, the effect of leakage currents and resulting offset voltage errors are kept as low as possible. The deployed comparator has low input offset voltage and low input leakage currents, thus resulting in a systematic minimization of the error induced by the control logic. The experimental measurement data of the voltage difference at the comparator input terminals \(\Delta V_{comp}\) over the specified temperature range (test cases \(P_{1}\) to \(P_{6}\)) of ten PUF cores is visualized in Figure 4(a). The data shown in this plot corresponds to the voltage differences reached at each temperature level, readout over 125 challenge-response cycles, which already provides sufficient statistics for a narrow distribution of the reliability metric discussed later in this paper (see Figure 6).