# Configurable Hardware Core for IoT Object Detection
## 5 Results
### Performance of the Accelerator  
The Tiny-YOLOv3 was executed in the proposed accelerator with the configurations referenced in Table 5 but with full on-chip memory; that is, the on-chip memory to cache the input feature maps was maximized for all configurations (see the configuration parameters in Table 7).  
All architectures were synthesized with a clock frequency of 100 MHz and tested with Tiny-YOLOv3 (see the performance results in Table 8 and Figure 9).  
The most efficient solutions use 13 cores per column, since the size of feature maps are a multiple of 13. The A6 and A5 configurations use the same number of cores, but A6 is faster since the lower number of cores per column improves the efficiency. Both A8 and A2 architectures have the same number of cores, but architecture A8 is for 16-bit quantization. The 8-bit architecture is slightly faster and consumes fewer resources at the cost of 0.7 pp in accuracy.  
\begin{table}
\begin{tabular}{l c c c c c c c c} \hline \hline
**Parameter** & \multicolumn{8}{c}{**Accelerator**} \\ \hline Architecture & A1 & A2 & A3 & A4 & A5 & A6 & A7 & A8 \\ \hline nCols & 8 & 4 & 2 & 8 & 4 & 8 & 4 & 4 \\ \hline nRows & 13 & 13 & 13 & 8 & 8 & 4 & 4 & 13 \\ \hline nMACs & \multicolumn{8}{c}{4} \\ \hline DDR\_ADDR\_W & \multicolumn{8}{c}{32} \\ \hline DATAPATH\_W & \multicolumn{8}{c}{8} \\ \hline MEM\_BIAS\_ADDR\_W & \multicolumn{8}{c}{3} \\ \hline MEM\_WEIGHT\_ADDR\_W & \multicolumn{8}{c}{14} \\ \hline MEM\_TILE\_ADDR\_W & 15 & 15 & 15 & 15 & 15 & 16 & 16 & 15 \\ \hline MEM\_TILE\_EXT\_ADDR\_W & \multicolumn{8}{c}{15} \\ \hline \hline \end{tabular}
\end{table}
Table 7: Configuration parameters for the accelerator.  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline
**Arq** & **A1** & **A2** & **A3** & **A4** & **A5** & **A6** & **A7** & **A8** \\ \hline Exec. (ms) & 68 & 135 & 268 & 129 & 259 & 246 & 492 & 140 \\ FPS & 14.7 & 7.4 & 3.7 & 7.8 & 3.9 & 4.1 & 2.0 & 7.1 \\ FPS/core & 0.14 & 0.14 & 0.14 & 0.12 & 0.12 & 0.13 & 0.13 & 0.14 \\ \hline \hline \end{tabular}
\end{table}
Table 8: Tiny-YOLOv3 execution times on the proposed architecture with different configurations of the core matrix.  
Table 9 presents the Tiny-YOLOv3 network execution times on multiple platforms: Intel i7-8700 @ 3.2 GHz, GPU RTX 2080 ti, and embedded GPU Jetson TX2 and Jetson Nano. The CPU and GPU results were obtained using the original Tiny-YOLOv3 network [42] with floating-point representation. The CPU result corresponds to the execution of Tiny-YOLOv3 implemented in C. The GPU result was obtained from the execution of Tiny-YOLOv3 in the Pytorch environment using CUDA libraries.  
The Tiny-YOLOv3 on desktop CPUs is too slow. The inference time on an RTX 2080 ti GPU showed a 109 speedup versus the desktop CPU. Using the proposed accelerator, the inference times were 140 and 68 ms, in the ZYNOQ7020. The low-cost FPGA was 6X (16-bit) and 12X (8-bit) faster than the CPU with a small drop in accuracy of 1.4 and 2.1 points, respectively. Compared to the embedded GPU, the proposed architecture was 15% slower. The advantage of using the FPGA is the energy consumption. Jetson TX2 has a power close to 15 W, while the proposed accelerator has a power of around 0.5 W. The Nvidia Jetson Nano consumes a maximum of 10 W but is around 12\(\times\) slower than the proposed architecture.