# Design and Development of an Embedded Controller for a Hydraulic Walking Robot WLBOT
## 4 Embedded Controller Software Design  
### Software Architecture  
As the essential part of the control system, the software component is supposed to take responsibility for the reasonable arrangement of multiple tasks. The control frequency of the embedded controller affects the accuracy and stability of the robot control. It's vital to utilize the CPU resources effectively, select the interrupt cycle and configure the priority reasonably. The software program consists of the main program module and four interrupts, which are shown in Figures 6 and 7. The interrupt priority is configured in Table 1 and makes the interrupt service routine (ISR) run properly. The flow chart of the main program is shown in Figure 6. When the embedded controller is powered on, the main program will start. The initialization will be implemented firstly and CAN receive interrupt will also be enabled to wait for a command from PCM-3365. When the controller gets a start command, it will set the flag \"Start\". After that, both ADC1 and ADC3 sampling and interrupt will be enabled as well as the control interrupt. Then the main program will be waiting for the interrupt until the stop command comes. When it comes to the stop command, all the interrupts and ADC sampling will be disabled and the DAC output will be set to zero to avoid servo valves' misoperation. Before the end, all the test data will be copied from the external SRAM to the SD card for further study. There are four interrupts as Table 1 shows and the flow chart of ISR is illustrated in Figure 7. When the CAN receive interrupt comes, the controller reads data from PCM-3365 and makes different responses according to different commands. Especially, when it gets a start command, the control strategy will be stored. In ADC1-DMA and ADC3-DMA interrupt, the sampling data will be processed in the median and mean filtering. After that, the processed data will be stored in the temporary arrays for the control algorithm to use. As for the control interrupt, the control algorithm will be calculated and all the processed data will be stored in external SRAM for further use. Figure 6: The flow chart of the main program. Research on the Relationship Between ADC-DMA Interrupt Cycle, Sampling Data Volume, and ADC Sampling Rate  
As we need to sample 14 sensor signals, we select both ADC1 and ADC3 controllers while each controller can offer seven sampling channels. ADC1 selects DMA2 stream0 and ADC3 selects DMA2 stream1. When it comes to a start command from PCM-3365, the embedded controller starts continuous sampling. When the data buffer of each DMA is full, an interrupt will be triggered. For the configuration of DMA in ADC sampling, we can reduce the burden of CPU, which greatly improves the embedded controller's efficiency. For STM32F4 series chips, the total ADC conversion time \(T_{cv}\) is calculated as follows:  
\[T_{cv}=\text{Sampling time}+12\text{ cycles} \tag{1}\]  
The shortest sampling time can be configured as three cycles. Though the extension of the sampling time will improve the accuracy of sampling, it reduces the AD conversion rate. Since the maximum frequency of STM32F40/ZGT6 is 168 MHz, to ensure the accuracy of sampling, ADCCLK prescaler is configured to a division factor of 4, and thus the maximum sampling clock frequency is 21 MHz. The ADC-DMA interrupt cycle \(T_{it}\) can be calculated as follows:  
\[T_{it}=NdT_{cv}=\frac{Nd}{f_{s}} \tag{2}\] \begin{table}
\begin{tabular}{c c c} \hline \hline
**Interrupt** & **Preemption Priority** & **Subpriority** \\ \hline Control interrupt & 1 & 0 \\ CAN receive interrupt & 1 & 1 \\ ADC1–DMA interrupt & 2 & 0 \\ ADC3–DMA interrupt & 2 & 1 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Configuration of interrupt priority. Figure 7: The flow chart of ISR. where \(N\) is the number of ADC sampling channels, \(d\) is the sampling data volume of each channel when the data buffer of DMA is full, and \(f_{s}\) is the actual sampling rate. Our primary selection is \(d=100\).