# Numerically Optimized Fourier Transform-Based Beamforming Accelerated by Neural Networks
## 5 Replacing Optimization Algorithms by Trained ANNs
### Generating Datasets for CTRLNN Training  
For the CTRLNN sub-blocks, the training dataset was generated using the analytical model of a varactor-controlled PMS that we have developed in an earlier work of ours [29]. The structure of the PMS is depicted in Figure 12a. The unit cell is inside a dashed square in this figure. The unit cells are squares with the size of 6.8 \(\times\) 6.8 mm\({}^{2}\). As compared to [28], the patch size \(w\) can be reduced from 3 mm to 1.3 mm to enable a higher operating frequency of 10 GHz. The independent units to which the control voltages are applied can be either single unit cells of the PMS or groups of unit cells. The figure also shows \(X\)- and \(Y\)-controlling lines to which pulsed control voltage can be applied. For more details on the control network layout and operation, the reader is referred to [29].  
The top layer of the PMS contains a chessboard-like array of square patches loaded with varactors at the patch corners. The layers with \(X\)- and \(Y\)-controlling lines and other elements (filtering and memory capacitors [29]) are located below. By analyzing this structure, we can relate the required reflection phases to the necessary input bias voltages applied to the varactors. Indeed, the bias voltage determines the varactor diode junction capacitance that in turn determines the resonant frequency of the cell and the local reflection phase [29]. We use these relations to generate the datasets for the CTRLNN.  
The complex reflection coefficient at every unit cell is calculated using the analytical model developed in [29]. The diode junction capacitance varies with the applied reverse bias approximately as  
\[C=C_{0}(V/\varphi_{\mathrm{I}}+1)^{-\gamma}, \tag{14}\]  
where \(C_{0}=1.09\) pF is the varactor diode capacitance at \(V=0\) V, and \(\gamma=0.68\) is the slope of the \(\log C\) vs. \(\log V\) curve (Figure 12b). The value of the built-in junction potential \(\varphi_{\mathrm{I}}\) is  
Figure 12: (**a**) Geometry of the PMS. The dashed square delimits a unit cell of the structure. The period of the structure \(d=6.8\) mm. The wire radius is \(r_{0}=0.3\) mm and the patch width is \(w=3\) mm for a PMS operating at 5 GHz and \(w=1.3\) mm at 10 GHz. (**b**) Capacitance vs. voltage for the varactor diode model MA46H120 simulated in Agilent ADS.  
about 0.7 V for Si and 1.3 V for GaAs at room temperature. Figure 12b shows the junction capacitance as a function of bias voltage for the varactor diode used for modeling [29].  
From Equation (14), the reverse voltage is  
\[V=\Big{(}(C_{0}/C)^{1/\gamma}-1\Big{)}\varphi\eta. \tag{15}\]  
The phase of complex electric field reflection coefficient can be computed as  
\[\varphi=\angle R_{\mathrm{s}}^{TM}=\angle\bigg{(}\frac{1-Y_{\mathrm{s}}^{TM} \cos\theta}{1+Y_{\mathrm{s}}^{TM}\cos\theta}\bigg{)}, \tag{16}\]  
where \(Y_{\mathrm{s}}^{TM}\) is the normalized complex input admittance of the MS structure understood as a parallel connection of the surface admittance of the varactor-loaded patch grid and the input admittance of a wire medium slab [29].  
For generating the datasets to train the CTRLNN sub-blocks, the reflection phases obtained by this analytical model are imported into the CTRLNN model as training inputs. The corresponding varactor bias voltages are the outputs of this training model. Like before, about 70% of the dataset is used to train the CTRLNN, and the remaining data are utilized for validation. The output neurons of the CTRLNN produce the values of bias voltages in the range from 1 to 9 V.