# Improving Hardware in LUT-Based Mealy FSMs
## 5 Example of Synthesis
\begin{table}
\begin{tabular}{c c c c c c} \hline \(a_{m}\) & \(a_{T}\) & \(Y_{m}\) & \(Y_{T}\) & \(P_{g}\) & \(g\) \\ \hline \(a_{1}\) & \(a_{2}\) & \(Y_{0}\) & \(Y_{1}\) & \(P_{1}\) & 1 \\ \hline \(a_{1}\) & \(a_{3}\) & \(Y_{0}\) & \(Y_{2}\) & \(P_{2}\) & 2 \\ \hline \(a_{2}\) & \(a_{3}\) & \(Y_{1}\) & \(Y_{3}\) & \(P_{3}\) & 3 \\ \hline \(a_{2}\) & \(a_{4}\) & \(Y_{1}\) & \(Y_{2}\) & \(P_{4}\) & 4 \\ \hline \(a_{2}\) & \(a_{5}\) & \(Y_{1}\) & \(Y_{4}\) & \(P_{5}\) & 5 \\ \hline \(a_{3}\) & \(a_{4}\) & \(Y_{2}\) & \(Y_{5}\) & \(P_{6}\) & 6 \\ \hline \(a_{3}\) & \(a_{4}\) & \(Y_{3}\) & \(Y_{5}\) & \(P_{7}\) & 7 \\ \hline \(a_{4}\) & \(a_{5}\) & \(Y_{2}\) & \(Y_{4}\) & \(P_{8}\) & 8 \\ \hline \(a_{4}\) & \(a_{1}\) & \(Y_{2}\) & \(Y_{0}\) & \(P_{9}\) & 9 \\ \hline \(a_{4}\) & \(a_{5}\) & \(Y_{5}\) & \(Y_{4}\) & \(P_{10}\) & 10 \\ \hline \(a_{4}\) & \(a_{1}\) & \(Y_{5}\) & \(Y_{0}\) & \(P_{11}\) & 11 \\ \hline \(a_{5}\) & \(a_{1}\) & \(Y_{4}\) & \(Y_{0}\) & \(P_{12}\) & 12 \\ \hline \end{tabular}
\end{table} 
Table 4: Table of pairs \(P_{g}\) for Mealy FSM \(U_{3}(S_{1})\). \begin{table}
\begin{tabular}{c c c c c} \hline \(a_{m}\) & \(K(a_{m})\) & \(X_{h}\) & \(Z_{h}\) & \(h\) \\ \hline \(a_{1}\) & 000 & \(x_{1}\) & \(z_{1}\) & 1 \\  & & \(\overline{x_{1}}\) & \(z_{3}\) & 2 \\ \hline \(a_{2}\) & 001 & \(x_{1}\) & \(z_{1}z_{2}\) & 3 \\For example, the following relations take places for the first row of Table 4: \(Y_{m}=Y_{0}\), \(Y_{T}=Y_{1}\) and \(a_{T}=a_{2}\). As follows from Figure 8, there are the codes \(K(Y_{0})=000\) and \(K(Y_{1})=100\). As follows, for example, from Table 5, there is the state code \(K(a_{2})=001\). So, the column \(T_{g}\) of Table 6 contains the symbol \(T_{3}\) for the row \(g=1\). All other rows are filled in the same manner. Using the table of \(LT\), the SBF (12) is derived. The SOPs of corresponding functions include the terms (13). In the discussed case, this is the following SBF:  
\[ \begin{array}{l}T_{1}=P_{5}\lor P_{8}\lor P_{10}=v_{1}\;\overline{v_{2}}\; \overline{v_{3}}\;\overline{z_{1}}\;z_{2}\lor\overline{v_{1}}\;\overline{v_{2 }}\;v_{3}\;\overline{z_{1}}\;z_{2}\;\lor v_{1}v_{3}\;\overline{z_{1}}\;z_{2}; \\ T_{2}=P_{2}\lor P_{3}\lor P_{4}\lor P_{6}\lor P_{7};\\ T_{3}=P_{4}\lor P_{6}\lor P_{7}.\end{array}  \tag{18}\]  
_Step 9_. To obtain the LUT-based circuit of Mealy FSM \(U_{3}(S_{1})\), the step of technology mapping should be executed [31]. This can be done only with the help of some industrial CAD tools. In the case of Virtex-7-based circuits, the industrial package Vivado [47] should be used. This CAD tool executes the process of technology mapping. As a result, we can extract the real characteristics of an FSM circuit (such as the LUT count, number of slices, number of flip-flops, maximum operating frequency, and power consumption) from the Vivado reports. This CAD tool can be used starting from the FPGAs of the Virtex-7 family. So, it is impossible to use Vivado for implementing the circuit of FSM \(U_{3}(S_{1})\) using LUTs with four inputs. In the next section, there are shown the results of experiments conducted with the help of the industrial CAD package Vivado and the library of standard benchmark FSMs [56].