## 1 Introduction  
The Large Hadron Collider (LHC) provides proton-proton collisions, at the centre of mass energies up to \(\sqrt{s}=13\) TeV, which are studied by four large experiments: ATLAS [1], CMS [2], LHCb [3], and ALICE [4] (focused mainly on ion-ion collisions). New Physics phenomena may be studied via direct searches (production of new particles) or indirect ones where we concentrate on precise measurements of selected observables and compare the results with the Standard Model predictions. In both scenarios, the task of discovering New Physics requires, for instance, very precise and robust tracking systems that are able to provide a momentum measurement with very high resolution (typically better than one percent). This in turn, sets also stringent demands on the quality and functionality of the readout electronics. The upgrade of the LHC machine will be capable of delivering more than an order of magnitude higher luminosity than presently utilised by the Large Hadron Collider beauty (LHCb) detector [5]. To conform with higher luminosity and the fully software-based trigger, all sub-detectors require front-end electronics that provide readout at the LHC bunch-crossing rate of 40 MHz [6]. The Upstream Tracker (UT) is a new sub-detector within the LHCb experiment. It plays a critical role in the software trigger, enabling a fast estimate of the momentum of charged particles produced in the \(pp\) collisions. It is based on silicon strip sensors organised in two pairs of planes with a small 5\({}^{\circ}\) tilt between the strips within a pair [6]. The detector area is predominantly covered by 97 mm \(p^{+}\)-in-\(n\) strips with 190 um pitch. In the vicinity of the beam pipe sensors doping is reversed to \(n^{+}\)-in-\(p\) for high radiation resistance and the density of the strips is doubled. Additionally, in the central area with the highest occupancy of particles, the strip length is reduced in half to reduce ambiguities in the pattern recognition. All strip sensors in the UT will be read out by a new dedicated 128-channel Application Specific Integrated Circuit (ASIC) called SALT (Silicon ASIC for LHCb Tracking) [7]. The specifications of the SALT, based on the expected sensor characteristics and the operating conditions, are shown in Table 1.  
The SALT chip is one of the first multi-channel low-power readout ASICs deployed in an High Energy Physics (HEP) experiment that features a fast Analog-to-Digital Converter (ADC) in each channel. Such an architecture was not possible to realise in the past, mainly due to high power consumption of the ADC. Recently, with advanced CMOS technologies and development of very low-power ADC architectures, it has become possible, and different groups started to develop readout ASICs [8; 9; 10; 11; 12] using such architecture. The latest trend is to add, beyond the amplitude measurement, timing information to the \begin{table}
\begin{tabular}{l l} \hline \hline
**Variable** & **Specification** \\ \hline Technology & CMOS 130 nm \\ Channels per ASIC & 128 \\ Power dissipation per channel & \(<\)6 mW \\ Radiation hardness & 30 Mrad TID + TMR against SEE effects \\ \hline Sensor input capacitance & 1.6–12 pF \\ Signal to Noise ratio & \(>\)10 for MIP \\ Input signal polarity & Both, positive and negative \\ Dynamic range & Input charge up to \(\sim\)30,000 e\({}^{-}\) \\ Pulse shape and tail & \(T_{peak}\sim\)25 ns, tail after 2 \(\times\)\(T_{peak}\sim\)5\% amplitude \\ \hline ADC bits & 6 bits (5 bits for each polarity) \\ ADC sampling rate & 40 MHz \\ DSP functions & Pedestal and common mode subtraction, zero suppression \\ Output data interface & Five serial links @ 320 Mbit/s (SLVS standard) \\ Slow controls interface & I\({}^{2}\)C \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Specifications of the SALT Application Specific Integrated Circuit (ASIC). readout [8; 11; 12].