# A Review of Sharp-Switching Band-Modulation Devices
## 5 Alternative Applications of Sharp Switching
### Dynamic Memory Cell: Operation as Capacitorless DRAM  
The \(Z^{2}\)-FET stands out as a competitive capacitor-less DRAM cell [13], especially for embedded applications, due to its full compatibility with standard FD-SOI CMOS process flow and low-voltage designs [33]. Its dynamic memory operation relies on transient modulation of the onset voltage V\({}_{\text{ON}}\)[34]. It is necessary to form the horizontal doping profile of the virtual NPNP Shockley diode (i.e., floating-body thyristor), by biasing the gate terminals [11]. The turn-on voltage V\({}_{\text{ON}}\) is modified by altering the carrier population within the body of the device. Normally, a high carrier density under the top gate, as in the DC regime, lowers the device turn-on voltage V\({}_{\text{ON-1}}\) as the height of the barrier is reduced. This is the standard memory '1'-state of the \(Z^{2}\)-FET. However, a short pulse on the front gate cannot quickly populate the body underneath, leading to a deep-depletion regime that yields an increased potential barrier, corresponding to a higher triggering voltage V\({}_{\text{ON-0}}\)[35]. This would be the '0'-state. The difference (V\({}_{\text{ON-0}}\)-V\({}_{\text{ON-1}}\)) defines the dynamic memory window, with a typical value of 200-300 mV (Figure 6). The \(Z^{2}\)-FET memory cell can be read out with an anode voltage pulse in the V\({}_{\text{ON-0}}\) < V\({}_{\text{A}}\) < V\({}_{\text{ON-1}}\) range: the current is high in the '1'-state (V\({}_{\text{A}}\) > V\({}_{\text{ON-1}}\)) and negligible in the '0'-state (V\({}_{\text{A}}\) < V\({}_{\text{ON-0}}\)) [34]. Figure 17a depicts the \(Z^{2}\)-FET dynamic memory for an \(n\)-type device (top gate located beside the \(P^{+}\) anode terminal), with virtual body doping induced by the top (V\({}_{\text{FG}}\)) and bottom (V\({}_{\text{BG}}\)) gates. Figure 16: N-type \(Z^{2}\)–FET DC curves showing the static memory operation. The anode current needed to hold the ‘1’-state limits the application of \(Z^{2}\)–FET-based single-transistor SRAM to low-density chips. In any DRAM cell, four main operations are performed: read, write, erase, and hold. The memory readout process (R) aims at discriminating the cell states based on the current level. The readout anode voltage V\({}_{\rm A}\) is set inside the dynamic memory window (see Figure 17b). In the '1'-state, the Z\({}^{2}\)-FET essentially behaves as a forward-biased PIN diode, with a large output current. Conversely, in the '0'-state, the central PN junction is reverse-biased and passes a very low leakage current. Hence extremely high current ratios I\({}_{1}\)/I\({}_{0}\) can be obtained, enabling easy memory state discrimination. It is worth noting that, as in most capacitorless alternatives (MSDRAM, A2 RAM, ZRAM,... [36; 37]), the readout process is based on current rather than voltage sensing. The holding phase (H) is expected to preserve the programmed memory states for as long as possible. A natural trade-off arises as a consequence of the dual goal of this operation; maintaining a high carrier concentration in the '1'-state and a low carrier concentration in the '0'-state. To save energy, the anode is grounded while the gates are biased to ensure the corresponding memory-state barrier conditions. Finally, the mechanisms to produce suitable carrier populations underneath the gate are known as write (W) and erase (E) operations. The carrier storage needed to program '1' is achieved by grounding the gate, thereby lowering the injection barrier, and then forward-biasing the cell with an anode pulse to allow carrier flow. The sudden building of the barrier with a positive top-gate bias pulse captures the flowing electrons under the gate. On the other hand, the carrier evacuation for writing the '0'-state is achieved through capacitive coupling, by grounding the top gate without any anode pulse; the carriers under the front gate are, thus, expelled [13]. Figure 18 shows an example of voltage pattern with all four operations and the anode current readout as a function of time.