# Error Mitigation Methods for FSM Using Triple Modular Redundancy
## 5 Experimental Results
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Name** & **In** & **Out** & **State** \\ \hline dk15 & 2 & 5 & 4 \\ lion & 2 & 1 & 4 \\ mc & 3 & 5 & 4 \\ s8 & 4 & 1 & 5 \\ tav & 4 & 4 & 4 \\ train4 & 2 & 1 & 4 \\ bbara & 4 & 2 & 10 \\ bbtas & 2 & 2 & 6 \\ beecount & 3 & 4 & 7 \\ dk14 & 3 & 5 & 7 \\ dk17 & 2 & 3 & 8 \\ dk27 & 1 & 2 & 7 \\ ex5 & 2 & 2 & 9 \\ ex6 & 5 & 8 & 8 \\ ex7 & 2 & 2 & 10 \\ lion9 & 2 & 1 & 9 \\ s27 & 4 & 1 & 3 (6) \\ shiftreg & 1 & 1 & 8 \\ dk512 & 1 & 3 & 15 \\ train11 & 2 & 1 & 11 \\ bbsse & 7 & 7 & 16 \\ cse & 7 & 7 & 16 \\ sse & 7 & 7 & 16 \\ ex2 & 2 & 2 & 19 \\ keyb & 7 & 2 & 19 \\ tma & 7 & 6 & 20 \\ s1 & 8 & 6 & 20 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Set of benchmarks. \begin{table}
\begin{tabular}{l c c c c c c c c c c c c c c c c c c c c} \hline \multicolumn{13}{c}{**Model 0**} & \multicolumn{1}{c}{**Model 1**} & \multicolumn{1}{c}{**Model 2**} & \multicolumn{1}{c}{**Model 3**} & \multicolumn{1}{c}{**Model 4**} & \multicolumn{1}  
\begin{table}
\begin{tabular}{c c c c c c c c c c c} \hline \hline  & \multicolumn{2}{c}{**Model 0**} & \multicolumn{2}{c}{**Model 1**} & \multicolumn{2}{c}{**Model 2**} & \multicolumn{2}{c}{**Model 3**} & \multicolumn{2}{c}{**Model 4**} \\
**Name** & **LUTs** & **Power [W]** & **LUTs** & **Power [W]** & **LUTs** & **Power [W]** & **LUTs** & **Power [W]** & **LUTs** & **Power [W]** \\ \hline dk15 & 17 & 1.424 & 17 & 1.424 & 52 & 0.221 & 17 &  
It is difficult to draw clear conclusions from Figure 14a. It can be seen that the results for Model 3 are somehow distorted (the complex redundancy of model 3 gives virtually the same results as the FSM in its simplest form--Model 0). The reason for this may be the complex logic resource sharing and optimization algorithms. It should be noted that the optimization process is a multi-stage process. It also includes placement and routing. This means that, in many cases, optimization in terms of placement or routing of connections can spoil the results of optimization in terms of the number of LUTs or power. The results for Models 2 and 4 seem reliable, but it is difficult to draw too far-reaching conclusions here. The situation is slightly different for power (Figure 14b). Here, as expected, the highest power is found for Models 3 and 4. An important conclusion from the analysis of this graph is that a significant expansion of the circuit with redundancy elements does not result in a significant increase in power. In the authors' opinion, it is more valuable and reliable to compare the results in the ABC system. The ABC algorithm is publicly available, whereas the Vivado system is a commercial tool and some of its algorithms are implicit. The synthesis in Vivado targets logic blocks with significant flexibility in the number of inputs. In ABC, fixed blocks with \(k=4\) are assumed. Taking this into account in the FSM synthesis (ABC), the use of TMR voters for safest architectures (Model 3 or 4) gives the most efficient results for model 4 (full triplication of the FSM). The results obtained for ABC and Vivado power are further presented in Tables 6 and 7, whereby the rightmost column corresponds to the arithmetic mean calculated for the TMR-derived models (Model 1-4). The results of the average obtained from all benchmarks for each model are presented in the last row of the table and in the bar charts in Figures 15 and 16, respectively. For the ABC system, the trend of individual benchmarks is maintained, with Model 3 having higher values than Model 4 (Table 6). The results of the average reflect this well--Figure 15. For the Vivado system, the individual cases (Table 7) vary quite a bit and do not preserve a common trend. In view of this, the average for Models 3 and 4 is very similar. It should be noted that the mean values for Model 3 and 4 are comparable and clearly worse than the average (Figure 16). Figure 14: Comparison of synthesis results in the Vivado system in terms of the number of LUT blocks (**a**) and power (**b**).