# A Ku-Band GaAs Multifunction Transmitter and Receiver Chipset
## 3 Circuit Blocks of the Ku-Band Multifunction Chipset
### Serial-to-Parallel Converter (SPC)  
As the number of digital control bits increases, the interconnection between the multifunction chip and the digital control unit becomes demanding, especially in a large-scale phased-array system. To alleviate the interconnection complexity, an SPC is integrated into the multifunction chip, which enables serial data input for controlling the 5-bit attenuator and 4-bit phase shifter.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameter** & **Design Value** & **Parameter** & **Design Value** \\ \hline M\({}_{1}\), M\({}_{4}\), M\({}_{8}\), M\({}_{9}\), M\({}_{14}\) & \(5\times 75\)-\(\mu\)m & L\({}_{1}\), L\({}_{3}\), L\({}_{9}\) & 212.7 pH \\ M\({}_{2}\), M\({}_{5}\), M\({}_{7}\), M\({}_{10}\), M\({}_{11}\), M\({}_{12}\), M\({}_{13}\), M\({}_{15}\) & \(5\times 125\)-\(\mu\)m & L\({}_{2}\), L\({}_{4}\), L\({}_{10}\) & 619.7 pH \\ M\({}_{3}\), M\({}_{6}\), M\({}_{16}\) & \(9\times 100\)-\(\mu\)m & L\({}_{5}\) & 102.1 pH \\ R\({}_{G}\) & 2.1 k\(\Omega\) & L\({}_{6}\) & 1.3 nH \\ C\({}_{1}\), C\({}_{2}\) & 205.4 fF & L\({}_{7}\), L\({}_{8}\) & 513.4 pH \\ \hline \hline \end{tabular}
\end{table}
Table 2: Design parameters of the 4-bit digital phase shifter.  
Figure 8: Measurement results of the 4-bit digital phase shifter: (**a**) insertion loss and matching performance in the reference state, (**b**) phase shift for all 16 states, (**c**) input and output matching for all 16 states, (**d**) RMS phase and parasitic amplitude errors.  
Figure 9 shows a block diagram and micrograph of the 9-bit SPC. It consists of a 9-bit shift register, nine latches, three input voltage transformers (IVT) for serial data input (\(\mathrm{D_{in}}\)), clock (CLK), enable (EN), nine output voltage transformers (OVT) for control of the attenuator and phase shifter and one OVT for serial data output (\(\mathrm{D_{out}}\)).  
A simple direct-coupled FET logic (DCFL) is adopted for an inverter due to the small chip area and low DC consumption [21]. As shown in Figure 10a, the inverter consists of an E-mode switching HEMT and a D-mode load HEMT. By adding a 1-k\(\Omega\) resistor in series with the load transistor, static power consumption can be reduced while sacrificing the switching speed. The static DC current is 0.65 mA. The shift register is based on a conventional D-flip flop, as shown in Figure 10b. Figure 10c shows the schematic diagram of the latch. A diode-coupled feedback is added to the output of the latch. This compensates for the reduced voltage swing caused by the finite on-resistance of the E-mode HEMT of the inverter logic.  
The input signals (\(\mathrm{D_{in}}\), CLK, EN) follow the Transistor-transistor logic (TTL), which swings from 0 to 5 V. To transform the TTL level to the DCFL inverter level (0 to 1 V), the IVT is designed as shown in Figure 11a. Similarly, two OVTs are designed for two different purposes. The first OVT, shown in Figure 11b, transforms the DCFL level to the control level of the digital attenuator and phase shifter (\(-5\) to 0 V). The second OVT shown in Figure 11c transforms the DCFL level back to the TTL level. The SPC test cut shown in Figure 9 occupies an area of \(1.8\times 0.8\) mm\({}^{2}\), excluding probing pads, and consumes DC power of 350 to 415 mW depending on the input data.  
Figure 10: Schematics of (**a**) the inverter, (**b**) shift register, (**c**) latch.  
Figure 9: Block diagram and chip micrograph of the 9-bit SPC.