## 2 Related Works  
The goal of topology reconfiguration is to determine the mapping from virtual locations to physical cores to re-establish a consistent logical connectivity for high-level applications. In recent years, researchers have proposed various optimization algorithms to address the topology reconfiguration challenge in NoCs. [PERSON] et al. introduced the Row-Wave Column Borrowing (RRCS) algorithm [23], which was later optimized by [PERSON] et al. to include a bidirectional search in the local neighborhood, addressing the suboptimal solutions resulting from one-way searches [24]. [PERSON] et al. proposed the CRS-TS algorithm, which generates an initial topology using the CRS algorithm with row double-shift and column-shift operations, followed by optimization through a forbidden search technique [25,26]. Building on these, [PERSON] et al. compared these algorithms and developed a two-stage topology reconfiguration algorithm that employs core-level redundancy. This approach includes a greedy strategy and an intelligent optimization method based on the memetic algorithm, both designed to refine the initial topology for improved communication performance [27]. However, although these algorithms can achieve a better reconfiguration of the logical topology, there is no guarantee that the logical topology is exactly the same as the physical topology, as the positions of the routers and cores may change throughout the topological structure. To address this issue, a 2D REmesh structure was proposed for logical topology reconfiguration. This structure guarantees consistency between the logical and physical topology, enabling complete reconfiguration of the logical topology. Furthermore, the proposed core mapping methodology, initially developed for 2D mesh architectures,demonstrates adaptability to other regular topologies through targeted structural modifications. For honeycomb configurations, axial coordinate systems and tri-directional routing protocols are essential to leverage hexagonal symmetry, though non-Manhattan interconnects introduce wiring complexity and congestion management challenges [28]. Circulant and Spidergon topologies require cyclic channel allocation and modulo-based addressing to align with circular symmetry, yet their limited path redundancy increases fault recovery latency and arbitration overhead [29; 30]. While the regularity of mesh architectures inherently simplifies deterministic mappings, extending these principles to non-orthogonal topologies necessitates balancing algorithmic generality with architectural trade-offs, particularly in optimizing communication locality and fault resilience [31]. Building upon this foundation, an optimized topology reconfiguration bidirectional searching fault-tolerant algorithm for REmesh network-on-chip (BSTR) was proposed [32]. The algorithm categorizes routers and assigns connections to the corresponding cores. By employing a bidirectional search, it overcomes the limitation of the original TRADE algorithm which only considers unidirectional searches, enhancing the success rate of topology reconfiguration. Similarly, a novel topology reconfiguration backtracking algorithm for 2D REmesh networks-on-chip (BTTR) based on the same structure was proposed [33]. This algorithm considers both core allocation and router placement, utilizing recursive backtracking with pointers for searching, which enables dynamic reconfiguration with advanced fault tolerance capabilities. However, these algorithms also have the following limitations:  
1. They do not adequately take into account the spatial distribution of faulty cores, potentially leading to suboptimal solutions;
2. They exhibit higher computational complexity and cannot maintain a balance between the topology reconfiguration rate and the topology recovery time;
3. They could achieve a higher resuccess rate of topology reconfiguration for low-scale, low-fault-rate topology, but it may not be applicable to high-scale, high-fault-rate topology in embedded systems.