## 1 Introduction  
With the advancements in semiconductor technology, highly integrated and miniaturized designs of semiconductors are being used to improve the overall performance of the devices. In this regard, the high aspect ratio (HAR) patterns prevail with the aim to reduce critical dimensions in the current semiconductor manufacturing processes. Plasma etching techniques such as reactive ion etching (RIE), which employs reactive ionized gases in the plasma, are used for HAR patterning. Studies have examined the importance of suppressing lateral etching and increasing vertical etching in HAR silicon etching so as to achieve a smooth vertical sidewall profile with a high etch rate and selectivity [1]. When the aspect ratio of the etch pattern is increased, 3D-NAND flash memory products have exhibited feature distortions, such as twisting, bowing, and edge roughening [2]. These etch pattern distortion problems are caused by the energetic ions in the plasma, as observed in the retarded etch rate in the high aspect ratio contact (HARC) pattern etch process due to ion charging inside shallow and deep contract holes. This etch rate retardation can be overcome by employing high frequency bias power in semiconductor etch equipment to increase plasma potential in HARC pattern etch so as to increase the ion bombardment energy across the plasma sheath. Ion energy distribution and ion angular distribution that enters a wafer perpendicular to the plasma sheath surface are controlled using low-frequency bias power [3,4]. When the bias power is increased to the level of a few kilowatts, surface collision with the wafer surface increases, causing the heated ions to become uncontrollable which results in the distorted etch sidewall profile. From the thermal perspective, the increased wafer surface temperature may lead to undesirable chemical reactions, and the thermal stress caused by temperature variation or differences in the coefficient of thermal expansion in 3D multilayer structures such as the Oxide/Nitride/Oxide (ONO) stack process may lead to wafer warpage [5,6]. The etched feature profile and critical dimension uniformity are controlled via the temperature of wafer-in-process (WIP) [7]. Wafer-temperature uniformity can create multiple integrated circuits (ICs) that have the etch profiles required for a wafer. Research is being conducted to control wafer-temperature uniformity from the component perspective. In the case of electrostatic chuck that is in direct contact with the wafer, a multi-physics simulation including backside gas flow was investigated to improve WIP temperature uniformity for etch equipment [8]. Studies have also proposed methods to improve WIP temperature uniformity based on the heat transfer or the cooling path shape of the chuck for the contact region between electrostatic chuck and wafer [9, 10, 11, 12]. In addition, the wafer-temperature uniformity is also improved by tuning the height and the baffle shape of the edge ring [13]. Previous research works have showed that controlling WIP temperature is a key parameter to ensure the etching profile in HARC. The etch process employs reactive ionized gas species, such as SF\({}_{6}\), Cl\({}_{2}\), or C\({}_{4}\)F\({}_{8}\) with a mixture of additive gases of O\({}_{2}\), N\({}_{2}\), He, Ar, etc. The ratio and flow rate of the injected gases affect the etch rate and uniformity [14, 15, 16]. This shows that both the physical reaction of the inert gas and the chemical reaction of the reactive gas on the wafer surface should be considered in the etch process. Excessive chemical reactions in procedures requiring anisotropic etch may result in poor surface uniformity and rough sidewalls due to the isotropic etch and unpredictable radical movement [17]. Thus, the parameters that affect temperature changes need to be optimized to control temperature-sensitive chemical reactions. Temperature sources such as chuck temperature and chamber wall temperature might indirectly affect WIP temperature during the etching process [18,19].