# Arrayable TDC with Voltage-Controlled Ring Oscillator for dToF Image Sensors
## 3 TDC Circuit Design and Implementation  
The voltage-controlled oscillator in this article adopts a ring oscillator design [15]. In order to meet the requirements of TDC single-pixel integration, key parameters such as area, power consumption, and time accuracy need to be synergistically optimized. At the same time, a four-stage ring oscillator is used to suppress common mode interference, and the circuit structure is shown in Figure 3.  
Compared to the differential delay unit voltage-controlled oscillator (VCO), which has a wide tuning range (>50%) and high frequency capability (GHz level) suitable for reconfigurable RF systems, the fully integrated relaxation oscillator exhibits disruptive advantages in the mid-low-frequency high-precision clock field: the differential VCO has a temperature drift > 500 ppm/\({}^{\circ}\)C due to the temperature sensitivity of the delay chain, while the relaxation architecture compresses the temperature drift to 23.4 ppm/\({}^{\circ}\)C through voltage delay feedback (VDF), optimizing the voltage sensitivity to \(\pm\)0.15%/V [16]. In terms of noise performance, the relaxation oscillator achieves 156 dBc/Hz COM with switch capacitor swing enhancement (SCSB) and self-threshold calibration (CSTA), significantly better than the typical \(-\)140 dBc/Hz COM of the differential VCO at \(-\)150 dBc/Hz (limited by circular structure flicker noise). In terms of power consumption, the relaxation scheme only consumes 51.4 \(\mu\)W at 1.6 MHz, which has a numerical advantage over the GHz level differential VCO (>100 \(\mu\)W) [17]. The essential trade-off lies in the following application scenario: the differential VCO is suitable for wideband systems such as software defined radio, while the relaxation oscillator, with its ultra-stable frequency and low phase noise at the near end, has become the optimal clock solution for biosensing and IoT nodes. In the design of ring oscillator architecture, the four-stage topology exhibits unique stability and gain optimization mechanisms compared to the three-level implementation: the four-stage ring oscillator introduces a first-stage non-reverse buffer unit to maintain the equivalent oscillation phase of 360\({}^{\circ}\) while breaking the potential DC balance point locking risk of symmetrical topology [18]. This structure satisfies the Barkhausen criterion, and the oscillator oscillation condition is shown in Equation (2):  
\[H_{delay}(s)=\frac{-A}{1+\frac{s}{\omega}} \tag{2}\]  
In the formula, \(\omega\) is the pole of the unipolar delay module, and \(A\) is the circuit gain. The overall loop gain can be obtained as shown in Equation (3):  
\[H_{ALL}(s)=-\frac{A^{4}}{\left(1+\frac{s}{\omega}\right)^{4}} \tag{3}\]  
Figure 3: Pseudo-differential delay unit. In the analysis of the starting frequency of a ring oscillator, based on the Barkhausen stability criterion, the total phase shift of the four-stage cascade is \(180^{\circ}\), which satisfies the oscillation phase condition, with a single-stage phase shift of \(45^{\circ}\). The oscillation frequency at this time can be obtained through Formula (4), and by substituting \(\omega_{osc}=\omega\), the circuit gain can be obtained as shown in Formula (5):  
\[\arctan\Bigl{(}\frac{\omega_{osc}}{\omega}\Bigr{)}=45~{}^{\circ}\mathrm{C} \tag{4}\]  
\[\mathrm{A}=\sqrt{1+\Bigl{(}\frac{\omega_{osc}}{\omega}\Bigr{)}^{2}}=\sqrt{2} \tag{5}\]  
The delay circuit of the ring oscillator adopts a pseudo-differential pair delay unit circuit, as shown in Figure 3. The positive-feedback quasi-differential inverter unit circuit consists of a positive feedback section and a differential inverter circuit, compared to the cascaded NMOS transistor MN1 used as the main control switch in this paper. The function of MN1 is to control the on and off of the ring oscillator. EN_VCO is the pulse-level signal in the preprocessing circuit. The MP1 tube and MP2 tube cross-coupling architecture and differential pair input synergy accelerate the flipping of output nodes.