## 2 Materials and Methods
### Delay-Locked Loop (DLL)  
The 40 MHz main clock delivered to SALT as a part of the TFC protocol is synchronous with the beam. However, its phase, although constant, is difficult to predict in advance. Therefore, it is shifted in the dedicated low power DLL to obtain a precise alignment between the ADC sampling phase and the bunch crossing. The DLL produces a second replica of the 40 MHz clock, which is used to tune the delay of the internal test pulse for the analogue front-end.  
Figure 4 shows the block diagram of a DLL. The central block is the Voltage Controlled Delay Line (VCDL), which includes 64 delay cells and creates 64 independent clock phases. Two of them (for the ADCs and the internal test pulse generators) are selected by a pair of independent multiplexers (CLK Multiplexer) connected directly to the VCDL. These signals are delivered to the second pair of multiplexers (Out Multiplexer) which select between them or main clock (_MAIN_CLK_). This bypass function is utilised during the DLL synchronisation process to avoid randomly changing phases in the outputs. More details on the DLL core design can be found in [24].  
A DLL is relatively sensitive to variations of Process, Voltage, and Temperature (PVT) parameters. Although the feedback loop can compensate for small changes of temperature and voltage, to cover a full range of PVT variations, biasing currents have to be adjusted. In the SALT, two 7-bit voltage DACs controlling biasing currents of the charge pump and the VCDL were implemented for this purpose. The VCDL is significantly more sensitive to PVT changes and its biasing current has to be adjusted for each chip. The Current Test (CT) logic was added to simplify this procedure. This block is active only during the VCDL configuration procedure and allows for the determination of the optimal value of the VCDL current. It measures the time delay of _ph32_ (one of the 64 VCDL outputs, placed exactly in the middle of the delay line) using _MAIN_CLK_ as the sampling clock. When the time delay of _ph32_ is around half of the _MAIN_CLK_ period, the CT logic sets the high state to output _dll_cur_ok_.  
In the case of the significant change of some PVT parameters the VCDL may be out of range or DLL may lock to \"harmonic\" delay, that is, a delay which is a multiple (2, 3, or more) of the 25 ns reference period. The first case is easy to detect with the control voltage \(V_{DLL}\) monitoring (see Section 2.8), but the second one is more demanding. To address this issue, a Harmonic Lock Detector (HLD) circuit was designed and implemented.  
The HLD circuit checks the phase relation between main clock and VCDL outputs: _ph9_, _ph18_, and _ph41_. On the contrary to the CT logic, in the HLD block _MAIN_CLK_ is sampled at the rising edge of the aforementioned signals. The result is available as a 3-bit signal _dll_hld_debug_ and may be read from one of the SALT registers. When the DLL  
Figure 4: Delay-Locked Loop (DLL) block diagram: PD—Phase Detector, CP—Charge Pump, LPF—Low Pass Filter, VCDL—Voltage Controlled Delay Line, CT—Current Test, HLD—Harmonic Lock Detector.  
is synchronised properly, _dll_hld_debug_ is equal to 110. An additional single bit _dll_hld_, informs the user about the harmonic lock status.