## 3 Proposed Design Methodology
### Third-Stage Amplifier Design  
The minimum gain required for this LNA is 24 dB. It is apparent from Table 2 in the previous section that the total available gain from the first two stages is only 18.075 dB, which is insufficient to meet the small-signal gain requirement. Therefore, a third amplification stage is necessary. To fulfill this requirement, a gate width transistor of \(4\times 75\)\(\mathrm{\SIUnitSymbolMicro m}\) from the WIN Foundry PIH1-10 technology is selected for implementation in the third stage. The small-signal and noise parameters of this transistor are provided in Table 3.  
As previously mentioned, once the transistor has been selected, the next step is to evaluate its stability over the operating bandwidth. By plotting the input and output stability circles, it becomes evident that the device is unstable in the frequency range of 13-15 GHz. Therefore, a stabilization network is necessary. Since this stage is treated as a single-stage power amplifier, the stabilization network is introduced at the gate terminal of the transistor rather than its source terminal.  
As can be seen in Figure 8, an RC network is inserted before the transistor to improve the bandwidth of the amplifier while increasing the stability of the device. However, the RC network increases the noise Figure for the third stage, but this will not affect the overall LNA's NF. According to [10], if the gain is high enough, the first stage amplifier will dominate the noise characteristic of cascaded amplifiers. The preliminary values of the resistor and capacitor in the RC network are chosen to make Rollett's stability factor of the active device higher than unity and achieve a minimum available gain of 7 dB.  
The RC network and the FET can be considered as a single active device, denoted as 'AD3', as illustrated in Figure 8. A load-pull simulation, shown in Figure 9, is conducted to determine the source and load impedance values that yield the highest available power gain [10]. The corresponding input impedance, \(Z_{in,AD3}\), and output impedance, \(Z_{L,AD3}\)  
Figure 8: The Third Stage Amplification Block.  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Value** \\ \hline \(S_{11}\) & \(0.865/-170.2^{\circ}\) \\ \(S_{21}\) & \(3.014/75.8^{\circ}\) \\ \(S_{12}\) & \(0.083/-7.1^{\circ}\) \\ \(S_{22}\) & \(0.481/-159.8^{\circ}\) \\ \(\Gamma_{opt}\) & \(0.553/145.5^{\circ}\) \\ \(NF_{min}\)(dB) & \(0.90\) \\ \(R_{n}(\Omega)\) & \(3.85\) \\ \hline \hline \end{tabular}
\end{table}
Table 3: FET small signal and noise parameters with \(4\times 75\)\(\mathrm{\SIUnitSymbolMicro m}\) gate width at 15 GHz. The source terminal is ideally grounded.  
are listed in Table 4. To design the IMN and OMN for the final stage, the input and output impedances are matched to the system reference impedance, \(Z_{0}\).  
To summarize the design steps of the third stage, the reader can follow these steps:  
1. Determine the appropriate transistor device.
2. Perform a stability analysis and insert a stabilization network at the gate terminal if necessary.
3. Perform a load-pull simulation to determine the optimum load impedance that maximizes power gain delivered to the load.
4. Match the input and output impedances to the system reference impedance \(Z_{0}\) to design the IMN and OMN of the final stage.