# Hardware Design for Cascade-Structure, Dual-Stage, Current-Limiting, Solid-State DC Circuit Breaker
## 1 Introduction  
The introduction of high-frequency converters and power electronic devices has made it more convenient and efficient to integrate distributed power sources into the grid [1, 2]. Renewable energy sources such as wind and photovoltaic (PV) power are gradually transitioning from supplementary to primary energy sources, with their share continuing to arise [3, 4, 5, 6]. Since its development in the 1990s, flexible direct current (DC) transmission technology has emerged as a new form of DC transmission following AC transmission and conventional DC transmission, achieving significant progress [7, 8, 9]. Compared to traditional DC transmission technology, flexible DC technology exhibits various advantages: it can achieve the independent control of active and reactive power, avoid the introduction ofreactive power compensation devices, reduce harmonic levels, solve commutation failure problems, and require less land area [10,11].  
The low damping characteristics of DC grids mean that when short-circuit faults occur, the impact is extensive and extremely fast, necessitating the rapid isolation and clearance of DC faults [12,13]. Configuring DC circuit breakers at the connection points between converter stations and DC lines is an effective choice for dealing with DC system faults; this method does not interfere with normally operating lines and does not interrupt normal power transmission [14, 15, 16]. Solid-state DC circuit breakers offer faster fault clearance speeds and simpler control methods compared to mechanical and hybrid DC circuit breakers, and can achieve bidirectional current interruption through the antiparallel connection of semiconductor devices [17,18].  
Reference [19] developed a small solid-state circuit breaker experimental platform based on PMOS with an input voltage of 48 V. The circuit breaker does not require an additional power supply, using a self-powered method, and uses domestically mature PMOS and Schottky diodes to complete fault blocking within a few microseconds. Reference [20] developed a reverse-blocking-type IGCT-based solid-state DC circuit breaker prototype with an antiparallel structure, which is cost-effective, compact, and highly reliable. By simulating the generation of short-circuit currents through an LC resonant circuit, it achieved a current capacity of 2 kA under a system voltage of 750 V and could cut off a fault current of 10 kA within hundreds of microseconds. Reference [21] designed a low-power DC solid-state circuit breaker experimental prototype rated at 48 V using a digital-analog hybrid control system based on DSP and emulators. The system's rated current was 1 A, and it successfully completed tests for eight possible fault conditions. Reference [22] proposed and designed a solid-state DC circuit breaker (SSCB) prototype based on SiC MOSFETs. Through the design of adaptive driving circuits, control logic, and current-sensing branches, the prototype can clear faults with a peak current of 48 A and limit overvoltage to 800 V within 15 microseconds.  
Based on the above experimental prototype production schemes, this paper proposes a small-capacity hardware topology for a cascade-structure, dual-stage, current-limiting, solid-state DC circuit breaker. A simulation model is established in MATLAB/SIMULINK(R2017b) to verify the effectiveness of the topology and construct a small-capacity experimental prototype. The prototype introduces electrolytic capacitors as the power supply system for the circuit breaker, with current detection modules connected in series in each branch to test the current data of each branch. A microcontroller drives the semiconductor devices, silicon-controlled rectifiers (SCRs), and metal oxide semiconductor field-effect transistors (MOSFETs) via optocouplers and drive modules, ultimately completing the experimental verification.