# Analysis and Modeling of Mueller-Muller Clock and Data Recovery Circuits
## 1 Introduction  
With the rapid development of integrated circuits and the emergence of advanced process nodes, the data transfer rate of high-speed serial interfaces (i.e., serializer/deserializer) has grown exponentially [1]. The rapid growth of data rate makes the classical Bang-Bang phase detector (BBPD) no longer suitable for high-speed clock and data recovery (CDR). However, the advantage of the Mueller-Muller phase detector (MMPD) that requires only one sample per symbol alleviates the problem of BBPD timing tension and exponential growth of power consumption in high-speed situations, making Mueller-Muller baud-rate sampling widely used in the serial IO design [2, 3, 4, 5, 6].  
Compared to the Mueller-Muller baud-rate sampling technique, a lot of work has been done on Bang-Bang CDR. In [7], [PERSON] et al. linearized the BBPD using the effect of metastability and input jitter, combining with the behavioral characteristics of large signals to characterize the jitter transfer and jitter tolerance of the CDR. However, for jitter transfer, we are more concerned about the bandwidth of the CDR after locking (i.e., in a small range). In [8], [PERSON] et al. described a linear model for the general architecture of digital clock and data recovery. They linearized the BBPD using Gaussian jitter and derived the gain formula, and then obtained a linear model of the CDR in combination with the analysis of other modules of the digital CDR loop, in which the input jitter of the BBPD needs to be simulated accurately each time. The authors in [9] summarized the existing linear models of BBPD and analyzed the effect of random jitter and finite loop delay on the loop characteristics. Nevertheless, there is no analysis of linearization for the MM-CDRs in previous work, which all focus on the use of the Mueller-Muller baud-rate sampling technique. For example, [PERSON] et al. [10] introduced an unequalized MM-CDR, which can adjust the phase lock position according to the extracted channel response and achieve the adaptive channel response; while [PERSON] et al. [11] presented a weight-adjusting sign-signMueller-Muller clock and data recovery circuit. These studies only apply the MMPD without a systematic analysis of the MM-CDR, affecting the circuit design performance and extending the circuit design cycle. To solve these problems, we propose the gain formula of MMPD for the first time using the jitter characteristics of the input, then give the joint analysis method of voter and MMPD, and finally analyze the error jitter for the overall system. Through the above modeling, we address the theoretical gap and provided the basis for the design for MM-CDR.  
In this work, we propose a linear model for a Mueller-Muller CDR. The remainder of this article is organized as follows. Section 2 discusses the working principle of MMPD and presents a linear gain model for it. Section 3 describes the gain model of the MMPD-based voter and builds a small-signal model of the MM-CDR to analyze the jitter tolerance and jitter transfer. Section 4 analyzes the error jitter between recovery clock and input data. Section 5 demonstrates the simulation results that validate the analysis of Section 4, and Section 6 draws the conclusion.