## 3 HD-VLL for Hybrid DS/FH Spread Spectrum Signals
### Hd-Vll  
According to the discussion in Section 3.1, the filter output of the second-order VLL loop filter remains constant during a loop update period without taking into account the phase variation caused by acceleration and jerk, eventually causing the accumulated phase tracking error. To address the accumulated phase tracking error of the second-order VLL under high dynamic conditions, an HD-VLL based on the second-order VLL is proposed, which can simultaneously process jerk, acceleration, and velocity. By comparing (6) and (8), it can be seen that at the \(i\)th sampling point of the \(k\)th loop update period, the phase variation generated by jerk and acceleration is \(\pi f_{cj}a(iT_{s})^{2}/c+\pi f_{cj}\dot{a}(iT_{s})^{3}/3c\), which should be compensated in real time. However, it is observed that the values of acceleration and jerk cannot be obtained directly; thus, it is necessary to find reasonable estimates of acceleration as well as jerk, respectively. The structure of the second-order VLL loop filter is depicted in Figure 4.  
In the figure, \(\omega_{nv}\) and \(K\) represent the characteristic angular frequency and the gain of the second-order VLL loop filter, and \(z^{-1}\) represents the unit delay, respectively. The corresponding discrete transfer function is  
\[V(z)=\frac{(\sqrt{2}\omega_{nv}T+\omega_{nv}^{2}T^{2})-\sqrt{2}\omega_{nv}T\cdot z ^{-1}}{K(1-2z^{-1}+z^{-2})}, \tag{9}\]  
After filtering the input velocity error signal, the filtered state variables of the high-order loop filter also contain high-order information in addition to the filtered velocity error result, such as acceleration and jerk [24; 25; 26; 27; 28; 29; 30]. In the second-order VLL loop filter structure shown in Figure 4, signal 1 located before Integrator 1 is actually the filtered second-order change rate of the velocity error (i.e., jerk), and the corresponding discrete transfer function between the input and 1 is  
\[V_{\hat{a}}(z)=\frac{\omega_{nv}^{2}}{K}. \tag{10}\]  
Signal 2, located before Integrator 2, is actually the filtered first-order change rate of the velocity error (i.e., acceleration), and the corresponding discrete transfer function between the input and 2 is  
\[V_{a}(z)=\frac{\sqrt{2}\omega_{nv}+\omega_{nv}^{2}T-\sqrt{2}\omega_{nv}z^{-1} }{K(1-z^{-1})}. \tag{11}\]  
Hence, there is high-order information in the second-order VLL loop filter, which makes it adaptable to scenarios with certain acceleration and jerk. The filter output \(\hat{v}_{\hat{a}k}\), which is obtained by integrating the filtered acceleration and the filtered jerk, is constant during a loop update period and is actually the estimate of the velocity at the start of the next loop update period. However, as the acceleration and jerk become greater, it is not only necessary to estimate the velocity variation between adjacent loop update periods, but also to provide a reasonable prediction of the velocity variation caused by acceleration and jerk at each sampling point during the loop update period. In this way, the difference between the local instantaneous phase of the replica signal and the instantaneous phase of the received signal at each sampling point can be as small as possible. Therefore, the structure of the HD-VLL is proposed by adding acceleration and jerk compensation modules operating at the system clock to the second-order VLL loop filter. According to the previous analysis, 1 is regarded as the estimated value \(\hat{\hat{a}}\) of jerk \(\hat{a}\), and 2 is regarded as the estimated value \(\hat{a}\) of acceleration \(a\), so the acceleration and jerk compensation modules should compensate for a phase of \(\pi f_{cj}\hat{a}(iT_{s})^{2}/c+\pi f_{cj}\hat{a}(iT_{s})^{3}/3c\) at the \(i\)th sampling point. Since the process of summing \(i\) or \(i^{2}\) by the accumulator is analogous to the integration process of the continuous signal, the workflow of HD-VLL to generate the local instantaneous phase is given below.