# Study on Single-Event Transient Hardness of Semi-Enclosed Gate NMOS
## 1 Introduction  
As spacecraft electronic systems advance towards higher integration, the reliability issues induced by the space radiation environment have become increasingly prominent. Among these issues, single-event effects (SEEs), which are transient fault phenomena triggered by high-energy particles, have emerged as a critical technical bottleneck limiting the long-term operation of onboard equipment [1, 2, 3, 4, 5, 6]. When high-energy charged particles (including protons, electrons, and heavy ions) penetrate semiconductor devices, the transient plasma generated by their ionization can induce abnormal charge transport at sensitive nodes of the device. This may lead to severe consequences such as logic state errors, memory cell upsets, and even functional module failures [7]. Notably, as CMOS technology advances into the nanoscale, the reduction in critical charge and sensitive volume due to device miniaturization has resulted in an increased susceptibility to SEEs [8, 9, 10, 11, 12]. This heightened sensitivity underscores the growing challenge of ensuring the reliability of nanoscale electronic devices in radiation-prone environments. To enhance the level of radiation-hardened design, the enclosed gate NMOS achieves effective management of radiation-induced charge through its unique gate topology. This device employs a fully enclosed gate structure, which reconstructs the electric field distribution near the drain-body junction, significantly improving the directional collection capability of ionized charge. As a result, the enclosed-gate NMOS demonstrates remarkable advantages in radiation resistance, making it a promising solution for applications in radiation-prone environments [13, 14, 15, 16, 17, 18, 19]. To further balance the requirements of radiation hardness and integration density, the academic community has proposed a variant of the semi-enclosed gatestructure. This design adopts a partially enclosed gate layout, achieving approximately 40% optimization in the layout area while maintaining electric field control capabilities. This is of significant importance for enhancing the radiation resistance of high-speed circuits. Currently, academic research on semi-enclosed gate structures has mainly focused on their protective mechanisms against Total Ionizing Dose (TID) effects (TID is a performance degradation phenomenon in electronic devices caused by cumulative radiation dose during prolonged exposure to ionizing radiation environments, which can ultimately lead to failure of electronic devices [20]. ), while analysis of mechanisms related to single-event effects (SEEs) has been relatively scarce [21,22]. Therefore, this study systematically constructs comprehensive physical process models for a Single Event Transient (SET) based on TCAD three-dimensional (3D) device(TCAD 2017) simulation software and Virtuoso simulation software(the version number is 6.1.7). TCAD simulation is used to investigate the behavior of a single device under single-event transient conditions, while Virtuoso simulation is employed to study the single-event transient effects of a semi-annular gate NMOS transistor in a digital inverter circuit. The purpose is to investigate, through simulation analysis, the superiority of enclosed gate NMOS over traditional NMOS in resisting SET effects, and to study the SET performance of semi-enclosed gate NMOS transistors under different radiation conditions, including current transient pulses, internal electric fields, and changes in the internal potential of the device. This work demonstrates the advantages of the semi-enclosed gate structure in mitigating SET. SET is a phenomenon in integrated circuits where heavy particles from cosmic rays penetrate semiconductor materials (such as silicon) and cause ionization, generating electron-hole pairs that lead to transient voltage or current disturbances [23, 24, 25, 26, 27, 28, 29].