# DDR4 BER Degradation Due to Crack in FBGA Package Solder Ball
## 3 Simulation of Solder Ball Crack in Data Channel  
The simulation setup to see the effect of crack in DDR4 data channel and the simulation results are described in this section. Figure 3 shows location of crack in DDR4 FBGA package solder ball. The crack occurs at the solder ball of the DDR4 data channel. The data eye is measured at the DDR4 receiver. The simulation setup consists of FPGA memory controller connected to DDR4 memory through a transmission line. The vias, DIMM socket, and pcb stack are not included in the simulation. There is no random jitter or noise in the simulation and the simulation qualitatively shows the effect of crack. The DDR4 data channel containing the cracked solder ball is shown in Figure 4. FPGA memory controller IBIS model is used for simulation [17]. Driver impedance is set to 40 Ohms. The package length describes the pin delay due to trace length in the package. R, L, C pin parameters for FPGA are used. Board transmission line is a microstrip line having 40 Ohms characteristic impedance. The electrical model for cracked solder ball is used in the simulation. The self-resistance of the solder ball is 6.9 millionhm. The self-inductance of the solder ball is 69 picohenry. The capacitance due to crack in the solder ball is 325 picofarads. DDR4 package length describes the pin delay due to trace length in the  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Length (m)** & **Cross Sectional Area (mm\({}^{2}\))** & **Capacitance (F)** \\ \hline
2.00 \(\times\) 10\({}^{-8}\) & 5.50 \(\times\) 10\({}^{-12}\) & 9.74 \(\times\) 10\({}^{-14}\) \\
5.00 \(\times\) 10\({}^{-5}\) & 1.37 \(\times\) 10\({}^{-8}\) & 2.44 \(\times\) 1  
package. R, L, and C pin parameters for DDR4 memory are used. The on-die termination for DDR4 is 40 Ohms. Micron DDR4 IBIS model is used [18]. JEDEC standard defines DDR4 receiver mask (RX Mask) as shown in Figure 5. Time data input valid window (T\({}_{\rm{divw}}\)) defines RX mask along time axis. Voltage data input valid window (V\({}_{\rm{divw}}\)) defines RX mask along voltage axis [1]. The top margin is defined as the voltage margin between top of the RX mask and top of the data eye. Low margin is defined as the voltage margin between the lower part of the RX mask and low part of the data eye. The width of the data eye is the horizontal opening of the data eye at either V\({}_{\rm{HI}}\) or V\({}_{\rm{IL}}\), whereas V\({}_{\rm{IH}}\) and V\({}_{\rm{IL}}\) are voltage high and voltage low thresholds, as shown in Figure 5.  
Hyperlynx software was used for simulation. The driver impedance is set to 40 Ohms and the DDR4 termination is set to 40 Ohms. Pseudo random binary sequence (PRBS) signal is applied to the DDR4 data channel and data eye is captured at the DDR4 receiver. The data channel response when there is a cracked solder ball in the data channel is compared with the case when there is no crack in the solder ball. The simulation results show that the cracked solder ball decreases the data eye width, top margin and low margin. This qualitatively shows that there will be increase in bit error rate due to cracks in solder ball. Figure 6a shows 2.133 Gbps PRBS signal for DDR4 data channel when there is no crack in the DDR4 package solder ball. The rectangle inside the data eye shows the DDR4 receiver RX mask. Figure 6b shows a data eye when there is a crack in the solder ball. The width of the data eye for Figure 6a is 0.8598 UI and the width for Figure 6b is 0.8414 UI,  
Figure 4: DDR4 data channel containing the cracked solder ball. Figure 5: DDR4 data eye showing receiver RX mask, eye width, top and low margin. Figure 3: Diagram of simulation setup. where UI is unit bit interval. The top margin of data eye when there is no crack is 0.1726 V and the top margin is 0.1653 V when there is crack in solder ball. The low margin is 0.1864 when there is no crack and the margin is 0.1726 when there is a crack in solder ball. The crack decreases the data eye width, top margin and low margin. This will result in increased bit error rate.