## 9 Discussion  
In this paper, we analyzed and experimentally verified a series of design strategies for near-field communication interfaces to enable an operation with high data rate, low power consumption, small footprint, and resilience against interference from wireless power transfer links:  
First, it was shown that data coil topologies can be optimized for minimal inductive coupling to wireless power transfer coils situated on the same substrate. While the C-shaped coil performs well for a lateral offset of primary and secondary coil systems, the butterfly-shaped coil combines the advantage of small interference to the complete energy coil system for axial alignment (even for the coil not being on the same substrate) and the advantage of not having zeros of data coil coupling for an axial alignment. This is also supported by the experimental data, which showed that computed and realized self-inductances and mutual inductances are in close agreement, with a maximum relative deviation of about 5%. Moreover, the selective coupling of the data coils on the one hand and the limited mutual inductance of data and energy coils on the other hand even persist in dielectric media, as long as the coils show minor detuning due to a low number of turns. Complementing the design of the resonators, the optimal resonator tuning obtained from the mathematical analysis and the analog front-end successfully translated into a design with the desired characteristics of fast transient settling, as shown by the acquired link signals of Figure 20. The voltage amplitudes at the receiver (cf. Figure 19) and the energy carrier suppression of the impedance matching network (cf. Figures 8 and 25) are in close agreement to the simulated designs. Secondly, the proposed concept of a single-bit sampling digital transceiver architecture was successfully evaluated: Here, the conversion of an analog sinusoidal signal to a rectangular wave by a comparator stage, the clock synchronization by a custom and minimalistic digital counter circuit, the down-conversion to baseband by a single XNOR gate, the subsequent low-pass filtering by digital moving average filter, and the symbol mapping using a simple decision stage resulted in a series of favorable characteristics: The digital design can be synthesized with less than 400 look-up tables and 200 D-flip-flops, so that it can be programmed into the smallest of today's commercially available FPGA circuits. Although the internal sampling clocks are as high as 108.48 MHz, the power consumption is limited to 4.4 mW for the transmitter and 2.5 mW for the receiver, which yields a normalized energy consumption of 646 pJ/bit for the transmitter and of 364 pJ/bit for the receiver at a data rate of 6.78 MBit/s. Due to the mostly-digital implementation with the FPGA and the compact analog front-end, a net PCB footprint of 33 mm\({}^{2}\) is achieved, which is well below the initial request of 100 mm\({}^{2}\). The synchronous demodulation and the sampling of eight points per carrier period result in a bit-error rate as low as \(2\times 10^{-7}\) for coil separation distances of up to 10 mm. The measured BER levels are in the same order of magnitude as the predictions of the proposed simulation concept, which takes the hysteretic behavior of the comparator stage into account. These given performance metrics are compared to state-of-the-art high-speed transceivers in Table 5: Here, the custom transceiver of this work provides an energy consumption per bit which is approximately 10 times lower than that of commercial NFC devices. At the same time, it outperforms the devices with respect to the maximum data rate, which is available for both transmitter and receiver. Although the data rates of transceivers with pulse-harmonic modulation exceed the given concept,  
Figure 25: Measured voltage transfer function of the primary impedance matching network. it must be noted that these are highly susceptible to interference, especially to strong signals from an additional wireless power transfer link.