# GS-AGC: An Adaptive Glare Suppression Algorithm Based on Regional Brightness Perception
## 3 An Adaptive Glare Suppression ALGORITHM Based on Regional Brightness Perception
### Gs-Agc
These qualities are crucial for meeting the real-time requirements of the algorithm. #### 3.3.2 Modular Design of the Algorithm

Figure 7 presents the general architectural framework of the FPGA accelerator designed for the GS-AGC algorithm. The framework consists of two main components: the processing system and the FPGA acceleration core system. The processing system is responsible for access and control tasks and comprises ARM CPU cores and external memory. On the other hand, the FPGA acceleration core system is dedicated to implementing the algorithm's acceleration tasks and is divided into three modules: the access module, the Gamma_trans image processing module, and the parameter cache module. To achieve higher processing speed in Vivado_HLS global processing and image processing, the framework employs a pipelined operation. This approach incorporates concurrent caching and processing of image data within the FPGA, enabling the implementation of IP cores with low latency and high bandwidth. Figure 5: Flow chart of the GS-AGC algorithm. Figure 6: Image processing framework. 1. Memory access module During runtime, the CPU initializes the off-chip memory module and stores both the low-illumination image and the corresponding grayscale image data in the external DDR memory. Additionally, the CPU is in charge of transmitting the input image for processing to the access memory module via the AXI bus. The access memory module retrieves the input image from the external storage and caches it into the cache module. 2. Parameter Cache Module During transmission, to ensure the integrity of the transmitted data, the parameter cache module incorporates block random access memory (BRAM) located on the chip. Within the FPGA, the BRAM resources consist of individual RAMs that are primarily responsible for caching the image data and the results obtained from the Gamma_trans module after processing. 3. Image processing module The image processing module nonlinearizes the image through a brightness-based calculation of the pixels in the image, as well as by evaluating the brightness of the pixels in the surrounding region. The output of this operation is transferred to the image processing module to achieve the overall enhancement and regional suppression of the image. To accelerate the algorithm, custom computation combined with parallel computation was utilized. A dedicated circuit was designed using Vivado 2017.4 to perform mathematical calculations for the custom computation, with multiple circuits performing parallel computations simultaneously. During the data parallel computation stage, a pipeline was used to fetch data from the cache module, perform calculations, and write the results back to the cache module. When traversing the pixels, the #Pragma HLS PIPELINE directive in Xilinx HLS guided the synthesis process and added the PIPELINE to the J loop, which was unrolled along the input image's width direction. This enabled HLS to process one pixel per clock cycle. The HLS completely expanded the window calculation, allowing for the read of nine data at once and increasing the bandwidth. The algorithm is shown in Algorithm 3. Figure 7: Overall design framework of FPGA acceleration core. For this purpose, the Gamma_trans nonlinearized operation was implemented as a pipelined multiply-add operation with the help of DSP Slice. The pipeline consists of fetching data from the cache module, performing the arithmetic operation, and writing the result back to the cache module. The pipelining cycle is determined by the execution time of the segment of the task with the longest execution time. By designing the pipelined system, the FPGA's throughput could be improved, and the logic resources could be better utilized for the parallel processing of the two tasks of parameter caching and image processing. ## 4 Experimental Results and Analysis

### Experimental Preparation

#### 4.1.1 Experimental Dataset

In this paper, the low-light image dataset BDD [42] created by the University of Berkeley AI Lab (BAIR) was primarily utilized.