# Design and Research of Photonic Reservoir Computing for Optical Channel Equalization
## 3 Results and Discussion  
### Parameter Optimization of Reservoir Photonic Devices  
In the reservoir layer of PhRC, besides the number of nodes affecting the equalization results, the splitting ratio of DCs and the length of waveguide delay lines also have significant impacts on the outcomes. Therefore, we study the equalization performance of PhRC when both factors and the number of nodes change. The distorted 25 Gb/S OOK signal is generated by a 20 km SSMF, of which the BER is 2.108 \(\times\) 10\({}^{-2}\). Due to the difficulty in fabricating DCs with a splitting ratio coefficient \(R_{dc}\) of 0.1 and the high similarity in device characteristics \(R_{dc}\) of between 0.2 and 0.8, values within the \(R_{dc}\) range of 0.2 to 0.5 are selected for discussion. During optimization, the waveguide delay line coefficient is held constant at 0.1 while \(R_{dc}\) is varied from 0.2 to 0.5 in increments of 0.1 to assess equalization ability. When the number of reservoir nodes ranged from 12 to 48, the impact of different \(R_{dc}\) on noise equalization results is discussed for each reservoir layout, as shown in Figure 4a. The equalization performance across four PhRC reservoir layer layouts indicates that, except for the 12-node layout, all other PhRC layouts can reduce the BER of the distorted signal, during fluctuation of \(R_{dc}\). Notably, the 36-node layout achieves an equalized signal's BER of 1.859 \(\times\) 10\({}^{-5}\), representing a three-orders-of-magnitude reduction compared to the BER of the distorted signal. As the \(R_{dc}\) increases from 0.2 to 0.5, the BER of the equalized signals in all four PhRC layouts with different reservoir node counts exhibits a downward trend. This suggests that an unbalanced DC splitting is harmful to the equalization performance of PhRCs. This is because a significant bias in DC splitting towards one port results in reduced output power at the other port, weakening the influence of this low-power signal on the subsequent node. Similarly, a higher output power can significantly affect or even overshadow the signal at the next node, disrupting the intended information exchange. When the DC splitting is more balanced, signals interacting between \begin{table}
\begin{tabular}{c c c c} \hline
**Device Name** & **Parameter** & **Value** & **Units** \\ \hline \multirow{3}{*}{Si wavelength} & insertion loss & 3.5 & dB/cm \\  & \(n_{\mathit{eff}}\) & 2.58 & / \\  & \(n_{g}\) & 4.33 & / \\ \hline \multirow{2}{*}{PD} & responsivity & 0.85 & A/W \\ \cline{2-4}  & Er lifetime & 10 & ms \\ \multirow{2}{*}{EDFA} & backward pump power & 0.1 & W \\  & backward pump wavelength & 980 & nm \\ \multirow{2}{*}{} & noise figure & 3.5 & dB \\ \hline \end{tabular}
\end{table} 
Table 1: _Cont._nodes can more evenly incorporate information from each input path, thereby providing higher performance without change the node connection topology. When comparing the four node counts individually, it is evident that the 12-node layout performs worst at \(R_{dc}\) of 0.2, 0.3, and 0.4, and second-worst at \(R_{dc}\) = 0.5. The 24-node layout is second-worst at \(R_{dc}\) of 0.2 and 0.3, worst at \(R_{dc}\) = 0.5, and only slightly better than the 36-node structure at 0.4. The 36-node layout is optimal at \(R_{dc}\) of 0.2 and 0.5, second-best at \(R_{dc}\) = 0.3, and second-worst only at \(R_{dc}\) = 0.4. The 48-node layout is second-best at \(R_{dc}\) of 0.2 and 0.5, optimal at all others. These results indicate that layouts with fewer nodes are more sensitive to changes in the DC splitting ratio and more challenging to achieve good channel noise equalization. At the four node count of PhRCs, the optimal result for the DC splitting ratio coefficient is 0.5. The length of the waveguide delay line primarily influences the duration of signal interaction at each optical node, remaining fixed once the chip fabrication is completed. Due to the existence of insertion loss, the length of the waveguide delay line also affects the overall optical power loss within PhRC.