# Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices
## 3 Electronic Packaging
### High-Speed Routing  
High-speed SMA (18-25 GHz) and SMK (46 GHz) connectors have \(a\approx\)1 cm\({}^{2}\) footprint on the PCB, while the pitch of the electrical bond-pads on a PIC is typically 100 \(\upmu\)m. Therefore, the pitch of the high-speed 50 \(\Omega\) transmission lines must be reduced by two orders-of-magnitude between the connector and the PIC, while maintaining the path-length of different electrical-channels to preserve signal timings. This usually results in PICs surrounded by circular or semi-circular PCBs, with an area that increases proportional to the square of the number of electrical channels--see Figure 11.  
On standard high-dielectric PCB (\(D_{K}\approx 10\)), the minimum feature size limits the pitch of 50 \(\Omega\) transmission lines to about 300 \(\upmu\)m, which is a factor of three greater than the bond-pad pitch on the PIC. This 'gap' can be bridged by a pitch-reducing multi-level ceramic interposer, designed using a finite element mode (FEM) high frequency structural simulator (HFSS). The interposer offers smaller feature sizes and higher manufacturing tolerances than those possible for PCBs. The electrical connection between the interposer and the bond-pads on the PIC are made using 10-20 \(\upmu\)m diameter Au wire-bonds. For DC (direct current) connections, circular cross-section wire-bonds are used, but for high-speed connections 'ribbon' or 'tape' wire-bonds are preferred. Ribbon wire-bonds have a higher surface area-per-unit-volume, which offers lower resistance to high-speed signals, because of the skin effect.  
To reduce induction effects, all wire-bonds should be as short and straight as possible. This often means that the PIC should be recessed into the PCB, to allow for a 'flush' wire-bond. Once connected  
Figure 11: Examples of electrical-routing structures needed for high-speed photonic packages; (**a**) Image of the semi-circular PCB-to-PIC routing needed to ensure that multiple signals arrive at the same time; (**b**) Microscope image of a pitch-reducing ceramic interposer used to match the minimum-pitch on a standard high-dielectric PCB (300 \(\upmu\)m) to the bond-pad pitch on the PIC (100 \(\upmu\)m); (**c**) Microscope image of the ‘tape’ or ‘ribbon’ wire-bonds used to connect the PCB to the ceramic interposer; (**d,e**) On-PIC high-speed transmission lines in the co-planar ground-signal-ground geometry.  
to the PIC, wire-bonds are very sensitive to any shearing force, and so the PIC, interposer, and PCB must be rigidly connected in the the mechanical package. 'Glob top' encapsulation of the wire-bonds with silicone or epoxy can offer further protection, but can only be used in packages where it will not interfere with Fiber-to-PIC coupling, or other integrated components.  
Once transferred to the PIC, the high-speed signals must be routed from the bond-pads to/from the relevant on-PIC components. Although different cross-section geometries are possible on the PCB and interposer (micro-strip, strip-line, and co-planar transmission-lines), Si foundry design rules typically restrict the high-speed transmission lines to a co-planar geometry. To avoid significant losses and reflections, HFSS must be used to optimize these on-PIC transmission lines within the boundary conditions of the very specific materials and layer-thicknesses available at the Si foundry [6; 7; 8].