# Stability of Single Electron Devices: Charge Offset Drift
## 1 Introduction  
Single electron devices (SEDs) confine individual electrons through the classical electrostatic effect known as Coulomb Blockade. This ability to manipulate individual electrons leads to several applications. Metrologists have pursued electron-counting standards for capacitance [1; 2] and current [3; 4; 5; 6; 7; 8; 9; 10] since the realization of SEDs. Others have worked to perform logic or memory applications with SEDs because of the prospect for doing so at very low power [11; 12; 13; 14]. A flurry of work has been done to make SEDs into viable qubits for solid state quantum computing [15; 16]. SED devices as qubits have been successfully implemented in many solid state environments including carbon nanotubes [17], GaAs [18; 19; 20], SiGe [21; 22] and silicon [23; 24] quantum dots, as well as single dopant devices [25; 26].  
Each of these applications would ultimately require the integration of many SEDs. For instance, a useful current standard would give at least 100 nA of current. (The lowest uncertainty calibrated resistors are near 1 M\(\Omega\) resistance and a typical voltage from the Josephson voltage standard is \(\approx\)1 V. Thus a useful current standard would have a current of at least 100 nA, preferably 1 \(\mu\)A.) If this current is obtained in a single SED device, it would require manipulation at THz frequencies. Since errors involved in charge pumping generally increase with the operation frequency, such a standard would be very difficult to implement. Integrating 100 SEDs together operating at 100 times lower frequency would give the same current and might do so at an acceptable error rate. As a second example, consider the field of quantum computing where integration of devices presents a grand challenge. Ultimately, the most fault-tolerant implementation of a quantum computer requires integration of \(10^{8}\) devices including error correcting qubits while obtaining an error threshold of less than 0.1% [27]. Though detailed considerations of what is necessary depend on the actual physical implementation, computation would most easily and efficiently be performed if each individual device is stable during initialization, manipulation, and readout. Clearly, any non-idealities in the device will degrade its operation.  
This review will focus on one such non-ideality, a time instability known as charge offset drift and denoted by \(\Delta Q_{0}\) or \(Q_{0}(t)\). First, we will explain what charge offset drift is, how it is manifested in devices, and how it degrades the prospects for some of the technologies listed above. We will then discuss a compendium of experimental results in metal-based and silicon-based devices as well as devices which combine the two material systems. We will find that the metal-based devices show a large amount of charge offset drift and that all-silicon devices show almost none. Devices made in silicon with metal gates will present an intermediate case. We will then discuss this dichotomy within the framework of glassy relaxation, which is characterized by a collection of two-level systems (TLSs) that evolve toward a global minimum in the free energy by slowly passing through local minima. The microscopic identity of the TLSs in metallic devices is not known. In silicon-based devices, this may be caused by tetrahedra in SiO\({}_{2}\) reorienting or charging and discharging. Finally, we will conclude with a discussion of the prospects for SEDs in light of the nature of the charge offset instability.