## 1 Introduction  
Ensuring pristine and appropriately conditioned surfaces is a critical challenge across all generations of semiconductor packaging technology, directly impacting manufacturing yield and long-term device reliability. Contaminants such as oxides and organic residues on critical interfaces can compromise assembly processes like wire bonding, die attachment, moulding, and underfilling, often leading to package failures such as delamination or poor electrical contact [1,2]. Plasma cleaning has emerged as an indispensable technology to address these surface challenges, offering precise, non-contact removal of contaminants and tailored surface modification capabilities essential for both traditional and cutting-edge packaging solutions.  
For instance, in packages utilizing traditional lead frames--which serve as the structural base and electrical interface for many devices--plasma treatment is vital for removing oxides from copper or alloy surfaces and eliminating organic residues prior to moulding or die attachment, thereby preventing subsequent failures. Typically made from metal alloys such as copper, alloys, or alloy 42 (an iron-nickel alloy), lead frames are designed to ensure efficient heat dissipation and reliable signal transmission. The lead frame's layout includes a central pad for die attachment, with leads extending outward to form the package's terminals. These leads are later trimmed and formed into the final shape, depending on the package type, such as QFP (quad flat package) or SOP (small outline package). Advanced lead frames may also feature plating with silver, gold, or palladium to enhance conductivity and corrosion resistance. The issue with copper lead frames is that oxide formation on the copper surfaces can reduce quality and yields through package failures such as delamination.  
Equally critical is the role of plasma in advanced and emerging packaging paradigms, such as flip-chip, 3D-stacked ICs with through-silicon vias (TSVs), wafer-level packages (WLPs), and hybrid bonding. These technologies, characterized by high interconnect densities, fine features, and diverse material interfaces, often impose even more stringent requirements for surface cleanliness and preparation to achieve the necessary electrical performance and mechanical robustness. Plasma processes are employed here for tasks ranging from cleaning under-bump metallization (UBM) and activating surfaces for under-fill adhesion to preparing TSV sidewalls and enabling direct bonding interfaces.  
This paper provides a comprehensive review of plasma cleaning and surface treatment techniques relevant to semiconductor packaging. It delves into the fundamental mechanisms (physical bombardment and chemical reactions) [2], the different plasma generation systems, common evaluation methods like contact angle measurements [3], and specific applications. This review covers the established use of plasma for lead frame preparation [4] and extends to its crucial functions within various state-of-the-art packaging technologies. Figure 1 presents the flow adopted in this paper showing how the various sections are set up. This is provided to give the reader an easy pictorial reference with regard to the section setup adopted for this paper, thus making it easy for the reader to follow.