# Design of Low-Power ECG Sampling and Compression Circuit
## 3 Proposed Scheme  
### Adc  
SAR ADC has the advantages of simple structure and low power consumption in medium and low-speed applications. Thus, a 12-bit SAR ADC is designed with the circuit structure illustrated in Figure 3. ADC is often inactive in the sampling and compression circuit, so an asynchronous format is adopted to avoid a high-frequency clock. The capacitor array and comparator are optimized to further reduce the area and power consumption and improve the data accuracy. Figure 3: The structure of SAR ADC. Figure 2: The compression and storage structure. The capacitor array can effectively avoid static power and only generate dynamic power when capacitors are switched. However, the area of the capacitor array increases significantly as accuracy improves. Therefore, this paper adopts the top plate sampling scheme and uses bridge capacitors \(C_{\text{Pb}}\) and \(C_{\text{Nb}}\) to divide the capacitor array into a split structure of high 8 bits and low 4 bits, reducing the number of capacitors from 4096 to 288 (92.97%). We choose the monotonic switching scheme, which can reduce the switching power by 81% compared with the traditional scheme [18], and is more suitable for the ECG sampling and compression circuit. The Monte-Carlo simulation is performed to evaluate the influence of capacitor mismatch, and 100 simulations are completed for each capacitance value in the range of 7.02 fF to 21.53 fF. The simulation results are shown in Table 1, listing the corresponding Signal-to-Noise Ratio (SNR), Spurious Free Dynamic Range (SFDR), Effective Number of Bit (ENOB), and the standard deviation of ENOB for different capacitance values. The capacitance value is set to 15.59 fF based on the compromise of area and power consumption. The comparator is the most critical analog module in SAR ADC, and this paper utilizes a bipolar dynamic latch comparator without static power consumption. Since the ECG signal is small and the offset of the existing comparator is typically in the order of tens of millivolts, low-value data can be lost. Therefore, during the pre-amplification stage, the calibration technique is used to reduce the offset voltage. For a two-stage dynamic comparator, the offset voltage comprises a pre-amplification and latch stage offset. The offset voltage of the comparator can be expressed as Equation (4):  
\[V_{\text{OS}} =V_{\text{OSP}}+\frac{V_{\text{OSL}}}{A} \tag{4}\]  
where \(V_{\text{OS}}\) is the offset voltage of the comparator, \(V_{\text{OSP}}\) and \(V_{\text{OSL}}\) are the equivalent input offset voltage of the pre-amplification and latch stages, respectively, and \(A\) is the gain of the pre-amplification stage. The pre-amplifier stage offset is mainly caused by the mismatch of input transistor threshold voltage (\(V_{\text{TH}}\)), width-to-length ratio (\(W/L\)), and load capacitance (\(C_{\text{L}}\)) [19], as shown in Equation (5):  
\[V_{\text{OSP}} =\Delta V_{\text{TH}}+\frac{V_{\text{GS}}{-}V_{\text{TH}}}{2} \times\left(\frac{\Delta W/L}{W/L}+\frac{\Delta K^{\prime}}{K^{\prime}}- \frac{\Delta C_{\text{L}}}{C_{\text{L}}}\right),\ \ \Delta V_{\text{TH}}=\frac{A_{\text{VT}}}{ \sqrt{WL}} \tag{5}\]  
where \(K^{\prime}\)\(=\)\(1/2\mu_{n}C_{\text{ox}}\), \(\Delta V_{\text{TH}}\), \(\Delta W/L\), and \(\Delta C_{\text{L}}\) are threshold voltage mismatch, width-to-length ratio mismatch, and load capacitance mismatch, respectively, and \(A_{\text{VT}}\) is the threshold voltage mismatch coefficient. This paper adopts a digitally-assisted analog fine-tuning technique and places the auxiliary transistors \(\text{M}_{\text{OCP}}\) and \(\text{M}_{\text{OCN}}\) on both sides of the input pair transistors. By applying an unbalanced voltage to the gate of the auxiliary transistors, the current on the corresponding branch of the comparator is changed, thus reducing the influence of the MOS transistor offset.