## 3 Design and Implementation of Emulators in Hardware in the Loop
### Boost Converter  
For the calculation of the design parameters of the DC-DC boost PEC, a PVP of 430 W from the supplier Topsun Co., Ltd., Jeonnam, South Korea [60] was considered, taking as the operating point, the maximum power point, with this, the input voltage of the converter will be the maximum power voltage. In addition, a voltage ripple, \(v_{r}\), of 5%, a switching frequency, \(f\), of 10 kHz and an inductor resistance, \(r\) of 0.09375 \(\Omega\) were defined. To calculate the load resistance \(R_{L}\), the \(V_{out}\) in steady state was considered, with a duty cycle \(D\) of 50% and with the \(i_{L}\) equal to the \(I_{mpp}\); this condition satisfies Equations (11) and (12). \[(1-D)i_{L}(t)-\frac{1}{R}V_{out}(t)=0 \tag{11}\]  
\[V_{out}=\frac{V_{in}}{1-D} \tag{12}\]  
On the other hand, for the calculation of the minimum values of \(L\) and \(C\), Equations (13) and (14) were used. The design parameters obtained with this process are presented in Table 3.  
\[L_{min}=\frac{(1-D)^{2}(D)(R_{L})}{2f} \tag{13}\]  
\[C_{min}=\frac{D}{(R_{L})(f)(v_{r})} \tag{14}\]  
In Equation (15), the PEC model used for the design of the boost converter emulator (BCE) is presented. This model was proposed with a pair of integrals for the state variables \(i_{L}\)(\(t\)) and \(V_{out}\)(\(t\)). \[ \begin{array}{c}i_{L}(t)=\frac{1}{L}\int\ [-ri_{L}(t)-(1-D)V_{out}(t)+V_{in}(t)]dt\\ V_{out}(t)=\frac{1}{C}\int\ [(1-D)i_{L}(t)-\frac{1}{R_{L}}V_{out}(t)]dt\end{array}  \tag{15}\]  
For the implementation of the integrals in the FPGA, the trapezoidal integration method was used, in this way, if the state variables are denoted with \(x\), the integral can be calculated according to Equation (16). Figure 11 shows the algorithm used for the implementation of Equation (16) in the FPGA with a period of 10 usec. \[x(t)=\int\limits_{TK}^{T(K+n)}\frac{dx(t)}{dt}dt\cong\frac{T}{2}\sum\limits_{ j=1}^{n}[x\
u(T(K+j-1))+x\
u(T(K+j))] \tag{16}\] \begin{table}
\begin{tabular}{c c} \hline \hline
**Variable** & **Data Type Selected** \\ \hline \(V_{in}\) & 49.25 V \\ \(V_{out}\) & 98.5 V \\ \(R_{L}\) & 25 \(\Omega\) \\ \(f\) & 10 kHz \\ \(v_{r}\) & 5\% \\ \(r\) & 0.09375 \(\Omega\) \\ \(C\) & 45.8 uF \\ \(L\) & 400.5 uH \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Parameters obtained from the converter design. Applying Equation (15) and the algorithm proposed for the integral, the code to obtain \(i_{L}(t)\) was developed as shown in Figure 12. While the code to model the output voltage \(V_{out}(t)\) is illustrated in Figure 13.  
To define the weight of the type of data at the output of each operation through the data flow in this virtual instrument (VI), a series of experiments were carried out in which the behavior of the open-loop system was observed. The number of bits allocated was gradually reduced until reaching a break-even point; wherein the numerical precision provides a suitable approximation without using more bits than is necessary for this purpose. The methodology used to define these weights is based on [59] p. 63. To define the integration period, a similar procedure was carried out. Initially a period was assigned and an experiment was carried out, observing the behavior of the output of the open-loop system. Subsequently, the period was reduced and the weight of the selected data type was modified in the constant that represents this data (T/2 in Figures 11-13). As the data type weights change, the time required to run a simulation step also changes. The process described is carried out interactively until the programmed period corresponds to the actual execution period. Another aspect that must be considered is that the algorithm for calculating the integrals depends on the voltage value calculated in  
Figure 11: Algorithm for calculating the integral. Figure 12: Code for the calculation of \(i_{L}(k)\). Figure 13: Code for the calculation of \(V_{out}(k)\). the PVPE, so that the integration period must be greater than the time that the PVPE takes to execute a step.