# Configurable Hardware Core for IoT Object Detection
## 5 Results
### Comparison with Other FPGA Implementations  
The proposed implementation was compared with previous accelerators of Tiny-YOLOv3. We report the quantization, the operating frequency, the occupation of FPGA resources (DSP, LUTs, and BRAMs), and two performance metrics (execution time and frames per second). Additionally, we considered three metrics to quantify how efficiently  
Figure 9: The number of cores versus frames per second of each configuration of the architecture. The graphs indicate the configuration as number of lines of cores and number of columns of cores).  
\begin{table}
\begin{tabular}{l c c c} \hline \hline
**Software Version** & **Platform** & **CNN (ms)** & **FPS** \\ \hline Floating-point & CPU (Intel i7-8700 @ 3.2 GHz) & 819.2 & 1.2 \\ Floating-point & GPU (RTX 2080 ti) & 7.5 & 65.0 \\ Floating-point & eGPU (Jetson TX2) [43] & - & 17 \\ Floating-point & eGPU (Jetson Nano) [43] & - & 1.2 \\ Fixed-point-16 & **ZYNQ7020** & **140** & **7.1** \\ Fixed-point-8 & **ZYNQ7020** & **68** & **14.7** \\ \hline \hline \end{tabular}
\end{table}
Table 9: Tiny-YOLOv3 execution times on multiple platforms.  
the hardware resources were being used. Since different solutions usually have a different number of resources, it is fair to consider metrics to somehow normalize the results before comparison. FSP/kLUT, FPS/DSP, and FPS/BRAM determine the number of each resource that is used to produce a frame per second. The higher these values, the higher the utilization efficiency of these resources (see Table 10).  
The implementation in [39] is the only previous implementation with a Zynq 7020 SoC FPGA. This device has significantly fewer resources than the devices used in the other works. Our architecture implemented in the same device was 3.7X and 7.4X faster, depending on the quantization. For the same 16-bit quantization, the FPS/kLUT, FPS/DSP, and FPS/BRAM metrics of the proposed architecture were 3.5\(\times\), 2\(\times\), and 3\(\times\) better, respectively. This shows that besides allowing smaller data quantizations, the architecture also improves the utilization efficiency of the FPGA resources for the same ZYNQ7020.  
Compared to [40], the proposed work was slower and less efficient in terms of BRAMs but more efficient in terms of LUT and similarly efficient in terms DSP. The lower BRAM efficiency has to do with the fact that BRAM contents (weights and activations) are shared by multiple cores. An architecture with more cores has a higher FPS throughput, and each BRAM feeds more cores, which increases its utilization efficiency. However, this work used only a quarter of the resources, ran in a low-cost FPGA, and used the LUTs more efficiently. The work [38] used 8-bit quantization to increase the throughput at the cost of accuracy. Besides, it ran in a high-density FPGA not appropriate for IoT and only considered a limited target dataset. The number of resources was also not reported.  
The work in [41] did not provide the performance of the architecture, only the occupied resources. The solution had a high utilization of LUTs and considered a quantization of 18 bits. This quantization takes advantage of the size of DSP multipliers (\(18\times 25\)) and BRAMs (can be configured with 72 of datawidth). However, it does not match the external memory bandwidth (usually 32 or 64 bits). This mismatch complicates data transfer.