## 4. Jitter Generation Method  
This section details the methods of jitter generation, including digital synthesis and logical combination method for high-precision jitter generation. Figure 3 shows that the digital synthesis method of generating controllable jitter can be divided into clock and data recovery circuit (CDR), jitter generation, delay compensation, jitter synthesis, and logical combination. The method is described in detail referring to the jitter generation block diagram. The core idea of this paper has two points. The first point is to use digital synthesis to generate jitter. It is necessary to generate delay via a field-programmable gate array (FPGA) and programmable delay line for digital synthesis, where FPGA controls jitter frequency and programmable delay line controls jitter amplitude. The second point is to use logical combination to select the signal edge of generating jitter. The jitter of the falling edge is directly generated by the AND gate, and the jitter of the rising edge is excited by the XOR gate and then through AND gate. The data pattern is obtained by fanning out from the input data pattern when selecting signal edges. The jitter generation circuit generates jitter clock by using a field-programmable gate array (FPGA) and programmable delay line, which control frequency and amplitude of jitter separately. This circuit is mainly divided into three parts, as shown in Figure 4: data processing, digital synthesis, and programmable delay. Data processing is the analysis of the data sent by the host computer; digital synthesis includes variable clock, address generation, ROM waveform, and amplitude processing; and the delay line implements a quantitative delay of the clock signal for jitter generation. The frequency  
Figure 3. Digital synthesis method of generating controllable jitter. of the jitter generation is determined by the clock generating the address and the number of data in the ROM, and the amplitude of the jitter generation is determined by the value of the delay of the delay line. The data processing is to process the address and command sent by the host computer. The different addresses correspond to the amplitude, frequency, and profile control, respectively, and their commands have different control modes. When the frequency control is performed, a control word is sent to control variable clock to change the clock output. When the profile control is performed, the value of the address generator is changed and the different profile of jitter required to be stored in the ROM is read, and when the amplitude control is performed, the amplitude of the data extracted from the ROM is processed by changing the magnitude of the delay. Digital synthesis consists of a variable clock generated by phase-locked loop, an address generator, a ROM look-up table, and amplitude processing. The clock generated by the variable clock is used to control the address generator to generate an address for reading the jitter model in the ROM lookup table and send the jitter model to the amplitude processing. The mathematical jitter model in the ROM lookup table can be modified to any desired jitter model, and the jitter model in this design is a mathematical model of pre-set period jitter. The frequency of the variable clock determines the frequency of the jitter generation. The phase-locked loop used in this design produces a variable clock with a resolution of 1 millihertz (mHz). Therefore, the resolution of the frequency of jitter generation is 1 millihertz (mHz). Programmable delay is used to achieve the clock jitter generation. The programmable delay line used in this design is divided into analog control and digital control. The digital control port of the programmable delay chip implements a minimum delay resolution of 10 ps, the minimum resolution of the analog control is 2 ps, and the analog input of the programmable delay line is controlled and calibrated by a high-precision digital-analog convertor with very fine analog output steps.