# A Novel RFID Authentication Protocol Based on Reconfigurable RRAM PUF
## 4 Protocol Details
### Registration Phase  
At this stage, the Registrar initializes the tag chip. The configuration process is shown in Figure 3a. Perform an initial forming operation on the newly prepared RRAM, so that a stable conductive path is formed inside all RRAM memory cells. At this time, the RRAM cell device presents a low resistance state (LRS). Since the resistance values of different RRAM cells present a more discrete distribution in the high resistance state, a reset voltage of the same pulse width is then applied to all RRAM memory cells row by row, causing the conductive filaments inside the RRAM cell to break and turn into high resistance state. Then, an appropriate reference current \(\mathrm{I}_{\mathrm{REF}}\) is set, so that the RRAM cells whose read data is \"1\" account for about 50% of the total number of cells. (The read operation is specifically that when the read current of the selected RRAM cell is greater than the reference current, the read data is \"1\", and when the read current is less than the reference current, the read data is \"0\".) After completing the above steps, perform the separation resistance operation, specifically applying the set voltage to the RRAM cell whose read data is \"1\", so that the selected cell turns into a low resistance state; applying reset voltage on the RRAM cell whose read data is \"0\", so that the selected cell turns into a high resistance state. The step of separating the resistance described above can improve the stability of data output.The configuration ends until all RRAM cells have successfully completed the configuration and can read stable data normally. After completing the above steps, the relative resistance of each cell can be read out and the \"native model\" RS of the PUF module can be created, and then stored at the legitimate database. The model here is essentially different from the model mentioned in [10]. In [10], the registrar established an approximate model for each PUF module through machine learning, so there is an inevitable error rate. On the other hand, the PUF module itself also has intra-HD, so the final response of the model  
Figure 2: (**a**) Structure of proposed RRAM PUF circuit. (**b**) Microphotograph of the fabricated RRAM array chip.  
may be very unreliable. The model RS in this paper, when inputting an arbitrary challenge, theoretically produces the same response as the entity of PUF.  
In order to reduce the bit error rate of the output, after the configuration is completed, it is also necessary to set the relatively low resistance cell to LRS to increase the resistance difference (similar to the \"Forming\" operation, \"Set\" causes the conductive filaments to form inside the RRAM cell by applying an electric field, but the required voltage is usually much smaller than \"Forming\").  
The reader side stores information <ID', K\({}_{i}\), K\({}_{i-1}\), S, RS> for each tag, where ID is the unique identifier of the tag. K\({}_{i}\) and K\({}_{i-1}\) are keys shared with the tag and will be updated after each authentication. When initializing, K\({}_{i}\) = K\({}_{i-1}\). S is the authentication completion identifier, S = 1 means that the corresponding tag last round authentication is successful, and it is not attacked, and S = 0 means the last round authentication failure. RS is a PUF native model. The tag side saves information <ID, K, M\({}_{0}\)>, in which ID is the unique identification number, K is the key shared with the reader side, and is updated after each authentication. M\({}_{0}\) is the seed of random number.