## 2 System Architecture and Design Principles
### Optimization of OOK Demodulation Design  
The implementation of OOK modulation on FPGA platforms offers significant advantages, including simplicity, efficiency, and low resource utilization, making it ideal for resource-constrained environments. Its binary nature minimizes power consumption, while its inherent robustness enhances performance in challenging conditions. Furthermore, FPGA flexibility enables seamless integration of OOK with signal processing tasks like error correction and filtering, simplifying system design and improving overall performance. This combination provides a cost-effective solution, reducing hardware costs while leveraging FPGA versatility for scalable system development [12; 35; 36; 44]. However, OOK performance can be degraded by turbulence, noise, and interference in complex environments [50]. To address these challenges, this study optimizes OOK demodulation and incorporates digital signal processing techniques, including AGC, MF, and BEDF, to enhance the system's anti-interference capabilities. First, a fully digital AGC system was designed to reduce the impact of optical intensity scintillation on demodulation sensitivity, which is caused by underwater turbulence, bubbles, and suspended particles. The technique employs a closed-loop feedback mechanism, whose core function is to dynamically adjust the system gain by calculating the average energy of the sampled signal through a sliding average filter and comparing it to a predefined threshold. This process ensures that the output signal amplitude remains within the desired range. The system's principle is illustrated in Figure 5. First, the analog signal output from the APD is converted from analog to digital by a 12-bit ADC. The converted digital signal \"_Adc_data_\" is then processed by the absolute value module to obtain the amplitude information of the signal. Next, the absolute value \"_Abs_data_\" is fed into an  
Figure 4: Structure diagram of RS decoding. average accumulator, which averages 32 samples under the control of a counter to achieve sliding-average filtering and obtain the average value of the signal amplitude. This average value \"_Ave_data_\" is subsequently compared with a preset threshold \"_Aim_avg_\". The result of the comparison is used to calculate a dynamic gain coefficient. In order to smooth this gain coefficient, it is fed into a filter to obtain a smoothed feedback coefficient. This feedback coefficient \"_Gain factor_\" is used to make closed-loop dynamic adjustments to the \"_Adc_data_\" for automatic gain control. This FPGA-based solution offers greater flexibility and portability than analog AGC. By precisely realizing these operations on the FPGA, the algorithm parameters can be flexibly adjusted to suit different application requirements and environmental conditions. In addition, the programmability of FPGAs allows for rapid reconfiguration and upgrading of the system without the need to change the hardware, thus increasing the adaptability and maintainability of the system. After that, the output signal \"_AGC_data_\" after gain control is demodulated; in order to prevent spike noise and burr interference in demodulation, we designed MF and BEDF for processing, respectively, and the optimized demodulation structure is shown in Figure 6. First, the input signal \"_Din_\" undergoes rectification and low-pass filtering. The spike noise within the envelope signal of the filtered output is removed through MF, with the filter window size selected as 9 based on simulation results. The process of implementing MF on an FPGA begins with the low-pass filtered output signal, which is first fed into a shift register that stores the most recent nine samples of data (\(d_{1}\) to \(d_{9}\)). These samples are then divided into three groups, each containing three samples. Within each group, the samples are sorted to determine the maximum, median, and minimum values. Next, the median value from each group is selected to form the final output \"_Dout_\".