# Highly Adaptive Reconfigurable Receiver Front-End for 5G and Satellite Applications
## 6 HARRF SPDT Design
### Series vs. Shunt FET Configuration  
* Series FETs: Used primarily to handle higher power and to lower the ON resistance. By stacking multiple FETs in series, the drain-source voltage across each FET is reduced, mitigating breakdown issues at high power levels or high operating voltages.
* Shunt FETs: These help improve isolation by providing an alternate low-impedance path to ground when they are turned ON (pinched-off for the main path). In the distributed design, the parasitic off-state capacitance of the shunt FETs can be absorbed into the matching network, effectively extending the bandwidth of operation.  
In this design, each series FET is sized at \(3\times 275\) um to provide the necessary current handling capability. Table 4 shows some key design requirements and corresponding simulated performance at three spot frequencies (10 GHz, 26 GHz, and 38 GHz).  
From Table 4, it can be seen that the design meets or exceeds the typical requirements for reflection coefficients (\(S_{11}\) and \(S_{22}\)) and isolation (\(S_{12}\)) across a wide frequency range. The insertion loss (\(|S_{21}|\)) is also held to approximately 3 dB or less, which is acceptable for many wideband radar, 5G, and SATCOM front-end applications.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Band** & \(\mathbf{V_{d2}}\) & \(\mathbf{V_{d3}}\) & **SPDT On-State** & **SPDT Off-State** \\ \hline Left Arm & 0 V & 2 V & \(-1.5\) V & 0 V \\ Right Arm & 2 V & 0 V & 0 V & \(-1.5\) V \\ \hline \hline \end{tabular}
\end{table}
Table 3: Brain voltage states for switchable wideband receiver front-end with SPDT.  
Figure 18: Schematic of the distributed SPDT switch. Each branch has two series FETs and four stacked shunt FETs to achieve broadband operation and improved power handling.  
The considerable insertion loss in the wideband SPDT switch is due to several reasons, including resistive losses in the switching transistors, parasitic capacitances, impedance mismatches, and substrate losses. At elevated frequencies (exceeding 60 GHz), \(S_{21}\) (transmission coefficient) markedly declines, attaining \(-12\) dB at 90 GHz, signifying substantial power attenuation. Resistive losses from the on-state resistance (\(R_{o}n\)) elevate insertion loss, whilst parasitic capacitances (\(C_{d}s,C_{g}d\)) cause frequency-dependent attenuation, hence diminishing transmission efficiency as capacitance-related reactance decreases with rising frequency. Mismatch losses are apparent in the elevated \(S_{11}\) and \(S_{22}\) values, resulting in signal reflections and decreased power transfer efficiency, while dielectric and substrate losses further impair performance at millimetre-wave frequencies. The cumulative insertion loss can be quantitatively represented as the total of resistive, capacitive, and mismatch-induced losses, with high-frequency signal attenuation intensified by substrate dielectric loss. To alleviate these losses, it is advisable to implement design optimisations, including the reduction of \(R_{on}\) through shorter gate-length FETs, the minimisation of parasitic capacitances using enhanced layout approaches, the improvement of impedance matching through multi-stage networks, and the use of low-loss dielectric substrates. Employing these strategies can markedly enhance the switch's performance for millimetre-wave and 5G applications, guaranteeing improved signal integrity and reduced insertion loss over the operating frequency spectrum.  
Table 4 (shown earlier) summarises the design requirements and performance at spot frequencies of 10 GHz, 26 GHz, and 38 GHz. The proposed switch meets or exceeds these requirements, thereby satisfying minimum industry standards.