# Phase Calibrated Ring Oscillator PUF Design and Application
## 4 Phase Calibrated PUF
### Phase Calibration Process  
The Phase Calibration Process (PCP) is a critical part of our solution, which aims to measure the frequency of ROs quickly and accurately. The basic idea is to shift the phase of the RO output signal in order to eliminate asynchronous timing measurement error. To implement it on FPGAs, we use a primitive that offers a programmable delay function, i.e., Xilinx provides an input delay resource called IDELAYE2 [19]. It can be accessed directly from the FPGA logic and allows incoming signals to be delayed on an individual input pin basis. Figure 9 shows the IDELAYE2 primitive, which offers a variable delay mode that can control the delay value after configuration by manipulating the control signals CEand INC. When CE goes high, the increment/decrement operation begins on the next positive clock edge. The programmable delay taps into the IDELAYE2 primitive wrap-around. When the last tap delay is reached (Tap 31), a subsequent increment function will return to Tap 0. In Figure 9, a reset is detected (LDis High) in the first clock event, causing the output DATAOUT to select Tap 0 as the output from the 31-tap chain. In the second clock event, a pulse on CE and INC is captured on the rising edge of C. This indicates an increment operation. The output changes without glitches from Tap 0 to Tap 1. In the third clock event, CE and INC are no longer asserted, thus  
Figure 8: Intra-PUF Hamming distance without ECC.  
completing the increment operation. The output remains at Tap 1 indefinitely until there is further activity on the LD, CE or INC pins.  
The architecture of our Phase-Calibrated PUF (PCPUF) is shown in Figure 10. It mainly consists of a 128-RO array, a control unit, a comparison unit, a pair of decoders, MUXes, IDELAYE2s and counters. The tap control is to control the delay of IDELAYE2. Since PCP requires a strict RO enable timing, only one selected RO pair is enabled in the measurement period. Otherwise, the control unit resets all the ROs.  
Algorithm 2 shows the details of the PCP. In order to generate a one-bit response, the first two seven-bit values of the challenge register are loaded to the register \(addr\_A\) and register \(addr\_B\). After checking the values, we reset \(CounterA\) and \(CounterB\). The tap value is loaded to IDELAYE2 primitives before being added by one. By default, the tap value is zero. When the delay is set, the control unit enables the selected RO pair and starts testing. Each measurement takes 16 clock cycles. Then, the tap value is added by one, and the new measurement starts. Between two measurements, the selected RO pair is kept disabled before the delay is set. When we complete the test from Tap 0 to Tap 31, a one-bit output is generated by comparing the counter values. Then, the challenge register shifts its value and launches the next response generation. Though the PCP slows down the response generation compared to the traditional RO PUFs, the PCPUF still keep an output speed of 625,000 bit/s.  
Figure 10: Architecture of Phase-Calibrated PUF (PCPUF).  
Figure 9: Input delay resource and timing diagram.  
```
1:procedurePCP
2:\(tap\gets 0\)
3:Loop 1:
4: reset \(CounterA\), \(CounterB\)
5: load \(addr\_A\), \(addr\_B\)
6:if\(addr\_A=addr\_B\)then\(addr\_B\getsaddr\_A+1\)
7:Loop 2:
8: load \(tap\) to \(IDELAYE2\)
9:\(tap\gets tap+1\)
10: enable \(RO(addr\_A)\), \(RO(addr\_B)\)
11:Loop 3:
12: enable \(CounterA\), \(CounterB\)
13: read \(RO(addr\_A)\), \(RO(addr\_B)\)
14:if\(count\ cycle<16\)thengoto Loop 3
15: keep \(CounterA\), \(CounterB\)
16: disable \(RO(addr\_A)\), \(RO(addr\_B)\)
17:if\(tap<32\)thengoto Loop 2
18:if\(CounterA>CounterB\)then
19: output 1
20:else
21: output 0
22: shift \(Challenge\)
23:goto Loop 1.
```  
**Algorithm 2** PUF phase calibration process.