## 3 Proposed Scheme
### Error-Detecting and -Correcting Scheme
#### 3.2.2 Error Correcting
\begin{table}
\begin{tabular}{c c c c c c c c c c c c c c} \hline \hline \multicolumn{2}{c}{**Error Symptom**} & \multicolumn{1}{c}{**Error Occur Probability of Possible Error Patterns**} \\ \hline
**Parity Check1** & **Parity Check2** & & & & & & & & & & & & \\ \hline \(\times\) & \(\surd\) & \(\surd\) & & & & & & & & & & & \\  & & & & & & & & & & & & & & \\ \hline \multirow{4}{*}{\(\times\)} & \multirow{4}{*}{\(\times\)} & \multirow{4}{*}{\(\times\)} & \multirow{4}{*}{\(\times\)} & \(P_{br(i,4)}\) & \(P_{br(i,5)}\) & \(P_{br(i,6)}\) & \(P_{br(i,4)}\) & \(P_{br(i,5)}\) & \(P_{br(i,6)}\) & \(P_{br(i,6)}\) & \(P_{br(i,6)}\) & \(P_{br(i,6)}\) & \(P_{br(i,6)}\) & \(P_{br(i,6)}\) & \(P_{br(i,6)}\) \\  & & & & & & & & & & & & & & \\ \cline{1-1}  & & & & & & & & & & & & & & & \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Error Occur Probability of error patterns based on error symptoms. position check result is not 0 (the second error mode), execute Step 3. Step 2: The first mark position verification failed, and the first mark position test was successful. (a) Single-bit error: The error is considered in the non-repeat region of the row. Step a1-1: Select the lowest-channel-reliability bit from the non-repeat area, flip the position, and check the line for errors again. If the test result is 0, the error correction is complete; otherwise, continue the error correction. Step a1-2: Select the bit with the second-lowest channel reliability from the non-repeat area of the line, and check the line for errors again. If the test result is 0, the error correction will be completed (in the application process, only the bit with the second-lowest reliability may not be selected, and the lowest-reliability bit can be selected for flipping one by one); otherwise, execute (b). (b) Double-bit error: Two errors are considered to occur in the non-repeat region of the row \(i\). Step b1-1: Combine the first line non-repetition zone bits, select the bit combination with the lowest channel reliability (bit channel reliability multiplication), flip the two positions, and check the line for errors again. If the test result is 0, the error correction is complete; otherwise, the error correction continues. Step b1-2: Select the bit combination with the second-lowest reliability, flip the two positions, and check the line for errors again. If the test result is 0, the error correction is complete; otherwise, the error correction fails and the error correction ends. (In the application process, the bit combination with the second-lowest reliability may not be selected according to the device performance and requirements, and the lowest-reliability bit combination can be selected for flip verification.) Step 3: Error mode: The first mark position check failed, and the first position mark test failed. (This indicates that the same error occurred with high probability in two checks.) (a) Single-bit error: The error occurs in two adjacent rows. Step a2-1: Select the lowest-channel-reliability bit from the row repetition area, flip the position of the bit, and check the line for errors again. If the test result is 0, the error correction is complete; otherwise, the error correction continues. Step a2-2: Select the bit with the second-lowest channel reliability from the row repetition zone, flip the bit, and check the error of the line again. If the test result is 0, the error correction is complete; otherwise, continue the error correction. (In the application process, the bit combination with the second-lowest reliability may not be selected according to the device performance and requirements, and the lowest-reliability bit combination can be selected for flip verification.) (b) Two-bit error: Both errors are considered to occur in two adjacent rows, or one in the non-repeat region and one in the non-repeat region.