# A 13.44-Bit Low-Power SAR ADC for Brain-Computer Interface Applications
## 2 Circuit Topology
### Capacitive DAC Array Design
To ensure proper binary weighting accuracy, the smallest capacitor in the MSB array must maintain precisely twice the weight of the largest capacitor in the LSB section--this critical ratio guarantees that when applying VR step inputs at test points 1 and 2, the resulting DAC output voltage Vo exhibits correct code transition behavior meeting the \(dV_{01}=2 dV_{02}\) relationship, and:  
\[dV_{O1}=\frac{KC_{u}(C_{a}+C_{LI})}{X}\cdot V_{R}, \tag{8}\]  
\[dV_{O2}=\frac{2^{L-1}C_{a}C_{u}}{X}\cdot V_{R}, \tag{9}\]  
where the variables \(C_{u}\), \(C_{a}\), and \(C_{LI}\) represent the unit capacitance serving as the fundamental weighting element, the bridge capacitor that couples the MSB and LSB arrays while compensating for voltage division effects, and the total LSB capacitance incorporating both designed values and parasitic components, respectively. Hence, we derive that:  
\[\frac{C_{a}}{C_{u}}=\frac{k}{2^{L}-k}\frac{C_{LI}}{C_{u}}, \tag{10}\]  
\[C_{LI}\geq\left(2^{L}-1\right)C_{u}, \tag{11}\]  
Simplification yields the following:  
\[\left\{ \begin{array}{l}\frac{C_{a}}{C_{u}}\geq 1,K=1\\ \frac{C_{a}}{C_{u}}>K,K>1\end{array} .\right. \tag{12}\]  
The finalized bridge capacitor values under various K conditions are presented in Table 1.  
Figure 10: Segmented CDAC architecture. Furthermore, the bridge capacitor's value is determined solely by the parasitic capacitance associated with the LSB capacitor array while remaining independent of MSB parasities--this critical distinction arises because the MSB parasitic components merely introduce a constant charge offset that uniformly scales the DAC's gain factor without affecting code-to-code transition linearity, whereas LSB parasities directly modify the inter-segment charge division ratio and, thus, must be explicitly compensated through careful bridge capacitor sizing to maintain the required \(\mathrm{C_{a}/C_{Lt}}\) proportionality that ensures monotonic step progression. The incorporation of redundancy effectively corrects comparator decision errors typically caused by four key factors: parasitic resistance and inductance in power/ground routing that induce supply voltage ripple, the limited driving capability of the \(\mathrm{V_{REF}}\) buffer, the excessive settling time from large RC time constants in the CDAC capacitor switch network, and intrinsic comparator noise. This redundancy creates multiple digital code representations for single analog values (e.g., value 4 mapping to both 01000 and 00111 codes) through strategically allocated decision threshold overlap, thereby establishing error tolerance margins that absorb timing uncertainties and noise-induced metastability while maintaining conversion accuracy. In the CDAC array of this design with redundancy insertion, the redundancy allocation per bit is tabulated as shown in Table 2.  
The unit capacitance \(\mathrm{C_{u}}\) in the CDAC is bound by two critical factors:  
1. \(\mathrm{kT/C}\) noise constraint The quantization noise of an ADC must exceed its sampling thermal noise. \[\frac{kT}{C_{unit}}\leq\frac{V_{REF}^{2}}{12.2^{2N}}\Rightarrow C_{unit}\geq \frac{12\cdot 2^{24}kT}{V_{REF}^{2}}=96.4\ \mathrm{fF}.\] (13)
2. Capacitor mismatch Process variations and parasitic capacitance introduced during the layout design inevitably cause capacitor mismatch.