## 8 Comparison with Other Emerging Interconnect Technologies  
In the last few years, several alternative interconnect technologies have been envisioned for novel intra-chip and inter-chip communications. 3D integration using TSVs is a methodology for stacking multiple active dies to reduce the planar distance between them. Dense TSVs over short vertical distances can provide high data rates between multiple dies for low power consumptions. However, 3D integration with TSVs require precise alignment of dies to avoid structural damage to the TSVs. Moreover, due to the reduced footprint of 3D ICs, the power dissipation density and temperature of 3D ICs can be very high requiring sophisticated cooling mechanisms such as microfluidic channels [18]. As an alternative to 3D integration, 2.5D integration has emerged more recently. In 2.5D integration, a substrate board or a silicon interposer is used to integrate the various chips in the system, which may include 3D stacks of memory subsystems [96]. The interposer itself is a recent technology where a relatively large bare silicon die with metal routing layers provides interconnection between the chips attached to it [15]. This reduces the stringent demands on the fabrication technologies of the 3D processes such as die alignments. However, the system performance is limited by the bandwidth density and on-die global wire characteristics of the interposer. Chip-to-chip photonic interconnects have emerged as another enabling technology for high bandwidth interconnections [13]. In [97] the authors report the design of a large-scale microprocessor with 70 million transistors that are capable of communicating using light using fabrication CMOS manufacturing processes without any special steps for the silicon-photonic devices. A chip-to-chip monolithically integrated photonic interconnects is proposed in [98]. A unified inter and intra-chipoptical interconnection networks are discussed in [99]. In the photonic multi-chip system, the inter-chip communication happens through high bandwidth photonic interfaces. However, photonic interconnect poses many new challenges such as huge static power consumption, particularly due to the on-chip laser sources. The laser source used for optical signal generation typically has very low efficiency and are difficult to fabricate using SOI technology [100]. The micro-ring resonators used in the optical interconnect architectures needs thermal tuning as its wavelength selectivity varies with temperature. Moreover, the photonic signal cannot be buffered directly and therefore requires electrical conversion and hence introduce electro-optic conversion delay. RF-Interconnects with microstrip waveguides were proposed to provide data freeways in intra-chip NoCs as well as chip-to-chip communications [28; 101]. The Zenneck surface wave interconnect (SWI) is an emerging interconnect which is essentially an inhomogeneous 2D electromagnetic wave (EM) supported by a surface. The surface is a designed waveguide that traps the EM in two dimensional media [54]. As a result, the electrical-field decay rate in the SWI from the source horizontally along the boundary is around (1/\(\surd\)d) where d is the distance from the source [54]. This low power dissipation allows the SWI to offer relatively linear Joules per bit scaling compared to the higher order scaling of regular global buffered wire interconnects. However, though the surface wave interconnect provides energy efficient multicast/broadcast message transmission the surface itself needs to be designed carefully to match the desired impedance. Therefore, designing such surface with precise dimension and material is very challenging. Moreover, making the surface wave incident at the required Brewster angle for maximum transmission efficiency requires additional transducer and hence increase the complexity. THz band communication using Graphene or Carbon Nanotube (CNT)-based antennas [102; 103; 104; 105] has drawn much attention for intra and inter-chip communication as it provides low energy and high bandwidth.