# A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
## 2 Operation Principle of the Proposed DTC
### Circuit Description of 3D Vernier DTC  
The simplified block diagram and timing diagram of the proposed 3D Vernier DTC are shown in Figure 3. Three PLLs (\(\mathrm{PLL_{F}}\), \(\mathrm{PLL_{M}}\) and \(\mathrm{PLL_{S}}\)) with approximate periods are utilized to generate the time difference \(\Delta\)T\({}_{1}\), \(\Delta\)T\({}_{2}\) and \(\Delta\)T. The high resolution is obtained by employing the Vernier principle two times. The main challenge in the circuit design of the proposed DTC is aligning the rising edge of \(\mathrm{S_{F}}\), \(\mathrm{S_{M}}\) and \(\mathrm{S_{S}}\) at the correct time. The accuracy of phase coincidence measurement should be better than 1 least significant bit (LSB) of DTC to distinguish the correct phase coincidence moment. Since the PLLs can realign the rising edges of \(\mathrm{S_{F}}\) and \(\mathrm{S_{M}}\) to \(\mathrm{S_{REF}}\), each rising edge of \(\mathrm{S_{REF}}\) indicates one phase coincidence of \(\mathrm{S_{F}}\) and \(\mathrm{S_{M}}\). Even if there is an error between the two rising edges, it is a constant value decided by the PLLs. Similarly, the rising edge of \(\mathrm{S_{S}}\) can be synchronized to \(\mathrm{S_{REF}}\)_D. \(\mathrm{S_{REF}}\),D is generated from \(\mathrm{S_{REF}}\) by the programmable delay line (PDL), which is realized with D-type flip-flop (DFF) as shown in Figure 4. Because of the DFFs identity among the whole programmable delay line,  
Figure 2: Timing diagram of the proposed three delay lines (3D) Vernier DTC. they have the same synchronization deviation with different input value. Since the step size of this PDL is T\({}_{\rm F}\), SREF_D is a delay of SREF with \(\alpha\)T\({}_{\rm F}\). Therefore, the rising edge of SREF_D is synchronized to S\({}_{\rm F}\). The rising edge of SREF_D indicates the phase coincidence of S\({}_{\rm F}\) and S\({}_{\rm S}\), as shown in Figure 3b. The reset signal S\({}_{\rm RST}\) would periodically reset the counter in the pulse generators. The counters in the pulse generator are reloaded and enabled by S\({}_{\rm RST}\). Thus, the duty cycle of output signals _START_ and _STOP_ would be 50%. The clock of pulse generators are provided by PLLM and PLL\({}_{\rm S}\). The preset value \(2\alpha+\beta\) and \(\alpha+\beta+\gamma\) of pulse generators are generated from the computation unit. Figure 5 shows the schematic diagram of the output pulse generator. After CNTM or CNTS count to 0, the output of the NOR gate will be pulled high. Then the output of the two DFFs will be flipped at the next rising edge of S\({}_{\rm M}\) or S\({}_{\rm S}\). Figure 4: Schematic diagram of a programmable delay line (PDL). Figure 3: Simplified block diagram and timing diagram of proposed DTC: **(a)** Block diagram, **(b)** Timing diagram. Since the logic gates in PDL are synchronized to \(S_{F}\) and the logic gates in pulse generators are synchronized to \(S_{M}\) or \(S_{S}\), the latency mismatch between these signals would cause time error on DTC output. Thus, we insert some delay cells which consist of inverters in the output path of START or STOP signals to compensate for the timing mismatch introduced by the different transmission path. When the proposed DTC is implemented with Stratix III FPGA, the delay in the start path is a little larger than it is in the stop path. The residual different route delays can be compensated for by adding a constant value on the input value X. The Altera Quartus II software can specify the arrival times of different signals at the expense of considerable increases of compilation time and area by enabling netlist optimizations and physical synthesis options [14; 15]. Moreover, the arriving time of \(S_{F}\), \(S_{M}\), \(S_{S}\), STRAT and STOP signals can be specified by _set_input_delay_, _set_max_delay_ and _set_min_dead_ constraints by users. Moreover, the proposed DTC is insensitive to PVT variation because the output signals are synchronized to PLLs' outputs.