# Design and Implementation of a System-on-Chip for Self-Calibration of an Angular Position Sensor
## 3 Calibration Method Design  
### Architecture Description of the Proposed SoC  
The calibration scheme is implemented in a SoC based on the Cortex-M3 processor. The SoC combines software control and hardware calculation for more flexible processing of signals. As shown in Figure 2, the system collects digital signals from the sensors through an analog to digital converter and calibrates the signals through an on-chip self-calibration module, which is performed in the coprocessor. The coprocessor implements signal demodulation and angle calculation, while the parameter configuration and control algorithm is implemented in the Cortex-M3 processor. The General Purpose Input Output (GPIO) is used for signal output during debugging. The Universal Asynchronous Receiver/Transmitter (UART) is used to send measurement data to the computer for further processing. The Phase Locked Loop (PLL) is used to generate the system clock signal, while the Static Random-Access Memory (SRAM) is used to store the program and data.  
Throughout the system architecture, Cortex-M3 is an open source IP processor core for education. As a low-power 32-bit processor, it has been widely used in the embedded field. AHB and APB belong to ARM's Advanced Microcontroller Bus Architecture (AMBA), which defines the data and command communication between the processor core and external devices. It is an industrial bus protocol. They are designed with combinatorial logic for performing the assignment of data and instructions. Among them, AHB is used for high-speed communication with the processor core, and APB is used for low-speed traffic with peripherals. The self-calibration module is a module designed and proposed, and the mathematical principles and implementations involved are described in the next section. The UART implements communication between the system and other communication devices, and supports baud rate generation, data transmission and reception, and interrupt control. Since the module is mounted on the APB, an additional APB-UART interface module design is required. The PLL is a module that generates a clock that drives the entire system, and mainly includes a phase detector, a loop filter, and a voltage controlled oscillator. The design at the FPGA level can call the IP provided by Altera Corporation. SRAM is used to store programs and data. It can be described and designed with registers and combinatorial logic. It can also call IP generation. In the experiment, IP generation method is adopted for design.  
The system has two operation modes: demodulation and calibration. In the demodulation mode, the coprocessor generates sinusoidal, cosine, and DC signals as a set of bases to perform parameter identification of the two sensor output signals. In calibration mode, the coprocessor calibrates the signal based on the parameter values obtained in demodulation mode, and then calculates the angular value measured by the sensor. Demodulation mode operates when the measurement angle signal changes at a certain frequency, while calibration mode does not have this constraint. Both modes allow gating control and the control signal comes from the program running in the Cortex-M3 processor.  
The self-calibration coprocessor is designed for signal demodulation and angle calibration, which is the key system module. The demodulation module is based on least mean square error, which is described in the next section.