# Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology
## 7 Error Analysis  
In this section we analysis the robustness of the proposed design, which comes from two major sources: (1) random bit generation through stochastic switching is much more reliable for MTJ devices; and (2) when information is encoded with random bit streams, complicated operations can be converted into much simpler operation that are typically not only cheaper to implement but also much more error-resilient. In the following, we provide an intuitive explanation of the robustness of our proposed implementation. In our proposed architecture, each signal \(X\) is represented as a stochastic bit stream with its expected value \(\mathbb{E}[X]=p_{X}\). As in a conventional deterministic-based neural network, the value of signal \(X\) in our design will also be distorted with errors manifested by flip errors of its random bit stream. Let \(e\) denote the bit error vector with an expected value \(p_{e}\), the stochastic signal \(X\) thus becomes \(X^{*}=X\bigoplus e\). Mathematically, the expected value of the signal \(X\) with its bit flipping errors can be defined as  
\[p_{X^{*}}=\mathbb{E}[X]=p_{X}+p_{e}(1-2p_{x}) \tag{4}\]  
With the standard definition of mean square error (MSE), the difference between the estimated value \(\widetilde{p}_{X^{*}}\) and the exact value \(p_{X}\) can be written as  
\[E_{X^{*}}=\mathbb{E}[(\widetilde{p}_{X^{*}}-p_{X})^{2}] \tag{5}\]  
In our S-ANN, we assume the estimated value \(\widetilde{p}_{X^{*}}\) to be the average of \(n\) independent random samples of \(X^{*}\), which is equal to \(\widetilde{p}_{X^{*}}=1/n\sum_{i=1}^{n}=X_{i}^{*}\). Therefore, the expected value of \(X^{*}\) can be written as  
\[ \begin{split}& E_{X^{*}}=\mathbb{E}[(\widetilde{p}_{X^{*}}^{2}-p_{X}^ {2}-2p_{X}\widetilde{p}_{X^{*}})]\\ &=(p_{X^{*}}-p_{X})^{2}+\frac{p_{X^{*}}(1-p_{X^{*}})}{n}\end{split}  \tag{6}\]  
Combing Equations (4) and (6) leads to  
\[ \begin{split} E_{X^{*}}&=p_{e}^{2}(1-2p_{X})^{2}+ \frac{1}{n}[p_{X}(1-p_{X})\\ &\quad+p_{e}(1-p_{e}(1-4p_{X}(1-p_{X})))]\end{split}  \tag{7}\]  
This clearly shows that the MSE error of \(X\) depends on both bit stream probability \(p_{X}\) and bit flip error rate \(p_{e}\). With the increasing of bit stream size \(n\), \(E_{X^{*}}\) monotonically decreases. Given a sufficiently large \(n\), \(E_{X^{*}}\) quickly converges. Also, Equation (7) also reveals that the bit stream probability of \(p_{X}=1/2\) has better error resilience. Guided with the above analysis, we have conducted extensive Monte Carlo simulations with 32 as the bit switch. Figure 15 presents our simulation results and clearly shows that our stochastic method possesses inherent error resilience. As such, device or circuit errors have much less effect on the expected value of a stochastic bit stream. Specifically, even a portion of a stochastic bit stream (\(n\) bits in size) are flipped, their negative effect to the overall expected value will be reduced by \(n\) times. More importantly, such an error will be significantly diminished as \(n\) increases. Furthermore, bit flipping in a digital circuit tend to be symmetrical, i.e., equal numbers of \(0-\text{to}-1\text{ s}\) or \(1-\text{to}-0\text{ s}\). As a result, a large portion of bit flipping within a given random bit stream will naturally cancel out, thus posing negligible error on the overall \(X\) value [43]. To further validate our proposed proposed design methodology, we now quantitatively consider various error components in our proposed architecture. MTJ Random Number Generation Error (\(e_{\text{m}}\)) forms the first error component of our stochastic synapse circuit. Mitigating MTJ device variations has been the main focus of many researches. Fortunately, our method utilizes MTJ's probabilistic switching behavior to build up the stochastic computing scheme, therefore quite insensitive to its device variations.