## 6 Evaluation  
The proposed table-based adaptive DPLL algorithm is evaluated by comparing it with the other existing adaptive DPLL algorithms. Arranged in [3], the selected algorithms for comparison are the FAB, FL, and LBCA, which are adaptive DPLL algorithms that continually adjust the noise bandwidth of the DPLL in accordance with the SNR and the dynamic stress in an optimal manner. These algorithms are implemented in the software receiver and evaluated based on two aspects: the phase jitter performance and the computational complexity.  
To compare the phase jitter performance, the standard deviation of the carrier phase tracking error for each adaptive DPLL algorithm is measured numerically for each environmental condition. Figures 16 and 17 show the numerical jitter calculation results with respect to the C/N\({}_{0}\) and jerk, respectively. Each point in the figures is obtained with 100 iterations of the 150 s simulation. As expected, Figure 16 shows that the fixed-bandwidth loop has the largest jitter value, and the proposed algorithm has a similar performance to the FAB. The FL and LBCA have slightly better performances than the proposed algorithm. Figure 17 shows that all the adaptive DPLL algorithms have similar performances for the jerk dynamic stress, while the fixed-bandwidth loop cannot track high dynamic signals.  
The theoretical computational complexities of each adaptive DPLL algorithm are presented in Table 3. To concentrate on the core of the adaptive algorithms, the estimators for the SNR and the dynamic stress are excluded in this evaluation. The proposed algorithm has the smallest amount of calculation because it only contains relatively simple calculations for the determination of the table index and the calculation of the next integration time. On the other hand, the FL has the largest amount of addition (subtraction) and multiplication calculation, while the FAB and LBCA have seventh-root calculations and exponential functions that are relatively heavy operations, respectively. The execution time measurement results for each algorithm are presented in Figure 18. Each algorithm is implemented in C, and the execution time is measured using the clock() function with \(10^{9}\) iterations for each algorithm. Each execution time result of the adaptive DPLL algorithm contains the  
Figure 15: Carrier tracking error at the high dynamics region (500–550 s): **(a)** Proposed algorithm; **(b)** Fixed bandwidth (B\({}_{n}\) = 15 Hz, T = 20 ms). The fixed-bandwidth loop loses lock at approximately 510 s immediately after the jerk dynamic stress occurs. The error for the proposed algorithm increases temporally while the jerk dynamic stress exists and converges to zero immediately after disappearing.  
execution time of the standard loop filter. The comparison results show that the proposed algorithm has a 2.4-5.4 times faster execution time compared to the other algorithms.  
Figure 16: Numerical jitter calculation result with respect to the C/N\({}_{0}\). The proposed algorithm has a similar performance to the fast adaptive bandwidth (FAB). Fuzzy logic (FL) and loop-bandwidth control algorithm (LBCA) have slightly better performances.  
Figure 17: Numerical jitter calculation result with respect to the jerk dynamic stress. All adaptive DPLL algorithms have similar performances.  
From the evaluation results presented in this section, the proposed algorithm has a similar phase jitter performance to the other existing adaptive DPLL algorithms for the various C/N\({}_{0}\) and jerk dynamic stresses, while also having a faster execution time.