## 1 Introduction  
Currently, there are various important integrated circuit (IC) devices, ranging from pivotal calculators to security-sensitive devices. Many of these IC devices face the risk of fault injection attacks. The consequences of these attacks include sudden failure of the IC and the leak of key secret information [1; 2; 3; 4]. Over the years, many fault injection methods have emerged, namely, heavy ion radiation, electromagnetic interference, and laser exposure, posing an increasingly high threat to IC devices. In the field of IC security, widespread attention has been paid to the protection against fault injection attacks [5; 6; 7; 8; 9; 10], resulting in multiple measures to prevent the ICs from being attacked by fault injection. The typical measures include physical protection [11], the hardware/time redundancy (module duplication/re-computation) method [12; 13; 14; 15], and the error detection codes (EDC)-based technique [16; 17; 18; 19; 20; 21; 22; 23]. Among them, the EDC-based technique achieves the best tradeoff between fault coverage and hardware/time overheads [24]. Recently, [PERSON] et al. [25] presented a novel differential fault attack (DFA)-aware floor-planning technique, which mitigates the threat from different fault attacks. The authors confirmed that this technique, involving no algorithm, circuit nature, or protocol, falls into the category of physical protection. Despite being an attractive approach to design secure ICs, the DFA-aware technique is not directly linked to our research, which focuses on the EDC-based technique for fault detection. Finite field arithmetic has important applications in cryptography and coding theory. One of the most essential and complex operation over a finite field is the modular division/inversion (MD/MI) over a prime field. The secure implementation of this operation preludes the security of related cryptographic devices. Because of modular division in cryptography, researchers have paid much attention to it. Various algorithms have been presented to compute modular division. They can be classified into three categories: repeated exponentiation, the extended Euclidean algorithm, and the extended binary GCD algorithm. The extended GCD algorithm is most suitable to be implemented in hardware. Many implementation architectures of this algorithm have been presented [26; 27; 28; 29; 30; 31; 32; 33]. These works made great contributions to improve hardware implementation performance of modular division, however, they did not guarantee the architectures were reliable when the chip was injected into the fault. Considering the reliability of finite field arithmetic, researchers have also developed many fault detection schemes [6; 10; 34; 35; 36; 37; 38; 39; 40]. Some scholars [34; 35; 36] explored deep into concurrent error detection schemes for division/division over the Galois field GF(2m). Based on time redundancy, [PERSON] and [PERSON] [34] put forward a security scheme for MD over polynomial basis and normal basis finite fields but did not implement the proposed scheme. [PERSON] and [PERSON] [35] proposed a fault detection scheme for multiplicative division on GF(2m) based on parity prediction. [PERSON] et al. [36] applied a similar technique to ensure the structural reliability of an extended Euclidean algorithm over GF(2m). The parity prediction scheme is efficient for MD over GF(2m), but not the best choice for arithmetic operations like MD over a prime field. This is because the parity prediction of arithmetic operations is usually more complicated than logic operations. The complexity leads to large area and time overheads. Compared with parity code, arithmetic codes are efficient in protecting arithmetic operations [37]. Some fault-tolerant schemes have been investigated based on different arithmetic codes [6; 10; 38; 39], yet fail to tackle MD over a prime field. Focusing on modular division over a prime field, [PERSON] et al.