## 2 Related Work  
Different firewalls have been implemented in hardware on FPGAs and the results have been presented in the literature. The most common type of firewall is the one often referred to as the stateless firewall. This device does not store the status of the network connection, but every packet is analyzed as it is, by comparing against a set of rules the information contained in the header of the network and transport layers. [PERSON] and [PERSON], in 2018, proposed a network firewall based on an FPGA to monitor Ethernet traffic [28]. The system was implemented on the NetFPGA-1G hardware accelerator that integrates a Xilinx Kintex-7 325T FPGA. The verification of the firewall rules was implemented using a content addressable memory (CAM) for high-speed data search. The firewall was designed with both software and hardware components and its performance was tested on a network with four different Ethernet ports. The results showed that the firewall latency was 402 us and the maximum data throughput was about 800 Mb/s, over two times the data throughput achieved with a Linux-Iptables software firewall. [PERSON] et al., in 2017, presented the design of an Ethernet firewall based on an FPGA [29]. The proposed system was implemented on an Altera EP4 CE115F29 FPGA, exploiting a microcontroller (NXP Semiconductor MK60 DN512 VLQ10) to test the firewall rules based on a whitelist approach and two external devices (Marrell Technology 88E111) to handle the physical layer of the Ethernet protocol. Tests were carried out with two PCs exchanging Ethernet data through the firewall, and the results showed that a maximum data throughput of 950 Mb/s and a latency of 61.266 us could be achieved. [PERSON] and [PERSON], in 2018, presented the design and implementation of a hardware firewall using FPGA [30]. The proposed firewall, implemented on a Xilinx Spartan 6 FPGA development board, features logic to compare the packet IP addresses with a set of addresses stored on non-volatile memory to decide if the packet must be transmitted or discarded. The authors reported that the proposed hardware firewall is faster than a conventional software firewall. However, the system was tested only with packets generated on the same FPGA board and with a fixed size of 512 bits. [PERSON] and [PERSON], in 2011, proposed a hardware network firewall on an FPGA [31]. The proposed system was implemented on an Altera Stratix II EP2560F672C5 FPGA and was designed using a NIOS II soft-core 32-bit microprocessor implemented in the FPGA programmable logic, an Ethernet module LAN91C111 (Microchip Technology) to handle the physical and medium access control layers of the Ethernet protocol, two RAM modules to store the firewall rules and a CAM for low packet processing latency. The system was tested by interfacing the firewall with two PCs used to generate packets. The measured packet processing time was 1.24 us for ARP packets and 1.76 us for ICMP packets. [PERSON] et al., in 2016, presented an FPGA-based firewall for enhancing the security of IP networks [32]. The proposed firewall architecture features packet filtering algorithms realized with circuits implemented in the FPGA programmable logic, two cores of an ARM Cortex A9 microprocessor, 1 GB of dynamic RAM (DDR3) and an SD card reader to store the microprocessor OS and statistical data generated by the firewall. The proposed architecture was simulated for both Xilinx and Altera FPGAs, and a maximum working clock frequency of 300 MHz was estimated. [PERSON] et al., in 2019, presented a fully functional FPGA firewall for the detection of cyber-attacks in 5G networks [33]. The firewall was implemented on a P4-NetFPGA development board and was designed using a pipeline to minimize the latency. Tests were carried out by connecting the firewall between two PCs, and the results showed how the firewall latency was only marginally affected by the number of firewall rules. The system was designed for a 10 Gb/s network but a maximum data throughput of 3.67 Gb/s was reported.