# Stability of Single Electron Devices: Charge Offset Drift
## 4 Conclusions  
We have reviewed the experimental results on the low-frequency stability of SEDs known as charge offset drift in three classes of devices. This lack of stability stymies the use of SEDs in many applications, including as a current standard and as qubits, because it precludes integration of SEDs. This charge offset drift instability is most prominent in devices based on the Al/AlO\({}_{x}\) material system. It is essentially not present in SEDs fabricated entirely within the Si/SiO\({}_{2}\) system. Moderate levels of \(\Delta Q_{0}\) are obtained in devices that combine the two material systems.  
The origin of charge offset drift is revealed unambiguously by the power spectral density, \(S_{Q}\), of the noise to be TLS switching events. Distinct TLSs can be found in all-silicon devices by scanning through energy with either temperature or gate voltage. In small numbers, these defects result in a Lorentzian power spectrum. The level of interaction between TLS defects present in the amorphous insulators, AlO\({}_{x}\) and SiO\({}_{2}\), accounts for the large difference in stability between devices fabricated in the different material systems. The TLSs in SiO\({}_{2}\) are not triggered to switch by the switching behavior of other nearby TLSs, while those in AlO\({}_{x}\) interact and result in glassy relaxations of the material. A theory adapted from glassy relaxation qualitatively explains the observation of the non-equilibrium transient relaxation observed in metallic devices in addition to providing a numerical estimate of the frequency of charge offset drift switching events that is in general agreement with the experiments.  
Figure 12: The potential landscape for a two-level fluctuator. Each amorphous insulator has many such potential landscapes described by distributions in \(V\), \(d\), and \(\Delta\).  
The prospects for overcoming the barrier to integration presented by large \(\Delta Q_{0}\) are unclear for metal based devices. Exploration of other material systems may be in order, though it is generally believed that metal oxides are much more defective than SiO\({}_{2}\). There do not appear to be any obstacles to integrating all-silicon SEDs. The usual industry-standard techniques for maintaining excellent device uniformity though high-quality gate oxidation, forming gas anneals, and various cleaning procedures would appear to be enough to integrate these devices. While devices with dots residing in the silicon with Al gate electrodes show smaller drift than metallic devices, the level of drift will make direct integration of these devices a challenge. This is because an unintentional AlO\({}_{x}\) layer is formed at the interface between the SiO\({}_{2}\) gate dielectric and the Al gate layer.  
An interesting area for future work may be the use of silicide gates in the Si/SiO\({}_{2}\) material system. Some silicides, when oxidized, form metallic oxides, while others form SiO\({}_{2}\)[53]. Devices made in this way will help to reduce the resistance of gates made of polySi so that they can be operated at higher frequencies and may reduce the tendency of metallic gates to produce strain-induced barriers [54]. If those devices are also immune to the effects of charge offset drift, they may represent a large advance in the capability of current all-silicon based devices.  
[PERSON] organized and wrote the manuscript. [PERSON] contributed to the scientific ideas and discussion.  
The authors declare no conflict of interest.