# Hard SyDR: A Benchmarking Environment for Global Navigation Satellite System Algorithms +
## 2 Background and Motivation
### The PYNQ Flow  
To the best of our knowledge, no straightforward way to transform Python code into hardware designs exists. We are aware of several Python-embedded Hardware Description Languages (HDLs), including Amaranth [31], MyHDL [32], and Mambo [33], but their use in SyDR would require vast re-development efforts. Moreover, as we only aim for a partial conversion of SyDR, we need a software framework and a hardware platform that support low-overhead communication between each other and with which a synthesizable hardware design can be attained with minimal re-development efforts. These characteristics match exactly the purpose of recent MPSoC and RFSoC systems proposed by the leading FPGA manufacturers, Intel and AMD, which integrate Central Processing Units (CPUs) with an FPGA on a single chip. These platforms enable previously unseen degrees of freedom for implementing processing in the CPUs and FPGA concurrently. For our purposes, the AMD Zynq platform is a relevant example of such a platform as it is easily accessible through the associated Python-embedded PYNQ flow [12; 34]. Thus, we chose the AMD KV260 development board [35] to perform the first implementation of our system. This board is used as our target platform throughout the paper. Zynq chips are logically split into two parts: the Processing System (PS) comprising general-purpose (ARM) CPU cores, caches, I/O devices, etc., and the Programmable Logic (PL) comprising an FPGA [34]. An Advanced eXtensible Interface (AXI)-based Networkon Chip (NoC) serves to interconnect the PS's devices with the PL. The PS-PL interface in particular comprises a total of nine master or subordinate interfaces with bit-widths of either 32 or 64 available from within the PYNQ environment [36], which is specified in more detail in [37], Chapter 35. The PYNQ flow abstracts reasoning about data movement over these interfaces as well as the dynamic loading of different designs (denoted by _overlays_) in the PL from Python code running in the PS [12]. These features render PYNQ an ideal fit for our proof-of-concept implementation and directly enable our partial conversion of SyDR with only the processing algorithms ported to an FPGA. However, to be implemented on an FPGA, a hardware design must be _synthesized_ into a _bitstream_ using AMD Vivado (version 2022.2). This requires algorithms to be written in an HDL like VHDL or (System)Verilog. This implies a step of design conversion either directly from Python to HDL, or from Python via a lower-level language to HDL. Although the first option is more direct, it generally involves long development cycles for design and verification. Instead, we opt for the second option and choose C++ as the intermediate language, as it permits us to shortcut the hardware design process by using HLS to generate HDL code [38]. Both conversion strategies are illustrated in Figure 3.  
Using C++ and HLS has multiple benefits: (1) it reduces the required development efforts; (2) it enables using the AMD Vitis HLS (version 2022.2) flow to automatically configure the interfaces needed between the PS and the PL [12]; (3) it permits testing algorithms without an FPGA board using a library for interfacing external functions with Python, e.g., ctypes [39]; and (4) in the future, it may allow us to explore compiler-enabled AxC techniques such as precision tuning [40]. Moreover, HLS simplifies design space exploration into dataflows, pipelining, and initiation intervals of functions and loops with precompiler annotations [38]. This renders it an ideal fit for our proof-of-concept, benchmarking-focused use case. We are aware that the typical HLS flow tends to produce hardware designs with lower performance and higher resource consumption than expert-written HDL equivalents [41]. Yet, as the latter would require intricate knowledge both of GNSS processing and development in HDLs, we see HLS as a reasonable shortcut to obtain coarse, yet indicative, hardware results.