# FPGA Applied to Latency Reduction for the Tactile Internet
## 2 Related Work  
The authors of [26] presented a tactile internet environment that used a glove type device in conjunction with a robotic manipulator. The environment was developed using a general purpose processor, which made the execution of the algorithms sequential. In order to send the data, the tactile glove produced a latency of approximately \(4.82\,\mathrm{ms}\), and the hardware responsible for performing the inverse kinematics calculations took an interval of \(0.95\,\mathrm{ms}\). The latency values obtained in this application could be improved by hardware structures that allow algorithms parallelization. Studies in the literature demonstrate the benefit of using FPGA to accelerate the sample rate for data acquisition from devices associated with haptic systems. The authors of [27] presented an implementation for controlling a 3-DoF (Degree of Freedom) device. The presented technique proposed to increase the device sampling rate using FPGA hardware together with a real-time operating system (RTOS) in order to increase the resolution acquisition of the stiffness sensor. The control technique presented was developed in 32-bit fixed point, and trigonometric functions were implemented using lookup tables. The work described in [28] presented a control system for one-dimensional haptic devices (1-DoF). The FPGA control implementation used single-precision floating point representation (IEEE std 754) and the algorithms performed all calculations in 50 \(\upmu\)s. The processing time was satisfactory; however, the data frame size to be sent over the network increased with the size of the DoF. This peculiarity can increase latency for more complex haptics systems with many DoFs. In the same topic of previous works, an implementation for bilateral control of single-dimensional haptic devices (1-DoF) was presented in [29]. A more accurate control techniques based on the sliding mode control (SMC) was implemented in FPGA, and to assist in performing the complex calculations, the CORDIC (COordinate Rotation DIgital Computer) was used. The hardware was designed to locally control two devices, one master and one slave. In the implementation, a 24-bit fixed point was used, of which 9 bits in the integer part and 14 bits for the fractional, and the total execution time of the controllers was of 7.2375 \(\upmu\)s.  
The works [27; 28; 29] presented a control that depends directly on the encoder reading of the device motors. Usually in commercial models, accessing the device electronics can be tricky requiring some reverse engineering and specific knowledge to make the appropriate encoder connections. On the other hand, some works abstract the data acquisition and work directly with robotics algorithms. These algorithms may require high computational power that can surpass the capabilities of many general-purpose processors (GPPs) that perform the operations sequentially. Some studies demonstrate the benefit of using FPGA to accelerate robotic manipulation algorithms related to haptic systems. A hardware architecture implemented in FPGA for performing the forward kinematics of 5-DoF robots using floating point arithmetic was described in [30]. In this hardware implementation, all the forward kinematics calculations were performed within 1.24 \(\upmu\)s which represents 67 clock cycles in a frequency of 54 MHz. The equivalent software implementation has a total processing time of 1.61036 ms. Overall, the hardware implementation is 1298\(\times\) faster than the software implementation, which means a considerable acceleration in the forward kinematics processing time. The authors of the paper [31] presented an FPGA implementation of inverse kinematics, velocity calculation and acceleration of a 3-DoF robot.