# Enhancing the SRAM PUF with an XOR Gate
## 5 Discussion  
This research presents a novel SRAM-based PUF design that addresses several limitations of previous designs while maintaining the simplicity and accessibility of SRAM devices. The proposed PUF utilizes two SRAM devices in conjunction with an XOR gate. To evaluate its performance, ten ISSI IS64 WV6416 BLL SRAM chips were tested at three different temperatures: 0 \({}^{\circ}\)C, 23 \({}^{\circ}\)C, and 80 \({}^{\circ}\)C. To ensure accurate measurements, GPIO jumper cables were employed to isolate the SRAM devices from external circuitry and mitigate any thermal influences. A notable limitation of this study is the small sample size of SRAM devices tested. With only ten SRAM devices included, the sample size may not provide sufficient statistical significance for the results. Future research should involve a larger number of SRAM devices to enhance the robustness of the findings. The PUF was evaluated based on three metrics: bit-error rate (BER), inter-bit Hamming Distance (\(HD_{inter}\)), and entropy. The results demonstrated impressive BER performance, with an average BER of 0.2% at the temperature at which it was initially enrolled. However, the average BER increased to approximately 10% where the temperature was furthest from the temperature during enrollment. The increase in BER likely comes from cells that become flaky at different temperatures. When the wrong temperature enrollment is used, some flaky cells may not be detected and may therefore be masked. If temperature is not properly accounted for, the BER is still low enough to allow for correction by ECC or RBC. However, at more extreme values of enrollment and challenge, the BER may become large enough to cause false rejections during authentication, rejecting a valid user. This downside can be mitigated by using multi-temperature enrollment, where a flaky cell at any temperature is masked away during selection. On top of a low BER, the design exhibited a high \(HD_{inter}\) value of 0.4966 and a substantial entropy of 0.9982. Compared to previous SRAM PUF implementations, the SRAM XOR PUF showed superior performance. While the microcontroller SRAM PUF achieved a lower BER, the SRAM XOR PUF performed equally or even better in other metrics. A detailed comparison of the PUF metrics between the SRAM XOR design and previous designs can be found in Table 5. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**BER** & **0 \({}^{\circ}\)C** & **23 \({}^{\circ}\)C** & **80 \({}^{\circ}\)C** \\ \hline
0 \({}^{\circ}\)C Enrollments & 0.0037 & 0.0079 & 0.1043 \\
23 \({}^{\circ}\)C Enrollments & 0.0043 & 0.0025 & 0.0430 \\
80 \({}^{\circ}\)C Enrollments & 0.0753 & 0.0325 & 0.0020 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: The BER of a 1-million-bit-long key at different temperatures when using enrollments taken at varying temperatures. Each key used for BER measurement was 1 million bits long. Moreover, the number of CRPs for our PUF was significantly higher than that for other PUFs. This increased number enhances security by making it more difficult for an attacker to reliably clone the PUF within a short time frame if they have limited-time access to the PUF's challenges and responses. Additionally, a higher number of CRPs provides improved protection against eavesdropping attacks, in which an attacker may attempt to exploit previously known CRPs to reconstruct parts of the authentication key [4]. However, the increase in CRPs comes at the cost of response reliability, which is decreased by approximately 50%. This decline occurs because if just one of the SRAM bits is unreliable, it can render the entire response unreliable. However, a notable drawback was observed in the SRAM devices, specifically the non-uniform distribution of '1's and patterns unique to individual SRAM devices. This device vulnerability poses a potential security risk to the overall PUF design.