# Review of Task-Scheduling Methods for Heterogeneous Chips
## 1 Introduction  
As Moore's Law gradually becomes less effective, traditional chip architectures that rely on improving the performance of a single computing core are increasingly facing significant difficulties. The enhancement of computing power is no longer dependent on increasing the number of transistors. To address this challenge, heterogeneous chip architectures have gradually become an important key technology in modern computing systems. Figure 1 presents the publication and citation statistics of papers related to heterogeneous chips and task scheduling. The data in the figure come from the Web of Science [1]. From 2017 to 2023, the annual average citation growth rate was 29.51%, while the number of papers published each year increased by 100%, as shown in Figure 1. By integrating various types of computing units, such as central processing unit(CPU), graphics processing unit (GPU), field programmable gate array (FPGA), and specialized accelerators, heterogeneous chips can optimize for different task requirements, whichprovides more flexible and efficient computational ability. This architecture not only improves computational density and overcomes the performance limitations of single-processor architectures but also achieves a better balance between power consumption, performance, and cost [2]. Although heterogeneous chips have significant performance improvement potential, their performance is inferior to that of homogeneous chips without appropriate task-scheduling methods. The task-scheduling method of heterogeneous chips faces the following challenges:  
* The computing power, memory bandwidth, and latency of different processing units of heterogeneous chips are very different. Choosing the most suitable processing unit according to the characteristics of the task to avoid the waste of resources is the key problem in task scheduling [3]. * Computational tasks and dynamic changes in heterogeneous chip states increase the complexity of scheduling methods. The arrival time, execution time, priority, and other factors of tasks will change at any time. In contrast, the system load, resource availability, and other factors are also constantly fluctuating, which requires a high degree of real-time and adaptiveness [2]. * Scheduling methods must find a balance between real-time and complexity, especially in heterogeneous chips that accommodate multiple optimization goals. The delay of the scheduling methods directly affects the efficiency of the heterogeneous chip. In addition, the resource conflict between tasks is also a non-negligible problem. Some tasks need to share processing units or have dependencies with each other to improve the problem's complexity [4]. To address these challenges, this paper systematically reviews the first task-scheduling approach for heterogeneous chips. Specifically, the contributions of this paper include three aspects:  
* This paper discusses the challenges of heterogeneous chip task scheduling in-depth, innovatively dividing the scheduling method into two parts: the scheduling framework and the scheduling algorithm, systematically combing the current research status of the heterogeneous chip task-scheduling method. In terms of scheduling framework, this study divides the existing task-scheduling framework into two main types, centralized and distributed, according to the differences in the system architecture and control mode. For the scheduling algorithm, according to the scheduling mechanism, i.e., dynamic, heuristic, mixed, and optimized, five categories are created, and a detailed summary and analysis is provided for each category. Figure 1: Publication and citation trends of papers in the past five years. Based on the in-depth investigation and systematic analysis of recent experiments and evaluation examples, this paper compares the heterogeneous chip task-scheduling method. On the one hand, the experimental evaluation system is based on multiple dimensions, such as load balancing, energy efficiency optimization, and real-time guarantee.