## 3 Results
### Packet Assembling and Sending Times
N/A marks indicate that data collection was attempted but unsuccessful at that particular frequency. Empty cells indicate that measurements were not performed at that frequency. Figure 8: Mean packet assembly times for varying numbers of samples per packet, using optimized hexadecimal representation with bit-shifting (HS). Legend label numbers denote the number of samples in one packet. \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline  & \multicolumn{3}{c}{**Mean Assembly Time [ms]**} & \multicolumn{6}{c}{**STD of Assembly Time [ms]**} \\ \hline \(f_{\text{s}}\) **[Hz]** & **1D** & **2D** & **5D** & **10D** & **1D** & **2D** & **5D** & **10D** \\ \hline
100 & 0.446 & 0.905 & 2.270 & 4.525 & 0.004 & 0.006 & 0.021 & 0.033 \\
200 & 0.452 & 0.901 & 2.260 & 4.515 & 0.007 & 0.005 The results in Figures 8 and 9 demonstrate that, at a constant sampling frequency, both assembly and send times increase as the number of samples per packet grows. This outcome is expected because the microcontroller must accumulate the specified number of samples before it can execute the assembly and send processes. The more samples that need to be accumulated, the more time is required for these tasks. For example, at sampling frequencies of 100 Hz and 1750 Hz, the assembly times are 0.040 ms and 0.990 ms, respectively. Similarly, with the same number of samples per packet, the assembly and send times increase with increasing sampling frequency (except in the case of one sample per packet). This behavior is due to the operation of the scheduler, where the assembly and send tasks are interrupted at each sampling interval by the sensor reading tasks (see Figures 4 and 6). Although the additional time required for these tasks is not ideal, it enables the system to operate at higher sampling frequencies. For instance, when packets contain only one sample, the maximum achievable sampling frequency is limited to 500 Hz. In contrast, by including 26 samples in each packet, the system can reach sampling frequencies up to 1750 Hz. It is worth noting that in all the results in Tables 3 and 4 and Figures 8-10, the values and curves corresponding to the scenarios with one sensor sample in a packet closely resemble the results that would be obtained with a system with the same architecture, but without our scheduler and methodology. In such systems, only one sample per packet is a viable option. In Figure 10, we compare the mean time to perform all the tasks required to process (stream) a packet. This includes reading one, five, ten, or 26 sensor samples, assembling the samples into a packet, and sending the packet. The packet processing time increases with both the number of samples per packet and the sampling frequency, as shown previously in Figures 4 and 6, and decreases with the use of more efficient value representation--from decimal to hexadecimal, and further to hexadecimal with bit-shift, as illustrated in Table 2 and Figure 10.  
The relationships between assembly and send times in terms of the number of sensor samples per packet or the sampling frequency were already discussed in connection with Figures 4 and 6. Analysis of Table 2 and Figure 10 shows that the transition from decimal to hexadecimal value representation significantly increases the achievable sampling frequency. This improvement is due to the ability to include more samples per packet and reduce processing times for data formatting (compare the blue lines (D) with the red (H) and green lines (HS) in Figure 10). Further optimization of the formatting of 16-bit and 32-bit integers into hexadecimal ASCII representation results in an additional reduction in processing time (compare the red (H) and green lines (HS) in Figure 10). Figure 9: Mean packet sending times for varying numbers of samples per packet, using optimized hexadecimal representation with bit-shifting (HS). Legend label numbers denote the number of samples in one packet.