# An Energy-Efficient Convolutional Neural Network Processor Architecture Based on a Systolic Array
## 4 Hardware Implementation and Evaluation
### Hardware Verification  
This paper uses the Xilinx Zynq-7000 SoC ZC706 evaluation board kit for hardware verification, as shown in Figure 12, which contains a dual-core ARM Cortex(tm)-A9 (ARM, Cambridge, UK) processing system (PS) and an XCZ045 FPGA programmable logic (PL). The proposed CNN processor is implemented on the PL. The software code on the PS is responsible for controlling DMA and writing operation parameters to the instruction registers. We use Xilinx Vivado (AMD, Santa Clara, CA, USA) to synthesize and lay out the processor, as shown in Figure 13.  
The timing analysis result shows that the maximum clock frequency of the processor can reach 150 MHz on XCZ045 FPGA, as shown in Figure 14.  
Figure 12: ZC706 evaluation board.  
Figure 13: Layout of the proposed CNN processor.  
and addition in PEs are pipelined operations, each PE completes two operations in each clock cycle. The mac array contains 128 PUs and has 128 \(\times\) 3 = 384 PEs. When all PEs are involved in the computing, we can obtain the peak throughput as:  
\[2\times 384\times 150\ \text{MHz}=115.2\ \text{GOP/s} \tag{6}\]  
The resource utilization report is shown in Figure 15. It can be seen that this design uses 530 Block RAM, with a utilization rate of 97.25%, which is as expected. The DSP utilization rate reaches 50%. The utilization of LUTRAM (mainly used for distributed storage) and FF is relatively small, being about 20%.  
To estimate the power of the CNN processor, we used the Xilinx Power Estimator (XPE) (AMD, Santa Clara, CA, USA) which is a power evaluation tool provided by Xilinx. Taking the hardware utilization rate shown in Figure 15 as the evaluation indicator, the estimated on-chip power consumption is 3.801 W. We compared the performance with other CNN processors based on FPGA, as shown in Table 5, where the energy efficiency (GOP/s/W) represents the ratio of the throughput to power, and the DSP efficiency (GOP/s/DSP) represents the ratio of the throughput to DSP usage.  
Figure 14: Timing analysis report.  
Figure 15: Resource utilization report.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Reference** & [24] & [25] & [26] & [27] & [2] & **This Work** \\ \hline Platform & Zynq & Zynq & Zynq & Zynq & Arria 10 & Zynq \\  & ZC706 & ZC706 & ZC706 & XC7Z020 & GX1150 & ZC706 \\ Frequency (MHz) & 150 & 166 & 200 & 214 & 240 & 150 \\ Technology & 28 nm & 28 nm & 28 nm & 28 nm & 20 nm & 28 nm \\ Precision & 16 bits fixed & 16 bits fixed & 16 bits fixed & 8 bits fixed & 16 bits fixed & 16 bits fixed \\ Throughput (GOP/s) & 136.97 & 201.1 & 107.9 & 84.3 & 968.03 & 115.2 \\ Power (W) & 9.63 & 9.4 & 6.23 & 3.5 & 40 & 3.8 \\ Energy EFF (GOP/s/W) & 14.22 & 21.39 & 17.32 & 24.09 & 24.20 & 30.32 \\ DSP Used & 900 & 900 & 448 & 571 & 3136 & 449 \\ DSP EFF (GOP/s/DSP) & 0.15 & 0.23 & 0.24 & 0.15 & 0.30 & 0.26 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Performance comparison with state-of-the-art CNN processors.  
Thanks to computing based on a systolic array and multi-level memory that realizes the reuse of image and weight values, the proposed CNN processor achieves lower power and better energy efficiency than other designs. It also achieves a good DSP efficiency as a result of the reuse PEs in 2D convolution. In fact, the performance of the CNN processor still has much room for improvement. We find that the utilization of DSP is relatively low, which is caused by insufficient block RAM resources. If we optimize the storage structure or use a platform with more resources, the PE array can be expanded to increase the DSP utilization, so as to obtain a higher throughput.