# Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation
## 2 Interface Trap Charges in M3 DINV  
Figure 1 shows the M3 DINV structure and the locations of the interface trap charges that can be generated during its fabrication. The M3 DINV used in the simulation consists of N-type and P-type MOSFETs on the top and bottom layers, respectively [13; 14]. Doping concentration of the MOSFET's source/drain, lightly-doped doping (LDD), and the channel are \(10^{21}\), \(10^{18}\), and \(10^{15}\) cm\({}^{-3}\), respectively. The gate length and gate oxide thickness were simulated with a length of 30 nm and a thickness of 1 nm. SiO\({}_{2}\) was used for the gate oxide, ILD, and Box. The thicknesses of the ILD were 10 and 100 nm. In the TCAD simulation, the device simulator ATLAS [15] manufactured by Silvaco was used. The models used for device simulation were Lombardi CVT mobility, Shockley-Read-Hall Recombination, AUGER recombination, and Fermi-Dirac statistics. The extracted interface trap charge distribution was used for the simulation. Figure 1: Location of generated interface trap charges in the M3 DINV cell structure. In the magnified figure for the active region (**right figure**), x denotes the positions of interface trap charges. Here ML, MINV, and BOX mean metal line, metal inter-layer via, and buried oxide, respectively. Figure 2 shows the interface trap charge distributions generated in the top and bottom gate-oxide and silicon interfaces extracted in a previous study [13] and the drain current-gate voltage (\(I_{ds}\)-\(V_{gs}\)) characteristics. The inset graph of Figure 2a shows the interface trap charge distribution generated at the ILD and silicon interface [13]. Figure 2b shows \(I_{ds}\)-\(V_{gs}\) characteristics obtained by fitting the interface trap charge extracted from the reference results [13]. The distribution is extracted by fitting the energy level and charge density parameter of the interface trap charge by using the TCAD simulation results with the same structure as the reference results. The \(I_{ds}\)-\(V_{gs}\) characteristics (lines) of the top and bottom transistors using the extracted interface trap charge were verified by matching the experimental data (symbols). Using the interface trap charge distribution extracted from the experimental data, the \(I_{ds}\)-\(V_{gs}\) characteristics according to various biases of this device were obtained by TCAD simulation. Based on the \(I_{ds}\)-\(V_{gs}\) characteristics of TCAD simulation, the SPICE model parameters of the bottom P-type and top N-type MOSFETs for circuit design are extracted as shown in Tables 1 and 2 at \(T_{\text{ILD}}\) = 10 (and 100 nm), respectively. As the bottom layer P-type MOSFET is not affected by the thickness of the \(T_{\text{ILD}}\), the extracted parameter is the same for \(T_{\text{ILD}}\) of 10 and 100 nm. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameter** & **Unit** & **Description** & **Value** \\ \hline DLQ & m & Effective channel length offset CV & \(4\times 10^{-8}\) \\ VFBO & V & Geometry-independent flat-band voltage & 0.3 \\ CTO & - & Interface states factor & 0.4 \\ CICO & - & Geometry-independent part of substrate bias dependence factor & 2.2 \\ CFL & V\({}^{-1}\) & Length dependence of DIBL & 1.3 \\ UO & m\({}^{2}\)/V/s & Zero-field mobility & \(1.9\times 10^{-3}\) \\ MUEO & m/V & Mobility reduction coefficient & 4.3 \\ THEMUO & - & Mobility reduction exponent & 1 \\ FETAO & - & Effective field parameter & 3 \\ PSECL & - & Length dependence of short channel effect above threshold & 0.15 \\ THESATO & V\({}^{-1}\) & Geometry-independent velocity saturation parameter & 3 \\ AXO & - & Geometry-independent of linear/saturation transition factor & 0 \\ ALPL1 & - & Length dependence of CLM pre-factor ALP & 0.0005 \\ VPO & V & CLM logarithm dependence factor & 0.04 \\ CGBOVL & F & Oxide capacitance for gate-substrate overlap & \(9\times 10^{-16}\) \\ CFRW & F & Outer fringe capacitance & \(2.8\times 10^{-16}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Summary of extracted LETI-UTSOI model parameters for the bottom P-type MOSFET.