## 2 Design of the Proposed DPA
### Design of the DPA Load Network  
The dynamic power dividing network also affects the load design methodology due to its advantages in maintaining good AM-AM characteristics. Since there is more margin lowering the peaking amplifier bias with dynamic power dividing applier, it is more beneficial when the DPA load network is designed to have a wide OBO range. In this paper, the OBO extension method is applied to the DPA load network design since the dynamic power divider can relieve the burden on linearity when the peaking amplifier is required to have a deeper operation class for extended high-efficiency range.  
Figure 5 presents the schematic and simulated results of the load network used in this design. The impedances at the power combining node are controlled to achieve the desired OBO extension. Figure 5b shows the impedance values at the center frequency for \(Z^{\prime}_{C,low}\), \(Z^{\prime}_{C,peak}\), and \(Z^{\prime}_{P,peak}\). Based on the design method through multiple backoff parameters presented in [10], the virtual stub (VS) parameter \(\theta_{k}\) is 16.8\({}^{\circ}\), and the outphased current combining (OCC) parameter \(\Delta\theta\) is 56.5\({}^{\circ}\). This set of backoff parameters will result in modulating the carrier load impedance 2.51 times higher for an OBO range of 7.02 dB. The load network is initially based on lumped components to match the required impedances, then are converted into transformer-based networks as shown in Figure 6.  
Figure 5: The proposed DPA load network: (a) Lumped model equivalent circuit; (b) Simulated impedances at the power combining node for 24–32 GHz.  
Figure 6: Practical implementation of the DPA load network: (a) Transformer equivalent circuit conversion; (b) Simulated impedances at the transistor current source planes for 24–32 GHz.  
The schematic of the load network in Figure 6 is designed by adding additional shunt inductors and tuning shunt capacitor values to form a pi-type transformer equivalent circuit. The load network can, therefore, be implemented simply only with transformers and additional capacitors. Figure 6b shows the simulated results of the load impedances presented at the current source plane of the carrier and peaking amplifiers with the proposed DPA load network. The simulated values are well matched to the optimum load impedance of 70 \(\Omega\) at peak power and 175 \(\Omega\) at low power. The load modulation ratio result of 2.5 also agrees well with the original intention described in Figure 5.  
Figure 7a presents the full schematic of the proposed DPA with the dynamic power dividing network. Unit transistor size with a gate length of 30 nm and unit gate width of 1 \(\times\) 20 \(\upmu\)m was selected, and a total of 6-unit transistors were used for one half of a differential cell. The differential cell was used identically for the drive and main stages to minimize the source degeneration effect and was supplied with a drain voltage of 1 V and a quiescent current of 10 mA. Cross-coupled capacitors were applied to neutralize the gate-to-drain capacitance at the fundamental frequency for higher gain and stability. The second harmonic impedance termination is realized using a resonance by adding a shunt inductor at the virtual ground made by shunt capacitors across the differential port.  
Figure 7: Full schematics of the DPAs with the following: (**a**) The proposed dynamic power dividing network; (**b**) A conventional dual-driven DPA using a hybrid coupler.  
When compared to the conventional DPA that has dual-drive amplifiers for the carrier and peaking amplifiers, as shown in Figure 7b, the proposed DPA has two fewer transformers using a single drive amplifier. In addition, compared to the conventional case, which has an isolated power divider, the proposed DPA can have a smaller size since the dynamic power dividing network has a simplified structure including the phase offset line and impedance matching networks.