# DRAM Retention Behavior with Accelerated Aging in Commercial Chips
## 4 Experimental Results and Analysis
### Aging Effects on Retention Error
#### 4.3.1 Increase in Retention Error with Aging  
The number of total erroneous cells (retention errors) for all three different retention times (\(t_{\text{ref}}=10\) s, 20 s, 50 s) increases drastically as the devices age (Table 1). We observe about a 5-10% increase in retention error after 8 h of aging and about 15-30% after 16 h  
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Vendor**} & \multirow{2}{*}{**Chip Number**} & \multirow{2}{*}{**Retention Time (\(t_{\text{ref}}\))**} & \multirow{2}{*}{**Pattern**} & \multicolumn{2}{c}{**No. of Errors**} & \multicolumn{2}{c}{**No. of Errors**} & \multicolumn{2}{c}{**No. of Errors**} & \multicolumn{2}{c}{**\% Change Errors**} \\  & & & & **(\(t_{\text{0}}=\text{0}\) h)** & **(\(t_{\text{1}}=\text{8}\) h)** & **(\(t_{\text{2}}=\text{16}\) h)** & **(\(t_{\text{2}}=\text{16}\) h)** & **(\(t_{\text{2}}=\text{16}\) h)** \\ \hline \multirow{4}{*}{Micron} & \multirow{4}{*}{MT8} & \multirow{4}{*}{10 s} & 0x00 & 802 & 898 & 11.97\% & 953 & 18.83\% \\ \cline{3-8}  & & & 0 xFF & 978 & 1040 & 6.34\% & 1144 & 16.97\% \\ \cline{3-8}  & & & 0x00 & 11,130 & 12,076 & 8.50\% & 13,029 & 17.06\% \\ \cline{3-8}  & & & 0 xFF & 12,306 & 12,759 & 3.68\% & 14,240 & 15.72\% \\ \cline{3-8}  & & & 0x00 & 202,659 & 222,322 & 9.70\% & 232,886 & 14.92\% \\ \cline{3-8}  & & & 0 xFF & 222,006 & 226,026 & 1.81\% & 243,442 & 9.66\% \\ \hline \multirow{4}{*}{Hynix} & \multirow{4}{*}{HMT3256 BF8C-H9} & \multirow{4}{*}{20 s} & 0x00 & 531 & 587 & 10.55\% & 743 & 39.92\% \\ \cline{3-8}  & & & 0 xFF & 557 & 610 & 9.52\% & 649 & 16.52\% \\ \cline{3-8}  & & & 0x00 & 12,234 & 14,279 & 16.72\% & 16,275 & 33.03\% \\ \cline{3-8}  & & & 0 xFF & 12,488 & 13,541 & 8.43\% & 16,075 & 28.72\% \\ \cline{3-8}  & & & 0x00 & 338,707 & 404,833 & 19.52\% & 455,105 & 34.37\% \\ \cline{3-8}  & & & 0 xFF & 364,282 & 391,104 & 7.36\% & 458,367 & 25.83\% \\ \hline \multirow{4}{*}{Samsung} & \multirow{4}{*}{M471B5773 DH0-CH9} & \multirow{4}{*}{10 s} & 0x00 & 87 & 86 & \(-\)1.15\% & 88 & 1.15\% \\ \cline{3-8}  & & & 0 xFF & 11,759 & 10,052 & \(-\)14.52\% & 10,085 & \(-\)14.24\% \\ \cline{1-1} \cline{2-8}  & & & 0x00 & 232 & 230 & \(-\)0.86\% & 234 & 0.86\% \\ \cline{1-1} \cline{2-8}  & & & 0 xFF & 209,714 & 178,239 & \(-\)15.01\% & 188,041 & \(-\)10.33\% \\ \cline{1-1} \cline{2-8}  & & & 0 xFF & 653 & 648 & \(-\)0.77\% & 648 & \(-\)0.77\% \\ \cline{1-1} \cline{2-8}  & & & 0 xFF & 5,953,567 & 5,228,952 & \(-\)12.17\% & 5,455,663 & \(-\)8.36\% \\ \hline \hline \end{tabular}
\end{table}
Table 1: Summary of retention error for sample DRAM modules.  
of aging for Micron and Hynix DDR3 modules. When deployed in the field for several months or years, the change in retention error will be significant enough to distinguish an aged module from a new one. In the case of the Samsung modules, we observe a deviation of aging behavior as very few errors are induced for data pattern 0x00 because of design variation. The errors induced for data pattern 0 xFF are clustered in a few rows and decrease with aging. In this case, the design-induced variations dominate over aging impacts.  
Moreover, for our chosen data patterns, we observe that the 0x00 pattern induces a slightly higher retention error than the 0 xFF pattern, as shown in Table 1. Even though there are some variations in retention error due to input patterns, they are in the same range, which illustrates that the number of true cells and anti-cells is almost equal in Micron and Hynix manufactured DRAM chips. On the other hand, the Samsung modules do not show any error for the input pattern 0x00, which indicates that the Samsung chips do not have the architecture of true cells and anti-cells; instead, all the cells are designed following the same true-cell architecture.