## 4 Results and Discussions
The crystallographic Silicon (Si) channel orientation is \(<\)110\(>\). Each NWT has cross-sectional area \(\approx\)10\(\pi\) nm\({}^{2}\). The gate length = 12 nm. In Figure 6, it is clear that \(\tau\) constitutes a function of L\({}_{\rm G}\). In particular, \(\tau\) is correlated in a direct way to the device's speed, where the NWTs' speed with respect to \(\tau\) can be expressed as follows:  
\[\tau=C_{\rm G}(V_{\rm DD}/I_{\rm off}) \tag{2}\]  
Figure 5: The effect of 9 cross-section aspect ratios for Si NWTs on the I\({}_{\rm D}\)-V\({}_{\rm G}\) curves. Dotted lines represent a low drain voltage (namely, V\({}_{\rm D}\) = 0.05 V), whereas continuous lines represent a high drain voltage (namely, V\({}_{\rm D}\) = 0.7 V). \(<\)110\(>\) is the channel orientation for Si, while the gate length amounts to 12 nm. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Z (nm) \(\times\) Y (nm)** & **Q\({}_{\rm M}\) (\(\times\)10\({}^{7}\)/cm)** & **C\({}_{\rm G}\) (10\({}^{-10}\) F/cm)** & **Q\({}_{\rm M}\)/C\({}_{\rm G}\) (10\({}^{17}\)/F)** \\ \hline \multicolumn{5}{c}{\(<\)110\(>\)} \\ \hline
4.44 \(\times\) 9.0 & 2.73300 & 1.14010 & 2.3970 & \\
5 \(\times\) **8.10 (Phi)** & 2.84200 & 1.14740 & **2.4760** & \\
5.7 \(\times\) 7.0 & 2.75000 & 1.12900 & 2.4350 & \\
6.0 \(\times\) 6.66 & 2.58010 & 1.10930 & 2.3260 & \\ \hline
6.320 \(\times\) 6.320 & 2.54800 & 1.10920 & 2.2970 & Circular \\ \hline
6.660 \(\times\) 6.0 & 2.63160 & 1.11680 & 2.3560 & \\
7.0 \(\times\) 5.70 & 2.77380 & 1.13520 & 2.4400 & \\
**8.10 \(\times\) 5 (1/Phi)** & 2.89200 & 1.16020 & **2.4910** & Prolate NWT \\
9.0 \(\times\) 4.44 & 2.72700 & 1.13710 & 2.3980 & \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Quantum charge to the gate capacitance ratio at identical Q\({}_{\rm M}\) at zero gate bias (for NWTs with crystallographic Silicon channel orientation \(<\)110\(>\). \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Z (nm) \(\times\) Y (nm)** & **Q\({}_{\rm M}\) (\(\times\)10\({}^{7}\)/cm)** & **C\({}_{\rm G}\) (10\({}^{-10}\) F/cm)** & **Q\({}_{\rm M}\)/C\({}_{\rm G}\) (10\({}^{17}\)/F)** \\ \hline \multicolumn{5}{c}{\(<\)100\(>\)} \\ \hline
4.44 \(\times\) 90 & 2.73220 & 1.13500 & 2.40720 & \\
5 \(\times\) **8.10 (Phi)** & 2.89000 & 1.15970 & **2.49200** & \\
5.7 \(\times\) 7.0 & 2.77940 & 1.13840 & 2.44410 & Oblate NWT \\
6.0 \(\times\) 6.66 & 2.64030 & 1.11840 & 2.36070 & \\ \hline
6.320 \(\times\) 6.320 & 2.61020 & 1.11600 & 2.33760 & Circular \\ \hline
6.660 \(\times\) 6.0 & 2.64020 & 1.11800 & 2.36150 & \\
7.0 \(\times\) 5.70 & 2.77930 & 1.13800 & 2.44220 & \\
**8.10 \(\times\) 5 (1/Phi)** & 2.89100 & 1.15980 & **2.49100** & Prolate NWT \\
9.0 \(\times\) 4.44 & 2.73210 & 1.13410 & 2.40900 & \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Quantum charge to the gate capacitance ratio at identical Q\({}_{\rm M}\) at zero gate bias (for NWTs with crystallographic Silicon channel orientation \(<\)100\(>\). where \(\rm C_{G}\) represents the total gate capacitance; \(\rm I_{off}=(I_{H}+I_{L})/2\) represents the effective current, where \(\rm I_{H}=I_{D}\) (\(\rm V_{G}=V_{DD}\), \(\rm V_{D}=V_{DD}/2\)), and \(\rm I_{L}=I_{D}\) (\(\rm V_{G}=V_{DD}/2\), \(\rm V_{D}=V_{DD}\)). \(\rm V_{DD}=0.6\) V, and the leakage current is \(\rm I_{off}=0.6~{}\rm\mu A/\rm\mu m\). Figure 6 illustrates that NTWs with 8.10 nm \(\times\) 5 nm and 5 nm \(\times\) 8.10 nm are associated with the lowest value of \(\tau\), and the evaluation of \(\tau\) is consistent with the \(\rm Q_{M}/C_{G}\) results (see Table 2). A much more systematic design of experiments would identify how NWTs' FOMs interact with other variables that are correlated to AR. Figure 7 shows a possible design of such experiments, including the effect of gate lengths and oxide thickness, and NWT cross-sectional dimensions on \(\rm I_{off}\), \(\rm I_{on}\) and sub-threshold slope (SS).