# A 7.5-9 GHz GaAs Two-Channel Multi-Function Chip
## 2 Circuit Design
### Phase Shifter Design  
The schematic of the 6-bit phase shifter is illustrated in Figure 4. The 6-bit phase shifter provides 64 states in steps of 5.625\({}^{\circ}\), which corresponds to phase shifts of 45\({}^{\circ}\), 5.625\({}^{\circ}\), 11.25\({}^{\circ}\), 22.5\({}^{\circ}\), 90\({}^{\circ}\), and 180\({}^{\circ}\). The major consideration for the order of the 6-bit phase shifter is the input and output characteristic. Each FET's on-state (0 V) and off-state (\(-\)3 V) is controlled by the gate bias voltage, which also is provided by the serial-to-parallel converter.  
Series FETs filter topology is applied in 5.625\({}^{\circ}\) bit, which causes low insertion loss. The bridge-T-type topology is selected for the 11.25\({}^{\circ}\) and 22.5\({}^{\circ}\) bits. The FETs' parasitic parameters are absorbed as phase shift element, and the topology has a good phase shift flatness. For the 45\({}^{\circ}\), 90\({}^{\circ}\), and 180\({}^{\circ}\) bits, switched filter topology is implemented. Between two SPDT switches, one path is constructed using a high-pass filter network which causes signal phase lead, and the other path is constructed using a low-pass filter network which makes signal phase lag. The necessary phase shift is obtained by switching the signal between the two paths. Although the use of two SPDT switches introduces higher insertion loss compared to other bits, the implementation of high phase shift values using this topology provides a low amplitude imbalance, good match characteristics, and phase shifter flatness.  
The parameters of phase shifter design are shown in Table 3.  
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Unit Cell**} & \multicolumn{6}{c}{**Parameter**} \\ \cline{2-9}  & **FET1 (\(\mu\)m)** & **FET2 (\(\mu\)m)** & **FET3 (\(\mu\)m)** & **FET4 (\(\mu\)m)** & **_R1 (\(\mathrm{\SIUnitSymbolMicro}\)_) & **_R2 (\(\mathrm{\SIUnitSymbolMicro}\)_) \\ \hline
0.5 dB & 2 \(\times\) 50 & 2 \(\times\) 50 & - & - & 595 & - \\
1 dB & 2 \(\times\) 50 & 2 \(\times\) 50 & - & - & 204 & - \\
2 dB & 4 \(\times\) 80 & 4 \(\times\) 45 & - & - & 192 & 7 \\
4 dB & 6 \(\times\) 50 & 2 \(\times\) 25 & - & - & 43.5 & 11.5 \\
8 dB & 6 \(\times\) 50 & 4 \(\times\) 25 & 4 \(\times\) 45 & 4 \(\times\) 25 & 76 & 15 \\
16 dB & 6 \(\times\) 45 & 2 \(\times\) 50 & 4 \(\times\) 50 & 4 \(\times\) 50 & 38 & 16 \\ \hline \hline \end{tabular}
\end{table}
Table 2: The parameters of attenuator design.  
Figure 4: The schematic of the 6-bit digital phase shifter.  
\begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline \multirow{2}{*}{
\begin{tabular}{c} **Unit** \\ **Cell** \\ \end{tabular} } & \multicolumn{6}{c}{**Parameter**} \\ \cline{2-10}  & **FET1 (\(\mu\)m)** & **FET2 (\(\mu\)m)** & **FET3 (\(\mu\)m)** & **FET4 (\(\mu\)m)** & **_R1 (\(\mathrm{\SIUnitSymbolMicro}\)_) & **_R2 (\(\mathrm{\SIUnitSymbolMicro}\)_)** \\ \hline
0.5 dB & 2 \(\times\) 50 & 2 \(\times\) 50 & - & - & 595 & - \\
1 dB & 2 \(\times\) 50 & 2 \(\times\) 50 & - & - & 204 & - \\
2 dB & 4 \(\times\) 80 & 4 \(\times\) 45 & - & - & 192 & 7 \\
4 dB & 6 \(\times\) 50 & 2 \(\times\) 25 & - & - & 43.5 & 11.5 \\
8 dB & 6 \(\times\) 50 & 4 \(\times\) 25 & 4 \(\times\) 45 & 4 \(\times\) 25 & 76 & 15 \\
16 dB & 6 \(\times\) 45 & 2 \(\times\) 50 & 4 \(\times\) 50 & 4 \(\times\) 50 & 38 & 16 \\ \hline \hline \end{tabular}
\end{table}
Table 2: The parameters of attenuator design.