# Total Ionizing Dose Effects in Advanced 28 nm Charge Trapping 3D NAND Flash Memory
## 3 Results and Discussions  
This section delineates the impact of radiation on NAND Flash memory performance, focusing on the raw bit error rate (RBER). The raw bit error rate refers to the bit error rate of flash memory without error correction code. In this work, we read data from the irradiated chip byte by byte and compared the collected data with the original data pattern to calculate the raw bit error rate. The following formula is used to compute the RBER:  
\[\text{RBER}=\frac{\text{Total bit error counts in a page}}{\text{Total number of bits in the page}}\times 100\% \tag{1}\]  
A. Raw Bit Error Rate  
The RBER was assessed following TID irradiation, examining memory function under various operating modes, bias states, and data patterns. Figure 2 illustrates the correlation between the RBER and dose under different operating modes and bias states. The analysis reveals that TLC mode exhibits a higher sensitivity to total dose effects. Initially, no bit errors were detected in TLC mode at a dose of 0 krad (Si). However, at a total dose of 10 krad (Si), bit errors began to manifest, with the rate of errors accelerating as the dose increased. In contrast, SLC mode demonstrated minimal bit errors, which remained significantly lower than those in TLC mode, even as the dose escalated. Compared with SLC mode, TLC mode has a greater threshold voltage distribution due to the extra programming state, which lead to the noise margin correctly identifying the cell states being smaller than in SLC mode. When the TID effect causes the programming state's threshold voltage to shift, the flash operating in TLC mode will have more errors, resulting in an increase in the RBER. The effect of radiation on memory also varies with bias states. Figure 3 displays the RBER-dose relationship under different bias states in both TLC and SLC modes. A comparison of the magnitudes in Figure 3a,b underscores the greater susceptibility of TLC mode to TID, aligning with the observations in Figure 2. Figure 3 illustrates that, irrespective of the operating mode, memory under the read-only state is most vulnerable to TID effects. Conversely, the erase-program-read cycle state exhibits the strongest resistance to TID effects. Compared with the static state, since the data of memory in the dynamic erase-program-read state are constantly updated, the corresponding RBER always displays initial error counts and has the lowest number of errors. However, the dynamic erase-program-read state will apply the maximum voltage in all of three bias states to the high voltage charge pump, and the combined action of repeated program/erase cycles and TID effect will lead to a lot of defects in the oxide layer. This means that the dynamic erase-program-read state has the lowest TID tolerance and fails when the radiation dose exceeds 30 krad. The read-only bias state also repeatedly applies a voltage to the gate, and the charge is more likely to leak out of the charge trap layer compared to the static state. So, the memory in the read-only bias state has the highest RBER. Further examination was conducted on the TID effects across three different data patterns (patterns = 00, AA, and FF). Figure 4 illustrates the bit error count for four scenarios. The radiation tolerance of Flash memory is influenced by the stored data pattern, with the 00 pattern being the most vulnerable to radiation and the FF pattern exhibiting almost no susceptibility to TID. Comparative analysis with similar memory technologies revealed that 3D NAND's performance, as reported in [20], indicates an RBER of approximately 0.1 in Multi-Level Cell (MLC) mode under read-only operation at a radiation dose of 40 krad (Si). In contrast, the RBER in SLC mode at the same radiation dose is 1e-5. Our findings demonstrate that at a radiation dose of 40 krad (Si), the RBER in TLC mode is \(1\times 10^{-2}\), and in SLC mode, it is \(2\times 10^{-6}\), with both figures presenting an improvement over the results in [20].