# Grating-Assisted Fiber to Chip Coupling for SOI Photonic Circuits
## 8 Packaging and Testing  
For silicon based PICs, the route from proof of concept design to a commercially viable prototype is incomplete without a robust packaging platform. Most developments in silicon photonics is centered around research and development, although emphasis on packaging and assembly is steadily gaining importance. If the full potential of silicon photonics is to be realized, it is essential to incorporate durable, low cost and high volume packaging solutions. Compared to electronic prototypes, packaging photonic chips demands much higher alignment accuracies, thermal management and integration of a host of complex active and passive optical elements [61]. As elaborated before, the main challenge associated with packaging of PICs is the large size mismatch between the fiber core and a single mode SOI waveguide. Typically both edge coupling and grating based packaging solutions have been available with the former already emerging as an industry standard for III-V device integration. Packaging of edge coupling schemes can be accomplished through fiber pigtailing at the input and out waveguide facets through laser welding of lensed fibers mounted on a metallic ferrule. However, owing to tight alignment requirements (0.5 \(\upmu\)m 1 dB power penalty) and complex post processing steps of polishing, cleaving and dicing, edge coupler packages are only being offered with single fiber mounts. Edge coupling is primarily preferred by research groups working on high power, broadband applications such as nonlinear signal processing. Having said that, recently a new in-plane technique based on evanescent coupling has been demonstrated by IBM Zurich in which optical mode from SOI PIC initially couples evanescently to a second chip with a polymer waveguide before being transmitted to the output fiber port [62]. This scheme promises edge-coupler like performance with much more relaxed alignment and processing requirements. Consequently, most fiber-chip packaging services for SOI platform are offered via grating couplers. Grating couplers have much a better alignment tolerance amounting to \(\pm\)2.5 \(\upmu\)m 1 dB power penalty and a CMOS compatible planar processing that is suitable for high volume manufacturing and wafer-scale testing. Commercial packaging service ePIXpack offers multiport fiber array connector of up to 32 ports [63; 64; 65]. The fibers are mounted vertically on a v-groove bottom with a glass lid that is polished at near normal coupling angle to the SOI chip, along with a glob-top encapsulation (see Figure 18a). Post packaging, fiber to grating coupling efficiencies of up to 30% has been reported in this technique. Vertical based mount packaging can be fragile and faces mechanical stability issues. To address this, a new kind of quasi-planar packaging approach using angle-polished fibers has recently emerged [66; 67; 68]. In this approach, propagating light in fiber core undergoes total internal reflection (TIR) at the core cladding interface at the polished fiber facet leading to near-normal incidence at the grating on SOI chip placed in the base. This packaging scheme has been demonstrated to yield a peak fiber to chip coupling efficiency of up to -4.5 dB [67]. Angle polished fiber packaging service is currently offered by ePIXfab (see Figure 18b). The design incorporates use of input and output shunt waveguides which need only a single active alignment for a fiber array. Broadly speaking, packaging can be done using both an active and passive alignment process [69]. In active alignment scheme, coupling from fiber to chip is constantly monitored as a function of fiber freespace position with the help of a source and a detector for precise alignment. However, this considerably increases cost and cycle time and presents a significant impediment to adapting for mass manufacturing. Conversely, vision based passive alignment packaging can be implemented where the fiber core and grating images are aligned before being bought into contact.