# Design of Low-Power ECG Sampling and Compression Circuit
## 5 Conclusions  
This paper proposes a novel ECG sampling and compression circuit to solve the problems of a large area and high power consumption. The 12-bit SAR ADC is customized and integrated into the sampling and compression circuit according to the data processing requirements. The capacitor array uses the top plate sampling scheme and bridge capacitors to reduce the area and power consumption, and the comparator applies a calibration technique to minimize the offset voltage to 0.29 mV. On the premise of ensuring the reconstruction quality, the CS module completes the matrix calculation, and pulsed latches store the results. The addition calculation approximates the addend, and accurate calculation and approximate calculation are carried out for the high and low parts of the \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**Source**} & **Tech** & **Supply** & **ADC** & **ENOB** & **Frequency** & **Area** & **Power** & **FOM** \\  & **(nm)** & **(V)** & **(bit)** & **(bit)** & **(kHz)** & **(mm2)** & **(\(\mu\)W)** & **(\(\mu\)W)** & **(f)\({}^{\star}\)mm\({}^{2}\)/conv** \\ \hline \multirow{2}{*}{[PERSON] [10]} & \multirow{2}{*}{90} & \multirow{2}{*}{core 0.6} & \multirow{2}{*}{8} & \multirow{2}{*}{/} & \multirow{2}{*}{20} & \multirow{2}{*}{(CS module)} & \multirow{2}{*}{(CS module)} & \multirow{2}{*}{/} \\  & & & & & & & 0.128 & 2.4 \\ \multirow{2}{*}{[PERSON] [11]} & \multirow{2}{*}{65} & \multirow{2}{*}{core 0.65} & \multirow{2}{*}{8} & \multirow{2}{*}{/} & \multirow{2}{*}{100} & \multirow{2}{*}{(CS module)} & \multirow{2}{*}{(CS module)} & \multirow{2}{*}{/} \\ \multirow{2}{*}{[PERSON] [12]} & \multirow{2}{*}{180} & \multirow{2}{*}{core 1.8} & \multirow{2}{*}{11} & \multirow{2}{*}{8.99} & \multirow{2}{*}{100} & \multirow{2}{*}{8.51} & \multirow{2}{*}{10.08} & \multirow{2}{*}{157.511} \\  & & & & & & & & \\ \multirow{2}{*}{[PERSON] [13]} & \multirow{2}{*}{180} & \multirow{2}{*}{core 1.8} & \multirow{2}{*}{10} & \multirow{2}{*}{9.3} & \multirow{2}{*}{4000} & \multirow{2}{*}{3} & \multirow{2}{*}{155} & \multirow{2}{*}{17.218} \\  & & & & & & & & \\ \multirow{2}{*}{Our work} & \multirow{2}{*}{55} & \multirow{2}{*}{12} & \multirow{2}{*}{11.1} & \multirow{2}{*}{100} & \multirow{2}{*}{0.325} & \multirow{2}{*}{2.951} & \multirow{2}{*}{4.369} \\ \hline \hline \end{tabular}
\end{table} 
Table 4: The comparisons among different sampling and compression circuits. Figure 13: The reconstruction results of the compressed data. ECG signal, respectively. The sampling and compression circuit realizes the functions of analog-to-digital conversion, matrix generator, compression and storage, and SPI output. In a 55 nm CMOS process, the ADC area is 0.011 mm\({}^{2}\), and the power consumption is 0.214 \(\upmu\)W. The developed solution optimizes the CS module and reduces its area and power consumption by 19.5% and 31.7%, respectively. When the supply is 1.2 V and the frequency is 100 kHz, the area and power consumption of the sampling and compression circuit are 0.325 mm\({}^{2}\) and 2.951 \(\upmu\)W, respectively, presenting apparent advantages. The ECG signal reconstruction is completed based on the BSBL algorithm, with the measured PRD of the reconstructed data being less than 2%. Therefore, the proposed sampling and compression circuit has the advantages of low power consumption and high reconstruction performance, which can be used in medical monitoring and diagnosis. Conceptualization, Z.Z. and Z.Y. ; methodology, Z.Z. and Y.N. ; software, Z.Z. and X.C. ; validation, Y.N. and X.C. ; formal analysis, Y.N., X.X. and X.C. ; investigation, Z.Z., Y.N. and X.X. ; resources, Z.Y. and X.G. ; data curation, Z.Z. and X.X. ; writing--original draft preparation, Z.Z. and Z.Y. ; writing--review and editing, Z.Z. and Z.Y. ; visualization, Z.Z. and Z.Y. ; supervision, Z.Y. and X.G. ; project administration, Z.Y. and X.G. ; funding acquisition, Z.Y. and X.G. All authors have read and agreed to the published version of the manuscript.