## 2 Proposed Circuit
### The Multiple-Input DDCCTA
The voltage at the x-terminal, neglecting the impact of the common-mode rejection ratio (CMRR) limitation of the internal amplifier, can be expressed as  
\[V_{x}=K_{v}\big{(}V_{y+1}+V_{y+2}-V_{y-1}-V_{y-2}\big{)} \tag{2}\]  
The voltage gain \(K_{v}\) by assuming identical capacitances C\({}_{\text{C1}}\) can be expressed as  
\[K_{v}=\frac{\Big{(}\frac{g_{\text{m}1,2}}{3}\Big{)}\Big{(}\frac{r_{\text{d}2} r_{\text{d}5}}{r_{\text{d}2}+r_{\text{d}5}}\Big{)}(g_{\text{m}6}+g_{\text{m}9})(r_{ \text{d}6}+r_{\text{d}9})}{1+\Big{(}\frac{g_{\text{m}1,2}}{3}\Big{)}\Big{(} \frac{r_{\text{d}6}r_{\text{d}8}}{r_{\text{d}2}+r_{\text{d}5}}\Big{)}(g_{\text{ m}6}+g_{\text{m}9})(r_{\text{d}6}+r_{\text{d}9})} \tag{3}\]  
The transconductance of the transistors M\({}_{1}\) and M\({}_{2}\) expressed by (3) is divided by 3 due to the input capacitive divider. However, due to the two-stage structure of the internal op-amp, the value of \(K_{v}\) can be close to unity, with its gain error typically less than 1%. The resistance at the x-terminal can be expressed by  
\[r_{x}=\frac{1}{\Big{(}\frac{g_{\text{m}1,2}}{3}\Big{)}\Big{(}\frac{r_{\text{d} 2}r_{\text{d}5}}{r_{\text{d}2}+r_{\text{d}5}}\Big{)}(g_{\text{m}6}+g_{\text{m}9 })} \tag{4}\]  
Because the gates of the transistors M\({}_{7}\), M\({}_{8}\), M\({}_{9}\) (M\({}_{12}\), M\({}_{13}\), M\({}_{14}\)) are controlled with a voltage identical to the voltage at the gate of M\({}_{6}\) (M\({}_{9}\)), the currents at the \(z_{-}\) and \(z_{+}\)-terminal by neglecting second-order effects are equal to the current at the x-terminal. The minus-type output (\(z_{-}\)-terminal) of the DDCC can be obtained using the cross-coupled current mirrors\(\text{M}_{9}\), \(\text{M}_{10}\), \(\text{M}_{11}\) and \(\text{M}_{13}\), \(\text{M}_{14}\), \(\text{M}_{16}\). Thus, the current \(I_{x}\) can be conveyed to the terminals \(z\), \(z_{+}\), and \(z_{-}\). The output resistances at the \(z\)-, \(z_{+}\)-, \(z_{-}\)-terminals are expressed, respectively, by  
\[ \begin{array}{l}r_{z}=\frac{r_{d}r^{2}+r_{d12}}{r_{d}s^{2}r_{d12}}\\ r_{z+}=\frac{r_{d12}+r_{d12}}{r_{d}s^{2}r_{d13}}\\ r_{z-}=\frac{r_{d11}+r_{d16}}{r_{d11}r_{d16}}\end{array}  \tag{5}\]  
The multiple-output \(z_{+}\), and \(z_{-}\) terminals can be obtained using multiple-output current mirrors. The second building block of the proposed DDCCTA is the transconductance amplifier (TA). The circuit consists of a differential amplifier and current mirrors. The input differential stage of TA is realized using a linearized MOS differential transconductance amplifier operating in strong inversion, which was proposed in [51]. In this work, the same technique is modified to the input differential amplifier operating in weak inversion. This technique can improve the linearity of input differential pairs. The transistors \(\text{M}_{3}\) and \(\text{M}_{4}\) work as source degeneration resistors since they operate in a triode region with \(V_{DS}=0\) at the operating point. It should be noted that the gates of \(\text{M}_{3}\) and \(\text{M}_{4}\) are connected to the input terminals, thus this source degeneration resistor can operate as a voltage-controlled resistor to linearize the TA transconductance for a wider range of input voltages. If the current mirrors around the input differential amplifier TA are identical and have unity current gain, the transconductance of TA can be expressed as follows  
\[g_{m}=\frac{4k}{4k+1}.\frac{I_{SET}}{n_{p}U_{T}} \tag{6}\]  
where \(n_{p}\) is the subthreshold slope factor for a p-channel transistor, \(U_{T}\) is the thermal potential (\(\approx\)25 mV at 27 \({}^{\circ}\)C), \(I_{SET}\) is the biasing current, and \(k\) is the ratio of the aspect ratios of \(\text{M}_{3,4}\) to \(\text{M}_{1,2}\) given by  
\[k=\frac{\left(W/L\right)_{3,4}}{\left(W/L\right)_{1,2}} \tag{7}\]  
The coefficient \(k\) will affect the circuit linearity, and the optimum linearity can be achieved for \(k=0.5\)[52].