# A Review of Sharp-Switching Band-Modulation Devices
## Operating Principles and Models
### Regions of Operation  
Five regions, indicated by capital letters in Figure 9, can be identified in \(Z^{2}\)-FET steady-state operation (Figure 9):  
Figure 8: Output characteristics of a \(Z^{2}\)–FET for variable voltage applied to the ground plane. \(\mathrm{V_{FG}}=1.5\) V, other parameters as in Figure 4 (adapted from [27]).  
_Point O: 'Initialization'_: The front gate and back gate are biased to produce the NPNP electrostatic structure, by transforming the PIN diode into a virtual thyristor (Figure 10a). The potential profiles are governed by the two MOS capacitors, respectively formed by (i) the gate and the overlapped body, and (ii) the back gate, the BOX, and the underlapped body (see Figure 11a).  
Figure 10: Electrostatic potential profiles from cathode (source) to anode (drain) during each DC operating regime: (**a**) initialization, (**b**) IOFF region, (**c**) barrier collapse, and (**d**) negative differential resistance. TCAD simulations adapted from [29].  
Figure 9: S-shaped output characteristic I\({}_{\rm A}\)–V\({}_{\rm A}\) computed with [PERSON]’s physical model [28] and [PERSON]’s compact model [29]. The capitals separate the five regimes in steady-state operation.  
_From O to A: 'OFF region'_: The device is in the I\({}_{\text{OFF}}\) state. The voltage drop on the anode and cathode junctions is negligible. Increasing V\({}_{\text{A}}\) results in stronger reverse-biasing of the center junction, where the GR current is very low. As the _effective_ gate bias (V\({}_{\text{FG}}\)-V\({}_{\text{A}}\)) decreases, the \(N^{*}\) electron concentration tends to fall. The drain voltage increase produces a potential rise in the gated region (Figure 10b). The \(Z^{2}\)-FET current is simply the leakage current of the unbiased P-N junctions.  
_From A to B: 'Barrier collapse'_: As soon as the reverse bias on the central junction reaches a maximum, the anode and cathode junctions become forward biased. Injected holes flow towards the cathode and recombine with the electrons from the cathode. The hole diffusion current dominates, which is reflected by the slope \(\Delta\text{V}_{\text{A}}/\Delta\text{I}_{\text{A}}\approx 60\) mV/decade. The holes gradually accumulate in the gated region, and the electrons in the ungated region. The potential in the gated region reaches the maximum. The increase in anode voltage makes the potential in the ungated region less negative, leading to a lowering of the potential barrier between the gated and ungated regions. The central junction is less and less reverse-biased, until it eventually turns on at point \(B\), corresponding to the sharp switch that defines V\({}_{\text{ON}}\), as V\({}_{\text{A}}\) is swept upward (Figure 10c).  
_From B to C: 'Negative differential resistance'_: The anode voltage shared by the three forward-biased junctions is unnecessarily large. The negative-resistance region means that the current increases even if V\({}_{\text{A}}\) is reduced. The potential in the gated region goes from MOS depletion to inversion value. The end of this regime denotes the sharp switch under reverse bias scan V\({}_{\text{OFF}}\) (Figure 10d).  
_From C to D: 'PIN diode'_: The energy barriers are demolished, and the device operates as a forward-biased PIN diode in double-injection mode. The region of very high current is affected by the series resistance, which limits the effective voltage drop on the diode.  
This short description highlights that the \(Z^{2}\)-FET's behavior results from the competition between the MOS transport, driven by minority carriers, and the PIN diode with ambipolar transport. The sharp switching from I\({}_{\text{OFF}}\) to I\({}_{\text{ON}}\) and vice versa reflects the sudden shift from a MOS mode to PIN mode of operation.