# FPGA Implementation of a Deep Learning Acceleration Core Architecture for Image Target Detection
## 3 Results and Discussion
### Computational Scheduling Kernel Implementation and Validation  
The computational scheduling kernel designed in this paper includes the computation of the convolutional layer, the pooling layer, and the fully connected layer, where the convolutional layer contains four pipelines: Pipeline 1 is the loading pipeline for the parameter data when the number of output channels is equal to the output tensor channels during partial computation, Pipeline 2 is the loading pipeline for the parameter data when the number of output channels is not equal to the output tensor channels during partial computation, Pipeline 3 is the loading pipeline for the bias data in the batch layer,  
Figure 15: Video processing heterogeneous system board. Pipeline 4 is the main pipeline for reading the data stored on the chip and pushing it to the computation matrix to get the result of the convolutional layer. All four pipelines have an initial interval of 1 to maximize computational efficiency and data throughput. The pipeline length of pipeline 2 is 173 because when the number of output channels of the partial computation is not equal to the number of output channels of the output tensor, the address of the parameter load is not continuous and needs to be cut off into several burst transfers, so the pipeline is lengthened to avoid blocking caused by the untimely return of AXI-MM data, which reduces the efficiency of data reading. The pooling layer has the most straightforward pipeline since it does not require loading parameters, with only one main pipeline for computation and the same initial interval of 1. The fully connected layer contains three pipelines: pipeline one is the fully connected multiplication parameter loading pipeline, pipeline 2 is the fully connected bias parameter loading pipeline, and pipeline 3 is the main pipeline for computing the entire connection. Pipeline experiment results are shown in Figure 16.  
The computational scheduling kernel runs at 300 MHz with 3.33 ns per clock cycle. With the HLS pipeline design, the most extended single-cycle instruction takes 2.91 ns, with a timing margin of 0.42 ns, which meets the setup hold time for FPGA operation. The overall resource consumption of the computational scheduling kernel is shown in Table 2.  
The convolutional layer consumes the most lookup table and trigger resources, mainly because it needs to compute the accumulation of three dimensions in parallel. In contrast, the fully connected layer only needs to compute the accumulation of two dimensions, \begin{table}
\begin{tabular}{l c c c c c} \hline \hline  & **LUT** & **FF** & **DSP** & **BRAM** \\ \hline Computational scheduling kernel as a whole & 47739 & 33316 & 54 & 69.5 \\ Convolutional Computing Pipeline & 36847 & 25028 & 41 & 0 \\ Pooling Computing pipeline & 2400 & 1864 & 9 & 0 \\ Fully Connected Computing Pipeline & 7169 & 4756 & 4 & 0 \\ ZU15 EG on-chip resources & 341280 & 682560 & 3528 & 744 \\ Computational scheduling kernel Occupancy & 13.9\% & 4.8\% & 1.5\% & 9.3\% \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Computational scheduling kernel resource consumption. Figure 16: Pipeline experiment results: (**a**) Convolutional layer pipeline synthesis result. (**b**) Fully connected layer pipeline synthesis results. (**c**) Computational scheduling kernel pipeline diagram. input channel parallelism and pixel parallelism. At the same time, the convolutional layer computes data access addresses and loop counts most frequently, which requires partial multiplication, such as calculating the data address of a pixel in the input tensor or calculating the total number of current loops. Hence, the convolutional layer consumes the most DSP resources of the three.