## 1 Introduction
### Related Hardware Accelerators and Limitations  
The studies most related to the work performed here, employing non-digitized bit-serial polynomial multiplication methods, include [1; 3; 4; 12; 13; 14; 15; 16; 17]. These hardware accelerators are implemented on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. Also, we identified an open-source polynomial multiplier generator tool, which is versatile and flexible and can be accessed using [12]. This generator allows users to generate Verilog codes of multiple polynomial multiplication architectures, including Schoolbook, Karatsuba, Booth, and Toom-Cook. In addition, it is also possible to generate Verilog code for a digit-parallel kind of wrapper. The initial results on 65 nm and an Arix-7 FPGA are described in [3]. More comprehensive results, including 15 nm technology, are presented in [1]. An efficient multiplication design is described in [4], where a radix-2 Montgomery polynomial multiplication approach is considered for hardware acceleration on a Virtex-6 FPGA over polynomial lengths of 1024 bits. Their design achieves a maximum frequency of 53 MHz and performs one polynomial multiplication in 19.26 \(\upmu\)s. Moreover, their accelerator utilizes 2566 FPGA look-up tables (LUTs). For similar operand lengths of 1024 bits, as implemented in [4], a Montgomery modular multiplication accelerator is also described in [13], where the implementation results are reported on a Xilinx Virtex-5 FPGA. The maximum achieved frequency is 400 MHz, the computation time for one polynomial multiplication is 0.88 \(\upmu\)s, and the hardware resource utilization is 6105 slices. An attractive polynomial multiplication design is presented in [14]. This architecture targets operand sizes of 163 bits and uses a programmable-cellular-automata-based bit-serial approach for multiplying polynomials. The implementation results are given on a Xilinx Virtex-II FPGA. For this design, the achieved operating frequency is 177 MHz, and the time for one polynomial multiplication of 163 bits is 0.91 \(\upmu\)s. Overall, the hardware design utilizes 225 FPGA slices on older Virtex-II devices. The architectures of Booth polynomial multipliers are considered in [15; 16; 17]. In [15; 18], a radix-4 Booth multiplier accelerator is presented where the authors use an approximation technique to generate the partial products. The area and power results are realized on a 65 nm ASIC, and the authors reported values of area and power are 478.8 \(\upmu\)m\({}^{2}\) and 0.113 mW, respectively. Another radix-4 Booth multiplier accelerator is implemented in [16], where the targeted operand size is 8 \(\times\) 8. The synthesis results in power, delay, and area are reported for Synopsis 32 nm technology. We recommend that readers refer to [16] to understand the complete Booth multiplications quickly. In [17], a hardware implementation of the radix-4 Booth multiplier is implemented on a Spartan-6 FPGA for operand lengths of 32 \(\times\) 32 bits. This design can operate on a maximum of 100 MHz and uses 278 LUTs as an area. Exciting work is described in [18], where bit-serial multiply-accumulate units (MACs) are implemented for various applications, including deep learning, image processing, and signal processing. Moreover, this work investigates the potential of bit-serial solutions by applying Booth encoding to bit-serial multipliers within MACs to enhance area and power efficiencies. They present two hardware accelerators of bit-serial MACs, one regarding the radix-2 and the other the radix-4 Booth encoding multiplier. The related efforts on non-digitized bit-serial multiplication accelerators reveal that the existing architectures are frequently designed and optimized for a specific operand length [4; 14; 15; 16; 17; 18]. The open-source tool of [12] for several polynomial multipliers considers the Booth multiplication method.