## 4 Design and Implementation of Matched Filter Based on High-Power Clock Multiplexing
### Implementation of Matched Filter Based on High-Power Clock Multiplexing  
Because the increase in length will increase the complexity of hardware implementation, this paper presents a solution of high-power clock multiplexing, which can effectively reduce the resource consumption. Taking 8\(\times\) clock multiplexing as an example, the structural difference between multiplexing and non-multiplexing is shown in Figure 9.  
Figure 8: The relationship between the maximum value of \(P_{acq}\) and \(L\). Figure 9: Comparison of non-multiplexed and multiplexed long code matched filters. We assume that the spread spectrum ratio is \(N\), the number of incoherent accumulations is \(L\), and the system is driven by an \(8\times\) code clock (denoted as \(sclk\)). The minimum code phase step during code acquisition is half the chip width, corresponding to the sampling of the \(2\times\) code clock, that is, two sample points per chip. Since the system is driven by \(8\times\) code clock (denoted as \(sclk\)), the duration of each sample point is four \(sclk\) cycles. Therefore, the length of the shift register of the matched filter input data is designed to be \(N/4\). The input signal \(r(k)\) is shifted once every four \(sclk\) cycles, and the register enters a sample point. The length of a symbol after the spread spectrum is \(N\) chips, with \(2N\) sample points. Therefore, stepping through \(2N\) times yields the complete signal after spreading for one symbol. Since \(X_{l}\) is only updated every four \(sclk\) cycles, the data in the register can be completely updated every \(2 Nsclk\) cycles. When the correlation operation is performed, one sample point is taken for each code slice. Using \(sclk\) drive, four partially relevant values can be obtained during this period,  
\[Y_{l,l}(q)=X_{l}(q)C_{l}=\sum_{k=l\overline{l}N/4}^{I(l+1)N/4-1}r(k-q)c{{}_{l} }^{*}(k),\;I=0,1,2,3 \tag{12}\]  
where \(q=l\overline{l}N/4,l\overline{N}/4+\frac{1}{2},\;\ldots,\;I(l+1)N/4-1\). After the data in the register are fully updated four times, that is, after \(8N\)\(sclk\) cycles, the fully correlated value of a symbol can be obtained, which can be expressed as  
\[Y_{l}(q)=\sum_{k=l\overline{N}}^{(l+1)N-1}r(k-q)c{{}^{*}}(k),\;\;\text{where} \;q=l\overline{l}N,l\overline{N}+\frac{1}{2},\ldots,(l+1)N-1 \tag{13}\]  
In order to save storage resources, FIFO with a depth of \(2N\) is designed, and \(sclk\) is used as the working clock. If the partial correlation value \(Y_{l,l}(l\overline{l}N/4)\) is directly taken as the current input of the FIFO, then the current output of the FIFO is \(Y_{l-1,l}((l-1)l\overline{N}/4)\). Assuming that the input of FIFO is \(a\) and the output is \(b\), in order to obtain the fully correlated value of (13), the input design of FIFO is as follows:  
\[a=\left\{ \begin{matrix}Y_{l,l}(q)+b,&I\
eq 3\\ 0,&I=3\end{matrix} \right. \tag{14}\]  
Thus, every eight \(sclk\) cycles (corresponding to one sampling cycle), we can obtain a fully correlated value corresponding to a certain code phase,  
\[Y_{l}(q)=Y_{l,l}(q)+b\left|{}_{l=3}\right. \tag{15}\]  
According to Formula (5), in order to improve the reliability of the synchronous decision, the correlation values of \(L\) symbols are incoherently accumulated before the decision. An FIFO with a depth of \(2N\) is designed and driven by the sampling clock (2x code clock). If \(Z_{l}(l\overline{l}N)\) is directly taken as the current input to the FIFO, then the current output of the FIFO is \(Z_{l-1}((l-1)N)\). Assuming that the input of FIFO is \(a\) and the output is \(b\), in order to obtain the decision statistics after cumulation, the input design of FIFO is as follows:  
\[a=\left\{ \begin{matrix}Z_{l}(q)+b,&count<2N(L-1)\\ 0,&count\geq 2N(L-1)\end{matrix} \right. \tag{16}\]  
In this way, the \(2N\) cumulative decision statistics corresponding to each code phase are obtained in each \(L\) symbol period,  
\[Z(q)=Z_{l}(q)+b\left|{}_{count\geq 2N(L-1)}\right. \tag{17}\]The result of (17) can be compared with the set threshold to make a synchronous decision.