## 3 Compact Model Validation
### De-Embedding Procedure  
#### 3.1.1 InGaAs/InGaAsP UTC-PD De-Embedding  
At high frequencies (high data rates), the impact of the parasitic interconnects becomes even more important and must be accurately modelled. In our compact modelling work, this step is thus very important. Accessing the intrinsic physical parameters of the UTC-PD requires careful modeling of the RF pads and access lines. To achieve this goal, test structures reproducing the pads and access lines are required, such as the Open and the Short test structures presented in Figure 4. Indeed, there are several de-embedding techniques that can be applied to on-wafer devices, as reported in the literature [24]. A comprehensive investigation of the validity of these methods has been reported in [25]. The de-embedding methods are generally based on on-wafer \(S\)-parameter measurements of different dedicated test structures, which are then subtracted from the global \(S\)-parameter measurements of the devices under test. The number of test structures and the complexity of the de-embedding method mainly depend on the frequency at which the device operates. In this article, we show the limitations of the basic Open-Short de-embedding method at high frequencies (110 GHz). We then introduce a new de-embedding method that we have developed, which can be adapted to different designs of test structures and the frequency range of use. In order to apply the de-embedding method on the InGaAs/InGaAsP UTC-PDs, one-port \(S\)-parameter measurements were performed up to 110 GHz on dedicated test structures, which consist of an Open, a Short and some other complementary test structures that are presented later. The \(S\)-parameter measurements were preceded by an off-wafer SOLT calibration on a CS-5 substrate, in order to bring the measurement reference planes at the probe tips (Picoprobe tips). The One-port \(S\)-parameter measurements were performed using an Agilent E8361 PNA, with a frequency extender for the 67-110 GHz frequency range. The Open and Short test structures are usually modeled by a single capacitance, an inductance, and a resistance. Due to the specific design of the InGaAs/InGaAsP UTC-PDs, this representation at high frequency is no longer valid as shown by the frequency-dependent behaviors shown in Figure 5a. Consequently, complementary structures have been designed (Figure 5b), that reproduce the pads and the access lines. Along with these, an on-wafer characterization and a step-by-step reconstruction of the distributed network \begin{table}
\begin{tabular}{c c c} \hline \hline
**UTC-PD Technology** & **Draw Active Area (\(\mu\)m\({}^{2}\))** \\ \hline UTC-PD type I & InGaAs/InGaAsP & 100, 125 and 150 \\  & InGaAs/InP & 13 \\ \hline UTC-PD type II & GaInAsSb/InP & 64, 79 and 100 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Geometries of the UTC-PDs under study. Figure 4: Schematic of: (**a**) Open and Short test structures; (**b**) schematic of the UTC-PD connected to the pads and access lines. allows to extract the intrinsic characteristics of the UTC-PDs. With the equivalent circuits of the pads and access lines determined, the \(S\)-parameter matrix can be simulated, and the reflection coefficient of the UTC-PD can therefore be calculated by the following expression:  
\[\Gamma_{UTC\text{-}PD}=\frac{S_{11}-\Gamma_{M}}{S_{11}S_{22}-S_{22}\Gamma_{M}-S_{ 12}S_{21}} \tag{9}\]  
where, \(S_{\text{ij}}\) are the S- matrix elements of the pads and access lines and \(\Gamma_{M}\) is the measured total reflection coefficient. The overall equivalent circuit of the pads and access lines has three sections, as shown in Figure 5c,d. The first section represents the equivalent electrical circuit of the pads. It includes an inductance, \(L_{Pad}\), and a capacitance, \(C_{Pad}\), of the pads. The lumped parasitic elements of the pads can be determined from measurements of the reflection coefficients of the Pads-Short, \(\Gamma_{Pad\_Short}\), and Pads-Open, \(\Gamma_{Pad\_Open}\), test structures.