## 2 Background Information for FPGA-Based Mealy FSMs  
A Mealy FSM has M internal states, L external inputs, and N outputs used by other blocks of a CPS. To organize interstate transitions, special internal objects are used. These include R1 state variables and R1 input memory functions (IMFs). These objects are combined into corresponding sets \(S\), \(I\), \(O\), \(SV\), and \(D\)[14], which represent the following: \(S=\{s_{1},\ldots,s_{M}\}\), \(I=\{i_{1},\ldots,i_{L}\}\), \(O=\{o_{1},\ldots,o_{N}\}\), \(SV=\{T_{1},\ldots,T_{R1}\}\), and \(D=\{D_{1},\ldots,D_{R1}\}\). The sets \(S\), \(I\), and \(O\) uniquely follow from, for example, the FSM state transition graph (STG) [23]. However, the value of the parameter R1 is chosen by the circuit designer during the state assignment stage [23]. In the case of MBCs [24], the following formula determines the value of R1:  
\[R1=\lceil\log_{2}M\rceil. \tag{1}\]  
Formula (1) determines the number of bits for MBCs (this is the minimum possible number for the given number of states). In the case of one-hot state assignment [24], the value of R1 is equal to the number of states (\(R1=M\)). The state variables \(T_{r}\in SV\) create so-called full state codes \(FC(s_{m})\). Each state code bit corresponds to a flip-flop from a register \(RG\). The register is controlled by IMFs and two special pulses, \(Res\) and \(Clk\)[25]. The pulse \(Res\) executes the initialization of the FSM operation. This pulse sets an FSM in the initial state \(s_{1}\in S\). The pulse \(Clk\) determines the instant of state code loading into RG. The \(r\)-th bit of \(FC(s_{m})\) is determined by the value of \(D_{r}\in D\). Like the vast majority of researchers, we use D flip-flops to organize the register RG [26]. The following internal resources of FPGA fabric are involved in implementing an FSM circuit: LUTs, flip-flops, programmable interconnections, a synchronization tree, and programmable input-outputs [27; 28]. In this paper, we consider a case where FPGAs of AMD Xilinx [25] are used. A LUT is a functional generator having \(S_{L}\) inputs and a single output [24; 29]. A LUT may keep a truth table of any Boolean function it depends on up to \(S_{L}\) Boolean arguments. Nowadays, the value of \(S_{L}\) does not exceed 6. However, using dedicated multiplexers, the number of inputs can be increased to 8 (within a single CLB) [27]. If the number of Boolean arguments exceeds 8, then a corresponding function is represented by a multi-CLB circuit. This leads to the necessity of minimizing the number of LUTs and their levels in the resulting circuit [30; 31]. In this paper, we denote by the symbol \(LUTer\) a block consisting of LUTs, multiplexers, flip-flops, and interconnections. All these elements are programmable [32]. Two systems of Boolean functions (SBFs) represent an FSM logic circuit. They are the following [17]:  
\[D=D(SV,I); \tag{2}\]  
\[O=O(SV,I). \tag{3}\]  
These SBFs define a so-called \(P\) Mealy FSM whose architecture is shown in Figure 1[14]. In Figure 1, the block \(LUTerSV\) implements IMFs (2). The IMFs determine the next state code (a code of the state of transition). The flip-flops of register RG are distributed among the elements of \(LUTerSV\). The pulses \(Clk\) and \(Res\) control the operation of flip-flops. The block LUTerOF generates output functions (3). Figure 1: Architecture of \(P\) Mealy FSM. The analysis of SBFs (2) and (3) shows that their functions depend on variables \(T_{r}\in SV\) and \(i_{l}\in I\). Each function \(f_{b}\in D\cup\gamma\) depends on \(R_{b}\leq R1\) state variables and \(L_{b}\leq L\) inputs. The number of LUT levels in the corresponding circuit depends on the following condition:  
\[R_{b}+L_{b}\leq S_{L}. \tag{4}\]  
If (4) holds, then there is a single LUT in the corresponding logic circuit. The FSM circuit is single-level if condition (4) holds for each function belonging to SBFs (2) and (3). In this case, the resulting FSM circuit is characterized by the best possible values of its main characteristics.