# A Ku-Band Fully Differential Low-Power High-Input TdB Low-Noise Amplifier
## 2 Circuit Design  
This paper proposes a design for a low-noise amplifier with enhanced common-mode noise rejection properties, high input P1 dB, and low-power-consumption characteristics. Additionally, as detailed in reference [16], the differential architecture is advantageous for reducing harmonic-induced distortion due to the cancellation of the second harmonic component at the balun and virtual ground node. Figure 1 depicts the schematic of the proposed amplifier. A fully differential two-stage CS-CS structure has been selected to improve handling capability for high dynamic range signals under a low supply voltage of 1 V while ensuring adequate gain. This configuration offers several advantages. By introducing a differential architecture, it facilitates a higher input P1 dB compared to a single-ended counterpart. Additionally, it allows for the application of neutralizing capacitors and is resistant to common-mode noise. Introducing a differential structure instead of a single-ended structure may double power consumption due to the increased total width of the transistors and can also deteriorate the noise figure because of additional components. To address this issue, we applied large transistors to the CS structure. Compared to a cascode structure, the CS structure offers advantages in minimizing power consumption by operating at lower supply voltages. Evaluating the trend of change in the noise figure while increasing the width of the transistor contributes to an improvement in the noise figure. Moreover, increasing the number of parallel transistors while maintaining a constant total width configuration offers the advantage of reducing total gate resistance, thus improving the noise figure [17]. To find the optimal size for the M1 transistor in the first stage, which has the most significant impact on the noise figure, schematic-level simulations were performed using a process design kit. Figure 2a illustrates the noise figure and power consumption with respect to the transistor width variations ranging from 6 to 192 \(\upmu\)m at 14 GHz. Power consumption increases linearly as the width of the transistor increases. However, the noise figure decreases nonlinearly. Although noise figure improvement at the low-current region is large, it is difficult to select a transistor with a small width due to the large absolute noise figure value. Furthermore, when the width of the transistor is wider than 60 \(\upmu\)m, a current increase of more than two times is required to achieve a 20% improvement in the noise figure. Therefore, considering this tendency, the width of the M1 transistor was selected as 60 \(\upmu\)m. Figure 2b demonstrates an improvement in the noise figure as the total width of the transistor is fixed at 60 \(\upmu\)m and the number of transistors connected in parallel (multipliers) is increased. The enhancement in the noise figure due to the increase in multipliers is clearly evident, with the improvement being pronounced up to six multipliers. As a result, six transistors with a gate width of 1 \(\upmu\)m were selected and used in parallel. Additionally, we applied a source degeneration inductor L1 to facilitate matching between the optimum noise impedance and input impedance [18]. The bias setting for the output stage, where final amplification is achieved, involves a trade-off among several factors. These factors include power consumption, gain, distortion, and the maximum signal handling level of the amplifier. In general, class A biasing, commonly used for an LNA, provides high gain but makes it challenging to optimize power consumption and limits the handling of a high-power-level input signal. Therefore, applying class AB bias to the output stage of a low-noise amplifier can be a good choice for achieving high power efficiency and a high P1 dB [19; 20]. Typically, class AB biasing can result in reduced gain and increased signal distortion compared to class A. Therefore, in this paper, we carefully varied the bias and conducted thorough simulations.