## 1 Introduction  
Wireless sensor networks based on IEEE Standard 802.15.4 [1] can be considered as an emerging technology that will be widely used in this century. Due to the expected autonomous operation of these networks, one of the main demands on the networks and their components design is to have low-power consumption. This power consumption can be reduced by constructing low-power sensor nodes and by the design of such protocols in the network that will reduce this consumption. In this paper the physical layer design is proposed, based on the chip interleaving technique, which can reduce power consumption in the network. There are not too many references talking exclusively about physical layer design. A paper related to the modulator and demodulator design is presented in [2]. The whole transceiver design is presented in [3]. Paper [4] presents possibility of using OFDM in wireless sensor networks for underwater communications. In [5] a low power cooperative multiple inputs multiple output scheme with low density parity check channel codes is proposed for an adaptive fault tolerant systems. Some issues related to the physical layer performance estimation are presented in [6], which is not targeted to the design but to the problems of position estimation. The processing in the physical layer includes techniques applied in direct sequence spread spectrum (DSSS) systems and code division multiple access systems (CDMA). It was shown that the chip interleaving techniques can reduce the influence of fading in DSSS and CDMA systems [7, 8, 9, 10]. Following this finding, it was also shown that the chaotic sequences can be used in these systems, which increases security in signal transmission [9] when appropriate sequence synchronization is achieved [11, 12]. Following these findings this paper is proposing theoretical model of a communication system representing physical layer of wireless sensor networks. The system is analyzed for two basic cases. First case, when a single-correlator receiver is used for a binary signal transmission and the second case when an \(N\)-correlator receiver is used for symbol transmission. The spreading sequences used are defined by the Standard [1]. The contributions of this paper are as follows. Firstly, the mathematical model of communication system representing physical layer is based on the discrete time domain signal representation and processing. In the existing theory, these signals and their processing are represented in continuous time form. However, signals in analog form are not suitable for direct implementation of the system mathematical model into digital technology; thus, all signals in this paper are represented in discrete time form. Secondly, in contrast to published work in [2, 3], where the signals are analyzed in analog form and theoretical expressions for the BER are not derived, in this paper the exact theoretical analysis was performed and the expressions for probability of chip, symbol and bit error are derived for the case of noise, fading and interleaver presence inside communication system. According to the authors' knowledge, these expressions have not been derived yet in the closed form as it was done in this paper. In addition, the derivative of theoretical expressions for the system with interleavers makes a particular contribution of this paper. Thirdly, simulators are developed in MATLAB and simulation results confirmed theoretical findings. These simulators included transceiver simulation according to the Standard [1] and channel simulation. The channel simulator generated and controlled the noise power and fading in discrete time domain. The discrete time domain theoretical model and discrete time domain simulators design allowed direct implementation of the system in DSP technology. Namely, it is quite simple to develop programs in, say, C language for DSP design having confirmed the system operation by simulation in MATLAB.