# Current-Feedback Instrumentation Amplifier Using Dual-Chopper Fill-In Technique
## 1 Introduction
In contrast to the AZ technique, the chopping technique does not generate aliasing owing to sampling, allowing for the implementation of lower-noise characteristics. CFIA was therefore implemented using the chopping technique in this study. The chopper amplifier can achieve lower noise without requiring noise folding in the AZ amplifier, although it is subject to two major drawbacks: ripple and glitch. A ripple is the upmodulated offset resulting from the chopper operation. In Figure 3a, the offset of the operational transconductance amplifier (OTA) is converted to current like a red signal, and then changed to high frequency ripple component at the same frequency as the chopper frequency (\(f_{ch}\)), like a pink signal. When a low-frequency filter (LPF) is used to eliminate ripple, the overall bandwidth is reduced below the chopper frequency, and a large area becomes necessary, owing to the large RC constants. Figure 3b demonstrates that a chopper glitch also occurs at the edge of the chopper clock, owing to the delay caused by the finite bandwidth of the operational OTA. The blue signal through chopper is delayed in voltage to current conversion, as is the red signal, due to the finite bandwidth of the OTA. After that, the signal that went through chopper again has a glitch in the form of a pink signal. WThis results in input signal distortion at a frequency twice the chopper clock frequency (\(2f_{ch}\)). During the up- and downconversion operations of the chopper, chopper glitches and their harmonics produce intermodulation  
Figure 3: Drawbacks of the chopping technique: (**a**) ripple and (**b**) glitch. Figure 2: Conventional DOC techniques: (**a**) AZ and (**b**) chopping. distortion (IMD). Recent reports indicate that fill-in techniques reduce glitches and glitch-induced IMD [7]. In [7], chopped AZ amplifiers were used in a ping-pong manner; however, in this study, we employed a dual chopper amplifier with a ripple rejection loop. Because the chopper amplifier does not experience noise folding owing to sampling operations, this amplifier can achieve a low-noise floor that is nearly limited by the thermal noise level. Moreover, the correlated noise components of the dual-channel chopper amplifier can be reduced [8], resulting in a reduced noise level. In the dual-path structure, the layout matching of the switch and amplifier causes similar offsets and charge injections for the two paths, accounting for much of the switching noise. The noise caused by non-ideal switch behavior can then be eliminated by the adder. Moreover, the adder can mitigate other sources of common mode noise in the two paths, such as supply noise. Figure 4 depicts the noise structure, which is comprised of two paths and an adder. The equivalent noise at the output of the adder is expressed as:  
\[V^{2}{}_{neq(rms)}=\left(V^{2}{}_{n1(rms)}+V^{2}{}_{n2(rms)}-2\alpha V_{n1(rms )}\cdot V_{n2(rms)}\right)\cdot A^{2}, \tag{3}\]  
where \(A\) is the gain of the adder, and \(\alpha\) is the correlation efficiency between the noise source path, ranging from 0 to 1. The proposed fill-in technique uses a dual path with \(\alpha\) greater than 0. Therefore, additional noise reduction is possible, as shown in Equation (3). A low-noise CFIA employing a dual-chopper fill-in technique with a ripple reduction loop (RRL) is proposed in this study. Conventional chopper amplifiers suffer from glitches due to the chopper operation and the amplifier phase delay. In the proposed circuit, the glitch can be reduced by using the dual-channel fill-in technique. Glitch-induced IMD reduction was achieved using the fill-in technique. A wider bandwidth was also achieved by relaxing the LPF requirement using the RRL and glitch reduction. Using the chopping technique, noise folding was prevented, and a low-noise characteristic was implemented. An additional noise reduction was achieved through a noise correlation factor between the dual channels.