# A Review of Test Stimulus Compression Methods for Ultra-Large-Scale Integrated Circuits
### Increase in Test Power Consumption  
The design of scan circuits can effectively enhance the controllability and observability of the Circuit Under Test (CUT). However, correspondingly, during the process of test stimulus input into the scan circuits, the flip-flops within the scan chains generate additional test power consumption due to their charging and discharging operations [10]. This test power consumption can impact the reliability and operational performance of the chip. During testing, in order to reduce test time, the switching activity of circuit nodes within the chip is significantly increased. This results in test power consumption that is substantially higher than that of normal operating modes [11]. Excessive test power consumption not only affects the quality of chip testing but also introduces issues of heat dissipation, thereby reducing test efficiency. When the heat generated by increased test power consumption exceeds the thermal tolerance of the chip design, it can potentially lead to chip failure or permanent damage [12]. Especially for emerging devices, e.g., spintronic and SiNW FETs devices. High temperatures can lead to instability of the spin state, thereby affecting spintronic device reliability and longevity [13]. SiNW FETs have a higher density of surface states and defect states, which can vary with temperature changes, affecting carrier scattering and recombination [14]. As the scale of chip integration continues to expand, the corresponding chip cooling measures remain limited, making the issue of test power consumption increasingly prominent and a significant factor affecting the quality and efficiency of chip testing. Among the aforementioned challenges, the increase in testing costs has garnered substantial attention and concern from researchers. Increased transistor density necessitates extensive structural, functional, and parametric tests. The iterative updates of ATE struggle to keep pace with the advancements in integrated circuit manufacturing processes. During testing, the number of test channels and the test bandwidth are constrained by the physical limitations of the test equipment, resulting in limited data transmission rates [15; 16]. Given the larger number of test patterns required, efficient test stimulus compression techniques are crucial. Test stimulus compression methods, as an effective means to shorten test time, directly impact the efficiency and cost of integrated circuit testing [17] and have been widely applied in chips with multi-chiplet integration. The advantages of its application can be summarized as follows:1. **Optimization of Test Data Volume:** Reducing the volume of test data is crucial for decreasing testing costs and increasing test efficiency. Through test stimulus compression, the number of required test vectors and the volume of data can be significantly reduced without compromising the quality of chiplet testing. 2. **Reduction of Test Power Consumption:** Test stimulus compression can decrease power consumption during testing by reducing the transmission of test vectors, which is particularly important for 3D heterogeneous integrated circuits with multi-chiplet integration and emerging devices such as SiNW FETs and spintronic devices. 3. **Improvement of Test Efficiency:** In chiplet design, test stimulus compression can reduce the transmission and processing time of test vectors, thereby accelerating the test speed and enhancing overall test efficiency. 4. **Strong Portability:** Chiplet technology allows for the \"LEGO-like\" assembly of modules with different functions. Test stimulus compression methods need to be adaptable to this modular design, providing flexible test solutions for different chiplet combinations. In this paper, test stimulus compression methods are categorized into three types based on their compression principles: coding-based compression methods, scan chain structure optimization-based compression methods, and compression methods that enhance the efficiency of coding compression.