# The Eye-Opening Arbiter-PUF FPGA Implementation with Auto Error Detection
## 3 Eliminating Deterministic FPGA Routing Delays to Avoid EoA-PUF Bias
### Arbiter Routing Bias in FPGA-Based EoA-PUF
#### 3.2.3 Experimental Results of PDL Tuning  
In the first experiment, all possible combinations were evaluated for illustration purposes for one single arbiter instance. The results are shown in Figure 7. Therein, we show the arbiter D-FF decisions upon the symmetric calibration pulse as color code over the tuning of the PDLs on the x- and y-axis. Thereby, the \"tuning level\" of D-FF\({}_{\text{a}}\) is defined as \(L_{\text{a}}=\text{PDL}_{\text{ad}}-\text{PDL}_{\text{ac}}\), which is the unary-coded relative delay difference of D-FF\({}_{\text{a}}\)'s clock vs. data input. The same is defined for D-FF\({}_{\text{b}}\) and \(L_{\text{b}}\). Each combination of tuning levels was measured nine times, and the median was taken for evaluation. For tuning levels with multiple possible combinations, the averaged r of these combinations is plotted in Figure 7. Multiple combinations can occur, e.g., for \(\langle L_{\text{a}},L_{\text{b}}\rangle=\langle 20,19\rangle=\langle 20,20-1 \rangle/\langle 20,19-0\rangle\). Four dedicated areas for r = 00/01/10/11 can be observed: when C- and D-inputs would arrive simultaneously, one would expect a \(\langle 00\rangle\) output due to setup-time violations. In contrast, for no delay tuning \(L_{\text{a/b}}=0\), \(\langle 11\rangle\) is the dominant output in this particular arbiter. The underlying reason is that the clock is deterministically routed slower than the data input. By making both \(L_{\text{a/b}}\) significantly lower, i.e., the data delayed vs. the clock, no D-FF\({}_{\text{a/b}}\) can sample the input impulse and we end in a \(\langle 00\rangle\) output. By either making D-FF\({}_{\text{a}}\) or D-FF\({}_{\text{b}}\) significantly slower vs. the other, we allow one D-FF to sample the input impulse and the other not. This then results in a strong bias and outputs \(\langle 01\rangle\) or \(\langle 10\rangle\), respectively. Looking closely, the \(\langle 10\rangle\)-area is slightly narrower than the \(\langle 01\rangle\)-area in this particularly measured arbiter. This originates from a random mismatch of the measured arbiter, either in the routing delays or the four PDLs, and thus looks different for every PUF instance. After those observations, we need to decide which set of PDL tuning is optimally chosen. In the actual PUF, the two pulses arrive at the arbiter with a random mismatch-affected phase difference. Same (but opposite) phase difference should have equal probability to bring the D-FF\({}_{\text{a/b}}\) outputs to a final \(\langle 10\rangle\) or \(\langle 01\rangle\) decision and thus a 0 or 1 output of the PUF. Figure 7: Output of the D-FF\({}_{\text{b}}\)\(r=\langle\text{D-FF}_{\text{b}}\rangle\langle\text{D-FF}_{\text{a}}\rangle\) depending on all different tuning levels, which are the differences regarding unary-coded PDL-input vectors of the same D-FF. The green area is biased to \(\langle 10\rangle\), whereas the light blue area is biased to \(\langle 01\rangle\) as response. The ideal tuning set for sensitive decisions is marked with a red circle. The black arrow indicates the tuning adjustment for unbiased decisions with increasing robustness. \(L_{\text{a/b}}=1\) corresponds to an average of 7 ps as the PDLs are built with the H-SDE measured in Figure 5.  
This translates to an optimal tuning in the \(\langle 11\rangle\) area but with equal distance to both the \(\langle 10\rangle\) and \(\langle 01\rangle\) bias areas, indicated by the arrow in Figure 7. The farther the tuning setting is from the \(\langle 01\rangle\) and \(\langle 10\rangle\) regions, the larger the input pulse's random delay mismatch needs to be in order to force a decision by the arbiter.