# A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications
## 5 Simulations of the Proposed Fully Digital BPSK Demodulator
### Comparison with the State-of-the-Art  
In order to compare the proposed solution with others presented in the literature, we suggest two Figures of Merit (_FoM_s) for demodulators for Data-Link in IMDs as extracted from the review of [PERSON] et al. in the Ref. [32]. The most important parameters for these devices are power consumption, area occupation, maximum bit-rate and energy-per-bit, \(E_{b}\), and all of them could be summarized with the following equations [32,43]:  
\[FoM_{1}=\frac{DR}{f_{d}\cdot P_{DD}\cdot A} \tag{8}\]  
\[FoM_{2}=\frac{DR}{f_{d}\cdot P_{DD}\cdot\frac{A}{(I_{min})^{2}}} \tag{9}\]  
where \(DR\) is the data rate, \(f_{d}\) is the carrier frequency and \(A\) is the area occupation. The ratio \(DR/f_{d}\) is also defined as the _Data-to-Carrier Frequency Ratio_ (_DCFR_) and is sometimes expressed in percentages. On the other side, the ratio \(DR/P_{DD}\) is the inverse of the parameter \(E_{b}\). It could be noted that these _FoM_s increase if the data rate increases too and if the \(E_{b}\) decreases. Moreover, the demodulator power consumption \(P_{DD}\) is expressed in micro-watts, while the area in \(\upmu\)m\({}^{2}\) and the \(L_{min}\) is reported in \(\upmu\)m. As can be seen, the _FoM_\({}_{2}\) reported above includes both data, power and area parameters, also taking into account the technology used with the parameter \(L_{min}\), while the first, \(FoM_{1}\) does not include any technological parameter. The comparison with the state-of-the-art is reported in Table 6, where we have taken other works into account that take advantages from the US-link in order to establish a data downlink. It could be observed that the proposed fully digital BPSK demodulator is the only one that exploits the BPSK demodulation scheme, and it also presents the lowest \(E_{b}\) parameter. This is mainly due to an overall power consumption, \(P_{DD}\), that equals to about 3.3 \(\upmu\)W, that makes the system very competitive with the state-of-the-art, with a data rate that is more than 25 times higher than other solutions reported in Table 6. Furthermore, as a result of the comparison with the other works that report the area occupation (or alternatively, it was possible to evaluate this parameter from the die photo of the IC), the solution presented in this work shows the lowest area occupation. Starting from these considerations, the proposed demodulator is more than 2400 times \(FoM_{1}\) and about 60 times higher \(FoM_{2}\) compared to the other solutions reported in Table 6.  
Figure 17: Top view of the proposed demodulator layout. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & \multicolumn{3}{c}{**Corners @ \(V_{DD}=0.9\,\mathrm{V}\), \(I_{REF}=425\,\mathrm{nA}\) and \(T=37\,\mathrm{\SIUnitSymbolCelsius}\)**} \\ \hline
**Parameter** & **TT** & **FF** & **FS** & **SF** & **SS** \\ \hline \(f_{OSC}\) (MHz) & 4.2 & 4.00 & 4.31 & 4.13 & 3.92 \\ \(P_{DD}\) (\(\upmu\)W) & 1.3 & 1.44 & 1.27 & 1.25 & 1.15 \\ \hline \end{tabular}
\end{table} 
Table 5: Current Starved Gated Ring-Oscillator (CSGRO): post-layout corner simulations at body temperature. \begin{table}
\begin{tabular}{c c c c c c c c c c c} \hline \hline
**Parameter** & [23]\({}^{\text{C}}\) & [18]\({}^{\text{C}}\) & [18]\({}^{\text{C}}\) & [19]\({}^{\text{C}}\) & [24]\({}^{\text{C}}\) & [20]\({}^{\text{C}}\) & [22]\({}^{\text{C}}\) & [9]\({}^{\text{C}}\) & [22]\({}^{\text{C}}\) & [21]\({}^{\text{C}}\) & **This Work.\({}^{\text{S}}\)** \\ \hline Year & 2013 & 2016 & 2016 & 2017 & 2018 & 2019 & 2020 & 2021 & 2022 \\ Technology (nm) & 350 & 500 & 180 & 65 & 180 & 65 & 65 & 65 & **28** \\ Application & Deep-Issue & Back- & & & & & & & & \\ \multicolumn{1}{c}{} & Stem.