## 2 Methods  
Figure 1a shows the device structure of a conventional HJLTFET, in which the PG is located at the source region and has a larger workfunction than CG for inducing a P\({}^{+}\) source while CG is located at the middle for inducing an intrinsic channel, InAs/GaAs\({}_{0.1}\)Sb\({}_{0.9}\) heterostructure is introduced at the source-channel interface and a heavy doping is considered in the silicon body with concentration of \(1\times 10^{19}\) cm\({}^{-3}\), resulting in a junctionless P\({}^{+}\)-I-N\({}^{+}\) structure with appropriate workfunctions for PG and CG by the charge plasma concept. Compared with a conventional HJLTFET, a DMGE-HJLTFET still uses InAs/GaAs\({}_{0.1}\)Sb\({}_{0.9}\) at the source-channel interface and introduces a lightly doped source, moreover, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions \(\Phi_{\text{M1}}\), \(\Phi_{\text{M2}}\) and \(\Phi_{\text{M3}}\), respectively, where \(\Phi_{\text{M1}}=\Phi_{\text{M3}}<\Phi_{\text{M2}}\), as shown in Figure 1b. As a result, the DMGE-HJLTFET has larger ON-state current and lower OFF-state current than HJLTFET, so it will have great potential to be applied in future ultra-low power integrated circuit.  
The detailed parameters of the conventional HJLTFET and DMGE-HJLTFET used in the simulation were as follows: the length of source region (L\({}_{\text{S}}\)), the length of channel region (L\({}_{\text{CH}}\)) and the length of drain region (L\({}_{\text{D}}\)) were all 20 nm; the gap length (L\({}_{\text{SG}}\)) between source and channel was 5 nm; the thickness of HfO\({}_{2}\) (T\({}_{\text{OX}}\)) was 2 nm, the thickness of the body (Tb) was 5 nm; the length of auxiliary gate (L1) was 7 nm, the length of control gate (L2) was 10 nm, the length of tunnel gate (L3) was 3 nm; the workfunction of polarity gate (\(\Phi_{\text{PG}}\)) was 5.9 eV, the workfunction of control gate (\(\Phi_{\text{CG}}\)) was 4.4 eV, the workfunction of auxiliary gate (\(\Phi_{\text{MI}}\)) and the work function of tunnel gate (\(\Phi_{\text{M3}}\)) were 4.1 eV. In addition, the N-type doping concentration of the channel region and drain region were all \(1\times 10^{19}\) cm\({}^{-3}\) in the HJLTFET and DMGE-HJLTFET; whereas the N-type doping concentration of source region in the HJLTFET and DMGE-HJLTFET were \(1\times 10^{19}\) cm\({}^{-3}\) and \(5\times 10^{17}\) cm\({}^{-3}\), respectively.  
Figure 1: Cross-sectional view of (**a**) a conventional heterostructure junctionless tunnel field-effect transistor (HJLTFET); (**b**) a dual material gate-engineered (DMGE)-HJLTFET.  
All the simulations were performed using ATLAS Silvaco TCAD version 5.20.2.R (Silvaco International, Santa Clara, CA, USA). To consider the band to band tunneling phenomenon in the case of TFET and the spatial variation of the energy bands, the nonlocal BTBT model (BBT.NONLOCAL) was used. The presence of a highly doped channel meant that the Shockley-Read-Hall related to concentration (CONSRH) was activated to account for the minority carrier recombination effects. In addition to this, Fermi statistics (FERMI) and band gap narrowing (BGN) model were also activated. Moreover, a quantum confinement model given by [PERSON] (HANSCHQM) was also used to take into account quantum confinement effects due to the increased doping levels and thinner gate oxide in the channel. Furthermore, the Schenk model for trap-assisted tunneling (SCHENK.TUNN) was also involved to include the tunneling of electrons from the valence band to the conduction band through trap or defect states and phonon-assisted tunneling effects.