# A Crypto Accelerator of Binary Edward Curves for Securing Low-Resource Embedded Devices
## 1 Introduction
### Related Work  
There have been notable breakthroughs in utilizing the FPGAs for the performance improvement of point multiplication on BEC. For example, the work in [16] focuses on optimizing hardware resources by introducing a low-complexity architecture. Moreover, the architecture leverages a digital parallel least significant multiplier and employs advanced instruction scheduling techniques. The synthesis on various platforms ensures adaptability and efficiency across different hardware configurations. However, the research in [16] did not discuss the results of computational speed. In order to address the issue of computational speed, the work in [23] proposes two architectures: one for general BEC and another for special BEC. The authors also employ three finite field multipliers. The presented structures aim to strike a balance between resource utilization and latency. The first structure utilizes three parallel multipliers for high-speed performance. However, it requires a significant amount of hardware resources. For curve parameters \(d_{1}\) and \(d_{2}\) equal to 59, it consumes 4454 slices and achieves a latency of 34.61 microseconds. To address the resource utilization issue, the authors propose a second structure that employs two multipliers. This results in a significant reduction in hardware resources, utilizing only 3521 slices. Another work for high-speed BEC applications with a reconfiguration feature is presented in [24]. It achieves a maximum clock frequency of 48 MHz, indicating its capability for high-speed operations. Nevertheless, it employs a relatively high number of hardware resources (21,816 slices for regular BEC and 22,373 slices for BEC with halving). It may limit its applicability in resource-constrained environments. While the architecture handles the halving operation with minimal additional resources, its reconfigurability may come at the cost of increased resource requirements, making it less suitable for certain low-resource scenarios. As a result, the design requires further optimizations to achieve a more balanced trade-off between speed and hardware resource utilization. In other words, in addition to the computational speed, the area efficiency is equally important. The work in [25] optimizes the area utilization. For this purpose, the authors propose the utilization of a digit-serial multiplier. As a result, the area is 2138 slices for Virtex-6 and 2153 slices for Virtex-5. The limitation of the research lies in the usage of a digit-serial multiplier, as it significantly compromises the speed of the architecture. The authors of [26] strive for further optimization by employing a pipe-lined digit-serial multiplier. It not only shortens the critical path but also enhances the overall efficiency by optimizing both the throughput and area utilization. When considering a specific value of a curve parameter (\(d=59\)), the implemented hardware on the Virtex-5 platform for the group hopscotch curve (GHC) utilizes 8875 slices while achieving a latency of 11.03 microseconds. Additionally, for BEC computations, the latency is 11.01 microseconds, and the architecture uses 11,494 slices. The limitation of the research is that it does not explore the impact of different curve parameters on the proposed optimizations. The latest research, exemplified by studies such as [27], is dedicated to optimizing various design factors, including latency, area utilization, and throughput, even further. In [27], the authors introduce two innovative architectures, which leverage a combinedparallel multiplier (PM) technique. The first architecture achieves substantial improvements, showcasing enhancements of 62%, 46%, and 152% for \(GF(2^{233})\), \(GF(2^{163})\), and \(GF(2^{283})\), respectively. The second architecture allows the high-speed computation of individual PM operations, resulting in reduced latency and improved overall performance. These advancements contribute to the ongoing optimization efforts in the field.