## 2 Background and Motivation
### Cliff Potential Performance Analysis  
In this section, we show a simple example to analyze the performance potential mentioned above. As shown in Figure 2(a), given that the access flow is \(ABCDABCDAB\), the hit position is 4, so that when the capacity is less than or equal to 3, the miss rate is 1.0, and in other points, the miss rate is 0.4. There is a cliff between 0 and 4. This is assuming that the access is running in a two-layer cache which is composed of DRAM and SSD. Under the traditional cache architecture, the dram layer did not receive any hits, but if we reverse the hierarchy (SSD-DRAM) it can be found that the overall number of DRAM hits reached the limit, as shown in Figure 2(b). The reason for this is that the performance area of the cliff has an effective cache hit. Figure 2: Partition Scheme to Eliminate the Cache Performance Cliff [7; 19]. For further explanation, the access element is increased from 4 to 8, and the request flow is expanded from 10 to 80. Now, we use the two-dimensional cliff removal method proposed in Section 2.1 to allocate cache resources, and calculate the times of cache hits for each layer. The overall cache capacity is 8, and so the feasible capacity combinations are (0, 8), (1, 7), (2, 6), (3, 5), (4, 4), (5, 3), (6, 2), (7, 1), and (8, 0). Since the convex hull of the original MRC curve contains only two points, \(\sigma_{1}\) and \(\sigma_{2}\) are both 0. It can be found from Table 1 that the DRAM layer hits increase as the capacity increases, but if we want to obtain the highest hit times, the DRAM capacity must be set to 8, which is the same as the traditional method at this time. However, when considering the position of the cliff, we can easily realize the same hit number by only setting the position to 8 in the cache as in the DRAM. Based on this theory, we use the actual trace for further analysis. From the MSR Cambridge trace, we select proj_3 and hm_0 to construct MRC, as shown in Figure 3(a). There is an obvious performance cliff between the 406 MB and the 540 MB capacity point in proj_3, and hm_0 does not contain the performance cliff, so that its MRC can be regarded as an approximate convex curve. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Capacity** & \(\rho_{1}\) & \(\sigma_{1}\) & \(\rho_{2}\) & \(\sigma_{2}\) & **DRAM Hit** \\ \hline (0, 8) & & & & 0 \\ (1, 7) & 0.875 & 0 & 0.375 & 0 & 9 \\ (2, 6) & 0.75 & 0 & 0.5 & 0 & 9 \\ (3, 5) & 0.625 & 0 & 0.375 & 0 & 18 \\ (4, 4) & 0.5 & 0 & 0.5 & 0 & 36 \\ (5, 3) & 0.375 & 0 & 0.625 & 0 & 36 \\ (6, 2) & 0.25 & 0 & 0.75 & 0 & 9 \\ (7, 1) & 0.125 & 0 & 0.875 & 0 & 63 \\ (8, 0) & & & & 0 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: DRAM layer hits under each capacity. Figure 4: Cache Performance Gains as Capacity Increases. Figure 3: Access characterization of Performance Cliff. Figure 4b shows the performance gain difference between the miss rate when the capacity is increased by 64 kb. From the figure, the cache gain in the cliff performance area is significantly higher than that in the non-cliff area. Since there is no performance cliff in \(\text{hm}\_0\), except for the initial stage, no obvious performance gains are found. The performance cliff is not friendly to traditional multi-level cache because high-performance media is at the top, and the front-end area of the MRC indicates its performance. The cache performance cliff contains a stable area, and its miss rate to capacity ratio is very low, but it occupies valuable high-performance cache resources. The overall hit rate is fixed when the total capacity remains the same. The better the top-level cache hit rate, the higher the cache performance. This relationship can be expressed by Equation (3); the overall delay of the cache layer is positively correlated with the hit rate of SSD. Since the speed difference between SSD and DRAM is too large, \(h_{dram}t_{dram}\) can be approximately ignored. Assuming that the value of \(t_{std}\) is fixed, the latency is proportional to \(h_{ssd}\).