## 3 Results and Discussion  
The EQE of LEDs is mainly limited by the TIR between GaN and air interface [12]. Therefore, it is very important to increase photon escaping by changing the TIR [34]. The patterned sidewalls can increase photon escaping by reducing the TIR, thereby achieving an improvement in light efficiency. However, the common patterned sidewalls will lose a certain area of the active region, which is disadvantageous for the limited area of the micro-LEDs. To this end, a concave-convex circular composite structure sidewall, which reduce the loss of the active region area while reducing the TIR and increasing the photon escape, is designed in this paper. Figure 2a shows top-view SEM image of Device A (Flat) with flat sidewalls. The tilt-view SEM images of the patterned sidewalls (concave circular sidewall, concave-convex circular composite structure sidewall with the concave- and convex-circle radius of 2-3.5 \(\upmu\)m) of Devices B-F are shown in Figure 2b-f. As shown in the above figures, the sidewalls of all devices are uniform and smooth. Meanwhile, it is found that the convex circular portion of the concave-convex circular composite structure sidewall becomes a convex-like structure. This is due to the optical proximity effect in the process of lithography, which results in the loss of a portion of area on both sides of the convex circular portion during ICP etching. As well, the concave circular sidewalls turn to wave-like structure for the same reason. To check up the patterned sidewalls etching is damage-free process, the electrical properties, such as voltage and resistance, of micro-LEDs with flat sidewall and different patterned sidewalls are studied. Figure 3 shows the current density-forward voltage (J-V) properties of the investigated devices. Figure 1: The schematic diagrams and corresponding sidewall designs of studied devices. Figure 2: (**a**) Top-view SEM image of Device A (Flat) with flat sidewalls; (**b–f**) Tilt-view SEM images of sidewalls of devices B–F. The corresponding reverse-biased current-voltage properties are shown in Figure 4. The forward voltage of all devices are almost in coincidence under the same current density. Wherein, the forward voltages of all studied devices at the current density of 1273.8A/cm\({}^{2}\) are approximately 4.6 V. This indicates that damage isn't introduced during the ICP etching process of patterned sidewalls, resulting in a decline in electrical characteristic. At the current density of 2292.9 A/cm\({}^{2}\), all studied devices except Device B have the forward voltage of around 5.1 V. However, Device B have the forward voltage of 5.2 V. This is because the Device B using the concave circular sidewall structure loses about 5.15% of the active region area, resulting in an increase in resistance (as shown in Figure 5). With a reverse bias voltage of 10 V, the leakage current of all studied devices are approximately 29 nA. This indicates that a large reverse leakage current isn't induced during the ICP etching process of patterned sidewalls structure [31]. Figure 4: Reverse biased current-voltage properties of all studied devices. Figure 3: Forward voltage as a function of current density of all investigated devices. According to the measured J-V properties, the series resistance (Rs) of the studied devices can be calculated as [31,32,35]:  
\[I(dV/dI)=JS(dV/d(JS))=(JS)\text{Rs}+nKT/q \tag{1}\]  
Wherein, \(S\) indicates the area of the active region, \(n\) indicates the ideal factor, \(K\) and \(T\) indicate the Boltzmann constant and absolute temperature, respectively, and \(q\) indicate the electronic charge. Figure 5 shows \(I(dV/dI)\) versus current density (J) characteristics of all studied devices. The Rs of all devices can be estimated by using \(I(dV/dI)\)-J characteristics. The Rs of devices A, C, D, E, and F are around 5.0 \(\Omega\). And the Rs of Device B is 5.1 \(\Omega\), an increase of 0.1 \(\Omega\) compared with those of other devices.