## 1 Introduction  
In the highly competitive semiconductor manufacturing industry, yield analysis plays a vital role in increasing production efficiency and reducing operating costs. This is because yield is one of the most critical factors in profit, and yield analysis results are applied to enhance yield and adjust settings for poor process conditions. If yield can be predicted in advance, production planning efficiency would increase, and the accomplishment of the yield enhancing plan would be confirmed punctually. Since modern electronic devices are scaled and complicated, the overall manufacturing procedure takes over several weeks from the input of wafers to the chip packaging. Briefly, the fabrication of a device generally consists of three stages: (1) the wafer fabrication procedure constructs integrated circuits on each wafer via hundreds of precise and well-controlled processes; (2) the assembly utilizes wafer probing test results to sort dice and encases each die through multiple steps; and (3) the final test stage includes electrical testing to verify the reliability and the quality of produced chips. When there is a problematic situation that lowers the yield in the wafer fabrication stages and the cause of the lowering yield is detected in the final test phase, it lowers the profit and takes a considerable time to normalize the whole manufacturing procedure [1]. Therefore, at the end of the wafer fabrication phase, there are probing and testing steps to exclude wafers expected to have a low final test yield. Developing a model to predict the yield and counteract the lowering yield procedures in a timely manner based on the induced knowledge, is one way to effectively utilize the intermediate test results. The prediction models can strengthen the competitiveness of a semiconductor manufacturer. In work-site operations, a substantial part of yield analysis is practiced manually by experienced domain engineers. For instance, the wafers expected to have yield improvement are analyzed to confirm yield-enhancing process conditions. After the confirmation, the wafers with the modified process are predicted to have the same yield gain. On the other hand, if an instrument malfunctions, the wafers processed in the machine for a certain amount of time are predicted to have a lower yield. This method has a limit because there are possibilities for engineers to miss yield-affecting circumstances and for the same condition of one step to affect each wafer differently. Moreover, there are overfull data to monitor and examine manually in practical yield prediction. The various monitoring systems in production lines include metrology and inspection tools for monitoring processes, sensors on instruments to check the process conditions, and tests of properties for each wafer, such as electric die sorting (EDS) yield, wafer acceptance test (WAT), and final test (FT) [2]. These systems monitor only a limited number of wafers, a part of the area on chips, or certain conditions due to limitations of time, capacity, and cost. Therefore, they are not enough to identify multifaceted factors that enhance or lower the yield. Another limitation is that various data are stored in several systems separately for individual areas and are organized in different formats, while there are plenty of kinds of data, including numerical type, categorical type, and serial type, among others. Additionally, practical yield analysis is repeatedly conducted for each stored data to screen the yield-related features. Consequently, the yield analysis necessarily includes wide ranging data and needs to be expandable. An overview of the related literature is presented in this paragraph. In previous studies, semiconductor yield analysis has a long history, and particular research on yield modeling is summarized in the reference [3]. Various perspectives include defective yield loss [4], statistical process control [5], and integrated process specification systems [6].