## 3 Proposed FFT Kernel Architecture
### Architecture Modules
#### 3.2.2 Module 2  
Figure 11 presents the block diagram of Module 2 (i.e., the sorting buffer), comprising six chains of shift registers (SRs) and multiplexers. The six streams of data from Module 1 were sent or routed to six SR chains (1-6) through paths A to F, respectively. Module 2 conducted the intermediate data  
Figure 10: Detailed operations of Module 1 and control of multiplexers (M1–M5) based on clock cycles.  
Figure 9: Block diagram of Module 1.  
sorting of raidx-2/8/8 operations. For the radix-2/8 calculation, six-stream radix-2 data from Module 1 were stored in six-chain SR and then selectively read out to Module 4 for the first BF8 operations. The calculated results were stored back into the SR chain 1 by using configurable path routing and were prepared for subsequent radix-8/8 calculation. To continue radix-8/8 operations, eight data paths were selected from SR chain 1 and the output to Module 3 (CMU) for W\({}_{64}\) multiplication and the subsequent execution of the second BF8. Figure 11 shows each SR chain was structured using eight SR units, which were classified into two types: Type I and Type II. Both types exhibited eight stages of flip flops and front multiplexers to support the data shift and hold. Type I was used for SR chain 1, whereas providing parallel data accesses for eight flip flop stages. Type II was used for SR chains 2-6 and optionally enabled the routing input from other SR units.  
Figure 12 details the sorting operations of Module 2 corresponding to the periodic 10 TS units (i.e., TS0 to TS9) in Figure 8. In Figure 12, the data of each of the six A, B,..., or F streams from Module 1 (Figure 11) were represented using eight 8-sample data sections (i.e., X0, X1,..., and X7, where X can refer to A, B,..., or F). A, B,..., or F indicate the current six streams, whereas A', B',..., or F' denotes the next six streams. Figure 12 at TS0 show that seven data sections of each stream (e.g., A0-A6 and B0-B6) were prepared in SR chains. From TS0 to TS5, the first BF8 operation was performed for the eight-section A, B,..., and F sequence, and the calculated results were stored back to SR chain 1. At next TSs (i.e., TS1-TS6), the first BF8 outcomes stored in SR chain 1 for B-F streams were sent out for CMU and for second BF8 operations. The data access schemes of SR chain 1 for first BF8 (stored in) and CMU/second BF8 (sent out) were alternately changed to satisfy the radix-8/8 data permutation [Equation (5)]. This observation was enabled using type I SR (Figure 11), which proved dual serial/parallel data shifts. Figure 12 shows the data of the new-coming six sequences, namely A', B',..., and F', were sent to Module 2 after TS3. By appropriately routing the data across the SR chains (the red dashed line in Figures 11 and 12), the eight-section data of A', B',..., and F' streams were regularly arranged in SR chains for new preparation at TS7/TS8/TS9. Therefore, the proposed sophisticated sorting buffer scheme allowed Module 2 to efficiently access intermediate data for radix-2/8/8 operations. The number of word storage elements for Module 2 was 64 per stream. By combing the level of two 32-element RAMs for Module 1, the total number of storage elements was 128. This process facilities the use of minimum memory sizes for 128-point FFT as the level of SDF/MDF-based designs [9; 24; 25; 26].  
Figure 11: Block diagram of Module 2 (sorting buffer).