# An FPGA-Based Four-Channel 128k-Point FFT Processor Suitable for Spaceborne SAR
## 4 Experimental Evaluation and Results
### Performance Evaluation  
In order to evaluate the processing accuracy of the proposed FFT processor, we used the calculation result of the double-precision floating-point number FFT in Matlab as the accurate value for comparison. The width of a double-precision floating-point number was 64-bit, including 52 decimal bits, so its accuracy was considered to be much higher than a 32-bit fixed-point number. Meanwhile, we used the calculation result of single-precision floating-point number FFT in Matlab as a comparison group, which has been widely used in practice. We selected the largest relative error in the calculation result as the standard for evaluating calculation accuracy, because in actual scenes, we often care about the largest value of the data in a frequency domain, which is the main frequency component. If the maximum relative error is small, the result can be guaranteed to have high accuracy near the main frequency component. Figure 14 shows the frequency domain waveform diagram of the FFT calculation result in FPGA. Each calculation result has been divided into a real part and an imaginary part. Table 7 lists the maximum relative error values of four sets of signals in the 32-bit fixed-point number result implemented by FPGA and single-precision floating-point number result implemented by Matlab. The accuracy of the 32-bit fixed-point number in FPGA was about 10 times higher than the single-precision floating-point number in Matlab, indicating that the proposed FFT processor has better calculation accuracy because the accuracy of the 32-bit fixed-point number was originally higher than the single-precision floating-point numbers. Moreover, according to the fixed-point adjustment proposed in Section 2.2, the width of the fixed-point numbers was constantly expanding, so our data scale was actually larger than the floating-point number, which can be considered as the exchange of hardware resources for improvement of accuracy. \begin{table}
\begin{tabular}{c c} \hline
**Name of Test Signal** & **Function Expressions of Test Signal** \\ \hline Real sine signal & \(0.9\times\sin(2\pi\times 0.1\times\mathrm{t})\) \\ Complex sine signal & \(0.9\times\exp(\mathrm{j}\times 2\pi\times 0.1\times\mathrm{t})\) \\ Periodic square wave signal & \(0.9\times\mathrm{square}(100\times\mathrm{t})\) \\ Periodic sawtooth signal & \(0.9\times\mathrm{sawtooth}(100\times\mathrm{t})\) \\ \hline \end{tabular}
\end{table} 
Table 6: Function expressions of four test signals. \begin{table}
\begin{tabular}{c c c c c} \hline  & **Real Sine Signal** & **Complex Sine Signal** & **Square Save Signal** & **Sawtooth Wave Signal** \\ \hline
32-bit Fixed-point & \(1.84\times 10^{-4}\) & \(6.05\times 10^{-4}\) & \(4.18\times 10^{-4}\) & \(3.05\times 10^{-4}\) \\ Single-precision & \(1.25\times 10^{-4}\) & \(5.1\times 10^{-4}\) & \(4.8\times 10^{-4}\) & \(2.2\times 10^{-4}\) \\ \hline \end{tabular}
\end{table} 
Table 7: Maximum relative error of 32-bit fixed-point number on FPGA and single-precision floating-point number on Matlab. In order to evaluate the real-time performance of the proposed processor, we chose Xilinx LogiCORE IP Fast Fourier Transform v9.1 (xfft 9.1) as a comparison, which was limited by the lack of literature focusing on implementing large point FFT processors on an FPGA device. The maximum transform length supported in xfft 7.1 IP was 65,536; we used the single-channel FFT structure in Section 2.3 as the experimental group. The Xilinx IP can be set to four architectures, including Pipelined: Streaming I/O, Radix-4: Burst I/O, Radix  
Figure 14: Frequency domain diagram of the results of four test signals calculated by Field Programmable Gate Array (FPGA). 2: Burst I/O and Radix-2 Lite: Burst I/O. Table 8 lists the transform cycles of the proposed processor and four architectures in Xilinx IP. Compared with the four architectures, the cycles of the proposed FFT processor are slightly smaller than the Pipelined architecture, and far less than the other three architectures, which is acceptable.