## 4 Simulation and Experiment Results  
### Proposed Three-Level Communication Simulation  
Figure 7 is a simulation circuit diagram for verifying the validity of the proposed communication scheme. The simulation circuit consists of a half-bridge inverter for communication signal generation and a detector for three-level voltage detection. The photo-coupler in the detector was modeled using a voltage sensor and a comparator. In addition, it consists of an exclusive OR circuit that can detect the received signal, and the serial transmission signal is generated by using visual C in DLL (Dynamic Link Library).  
In order to verify the validity of the communication hardware proposed in this paper, the simulation was carried out in two stages. First, we conducted a simulation to check the normal transmission and reception of the communication hardware proposed in this paper. Then, when the  
Figure 6: Simultaneous bidirectional communication waveforms.  
Figure 7: Three-level communication simulation schematic.  
same protocol was used and the communication hardware proposed in this paper was applied, we attempted to verify whether the dynamic performance characteristics were improved compared to the existing communication methods.  
Figure 8 shows the results of the simulation performed by setting 19,200 bps, 8-bit data, 1 stop bit, and non-parity to verify asynchronous serial communication. As shown in Figure 8, the transmission signal \(V_{s1}\) of Module1 is an ASCII(American Standard Code for Information Interchange) code character 'U' having a hexadecimal number '\(0\times 55\)' and the transmission signal \(V_{s2}\) of Module 2 is an ASCII code character 'N' having a hexadecimal number '\(0\times 4\)E'. A three-level reception signal such as \(V_{L1}\) is generated in the communication line by transmission data of 'U' and 'N' which are real-time full-duplex communication signals of the two modules. The voltage level of the communication line is determined by the transmission signals of both modules \(V_{s1}\) and \(V_{s2}\). In order to obtain the transmission data on the transmission side, a combination of transmission data generated from the reception side and the three-level voltage of the communication line is required. That is, the reception information can be obtained by combining the \(V_{L1}\) with the three-level voltage and the transmission signal TX of the reception side through the reception information extraction circuit. The feature of this method is that it can increase the communication speed compared with the existing serial communication method by simultaneously transmitting and receiving. Furthermore, it is impossible to separate another module's transmission signal when the information of the transmission data of one module is absent from the three-level signal generated in the communication line. Even though the same ASCII character data is transmitted, since the communication is asynchronous, the three-level signal appearing on the communication line always appears in a different form. Also, when the receiver generates a transmitting signal for security when receiving an important signal, it is impossible for other devices to acquire accurate transmission data in the middle of the communication line. Therefore, the hardware proposed in this paper not only improves the communication speed compared to the existing method, but also excels in terms of the security of communication.  
Figure 8: Simultaneous bidirectional simulation results.