# A Low-Overhead Countermeasure against Differential Power Analysis for AES Block Cipher
## 4 Implementation Results
### Area and Timing Results  
The area and timing results (in terms of clock cycles) are given in Table 1. Column one provides the implemented design. The achieved clock frequency (freq. in MHz) is provided in column two. The area information in terms of slices, look-up-tables (LUTs) and flip-flops (FFs) are shown in columns three to five, respectively. The timing information in terms of required clock cycles to execute encryption (ENC) and decryption operations (DEC) is presented in columns six to seven, respectively.  
As shown in Table 1, DESIGN-I achieves 1.21 times higher clock frequency as compared to DESIGN-II. When considering the hardware utilization for comparison, DESIGN-II utilizes 1.68, 1.60 and 2.02 times higher slices, LUTs and FFs, respectively. This is due to the required additional logic for the implementation of our proposed countermeasure and Algorithm 1. Subtraction of FPGA slices of DESIGN-I from DESIGN-II determines the FPGA slices (i.e., 290) required for the implementation of additional logic. The percent increase in (when comparing DESIGN-II with DESIGN-I) slices, LUTs and FFs is also given in Table 1. The clock cycles required for the execution of encryption and decryption operations are identical in DESIGN-I and DESIGN-II (i.e., 12). Concerning the computational complexity (in terms of time required to perform one encryption and decryption operations) of our DESIGN-I, each encryption/decryption operation require 0.048 ms (ratio of 12 over 250). Similarly, the computational complexity of our DESIGN-II is 0.058 ms (ratio of 12 over 205). With the utilization of lower hardware resources, presented in Table 1, we believe our DESIGN-II is more beneficial for the applications that require prevention against DPA attacks.  
It is important to note that the additional FPGA slices (290) to implement our proposed countermeasure is 68% of our DESIGN-I (where the achieved slices value is 424). It reveals that the proposed countermeasure is not suitable for the lightweight implementations of AES. However, it is preferred to use in applications that demand high-speed AES implementations. For example, in 2019, a high-speed area-efficient implementation of AES on Xilinx Artix-7 (XC7A100T-1 CSG324C) FPGA is reported in [42]. Their architecture utilizes 15,850 slices. Our proposed countermeasure has more meaning in such an implementation because it has 54.6 times the hardware resources of [42].  
\begin{table}
\begin{tabular}{l c c c c c c} \hline \hline \multirow{2}{*}{**Designs**} & \multirow{2}{*}{**Freq.**} & \multicolumn{2}{c}{**Utilized Area**} & \multicolumn{3}{c}{**Clock Cycles**} \\ \cline{3-6}  & & **Slices** & **LUTs** & **FFs** & **ENC** & **DEC** \\ \hline DESIGN-I & 250 & 424 & 1314 & 538 & 12 & 12 \\ DESIGN-II & \
\begin{tabular}{c} 205 \\ (\(-\)18\%) \\ \end{tabular} & 714 (+68\%) &
\begin{tabular}{c} 2110 \\ (+60\%) \\ \end{tabular} & 1089 & 12 & 12 \\ \hline \hline \end{tabular} DESIGN-I is without the countermeasure. DESIGN-II is with the inclusion of countermeasure.  
\end{table}
Table 1: Area and clock cycles information on a Zynq 7020 SoC (Artix-7 device).  
Figure 3: Hardware setup to collect power traces.