## 5 Experiments and Results
### Performance Evaluation of the Data Controller  
We deployed the proposed hardware architecture on the FPGA to demonstrate its efficiency. The peak theoretical bandwidth of the DDR3 chip with a bit width of 64 bit and a working clock of 800 MHz in the existing processing board is:  
\[B=800M\times 64\times 2/8=12.8 GB/s \tag{11}\]  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Resource** & **Utilization** & **Available** & **Utilization (\%)** \\ \hline Slice LUTs & 27,369 & 433,200 & 6.32\% \\ Slice Registers & 20,514 & 866,400 & 2.37\% \\ Block RAM & 60 & 1470 & 4.08\% \\ DSPs & 0 & 3600 & 0.00\% \\ \hline \hline \end{tabular}
\end{table}
Table 4: Hardware resource utilization of the data controller proposed.  
When considering the efficiency loss caused by row activation and precharging, the actual bandwidth is:  
\[B_{\eta}=B\times\eta \tag{12}\]  
where \(\eta\) is the efficiency.  
We recorded the actual measured access bandwidth and included it in the above equation to calculate the access efficiency, providing the indicators listed in Table 5. Compared with the theoretical calculation results in Section 3.3.2, the experimental data bandwidths are slightly lower than the theoretical results due to the hardware communication overhead.  
The FPGA needs to use dual-port RAM as a data buffer between DDR3 and the processing engine. In the experiment, the burst transmission length of DDR3 is eight. According to the sub-matrix cross-storage method, the utilization rate of DDR3 burst transmission data is 100%. For data access in the range direction, the read 8 \(\times\) 64 bit data belong to two range lines, so two RAMs are needed to cache the data. For data access in the azimuth direction, the read 8 \(\times\) 64 bit data belong to four azimuth lines, so four RAMs are needed to cache the data. In order to take into account both the range and azimuth access requirements, four dual-port RAMs should be included in the system design.  
The recent FPGA-based implementations were also compared in this section. The comparison results of the proposed data controller and several recent FPGA-based implementations are presented in Table 6. The \"range\" and \"azimuth\" in the table represent the performance during the range direction access and azimuth direction access, respectively. \"Matrix transposition time\" refers to the time for reading in the range direction and then writing in the azimuth direction, which can be calculated by the DDR3 access bandwidth. The experimental results show that the data controller proposed achieves a very high data bandwidth in both the range and azimuth directions. As the data controller proposed has the characteristics of independently controlling the dual-channel storage unit, it has strong flexibility and can complete the read and write tasks separately, making the processing engine twice the throughput rate. Compared with the previous FPGA-based implementations, the data controller proposed has a higher data bandwidth and greater flexibility in terms of its design, while ensuring higher access efficiency, leading to a trade-off between resources and speed, which is very suitable for real-time SAR processing systems in spaceborne scenarios.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline  & **Range** & **Range** & **Azimuth** & **Azimuth** \\  & **(Read)** & **(Write)** & **(Read)** & **(Write)** \\ \hline Theoretical bandwidth & 12.8 GB/s & 12.8 GB/s & 12.8 GB/s & 12.8 GB/s \\ Measured bandwidth & 10.24 GB/s & 8.45 GB/s & 10.24 GB/s & 8.45 GB/s \\ Efficiency & 80\% & 66\% & 80\% & 66\% \\ \hline \hline \end{tabular}
\end{table}
Table 5: Measured bandwidth of the method proposed.