# A Novel ASIC Implementation of Two-Dimensional Image Compression Using Improved B.G. Lee Algorithm
###### Abstract  
A 2D Discrete Cosine Transform and Inverse Discrete Cosine Transform using the B.G. Lee algorithm, incorporating a signed error-tolerant adder for additions, and a signed low-power fixed-point multiplier to perform multiplications are proposed and designed in this research. A novel Application Specific Integrated Circuit hardware implementation is used for the 2D DCT/IDCT computation of each \(8\times 8\) image block by optimizing the input data using the concepts of pipelining. An enhanced speed in processing and optimized arithmetic computations was observed due to the eight-stage pipeline architecture. The 2D DCT/IDCT of each \(8\times 8\) image segment can be quickly processed in 34 clock cycles with a substantially reduced level of circuit complexity. The B.G. Lee algorithm has been implemented using signed error-tolerant adders, signed fixed-point multipliers, and shifters, reducing computational complexity, power, and area. The Cadence Genus tool synthesized the proposed architecture with gpdk-90 nm and gpdk-45 nm technology libraries. The proposed method showed a significant reduction of 31.01%, 12.17%, and 21.11% in power, area, and PDP in comparison to the existing image compression architectures. An improved PSNR of the reconstructed image was also achieved compared to existing designs. discrete cosine transform; error-tolerant adder; pipelining; low-power; fixed-point multiplier; Application Specific Integrated Circuit; Verilog; PSNR +
Footnote †: journal: Applied Sciences  
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Footnote 1: email: {T.,  
implementation is essential to reduce the power while maintaining the speed required for high-performance processors. The efficiency of the hardware resources used, such as multipliers and adders, directly indicates the performance of the hardware implementation of the DCT algorithm used. DCT implementations with reduced hardware and optimized arithmetic computations have been proposed and designed in the past. A computationally intensive algorithm, DCT encompasses many multiplications. In the contemporary era, several DCT algorithms were designed to minimize the computations and power consumed. The DCT has recently taken over as the de facto norm for compressing images before transmission via communication channels with constrained capacity. In contrast to the Fast Fourier Transform, lesser multiplications are one of the main advantages of DCT and the computationally efficient Fast Cosine Transform. Numerous excellent algorithms were devised in the past, and there is considerable literature to support these algorithms. Although there is a noticeable reduction in the computational complexity of DCT implementations using fast algorithms, there still arises a necessity to perform floating-point operations. Despite their accuracy, floating-point computations are costly when considering circuit complexity and power. One way to improve these fast algorithms' speed is by minimizing the floating-point operations. This issue can be circumvented to a small extent by utilizing fixed-point multipliers and shifters. Different algorithms are presented in the literature, and it was found that the algorithms could be improved using various techniques. In existing DCT algorithm implementations, there was a trade-off between the design metrics of power, area, and delay. In the past, various techniques were used to lower the hardware complexity of the algorithms. An implementation of the Loeffler DCT algorithm was designed by [PERSON] et al. [7] using adders and shifters. A Flow Graph Algorithm (FGA) was proposed by using unsigned constant coefficient multiplications. Improvements in power, speed, and area were achieved as add and shift operations were used to accomplish multiplications. [PERSON] et al. [8] presented an algorithm by incorporating algebraic integer coding in the ID DCT computation. This modified ID transform was used to realize a 2D DCT architecture further. The 2D DCT computation of the proposed architecture was based on the Arai algorithm.