# Review of Ka-Band Power Amplifier
## 4 Conclusions  
This paper reviewed the background, technologies and circuit topologies of the Ka-band power amplifier for the satellite communication system. The Ka-band power amplifier is a key component and hot research topic in broadband satellite communication systems with the rapid growth of low orbit Sat-COM application in recent years. The features, advantages, and trends of the different technologies and topologies of Ka-band PA are summarized and discussed in detail. III-V technologies, such as GaAs, GaN, and InP HEMT, are traditionally used to implement the Ka-band power amplifier, due to their advantage in high output power and linearity. However, the Ka-band PA based on silicon technologies is growing rapidly due to their tremendous advantage of low cost and high level of integration. The circuit topologies adopted by the Ka-band PA include common source, cascode, stacked field-effect transistor (FET), power combining, and Doherty structure. The common source topology is the simplest structure with a balance performance of gain, bandwidth, and power. The cascode topology shows good power gain, but a disadvantage on linearity due to the memory effect. The stacked-FET topology shows a very good voltage swing but decreased efficiency and linearity performance due to the imbalance on each layer of the stacked FET. The power combining method is a promising method to achieve the desired  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline
**Ref.** & **Tech** & **Frequency** & **Gain** & **Psat** & **PBO +** & **PAEpeak** & **Area** & **Topology** \\ \hline
[95] & 150 nm GaAs & 26.4 & 10.3 & 25.3 & 27 & 38 & 25 & Doherty PA \\ \hline
[96] & 150 nm GaAs & 25.5–29.5 & 15 & / & 27 & 37 & 4.93 & Doherty PA \\ \hline
[97] & 150 nm GaAs & 28.5–31.5 & 10.5 & / & 32 & 38 & 4.59 & Doherty PA \\ \hline
[98] & 28 nm CMOS & 32 & 6.7 & 19.8 & / & 21 & 1.87 & [PERSON] PA \\ \hline
[99] & 90 nm CMOS & 28.7–41.9 & 19.8 & 20.7 & 13.1 & 32.7 & 0.203 * & [PERSON] PA \\ \hline
[100] & 150 nm GaAs & 38–46 & 7 & 21.8 & 17 & / & 2 & [PERSON] PA \\ \hline
[103] & 150 nm GaAs & 29–31.8 & / & 25.7–26.8 & 21–32 +-4 & 31–38 & 3.57 & [PERSON] PA \\ \hline
[104] & 150 nm GaAs & 25.8 & 7 & 25.1 & 12.6 & 16.5 & 2.25 & [PERSON] PA \\ \hline
[105] & 45 nm SOI CMOS & 28 & 10 & 22.4 & 28 & 40 & 0.63 * & [PERSON] PA \\ \hline
[106] & 130 nm SiGeBiCMOS & 28 & 20.5 & 28.3 & 27.8 & 30.4 & 4.19 & Doherty PA \\ \hline \hline \end{tabular}
\end{table}
Table 5: Comparison of the measurement results with the Doherty PA in CMOS.  
power level with limited voltage swing, and the power combining synthesis network is an important design challenge. The differential topology is commonly used in CMOS PA for the Ka band. The Doherty architecture is a potential method to break the limitation of efficiency of CMOS PA at the Ka band.  
Conceptualization, Z.W. and S.H.; investigation, L.G.; data curation, L.L. writing--original draft preparation, Z.W.; writing--review and editing, S.H. All authors have read and agreed to the published version of the manuscript.  
This work was financially supported by the National Natural Science Foundation of China (61501261), the China Postdoctoral Science Foundation (2017M621793), and the project foundation of RIMA-LAB (KFJ)20200101).  
Not applicable.  
The authors declare no conflict of interest.