## 5 Hardware Implementation and Experimental Results
### FIR3 (Farrow interpolator)  
Figure 23 exhibits the block diagram of cubic-Lagrange-polynomial-based FIR3 (Farrow interpolator) in the LTE DFE, where mu signifies \(\mu_{k}T_{o}\), To_inv means \(1/T_{o}\), and xd indicates the input signal. The 1-bit signal, condition, became 1 when mu exceeded \(T_{o}-T_{i}\) and became 0 otherwise. The upper part of FIR3 consists of the subpart for obtaining \(\mu_{k}\) by means of multiplying \(\mu_{k}T_{o}\) by \(1/T_{o}\) and the subpart for obtaining \(\mu_{k}\), \(\mu_{k}\)\({}^{2}\), and \(\mu_{k}\)\({}^{3}\) in sequence by repeatedly multiplying \(\mu_{k}\). Thus, the upper circuitry represents the 0-th-, first-, second-, and third-order terms from left to right. Below the part exists the integrate-and-dump circuitry, which serves the purpose that the input signal was accumulated to obtain the output signal and subsequently the accumulated signal was delivered to the lower part of FIR3, according to the condition signal. The lower part of FIR3 was made up of polynomial coefficients with respect to \(\mu_{k}\). The length of the interpolation filter was 6\(T_{o}\), which means the polynomial operations were run over 6 intervals, and hence a total of 6 cubic polynomials of \(\mu_{k}\) existed, leading to a total coefficient count of 24. This was also identified in the farrow_matrix inside the Matlab script inset. At the very end of the circuitry existed a multiplier, which multiplied the signal by a scale value for coefficient normalization. The scale value for the polynomial coefficients was supplied externally since it varied according to \(T_{o}\) and \(T_{i}\). In the case of the functional model, this value  
Figure 22: FIR1 (CIC filter) application-specific integrated circuit (ASIC) synthesis results. was 0.969467455621302 for \(T_{i}/T_{o}=128/325\) and 1.454201183431953 for \(T_{i}/T_{o}=192/325\). In the case of the bit-accurate and the RTL models, it was 0.969451904296875 for \(T_{i}/T_{o}=128/325\) and 1.454193115234375 for \(T_{i}/T_{o}=192/325\). It was calculated from \(T_{i}/T_{o}/832\) where 832 was the total sum of the internal polynomial coefficients. By multiplying the normalization value at the end separately (instead of normalizing the internal coefficients), the internal coefficients could be constantly used regardless of the \(T_{i}/T_{o}\) value. The proposed integrate-and-dump circuitry was governed by the 1-bit signal, condition, as highlighted in cyan in Figure 23. By means of the operation of the integrate-and-dump circuitry, the period of the output of FIR3 was an integer multiple of the clock period, although the output of FIR3 held a non-integer value resulting from a rational-number interpolation. For instance, in the case of a fractional interpolation by 128/325, the period of the FIR3 output was twice or three times the input period and in the case of a fractional interpolation by 192/325, the period of the FIR3 output was equal to or twice the input period. The critical path of FIR3 in the ASIC is highlighted in red in Figure 23, in which case the critical path had a 19-bit-by-25-bit multiplier between two flip-flops since this was the widest multiplier in the circuitry. The former flip-flop had a delay of 0.52 ns and the multiplier had a delay of 3.72 ns, a total of 4.22 ns critical path delay. The critical path of FIR3 in the FPGA (Xilinx XC6 VLX550T) is highlighted in green in Figure 23. Whereas polynomial coefficient multiplication was carried out with high-speed constant multipliers in the case of the ASIC synthesis, digital signal processor (DSP) slices with general multipliers were utilized even for constant multiplication in the case of the FPGA P&R. The critical path for the FPGA was  
Figure 23: Block diagram of FIR3 (Farrow interpolator).