## 3 Proposed Low-Latency Compact Baseband System for Wireless VR
### Hardware Architecture for Baseband Processing  
To support the proposed baseband processing associated with the block-level interleaved-BCH ECC, we introduce in this work the dedicated hardware architecture that minimizes the hardware overheads while proving the high-throughput and low-latency data transmission. Figure 7 illustrates the block diagram of the proposed baseband architecture that can support both TX and RX modes. Note that we utilize the flexible FIFO architectures that can change the bandwidth of interfaces. More precisely, the IFIFO can support 16b and 18b input interfaces, which are used for TX and RX modes, respectively. Similarly, the OFIFO provides two options at the output interface, as depicted in Figure 7. By utilizing the flexible interfaces, it is possible to minimize the complexity overheads to support the different transmitting rates between the serialized video stream and the RF data, which are caused by appending the ECC parity information. Then, the 18-parallel BCH encoder in Figure 7 accesses IFIFO to get one 18b data block at a time. In the parallel encoder, whose internal processing architecture is detailed in Figure 8a [28; 29], there is a path to directly transfer the issued data block to the interleaver so that the proposed digital baseband processing continuously constructs the frame segments. The interleaver generates the proper address to shuffle the data blocks, as depicted in Figure 6, and the following unified buffer manager transfers the encoded data blocks to the current frame buffer. After encoding all the CCs, i.e., generating a data frame to be transmitted, the OFIFO accesses the FB\(x\) through the unified buffer manager to take 18 bits at a time, which is transferred to the analog serializer producing the bit-stream for a transmission lane of 60 GHz RF circuits.  
Note that the proposed baseband architecture in Figure 7 can be also used for supporting the RX mode. In contrast to the digital baseband system in TX mode receiving 16b-parallel data stream from the de-serializer handling the host multimedia source, the de-serializer now manages the input  
Figure 6: The example of the burst error correcting with proposed interleaving scheme.  
Figure 7: Block diagram of the proposed digital baseband system.  
bit-stream from the RFIC associated with the higher transmission rate, generating the parallel data stream of 18 bits. By changing the interface mode, therefore, the IFIFO now accepts 18 bits at a time, and the following de-interleaver directly accesses the received data block of 18 bits to reconstruct the received CCs by scattering the writing address of the current frame buffer controlled by the unified buffer manager. The 18-parallel BCH decoder is utilized to decode a data block at every cycle. More precisely, as described in Figure 8, the well-known three-stage pipelined decoder architecture associated with the codeword FIFO is introduced where each stage is fully optimized by adopting the previous techniques including the common subexpression (CSE)-elimination on syndrome calculation (SC) and Chien search (CS) units [34] and the low-complexity folded architecture on key equation solver (KES) unit [35]. As depicted in Figure 7, the decoded block is moved to the OFIFO, which is accessed by the serializer with the 16 output interface, providing the original media information to the wireless HMD.  
To provide the data rate of more than 12 Gbps, which is sufficient to transfer the uncompressed FHD video stream, we utilize two identical baseband systems in Figure 7, each of which is connected to the orthogonal transmission lane of QPSK modulation. By removing all the complicated iterative processing in the previous specifications targeting the near-field wireless communication [6; 7; 8], the proposed baseband processing still recovers the erroneous channel conditions with the simple hardware configurations, acceptable for wireless VR systems whose HMD architecture is normally energy-limited.