# A Review of Cell Operation Algorithm for 3D NAND Flash Memory
## 2 Program Algorithm
### Improvement of Program Performance  
Most major 3D NAND memory manufacturers, such as Samsung, SK Hynix, and Micron, began to produce TLC NAND products from 2015, and competition to improve program throughput of TLC operation has started to accelerate [11]. Regarding multi-plane operation, in the middle of 2010, two-plane architecture started to be used; now, four-plane operation has become the mainstream [30; 31; 32]. In addition, starting from a programming time of \(\sim\)800 us in 2014, current TLC NAND products are required to operate at value of less than 400 us [6], as shown in Figure 1. In the future, the market will continuously demand high performance NAND flash memory with lower cost and higher bit density. In addition, among NAND flash manufacturers, QLC product development is in progress and competition to improve QLC performance is expected to intensify in the next few years. In this chapter, we will review several algorithms to improve program performance. In 2D NAND, as the device size is scaled down, cell-to-cell interference by capacitive coupling between adjacent WLs increases rapidly, so a coarse and fine reprogram scheme was generally applied [33]. In the early stages of the transition from 2D to 3D NAND, this reprogram operation was also adopted in 3D NAND for enhancing the cell distribution width. However, as the cell characteristics and reliability of the charge trap device of 3D NAND have progressively improved, the page buffer circuit accepts 3 pages of data at once and completely performs the programming operation in a single Incremental Step Pulse Program (ISPP) sequence, as shown in Figure 3[34]. As a result, program throughput has been dramatically improved and power consumption greatly reduced. Next, 3 bits/cell 3D NAND Solid-State Drives (SSDs) have been shipped in earnest for both Client and Data Center applications. Several methods of reducing the time of the verify operation have been proposed to reduce the programming unit time. In NAND flash memory, the number of pulses for verifying is much larger than that of the program pulse during entire actual program time; this is because the verify operation must be performed individually on all cells to check if target threshold voltage is reached, whereas the program pulse is applied for all cells at once. D.-h. [PERSON] et al. proposed a new predictive verify concept to reduce the number of verifications [36], as shown in Figure 4. In general, after the program pulse is applied, verification is performed to check if threshold voltage has reached the target level. If it is expected that threshold voltage has reached the target level right after the program pulse, the next verify operation step could be skipped. In this case, since the probability of not being able to program to the target threshold voltage also increases, it is likely to widen the left side of the final cell distribution. Therefore, the trade-off between the program performance and cell distribution must be carefully considered. On the other hand, [PERSON] et al. suggested a dual verify scheme [31]. To simultaneously perform verification of two adjacent Vt levels in one verify operation, two different BL bias were applied from a page buffer circuit, wherein two distribution levels were verified in one WL step. This method was applied to QLC with a small gap between adjacent Vts, but it can be also adopted to TLC when the BL bias increases further. As another way to enhance the program performance, a slow bit bypass scheme to decrease the number of last program pulses for verifying the highest Vt level has been proposed [37]. An increase in the number of program loops in NAND memory mainly occurs when the slowest cells are programmed to the highest Vt distribution. As the number of program pulses increases, electric field across tunneling oxide increases, which accelerates the degradation of the reliability characteristics. Moreover, worsening of program disturb characteristics and programming time are inevitable.