## 2 Proposed Time-Based Sensor
### Circuit Operation  
Figure 2 presents the block diagram depicting the direct measurement time-based sensor, while Figure 2 displays a timing diagram illustrating the relative signals. The time-based sensor operates in two distinct phases: an initial phase and a discharging phase. During the initial phase, a current source, \(I\), is used to charge the node \(V_{c}\) to a threshold voltage, \(V_{1}\), by closing the switch \(S_{charge}\) for time duration \(t_{charge}\). This charging process can be expressed as:  
\[V_{1}=\frac{I}{C_{metal}}t_{charge} \tag{1}\]  
Subsequently, the voltage signal \(V_{1}\) is converted into a time-domain signal using a pulse generator, producing a corresponding \(Enable\) pulse signal. The pulse width of the \(Enable\) signal is then quantized by the system clock, \(f_{CLK}\), resulting in a digital code, \(D_{delay1}\), that is stored in the timing controller for later processing.  
Following the initial phase, the discharging phase begins by closing switch \(S_{rst}\) and resetting the \(V_{c}\) node to a ground state. Subsequently, the switch \(S_{charge}\) is closed for a duration equivalent to twice of the charging period, \(2t_{charge}\), leading to the \(V_{c}\) node being charged to a voltage \(V_{2}\):  
\[V_{2}=\frac{I}{C_{metal}}2t_{charge}=2V_{1} \tag{2}\]  
The \(V_{2}\) voltage is transformed into another \(Enable\) pulse, which is then quantized to yield \(D_{delay2}\). By comparing the digital values \(D_{delay1}\) and \(D_{delay2}\), it can be determined whether the \(V_{c}\) node has fallen below the threshold voltage \(V_{1}\). Notably, due to the negative gain of the pulse generator, a higher voltage results in a shorter pulse width, leading to a smaller \(D_{delay2}\) when compared to \(D_{delay1}\).  
As \(D_{delay2}\) is found to be smaller than \(D_{delay1}\), the timing controller triggers a discharge pulse to turn on the switch \(S_{discharge}\) for one clock period, \(T_{CLK}\), and increments the count of the discharge cycle, \(N_{DC}\), where \(N_{DC}\) represents the digital value of the accumulated discharge cycles. While the discharge switch is closed, the charge stored on \(C_{metal}\) begins to discharge through the resistor \(R_{metal}\). This discharge process follows an exponential decay pattern, resulting in a new voltage, \(V_{2}^{\prime}\), on node \(V_{c}\). Subsequently, this new voltage generates another \(Enable\) pulse along with the corresponding digital code \(D_{delay2}^{\prime}\).  
Figure 2: (**a**) Time-based sensor block diagram for direct measurement. (**b**) Timing diagram of the relative signals.  
The comparison and discharge process continues until the voltage on \(V_{c}\) node drops below the threshold voltage \(V_{1}\), signaling the conclusion of the discharge phase. The entire discharge process spanning from \(V_{2}\) to \(V_{1}\) can be represented by:  
\[V_{1}\leq V_{2}e^{-N_{DC}T_{CLK}/R_{metal}C_{metal}} \tag{3}\]  
Here, \(N_{DC}T_{CLK}\) represents the total discharge period. Rearranging the terms, the accumulated discharge cycle can be expressed as the corresponding RC time-constant:  
\[N_{DC}\approx\frac{R_{metal}C_{metal}\ln(2)}{T_{CLK}} \tag{4}\]  
For a detailed visual overview of the described processes, a complete operation flowchart is depicted in Figure 3.