# A Photon Imaging Detector Model with High Resolution and High Counting Rate
## 2 Detector Structure  
Figure 1 shows a schematic diagram of the detector structure, which consists of MCP stacks, a XS anode, pulse-processing electronics, and a computer. The incident photon is converted into a primary electron at the MCP input. The electron is then amplified within the pores of the MCP. The resulting electron cloud of 10\({}^{6}\)-10\({}^{7}\) electrons is accelerated towards the XS anode and collected on two orthogonal sets of metal strips. A signal processing electronic system is used to receive and process the output signal of the anode, including signal amplification, shaping, analog-to-digital conversion, and peak extraction, etc. Finally, the peak value of each anode (proportional to the amount of charge) is transmitted to the computer for centroid calculation and imaging. A traditional signal processing system includes charge-sensitive amplifiers (CSAs), Gaussian shaping amplifiers, analog-to-digital converters (ADCs), and FPGA for signal acquisition, peak extraction, and data transmission, as shown in Figure 2. The output of the anode is a short-duration current pulse, which is converted into a negative exponential voltage signal by the CSA. A pole/zero cancellation circuit is used to shorten the long tail and correct the overshoot of the output pulse. In order to measure and extract the peak value, the CSA output is amplified and shaped into an approximate Gaussian voltage signal by the shaping amplifier. Subsequently, the Gaussian shaping amplifier output is digitized by the ADC and transmitted to FPGA for peak extraction. Finally, FPGA transmits the peak value of each channel to the computer through Ethernet. The purpose of Gaussian shaping amplifiers is not only to transform the shape of the CSA output pulse from a long tail pulse to a Gaussian curve, but also to filter much of the noise from the signal of interest. Generally, the longer the shaping time, the better the noise filtering effect [18]. The shaping time of amplifiers with satisfactory noise filtering capability is usually more than several hundred nanoseconds. However, in the case of high count rates, pulse pile-up with a long shaping time will become a problem, resulting in inaccuracies or even an inability to extract the peak. In recent years, advances in microelectronics enabled the CSA and shaping amplifiers to be combined into preamplifiers with fast shaping time and low noise. In 2006, researchers at the University of California at Berkeley developed a fully parallel signal processing system, in which the RD20 amplifier (~40 ns rise time, ~200 ns fall time, ~900 e RMS with the anode connected) with charge amplification and waveform shaping was used. This  
Figure 1: Schematic diagram of XS detector structure. signal processing technique allows for high counting rates exceeding 1 MHz with the same high spatial resolution (<10 \(\upmu\)m FWHM) [11; 19]. After the development phase lasting more than ten years, the team's researchers improved the performance of the XS detector to a spatial resolution of <20 \(\upmu\)m at a >5 MHz counting rate [20; 21]. The detection system with this architecture achieves excellent performance. However, in the case of a varying count rate, the fixed shaping time makes it unable to fully exert its advantages. For example, at low count rates, a system with a long shaping time will have lower noise than a system with a short shaping time. At a higher count rate, using a short shaping time at the expense of noise filtering performance can keep the detector working, without serious waveform superposition and data congestion. Therefore, a new signal processing system with digital trapezoidal shaping is proposed, as shown in Figure 3. Similar to the traditional architecture, the CSA is used to amplify the anode pulse. However, there is no Gaussian shaping amplifier, and the CSA output is directly digitized by the ADC and then transmitted to FPGA. The shaping and filtering are performed by the trapezoidal shaping filter in FPGA.