# Configurable Hardware Core for IoT Object Detection
## 6 Conclusions and Future Work  
This study described the design of a configurable accelerator for object detection with YOLO in low-cost FPGA devices. The system achieved 7 and 14 FPS running the Tiny-YOLOv3 neural network with precision scores of 31.5 and 30.8 mAP\({}_{50}\) in the COCO 2017 test dataset (close to 32.9 of the original model with floating-point), for 16- and 8-bit  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & [38] & [39] & [41] & [40] & **Ours** \\ \hline Device & ZYNQZU9 EG & ZYNQ7020 & VirtexVX485T US XCKU040 & ZYNQ7020 \\ \hline Dataset & Pedestrian signs & \multicolumn{4}{c}{COCO dataset} \\ \hline Quant. & 8 & 16 & 18 & 16 & 16 & 8 \\ \hline Freq. (MHz) & - & 100 & 200 & 143 & 100 & 100 \\ \hline DSPs & - & 120 & 2304 & 832 & 208 & 208 \\ \hline LUTs & - & 26 K & 49 K & 139 K & 27.5 K & 33.4 K \\ \hline BRAMs & - & 93 & 70 & 384 & 120 & 120 \\ \hline Exec. (ms) & 9.6 & 532.0 & - & 24.4 & 140 & 68 \\ \hline FPS & 104 & 1.9 & - & 32 & 7.1 & 14.7 \\ \hline FPS/kLUT & - & 0.07 & - & 0.23 & 0.26 & 0.44 \\ \hline FPS/DSP & - & 0.016 & - & 0.038 & 0.034 & 0.068 \\ \hline FPS/BRAM & - & 0.020 & - & 0.083 & 0.058 & 0.116 \\ \hline \hline \end{tabular}
\end{table}
Table 10: Performance comparison with other FPGA implementations.  
quantizations, respectively. Given the drastic simplification achieved with the fixed-point representation, this accuracy loss is acceptable.  
The configurability of the accelerator allows tailoring the design of the architecture for different FPGA sizes and Tiny-YOLO versions, as long as the CNN only uses the layers supported by the accelerator. The tested design was implemented with 16- and 8-bit fixed-point representation of weights, bias, and activations, but other quantization sizes can be considered.  
The results are very promising, considering that a low-cost FPGA was utilized and that the solution is at least 6X faster than a state-of-the-art CPU. To improve the throughput of the object detection in IoT devices, two research directions can be followed. At the algorithmic level, model reduction with negligible accuracy loss is fundamental. Tiny models were a step towards this, and they keep improving. Otherwise, the high computing requirements of the backbone CNN of object detectors limit its applicability to edge devices. Quantization is another fundamental aspect since it also determines the computational requirements. In the case of the FPGA where the datapath of the computing units can be customized, this is a major optimization aspect. Finally, hardware-oriented algorithm optimizations benefit from a more efficient hardware design. An integrated algorithm-hardware development provides better solutions.  
Conceptualization, P.R.M., D.P., M.P.V. and J.T.d.S.; methodology, P.R.M., D.P., M.P.V., J.T.d.S. and H.C.N.; software, P.R.M. and D.P.; validation, P.R.M., D.P., M.P.V., J.T.d.S. and H.C.N.; formal analysis, P.R.M., D.P. and J.T.d.S.; investigation, P.R.M., D.P., M.P.V., J.T.d.S. and H.C.N.; resources, P.R.M., D.P., R.P.D., J.D.L. and J.T.d.S.; data curation, P.R.M., D.P., M.P.V., J.T.d.S., J.D.L. and R.P.D.; writing--original draft preparation, P.R.M. and D.P.; writing--review and editing, P.R.M. and M.P.V.; visualization, P.R.M., D.P., J.D.L. and R.P.D.; supervision, M.P.V., J.T.d.S. and H.C.N.; project administration, J.T.d.S.; funding acquisition, J.T.d.S. All authors have read and agreed to the published version of the manuscript.  
This work was supported in part by the Fundacao para a Ciencia e Tecnologia (FCT) under Grant UIDB/50021/2020 and in part by the projects PTDC/EEI-HAC/30848/2017, through INESC-ID and IPL/IDI&CA/2020/TRAINEE/ISEL through Instituto Politecnico de Lisboa.  
The authors declare no conflict of interest.