# Current-Feedback Instrumentation Amplifier Using Dual-Chopper Fill-In Technique
## 4 Conclusions and Discussion  
In this study, we present a dual-chopper CFIA with an RRL for glitch reduction. The chopping technique was used to obtain noise characteristics in the amplifier. However, glitches caused by chopping occur at each edge of the chopper clock, resulting in glitch-induced IMD. Owing to the input offset, the chopping technique also produces ripples.  
Glitch-induced IMD was reduced in this study using a fill-in technique, whereby only neat signals were alternately used as outputs by avoiding the glitch section with a dual-chopping channel CFIA. By using the dual channel, it was possible to obtain an effect of noise reduction according to the noise correlation factor between channels. The RRL was implemented to reduce the ripple caused by chopping so that a high-order LPF was not required.  
The proposed CFIA is based on a low-noise chopper fully differential difference amplifier with a cascode stage and a Monticelli class-AB output stage, which can drive a larger load and increase power efficiency.  
The proposed dual-chopper CFIA was constructed using a standard 0.18 \(\upmu\)m CMOS process, occupying an effective area of 1.28 mm\({}^{2}\), and its current consumption with a 1.8-V power supply is 29.5 \(\upmu\)A. The proposed CFIA had a gain of 51 V/V and GBW of 420 kHz.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & **This Work** & **[9]** & **[10]** & **[11]** & **[4]** \\ \hline
**Architecture** & **CFIA** & **CFIA** & **CFIA** & **CFIA** & **CFIA** \\  & chopping + & Multipath +chopper & & Multipath + chopper & Auto-zeroing + \\  & fill-in + RRL & stabilization +RRL & & stabilization +RRL & chopping +ping-pong \\ Technology (\(\upmu\)m) & 0.18 & 0.18 & 0.18 & 0.18 & 0.5 \\ Supply voltage (V) & 1.8 & 3.3 & 1.8 & 1.8 & 3.0–5.0 \\ Current consumption (\(\upmu\)A) & 29 & 123 & 2.23 & 169 & 1700 \\ Power consumption (mW) & 52.2 & 405.9 & 4.014 & 304.2 & 5100–8500 \\ Active area (mm\({}^{2}\)) & 1.28 & 1.28 & 0.536 & 1.4 & 2.5 \\ Gain bandwidth (Hz) & 420 k & 1.92 M & 580 k & 59.2 k & 800 k \\ Input-refer noise & 53.3 @1 Hz & & & & \\ (mV/V /Hz) & 24.7 (integrated) & 10 & 86.6 & 18.3 & 27 \\ CMRR (dB) & 108.8 & \textgreater{}100 & 176.6 & 162 & 142 \\ PSRR (dB) & 105.3 & \textgreater{}90 & 119 & 112 & 138 \\ Offset (V) & 11 n & 1 n & - & - & 2.8 \(\upmu\) \\ NEF \({}^{*}\) & 4.4 & 4.3 & 4.94 & 14.2 & 13.5 \\ \hline \hline \end{tabular} \({}^{*}\) NEF = V\({}_{\text{ni}}\)(V/2-I\({}_{\text{tot}}\)/\(\uppi\)+U\({}_{\text{T}}\)-4 kT-BW).  
\end{table}
Table 6: Performance summary of the proposed CFIA and comparison with other studies.  
Figure 18: Measured (**a**) output offset and (**b**) input-referred offset.  
The input-referred noise at 1 Hz was 53.3 nV/vHz, and integrated noise was 24.7 nV/vHz, with an NEF of 4.48. The CMRR and PSRR have values of 108.8 dB and 105.3 dB at 100 Hz, respectively. The input offset is 11 v, with a 51 V/V gain. The IMD amplitude at the chopper frequency harmonic is -70 dB.  
Conceptualization and supervision, H.K.; investigation and writing--original draft preparation, G.C.; writing--review and editing, K.N., M.Y., S.K., B.J., K.K. and H.S. All authors have read and agreed to the published version of the manuscript.  
This work was supported (funded) by Nanomedical Devices Development Project of NNFC (CP22021M). This research was supported by the MSIT (Ministry of Science and ICT), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2021-2017-0-01635) supervised by the IITP (Institute for Information & Communications Technology Planning & Evaluation). This study was supported by a National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (No. 2022R1A2C100517011).  
Not applicable.  
The EDA tool was supported by the IC Design Education Center (IDEC) in Korea.  
The authors declare no conflict of interest.