# Multi-Line Prefetch Covert Channel with Huge Pages
## 8 Discussion  
Our evaluation demonstrates that the proposed multi-line prefetch-based covert channel significantly outperforms previous single-line encoding schemes in its throughput. However, several avenues remain for further enhancements of the channels' reliability, robustness, and stealthiness. Accuracy Optimization:  
While our current implementation achieves an up to 83.34% decoding accuracy with write-access encoding and 81.23% with read-only encoding, the accuracy could be improved further through several techniques. First, tuning the synchronization intervals between the sender and the receiver could mitigate the timing drift and system noise that degrade the decoding precision. Second, our current use of a bucket-based message encoding strategy--where each message corresponds to a specific number of accessed cache lines--already improves the robustness by reducing the decoding ambiguity. Increasing the bucket size further (i.e., using larger groups of cache line accesses per message) can improve the accuracy, especially under noisy conditions, at the expense of a reduced throughput. Research on AMD SEV: We also evaluated the decoding accuracy on AMD SEV VMs with 2 MB huge pages under write-access encoding. The results demonstrate a  
Figure 3: Bucket size vs. accuracy for 2 MB huge page, write-access setting on AMD SEV. consistent increase in accuracy with larger bucket sizes, reaching up to 88.03%. This confirms the effectiveness of the bucket-based strategy in virtualized TEEs. Write access causes observable coherence-induced latency changes, allowing for higher reliability in detection even under cloud-based timing variability. Future research on AMD SEV platforms could explore dynamic channel adaptation strategies to maintain the decoding accuracy under varying system loads and noise conditions. For instance, runtime adjustment of the bucket sizes or synchronization intervals could improve the robustness in multi-tenant cloud environments. Additionally, as SEV-SNP introduces stricter integrity protections and memory access controls, it would be valuable to evaluate whether covert channels based on cache coherence events remain practical under these constraints. Investigating the interaction between SEV's memory encryption and microarchitectural behaviors--such as cache sharing and prefetch activity--could offer deeper insights into the resilience or detectability of such attacks in evolving confidential computing infrastructures. Machine-Learning-Based Decoding: Integrating a lightweight machine learning model for classification of the timing traces could enhance the decoding accuracy further, especially in noisy or unpredictable environments. By training the model on the observed timing patterns associated with different line access counts or cache states, the receiver can distinguish between valid message values and false positives caused by system activity or cache noise better [33; 34; 35; 36]. Expanding Coherence Exploits:  
Our current design focuses on leveraging the MESI cache coherence protocol, primarily through read and write operations that trigger transitions from the shared (S) state to the modified (M) state, as well as from the invalid (I) state to the modified (M) state. Future work could investigate a broader range of MESI state transitions, including the exclusive (E) state, which may display distinct timing characteristics or variations in the coherence traffic patterns. These additional behaviors could potentially enhance the bandwidth of the covert channel, the improve stealth by reducing observable system events, and offer greater flexibility in encoding strategies. Cross-Platform Considerations: While our implementation and evaluation focus on Linux due to its flexible support for huge pages, prefetch instructions (e.g., __builtin_prefetch()), and high-resolution timing via rdtscp or clock_gettime(), it is important to briefly consider other major operating systems.