## 2 Background
### Schoolbook Strategy
For example, in existing Booth multiplication designs [4; 17; 18], the most frequently used adder circuit is a carry-save, which efficiently computes the sum of three or more binary numbers. Such adder architectures benefit when implementing optimized variants of a Booth multiplier like radix-2, radix-4, radix-8, and so on. Instead of the carry-save adder, other possible circuits are the carry-lookahead adder, ripple-carry adder, etc. Note that these different adder circuits have their advantages and limitations. We want to let the reader know that subtractor designs can be implemented using adder logic in the digital circuit domain. An adder-subtractor can add and subtract binary numbers in one circuit. However, our accelerator is parameterized and flexible, so we prefer the most straightforward solutions for implementing these circuits. We used the Verilog HDL adder and subtractor operators (+ and \(-\)) to enforce these blocks. ### Multiplexer (4 \(\times\) 1)

The multiplexer is a routing network between the adder, subtractor, and _Reg-A_. The corresponding inputs to this multiplexer are from the adder, subtractor, and _Reg-A_. Similarly, its output is also connected to the accumulator register to hold the accumulated result, as shown in Figure 1. The control block will generate the two-bit control signal, shown with red dotted lines in Figure 1, to select the correct input signal for multiplexer output. Whenever a similar control signal to this multiplexer is input, meaning 00 or 11, the multiplexer selects the value from _Reg-A_--which signals not to do anything and holds the previous value of the _Reg-A_. For the other two cases, when the two-bit control signal is 01 or 10, the multiplexer selects the output from the adder or subtractor to update the accumulator, respectively. ### Shift-Right-Add Block

The _shift-right_add_ unit in Figure 1 takes three inputs and produces one output. The inputs are \(b_{j+1}\), \(b_{j}\), and _Reg-A_, while the output is the resultant polynomial \(c\). We already mentioned in Section 2.2 that the _shift_right_add_ function in lines 6 and 9 of Algorithm 2 facilitates the multiplication of the multiplicand by 2 through the shift and add operations. This means that whenever the values for \(b_{j+1}\) and \(b_{j}\) are 01 or 10, perform a 2-bit shift in _Reg-A_ towards the right, and then, update the corresponding _Reg-c_. Similarly, whenever the values for \(b_{j+1}\) and \(b_{j}\) are 00 or 11, this means do not do anything and keep _Reg-c_ as its previous value. ### FSM Controller

This work employs an FSM controller to execute control functionalities, as illustrated in Figure 2. The controller's primary responsibilities include (i) generating control signals for the \(4\times 1\) routing multiplexer and (ii) inspecting two bits of \(b_{j+1}\) and \(b_{j}\) in one clock cycle from _Reg-b_. The controller logic is characterized by two states, outlined in Figure 2. We provide some more specific details about these two states below. The FSM's initial state is state-0. This is an idle state, which means the multiplier will stay in this state until the _start_ signal is 1. Moreover, upon reset, it means that when the _rst_ signal is 1, the FSM of the multiplier design initializes all registers with their default values--whenever the FSM receives a _start_ signal with 1, it turns to state-1. State-1 of the FSM ensures the complete polynomial multiplication computation. It starts execution when it receives the _start_ signal as 1. Moreover, our parameterized multiplier accelerator design uses an additional 12-bit _count_ register, not previously shown in Figure 1. The reason to use a 12-bit register is to provide flexibility for multiplying polynomials up to \(2^{12}\). This means users can multiply polynomials up to operand lengths of 4096 bits. This is the limitation of our accelerator design. It is possible to increase the size of this _count_ register, but the implementation results reported in this paper are with a 12-bit _count_ register.