## 3 Prototyping of the Proposed CAPT Framework
### Optimizations  
Automatically synthesizing the behavior from high to low abstract levels allows fast algorithm prototyping, but there are still performance gaps between it and manual implementations in terms of time control, execution speed, consumption, and other factors [53; 54]. As indicated in ref. [52], the quality of the HLS-based implementations is impacted by the following three factors: high-level description of language, optimization forms, and applying orders of optimization forms [55; 56]. In the case of this paper, multiple optimization forms are made successively at the interface, loop, and instruction levels in order to accelerate the implementation by improving the parallelism of the code. According to the estimations, the first loop nest costs almost all the clock cycles in the original implementation (7454790 vs. 7455344 cycles), so the main goal of the optimization work is to accelerate this part. First, the memory ports of the target core are optimized in order to mitigate access conflicts and reduce consumption due to the logic controls. According to Algorithm 3, **x** and **W1** are the frequently-activated ports in the first loop nest, and this will lead to access conflicts when parallelizing. We therefore partition the related arrays from a single to multiple ones to expand the bus width. An index \(D_{\text{opt}}=4,8,16,\dots\) is defined to present the optimization depth. The optimized memory port protocol is shown in Table 2, demonstrating that the band of the two ports is multiplied by \(D_{\text{opt}}\times\). With Vivado HLS, this optimization is made by inserting the directives of \(array\_partition\) into the code (see Lines 1 and 2 of Algorithm 4). The option _cyclic_ creates smaller arrays by interleaving elements from the original array. The array is partitioned cyclically by putting one element into each new array before coming back to the first array to repeat the cycle until the array is fully partitioned. The option \(factor\) specifies the number of smaller arrays that will be created. ```
0: utterance sample \(\textbf{x}[m]\), coefficients \(\textbf{W1}[n\times m]\), \(\textbf{W2}[n]\), \(\textbf{B}\) and \(\textbf{ETA}\)
0: decision RETURN
1:#pragma HLS ARRAY_PARTITION variable=x cyclic factor=\(D_{\text{opt}}\) dim=1
2:#pragma HLS ARRAY_PARTITION variable=W1 cyclic factor=\(D_{\text{opt}}\) dim=2
3:Initialization
4:for\(i\in\{0,1,2,\ldots,n-1\}\)do
5:for\(j\in\{0,1,2,\ldots,m/D_{\text{opt}}-1\}\)do
6: #pragma HLS OCCURERENCE
7:\(ind\_\{1,2,\ldots,D_{\text{opt}}\}\leftarrow\{j\times D_{\text{opt}},j\times D _{\text{opt}}+1,\ldots,j\times D_{\text{opt}}+D_{\text{opt}}-1\}\)
8:\(reg\_\{1,2,\ldots,D_{\text{opt}}\}\leftarrow\textbf{x}(ind\_\{1,2,\ldots,D_{ \text{opt}}\})\times\textbf{W1}(i,ind\_\{1,2,\ldots,D_{\text{opt}}\})\)
9:\(\textbf{h1}(i)\leftarrow\sum_{k=1}^{D_{\text{opt}}}(reg\_\{k})\)
10:endfor
11:endfor
12:for\(i\in\{0,1,2,\ldots,n\}\)do
13:#pragma HLS PIPELINE
14:if\(\textbf{h1}(i)\geq 0\)then
15:\(reg\leftarrow reg+\textbf{h1}(i)\times\textbf{W2}(i)\)
16:endif
17:endfor
18:\(h2\gets reg+B\)
19:\(\delta 2\gets 1/(1+\exp(-h2))\)
20:if\(\delta 2\geq\)ETAthen
21: RETURN\(\leftarrow\)true
22:else
23: RETURN\(\leftarrow\)false
24:endif
```  
**Algorithm 4** Pseudocode of the Optimized CAPT implementation at \(D_{opt}\)  
Next, the FSM control flow is simplified via loop manipulations. As shown in Algorithm 4, we first move all the register allocation operations of Algorithm 3 to the beginning of the routine, which fuses States 0 and 7 into a single one during synthesis. The isolation between the second and third loops is therefore broken, so we can further simplify the control flow via loop mergence. The merged loop is shown in Lines 13-18 of