## 3 Analog Fronthaul Based on the Development of a Real-Time A-IFoF Transceiver
The developed platform implemented the Ethernet en/de-capsulation of the data, the baseband processing in both the transmitter (Tx) and receiver (Rx) sides and the interfacing with the optoelectronic units transferring analog radio waveforms. The details of each implementation block are briefly discussed below:  
* **Ethernet en/de-capsulation:** RFSoC has increased capabilities in terms of its Gigabit Ethernet connectivity, as its Gigabit transceivers (GTY) can support up to 25 G Ethernet with the MAC and physical coding sublayer (PCS) that are implemented on the FPGA fabric. The Ethernet core performed data link layer functionalities in order to map the incoming Ethernet traffic to the DSP engine, as well as to recover the Ethernet frames from the demodulated waveforms. These functionalities include basic error handling, flow control for access to the physical layer, frame encapsulation and virtual local area network (VLAN) tagging. * **Baseband processing:** The signal processing functions of the implemented A-IFoF transceiver were executed within the FPGA fabric of the RFSoC platform. The multiple lane processing of up to 4 independent data streams was applied for low-latency implementation. Two independent and identical transmitter/receiver side DSP block chains were developed within the RFSoC for the establishment of full-duplex connectivity. At the transmitter side, the incoming bit-stream was initially mapped to quadrature phase shift keying (QPSK) symbols, while the OFDM signals were generated using a fixed 256-tap inverse frequency Fourier transform (iFFT) algorithm. The FPGA clock was 256 MHz, corresponding to the transmission of 204 MHz of useful bandwidth after zero-padding (52 out of 256 sub-carriers). A cyclic prefix (CP) of 64 samples' length was inserted into the signal before its digital-to-analog conversion. At the receiver side, the timing synchronization of the signal was achieved through an auto-correlation function that was targeting the identification of the CP, which indicates the start of the OFDM signals. After the CP elimination, a 256-tap FFT function was used for the demodulation of the OFDM symbols. Following this, a zero-forcing (ZF) algorithm was implemented for the channel estimation and equalization of the received data. For this purpose, 21 pilot sub-carriers that were multiplexed with the data subcarriers were also transmitted. * **RF data converter functions:** The RFSoC device was equipped with 8 DACs and an equal number of ADC units that were supporting sampling rates of up to 4 Gbps. Moreover, each converter had its own dedicated digital datapath that was implementing DSP blocks, such as interpolation, decimation filters and digital mixers in order to digitally up-/down-convert (DUC/DDC) from/ to the baseband. The programmability of the analog mixed signal (AMS) blocks offered the ability to process real or complex signals and support multi-band operation. * **Electro-optic interfaces:** Highly linear optoelectronic units were used in order to realize an IM/DD communication strategy for the optical segment. In more detail, the use of an electro-absorption modulated laser (EML)-based analog IFoF transmitter was selected as a cost effective, integrated solution that has been extensively proposed for the emerging densified 5G network topologies [35]. Commercial off-the-shelf photoreceivers were used in order to detect the analog optical signals, thereby providing the radio waveforms to the mixer stages of the mmWave boards. As such, the specific power consumption details of each stage of the transceiver are presented in Table 1. Apparently, the conversion of the digital streams to analog signals and vice versa is the most power-consuming process. The evaluation of the presented A-IFoF transceiver design was initially performed through the investigation of latency and power-consumption measurements (Table 1).