## 3 Results and Discussion
The case of bare PDMS without any TiO\({}_{2}\) NS embedded shows that the temperatures of the chipset and TIM were 67.18 \({}^{\circ}\)C and 44.83 \({}^{\circ}\)C, respectively, which is about a 50% temperature difference ratio between them. This means that the applied heat could not be easily transferred from the chipset to TIM due to the heat trapped inside the chipset because of the high thermal resistance between them. In the case of TIM with the 20 wt% TiO\({}_{2}\) NS-filler in PDMS, the temperatures of the chipset and TIM were lowered to 58.19 \({}^{\circ}\)C and 44.83 \({}^{\circ}\)C, respectively, with a temperature difference ratio of about 37.7% between the chipset and TIM. Meanwhile, TIM with the 20 wt% TiO\({}_{2}\) NS- filler/monolayer in PDMS maintained a chipset temperature of 45.18 \({}^{\circ}\)C and TIM temperature of 40.58 \({}^{\circ}\)C, which were not only the lowest temperatures among the samples but exhibited a reduced temperature difference of only 11.3%. These smallest temperature differences indicate that the TiO\({}_{2}\) NS-monolayer results in low interface thermal resistance and efficient heat conduction, as shown in Figure 6a. Based on these results, simulations were conducted successively by changing of the TiO\({}_{2}\) NS-filler loading fraction from 0 wt% to 20 wt%, 30 wt%, and 40 wt%, with and without the TiO\({}_{2}\) NS-monolayer. The thermal conductivities of fabricated TIMs were enhanced, which lowered the chipset temperature by about 20.3% (from 59 \({}^{\circ}\)C to 47 \({}^{\circ}\)C) with increasing loading fractions of the TiO\({}_{2}\) NS-filler from 0% to 40 wt%; additional heat dissipation enhancement via inclusion of the TiO\({}_{2}\) NS-monolayer lowered the chipset temperature by an additional 10-15% compared to TIMs without the TiO\({}_{2}\) NS-monolayer. The increased thermal conductivity was affected by the TiO\({}_{2}\) NS-monolayer for all filler loading fractions, as evidenced through the lowered chipset temperatures and experimental results. The detailed heat transfer processes between the chipset and TIM with TiO\({}_{2}\) NS-filler/monolayer are considered in Figure 7. The increase in thermal conductivity and reduction in thermal resistance at the interface due to the TiO\({}_{2}\) NS-monolayer can be attributed to how the embedded TiO\({}_{2}\) NSs can maximize the effects of heat absorption from the heat source. In the case of TiO\({}_{2}\) NSs embedded in PDMS TIMs without a TiO\({}_{2}\) NS-monolayer, the heat absorption from the heat source is not easily observed due to the high thermal resistance of uneven contact points between the chipset and TIM, as well as the poor thermal conductivity of PDMS [29]. Moreover, the relatively small area for  
Figure 6: **(a)** The typical simulated thermal distribution results according to the presence or absence of the TiO\({}_{2}\) NS-filler (20 wt%) and monolayer in PDMS matrix. **(b)** The simulated temperature (at steady-state) of heat sources according to concentration of the TiO\({}_{2}\) NS-filler with and without TiO\({}_{2}\) NS-monolayer in PDMS matrix as the TIM. heat conduction from the chipset to TIM due to the limited contact interface between them hindered effective heat dissipation [30]. However, the TiO\({}_{2}\) NS-monolayer with TIM can absorb large quantities of heat with higher thermal conductivity than PDMS. In this way, the absorbed heat can be released into the TIM through a large surface contact area with the TiO\({}_{2}\) NS-monolayer. The released heat is transferred outside following the heat path formed by the TiO\({}_{2}\) NS-filler, which can result in strong cooling effects on electronic devices without additional loading fraction changes of the TiO\({}_{2}\) NS-filler [31]. Consequently, the suggested facile TiO\({}_{2}\) monolayer embedding method is an effective way to fabricate a low-cost and high-performance TIM, which has enormous potential for heat dissipation technology.