## 4 Analysis of Our Current Approach
The block _LUTerASV2_ implements SBF:  
Figure 4:0  
Let us analyze the proposed solution. The partition \(\pi_{\text{S2}}\) has \(J\) classes. Obviously, the following conditions take place:  
Figure 4:1  
Figure 4:2  
Due to the validity of condition (27), we can state that the circuit of the \(P_{2T}Y\) Mealy FSM (Figure 5) is not slower than the circuit of the equivalent FSM \(P_{T}Y\) (Figure 3). Due to the validity of condition (28), we can state that the circuit of _CorePC_ for FSM \(P_{2T}Y\) should perform better LUT counts than it does for block _CorePF_ of the equivalent FSM \(P_{T}Y\). The same is true for block _LUTerASV_ of the equivalent FSMs \(P_{T}Y\) and \(P_{2T}Y\). Therefore, we could expect that a circuit of \(P_{2T}Y\) FSM (Figure 5) requires a smaller area and is not slower compared to a circuit of equivalent \(P_{T}Y\) FSM (Figure 3). These assumptions of ours have been confirmed by the conducted studies, the results of which are given in Section 6. Let us show the features of our method in comparison with the methods proposed in [20; 22]. In the article [20], we discussed \(P_{T}Y\) FSMs with two-fold state assignment and encoding of output collections. The \(P_{2T}Y\) FSMs have the following differences. First, in \(P_{T}Y\) FSMs, the codes of all states are converted, while in \(P_{2T}Y\) FSMs, only a part of the code is converted. This allows for optimizing the code converter circuit (compared to the circuit used in equivalent \(P_{T}Y\) FSMs). Secondly, the use of two cores allows us to encode OCs such that some variables \(a_{r}\in AV\) are generated only by the LUTs of _CoreFC_. This allows for reducing the number of LUTs generating output signals (compared to this number for equivalent \(P_{T}Y\) FSMs). In the article [22], we discussed so-called \(P_{2}C\) FSMs, where two cores of LUTs are used. However, \(P_{2}C\) FSMs are based on one-hot encoding of outputs. In \(P_{2T}Y\) FSMs, we use maximum binary codes of output collections. This allows for reducing the number of LUTs generating output signals (compared to this number for equivalent \(P_{2}C\) FSMs). In this paper, we propose a synthesis method aimed at LUT-based \(P_{2T}Y\) Mealy FSMs. The synthesis process starts from the FSM state transition graphs [17]. Next, these graphs are transformed into equivalent state transition tables (STTs) [17]. The sequence of steps of the proposed method is the following:  
1. Creating an STT of \(P\) Mealy FSM. 2. Pre-formation of sets \(S^{0}\) and \(S1\). 3. Pre-formation of partition \(\pi_{\text{S2}}\) of set \(S1\). 4. Final formation of sets \(S^{0}\) and \(S1\) and partition \(\pi_{\text{S2}}\). 5. Creating full state codes \(FC(s_{m})\). 6. Encoding of output collections \(O_{q}\subseteq O\) and finding SBF (7). 7. Creating a table of _CoreFC_ and deriving SBFs (19)-(21). 8. Encoding of states \(s_{m}\in S^{j}\) by partial state codes \(PC(s_{m})\). 9. Generating tables describing the blocks of _CorePC_ and deriving systems (22) and (23). 10. Creating a table of _LUTerFA_ and SBFs (24) and (25). 11. Creating a table of _LUTerASV_ and systems (26). 12. Creating the \(P_{2T}Y\) Mealy FSM circuit. To show that the model of \(P_{2T}Y\) FSM is used to synthesize FSM \(A\), we use the symbol \(P_{2T}Y(A)\). Let us explain how to execute the steps of the proposed design method.