# Improving Hardware in LUT-Based Mealy FSMs
## 7 Conclusions  
Nowadays, the majority of digital systems are implemented using FPGAs. So, FPGAs are used for implementing circuits of FSMs representing various sequential blocks. As the complexity of the FSMs (the numbers of inputs, outputs and states) increases, the contradiction between this significant complexity and a very small number of LUT inputs increases, too. Modern LUTs have around six inputs. This value is still rather small compared with numbers of literals in SBFs representing FSM circuits. This leads to using various methods of functional decomposition in the LUT-based FSM design. It is known [39] that the functional decomposition leads to multi-level LUT-based FSM circuits having spaghetti-type interconnections.  
In many cases, the characteristics of FPGA-based FSM circuits can be improved due to applying the methods of structural decomposition instead of using the methods of functional decomposition [13]. Our research [15] shows that three-block circuits of LUT-based Mealy FSM circuits require fewer LUTs than some of their counterparts. But this gain is connected with the introduction of some additional functions. This requires using additional chip internal resources to generate these functions. This is the main disadvantage of the three-block FSM circuits.  
In this article, we propose to use the codes of collections of outputs to represent both the outputs and state variables of Mealy FSMs. This is connected with using two registers keeping codes of COs. Using this approach, it is possible to generate in parallel FSM outputs and codes of the transition states. This leads to Mealy FSM circuits having two levels of LUTs. These circuits require fewer LUTs than it is in the equivalent three-block FSM circuits. The experiments prove that the proposed approach allows reducing hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs.  
Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without a significant reduction in the performance. The gain in LUT counts and area-time products increases with the increase in the numbers of FSM states and inputs. Our approach loses in terms of power consumption (on average 9.62%) and power-time products (on average 10.44%). As the experiments show, the proposed two-block FSMs have practically the same cycle times (maximum operating frequencies) as their three-block counterparts. This analysis allows us to conclude that the proposed method can be used for improving the LUT counts of various FPGA-based sequential devices.  
Conceptualization, A.B., L.T. and K.K.; methodology, A.B., L.T. and K.K.; formal analysis, A.B., L.T. and K.K.; writing--original draft preparation, A.B., L.T. and K.K.; supervision, A.B. All authors have read and agreed to the published version of the manuscript.  
**Funding:** This research received no external funding.  
**Institutional Review Board Statement:** Not applicable.  
\begin{table}
\begin{tabular}{l c c c c c c} \hline \hline
**Methods** & **Auto** & **One-Hot** & **JEDI** & \(\mathbf{U_{2}}\) & **Our Approach** & **Gain, \%** \\ \hline LUT counts & 1808 & 2104 & 1489 & 1323 & **1234** & +7.21 \\ \hline Maximum operating frequency, MHz & 8127.08 & 8061.22 & **8701.97** & 8536.27 & 8658.86 & +1.42 \\ \hline Number of FFs without output register & **251** & 2011 & **251** & **251** & 414 & \(-\)39.37 \\ \hline Number of FFs with output register & 584 & 2344 & 584 & 584 & **414** & +41.06 \\ \hline Power, Watts & 76.788 & 83.136 & 64.747 & **55.070** & 60.930 & \(-\)9.62 \\ \hline Area–time products & 12,228.61 & 14,168.64 & 8859.93 & 7540.03 & **7035.28** & +7.17 \\ \hline Power–time products, n] & 484.24 & 528.25 & 365.05 & **301.91** & 337.11 & \(-\)10.46 \\ \hline \hline \end{tabular}
\end{table}
Table 21: Final comparative table.