## 2 Circuit Description
### Proposed 0.45 V CDTA
It should be noted that the input resistances \(r_{p}\) and \(r_{n}\) of this CDTA structure are equal, since CCII\(-\) and CCII\(+\) are identical. The input-referred thermal noise of the differential amplifier is used to determine the input noise of the proposed CDTA, which can be expressed by  
\[\overline{v}_{n}^{2}\cong 2\frac{8 kT}{3\overline{s}_{mb1}^{2}}(g_{m1,2}+g_{m4,5}) \tag{7}\]  
\(k\) is the Boltzmann constant (\(\sim\)1.38 \(\times\) 10\({}^{-23}\) J/K), and \(T\) is the absolute temperature. The TA of the CDTA is composed of a bulk-driven (BD) linearized differential pair and current mirrors. To achieve high output resistance and, consequently, improve the DC voltage gain, self-cascode current mirrors are utilized. The linearity of the input pair is enhanced through the use of BD transistors M\({}_{3}\) and M\({}_{4}\), which operate in the triode region [38]. The biasing current, \(I_{set}\), is employed to adjust the transconductance \(g_{m}\). Assuming unity-gain current mirrors, the DC transfer characteristic of the TA in the subthreshold region is given by  
\[I_{x}=2I_{set}tanh\left(\eta\frac{V_{z}}{2n_{p}U_{T}}-tanh^{-1}\left[\frac{1} {4m+1}tanh\left(\eta\frac{V_{z}}{2n_{p}U_{T}}\right)\right]\right) \tag{8}\]  
where \(\eta=g_{mb}/g_{m}\) is the bulk-to-gate transconductance ratio, \(n_{p}\) is the subthreshold slope factor, \(U_{T}\) is the thermal potential, and \(m=(\mathrm{W}/\mathrm{L}_{3,4})/(\mathrm{W}/\mathrm{L}_{1,2})\) should be equal to 0.5 for optimal linearity in the weak inversion region [38]. The small-signal transconductance of the OTA is expressed as follows:  
Figure 3:0  
The DC voltage gain is  
Figure 3:1Thus, the voltage gain is increased by employing self-cascode connections, which enhance the output resistance of the TA stage. The circuit was designed as follows. The bias currents in the whole structure determine its power dissipation and should be chosen as low as possible. However, their minimum values in the input stage of the CCII are limited by thermal noise, which is a dominant source of noise in the proposed design. Taking into account (7), Ig was set to 50 nA, which provides the required level of noise. The biasing currents in all other branches were also set to I\({}_{\text{B}}\), which entailed \(g_{mg}/g_{ml}\)= 1 and unity-gain current mirrors in the structure. This resulted in \(g_{mg}/g_{mb1}\) equal to about 3 at the operating point, which resulted in a moderate Miller compensation capacitor Cc. The W/L ratios of the transistors in the input stage were chosen to obtain V\({}_{\text{DS}}\) = (V\({}_{\text{DD}}\) - V\({}_{\text{SS}}\))/3 for each transistor in this stage at the operating point for the assumed biasing currents. For V\({}_{\text{DD}}\) = 0.45 V, this means that V\({}_{\text{SG3}}\) = 0.3 V and V\({}_{\text{GS1,2}}\) = 0.3 V if the gate terminals of M\({}_{1}\) and M\({}_{2}\) are connected to the lowest potential, which is advantageous to decrease the bulk currents and W/L ratios of the input transistors. For the diode-connected p- and n-channel transistors in the current mirrors, 1V\({}_{\text{GS}}\)! were chosen to be equal to about mid supply. Such a choice gives a maximum voltage headroom for possible PVT variations and signal swing. The biasing currents for the transconductance amplifier were chosen to obtain the required value of its transconductance (see (9)). The coefficient \(m=(\text{W/L}_{3,4})/(\text{W/L}_{1,2})\) was chosen to be equal to 0.5 for optimal linearity. As previously, in the input stage the voltage drops across the main elements (biasing sources M\({}_{12,12c}\) and M\({}_{13,13c}\) and cascode current mirrors M\({}_{6,6c}\) and M\({}_{7,7c}\)), and the V\({}_{\text{DS}}\) of the input transistors M\({}_{1}\) and M\({}_{2}\) were equal to around (V\({}_{\text{DD}}\) - V\({}_{\text{SS}}\))/3 for nominal biasing currents to maximize voltage headroom for possible PVT variation, transconductance tuning, and signal swing.