# Nanofabrication Techniques in Large-Area Molecular Electronic Devices
## 1 Introduction  
The impact of the omnipresent Complementary Metal-Oxide Semiconductor (CMOS) electronic industry on the global economy is enormous, due to its role not only in the production of computers, mobiles, tablets, etc., but mainly as an essential component in products from many other industries (automobile, aeronautics, artificial satellites, trains, security and armies, communication systems, computer science, robotics, energy, financial services, diagnostic equipment in hospitals, booster of the research, development, and innovation, etc.). Thus, the global market for electronic components is expected to grow in the 2020-2025 period at a compound annual growth rate of ca. 4.8% [1]. The new scenario imposed by the COVID-19 pandemic has further evidenced the relevance of the electronic industry in our society. Could the reader imagine how the months of confinement would have been like without the internet, teleconferencing, online teaching, streaming videos, online shopping, etc.? If we look back over the historical development of the electronic industry, the last four decades have witnessed enormous and rapid progress in the miniaturization of electronic devices (Moore law) from 3 \(\upmu\)m transistors in 1980 to the current 7 nm technology already in the market, using the fiffet (rin Field-effect transistor) technology, with microprocessors that incorporate more than 50 billion transistors and pursuing the 5 nm transistor in 2020. This miniaturization is accompanied by a reduction in the global size and weight of electronic components, an increase in switching performance andfaster processors, an increase in logic area efficiency, as well as a decrease in the energy consumption and consequently longer battery life. It is expected that if the surface area of a transistor decreases by two every two years (reduction of the lateral size by 1.4), the 3 nm technology could appear in 2022 (the mit has created a 2.5 nm transistor [2]), and by 2024, 1 nm transistors might emerge. There are, however, a number of associated technological problems within this miniaturization race that will need to be overcome for these predictions to be reached. In devices thinned to a few nanometers, quantum effects governing the electron behavior appear, which can make transistors unreliable, due to the quantum uncertainties [3]. The reduction in the size of transistors is also associated with a dramatic increase in the fabrication process costs (second Moore law) which has resulted in a drastic decrease of foundries (from 20 foundries for 130 nm technology to only four major companies providing transistors in the 10 to 7 nm range), which is ultimately reflected in the cost of electronic devices in the market and could make future nodes unaffordable, due to the manufacturing costs for ultra-large-scale implementation [4]. Additionally, when an increasing number of transistors are ensemble into a small area of a single piece of an integrated circuit, inelastic scattering of electrons [5] results in waste-heat that emerges as an additional problem as chips get too hot, which requires efficient heat dissipation systems [3]. The technological and economic limits of the current cmos technology are therefore imminent, and scientists all over the world are working on alternative technologies, due to the continual and growing social demand for more efficient, more rapid, more versatile, and low-power devices, not to mention flexible electronics. In 2016, the eighteen years old tts[6] (International Technology Roadmap for Semiconductors) was renamed as irds[7] (International Roadmap for Devices and Systems), which is a clear reflection of the need of alternative technologies in the XXI century.