# Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL
## 2 FPGAs and the HARP Platform
### The HARP Platform  
The HARP is a CPU-FPGA platform that is developed by Intel to spur research in CPU-FPGA heterogeneous computing platforms. In a first stage, in 2015, an Intel Xeon CPU was combined with an Altera Stratix V FPGA in a discrete configurable platform (DCP). These two chips were connected using a single Intel QuickPath Interconnect (QPI) channel, and shared DRAM memory. For clarity, this first-generation HARP platform will be referred to as HARPv1. In a later stage, in 2017, the second generation of HARP was introduced, here mentioned as HARPv2. HARPv2 consists of a 14 core Intel Broadwell Xeon CPU combined with an Intel Arria 10 GX1150 FPGA [8]. In HARPv2, the CPU and FPGA also share DRAM memory, but they are connected through one QPI channel and two Peripheral Component Interconnect Express (PCIe) channels. Instead of a discrete configuration of 2 separate chips, as in HARPv1, HARPv2 combines both chips in a Multi-Chip Package (MCP) [5]. Besides the single DDR memory, the FPGA has a coherent cache and physical to virtual memory address translation Intellectual Property (IP) core.  
The CPU and the FPGA in the HARPv2 platform are connected through three physical channels: one QuickPath Interconnect (QPI) channel and two Peripheral Component Interconnect Express (PCIe) channels. QPI is an interconnect technology, developed by Intel, that connects processors in a distributed shared memory style [9]. PCIe, on the other hand, is a general purpose I/O interconnect defined for a wide variety of computer and communication platforms. The HARPv2 uses a PCIe Gen3x8 interconnect. This indicates that the PCIe connection uses the third generation PCIe technology, and has a bit width of 8 bits.  
The QPI channel has 16 data connections, and therefore a bit width of 2 B. Its maximum transfer rate is 6.4 GT/s. This results in a maximum, one-way bandwidth of 12.8 GB/s [9]. Similar calculations can be done for the PCIe channels. The used PCIe connection is of third generation, and has a bit width of 8 bits. However, compared to the QPI channel, the PCIe uses a less efficient data encoding scheme, which results in a physical channel with an efficiency of 98.5%. Therefore, for every 130 bits sent, only 128 bits are useful. The maximum amount of transfers per second equals 8 GT/s. This results in a maximum raw bandwidth of 98.5% \(\times\) 1 byte \(\times\) 8 GT/s = 7.88 GB/s.These characteristics are shown in Table 1. The theoretical maximum unidirectional bandwidth of both QPI and 2 PCIe connections combined is 28.56 GB/s. The effective measured bandwidths are 17.02 GB/s for separate reads or writes of 64 byte lines. A combined read/write benchmark such as memcopy yields 26.7 GB/s, i.e., 13.35 GB/s for reads and writes, respectively.  
Based on previous calculations, one could conclude that the HARP platform can obtain read- and write-bandwidths up to 28.56 GB/s. Above results are, however, theoretical bandwidths and they do not account for packet overhead and other effects. Therefore, the maximum bandwidth that can be achieved will be lower, and can also vary for different types of data transfers.  
An FPGA is configured by an FPGA bitstream. In the HARPv2 platform, the FPGA bitstream consists of two parts: the FPGA Interface Unit (FIU) and the Accelerator Functional Unit (AFU). The FIU contains Intel-provided IP. It implements I/O control, power and temperature monitoring and partial reconfiguration, and it provides one or more interfaces to the AFU. The AFU, on the other hand, consists of programmer-defined FPGA code and determines the functionality of the FPGA. The architecture of the FIU and the AFU, and their internal structure is shown in Figure 1.  
\begin{table}
\begin{tabular}{c c c} \hline \hline  & **QPI** & **PCIe Gen.3\(\times\)8** \\ \hline width & 16 bits & 8 bits \\ max \#transfers per second & 6.4 GT/s & 8 GT/s \\ maximum raw unidirectional bandwidth & 12.8 GB/s & 7.88 GB/s \\ \hline \hline \end{tabular}
\end{table}
Table 1: QPI and PCIe characteristics.