# An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios
## 4 Results and Discussion  
The proposed architecture was evaluated in terms of performance, resource utilization, power consumption, and reconfiguration latency. The results are further discussed within the context of the considered application domain. The functional correctness of all modulators was verified by checking the simulation results against the values produced by MATLAB scripts [40; 41]. The periodograms in Figure 4 were obtained from I/Q samples produced by the implemented modulators operating in Mode 1. Table 2 presents values for the latency--amount of clock cycles to produce the first output sample--for each of the six modulator variants supported. Higher latencies were observed for FBMC, mainly because of the larger IFFT sizes and the time overhead associated with the overlap-and-add operation after the IFFT module. In turn, UFMC showed smaller latencies due to the parallel processing of each sub-band, as well as the smaller IFFT sizes employed. These results are in line with the observations made in [42]: UFMC was more suitable for short packet and low latency transmissions, while FBMC was more efficient for long sequence transmissions. The sub-band parallel processing approach in our design made the UFMC datapath latency independent of the number of sub-bands. Therefore, the latency per sub-band was also 421 clock cycles, which is lower than the 516 clock cycles recorded by [PERSON] et al. [28]. In steady-state operation and after the initial latency, all the modulators produced one sample per clock cycle. Therefore, their processing throughput was dictated by the clock frequency used for baseband processing. Table 3 provides a general overview of the resource utilization for the static and reconfigurable parts of the system. The static part comprised modules for DFS and DPR implementation, DMA access, and communication between the PL and PS sections. This represents less than 32% and 5% of the available slices and block RAMs (BRAMs), respectively. On the other hand, the aggregate amount of \begin{table}
\begin{tabular}{l c c c c c c} \hline \hline \multirow{2}{*}{**Modulator**} & \multicolumn{3}{c}{**Mode 1**} & \multicolumn{3}{c}{**Mode 2**} \\ \cline{2-7}  & **OFDM** & **FBMC** & **UFMC** & **OFDM** & **FBMC** & **UFMC** \\ \hline Latency & 2356 & 7743 & 421 & 5172 & 17,469 & 421 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Processing latency (in clock cycles). reserved resources for the three RPs accounted for 52.6% of slices, 64.3% of BRAMs, and 72.7% DSP blocks. The exploitation of reconfigurable techniques such as DFS and DPR had an associated resource overhead that is quantified in Table 4. The combined DPR and DFS resource overhead was very small: less than 4% of the slices and around 1% of the BRAMs available in the xc7z020. To better understand how the RP resources were actually used, Table 5(a) exhibits the resource utilization per modulator variant. The UFMC modes registered a higher slice and DPS utilization compared to OFDM and FBMC. Most of the slices used in the UFMC modulator implemented the multiplier-less FIR filters. Recalling the DSP block utilization analysis from Section 3.1, the 18 DSP blocks came from the six blocks used in each sub-band branch. The higher BRAM utilization in FBMC modulators was mainly caused by the overlap-and-add of \(K\) consecutive symbols. Table 5(b) shows resource utilization for baseband modulators in [19; 28]. The operation of the modulators from [19] was defined by setting parameter values, which means that the modules had to be dimensioned for the most resource-demanding mode of operation. For both OFDM and FBMC, the most demanding mode of operation was equivalent to Mode 1 from Table 1. The authors also claimed a maximum clock frequency of 200 MHz for their designs, but only reported post-synthesis results. Additionally, they used LUT RAMs instead of the BRAMs available on the xc7z020 to implement memory elements. Thus, it is hard to do a fair LUT utilization comparison with our work.