###### Abstract  
Polar codes are the first family of error-correcting codes that can achieve channel capacity. Among the known decoding algorithms, Successive-Cancellation List (SCL) decoding supported by a Cyclic Redundancy Check (CRC) shows the best error-correction performance at the cost of a high decoding complexity. The decoding of Rate-1 nodes belongs to the most complex tasks in SCL decoding. In this paper, we present a new algorithm that largely reduces the number of considered candidates in a Rate-1 node and generate all required candidates in parallel. For this purpose, we use a partial order of the candidate paths to prove that only a specified number of candidates needs to be considered. Further complexity reductions are achieved by an extended threshold-based path exclusion scheme at the cost of negligible error-correction performance loss. We present detailed Application-Specific Integrated Circuit (ASIC) implementation data on a 28 nm Fully Depleted Silicon on Insulator (FD-SOI) Complementary Metal-Oxide-Semiconductor (CMOS) technology for decoders with code length 128. We show that the new decoders outperform state-of-the-art reference decoders. For list size 8, improvements of up to 158.8% and 62.5% in area and energy efficiency are observed, respectively. p 2022 11 / 560[[https://doi.org/10.3390/electronics11040560](https://doi.org/10.3390/electronics11040560)]([https://doi.org/10.3390/electronics11040560](https://doi.org/10.3390/electronics11040560)) 10.3390/electronics11040560 10.  
drawback of SCL decoding is a high computational complexity caused by the usage of \(L\) parallel SC decoders and sorting. The reduction of the number of path splittings is one approach to reduce the computational complexity of SCL decoding. In [7], a condition for path splitting in conventional SCL decoding was presented along with an additional path pruning scheme to further reduce the average number of decoding paths. In [8], an auxiliary path metric was introduced for a set of unreliable information bits in CRC aided SCL (CA-SCL) decoding to determine whether a path split leads to an erroneous path. Together with a threshold, these metrics are used to judge whether path splitting is necessary or not. In [9], an additional path contraction mechanism further reduces the number of paths. Although Refs. [7; 8; 9] reduce the computational complexity of SCL decoders in terms of the number of path splittings, they do not exploit the potential of low latency and complexity reduction by tree pruning as in Fast-SSC decoding. In Fast Simplified SCL (Fast-SSC) decoding, the Fast-SSC decoding algorithm was adapted for the use in SCL decoding [10; 11]. The key enabler for Fast-SSCL decoding according to [11] is the use of the information about the order of the input paths and the order of bit estimations in Rate-1 nodes. A parallel decoding approach for Rate-1 nodes was introduced in [12] to enable high-throughput hardware implementations of Fast-SSCL decoders. However, due to numerous candidate paths for increasing list sizes, the maximum node size of Rate-1 nodes was restricted. The authors of [13] present a node reliability-based path expansion scheme using precomputed flipping patterns. While the node reliability results from code construction, the determination of these patterns remains open. The approach of an adaptive candidate selection method based on the reliability of the input paths was presented in [14]. However, they only presented an example for a Rate-1 node in Simplified SCL (SSCL) decoding with list size \(L=8\), while a formal presentation of an algorithm is missing. An advanced parallel decoding algorithm for Rate-1 nodes in Fast-SSCL decoders was presented in [15]. Based on a Minimum-Combinations (MC) set relative to the list size, redundant path splittings are eliminated, and a significant latency reduction is achieved.