# Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications
## 4 Comparison of the Designed Antenna vs. the State-of-the-Art  
This section compares the achieved performance vs. known works published in recent literature, e.g., Ref. [31, 37, 40, 67, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94]. Specifically, Table 2 compares the proposed design to [31, 37, 40, 67, 79, 83] in terms of area, gain, HPBW and bandwidth. With respect to antennas in the sub-10 GHz domain [40, 69], the area occupation of the antenna design in Section 3 is limited to about 0.6 mm\({}^{2}\). This size is compliant with integration on a single-chip. On the contrary, the size of the antennas proposed in Ref. [40, 69] is orders of magnitude higher than the on-chip bow-tie antenna in this work. Indeed, in Ref. [40], the authors present a 3 cm\({}^{2}\) dipole antenna, operating at 10 GHz, with a 2.8 dBi gain and a HPBW of 85 degrees at 10 GHz. Still at 10 GHz, in Ref. [40], the authors also present a 3.75 cm\({}^{2}\) Vivaldi antenna with a gain of 5.8 dBi and a HPBW of 65 degrees. With respect to other on-chip antennas, operating at around 60 GHz, and proposed in literature, the antenna design in Section 3 offers a better trade-off between size, gain, bandwidth and HPBW. For example, the zig-zag antenna adopted for WiNoC in [31] has been designed with a trace width of 10 \(\upmu\)m, with an arm length of 60 \(\upmu\)m and a bend angle of 30 degrees. The axial length of the zig-zag antenna is 0.38 mm. The substrate is represented by a 2 \(\upmu\)m thick SiO\({}_{2}\) layer, with a relative dielectric permittivity constant \(\varepsilon\)r of 3.9. The substrate is a high-resistivity silicon substrate with a thickness of 633 \(\upmu\)m and electrical parameters of \(\rho\) = 5 k\(\Omega\cdot\)cm and \(\varepsilon\)r = 11.7. The same antenna has also been adopted in [37]. The zig-zag antenna has a lower size, 60 \(\upmu\)m \(\times\) 380 \(\upmu\)m, than the proposed \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Antenna** & **Area, mm\({}^{2}\)** & **Feed/Match Circuit** & **Gain, dB** & **HPBWxy** & **Bandwidth** \\ \hline This work & 0.512 & Included & \(-7.3\) @ 60 GHz & 110\({}^{\circ}\) & 51 to 100 GHz \\ [31, 37] & 0.023 & Not included & \(-26.5\) @ 60 GHz & 60\({}^{\circ}\) & 51 to 66 GHz \\ [40], Dipole & 375 & Included & 5.8 @ 10 GHz & 65\({}^{\circ}\) & 8 to 11 GHz \\ [40], Vivaldi & 300 & Included & 2.8 @ 10 GHz & 85\({}^{\circ}\) & 9 to 11 GHz \\ [67] & 156 & Included & 5 @ 60 GHz & 184\({}^{\circ}\) & 57 to 64 GHz \\ [79] & 2 & Included & \(-30\) @ 3 GHz & N/A & N/A \\ [83] & 1.4 & Not included & \(-38.65\) @ 60 GHz & 33\({}^{\circ}\) & 6 GHz \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Comparison to the state-of-the-art. Figure 5: Radiation pattern and antenna gain at 50 GHz, 60 GHz, 100 GHz. bow-tie antenna, although the reported area for the zig-zag antenna does not consider the feeding and impedance matching network. The maximum gain of the zig-zag antenna is only \(-26.8\) dBi at 60 GHz: i.e., the gain is about 19 dB lower than the antenna design proposed in this work. The connection distance using the zig-zag antenna is limited to 2 cm in [31]. For example, in a complex MPSoC design with a size L of some centimeters per side, e.g., the INTEL48 core in [95] with L about 2.5 cm, the tiles that are placed in the layout at opposite parts of the MPSoC can have a distance (along the diagonal of the chip) up to 3.5 cm. Moreover, the return loss for the zig-zag antenna is below \(-10\) dB only in the spectrum range from 51 GHz to 66 GHz. Instead, the proposed bow-tie antenna has an upper bound limit of 100 GHz. In terms of HPBW, along the X-Y plane of interest, the zig-zag antenna has a value of about 60 degrees, almost halved vs. the 110 degrees of the proposed design, see Figure 3.  
The half-wave dipole and the double-slot antennas proposed in 65 nm SOI technologies in Ref. [59], having a comparable size to the bow-tie design, reach a positive gain of a few dBi, but use a PEC (Perfect Electric Conductor) plane under the chip.