# Hardware Design for Cascade-Structure, Dual-Stage, Current-Limiting, Solid-State DC Circuit Breaker
## 5 Simulation and Experimental Results
### Simulation Verification  
MATLAB/SIMULINK simulation validation for the topology shown in Figure 1a is performed with the following parameter design: system voltage: 30 V; load resistance: 30 \(\Omega\); \(L_{s1}=L_{s2}=2\) mH; \(R_{1}=10\)\(\Omega\); \(R_{0}=1\)\(\Omega\); \(C_{s}=1\)\(\mu\)F; \(R_{s}=2\) k\(\Omega\). The simulation results are as follows:  
Figure 10: (**a**) Experimental platforms; (**b**) experimental prototype.  
Figure 9: (**a**) Circuit diagram of the MOSFET drive circuit; (**b**) equivalent circuit diagram of the MOSFET gate-source voltage.  
Shown in Figure 11a are the simulation waveforms for each branch during the fault interruption process of the hardware topology circuit breaker. It can be observed that at system startup, the steady-state branch and the power electronics branch are in the conduction and turn-off states, respectively. The system's rated current gradually rises and stabilizes due to the current-limiting inductor. At time \(t_{0}\), a load short-circuit fault occurs on the right side of the circuit breaker. The steady-state branch current \(i_{s}\) begins to increase under the suppression of the auxiliary current-limiting branch until time \(t_{1}\), when the steady-state branch current reaches the turn-off threshold, and the branch is turned off while the power electronic branch is conducted. Current then rushes into the power electronics branch and continues to rise as shown in the figure at \(i_{z}\). By time \(t_{2}\), the current in the power electronics branch rises to the carrying threshold, which turns off the power electronics branch, and the current is transferred to the buffer circuit's capacitor. The buffer capacitor charges rapidly as shown in the figure at \(i_{c}\), and its voltage rises to the varistor MOV activation voltage at time \(t_{3}\). The varistor quickly dissipates the residual energy of the circuit breaker and successfully isolates the fault by time \(t_{4}\) as shown in the figure at \(i_{mov}\). Figure 11b shows the overall trend of the short-circuit current \(i_{dc}\). It is evident that when the current flowing through the buffer capacitor drops to zero, the surge protector clamps the induced overvoltage from inductive components in the system to 68 V, effectively protecting the system and the internal semiconductor devices of the circuit breaker from overvoltage impacts.  
After a certain period following fault isolation, the circuit breaker will perform a reclosing operation based on the type of short-circuit, as shown in Figure 12a. After fault isolation, reclosing occurs after 2.5 ms. At this point, the load fault has been cleared. During reclosing, the power electronics branch is initially conducted, allowing the current to establish and rise within this branch. After a 200 us delay for fault determination, if the current \(i_{z}\) in the power electronics branch is less than or equal to the system's rated current, the steady-state branch is then conducted, and the power electronics branch is turned off, transferring the system's rated current to the steady-state branch and restoring the system to its normal operating state. Conversely, as shown in Figure 12b, if after the 200 us delay, the current \(i_{z}\) in the power electronics branch is much higher than the system's rated current, then the power electronics branch is quickly turned off to prevent further damage. The residual energy is dissipated through the varistor and the energy dissipation branch, maintaining the system in a disconnected state.  
Figure 11: (**a**) Simulation waveforms of branch currents; (**b**) interrupting overvoltage waveform.