## 3 Algorithms for Microcontroller
The timing can be adjusted depending on the particular IGBT type and is currently set to 20 us. If the gate monitoring timer reaches the end of the transient period, substate #2 of the finite-state machine is changed into substate #3 of the \"on\" state, as shown in Figures 3 and 4. The validation of the gate voltage is carried out by substate #3's algorithm. The gate voltage is converted by the ADC and validated by the finite-state machine approximately every 3 us in the infinite loop of the finite-state machine. If the gate voltage exceeds the acceptable values, the control signal is blocked, and a feedback pulse with a duration of 1 us is produced (see Figure 2c). Figure 4: Timing diagrams of algorithm implementation in the microcontroller (blue—control command; red—feedback signal). If the transistor is switched off, monitoring of the gate voltage is also performed. Similar to the case with the switched-on transistor, the voltage verification by analog circuit #4 (Figure 1) starts with the gate monitoring timer. The changing of initial substate #1 into substate #2 in the \"off\" state occurs as shown in Figures 3 and 4, and monitoring the gate voltage is enabled. If the acceptable value is exceeded, the feedback signal is held up until the voltage is established within acceptable limits, as in the case of monitoring the +15 V power supply. Measuring the gate voltage in the switched-off state of the IGBT is equivalent to monitoring the -9 V power supply on the driver board. At the end of each cycle of the finite-state machine, the condition of the transistor's switching should be checked. The switching process can lead to an incorrect estimation of the electrical parameters of the gate or collector voltage. If commutation occurs while the finite-state machine is running, the evaluation result of this cycle is considered to be incorrect. One cycle of an infinite loop takes approximately 3 \(\upmu\)s. The timeline of interrupts and the states of the finite-state machine are shown in Figure 4.  
The algorithm for the generation of the feedback pulses is based on the utilization of the PWM module of the microcontroller. Timing diagrams of the PWM module's operation are shown in Figure 5. This peripheral device provides a quick response to the edge of the control signal and determines pulses of the required duration. If the edge of the control signal appears, an internal synchronization signal is generated after a delay. This delay is associated with the filtering of the input discrete signal by the microcontroller. This synchronization signal forces the PWM module to reset the timer counter and load values from the shadow counter-compare (CMP) register to the active CMP register. If the timer counter is less than the CMP value, then the feedback signal is in a low state; otherwise, the feedback is in a high state within the time interval from \(t_{2}\) to \(t_{4}\), equal to 700 ns. At the instance of time \(t_{1}\), the synchronization signal appears, and the value equal to \"DELAY\" stored in the shadow register is loaded into the active CMP register. The CMP value \"DELAY\" corresponds to the time necessary to provide a delay in the feedback pulse equal to 250 ns. The XINT interrupt occurs at the instance of time \(t_{3}\) and is triggered by the edge of the control signal. The algorithm of this interrupt function changes the condition of the loading values from the shadow CMP register to the active CMP register. The \"PRD\" value, which is equal to the period value of the counter, is loaded into the shadow register CMP. Thus, the new loading of the CMP occurs at time \(t_{4}\) when the PWM counter reaches the value \"PRD\". At this moment, the feedback signal state changes from a high to a low state because the CMP value becomes unattainable for the timer counter. At the end of the XINT interrupt, at time \(t_{5}\), the CMP shadow register is loaded with the value \"DELAY\", and the loading from the shadow CMP register to the active CMP register is configured by the synchronization signal again.