# XOR Multiplexing Technique for Nanocomputers
## 1 Introduction  
System reliability has always been an issue of widespread concern, and reliable systems have been widely required by various applications [1; 2; 3; 4; 5; 6; 7; 8]. If the reliability of the system is not guaranteed, it will most likely cause serious consequences and even threaten human life. However, with silicon technology scaling, the reliability of nano-components is generally not very good. Hence, how to build reliable systems out of unreliable components is an inevitable problem. In order to solve this problem, scholars have investigated several redundant fault-tolerant techniques, such as N-tuple modular redundancy (e.g., triple modular redundancy) [9; 10] and reconfiguration [11; 12; 13]. However, these techniques do not yield high fault tolerance for nanocomputers due to the extreme high devices' density and the high percentage of faulty components. Since faulty components are the building blocks of the [PERSON]'s multiplexing technique, faulty components are an integral part of the system. As a result, [PERSON]'s multiplexing technique has received attention again [14]. A wealth of papers that reported the performance analysis of multiplexing technique have been published and, among them, the most attention was paid to NAND multiplexing [15; 16; 17; 18] and majority multiplexing [19; 20; 21], first proposed by [PERSON]. The multiplexing technique has been studied as an effective fault-tolerant technique for protection against the increasing transient faults in nanoelectronic circuits [22; 23; 24; 25]. Hence, in addition to the two multiplexing techniques, scholars paid attention to other types of multiplexing technique, e.g., NOR-2 multiplexing [26].  
None of those multiplexing schemes mentioned how to realize the function of XOR or XNOR. In fact, they are unable to achieve it. As a universal logic gate, XOR and XNOR are widely used inintegrated circuits, therefore it is necessary to study XOR multiplexing or XNOR multiplexing. In this paper, we present the XOR multiplexing technique for nanocomputers. This will make the research of multiplexing technique more comprehensive. The newly designed architecture is composed of XOR gates and NAND gates, where the XOR gates constitute the executive unit and the NAND gates constitute the restoring organs. The executive unit performs the desired logic function and the restoring organs perform the error correction function. First, we analyzed the error distributions in the XOR multiplexing unit and compared it with [PERSON]'s NAND multiplexing unit. Then, the error distributions of the multiple stages system and the comparison are presented. Last, we analyzed the system performance of the architecture, i.e., its fault-tolerant ability. The system performance of the architecture is evaluated by studying its fault-tolerant ability, which can be defined by the gate error threshold and the input signal error threshold, where the gate error threshold is the maximum gate error probability in which the system can still work properly, and the input signal error threshold is the maximum input signal error probability that the system can tolerate. The experiment's results show that the XOR multiplexing unit is more reliable than the NAND multiplexing unit and this technique has a high fault-tolerant ability and a unique feature; we name this as the critical point property, which can indicate the fault tolerant ability of the system.  
The rest of paper is arranged as follows. In Section 2, we present the error distributions in the XOR executive unit and the XOR multiple stages multiplexing system, then compare them to the NAND executive unit and the NAND multiple stages multiplexing system. In Section 3, we discuss the bifurcation analysis, which is followed by Section 4: the fault-tolerant ability analysis of the XOR multiplexing system. Section 5 concludes the paper.