## 2 Design of Dual-Band Matching Networks
### Implementation of Dual-Band Output Matching Network  
Now, we can take the next step to implement the dual-band output matching network according to the proposed methodology. The simulated power and PAE contours for 2.4 and 5.5 GHz are shown in Figure 2. In general, the pursuit is not singularly focused on either efficiency or output power; instead, a tradeoff between output power and PAE is normally made. In this design, the optimal load impedances are determined as 15.05 + \(j15.08\) at 2.45 G and 9.87 + \(j15.86\) and 5.5 G, respectively. The corresponding \(R_{opt}\) and \(C_{out}\) are 30.17 \(\Omega\) and 2.16 pF at 2.4 GHz and are 35.36 \(\Omega\) and 1.32 pF at 5.5 GHz. Therefore, the calculated values of the \(\left|\Gamma_{\text{\emph{ins}}}\right|\) and _IL_ are plotted in Figures 3 and 4. Thus, we now have the optimum values of \(L_{p}\), \(L_{s}\), and \(C_{\text{sites}}\). Figure 2: Simulated power contours and PAE contours in 2.4 and 5 GHz bands. (**a**) 2.4 GHz. (**b**) 5.5 GHz. We then take the next step to implement the output matching network with optimum values. In this design, the used CMOS process only has one thick metal layer. Consequently, all inductor coils are designed using the thickest metal layer with an octagonal shape to enhance the \(Q\) value of the inductors. To further improve the quality factor of the transformer, this design integrates a patterned ground shielding (PGS), constructed from poly layers, into the on-chip transformer to mitigate substrate losses. Simultaneously, a low doping substrate beneath the transformer is used to increase resistivity, thereby reducing the substrate magnetic losses. Therefore, the total layout of the transformer is depicted in Figure 5, and the parameters obtained from electromagnetic (EM) simulation for \(L_{p}\), \(L_{s}\), and \(k\) are as shown in Table 1.  
Figure 4: Insertion loss contours of output matching network. (a) 2.4 G. (b) 5.5 G.  
Figure 3: Reflection coefficient contours of output matching network. (a) 2.45 G. (b) 5.5 G.  
The schematic of the switching capacitor is shown in Figure 14. Two stacked thick-gate transistors are used, considering reliability when the switch is closed [16; 27]. The quality factor of the switching capacitor is mainly determined by the on-resistance of the switching transistors, while the on-resistance is determined by the size of the transistor. To increase the quality factor of the switching capacitor, larger transistor sizes are preferred. However, larger transistor sizes result in a larger parasitic capacitance in the off state, which is a capacitance that must be considered in the matching network. Therefore, the size of the switch needs to be carefully balanced, taking into account both on-state resistance and off-state capacitance. The on-resistance and off-state parasitic capacitance have been simulated for different transistor sizes, as shown in Figure 6. In this design, the \(C_{sws}\) is 1.37 pF, and the switching transistor size is 900 \(\upmu\)m/280 nm. Furthermore, by using parallel switching capacitors, the parasitic resistance of the overall switching capacitors can be further reduced when the switches are closed. Finally, the achieved output load impedance and the insertion loss of the output matching network in this design are shown in Figures 1 and 7. The insertion loss is higher than the target at the 5.5 GHz band due to the requirement of operating bandwidth at 2.4 G bands. The value of the transformer windings (\(L_{p},\ L_{s}\)) cannot be too small, causing larger insertion loss in 5.5 GHz band, and the degradation of the insertion loss is acceptable in practice. The simulation results demonstrate that the implemented output matching network exhibits superior matching performance across both the 2.4 GHz and 5 GHz frequency bands, fully validating the effectiveness of the dual-band matching network design methodology presented in this work.