# Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories
## 4 P/E Cycling
These results can be explained by the V\({}_{th}\) distributions' changes that depended on the temperature. According to the simulated results by [PERSON] et al. (2016), V\({}_{th}\) distributions are tight at high temperatures (narrower overlap regions cause fewer error bits) but widened at cold temperatures (wider overlap regions cause more error bits). Furthermore, by normalizing the RBER, it was observed that, although RBER increasing at a rate of 70 \({}^{\circ}\)C was greater than that at 0 \({}^{\circ}\)C, the degradation tendencies did not show a clear temperature dependence in the whole temperature range as shown in Figure 3b. Considering that different V\({}_{th}\) distributions had different sensitivities to the cells' degradations, it was necessary to use a unified criterion to study the cells' degradations by cycling stress at different temperatures. Next, for further evidence, cross-temperature characterizations were conducted to study the temperature effects on P/E cycling stress-related cell degradations. As shown in Figure 4, we designed the following experiment: firstly, we selected three groups of blocks, and all groups performed 1000 P/E cycles at 25 \({}^{\circ}\)C (Stage-1); secondly, 1000 P/E cycles were executed in three groups, \(-\)30, 25, and 70 \({}^{\circ}\)C (Stage-2); then, the temperatures were lowered to 25 \({}^{\circ}\)C, and 1000 P/E cycles were subsequently performed on all groups (Stage-3). Finally, each group operated 3000 read cycles at 25 \({}^{\circ}\)C. It can be observed that, no matter \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Fitting Parameter** & \(\mathbf{k_{1}}\) & \(\mathbf{k_{2}}\) & \(\mathbf{k_{3}}\) & \(\mathbf{k_{4}}\) \\ \hline \(\alpha(T)\) & \(-\)0.0214 & \(-\)0.13205 & / & / \\ \(\beta(T)\) & / & / & \(-\)391.98 & 707913 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: The values of fitting parameters in \(\alpha(T)\) and \(\beta(T)\). Figure 2: Measured operation times during P/E cycling at different temperatures: (**a**) erase time (\(t_{erase}\)) and (**b**) program time (\(t_{prog}\)). \(t_{erase}\) depends on the temperature, while \(t_{prog}\) depends on both the temperature and P/E cycles, which agreed well with the simulation curves in the blocks with higher than 100 P/E cycles. what the temperature we chose in stage-2, the RBER degradation tendency trends were almost the same in stage-3 and read cycles after cross-temperature P/E cycles. On the one hand, it can be concluded that thermal experiences (up to 70 \({}^{\circ}\)C) have negligible impacts on RBER degradation; on the other hand, the 3D NAND is suitable for high-temperature operations because the RBER is lower and the effects of P/E cycling caused damage will not be accelerated at higher temperatures. It should be noted that no matter what the operation mode we adopted, operations at higher temperatures did cause larger degradations to memory cells such as enhanced interface trap generation. Fortunately, these damages do not cause worse error bits degradation using the same criteria (Stage-3) as shown in Figure 4.