# Elliptic-Curve Crypto Processor for RFID Applications
## 2 Preliminaries
### PM Computation over \(Gf(2^{M})\)
As described in the previous section (Section 3.4.1), 6 states are required for the implementation of swap statements. Therefore, six clock cycles are required for this task. For each inversion computation, \(m-1\) squares followed with

Figure 3: FSM Controller of the Proposed Hardware Accelerator Architecture of ECP. 9 multiplications are needed [29] over \(GF(2^{163})\). Therefore, \(m+(9\times m)\) clock cycles are needed for each inversion, where \(m\) determines the key length. Finally, twelve clock cycles are required to perform the remaining sequence of routines in the projective-to-affine conversion. Consequently, it requires a total of 2627 clock cycles for one PM computation. Out of 2627 cycles, 5 cycles are for affine-to-projective conversion, 993 clock cycles are for PM computation in a projective coordinate and 1629 clock cycles are for projective-to-affine conversions. These clock cycles can be computed using Equation (1). \[Total\ clock\ cycles\ =\ \sum_{Affine\_to\_Proj\_Conv}\ +\ \frac{15+(6\times m)}{PM\_in\_Proj\_Coond}\ +\underbrace{3\times(inversion)+12}_{Proj\_to\_Affine\_Conv} \tag{1}\]

## 4 Implementation Results and Comparisons

This section includes two subsections where the implementation results are given in Section 4.1 and a comparison with the state-of-the-art is given in Section 4.2. ### Results

We have modeled our architecture in Verilog over \(GF(2^{163})\) using the Vivado design tool. The performance of the proposed ECP architecture is evaluated with the integration of a schoolbook polynomial multiplier in two different logic styles (i.e., sequential and combinational). Therefore, the implementation results in the state-of-the-art 7-series FPGA devices are summarized in Table 1. For Kintex-7, Artix-7 and Virtex-7 FPGA boards, the chosen devices for logic synthesis are XC7K325 TFFG900-2, XC7A200 TFBG676-2 and XC7 VX485 TFFG1761-2, respectively. The first column in Table 1 shows the implementation device. The provided clock period and the corresponding clock frequency (in MHz) are given in column two and column three, respectively. The time required to perform one PM computation, i.e., latency (in \(\upmu\)s), is presented in column four. The area information in terms of look-up-tables (LUTs) and flip-flops (FFs) is shown in column five and column six, respectively. Finally, the last column (column seven) provides the utilized power (in \(\upmu\)W). The latency of the architecture is computed by using Equation (2). \[Latency\ (in\ \mu\textsuperscript{s})=\frac{Clock\ cycles}{Freq\ (MHz)} \tag{2}\]

#### 4.1.1 Use of a Polynomial Multiplier as Sequential Logic

The use of a schoolbook multiplier as a sequential logic results in a shorter critical path with an increase in both area and clock frequency. Therefore, Table 1 shows that the proposed accelerator architecture utilizes 1786 LUTs and 1855 FFs on modern 7-series FPGA devices (Kintex-7, Artix-7 and Virtex-7). With the utilization of same hardware resources (in terms of LUTs and FFs) for several 7-series FPGA devices, the achieved clock frequency on both Kintex-7 and Virtex-7 devices is 909 MHz which is comparatively 1.18 times higher as compared to the frequency achieved on Artix-7 (769 MHz). On the other hand, the power achieved on both Kintex-7 and Atix-7 devices is 0.647 mW which is comparatively 1.13 times lower than the power achieved on Virtex-7 FPGA (0.733 mW).