## 4 Discussion  
We have obtained a new integer algorithm for type II DCT that has good approximation properties and allows efficient VLSI implementation. Moreover, it allows an efficient integration of the obfuscation technique with low overheads. The involved overhead of incorporating the obfuscation technique is low and consists of 22 four-way, one-bit multiplexers. The area overhead of the multiplexers is under 1% of the total chip area, while the impact on the speed of the DCT core operation is minimal because the multiplexers are not on the critical data path of the systolic arrays. For the proposed integer algorithm, a new systolic array-based VLSI architecture has been obtained. It consists of five linear arrays, each having four processing elements, and one array with two processing elements, all working in parallel. Due to the fact that the proposed integer algorithm is using only small integers and each processing element contains a multiplier with a small constant implemented with two adders (with two exceptions where we use three adders), the hardware complexity was significantly reduced and, at the same time, the speed performances were increased due to the fact that in the systolic chains the delay on the critical path is mostly \(3T_{a}\), where \(T_{a}\) is the delay of one adder. Thus, we can use only adders/subtracters and shift operations to implement the proposed VLSI architecture. As it can be seen from Table 2, to implement the constant multipliers we mostly need only 2 adders and shift operations, with 2 exceptions, where for coefficients 106 and 90 we use 3 adders. Due to the fact all five systolic arrays are working in parallel and due to the use of the pipelining mechanism, where the critical path has a delay of mostly \(3T_{a}\), we can obtain high speed performances at a significantly reduced hardware cost due to the use of only adders to implement the proposed VLSI architecture. Moreover, the proposed solution can efficiently integrate the hardware security technique with a slight increase in the hardware complexity with only 22 MUXs, without affecting the speed performance. Furthermore, the proposed solution has similar advantages to other systolic array VLSI implementations of type II DCT, such as efficient VLSI implementation and low I/O cost. In Table 3, a comparison in terms of area, power, and speed performance is presented. The proposed IntDCT solution is compared to similar solutions from the literature. \begin{table}
\begin{tabular}{c c c} \hline
**Coefficient (C)** & **Representation** & **Number of Adders/Subtractors** \\ \hline
127 & \(2^{7}-2^{0}\) & 1 \\
81 & \(2^{6}+2^{4}+2^{0}\) & 2 \\
13 & \(2^{4}-2^{1}-2^{0}\) & 2 \\
100 & \(2^{6}+2^{5}+2^{2}\) & 2 \\
122 & \(2^{7}-2^{2}-2^{1}\) & 2 \\
113 & \(2^{7}-2^{4}+2^{0}\) & 2 \\
37 & \(2^{5}+2^{2}+2^{0}\) & 2 \\
60 & \(2^{6}-2^{2}\) & 1 \\
125 & \(2^{7}-2^{1}-2^{0}\) & 2 \\
106 & \(2^{6}+2^{5}+2^{3}+2^{1}\) & 3 \\
25 & \(2^{4}+2^{3}+2^{0}\) & 2 \\
71 & \(2^{6}+2^{3}-2^{0}\) & 2 \\
48 & \(2^{5}+2^{4}\) & 1 \\
118 & \(2^{7}-2^{3}-2^{1}\) & 2 \\
128 & \(2^{7}\) & 0 \\
90 & \(2^{6}+2^{4}+2^{3}+2^{1}\) & 3 \\ \hline \end{tabular}
\end{table} 
Table 2: Representation of the constant multiplication coefficients used in the PEs. All the referenced designs in Table 3 were mapped to a 45 nm standard cell library using Synopsys Design-Compiler, whereas our design was mapped to Nangate's OpenCell Library based on NCSU's 15 nm FreePDK15 using Cadence Genus 21.14. As can be seen from Table 3, a considerable reduction in power consumption has been obtained for the proposed solution due to a reduced hardware complexity based on as few as 29 adders to implement the hardware core with 5 linear systolic arrays. One of the most important advantages of using the systolic array architectural paradigm is a significant reduction in the delay on the critical path, as emphasized in Table 3, where an improvement of more than 93% was obtained as compared to the referenced designs.