# Tunneling Current Variations in Small-Sized Devices Based on a Compact Threshold Voltage Model
## 1 Introduction  
Strained Si materials offer the advantages of high carrier mobility, adjustable band gap, and compatibility with the traditional Si process. They are the preferred alternative in research on high-speed, high-performance, scaled MOSFETs [1; 2]. Threshold voltage is the most critical parameter of MOSFETs, and it affects the AC/DC and subthreshold characteristics of the device. Research on the threshold voltage of strained silicon devices is significant, as it determines the devices' on-off characteristics. Studying the threshold voltage of strained silicon devices helps to understand their operating state and features and can lead to optimized device design and improved performance and reliability. As device dimensions continue to shrink, the influence of short-channel effect becomes more significant. Strained silicon devices can mitigate or suppress short-channel effect through strain engineering techniques, and the threshold voltage is a crucial parameter in studying these effects. Accurate control of the threshold voltage and accurate threshold voltage adjustment are crucial for process optimization and device fabrication. Researching the threshold voltage of strained silicon devices can facilitate the development of improved process methods and technologies, enabling more precise and stable control of threshold voltage, thereby enhancing process controllability and stability. When designing integrated circuits using strained silicon devices, it is necessary to have an accurate threshold voltage model. By delving into the factors that influence threshold voltage, more precise models can provide essential theoretical support for integrated circuit design and for optimizing performance to meet design requirements. So, research on the threshold voltage of strained silicon devices plays a significant role in optimizing device performance, suppressing short-channel effect, optimizing processes, and supporting integrated circuit design. In current state-of-the-art chip designs, to stop short-channel effect, advanced device designsare extensively used, and strained silicon devices are among these designs. Examples include Intel's Core processor using 32 nm process technology and TSMC's 7 nm process, where strained silicon technology has been implemented. This research is essential for advancing the development and application of strained silicon technology. There are many studies on the threshold voltage of strained Si NMOSFETs [3; 4; 5; 6; 7]. However, the influences of substrate bias, short-channel effect, narrow-channel effect, and drain-induced barrier lowering effect on threshold voltage have still not been fully considered, and therefore the results cannot be fully applied to the design requirements of devices and integrated circuits under realistic process conditions. In this paper, a threshold voltage model of a long channel is built using the gradual channel approximation theory and the potential of the strain Si MOSFET longitudinal is analyzed. The influence of substrate bias on threshold voltage is fully considered in the model. However, a one-dimension method cannot meet the requirement of threshold voltage accuracy for scaled devices. To improve the threshold voltage accuracy, two-dimensional and quasi-two-dimensional analysis methods are often used [8; 9]. When solving a two-dimensional Poisson equation in the depletion region utilizing a two-dimensional method, the physical meaning of model parameters is deficient due to some approximations made on boundary conditions. In this paper, a quasi-two-dimensional method is used to solve a two-dimensional Poisson equation. A threshold voltage model is built fully considering the short-channel effect, DIBL effect, and the narrow-channel effect. To ensure that the simulation results can better match test results, it is necessary to correct the model using process parameters [10]. So, an integrated physical compact model for threshold voltage of a strained Si NMOSFET is built fully considering the physical effects on threshold voltage.