# FPGA Implementation of a Deep Learning Acceleration Core Architecture for Image Target Detection
## 2 Proposed Method
### Parallel Acceleration of Computational Layers in CNN  
#### 2.1.1 Parallel Acceleration of Convolutional Layers  
The convolutional layer is the most computationally intensive for a general CNN. For an input size of 224 \(\times\) 224 \(\times\) 3, convolution with a 7 \(\times\) 7 \(\times\) 3 \(\times\) 64 convolutional kernel is approximately equivalent to the number of input parameters multiplied by the number of convolutional kernel parameters; however, for batch, activation, and pooling layers, the computation is only approximately the size of the input size itself, which is a reduction in computation by thousands of times compared to convolutional layers. Therefore, the design of the acceleration core for CNN needs to focus on the acceleration scheme of the convolutional layer. Figure 1: The architecture consists of three parts, the first part is the video capture channel, the second part is the deep learning acceleration core, the third part is the scheduling system. As shown in Figure 3, taking the example of a convolution operation between a 4 \(\times\) 4 \(\times\) 3 input tensor and a 2 \(\times\) 2 \(\times\) 3 \(\times\) 2 convolution kernel, the parallel acceleration of the convolution layer is divided into three main dimensions: input channel parallelism, output channel parallelism, and pixel parallelism. Figure 3: The parallel acceleration of the convolution layer is divided into three main dimensions: input channel parallelism, output channel parallelism, and pixel parallelism. Figure 2: A full view of our proposed method. Input channel parallelism is the parallelization of the product of the input tensor and the convolution kernel. The results are added together to obtain a pixel of the output channels. Input channel parallelism calculates the channel vector of one pixel of the input tensor and one pixel of the convolution kernel in a dot product operation each time and finally adds up the results. The hardware implementation of this operation requires the logic to access all channels of the input vector and the convolution kernel simultaneously, so the bit width of the computational kernel needs to be adjusted accordingly. For example, for a kernel with eight input channels in parallel, a single data transfer from the kernel requires 8\(\times\) the data bit width. If the number of input channels is less than 8, the rest of the bit widths are complemented by 0. Suppose the number of input channels exceeds 8; only eight are counted in each computation. The computation is divided into multiple computations, complementing the last by 0. Output channel parallelism refers to the simultaneous convolution of an input tensor with multiple convolution kernels to obtain multiple channels of the output tensor. This operation does not increase the bandwidth requirement of the computational kernel for the input data. However, it requires the computational kernel to be able to access the values of the convolution kernel on multiple output channels at the same time. Pixel parallelism means that the elements of the input tensor at different positions are convolved with the convolution kernel. In contrast, the elements of the output tensor at different positions are obtained in parallel. Take the example of a 4 \(\times\) 4 \(\times\) 3 input tensor and a 2 \(\times\) 2 \(\times\) 3 \(\times\) 2 convolution kernel. Assuming the top-left corner of the input tensor is 1, the pixel values in the first row of the output tensor are obtained by simultaneously computing the convolution of the pixels in positions 1, 2, and 3 with the convolution kernel. This operation requires simultaneous access to the element values of the input channel at different pixel points. It requires a hardware design that increases the access bandwidth of the computational kernel. For example, in a parallel scheme with a pixel parallelism of 4, the input tensor is divided into different data buffer groups by column. The number of pixels in parallel is complemented by 0.