# Averting BER Floor with Iterative Source and Channel Decoding for Layered Steered Space-Time Codes
## 2 Overview of Layered Steered Space-Time Codes
### Receiver Model  
The received signal vector is mathematically given by \(Y=HWX+n\), where \(X\) shows the transmitted signal vector, \(H\) represents the \(N_{r}\times N_{t}\) matrix for a Rayleigh fading channel and \(n\) indicates the additive white Gaussian noise vector as discussed in [33; 34]. The entries of \(n\) essentially have zero mean. The three-stage receiver model consists of the outer SBC decoder, the intermediate URC decoder, and the inner SP demapper. These three stages are respectively labelled as 1, 2, and 3 in Figure 1. These constituent decoders iteratively exchange information between each other in the decoding process for attaining convergence [14]. [PERSON] presented the logarithmic-likelihood ratios (LLRs) concept for scenarios where the constituent decoders iteratively share information with each other [40; 41]. LLR is actually the logarithm of the probability ratio of a bit for its legitimate binary values. In Figure 1, the LLRs are represented with \(L(.)\) and distinguished with the superscripts 1, 2 and 3 for each decoder accordingly. Other associated decoding terminologies used are _a priori_ or intrinsic Information (\(I_{A}\)), _a posteriori_ information and Extrinsic Information (\(I_{E}\)) elaborated in [40; 41]. We have used the subscripts of \(a\), \(p\), and \(e\) with the \(L(.)\) values for _a priori_, _a posteriori_ and extrinsic values respectively.  
The LSSTC decoder forwards the received complex symbols to the SP demapper in the LLR format [21]. The information exchange between SP demapper and URC decoder constitutes an inner iteration as shown in Figure 1. As SP assists in enhancing the diversity gain with the aid of multiple antennas, but this improvement comes at the cost of increased SP decoding complexity. The SP demapper continues to share information with the URC decoder for providing an enhanced extrinsic information to the URC decoder. Subtracting _a priori_ LLR value \(L_{a}(.)\) from the _a posteriori_ LLR value \(L_{p}(.)\) value results in extrinsic LLR information \(L_{e}(.)\) as labelled in Figure 1. \(L_{p}^{2}(r)\) values are generated with the aid of maximum a posteriori (MAP) algorithm [42] by deinterleaving \(\Pi_{\text{in}}^{-1}\) the \(L_{a}^{3}(r)\) information and then allowing it to the URC decoder. With the aid of interleaver \(\Pi_{\text{in}}\), \(L_{e}^{2}(r)\) are converted to \(L_{a}^{3}(r^{\prime})\) and fed back to the SP demapper in next iterations.  
For the outer iteration, \(L_{a}(.)\) values are passed through the URC decoder and the output is deinterleaved via \(\Pi_{\text{out}}^{-1}\). The information is then forwarded to the SBSD which yields a posteriori \(L_{p}^{1}(s)\). Subtracting the _a priori_\(L_{a}^{1}(s)\) information from \(L_{p}^{1}(s)\) generates \(L_{e}^{1}(s)\) which is interleaved via \(\Pi_{\text{out}}\) to generate \(L_{a}^{2}(s^{\prime})\) for feeding as a priori input to the URC decoder in next iterations. Furthermore, for our proposed design, we have considered a system iteration \(I_{sys}\) to complete one cycle after one inner and two subsequent outer iterations, that is \(I_{sys}=I_{in}+2I_{out}\). After one \(I_{sys}\), the a posteriori \(L_{p}(c)\) is forwarded to the SBC decoder for generating the reconstructed bit stream \(\hat{x}_{k}\) for feeding to the H.265 decoder.  
The bits from the H.265 decoder are used for performance evaluation and simulation results of our three-stage LSSTC design.