# On Noise Modeling of Capacitive Feedback Transimpedance Amplifiers in CMOS
## 4 Discussion
The major differences are caused by the absence of both flicker noise components (correspondingly from \(M_{1}\) and \(M_{5}\)) and missing resistor noise contribution in the biasing circuit. The latter observation is consistent with the discussion in the previous section, as the biasing circuit was often assumed to possess infinite resistance and was omitted from consideration while developing the noise models by other authors. Of importance is that our proposed noise model does not assume fixed TIA gain when scaling the noise from \(R_{2}\). As we see, the noise models that are commonly found in the literature are inadequate for estimating the noise level in realistic capacitive feedback TIA when voltage headroom constraints are applied (i.e., for realistic circuits with biasing circuits), and such models may significantly underestimate the noise level at all frequency ranges. One can notice here a distinct difference in the proposed TIA architecture when compared to the classical resistive-feedback approach. In simple resistive-feedback TIA, both the dominating noise source and the gain are mainly defined by the feedback resistor \(R_{\rm F}\). However, in the proposed design, the baseline noise is defined by a set of different parameters along with a more complex gain definition. We believe that it is exactly this feature of the proposed architecture that provides a better trade-off for the main amplifier parameters when compared to the classical TIA designs still widely adopted for numerous applications [28]. While in the classical resistive approach almost everything depends on a single value of \(R_{\rm F}\), in capacitive feedback, the dependency is far more complex, which provides the designer with alternative and complementary tuning knobs for circuit optimization and tuning. A careful inspection of the previous results reveals that the gain adjustment method based on two tuning knobs (\(R_{\rm bias,1}\) and \(C_{\rm 1}\)) may be also a weakness of the proposed schema. For the exemplary realistic CMOS configuration presented above, the passband in the middle may be not sufficiently flat, as the gain in the low-frequency range is mainly adjusted with the bias resistor of \(M_{\rm 1}\), while \(C_{\rm 1}\) controls the gain adjustment at higher frequencies. In the particular example above, this leads to a drop of around 0.7 dB\(\Omega\) and this may have a negative impact on the performance of the complete front-end. The small pitch or step appears in the middle of the passband and it cannot be easily tuned out by a careful selection of both tuning parameters available to the user. In practice, this means that the pitch is likely to be maintained no matter how the two tuning knobs are selected, and the flatness in the passband depends on correspondence between both values, as well as on the rest of the circuit parameters. This may make the process of the gain adjustment far less intuitive. An idea for the solution comes from the observation that the exact position of the transition point between the frequency ranges (dominated by, correspondingly, \(R_{\rm bias,1}\) and \(C_{\rm 1}\)) depends itself on the value of \(r_{\rm DSS}\). The preliminary results using the cascade in the current source with the transistor \(M_{\rm 5C}\) on top of \(M_{\rm 5}\) confirm that further improvement in base noise levels can be achieved (see Figures 12 and 13) along with the improved flatness of the gain plateau (not shown). The preliminary results for the cascade configuration with \(Z_{\rm T}=10\) k\(\Omega\) confirm that the noise minimum decreases from approximately 1.6 pA/\(\sqrt{\rm Hz}\)\(-\) 1.8 pA/\(\sqrt{\rm Hz}\) in the case of non-cascode configuration (CMOS and BiCMOS) to around 0.6 pA/\(\sqrt{\rm Hz}\) in the case of cascode-based configurations. This is a significant performance improvement in terms of noise at a price of somehow larger \(r_{\rm DSS}\).