# An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios
## 2 Background and Related Work  
This section discusses the impact of some aspects of digital baseband processing in 5G scenarios and reviews related work on reconfigurable FPGA-oriented baseband processors for multi-waveform and flexible wireless communications. Carrier aggregation (CA) is a technique with the potential to increase system capacity and enhance spectrum usage. It is already exploited in 4G/LTE communications, and 5G will surely rely on it to improve spectrum efficiency within heavily used frequency bands and also across different frequency bands (from low-band to mmWaves) [8]. There are two main types of CA: contiguous CA and non-contiguous CA. In the former case, aggregated component carriers are adjacent to each other, whereas in the latter case, they are fragmented along the spectrum. Although contiguous CA does not require deep changes in the transceiver PHY, multiple and flexible PHY blocks are needed for non-contiguous CA, in order to adaptively tune communication parameters for each component carrier to aggregate [9]. Another technique that can be combined with CA to boost spectrum utilization efficiency is Dynamic Spectrum Access (DSA): a mechanism through which idle spectrum resources (spectrum holes) from different primary (licensed) users are opportunistically accessed by secondary (non-licensed) users [10]. To avoid interferences with primary users, secondary users monitor and detect available spectrum holes through spectrum sensing techniques. Due to the spectral agility and multitude of 5G service requirements, it is unfeasible and inefficient to design separate standalone radio systems for each service or use case. Instead, a 5G baseband system should be flexible enough to support and multiplex a wide variety of services. This is also the case for C-RAN architectures, where the centralized baseband processing should be carried out by adaptive and reconfigurable hardware according to the concept of software-defined radio [11]. Prior to the advent of 5G communications, the growing interest in SDR and cognitive radio led to research efforts towards flexible and reconfigurable baseband processors. Apart from the trade-offs between GPU flexibility and ASIC performance, the possibility for DPR in SRAM-based FPGAs makes them compelling hardware platforms for baseband architectures for agile and flexible radio communications [11; 12; 13]. Early works exploited DPR for the design of specific modules in the baseband processing chain, like FIR filters or constellation mappers [14; 15]. One of the first multi-waveform flexible PHY architectures for SDR transmitters was proposed by [PERSON] et al. [16]. This architecture was implemented on a Xilinx Virtex-5 FPGA device, and it combines two reconfiguration techniques: (a) DPR is employed to dynamically change the baseband processing mode of operation; and (b) DFS is used to adapt the clock frequency of the digital up-converter and the baseband processor. The implementation supports two waveforms (OFDM and WCDMA ) and several 3G/4G standards and modes of operation. This work focuses on the resource efficiency achieved with DPR compared with an equivalent static multi-mode design, but lacks a comprehensive analysis of the DPR/DFS latency or the impact of DFS on power consumption. [PERSON] et al. [17] also exploited DPR in a multi-standard OFDM transceiver implementation. These works paid little attention to the impact of CA on the PHY, as the architectures considered a single reconfigurable baseband processor only. As discussion about 5G progressed, the interest in alternative waveforms to mitigate OFDM weaknesses increased [1], and multi-waveform coexistence scenarios are likely to be a reality in future communications [3]. For instance, [PERSON] et al. [18] presented a scenario combining DSA with multi-waveform coexistence, where 5G networks use the existing 4G-LTE infrastructure as an anchor.