# Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency
## 5 Proposed Hardware Realization of Flexible 5G NR LDPC Encoder
### LDPC Encoder Architecture  
The hardware architecture of the proposed flexible encoder is shown in Figure 11. Information bits are stored in the input buffer dual-port memory. In order to implement double buffering, the input buffer can receive information bits for two adjacent codewords. One half of memory is used for reads during the current codeword encoding, while the other half is used for information bits storage for the next codeword. Consequently, there is no need for any information bits repackaging when the encoding starts, which removes the need for additional clock cycles and increases the encoding speed. Depending on the lifting size, the encoder can work in one of the three modes determined by the circular shifter. If lifting size is in the range \(192<Z\leq 384\), the encoder serially processes one CPM per clock cycle, from one row of the base graph matrix. The information bits group of maximum bit length 384 is read from the input buffer. Info bits are shifted and used for the calculation of GF(2) sums for \(\lambda\) vectors. All GF(2) additions are realized using the XOR operation. If lifting size is in the range \(96<Z\leq 192\), the encoder serially processes up to two CPMs per clock cycle, from two adjacent rows defined by the optimized schedule. In this case, a word that is read from the input buffer memory consists of an information bits group (of maximum bit length 192), and its copy is placed in the word's high bits. This is provided by the input interface, which is not shown in Figure 11. Circular shifting network works as two independent CSs with shift sizes equal to the given code lifting size. If lifting size is in the range \(2\leq Z\leq 96\), the encoder serially processes up to four CPMs per clock cycle, from four adjacent rows defined by the corresponding optimized schedule. The input buffer now contains words that consist of four identical copies of information bits groups. They are independently shifted in the CS and then used for the calculation of four independent GF(2) sums. During the process of \(\lambda\) vectors calculation, information bits are also passed to the output codeword generator that writes the data to the output buffer. Figure 11: Proposed 5G NR LDPC encoder architecture. Since, as described, the parallelism of the \(\uplambda\) vectors calculation is different for different lifting sizes, there is a need for a separate block, marked as \"Merge/Select \(\uplambda\)\" in Figure 11, whicharranges the \(\uplambda\) vectors data in the appropriate order for later core parity bits calculation. After the calculation of all \(\uplambda\) vectors, the process continues in the same manner for the next rows in the base graph matrix. During that time, core parity bits are calculated in parallel. BG1 and BG2 have different equations for the calculation of core parity bits. However, most of the logic can be shared by inserting a few additional multiplexers that rearrange data paths depending on the base graph selected. The circular shifter marked as CS(1) shifts data only by 1, to the left or right depending on the base graph. Since the shifter should support only two shift values, it can be implemented using just a fragment of resources that are used for the main CS, although it should still support all lifting sizes defined in the 5G NR standard. When calculated, the core parity bits are also passed to the output codeword generator. Calculated core parity bits are returned to the main CS input since they are used for additional parity bits calculation. One of the four core parity bit groups is selected based on the control CPM data. Depending on the lifting size, the selected core parity bits group is copied in the same way as it has been for information bits in the input buffer. Finally, four sets of multiplexers determine whether the information bits group or the core parity bits group should be passed to the CS. Outputs of the \"GF(2) Sum\" block are now additional parity bits, which are passed to the output codeword generator.