## 3 General Strategies for Energy Efficient BSN Hardware
### Supply Voltage Management  
Lowering the supply voltage to a circuit is a well known approach for reducing energy. In this section, we first discuss the limit of lowering voltage to reduce energy consumption, and then describe how dynamic voltage scaling can allow us to tradeoff energy and performance. For digital circuits, energy of computation varies as the square of the supply voltage (V\({}_{\mathrm{DD}}\)), which makes it desirable to operate at the lowest possible voltage while preserving functionality and meeting timing constraints. Taking this principle to the extreme, we observe that sub-threshold (sub-V\({}_{\mathrm{T}}\)) operation of digital integrated circuits provides one important option for energy efficient processing. Sub-V\({}_{\mathrm{T}}\) circuits use a V\({}_{\mathrm{DD}}\) that is below the threshold voltage, V\({}_{\mathrm{T}}\), of the transistors. This makes the transistors \"off\" by conventional definitions, but the change in transistor gate-to-source voltage (V\({}_{\mathrm{GS}}\)) produces a difference in sub-V\({}_{\mathrm{T}}\) conduction current that allows static digital circuits to operate robustly, although slower than they would be at higher voltage. The lower speeds are still more than sufficient for many BSN operations (up to 10's of MHz). Both the off-current and the on-current of the transistors vary exponentially with V\({}_{\mathrm{DD}}\) in the sub-V\({}_{\mathrm{T}}\) region (V\({}_{\mathrm{GS}}<\) V\({}_{\mathrm{T}}\)). Nevertheless, the on-current in sub-V\({}_{\mathrm{T}}\) remains larger than the off-current by enough (1000\(\times\) or so) to enable proper functionality of the digital gates. Due to the quadratic relationship between energy and V\({}_{\mathrm{DD}}\), the main advantage of sub-V\({}_{\mathrm{T}}\) operation is a reduction in energy consumption of over 10\(\times\) compared to traditional circuit implementations. In fact, sub-V\({}_{\mathrm{T}}\) operation has been shown to minimize energy per operation in conventional CMOS circuits [6]. For this reason, sub-threshold operation will play an important role in custom hardware for BSNs. There are some challenges to making sub-V\({}_{\mathrm{T}}\) digital circuits work. Most notably, the reduced I\({}_{\mathrm{or}}\)/I\({}_{\mathrm{off}}\) ratio combines with process variations in the threshold voltage to increase the potential for circuit failure. Sub-V\({}_{\mathrm{T}}\) circuits also must be level converted to interface with super-V\({}_{\mathrm{T}}\) design, such as radios or sensors. Additionally, design of sub-V\({}_{\mathrm{T}}\) circuits is not yet commonplace. Standard cells used in designs are rarely designed for this voltage of operation, in which transistor strengths change. Nevertheless, sub-V\({}_{\mathrm{T}}\) operation is an emerging approach that is very useful for BSN nodes [7]. Operating at a low voltage all of the time may not be a viable option for all BSNs, because lower voltages slow down circuit speed. Given that a BSN's processing latency and throughput requirements may change during execution in response to real-time data and mode changes, dynamic voltage scaling (DVS) can be employed to minimize V\({}_{\mathrm{DD}}\) given those requirements. When high performance is necessary to meet system level requirements, the circuits can operate at the energy-costly higher voltage level. By reducing the circuit's V\({}_{\mathrm{DD}}\), quadratic energy savings can be achieved instead of just the linear savings obtained through power gating (Figure 4). Different DVS schemes propose different approaches to scaling in terms of the circuit topology and interval at which the voltage is changed, and  
Figure 4: Energy-workload curve of normal operation and dynamic voltage scaling (DVS). the overhead of most schemes are minimal compared to the energy savings accomplished, especially when that scaling includes dropping to sub-\(\rm V_{T}\) levels when permissible [8]. Some COTS chips provide built-in DVS capabilities or allow for development of DVS schemes.