# An Embedded Sensor Node Microcontroller with Crypto-Processors
## 3 Microcontroller Design
### Sha-1  
Secure Hash Algorithm (SHA-1) is probably the most widely used algorithm for secure hash calculation. SHA-1 generates a 160-bit message digest of a 512-bit input block. It is based on principles similar to those of MD4 and MD5, but has a more conservative design. The SHA-1 core of the TNODE5 microcontroller requires 160 clock cycles to generate a 160-bit hash message. It can be used to ensure data integrity and (in combination with ECC) to generate digital signatures executing the elliptic curve digital signature algorithm (ECDSA). In addition, the SHA-1 has a programmable initial value register, which makes it suitable for generation of pseudo random numbers. These numbers are required by various cryptographic operations.  
The internal architecture of the implemented SHA-1 core is designed to process 512-bit input data blocks. The bit-stuffing technique is employed to align the data size to the 512-bit boundary. The bit-stuffing operation is performed in software. The information on the actual data size is stored in the control register. The 32-bit registers H0-H5 are used to store the 160-bit secret key. The 32-bit  
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline  & **Architecture** & **Binary Field** & \begin{tabular}{c} **Frequency** \\ **(MHz)** \\ \end{tabular} & \begin{tabular}{c} **Technology** \\ **Node (nm)** \\ \end{tabular} & \begin{tabular}{c} **Runtime** \\ **(Cycles)** \\ \end{tabular} & \
\begin{tabular}{c} **Power** \\ **(\mu\(\mu\)W)** \\ \end{tabular} &
\begin{tabular}{c} **Energy** \\ **(\mu\(\mu\)J)** \\ \end{tabular} \\ \hline
[58] & Dedicated Hardware & ECC-133 & 0.5 & 130 & 57,720 & 30 & 3.46 \\
[58] & Dedicated Hardware & ECC-163 & 0.5 & 130 & 95,159 & n.a. & n.a. \\
[59] & Software & ECC-163 & 1 & 130 & 72,169,05 & 49.1 & 354.35 \\
[59] & Dedicated Hardware & ECC-163 & 1 & 130 & 54,376 & 181.7 & 9.9 \\
[59] & Drop-in Module & ECC-163 & 1 & 130 & 182,130 & 70 & 12.8 \\ This Work & Dedicated Hardware & ECC-233 & 20 & 250 & 13,164 & 6230 & 4.1 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Comparison of different ECC implementations.  
registers W0-W15 are loaded with a 512-bit input data block. The hardware blocks within the SHA-1 core are responsible for generating the signature by performing the algorithm that is described with functions f, K and G. The functions f and K generate intermediate results of the hash algorithm. The function G performs the major hash generation operation and saves the signature back to the H register. This is illustrated in Figure 3. The generation of a signature for a 512-bit block takes 80 clock cycles.  
The SHA-1 algorithm was the standard cryptographic hash function during the development of the TNODE microcontroller. The recent reports show that the SHA-1 can be broken with approximately \(2^{57}\) equivalent SHA-1 evaluations [60]. The more powerful SHA-3 algorithm was standardized in 2014 and it is becoming the next leading secure hash function. For a new version of the TNODE the implementation of SHA-3 will be considered as the standard option. However, the hardware implementation of SHA-3 would contribute to additional costs regarding performance, power and area of the final chip.