## 1 Introduction  
The residue number system (RNS) [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11] has been widely used in the field of cryptography [10] for purposes such as Fermat number transform [12], elliptic curve ciphers [4, 13], Caesar ciphers [4], IDEA (International Data Encryption Algorithm) [13] block ciphers and asymmetric encryption [10] algorithms. The parallel carry-free feature of the RNS will speed up arithmetic operation when the RNS is applied over a binary-based system, thereby greatly reducing the propagation delay and hardware cost of the system. Therefore, the RNS has found wide application in communication systems, digital signal processors [6], digital filters [3], finite-impulse response (FIR) filters [3, 7], fast Fourier transform (FFT) [7], fault-tolerant detection [11], error correction coding [11, 14] and other fields [12]. Parallel-prefix adders [15] can provide a very efficient modulo arithmetic operation in RNS mathematical computation. Parallel-prefix adders [15] such as Kogge Stone adder, Sklansky adder, Ladner Fischer adder and Ling's adder are some of the most commonly used circuit architectures in modular operation. Modulo (2\({}^{n}\) + 1) multipliers [2, 13, 16, 17, 18, 19, 20, 21], modulo (2\({}^{n}\) - 1) multipliers [1, 8, 21, 22, 23, 24], modulo (2\({}^{n}\) + 1) adders [15, 25, 26] and modulo (2\({}^{n}\) - 1) subtractors [26], which are ROM (Read Only Memory)-less modular arithmetic operations, are most commonly used. Many modular multiplication methods have been reported, such as diminished-1 modulo multiplication [12, 15, 16, 27, 28], weighted modulo multiplication [2, 19, 26, 29], and Booth-encodermultiplication [8; 30]. Diminished-1 and weighted representations are commonly used in modulo (\(2^{n}-1\)) and modulo (\(2^{n}+1\)) multipliers. For the diminish-1 and weighted representation, \(n\) bits are required for the numbers [0, \(2^{n}-1\)] and \(n+1\) bits are needed for the numbers [0, \(2^{n}\)], respectively. For diminished-1 modular multiplication [12; 15; 16; 27; 28], 1 needs to be subtracted from both the multiplicand and multiplier during operation; therefore, the multiplicand and multiplier cannot be 0 and their operation range is only [1, \(2^{n}-1\)]. Thus, it is important to use an additional conversion circuit and a zero detection circuit, as well as to add back one adder after processing the sum of all the partial products. However, this will increase the hardware area, power consumption, and delay time in the design of diminished-1 modulo multiplication. To address these shortcomings, the weighted modular multiplication architecture was proposed [2; 19; 26; 29], which has an improved operation range of [0, \(2^{n}\)] and greatly reduces the delay time and circuit area. It is worth noting that the zero-detection circuit is not required for weighted modular multiplication. Booth-encoder modular multiplication, which uses two bits as the multiplier in operation, can further reduce the area and delay compared to weighted modular multiplication. The partial product of radix-4 Booth-encoder modular multiplication [8; 30], which uses three bits as the multiplier, is reduced by nearly half compared to that of conventional Booth-encoder modular multiplication. This will considerably reduce the use of the full adder, thereby minimizing the circuit area and delay time. This study proposes an FPGA implementation of multifunction modulo (\(2^{n}\pm 1\)) multiplier based on radix-4 Booth encoding that can operate both the modulo (\(2^{n}+1\)) multiplier and modulo (\(2^{n}-1\)) multiplier in the same hardware. [PERSON] and [PERSON] [8] presented a modified Booth-encoder-based multifunction modulo (\(2^{n}\pm 1\)) multiplier using the structure of a modified Booth-coded 1's complement modulo (\(2^{n}-1\)) multiplier [1] and a modified Booth-based modulo (\(2^{n}+1\)) multiplier [18] and combined them into a multifunction modulo (\(2^{n}\pm 1\)) multiplier.