## 2 Background
### Schoolbook Strategy
\begin{table}
\begin{tabular}{l l l l l l} \hline \multirow{2}{*}{**Operand Sizes (\(j\times k\))**} & **Area Utilization** & \multicolumn{2}{c}{**Timing Details**} & \multicolumn{2}{c}{**Power Results**} \\ \cline{2-7}  & **Slices/LUTs/FFs** & **CCs** & **Freq** & **Lat** & **D/S/TP** \\  & & & **(MHz)** & **(\(\upmu\)s)** & **(\(\upmu\)W)** \\ \hline \multicolumn{7}{l}{Key lengths by NIST for use in a binary field ECC (taken from [29])} \\ \hline
163 \(\times\) 163 & 245/584/827 & 82 & 584 & 0.140 & 153/324/477 \\
233 \(\times\) 233 & 337/830/1180 & 117 & 568 & 0.205 & 161/324/485 \\
283 \(\times\) 283 & 413/1010/1432 & 142 & 564 & 0.251 & 192/324/516 \\
409 \(\times\) 409 & 582/1457/2070 & 205 & 558 & 0.366 & 275/325/600 \\
571 \(\times\) 571 & 775/2027/2880 & 286 & 546 & 0.523 & 372/326/698 \\ \hline \multicolumn{7}{l}{Key lengths by NIST for use in a prime field ECC (taken from [29])} \\ \hline
192 \(\times\) 192 & 291/686/973 & 96 & 581 & 0.165 & 184/324/508 \\
224 \(\times\) 224 & 319/800/1135 & 112 & 574 & 0.194 & 154/324/478 \\
256 \(\times\) 256 & 358/910/1295 & 128 & 578 & 0.221 & 177/324/502 \\
384 \(\times\) 384 & 520/1369/1946 & 192 & 560 & 0.342 & 254/325/579 \\
521 \(\times\) 521 & 700/1853/2633 & 261 & 549 & 0.475 & 344/325/669 \\ \hline \end{tabular}
\end{table} 
Table 1: _Cont._

#### 4.1.2 Booth Designs for Operand Sizes Recommended by NIST

If we consider the binary and prime ECC fields recommended by NIST for evaluation, there is an increase in the hardware area in slices, LUTs, and FFs with the rise in the operand size. The area increase can be seen in columns two to four of Table 1. The reported area values benefit the related community in deciding whether to choose our implemented Booth multiplier or not for their choice of application. As expected, the clock cycles, power consumption, and computation time or latency increase with the increase in operand sizes. The operating frequency shows a decrease with the rise in operand length. Similar to the throughput and throughput/area results from Figure 3a,b, we provide throughput and throughput/slices results for prime and binary ECC fields in Figure 4a,b. The throughput and throughput/area values are calculated using Equation (3) and Equation (4), respectively. Summarizing the findings, it is evident that the increase in operand sizes decreases throughput and the throughput/area ratio. Moreover, these figures show that for shorter operand sizes of 163 \(\times\) 163 and 192 \(\times\) 192, the values for throughput and throughput/slices ratio are higher than the larger operand sizes such as 571 \(\times\) 571 and 521 \(\times\) 521. Figure 4: Throughput and throughput/area results of the Booth multiplier for operand sizes of NIST prime and binary ECC fields. (**a**) Throughput of the Booth design with recommended key lengths by

Figure 3: Throughput and throughput/area results of the Booth multiplier when the operand sizes are in powers of two. (**a**) Throughput of the Booth design when operand sizes in powers of two. (**b**) Throughput/slices of the Booth design for operand sizes in powers of two. NIST for prime and binary fields in ECC. We selected these key lengths as operand sizes to our Booth multiplier based on [30]. (**b**) Throughput/slices of the Booth design with recommended key lengths by NIST for prime and binary fields of ECC. We selected these key lengths as operand sizes to our Booth multiplier based on [30]. #### 4.1.3 Summary of the Results

Table 1 and Figures 3a,b and 4a,b demonstrate that the increase in operand length increases the hardware area and computation time, while as expected, it decreases the operating frequency. Moreover, our Booth multiplier accelerator with shorter operand lengths is convenient for a wide range of applications, including but not limited to WSNs, RFID, elliptic curves, error-correcting codes, signal-processing algorithms for filtering, convolution, correlation, etc.