# Parasitic-Based Active Gate Driver Improving the Turn-On Process of 1.7 kV SiC Power MOSFET
## 2 The Active Gate Driver
#### Gate Voltage Manipulation for the Turn-On Cycle Improvement  
The measurement of the \(V_{\rm Ls}\) voltage can be used as a feedback loop for the method presented in Figure 2. The multi-level gate voltage (\(V_{\rm CG}\)--see Figure 1) method's purpose is to decrease power losses, drain current overshoot (\(I_{\rm rr}\)) and oscillations of the drain current at the turn-on cycle of a SiC MOSFET by changing the \(V_{\rm CG}\) voltage from 15 V to higher at times specified by the regulation system. For the chosen device (CAS300M17 BM2 [19]), the \(V_{\rm CG}\) value recommended by the manufacturers of SiC MOSFETs is 15 V; thus, such level was chosen. The second level of \(V_{\rm CG}\) may be selected between 15 and 30 V--the peak gate voltage allowed for this module; in this case, 30 V was chosen to obtain the maximum increase in the switching speed without damaging the gate oxide layer. Similar to other AGD methods for SiC MOSFET switching improvement, this approach is based on gate current manipulation of the device at the right moments of the switching transient. Thus, in that case, the aim is to improve the turn-on cycle without an unnecessary increase in \(di_{\rm D}/dt\) that would cause overshoot and oscillations of the drain current. What distinguishes this method from the many others is that the \(R_{\rm G}\) value is constant. Usually, the gate resistor  
Figure 1: SiC MOSFET (DUT) in the double-pulse test (DPT) setup with the active gate driver (AGD) in which the feedback loop is based on the parasitic source inductance voltage (\(V_{\rm Ls}\)). \(V_{\rm CG}\)—gate voltage, \(R_{\rm G}\)—gate resistance, \(S_{\rm Kelvin}\)—Kevin source, \(i_{\rm D}\)—drain current, \(v_{\rm DS}\)—drain-source voltage, \(L_{\rm S}\)—parasitic inductance, \(v_{\rm GS}\)—gate-source voltage. \(R_{\rm G}\) is placed as near as possible to the gate terminal of the SiC MOSFET to make the \(i_{\rm G}\) path as short as possible. The sequence of the proposed method appears as follows: at \(t_{0}\), the driving signal (\(DS\)) is changing from the low state to the high state which begins the turn-on cycle of the SiC MOSFET. The \(V_{\rm GG}\) voltage at the same time is changing from \(-5\) (low stage \(V_{\rm GG}\) level) to \(30\) V. The purpose of the first boost of \(V_{\rm GG}\) to the value of \(30\) V is to reduce the time delay between \(DS\) and \(v_{\rm GS}\) reaching the threshold voltage \(V_{\rm Th}\). At \(t_{0}\), the gate-source voltage \(v_{\rm GS}\) starts to rise from zero. After the \(v_{\rm GS}\) voltage crosses the threshold voltage \(V_{\rm Th}\) at \(t_{1}\), the drain current \(i_{\rm D}\) starts to rise. The \(V_{\rm Ls}\) voltage at \(t_{1}\) will start to rise from \(0\) V to the value proportional to \(d_{\rm ID}/dt\) and \(L_{\rm S}\); thus, the beginning of the rise of the current can be sensed. In order to decrease the \(d_{\rm ID}/dt\) ratio during the interval between \(t_{1}\) and \(t_{2}\), \(V_{\rm GG}\) is reduced to \(15\) V at time \(t_{1}\). This gate current manipulation stage target is to not cause any serious oscillations of the drain current in the main power circuit. Then, the gate-source voltage is latched from  
Figure 2: The multi-level gate voltage method waveforms for the turn-on cycle improvement of the SiC MOSFET with an inductive load. \(DS\)—logical driving signal of the device, \(V_{\rm GG}\)—gate voltage of the SiC MOSFET, \(v_{\rm GS}\)—gate-source voltage, \(v_{\rm DS}\)—drain-source voltage, \(i_{\rm D}\)—drain current, \(V_{\rm DD}\)—drain-source voltage before the turn-on of the MOSFET, \(I_{0}\)—drain current after switching on the device, \(V_{\rm Th}\)—threshold voltage, \(V_{\rm Miller}\)—Miller voltage, \(I_{\rm rr}\)—drain current overshoot, \(V_{\rm Ls}\)—ideal source parasitic inductance voltage waveform. \(t_{2}\) to \(t_{3}\) at [PERSON]'s plateau.