## 3 Design of Ternary Logic Circuits  
### Functional Ternary Logic Gates  
The truth table of ternary NOT-AND (NAND) and ternary NOT-OR (NOR) gates are given in Figure 3a. The two-input ternary logic functions of T-NAND and T-NOR gates [11] are defined by the following two equations:  
\[Y_{NAND}=\overline{min\{A,B\}} \tag{1}\]  
\[Y_{NOR}=\overline{\max\{A,B\}} \tag{2}\]  
For the T-NAND, it contains two steps of logic operations: Firstly it minimizes the two inputs of A and B, and then outputs the result after a NOT transformation. If the minimum input is \"0\", the output is \"2\". If the minimum input is \"1\", the output is \"1\". If the two inputs are all \"2\", the output is \"0\". The designed circuits are shown in Figure 3b, where 4 BP transistors and 2 MoS\({}_{2}\) transistors are involved. According to our pre-demonstrated STI as shown in section II, the parameters of the transistors are designed to be L\({}_{\text{ch}}=\) 0.1 \(\upmu\)m for BP1 and BP1', L\({}_{\text{ch}}=\) 1.8 \(\upmu\)m for BP2 and BP2' and L\({}_{\text{ch}}=\) 1 \(\upmu\)m for the two MoS\({}_{2}\) FETs. The core question of T-NAND simulation will be the calculation of the resistance of each part at different input voltage. Here, one important thing which needs to be pointed out is that the effective source voltage V\({}_{\text{s}}\) of the pull-up part will be V\({}_{\text{out}}\), while that of the pull-down part is always V\({}_{\text{s}}=\) 0. When input of A is \"0\", the MoS\({}_{2}\)' FET is fully turned off, so the output is \"2\", no matter what B is; When the input of A is \"1\", the BP1' FET plus the MoS\({}_{2}\)' FET is half turned on, so the output will not be \"0\" (but it will be \"1\" or \"2\", dependent upon B); When the input of A is \"2\", the BP1' FET plus the MoS\({}_{2}\)' FET is turned on as n-type, so the output is dependent on the input of B (Figure 3c). For the T-NOR, it also contains two-step of logic operations: It maximizes the two inputs of A and B, and then outputs the result after a NOT transformation. If the maximum input is \"2\", the output is \"0\". If the maximum input is \"1\", the output is \"1\". If the two inputs are both \"0\", the output is \"2\". The designed circuits for the T-NOR are shown in Figure 3d, where four BP transistors and two MoS\({}_{2}\) transistors are involved. The transistors' parameters are similar to that of a T-NAND. When the input of A is \"2\", the BP2' FET is fully turned off, so the output is \"0\", no matter what B is; When the input of A is \"1\", the BP2' FET is half turned on, so the output will not be \"2\" (yet it will be \"0\" or \"1\", dependent on B); When the input of A is \"0\", the BP2' FET is turned on as a p-type, so the output is dependent on B (Figure 3e). Ternary AND and ternary OR gates are known as the minimum and maximum gates. These two gates can be generated by adding one ternary NOT gate after T-NAND and T-NOR, respectively. Therefore, the two-input T-AND gate needs nine FETs (six for T-NAND and three for NOT), and the T-OR gate also needs nine FETs. Similar design methods can be used to implement the multi-input T-AND and T-OR logic gates. The ternary logic gates presented in Figure 4a,b can be used for designing ternary arithmetic circuits. As required for the ternary circuits, a design of a ternary decoder [9; 10; 11] is presented in Figure 4a. The ternary decoder is a one-input, three-output combinational circuit, and generates unary functions for an input X\({}_{\text{k}}\). The response of the ternary decoder to the input \(X\) is given by  
\[X_{k}=\left\{ \begin{array}{ll}2&if&X=k\\ 0&if&X\
eq k\end{array} \right. \tag{3}\]  
where \(k\) can take logic values of \"0\", \"1\" or \"2\". Note that the outputs of the decoder have only two logic values (namely \"2\" and \"0\"), corresponding to highest logic state (\"2\") and lowest logic state (\"0\") in binary logic, therefore, binary OR gates can be used here. A ternary buffer is also presented in Figure 4a. The ternary buffer contains one DCI and one STI.