## 2 Circuit Implementation
### ECG Monitoring Channel  
A block diagram of the input high pass filter (HPF) and the current-reused CFIA is shown in Figure 6. The input HPF is implemented to reduce the baseline wander. Since baseline wander has a low-frequency noise of less than 1 Hz, the input HPF should be designed to have a cutoff frequency of several Hz, demanding a very large resistance. Considering the HPF design in terms of area, a pseudo-resistor is used in the input HPF due to the fact that it is much less than the area of consumption when compared with a passive resistor with the same resistance value. The input HPF also determines the input reference voltage, VREF. Figure 5: Schematic of the amplifier utilizing a buffer and window comparator. Figure 6: Block diagram of the input high pass filter (HPF) and current-reused current-feedback instrumentation amplifier (CFIA). The current-reused CFIA has a very high input impedance (more than 10 G\(\Omega\)) as the CFIA topology receives the input signal as a gate oxide of the input transistor. It is about 20 times larger than the CCIA [11]. Due to the very high input impedance, it is possible for the proposed CFIA to achieve a high CMRR and to prevent signal distortion. The current-reused CFIA also adopts the AC-coupled capacitive feedback loop connected to the fully differential difference amplifier (FDDA). The capacitive feedback is not only amplification, but also has an HPF function, which can help to eliminate the residual baseline wander. The lower cutoff frequency of the feedback loop is controlled by the voltage of current bias, PESUDO_CONT, connected to the gate of the tunable pseudo resistor. Assuming the FDDA is ideal, the closed-loop gain by the capacitive feedback is expressed using the following equation:  
\[\text{closed loop gain}\approx\frac{2\times\text{C}_{\text{A2}}}{\text{C}_{ \text{A1}}}+1. \tag{2}\]  
A detailed schematic of the FDDA in the current-reused CFIA is shown in Figure 7.  
The current-reused CFIA adopts an inverter-based differential-difference cascode input stage combined with floating class-AB biasing. To gain the driving capability of the capacitive feedback load and a wide output range with high-power efficiency, a class-AB output stage is implemented. To ensure to stability, NMC is adopted. In the fully differential output structure, the output CM voltage should be V\({}_{\text{REF}}\) to enable a high CMRR and a wide output range. To maintain the output CM voltage at V\({}_{\text{REF}}\), a common-mode feedback (CMFB) circuit is adopted. The inverter-based differential-difference cascode input stage is cooperatively biased by the current sources MP\({}_{5-6}\) and MN\({}_{5-6}\). After biasing, the trans-conductances of the stacked NMOS and PMOS differential input pair are merged, which leads to amplification of the input signal with high G\({}_{\text{m}}\)/I\({}_{\text{d}}\) efficiency. In addition, the cascode amplifiers MN and P\({}_{7-10}\) are implemented to obtain high open-loop gain by increasing the impedance at nodes A-D. Assuming symmetric elements have the same small signal parameter, the impedance at nodes A-D is briefly expressed using the following equation:  
\[\text{R}_{\text{A-D}}\approx\frac{\text{gm}_{\text{p11}}}{\text{gm}_{\text{n1 1}}}\times\frac{\text{gm}_{\text{p,n7}}\times\text{r}_{\text{op,n1}}\times \text{r}_{\text{op,n7}}}{2}. \tag{3}\]  
When \(\text{gm}_{\text{P11}}=\text{gm}_{\text{N11}}\), Equation (3) can be re-expressed as the following equation:  
\[\text{R}_{\text{A-D}}\approx\frac{\text{gm}_{\text{p,n7}}\times\text{r}_{ \text{op,n1}}\times\text{r}_{\text{op,n7}}}{2}. \tag{4}\]  
Figure 7: Detailed schematic of the fully differential difference amplifier (FDDA) in the current-reused CFIA.