# Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication
## 3 Combined Min-Sum Algorithm
### Memory Blocks

In our proposed architecture, two memory blocks are utilized, one for the input LLR values (PMEM) and one for the check to variable messages (RMEM). Assume that all input LLRs and exchanged messages are quantized on \(w=4\) bits. PMEM memory is implemented by an input register that stores the input LLR values (prior values) or posterior values \(P_{n}\) from the previous layer. The memory is organized in \(n_{b}=68\) register memory blocks, denotes by \(P_{i}\) (\(i=1,2,...,n_{b}\)) corresponding to the number of columns of the base matrix. Each register memory block consists of \(Z=56\) memory

Figure 4: Proposed overall low-complexity high-throughput pipelined layered QC-LDPC decoder architecture. locations with \(w=4\) bits of word-length, i.e., \(Z\times w=224\) bits, and these stored 56 LLRs are read from register memory block in a single clock cycle. Thus, a total of \(Z\times w\times m_{b}=15\),232 bits of input memory is implemented in the proposed decoder. RDMEM memory is implemented as a dual port RAM, which stores \(Z=56\) compressed check to variable messages \(R_{m,n}\) for all \(L=m_{b}\) layers. With the proposed CNBP architecture, two minimum values of \((w-1)\) bit-width, a minimum index of bit-width \(\lceil log_{2}d_{c}\rceil\), and \(d_{c}\)-sign values are stored in RMEM for each decoding layer. Hence, a total of \(m_{b}\times Z\times(2\times(w-1)+\lceil log_{2}d_{c}\rceil+d_{c})=77\),280 bits of RMEM memory is required for all \(Z=56\) CNBPs. Therefore, the overall memory size used in our LDPC decoder is 92.512 kb. ### Switch Network

A switch network (SN) is an \(Z\)-input, \(Z\)-output hardware structure that can put the input signals in the arbitrary order at the output. For the implementation of the QC-LDPC decoder, the switch network is an essential module. The proposed decoder consists of \(d_{c}=19\) check node and \(d_{c}=19\) variable node circular shift networks. Each of them consists of \(Z\)\(w-\)bit inputs and \(Z\)\(w-\)bit outputs. The barrel shifters are used to implement the cyclic shift permutations according to the shift values provided by the cyclic shifter controllers. In this decoder, the switch networks are implemented with \(\lceil log_{2}Z\rceil\)-stage \(Z\times Z\) barrel shifters. There is no re-shuffling network in this architecture as we applied an \(H\)-matrix reformulation technique proposed in [33]. ### Variable Node Units

The proposed decoder consists of \(Z=56\) VNUs, which implement the variable node update step shown in Algorithm 1. The detailed architecture of a VNU in the proposed decoder is shown in Figure 5. Each VNU takes \(d_{c}\) inputs at bit-width \(w\) LLR message \(P_{n}^{i}[l-2]\) and the check-to-variable node message from RMEM memory, i.e., \(R_{m,n}^{i-1}[l]\). Each variable node message is computed by subtracting the corresponding check-to-variable node message from the LLR message, that is \(L_{m,n}^{i}[l]=P_{n}^{i}[l-2]-R_{m,n}^{i-1}[l]\). This operation is implemented by a \(w\)-bit subtractor, hence the value \(L_{m,n}^{i}[l]\) outputted by the VNU is quantized on \(w\) bits. It should be noted that the check-to-variable node message is stored in RMEM as a _compressed_ message of \(2(w-1)+\lceil log_{2}d_{c}\rceil+d_{c}=30\) bits. For a check node \(m\), the corresponding \(R_{m,n}\) message in _decompressed_ format is given by the \(d_{c}\) values \([R_{m,n_{1}},R_{m,n_{2}},...,R_{m,n_{d_{c}}}]\), where \(n_{1},n_{2},...,n_{d}c\) denote the variable nodes connected to \(m\). For a check node \(m\), the corresponding \(R_{m,n}\) message in _compressed_ format is given by the signs of the above \(d_{c}\)\(R_{m,n_{i}}\) messages, denoted by \(sign\), their first and second minimum, denoted by \(min1\) and \(min2\), and the index of the first minimum, denoted by \(indx\). Figure 6 shows an \(R_{m,n_{i}}\) message in decompressed and compressed format.