# Elliptic-Curve Crypto Processor for RFID Applications
## 2 Preliminaries
### PM Computation over \(Gf(2^{M})\)
Column four and five present the clock frequency (Freq, in MHz) and clock cycles (CCs), respectively. The time required to perform one PM computation, i.e., latency (in ms), is presented in column six. The area information for FPGAs (in terms of LUTs/FFs) and ASIC (in terms of # of gates/chip size in mm\({}^{2}\)) devices is shown in column seven. Finally, the last column (i.e., column eight) provides the power (in \(\mu\)W) information. #### 4.2.1 Comparison for ASIC Implementations (Described for RFID Applications)

As shown in Table 2, the ECC accelerator architectures (specifically tailored for RFID applications) are synthesized on different ASIC commercial technologies. Therefore, the area comparison for these architectures is not possible as we have used an FPGA while the ASIC platform is considered in [14; 19; 20; 21; 22] for implementations. Comparison with respect to other parameters, i.e., clock frequency, CCs, latency and power (where given in state-of-the-art implementations), is provided in the text that follows. **Comparison in terms of clock cycles:** All the RFID-related architectures, reported in [14; 19; 20; 21; 22], require more clock cycles as compared to the proposed accelerator architecture. This is due to the use of different architectural styles, i.e., \(8/16/32\)-bit (including datapath logic, memories, FFs), for the computation of PM operation. In our case, we have only used an 8-bit interface to load ECC parameters and coordinates of the initial point externally from EEPROM (shown in Figure 2), while the building blocks of our architecture (shift buffers/registers, arithmetic unit and register array) are \(m\)-bit length, where \(m\) is the key size, i.e., 163. Subsequently, the proposed accelerator architecture requires 105 (ratio of 27,5816 over 2627), 164 (ratio of 430,654 over 2627), 113 (ratio of 296,964 over 2627), 83.4 (ratio of 219,148 over 2627) and 190.3 (ratio of 500 k over 2627) times lower clock cycles as compared to [14; 19; 20; 21; 22], respectively. **Comparison in terms of clock frequency, latency and power:** We have provided a comparison with respect to operational clock frequency, latency and power parameters with our Kintex-7 FPGA implementation, as we have achieved low-power and low-latency values for this modern device (see Table 1 for implementation results). Concerning only the clock frequency for comparison, our accelerator architecture is 804.4 (ratio of 909 over 1.13), 67 (ratio of 909 over 13.56), 107 3.1 (ratio of 909 over 0.847), 2272.5 (ratio of 909 over 0.4) and 4.5 (ratio of 909 over 200) times faster as compared to the solutions described in [14; 19; 20; 21; 22], respectively. Furthermore, the accelerator architectures, described in [14; 19; 20; 21] over \(GF(2^{163})\) require 84,722 (ratio of 244 over 2.88 \(\times\) 10\({}^{-3}\)), 11,041.6 (ratio of 31.8 over 2.88 \(\times\) 10\({}^{-3}\)), 121,736.1 (ratio of 350.6 over 2.88 \(\times\) 10\({}^{-3}\)) and 190,208.3 (ratio of 547.8 over 2.88 \(\times\) 10\({}^{-3}\)) times higher computation time as compared to this work. Moreover, the architecture of [22] over \(GF(\mathbb{P}_{192})\) requires 868 (ratio of 2.50 over 2.88 \(\times\) 10\({}^{-3}\)) times higher computation time as compared to our PM architecture over \(GF(2^{163})\). It is important to note that the power comparison is only possible for solutions, described in [14; 21]. The remaining ECC architectures for RFID applications do not consider power for implementations, as shown in Table 2. The use of three \(m\)-bit shift registers in