## 2 Design Flow and the Overall DFE Architecture  
The design flow taken for the DFE targeted at LTE CA is diagrammed in Figure 2. The input of the DFE for LTE CA, modeled in Matlab, comes in from the ADC. The OFDM receiver (RX) was also modeled in Matlab. In the beginning, the output of the ADC is fed to the DFE Matlab model whose output is given to the OFDM receiver model, from which the error performance of the DFE functional model is obtained. After the error performance satisfies the design requirement specification, the DFE C++ functional model is constructed, which fulfills the same behavior as the DFE Matlab functional model. The discrepancy between the output of the Matlab model and that of the C++ model is made to be less than \(-200\) dB. The cycle-accurate model of the DFE is constructed subsequently, where the hardware architecture is taken into account, namely, the model closely mimics the hardware behavior, but the quantization is not applied yet. The deviation of the output of the cycle-accurate model from that of the C++ functional model is also rendered less than \(-200\) dB. Next, the bit-accurate model is constructed, which also closely resembles the hardware behavior and furthermore applies quantization that occurs in digital hardware. The bit-accurate DFE model is fed with the input and the resulting output is applied to the OFDM receiver model, from which the error performance is obtained. The word length and hardware structures are varied to meet the required performance. Finally, the HDL DFE model is constructed such that the model behaves exactly the same as the bit-accurate model, leading to the same output and zero error. The error performance is verified up  
Figure 1: Proposed receiver digital front-end (DFE) architecture. front in the bit-accurate model phase and hence the Verilog HDL model is synthesized and optimized to meet the other requirements, namely, speed and area. A signal path of the DFE for LTE CA consists of FIR1 (CIC filter), FIR3 (Farrow interpolator) [16], digital mixer, FIR4 (carrier aggregation filter or CAF), and FIR5 (channel selection filter or CSF), as exhibited in Figure 3. In order to process both the in-phase and quadrature signals, a pair of CIC filters and Farrow interpolators are employed [17]. A pair of digital mixers is used to facilitate CA. A quad of carrier aggregation filters and channel selection filters exist to accommodate in-phase and quadrature signals and two carriers (carrier1 and carrier 2) in CA. FIR2 shown as a shaded box in Figure 3 may serve as an antidooping filter in an attempt to partly cancel the drooping in the CIC filter and Farrow interpolator, which is not necessary in the current version. An RF phase-locked loop (PLL) reference clock can be set to 26 MHz, 39 MHz, 45.5 MHz, and 52 MHz for the overall DFE in Figure 3 and an active-low synchronous reset was used to initialize the register values. The mode select signal, casen, determines which frequency mode was adopted for the LTE DFE. Ten frequency modes or cases of 20 MHz, 15 MHz, 10 MHz, 5 MHz, 3 MHz, 1.4 MHz, 20 MHz + 20 MHz (CA), 20 MHz + 15 MHz (CA),  
Figure 3: Block diagram of the DFE top module. Figure 2: DFE design flow. 20 MHz + 10 MHz (CA), and 5 MHz + 5 MHz (CA) were supported. The ADC outputs, out_ADC_real and out_ADC_imag, were fed to the DFE circuitry as the in-phase and quadrature inputs, respectively. (2, 14) after out_ADC_real, for instance, denotes 2 integer bits and 14 fractional bits. Four outputs, in-phase and quadrature outputs for carrier1 and carrier2, exist for the four CSFs. Two auxiliary outputs, valid_end1 and valid_end2, of the DFE exist to represent the timing of the carrier1 and carrier2 outputs. Specifically, if one of the auxiliary outputs is high, the in-phase and quadrature outputs of carrier1 are regarded as valid. Likewise, if the other auxiliary output is high, the in-phase and quadrature outputs of carrier2 are deemed valid.