# Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices
## 2 Materials and Methods
### The Proposed Control Method  
In Figure 5, the subsystem FPGA is represented. As shown in Figure 3, the measured output current has been used to control the PWM generation. For this purpose, two comparators have been instantiated on the FPGA subsystem. Figure 4: Simulink model of the subsystem “BRIDGE”. When the output current oversteps the limits imposed by the comparators, the proposed control method sends a reset signal to synchronize the FSM that generates the PWM. The comparators must set up in order to limit the current in the Upper Bound (_UB_) and Lower Bound (_LB_). The lower bound is calculated as the minimum value of the load current (\(I_{0}\)) divided by the number of the inverters (N). The upper bound is calculated as the lower bound plus the difference of the maximum and minimum load current divided by the number of inverters, as shown in (7) and (8). \[LB=\frac{\min(I_{0})}{N} \tag{7}\]  
\[UB=\frac{\min(I_{0})}{N}+\frac{\max(I_{0})-\min(I_{0})}{N}=\frac{\max(I_{0})}{N} \tag{8}\]  
The minimum current value (\(\min(I_{0})\)) is the value of the initial simulation conditions: in this case it is 10 A. Meanwhile, the maximum current value (\(\max(I_{0})\)) can be expressed as the value of the initial conditions plus the current excursion on the load. These bounds are fixed to respect the normal behavior of the load current. In the setting of the comparators, their precision has been considered, estimating it as 10 mA. _UB_ and _LB_ have been rounded to the second decimal place to respect the precision of the comparators: the UB has been rounded down and the LB has been rounded up to consider a margin in respect to the maximum and minimum values. Due to the approximation, an increase in the PWM frequency can be seen because lower excursion of the current means higher oscillating frequency. To better understand this control, a two parallel-connected inverters system has been simulated with a current operating point of 10 A on the load, which means an output current of 5 A for each inverter. In normal behavior, the load current starts from 10 A and increases until 13 A, and then returns to 10 A, forming a triangle waveform (because of the input square wave) respecting the PWM period. Specifically, when the PWM is in the high logical state, the current increases, and when the PWM is in the low logical state, the current decreases. This means that each inverter has an increase of 1.5 A from the initial operating point and the comparators should be set up at 5.01 A for the lower bound and at 6.49 A for the upper bound. In Table 1, the configurations of the comparators for a number of parallel inverters ranging from 2 to 6 are reported. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & \multicolumn{5}{c}{**Number of Parallel Inverters**} \\ \cline{2-6}  & **2** & **3** & **4** & **5** & **6** \\ \hline
**LB [A]** & 5.01 & 3.34 & 2.51 & 2.01 & 1.67 \\ \hline
**UB [A]** & 6.49 & 4.33 & 3.24 & 2.59 & 2.16 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Comparator configurations. Figure 5: Simulink model of the subsystem FPGA. In Figure 6, the proposed control method is shown, and the model-based design, with the value of UB and LB related to the case of a system with two parallel-connected inverters (5.01 A and 6.49 A, respectively), is described. The FSM shown in Figure 7 has been used to generate the output PWM signal in the FPGA subsystem. In each inverter, the same FSM has been instanced. As shown in Figure 1, the designed inverter module is composed of the FPGA (low-power and logical part) which, through our algorithm, controls the power part (the BRIDGE). The algorithm is instanced in the FPGA, supplied with a voltage of 3.3 V, therefore, the two states correspond to the high logical level of 3.3 V in state S0 and to the low logical level 0 V in state S1.