# Review of Ka-Band Power Amplifier
## 3 Topologies
### Stacked FET
Figure 11: The n-layer stacked-FET amplifier circuit schematic diagram. In 2017, [PERSON] first proposed a high efficiency high gain 3-stacked PA without an output matching network by selecting appropriate transistor size (see Figure 12b) [61]. Fabricated in 90 nm CMOS process, the PA chip achieves gain of 17.2 dB and with an adaptive bias network. In 2018, [PERSON] proposed a stacked cascode broadband PA in 180 nm SiGe BiCMOS [62]. It is known that high-order matching networks can achieve broadband. This paper proposed a broadband PA based on 6 order LC input matching network and inter-stage neutral capacitance. The PA achieved P1 dB of 23.6 dBm and peak PAE of 31.7%. The fractional bandwidth of the PA is 63.3%, covering the whole Ka band (26.5 to 40 GHz). A fully integrated 3-stage stacked PA with neutralization technique for 5G applications was reported [63]. The neutralization technique keeps the output voltage of each transistor the same. The 3-stage stacked PA targeted 24.8 dBm output power and 17.5 dB gain at 38 GHz, adopting its 65 nm CMOS process. In 2020, [PERSON] first proposed a 2-stage 2-stacked HBT Class- F\({}^{-1}\)PA in the 130 nm SiGe BiCMOS [64]. The PA, composed of a Class-F driving stage and a Class-F\({}^{-1}\) power stage, achieved 30.1% PAE and 22.1 dB gain while maintaining output power higher than 21.2 dBm. A summary comparison with stacked-FET PA measurements is given in Table 3. \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline
**Ref** & **Tech** & **Frequency** & **Gain** & **Psat** & **P1 dB** & **PAEpeak** & **Area** & **Topology** \\  & **(GHz)** & **(dB)** & **(dBm)** & **(dBm)** & **(\%)** & **(mm\({}^{2}\))** & **Topology** \\ \hline
[59] & 28 nm CMOS & 28 & 10/13.6 & 10.1/15.1 & 14/18.6 & 36.5/43.3 & 0.28\# &
\begin{tabular}{c} 1-Stage CS \\ differential /2-stage stacked \\ \end{tabular} \\ \hline
[60] & 150 nm GaAs & 26–31 & 16.7 & 31.5 & / & 33 & 2.08 &
\begin{tabular}{c} 3-stage \\ stacked \\ \end{tabular} \\ \hline
[61] & 90 nm CMOS & 32 & 17.2 & 17.6 & 13.2 & 25.3 & 0.3 \# &
\begin{tabular}{c} 3-stage \\ stacked \\ \end{tabular} \\ \hline
[62] & \
\begin{tabular}{c} 180 nm SiGe \\ BiCMOS \\ \end{tabular} & 26.5–40 & 20.1 & 25.3 & 23.6 & 31.7 & 1.26 &
\begin{tabular}{c} cascade \\ stacked \\ \end{tabular} \\ \hline
[63] & 65 nm CMOS & 38 & 17.5 & 24.8 & 21.7 & 24.3 & 0.146 \# &
\begin{tabular}{c} 3-stage \\ stacked \\ \end{tabular} \\ \hline
[64] & \
\begin{tabular}{c} 130 nm \\ SiGe BiCMOS \\ \end{tabular} & 38 & 22.1 & 21.2 & 17.5 & 30.1 & 0.75 \({}^{\star}\) &
\begin{tabular}{c} 2-stage \\ Class-F\({}^{-1}\) \\ stacked \\ \end{tabular} \\ \hline \hline \end{tabular} \# Core area. * Without pad.  
\end{table} 
Table 3: Comparison of the measurement results with the stacked-FET PA.  
Figure 12: **(a)** 1-Stage 2-stack PA in 28 nm CMOS [59], **(b)** 3-stack PA in 90 nm CMOS [61]. Stacked-FET amplifiers connect transistors in series so that the output power of the power amplifier is high and has a compact area. As we can see from Table 3, the maximum area of the stacked-FET amplifier is 2.08 mm\({}^{2}\), using the GaAs process. Because the Si process has a higher degree of integration, the minimum core area of CMOS is only 0.146 mm\({}^{2}\) in the case of 3-stacked structures. The PAE of all the chips mentioned above basically exceeded 25%, with the highest reaching 43.4%, and the highest output power of GaAs and SiGe reached 31.5 and 25.3 dBm.