## 2 Materials and Methods
### Design and Implementation of swHPFM
#### 2.2.2 SPM Access Strategy Based on DMA  
In the structured grid axial compressor rotor algorithm, the array structure can be divided into two regions, namely, an outer layer and an inner layer, as illustrated in Figure 8. For many functions, such as the original quantity, residual, and source item, only the inner layer is calculated, without communicating the outer-layer data. Since the size of the SPM is only 64 KB, it is wasteful to transmit redundant data to the SPM. The proposed SPM access strategy (SAS) can effectively overcome this problem by only reading the valid data. When the SW26010 processor transfers data from its main memory to the its CPE' SPM of its CPE, it is limited in four aspects: space, transmission efficiency, mapping, and data dependence. The space limitation refers to the SPM space of the CPE being only 64 KB, and the user-available space in the LDM being limited to about 60 KB, namely, \(\text{LDM}_{size}\leq 60\) KB. The transmission efficiency limitation refers to the peak performance of the DMA access being reached only if the main memory address of the data is 128-byte-aligned, and its size being a multiple of 128 bytes. To ensure transmission  
Figure 8: Array structure. In the algorithm, the array structure can be divided into two regions, namely, an outer layer and an inner layer. Figure 7: Parallel computing of master-slave cores in CGs. The MPE is responsible for judging and controlling the whole simulation cycle, including calling the file reading module to read the grid data and communicating the boundary data by the MPI. The CPE is responsible for data parallel computing. efficiency, Block\({}_{size}\%\)128 = 0 should be guaranteed on the premise of the alignment of the main memory addresses. The mapping and data dependence limitations means that the amount of transferred data must guarantee the integrity of a kernel function. Blocking rules that are based on the space, transmission efficiency, mapping, and data dependence limitations are presented, as shown in Equation (4), in which \(\mathit{Total}_{size}\) denotes the size of the data to be transferred, and \(\mathit{core}\_{number}\) represents the total number of computing cores, whose value is 64, if all the slave cores are used. _Block_ denotes the total number of blocks that are required for transmission. \[Block=\left\lceil\frac{Total_{size}}{2^{10}\times{\mathit{LDM}_{size}}\times{ \mathrm{core}\_{number}}}\right\rceil \tag{4}\]  
To effectively utilize the space of the SPM, only the valid data of the inner layer can be transmitted; hence, the stride access method was used. First, when executing the data transmission, the stride on the main memory should be calculated, according to the outer and inner data sizes. For double-precision data, \(\mathit{Stride}\) = \(\mathit{Boundary}_{size}\times 8\) bytes, wherein \(\mathit{Boundary}_{size}\) denotes the number of boundary layers in the three-dimensional array of the fluid machinery algorithm. Then, \(\mathit{Carry}_{size}\), which denotes the amount of data that are passed by the DMA, is calculated via Equation (5), wherein \(\mathit{Valid}\_{Data_{size}}\) represents the size of the valid data of the inner part. \[\mathit{Carry}_{size}=\frac{Valid\_Data_{size}}{Block} \tag{5}\]  
Finally, the data on the CPE are tiled based on the mapping rules, as expressed in Equation (6). When CPE initiates a load/store data request, it is necessary to map each required datum to the main memory address. Our method enables continuous data blocks to be executed in the same time step. In Equation (6), Bias represents the offset of the main memory, \(\mathit{Block}_{index}\) denotes the index of the current data block, and \(\mathit{Thread}_{index}\) denotes the current number of threads of the CPE.