## 3 Compensation of Unbalanced Three-Phase 4-Wire Linear Systems
### ZSCC Compensator with Balanced Voltages  
Figure 3 shows the four-wire system proposed in Figure 2, but with only the ZSCC compensator and the equivalent network load downstream of the bus. Supposing that the voltages in the bus are balanced, the line-to-neutral voltages coincide with the positive-sequence voltages in Equation (10), where \(\underline{a}=e^{j120}\). \[\frac{V_{an}}{V_{an}}=\frac{V_{a+}}{V_{+}}\qquad\frac{V_{bm}}{V_{bn}}=\frac{ \underline{a}^{2}}{V_{+}}\qquad\frac{V_{cn}}{V_{cn}}=\frac{\underline{V}_{c+ }}{\underline{a}}\;V_{+} \tag{10}\]  
Figure 2: Proposal for compensation of an unbalanced three-phase four-wire linear system. Using the Fortescue transformation matrix, the line currents of the load expressed in symmetric components are determined by Equation (11). \[I_{\underline{dL}}=I_{\underline{dL}+}+I_{\underline{dL}-}+I_{\underline{dL}0} \quad\quad I_{\underline{hL}}=I_{\underline{bL}+}+I_{\underline{bL}-}+I_{ \underline{bL}0}\quad\quad I_{\underline{cL}}=I_{\underline{cL}+}+I_{ \underline{cL}-}+I_{\underline{cL}0} \tag{11}\]  
In addition, it is known that \(I_{\underline{aL}0}=I_{\underline{bL}0}=I_{\underline{cL}0}\). The objective of the ZSCC compensator is to compensate for \(I_{\underline{aL}0}\), \(I_{\underline{bL}0}\) and \(I_{\underline{cL}0}\), which are the zero-sequence currents of the respective loads. Figure 4a shows the vector diagram corresponding to phase A, where it is considered that the line-to-neutral voltage is \(V_{\underline{an}}=V_{\underline{an}}e^{i0}\) and that the zero-sequence current of the load is \(I_{\underline{aL}0}=I_{\underline{aL}0}e^{-i\beta I_{\underline{aL}0}}\). Therefore, the zero-sequence current to compensate will be equal to the zero-sequence current of the load but with the opposite sign. As \(I_{\underline{aL}0}\) is delayed with respect to \(V_{\underline{an}}\), the reactance \(X_{\underline{aw}}\) of the compensator must be capacitive (capacitor), hence the current of the compensator \(I_{\underline{aW}}\) is advanced \(+\frac{\pi}{2}\) with respect to \(V_{\underline{an}}\). Obviously, it is impossible to comply with \(I_{\underline{aW}}=-I_{\underline{aL}0}\), therefore, the compensator will consume an additional current \(I^{\prime}_{\underline{aW}}\), such that \(I^{\prime}_{\underline{aW}}=I_{\underline{aL}0}\,e^{i\beta I_{\underline{aL}0}}\) (see Figure 4b). It follows that \(I_{\underline{aW}}\) will be determined by Equation (12). \[I_{\underline{aW}}=I^{\prime}_{\underline{aW}}-I_{\underline{aL}0} \tag{12}\]  
Figure 4: Vector diagram referring to phase A. (**a**) Initial situation and (**b**) Compensated situation. Figure 3: Compensation of zero-sequence currents. If we consider phases B and C, taking into account that \(\underline{V_{bn}}=V_{bn}e^{-j120}\) and \(\underline{V_{cn}}=V_{cn}e^{j120}\) and performing the same procedure as in phase A, it is observed that \(\underline{I_{bL0}}\) is advanced with respect to \(\underline{V_{bn}}\), therefore, the reactance \(X_{bw}\) to be placed in phase B of the ZSCC compensator is inductive (coil), as seen in Figure 5a. On the other hand, \(\underline{I_{cL0}}\) is delayed with respect to \(\underline{V_{cn}}\), therefore, the reactance \(X_{cw}\) to be placed in phase C of the ZSCC compensator is capacitive (capacitor), as shown Figure 5b. That \(X_{aw}\), \(X_{bw}\) and \(X_{cw}\) do not have the same sign is evident since the arithmetic sum of the unbalanced powers of the compensator must be zero. In the same way as Equation (12), \(\underline{I_{bW}}\) and \(\underline{I_{cW}}\) are determined by Equation (13) and (14), respectively. \[\underline{I_{bW}}=I^{\prime}_{bW}-\underline{I_{bL0}} \tag{13}\]  
\[\underline{I_{cW}}=I^{\prime}_{cW}-\underline{I_{cL0}} \tag{14}\]  
If we join the vector diagrams of the three phases, the diagram in Figure 6 is obtained. It shows that currents \(I^{\prime}_{aW}\), \(I^{\prime}_{bW}\) and \(I^{\prime}_{cW}\) form a system of negative-sequence currents.