# A g\({}_{m}\)/I\({}_{\rm D}\)-Based Low-Power LNA for Ka-Band Applications
## 3 MOSFET Characterization and Simulation Results  
To include the effect of metal interconnections on FET performance early in the design process, the layout of the cascode is developed first [40]. The new component consists of the raw PDK FET device, an RCC (resistance, capacitance, and coupled capacitance) parasitic extraction of the low-level, thin metal layers, and an EM characterization of the high-level, thick metal layers to account for parasitic inductance. As indicated in expression (10), the value of NF\({}_{min}\) can be optimized [38]. Note that \(R_{G}\) is the gate resistance, \(R_{S}\) is the source resistance, \(f\) is the working frequency, and \(f_{T}\) is the unity current gain frequency. \[NF_{min}=1+K\cdot\sqrt{(g_{m}\cdot(R_{G}+R_{S}))}\cdot\frac{f}{f_{T}} \tag{10}\]  
The circuit is implemented using the GlobalFoundries 45 nm RFSOI PDK. The technology has seven copper (Cu) layers (M1-M3, C1, UA, OA, OB) and one aluminum (Al) layer with a thickness of 4.125 \(\upmu\)m. The RCC extraction is obtained using Calibre xRC extraction, \begin{table}
\begin{tabular}{c c c c} \hline
**Parameter** & **IC\({}_{1}\) = 0.48** & **IC\({}_{2}\) = 1.58** & **IC\({}_{3}\) = 4.92** \\ \hline V\({}_{GS}\) (mV) & 182 & 255 & 360 \\ \hline V\({}_{TH}\) (mV) & 94 & 88 & 76 \\ \hline I\({}_{D}\) (mA) & 0.67 & 2.2 & 6.8 \\ \hline g\({}_{m}\) (mS) & 12 & 28.7 & 55.2 \\ \hline g\({}_{m}\)/I\({}_{D}\) (S/A) & 18 & 13 & 8 \\ \hline W/L & 1.25 k & 1.25 k & 1.25 k \\ \hline NF\({}_{min}\) (dB) & 3.9 & 1.9 & 1.4 \\ \hline G\({}_{max}\) (dB) & 8.6 & 14.2 & 17 \\ \hline P\({}_{DC}\) (mW) & 0.6 & 1.98 & 6.2 \\ \hline L\({}_{source}\) (pH) & 180 & 135 & 104 \\ \hline L\({}_{gate}\) (pH) & 458 & 408 & 352 \\ \hline L\({}_{drain}\) (pH) & 500 & 500 & 500 \\ \hline FoM\({}_{IC}\) & 5.7 & 4.2 & 2 \\ \hline \end{tabular}
\end{table} 
Table 1: Values of the DC and AC parameters of the three selected ICs. and the EM characterization is obtained from EMX Planar 3D software. A staircase configuration is used to optimize the NF (\(NF_{min}\)) of this device by reducing parasitic capacitances and gate and source resistances. To facilitate DRC rules compliance and current flow, the FETs are divided into four instances. In addition, a C\({}_{GS}\) capacitor (C\({}_{st}\) in Figure 2) is added in metal layer C1 to improve device stability. The 3D view of the developed layout is presented in Figure 7.  
Once the MOSFET characterization is available the schematic in Figure 2 is set up and the values of the inductors needed are adjusted to compensate for the deviations introduced by the new RCC + EM characterization of the cascode MOSFETs. The gate inductor is adjusted to 409 pH to achieve input impedance matching, L\({}_{drain}\) is reduced to 313 pH, L\({}_{source}\) is reduced to 130 pH and substituted by a transmission line, and C\({}_{out}\) is adjusted to 24 fF to improve S\({}_{22}\). In addition, for proper AC grounding, a number of 1 pF shunt capacitors are added at the gate of M\({}_{CG}\). The final cascode layout is shown in Figure 8.  
A post-layout extraction of the S-parameters after EM simulation with all the passive components in the final circuit is performed to verify the LNA. The simulation results are presented in Figure 9, showing a gain of 11.4 dB and a NF of 3.8 dB at a central frequency of 28 GHz. Regarding the input and output return losses, an \(\mid\)S\({}_{11}\)\(\mid\) of 12.7 dB and an \(\mid\)S\({}_{22}\)\(\mid\) better than 10 dB are obtained. The LNA draws a total of 1.98 mW from a 0.9 V DC supply and occupies a core area of 0.723 \(\times\) 0.598 mm\({}^{2}\). As shown in Figure 9b, a two-tone simulation with 100 MHz spacing is conducted to verify the LNA's linearity, demonstrating a P-1 dB of 1.8 dBm and an IIP3 of \(-\)1 dBm. Table 2 presents a comparison with some of the most relevant state-of-the-art solutions. In [41], the authors develop a mm-wave multi-band LNA in 45 nm CMOS SOI using a three-stage differential cascode with interstage transformer-based matching networks to save area.