## 4 Experimental Results  
### Electrical Characterization  
The chip was fabricated in AMS \(0.35\)\(\mu\)m, \(3\) V 4M2P CMOS process and occupies a total area of \(3.1\times 2.7\) mm\({}^{2}\), pads included (see Figure 11). The preamplifier has a mid-band gain of about \(65\) dB, a high frequency cut-off of \(10.5\) kHz and a low-frequency cut-off tunable from \(1\) Hz to \(1\) kHz (see Figure 12). The input-referred noise, for \(f_{HP}=300\) Hz, is \(3.05\)\(\mu\)V, while the current consumption is \(4\)\(\mu\)A for the first stage, \(0.001\)\(\mu\)A and \(0.3\)\(\mu\)A for the \(G_{M}-C\) high-pass filter and the second amplifying  
Figure 11: Photo of the board adopted during the neuroscience experiments with rats and microphoto of the die. stage respectively, resulting in an overall \(NEF\) of \(2.5\). The input-referred power spectral density is shown in Figure 13 for different values of the \(G_{M}\)-\(C\) filter high-pass corner frequency. The plateau of \(-152\) dBV\({}^{2}\)/Hz corresponds to an input-referred noise of about (\(25\) nV)\({}^{2}\)/Hz, close to the expected value. Note that, for \(f_{HP}=300\) Hz, the \(1/f^{2}\) input-referred noise is mainly due to the \(G_{M}\)-\(C\) high-pass filter, as predicted by Equation (14). The common-mode rejection ratio (\(CMRR\)) and the power supply rejection ratio (\(PSRR\)) of the overall pre-amplifier are higher than \(65\) dB and \(50\) dB, respectively, while the cross-talk between adjacent channels due to the analog multiplexing is lower than \(-40\) dB. With regard to the AD converter, Figure 14 shows the results of static measurements. The converter features a DNL less than \(0.45\) LSB and an INL less than \(1\) LSB. Figure 15 shows the output spectrum of the ADC for a full-scale sine wave at \(1\) kHz frequency as input signal. The signal to noise plus distortion ratio (SNDR) is close to \(45\) dB, and the number of effective bit (ENOB) is thus about \(7.2\). Figure 12: Measured transfer function for different high-pass corner frequencies set by the \(G_{M}\)-\(C\) filter. Figure 13: Measured input-referred noise for different high pass-corner frequency. Considering the modulator, the frequency range covered by the VCO spans from \(310\) to \(460\) MHz (see Figure 16), allowing to lock the PLL loop to a frequency of \(400\) MHz frequency even with a large spread of tank component values and for sizable variations in power supply and temperature. When no data modulation is performed, the modulator phase noise (see Figure 17) is less than \(-123\) dBc/Hz at \(1\) MHz offset from the carrier. The phase noise spectrum has a typical low-pass shape, with \(50\) kHz cut-off frequency, since it is completely dominated by the charge-pump noise [34], while the VCO phase noise is much lower. The rms integral frequency noise of the modulator in the \(10\) Hz to \(10\) kHz band is less than \(3\) kHz (see the residual frequency FM in Figure 17), whereas the output spectrum of the synthesizer when acting as frequency modulator is depicted in Figure 18: more than \(98\%\) of the signal power is included in a \(3\) MHz band. Figure 14: Measured DNL and INL of the integrated AD converter. Figure 15: Spectrum of the ADC output for a \(3\) V sine wave at \(1\) kHz frequency as input signal. Figure 16: Oscillation frequency varying the analog tuning voltage and for different coarse tuning bit configuration. Figure 17: Measured phase noise of the phased-locked loop when the modulation is off.