# Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection
## 6 Clock and Data Recovery (CDR) Circuits
### CDR Examples  
Figure 42 shows a block diagram of a receiver, which includes CDR circuitry. First, a TIA converts and amplifies the input current-mode signal from PD into a voltage-mode signal. Subsequently, a clocked sampler such as a StrongArm latch retimes the voltage-mode signal with the sampling clock and also regenerates the signal to digital rail-to-rail swing. The operation principles and characterization of the clocked samplers can be found in [118]. As mentioned above, the frequency of the sampling clock should be well-aligned with the bit-rate of the incoming data. Depending on the applications and architectures, the sampling clock can be generated within the CDR circuit and can also be provided from a transmitter or a global clock generation circuit. The categorization and analysis on the clocking architecture are provided in [120; 121]. The relative phase of the sampled data and the clock is compared in the phase detector circuit. According to the relative phase information obtained from the phase detector, a phase adjusting circuit aligns the sampling timing to the optimum position, which is the center of the eye in Figure 41.  
The first CDR example to be introduced was presented in [44] by Luxtera Inc. in 2006. As shown in Figure 43, it consists of two negative feedback loops: one for the precise phase alignment and the  
Figure 41: Dependency of BER on sampling timing. (**a**) Qualitative explanation of BER degradation and (**b**) quantitative relation of BER with sampling timing using the formula in [105]. Figure 42: Simplified block diagram of a complete high-speed photodetecting receiver including CDR. other for the initial frequency acquisition. In order to avoid interference between the loops, a locking procedure that locks the loops sequentially is used in the CDR. At the initial stage, the frequency acquisition loop is enabled until a frequency lock detector determines that the frequency of the CDR clock is sufficiently close to the data rate of the incoming data using an externally provided reference frequency. Subsequently, the CDR enters the normal CDR operation state, where the lock detector activates the phase alignment loop and simultaneously disables the frequency acquisition loop in order to track the optimum sampling phase. Although the frequency acquisition loop is disabled in the normal operation, the residual frequency error can be tracked only with the phase alignment loop, as long as the frequency error is within the lock-in range [122; 123]. If a large frequency error out of the lock-in range is introduced, the lock detector re-enables the frequency acquisition loop. Notably, a single voltage-controlled oscillator (VCO) generating the CDR clock is shared between the two loops. Since the clock frequency generated by the VCO is proportional to the control voltage of the VCO, the phase of the clock is adjusted by changing the control voltage of the VCO for a short period of time, whereas the control voltage is changed permanently for the frequency acquisition. In the front-end, a limiting amplifier, which consists of five-stage cascaded gain stages, restores the low-swing signal from TIA to the logic level signal because this CDR uses a linear phase detection scheme that requires logical processing of data before recovery. The linear phase detection scheme provides predictable loop dynamics of the CDR as compared to the non-linear phase detection, which is represented by bang-bang phase detection or Alexander phase detection. However, a large amount of power is dissipated in this CDR structure owing to the limiting amplifier stage and the logic gate operating at a high data rate. Further detailed explanations and comparisons of the phase detecting schemes can be found in many publications, such as [104]. With the implementation of the CDR, the receiver achieves an exceptional sensitivity of \(-19.5\) dBm at the data rate of \(20\) Gb/s.