## 3 Proposed Instrumentation
### Test Execution and Monitoring  
The plot in Figure 3 shows the SEL monitoring approach. The power switches feeding the memory are disabled after a hold time following the detected SEL, allowing the monitoring of the memory behavior under the initial part of the SEL. The SEL detection is triggered when the current feeding the memory is over a given threshold value. This current value is reasonably large to ensure the memory function and not trigger false SEL, and, at the same time, small enough to always be triggered with actual SEL as soon as possible. The hold time is short enough to protect the circuit from unrecoverable damage. The power is enabled again after a cut time to recover the memory functionality and continue the test execution. Hold and cut times are configurable prior to the test run and depend on the experimental target. For this work, we defined 50 ms and 200 ms, respectively. The current threshold is also configurable and was set at 80 mA for most of the experiment. Using these configurable parameters, we carried out test runs at the end of the experiment with different variations to verify the full effect of the induced SELs. It is worth mentioning that the current threshold allowed additional tests without the need to physically access the setup inside the irradiation room, since it can be updated in real-time through the host computer using the available commands. Four test modes were used to explore realistic fault models: 1. standby, when no operations are performed, leaving the device in a powered-on state; 2. chip-enabled, similar to standby, but the memory chip-select is set (now, the memory controlling logic is powered); 3. static, the memory is written, and then, after a sufficient period, it is read back; and 4. dynamic, in which the memory is constantly written and read using two different algorithms and errors are reported when detected by read accesses. In particular, for the dynamic mode, we applied two algorithms discussed and tested in [10]: March C-, displayed in (1), and March Dynamic Stress, displayed in (2). In dynamic test mode, the algorithms constantly access the memory by employing read and write operations in order to emulate realistic applications and detect functional faults. In the Equations (1) and (2), the arrow indicates the addressing order (either '\(\uparrow\)' increasing or '\(\downarrow\)' decreasing), '\(w\)' (write), and '\(r\)' (read) indicates the operation, and the following Boolean number indicates the data background. The algorithms are composed of elements indicated by the arrow, followed by the operations in parenthesis. In our work, the operations enclosed by the parenthesis are performed in sequence in each memory address. When the addressing order is '\(\uparrow\)', the operations are executed from the address 0 to \(N\), and when it is '\(\downarrow\)', the operations are executed from the address \(N\) down to 0, with being \(N\) the highest memory address. Thus, e.g., the element '\(\uparrow\) (\(r0\), \(w1\))', goes from the first address up to the last one, applying a read operation (where a solid '0' data background is expected) followed by a write operation (using the solid '1') in each address. A bracket pair '\(\{\)\(\}\)' delimits a complete dynamic test algorithm. Figure 3: SEL monitoring method. The current threshold and hold/cut times are configurable. from the digital sensor. Every error reported by the test engine records the cycle counter at the error detection, the test identification, and the error data and address. The current logging is concurrently performed and reports the cycle counter and current values. The cycle counter operates with a clock period of 80 ns. In general, for memory testing, the SEL current threshold is defined before a test run and is not modified during the execution. However, dynamic threshold changing could be a required feature to support elaborated testing schemes in complex systems.