# A Multilevel Switched Capacitor Inverter with Reduced Components and Self-Balance
## 2 Design of Proposed SCMLI
### Capacitor Analysis  
The capacitor voltage of the proposed SCMLI can be balanced without the extra loops, which is crucial to generate the ideal voltage. The capacitors \(C_{1}\), \(C_{2}\), and \(C_{3}\) can be charged through a parallel charging mechanism in each cycle, as shown in Table 1 and Figure 3.  
To diminish the voltage ripple and improve the quality of the voltage waveform, the maximum voltage ripple of the capacitor is set to remain below 10% of the rated capacitor voltage. The voltage ripple is related to the continuous discharging amount of capacitor. It can be seen in Figure 4 that the points of \(u_{\text{ref}}\) intersect and that the carriers are set to \(t_{i}\) (\(i=1,2,3\ldots,12\)), which can be calculated by  
\[t_{i}=\frac{\arcsin\Bigl{(}\frac{i}{6M}\Bigr{)}}{2\pi f_{\text{o}}}, \tag{2}\]  
where \(f_{\text{o}}\) is the output frequency and \(M\) is set to 0.9. As is shown in Figure 4, the maximum discharging interval of the capacitors \(C_{1}\) and \(C_{2}\) is [\(t_{4}\)-\(t_{7}\)], whilst the maximum discharging interval of capacitor \(C_{3}\) is [\(t_{3}\)-\(t_{8}\)]. The instants \(t_{3}\), \(t_{4}\), \(t_{7}\), and \(t_{8}\) can be calculated by  
\[t_{3}=\frac{\arcsin\Bigl{(}\frac{1}{2M}\Bigr{)}}{2\pi f_{\text{o}}}, \tag{3}\]  
\[t_{4}=\frac{\arcsin\Bigl{(}\frac{2}{3M}\Bigr{)}}{2\pi f_{\text{o}}}, \tag{4}\]  
\[t_{7}=\frac{\pi-\arcsin\Bigl{(}\frac{2}{3M}\Bigr{)}}{2\pi f_{\text{o}}}, \tag{5}\]  
\[t_{8}=\frac{\pi-\arcsin\Bigl{(}\frac{1}{2M}\Bigr{)}}{2\pi f_{\text{o}}}, \tag{6}\]  
The capacitors \(C_{1}\) and \(C_{2}\) have the same discharge cycle and rated capacitor voltage. For the simplicity of analysis, only capacitor \(C_{1}\) is calculated. According to Equations (3)-(6), the maximum discharge amount of \(C_{1}\) and \(C_{3}\) can be obtained as  
\[\Delta Q_{1}=\int_{t_{4}}^{t_{7}}I_{\text{o}}\text{sin}(2\pi f_{\text{o}}t)dt, \tag{7}\]  
\[\Delta Q_{3}=\int_{t_{3}}^{t_{8}}I_{\text{o}}\text{sin}(2\pi f_{\text{o}}t)dt, \tag{8}\]  
where \(\Delta Q_{1}\) and \(\Delta Q_{3}\) are the maximum discharge amounts of \(C_{1}\) and \(C_{3}\), respectively, whilst \(I_{\text{o}}\) is the output current. Supposing that the coefficient defining maximum admissible voltage ripple is 0.1, then the capacitance can be calculated by  
\[C_{1}=C_{2}\geq\frac{\Delta Q_{1}}{0.1V_{\text{C1}}}, \tag{9}\]  
\begin{table}
\begin{tabular}{c c c} \hline
**M** & **Number of Levels** & **Output Voltage Levels** \\ \hline \(0<M\leq 1/6\) & 3 & \(\pm V_{\text{dc}},0\) \\ \(1/6<M\leq 1/3\) & 5 & \(\pm 2\ V_{\text{dc}},\pm V_{\text{dc}},0\) \\ \(1/3<M\leq 1/2\) & 7 & \(\pm 3\ V_{\text{dc}},\pm 2\ V_{\text{dc}},\pm V_{\text{dc}},0\) \\ \(1/2<M\leq 2/3\) & 9 & \(\pm 4\ V_{\text{dc}},\pm 3\ V_{\text{dc}},\pm 2\ V_{\text{dc}},\pm V_{\text{dc}},0\) \\ \(2/3<M\leq 5/6\) & 11 & \(\pm 5\ V_{\text{dc}},\pm 4\ V_{\text{dc}},\pm 3\ V_{\text{dc}},\pm 2\ V_{\text{dc}},\pm \Psi_{\text{dc}},0\) \\ \(5/6<M\leq 1\) & 13 & \(\pm 6\ V_{\text{dc}},\pm 5\ V_{\text{dc}},\pm 4\ V_{\text{dc}},\pm 3\ V_{\text{dc}},\pm 2 \ V_{\text{dc}},\pm V_{\text{dc}},0\) \\ \hline \end{tabular}
\end{table}
Table 2: The relationship between \(M\) and the output level.  
\[C_{3}\geq\frac{\Delta Q_{3}}{0.1V_{\rm C3}}, \tag{10}\]  
where \(V_{\rm C1}\) and \(V_{\rm C3}\) are the rated voltages of \(C_{1}\) and \(C_{3}\), respectively. The voltage ripple of the capacitors can be kept within an acceptable bound through a suitable capacitance.