## 4 Experimental Results and Analysis
### Computation Time on Galois Field  
In this subsection, we evaluate the decoding performance of each Galois field multiplication method. For the analysis, we choose to use the 128 bit SIMD instruction set to parallelize the Galois field multiplications.  
Let _COMPUTE_ represent the loop-based algorithm, _TL_ the table-based algorithm, and _VECTOR_ the parallelized SIMD implementation of the loop-based algorithm, for the Galois field operations. We estimate the performance of the three multiplication methods on real machines: an Intel _Core 2 quad Q9400_, an AMD _Phenom-X4 9550_, and the Cell BE, all of which are described in Table 2.  
Figure 10: Decoding time of HP, RRP, and DVP on the Cell BE with various coefficient matrix size; **(a)** 64 \(\times\) 64; **(b)** 128 \(\times\) 128; **(c)** 256 \(\times\) 256; and **(d)** 512 \(\times\) 512.  
Figure 11 presents the normalized performance of the _TL_ and _VECTOR_ methods over the _COMPUTE_ method, on each type of core. All the cores display speed-up factors greater than '1' compared to the _COMPUTE_ algorithm. In fact, _COMPUTE_ obviously incurs greater overhead than _TL_, thus _TL_ should be faster than _COMPUTE_. In addition, _VECTOR_, a parallelized method using SIMD instructions, is faster than all the other methods in processing 128 bit multiplications in parallel. The speed advantages in the PPE and SPE, obtained when using the _VECTOR_ algorithm, are significant and noticeable.  
In particular, the _VECTOR_ algorithm executed on the PPE shows a speed increase by a factor of 7.71. Although the PPE incorporates data cache, just as other generic processors, the PPE has less than half of L1 data cache size compared to the other generic processors. In addition, the L2 cache is much smaller compared to the cache of the other general purpose processors. Therefore, the _VECTOR_ algorithm exhibits a greater speed-up than other generic processors because it strongly depends on computation capability of SIMD execution unit. On the other hand, the SPE also has no data cache and merely has high-bandwidth embedded SRAM, referred to as the local store. However, it shows similar speed-up results compared to the other processors since its local store is as fast as the data caches.  
In Figure 12, we present the speed increase exhibited by _TL_ and _VECTOR_ with respect to _COMPUTE_, in the performance of actual decoding, using each method on the Cell BE architecture. Each method using DVP (PPE with 2 threads and SPE with 6 threads) is evaluated on the different core architecture, with varying data sizes between 16 KB and 1 MB, on a coefficient matrix of size 128. In real decoding processes, the speed increase of _TL_ is increased on PPE, but decreased on SPE compared with result on Figure 11. On the other hand, _VECTOR_ shows lower performance. As _TL_ depends on the performance of cache rather than computing power and performance of entire decoding process affected by cache, _TL_ shows the improved performance with PPE. However, with the absence of data cache, SPE shows lower performance using _TL_. Furthermore, _VECTOR_ requires computing power and entire decoding process has additional overhead compared to the single multiplication. Therefore, it represents lower speed-ups compared to the results shown on Figure 11.  
Despite of the low performance on small data size of SPE, SPE represents similar speed-ups when data size becomes large. Since SPE should be controlled by PPE to synchronize the decoding process between SPEs and transfer data from main memory, the SPE shows lower performance with small data size when the synchronization and data transfer overhead charges large proportion.  
From the results in Figure 12, we intuitively find the parallelized SIMD multiplication is the optimal solution to achieve high-performance decoding.  
Figure 11: Speed-up of Galois Field operation.