## 1 Introduction  
In the current era of multicore systems, core integration on System-on-Chip (SoC) devices has increased significantly due to ongoing research and development. However, this significant growth in the integration density of processing elements on System-on-Chip (SoC) devices raises significant performance and scalability concerns. The conventional bus-based architecture fails to satisfy the ever-increasing requirements for high-volume and high-speed communication imposed by the increasing number of cores. Therefore, looking for alternate approaches to overcome these constraints and raise the effectiveness of multicore systems is vital. Network-on-Chip (NoC) has surfaced as a viable solution [1, 2] to meet the current communication needs of the very large scale integration (VLSI) paradigm at the deep nanoscale level. Network on Chip comprises integrated processor cores (IP), a network interface (NI), routers, and the links that connect them. In NOC, cores employ a packet-based switching technique for communication through the routers with the help of interconnection links. The NoC topology signifies the physical organization of the architecture, defining the arrangement of routers and cores. Various standard topologies have been designed and employed for NoC depending on the interconnected networks. Out of these, the mesh topology is the most prominent [3; 4], featuring shorter paths between interconnected cores and high bisection width. These features make it suitable for use in numerous application mapping techniques. Due to its built-in parallelism and concurrent communication features, NoC is a popular computing engine for future many-core real-time systems [5]. Of the many key concerns in NoC designs, such as router architecture, topologies, and routing algorithms, the NoC's IP mapping issue has gained substantial attention [6]. IP mapping is an NP-hard combinatorial optimization issue [7; 8] that requires discovering the best way to map IPs onto a certain NoC architecture while attempting to meet predefined metrics [9]. The random placement of the IP core in NoC designs does not effectively influence the network's overall efficiency. Achieving high performance with low communication cost, latency, and throughput requires excellent or even optimal IP core mapping onto NoC systems. Because a mapping problem with n number of IPs leads to n! possible solutions, obtaining optimal solutions through exhaustive enumeration of all permutations is not practical. Consequently, more efficient methods must be discovered to overcome this issue. As it is an NP-Hard problem, there are no exact approaches to finding the solution in polynomial time. Even small-scale cases may need significant computing time [10]. Therefore, heuristic approaches are a practical and effective strategy for finding high-quality solutions [6; 11]. In addition, rapid growth in the amount of data represents a challenge to researchers and data scientists in analyzing and extracting relevant information. Swarm intelligence is increasingly used for many optimization tasks, including feature selection, a complex task essential for reducing data dimensionality in high-dimensional datasets [12]. Although various heuristic-based techniques have been employed to solve the NoC application mapping problem, they still solve the problem at the cost of certain factors, and all have certain drawbacks. The well known Ant Colony optimization method has disadvantages such as parameter sensitivity, sluggish convergence rate, and precociousness. Certain evolutionary algorithms suffer from longer computation times in certain cases, along with poor stability. Although heuristic searches are extensively employed to solve the IP mapping issue, they often have the drawback of quickly settling on a local optimum. However, efficient local and global search capabilities on the part of heuristic algorithms can help to achieve optimum results.