## 1 Introduction  
Jitter is becoming an important factor in high-speed serial links and integrated circuits (ICs). New high-speed serial data standards are emerging, such as universal serial bus (USB) and the peripheral components interconnect express (PCIE). These serial standards are more susceptible to jitter and greatly cause bit error rate (BER) [1; 2], and with them the requirement for effective compliance and characterization measurement [3; 4]. As data rates for new generation IC continue increases, jitter injected module (JIM) is intended to generate controllable jitter, simulating the test environment of high-data links and evaluating the performance of IC [5; 6; 7]. In addition, the synchronous trigger circuit is also concerned with the jitter between the signals; however, it only considers the rising edge of signals. Jitter generation can perform jitter tolerance measurements by generating quantized controllable jitter and injecting different types of jitter into the incoming high-speed data stream, detect the BER of the code stream transmitted in the channel, and verify the ability of the receiver clock data recovery (CDR) while maintaining performance levels [8; 9]. It can also be used to simulate the test environment of high-data links while evaluating the performance of the integrated circuit or system [5; 6; 7]; be used in CSC spread spectrum to reduce interference [10], improve the linearity of the CDR phase detector (PD) [11]; and measure the input of the phase interpolator for measuring the correlation jitter between data signal and CDR [12] and timing specifications for routers, gateways, or digital subscriber line access multiplexers (DSLAMs) [13]. In industry as well as in academia, the concept of jitter is varied (for a detailed introduction, please refer to [14; 15]). The definition used in this paper is time interval error (TIE) jitter. Jitter refers to the short-term variation of a digital signal from ideal positions at an important point in time. It can also refer to the deviation of an actual signal from the edge of an ideal signal, that is, the deviation of the time of the signal. Jitter can be characterized primarily by two typical jitters: random jitter (RJ) and deterministic jitter (DJ). DJ is bounded jitter, which can be divided into data-dependent jitter (DDJ), periodic jitter (PJ), and bounded uncorrelated jitter (BUJ). DDJ can be divided into duty cycle distortion (DCD) and intersymbol interference (ISI) [2; 16]. References [17; 18; 19] describe analog modulation, using two signal generators to implement clock and modulation signals that act as jitter profiles first, and then a jitter clock is generated that is used as an external clock source to provide a clock for a pattern generator. Finally, the jitter data pattern is generated by data pattern and jittery clock. This method is complicated by multiple instruments, and the analog modulation introduces uncontrollable noise, which affects the accuracy of the generated jittered data signal, and the method cannot select the data edge to generate jitter. The method in reference [20] uses \(\sum\Delta\) modulation, using a 1-bit ADC (analog-to-digital convert) or DTC (digital-to-time convert), and is first performed on the clock signal and the desired jitter profile and then by using the TMF (time mode filter) filters' quantization noise to generate jittery clock. Finally, the jittery clock signal and the data pattern are synthesized through a latch to obtain jittery data pattern. This method reduces the introduced noise via digital-analog combination, but the \(\sum\Delta\) modulation still generates quantization noise, so a low-pass filter is required for filtering noise, which is complex and limits the frequency of the resulting jitter. This method also cannot select the edge of the data pattern to generate jitter. The present paper generates jitter by employing a digital synthesis method where the jitter amplitude depends on the delay and the jitter frequency depends on the frequency of variable clock.