## 3 Operation of the Proposed Converter
### Operation Principle during the SIDO Mode  
The typical waveforms and current paths of the converter under SIDO mode are shown in Figures 4 and 5, assuming the SC is completely charged and its voltage is higher than V\({}_{\text{O}}\). The steps of operation during this mode can be described as follow: \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Parameters**} & **Standard Boost** & **Boost Converter** & **Boost Converter** & **Buck/Boost** & **Buck/Boost** & **SC-Stage in the** \\  & **Converter** & **in [17]** & **in [18]** & **Converter in [20]** & **Converter in [23]** & **Converter in [23]** & **Proposed MPC** \\ \hline Max. current stress on & & Q\({}_{\text{1}}\geq\text{1}\)3 to & Q\({}_{\text{2}}\geq\text{1}\)2 to & Q\({}_{\text{1}}\geq\text{4}\) Io & Q\({}_{\text{2}}\geq\text{2}\) Io & Q\({}_{\text{1}}\geq\text{4}\) Io & Q\({}_{\text{2}}\geq\text{2}\) Io \\ semiconductor switches & & Q\({}_{\text{2}}\geq\text{5}\) Io & Q\({}_{\text{4}}\geq\text{2}\) Io & Q\({}_{\text{2}}\geq\text{2}\) Io & Q\({}_{\text{2}}\geq\text{2}\) Io & Q\({}_{\text{2}}\geq\text{2}\) Io & Q\({}_{\text{2}}\geq\text{2}\) Io + I\({}_{\text{per}}\) + I\({}_{\text{batt}}\) \\ \hline \hline \end{tabular}  
* * Excluding filtering capacitors at input/output. ** Based on the implementation of the proposed phase-shifted carriers modulation technique described in Section 4 voltage range for the SC (Vmax and Vmin) depending on each topology to enable \(\approx\)93.75% utilization of REC of the SC (targeting the design at point C that enables 25% more utilization of the REC compared to traditional designs at point A). For fair comparisons between the single input and the multi-input converters considering devices count, sizing of the passive components, and current rating, only the SC-stage in the multi-input converter is considered in this comparison. According to Table 1, the proposed converter architecture through its SC-stage enabled the achievement of the targeted 25% enhancement for the utilization of SC, and hence size reduction by the same percentage without added penalty in the converter parameters in terms of component size, count, or current stress compared to other topologies presented. The switch S5 and the diode D2 of the proposed converter have higher current stress as it should handle the PV current in addition to both battery and SC currents during some modes of operations, but it is still lower current stress compared to the other topologies presented. In addition to this enhancement for the interfaced SC, the proposed MPC can also enable energy manipulation between battery and SC, which may be required in some HESS applications that require pre-charge/pre-discharge of SC before a scheduled peak power loading/generation.**  
\end{table} 
Table 1: Cont. * Step I: PV switch S5 is turned ON whilst the battery stage switch S3 is still in conduction from the previous cycle. The voltage across L3 is V\({}_{\text{PV}}\), and the voltage across L2 is V\({}_{\text{batt}}\), where the diode D2 is OFF;
* Step II: S5 is still in conduction, and D2 is still OFF when S3 is switched OFF. The voltage across the L2 becomes zero (shorted to ground via S4 and S5) whilst the voltage across L3 is still V\({}_{\text{PV}}\);
* Step III: S5 is switched OFF, and D2 starts conduction whilst S3 is still OFF. Therefore, the voltage across the L2 is (-VO), and the voltage across L3 is (V\({}_{\text{PV}}\)-V\({}_{\text{O}}\));
* Step IV: S5 is still OFF, and D2 is still ON when S3 is switched ON. Therefore, the voltage across the L2 is (V\({}_{\text{batt}}\)-V\({}_{\text{O}}\)), and the voltage across L3 is (V\({}_{\text{PV}}\)-V\({}_{\text{O}}\)).