## 2 Chip Architecture
### ISC Chip Architecture and Circuits  
Figure 2 shows the block diagram of the ISC chip. It consists of imaging pixel and LPR cell arrays, readout circuits for image signals including Vertical (V.) and Horizontal (H.) shift registers and readout circuits for communication signals including V- and H- address generators, analog multiplexer, and bandpass readout amplifiers. Figures 3(a,b) show the imager pixel and LPR cell, respectively. Both the pixel and LPR cell use four transistor circuits. In the LPR cell, the gate of transistors M\({}_{1}\) and M\({}_{2}\) are connected to constant bias sources. To respond to the light pulse charge, the transistor M1 is working in sub-threshold region. The detailed operation of the LPR cell is described in the next section. The operation of the imager pixel is same as that of the conventional 4-transistor active pixel with a pinned diode [9,10], which is controlled by signals, SL, RT and TX for pixel selection, resetting floating diffusion (FD) amplifiers and charge transfer from a photodiode to the FD, respectively. The detailed operation of the  
Figure 1: Image-Sensor-Based Optical Communication System. Figure 2: Architecture of the CMOS ISC chip (R: LPR cell, I: Image Pixel). CMOS image sensors using pinned photodiodes is described, for instance, in [11]. The connections of control signals and outputs for the imager pixel and LPR cells are shown in Figure 3(c). The imager pixels and LPR cells are assigned to odd and even rows, respectively. In order to read out 5 \(\times\) 5 LPR cell outputs at the same time, every five horizontal pixels are connected to five horizontal signal lines. If the \(i\)-th LPR cell is the center, the five LPR cells are selected by signals \(H_{i\text{-}2}\), \(H_{i\text{-}1}\), \(H_{i\text{-}}\), \(H_{i\text{-}1}\),and \(H_{i\text{-}2}\) from the H-address generator. The outputs are connected to a row selector as shown in Figure 4, where five row outputs of the LPR cells, D\({}_{\text{j-}2}\), D\({}_{\text{j-}1}\), D\({}_{\text{j}}\), D\({}_{\text{j+}1}\) and D\({}_{\text{j+}2}\), are selected by the V-address generator. To do this, the outputs of the V-address generator are activated to make the bus switches for LPR cell outputs, D\({}_{\text{j-}2}\), D\({}_{\text{j-}1}\), D\({}_{\text{j}}\), D\({}_{\text{j+}1}\) and D\({}_{\text{j+}2}\) on as shown in Figure 4. The selected 5 \(\times\)5 or 25-channel LPR cell outputs are connected to 25-channel bandpass amplifiers whose circuit schematic of one channel is shown in Figure 5.  
Figure 3: Imager Pixel and LPR Cells. The waveforms of each stage of a readout channel are shown in Figure 6. At the input, a load current source for a source follower is connected. The in-pixel transistor M3 in Figure 3(b) and the current source comprise a source follower when M4 is turned on. The output is amplified by a bandpass amplifier whose frequency response is shown in Figure 7. The source follower has a large offset deviation mainly due to the threshold voltage variation of M3. This may disturb the detection of the LPR signal of small amplitude if the source follower output including DC components is directly amplified. The input capacitor C\({}_{1}\) of the bandpass amplifier cuts the DC component of the input signal and the resulting small AC signal modulated for optical communication using, e.g., Manchester coding, is amplified by the gain given by the capacitor ratio, C\({}_{1}\)/C\({}_{2}\). In the bandpass amplifier, the high-pass cut-off frequency f\({}_{\mathrm{CHP}}\) in Figure 7 is given by 1/2\(\pi\)RC\({}_{2}\). The high-pass cut-off frequency has to be sufficiently lower than the carrier frequency to be used for spatial optical communication in order to pass the lower sideband of the modulated signals. For testing the designed ISC chip at the carrier frequency of 100 kHz to 1 MHz, the cutoff frequency is chosen as a few kHz.