# Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation
## 3 Parameter Extraction for Circuit Simulation
\(V_{dd}\) (= 1 V) is the DC bias of M3 DINV. Figure 6 shows the transient response characteristics of M3 DINV at \(T_{\rm ILD}=10\) and 100 nm. The load capacitance of M3 DINV is \(C_{L}=1\) fF. The symbols and lines show the results of the TCAD mixed-mode and HSPICE circuit simulations, respectively. The black square (solid line), the red circle (red dotted line), and the green triangle (green dotted line) show the input and output voltages both with and without the interface trap charge, respectively. The HSPICE circuit simulation results match the TCAD mixed-mode results. The change in capacitance due to the interface trap charge at the interface is not large, but the on-current level is greatly reduced by the interface trap charge; thus, it can be confirmed that the propagation delays due to the reduced current increases. Figure 7 shows the circuit diagram used for circuit simulation. Figure 7a-d are three stages fanout-3 ring oscillator [20], \(2\times 1\) MUX [21], D Flip-Flop [22], and 6T SRAM [23], respectively. Figure 6: (**a**) Transient response of M3 DINV at \(T_{\rm ILD}=10\) nm and (**b**) transient response of M3 DINV at \(T_{\rm ILD}=100\) nm. The symbols and lines denote the TCAD mixed-mode circuit simulation and HSPICE simulation results of M3 DINV, respectively. The black squares (and black solid lines), red circles (and red dash lines), and green triangles (and green dot lines) denote the input voltage \(V_{IN}\), and the output voltages \(V_{\rm OUT}\)s of M3 DINV both with and without the interface trap charges, respectively. Load capacitance \(C_{L}=1\) fF. Figure 7: Schematic used for circuit simulation. (**a**) Three stages fanout-3 ring oscillator, (**b**) 2 to 1 multiplexer, (**c**) D flip-flop, and (**d**) 6-transistor static random-access memory. Tables 3 and 4 show the power consumption, frequency, and propagation delay of three types of fanout-3 ring oscillators (FO3-RO) consisting of M3 DINVs both with and without interface trap charges, respectively. Tables 3 and 4 show the simulation results of the HSPICE circuit of the FO3-RO both with and without interface trap charges at \(T_{\text{ILD}}\) = 10 and 100 nm, respectively. Comparing FO3-ROs both with and without interface trap charges, the power consumption of FO3-ROs with interface trap charges is almost same as that without them. However, the operating frequency of FO3-ROs with interface trap charges is reduced by approximately 20 and 25% at \(T_{\text{ILD}}\) = 10 and 100 nm, respectively  
Figure 9 shows the butterfly curve result of the 6T SRAM [23] consisting of M3 DINVs. Figure 9a,b shows the retention and read static noise margins (SNMs) at \(T_{\text{ILD}}\) = 10 nm, respectively. Figure 9c,d shows the retention and read SNMs at \(T_{\text{ILD}}\) = 100 nm, respectively. The symbols and lines denote the SNMs of SRAM both with and without interface trap charges, respectively. The differences between \(T_{\text{ILD}}\) = 10 and 100 nm in the retention SNMs and the read SNMs of SRAM without interface trap charge are approximately 5 mV (1.8%) and 8 mV (7.14%), respectively. They reflect the trend in SNMs of planar 6T SRAM (neglecting any coupling between the P-type and N-type MOSFETs, almost equivalent with \(T_{\text{ILD}}\) = 100 nm) and 3D 6T SRAM (including coupling between the P-type and N-type MOSFETs, almost equivalent with \(T_{\text{ILD}}\) = 10 nm) [24]. The retention and read SNMs of the SRAM with \(T_{\text{ILD}}\) = 10 nm increased by 17 mV (6.4%) and decreased by 43 mV (35.8%) owing to the interface trap charges, respectively. The retention and read SNMs of SRAM with \(T_{\text{ILD}}\) = 100 nm increased by 10 mV (3.6%) and decreased by 40 mV (55%) due to the interface trap charges, respectively. Figure 8: Simulated transient results of a 2 \(\times\) 1 MUX consisting of M3 DINVs both with and without interface trap charges. The input voltages \(V_{A}\), \(V_{B}\), and \(V_{SEL}\), and the output voltage \(V_{OUTS}\) of the 2 \(\times\) 1 MUX both with and without interface trap charges.