# Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories
## 4 P/E Cycling  
The NAND flash memory tested in this experiment was a 3D CT TLC NAND flash chip, and the stored data were divided into eight states according to the V\({}_{th}\) of the storage cell. Ideally, the V\({}_{th}\) between adjacent states has a wide read margin, but the V\({}_{th}\) of adjacent states had overlapping regions in practice, and these overlapping regions were the source of error bits. It should be noted, due to the limited memory window for programming in a high-bit density NAND flash, such as TLC mode, overlapping regions do exist as shown in Figure 1b. The experimental procedure was as follows: firstly, we raised the temperature to the set value; then, we performed 3000 P/E cycles in randomly selected blocks in the chip, and several blocks were characterized to make sure that our results were reliable and stable; finally, the program/erase times of each P/E cycle was recorded in real-time, and the data were exported for analysis. ```
Definitions:
1:\(P_{n}\): the number of P/E cycles, be initialized to 0;
2: T: the temperature of experiment;
3:\(T_{target}\): the target temperature of experiment;
4:\(R_{count}\): the number of read cycles, be initialized to 0;
5: MAX \(R_{n}\): the maximum number of read cycles;
6:
7:
8: Raise T to \(T_{target}\);
9:else
10: Wait 5 min;
11:
12: Execute erase/program operation;
13:\(P_{count}\) + = 1;
14: Collect program time and erase time;
15:
16: Execute the dump operation;
17: Calculate RBER;
18:endif
19:
20:endfor
21: Change NAND block;
22:
23:While\(R_{count}\) \(\leq\) MAX \(R_{n}\)do
24: Execute sequential read operation on NAND block;
25:\(R_{count}\) + = 1;
26:if\(R_{count}\) == 1 \(\mid\)\(R_{count}\) % 100 == 0 then
27: Execute the dump operation;
28: Compare and calculate RBER;
29: Collect error classification;
30:endif
31:endwhile
32:endif
```  
**Algorithm 1**The process of experiment. Figure 2 shows the program time (\(t_{prog}\)) and the erase time (\(t_{erase}\)) when performing P/E cycling at various temperatures. In the case of \(t_{erase}\), it had a strong dependence on the temperature, but the effects of P/E cycles were negligible. The higher the temperature, the shorter \(t_{erase}\). However, \(t_{prog}\) depended on both P/E cycles and the temperature as shown in Figure 2b. For blocks after a certain number of P/E cycles, the higher ambient temperature of the NAND flash memory, the less time it took to execute the program operation. While at the same ambient temperature, \(t_{prog}\) decreased with P/E cycles. Thereby, we propose a temperature-dependent cycling program time (TCPT) model on the basis of following equation:  
\[t_{prog}=\alpha(T)\cdot n_{pe}+\beta(T) \tag{1}\]  
\[\alpha(T)=k_{1}\cdot T+k_{2},\ \beta(T)=k_{3}\cdot T+k_{4} \tag{2}\]  
\(T\), \(n_{pe}\), and \(t_{prog}\) are the temperature, P/E cycles, and program time, respectively. \(\alpha(T)\) and \(\beta(T)\) are the temperature-related functions with fitting parameters \(k_{n}\) (\(n\) = 1-4). As shown in Figure 2b, for blocks with higher than 100 P/E cycles, simulation curves agreed well with the experimental data, indicating that the model was effective at predicting the program latency in a wide temperature range. The values of the fitting parameters are listed in Table 1.  
Figure 3 shows the measured RBER when the P/E cycling was performed at different temperatures. No matter what the temperature we choose, RBER has an initially higher value at the fresh state with a decreasing trend in sub-200 P/E cycles, and then it increases during subsequent P/E cycling. Initial higher RBER could possibly come from the unstable initial stage after factory, and the gradually increased RBER can be explained by P/E cycling stress caused cell degradation. During the P/E cycling, defects generated in both the tunneling layer and CT layer and the stability of the NAND cells became worse. The most important thing was that RBER could be suppressed at high temperatures, while it degraded at cold temperatures.