## Instrumentation
### Detector  
A DSP \(+\) FPGA card (digital signal processor TMS320C6713 and field programmable gate array Xilinx XC3S1000, Innovative P25M; Innovative Integration, Simi Valley, CA, USA) resident in the data acquisition computer is used for digitization and detection analysis. Detection analysis begins after the analog signal out of the quad-amplifier has been digitized and error-corrected by the DSP \(+\) FPGA card. The digital signal is processed to determine if there is a candidate transmitter message. Candidate messages are identified by performing a cross-correlation of the received acoustic signals with a known square function that is the same length as a transmitter message, which is 1,860 samples long. It is equivalent to computing windowed energy with a window size of 1,860 samples. When a candidate message is present, the cross-correlation peaks at the beginning of the candidate message. The coding architecture for the detector consists of three components. The first component deals with the logic in the FPGA and is written in VHDL (VHSIC [Very High Speed Integrated Circuits] Hardware Description Language) and coded using the Xilinx ISE (Integrated Software Environment). The second component deals with the DSP and is coded in C using the Code Composer Studio IDE(Integrated Development Environment). The third component is the user interface incorporated with the host program to send and receive information from the DSP + FPGA PCI card and the user interface is coded in C++ using Visual Studio. Framework Logic is provided for the P25M board by Innovative Integration as a VHDL-based project in the Xilinx ISE environment. This framework provides an environment that connects the onboard analog-to-digital converter (ADC) and digital-to-analog converter (DAC) with the DSP. The framework logic allows for control of the ADC and DAC settings and also provides captured data to the DSP logic. Through the DSP logic, the user is able to process the data and have it transferred to the host computer. The cross-correlation calculations on the ADC data are handled in the FPGA logic using two multipliers--a FIFO (first-in first-out) and an accumulator. The raw data and cross-correlation data are then passed along to the DSP to identify the packets of data to save to a data file. The DSP code allows for the simple passing of ADC data from the FPGA to the host computer. Each packet of data processed by the DSP is 8,192 samples of raw data. Two thresholds are used for detection analysis. The first is a function of background noise, usually set 1.5 to 2 times the background noise. The second threshold is the number of samples above the first threshold with the cross-correlation values at these samples monotonically increasing. If these thresholds are met by the cross-correlation, then a candidate message is detected. To ensure the entire signal and any possible reflections are captured, one packet before this detection and three packets after this detection are sent over to the host PC to be saved, resulting in 40,980 samples or 16 ms in recording time per data file. The host code is a modification of the original host code provided by Innovative Integration. This code had premade dynamic-link libraries (DLLs) that make it easy to interact with the installed PCI board containing the FPGA and DSP. This code has been modified to save the data from the ADC in customized file format. Other changes made to the host program are the ability for the user to choose the location to which the data should be saved and the base waveform file name. This code provides a simple interface for the user to interact with the DSP + FPGA board. As an example, if we set the first threshold to twice that of background noise and the second threshold to 250, the correlation values corresponding to an impulse noise (Figure 5) are larger than the first threshold, but the number of samples above the first threshold with the correlation values monotonically increasing is only 152, smaller than the second threshold.