# Balancing the Leakage Currents in Nanometer CMOS Logic--A Challenging Goal
## 5 Analysis Results
As an attack strategy we have chosen Moments-Correlating DPA (MCDPA) [38], since this analysis technique does not depend on the choice of a particular leakage model and therefore allows a fair comparison. Please note that the same attack has also been successfully applied to experimental static power side-channel measurements in [12]. Our results are shown in Figure 11 for 40 nm technology and Figure 12 for 65 nm technology. To exclude any influences of the probabilistic nature of additional noise to the traces we have used exactly the same noise distribution for classic logic, BSPL and iBSPL. Although it is clearly more difficult to recover the key difference in the case of the BSPL circuit compared to regular logic cells, the SBoxes synthesized with iBSPL cells again provide the highest level of protection in this analysis. In fact, most of the attacks are not able to isolate the correct key difference (black) from the incorrect ones (grey) using the available number of traces. As a matter of fact, both gate leakage and subthreshold leakage are sensitive to the supply voltage and temperature. Hence, an iBSPL-based circuit should be powered through a built-in voltage regulator to prevent the attacker from exploiting the information by supply voltage manipulation. Furthermore, an internal temperature sensor should monitor the circuit temperature and put the chip in an idle mode, if its temperature exceeds \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Cells** & **Technology** & **Dynamic Energy (Average)** & **Static Energy (Average)** & **Latency (Average)** & **Latency (Average)** \\ \hline \multirow{2}{*}{BSPL} & 40 nm & +21.57\% & +195.46\% & +42.20\% & +6.13\% \\  & 65 nm & +35.04\% & +192.09\% & +69.98\% & +10.89\% \\ \hline \multirow{2}{*}{iBSPL} & 40 nm & +10.87\% & +109.65\% & +13.56\% & +1.65\% \\  & 65 nm & +3.86\% & +88.10\% & +12.92\% & +0.34\% \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Energy and latency overhead of the PRESENT SBox synthesized in BSPL and iBSPL cells compared to regular CMOS logic. the tolerable temperature. This is essential to avoid the adversary to operate the chip at a high temperature to better exploit the information leakage. Finally, to assess whether balancing the static power consumption in BSPL and iBSPL cells has any impact on the exploitability of their dynamic power consumption, we have performed MCDPA attacks on simulated dynamic power curves as well. The results are shown in Figure 13. Although BSPL seems to be more susceptible to such attacks, which makes sense due to the increased number of transistors switching for every input change, iBSPL seems to be not any more vulnerable than regular CMOS logic. As already discussed in [27] it makes sense to combine the static power balanced circuits with a masking scheme to provide protection against both types of power analysis adversaries, static and dynamic. Figure 9: Information theoretic analysis of Classic, BSPL and iBSPL logic gates. Figure 10: Information theoretic analysis of the PRESENT SBox synthesized in Classic, BSPL or iBSPL logic gates for different levels of process variations considered. Figure 11: Average of 500 MCDPA attacks using 5000 simulations of noisy SBox leakage currents for random inputs modeling different levels of intra-die process variations (40 nm). Figure 12: _Cont_.