## 3 Circuit Simulation and Experiment
Figure 12: The relationship between the final output voltage \(V_{f}\) and the sampling capacitance \(C_{h}\) when varying the diode junction capacitance \(C_{j}\) in the simulation software, where \(V_{m}=2\) V.  
The simulation results in Figure 13 show that the final output voltage \(V_{f}\) varies linearly with the peak voltage \(V_{m}\) at different equivalent capacitance \(C_{eq}\). The solid line represents the fitting curve obtained from (18), and the dots represent the simulation results. The horizontal axis represents the peak value of input pulse signal, while the vertical axis represents final voltage. Due to the existence of voltage step, there is a threshold for the measurement of the PDSH circuit, and the output of the PDSH circuit is 0 V when the peak voltage is less than the threshold. According to (18), the magnitude of the threshold is determined by the relative values of the equivalent capacitance \(C_{eq}\) and the sampling capacitance \(C_{h}\). The linear relationship between the final output voltage \(V_{f}\) and the peak voltage \(V_{m}\) is also confirmed in experiments using different types of diodes, as shown in Figure 14.  
Figures 13 and 14 verify that the final output voltage \(V_{f}\) and peak voltage \(V_{m}\) meet the (18) in both simulation and experiment, thus confirming the accuracy of the voltage step model. The voltage step error of the PDSH circuit can be corrected using the linear relationship between the final output voltage \(V_{f}\) and the peak voltage \(V_{m}\). Figure 15 illustrates the error between the correction value of the final output voltage \(V_{f}\) and the peak voltage \(V_{m}\). Figure 14: The experiment results of the variation of the final output voltages \(V_{f}\) with the peak values \(V_{m}\), where \(C_{h}\) = 51 pF. Figure 13: The simulation results of the variation of the final output voltages \(V_{f}\) with the peak values \(V_{m}\), where \(C_{h}\) = 50 pF. The horizontal axis represents the peak value of input pulse signal, while the vertical axis represents the error between peak value and correction value. Experimental results demonstrate that the maximum measurement error of the PDSH circuit after voltage step error correction is 19.87 mV. Therefore, Figure 15 shows that the calibration of voltage step error significantly improves the measurement accuracy of the PDSH circuit. The preceding section presents a derivation of the factors influencing the measurement speed of the PDSH circuit for nanosecond pulse. Additionally, the equivalent circuit model is established for the voltage step process in the PDSH circuit, effectively reducing voltage step errors. In this section, the simplified model derived in this paper for the measurement speed of the PDSH circuit yields a maximum error of 1.98 ns in simulation results and 2.03 ns in experimental results. In comparison to [PERSON] analysis of the dynamic performance of the PDSH circuit [21], as well as the circuit bandwidth analysis conducted by [PERSON] [22] and [PERSON] [23], the simplified model proposed in this study provides a clear and straightforward approach to determine the capability of the PDSH circuit in accurately measuring nanosecond pulse peak values. Furthermore, in order to mitigate voltage step errors, [PERSON] [24] and [PERSON] [10] analyzed the underlying causes of voltage step phenomena and proposed a CMOS PDSH circuit. While the CMOS PDSH circuit successfully avoids the generation of voltage step errors, some new issues are introduced, such as overshoot and pedestal voltage errors. In contrast, this study addresses voltage step errors by establishing an equivalent circuit model for the voltage step process in the PDSH circuit. Experimental results demonstrate that after voltage step error correction, the maximum measurement error of the PDSH circuit is reduced to 19.87 mV.