###### Abstract
The EPYC Threadripper processor node is available as a 4-chip System-in-Package (SiP) with 8 cores in each chip, fabricated in 14 nm lithography technology. However, these new approaches require multiple chips to be interconnected efficiently to ensure desired performance with low cost. Moreover, the existing multi-chip systems can have processing chips such as multicore chips, CPUs, GPUs or a heterogeneous mix of such chips [9] (e.g., AMD's Fusion Accelerated Processor Units (APUs)) depending upon desired functionality. Applications running in a heterogeneous environment comprising of CPU and GPU chips require low latency and energy efficient memory access mechanism to ensure high performance. In such systems, different kinds of traffic interactions exist such as bandwidth-sensitive memory accesses and latency-sensitive control or cache-coherency messages. To ensure high performance for such multicore multi-chip system, a cache coherency aware interconnect is highly desirable to enable multicast/broadcast-based cache coherency/control message transmission without degrading system performance as even a small proportion of such messages can substantially impact the overall performance [10]. Moreover, due to scaling up of the number of individual chips in the multi-chip system, (homogeneous or heterogeneous) shared resources such as interconnect and memory subsystem are going to become a dominant bottleneck. As the number of multicore processors in the system increase, the average throughput per core in the system decreases. This is because, for a uniform random distribution \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Dies Per Package** & **Cores Per Die** & **Die Dimension (X \(\times\) Y) (mm)** & **Good Die Per Wafer** & **Yield (\%)** \\ \hline
1 & 64 & \(20\times 20\) & 86 & 60.8 \\
2 & 32 & \(20\times 10\) & 232 & 77.5 \\
4 & 16 & \(10\times 10\) & 545 & 87.9 \\
8 & 8 & \(10\times 5\) & 1186 & 93.7 \\
16 & 4 & \(5\times 5\) & 2471 & 96.8 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Yield improvement with chip size reduction. of hence it creates a bottleneck for the inter-chip interconnection fabric. The same phenomenon is observed for a decrease in localization of data packets within the same chip [11]. In traditional multi-chip platforms, inter-chip communication happens through C4 bumps or through Peripheral Component Interconnect (PCI) or PCI express (PCIe) which is a common local I/O bus standard. Recent trends according to the ITRS [6] predicts that the pitch of the wired I/O interconnects, solder bumps or pads in ICs is not scaling as fast as the gate lengths or pitch of on-chip interconnects. This implies a gap in density and performance of traditional I/O systems relative to on-chip interconnections. The wiring complexity of both on-chip and off-chip interconnects exacerbates the problem by posing design challenges, crosstalk, and signal integrity issues [12]. Moreover, typically intra-chip and inter-chip interconnections are designed separately to provide design flexibility and modular design approach. However, switching between protocols is necessary if the off-chip communication protocol is different from the on-chip one incurring overheads in inter-chip data transfer. Moreover, each of the heterogeneous components might operate at different voltages and frequencies and therefore will need voltage/frequency conversion while communicating with memory modules or other chips in the system. Therefore, we need an energy efficient, seamless, scalable interconnection network, which can address homogeneous, heterogeneous and memory integration challenges for different multi-chip environments/systems. While metallic inter-chip interconnects are not scaling well, research in recent years have brought to light many emerging alternative interconnect solutions such as inter-chip photonics [13], vertically integrated monolithic 3D ICs [14] or silicon interposers [15; 16] as solutions to the off-chip interconnection challenges.