# Dynamic Information Flow Tracking: Taxonomy, Challenges, and Opportunities
## 2 Background
### Tag Storage  
In gate-level DIFT design, the tag is stored in an extra gate logic. For micro-architecture-level DIFT design [21; 22; 28], the tag is often stored in registers or memory of a modern processor. Therefore, the register files and memory need to be extended to support tags. In addition, the processor pipeline stages need to be modified to transfer the tag in parallel  
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \# & **Tag** & **Type** & **CFI** & **DFI** & **NI** & **Performance** & **Hardware** \\ \hline
[23] & 4 bit/register & HW-In core & ✓ & \(\times\) & \(\times\) & - & - \\
[27] & 1 bit/word & HW-Off Core & \(\times\) & \(\times\) & ✓ & 1–3.7\% & Unspecified \\
[28] & 4 bit/word & HW-Off Core & \(\times\) & \(\times\) & ✓ & 0.79\% & 16\% BRAM, 7.64\% LUTs \\
[24; 25] & 1 bit/word & HW-Off core & ✓ & ✓ & \(\times\) & 1.6\% & 60\% BRAM, 28.36\% LUTs \\
[34] & 1 bit/tens of bytes & HW-Off core & ✓ & ✓ & \(\times\) & 50–60\% & 4–5\% Memory, 5\% Power \\
[32] & 1 bit/byte & HW-Inter Core & \(\times\) & \(\times\) & ✓ & 9.7-12\% & Unspecified \\
[19] & bus request tag & HW-IP wrapper & \(\times\) & ✓ & \(\times\) & Unspecified & 31\% Area \\
[20] & variable tag size & HW-SoC DIFT & \(\times\) & \(\times\) & ✓ & 7.25\% & Unspecified \\
[31] & Extra tag register & HW-SW Codesign & \(\times\) & ✓ & \(\times\) & 0–100\% & Unspecified \\
[41] & 1 bit/word & HW-SW Codesign & ✓ & \(\times\) & \(\times\) & Unspecified & 3.125\% Memory \\
[33] & pointer-sized & HW-SW Codesign & ✓ & ✓ & ✓ & 10–40\% & Unspecified \\ tag/word & tag/word & & ✓ & ✓ & 5\% & 15.4\% logic elements \\
[29] & single bit & HW-Tagged Memory & ✓ & ✓ & ✓ & 25.2\% & 6.25\% Memory \\
[30] & 2 bit & HW-Tagged Memory & ✓ & ✓ & ✓ & 25.2\% & 6.25\% Memory \\ \hline \hline \end{tabular}
\end{table}
Table 1: \(Cont.\)with the instructions being executed. There are two basic types of tag storage, normal storage and shadow storage. For normal storage, the register files need to be extended to support the corresponding tags. Thus, the normal memory can be partitioned into normal data memory and tag memory. Extra access controls on tag memory should be enforced to prevent illegal tag modifications. In shadow storage, extra storage are allocated to store tags. Normal instructions cannot access the storage, as the shadow storage is not connected to the data bus. However, this type of storage is difficult to expand, especially after deployment. For system-on-chip (SoC)-level DIFT design, tag storage can be allocated to either IP wrappers or other dedicated hardware components and is often customized based on the target IP.  
For software-based DIFT methods, the tag is stored in the same storage space as other data. For instance, the DIFT solution proposed in [11] stores the tag adjacent to data for spatial locality. This may cause large performance and storage overheads, as the tag fetching requires extra clock cycles for memory access. Even adopting byte-level tags introduces a 25% storage overhead on a 32-bit processor. In addition, extra security checks need to be performed on tag storage to prevent illegal tag accesses and modifications.  
For a software and hardware co-design-based DIFT framework, the tag storage can use normal storage or shadow storage. New instructions may be inserted to support the tag management [33] and to access the shadow storage [35].