## 1 Introduction  
Machine learning and the integrated circuit (IC) manufacturing industry have advanced rapidly in the last decade. The expansion of the IC industry especially has led to a new pursuit of efficiency in all aspects. Verification is one of the core steps in the chip design and production process, so traditional inspection methods needed to be replaced by new automated inspection means urgently. Therefore, efficient verification techniques based on computer vision or machine learning algorithms have received a lot of attention in recent years [1; 2; 3; 4]. In the proposed process of such verification techniques, their validity is mostly derived from the high-quality ICs' images being utilized as a test set. The goal of this paper is to suggest an algorithm for the effective classification of low-quality ICs' images in order to reduce the stringent requirements on samples and provide a reliable, valid, and easily accessible database for the subsequent verification procedures. With annual semiconductor sales exceeding USD 400 billion for the first time in 2018 [5], the need for reliability verification in the semiconductor industry has reached a new pinnacle, and there are two common types of defect objects in reliability verification, which are unintentional defects and malicious hardware Trojans (HTs). Unintentional defects can be caused by immature processes that result in low yields or poor processing environments, such as solder joint offsets and stained spots. These defects are not the original design intent, so they can be solved by improving the process and production environment. In contrast, HTs are human-implanted and can exist in two important stages of IC production, including design and manufacturing. Even more problematic is the fact that today's IC production is a global collaborative model, with various stages of the industry scattered around the globe, making it easy for HTs to break in. HTs can leak secret information, disable ICs, or cause other catastrophic consequences [6, 7, 8]. In 2009, a statistical approach was proposed with the idea of constructing a series of fingerprints based on the path delay of gold chips to verify whether the chips contain HTs by comparing the delay parameters of the chips with the fingerprints [9]. With the booming development of computer vision, vision-based techniques are one of the hot research topics in the last decade. A machine learning algorithm based on power analysis was proposed in [10], which aims to obtain the hardware Trojan infection algorithm and use machine learning to detect hardware Trojan implantation. One HT classification method is called Hardware Trojan Learning Analysis (ATLAS) [11], which identifies HT-infected circuits using a gradient boosting (GB) model on data from the gate-level netlist (GLN) stage. A method is proposed to extract the basic features of digital circuits using Haar features and augment their features with the AdaBoost learning algorithm to generate strong classifiers [12]. Two hardware Trojan detection algorithms based on support vector machine (SVM)-supervised machine learning were designed [13,14]. In [15], the intrinsic nature of many cores providing feedback to the online learning algorithm based on the core information and its behavior with incoming packets was designed for a real-time online learning method. As a latecomer, deep learning has also made a lot of achievements in this field in recent years. A deep learning (DL) class of ML was proposed based on extracting the raw circuit features and feeding them into a DL model (deep stacking autoencoder) that extracts the features which contribute to HT detection [16]. A novel, golden, reference-free HT detection method named GNN4 TJ [17] was proposed in the register transfer level (RTL) based on a graph neural network (GNN).