# Real-Time Method and Implementation of Head-Wave Extraction for Ultrasonic Imaging While Drilling
## 5 Test and Analysis
### Laboratory Tests  
We then performed various tests on the function correctness, high temperature resistance, and system performance of the echo reception pre-processing module in our laboratory. Figure 10 shows the actual image and test results of the reception pre-processing module during the temperature resistance test. Figure 10 reveals that our module exhibited good temperature resistance; it could work stably for a long time in a downhole environment of 150 \({}^{\circ}\)C. In the test, the gain control program of CPLD is set to a constant gain output mode, and the gain is fixed to 36 dB. According to the test results of Figure 10, the error between the measured gain and the theoretical value is small, indicating that the circuit performance is basically stable at different temperatures.  
In the quantitative response test, the gain control program of FPGA is set to the constant gain output mode, and the gain size is set by the program, which is manually adjusted during the test. The frequency of the fixed sinusoidal input signal is 250 kHz.  
Table 1 is the data record and calculation results of the quantitative response test. It can be seen from the table that the measured gain of the circuit is basically consistent with the theoretical gain under different gain conditions, and the maximum relative error is \(-2.75\%\). It can be shown that the pre-processing module has a stable programmable dynamic amplification function. Under different gain modes, the amplification accuracy meets the design requirements of downhole applications.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Theoretical Gain** & **Input** & **Output** & **Ratio** & **Actual Gain** & **Relative Error** \\
**(dB)** & **(mV)** & **(mV)** & **Ratio** & **(dB)** & **(\%)** \\ \hline \(-4\) & 1000 & 640 & 0.64 & \(-3.89\) & \(-2.75\) \\ \(6\) & 500 & 984 & 1.96 & 5.88 & \(-2.0\) \\ \(16\) & 300 & 1984 & 6.61 & 16.41 & 2.55 \\ \(26\) & 300 & 6125 & 20.41 & 26.20 & 0.77 \\ \(36\) & 100 & 6602 & 66.02 & 36.39 & 1.09 \\ \(46\) & 20 & 3725 & 186.25 & 45.40 & \(-1.30\) \\ \(56\) & 10 & 6175 & 617.50 & 55.81 & \(-0.33\) \\ \(66\) & 5 & 9414 & 1882.8 & 65.50 & \(-0.76\) \\ \hline \hline \end{tabular}
\end{table}
Table 1: The performance test results of the pre-processing module.  
Figure 10: Actual image and test result of the echo reception pre-processing module. (**a**) Actual image; (**b**) Gain at different temperatures.  
In another test, 10 different depths of waveform data are used to test the circuit and program performance, as shown in Figure 11. The first wave and arrival time extraction algorithms are run using FPGA (instrument used) and DSP (28377D) circuits, respectively, and the results are compared. The Table 2 data show that the results calculated by the two platforms are relatively close, indicating the reliability of the algorithm. The FPGA runs the algorithm for 14 ms per waveform, the DSP is 18 ms per waveform, and the efficiency of the FPGA is higher. So, the FPGA is used as the controller to process the collected data in the actual instrument, which improves the efficiency of real-time data processing.