# A 60 GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers
###### Abstract  
In this article, we show a 60 GS/s two-stage 8 \(\times\) 8 time-interleaved sampling circuit, where the second-stage nonlinearity can be controlled by using the voltage that optimizes the static distortions of the sampler. A calibration algorithm can extract the nonlinear contributions of the stages and compensate for them by setting the optimal bias voltage. This can also be used to cancel the front-end nonlinear effects. The sampler was verified by implementing it in TSMC 5 nm FinFET, and a calibration system in a Pulse Amplitude Modulation transceiver, detecting and minimizing the nonlinearities, is presented. The optimum voltage biasing of the sampler was obtained by co-simulating the circuit with the linearity calibration loop implemented in Verilog-A. The histogram of the sampled signal at the slicer input is shown before and after the calibration to show the improvement in the sampled eye opening. Moreover, the resulting bias is equal to the one that maximizes the total harmonic distortion in transient simulations with a 1 GHz input signal, obtaining a minimum of 48.5 dB of total harmonic distortion across different PVT conditions.  
PAM-8; SerDes receivers; track-and-hold; time-interleaved; linearity +
Footnote †: journal: _Electronics_  
_Acticle_  
A 60 GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers  
_Electronics_  
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Electron_  
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approaching the ideal case for 50 dB, meaning this value should be a target for the analog circuit design.  
To maximize the system performance, the THD, especially of critical blocks such as the track and hold (TH) of time-interleaved (TI) receivers, needs to be optimized through calibration as a consequence of the low circuit linearity across PVT in scaled technology nodes. This solution is normally adopted in the reduction in distortions derived from the interleaved channels mismatches [9; 10]. In the literature, the calibration of static distortion is rare [11; 12], and no co-simulation nor indepth modeling of AFE components is introduced in the system simulation. The scope of this paper is to find a TI-TH circuit capable of achieving through calibration a receiver THD of the order of 50 dB across different PVT conditions to maximize the performance of a PAM-8 receiver (RX). Here, we show the TI sampler presented in [8] using an improved and simpler calibration loop compared to the cited one, where the complexity scales with the number of nonnegligible residual ISI pre- and post-cursors, and a gain error can introduce a component that does not let the system set to the desired value. The proposed loop uses an algorithm that eliminates the errors given by the gain and residual ISI while having a fixed complexity. Furthermore, this improved calibration was implemented in cadence virtuoso with a Verilog-A model, and its performance was verified via co-simulation with the analog circuit, while in [8] MATLAB, modeling of the analog was used.  
This work is divided into three major sections. First, in Section 2, the implemented track-and-hold circuit is described, and its linear behavior with the control voltage is shown. Then, the calibration feedback loop is propose,d and its analytical functioning is described in Section 3. Lastly, Virtuoso co-simulation of the transistor-level TH circuit and Verilog-A receiver model were performed, and the simulation results are presented in Section 4.  
Figure 1: (a) MSE and (b) SER with the varying of SNR for various THD [8].