# R&D of an Innovative OFDM Communication Payload for Small-Size AUV
## 2 Systems and Methods
### Doppler Estimation and Compensation Implementation
#### 2.3.3 Agile and Low Computational Overhead Doppler Compensation Approach  
Especially for small-size AUV platforms, the high calculation and storage requirements on CPU result in expensive system costs, which is not conductive to the small-size AUV applications. To address the above limitations, an UWA OFDM payload is designed to enable agile Doppler compensation with low computational overhead. The payload adopts AD9954 chip to generate the control signal of clock frequency, then the sampling rate at the ADC process can be regulated in real time through adjusting the clock frequency of the external clock source of Inter-IC Sound (I2S) bus. The Doppler compensation is accomplished while the acquisition of data segment is performed. The transmission and reception of signal sequence are realized by a UWA OFDM modem with the architecture presented in Figure 2. The hardware module of the UWA OFDM system mainly consists of STM32F407 processor, signal processing circuit as well as power management unit. Note that, the STM32F407 chip as a core processor witha 32-bit ARM Cortex-M4 core is used exclusively to control timers for data acquisition and processing. In the process of signal acquisition, the CPU drives the audio acquisition chip WM8978 through the I2S bus interface to perform the ADC process of received signal. The selection of the external clock as the \(I2S\_CLK\) clock source provides the feasibility for the real-time adjustment of the sampling rate. The sampling rate for the ADC acquisition process can be expressed as  
\[F_{s}=\frac{I2S\_CLK}{2\cdot W_{f}\cdot(2\cdot I2 SDIV+ODD)\cdot 8}, \tag{22}\]  
where \(I2S\_CLK\) is the clock frequency of the external clock, \(W_{f}\) denotes the frame width of the channel and \(I2 SDIV\) denotes the value of the I2S linear prescaler with the range of [25]. \(ODD\) is the odd factor for the linear prescaler, and its value is 0 or 1. As described in (22), the adjustable sampling rates can be acquired through the different combinations of \(I2S\_CLK\), \(I2 SDIV\) and \(ODD\). In conclusion, the core of the sampling rate adjustment can be converted into generating an external clock control signal. The highly integrated DDS chip AD9954 is felicitously used as a programmable clock generator to produce an external clock control signal due to its ability to generate up to 200 MHz analog sine wave, fast frequency conversion and high frequency resolution through inputting control words in the serial I/O port. The frequency of the AD9954 output signal can be expressed as  
\[F_{o}=\left\{ \begin{array}{ll}FTW\cdot F_{sys}/2^{32},&0\leq FTW\leq 2^{31} \\ F_{sys}\cdot(1-\left(FTW/2^{32}\right)),&2^{31}<FTW<2^{32}-1\end{array} \right.. \tag{23}\]  
where \(F_{sys}\) is the system clock, \(FTW\) is the frequency conversion bytes, and \(2^{32}\) denotes the capacity of the accumulator. In the processing of signal reception, firstly, the pre-amplifier and bandpass filter are adopted to complete the functions of amplification, filtering and denoising for the received OFDM packets. Secondly, the CPU applies the Doppler factor to calculate the required sampling rate with respect to Doppler correction, further obtains the frequency of external clock control signal according to the (22). Afterwards, the CPU drives the AD9954 chip to generate the clock control signal with corresponding frequency through inputting control words into the serial I/O port; the Doppler compensation is completed synchronously in the acquisition process of the received signal. Thirdly, after acquisition of the OFDM symbol, the CP that can resist the inter symbol interference is removed in order to facilitate the OFDM symbol demodulation. Fourthly, FFT operation is carried out to accomplish the transformation from the time domain signal to the frequency domain signal, and then the mapped sequences located at the corresponding frequency band of OFDM symbol are  
Figure 2: The block chart of the OFDM receiver. isolated for differential quadrature phase shift keying (DQPSK) demodulation.