## 3 SRAM Characteristics  
All the experimental data are obtained from SRAMs designed and implemented on a 65-nm commercial CMOS technology using standard Vt transistors with a nominal supply voltage of V\({}_{\text{DD}}\) = 1.2 V. The memory block contains a total of 16,384 cells, distributed in 256 rows and 64 columns. The used SRAM cell is the standard 6T-cell (Figure 1a). Its layout is a full-custom design, following the so-called structured or wide-layout design [30]. The layout structure can be seen in Figure 1b and the sizes of the transistors are W\({}_{\text{n}}\) = W\({}_{\text{p}}\) = 0.15 um. This layout type provides better parameter variation control by applying design for manufacturing techniques, which include avoiding bends in the diffusion regions by having all nMOS and pMOS transistors of the same width, and setting all poly lines aligned and placed in the same direction [31]. The cell power supply can be controlled so that they can be shut down and set to nominal voltage. This makes it possible to power down the memory, power it up again, and read cell values. In Figure 2, a diagram of the structure of SRAM memory used in this paper is shown.  
Figure 2: Diagram of the SRAM memory. It has a total of 16,384 cells, structured in 256 rows and 64 columns.  
Cells are written and read through pass-transistors, which are controlled by a word-line signal (WL) common to all cells in the same row (Figure 2). When pass transistors are activated, cells are connected to the bit-lines (BL and BLB), which are common to all cells in the same column (Figure 2). Each set of 8 columns is connected to a sense-amplifier to read cell contents, so we have a total of 8 sense amplifiers for the 64 columns. The memory has a row decoder to allow selecting the actual row to be accessed. It also has a column decoder to select the column that needs to be connected to the sense amplifier, and thus read out. All control signals are generated from a control unit, which can be externally controlled by a logic analyzer. The memory uses words of eight bits to write or read data.  
Simulations were performed with the Spectre simulator using Monte Carlo analysis to take into account parameter variations. Moreover, a set of 16,384 simulations were performed to have the same amount of data as from experimental results. Start-up process simulations require pass transistors to always be cut-off (for instance, simulations of the parameter proposed in Section 5). In this case, the cell is isolated from the rest of the circuit and can be simulated alone without affecting the results. We corroborated this hypothesis and performed all cell start-up simulations with one single cell. This is an important advantage in terms of simulation time of the Monte Carlo analysis described in Section 5. However, other 6T-cell parameters, like for instance the word-line voltage margin [32] parameter shown in Table 1, need to be computed with the cell being accessed through pass transistors. In this case, simulations were performed considering all the involved circuitry.  
The memory cell was characterized computing some parameters of interest. Table 1 summarizes these results.  
In this paper, the SRAM memory is intended to be used as PUF. Therefore, in addition to cell related parameters, other PUF related parameters have been obtained following the usual definitions, which can be found in [5; 33], and are summarized in Table 2.  
Reliability was obtained over a temperature range of \(-20\)\({}^{\circ}\)C to \(+60\)\({}^{\circ}\)C. Another parameter that can be calculated is bit error rate (BER), which will be further discussed in Section 4.