# Sound Activity Monitor Circuit for Low Power Consumption of Always-On Microphone Applications
## 2 Proposed Approach and Detailed Circuit
### Detail Circuits  
Figure 7 shows a detailed circuit diagram of the source follower block (SF). The device that functions as a source follower is MP\({}_{10}\) and transmits an AC signal from the input (_VIN_) to the output (_VOUIT_). The DC voltage on the _VIN_ is set to \(V_{b}\) via high resistance (R\({}_{\text{bsf}}\)). The high-resistance value of the resistor (R\({}_{\text{bsf}}\)) is implemented as a pseudo-resistor using a PMOS. In the source follower (MP\({}_{10}\)), current flows as much as \(I_{LP}\) in the low power mode and as much as (\(I_{LP}+I_{NP}\)) in the normal power mode. When the _WUIP_ is _LOW_, it becomes low power mode, and the current \(I_{LP}\) mirrored by MN\({}_{12}\) and MN\({}_{10}\) flows through the source follower MP\({}_{10}\). Since the switch SW\({}_{\text{np}}\) is turned off, the switch SW\({}_{\text{lp}}\) is turned on, and the MOS MN\({}_{11}\) is turned off, no additional current is added to the source follower MP\({}_{10}\). When the _WUIP_ is _HIGH_, it becomes normal power mode, and the current \(I_{LP}\) mirrored by MN\({}_{12}\) and MN\({}_{10}\) is added to the current flowing through the source follower MP\({}_{10}\). In addition, since the switch SW\({}_{\text{np}}\) is turned on and the switch SW\({}_{\text{lp}}\) is turned off, current \(I_{NP}\) mirrored through MN\({}_{13}\) and MN\({}_{11}\) is added to the source follower MP\({}_{10}\). Eventually, in normal power mode, a current of (\(I_{LP}+I_{NP}\)) flows through the MOS MP\({}_{10}\). Figure 8 shows the detailed circuit of the OA block. The OA consists of a high-pass filter block (HPF), an amplification block (Ainv), and a common-mode feedback block (CMFB). The high-pass filter (HPF) removes DC and low-frequency components input from SF and is implemented with MIM capacitor (C\({}_{20}\)) and PMOS-based pseudo-resistor (R\({}_{\text{oa}}\)). The amplification block (Ainv) is implemented as an inverter-based amplification architecture. Inverter-based amplifiers are commonly used because of their simple structure and good efficiency [16; 17]. While inverter-based amplifiers may have poor linearity for  
Figure 6: Architecture approach 5: After a predetermined delay time (\(T_{gl}\)) elapses after the sound input disappears at \(t_{2}\), a falling edge at \(t_{3}\) is expressed as a wakeup signal (_WUIP_). Figure 7: Detailed circuit diagram of the source follower stage. large inputs, nonlinearity during amplification is not an issue in SAM applications. Current \(I_{\alpha}\) is supplied from the top of Ainv and flows through a differential inverter-based amplifier to NMOS (MN\({}_{21}\)) functioning as common-mode feedback control. When the common-mode voltage of OA output is greater than \(VDD/2\), \(Vcmfb\) increases and the current flow of NMOS improves, so that the common-mode voltage of OA output decreases. On the contrary, when the common-mode voltage of the OA output is less than the \(VDD/2\), the \(Vcmfb\) decreases and the current flow of the NMOS (MN\({}_{21}\)) decreases, thereby increasing the common-mode voltage of the OA output. Figure 9 shows the detailed circuit of the AMP2 block. The AMP2 performs additional amplification, low cutoff-frequency adjustment, and common-mode signal removal. AMP2 has a charge amplifier structure, and the amplification ratio is defined as a ratio of \(\rm C_{in}/C_{f}\)[18; 19; 20]. The low cutoff frequency (\(f_{c,low}\)) is determined by the feedback resistor \(\rm R_{f}\) and the feedback capacitor \(\rm C_{f}\). as in Equation (3). The low cutoff frequency can be changed by adjusting the feedback resistance. Since the feedback resistor \(\rm R_{f}\) needs to have a large resistance value, it is implemented as a PMOS-based pseudo-resistor. The internal amplifier (AMP_AMP2) of the second amplifier (AMP2) consists of a two-stage amplifier structure and a common-mode feedback block. \[f_{c,low}=1/[2\pi\;\rm R_{f}\times C_{f}] \tag{3}\]  
Figure 10 shows the detailed circuit of the CMP block.