# Maintaining Secure Level on Symmetric Encryption under Quantum Attack
###### Abstract  
Quantum computing is currently being researched in many countries, and if implemented in the near future, it may pose a threat to existing encryption standards. In the quantum computer environment, asymmetric encryption can be solved by Shor's Algorithm in polynomial time, and the difficulty of breaking symmetric encryption using brute force is reduced from \(N\) times to square root \(N\) times by Grover's Algorithm. We take the Advanced Encryption Standard as the theme and increase the key length from the original standard 192 bits and 256 bits to 384 bits and 512 bits, respectively, in order to maintain the security level of AES 192/256 under the environment of quantum computing, so we propose the key schedule of AES 384/512, and write the software in C++ on FPGA. The experimental results show that our scheme can achieve Level III and Level V security levels in a quantum computer attack environment. In addition to increasing the length of the key, we use the LUT method in the process of writing SubBytes to replace the array and speed up the computation to optimize the execution speed. In addition, the proposed scheme is still based on 128-bit computing blocks, rather than computing blocks in larger blocks.  
quantum computing; [PERSON]'s algorithm; [PERSON]'s algorithm; advanced encryption standard; strict avalanche criterion; Rijndael algorithm +
Footnote †: journal: Applied  
002320  
original key length will be cut in half; that is, the highest security level of AES 256 will become as low as AES 128.  
In order to ensure that the AES [7] maintains the original security level in the quantum computer environment, we decided to expand according to [PERSON]'s theory and try to increase the encryption key to maintain the original security strength. We use Field Programmable Gate Array (FPGA) to achieve verification, and the overall algorithm acceleration and optimization to achieve the effect of hardware accelerated computing.  
We propose the AES algorithm for countering quantum computing to improve the security of the algorithm. The following are the main contributions of this paper:  
* To follow the framework of the original AES algorithm, and extend the key length to 384 bits and 512 bits in order to resist the threat introduced by quantum computers, and do an avalanche test on C++ software to prove the security of the AES 384 bits and 512 bits key.
* Improve the speed of AES encryption and decryption, write the AES algorithm into FPGA by using hardware description language, make use of its instruction parallelization characteristics, make parallel calculations, accelerate the encryption and decryption calculation, and achieve a hardware acceleration effect.
* Use different calculation structures and increase the amount of calculation per unit of time by adding registers, and use the space-for-time method for optimization.  
In Section 2, a literature review on the state of quantum computing, AES, etc. will be undertaken. In Section 3, the basic architecture and calculation method proposed in this paper will be described. In Section 4, it is described how to implement the proposed method on FPGA, which involves implementation performance comparison and simulation implementation screen. Finally, the conclusion of this work is stated in Section 5.