## 5 Conclusions  
A novel design approach of a Petri net-based concurrent control system is proposed in this paper. The method is oriented toward effective realization of the system in an FPGA device. To achieve this, the system is optimized by authors' techniques. In particular, the sequential and combinational parts of the system are reduced and optimized. The proposed design flow includes all the necessary steps that are required to implement the concurrent control system within the programmable device. Firstly, the system is modeled by an interpreted Petri net, which is transformed into the Verilog hardware description language. The optimization of the design is performed by reducing the redundant sequential logic and further functional decomposition. Finally, the system is implemented within an FPGA. \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multicolumn{3}{c}{**Benchmarks**} & \multicolumn{6}{c}{**Number of Blocks**} \\ \hline
**Name** & **In** & **Out** & **Decomp** & **ABC** & **DAOmap** & **DDBDD** & \begin{tabular}{c} **BDS-PGA** \\ **2.0** \\ \end{tabular}  & **MultiDec** & **PdekBDD** \\ \hline
5 xp1 & 7 & 10 & 13 & 23 & & 19 & 14 & 14 & 10 \\
The efficiency of the proposed technique was verified experimentally. To perform this, a real-life example of a photovoltaic concurrent control system was designed and optimized. The obtained results indicate a high reduction in the number of utilized logic blocks compared to the traditional solutions. A photovoltaic system designed and optimized with the presented method requires 91 LUTs and 114 flip-flops, while the classical approach utilized 126 LUTs and 114 FFs. This means that the number of LUTs was decreased by 28%, which is a very good result. It should be underlined that thanks to the introduced sequential reduction in the system, the number of logic blocks significantly decreased, while the number of flip-flops remained unchanged. Although the experimental results confirm the high efficiency of the proposed technique, there are also limitations of the presented method. First of all, the introduced sequential optimization idea can be applied only to the systems operating in a single-clock domain. This means that all registers of the design ought to be oscillated by the same clock. Nevertheless, let us point out that such a situation is usual in the case of FPGA-oriented systems. Furthermore, the presented method involves Petri net theory. Although the modeling of the system with Petri net is relatively easy and comfortable, it requires specific knowledge from the designer, especially in terms of concurrent systems oriented toward implementation within FPGA devices. Finally, the proposed method assumes the transformation of the system to the Verilog code and further optimization of the sequential and combinational parts. At this moment, the above mechanisms are semi-automated. There exists the transformation of the Petri net-based system to the Verilog code (within the authors' Hippo system), but it ought to be supplemented by adequate input and output signals. Similarly, there is a tool for functional decomposition, PdekBDD (developed by the authors). Nevertheless, the authors of this paper plan to extend their tools, especially with such optimistic experimental results. Plans for the future include further development of the proposed idea. In particular, it is planned to apply the verification of the system at the early prototyping stage. Such an examination may help avoid mistakes caused by the designer that are usually detected during the synthesis process. Furthermore, the presented photovoltaic system is going to be extended to the farms of panels. As shown by the preliminary research results, the traditional realization permits the implementation of 503 controllers of solar panels, while the presented technique allows for the realization of 696 cells within the single FPGA. Therefore, it is planned to perform more complex research in order to confirm such a high efficiency of the proposed technique. Conceptualization, R.W. and A.O.