# Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers
## 3 Related Works
### Parallel Implementation of CTR Mode of Operation on the NEON Engine
#### 4.2.2 HIGHT-CTR Optimization
In Round 3, the round function for \(X_{2,0}\) and \(X_{2,1}\) words is performed, but both can be pre-computed due to a fixed nonce part, so round operations for Round 3 are not required. Steps 9-10 is the process of simply increasing the counter value. In Step 11, the round keys to be used in Round 4 and Round 5 are loaded into vector registers. In Round 4, the pre-computed \(X_{3,0}\) words are affected by the variable counter, so the round function is required. In Steps 12-18, round operations are performed for \(X_{3,0}\) word. In Step 19, finally, the pre-computed value to be used in Round 6 and Round 7 are loaded into the vector registers. In Round 5, all of the words \(X_{4,0}\) and \(X_{4,1}\) words are affected by the counter,so round operations are performed normally. In Round 6, the round function for \(X_{5,0}\) word is performed with the pre-computed \(X_{5,1}\) word. In Steps 20-25, the round function is completed only by \(ROL_{1}\), modular addition, and \(XOR\) operations through pre-computed \(X_{5,1}\) words. In Round 7, the round function is performed using the last pre-computed value. In the later implementation, it is the same as the proposed parallel implementation of revised CHAM-64/128. Through the proposed parallel implementation of revised CHAM-CTR mode optimization, some round operations up until seven rounds were bypassed, and maximum encryptions were processed simultaneously. ## 5 Evaluation

We evaluate the proposed data parallelism technique and CTR mode optimization technique on Raspberry Pi 4B [21], which is the most popular embedded device. Raspberry Pi 4B supports up to 4 GB with an upgraded internal memory compared to previous models, and supports ARM Cortex-A72, a 64-bit processor as a microcontroller unit. We compiled using aarch64-linux-gnu-gcc in the Ubuntu 19.10 environment, and VS Codium was used as the development environment. To our knowledge, there are no studies on the optimization of CTR mode using LEA, HIGHT, and revised CHAM in ARMv8 architecture. Thus, we compare the performance of our work and the existing optimization works [9; 10] of LEA, HIGHT, and revised CHAM, respectively, in ARMv8 architecture. ### Parallel Implementation of LEA-CTR Mode on the NEON Engine

Table 5 shows the performance comparison of LEA parallel implementation. [PERSON] et al. [9] presented parallel implementation of LEA utilizing NEON engine in Apple A7 and Apple A9. A total of 24 encryptions were performed simultaneously using all vector registers, but a transpose process was required to apply data parallelism. We ported the [PERSON] et al. 's implementation to our target device, ARM Cortex-A72, for fair situations. Our Work 1 is the proposed parallel implementation of LEA, and processes 24 encryptions simultaneously as shown in [9]. We reduce the computational overheads by automatically applying the transpose operation when loading data from memory to vector registers and storing data from vector register to memory. By removing the transpose operation process, our Work 1 shows 3.09%, 2.77%, and 2.63% performance improvement in LEA-128, LEA-192, and LEA-256, respectively, than the results ported to our target platform [9]. Until now, this is an optimization work of block ciphers. IoT devices send massive amounts of data in the real world, so the mode of operation should be applied when encrypted. Among them, the CTR mode is widely used in the current industry. Our Work 2 is the proposed CTR mode optimization technique. Our Work 2 performs 24 encryptions simultaneously. In particular, CTR mode optimization was applied, so that the round operations of the initial few rounds were processed only by simply looking up the pre-computation table, thereby reducing the computational overheads on the round operations efficiently. Moreover, by pre-computing one round more than the previous work [7]. Our Work 2 in LEA-128, LEA-192, and LEA-256 achieved 8.76%, 6.39%, and 5.82% performance improvement respectively over [9].