## 3 Proposed SQRD Algorithm with a Novel Modified RVD
### Proposed Modified RVD
As for the non-zero element \(\mathbf{S}_{7,6}\) (i.e., \(r_{3,A}^{I}\)), it will be zeroed with processing engine#4 when \(r_{4,4}\) of \(\mathbf{R}^{c}\) is obtained. ### Processing Engines

Figures 5-7 present the block diagram of the proposed processing engines (PEs). All these PEs comprise three kinds of CORDIC-based Givens rotation structures: processing unit a (PUa), processing unit b (PUb), and processing unit c (PUc). Figure 8 shows their architecture based on CORDIC module, all of which can work in vectoring mode (VM) and rotation mode (RM). In VM, elimination operation is applied to the leading column elements of the current input matrix; in RM, the rotation directions generated in the vectoring mode are retrieved for rotation operations of subsequent elements. PUa processes paired complex rows, zeroing the lower one and turning the upper one into a real number [25]. In vectoring mode, the upper-left three CORDIC modules are used, whereas in rotation mode, all of the four CORDIC modules are occupied. PUb is used for the paired rows of which the leading elements are real numbers and the rest are complex numbers. In vectoring mode, the upper CORDIC module processes the leading paired real elements and zeros the lower one; in rotation mode, the two CORDIC modules are used for the rotation operations of the following complex elements. PEc with only one CORDIC module processes paired real inputs. As these processing units have different processing delays (PUa has two CORDIC stages, whereas PUb and PUc have one), delay elements (DEs) are used to align the data sequences for the subsequent processing unit or sorting module. Among all these Givens rotation structures, all the processing units in PE#1 and PE#2, PUa#4 in PE#3, and PUc#2 in PE#4 are used for SCGR, whereas PUc#3 in PE#3 and PUc#4 in PE#4 are dedicated to RGR. The processing units with multiplexers (MUXs) at input and output ports, including PUb#2 and PUc#2-4, form the time-sharing Givens rotation structure, which will be introduced in the next subsection. Figure 4: The processing diagram of real Givens rotation (RGR) for \(4\times 4\) MIMO system. ### Time-Sharing Givens Rotation Structure

During the SCGR procedure for \(4\times 4\) MIMO system described above, the current input matrix of PE#2 is of the size \(3\times 3\) after the elimination process of the first column of \(\mathbf{H}\) with PE#1. With the sorting procedures inserted in the column elimination processes, the Givens rotation structures of PE#2 process only three columns and stay in an idle state for one clock cycle within every processing cycle (four clock cycles). Similarly, the periods of idle state of PE#3 and PE#4 in every processing cycles are two and three clock cycles, respectively. As a result, quite a few processing units are operating in an unsaturated state, which causes inefficiency of the SQRD hardware architecture. On the other hand, the elimination process of non-zero elements below the diagonal of \(\mathbf{S}\) in RGR needs many Givens rotation operations which are independent of the process of SCGR. Given this, we design a time-sharing (TS) Givens rotation structure to take advantage of these idle states mentioned above to share parts of the Givens rotation operations in RGR, which can save hardware cost as well as improve hardware efficiency. Figure 5: Block diagram of processing engines (PEs): (**a**) processing engine#1; (**b**) processing engine#3. Figure 6: Block diagram of processing engine#2. Figure 7: Block diagram of processing engine#4. Figure 9 shows the deeply pipelined processing flow of the proposed SQRD processor with time-sharing Givens rotation structure. The index \((i,j)\) in the box denotes the element being processed in the \(i\)th row and \(j\)th column of the first \(\mathbf{H}\) during SCGR procedure or the first \(\mathbf{S}\) during RGR procedure.