# Algorithmic Method for the Design of Sequential Circuits with the Use of Logic Elements
## 3 Designing of Sequential Circuits Using Logic Elements  
Based on the graph of the system shown in Figure 4, we find that:  
* A+ input requires the product function s k1 to be implemented (s signal from start button, k1 memory status),
* B+ input requires the sum function execution of two components (a1 k1 + k3) because the actuation state of the B actuator occurs twice, where the product a1 k1 is the first state appearing under the influence of the position of the actuator A and the memory state k1, while the second state of activation of the B actuator appears under the influence of the state of memory k3,
* input B\(-\) requires the implementation of the function of the sum of two components (k2 + k4) because the B actuator OFF state occurs twice: i.e., under the influence of memory state k2 and memory state k4,
* C+ input requires the product function b0 k2 to be implemented (product of the state of the actuator B position and memory k2),
* inputs C\(-\) and A\(-\) require the implementation of the product function b0 k4 (product of the state of the actuator B position and the state of memory k4). In the electro-pneumatic system (Figure 5), the actuators are controlled by solenoid valves. Figure 4: Division of the graph into states. The signals generated on the border of the graph segments are used to control the memory of the system. The system graph (Figure 4) shows that memory switching occurs according to the following relationships:  
\[\text{x1}=\text{b1}\ \text{k1},\qquad\text{x2}=\text{c1}\ \text{k2},\qquad\text{x3}= \text{b1}\ \text{k3},\qquad\text{x4}=\text{a0}\ \text{c0}\ \text{k4},\]  
The input signals to the memory block are read from the graph because they correspond to those arches that occur on the border of division into groups:  
* the x1 signal generates the k2 state (through the memory input setting the k2 state), which simultaneously resets the k1 state (through the memory input resetting the k1 state),
* the x2 signal generates the k3 state (through the memory input setting the k3 state), which simultaneously resets the k2 state (through the memory input to reset the k2 state),
* the x3 signal generates the k4 state (through the memory input setting the k4 state), which simultaneously resets the k3 state (through the memory input to reset the k3 state),
* the x4 signal generates the k1 state (through the memory input setting the k1 state), which simultaneously resets the k4 state (through the memory input to reset the k4 state). Figure 5: Diagram of the electro-pneumatic system with the use of logic circuits. In the designed electro-pneumatic system, the 4/2 valves with electric control have been used (Figure 5). The valve state is set by applying a voltage signal to its coil. Loss of this voltage keeps the valve in the same state. Applying voltage to the second coil causes a change in its state. It should be noted that the use of a circuit memory consisting of a flip-flop RS and a buffer M is advantageous. The voltage buffer circuit has a high buffer input impedance and provides a gain of unity. Based on the graph of a simple system (Figure 4.) and the resulting diagram (Figure 5) general rules for creating an electro-pneumatic system diagram with the use of logic circuits can be formulated:  
1. Executive elements appearing in the graph are drawn in the general case of A-N, i.e., double-acting actuators cooperating with bistable solenoid valves;
2. The input signals bus, power signals bus and the memory bus are drawn;
3. The memory bus reflects the division of the graph from k1-kn;
4. To the input signals bus A1-N1, A0-N0 measuring sensors of executive elements A-N are connected. 5. System memory is created consisting of n RS flip-flops and M buffers, generating the memory state k1-kn;
6. The memory is controlled by signals generated as a result of the radial division of the graph x1-xn, respectively, whereby the signal x1 sets the memory to the state k2, the signal x2 to the state k3, etc., and the signal xn sets the memory to the state k1.