## 2 Related Work  
Boosted by the need to reduce the ever-increasing environmental footprint of large datacenters, energy efficiency plays a role of growing importance in modern HPC systems [1]. Various research efforts have been devoted to this topic, tackling the problem at any architectural level, from hardware and infrastructure level to operating system, scheduling, and algorithm level. The reduction in power consumption at the hardware level is often achieved through architectural changes and cooling methodologies [2; 22]. Dynamic voltage and frequency scaling (DVFS) is one of the most used hardware-level techniques to reduce the power consumption of a processor [23; 24]. Obviously, reducing the operating clock increases the duration of any running software, which may not only negatively affect the application performance [25; 26; 27; 28], but also induce faults in the computation (making it more prone to radiation and thermal drifts) and, consequently, cause additional processing and power consumption [8; 10; 29]. Nonetheless, DVFS is a frequently employed energy-saving method, e.g., to improve job scheduling algorithms with power budgeting capabilities [30; 31; 32]. Higher-level measures to contain the power consumption of a system often rely on Intel's RAPL [33; 34], which offers a mechanism to access power consumption measures related to the system's main hardware components. Although the reliability of these measures has been questioned in some works [19; 20], RAPL is still widely employed to enforce power-aware job scheduling in HPC infrastructures [35; 36] and an RAPL-alike interface is now also available for AMD's architectures [37]. In our work, we avoid the debate about RAPL reliability by employing environmental and vendor-specific onboard sensors to measure the energy performance of the system. Other approaches devoted to power consumption containment operate at the operating system- or job scheduling-level [4; 38; 39; 40] by suggesting the \"best\" job execution order to minimise the energy requirement of the infrastructure--without any modification to hardware components nor nodes' operational voltage/frequency. Concurrency throttling [12; 41] can be classified as another system-level strategy to reduce energy consumption. Some other attempts [3] operate at the software level and investigate the possibility of predicting the energy footprint of parallel algorithms from their characteristics (e.g., flops, memory occupation, communication scheme). Typically, these approaches can be classified into two classes. The first class includes works [7; 8; 9; 10; 29] that propose mathematical models of power consumption based on the algorithm's features. In particular, [PERSON] et al. [8] develop a seminal model of the application's power requirements mathematically combining the known features of the algorithm (i.e., operations, concurrency, and memory traffic) with those of the machine executing it (i.e., time and energy costs of each operation and each word of communication). Analogously to the approaches that could be tailored on top of the proposed dataset (which focuses just on linear solvers), [PERSON] et al. [42] restrict their attention to a particular kind of linear algebra task (i.e., matrix multiplication) and propose to relate energy with the algorithm's number of flops, sent messages, and memory occupation. The work [9] proposes a simpler energy model relating the operational frequency of a multi-core machine with the algorithm's features, and employs such a model to define an estimation methodology for the energy scalability of parallel algorithms. The work by [PERSON] et al. [29] builds on top of [PERSON] and [PERSON] [20] reliability model to design a scheduling policy that includes makespan and energy in the equation. Their idea is to allow the re-execution of some tasks in case of faults, while we propose to investigate the checkpointing and ABFT methods such as IMe.