# A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing
## 5 Discussion  
Until recently most architectures and devices for deep learning algorithms were developed for data centers. This scenario is changing due to a mixed solution that is due to a large part of inference and maybe training done at the edge near the sensors. It is true that training is still a task for data centers but inference has many advantages if run at the edge platform. Edge devices need a high-processing capacity at a low cost and low power with many of them subject to real-time analysis; high-performance computing at the edge. Given the vast set of different edge devices, it is expected that a single solution will not be enough to accomplish the requirements for all of them. Therefore, flexibility is another aspect to consider in a deep learning device. Flexible ASIC with additional functions reduces silicon efficiency and a fixed ASIC is unable to keep with the fast evolution of neural network models. CPUs are programmable but are less energy efficient and are unable to fulfill the performance requirements, whereas GPUs achieve high-performance computing but with high energy consumption. In the midterm, coarse-grained architectures, FPGAs, and SoC FPGAs offer high-performance with good energy efficiencies and enough flexibility to adapt architectures to network models. Even with the great advances in IC technology, designers are always under pressure to produce better solutions. To map large neural networks in embedded devices, both model and architectural optimizations have to be considered. New neural network models with fewer parameters have been proposed even with a small accuracy degradation. Several techniques have been successfully used that reduce the complexity of neural networks, including the reduction of the complexity of convolutions, filter ranking, etc. At the hardware side, data reduction and data quantization reduce the memory and computational footprint with negligible accuracy degradation. While most architectures already consider fixed-point representations, only a few implement pruning, zero-skipping, and other data reduction methods due to complexity and irregularities created by such techniques when implemented in hardware. Many of these optimization techniques must be integrated on the same architecture. Binary networks have to be more thoroughly analyzed and tested since they can be efficiently implemented in FPGAs with high-performance and low-energy consumption. Different tradeoff levels between design efficiency and accuracy are possible. Consequently, when designing a CNN for a particular application, the acceptable or required accuracy has to be considered. Deep learning algorithms have achieved higher accuracies for many problems compared to other \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Architecture** & **Year** & **Data** & **Configurability** & **Measured GOPs** & **GOPs/Watt** \\ \hline nn-X [63] & 2014 & 16-bit & Fine & 23.1 & 25 \\
[2] & 2016 & 16-bit & Fine & 137 & 14.2 \\ fpgaConvNet [66] & 2018 & 16-bit & Fine & 0.48 & - \\ MVTU [35] & 2016 & 1-bit & Fine & 2465 & 210 \\ DLAU [71] & 2017 & 48-bit & Fine & - & - \\ Angel-Eye [72] & 2018 & 8/16-bit & Fine & 84/137 & 24.1/14.2 \\ Lite-CNN [73] & 2018 & 8-bit & Fine & 133 & 33 \\ \hline Eyeriss [54] & 2018 & 16-bit & Coarse & 46.2 & 166 \\ CNN-RNN [55] & 2017 & 4-bit & Coarse & 1200 & 3900 \\ SMIV [56] & 2018 & 8-it & Coarse & - & - \\ DRP [57] & 2018 & 16-bit & Coarse & 960 & - \\ \hline DNPU [55] & 2017 & 4/16-bit & Limited & 250 (16b) & 4200 \\ Thinker [74] & 2018 & 8/16-bit & Limited & 368 & 1000 (8b) \\ EV6x [75] & 2017 & 8/12-bit & Limited & - & 2000 \\ NeuPro [76] & 2018 & 8/16-bit & Limited & 2000 & - \\ DNA [77] & 2017 & 8/16-bit & Limited & 1000 & - \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Main features of reconfigurable and configurable architectures for deep neural networks on the edge. machine learning algorithms and this has increased the applicability of these algorithms to many other applications.