## 3 Proposed Design Scheme
### Firmware Design
If both LPMode/TxDIS pins are inactive, it commands the PAM4 DSP IC to drive and proceed with power activation and optimization settings for the transmission photomultiplier. For operation and optimization of the PAM4 DSP IC, the manufacturer's datasheet was referenced and the API provided by the manufacturer was ported to the MCU to implement the drive driver. Finally, a function related to alarm monitoring was executed so that the optical transceiver status could be constantly monitored. If a monitoring and control request is received from the external host interface, the MCU generates an I2C request interrupt and performs the processing as requested. QSFP28 Register Configuration and Control Algorithm  
As described in Section 2.3, the QSFP28 optical transceiver should define the internal register to receive control and monitoring requests from the host system and should configure nonvolatile registers, such as the upper page 0 \(\times\) 02 area, at the request of the standard document. The proposed scheme allocates a portion of the MCU's flash memory  
Figure 6: QSFP28 firmware function design block diagram. to store nonvolatile data. For the host to access the upper page 0 \(\times\) 02 of the QSFP28 optical transceiver, it must first change the page selection address (0 \(\times\) 7F) value on the lower page. To implement the page access function, the proposed scheme designates that the MCU uploads the value of the flash memory area of the page to the RAM when the host changes the page selection register. In addition, the vendor specific area, page 0 \(\times\) 04, was used to store nonvolatile values such as the setting values for optimizing the optical component performance of the QSFP28 optical transceiver, calibration values for DDM accuracy, and values for optimizing PAM4 signals. The QSFP28 requires an algorithm to access and control registers to handle host requests. The standard document defines only the register structure and functions and must be directly implemented by the manufacturer for actual operation. Algorithm 1 shows the QSFP28 register control algorithm that includes page selection when requested by the host system over the I2C interface. The I2C interrupts occur in the MCU when I2C access occurs from the host. The MCU executes the I2C interrupt service function to store the _StartAddress_, _WriteCount_, and _WriteValue_ to be written to the I2C. For example, if a write action occurs on the host, the stop signal is checked for I2C communication and the I2C slave stop function is executed as shown in Algorithm 1. If this is a read operation, the register values of the lower and upper pages currently stored in the I2C buffer are sent as output to the host interface. The I2C buffer consists of a _LowerBuffer_ and _UpperBuffer_, totaling 256 bytes. When the I2C slave stop function is called, access to the first page-selection address is checked, and the values of the flash memory area, where the values of that page are stored, are copied onto the upper page buffer. If not selected, the buffer value with the specific address value is updated to a new value and the processing proceeds according to the function of that address. Finally, if the value of the address must be stored on the EEPROM, the function that stores it in the flash memory must be executed. At this time, all storage units in pages are 128 bytes. The DDM function monitors the status of the optical transceiver from the ADC IC and updates it to the register. The proposed design is monitored using the internal ADC in the MCU and the external ADC IC. The monitoring values include the optical power, transmission bias current, transmission component temperature, transceiver temperature,  
Figure 7: QSFP28 firmware sequence diagram for initialization and operation. and voltage. The monitored values are updated by converting them to values in units defined in the standard document when they are updated in that register.