# Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor
## 4 Decimal Multiplier
### Partial Product Generator  
Method 2 The second method to generate the partial product considers the following subsets of multiples: \(S_{1}=\{4\)A, 5A\(\}\) and \(S_{2}=\{0,\) 2A, 4A\(\}\). The advantage of these subsets is that subset \(S_{1}\) has only two multiples. The disadvantage is associated with the generation of multiple 4A as will be seen in the generation of multiples.  
Similar to method 1, any multiple of the set {0, A, 2A,..., 8A, 9A} can be obtained from the addition or subtraction between multiples of each set as shown in Table 5.  
Figure 4: Proposed partial product generator in method 1.  
Figure 3: Implementation for a single digit of block \(Sel-Add/Sub\) in method 1.  
The architecture of the partial product circuit is similar to that designed for method 1, except that the multiplexer has only two inputs: 4A and 5A (see Figure 5).  
Selectors \(S_{a}\) and \(S_{b}\), and operand selector \(op\) are functions of the multiplier digit, \(b_{i}=b_{i}[3]b_{i}[2]b_{i}[1]b_{i}[0]\), as described in Table 6.  
Also, to simplify the adder/subtractor of the partial product generator all multiples are represented in excess-3. Considering the equations of the propagate and generate expressions of the adder/subtractor with operands represented in excess-3, the expressions  
\begin{table}
\begin{tabular}{l l l l l l} \hline \hline \(b_{i}[3]b_{i}[2]b_{i}[1]b_{i}[0]\) & **Multiple** & **Operation** & \(S_{a}\) & \(S_{b}\) & **op** \\ \hline “0000” & 0 & 4A \(-\) 4A & “0” & “10” & 1 \\ “0001” & A & 5A \(-\) 4A & “1” & “10” & 1 \\ “0010” & 2A & 4A \(-\) 2A & “0” & “01” & 1 \\ “0011” & 3A & 5A \(-\) 2A & “1” & “01” & 1 \\ “0100” & 4A & 4A + 0 & “0” & “00” & 0 \\ “0101” & 5A & 5A + 0 & “1” & “00” & 0 \\ “0110” & 6A & 4A + 2A & “0” & “01” & 0 \\ “0111” & 7A & 5A + 2A & “1” & “01” & 0 \\ “1000” & 8A & 4A + 4A & “0” & “10” & 0 \\ “1001” & 9A & 5A + 4A & “1” & “10” & 0 \\ \hline \hline \end{tabular}
\end{table}
Table 6: Generation of selectors in method 2.  
Figure 5: Partial product generator for a single multiplier digit using subsets \(S_{1}=\{\)4A, 5A\(\}\) and \(S_{2}=\{\)0, 2A, 4A\(\}\).  
\begin{table}
\begin{tabular}{l l l l} \hline \hline
**Multiple** & \(\in S_{1}\) & \(\in S_{2}\) & **Operation** \\ \hline
0 & 4A & 4A & 4A \(-\) 4A \\ A & 5A & 4A & 5A \(-\) 4A \\
2A & 4A & 2A & 4A \(-\) 2A \\
3A & 5A & 2A & 5A \(-\) 2A \\
4A & 4A & 0 & 4A + 0 \\
5A & 5A & 0 & 5A + 0 \\
6A & 4A & 2A & 4A + 2A \\
7A & 5A & 2A & 5A + 2A \\
8A & 4A & 4A & 4A + 4A \\
9A & 5A & 4A & 5A + 4A \\ \hline \hline \end{tabular}
\end{table}
Table 5: Generation of multiples in method 2.  
of the propagate and generate signals for a single digit of block \(Sel-Add/Sub\) are as follows:  
\[p[3] =op\oplus ma[3]\oplus(S_{b}[0]\ \overline{S_{b}[1]}\ 2 ae3[3]+ \overline{S_{b}[0]}\ S_{b}[1]\ 4 ae3[3]) \tag{16}\] \[p[2] =op\oplus ma[2]\oplus(S_{b}[0]\ \overline{S_{b}[1]}\ 2 ae3[2]+ \overline{S_{b}[0]}\ S_{b}[1]\ 4 ae3[2])\] \[p[1] =op\oplus ma[1]\oplus(S_{b}[0]\ \overline{S_{b}[1]}\ 2 ae3[1]+ \overline{S_{b}[0]}\ S_{b}[1]\ 4 ae3[1])\] \[p[0] =op\oplus ma[0]\oplus(S_{b}[0]\ \overline{S_{b}[1]}\ 2 ae3[0]+ \overline{S_{b}[0]}\ S_{b}[1]\ 4 ae3[0])\] \[g[3] =ma[3]\] \[g[2] =ma[2]\] \[g[1] =ma[1]\] \[g[0] =ma[0]\]  
Propagate and generate signals are interconnected with a carry chain to generate the circuit for a single digit of block \(Sel-Add/Sub\) with a carry-in and a carry-out (see the implementation of a single digit in Figure 6).  
Similar to method 1, the complete partial product is obtained with a chain of these single-digit blocks. All N partial products are generated parallel with N partial product generators. The carry-in of the first module receives the \(op\) signal.