# Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology
## 1 Introduction
From the application point of view, data-path functions, in particular arithmetic functions, often operate on coarser arguments than control-path logic and are usually realized by fine-grain logic elements, while the implementation of control-path logic mostly benefits from coarser granularity. A rather interesting question is whether the logic blocks in an FPGA should be heterogeneous or homogeneous in size. The second challenge is to determine the optimal segmentation of routing interconnects. In conventional routing architecture, each routing channel consists of a group of interconnects with variable lengths. For example, Virtex II [18] has 16 Single, 40 Double, 120 HEX, and 24 long  
Figure 1: (a) Cross-section of a Magnetic Tunnel Junctions (MTJ)-CMOS hybrid chip; (b) Monolithically stacked 3D-Field Programmable Gate Arrays (FPGA) [7]. interconnects in each routing channel. In general, short segments are advantageous to routability but bad for delay and power performance, while long interconnects achieve better delay performance but may result higher power consumptions. For a given set of benchmark circuits, what is exactly the optimal segmentation for a particular routing architecture remains an open question. We propose the stochastic-based Spin-programmable Gate Array (SPGA) architecture to meet the above design challenges. Our objective is to develop an architecture that maximizes the application spectrum for both data-path and control-path applications without compromising performance and area efficiency, while fully exploiting the performance benefits entailed by the emerging MTJ devices, especially its inherent quantum-induced stochastic switching. The central idea of SPGA is to design and implement stochastic-based programmable logic blocks (SLB) in order to replace the traditional lookup-based (LUT) logic blocks. In addition, both the granularity and the input-output numbers of the new logic blocks can be dynamically configurable on a per-mapping basis at configuration time. More specifically, our major contributions include:  
* We invented a new curve-based method to reinterpret and redefine Boolean logic functions, therefore can efficiently implement multiple-input-multiple-output logic block without noticeable hardware usage overheads. This technique compounds the overall performance benefits resulting from the MTJ devices. * Taylor expansion, although mathematically elegant and powerful, has never been considered in hardware-assisted functional evaluation due to its excessive hardware cost. Our stochastic-based approach natively exploits the inherent Gaussian-like stochastic switching behavior of the emerging spintronic devices, therefore bypassing the excessive hardware overhead of Boolean-based methodology. * Due to the SPGA's unconventional architectural features, we have made several modifications to the existing academic-grade software flow of logic synthesis, technology mapping, placement, and routing. In particular, given the freedom of configuring the output number of SLBs, we developed a variant of the conventional technology mapping algorithm based on computing (\(k\), \(l\))-feasible cuts. The rest of our paper is organized as follows. In Section 2, we briefly overview the overall architecture of the Spin-Programmable Gate Array (SPGA). We then illustrate in Section 3 how a stochastic-based logic block (SLB) can be constructed with MTJ devices. In particular, We review the newly discovered stochastic switching behavior of Magnetic Tunneling Junctions (MTJ) and discuss the circuit design of a typical SLB. In Section 5, we detail each necessary module for logic synthesis, placement, and routing of SPGA. The performance comparison results of three performance metrics (hardware usage, delay, and energy consumption) between the SPGA architecture and three other island-style baseline FPGAs in Section 6. The error analysis are performed in Section 7. Finally, in Section 8, we summarize our findings and comment on several open research problems related to the SPGA architecture.