## 2 Materials and Methods
### Analog-to-Digital Converter (ADC)  
A fully differential Successive Approximation Register (SAR) ADC converts the analogue signal to the digital domain. The ADC provides 6-bit resolution with a 40 MSps  
Figure 2: Simplified block diagram of analogue front–end.  
sampling rate. One of the most important constraints of the ADC design is to keep the power consumption significantly below 1 mW, which drove the design to use a SAR ADC architecture. To further reduce the dissipated power, a Merged Capacitor Switching (MCS) scheme [19] was implemented. Since in the given technology the best capacitance matching is offered by a metal-insulator-metal capacitors, which are relatively large, a split capacitor DAC approach was used, as shown in Figure 3.  
In addition to the DAC switching scheme, two other features are implemented to reduce the power consumption: a dynamic comparator [20] and an asynchronous control logic, as shown in Figure 3. The dynamic comparator dissipates power only during the bit cycling process, while the main power saving in the asynchronous control logic comes from the fact that the fast clock signal for the conversion of subsequent bits is eliminated. Finally, additional power reduction is achieved by implementing part of the logic with dynamic flip-flops. At the input, bootstrapped switches [21] are used; although they costs some extra power, they increase the linearity of the ADC. More details on the ADC design and its multi-channel performance can be found in references [22; 23].  
To improve robustness against SEE events, the ADC control logic in the SALT was slightly modified. The sampling signal launches the ADC reset sequence regardless of whether the previous conversion was finished or stopped due to a SEE. Even though it causes the loss of two ADC samples for SEE event (one caused directly by SEE and the next one when the reset sequence is performed) it ensures continuous operation.  
Due to the fully asynchronous architecture of the ADC, the current consumption between conversions is almost zero. It is roughly uniform during the conversion which takes slightly more than half of the 40 MHz clock period. As a result, the current drawn by the ADC is approximately a square wave with roughly 50% duty cycle and amplitude twice as large as the average consumption. Such a pattern, amplified by all 128 ADC channels working synchronously can be an irremovable source of disturbances induced in the analogue front-end. One possible solution to this problem could be an artificial delay after each bit cycle increasing effectively the overall conversion length. However, the time structure of the current consumption in such a case would consist of large spikes, during each bit cycle, and the gaps in between. Moreover, the increased conversion length may cause issues at higher irradiation doses due to expected slowdown in ADC control circuitry. Therefore a definitely less sophisticated, yet robust approach was chosen. Since the averaged ADC power consumption is far below the ASIC specification, a circuitry drawing additional dummy current between the conversions was added to each ADC. This increases the average current, but makes it uniform in time. The additional current can be disabled by the ECS command, reducing the total power consumption, but increasing the probability of the interference with the analogue part of the ASIC.  
Figure 3: Block diagram of the 6-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).