# Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity
## 2 Related Work  
### NoC Router Architecture and Algorithms  
Scalable NoC contains a router at each hop to control access to shared resources. A classic NoC router [13] works as follows. The router first writes a received packet into buffer (BW) and computes the packet's admissible output port at the same time (RC). Then virtual-channel allocation procedure assigns a free VC of the output channel for the packet. Upon successfully obtaining a VC, the packet arbitrates for accessing the crossbar ports (SA). If all is successful, the packet can go through the switch traversal (ST) and link traversal (LT) stage to proceed to a neighbour router [13]. Going through these stages in series causes large delay on each hop, which makes the communication inefficient. Moreover, if any of the desired resources (e.g., buffer, crossbar) cannot be obtained, a packet is stalled, increasing the packet delay. It is widely accepted that latency is one of the key challenges of designing practical on-chip networks [14]. To address this challenge, various techniques such as adaptive routing, parallel execution, link improvement and structure simplification, have been proposed. Adaptive routing: Changing packet paths dynamically to avoid congestion reduces packet queuing delay effectively [15; 16]. However, at low-load conditions, adaptive routing brings negligible improvement. Moreover, the required pipeline of adaptive routing has higher complexity. Parallel execution: Some of the operations can be done in parallel. The work in [17] does VA and SA in parallel speculatively and prioritizes non-speculative packets in SA to increase resource utilization. The work in [18] exploits the abundant bandwidth inside the router and multicast flits to output ports speculatively rather than waiting for SA. Parallel processing of a packet can also happen on different routers with the help of control flits, which go ahead of data flits [19]. SA for a flit is done based on the control flit, while the data flit is traversing the link on the previous router. When the data flit arrives, it can bypass the SA stages and go directly to ST. However, the sideband network for control flits introduces extra wiring and power overhead. Link improvement: Low-swing signalling [20] and an asynchronous link [21; 22] have been adopted in NoCs to allow multiple-hop traversal in one cycle. Low-swing signalling has poor bandwidth density, and the asynchronous link can have signal skew issues due to interference [23]. In chips operating at high frequency, the signal traversal length can be limited due to the small clock cycle. Structure simplification: The simplicity of the ring topology allows the router to have a simple and low-latency micro-architecture [12]. In 2D mesh topology, the dimension-sliced router (DSR) is proposed to reduce router cost and latency [11]. DSR abandons the input buffers of routers and decouples the datapath of the two dimensions to the reduce cost. Figure 2 shows the datapath of DSR, which supports dimension-ordered routing. Intra-dimension traversal in DSR incurs single-cycle delay (including link traversal). CMP workloads require low-latency adaptive routers to reduce communication latency and require VC support in NoC to achieve message isolation. Existing approaches that aim at reducing the latency of NoC routers such as lookaheads [24] add wiring and logic complexity to routers and increase NoC's area overhead and power consumption. Speculation [17] does not reduce the worst-case pipeline delay. Simple NoC micro-architectures, like [11; 12], are not adaptive and have no VCs. High radix routers [25; 26] usually have higher serialization delay and do not work well under adversarial traffic [22]. NoC with multi-hop traversal in single cycle capability, such as SMART [22], showssignificant latency reduction. However, such a feature may not be sustained in chips operating at a high frequency, or with long links (e.g., hierarchical topology), or in the combination of two.