## 4 FPGA Implementation of PID Controller and BB-BC
### BB-BC Algorithm in FPGA  
Several FPGA-based implementations of evolutionary algorithms have been presented in the literature to accelerate the optimization process. Most of these approaches focus on the optimal design of hardware accelerators to achieve high performance and flexibility [25; 26] and satisfy other genetic algorithm features, such as multi-objective optimization [27]. In our approach, we adopted the BB-BC optimization algorithm due to its low computational time and high global convergence speed. These features of the BB-BC algorithm mainly motivated our work, since an FPGA-based BB-BC accelerator can greatly reduce the computational time providing an ideal platform for large-scale adaptive or latency-sensitive optimization problems [28].  
In this subsection, we describe the FPGA design architecture of the BB-BC algorithm. Figure 6 depicts the top-level design diagram of the FPGA BB-BC architecture consisting of the following blocks:  
Figure 5: Block diagram of a typical PID controller FPGA architecture.  
* Random Number Generation: It generates the random numbers \((\overrightarrow{x}^{i})\), either to form an initial population (iteration 0) or to form new candidates around the CoM (iteration > 0). A typical linear feedback shift register (LFSR) is used to generate random numbers based on a configurable seed. Note that the boundaries of the random numbers are determined by the upper and lower values of the optimization function variables. In each iteration, the module generates N candidates sequentially, where N is the population size, with each one consisting of L random numbers, where L is the number of features of each candidate. The generated random numbers of each iteration are stored in a RAM in order to be processed later for the calculation of center of mass.
* Objective Function: After the random number generation, this module calculates the objective function (\(f^{i}\)) for each candidate \((\overrightarrow{x}^{i})\) using the ITAE equation, which is also stored in the RAM. Both the random number generation and objective function modules have been implemented following a simple, serial processing model, where a single element is processed in each clock cycle, providing a low-cost FPGA circuit. Note that both modules can be parallelized (i.e., to generate the random numbers and calculate the objective functions concurrently using many processing elements working in parallel) and pipelined in order to improve performance, as proposed in [28].
* Calculate Center of Mass: It reads the candidates and their objective function values from the RAM and calculates the center of mass which is forwarded in the random number generation module to generate the population in the next iteration cycle.
* Evaluate Function: It reads the objective function values of the candidates from the RAM in order to select the best fitness candidate which is store in RAM too, and from output signal when the FPGA-BBBC control the HVAC model.
* Control Unit: It orchestrates the operation of the other modules and repeats the BB-BC steps until the stopping criteria are met.
* Solution: It includes a register that stores the outcome of the BB-BC algorithm.  
Figure 6: Top-level diagram of the BB–BC FPGA architecture.  
Note that a high-performance FPGA architecture of BB-BC algorithm has been presented in [28] which incorporates parallel pipelined engines to accelerate the execution of BB-BC. This FPGA BB-BC architecture has been optimized in terms of execution latency and is very suitable for control applications with strict real-time requirements. However, this performance optimization has been achieved at the expense of extra hardware area and power consumption. Thus, the optimized FPGA architecture of [28] is suggested only for time sensitive control applications.  
Table 3 presents the device utilization summary on a Xilinx Zynq XCZZ010 FPGA device.