# Efficient LDPC Encoder Design for IoT-Type Devices
## 6 Numerical Results  
Our research is supported by the experimental results, which cover three aspects: memory utilization, encoding time, and error-correction performance. The optimized memory enables the use of smaller, lower-cost, and more energy-efficient microcontroller devices; optimized timing can potentially decrease energy consumption, and likewise, the error-correction performance, which is greater than in the case of typical block codes, can enable lower transmission power in wired or wireless transmission systems. The QC-LDPC codes used for encoder verification and system performance simulation were obtained with a code graph optimization method, consisting of two phases:  
1. Base graph construction, that is, a graph corresponding to the \(I\times J\) base matrix \(\mathbf{W}\) indicating non-zero submatrices in \(\mathbf{H}\) in (1). 2. Cyclic lifting of the base graph, with cyclic shift values \(s_{i,j}\) in (1) obtained with an iterative search algorithm. The code construction algorithm is summarized as Algorithm 1. Several different parity-check matrices (\(\mathbf{H}1,\ldots,\mathbf{H}8\)) with diversified block lengths, regular and irregular, as listed in Table 2, were used for the experimental study. For example, the parity-check matrix of a regular \((3,6)\), \((1024,512)\) code with submatrix size \(P=32\) is provided in Figure 5. This matrix, referred to as H1 in Table 2, corresponds to an optimized graph, free of length-4 and length-6 cycles and a minimized number of length-8 cycles. ```
Input: Base matrix size \(I\times I\), submatrix size \(P\), variable nodes degree distribution \(\lambda=[\lambda_{2},\lambda_{3},\dots,\lambda_{d_{iVmax}}]\) Output: Binary matrix \(\mathbf{H}_{IP\times P}\) consisting of \(I\times J\) circulants of size \(P\times P\)
1[Base matrix construction]
2 If possible (that is, if \(\lambda_{2}\geq I/J\)), insert dual diagonal at the right side of the base matrix \(\mathbf{W}\). 3 Utilizing the PEG algorithm [20], progressively add edges into the base graph (ones into the remaining part of \(\mathbf{W}\)), subject to the degree distribution \(\lambda\). 4[Cyclic shift values determination]
5 If \(\mathbf{W}\) is not dual diagonal, then by row and column permutations, convert it to the ALT (almost lower triangular) form. 6 If \(\mathbf{W}\) is dual diagonal, then fix the cyclic shift values on dual diagonal such that \(\mathbf{\Phi}=\mathbf{I}\), according to the expressions in [45]. 7 In the base graph corresponding to \(\mathbf{W}\), identify all short closed walks (if the length of the shortest cycle is \(g\), then closed walks up to length at least \(g+4\) should be identified). 8 For every closed walk, formulate a condition involving cyclic shift values \(s_{i,j}\) such that corresponding cycles in the lifted code graph do not exist [24]. 9 For every condition, iteratively modify associated \(s_{i,j}\) values in order to satisfy the greatest possible number of conditions for the non-existence of corresponding cycles. 1[Matrix construction]
1 From the obtained \(\mathbf{W}\) and \(s_{i,j}\), \(i=1,\dots,I\), \(j=1,\dots,J\), construct \(\mathbf{H}\) as in (1). ```  
**Algorithm 1**QC-LDPC parity-check matrix construction. The parameters of the RS and BCH codes, which are counterparts of LDPC \(\mathbf{H}1,\dots,\mathbf{H}8\), are also presented in Table 2. These codes were used for an experimental comparison of the developed QC-LDPC scheme with classical block codes. Every RS code is clearly defined by its \((N,K)\) parameters and for BCH codes, we also provide the correction capability parameter \(t_{BCH}\), defined as in [49]. The generator polynomials of RS and BCH codes are obtained as described in [49]. Figure 5: Parity-check matrix of a (1024,512) QC-LDPC code with submatrix size \(P=32\). The cyclic shift values are provided for non-zero submatrices.