## 3 The Proposed VLSI Architecture for the New Integer DCT Algorithm
### VLSI Implementation  
The RTL description of the IntDCT was performed using SystemVerilog. An example simulated operation of the IntDCT core implementation is illustrated in Figures 10-12. The operation of the IntDCT core was exemplified for 2 batches of 16 input samples: \(x=121\), 106, 92, 79, 67, 56, 37, 29, 22, 16, 11, 7, 4, 2, and 1, immediately followed by \(x=10\), 20, 30, 40, 50, 60, 70, 80, 80, 70, 60, 50, 40, 30, 20, and 10. Figure 10: Illustration of the IntDCT systolic array operation for the \(0\ldots 20\) time unit interval. In the figure, \(x\) represents the input samples to the DCT core; \(y\) represents the unscaled output samples of the DCT core; and \(x_{1a}\), \(y_{1a}\), \(x_{1b}\), \(y_{1b}\), \(x_{2a}\), \(y_{2a}\), \(x_{2b}\), \(y_{2b}\), \(x_{3}\), \(y_{3}\), \(x_{4}\), and \(y_{4}\) represent the inputs and outputs of the five systolic arrays corresponding to Equations (6), (7), (9)–(13), respectively. The _reset\({}_{n}\)_ signal resets the control state machine while the _restart_ signal restarts the computations for a new input batch. The signal \(ds_{i}\) represents the data shift commands for the systolic arrays when input data are shifted through the chain and partial results are progressively computed. The signals \(os_{i}\) are the output sample commands when valid outputs are sampled from the chains and pushed into following shift registers. The first output sample is produced after 32 samples, therefore the latency of the implemented IntDCT core is \(32T_{clk}\). The expected unscaled output sequence for the first input batch is \(y\) = 89,088, 53,000, 13,144, 5784, 3216, 2024, 1368, 1192, 720, 488, 424, 360, 208, \(-\)8, 104, and 152, which is produced by the implementation, as can be observed in Figures 10-12. In the figures, the first input sample batch is highlighted with blue and the second input samples batch is highlighted with green. The first output samples batch is highlighted with magenta and the second output samples batch is highlighted with yellow. The partial results produced by the systolic chains are highlighted with the color corresponding to the outputs which they contribute to. Figure 11: Illustration of the IntDCT systolic array operation for the \(19\ldots 39\) time unit interval. In the figure, the first input sample batch, together with the auxiliary input sequences related to this batch, are highlighted with blue, while the second input samples batch, and the corresponding auxiliary input sequences are highlighted with green. The first output samples batch is highlighted with magenta, while the second output samples batch, in the following figure, is highlighted with yellow. The partial results produced by the systolic chains are highlighted with the color corresponding to the outputs which they contribute to. For characterization purposes, we have synthesized the IntDCT core using Cadence Genus 21.14 with Nangate OpenCell Library and NCSU's 15 nm FreePDK15. We have considered an 8 bits width for the input samples and an 18 bits width for the unscaled output samples. Table 1 summarizes the synthesis results in terms of area, power, and delay for the IntDCT. It can be observed that the minimum constrained clock period for which the synthesis tool is able to find a solution is 4.17 GHz. At this frequency, the dynamic power is 52.1 mW. The proposed solution has further potential for optimization by early scaling the partial results (currently, the output needs to be divided by 128, i.e., the least 7 significant bits can be discarded) along the systolic chains. Another means to increase the operating frequency is to add a pipeline stage for the computation of the auxiliary inputs in Equation (5).