## 1 Introduction  
Low-density parity-check (LDPC) codes are linear block codes that correct errors by adding parity bits, first proposed by [PERSON] in 1962 [1, 2, 3]. These codes are known to approach the channel capacity, with a code construction that allows them to work at a noise threshold close to the Shannon limit in memory-free symmetric channels [4, 5]. In other words, LDPC codes can be transmitted at a rate lower than the channel capacity while maintaining a low bit error rate through logical coding schemes [6]. Additionally, the sparsity of the parity check matrix (PCM) used in LDPC makes it feasible to implement LDPC codes on field-programmable gate arrays (FPGAs) on a large scale [7]. As a result, LDPC codes have been widely adopted in both wired and wireless standards such as IEEE 802.3 an, IEEE 802.3 ba, IEEE 802.11n, IEEE 802.16e, DVB-S2, CCSDS, and others [8]. Quasi-Cyclic LDPC (QC-LDPC) codes are a type of LDPC that can offer several advantages over other error-correcting codes, including low complexity implementation, high error correction performance, flexibility, and wide usage in practical applications. They can be efficiently encoded using simple operations such as shifting and XOR [9]. Their regular structure also makes them easier to decode, and they can be designed to have a high code rate while still maintaining good error correction performance [10]. Additionally,they are also highly flexible, and can be designed to meet the requirements of different applications, including wireless communication systems, optical communication systems, and storage systems. CCSDS (8176, 7154) LDPC perfectly inherits the characteristics of QC-LDPC and maintains a high code rate, and has therefore been adopted for multiple situations [11]. The data processing speed of many specialized sensors, such as optical sensors, intelligent sensors, and biomaterial-based sensors, has been a pressing need for improvement [12; 13; 14]. With the intensification of the demand for communication speed in the sensor networks, the requirements for coding gain and throughput pertaining to channel coding in high-speed communication systems have correspondingly escalated [15]. While various decoding methods have been proposed, achieving high throughput with minimal hardware requirements and low power consumption remains a challenge. For instance, a LDPC decoder for 5G NR on FPGA proposed by [PERSON] achieves a max throughput of 2.2 Gbps at 10 iterations, but consumes 96 block RAMs and 225,191 look-up tables (LUT) [16]. Similarly, [PERSON]'s decoder for a (1944, 1620) LDPC code achieves a throughput of 1.8 Gbps, requiring 100,000 registers, 65,000 LUTs, and 22 KB RAMs, which indicates low hardware utilization efficiency (HUE) [17]. And the decoder for ultra-long code with size of 149,504 \(\times\) 262,144 in [18] consumes 51,000 LUTs, 1000 DSPs, and 32 Mb RAMs, reaching a throughput of 108 mbps, but can work at a very low SNR. Nevertheless, designing high-performance LDPC decoders with minimal resource requirements and low power consumption remains a formidable challenge. The conventional decoder designs of LDPC codes, which employ the variable node processing unit (VNU) and check node processing unit (CNU) sequentially in each iteration cycle, often result in low HUE and low throughput. Although data interleaving has been proposed to enhance HUE by allowing variable node processing (VNP) and check node processing (CNP) to work on separate block data simultaneously, it doubles the memory requirements [19]. Folding is another technique that combines different block data to achieve the ideal memory depth, but sacrifices the decoder's throughput [7]. To address these limitations, overlapped message passing has been proposed as an algorithm-level solution to overlap the CNU and VNU operations [20]. To maximize the overlap depth, which is the number of CNNs and VNU's concurrently involved in a single iteration, and enhance the throughput, a permutation vector-based LDPC code construction approach has been proposed.