# Wide-Band Interference Mitigation in GNSS Receivers Using Sub-Band Automatic Gain Control +
## 3 Design and Implementation  
The HDDM-AGC algorithm uses the HDDM [6] to deconstruct an input signal into multiple frequency bands. It is achieved through a shift register, a window function, an \(N\)-Point FFT. Each frequency band has a separate IM AGC module. At the end of the process, the HDDM reconstructs the frequency bands back together in a single output data stream. This is realized using an inverse fast Fourier transform (IFFT), a triangular delay register, and a combiner. The AGC module performs the IM and spectrum regulation. Figure 2 shows the block diagram of the AGC module. It consists of four sections. First, a resource-efficient bit-shift AGC is implemented (red box, top left). The benefit is that no multiplication is used-saving significantly on digital signal processor (DSP) slices for firmware implementations. The number of shifts \(M\) depends on the implementation. Second, a control logic circuit (green box, bottom left) determines the average signal amplitude in the frequency band. It approximates the mean signal amplitude over \(K\)-Samples:  
\[c[n,l]=\frac{1}{K}\sum_{m=0}^{K-1}\lvert x_{\mathrm{i}}[n-m,l]\rvert \tag{1}\]  
where \(x_{\mathrm{i}}[n,l]\) is the in-phase component of the signal at the \(n\)-th sample for the \(l\)-th channel of the HDDM, \(\lvert\cdot\rvert\) is the absolute operator, and \(c[n,l]\) is the control value for the bit-shifting AGC. An empirical evaluation determined that using both the in-phase \(x_{\mathrm{i}}[n,l]\)  
Figure 1: HDDM block diagram. ©IEEE. Reprinted, with permission, from [11]. and the quadrature-phase \(x_{\text{q}}[n,l]\) of the signal for this implementation did not yield a significant improvement and was omitted to limit resource use. A larger value of \(K\) implies a slower but more stable AGC response. The control signal is then mapped to the number of bit-shifts:  
\[\hat{p}[n,l]=\lfloor\log_{2}(\lambda_{\text{a}}\times c[n,l])\rceil \tag{2}\]  
where \(\lambda_{\text{a}}\) is a scaling factor, \(\lfloor\cdot\rceil\) rounds the value to the nearest integer, and \(\hat{p}[n,l]\) is the number of bits for the signal to shift. Lastly, the shifting bits are limited to the AGC range:  
\[p[n,l]= \begin{cases}0&\text{if }\hat{p}[n,l]<0\\ M&\text{if }\hat{p}[n,l]>M\\ \hat{p}[n,l]&\text{otherwise}\end{cases}  \tag{3}\]  
where \(p[n,l]\) is the final bit-shifts. An alternative approach would be to use the energy (i.e., \(x_{\text{i}}^{2}[n-m,l]+x_{\text{q}}^{2}[n-m,l]\)) for the control signal (theoretically, this would be the better approach). However, it requires an additional multiplication which increases field-programmable gate array (FPGA) complexity unnecessary with an insignificant improvement to the AGC adaption capability. This optimization is a key trade-off in the FPGA design. Third, the control logic drives a multiplexer (yellow multiplexer, center) which selects the appropriate AGC channel. The in-phase \(y_{\text{i}}[n]\) and quadrature-phase \(y_{\text{q}}[n]\) output of the AGC stage is then defined as  
\[y_{\text{i}}[n]=x_{\text{i}}[n]\times 2^{-p[n,l]} \tag{4}\]  
\[y_{\text{q}}[n]=x_{\text{q}}[n]\times 2^{-p[n,l]} \tag{5}\]  
Finally, a PB is included (blue box, right) to blank any large values to which the AGC could not respond in time. The blanking is defined as  
\[z_{\text{i}}[n]= \begin{cases}y_{\text{i}}[n]&\text{if }y_{\text{i}}[n]<\lambda_{ \text{p}}\text{ or }y_{\text{q}}[n]<\lambda_{\text{P}}\\ 0&\text{otherwise}\end{cases}  \tag{6}\]  
\[z_{\text{q}}[n]= \begin{cases}y_{\text{q}}[n]&\text{if }y_{\text{i}}[n]<\lambda_{ \text{p}}\text{ or }y_{\text{q}}[n]<\lambda_{\text{P}}\\ 0&\text{otherwise}\end{cases}  \tag{7}\]  
Figure 2: AGC module block diagram. ©IEEE. Reprinted, with permission, from [11]. where \(\lambda_{\text{p}}\) is the PB threshold, and \(z_{\text{i}}[n]\) and \(z_{\text{q}}[n]\) are the in-phase and quadrature-phase outputs, respectively.