# An Energy-Efficient Convolutional Neural Network Processor Architecture Based on a Systolic Array
## 4 Hardware Implementation and Evaluation  
### Image Segmentation Strategy  
In this paper, the performance of the processor is evaluated using the VGG-16 model. The data storage required for the computation of the first convolutional layer of VGG-16 under 16 bit fixed-point quantization is at least 53 Mb, while the on-chip storage resources provided by the FPGA used in this paper are only 19.1 Mb. Therefore, the input feature map must be segmented to meet the limited on-chip resources. In this paper, the image of 13 convolutional layers of VGG-16 is segmented in three dimensions: length, width and channels. The selection of segmentation parameters needs to meet the following conditions:  
\[ \begin{array}{c}\text{L}\times\text{W}\times\text{C}\times\text{16 bit < imagebuf\_cap},\\ \text{C}\times\text{(M/N)}\times\text{K}\times\text{16 bit < filterbuf\_cap},\\ \text{(L}-\text{K}+1)\times\text{(W}-\text{K}+1)\times\text{(M/N)}\times\text{16 bit < biasbuf\_cap}\end{array}  \tag{4}\]  
where L, W and C, respectively, represent the length, width and channels of the image; K and M represent the size and number of the filters, respectively; and N is the number of PUs. In this design, imagebuf_cap, filterbuf_cap and biasbuf_cap are equal to 1 Mbit, 32 kbit and 32 kbit, respectively. Table 4 shows the specific segmentation parameters. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**CONV Layer** & **Image Size** & **L’** & **N\({}_{\text{L}}\)** & **W’** & **N\({}_{\text{W}}\)** & **C’** & **N\({}_{\text{C}}\)** \\ \hline CONV1 & \(224\times 224\times 3\) & 34 & 7 & 34 & 7 & 3 & 1 \\ CONV2 & \(224\times 224\times 64\) & 34 & 7 & 34 & 7 & 64 & 1 \\ CONV3 & \(112\times 112\times 64\) & 34 & 4 & 34 & 4 & 64 & 1 \\ CONV4 & \(112\times 112\times 128\) & 34 & 4 & 34 & 4 & 128 & 1 \\ CONV5 & \(56\times 56\times 128\) & 22 & 3 & 22 & 3 & 128 & 1 \\ CONV6 & \(56\times 56\times 256\) & 22 & 3 & 22 & 3 & 256 & 1 \\ CONV7 & \(56\times 56\times 256\) & 22 & 3 & 22 & 3 & 256 & 1 \\ CONV8 & \(28\times 28\times 256\) & 18 & 2 & 18 & 2 & 128 & 2 \\ CONV9 & \(28\times 28\times 512\) & 18 & 2 & 18 & 2 & 128 & 4 \\ CONV10 & \(28\times 28\times 512\) & 18 & 2 & 18 & 2 & 128 & 4 \\ CONV11 & \(14\times 14\times 512\) & 14 & 1 & 14 & 1 & 128 & 4 \\ CONV12 & \(14\times 14\times 512\) & 14 & 1 & 14 & 1 & 128 & 4 \\ CONV13 & \(14\times 14\times 512\) & 14 & 1 & 14 & 1 & 128 & 4 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Segmentation parameters of each convolutional layer of VGG-16. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Registers** & **Address (In Hex)** & **Direction** & **Description** \\ \hline input\_channel & 00 & Input & Number of input channels \\ output\_channel & 04 & Input & Number of output channels \\ ifmap\_size & 08 & Input & Input feature map size \\ filter\_size & 0C & Input & Filter size \\ convfc\_sel & 10 & Input & CONV/FC selection 1 \\ base\_addr & 14 & Input & Image values base address \\ acc\_start & 18 & Input & Operation start: f000000 \\ complete\_fb & 1C & Output & Operation completion feedback \\ \hline \hline \end{tabular} \({}^{1}\)CONV: convolution; FC: fully connected computation.  
\end{table} 
Table 3: Description of the instruction registers. L', W', and C' are the length, width and channels of the segmented image, respectively. N\({}_{\text{L}}\), N\({}_{\text{W}}\), and N\({}_{\text{C}}\) are the number of segments in the three dimensions, respectively. The calculation expressions are as follows (ROUNDUP is the rounding up function):  
\[ \begin{array}{c}\text{N}_{\text{L}}=\text{ROUNDUP}((\text{L}-\text{K}+1)/( \text{L'}-2)),\\ \text{N}_{\text{W}}=\text{ROUNDUP}((\text{W}-\text{K}+1)/(\text{W'}-2)),\\ \text{N}_{\text{C}}=\text{ROUNDUP}((\text{C}-\text{K}+1)/(\text{C'}-2))\end{array}