# Large Field-Size Elliptic Curve Processor for Area-Constrained Applications
## 4 Implementation Results and Performance Comparison
### Results  
The implementation results on FPGA and ASIC devices are shown in Table 2 and Table 3, respectively. For FPGA implementations, we have provided results on Xilinx Virtex 7 (a modern 28 nm technology) device. Moreover, the synthesis results for ASIC is provided on a commercial 65 nm process technology. Concerning Table 2, the targeted field length \(m\) is shown in column one. Columns two to four provide the area results in slices, look-up-tables (LUTs) and flip-flops (FFs). The timing information in terms of clock cycles, frequency (Freq), latency and throughput (Thrpt) are given in columns five to eight. A figure-of-merit (FoM) is defined in terms of a ratio of throughput over slices to evaluate the performance of the proposed crypto processor. Similarly, considering Table 3, the targeted field length \(m\) is shown in column one. Column two shows the area (in mm\({}^{2}\)) results. The timing information in terms of clock cycles, frequency (Freq), latency and throughput (Thrpt) are given in columns three to six. A FoM is also defined in terms of a ratio of throughput over area. For FPGA and ASIC implementations, the area (slices, LUTs, FFs for FPGA) and frequency values are collected from the synthesis tool (Vivado IDE for FPGA and Cadence Genus for ASIC). The clock cycles calculation is already described in Section 3.4. Similarly, the latency and throughput values are calculated using Equation (4)and Equation (5), respectively. Finally, the figure-of-merit values are calculated using Equation (6). \[\textit{Latency}\ (\upmu\upmu)=\frac{\textit{Clock cycles}}{\textit{Clock frequency}\ (\text{MHz})} \tag{4}\]  
\[\textit{Throughput}\ (\textit{Thrpt})=\frac{1}{\textit{Latency}\ (\upmu\upmu)}=\frac{10^{6}}{ \textit{Latency}} \tag{5}\]  
\[\textit{FoM}=\frac{\textit{Throughput}\ (\textit{Thrpt})}{\textit{Area}\ (\textit{ slices for FPGA})} \tag{6}\]  
_Comparison of \(GF(2^{409})\) & \(GF(2^{571})\) on FPGA._ Table 2 demonstrates that the increase in the field length increases hardware resources (slices, LUTs and FFs). For example, the slices, LUTs and FFs for \(GF(2^{409})\) field are 0.78 (ratio of 4439 over 5683), 0.87 (ratio of 12,568 over 14,356) and 0.69 (ratio of 4129 over 5961) times lower than \(GF(2^{571})\) field. Similarly, the computational cost to execute one PM operation on \(GF(2^{409})\) field is 0.67 (ratio of 13,903 over 20,551) times lower than \(GF(2^{571})\) field. Moreover, on a modern Virtex 7 FPGA device, our proposed architecture can operate on a maximum 357 MHz and 317 MHz clock frequency over \(GF(2^{409})\) and \(GF(2^{571})\) fields, respectively. As for as the computational cost for one PM execution is concerned, our proposed architecture over \(GF(2^{409})\) and \(GF(2^{571})\) require 38.94 \(\upmu\upmu\)s and 64.82 \(\upmu\)s, respectively. This indicates that the 0.71 (ratio of 409 over 571) times increase in the field length (i.e., from \(GF(2^{409})\) to \(GF(2^{571})\)) results in 0.60 (ratio of 38.94 over 64.82) times increase in computation time. If we calculate the ratio of increase in the field length (0.71) with the increase in computation time (0.60), the proposed accelerator architecture over a larger \(GF(2^{571})\) field length is more efficient than the architecture over \(GF(2^{409})\) field. As shown in column eight of Table 2, the throughput of our proposed accelerator design over \(GF(2^{409})\) and \(GF(2^{571})\) is 25.68 kbps and 15.42 kbs, respectively. Concerning our defined FoM for comparison, the last column of Table 2 shows that the proposed accelerator architecture over \(GF(2^{409})\) is more efficient than \(GF(2^{571})\) field. One of the reasons is lower field length (i.e., 409). The lower field length utilizes lower hardware resources and takes lower computational time. Thus, the ratio of throughput over slices results in a higher value for lower field length. _Comparison of \(GF(2^{409})\) & \(GF(2^{571})\) on ASIC._ Similar to FPGA results, Table 3 shows that the increase in the field length increases area.