## 3 Results and Discussion
### The PVTC Method for the Logic Circuit  
First, we build the voltage level pdf at the output of the basic logic gate cell based on the PVTC method and MC simulation. Figure 11 presents the voltage pdf curve for the NAND gate with an input of \"11\" by these two methods.  
As shown in Figure 11, the majority of the output is distributed around \"0\", which is a correct result for the NAND gate. However, due to the influence of noise effects, a minority of the output voltage level is distributed around \"1\". We can also find that the pdf estimation results by two methods are highly similar. Furthermore, Figure 12a-f presents the level pdf for the NAND gate and NOR gate with different input combinations. In Figure 12, the dashed lines are the pdf curve estimated by the PVTC method, and the solid lines are the pdf curve acquired by the MC method. Figure 12 illustrates that the voltage pdf estimation curves obtained by the two methods are all highly similar for different input combinations, thus verifying the effectiveness of the proposed method. Moreover, Figure 12a,c illustrate that the probability of occurrence for a transient fault is less when the input is \"00\" compared to when the input is \"11\" for the NAND gate due to the logical masking effect of combinational circuits. We can observe similar phenomena based on the results of the NOR gate.  
To fully investigate the effectiveness of the PVTC method, a multi-gate circuit is also tested. Here, the full adder in Figure 7 is selected, which is a frequently used structure in pipeline stages. Because the result of \(N_{2}\) is determined by inputs \(A\) and \(B\) and node \(N_{1}\) is also related to inputs \(A\) and \(B\), there is a correlation between \(N_{1}\) and \(N_{2}\). Conditional probability should be considered. Figure 13a,b present the level pdf curve for the sum signal and carry signal of the full adder circuit, respectively. To provide  
Figure 11: The pdf estimation of the output of the NAND gate with input “1, 1”.  
a brief illustration of the result, only the result with an input of \"000\" is listed. We also implemented experiments using other input combinations and obtained similar results.  
A comparison of the results of the transient fault rate and the runtime between the PVTC and MC simulations is shown in Table 1. We also calculate the error between the results obtained by the PVTC and MC simulations, which is defined as follows: (PVTC-MC)/MC. The experiments are conducted on a PC with a 3.30 GHz Intel Core i3-2120, 3 GB RAM, and the 32-bit Windows 8 operating system. The PVTC method is implemented in a Matlab R2011b simulation environment, and the MC simulations are implemented in an HSPICE C-2009.9 environment. Table 1 shows that the error between the two methods is less than 9%, which is sufficient for the transient fault mitigation design requirement. Moreover, the computational cost of the PVTC method is far less than that of the MC simulation, as the PVTC method is approximately two orders of magnitude faster than the MC method. As the transient fault rate when the input is \"01\" is the same as the rate when the input is \"10\" for the NAND gate, we only list the transient fault rate when the input is \"01\" for the NAND and NOR gates in Table 1.  
Figure 12: The level pdf for the NAND and NOR gates with different inputs. (**a**) NAND “00”; (**b**) NAND “01”; (**c**) NAND “11”; (**d**) NOR “00”; (**e**) NOR “01”; (**f**) NOR “11”.  
Figure 13: PVTC analysis for a full-adder circuit. (**a**) Sum signal; (**b**) Carry signal.