## 1 Introduction
\begin{split} M\left(z\right)&=\prod_{i=0}^{P-1} \left(1+\left(\lambda^{\ast}z^{-1}\right)^{2^{\ast}}\right)\!\!\left(1+\left( \frac{z^{-1}}{\lambda^{\ast}}\right)^{2^{\ast}}\right)\\ M\left(z\right)&=\prod_{i=0}^{P-1}\left(1+\left( \left(\lambda^{\ast}\right)^{2^{\ast}}+\frac{1}{\left(\lambda^{\ast}\right)^{ 2^{\ast}}}\right)z^{-2^{\ast}}+z^{-2^{-2^{-2^{-2^{-2^{-2^{-2^{-2^{-2^{-2^{- 2}}}}}}}}}}\right.\end{split}  \tag{4}\]  
The linear phase approximation of a stable IIR filter \(H_{\text{c}}(z)\) with a _complex_-conjugate pole pair \(\lambda=re^{+\
icefrac{{\mu}}{{\theta}}}\) and \(\lambda^{\ast}=re^{-\
icefrac{{\mu}}{{\theta}}}\), can be designed by determining \(\left|H_{\text{c}}^{\cdot}\left(e^{i\alpha_{\text{c}}}\right)\right|=\left|H_{ \text{c}}\left(e^{i\alpha_{\text{c}}}\right)\right|^{\
icefrac{{1}}{{2}}}\) and approximating the poles \(\lambda^{\prime}=r^{\prime}e^{-\
icefrac{{\mu}}{{\theta}}}\) and \(\lambda^{\ast}=r^{\prime}e^{-\
icefrac{{\mu}}{{\theta}}}\) of \(H_{\text{c}}^{\prime}(z)\) with:  
\[M\left(z\right)=\prod_{i=0}^{P-1}\left[1+\left(2\left(\left(r^{\ast}\right)^{ 2^{\ast}}+\left(r^{\ast}\right)^{-2^{\ast}}\right)\cos\left(2^{\ast}\theta^{ \ast}\right)\right)z^{-2^{\ast}}+\left(\left(r^{\ast}\right)^{-2.2^{\ast}}+4 \cos^{2}\left(2^{\ast}\theta^{\ast}\right)+\left(r^{\ast}\right)^{2.2^{\ast}} \right)z^{-2.2^{\ast}}\right] \tag{5}\]  
Despite the advantage of the logarithmically more efficient use of multipliers and adders, MFIR filters have not been popular. Indeed, the large number of delay elements required to approximate the behavior of an IIR filter was considered prohibitively expensive. This made them impractical for implementation on standard DSP platforms with fixed memory maps. Advances in Very Large Scale Integration VLSI technology in general, and Field-Programmable Gate-Array (FPGA) architectures in particular, make it necessary to re-evaluate MFIR filters and the technical barriers to their widespread use. Several applications and implementations of MFIR filters in modern FPGA fabrics [4; 5; 6], have shown that FPGAs are an ideal target platform for implementing efficient MFIR filters that are competitive to standard FIR and IIR equivalents implemented on the same fabric. The effects of coefficient-quantization have been studied and have shown that MFIR filter structures are less coefficient-quantization susceptible than the IIR filter they approximate [7]. It is clear from Equations (2-5) that MFIR filters are basically a cascade of simple sparse FIR filters. An example of a cascade of three MFIR stages realizing an MFIR filter approximating a real pole is given in Figure 1.  
Every stage in an MFIR filter has the same structure as the other stages but the number of delay elements differs. Therefore, it is obvious to design an optimized component that implements a general MFIR stage per MFIR filter approximation, _i.e._, a real pole approximation, a complex-conjugate pole pair approximation and their respective linear phase types. Figure 1: General architecture of an MFIR filter approximating a real pole (three stages). As floating-point arithmetic is only recently available in FPGAs, only fixed-point arithmetic is taken into consideration. Unfortunately, every fixed-point addition or multiplication requires a widening of the bus width, which has to be avoided; this implies that rounding must be applied to keep the data path widths manageable and implementable. In this text, rounding is defined as the process whereby the width of the data path after a multiplication or an addition is reduced to the original width of the data path before the multiplication or addition. This is done by taking the most significant bits, conventional rounding of the result, and using saturation if necessary. Scaling is defined as the process that changes the filter coefficients in order to increase the SNR based on the fulfillment of a specified criterion (as will be defined in Section 3) at the output of the filter.