## 1 Introduction  
Due to the current semiconductor material and limitations of the manufacturing process, analog-to-digital converters (ADCs) are unable to maintain a high conversion accuracy at a very high conversion speed. There is an irreconcilable contradiction between conversion speed and conversion accuracy. As the only interface between analog and digital parts of electronic devices, the contradictory relationship between conversion speed and conversion accuracy of ADCs has limited the development of digitalization to a certain extent. The use of time-interleaved analog-to-digital converter (TIADC) technology can theoretically increase the conversion speed of ADCs without reducing ADC conversion accuracy. The block diagram of the four-channel TIADC system and the trigger clock signal of each ADC are shown in Figure 1. The basic principle of the TIADC system is that \(M\) ADCs are interleaved sampled under the trigger of \(M\) interleaved clock signals. After the conversion, the converted data is output at the interleaved time by multiplexing technology, which can theoretically increase the conversion speed of the original single chip ADC by \(M\) times [1]. However, the TIADC system has strict matching requirements for the ADCs in the system, and a slight mismatch of the ADCs in the system will significantly reduce the performance of TIADC. Time skew mismatch, gain mismatch, and offset mismatch of ADCs have a large impact on the TIADC system, and the technology used to calibrate the effects of these mismatches has been well studied to date [2; 3; 4; 5; 6]. The gain mismatch error and offset mismatch error are linear errors, which are relatively easy to calibrate, and their calibration method is now mature. Therefore, among the three major mismatch errors, many studies have been undertaken on the calibration of time skew mismatch errors and many calibration methods have been proposed [7; 8]. In recent years, due to the improvement in calibration techniques for the mismatches mentioned above in TIADC systems, research has increasingly begun to focus on other mismatch errors for TIADC systems [9; 10; 11]. This paper focuses on the estimation of the memory nonlinear mismatch error of TIADC and its calibration. A previous paper [12] proposes a static nonlinear model of TIADCs, which can model the differential nonlinearity (DNL) and integral nonlinearity (INL) of ADCs well. However, it does not consider the memory effect of the internal electronic components in ADCs. Moreover, although the calculation of its calibration is simple, it is not ideal for real systems, and its practical calibration effect is limited. Currently, the description of memory systems or nonlinear systems is usually described by the Wiener model, Hammerstein model, Wiener-Hammerstein model, Volterra model, etc. Among these, the Volterra model is an extension of the power series and has many unique advantages in describing the memory nonlinearity of TIADC systems. It can not only describe the nonlinear mismatch in TIADC systems and the effect of memory effects on the system at the same time, it can also describe the effect of mismatches generated by gain, offset, and frequency response mismatches. Due to these advantages, the Volterra series is widely used in describing systems in electronics, remote sensing, medical, and other fields [13; 14; 15; 16; 17; 18]. However, the main difficulty in modeling memory nonlinearity for TIADC systems using the Volterra model currently lies in the estimation of the kernels for each order of the Volterra series. A previous paper [19] proposes an offline calibration method that uses a least squares (LS) method for the TIADC output to estimate the error parameters of the memory nonlinear mismatch. Its method design is simple and the error parameter estimation can achieve great accuracy when the quantity of input data is large enough, but it eventually leads to slow calculation speed and cannot meet the system requirements for real-time conversion speed.