## 3 Proposed Modulo (\(2^{n}\pm 1\)) Multiplier Based on Radix-4 Booth Encoding  
The system architecture of the proposed modulo (\(2^{n}\pm 1\)) multiplier based on radix-4 Booth-encoding is shown in Figure 5. The proposed modulo (\(2^{n}\pm 1\)) multipliers can support modulo (\(2^{n}+1\)) and modulo (\(2^{n}-1\)) multiplication functions in the same circuit hardware. Compared with the traditional modulo (\(2^{n}+1\)) or modulo (\(2^{n}-1\)) multipliers, the proposed multipliers can use the same architecture to distinguish between two different operations by selecting signal T. When T = 1, the modulo (\(2^{n}+1\)) multiplier is selected and, when T = 0, the modulo (\(2^{n}-1\)) multiplier is selected. The operation ranges of the multiplicand and multiplier are [0, \(2^{n}+1\)) and [0, \(2^{n}\)] for the modulo (\(2^{n}+1\)) multiplier and modulo (\(2^{n}-1\)) multipliers, respectively. The proposed modulo (\(2^{n}\pm 1\)) multiplier system architecture, shown in Figure 5, includes a partial product circuit unit, a correct circuit unit, an IEAC CSA tree, and a parallel prefix modulo (\(2^{n}\pm 1\)) adder. For the partial product circuit unit, the circuit architectures of BE and BS use the same circuit reported in [2], as shown in Figure 4. For each BS row array in the partial product, in the specific BS block with \(a_{7}\) input, the output signal is XOR with selection signal T, and the output of the XOR gate will feed into the next BS block stage. To increase the operating range of the modulo (\(2^{8}+1\)) and modulo (\(2^{8}-1\)) multipliers (for modulo (\(2^{n}+1\)) and modulo (\(2^{n}-1\)) multipliers, \(n\) is set to 8), as shown in Figure 5, the OR gate is used to connect \(b_{8}\) and \(b_{7}\) and the output of this OR gate will be subjected to an AND gate with selection signal T for the BE input of the first row and second row in the partial product block. An appropriate circuit unit is used to produce the compensation values for obtaining accurate output values for modular multiplication operations using modified Booth-encoding schemes. In the IEAC part, for the structure of the modulo (\(2^{n}-1\)) multiplexer, the original value of end-around-carry is retained. For the structure of the modulo (\(2^{n}+1\)) multiplexer, the original value of end-around-carry will be reversed. The proposed improved parallel prefix  
Figure 4: (**a**) Circuit of the Booth encoder [2] and (**b**) Circuit of the Booth selector [2].  
adder of modulo (\(2^{n}\pm 1\)) multipliers based on radix-4 Booth encoding (\(n=8\)) is shown in Figure 6. Assuming that the T signal passes through the XOR gate, when the signal is 0, the modulo (\(2^{n}-1\)) adder is calculated, and when the signal is 1, the modulo (\(2^{n}+1\)) adder is calculated.  
As an example of the proposed multifunction modulo (\(2^{n}\pm 1\)) multiplier based on radix-4 Booth encoding, \(n=8\) is chosen. Figure 7a,b show the operation process of the proposed modulo (\(2^{n}\pm 1\)) multiplier. For the modulo (\(2^{n}-1\)) multiplication operation with T = 0, A = 256, and B = 256, the final result is 1 (Figure 7a) and, for the modulo  
Figure 5: Proposed architecture of modulo (\(2^{n}\pm 1\)) multipliers based on radix-4 Booth encoding (\(n=8\)).  
(\(2^{n}+1\)) multiplication operation with T = 1, A = 256, and B = 256, the final result will be 1 (Figure 7b).  
In the next section, the proposed FPGA implementation of radix-4 Booth-encoding-based multifunction modulo (\(2^{n}\pm 1\)) multipliers are experimentally analyzed, and the results are compared with those of other methods in terms of the operation range, area, delay time, dynamic power, area-delay product (ADP), and power-delay product (PDP).  
Figure 6: Proposed improved parallel prefix adder of modulo (\(2^{n}\pm 1\)) multipliers based on radix-4 Booth encoding (\(n=8\)).  
Figure 7: Example of the proposed modulo (\(2^{n}\pm 1\)) multiplication operation (\(n=8\)). (**a**) T = 0; (**b**) T = 1.