# A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR
## 3 Experimental Results  
The proposed 100 Gb/s quad-lane SerDes receiver was implemented in a 40 nm CMOS process. Figure 10 shows the layout of the quad-lane SerDes receiver composed of four CTLEs, one shared MDLL, and four CDRs. The total active area of the quad-lane SerDes receiver is only 780 \(\upmu\)m \(\times\) 450 \(\upmu\)m (= 0.351 mm\({}^{2}\)). To achieve an aggregate data rate of 100 Gb/s, the proposed four-channel SerDes receiver consumes a total power of 241.8 mW (MDLL = 24.2 mW, CTLE \(\times\) 4 ea = 81.6 mW, CDR \(\times\) 4 ea = 136 mW), which results in a high-energy efficiency of 2.418 pJ/bit. Figure 11 shows the locking process of the proposed 25 Gb/s/lane quarter-rate all-digital CDR. When the CDR is activated, the initial tracking mode operates for 36 CLKcont cycles by using a repeated preamble of the \"0000111\" pattern to achieve a fast acquisition time and a constant data output sequence, where the CDR update rate is 3.125 GHz (= 0.32 ns). When the initial tracking mode is completed, and the DATA#1 output is synchronized to Dclk0, then the CDR enters the sequential tracking mode and performs 2x-oversampling. By controlling the decimation factor of the DLF, the CDR update rate can be adjusted to have \(f_{\rm{CLKcont}}\)/4 or \(f_{\rm{CLKcont}}\)/8 to minimize the dithering jitter. As shown in Figure 11, the lock time of the proposed CDR is only less than 12 ns. Figure 10: Layout of the proposed quad-lane SerDes receiver core block. Figure 9: Block diagram of the proposed multi-phase MDLL. Figure 12 shows the simulated locking process of the proposed CDR at 25 Gb/s/lane. When the CDR starts, the phase error (\(\Delta\)t) between the Dclk0 and the ideal lock point is about 70 ps. After the initial tracking mode using the preamble data pattern is finished, it can be confirmed that the phase error \(\Delta\)t becomes zero, and the CDR input D0 is synchronized to Dclk0. Figure 13 left shows the simulated eye diagram of the CTLE input when the channel loss is about 22.6 dB at 12.5 GHz, where the input data eye is completely closed. Figure 13 right shows the simulated  
Figure 11: Locking process of the proposed 25 Gb/s quarter-rate digital CDR. Figure 12: Simulated locking process of the proposed CDR at 25 Gb/s. eye diagram at the CTLE output operating at 25 Gb/s with a 2\({}^{31}\)-1 pseudorandom bit stream (PRBS) data pattern, where the data eye is opened with 0.67 unit interval (UI) (= 27 ps). Figure 14 shows the eye diagram of the recovered quarter-rate 6.25 GHz clock (Dclk0), which has a p-p jitter of 18 ps and a root mean square (RMS) jitter of 3.5 ps, respectively, when DF = 1/4. When DF = 1/8, it shows an improved p-p jitter of 16.5 ps and an RMS jitter of 3.5 ps, respectively. Figure 15 shows the eye diagram of the recovered quarter-rate 6.25 Gb/s data, which has a p-p jitter of 22 ps and an RMS jitter of 3.7 ps, respectively, when DF = 1/4. When DF = 1/8, it shows a p-p jitter of 20.5 ps and an RMS jitter of 3.6 ps, respectively. Figure 14: Post-layout simulation results of the recovered quarter-rate clock with decimation factor (DF) = 1/4 and 1/8. Figure 13: Post-layout simulation results of the proposed 25 Gb/s/lane CTLE operation with PRBS31 data sequence. Figure 15: Post-layout simulation results of the recovered quarter-rate data with DF = 1/4 and 1/8. Table 1 summarizes the performance of the proposed all-digital CDR with the state-of-the-art PI-based CDRs. The results in this work are the post-layout simulation values. It can be confirmed that the proposed CDR has the best energy efficiency of 2.34 pJ/bit (= 2.34 mW/Gb/s). Additionally, Ref. [29; 32] require a high-frequency clock generator of 10 GHz or higher as an external reference clock source. This means that the use of an additional PLL circuit, which has the disadvantage of power consumption and silicon area increase. Table 2 provides a comparison between this work and some recently published multi-lane SerDes receiver chips.