# A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer
## 4 Conclusions  
A summary of the performance achievements of this research is shown in Table 2. In the DSM operated with high OSRs, high-speed input buffers are required to drive the input stage of the DSM. The overall performances of the DSMs are highly dependent on the characteristics of the input buffers. The pre-charge scheme can relax the requirement of the input buffers. However, still low noise input buffers are required. Moreover, it is hard to optimize the power consumption and performance of the system using the commercial-off-the-shelf (COTS) components. In this paper, a single-bit incremental second-order DSM with a fully integrated coarse-fine input buffer without an external buffer was presented. In the coarse-fine input buffer, two parallel buffers, the pre-charge buffer and fine-settling buffer, are included. Using the coarse-fine input buffer, both the fast settling and low noise characteristics can be achieved. The proposed input buffer achieved an ENOB and SINAD of 13.14 and 80.87 dB, respectively. The modulator operates a single bit and sampling clock at 125 kHz. The proposed DSM was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-\(\upmu\)m CMOS process with an active area of 1.06 mm\({}^{2}\). The total current consumption with the coarse-fine buffer was 1.374 mA.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & **This Work** & \begin{tabular}{c} **ISCAS 2021** \\ [25] \\ \end{tabular} & \begin{tabular}{c} **ISSCC 2022** \\ [26] \\ \end{tabular} & \
\begin{tabular}{c} **IEICE 2018** \\ [27] \\ \end{tabular} &
\begin{tabular}{c} **BIOCAS 2018** \\ [28] \\ \end{tabular} \\ \hline Process(\(\upmu\)m) & 0.18 & 0.18 & 0.065 & 0.18 & 0.18 \\ Supply voltage (V) & 1.8 & 1.8 & 1.2 & 1.8 & 1.8 \\ Current consumption (A) & 1.374 m & 480 \(\upmu\)m & 61.9 \(\upmu\)m & 81.5 \(\upmu\)m & 14 \(\upmu\)m \\ Oversampling rate & 512 & 128 & 5 & - & 256 \\ Order of modulator & 2 nd & 4 th & 4 th & - & - \\ DT/CT & DT & DT & CT & DT & CT \\ SINAD (dB) & 80.87 & 97.7 & 84.1 & 64.6 & 80 \\ ENOB (bits) & 13.14 & 15.97 & 13.67 & 10.34 & 13 \\ Sampling frequency (Hz) & 125 k & 6.144 M & 5 M & 10 k & 1 M \\ Pass band frequency (Hz) & 122.07 & 24 k & 500 k & - & 4 k \\ Buffer usage (V/N) & Y & Y & Y & Y & N \\ Settling time (s) & 130 n & - & - & 134 n & - \\ \hline \hline \end{tabular}
\end{table}
Table 2: Performance summary comparison between the proposed delta-sigma modulator with previous studies.  
Figure 19: Sinusoidal input signal and bitstream output.  
**Author Contributions:** Conceptualization and supervision, H.K.; circuit design, measurement, and draft preparation, M.Y.; investigation, K.N.; visualization, G.C.; methodology, S.K.; writing--review and editing, B.J.; format analysis, H.S.; conceptualization, K.K.; project administration, H.K.; funding acquisition, H.K. All authors have read and agreed to the published version of the manuscript.  
This work was funded by the Ministry of Health and Welfare (MOHW, Korea) and the Korea Health Industry Development Institute (KHIDI, Korea). This work was supported by the Practical Technology Development Medical Microrobot Program (R&D Center for Practical Medical Microrobot Platform, H19C0642); the Ministry of Science and ICT (MSIT), Korea, under the Information Technology Research Center (ITRC) support program (IITP-2021-2017-0-01635) supervised by the Institute for Information & Communications Technology Planning and Evaluation (IITP), and the Nanomedical Devices Development Project of NNFC.  
Not applicable.  
The EDA tool was supported by the IC Design Education Center (IDEC) in Korea.  
The authors declare no conflict of interest.