# Balancing the Leakage Currents in Nanometer CMOS Logic--A Challenging Goal
###### Abstract  
The imbalance of the currents leaked by CMOS standard cells when different logic values are applied to their inputs can be exploited as a side channel to recover the secrets of cryptographic implementations. Traditional side-channel countermeasures, primarily designed to thwart the dynamic leakage behavior, were shown to be much less powerful against this static threat. Thus, a special protection mechanism called Balanced Static Power Logic (BSPL) has been proposed very recently. Essentially, fundamental standard cells are re-designed to balance their drain-source leakage current independent of the given input. In this work, we analyze the BSPL concept in more detail and reveal several design issues that limit its effectiveness as a universal logic library. Although balancing drain-source currents remains a valid approach even in more advanced technology generations, we show that it is conceptually insufficient to achieve a fully data-independent leakage behavior in smaller geometries. Instead, we suggest an alternative approach, so-called improved BSPL (iBSPL). To evaluate the proposed method, we use information theoretic analysis. As an attack strategy, we have chosen Moments-Correlating DPA (MCDPA), since this analysis technique does not depend on a particular leakage model and allows a fair comparison. Through these evaluation methods, we show iBSPL demands fewer resources and delivers better balance in the ideal case as well as in the presence of process variations. s +
Footnote †: journal: Applied Sciences  
article  
[color=gray!20,linewidth=0.5,linewidth=0. could be captured in sufficiently high quality to perform such attacks in real world experiments. Hence, several practical evaluations has been conducted on the subject [10; 11; 12; 13; 14; 15; 16; 17]. It was not only confirmed that those attacks are indeed feasible, but also that this source of information leakage can become the most informative side channel in certain scenarios. In detail, it was shown that the effectiveness of static power attacks can be increased exponentially by manipulating the operating conditions of devices [14; 16]. Previous works also demonstrated that common side-channel countermeasures against dynamic leakage behavior are less effective against its static counterpart [8; 10; 12; 16; 17]. For instance, due to a possibility to limit the noise in static power measurements, adversaries can exploit higher-order leakages of masked implementations with a lower data complexity [11; 12; 16]. The general consensus of all cited works is that static power attacks are indeed a real threat and that dedicated countermeasures must be developed to prevent this side channel from affecting the security of cryptographic circuits in advanced semiconductor technologies. Related Work. In recent years, first potential countermeasures against static power side-channel analysis (SPSCA) have been investigated [18; 19; 20; 21; 22; 23; 24; 25; 26]. Similar to the early situation in the field of DPA countermeasures, most of these approaches fall into the hiding category [2] and can be split into two major groups, randomization [18; 23; 24; 25] and equalization [19; 20; 21; 22; 26; 27]. Randomization approaches aim to reduce the signal-to-noise ratio (SNR) by generating additional noise to bury the signal in (either on-demand or on a constant basis). This is done, for example, by dedicated ring oscillator circuits [18]. Equalization approaches aim to reduce the data dependency of a circuit's dissipation to decrease the exploitable signal. The latter are also known as balancing techniques and come in different flavors. Some are based on conventional standard cells [20]; others require custom cell design [22; 26; 27]. Some are specifically targeting Hamming weight dependencies [19; 21]; others attempt to generally reduce the current variations depending on the input [20; 22; 26; 27].