## 6 Various Criteria for Assessing the Power Quality and Efficiency of the Studied System
### Power Quality
#### 6.1.2 Common-Mode Voltage (CMV)  
In three-phase sinusoidal power systems, balance and symmetry are fundamental under normal operating conditions. The phase voltages naturally compensate each other, and grounding the source's neutral point reinforces this symmetry. However, when a three-phase pulse width modulation (PWM) inverter is employed, the switching of asymmetrical voltages introduces a DC voltage (\(V_{dc}\)) across the load phases. This deviates from the ideal sinusoidal behavior, as the instantaneous sum of the load terminal voltages is no longer zero. This deviation leads to the emergence of CMV between the load and ground [135]. CMV results from the high-frequency switching of inverter devices. The common-mode currents induced between the stator windings and ground can have serious consequences, such as premature bearing degradation, increased thermal losses, and an overall decline in motor performance [73]. The CMV generated by the inverter can be expressed by the following equation [136]:  
\[V_{cmv}=\frac{1}{3}(V_{a}+V_{b}+V_{c}) \tag{15}\]  
In DTLI systems, like the one shown in Figure 5, the CMV for each inverter can be calculated using the formulas provided in the study of [58]:  
\[V_{cmv_{i}}=\frac{S_{i1}+S_{i3}+S_{i5}}{3}V_{dc} \tag{16}\]  
\[V_{cmv_{j}}=\frac{S_{j1}+S_{j3}+S_{j5}}{3}V_{dc} \tag{17}\]  
Consequently, the CMV of DTLIs can be calculated as follows [137]:  
\[V_{cmv}=\frac{V_{cmv_{j}}+V_{cmv_{j}}}{2} \tag{18}\]  
\[V_{cmv}=\frac{\left(S_{i1}+S_{i3}+S_{i5}\right)+\left(S_{j1}+S_{j3}+S_{j5} \right)}{6}V_{dc} \tag{19}\]  
In the context of DTLI systems, CMV-related issues become more critical due to the frequent high-frequency switching of the inverters' switches. This rapid switching can shorten motor life and increase the risk of inverter failure. Moreover, the impact of these issues is amplified by factors such as shaft voltages, bearing currents, and electromagnetic disturbances caused by common-mode leakage currents [138]. The effects of CMV on the system are primarily influenced by the parasitic parameters between the motor and ground. Among these, parasitic capacitance \((C_{s})\) and parasitic resistance \((R_{b})\) are crucial in the generation of bearing current, an undesirable component that can negatively affect the system's performance. A schematic diagram (Figure 16) effectively illustrates how these parasitic parameters contribute to bearing current generation in response to CMV. One of the key advantages of a DTLI connection is its ability to attenuate CMV, thereby mitigating the problems associated with it. The combination of spatial vectors resulting from the use of DTLIs leads to a variety of CMV levels, as thoroughly demonstrated in Table 3. From this table, it is evident that large vectors (such as \(V_{i1}V_{i4}\), \(V_{i2}V_{i5}\), \(V_{i3}V_{i6}\), \(V_{i4}V_{j1}\)  
Figure 16: CMV equivalent circuit of an OEWM. \(V_{1S}V_{2}\), \(V_{6}V_{3}\)) and zero vectors (\(V_{18}V_{77}\), \(V_{17}V_{8}V_{8}V_{7}\), \(V_{72}V_{8}\)) effectively eliminate CMV. On the other hand, zero vectors (\(V_{72}V_{7}\), \(V_{8}V_{8}\)) and intermediate vectors (\(V_{i1}V_{j3}\), \(V_{22}V_{i4}\), \(V_{i3}V_{57}\), \(V_{i4}V_{j6}\), \(V_{58}V_{j1}\), \(V_{i6}V_{j2}\), \(V_{i1}V_{57}\), \(V_{i2}V_{j6}\), \(V_{i3}V_{j1}\), \(V_{i4}V_{j2}\), \(V_{5}V_{j3}\), \(V_{i6}V_{j4}\)) generate varying levels of CMV. CMV Reduction  
Various approaches have been developed to mitigate CMV, including the use of passive and active common-mode filters [139; 140; 141; 142]. However, the implementation of these devices introduces additional costs and significant power losses. As a result, PWM methods have become the preferred solution for two-level inverters, though they do not fully eliminate CMVs [143; 144]. In a previous study [145], an approach was presented that exclusively uses even or odd space vector combinations to reduce CMV from \(\pm V_{dc}/2\) to \(\pm V_{dc}/6\), without relying on null vector states, within a conventional two-level inverter.