## 4 Experimental Result and Discussion
### Kernel Optimization and Evaluation  
For the first-order analysis of the optimization techniques, we assessed efficiency and occupancy of 32 different combinations presented in Section 3.2. For this purpose, we wrote CUDA kernel functions that calculate the objective function \(\frac{1}{2}\left\|\mathbf{G}(x)-\mathbf{d}\right\|_{2}^{2}\) for the \(500\times 500\) mesh size. The results acquired from this experiment are shown in Figure 7. In Figure 7, both metrics were scaled with a minimum value of 0 and a maximum value of 1. Figure 7a shows that CSE is the most dominant factor for efficiency. From the experimental results, we observe that efficiency tends to be proportional to the degree of CSE. We also notice that the thread block size and constant caching options have little effect on efficiency since the thread block size and constant caching affect only computing resource allocation and utilization of the GPU. By contrast, a higher degree of CSE decreases occupancy in most cases, as depicted in Figure 7b. In the \"without CC\" option, there is little difference in occupancy between the L and ML options and the MH and H options. This is because the difference in the number of precomputed subexpressions between the L and ML options and the MH and H options is relatively small, as shown in Table 3. However, in the \"with CC\" option, the H option shows higher occupancy than the MH option. To analyze this cause, we compared the reduced number of reduced register usage by constant caching for each CSE option. Constant caching decreases register usage per thread in all CSE options. For example, in the L, ML, and H options, the number of register usage per thread reduced by constant caching becomes 12, 8, and 6, respectively. However, in the MH option, only two registers per thread are saved by constant caching, and thus constant caching has only a trivial effect on occupancy when the MH option is used. \begin{table}
\begin{tabular}{c c} \hline
**Type** & **Specification** \\ \hline OS & Ubuntu 18.04 \\ CPU & Intel® CoreTM i9-10900K @ 3.70 GHz \\ RAM & 128 GB \\ GPU & NVIDIA GeForce RTX 2080 SUPER \\ CUDA version & 11.0 \\ CUDA compute capability & 7.5 \\ Host compiler & g++ 7.5.0 \\ \hline \end{tabular}
\end{table} 
Table 5: Hardware and software specification for experiment environment. Since the maximum number of resident threads per SM is limited, the number of thread blocks in an SM decreases when a thread block size increases. For this reason, the larger the thread block size, the greater the loss of active warps per reduced thread block by resource limitation in SM. Therefore, we can conclude that a small thread block size leads to high occupancy and better thread-level parallelism. Then, we compared the computation time of each configuration to select the best CUDA optimization configuration with the shortest average computation time. To this end, we measured the computation time of 1000 test runs for the 500 \(\times\) 500 mesh size. As shown in Figure 8, the most remarkable enhancement appears when the degree of CSE changes from the ML to the MH, and the H option is the best configuration of CSE regardless of the other options of the two optimization techniques. As for the thread block size option, the computation time increases as the thread block size is enlarged. Furthermore, thus, the thread block size of 64 shows the best performance, up to a 5.3% reduction in the computation time than other thread block size options. Constant caching also slightly reduces the computation time by up to 3.7%. Finally, we selected [CSE, constant caching, thread block size]=[H, \"with CC\", 64] as the best CUDA optimization configuration for our application, called _CUDA_optimized_. We also set a baseline configuration for the performance comparison, called _CUDA_baseline_,  
Figure 8: Average objective function computation time of configurations. Figure 7: Performance metrics of configurations. (**a**) Efficiency; (**b**) Occupancy. with the configuration [L, \"without CC\", 64].