# FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
## 3 FPGA Counters Implementations
### Software-Like Counters  
It is quite easy to imagine a software counter. It is just a variable that is increment-ed/decremented in case of particular events. Hardware-based counters that are designed by means of D (or others) flip-flops are also well known. Hardware-based counters work very fast in relation to software counters. Software counters must be executed somehow by means of the program, so it lasts (Listing 1, Section 2). However, there is no problem to design a very big block of independent counters. It is clear that those counters cannot work concurrently, but it is not a problem in the PLC that by definition works serially. The drawback of hardware-based big counter structure is the flip-flop and connections utilization. So, the idea is to compound those two implementations--in a nutshell, to implement software idea in hardware. Figure 8: The structure of the hardware-based counter block with CAL. Figure 7: The structure of the hardware-based counter block. **Listing 5. ** Verilog description of the counter block with CAL. always @(posedge clk)  if (reset && ce)  cv <= 32'b0;  else  if(ce)  if (ld)  cv <= pv;  else  if (! (cu && cd))  if (cu && (cv < PV_MAX))  cv <= cv + 1'b1;  else  if (cd && (cv > PV_MIN))  cv <= cv - 1'b1;  
assign qu = cv >= pv;  assign qd = cv <= 0;  
Figure 9: RTL schematic of the proposed counter structure. To design software-like counters, memories that implement elements of the structure presented in Figure 2 are necessary. Of course, memories should be driven by means of CRs (CR_b and CR_W), enabling inputs that realize consent to store data to particular memories and common address inputs. However, it would not be good to read data to CR, perform operations and write back data to the memory. It would be time ineffective. The best way is to design MUXes that are driven by decoded instruction. The structure with only Counter Value as a circuit result is presented in Figure 11.  
The idea is based on a MUX, which decides what happens to the counter at any given event--increment, decrement, set, reset--depending on which counter instruction is currently being executed. The ENable bits for each instruction are involved in controlling the multiplexer, as well as the signal coming from the CR_b that conditions every change of the CV state. This signal additionally controls the ENable signal of the counter cell. In the first case, such writing is blocked using an additional AND gate. Similarly, the question can be asked whether it is necessary to continuously calculate the state of the binary outputs of the counter--QU and QD. Note that this may mean the determination of their state during each cycle of the loop, so it takes time. An alternative is to determine the state during the execution of the command testing the binary state of the counter. The third solution requires additional memory, but the QU and QD calculation is executed once during CAL. Calculating the state of the binary outputs requires, of course, performing the comparison operation, which, in case of the existence of the CAL operation, is done during the execution of this operation. A fragment of a program for calculating the binary state of the counter, using the basic operations of the controller, could look as it is presented in Listing 6. Figure 10: The structure of the counter function block for four counters. // QU  LD CNT.CV  GE CNT.PV (GE - Greater or Equal)  ST CNT.QU // QD  LD CNT.CV  LE 0 (LE - Less or Equal)  ST CNT.QD
```

The implementation of such a program would only require that the computing unit have access to the current state of the counter (CV) and the Preset Value (PV) cell. The structure of soft-like counters block dedicated for short operators is shown in Figure 12. The most important element of the structure is the CV memory, which stores the current counter state. The multiplexer on the data input of this memory allows us to write the value from the PV memory, to keep the current value of the counter or to write a value modified by count up, count down or reset operation.