# A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures
## 1 Introduction  
Digital cores that are currently incorporated into advanced and up-to-date Systems on Chip (SoC) usually include Logic Built-In Self-Test (Logic BIST, LBIST) modules. A very popular LBIST architecture operated in the test-per-scan mode is STUMPS (Self-Test Using MISR/Parallel Shift register sequence generator) [1, 2] (pp. 288-290), [3] (pp. 176-177), [4] (pp. 522-525), or various versions of it [5, 6, 7, 8, 9]. The structural diagram of a typical LBIST module with the STUMPS architecture as depicted in Figure 1 includes some key components, such as a generator of pseudo-random tests, or more specifically, a Pseudo-Random Pattern Generator (PRPG) and a Multi-Input Signature Register (MISR). The PRPG module is intended to supply pseudo-random sequences of bits simultaneously to all scan paths of a circuit to be tested, and these sequences are then delivered as parallel test vectors to inputs of combinational logic blocks of such a Circuit Under Test (CUT). A PRPG module is usually designed as a shift register with linear feedback (Linear Feedback Shift Register--LFSR) [3] (pp. 65-71, 176-177), although Cellular Automata (CA) can also be used for these purposes [3] (pp. 72-75), [10, 11, 12, 13]. Some specific solutions may also comprise other types of linear registers such as PRPG modules, for instance Galois Linear Feedback Shift Register (GLFSR) [14, 15, 16]. Responses to test vectors gathered from outputs of a CUT are loaded in the parallel mode into scan paths, and then scan paths are switched to the serial mode and information from all scan paths is supplied to inputs of the MISR module where information is subject to compaction (lossy compression). The final content of the MISR is referredto as the signature, which provides information on whether the CUT is faulty or not. The substantial advantage of LBIST structures with the STUMPS architecture consists of the fact that such solutions offer much shorter testing times as compared to conventional built-in self-test solutions operated in the test-per-scan mode since pseudo-random sequences of bits are supplied simultaneously to a plurality of scan paths [3] (pp. 176-177). Although STUMPS architecture appeared as early as the 1980 s, it is still quite popular and constantly in use. There are numerous studies where researchers make efforts to improve the solution in terms of hardware overhead, testing time, power consumption, fault coverage, diagnosability, etc. [17; 18; 19; 20; 21; 22; 23; 24; 25; 26]. Some variations of the STUMPS architecture are implemented into hybrid LBIST, where pseudo-random testing is combined with deterministic testing or test data compression [27; 28; 29; 30; 31; 32].  
The remainder of this study shall have the following structure. Section 2 deals with some problems with fault coverage that may happen to basic options of the LBIST structure with the STUMPS architecture and explains the reasons for such problems. Section 3 outlines how PRPG modules are usually designed to remedy the aforementioned problems. New concepts for the implementation of PRPG modules into LBIST circuits with the STUMP architecture are shown in Section 4, where the implementation of specific DT-LFSR ring linear registers is proposed. The innovative structure, operation principle, and key properties of DT-LFSR Test Pattern Generators (DT-LFSR-TPG), designed according to the concept shown in previous sections, are brought together in Section 5. The logical synthesis results of the new type of pseudo-random pattern generators are presented in Section 6. The study ends up in Section 7 with a discussion of the results obtained, recapitulation, and key conclusions.