# A 2-V 1.4-dB NF GaAs MMIC LNA for K-Band Applications
## 3 Proposed Circuit  
The amplifier is implemented using the models of the 100-nm UMS PH10 GaAs pHEMT process, characterized by a 130-GHz transit frequency (\(f_{T}\)) and 1-dB NF @ 30 GHz. The schematic implementation of the proposed circuit is depicted in Figure 3, and the corresponding layout is shown in Figure 4.  
Figure 3: Proposed four-stage GaAs LNA detailed schematic. Ground-signal-ground (GSG) pads with 150-\(\upmu\)m pitch are used for the input and output RF signals. The gate voltages of each stage are provided through DC pads VG1, VG2, VG3, and VG4. Similarly, DC pads VD1, VD2, VD3 and VD4 are used to bias the drain voltage of each stage with 2 V. Instead of relying on inductors to bias the active devices as RF chokes, we use quarter-wavelength (\(\lambda\)/4) TLs with a length of 1 mm and a shunt capacitor of 0.53 pF. These bias lines are oversized to comply with the maximum ratings defined by the process design kit (PDK) to avoid electro-migration and aging issues. The main advantage of using \(\lambda\)/4 TLs is that, if designed correctly, they barely affect the matching networks and result in an almost negligible impact on the LNA's overall NF and gain. Additionally, in order to provide DC isolation, a 0.58-pF DC block capacitor (CB) is used in the interstage matching networks as an additional component. Since a very low NF is pursued, the designer must carefully choose the bias currents and inductances for each stage. Therefore, the first stage employs a device of four fingers with 5 \(\upmu\)m each, resulting in a total width of 20 \(\upmu\)m, and is biased with a current density of 0.47 mA/\(\upmu\)m for minimum NF and low-power operation. Since the first stage achieves a very low NF (about 1 dB @ 26 GHz) but a limited gain (about 6.5 dB for the same frequency), the next stages are biased with a higher current density of 0.53 mA/\(\upmu\)m to obtain a 9-dB gain-per-stage at the expense of a slightly higher NF. The device geometry selected for stages 2, 3 and 4 is 4 \(\times\) 7.5 \(\upmu\)m. Note that a \(V_{G}\) and a \(V_{D}\) of 0 V and 2 V are used to bias to all the transistors, respectively. Source degeneration is applied to all the CS stages since it prevents instability, reduces the NF, brings the \(S_{11}\) and \(S_{opt}\) closer together and increases the circuit resilience to process, voltage, and temperature (PVT) variations. The source transmission line (S1 in Figure 3) adds a small inductance which brings the \(S_{11}\) of the input transistor closer to \(S_{opt}\), as discussed in Figure 2b. The size of S1 is 420 \(\times\) 10 \(\upmu\)m\({}^{2}\), which is enough to ensure stability and a low NF for the first stage. The transmission lines S2, S3 and S4 are sized 200 \(\times\) 10 \(\upmu\)m\({}^{2}\), providing a lower inductance for a higher gain than the first stage. The selected source impedance for the first stage is equivalent to the device's \(S_{opt}\) and is given by (7). As seen, thanks to careful device sizing plus source degeneration, the real part of \(Z_{s1}\) is very close to 50 \(\Omega\). From the selected source impedance, one can obtain the  
Figure 4: Layout of the Low-Noise Amplifier. Pads 1, 2, 3 and 4 represent the terminals VG1, VG2, VG3, and VG4, respectively. Also, pads 5, 6, 7 and 8 represent the terminals VD1, VD2, VD3, and VD4, respectively. source reflection coefficient (\(\Gamma_{S}\)) and then the corresponding load reflection coefficient (\(\Gamma_{L}\)) by applying expression (8). After translating \(\Gamma_{L}\) into the load impedance \(Z_{L1}\), Equation (9) is obtained. Following this methodology, the source and load impedances for stages 2, 3 and 4 are obtained as (10) and (11), respectively. Since the interstage matching does not require any intermediate 50 \(\Omega\) termination, the stages are directly matched to each other.