## 3 Proposed FFT Kernel Architecture  
### Algorithm and Architecture Overview  
In conventional MDC/MDF FFT schemes [20; 21; 22; 23; 24; 25; 26], the number of paths is equal to the number of FFT streams. By contrast, a mixed-radix, mixed-multipath delay-feedback (MRM\({}^{2}\)DF) architecture was developed, which operated on a radix-dependent number of paths. For 128-point FFT operations, the MRM\({}^{2}\)DF design operated based on the mixed radix-2/8/8 algorithm, which can be described using Equations (1)-(5). A 128-point discrete Fourier transform (DFT) of a time domain sequence x(n), was defined as Equation (1), where X(k) and \(W_{128}^{nk}=\exp(-j2\pi nk/128)\) are the DFT results and twiddle factor, respectively. Moreover, n and k are represented using Equation (2), and Equation (1) can be derived using Equation (3), a two-step computation based on radix-2 and radix-64 operations  
Figure 5: Block diagram showing the hardware architecture of M-stream N-point FFT processor using a. four-stream 128-point FFT kernel. represented as BF2 and 64-point DFT, respectively. Between BF2 and 64-point DFT operations, 128-based (W128) twiddle factors must be multiplied with the BF2 output. Furthermore, the 64-point DFT operation in Equation (3) can be further decomposed into the radix-8/8 operation. By using Equation (4), a 64-point DFT can be derived as Equation (5), where two-stage radix-8 operations are performed. The two radix-8 stages correspond with the first and second butterfly 8 (BF8) operations, respectively. Similarly, 64-based (W64) twiddle factor multiplication is required between the first and second BF8 operations. For 64-point FFT operations, the MRM2 DF design executes the radix-8/8 algorithm as Equation (5). \[X(k)=\sum\limits_{n=0}^{127}x(n)\,W_{128}^{nk},\ k=0,\,1,\,\ldots,\,127 \tag{1}\]  
\[\left\{\begin{array}{l}n=64n_{1}+n_{  
* Points (i)-(iii) allow significant improvements in area efficiency compared with available designs that support multipath 128-point FFT (e.g., [21; 25]). Figure 6a presents the block diagram of the proposed MRM\({}^{2}\)DF FFT kernel, comprised of four modules (Modules 1-4). The operations associated with Modules 1-4 are illustrated in Figure 6b (association with color of Modules). Figure 6b shows that Module 1 is tasked with 4/5/6-path BF2 (radix-2) operations. Module 4 provides eight-path first and second BF8 (radix-8) computations. Intermediate data transfer for radix-2/8/8 calculations was achieved using a sorting buffer in Module 2. As mentioned previously, W\({}_{128}\) and W\({}_{64}\) twiddle factors must be multiplied with the output of the radix-2 and first radix-8 stage. Module 3 was a constant multiplication unit (CMU) for performing twiddle factor multiplications by using a novel resource-sharing scheme. Modules 1-4 are detailed in Section 3. For 64-point FFT, only Modules 2 and 3 were used to perform radix-8/8 operations. For example, for the six-stream 1024-point MDF FFT, Figure 7 shows an operation flow to generate a 128-point FFT block based on the MDF processing (Figure 5). In most OFDM standards (e.g., IEEE 802.11 ac for WiFi), the GI period is 1/4 or 1/8 of the symbol duration, depending on the channel conditions. For example, six streams of 1024 data samples were accessed to perform 1024-point FFT operations, and the number of GI samples was 256 (i.e., 1/4 symbol duration). Figure 5 shows that this mechanism allowed the calculation of six-stream 1024-point FFT through the radix-2\({}^{3}\) stages and 128-point FFT block. The corresponding radix-2\({}^{3}\) signal flow chart with the radix-2 (BF2) operations is shown in Figure 7 for reference. Through the three stages of MDF-based radix-2 operations (including twiddle factor multiplication), sets of 512/256/128-point FFT sequences were generated (corresponding with the color and slash in the signal flow chart). Finally, eight sets of six-stream sequences were generated, including 128 data and 32 GI\({}^{\prime}\) samples.