# Safety-Oriented System Hardware Architecture Exploration in Compliance with ISO 26262
## 4 Safety-Oriented System Hardware Architecture Exploration Framework
### System Hardware Architecture Exploration with Safety and Hardware Overhead Consideration
#### 4.3.2. ASIL-Oriented Hardware Architecture Exploration Algorithm
Then the \(DC_{DPF,L_{PT(c)}}\) for C(3) and C(4) can be decided according to the updated \(Gap_{SM,D}\) as illustrated in Table 6.

Then, the hardware architecture metrics can be updated in accordance with the deployed safety mechanisms as stated in the following:

\[\sum_{Safety-Related\ HW\ elements}\lambda_{s}=1.2\times 10^{-8}\]

\[\sum_{Safety-Related\ HW\ elements}\lambda_{SPF}=\lambda_{C(1)}+\lambda_{C(2)}=1.2\times 10^{-7}\]

\[\sum_{Safety-Related\ HW\ elements}\lambda_{RF}=\sum_{i=3}^{4}\lambda_{C(i)} \times\left(1-DC_{RF_{C(i)}}\right)=3.65\times 10^{-8}\]

\[\sum_{Safety-Related\ HW\ elements}\lambda_{DPF,L}=\sum_{i=3}^{4}\lambda_{C(i)} \times DC_{RF}(C(i))\times\left(1-DC_{DPF,L_{C(i)}}\right)=3.38\times 10^{-8}\]

\[SPFM_{ite,d}=1-\frac{\sum_{Safety-Related\ HW\ elements}(\lambda_{SPF}+ \lambda_{RF})}{\sum_{Safety-Related\ HW\ elements}\lambda}=1-\frac{1.57\times 10^{-7}}{ 1.43\times 10^{-6}}=89.06\%\]

\[LFM_{ite,d}=1-\frac{\sum_{Safety-Related\ HW\ elements}(\lambda_{DPF,\ L})}{ \sum_{Safety-Related\ HW\ elements}(\lambda-\lambda_{SPF}-\lambda_{RF})}=1- \frac{3.38\times 10^{-8}}{1.274\times 10^{-6}}=99.0\%\]

\[PMHF_{ite,d}=\lambda_{SPF}+\lambda_{RF}+\lambda_{DPF,L}=1.9\times 10^{-7}\]

Compared to the \(PMHF_{tar}\), \(SPFM_{tar}\), and \(LFM_{tar}\) for target ASIL B, we can conclude that only \(LFM_{tar}\) has been achieved and \(PMHF_{ite,d}\) and \(SPFM_{ite,d}\) still violate the target values. Thus, another design iteration is required to perform the weak-point analysis and exploration algorithm again to deploy and/or upgrade the safety mechanisms. The results of the weak-point analysis for the updated hardware architecture are shown in Table 7.

From Table 7, we can observe that all the MBPs have been resolved. The results show that the proposed exploration algorithm improves the system hardware architecture's failure rates in an efficient fashion. However, the target ASIL is still not achieved even though no MBP exists. Thus, the most critical weak point among all MCSs marked as POD should be identified further. According to Table 7, \(\{C(1)\}\) is the most critical POD weak point. Then, Algorithm 1 is performed to assign an appropriate safety mechanism to C(1) according to its \(Gap_{SM,D}\). As a result, the \(DC_{RF_{PT(c)}}\) and \(DC_{DPF,L_{PT(c)}}\) for C(1) are both decided to be 60%. Furthermore, the updated hardware architecture metrics are \(SPFM_{ite,d}=92.24\%\), \(LFM_{ite,d}=96.06\%\), and \(PMHF_{ite,d}=1.63\times 10^{-7}\), respectively. The results demonstrate that the \(PMHF_{ite,d}\) is still greater than the target value and, hence, another design iteration is required. The process for the next design iteration is similar to \begin{table}
\begin{tabular}{c c c c} \hline \hline
**MCS** & \(Gap_{SM,D}\) & **Deployed SM** & \(DC_{DPF,L_{PT(c)}}\) \\ \hline \([C(3)]\),\(SM_{C(3)}\) & \(3.1613\times 10^{0}\) & SM\({}_{\text{MMM}}\) & 90\% \\ \([C(4)]\),\(SM_{C(4)}\) & \(1.1588\times 10^{1}\) & SM\({}_{\text{HHH}}\) & 99\% \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Safety mechanism deployment for the \(PT\) according to \(DC_{DPF,L_{PT(c)}}\). \begin{table}
\begin{tabular}{c c c c} \hline \hline
**MCS** & \(Gap_{SM,D}\) & **Deployed SM** & \(DC_{RF_{PT(c)}}\) \\ \hline \([C(3)]\) & \(2.5990\times 10^{0}\) & SM\({}_{\text{MyM}}\) & 90\% \\ \([C(4)]\) & \(1.0475\times 10^{1}\) & SM\({}_{\text{HyH}}\) & 99\% \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Safety mechanism deployment for the \(PT\) according to \(DC_{RF_{PT(c)}}\). iteration 1 and 2, and the changes of \(DC_{RF_{T(i)}}\) and \(DC_{DPFL_{T(i)}}\) for each hardware element in the following design iterations are summarized in Table 8.

After performing the six design iterations, the updated hardware architecture metrics are \(SPFM_{itc,d}=95.69\%\), \(LFM_{itc,d}=97.8\%\), and \(PMHF_{itc,d}=9.18\times 10^{-8}\). As a result, all the target values for achieving ASIL B have been satisfied. The deployed safety mechanisms for the hardware element C(1)-C(4) are SMMMM, SMLL, SMMMM, and SMHHH, respectively.