## 3 Results
### Devices Featuring Ni-ALD Dielectric-Ni Junctions
#### 3.2.1 SET Devices with Ni-SiO\({}_{2}\)-Ni Tunnel Junctions
However, for devices with 12 or 13 cycles treated with two anneal steps, the conductance matched the Simmons equation within an order of magnitude, suggesting the ALD growth had filled in the pinholes and both NiO layers had been mostly reduced. The cause of oxidation in the top Ni electrodes remains to be investigated, but the oxidation of metals when deposited on SiO\({}_{2}\) has been reported for Cu, Mo, and W and has been attributed to oxygen containing contaminants, such as water, on the oxide surface [40; 41]. Furthermore, substituting aluminum for nickel as the top electrode (Ni-SiO\({}_{2}\)-Al) resulted in devices that were all electrical opens (i.e., no measurable tunneling current). This can be explained as resulting from the aluminum layer  
Figure 8: Evidence of parasitic oxide: Experimental and simulated \(G(V_{ds})\) dependences for an untreated Ni-SiO\({}_{2}\)-Ni SET at different temperatures. oxidizing at the surface where it makes a contact with the SiO\({}_{2}\) film, just as the nickel layer had, but causing an even greater increase in resistance due to the large band gap of aluminum oxide. Likewise, substituting palladium for nickel on the top layer (Ni-SiO\({}_{2}\)-Pd) shows behavior indicative of the top palladium layer oxidizing at the metal-SiO\({}_{2}\) interface but unlike Al\({}_{2}\)O\({}_{3}\), this oxide can be reduced. These experiments suggest that the oxidation of the top metal layer is unavoidable (at least for oxide dielectrics such as Al\({}_{2}\)O\({}_{3}\) and SiO\({}_{2}\)) and that reducing the NiO at the top interface is therefore just as necessary as doing so at the bottom interface [11]. From the experiments described above it was concluded that 12-13 PEALD cycles of SiO\({}_{2}\) (\(\sim\)1.1 nm) are suitable for cross-tie SETs because the resulting conductance is sufficiently below the quantum conductance, \(G_{Q}\) = 1/\(R_{Q}\)\(\approx\) 40 \(\upmu\)S, required to suppress quantum fluctuations [16], but high enough (\(>\)10 nS) to avoid signal-to-noise ratio problems. 2.2 Limitations of the \"Double Anneal\" Reduction Technique and Search for Alternative Reduction Methods  
As described above, the proposed process for fabricating Ni-SiO\({}_{2}\)/Al\({}_{2}\)O\({}_{3}\)-Ni SETs requires two reduction steps to eliminate the parasitic NiO in series with the tunnel junctions. However, prolonged exposure of the device to elevated temperatures (\(>\)375 \({}^{\circ}\)C) results in thermally induced deformation of the Ni nanowires, referred to as agglomeration [42] and consequently open circuits. Figure 9 shows a micrograph of agglomeration occurring in an SET device as a result of FGA at 400 \({}^{\circ}\)C.  
In addition to the thermally-induced deformation of thin metal films during anneal, the experiments also reveal very significant \"switching\" RTS noise, similar to that observed in Pt-Al\({}_{2}\)O\({}_{3}\)-Pt devices (Figure 7). Figure 10a shows a measurement of conductance \(G(V_{ds})\) with high \(V_{ds}\) resolution of an SET device subjected to two FGA treatments. The experimental data highlight the important feature of this noise: for \(\mid V_{ds}\mid\)\(<\) 2\(E_{c}/e\) where Coulomb blockade is present, the conductance jumps between two or more states, but appears remarkably stable once Coulomb blockade is suppressed for \(\mid V_{ds}\mid\)\(>\)\(>\)\(E_{C}/e\). By contrast, the sweep of gate bias, \(V_{g}\), at \(V_{ds}\) = 0 mV (Figure 10b) reveals very strong intensity of the RTS noise almost uniformly occurring along the \(V_{g}\) axis. This behavior is consistent with random charge trapping/detrapping processes in the vicinity of the island (e.g., in the barrier dielectric) acting as a strong modulation randomly shifting the CBOs along the \(V_{g}\) axis. However, once Coulomb blockade is overcome (by applying \(\mid V_{ds}\mid\)\(>\)\(>\)\(E_{C}/e\)), these fluctuations are suppressed because the gate can no longer modulate the conductance.