## 5 Experimental Results  
In order to validate the proposed MMPC, an experimental prototype has been developed that is able to deliver \(1\) kW of power at a bus voltage of 75 V. The experimental prototype shown in Figure 10 consists of three PMs (M1, M2 and M3) built based on the proposed topology discussed in Section 3 with specifications shown in Table 1.  
Figure 9: Block diagram of MMPC local control loop. Each PM interfaces with a programmable power supply that emulates a PV-module. Three lead acid battery modules have been used to provide energy storage capability for each module. The digital control platform consists of a powerful floating point digital signal processor (DSP) (Texas Instruments TMS320C6713) mounted on a commercial kit board that runs all the complex calculations required by the control, and a custom field-programmable gate array (FPGA) platform built around the (ProASIC(r)3) chip that is controlling the A/D feedback signal acquisition and the generation of the PWM signals. The evaluation of the proposed MMPC and associated management algorithms was achieved in four tests. Test 1, which is shown in Figure 11, was made for battery charging and assumed balanced batteries (i.e., the three battery modules had the same SoC). Initially the three PV-sources provided nearly equal power (around 117 W each) which resulted in an equal voltage contribution (around 25 V) for all the PMs to the MMPC bus voltage (75 V) and also in maintaining balanced charging powers (\(3\times 55\) W) for the battery modules. At t = 10 s, a disturbance had been introduced to the system by slightly reducing the load power by 5% as well as imposing an imbalance in the PV powers (P\({}_{\rm PV1}\) = 150 W; P\({}_{\rm PV2}\) = 117 W; P\({}_{\rm PV3}\) = 85 W). Accordingly, if the module voltage contributions were kept the same, the imbalance in PV powers would cause a direct imbalance in the charging powers of the battery modules which in turn would lead to significant SoC imbalances. In order to minimize this, the proposed management algorithm allowed the modules to contribute with imbalanced voltage/power to the bus voltage/load power in order to minimize the battery power imbalance which ultimately would provide minimum SoC imbalance. This was seen during the time (10 \(<\) t \(<\) 19 s), where the voltage contribution of M1 with highest PV power had been increased from 25 V to 35 V to direct most of the increased PV power (117 W\(\rightarrow\)152 W = +30%) to the bus/load. On the other hand, the voltage contribution of M3 with lowest PV available power (120 W\(\rightarrow\)85 W = -30%) had been decreased to 17 V (this is the minimum possible, equal to the PV voltage) to minimize the module \begin{table}
\begin{tabular}{c c c} \hline \hline
**Symbol** & **Description** & **Value** \\ \hline \(V_{\rm batt}\) & Battery module voltage & 36 V \\ \(V_{\rm PV-max}\) & PV-module voltage at MPP & 17 V \\ L\({}_{1}\) & Battery converter inductor & 375 \(\mu\)H \\ L\({}_{2}\) & PV-converter inductor & 187 \(\mu\)H \\ M & Total number PM & 3 \\ l\({}_{\rm bus}\) & Maximum load current & 14 A \\ V\({}_{\rm bus}\) & Bus voltage & 75 V \\ \(f_{\rm s}\) & Switching frequency & 10 kHz \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Design parameters of the experimental setup. Figure 10: Experimental setup for testing of the proposed modular multiport converter. power contribution to the bus, allowing for more power to charge the battery module (53 W\(\rightarrow\)42 W = \(-\)20% instead of 37 W). These imbalances in the voltage contributions of PMs was nearly compensating for the PV power imbalances, limiting the buildup of battery SoC divergence. Throughout the whole test, it can be seen that the control was able to maintain the bus voltage at 75 V under all conditions, unaffected by the PV imbalance. The second test, shown in Figure 12, evaluated the capability of the MMPC to maintain the bus voltage as well as balanced SoCs for the battery modules under the presence/absence of PVs power.