## 2 Inductance Model Description  
Figure 1a shows the cross-section schematic of a silicon-interposer-based 3D IC package, in which the interposer acts as bridges between the active chips and printed circuit board package [13; 14]. In addition to the interconnection, the interposer provides the functionalities with passive components integration. Various integrated passive devices, such as TSV inductors, TSV capacitors and TSV filters, have been presented [15; 16; 17]. However, these studies focus on the utilization of tiny TSVs. The TSV-based solenoid inductor has a low inductance and is not suitable for power device applications. In this design, a fully integrated power inductor is proposed, as shown in Figure 1. The proposed inductor is designed to be placed at the backside of the interposer for efficiently utilizing the silicon area and can be connected to the front side power circuits through TSVs. A thin oxide dielectric is inserted between the inductor and silicon substrate to obtain a high-quality factor. Figure 2 shows the major fabrication steps of the proposed power inductors. Firstly, the via structure is formed at the front side of the interposer by deep reactive ion etching (Figure 2a). The etched via is then processed with an oxide dielectric, a Ta barrier and a Cu seed layer, followed by the acid Cu electroplating (Figure 2b). The Cu damascene technique [18] is adopted to fabricate the redistribution layers (RDLs) and the vias connecting the TSVs to the RDLs (Figure 2c). The topside of the interposer wafer is temporarily bonded to a carrier by adhesive and a back grinding is carried out to a few microns to the TSVs (Figure 2d). The proposed inductor is implemented by the RDLs at the backside with the Cu damascene method and the vias connecting the TSVs and the inductor are completed (Figure 2e). Finally, one de-bonds the carrier wafer and assembles the TSV module on the package substrate (Figure 2f). With the help of the finite-element method simulation with HFSS software, the electrical performance of the proposed backside integrated inductor with a size of 1 mm\({}^{2}\) is investigated. Table 1 provides a performance comparison for the proposed backside integrated inductor with other state-of-the-art works. Where \(L\), \(Q\),\(f\) and \(R_{\text{DC}}\) are the inductor inductance, qualify factor, switching frequency and dc resistance, respectively; \(\eta\) is the inductor efficiency, which is estimated by the inductor parameters and the equation in [19; 20] for power efficiency. Since the oxide dielectric provides a good isolation between the inductor and the silicon substrate, it is observed that the proposed inductor achieves a higher qualify factor, leading to a peak inductor efficiency of 87.3% for a typical voltage conversion ratio of 1.8 V:0.9 V and load current of 100 mA. On the contrary, substrate loss and eddy current loss significantly decrease the quality and efficiency of the silicon-core inductors and magnetic-core inductors. Furthermore, in comparison to the toroidal inductor, the proposed embedded inductor is more compatible with the standard CMOS process. Figure 1: Schematic of (**a**) the 3D IC package and (**b**) the 3D view of the proposed backside integrated power inductor. Based on the above structure, the resistance-inductance-capacitance (RLC) model of the backside integrated inductor can be established. Considering that the inductance is one of the critical parameters for inductors in power management applications, this work focuses on the modeling and analysis of the inductance of the proposed inductor. For the basis analysis, it is assumed that the track width is \(w\), the track spacing is \(s\) and the track thickness is \(t\). The linked flux of the inductor determined its inductance. For a one-turn inductor, the overall inductance of the inductor is equal to its self-inductance.