# A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures
## 2 Motivation
#### Example 1  
Figure 2 depicts a fragment of a circuit to be tested by means of five scan paths. Serial inputs of these scan paths are fed from parallel outputs of a five-bit type I LFSR designed for the primitive polynomial \(p(x)=x^{5}+x^{4}+x^{2}+x+1\). Outputs of that register produce identical pseudo-random sequences of bits but with a sequential phase shift. The figure depicts an example of content in the scan paths and the register, whilst dotted lines indicate interrelationships between contents of individual scan paths. Outputs of these scan paths cells feed inputs of exemplary gates included in the CUT (gates G1-G4). To make the picture more clear, the remaining part of the CUT, where outputs of the mentioned gates are wired, is not shown in the figure. The foregoing example demonstrates that the following faults of the CUT are not detectable: stuck-at-1 at the output of the OR (G2) gate, stuck-at-0 at the output of the XOR (G4) gate, short (bridging fault) between inputs of the AND (G3) gate as well as an  
Figure 2: The example of faults that are undetectable by means of a conventional STUMPS-type LBIST structure. open break at the input of the CMOS transistor with the \(p\) channel (input A) within the NOR (G1) gate. The reason why those faults are undetectable lies in insufficient phase shift, actually equal to 1, between binary sequences produced at adjacent outputs of the TPG. Due to such an insufficient phase shift the content of both the \(j+k\)th and \(j\)th cells in the scan paths wired to respective \(i\)th and \(i+k\)th outputs of TPG shall be always equal to another (\(i=0\), 1,..., \(n-2\), \(j=0\), 1,..., \(L-2\), \(k=1\), 2,..., \(i+k<n\), \(j+k<L\)), where \(n\) stands for the length of the TPG and \(L\) is the length of scan paths (for the example in question \(n=5\), \(L=8\)). Therefore, the \"00\" pair of bits shall never appear at the A and B inputs of gate G2, which is mandatory to switch the gate output over to the state that is opposite to the fault, i.e., to zero. Likewise, it is also infeasible to deliver such combinations as AB = 01 or AB = 10 to inputs of the G4 gate, which is necessary to set the gate output to \"1\". Moreover, both inputs of the G3 gate are always equal, so they appear to be shorted, and that makes it infeasible to detect the type of the actual fault. In turn, the detection of a fault affecting the G1 gate needs to deliver the test vector sequence \"00,10\" to the AB inputs. Since inputs of that gate also always adopt the same state during the entire testing process, the aforementioned sequence shall never occur. The issue disclosed in Example 1 can be formulated in a more general way; i.e., a low phase shift between test bit sequences appearing at neighboring outputs of a pseudo-random TPG leads to a strong correlation between test vectors supplied to scan paths fed from these outputs. It is why these vectors may no longer be considered as pseudo-random ones, which adversely affects the fault coverage in digital CUTs with the STUMPS-type LBIST architecture [3] (pp. 177-181), [12; 34; 35; 36; 37; 38]. In addition, page 322 in [38] shows an example to demonstrate that test vector sequences generated by an I-type LFSR and feeding parallel inputs of a circuit tested in the test-per-clock mode shall be incapable of detecting some faults in the digital circuit under test. The concept of output channels from a Test Pattern Generator (TPG) frequently appears in reference studies. These channels are actually numerous scan paths fed from outputs of the TPG. The phase shift between binary bitstreams supplied to individual scan paths is also referred to as the separation factor between data channels or between scan paths' content [3] (pp. 184-188), [13; 34; 37; 39]. The low phase shift between bit sequences appearing at outputs of the type I LFSR register and their strong mutual correlation is also confirmed by the State-Time Diagram (STD) that depicts the sequence of test vectors produced by such a shift register [10].