# A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures
## 5 Pseudo-Random Pattern Generator DT-LFSR-TPG for LBIST Circuits with the STUMPS Architecture
The logic synthesis of DT-LFSR registers was carried out with the use of the commercial software LeonardoSpectrum from Mentor Graphics, Wilsonville, OR, US (currently Siemens EDA), as well as the TSMC 0.25 \(\upmu\)m standard cell library included in the ASIC Design Kit rev. 3.1, also made available by Mentor Graphics, Wilsonville, OR, US. The decision to use this particular standard cell library was triggered by the fact that the same technology, with 0.25 \(\upmu\)m, was used in [34] for synthesis of phase shifters investigated in that study. It enables a reliable comparison of experimental results disclosed in the further part of this paper against the ones discussed in [34]. Nevertheless, it should be mentioned herein that the structure of the DT-LFSR register is ring-shaped; therefore, it enables substantial reduction of length for all interconnections between the register cells and, in consequence, delays caused by these interconnections. To achieve the most satisfying results for the DT-LFSR structure, it is recommended that the so-called interleaving technique be applied [38; 63; 64]. The topology example of a D\({}^{3}\)T\({}^{17}\) register together with a network of interconnections between its cells, obtained by means of the mentioned interleaving technique, is shown in Figure 14. The rectangles designated in the picture with letters \"D\" and \"T\" stand for corresponding standard cells with both D flip-flops as well as configurable D/T flip-flops, whereas the rectangle designated with \"M\" corresponds to a multiplexer 2 to 1. Inputs and outputs of standard cells are deployed on the bottom and top edges of these cells. Directions of signal flows are indicated with an arrow for each interconnection presented in the picture. To achieve better clarity of the picture, the line of the clock signal is omitted. The only long interconnection in an DT-LFSR register as shown in Figure 14 is the line of the MODE signal and the interconnecting line between the output of the flip-flop No. 19 and the SO output of the entire module. Nevertheless,  
Figure 13: \(n\)-bit DT-LFSR: **(a)** Diagram of the internal structure of the synthesizable register model; **(b)** Internal structure of the configurable D/T flip-flop. propagation time down these interconnections has no impact on the maximum operational frequency of the register in the testing mode. Synthesis results summarized in Table 6 served as the basis to calculate hardware costs of DT-LFSR Test Pattern Generator (DT-LFSR-TPG) dedicated to LBIST structures with the STUMPS architecture and with 128, 256, 512, 1024, 2048, and 4096 scan paths within the structure. The numbers of scan paths selected for experiments were exactly the same as in Table IX in [34] to simplify a comparison of cost and maximum operational frequencies between the test generators investigated in this study and the ones shown in [34]. The results from the mentioned calculations are provided in Table 7, where columns 2 and 3 of the table specify \(t\) and \(n\) parameters of DT-LFSR registers with the D\({}^{n-t}\)T\({}^{t}\) structure incorporated into the DT-LFSR Test Pattern Generator (DT-LFSR-TPG). Corresponding implementation costs for each test pattern generator feeding the specific numbers of scan paths are listed in columns from 4 to 9. Similarly to Table 6, these costs are expressed as the number of equivalent two-input NAND gates. The grey background highlights solutions with the lowest cost for the specific number of scan paths. For instance, when an LBIST circuit with the STUMPS architecture contains 1024 scan paths, the cheapest test pattern generator of the DT-LFSR-TPG type is made up of 17 DT-LFSR registers and each of these registers can be designated as D\({}^{1}\)T\({}^{62}\). The overall cost of such a solution equals 7837 equivalent two-input NAND gates.