# Space Charge Effect and Resistance Switching in Doped Monocrystalline Silicones
## 3 Results
The voltage difference between \(V_{\rm U}\) and \(V_{\rm L}\) is \(\Delta V\). It is noted that both \(V_{\rm U}\) and \(\Delta V\) are proportional to \(L^{2}\). The \(L\) dependence of the critical voltages exhibits a non-uniform electric field distribution along a sample in a nonlinear regime due to the screening effect of free carriers [1; 2; 3; 7]. Next, the concentrations \(N_{D}{}^{+}\) of ionized donors and \(N_{t}\) of deep traps can be estimated from \(V_{\rm L}\) and \(V_{\rm U}\) according to [1]:  
\[N_{D}{}^{+}=\frac{2\varepsilon}{eL^{2}}(V_{\rm L}-V_{L}) \tag{1}\]  
and  
\[N_{t}=\frac{2\varepsilon}{eL^{2}}V_{U} \tag{2}\]  
Here, \(\varepsilon\) is the dielectric constant of silicon (\(\varepsilon\) = 12 for simplicity), \(L\) is the electrode spacing, and \(e\) is the electric charge constant. Both ionized donors and deep traps originated from dopants. Although the electric field was non-uniform in the ETF and MG regimes, \(N_{D}{}^{+}\) and \(N_{t}\) were constantly obtained from the above equations, which is in agreement with the theoretical prediction for homogeneous materials [1]. In fact, it was also the physical origin for the spatial distribution of the internal voltage difference in the MG regime as reported by [PERSON] et al. [7]. As mentioned above, the ionization and filling of dopants are voltage-dependent. It is noted that the dynamics of ionization and filling may undergo a relaxation under an external electric field due to the accumulation or dissipation of localized charges. Consequently, SCE could have voltage history dependence. Figure 3a demonstrates a voltage-dependent RS effect induced by SCE in a heavily doped n-Si with \(L\) = 8 mm (1126-1#). The applied voltage starts from zero up to the positive maximum, reverses down to the negative maximum, and finally comes back to zero. The measured current experiences four distinct processes, labeled as S1, S2, S3, and S4 in sequence (S for step). S1 represents the increasing branch of the I-V curve with the voltage increase, while S2 represents the decreasing one in Figure 3a. It was observed that S2 does not coincide with that of S1 when the voltage is higher than 6 V. Ionization becomes increasingly dominant in S2, so S2 has a lower resistance than S1. As the applied voltage is lower than 6 V, filling and ionization are dynamically balanced. Then, S2 overlaps with S1 exactly, as enlarged in the left top of Figure 3a. S1 and S2 form an RS loop in the first quadrant. While the polarity of the applied voltage is reversed in the third quadrant, the above process repeats. Finally, a complete RS loop comes into being. These observations indicate that RS in monocrystalline silicon is solely related to SCE, so the current Joule heating effect could be ruled out. Therefore, it is termed as SCE-RS. Figure 2: Electrode spacing dependence of two critical voltages. (**a**) Black, green, and blue curves are I–V curves with electrode spacing \(L\) of 2, 5, and 8 mm measured at room temperature for device 0129-7#. The inserted figure at the left top is the schematic setup, in which the white squares represent indium electrodes. (**b**) The lower and upper critical voltages, \(V_{\mathrm{L}}\) and \(V_{\mathrm{U}}\), as well as their difference and \(\Delta V=V_{\mathrm{U}}-V_{\mathrm{L}}\), versus the square of electrode spacing \(L^{2}\). Red, purple, and black data illustrate \(V_{\mathrm{L}}\), \(V_{\mathrm{U}}\), and \(\Delta V\) respectively. All of them exhibit a linear relationship with \(L^{2}\). as shown by schematic plots in Figure 3b,c. However, they differ from each other in the following aspects, including the type of loop, the underlying physics, and materials. First, the memristor loop has a cross around the zero voltage [9; 10; 11; 12; 13; 14; 15; 16; 17; 18; 19; 20], while the SCE-RS loop has rotational symmetry because of the existence of a linear Ohmic regime. In mathematics, the topological invariants are 1 and 0 for the loops of memristor and SCE-RS respectively, as illustrated in the inserts of Figure 3b,c.