## 3 Physical Layer Design
### Impact of Technology Scaling on Inter-Chip Wireless Interconnects  
As device geometries continue to scale, the fabrication of two novel transistor structures are attaining maturity. These are the FinFET and the Silicon-on-Insulator (SOI) transistor. Both these transistors attempt to reduce the channel cross-section and increase the gate electric field ultimately increasing the switching speed. However, the FinFET is emerging as the device of choice for fast digital processes whereas, the Fully Depleted Silicon-on-Insulator (FDSOI) processes are emerging as the device of choice for high-speed analog applications [70]. Therefore, as the technology shrinks with 45 nm SOI, 28 nm SOI and beyond, the power consumption of the mm-wave transceivers is expected to keep reducing and provide higher data rate efficiency per milliwatt of power. In Tables 2 and 3, we present the trend in bit energy efficiency of recently designed mm-wave OOK transmitters and envelope detectors (for OOK receivers) respectively, having comparable data rates at 60 GHz with technology node scaling. The trends point towards a promising reduction of energy consumption per bit with technology scaling reaching sub-1 pJ/bit at the 45 nm technology node.  
While the power efficiency per Gbps of data rate can be expected to increase with the progress of SOI technology nodes, the performance of wireline interconnects, I/O are not predicted to scale at the same rate [72]. Non-scalable pin size or pitch of solder bumps and balls imposes limitations on the bandwidth density of inter-chip I/O and will prevent power consumption per Gbps of wireline communication from scaling significantly. In [73] Global Foundries projects that the percentage of die area occupied by only analog I/O components would be between 40-60% in the 7 nm node. Therefore, it is expected that as technology scales and SOI processes develop the power-performance gap between wireless inter-chip interconnects and traditional wireline interconnects will continue to widen, pushing the advantage towards the wireless interconnections even more.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**References** & **This Paper** & **[67]1** & **[71]1** \\ \hline Technology node & 45-nm CMOS & 65-nm CMOS & 90-nm CMOS \\ Carrier Frequency & 60 GHz & 60 GHz & 60 GHz \\ Modulation & OOK & OOK & OOK \\ Maximum Data Rate & 16 Gb/s & 16 Gb/s & 10.7 Gb/s \\ Power Consumption & 3.9 mW & 19 mW & 31 mW \\ Supply Voltage & 1 V & 1 V & 0.8/1.8 V \\ RF output Pl4B & \(-\)3 dBm & 1.5 dBm & 5.1 dBm \\ Bit-Energy Efficiency & 0.24 pJ/bit & 1.2 pJ/bit & 2.9 pJ/bit \\ Active-Foot Print & N/A & 0.077 mm2 & 0.15 mm2 \\ FoM & 2.055 & 1.19 & 1.12 \\ \hline \hline \end{tabular}  
* Post-layout or post-fabrication results.  
\end{table}
Table 2: Performance Comparison of mm-wave OOK Transmitter across technology nodes.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**References** & **[68]** & **[69]1** & **[71]1** \\ \hline Technology & 45 nm & 65 nm & 90 nm \\ Conversion Gain & 16 dB & 12.9 dB & 16 dB \\ Carrier Frequency & 60 GHz & 60 GHz & 60 GHz \\ Required input Power & \(-\)12 dBm & \(-\)16 dBm & \(-\)8 dBm \\ Max Data Rate & 17 Gb/s & 18.7 Gb/s & 10.7 Gb/s \\ Power Consumption & 1.3 mW & 4.6 mW & 19.2 mW \\ Supply Voltage & 1 V & 1 V & 1.2 V \\ Responsivity & 3.15 V/mW & 6.1 V/mW & 5.89 V/mW \\ Bit-Energy Efficiency & 0.08 pJ/bit & 0.25 pJ/bit & 0.56 pJ/bit \\ \hline \hline \end{tabular}
\end{table}
Table 3: Summary and comparison of the ED across technology nodes.