# Atomic Layer Deposition (ALD) of Metal Gates for CMOS
## 1 Introduction
### Metal Gate and Effective Work Function (EWF)  
Another important issue relative to the dielectric thickness scaling is the depletion layer formed in the poly-Si gate near the interface of the gate and the dielectric, as shown schematically in Figure 6. The thinner is the dielectric, the stronger the field is generated by the channel inversion, and the more charges are involved in the depletion layer. The depletion layer forms an additional capacitor over the dielectric and impairs the impact of the gate voltage to channel. The thickness of the depletion layer is related to the carrier density of the poly-Si gate. The increase of doping level in the poly-Si can help to reduce the depletion thickness. The effort in employing more aggressive implantation for heavier doping poly-Si could induce givevous impurity penetration through the gate oxide [27]. Limited by this, the doping level of the n+ poly-Si is normally below 10\({}^{20}\) cm\({}^{-3}\) and that of p+ poly-Si is less than the mid of 10\({}^{19}\) cm\({}^{-3}\). This means that the depletion issue could not be released via increasing doping level. Beyond the 65 nm node, the poly-Si gate had to be phased out and replaced by metal gate electrodes. Figure 5: Comparison of the dielectrics in conduction and valence band offsets and permittivity. The work function is the first requirement for the metal gate electrodes. At beginning, the selection of the metal gate candidates was based on their work function in vacuum. Figure 7 lists more than 20 metals and their vacuum work functions [28]. When a metal is in a MOS structure, its work function shifts from its vacuum value. This value is normally termed as \"effective work function or _EWF_\". _EWF_ could be extracted from the C-V curves obtained with the MOS capacitors (MOSCAP) [29]. Figure 8 displays the simplified energy band diagram of an ideal MOS structure using n-type substrate under the condition of flat band, where \(\varPhi_{M}\) stand for the work function of the metal, \(\chi\) for the electron affinity, \(E_{g}\) for the band gap, \(\varPhi_{B}\) for the potential barrier between the dielectric and metal, and \(\Psi_{B}\) for the difference of potential between the Fermi level \(E_{F}\) and the intrinsic Fermi level at the midgap. Here, \"ideal\" means the fixed charge density in the dielectric is zero. As applied voltage is zero, the MOS structure has a flat band as shown in Figure 8, or the difference between the work functions the metal and the semiconductor, \(\varPhi_{MS}\), is zero. For n-type substrate  
\[\varPhi_{MS}=\varPhi_{M}-(\chi+\frac{E_{g}}{2q}-\psi_{B}) \tag{4}\]  
C-V measurement will give the curve as shown in the right plots of Figure 8. For p-type substrate, the case is similar. The \(\varPhi_{MS}\) is  
\[\varPhi_{MS}=\varPhi_{M}-(\chi+\frac{E_{g}}{2q}+\psi_{B}) \tag{5}\]  
For real dielectric with a fixed charge density of (\(\pm Q_{f}\)), the C-V curve will shift as shown in the plots. To have a flat band, a voltage of \(V_{fb}\) needs to be applied to shift the curve back. \[V_{fb}=\varPhi_{MS}+\frac{Q_{f}}{\varepsilon_{0}\kappa}EOT \tag{6}\]  
Assuming the \(Q_{f}\) is independent of \(EOT\), the measured \(V_{fb}\) as a function of \(EOT\) will intercept the \(y\)-axis at \(\varPhi_{MS}\). Using this intercept value and the band structure of the dielectric, the effective work function of the metal \(\varPhi_{M}\) could be extracted. Figure 6: Depletion layer formed in poly-Si. (a) schematic of a MOSFET; (b) band structure of poly-Si/oxide/semiconductor. The metal gate for CMOSFETs can be a single metal with one _EWF_ near midgap or two different metals (dual metal gate), one with _EWF_ near the edge of the conduction band, and the other near that of the valance band, separately. Equation (7) gives the \(V_{t}\) as a function of \(V_{fb}\).