# Silicon Integrated Nanophotonic Devices for On-Chip Multi-Mode Interconnets
## 2 Silicon Multi-Dimensional (De)Multiplexers
### Silicon Mode (De)Multiplexers
For instance, the MMI-based structures usually suffer from intrinsically high insertion losses due to the strong scattering at the input/output port, while for the Y-junction-based structures, a small feature size is usually required at the position where two arms are converged. The ADC has been widely considered as a better choice for realizing high-performance silicon mode (de)multiplexers, which is comprised of two closely placed waveguides with different core widths (see Figure 4c). Here, we show a design example for an ADC-based two-channel mode (de)multiplexer considering the first two TE modes (i.e., TE\({}_{0}\)/TE\({}_{1}\)). The input TE\({}_{0}\) mode in waveguide #0 can be coupled to the output TE\({}_{1}\) mode in waveguide #1 through evanescent coupling (see the inset of Figure 4a). The complete TE\({}_{0}\)-TE\({}_{1}\) coupling can be obtained only if the phase-matching and critical coupling conditions are simultaneously satisfied [72]. Figure 4a shows the calculated effective indices for TE\({}_{0}\) and TE\({}_{1}\) modes in a SOI waveguide with core width varying from 250 nm to 1 \(\upmu\)m. Here, we consider the 220-nm-thick SOI platform with a SiO\({}_{2}\) upper cladding. The core width is chosen to be w\({}_{\text{wg,0}}\) = 400 nm for waveguide #0 to fulfill the single-mode condition operating at 1.55-\(\upmu\)m wavelength. Thus, one can easily determine the core width for waveguide #1 as w\({}_{\text{wg,1}}\) = 835 nm, so that the effective indices are matched between TE\({}_{0}\) and TE\({}_{1}\) (see the dashed lines in Figure 4a). After that, we calculate the TE\({}_{0}\)-TE\({}_{1}\) coupling ratio with varied coupling length, as shown in the left panel of Figure 4c. Here, the gap width is chosen to be w\({}_{\text{gap}}\) = 200 nm. It can be observed that the curve is sinusoid-like and the first critical coupling length is \(\approx\)18 \(\upmu\)m. The light propagation profile is then calculated for the optimized ADC, as shown in the left panel of Figure 4d. From the profile, one can observe the efficient TE\({}_{0}\)-TE\({}_{1}\) mode conversion and the complete power transfer from waveguide #0 to waveguide #1. Additionally, the phase-matching condition is satisfied only between TE\({}_{0}\) in waveguide #0 and TE\({}_{1}\) in waveguide #1, so TE\({}_{0}\) mode can directly inject into waveguide #1 without evanescent coupling or mode conversion (see the dashed lines in Figure 4a), enabling a dual-mode (de)multiplexing. However, for the silicon ADCs, the phase-matching and critical coupling conditions can be perfectly fulfilled only at the central wavelength due to the strong waveguide dispersion, leading to a restricted working bandwidth. The bandwidth could be expanded by using SWGs [32; 33; 34] or hybrid plasmonics [35], but these structures are not easy to realize. Furthermore, a stringent fabrication is always required for ADCs since the mode conversion and light-coupling processes are quite sensitive to the parametric deviations, which could significantly increase the crosstalk [73]. These obstacles can be tackled by utilizing adiabatic ADCs [36; 37]. The idea is to introduce an adiabatic mode evolution by gradually changing the core widths (w\({}_{\text{wg,0}}\), w\({}_{\text{wg,1}}\)) along the coupling section. Here, we show a design example for an adiabatic TE\({}_{0}\)-TE\({}_{1}\) ADC with linearly varied core widths. For waveguide #0, the core width is linearly varied from w\({}_{\text{wg,0}}\) = 350 nm to w\({}_{\text{wg,0}}\) = 270 nm, while for waveguide #1, the core width is linearly varied from w\({}_{\text{wg,1}}\) = 630 nm to w\({}_{\text{wg,1}}\) = 810 nm. Here, the gap width is set to be w\({}_{\text{gap}}\) = 200 nm. Figure 4b shows the calculated effective indices for TE\({}_{0}\)/TE\({}_{1}\) modes in waveguide #0/#1 (see the solid lines) and TE\({}_{\text{S}}\)/TE\({}_{\text{AS}}\) super-modes in the dual-core ADC (see the dashed lines).