## 3 Circuit Simulation and Experiment
Figure 10a shows the rising time of the output voltage in simulation, delayed model, non-delayed model, and simplified model with different sampling capacitances. And Figure 10b demonstrates the rising time of the output voltage under different peak values  
Figure 9: (**a**) The change in output voltage of the PDSH circuit when (11) is not satisfied. (**b**) The variation of the difference between the input voltage and the output voltage of the PDSH circuit. of the input signal. The figure indicates that the delay time, as a secondary factor, can also have an impact on the measurement speed of the PDSH circuit. Meanwhile, the maximum error between the simplified model and the simulation results is 1.98 ns when \(C_{h}\) is 100 pF, indicating that the simplified model can accurately describe the measurement speed of the PDSH circuit. Figure 10 shows that the main source of error in the simplified model is not the delay time of the system but the simplification of the capacitor charging process, and the error is within the acceptable range. Figure 11 illustrates the rising time of the output voltage for experimental, delayed model, and simplified model at different peak voltages. The results indicate that the maximum error between the simplified model and experiment results is 2.03 ns. Simulations and experiments show that the simplified model can accurately and simply describe the measurement speed of the PDSH circuit. In order to quantitatively describe the step voltage error, the equivalent capacitance \(C_{eq}\) of the diode must be solved. According to (18), the equivalent capacitance \(C_{eq}\) can be obtained by fitting the data based on the final voltage \(V_{f}\) under different sampling capacitance \(C_{h}\). The change of equivalent capacitance of the diode can be achieved by changing the junction capacitance of the diode in the simulation software. Figure 10: The rising time of the output voltage in simulation, delayed model, non-delayed model, and simplified model of the PDSH circuit with different sampling capacitors and peak values, where \(t_{r}\) = 10 ns. (**a**) Different sampling capacitors with \(V_{m}\) = 1 V. (**b**) Different peak values with \(C_{h}\) = 50 pF. Figure 12 illustrates the relationship between the final output voltage \(V_{f}\) and the sampling capacitance \(C_{h}\) for different diode junction capacitances \(C_{j}\) when the peak voltage \(V_{m}\) is 2 V. The horizontal axis represents the sampling capacitance \(C_{j}\), while the vertical axis represents the final voltage \(V_{f}\). The simulation results are represented by dots, and the fitting curve based on (18) is shown as a solid line. Therefore, the equivalent capacitance \(C_{eq}\) of the diode can be calculated according to (18). Figure 12 shows that the relationship between the final output voltage and the sampling capacitance follows (18), which verifies the correctness of the voltage step model. Based on the above method, several types of diodes are experimentally measured for their equivalent capacitance \(C_{eq}\), and the results are shown in Table 1. The reverse recovery time \(T_{rr}\) and diode capacitance \(C_{d}\) are obtained from the datasheet. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Diode** & **Type** & \(T_{rr}\) & \(C_{d}\) & \(C_{eq}\) \\ \hline BAT54S & Schottky & 5 ns & 10 pF & 2.87 pF \\ BAW56 & Switching & 6 ns & 2 pF & 2.14 pF \\ SMMBD914 & Quick recovery & 4 ns & 4 pF & 1.98 pF \\ HSMS2812 & Schottky & & 1.2 pF & 0.89 pF \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Diodes and equivalent capacitance. Figure 11: The rising time of the output voltage in experiment, delayed model, and simplified model of the PDSH circuit with different peak values, where \(t,=15\) ns and \(C_{h}=51\) pF.