## 3 Proposed Low-Latency Compact Baseband System for Wireless VR  
### Baseband Processing with Block-Level Interleaved-BCH Codes  
Based on the channel observation, it is clear that the wireless VR system over 60 GHz RFIC should recover a number of burst errors. For some specifications targeting the high-speed near-field wireless communications, several candidates can support such a channel condition with different types of codes including low-density parity-check (LDPC) codes targeting the data rate of more than 6 Gbps [9; 10; 11; 12; 17]. However, the previous standards are normally defined to support various applications and thus they include several complicated processing steps to ensure the data integrity for different transmitting scenarios. If the recent WiGig standard were applied [6; 8], for example, the received data stream would be recovered by passing through a number of blocks including synchronization unit, channel estimator, de-mapper, de-interleaver, and iterative LDPC decoder [18; 19]. Therefore, the previous baseband system basically suffers from the long processing latency. In addition, the LDPC code uses the soft-decision inputs associated with a high-speed ADC architecture in general, consuming a huge amount of energy [20; 21]. Due to the time- and energy-consuming requirements on the baseband processing, the previous specifications targeting the near-field wireless communication are no longer effective for the proposed wireless VR system. There are also other types of ECCs used for the different applications rather than the near-field communications. for example, ECCs for cellular devices such as turbo codes [22] and polar codes [23] could be attractive candidates if we consider their stable error-correcting powers. Similar to the WiGig case, however, those ECCs cannot be used for the proposed system due to the low code-rate and the long latency. Some high-rate codes for memory applications can be also considered, but the storages normally necessitate long-length codewords, thereby increasing the energy consumption caused by the large-sized internal buffers and the multiple decoding levels for lowering the error bounds [24; 25; 26]. Considering the tight requirement on the latency, which is the most important player for utilizing the wireless VR system, we choose the BCH-based ECC solution correcting the burst errors of up to 1080 bits in a data frame of 106,920 bits as the previous LDPC code generally takes a long time to correct the existing errors by adopting the iterative decoding steps [27]. To reduce the complexity of baseband processing, we newly introduce a (106,920, 95,040) block-level interleaved BCH code, which consists of 60 (1782, 1584, 18) component BCH codes, as depicted in Figure 3. Even a CC is relatively weak, correcting only up to 18 bits among 1782b-length data, i.e., a fully-erroneous block is recovered by a CC, the proposed coding scheme is effective for recovering the long length of burst errors by presenting the block-level interleaving scheme. As shown in Figure 3, the proposed code is divided into 5940 blocks of 18 bits, i.e., 5280 data blocks (D\({}_{x}\)) from the input video stream and 660 parity blocks (P\({}_{x}\)) for the parity information. Note that each CC consists of 99 blocks: 88 data blocks and 11 parity blocks. More precisely, to construct a CC\({}_{i}\), we collect 88 D\({}_{x}\) blocks in order, i.e., D\({}_{60i}\), D\({}_{60i+1}\),..., D\({}_{60i+59}\), and append 11 P\({}_{x}\) blocks, as depicted in Figure 3. After constructing all CCs by utilizing the parallel BCH encoder, in the TX mode of the proposed baseband architecture, we start a block-level interleaving process, which shuffles the blocks to make the whole data frame tolerable to the burst errors. For the given data frame, as depicted in Figure 3, the block-level interleaving basically rearranges the order of transmission by generating 99 frame segments (FSs).