## 5 Experimental Results  
The locking simulation of the triple-loop wideband fractional-N all-digital phase-locked loop (WBPLL) is illustrated in Figure 8. The ADPLL consists of three loops: the automatic frequency control (AFC) loop, the counter-assisted phase-locked loop (CAPLL), and the digital sub-sampling phase-locked loop (SSPLL). The locking process sequentially progresses through these three loops. In Figure 8, the target frequency is set to 3.5 GHz. The simulation captures the operation of the WBPLL as it locks onto this frequency, demonstrating the coordinated functioning of the AFC, CAPLL, and SSPLL loops. These results highlight the effectiveness of the triple-loop architecture in achieving stable frequency locking. The verification of the locking process was conducted using SystemVerilog and Verilog-HDL modeling, incorporating post-simulation results from the time-to-digital converter (TDC), digital-to-time converter (DTC), and digitally controlled oscillator (DCO). Figure 8 provides a detailed view of the locking stages, illustrating how each loop contributes to overall frequency stabilization. The AFC loop initially brings the frequency close to the target, the CAPLL refines it further, and the SSPLL ensures fine adjustments and long-term stability. Additionally, Figure 9 shows the locking time for target frequencies ranging from 1.9 to 6.1 GHz, demonstrating the proposed WBPLL's stable locking performance across this frequency range when approximately 5500 random target frequencies were input. These simulation results confirm the robustness and precision of WBPLL, demonstrating its reliability as a solution for broadband frequency applications requiring precise and stable frequency control. Figure 7: Layout image of proposed WBPLL chip designed using 28 nm CMOS process. Figure 8: Simulation graph of WBPLL locking process to 3.5 GHz target frequency. Figure 9: WBPLL locking time graph for various target frequencies. In this study, it has been demonstrated that a wide range of frequencies can be synthesized using a ring oscillator (RO) structure instead of conventional LC structures. Table 1 shows that our proposed architecture has an overwhelming frequency range of 4.2 GHz compared to prior-art RO frequency synthesizers. Despite achieving this impressive range, we successfully designed the chip with a very compact total area of 0.055 mm\({}^{2}\). The normalized area is included in the table because the minimum MOSFET length varies with different technologies. Due to the differing minimum lengths provided by each process, direct size comparisons may be unfair. Therefore, the total area has been normalized according to the minimum length provided by each process. The performance values in Table 1 are derived using SystemVerilog and Verilog-HDL modeling, incorporating post-simulation results from the key cells of the PLL (DCO, TDC, DTC). Additionally, the IPN value meets \(-33.42\) dBc within the 10 kHz to 10 MHz range, fulfilling the 5G FR1 requirements. This indicates that our proposed digital SSPLL can be utilized in various applications due to its wide frequency synthesis range, compact chip area, and satisfactory IPN performance. Figure 10 shows the phase noise characteristics of the proposed WBPLL. Figure 10 presents the results for each noise contribution simulated in the S-domain model based on the post-simulation design specifications, operating at 3.5 GHz. The phase noise graph refers to the phase noise spectrum of a Single Sideband (SSB) signal, with the starting point being the carrier frequency. This spectrum represents the power difference between the signal and noise, normalized in Hz, as a function of the offset from the carrier frequency. Therefore, it is used to predict the expected real noise. This detailed analysis demonstrates the ability of the WBPLL to maintain low phase noise, with an integrated phase noise of \(-33.42\) dBc from 10 kHz to 10 MHz, across its operating range, further validating its suitability for high-performance applications.