# Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World
## 3 Ultra-Low Power MCU Architectures
### From Single Core to Multi Core  
Energy per instruction combined with increasing frequency are pushing designers toward the multi-core domain. Even though in many applications single core MCUs would be enough, the IoT trend is demanding more and more computational power. By splitting the workload on more low-frequency simple cores, it is possible to increase the parallel computation maintaining a low power budget. Since multi-core solutions are more complex than traditional MCUs, they introduce several new problems regarding data and connection management. Cache coherency is fundamental in such systems: when a core produces a new write operation, all the caches that contain this variable must be invalidated. Such coherency is maintained by a software locking mechanism that synchronizes data, preventing the invalidation of caches. In fact, every time a cache must be trashed, a lot of energy is wasted in order to flush the pipe of the core, restore cache and recompute previous instructions.  
Data transfer between cores is power demanding and requires a very complex connection infrastructure. A complex architecture, such as the multi-core one, translates to expensive silicon and power resources; however, many applications cannot be supported nowadays by a normal MCU. That  
Figure 8: Compressed data can be directly obtained while acquiring the signal.  
is the reason why the trend is moving from single core to multi-core, still maintaining low power budget by limiting the memory hierarchy.  
Common solutions present heterogeneous cores, in which one core is in charge of the heavy computation, while another core, usually smaller than the previous one, handles the peripheral requests. Since the two cores handle different tasks, they are decoupled, allowing for better energy management since each of them can be turned off completely.  
Figure 9 shows the trade-off between single core and multi-core architectures from a power-per-operation perspective. For high workload, a multi-core approach is more efficient. On the other hand, in near-threshold or deep-sleep cases, power leakage is dominant and multi-core, being composed roughly by twice the number of transistors (in case of dual-core), it is less energy efficient. However, a multi-core approach is convenient to reduce the active period by a factor equal to the number of cores, when working with a duty cycling behavior in which the MCU is active for a certain period and in deep-sleep for the rest of the time. In this way, dynamic power is reduced by increasing the deep-sleep period.  
Introducing a more efficient power management system, it is possible to reduce both dynamic and static power by handling each core separately. Dynamic Voltage and Frequency Scaling (DVFS) can be performed on each core, enhancing energy savings and decoupling their working points. Being able to operate each core independently, as well as shutting down them selectively, represents the best low power configuration. However, this needs a hardware overhead and an increased complexity to handle data that cross different frequency and/or voltage domains, requiring handshaking operations.  
Such cost is not always affordable so, sometimes, simpler solutions could be adopted like power gating. Cores would be subjected to the same voltage and frequency domain, but still capable to be switched off independently. This solution requires a ring of p-type MOS transistor all around the core, and being p-type MOS transistors larger than n-type MOS ones, the area overhead is not negligible. Furthermore, this ring introduces some performance degradation, affecting pull up resistance and consequently the current drain. However, power leakage is strongly reduced, still considering that the core requires a non-negligible time to be restored.  
Figure 9: Comparison between single core and multi-core architectures.