# FPGA Applied to Latency Reduction for the Tactile Internet
## 5 Simulated Tactile Internet Model
The signal received by the HMD can be expressed as  
\[\mathbf{u}^{HSD}(n)=\left[\tau_{1}^{HSD}(n),\tau_{2}^{HSD}(n),\tau_{3}^{HSD}(n)\right] \tag{53}\]2  
where  
\[\mathbf{u}^{HSD}(n)=\left[\tau_{1}^{HSD}(n),\tau_{2}^{HSD}(n),\tau_{3}^{HSD}(n)\right] \tag{53}\]3  
\[\mathbf{u}^{HSD}(n)=\left[\tau_{1}^{HSD}(n),\tau_{2}^{HSD}(n),\tau_{3}^{HSD}(n)\right] \tag{53}\]4  
and  
\[\mathbf{u}^{HSD}(n)=\left[\tau_{1}^{HSD}(n),\tau_{2}^{HSD}(n),\tau_{3}^{HSD}(n)\right] \tag{53}\]5  
where \(d_{x}^{b}(n)\), \(d_{y}^{b}(n)\), \(d_{z}^{b}(n)\), \(r_{x}^{b}(n)\), \(r_{y}^{b}(n)\) and \(r_{z}^{b}(n)\) are the latencies and the noises associated with the BC. Similarly to HSD, the HMD will minimize the effect of latency and noise from operations of Cartesian and joint space. For HMD, the calculations associated with the Cartesian space will be performed by the CPD-HMD module and associated with the joint space by the JPD-HMD module. In addition to the prediction and detection calculations, the HMD must transform the force signals received through signal \(\mathbf{q}(n)\) into a torque to be applied to the MD joints which is accomplished by the KFF-HMD hardware module. KFFHMD implements the Equations (39)-(41) presented in Section 4.3 and generate the signal expressed as  
\[\mathbf{u}^{HSD}(n)=\left[\tau_{1}^{HSD}(n),\tau_{2}^{HSD}(n),\tau_{3}^{HSD}(n)\right] \tag{53}\]6  
where \(\tau_{i}^{HMD}(n)\) is the torque associated with the \(i\)-th joint of the MD. Since the PHANToM Omni is a haptic device, it already has a built-in control system, FCS, which uses as reference signal the torques associated with the \(\mathbf{p}(n)\) array. After applying the torques to the MD joints via the \(\mathbf{p}(n)\) signal, the OP receives the feedback force signal, in other words, it feels the object touched by the SD in the ENV. This sensation is identified in by the \(\mathbf{\hat{o}}(n)\) signal expressed as  
\[\mathbf{u}^{HSD}(n)=\left[\tau_{1}^{HSD}(n),\tau_{2}^{HSD}(n),\tau_{3}^{HSD}(n)\right] \tag{53}\]7  
As illustrated in Figure 4, the MD, HMD, NW, HSD, and SD subsystems have the following runtimes: \(t_{MD}\), \(t_{HMD}\), \(t_{NW}\), \(t_{HSD}\) and \(t_{SD}\), respectively. The sum of these, times taking into account the forward direction (between OP and ENV) and the backwards direction (between ENV and OP), represent the total system latency that can be expressed as  
\[\mathbf{u}^{HSD}(n)=\left[\tau_{1}^{HSD}(n),\tau_{2}^{HSD}(n),\tau_{3}^{HSD}(n)\right] \tag{53}\]8  
Some works presented in the literature review agree that the ideal requirement is that \(t_{\text{latency}}\leq 1\,\text{ms}\), on the other hand, other works point out that the latency requirement can be expresses as \(t_{\text{latency}}\leq 10\,\text{ms}\), depending on the application [9; 10; 11; 53; 12]. Considering that 30% of the total latency time \(t_{\text{latency}}\) is spent by MD, HMD, HSD, and SD, it can be understood that  
\[\mathbf{u}^{HSD}(n)=\left[\tau_{1}^{HSD}(n),\tau_{2}^{HSD}(n),\tau_{3}^{HSD}(n)\right] \tag{53}\]9  
Assuming an equal time division among MD, HMD, HSD, and SD it is possible to affirm that the time associated with hardware, \(t_{\text{hardware}}\), whether the master, HMD, or the slave device, HSD, can be expressed as  
\[\mathbf{\hat{a}}(n)=\left[\hat{x}^{OP}(n),\hat{y}^{OP}(n),\hat{z}^{OP}(n) \right]. \tag{54}\]0  
Taking the \(1\,\text{ms}\) constraints into consideration and substituting this value in Equation (71), it is possible to affirm that the hardware time, \(t_{\text{hardware}}\), must meet the \(t_{\text{hardware}}\leq 37.5\,\text{\SIUnitSymbolMicro s}\) constraint for all cases (condition \(1\,\text{ms}\)) or the \(t_{\text{hardware}}\leq 375\,\text{\SIUnitSymbolMicro s}\) constraint for some specific cases (\(10\,\text{ms}\) condition). Recent studies from the literature show that the \(1\,\text{ms}\) restriction (\(t_{\text{hardware}}\leq 37.5\,\text{\SIUnitSymbolMicro s}\)) is difficult to achieve using hardware devices based on embedded systems such as microprocessors and microcontrollers [26; 54].