# A 12 dBm B1 dB N-Path Notch Filter for Transmitter Leakage Suppression in Wideband Receiver
## 3 Proposed N-Path Notch Filter Architecture  
The circuit diagram of the proposed N-path BRF is presented in Figure 5. At any given moment, one of the eight paths is active, with the high level of the clock signal enabling the corresponding MOS switch, while the other paths remain inactive. The high-linearity notch filter is designed with a two-stage cascade structure. Stage I comprises an N-path BFF with quarter-wavelength impedance transformation, enabling the notch filter functionality. This stage establishes a low-resistance path to the ground within the blocking band, thereby enhancing linearity. Stage II utilizes a conventional N-path BRF to further increase the overall rejection depth of the system. The switches of the N-path filter are driven by an eight-phase clock signal with a 12.5% duty cycle, ensuring precise timing and operation of the filter stages. As illustrated in Figure 6, for SOI CMOS processes, the linearity of the N-path filter is constrained by the linearity of the MOS switches, which are designed to remain correctly on or off under clock control without accounting for switch-induced nonlinear distortion. With a 130 nm SOI CMOS process, the absolute value of V\({}_{\mathrm{gs}}\) must not exceed 2.5 V. For switches in the on state, the gate is subjected to a maximum voltage of \(V_{DD}+V_{B}\), where a suitable DC bias \(V_{B}\) is applied to the source and drain of the switch. The maximum  
Figure 4: N-path BRF impedance characteristic curve at \(f_{LO}\) = 450 MHz. Figure 5: Schematic of the proposed N-path notch filter. positive swing of the input signal occurs when the on-state switch is critically closed and is given by:  
\[V_{in,pos}=V_{+}-V_{B}=V_{DD}-V_{B}-V_{TH}, \tag{2}\]  
where \(V_{TH}\) is the threshold voltage of the MOS switch. Similarly, the maximum negative swing of the input signal occurs when the off-state switch is critically open and is given by:  
\[V_{in,neg}=V_{B}-V_{-}=V_{B}-V_{EE}+V_{TH} \tag{3}\]  
where \(V_{EE}\) represents the voltage when the clock output is '0', typically set to \(V_{EE}\) = 0. \(V_{EE}\) can be set to a negative voltage to improve linearity, as is further discussed in the subsequent sections. To ensure symmetrical voltage swings, the positive and negative swings should be equal, i.e., \(V_{in,pos}=V_{in,neg}\). This condition leads to the equation:  
\[V_{B}=\frac{V_{DD}+V_{EE}-2V_{TH}}{2} \tag{4}\]  
Thus, the maximum swing is as follows:  
\[V_{+}-V_{B}=\frac{V_{DD}-V_{EE}}{2} \tag{5}\]  
the maximum blocking power of the circuit, without inducing significant nonlinearity, can be calculated as:  
\[P_{in,max}=10\log[\frac{(V_{DD}/2)}{2R_{equiv}}^{2}] \tag{6}\]  
\(R_{equiv}\) is the impedance of the filter input port at the blocking frequency. An excessive input amplitude during the positive voltage half-cycle results in a variation in the switch-on impedance, thereby inducing nonlinear distortion in the switch when it is in the on state. The resistance of the switch exhibits a dependence on the input signal amplitude, as expressed in Equation (7) [17]. Conversely, during the negative voltage half-cycle, an excessively large input amplitude causes the switch-off impedance to decrease or, in some cases, leads to unintended switching behavior, where the switch erroneously turns on despite being in the off state. This phenomenon generates nonlinear distortion, which is primarily due to charge sharing between different paths. \[R_{SW}=\frac{1}{\mu C\frac{W}{L}(V_{DD}-V_{in}-V_{TH})} \tag{7}\]  
According to Equation (6), the maximum \(P_{in,max}\) is obtained, with the ideal impedance characteristics of the band-stop filter, including low impedance in the stopband and  
Figure 6: (a) N-path BRF schematic, (b) filter switch bias voltage. matched impedance in the passband; this is achieved by the impedance transformation of the quarter-wavelength transmission line. As with the impedance characteristics of the N-path BRF, the input impedance \(Z_{in,sh}\) of the N-path BPF is given by Equation (8).