## 3 Results
### Properties of the NbO\({}_{\text{x}}\)/NbSe\({}_{2}\) Heterostructured Memristor Device  
Considering the highly electrical conductivity of our NbSe\({}_{2}\) flakes, we built the NbO\({}_{\text{x}}\)/NbSe\({}_{2}\) heterostructure for a memristor device as shown in Figure 4a. Before discussing, it is noted that the thin NbSe\({}_{2}\) flakes (below six layers) are very sensitive in ambient, which is easily damaged in a short period, suggesting unsuitability for our heterostructure memristor device (Figure S5). To perform this concept device, we are using the thick NbSe\({}_{2}\) flakes of 10 layers (Figure 4b). By exposing the thick NbSe\({}_{2}\) flakes under an ambient condition for 21 days, the native NbO\({}_{\text{x}}\) layer was formed on the NbSe\({}_{2}\) interface. Our NbO\({}_{\text{x}}\)/NbSe\({}_{2}\) heterostructure is operating in a lateral direction (Au-NbO\({}_{\text{x}}\)-Au) by resistance switching through the lateral NbO\({}_{\text{x}}\) layer on top of NbSe\({}_{2}\). Furthermore, in the NbO\({}_{\text{x}}\)/NbSe\({}_{2}\) lateral memristor, total resistance (R\({}_{\text{tot}}\)) can be considered as NbSe\({}_{2}\) resistance (R\({}_{\text{NbSe2}}\)) + NbO\({}_{\text{x}}\) resistance (R\({}_{\text{NbOx}}\)) (Figure S6) [31]. In the case of a low resistance state (LRS), R\({}_{\text{tot}}\) is more influenced by R\({}_{\text{NbSe2}}\) compared to R\({}_{\text{NbOx}}\) because of the formation of conductive filament interior of the oxide layer. Thus, during the LRS state, low R\({}_{\text{tot}}\) can be realized by using a thicker metallic NbSe\({}_{2}\) layer, resulting in high-performance LRS. Figure 4b shows the optical microscope images and AFM mapping images of intrinsic multi-layer NbSe\({}_{2}\) flake (top-panel) and the NbO\({}_{\text{x}}\)/NbSe\({}_{2}\) flake (bottom panel) are depicted. The intrinsic multi-layer NbSe\({}_{2}\) was observed to have a 12-nm thickness (black solid line in Figure 4c). After a period of 21 days in the air condition, the native NbO\({}_{\text{x}}\) oxide was formed. The height of the flake was increased up to 15 nm (blue solid line in Figure 4c) which can be interpreted as forming a 3-nm NbO\({}_{\text{x}}\) native oxide layer on top of the intrinsic NbSe\({}_{2}\) flake. Figure 4d shows the current-voltage (I-V) characteristic of our NbO\({}_{\text{x}}\)/NbSe\({}_{2}\) heterostructure memristor device. The inserted image is an optical microscope image of our device. Voltage was swept as 0 V \(\rightarrow\) +1 V \(\rightarrow\) -1 V \(\rightarrow\) 0 V between the drain and the source electrode with the duration time of 0.1s, which showed reproducible and nonvolatile hysteretic resistive switching behavior in synaptic memory. During the positive voltage sweep, the current increased via migration of positively charged oxygen vacancies (conductive filament (CF) formation), with which the device showed the HRS to LRS transition. The resistance state kept LRS with the reverse voltage sweep. Then, again, the reset transition process started at \(-\)1V, and the LRS to HRS transition was exhibited during the negative voltage sweep. Here, the noise had occurred during the I-V switching measurement, which is probably due to the non-uniform and ultra-thin native oxide layer (\(\sim\) 3 nm NbO\({}_{\text{x}}\)). It is suggested that the conductive  
Figure 3: Electrical properties of the CVD-grown NbSe\({}_{2}\) field-effect transistor (FET) device. (**a**) Optical image of the NbSe\({}_{2}\) device with drain and source electrodes; (**b**) transfer characteristic with gate voltage sweep from \(-\)50 V to 50 V under constant drain bias ranges from \(-\)0.5 V to 0.5 V. No switching property was observed according to the gate voltage. (**c**) Output characteristic with drain voltage sweep from \(-\)0.5 V to 0.5 V under constant gate bias ranges from \(-\)50 V to 50 V. Under different gate biases, a similar current level of drain bias was observed, which also shows the metallic properties, no gate dependency.