## 3 Circuit Description  
### Dco  
Figure 3 shows the block diagram of the digitally controlled oscillator (DCO). DCO is designed using a triple-loop configuration to achieve precise frequency control and stability over a wide frequency range. This design divides the control bits of the DCO into three main loops, each playing a critical role in frequency control and stability. The first loop, the automatic frequency control (AFC) loop, uses 6 bits out of the 15 total control bits and has a frequency change per 1-bit code step (Kdco) of 66.5 MHz. This loop is responsible for coarse frequency tuning, allowing the DCO to quickly approach the desired frequency with large frequency steps. The high Kdco value in this loop ensures rapid adjustments, which is essential for initial frequency acquisition. The second loop, the frequency-locked loop (FLL), uses 4 bits of the 15 control bits and is designed with a Kdco of 7.44 MHz. This loop provides finer frequency adjustments compared to the AFC loop, allowing for more precise frequency locking. The smaller Kdco value facilitates reduced phase noise and enhances the accuracy of frequency control. The third loop, the digital fractional-N SSPLL loop, utilizes the remaining 5 control bits with a Kdco of 531 kHz. This loop is dedicated to the finest frequency adjustments, enabling very small frequency steps for high-resolution tuning. The sub-1 MHz Kdco value in this loop is crucial for maintaining stability and reducing phase noise in the final output.  
For seamless transitions between the loops and to maintain frequency stability across process, voltage, and temperature (PVT) variations, careful overlap between the control ranges of each loop is necessary. The overlap regions ensure that there are no gaps in frequency control, which could otherwise lead to instability or frequency jumps. The overlap ratio between the AFC and FLL loops is approximately 24%, achieved using a successive approximation register (SAR) logic that provides stable frequency control regardless of PVT variations. The overlap ratio between the FLL and SSPLL loops is around 54%, facilitated by a moving average filter that smooths transitions and maintains stability. These carefully designed overlap ratios and control mechanisms allow the DCO to achieve a small Kdco relative to the number of control bits, enhancing the resolution and accuracy of frequency tuning. Performance-wise, the DCO covers a frequency range of 1.9-6.1 GHz with a resolution of 531 kHz/code using a 15-bit control. The incorporation of a digitally controlled delay element (DCDE) in the ring oscillator (RO) design plays a significant role in achieving these performance metrics [19]. The RO's frequency is directly proportional to the current, allowing for precise control over the oscillator's frequency. Although phase noise tends to worsen with increasing frequency, this effect is compensated by the increased current, resulting in consistent phase noise performance across the entire frequency band.  
In conclusion, the triple-loop configuration of the DCO, with its carefully designed overlap regions and control mechanisms, ensures high resolution and stable frequency control across a wide frequency range. The use of DCDE further enhances performance, providing a robust solution for applications requiring precise timing generation. This  
Figure 3: Block diagram of digitally controlled oscillator.  
design demonstrates significant improvements in phase noise and frequency stability, making it suitable for wideband PLL applications.