# A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR
## 2 Proposed Multi-Lane SerDes Receiver Architecture
### Proposed PI Controller  
Figure 5a shows the block diagram of the proposed PI controller. It consists of an initial phase tracker (IPT), an early/late (E/L) detector, a majority vote logic (MVL), a digital loop filter (DLF), a 2-to-1 MUX, and an octant phase controller. The proposed PI controller provides two operation modes; initial tracking mode and sequential tracking mode. Figure 5: (**a**) Proposed PI Controller with an initial phase tracker. (**b**) Octants phase planes with 72 phase steps depending on the control code: MA\(<\)1:0\(>\), MB\(<\)1:0\(>\), and PI\(<\)8:0\(>\). At power-on, the operation of the CDR starts in the initial tracking mode. The IPT uses a repeated preamble of the \"00001111\" pattern to achieve both the fast lock time and the constant data output sequence. During this mode, the IPT compares E\(<\)1\(>\) and E\(<\)3\(>\) edge information based on the phase of Eclk1. The PI controller quickly makes the rising edge of Eclk3 align with the first rising edge of the \"1111\" pattern. Since the phases of Eclk1 and Eclk3 are shifted 180 degrees, when the rising edge of Eclk3 is located at the center of the preamble \"0000111\" pattern, Dclk1 is automatically located at the center of D0 as shown in Figures 4b and 5a. In this initial tracking mode, the operation of the CDR is similar to the phase tracking operation of a delay-locked loop (DLL). The initial tracking mode is performed during 36 \(\mathrm{CLK}_{\mathrm{CONT}}\) cycles. The stop signal changes from zero to one after 36 \(\mathrm{CLK}_{\mathrm{CONT}}\) cycles. The frequency of \(\mathrm{CLK}_{\mathrm{CONT}}\) (\(f_{\mathrm{CLK}_{\mathrm{CONT}}}\)) is 3.125 GHz, which is half of the frequency of Eclk3, so the total initial tracking mode takes about 11.52 ns. The PI of the PI-based CDR must have the ability to randomly shift the phase of the output signal up to 360 degrees. Therefore, as shown in Figure 5b, the output signals MA\(<\)1:0\(>\) and MB\(<\)1:0\(>\) of the octant phase controller are used to allocate the octant phase planes. The PI\(<\)8:0\(>\) is used to divide the 45 degree phase into nine phases, so the resolution of the proposed PI corresponds to 5 degrees, which is about 2.22 ps in this design. Thus, the octant phase planes consist of a total of 72 phase steps, which are associated with an initial tracking mode of only 36 (= 72/2) cycles (for 180 degrees in both directions). After the initial tracking mode, the sequential tracking mode using 2x-oversampling is performed. The output of the eight samplers, D\(<\)3:0\(>\) and E\(<\)3:0\(>\), are used as an input to the E/L detector. The E/L detector compares the output of adjacent samplers and generates the Early\(<\)7:0\(>\) and Late\(<\)7:0\(>\) signals. The MVL determines whether the phases of the sampling clocks are earlier or later than the incoming data stream by majority voting. The digital loop filter (DLF) composed of an encoder and a variable finite-state machine (FSM) receives the EA\(<\)1:0\(>\) and LA\(<\)1:0\(>\) signals. It generates the \(\mathrm{UP}_{\mathrm{DLF}}\)/\(\mathrm{DN}_{\mathrm{DLF}}\) signals that can change the output signals of the octant phase controller. The encoder compares the EA\(<\)1:0\(>\) and LA\(<\)1:0\(>\) to generate the Comp signal and the Equal signal. If EA\(<\)1:0\(>\) has more numbers than LA\(<\)1:0\(>\), the output Comp signal goes high, and in the opposite case, the Comp signal goes low. If E\(<\)1:0\(>\) and L\(<\)1:0\(>\) have the same number of 1's, an Equal signal is generated, and the FSM maintains the previous value. The octant phase controller implemented with an up/down counter generates the control codes (MA\(<\)1:0\(>\), MB\(<\)1:0\(>\), and PI\(<\)8:0\(>\)) for the phase selector (PS) and the phase interpolator (PI). For the design of the proposed PI controller, a full-custom design was used for a high-speed operation. Both the E/L detector and the IPT operate at 6.25 GHz. Other PI controller blocks also operate at a high speed of 3.125 GHz, which results in the advantage of reducing the loop latency.