# In-Plane Monolithic Integration of Scaled III-V Photonic Devices
## 1 Introduction  
The integration of III-Vs on silicon is a long-standing goal because it would allow us to combine the attractive features of a low-cost, highly developed, and complex silicon platform with the added functionality of active photonic devices such as light sources and detectors. On one hand, there is mature Si technology which benefits from strong light confinement due to a high refractive index contrast between Si and SiO\({}_{2}\) and from highly optimized low-roughness etch technologies. Consequently, this has led to the demonstration of high-speed and low-loss passives [1; 2]. On the other hand, there are the III-V-based semiconductors which, due to their direct bandgap, allow for efficient light emission in the near-IR, where Si is transparent. Furthermore, the ability to tune the bandgap by changing the composition allows for the creation of heterostructures and quantum wells, which are essential parts of advanced semiconductor laser designs. Combining these materials directly is challenging, since they are not lattice-matched and have different thermal expansion coefficients and polarities. Thus, growing a planar sheet of III-V on top of silicon typically results in a poor material quality. The most common method for advanced integrated photonic applications is the direct-wafer bonding of a III-V wafer or individual III-V components on top of a Si wafer [3; 4; 5; 6]. This allows to grow the appropriate stack of III-V material lattice matched on a III-V carrier wafer, which may subsequently be recycled. It is of special interest for adding active components to silicon photonics, as this also allows to transfer high-quality III-Vmaterial onto a pre-patterned silicon or SOI wafer containing passive silicon features [1; 7; 8; 9], thereby creating hybrid photonic components; at IBM, we are also actively exploring this technique for use in advanced photonic devices [10]. Similarly, stacked devices have also been fabricated by transfer-printing the devices fabricated on the III-V substrate onto a Si photonics chip [11; 12]. Light then couples evanescently between the two layers, from the silicon waveguides to the bonded III-V active material or vice versa, depending on whether the application is emission or detection. For densely integrated photonic circuits foreseeing thousands of individual links, a seamless and local monolithic integration of III-V material is highly desirable. Vertical III-V nanowires (NWs) on silicon have been realized by selective-area growth through metal organic chemical vapor deposition (MOCVD), where the III-V material is grown out of an oxide mask [13; 14] or by extending device designs to nanowire arrays [15; 16]. However, the typical vertical orientation of the NWs makes the large-scale integration and electrical actuation of more advanced devices challenging. While the planar growth of NWs has been demonstrated [17; 18; 19], it is yet to be successfully implemented for photonic applications. Instead, NW pick-and-place techniques have been used successfully to demonstrate high-performance proof-of-concept devices by placing a III-V nanowire within a resonant cavity for either emission [20] or detection [21]. Aspect ratio trapping (ART) is another epitaxial technique which allows for the use of high-quality material in a horizontal device [22; 23]. Here, the propagation of defects after growth nucleation is terminated in one direction within an oxide trench. Nano-ridge lasers were fabricated by this method in [23; 24; 25; 26], but further development is necessary for implementing arbitrary geometries and doping profiles. An overview of the above fabrication methods is presented in Figure 1 with a focus on the integration scheme with Si and the III-V growth direction, which defines the inherent orientation of heterostructures or doping profiles and therefore is a determinant for the device architecture.