## 3 Proposed Driver Design  
Radiation tolerance requirements pose severe limitations in the design of an ASIC. Recently, several studies were conducted on deep sub-\(\upmu\)m platforms suitable for high-speed applications, e.g., 65 nm [36] and, even more recently, 28 nm [37] technologies. Total ionizing dose (TID)-induced charge trapping determines transistor parameter drifts and leads to the formation of current leakage paths in active regions next to shallow trench isolations (STIs) [38]. Moreover, p-type MOSFETs result in being less tolerant than n-type ones, and radiation-induced short/narrow channel effects are reported. As a consequence, few RHBD techniques have been drawn to extend the radiation hardness of a given ASIC design [39]. According to those rules, p-type and minimum-length MOSFETs have not been used throughout the design, and only thin-oxide enclose layout transistors (ELTs) have been exploited [40]. The whole driver consists of a five stage tapered chain of standard CML buffers followed by the proposed output stage, which needs to be capable of driving both differential, as well as single-ended SiPh modulators. The aforementioned radiation-related guidelines affect the architecture choice for the last stage. CMOS-like solution are surely not feasible since they harness p-MOSFETs. However, current steering structures, such as those presented in Section 2.2, are also not suitable. Connecting an LE phase shifter directly to the two output leads, the differential swinging would determine the pn-junction forward biasing. Instead, loading only one branch with a single-ended load would unbalance the circuit. Dummy loads can in principle be used to restore the balance, as is sometimes done in certain drivers [41]. Nevertheless, they undoubtedly introduce mismatches and possibly lead to spurious phase modulation at GHz-range frequencies, affecting jitter performances [29]. As shown in Figure 4, a pseudo-differential structure, i.e., a differential pair without a tail current source, appears to be a viable solution for the problem. Resistive pull-up is preferred to the SF-based topologies to save the voltage drop on the upper transistors and get the highest possible swing out of the circuit. Conventional SF-based topologies do not produce voltage gain, and their usage leads to more complex pre-driving and output stage designs [42]. For the ease of testing and to drive also terminated devices, the internal load resistors, indicated with \(R_{0}\) in Figure 4, are nominally chosen  
Figure 3: Output stages suitable for lumped-element (LE) device driving. (**a**) Source follower-based current-steering pair. (**b**) CMOS gate-like topology. Different transistor stacking arrangements can be exploited with the aid of floating supply rails [26; 31; 33; 34; 35]. Dealing with ring modulators (RMs), cathode and anode driver stages are sometimes separated (dashed line) to provide a slight forward bias to the pn-junction [32]. as \(50\,\Omega\). The tail current source removal also helps in enlarging the peak-to-peak output swing by saving the voltage headroom normally left for the biasing MOSFET (on the order of an overdrive voltage). The common-mode level of the last pre-driving CML stage should be lowered approximately by the same amount in order to drive the input transistors of the output stage properly. Anyway, the intrinsic input common-mode sensitivity associated with pseudo-differential structures has no great importance in this specific case since, dealing with non-return-to-zero (NRZ) signals, the circuit operates in switching large-signal mode [29]. To further increase the output swing, a doubled supply voltage \(V_{\mathrm{DD_{H}}}=2.4\,\mathrm{V}\) (with respect to the \(1.2\,\mathrm{V}\) applied elsewhere) is used in the last stage. A cascode structure is then implemented to keep voltage stresses on MOSFETs in the technology's safe operating area (SOA). Harnessing thick-oxide devices in the series transistor stacking could have allowed increasing even more the output supply voltage.