# Generating Airborne Ultrasonic Amplitude Patterns Using an Open Hardware Phased Array
## 3 Hardware Design
The generator blocks have a dataline of five bits to read phases or amplitudes when the line setPhase or setAmp goes high. It also has a swap line, which swaps the phases/amplitudes when it goes high; this is to implement the double buffer. Eight generator blocks are grouped into a multiplexer, giving a total of 32 multiplexed lines that are output from the FPGA, as well as the shift and latch clocks. There are six auxiliary general-purpose inputs/outputs (GPIOs) (we have denominated them from A to F) that can be operated, defined, and implemented by the user. For example, B is used as the UART input, D is used as sync out (internal 40 kHz reference), E can be used as sync in (40 kHz signal to synchronize the global counter), and A can be used as a UART out; C and F are free for custom applications. Figure 5 shows the block diagram of the FPGA firmware. The UART Reader and Distributor blocks operate with the internal clock, the generator blocks and multiplexers operate with a clock that is synchronized with the sync in signal. Thereby, when multiple boards operate together, the emission waves have exactly the same frequency. If the emission clocks were not synchronized, traveling waves would be created [41], making the generation of static fields impossible. A master board has its sync out connected to its sync in, slave boards take the sync signal from the master board. Figure 4: Ultrasonic array built with Through-hole components and emitters of 16 mm diameter. (**Left**) transducers of 16 mm diameter soldered on the printed circuit board (PCB). (**Center**) back of the board with the shift registers, drivers and decoupling capacitors. The FPGA board is connected through an expander board. (**Right**) detailed view of a shift register block. Figure 3: Board with surface mounted devices and emitters of 10 mm diameter. (**Left**) Top view of the Sonic surface where 16 \(\times\) 16 ultrasonic emitters can be seen. At the sides there are connectors for power, Universal asynchronous receiver-transmitter (UART) in, grounds, sync out and sync in. (**center**) bottom view where the shift register blocks can be seen with the FPGA on top. (**right**) closer view on a shift register block where a shift register demultiplexes a digital line into eight signals that are fed to four dual-drivers and then into eight ultrasonic emitters. The presented hardware has been optimized for an operating frequency of 40 kHz. This is the most common frequency for airborne ultrasonic phased arrays [9; 38; 41; 42], operating at higher frequencies is not straightforward. On the one hand, the multiplication of signals is used to reduce the required traces on the PCB and pins on the FPGA, our current system requires just a two-layer PCB and 40 GPIOs of the FPGA. However, this multiplexation leads to a 10.24 MHz shift clock. Increasing the frequency or phase resolution would require a higher clock frequency, which is beyond what is recommended for a simple PCB or the specs of the shift registers. On the other hand, commercially available transducers that operate at higher frequencies (e.g., 100 kHz or 400 kHz from MultiComp) are 10 mm in diameter and, thus, emit a very narrow beam. The emission from an array of these emitters would not interfere between each other and, thus, would not be suitable for the techniques presented here or phased-array techniques in general.