# Towards Large-Scale Fast Reprogramable SOA-Based Photonic Integrated Switch Circuits
## 4 Monolithically Integrated InP 8 \(\times\) 8 Space and Wavelength Selecting Switch  
Orders of magnitude increases in reconfigurability become possible when the use of wavelength division multiplexing (WDM) is combined with on-chip wavelength selective routing: The 8 \(\times\) 8 integrated cross-connect represents an elegant example of an in-plane circuit which provides a connectivity of up to 64 input and output channels [27]. Here, we perform both space domain switching and wavelength domain channel selection within the same monolithic circuit in order to show the highest level of connectivity and data capacity on a single InP photonic integrated chip. The architecture for broadband photonic and wavelength selective cross-connection is shown in Figure 2a. The circuit consists of a combination of a broadband photonic switch stage (PSS) for port selection and a wavelength selecting stage (WSS) for color selection, both based on the use of SOAs. Eight colorless WDM input ports connect to an array of pre-amplifying SOAs. Broadcast shuffle networks map each of the inputs to the eight output ports. The first stage of SOA gates is used for input port selection and connects to eight cyclic arrayed waveguide gratings (AWGs). The AWGs route the different wavelength channels to the second stage array of broadband SOAs to perform wavelength selection. Selected channels are aggregated with broadband fan-ins to provide the eight colorless outputs. The grey-scale layers in Figure 2a are the other seven identical layers implemented in the integrated circuit for both stages. The red boxes are the SOA-gates used in each of the stages. The device is realized on a re-grown active-passive InGaAsP/InP epitaxy. An optical image of the chip is shown in Figure 2b. The eight pre-amplified colorless inputs are broadcast through a shuffle network made of cascaded 1 \(\times\) 2 multimode interferometer (MMI) splitters. After port and color selection, the selected channels are combined with broadcast cascaded 2 \(\times\) 1 MMI couplers. The active islands in the InP wafer are used for SOA gates and preamplifiers, while the passive regions are used for waveguide wiring, splitters, and cyclic routers. The cyclic AWG used in the WSS is designed with a channel spacing of 3.2 nm (400 GHz) and a free spectral range of 25.6 nm. All input and output waveguides are positioned on a 250 \(\upmu\)m pitch to enable simultaneous access to all the ports using a commercially sourced lensed fiber array. The 136 SOA contacts are wire-bonded to an electronic printed circuit board (not shown). The chip is attached with conductive epoxy to a water-cooled block. The total footprint of the switch is 16.4 \(\times\) 6.7 mm\({}^{2}\). Electrical I-V characteristics are analyzed to identify 126 SOAs with good diode characteristics out of a total of 136. Two fails are attributable to an imperfect lithographic step causing electrode detachment, six are associated with bond-wire detachments, and two are short circuits. From the photonic switching stage to the output side, 432 paths out of 512 paths connections are verified: 84% of the paths from the input to the output side of the chip are electrically and therefore optically connected in this first prototype. Each path includes three SOAs as in the 16 \(\times\) 16 broadcast switch matrix, but the losses are modest, which indicates a more straightforward route to further scaling. However, in this case the multi-stage switch is characterized by an asymmetric chain of SOAs: Moving to a 16 \(\times\) 16 cross-connect, for example, implies the introduction of six splitters after the first amplifier which needs to be compensated by a longer second-stage SOA. Multi-path WDM 10 Gb/s data routing is demonstrated through the experimental control plane schematically shown in Figure 3. Very importantly, a common reference clock generator is needed for the programmable logic and the bit error rate test equipment to allow synchronization between the routed data and the switch controller.