## 6 Hardware Implementation  
In this section, we describe the hardware implementation results of our proposed lookup architecture in detail. The proposed satellite IP route lookup engine is implemented in Verilog HDL on a Xilinx Virtex-7 XC7 VX690T FPGA chip, and the development environment is Vivado 2019.2. Our prototype design is downloaded on the FPGA development board, which is equipped with two 4 GB DDR3 synchronous DRAMs (SDRAMs). We use a single DDR3 memory for next-hop information (NHI) storage. Table 5 shows the on-chip memory requirement in the hardware implementation. There are two types of on-chip BRAMs: 18 k-bit blocks and 36 k-bit blocks, which are automatically allocated for each module. Note that the memory of each module is allocated in standard blocks, thus the practical memory requirement of filter structure in the CBHF is \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Routing Prefix Set**} & \multirow{2}{*}{**Level/Filter**} & \multicolumn{3}{c}{**BF/CF**} & \multicolumn{3}{c}{**CBHF**} \\ \cline{3-8}  & & **Theoretical** & **Observed** & **Theoretical** & **Theoretical** & **\({}^{*}\)** & **Observed** \\ \hline \multirow{4}{*}{1 k} & 1/BF & 0.50000 & 0 & & & \\  & 2/BF & 0.02459 & 0.00783 & 0.52549 & 0.05098 & 0.00608 \\  & 3/CF & 0.02700 & 0.01135 & & & \\  & 4/CF & 0.00006 & 0.00081 & & & \\ \hline \multirow{4}{*}{5 k} & 1/BF & 0.75000 & – & & & \\  & 2/BF & 0.00716 & 0.00625 & & & \\ \cline{1-1}  & 3/CF & 0.02475 & 0.01089 & & & \\ \cline{1-1}  & 4/CF & 0.00006 & 0.00074 & & & \\ \hline \multirow{4}{*}{25 k} & 1/BF & 0.75000 & – & & & \\ \cline{1-1}  & 2/BF & 0.02488 & 0 & & & \\ \cline{1-1}  & 3/CF & 0.02761 & 0.01196 & & & \\ \cline{1-1}  & 4/CF & 0.00007 & 0.00092 & & & \\ \hline \hline \end{tabular} \({}^{*}\)Theoretical values after revision.  
\end{table} 
Table 4: Theoretical and observed false positive probability. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Routing Prefix Set**} & \multirow{2}{*}{**Level/Filter**} & \multicolumn{3}{c}{**CBHF**} & \multirow{2}{*}{**Total Memory**} \\ \cline{3-8}  & & & **Hash** & & **Width (Bits)** & **Depth** & **(Bytes)** & **(KB)** \\ \hline \multirow{4}{*}{1 k} & 1/BF & IP [31] & 1 & \(1+0\) & 2 & 0.25 & \\  & 2/BF & IP [31:23] & 4 & \(1+3\) & 1024 & 512 & \\  & 3/CF & IP [31:15] & \(1+1\) & \(4\times 8\) & 256 & 1024 & \\  & 4/CF & IP [31:7] & \(1+1\) & \(4\times 16\) & 2 & 16 & \\ \hline \multirow{4}{*}{5 k} & 1/BF & IP [31] & 1 & \(1+0\) & 2 & 0.25 & \\  & 2/BF & IP [31:23] & 4 & \(1+3\) & 4096 & 2048 & \\  & 3/CF & IP [31:15] & \(1+1\) & \(4\times 8\) & 1024 & 4096 & 6.25 \\  & 4/CF & IP [31:7] & \(1+1\) & \(4\times 16\) & 32 & 256 & \\ \hline \multirow{4}{*}{25 k} & 1/BF & IP [31] & 1 & \(1+0\) & 2 & 0.25 & \\  & 2/BF & IP [31:23] & 5 & \(1+3\) & 2048 & 1024 & \\ \cline{1-1}  & 3/CF & IP [31:15] & \(1+1\) & \(4\times 8\) & 4096 & 16,384 & \\ \cline{1-1}  & 4/CF & IP [31:7] & \(1+1\) & \(4\times 16\) & 32 & 256 & \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Configuration of CBHF structure for testing routing prefix sets. greater than that in Table 3. The on-chip memory requirement for other modules is shown as well. The value of total BRAMs is the capacity of memory required in KByte, and the utilization rate of total BRAMs is based on the amount of available block memory, which is 52,920 Kbits on an XC7 VX690T chip. The resource utilization is listed in Table 6. It is shown that the utilization of BRAM increases considerably as the size growth of the routing prefix sets increases, while the utilization of LUT and FF is almost invariant. In addition, the utilization of IO and BUFG is constant, since their numbers do not depend on the sizes of the routing prefix sets. In order to enhance system reliability, triple modular redundancy (TMR) is widely adopted in satellite applications, which requires two extra duplicate systems to guarantee correct operations.