A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9-6.1 GHz Frequency Tuning  
1 Department of Computer Science and Electrical Engineering, Handong Global University, 558, Handong-ro, Heunghae-eup, Bulk-gu, Pohang-si 37554, Gyeongsangbuk-do, Republic of Korea;  
[PERSON]DRESS]  
2 School of Electronic Engineering, Engineering Research Institute (ERI), Gyeongsang National University, 501, Jinju-daero, Jinju-si 52828, Gyeongsangam-do, Republic of Korea  
* Correspondence: [EMAIL_ADDRESS]  
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required for LC oscillators occupy a significant chip area, and such analog designs often lead to high power consumption. To address these issues, we propose a ring oscillator-based triple-loop all-digital PLL (ADPLL) that meets the performance, power, and area requirements for 5G networks and IoT applications. In the proposed triple-loop ADPLL configuration, we adopt automatic frequency control (AFC) and counter-assisted PLL (CAPLL) structures in the first and second loops, respectively. These structures were chosen because they allow for the shared use of counters, differentiators, and comparators, effectively reducing the chip area. Additionally, the second loop employs a counter-based PLL structure to minimize chip area while eliminating the time-to-digital converter (TDC) and TDC gain matching circuits. For stable loop switching, it is common to have three or more overlaps in the frequency range of a digitally controlled oscillator (DCO) between loops to ensure stable loop switching [11; 12; 13]. However, as the frequency overlap ratio between the loops controlling the DCO increases, the Kdco value rises for the same frequency range and digitally controlled bits. This degradation in Kdco adversely affects the performance of the PLL. In the proposed architecture, a moving average filter is used when switching from the second loop to the third loop. Despite the absence of the TDC in the second loop, this approach enables stable loop switching with only two overlaps in the ratio. This is achieved by applying the digital control bits obtained through the moving average filter to the DCO when the second loop is locked, thereby maintaining stable loop switching and acceptable noise performance. Furthermore, we control the ring oscillator (RO) frequency by adjusting the current with MOSFETs rather than using a Cap-switch structure [14], thereby reducing the RO area. To minimize power consumption, we introduce a divider-less digital sub-sampling PLL in the third loop. This approach significantly reduces the overall power consumption of the system by eliminating the power-hungry divider commonly used in PLL architectures. The ring oscillator-based triple-loop ADPLL proposed in this paper is an efficient design that simultaneously satisfies low power and low area requirements while maintaining high performance. Although ring oscillator-based ADPLs can suffer from poor out-of-band noise, increasing the PLL bandwidth significantly suppresses this noise. This enables the ADPLL to meet the integrated phase noise characteristics required for 5G FR1 communication as specified by 3 GPP, making it suitable not only for 5G networks but also for various IoT applications. Thus, the proposed design is not only energy-efficient and compact but also meets the stringent performance standards needed for advanced communication technologies. This article is organized as follows: Section 2 details the system architecture, describing the overall design and functionality of the proposed system. Section 3 focuses on the circuit description, offering an in-depth analysis of the circuit components and their operation. Section 4 shows the chip layout, designed compactly using the 28 nm CMOS process. Section 5 presents the experimental results, demonstrating the performance and validation of the proposed system through various tests.