# A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR
## 1 Introduction  
The role of optical or electrical networks that enable high-performance servers and data centers to perform energy proportional computing [1] is increasing day by day. Therefore, there is an increasing demand for energy-efficient electrical serial links (as shown in Figure 1) that require data rates of over 25 Gb/s/lane for tera-byte computing in recent servers and data centers. Figure 1 shows a block diagram of a typical high-speed serial-link serializer/deserializer (SerDes) architecture [2; 3; 4; 5; 6; 7; 8] where the transmitter (Tx) chip and the receiver (Rx) chip are connected through a backplane or copper cable channel. The serializer of Tx converts slow parallel data into high-speed serial  
Figure 1: Typical high-speed serial-link SerDes architecture. data by using the high-frequency clock, \(\mathrm{CLK_{TX}}\), generated by the phase-locked loop (PLL). The converted serial data (DATA_TX) is transmitted to the Rx chip through the lossy channel. The equalizer of the Rx chip receives the severely distorted \(\mathrm{DATA_{RX}}\) signal. It compensates for the channel losses and inter-symbol interference (ISI) to generate the clock and data recovery (\(\mathrm{CDR}\))\({}_{\mathrm{IN}}\) signal with an open eye. Subsequently, the clock and data recovery (\(\mathrm{CDR}\)) uses a data sampler and a clock recovery circuit to generate the recovered data and clock from the random input data. The recovered data is then converted into slow parallel data through the deserializer. Usually, the PLL of Rx receives the low-frequency reference clock and generates the multiplied high-frequency \(\mathrm{CLK_{RX}}\) signal for the CDR Conventionally, the CDR architectures have been implemented based on a PLL due to the advantage of an input jitter filtering capability. However, conventional PLL-based CDRs have a long lock time and a jitter accumulation problem [9; 10]. To implement an efficient energy proportional computing network, burst-mode communication has been used for passive optical networks (PON) [11; 12] and recently, an attempt has been made to increase the power efficiency by applying a burst-mode to a memory bus interface [13]. Therefore, a CDR technology having a fast lock time (= power-on time or acquisition time) is very important for low-power burst-mode implementation. It has become common to increase data throughputs using multiple lanes (or channels) of high-speed serial links as the aggregate I/O bandwidth of a single chip exceeds hundreds of Gb/s. Among these high-speed serial buses, multi-lane source synchronous serial-links have been used for backplane applications that provide connectivity between CPU and CPU, CPU and dual in-line memory modules (DIMMs), and CPU and bridge chips. Multiple serial point-to-point lanes can be placed in parallel to increase the aggregate bandwidth. The most representative multi-lane source synchronous serial-links are Intel QuickPath Interconnect (QPI) [14] and AMD HyperTransport (HT) [15]. Figure 2 shows typical multi-lane high-speed source synchronous serial-link architectures [16]. As shown in Figure 2a, in the source synchronous clocking structure, the Rx receiver uses the transmitted clock almost identically correlated to the noise environment of the Tx chip so that high-speed data can be restored with low power and low latency. If half-rate sampling is used on the Rx chip, the frequency of the transmitted clock can be lowered to half. As the data rate of the channel increases above a few Gb/s/lane, the method of Figure 2a has reached its limit, and as shown in Figure 2b, PLL (or DLL or just simple deskew circuits) has been added to the clock path at the Rx side, through which improved timing margin and skew cancellation [17; 18; 19; 20; 21]. If 1:2 de-multiplexing is used at the receiver path of each data lane, the forwarded clock rate can be reduced to 1/2 frequency.