# An Improved Low-Density Parity-Check Decoder and Its Field-Programmable Fate Array Implementation
## 4 Improved LDPC Decoder Hardware Design and Implementation
### Data Storage Section  
In this design, the storage modules include llr_ram, which stores the initial channel messages, and H_ram, which stores the confidence message matrix. The quantized channel information is received by the decoder and entered into the 24 llr_ram blocks through the buffer input module.  
Based on the structure of the H matrix in the IEEE 802.16e standard for the 672-length LDPC code, the 672 8-bit quantized data values are distributed across 24 dual-port RAMs (each llr_ram). Each RAM block has an 8-bit width and a depth of 32. Every dual-port RAM stores 28 8-bit quantized data values, and the storage structure is illustrated in Figure 5.  
To implement the correction factor \(\beta\), a 1-bit-wide read-write signal is used. With the enable signal, this read-write signal increments by one on each clock cycle. When the enable signal is active, the read-write signal cycles between 0 and 1.  
When the read-write signal is 0, a signal at one of the depths in each llr_ram is read. After performing a self-update using the shift-add operation under correction factor \(\beta\), the updated data is written back into the corresponding llr_ram depth when the read-write signal switches to 1.  
Figure 5: Channel information storage.  
All channel information undergoes a self-update within 28 clock cycles for the current iteration. To prevent signal overflow, both channel information and check node information are right-shifted once during the first, fourth, seventh, and every third subsequent iteration.  
Each row and column of the sub-matrices in the parity-check matrix H contains at least one non-zero element. Each sub-matrix is a cyclic right-shifted identity matrix, where the amount of shift is determined by the value of the corresponding element in the base parity-check matrix.  
This structure allows storing a one-dimensional array in RAM and, in conjunction with the shift address update module, writing/reading it into the corresponding position in the sub-matrix of H as a two-dimensional array.  
For instance, if the value at row i and column j in the base matrix is p, then the corresponding sub-matrix in H is a 28 \(\times\) 28 identity matrix cyclically right-shifted by p positions per row. The H_ram at this position stores 28 data values (from 0 to 27). Each depth s in H_ram represents the value of the non-zero element in row s and column s + p in the sub-matrix, as illustrated in Figure 6.  
In the RAM array composed of multiple H_ram modules, each H_ram corresponds to an element in the base parity-check matrix \(H_{\text{B}}\). Under the control of the main module and with the assistance of the check node processing (CNP) and variable node processing (VNP) modules, information is continuously exchanged, as illustrated in the Figure 7. If an element in the base matrix equals \(-1\), the corresponding sub-matrix in the H matrix will be a zero matrix and does not need to be stored.  
Figure 6: Confidence message matrix storage.  
Figure 7: Information exchange between nodes.  
According to the base parity-check matrix \(H_{\mathbf{b}}\) shown in Figure 3, there are 76 non-negative elements. Thus, 76 H_ram modules are required, each being a dual-port RAM with an 8-bit width and a depth of 31. These will store the information for the non-zero elements in the parity-check matrix.