# Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers
## 3 Related Works
### Proposed Data Parallelism Technique
#### 4.1.3 Revised CHAM Optimization  
We introduce an efficient data parallel implementation of the revised CHAM family. We describe our approach on the basis of the revised CHAM-64/128 because revised CHAM-128/128 and revised CHAM-128/256 are almost the same except for lanes because word units are different for revised CHAM-64/128. In the existing parallel implementation of revised CHAM [19], the transpose process was required to apply data parallelism, but we make data parallelism to be applied automatically when loading data from four vector registers to memory and storing data from four vector registers to memory through _LD4_ and _ST4_ instructions in the revised CHAM family. In addition, the maximum number of encryptions are performed simultaneously by utilizing all vector registers. Forty-eight encryptions are performed simultaneously, in revised CHAM-64/128, and 24 encryptions are performed simultaneously, the remaining revised CHAM. The vector register scheduling for processing maximum encryptions in revised CHAM-64/128 is shown in Figure 10. The register scheduling of the remaining revised CHAM is similar to that of LEA, and only the _v2_7 vector register needs to be set as a counter. Algorithm 4 shows a parallel implementation of odd and even rounds with a data parallelism technique of revised CHAM-64/128. Algorithm 4 may also look like the HIGHT optimized implementation of [10], but the HIGHT optimized implementation of [10] applied the task and data parallelism techniques, and, in Algorithm 4, only the data parallelism technique is applied. Our contribution in Algorithm 4 is that the data parallelism technique for HIGHT and the transpose operation required to apply data parallelism technique is processed with _LDN_ and _STN_ instructions without computational overhead. In addition, we apply only the data parallelism technique for revised CHAM-64/128, so there is no necessity for a transpose operation within the round function, which is required in revised CHAM-64/128 optimized implementation of [10]. The data parallelism technique is applied to the Algorithm 4, so it processes eight encryptions for the round function, and the remaining plaintexts are encrypted by interleaving instructions efficiently through the Temp registers. Since the revised CHAM-64/128 performs round operations in 16-bit-wise, the lane, which is the unit of parallel processing of vector registers, is set in units of 8 h. In Step 1, plaintexts are automatically transposed through the _LD4_ instruction and loaded from memory into four vector registers. Step 2 loads the round keys for processing four rounds into the four vector registers. In Step 3, one word of the plaintexts and the counter value are _XOR_ed. In Steps 4-5, the _ROL\({}_{1}\)_ operation is performed, and, in Step 6, _XOR_ operations are performed on the above result and round key. After that, modular addition is performed between the results of Step 3 and Step 6. In Step 8, _ROL\({}_{8}\)_ operation, the last operation of odd round, is performed, and, in 16-bit parallel processing, rotate shift operation can be efficiently processed with only _REV_16 instruction. Steps 9-10 increase counter value because one round is over. From Step 11, it means even round, and the counter value and one word of the plaintext perform _XOR_ operation again. Step 12 performs _ROL\({}_{8}\)_ operation, and Step 13 performs _XOR_ operation on the round key and result of Step 12. After that, step 14 performs a modular addition by 216 between the resulting values from steps 11 and 13. In Steps 15-16, an even round is completed through _ROL\({}_{1}\)_ operation. Finally, Steps 17-18 add 1 to the counter value. The encryption process of revised CHAM-64/128 is completed by repeating the above process 44 times, when the ciphertexts are stored in the memory, by automatically applying the transpose operation through the _ST4_ instruction. We achieve the processing of more encryptions simultaneously than previous work [10] through efficient vector register scheduling.