# Parasitic-Based Active Gate Driver Improving the Turn-On Process of 1.7 kV SiC Power MOSFET
## 2 The Active Gate Driver
#### Gate Voltage Manipulation for the Turn-On Cycle Improvement
\(t_{2}\) is the moment when the drain-source voltage \(v_{\text{DS}}\) is starting to decrease and when the \(i_{\text{D}}\) has reached its maximum value, which is sensed based on \(V_{\text{Ls}}\) changes from positive to negative values as the drain current overshoot occurs. The \(V_{\text{GG}}\) voltage is switched again to 30 V, which increases the \(dv_{\text{DS}}/dt\) ratio and reduces the period between \(t_{2}\) and \(t_{3}\) which in fact decreases the turn-on power losses in the device and its switching period. Notice that \(t_{2}\) occurs when the drain current has reached its maximum value. In order to suppress further negative effects of \(i_{\text{D}}\) overshoot, the gate current is increased through modification of the value of \(V_{\text{GG}}\) to 30 V. To prevent damaging the gate of the device, \(V_{\text{GG}}\) is again set to 15 V at \(t_{3}\). Finally, at \(t_{4}\), the gate-source voltage \(v_{\text{GS}}\) reaches 15 V, equal to \(V_{\text{GG}}\). The feedback loop of the studied device is based on sensing the two from moments in the turn-on cycle occurring at \(t_{1}\) and \(t_{2}\), based on the \(V_{\text{Ls}}\) measurements and thus responding with changes in the \(V_{\text{GG}}\) values appropriately, as depicted in Figure 2.  
The multi-level gate voltage method impact can be theoretically explained using Equations (2)-(6) based on fundamental knowledge [20]. From Equation (2), it can be concluded that the higher the voltage \(V_{\text{GG}}\) and the lower the resistance \(R_{\text{G}}\), the greater the gate current \(i_{\text{G}}\). However, the maximum \(V_{\text{GG}}\) should be taken into consideration. \[i_{\text{G}}(t)=\frac{V_{\text{GG}}-v_{\text{GS}}\left(t\right)}{R_{\text{G}}} \tag{2}\]  
In the proposed method, \(R_{\text{G}}\) is fixed so the gate current is only dependent on the difference between \(V_{\text{GG}}\) and \(v_{\text{GS}}\). The instantaneous gate-source voltage \(v_{\text{GS}}\) in the switching transient (3) also mainly depends on the \(V_{\text{GG}}\), \(C_{\text{GD}}\) and \(C_{\text{GS}}\) values. In the proposed method, the \(V_{\text{GG}}\) voltage is set to 30 V from \(t_{0}\) to \(t_{1}\) to minimize the delay time between the \(DS\) signal and the \(t_{1}\) moment where the \(v_{\text{GS}}\) crosses the threshold value and the drain current starts to rise. \[v_{\text{GS}}(t)=V_{\text{GG}}\bigg{(}1-e^{\frac{t-t_{0}}{2}}\bigg{)},\,\tau= R_{\text{G}}(C_{\text{GS}}+C_{\text{GD}}) \tag{3}\]  
Delay time between \(t_{0}\) when \(v_{\text{GS}}\) starts to rise and \(t_{1}\) when the MOSFET starts to conduct the drain current that is mainly dependent on the \(V_{\text{GG}}\) voltage and constant values of the device, as shown in Equation (4). To compensate the delay between the rising edge of the \(DS\) signal at \(t_{0}\) and \(t_{1}\) in \(\Delta t_{10}\), \(V_{\text{GG}}\) is set to 30 V.  
\[\Delta t_{10}=t_{1}-t_{0}=-\tau Ln\bigg{(}1-\frac{V_{\text{Th}}}{V_{\text{GG} }}\bigg{)} \tag{4}\]  
Another Equation (5) represents the rise time of the drain current from time \(t_{1}\) to \(t_{2}\), where \(I_{0}\) is the drain current in the steady state after the turn-on cycle (see Figure 2), \(g_{\text{m}}\) is the transconductance and \(V_{\text{Th}}\) is the threshold voltage at the turn-on cycle. A low value of \(\Delta t_{21}\) leads to a high \(di_{\text{D}}/dt\) ratio and, in consequence, current overshoot caused by the Schottky body diode (SBD) and the parasitic elements of the device. Thus, it is the reason for the \(V_{\text{GG}}\) voltage depletion in t\({}_{1}\) from 30 to 15 V.  
\[\Delta t_{21}=t_{2}-t_{1}=\tau Ln\frac{g_{\text{m}}V_{\text{GG}}}{g_{\text{m} }(V_{\text{GG}}-V_{\text{Th}})-I_{0}} \tag{5}\]  
The time of the drain-source voltage falling in the turn-on cycle can be presented by Equation (6), where \(V_{\text{DD}}\) is the drain-source voltage in the time before \(t_{0}\) and \(r_{\text{DS(ON)}}\) is the drain-source resistance of the SiC MOSFET.