# Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection
## 6 Clock and Data Recovery (CDR) Circuits
### CDR Examples
In [44], the fabrication of an optical TX in \(0.13\)-\(\upmu\)m technology is also provided, and the overall power consumption of the transmitter and the receiver is \(1.25\) W per channel. In [77; 124], a National Taiwan University group achieved a data rate of \(25\) Gb/s per channel using a similar structure. In order to overcome the limited speed of the conventional linear phase detector in [44], the studies in [77; 124] replaced the conventional linear phase detector with a mixer-based phase detector. While fabricated in \(65\)-nm CMOS technology, the front-end circuit and the CDR circuit dissipate \(40\) mW and \(100\) mW, respectively, at \(25\) Gb/s per channel. The subsequent CDR example to be introduced was [93] presented by a Stanford group in 2008. The work in [93] adopted an integration-based front-end presented in [125], as shown in Figure 44. Unlike the sequential locking CDR presented in [44], the work in [93] adopted a dual-loop CDR  
Figure 43: Sequential locking CDR presented in [29]. architecture where the phase alignment and frequency acquisition loops operate simultaneously. In this type of CDR, the loop bandwidth of a loop should be set an order of magnitude lower than that of the other loop, in order to prevent the interference between the loops [119; 126]. In [93], the loop bandwidth of the phase alignment loop was designed to be lower than that of the frequency loop to suppress the jitter transfer caused by the input data. Contrary to the sequential locking CDR, the VCO is not shared between the loops. An additional phase adjusting circuit based on a phase interpolator (PI) is used in the phase alignment loop. It cannot generate a clock but can change the phase of the input clock provided by the VCO according to the relative phase information extracted from the non-linear phase detector. The phase-adjusted clock is fed back into the VCO through a phase-frequency detector (PFD) so that the output phase of the VCO is eventually aligned with the data. Fabricated in 90-nm CMOS technology, the integration-based front-end and the CDR circuit consume 23 mW and 35 mW, respectively, and achieve receiver sensitivity of \(-5.4\) dBm at a data rate of 16 Gb/s. As CMOS technology scales down, many non-idealities appear in analog circuit components because the scaling mainly focuses on digital circuit elements. In order to overcome the various performance degradations introduced by the analog loop filters in previous CDR examples in [44; 77; 93; 124], a recently developed all-digital CDR technology, which replaces the analog loop filter with a digitally synthesized logic, was adopted in an optical receiver by the authors' group in [89]. In deep-submicron CMOS technology, a leakage current flowing through a MOS capacitor becomes no longer negligible due to the direct tunneling across the gate oxide [127]. Therefore, a considerable amount of current flows through the loop filter capacitor, leading to a static phase error and a deterministic jitter [128; 129; 130; 131]. Moreover, the performance of charge-pumps is degraded owing to the reduced voltage headroom and reduced output impedance of the CMOS devices, which also results in static phase error and jitter. In order to eliminate the analog components, the VCO and analog loop filter are replaced by a digitally-controlled oscillator (DCO) and a synthesized digital logic, respectively, in [89]. While the input analog voltage of a VCO adjusts the output clock frequency, the DCO frequency is determined by a multi-bit digital code. The digital code is achieved by processing the sampled data and reference clock using a digital loop filter. On the other hand, the main drawback of this all-digital approach is the long loop latency, which introduces a phase dithering and loop stability issue. Because of the relatively low operating speed of digital logic, a frequency-divided DCO clock is used for operating the digital filter.