# FPGA Implementation of a Deep Learning Acceleration Core Architecture for Image Target Detection
## 2 Proposed Method
### Computational Scheduling Kernel Pipeline Design  
#### 2.2.1 Convolutional Layer, Pooling, Fully Connected Layer Pipelining Methods  
This paper uses High-Level Synthesis Tool (HLS) pipeline and unroll methods to constrain the loops within the scheduling kernel, the software code is synthesized into pipelined hardware logic to improve computational efficiency. As shown in Figure 8, the pipelined approach shortens the initial interval of hardware execution so that a common computational logic between loops can implement different computational steps within a loop. An unpipelined HLS logic has an initial interval equal to the number of clocks, which takes three clocks to execute a round of computation. The second loop starts three clocks from the start of the first loop, so the initial interval is 3. The total time taken to complete the function is reduced from 9 clocks to 5 clocks, resulting in a significant increase in computational efficiency. The HLS unroll constraint allows operations within a loop to be executed separately so that operations with different loop counts can be performed simultaneously. Unroll requires the HLS to instantiate a finite number of hardware logic units for computation, the upper bound of the loop to be parallelized must be fixed and known at the time of synthesis. Therefore, in this paper, the number of parallelisms is set to a constant for each of the three levels of parallelism, input channel parallelism, output channel parallelism, and pixel parallelism, so that the HLS can perform the computation correctly in parallel. Compared to pipelining, parallelization takes less time but consumes three times more resources and requires no logical dependencies between loops. For example, if the second loop needs to use the result of the first loop, only pipelined logic can be used, not parallelized logic. All loops within the pipeline bound loop are parallelized, using parallel logic to implement the computation within the loop. In order to improve the overall efficiency of the acceleration core, the convolutional, pooling, and fully connected layers are all designed with independent pipelines at an initial interval of 1 to maximize the use of parallel computation units and data throughput bandwidth. The loop logic of the convolutional layer is the most complex of the three computations, and its loop nesting is shown in Algorithm 1. ```
1:for each \(input\_row\_iter\in[0,INPUT\_ROW\_ROUND]\)do
2:// loop level 1
3:// the traversal of the number of rows of the input tensor
4:for each \(input\_col\_iter\in[0,INPUT\_COL\_ROUND]\)do
5:// loop level 2
6:// the traversal of the number of columns of the input tensor
7:for each \(ocp\_round\in[0,OCp\_ROUND]\)do
8:// loop level 3
9:// the traversal of the number of the output channels
10:for each \(iter\_row\in[0,KERNEL\_WH]\)do
11:// loop level 4
12:// the traversal of the convolution kernel tensor rows
13:for each \(iter\_col\in[0,KERNEL\_WH]\)do
14:// loop level 5
15:// the traversal of the convolution kernel tensor columns
16:for each \(icp\_round\in[0,ICP\_ROUND]\)do
17:// loop level 6
18:// the traversal of the convolution kernel input channels
19:#pragma HLS pipeline
20:for each \(iter\_pp\in[0,PP]\)do
21:// loop level 7
22:// loops of pixel parallelism
23:for each \(iter\_ocp\in[0,OCp]\)do
24:// loop level 8
25:// loops of output channel parallelism
26:for each \(iter\_icp\in[0,ICP]\)do
27:// loop level 9
28:// loops of input channel parallelism
29:endfor
30:endfor
31:endfor
32:endfor
33:endfor
34:endfor
35:endfor
36:endfor
37:endfor

Figure 8: Top: pipeline constraint effect. Bottom: unroll constraint effect. Loop level 1 represents the traversal of the number of rows of the input tensor. Loop level 2 represents the traversal of the number of columns of the input tensor. For example, suppose the number of parallel pixels is 4. In that case, the loop level means that after each round of convolution, the pointer is shifted 4 pixels to the right until the traversal of a row is completed.