## 2 Materials and Methods  
### SALT Architecture Overview  
The block diagram of SALT is shown in Figure 1. The ASIC was designed in CMOS 130 nm technology offering good radiation resistance and low power consumption at sufficient speed. The SALT extracts, shapes and digitises analogue signals from the sensor, performs Digital Signal Processing (DSP), and transmits serially the output data. It uses an innovative architecture comprising an analogue front-end with fast and symmetrical shaping and a 40 MSPs 6-bit ADC in each channel.  
To synchronise the ADC sampling time to that of the \(pp\) collisions, a dedicated ultra-low power (0.7 mW @ 40 MHz) Delay-Locked Loop (DLL) circuit is used to shift and align an external clock. The digital ADC output is processed by the DSP block, which performs pedestal subtraction, Mean Common Mode (MCM) subtraction, and a Zero Suppression (ZS). Subsequently, the data packets are created and recorded in a local on-chip memory, which serves as a derandomising buffer. The data is then serialised via a number of data links called e-links [13]. The actual number of active e-links is between 3 and 5, and is set based upon utilising expected fraction of the output bandwidth while avoiding permanent memory overflow. In the UT detector, the number of active e-links is static for a particular chip and is established according to the expected data rate.  
The SALT is controlled via the LHCb common protocol consisting of two interfaces: the Timing and Fast Control (TFC) and the Experiment Control System (ECS) [14]. The TFC interface delivers fast commands synchronised with the 40 MHz experiment clock (a byte including 0-8 commands every clock cycle), while the ECS serves to configure and monitor the ASIC. The former is realised through an input e-link and the latter by an Inter-Integrated Circuit (I\({}^{2}\)C) interface.  
The SALT is a System-on-Chip (SoC) type ASIC. In addition to the previously mentioned blocks and functionalities, it encompasses: reference voltage generators in each analogue front-end channel, several 5-8 bit Digital-to-Analog Converters (DACs) to set biasing in different analogue blocks, several 6-bit monitoring ADCs for selected circuitry such as DACs, DLL or Phase-Locked Loop (PLL). The last functionality is also important for monitoring the ASIC performance over time, which is especially important in the high radiation environment. Moreover, various techniques were used to make the ASIC re  
Figure 1: The SALT ASIC block diagram.  
sistant against radiation induced effects like Total Ionizing Dose (TID) and Single Event Effects (SEEs) [15].  
The design presented below reflects the third SALT prototype. Previous prototypes exhibited a large 40 MHz disturbance at the output when the front-end was connected to an input capacitance of several picofarads, and the disturbance increased with the input capacitance value. The deterioration occurred after the transition from an 8-channel to a 128-channel chip, since no such disturbance was observed for the 8-channel ASIC prototype [16]. A number of modifications regarding the power distribution, analogue blocks and layout were been made to eliminate this effect, and are not discussed in detail here.