# A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures
## 5 Pseudo-Random Pattern Generator DT-LFSR-TPG for LBIST Circuits with the STUMPS Architecture
To meet the foregoing requirement, each single-DT-LFSR register incorporated into the DT-LFSR-TPG structure of the TPG must start its operation from a different seeding vector (i.e., from a different initial state). Let us assume that the seeding content \(S_{1}\) of the DT-LFSR1 register is adopted as the reference point and let us also assume that such a seeding content appears in the sequence of vectors produced at outputs of the foregoing register in the clock cycle No. 0. Therefore, the seeding content \(S_{i}\) of any  
Figure 12: LBIST module with STUMPS architecture that uses a set of DT-LFSR registers as a generator of pseudo-random test patterns. DT-LFSR\(i\) register should be included in the initial sequence in clock cycle \(d_{i}\), where \(d_{i}\) can be expressed by means of the following formula:  
\[d_{i}=(i-1)\times\Theta_{min},i=2,3,\ldots,Z \tag{7}\]  
If so, binary sequences produced at the \(r\)th outputs of the DT-LFSR1 and DT-LFSR\(i\) registers, where \(r=0,1,\ldots,n-1\), shall be mutually shifted with the phase shift of \(d_{i}\) clock cycles. The maximum number of scan paths \(m_{max}\) that can be wired to outputs of a TPG with the specific minimum limits for \(\Theta_{min}\) and \(\Phi_{Tmin}\) shall be defined by Equation (8). \[m_{max}=\frac{\Phi_{Tmin}}{\Theta_{min}} \tag{8}\]  
The maximum numbers \(m_{max}\) calculated from the foregoing equation are summarized in Table 2, where columns 2 and 3 of the table contain parameters of DT-LFSR registers incorporated into the TPG. The number of scan paths for various \(\Theta_{min}\) is provided in columns 4 to 9. The \(\Theta_{min}\) are adequately selected so as to cover the range assumed in [34; 39]. Please note that in cases when the presumed offset \(\Theta_{min}\) is known, Table 2 makes it possible to find out \(n\) and \(t\) parameters of the appropriate DT-LFSR register to enable designing of a TPG that is able to supply test sequences to any number of scan paths, or at least as many as practicable. For comparison, Table 3 summarizes the maximum number of scan paths that were obtained in [34; 39] for similar phase shifts \(\Theta_{min}\) as included in Table 2. The LFSR I and LFSR II symbols in the first column of the table correspond to the test pattern generator of the LFSR + PS type as outlined in [34], where the phase shifter is wired to outputs of LFSR registers of the respective I and II types. In turn, the LHCA 90/150 symbol stands for the generator of the CA + PS type designed to produce pseudo-random tests and including the LHCA 90/150 register and a phase shifter. In addition, Table 3 comprises results for  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**No. **} & \multirow{2}{*}{\(\mathbf{t}\)} & \  
==WARNING: Truncated because of repetitions==  
+++  
input signal M, such a circuit can perform as a D-type flip-flop (for M = 0) or a T-type flip-flop (when M = 1). Variations of parameters for the VHDL model make it possible to set up both the register length and the number of configurable D/T flip-flops included in the register, while the MODE signal shown in Figure 13a is dedicated to controlling the operation mode for the entire DT-LFSR register module. For MODE = 1, the module operates as a DT-LFSR linear shift register, whilst setting the MODE signal to zero switches the module to operation as a shift register, and its initial content can be seeded by feeding a corresponding series of bits to its serial input SI. The module also has a serial output SO, which enables serial sequencing of DT-LFSR registers included in a large DT-LFSR-TPG unit, where the SO output of the \(i\)th register is connected to the SI input of the register with the number \((i+1)\), where \(i=1,\ 2,\ Z-1\), and \(Z\) stands for the total number of DT-LFSR registers included into the test pattern generator. When MODE = 0, all DT-LFSR modules make up a single and long shift register, which makes it possible to seed any initial content of that registers.