## 2 Materials and Methods
### Definition and Design of the System's Components
#### 2.2.3 Internal Interfaces to Connect FPGA/LED Driver and FPGA/PD Driver  
To interconnect the various subsystems, an internal interface design was implemented. This interface serves two purposes: (i) it connects the FPGA with the LED driver, and (ii) it links the PD driver with the FPGA; these connections facilitate both the downlink and uplink, respectively. Purpose (i), the connection of the FPGA with the LED driver, requires an interface in the LiFi router to link the FPGA with the visible LED driver for the downlink. Additionally, at the USB dongle side, the interface connects the FPGA with the IR LED driver for the uplink. Each component that constitutes the FPGA/LED driver interface is detailed in Figure 15 and described further below. Figure 13: (**a**) Set-up of the frequency response of the PD driver implemented with three amplifier stages using the LUW-CN7N-KYLX-EMKM OSRAM LED; (**b**) frequency response of the PD driver implemented with three amplifier stages using the LUW-CN7N-KYLX-EMKM OSRAM LED. The digital-to-analog converter (DAC) has 10 parallel data input bits connected to the output of the FPGA data bus, as illustrated in Figure 15. The DAC clock frequency is determined by the sampling frequency. We assigned a sampling frequency of 40 MHz to the DAC clock. This value was selected based on the achieved bandwidth (\(BW\)) of 10 MHz for each optical channel. As such, it fulfils the Nyquist criteria, which mandates the converter's sampling frequency (\(f_{sampling}\)) to be at least double the signal bandwidth, as outlined in Equation (5):  
\[f_{sampling}\ \geq\ 2\cdot(BW) \tag{5}\]  
An amplifier is employed to convert the differential output of the DAC into a single-ended output, with a gain of 2 \(\frac{V}{V}\). The amplifier's GBW product amounts to 350 MHz. Finally, a low-pass filter is utilized to eliminate unwanted frequency components, with a cut-off frequency set at 30 MHz. For purpose (ii), which entails connecting the PD driver to the FPGA, the interface is implemented akin to the first configuration. This interface is required in the USB dongle to interlink the PD driver and the FPGA for the downlink. Furthermore, it is necessary in the LiFi router to connect the PD driver and the FPGA for the uplink. Each constituent block of the PD driver /FPGA interface is depicted in Figure 16 and described further below. Figure 16: Block diagram of the PD driver /FPGA interface. Figure 14: Frequency response of the PD driver implemented with three amplifier stages using the IR HSDL-4250 LED. Figure 15: Block diagram of the FPGA/LED driver interface. An amplifier is used to convert the single-ended signal from the PD driver into a differential signal, which is then connected to the reference inputs of the analog-to-digital converter (ADC). The amplifier has a gain of 2, and the GBW product is 350 MHz. A low-pass filter is implemented to eliminate frequency components outside the BW of interest, with the cut-off frequency set at 30 MHz. Considering that the system encompasses both downlink and uplink channels, the same interface design was replicated for each side of the visible and IR optical links. Interface Module for FPGA/LED Driver Connection  
In order to connect the FPGA pinouts with the LED driver, a digital-to-analog conversion was necessary because the LED is modulated using an analog signal [20]. For this task, the MAX5184 DAC was selected due to its 10-bit resolution and ability to handle clock signals up to 40 MHz. This DAC was manufactured by Analog Devices and bought on [[https://mouser.com/](https://mouser.com/)]([https://mouser.com/](https://mouser.com/)) (accessed on 5 September 2024). This converter features two differential outputs, each with an amplitude of 400 mV\({}_{\text{pp}}\)[34]. These outputs were then combined into a single-ended signal using the MAX4105 high-speed operational amplifier [35].