## 6 Possibilities of Paradigm Shifts in Computer Design and Methodologies
### Wafer Testing Made-Easy  
Manufacturing testing is one of the most expensive and time-consuming steps in IC and system integration. After manufacturing, the wafers first go through the wafer testing to check functional defects by applying the special test vectors. Wafer-level testing presents huge challenges to high fault-coverage due to severely restricted controllability and observability, especially for complex Systems-on-Chips (SoCs) or multicore processors. After wafer testing, pre-packaged chips are cut and tested, packaged, and retested to undergo packaging test to check if the package induced defects. Finally, the packaged dies that pass the packaging test are then assembled onto a substrate such as a PCB board to make the final product, and the product level testing is done to check the interconnections and the assembly process. As a result, it is very important to catch defects at the early stages of the life cycle of a chip to save cost and ensure quality. This wafer-testing is an important but a very challenging step due to lack of controllability and observability of an uncut die. Hence, traditionally wafer-level testing is restricted to basic tests using probes. The probe needles come in physical contact with the wafer and can cause damage to the wafer due to the stress applied by the probes and it can also affect the packaging, assembly, and long-term reliability. Further probe needles require frequent  
Figure 17: Comparative distance and access latency for hierarchical memory architecture.  
cleaning as they can accumulate debris on them and that causes contamination of needles which can lead to increase in contact resistance. The idea of reusing the NoC infrastructure as the Test Access Mechanism (TAM) for multicore SoCs to eliminate additional hardware overhead is proposed in [92]. Contact-less wafer testing has been proposed using capacitive coupling-based interconnects [93]. However, capacitive or inductive coupling requires close proximity of the test-bed to that of the chip and due to the footprint of on-die capacitors or inductors are not capable of providing sufficiently low-latency TAMs to deliver high volume test data for achieving high fault coverage. On-chip wireless transceivers can receive test data from an external equipment such as an Automatic Test Equipment (ATE) which will also be equipped with a wireless transceiver to send and receive test data and response respectively. This wireless TAM architecture is shown in Figure 18. Depending on the speed of the chosen physical layer and MAC efficiency, test data can be delivered at high rates to uncut dies in the wafer without requiring physical contact. The controllability and observability can be improved to the desired degree by deploying the wireless transceivers to receive and transmit test data at the required granularity or density.  
The same wireless transceivers can also be used as part of the TAM [94] for testing of cut and packaged dies as well. On-chip wireless interconnects have been envisioned and investigated for several years now. This on-chip wireless interconnect can be used to communicate with an ATE equipped with a transceiver operating at the same frequency and uses a MAC integrated with the other wireless nodes in the chip. Therefore, inter-chip wireless interconnect can be used for testing cut and packaged dies as well, to provide a low-latency and energy-efficient TAM.