# Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers
## 3 Related Works  
In this section, we give the description related to parallel implementation of the NEON engine and CTR mode optimization. ARMv7 architecture, in addition to the ARM core, supports the NEON engine that can effectively process data in parallel. In the NEON engine, parallel processing is possible to 64, 32, 16, and 8-bit wise depending on the lane within the 128-bit vector register. Until now, works on parallel optimization of various block ciphers utilizing the NEON engine in ARMv7 and ARMv8 architecture have been conducted [9; 10; 18; 19; 20]. Table 4 shows the number of simultaneously performed encryptions utilizing the NEON engine in related works. In WISA'16 [18], taking advantage of the independent cores of ARM and NEON, the authors proposed an optimized technique to efficiently hide cycles of ARM instructions into cycles of NEON instructions by interleaving NEON and ARM instructions. In the NEON engine, 12 encryptions were simultaneously performed using 16 vector registers, and one encryption was efficiently performed utilizing a barrel shifter in ARM core. For parallel implementation on the NEON engine, the authors presented the overall process for parallel processing in NEON engine as follows:  
\[\textit{Load}\longrightarrow\textit{Transpose}\longrightarrow\textit{ Encryption}\longrightarrow\textit{Transpose}\longrightarrow\textit{Store}\]  
It could be seen that the transpose operation was required for parallel processing in the NEON engine. Furthermore, utilizing OpenMP, the authors expanded the proposed one core optimization into four cores so that a total of 52 encryptions were performed, simultaneously. In WISA'18 [19], the authors presented the results of applying the above optimization method to CHAM-64/128. With taking advantage of the property that CHAM-64/128 is a 16-bit word-wise, in the proposed method, 24 encryptions were processed simultaneously in the NEON engine and four encryptions were processed simultaneously in the ARM core. In the NEON parallel process, the transpose operation was required as in the above method. Furthermore, the authors interleaved ARM instructions and NEON instructions in CHAM-64/128 as in the above optimization method, and optimized CHAM-64/128 by using multiple cores through OpenMP. Recently, various research results are introduced for ARMv8 architecture, the latest version of ARM core. Unlike ARMv7, ARMv8 architecture supports 32 128-bit vector registers instead of 16 128-bit vector registers. In journal of the Korea Institute of Information and Communication Engineering'17 [9], the author presented an efficient parallel implementation of LEA utilizing NEON engine in ARMv8 architecture for the first time. In the proposed data parallelism, 24 encryptions were simultaneously processed, but the transpose operation was required for data parallelism in the same way as the above optimization method. In ICISC'19 [20], the authors optimized AES using the ASIMD instruction set on ARMv8 architecture. the 4-way transpose MixColumns was introduced to efficiently process MixColumns on four encryptions. Through the 4-way MixColumns, the authors achieved improved performance in MixColumns. In IEEE ACCESS'20 [10], the authors \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Methods** & **Target Device** & **Target Block Cipher** & **\#Data Parallelism** \\ \hline [PERSON] et al. [18] & Cortex-A9 (ARMv7) & LEA & 12 \\ \hline [PERSON] et al. [19] & Cortex-A53 (ARMv8) & CHAM-64/128 & 24 \\ \hline [PERSON] [9] & Apple A7 and Apple A9 (ARMv8) & LEA & 24 \\ \hline [PERSON]. [PERSON] et al. [20] & Cortex-A53 (ARMv8) & AES & 4 \\ \hline  & & HIGHT & 24 \\ [PERSON] et al. [10] & Cortex-A72 (ARMv8) & Revised CHAM-64/128 & 16 \\  & & Revised CHAM-128/128 & 10 \\  & & Revised CHAM-128/256 & 8 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Previous block cipher implementations using NEON engine (#Data parallelism: the number of encryptions performed simultaneously on NEON engine).