## 6 Comparison to Other Designs  
As mentioned in the introduction of this paper, analog-based PUF designs benefit from relatively simple circuit designs, which make them suitable for the integration into IoT devices that are mostly bound to hard requirements such as being small-sized, low-cost and having limited resources. Various analog-based PUF designs have been reported earlier by other working groups [22; 23; 24; 25; 26]. In the following, we provide a closer look at other analog-based PUFs, similar to our system. The TV-PUF [23] uses two parallel blocks with cascaded pass-transistors. Cascading helps to accumulate the impact of \(V_{th}\) variation per pass-transistor, which is subtracted from \(V_{DD}\) over the amount of pass-transistor stages. A static voltage sense comparator is used to compare the voltage levels between the two activated blocks' output voltages and to generate a bit. The design is simulated and verified using 45 nm, 65 nm, and 90 nm technology processes. The TG-PUF [24] utilizes a stimulus/measurement circuit (STM) which consists of 20 'pseudo' pass gates, referred to as transmission gate (TG) [24]. An output voltage is generated, caused by a voltage drop over a TG, due to the devices' on resistance \((R_{on})\), which is addressed by a selection circuitry. Furthermore, a voltage-to-digital converter (VDC) is used to sense the generated output voltages. The design generates voltage differences which are utilized to generate bit-strings. Thresholding techniques are proposed and applied to generate stable bit responses. The design is fabricated and verified using a 90 nm technology process. The VTC-PUF [25] exploits staging of circuit blocks over 64 switches. The VTC circuit block consists of an inverter and a feedback transistor, which prevents the inverter output to swing either to the circuits \(V_{DD}\) or ground. The design uses two blocks as a pair. The switches act as a challenge and route the output of the blocks to the according next stage inputs. A voltage sense amplifier, attached to the last block, is used to compare the staged output voltage differences and generates a bit. This design is more robust against several ML algorithms in comparison to delay-based PUF architectures such as Arbiter PUFs, due to the cascading of nonlinear inverter characteristics. The design is simulated and verified using a 45 nm technology process. Table 2 shows the reliability, uniqueness, and uniformity metrics for related PUFs and the proposed PUF platform (bold). One should note that the reliability metric evaluations for the different PUF shown in Table 2 have been carried out under various temperature ranges. The smallest temperature range was used for VTC-PUF, reaching from 0 \({}^{\circ}\)C to 85 \({}^{\circ}\)C. All other works, also including the herein proposed evaluations, additionally applied negative temperatures to their PUF circuits. The direct comparison of the reliability metrics shows that our fabricated PUFs produce highly reproducible responses, even under extreme environmental conditions. In terms of the uniqueness metric, our evaluation results indicate that the PUF responses are unique, which in connection with the superior reliability value qualifies the proposed design for identification purposes. However, the uniformity analysis shows that additional effort has to be spent for pre- and post-processing techniques--as, for instance, additional hash functions and a fuzzy extractor, to make the PUF responses ready for cryptographic applications. Altogether, our proposed design shows statistics in the performance metrics close to the ideal values. Therewith, the PUF platform accomplishes the security-related requirements for PUF designs