## 3 Optical Buffering and TSI with Integrated Delay Lines
### Experimental Setup and Results for Optical Packet Buffering  
A close-up view of the SOI chip utilized is shown in Figure 8a. The chip is fabricated on a 4 um SOI platform and comprises three spiral waveguides, all based on 4 um thick, 1.875 um wide strip waveguides separated by 2 \(\upmu\)m gaps, while the Euler bends have a minimum bending radius of 36.9 \(\upmu\)m allowing an effective bending radius of 69 \(\upmu\)m for a 90\({}^{\circ}\) bend [51]. Despite the relatively narrow gap between adjacent waveguides in the spiral, optical radiative crosstalk in the fundamental mode is negligible, since the high confinement in the \(\upmu\)m -scale waveguide core, renders very small any interaction with the sidewalls. A three-stage design was used to couple light to the strip waveguides ensuring single mode operation. Light was first butt-coupled from a single mode fiber to a 10 \(\upmu\)m wide rib waveguide, that was subsequently tapered down to 3 \(\upmu\)m width. A 350 \(\upmu\)m long rib-to-strip converter was then employed to couple light into the strip waveguides [53]. Three waveguides were utilized with lengths of 0.52 m, 0.94 m and 1.46 m, which correspond to delay values of 6.5 ns, 11.3 ns and 17.2 ns at 1550 nm and are denoted as Delay 1, Delay 2 and Delay 3, respectively. The total insertion loss of the three delay lines was measured 20 dB, 25 dB and 30 dB respectively, while the input-output coupling loss was found to be 12.5 \(\pm\) 0.5 dB and the propagation loss was estimated at 0.12 \(\pm\) 0.01 dB/cm, in close agreement to the propagation loss values reported in [51]. Based on these measurements, the average delay versus loss efficiency is calculated at 0.93 dB/ns, while the delay versus footprint efficiency is found to be 2.6 ns/mm\({}^{2}\) by dividing the 17.2 ns delay to the 4.4 \(\times\) 1.5 mm\({}^{2}\) footprint of the largest waveguide. The experimental setup of the variable optical buffer is illustrated in Figure 8b. It comprises two cascaded WC stages (WC 1 and WC 2), fabricated by former CIPPhotonics, interconnected with an intermediate delay stage. A 1550 nm laser beam is modulated in a Optilab LiNbO\({}_{3}\) modulator, driven by an Anritsu Programmable Pattern Generator (PPG), to produce a periodic signal with a 256-bit period that incorporates three 35-bit-long 10 Gb/s NRZ data packets. Every packet consists of a 31-bit payload and a 4-bit header, while a 12-bit long inter-packet guardband is used between packets (I), (II) and packets (II), (III). The packet stream is split into two identical signals that are injected as push-pull control signals into the D and E ports of WC1. Three laser beams (\(\lambda_{1}\) = 1556.55 nm, \(\lambda_{2}\) = 1558.13 nm, \(\lambda_{3}\) = 1559.75 nm) are fed in separate LiNbO\({}_{3}\) modulators driven by respective PPGs to realize 54-bit-long envelope signals at a 40 MHz frequency, which are multiplexed in an Arrayed Waveguide Grating (AWG) after being properly synchronized and are launched into port G of WC 1 as the WC 1 input signal. The WC 1 output signal is injected into the delay stage, which comprises an Opneti AWG demultiplexer, the integrated delay lines and an AWG multiplexer. Each integrated delay line is preceded by a CIP SOA for SOI waveguide loss compensation purposes, while a CW holding beam (\(\lambda_{4}\) = 1557.7 nm) is used for reducing amplifier-induced noise. The delay stage output is amplified in an Erbium Doped Fiber Amplifier (EDFA) and is then filtered in a 5 nm Optical Band Pass Filter (OBPF) prior being split in two identical versions that are inserted as the two control signals into WC2. The WC2 input signal was provided by a CW 1550 nm laser, after being modulated in a LiNbO\({}_{3}\) modulator driven by a PPG to generate a 50-bit-long optical envelope at a 40 MHz frequency.