## 1 Introduction  
In recent years, due to the rise of the IoT, various types of sensors have been used in a wide range of applications, such as biomedicine, wireless technology, health detection, drones, and industrial transport [1; 2; 3]. In IoT systems, devices need to collect information from sensors, and they require ADCs as part of the receivers in sensor devices. IoT devices are often battery-powered, and it is challenging to change power sources frequently in devices used in healthcare, so these sensor systems need to run for long periods of time with low power consumption. Therefore, ADCs with low power consumption, high dynamic range, and a small area are well suited for these IoT devices. Low-power, medium-precision, small-area, and simple-structure SAR ADCs are the current research hotspots. The power consumption of a digital-to-analog converter's (DAC) capacitor array accounts for a large portion of the total SAR ADC power consumption [4; 5; 6]. For example, the DAC consumption in the study by [4] was 68% of the total SAR ADC power consumption. Therefore, an important way to improve DAC conversion schemes is to reduce the power consumption of SAR ADCs. Many literature studies have proposed switching schemes to improve DAC energy consumption. Compared with the conventional switching scheme, SC [7], MCS [8], RFM [9], VBSS [10], SMS [11], Tri-level [12], and VMS [13] reduce the switching energy by 37.48%, 81.26%, 90.61%, 96.89%, and 97.66%,respectively. In these schemes, MCS [8] and RFM [9], although low in complexity, have a common-mode shift of \(\rm V_{ref}/2\). VPSS [10] and SMS [11] reduce the common-mode shift while lowering the required switching energy, but with high dependence on the accuracy of \(\rm V_{cm}\). Tri-level [12] and VMS [13] are highly energy-efficient, but they have high control logic complexity and tend to increase the digital power consumption of the ADC. Therefore, it is necessary to design a combined energy-efficient switching scheme without increasing the complexity of the control logic while reducing the common-mode shift and decreasing the dependence on the accuracy of \(\rm V_{cm}\). In this paper, a bridged-switch energy-efficient switching scheme for SAR ADCs with a low-complexity capacitor drive circuit is proposed. In the switching scheme proposed in this paper, top-plate sampling [8] and closed-loop charge recycling [14] techniques are adopted so that neither the first nor the second comparison consumes switching energy. For the third comparison, this work utilizes bridging switches to connect the reference voltage-transformed subarrays to the main array, thereby reducing the amount of switching energy generated. Since the LSB depends only on the accuracy of \(\rm V_{cm}\), the switching energy is further reduced. The proposed switching strategy has an average switching energy value of 47.5 \(\rm CV^{2}_{ref}\), which reduces switching energy consumption by 96.52% while reducing the area by 75%. In addition to the DAC capacitor array, the key circuit blocks of the proposed SAR ADC are sampling switches, a comparator, and SAR logic. This work incorporates a gate-voltage bootstrap switching circuit for the sampling switches to mitigate sampling errors [15; 16], while the equipped comparator is a fully dynamic comparator characterized by high-speed performance and low power consumption [17; 18; 19]. Since the SAR logic is the second most power-consuming circuit module in SAR ADCs, dynamic SAR logic circuits based on bit-slice circuits are used to reduce the number of transistors in the SAR logic [20; 21; 22; 23]. The design of a 10-bit SAR ADC is based on the proposed switching scheme. The simulation results show that under the conditions of 1 MS/s and a 1.8 V supply, the ADC achieved 9.8-bit ENOB, 60.76 dB SNDR, and 69.85 dB SFDR. And \(\rm DNL=-0.16/0.14\) LSB; \(\rm INL=-0.25/0.11\) LSB. The overall circuit power consumption of the ADC was 14.7 \(\rm\upmu W\), and the FoM was 16.55 fJ/conv.-step.