# CUDA-Optimized GPU Acceleration of 3 GPP 3D Channel Model Simulations for 5G Network Planning
## 5 Channel Emulator Acceleration on GPU
\begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline \multirow{2}{*}{
\begin{tabular}{c} **Link** \\ **Type** \\ \end{tabular} } & \multirow{2}{*}{**Kernel**} & \multicolumn{8}{c}{**Execution Latency**} \\  & & \multicolumn{8}{c}{**Downlink (\(\mathbf{R_{x}}\times\mathbf{T_{x}}\))**} & \multicolumn{8}{c}{**Uplink (\(\mathbf{T_{x}}\times\mathbf{R_{x}}\))**} \\ \cline{3-10}  & & \(\mathbf{2\times 2}\) & \(\mathbf{4\times 4}\) & \(\mathbf{4\times 8}\) & \(\mathbf{8\times 8}\) & \(\mathbf{8\times 16}\) & \(\mathbf{16\times 16}\) & \(\mathbf{2\times 32}\) & \(\mathbf{4\times 32}\) \\ \hline \multirow{2}{*}{**Downlink**} & calcCIR (\(\mathrm{\SIUnitSymbolMicro}\)) & 6.56 & 11.71 & 8.64 & 10.72 & 11.52 & 25.09 & 8.90 & 9.47 \\  & applyFIR (\(\mathrm{\SIUnitSymbolMicro}\)) & 1.09 & 2.95 & 5.56 & 11.01 & 21.52 & 42.14 & 10.90 & 21.21 \\ \hline \multirow{2}{*}{**Uplink**} & calcCIR (\(\mathrm{\SIUnitSymbolMicro}\)) & 8.03 & 11.58 & 8.74 & 10.94 & 16.54 & 16.06 & 7.74 & 10.85 \\  & applyFIR (\(\mathrm{\SIUnitSymbolMicro}\)) & 1.37 & 2.4 & 4.58 & 9.62 & 21.70 & 33.16 & 12.46 & 22.68 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Kernel latency for a combination of MIMO elements in CDL-D LOS. Figure 7: Execution time on CPU and GPU platforms. once into on-chip buffers (our FPGA has more on-chip memory than our GPU). The DP version consumes more power in both cases due to more data being copied from DRAM and higher execution latency due to both memory access and on-chip computation. The GPU and FPGA power consumption is measured using the respective runtime support. In both cases, they are lower than their respective TDPs because only one-third of the on-chip compute resources were utilized due to memory bandwidth constraints, as shown in Table 5.

Table 5 reports resource usage for the acceleration platforms. For the FPGA, only one of the three chiplets (also called SLRs) in the package was used to achieve a good clock period. _Coding Style: CUDA vs. HLS_

Although both FPGA and GPU provide parallel computation, writing source code to efficiently program them is very different. In the case of GPU, it is necessary to explicitly exploit the multi-threaded nature of the platform by exploiting the three-dimensional parallel loop structure of the thread blocks, as shown in Listings 1 and 2 (note the absence of any explicit loop construct). On the other hand, the accelerated code for the FPGA is actually more similar to the CPU version, with only the addition of (1) loops to transfer data from DRAM to on-chip memory, and (2) loop pipelining, loop unrolling, and array partitioning directives to expose parallelism in the computation and memory architecture in a form appropriate for HLS. ## 7 Conclusions

In this paper, we have presented an efficient implementation of a 3 GPP 3D channel simulation model for GPU platforms, using various CUDA optimization techniques to exploit the parallelism and memory hierarchy of the GPU. The channel model is highly parameterized and can simulate a wide range of configurations required for real-world optimized 5G network deployments. The proposed GPU accelerator can provide fast and accurate channel simulations for 5G NR network planning and optimization, reducing the simulation time by about 240\(\times\) compared to a CPU-based C++ model. The degree of performance improvement is limited by the amount of on-chip memory, which limits concurrency. The GPU design also has higher single-precision performance than a previous FPGA design, but at the cost of higher power consumption. It is interesting to note that although FPGAs typically have lower floating-point performance than GPUs, in this case, the FPGA has higher performance due to the larger amount of on-chip memory used to store the data and reduce DRAM accesses, thus offsetting the lower computational performance compared to a GPU for this very memory-intensive channel model.