# FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
## 3 FPGA Counters Implementations
### Software-Like Counters
and A.M.; supervision, R.C. and M.C. All authors have read and agreed to the published version of the manuscript. This work was supported by the Polish Ministry of Science and Higher Education funding for statutory activities. The authors declare no conflict of interest. The following abbreviations are used in this manuscript: \begin{tabular}{l l} ALU & Arithmetic-Logic Unit \\ CD & Count Down \\ CE & Clock Enable \\ CPU & Central Processing Unit \\ CR & Current Result (accumulator) \\ CR\_b & Current Result: bit \\ CR\_W & Current Result: Word \\ CU & Count Up \\ CV & counter value \\ FF & Flip-Flop \\ FPGA & Field Programmable Gate Array \\ \end{tabular} 

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