# Efficient Design of Reversible Adder and Multiplier Using Peres Gates
## 6 Functionality Verification  
The functionality of the ripple carry adder (RCA) design using Peres gates was rigorously verified through simulation, encompassing a range of input scenarios. The simulation results confirm the correct operation of the RCA, producing accurate sum bits (S [n:0]) and carry-out (Cout_n) for different input combinations. The results confirm the adherence to the reversible logic principles and the preservation of information throughout the addition process. The simulation results demonstrate that the sum bits (S [n:0]) produced by the RCA accurately reflect the binary addition of the input numbers (A and B) and the carry-in (Cin). Figure 31: Simulation results for 4-bit multiplier for other input combinations. Figure 30: Simulation results for 2-bit multiplier. Figure 29: Simulation result for 2-bit multiplier. Each Peres gate strategically placed in the circuit performs a reversible XOR operation, contributing to the generation of the sum bits. The carry-out (Cout_n) serves as an overflow indicator, revealing whether there is a carry beyond the most significant bit. Simulation results affirm that the circuit correctly calculates Cout_n based on the input numbers and carry-ins, providing crucial information about the completion of the addition operation. The reversibility of the circuit is a fundamental aspect validated during functionality verification. The Peres gates, by design, enable the reconstruction of input states from output states. Simulation results confirm that the RCA and multiplier design exhibits reversibility aligning with the principles of reversible logic. The controlled-NOT (CNOT) operation performed by Peres gates was examined through simulation, ensuring that the NOT operation is selectively applied based on the control bits. The controlled nature of the XOR operations ensures that information is not lost during the addition process. The overall functionality verification provides confidence in the correct operation of the designed RCA and multipliers using Peres gates. The subsequent sections delve into the performance analysis, including considerations of speed, quantum cost, and comparative assessments with traditional non-reversible designs. The 4-bit ripple carry adder shown in Figure 20 is constructed with four full adders where the carry is propagated through all the four full adders connected in series. The 4-bit carry look-ahead shown in Figure 21 consists of four full adders along with the carry propagator and carry generator circuit. The 4-bit carry-save adder shown in Figure 22 is constructed from eight full adders. Both carry look-ahead adders and carry-save adders have more quantum cost and occupy a larger area than ripple carry adders. The 4-bit carry skip or carry bypass adder shown in Figure 23 uses four full adders, one 4-bit AND gate, and a multiplexer, and the quantum cost for this is less than the carry look-ahead adder and carry-save adder. From Figure 33, referring to 1-bit, 4-bit, 8-bit, and 16-bit adder configurations verified using RCViewer+ and ModeSim- Intel FPGA starter Edition 10.5b, we can easily develop the following expressions as given below. * The number of inputs/outputs (n) is calculated as
* N = n*3 +1
* where n-number of bits for the adder (in our case 1, 4, 8, 16,...)
* The number of garbage lines (g) can be calculated as g = 2*n
* The number of constant lines c = n
* The number of gates (Gate count) required for constructing an adder is calculated as GC = 2*n
* The number of two-qubit gates (TQ) is given by TQ = 8*n  
Figure 33: Performance analysis of different adder configurations using Peres gates. * And finally, the quantum cost (QC) is calculated by QC = 8*n  
Hence, by using the above equations, we can easily verify the following further adder configurations, as shown in Figure 34.  
A comparative analysis was conducted between the proposed reversible design and other reversible designs available in the literature. This analysis considered factors such as gate count, energy consumption, and overall circuit complexity.