## 5 Hardware Implementation and Experimental Results
### FIR4 (Carrier Aggregation Filter)  
The block diagram of FIR4 (CA filter) in LTE DFE is sketched in Figure 29. The FIR4 low-pass filter was in the transposed form of the FIR filter and designed in view of coefficient symmetry. Among the coefficient sets with respect to the LTE DFE operating modes, the set with the largest number of coefficients was of size 30 and hence the number of distinct coefficients in the FIR filter hardware was 15. The upper part of Figure 29 multiplies the input signal by the coefficients, yielding _x_-c0, _x_-c1, _x_-c2, _\(\ldots\)_, _x_-c14, 15 signals in total, which were connected to two paths in the opposite order, taking symmetry into account. The lower part of Figure 29 took on the ordinary transposed FIR filter form. What differs from the typical structure is the multiplexer (MUX) on the right part, which determines whether the center coefficient value is applied once or twice to the input signal, depending on the select signal of the MUX. If the select signal is 0, the center coefficient is subject to symmetry as are other coefficients. If the select signal is 1, the center coefficient is only applied once. The output period of FIR4 is the input period of FIR4 multiplied by the decimation factor.  
Figure 28: Digital mixer synthesis results.  
Figure 27: Complex multiplier.  
The critical path with the ASIC in a 180 nm CMOS technology is highlighted in red in Figure 29. There were a 15-bit \(\times\) 22-bit signed multiplier and a 23-bit adder between two flip-flops and this kind of form was identical to all the 15 coefficients, and hence the path with the largest delay reflecting the physical wire delay as well will be the path for coefficient 14 (ce14). In the case of the FIR4-carrier 1, the flip-flop + multiplier + adder overall delay was 0.29 ns + 5.36 ns + 4.77 ns = 10.42 ns and similarly in the case of the FIR4-carrier 2, the overall delay was 0.32 ns + 4.99 ns + 4.39 ns = 9.70 ns. The critical path with the XC6 VLX550T FPGA is highlighted in green in Figure 29. It also consists of a multiplier and an adder. In the case of the FIR4-carrier 1, the critical path delay was the multiplier + adder + route delay, equaling 3.441 ns + 0.890 ns + 1.375 ns = 5.706 ns while in the case of the FIR4-carrier 2, the delay was 3.441 ns + 0.712 ns + 1.699 ns = 5.852 ns.  
FIR4 has a module for carrier 1 and another module for carrier 2 in order to support LTE CA. Similarly to the ASIC synthesis of FIR1, FIR3, and the digital mixer, FIR4 is also successfully synthesized to meet the LTE requirements. The required operating frequency is the same as the FIR3 (Farrow interpolator) output sampling frequency. In the case of the 128/325 interpolation, the FIR3 output period was twice or three times its input period and in the case of the 192/325 interpolation, the FIR3 output period was identical to or twice its input period. Therefore, the harder to meet for the FIR3 output was twice its input period in the case of 128/325 whereas the harder to meet in the case of 192/325 was \(x1\) its input period. For instance, in case 10 (LTE CA 20 MHz + 20 MHz), FIR3 had an input period of 1/156 MHz and ran the 128/325 interpolation, and hence FIR4 should operate with a frequency of at least 78 MHz. This is because FIR4 should operate with twice the FIR3 input period, which equaled 2/156 MHz or 1/78 MHz. FIR4-carrier 1 should meet the required critical path delay of 1/78 MHz = 12.82 ns. Giving a 2 ns or so delay margin, the synthesis results exhibited a critical path delay of 10.42 ns, meeting the requirement at the cost of a small amount of area increase. Similarly for FIR4-carrier 2, the required critical path delay was 12.82 ns, and giving a 2 ns margin, the ASIC synthesis resulted in a 9.70 ns critical path delay, also satisfying the requirement.