## 5 Case Study Settings
#### Systems under Test  
The system consists of several PEs that were linked to each other using different types of interfaces. In this case, communication was delay sensitive, and required prompt re  
Figure 16: Simulations in code composer studio. (**a**) Normal communication (Tx to Rx), (**b**) delay Tx (at the beginning), delay Rx (at the beginning), (**c**) delay Tx (in between), delay Rx (in between), (**d**) delay Tx (both ((**b**),(**c**) cases)), delay Rx (both ((**b**),(**c**) cases)). (**e**) No data received at Rx. (**f**) No data transmitted from Tx. (**g**) Data overriding. (**h**) No synchronization. Figure 17: Injected synchronization bugs. sponses with precisely matched timing of different communication components. Therefore, communication in such a systems needs to happen in an efficient manner, even when resources, such as time, bandwidth and power, are limited. In this case, the SDR-embedded system allowed radio communications and offered reliable connectivity in all forms of severe environmental circumstances. Usually they are intended for the transfer multiple data streams, such as voice, images, video, or any other kind of data between the transceivers. The system under test is a high data rate communication system consisting of heterogeneous components, i.e., micro controller or general purpose processors (GPP), application-specific integrated circuits (ASICs), FPGA, and DSP. Many of these elements either are reconfigurable or programmable during the run time. A digital communication application specifically, and signal processing applications in common require sequential data stream processing, where input from one component is processed and transmitted to another component for more processing. The system also carries CODEC with related analog interfaces for voice-based applications. ASICs are used for analog-to-digital conversion, digital-to-analog conversion, digital up-conversion, and digital down-conversion. On the other hand, the DSP is a microprocessor, of which the architecture was built specifically to support number-crunching for signal processing applications. A microcontroller is used to configure various components in the system and to interface with the control panel. The FPGAs provide the system's glue logic, as well as interfaces with the system's devices. A single shared bus is used by all PEs to communicate with each other and all the combined PEs are referred to as a SoC. In this model, all the components that need to interact with each other directly were connected using dedicated interconnects and they communicated via inter-processor communication. A digital signal processing embedded communication system that interfaces a digital design with the RF end is shown in Figure 18.  
In this study, when inter-processor communication takes place in the system, sometimes data or packets may be lost, i.e., \"breaking-up\" of voice communication, data delay, data overriding, out of synchronization, etc. When we encounter these types of problems in a communication system, conversations alter drastically. The intended pauses in the conversation become longer when transmitted and may be mistaken for end of communication. This can happen when communication transceivers are on the move at high speeds or are in a difficult terrain where the loss of data occurs due interference from the environment. In such situations, data retransmission is required, which decreases the  
Figure 18: Digital signal processing embedded communication system interfaces. throughput of the system. This system has very high-speed synchronous interfaces that suffer from synchronization issues. We have experienced several synchronization bugs between the different serial interfaces mentioned in Table 1. These bugs are not algorithmic or logic errors. They are mostly due to timing and synchronization. This kind of system testing differs from non-real-time system testing, and is also a difficult task.