# A 60 GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers
## 4 Simulation Results  
The validation of the feedback loop was performed by firstly implementing the track-and-hold circuit in TSMC 5 nm technology. During the simulation of the sampler, parasitics were added to the schematics. Principally, they were resistances and capacitances deriving from the post-layout characterization of the technology with the main focus on contact and low metal parasitics, which are critical. While sampling the signal at 60 GS/s, the TH circuit had an output range of 505 mV\({}_{ppd}\) generated through a 6 dB gain at Nyquist, and it consumed 18.5 mA from a 0.93 V voltage supply to drive the 64 TI channels capacitive loads equal to 45 fF. The ADC, the digital part of the PAM-8 RX, and the calibration loop were implemented in Verilog-A to enable co-simulation with the actual circuit. TX, AFE, and the channel were modeled using an \(s\) parameter matrix. We performed a transient simulation of the receiver using a PRBS PAM-8 signal for three different PVT conditions. As shown in Figure 7a, the system adjusted the value of \(v_{corr}\) over time until it settled to the optimal value (around \(128\times 10^{3}\) symbols against the \(1.2\times 10^{6}\) in [12]). By plotting in Figure 8 the histograms of the sampled signals equalized by the FFE at the beginning and the end of the calibration (the three couples of histograms are normalized so that the systems have the same linear gain in both cases), we can easily see an improvement. In particular, the average variance of the eight symbols moved from 34 mV to 27 mV, from 43 mV to 36 mV, and from 27 mV to 19 mV, respectively, for the Typ, SS, and FF corners. Next, the receiver was simulated using an input sinusoid of 252 mV\({}_{ppd}\) at 1 GHz. Figure 7 b depicts the total harmonic distortion of the track and hold output signal with the varying of the \(v_{corr}\). The maximum linearity of over 48.5 dB was obtained for values of \(v_{corr}\) that matched the ones obtained through the transient calibration simulation, meaning that the system can maximize the static linearity. These simulations were also performed to obtain the  
Figure 8: Histograms of the reconstructed signals at the slicer input before and after the linearity calibration for (**a**) Typical, (**b**) SS, and (**c**) FF corner. Figure 7: (**a**) Settling of the \(v_{corr}\) overtime during the calibration of the system and (**b**) the THD of the TH circuit across different values of \(v_{corr}\) for three different PVT conditions, one MC point, and one after a temperature step (the plot stops at \(v_{corr}=0.33\) V due to the linearity saturation (FF) for higher values). plots in Figure 7 for a single Montecarlo (MC) point and after a temperature step. By looking at the MC results, we can see how the system set to a value that maximized the linearity while having lower linearity compared to the ideal case due to mismatches. The temperature tracking was verified by introducing a positive step (60 \({}^{\circ}\)C \(\rightarrow\) 100 \({}^{\circ}\)C) after the \(v_{corr}\) was settled in the Typical 60 \({}^{\circ}\)C condition (green case). The system set to the new value of \(v_{corr}\) that maximized the linearity for 100 \({}^{\circ}\)C, meaning the system tracked the temperature variations, which were slower in real applications and presented less criticality. The sampled PAC simulation of the system with the varying of \(v_{corr}\) was also performed, showing that the frequency response of the system had the same behavior (0.15% bandwidth variation), except for the gain as expected, which showed an 18% variation. In Table 1, the THD of the circuit proposed in this work is compared with the available literature. A fair comparison is illustrated in [14] where a THD of around 50 dB was obtained for a the same input frequency and output dynamic range for a single PVT condition.