## 7 Generalized FSM Architecture  
Unfortunately, there is a condition where the proposed method cannot be applied. For a given FSM, let the set of states include at least a single state \(s_{m}\in S\) for which the following condition is satisfied:  
\[L(s_{m})\geq S_{L}. \tag{35}\]  
Figure 12: Percent summary of results. It is obvious that the state satisfying condition (35) cannot be included in either set \(S^{0}\) or set \(S1\). To obtain partial functions generated during transitions from this state, it is necessary to apply the methods of functional decomposition. Thus, to take into account the presence of such states, it is necessary to introduce a _CoreFD_ based on functional decomposition into the architecture of \(P_{2T}Y\) FSM shown in Figure 5.  
We propose to split the set \(S\) by three disjoint sets (\(S^{0}\), \(S2\), \(S3\)). The set \(S^{0}\subseteq S\) includes states satisfying condition (18). The set \(S3\subseteq S\) includes states satisfying condition (35). The set \(S2\subseteq S\) includes the rest of the states, i.e., \(S2=S/(S^{0}\cup S3)\). The transitions from states \(s_{m}\in S3\) are determined by FSM inputs creating the set \(I3\). To encode these states, it is necessary to create the set of state variables \(ASV3\). This set includes its own unique state variables. Three sets of PBFs are generated by LUTs of _CoreFD_: \(D^{F}\) (IMFs generated during the transitions from states \(s_{m}\in S3\)); \(AV^{F}\) (additional variables encoding the OCs generated during the transitions from states \(s_{m}\in S3\)); and \(AV3\) (unique additional variables encoding the OCs generated during the transitions from states \(s_{m}\in S3\)). Therefore, the following partial SBFs are generated by LUTs of _CoreFD_:  
\[D^{F}=D^{F}(ASV3,I3); \tag{36}\]  
\[AV3=AV3(ASV3,I3); \tag{37}\]  
\[AV^{F}=AV^{F}(ASV3,I3). \tag{38}\]  
We denoted as \(P_{F2T}Y\) the proposed generalized architecture of the LUT-based FSM circuit. Here the letter \"F\" means the presence of the block _CoreFD_. The proposed generalized architecture is shown in Figure 13.  
The generalized architecture (Figure 13) includes three cores of PBFs. _CoreFC_ generates PBFs for states satisfying condition (18). _CoreFD_ generates PBFs for states satisfying condition (35). _CorePC_ generates PBFs for the rest of the states. In the \(P_{F2T}Y\) FSM, _LUTerFA_ generates the full functions represented by the following systems of disjunctions:  
\[D=D(D^{0},D^{1},...,D^{J},D^{F}); \tag{39}\]  
\[AV2=AV2(AV^{0},AV^{1},...,AV^{J},AV^{F}). \tag{40}\]  
Figure 13: Generalized architecture of \(P_{F2T}Y\) Mealy FSM. LUTerOF implements SBF (7). However, now the set AV is represented in the following form: \(AV=AV1\cup AV2\cup AV3\). To encode the states of a \(P_{F2T}Y\) FSM, the set \(ASV_{0}\) is used, where \(ASV_{0}=SV\cup ASV2\cup ASV3\). Therefore, _LUTerASV_ generates the SBF:  
Figure 12:0  
Naturally, the proposed architecture is universal. In this paper, we propose the following method for synthesizing an FSM with a generalized architecture:  
1. Creating an STT of a \(P\) Mealy FSM. 2. Pre-formation of sets \(S^{0}\), \(S2\), and \(S3\). 3. Pre-formation of partition \(\pi_{S2}\) of set \(S2\). 4. Final formation of sets \(S^{0}\) and \(S2\) and partition \(\pi_{S2}\). 5. Creating full state codes \(FC(s_{m})\) for states \(s_{m}\in S\). 6. Encoding of output collections \(O_{d}\subseteq O\) and finding SBF (7). 7. Creating a table of _CoreFC_ and deriving SBFs (19)-(21). 8. Encoding of states \(s_{m}\in S^{j}\) by partial state codes \(PC(s_{m})\). 9. Generating tables describing the blocks of _CorePC_ and deriving systems (22) and (23). 10. Encoding of states \(s_{m}\in S3\) by partial state codes \(PC(s_{m})\). 11. Generating tables describing the blocks of _CoreFD_ and deriving systems (36)-(38). 12. Creating a table of _LUTerFA_ and SBFs (39) and (40). 13. Creating a table of _LUTerASV_ and system (41). 14. Implementing a \(P_{F2T}Y\) Mealy FSM circuit using internal resources of a particular FPGA chip.