# Lateral Capacitance-Voltage Method of NanoMOSFET for Detecting the Hot Carrier Injection
## 3 Simulation Methodology  
The effects of electrical stresses depend on the value and polarity of the applied voltage and the duration of the stress time. These effects result in trapping of the charge in the oxide layer or/and at the interface. The expansion of this charge occurs mainly along the channel, while along the width of the channel the trapped charge is distributed homogeneously. Therefore, the effects of electrical stress are primarily a 2D problem rather than a 3D problem. In 2D simulation, the width of the device suitable for the third dimension in commercial software tools/programs, as well as in the TCAD Sentaurus used in this work, is usually 1 \(\upmu\)m. Further, in many papers that take into account the effects of electrical stresses, the different values of the widths are in a range that includes the value 1 \(\upmu\)m (e.g., 0.47 \(\upmu\)m and 0.87 \(\upmu\)m in [27], 0.81 \(\upmu\)m in [25], 10 \(\upmu\)m in [30]). Let us mention, however, that the dependence on the width is beyond the scope of this work. In addition, the 2D simulation takes less time. This is why we favored 2D simulation in our research. Two-dimensional simulations were carried out based on the Advanced TCAD Sentaurus program package. Two simulation methods were used in this work. The drift-diffusion model with allowance for the dependence of mobility on the doping, the saturation of the carrier velocity at high fields, and the influence of normal field component on the drain current was used for simulating threshold voltage dependence on a trapped charge area. The small signal AC analysis method was used for simulating C-V dependences of the side source-substrate and drain-substrate junctions. The frequency of the AC signal was selected as 1 MHz. The gate length of the simulated MOSFET 100 nm and the gate oxide thickness 3.7 nm were chosen from the range in which the main electrical stresses have so far been considered in the literature [25; 27; 30]. The doping level of the p-Si substrate (base) was \(5\times 10^{15}\) cm\({}^{-3}\). Our analysis consists of embedding a local positive charge with different linear sizes (d) along the channel into the gate oxide and defining its influence on the capacitance of the lateral drain-substrate and source-substrate junctions. At hot carrier injection (hypothesis at stake in this work), the oxide-trapped charge is concentrated at the drain end and is afterwards extended in the direction to the source region as the stress time increases. Therefore, the linear size of the charged area corresponds to the length of the charge distribution from the drain region along the channel towards the source region. The charge trapped in the gate oxide layer was modeled by a homogeneously charged area. In fact, the density of oxide-trapped charge induced by electrical stress has some distribution along the channel, depending on the stress condition [30; 31]. As our main objective is to check a law expressing the dependence of the capacitance of the lateral junctions on the linear size of the trapped charge, we considered (as assumption) the area charged homogeneously with an average density of trapped charge. Indirectly, to estimate how this assumption influences the results, we considered the dependence of the change in threshold voltage on the linear size of the homogeneously charged area (see Section 3). The results obtained were in good qualitative agreement with the experimental results in [30]. An evaluation/estimation and a quantitative comparison of the capacitance changes obtained from simulations and experiments were carried out. It can be seen (through simulation) that the maximum relative changes in the capacitance of the lateral drain-substrate were about 6%. Under certain conditions for introducing a charge into the oxide, this value was in the range of variation of the lateral capacitance carried out in experiments (see Figure 2 in [28] and Figure 1 in [29]).