# Electrical Coupling of Monolithic 3D Inverters (M3 INVs): MOSFET and Junctionless FET
## 1 Introduction  
Since metal-oxide-semiconductor field-effect transistors (MOSFETs) were developed, the performance of semiconductor integrated circuits has been steadily developed in accordance with Moore's Law [1]. Semiconductor devices with the gate length of less than 10 nm, which are core technologies required for the 4 th industrial revolution such as artificial intelligence (AI), internet of thing (IOT), cloud computing, big data, and virtual reality [2], have been developing. As the process technology advances by scaling-down, the physical limitations of silicon-based semiconductor processes and the increased integration have led to the problems in thermal budget, delay, and power consumption [3]. In order to solve such problems, various types of researches related on developments of semiconductor materials, process technology, and devices have been actively carried out [4]. The monolithic 3-dimensional (3D) integrated-circuit (M3 IC), which vertically stacks each tier on a previously fabricated tier, is one of the promising techniques to break the physical limits [5; 6]. This technology is more advantageous in density, delay, and cost because of the smaller length of the Via than the existing parallel integration which makes devices on each wafer and connects them with through-silicon via (TSV) between wafers [7]. This is one of the main problems with M3 IC which has the reduction the thermal budget of the MOSFETs in the 2 nd and subsequent tiers on the M3 DIC [8; 9]. MOSFET and junctionless field-effect transistor (JLFET) have opposite operating principles. The MOSFET controlsthe current through depletion and inversion, and the JLFET controls the current with or without depletion. MOSFET has different source/drain and channel doping types (n/p), whereas JLFET use one doping type for source/drain and channel. Therefore, JLFET is advantageous in terms of thermal budget because the dopant activation process of the MOSFET is unnecessary. The thermal budget of upper tier is constrained by maximum thermal budget of the lower tier or tiers. JLFET has little effect of short channel effect, which is a major problem in MOSFET, and shows good performance in terms of carrier mobility. In order to solve the thermal budget problem, enhance the immunity of mobility degradation, and possess the simplicity of fabrication, JLFET [10,11] on M3 IC has been proposed as the replacement of MOSFET [12].  
M3 IC technology stacking field-programmable gate-array (FPGA) logics and sensor devices have been reported, but the M3 IC consisted of stacked MOSFETs and its thickness of interlayer dielectric (ILD), \(T_{ILD}\), between vertically stacked devices was over 100 nm so that there are no electrical coupling between stacking devices [9]. Recently, a study considering the electrical coupling between stacked devices has been performed when the ILD in monolithic 3D inverter (M3 INV) consisting of MOSFETs is very thin (i.e., \(T_{ILD}\) < 50 nm) [13,14]. Interlayer coupling in monolithic 3D static random access memory (M3 SRAM) stacked vertically with tunnel field-effect transistor (TFET) and MOSFET has been investigated in terms of stability and performance [15]. However, no research has been reported on the electrical coupling between the upper and lower devices of the M3 IC consisting of JLFET [16] which can replace the MOSFETs.  
Therefore, it is necessary to investigate the electrical interaction between devices in M3 IC stacked with the next generation devices. In this paper, we will introduce the electrical coupling in terms of thickness variation of ILD in M3 INV stacked vertically with JLFETs, compared with one with MOSFETs. The structures and simulation method of the M3 INV with MOSFETs or JLFETs will be introduced (Section 2), and the electrical coupling of upper device at different gate voltage of lower devices, simulated with the DC/AC device parameter, will be investigated (Section 3). In Section 4, electrical characteristics of two types of M3 INV (MOSFETs and JLFETs) will be explained. Finally, Section 5 concludes.