# A 4.1 W/mm\({}^{2}\) Hybrid Inductive/Capacitive Converter for 2-140 mA-DVS Load under Inductor +
## 4 Measurement Results  
For steady state efficiency measurements the hybrid converter was stressed with two kinds of loads, resistive and digital, in both open and closed loop mode. On chip MOS transistor banks were used as resistive loads and a group of eight ring oscillators under inductor acted as the representative digital load. Figure 20 shows the efficiency for resistive loads for both the converters. The capacitive converter achieves 71% closed loop peak efficiency at 0.52 V while the inductive converter shows 76.4% peak efficiency at 0.9 V for a resistive load of 20 \(\Omega\). Vdd was 1.2 V. An ideal LDO is also included in this figure for comparison purposes. Figure 19: External SPDT switch and switch debounce circuit used for output voltage transient testing. Figure 17: Programmable transistor loads for steady state test. Figure 18: Gated ring oscillator used as digital load. Figure 21 shows the simulated (gray) and measured efficiencies (orange) vs. power from 2 mW to 140 mW for digital load. Two separate designs were included onchip, one with digital under inductor and one without. The measured peak efficiency for the inductive converter that was 74.3% peak without digital under inductor and 70.3% for digital under inductor. The measured plot in Figure 21 shows the values for the digital under inductor design. The slight decrease in efficiency can be attributed to the coupling losses between digital circuits and the inductor. An ideal LDO is included in this figure as well for comparison purposes. We note that we see a maximum efficiency increase at lower powers. This is particularly important as time spent in sleep modes (i.e., lower power) tend to dominate for portable devices. Figure 22 shows the die photograph. The converter achieves a power density of 0.387 W/mm\({}^{2}\). Re-using the area occupied by the inductor by placing digital circuits underneath the inductor increases the power density of the converter to 4.1 W/mm\({}^{2}\) as shown in Table 1. The power density using this technique is among the highest achieved to date. Figure 21: Efficiency vs. power consumption for digital loads. Figure 20: Efficiency vs. output voltage for resistive loads. Figure 23 shows the leakage profile for the converter. Since leakage current causes the majority of discrepancy between simulated and measured results, it is important to study the leakage results of the converter. The top graph in Figure 23 shows the leakage current verses digital voltage of the control loop of the chip when the clock is disabled. The two graphs below shows the dynamic digital power consumption of the chip vs. clock frequency. The y-intercept of the two graphs on the bottom chart corresponds to the peak leakage current of the top chart. This leakage is direct result of the gate leakage of the MOS capacitor and the subthreshold leakage of the switches involved. This is particularly true for switches involved with the inductive converter as they are especially large. Another reason for the measured efficiency offset (as compared to simulated results) in inductive converter is due to the systematic mismatch in the routing of the measurement circuitry. As shown in Figure 22, the digital under inductor prototype is placed to the far left to the output (filter capacitor) which results in IR routing drops. Better floor planning would have avoided this problem. Table 1 presents a technical summary of this design. The hybrid converter achieves 74.5% measured peak efficiency in the inductive mode of operation at 300 MHz clock frequency. The design uses a 2 nF on-chip MOS decoupling capacitor and 2 nH on-chip spiral inductor as passives. The output power ranges from 2 mW to 140 mW and the output ripple at 0.75 V output is 28 mV. Table 2 presents a performance comparison of the current design with some of the prior designs. Refs [3; 28; 29; 30; 31] are inductive converters while [8; 32; 33; 34] are capacitive converters.