## 3 Technology Background
### Fun
\begin{table}
\begin{tabular}{c c c} \hline \hline  & **Implementation \#1** & **Implementation \#2** \\ \hline
**Precision** & Single—32 bits & Half—16 bits \\
**Optimization** & Automatic (directives) & Automatic (directives) + Manual (code) \\ \hline
**LUTs** & 3089 & 4296 \\
**FFs** & 2612 & 4172 \\
**DSPs** & 10 & 18 \\
**BRAMs** & 8.5 & 4 \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Resource utilization: Single precision versus Half precision floating point implementations. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameter** & **Description** & **Value** \\ \hline _pixels_block & Number of input pixels & 32 \\ \(N_{\text{z}}\) & Number of bands per pixel & 256 \\ \(P_{\text{max}}\) & Maximum number of endmembers to extract & 32 \\ \(\alpha\) & Stop factor & 1.0 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: High-Level Synthesis (HLS)-Based hardware accelerator: configuration parameters. Although the maximum parallelization approach should ideally be better, communication latency discourages its use due to the excessive data traffic over the network. As it can be seen in Figure 3, the approach that targets minimum data transactions between master and slave nodes has provided better experimental results (100 ms faster on average). All network experiments performed in this work use the MPICH implementation of the MPI API, since it has already been proven that it renders better communication performance than other alternatives such as OpenMPI [46]. Figure 2: Network setup: ARTICo\({}^{3}\)-based computing cluster. ## 5 Experimental Results

Two experimental setups have been used to evaluate the runtime scalability of the ARTICo3-based endmember extraction. Single-node scalability has been tested using an in-house custom Zynq-7000 board (XCFZ020-1 CLG484) with integrated power measurement circuitry and thus, energy efficiency metrics have also been obtained. Multi-FPGA scalability, on the other hand, has been evaluated only in terms of computing performance using up to 8 commercial MicroZed development boards (XCFZ020-1 CLG400) arranged in a small Ethernet-based computing cluster. Both scenarios implement the reduction-based FUN endmember extraction using half-precision floating point hardware accelerators and, in the multi-FPGA setup, the data distribution approach for minimum communication over the network. In addition, all tests reported in this section have been performed using three synthetic hyperspectral images, since they enable the evaluation of a wider range of scenarios (e.g., different number of endmembers, different input sizes, etc.) than any of the represented by the real hyperspectral datasets used to validate the parallelization approach (see Section 4.1): one with a size of \(256\times 128\times 128\) and 10 endmembers, one with a size of \(256\times 256\times 256\) and 16 endmembers, and a final one with a size of \(256\times 512\times 512\) and 16 endmembers. The size of the input hyperspectral images is expressed as \(N_{\mathrm{z}}\times N_{\mathrm{y}}\times N_{\mathrm{x}}\), being \(z\) bands, \(y\) lines, and \(x\) samples. Table 8 reports the resource utilization for the ARTICo3 infrastructure (per node), as well as for the final ARTICo3 kernel (FUN + wrapper logic per accelerator). Since this kernel does not require

Figure 3: MPI-based communication overheads (four nodes, hyperspectral images with 128 samples, 128 lines and 256 bands). The top graph shows maximum parallelization, whereas the bottom graph shows minimum data transactions (i.e., communication). The cluster operates on a private network with a dedicated Ethernet switch (1 Gbps). any configuration register, the overhead introduced by wrapping the HLS-generated HDL is almost negligible in terms of LUTs and FFs, while there is a sharp increase in the BRAM count due to the local memory inside the hardware accelerator.