## 4 System Overview
### Proposed Architecture  
To experimentally validate and measure the beams generated by the proposed ADFT algorithms, a 5.7 GHz RF system with a digital processing back-end was meticulously designed and implemented. Figure 2a shows the overall architecture of the system based on a 32-element antenna array, encompassing key subsystems such as the antenna array itself, the RF receiver chain, and the digital hardware unit. Figure 2b shows the experimental setup of the proposed architecture. In addition to the digital cores responsible for executing the spatial DFT of the sampled signals, supplementary circuitry was developed within the FPGA. This additional circuitry facilitates real-time data manipulation and beam measurements across different angles, enhancing the flexibility and capability of the system.  
The re-configurable open architecture computing hardware (ROACH-2)-based digital signal processing (DSP) platform is shown in Figure 3, and it plays a crucial role by serving as an intermediary layer, enabling communication between the FPGA hardware (specifically its memory) and the onboard computer. The ROACH-2 board interfaces with the main host Linux server via a 1 Gbps Ethernet connection. A Python routine running on the host server is programmed to interact with the ROACH-2 platform, performing control functions and retrieving data from the FPGA memory while iteratively scanning through different angles. This unique system architecture not only ensures precise beam  
\begin{table}
\begin{tabular}{l c c} \hline \hline
**Method** & **Real Multiplications** & **Real Additions** \\ \hline Exact 32-point DFT (\(\mathbf{F_{32}}\)) & 1408 & 1666 \\ Radix-2 Cooley–Tukey FFT (\(N=32\)) [99] & 88 & 408 \\ \hline Approximate DFT (\(\mathbf{F_{32}}\)) [96] & 0 & 1282 \\ Fast algorithm for \(\hat{\mathbf{F}}_{32}\) (\(\prod_{i=1}^{8}\mathbf{W}_{i}\)) [97] & 0 & 144 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Performance of the DFT, the Cooley–Tukey FFT, and the discussed 32-point ADFT. Trivial multiplications by \(\pm 1\) or \(\pm j\) not counted; only real-valued input signals assumed.  
\begin{table}
\begin{tabular}{l c c c c c c c} \hline \hline
**Operation** & \(\mathbf{W_{1}}\) & \(\mathbf{W_{2}}\) & \(\mathbf{W_{3}}\) & \(\mathbf{W_{4}}\) & \(\mathbf{W_{5}}\) & \(\mathbf{W_{6}}\) & \(\mathbf{W_{7}}\) & \(\mathbf{W_{8}}\) \\ \hline Real multiplications & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ Real additions & 30 & 30 & 14 & 14 & 30 & 14 & 12 & 0 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Performance of the matrix factors of the ADFT fast algorithm. Trivial multiplications by \(\pm 1\) or \(\pm j\) not counted; only real-valued input signal assumed.  
measurements but also enhances the overall efficiency and automation of the experiment, providing a robust platform for validating advanced beamforming algorithms.  
Figure 3: ROACH-2-based DSP platform based on Xilinx Virtex-6 Sx475 FPGA, and 32-channel ADC card. We gratefully acknowledge Dr. [PERSON] at UC Berkeley and the CASPER community for their contributions to the ROACH-2 and CASPER tools.  
Figure 2: **(a)** The system architecture; **(b)** the experimental setup of the 32-beam array receiver operates at a 5.700 GHz to 5.800 GHz band followed by the ROACH-2 FPGA system (Xilinx Virtex-6 sx475T FPGA) digital back-end.