# Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems
## 3 Integrated Circuits
### 0.5 V-SAR ADC with Single-Clock Bootstrapping and Time-Delay Based Controller  
One of the most critical blocks in the implantable neural interface is the ADC. A successive approximation register (SAR) analog-to-digital converter (ADC) has been employed to satisfy the stringent power budget. In addition, a clock/timing generator should be integrated and shared between the channels to reduce the area consumption. In this work, we use a 0.5 V supply for the ADC to minimize power consumption and isolate the supply from the analog block (1.0 V), thereby reducing the switching noise induced from the 0.5 V supply. For the multi-channel system where a dedicated SAR ADC is implemented to every channel, a synchronous SAR controller can be a good choice to reduce design complexity. However, in the synchronous SAR ADC, the clock frequency should be at least a few times higher than the sampling frequency of the ADC to generate adequate control signals. This high-frequency clock generator consumes high power and can also interfere with delicate analog signals. As an alternative, an asynchronous SAR ADC can be used. It can eliminate a high-frequency clock generator, but requires a dedicated decision circuit which may cause meta-stability and time-varying sampling rates. In addition, the asynchronous controller is hard to be shared in multi-channel systems. With all these in considerations, we implemented a 0.5 V, 8-bit, rail-to-rail synchronous SAR ADC consisting of an input range boosting circuit block, an 8b capacitor digital to analog converter (CDAC), a low voltage single clock (LVS) bootstrapping sample and hold (S/H) circuit, a dynamic comparator, and a time-delay based controller, as shown in Figure 5[27]. In the proposed neural interface, this ADC is interfacing between the two different power supplies: 1.0 for analog and 0.5 V for digital circuits, respectively. The input voltage range over 0.5 V is being accommodated by using the input range boosting circuit. Figure 6 explains the operation of the input range boosting circuit. The comparator in the ADC compares the input range to check whether it is higher than 0.5 V or not before the MSB conversion (SEL [0]) is initiated. If the signal is above 0.5 V, the boost signal becomes 'high' and the reference signal is boosted up to 2\(V_{DD}\) (1.0 V) through \(C_{R}\) in Figure 5. The rest of conversion is  
Figure 4: Schematic of the double-gated, push-pull preamplifier and the table of dimensions and values for the transistors and capacitors used in the preamplifier. accomplished toward \(2V_{DD}\). Otherwise, the conversion is achieved with a reference to the 0.5 V supply. This input range decision can boost the resolution of the ADC by one bit. The low supply voltage can save power consumption of the ADC; however, it mandates an additional function such as bootstrap sampling to compensate for performance. To realize the reliable sampling operation with the low supply voltage while minimizing nonlinearities, the LVS bootstrapping circuit, based on the voltage multiplier circuits [28], is proposed in this SAR ADC, as shown in Figure 7a. The previous bootstrapping technique requires two-phase clocks [29], resulting in high power consumption (practically, doubling the switching speed). On the contrary, the proposed LVS circuit can generate a scalable bootstrapped voltage with a true single clock, which can be expressed as:  
\[V_{SAMPLE}=N\times V_{DD}+V_{IN} \tag{3}\]  
where \(N\) is the number of stages. The bootstrapped output signal and the operation of the LVS are illustrated in Figure 7b. During the pre-charge phase, \(V_{CLK}\) is high, \(M_{\text{1-3}}\) are 'on' and the capacitor, C, is charged to \(V_{DD}\), while \(V_{BS}\) is tied to the ground. Then, during the bootstrap phase, \(V_{CLK}\) is connected to low, \(M_{\text{4-5}}\) and \(M_{\text{S}}\) is 'on' and the LVS switch can generate \(V_{DD}+V_{IN}\).