## 3 Results
### Devices Featuring Ni-ALD Dielectric-Ni Junctions
#### 3.2.3 Optimization of Ni-SiO\({}_{2}\)-Ni Junction Fabrication
A comparison of \(G(V_{ds})\) scans also shows the significant decrease in noise as can be seen in the two side-by-side \(G(V_{ds})\) cross sections of Figure 14. It is quite clear that in the recipe that combines FGA treatment for the SiO\({}_{2}\)-covered island with subsequent RHP treatment of the finished devices, a drastic reduction of switching RTS noise is obtained along with electric characteristics much closer to that expected for MIM junctions [48]. Let us now compare the obtained experimental results with the expected performance based on the dimensions of imaged SETs (Figure 2g). In the case of identical junctions and a gate capacitance much smaller than that of the junctions, \(C_{s}=C_{d}>>C_{g}\), the absolute values of the slopes of the Coulomb diamonds (positive slope, \(\alpha=C_{g}/(C_{s}+C_{g})\), and negative slope \(\beta=-C_{g}/C_{d}\)) are expected to be nearly the same, and the highly asymmetric shape of the diamonds (e.g., Figures 7a and 11) thus indicates a variation in the thickness of the two tunnel junctions most likely due to non-uniformities in the barrier dielectric. Figure 15a shows experimentally obtained data from one FGA+RHP treated device with nearly identical slopes \(|\alpha|\approx|\beta|\). Simulations performed based on an orthodox theory model [20] enable fairly accurate extraction of the junction parameters. While variations of junction capacitances  
Figure 14: Comparison of electrical characteristics for Ni-SiO\({}_{2}\)-Ni devices measured at 0.4 K: (**a**) Coulomb diamonds of a device from batch A1 treated with double FGA along with a \(G(V_{ds})\) cross section at \(V_{g}=100\) mV; and (**b**) Coulomb diamonds of a device from batch B1 treated with FGA+RHP along with a \(G(V_{ds})\) cross section at \(V_{g}=170\) mV. The difference of CBO periods results from different device proximities to electrostatic gates, and hence a different gate capacitance. (\(\sim\)20%) and conductances (\(<\)50%) are fairly reasonable given potential variations in the thickness and junction areas, the absolute values of the capacitances appear to be significantly larger than expected from the parallel-plate model: \(C_{d}\approx C_{s}=\varepsilon_{0}\epsilon A/d=\) 28-40 aF (\(\varepsilon=\) 3.9 for SiO\({}_{2}\), \(A=\) 900-1200 nm\({}^{2}\), and \(d=\) 1.17 nm, the nominal thickness of 13 cycles of PEALD SiO\({}_{2}\)). A comparison of dimensions for devices fabricated using the cross-tie technique (Figure 1) and half-damascene process (Figure 2) shows a very significant narrowing of the island produced by the half-damascene technique. This is clearly beneficial because it lowers the junction capacitance and thus increases the charging energy. However, 3D simulations of the island total capacitance in half-damascene geometry show that the island capacitance can be more than double what would be expected from the parallel plate model due to fringing fields (Figure 16b). Thus the 3D capacitance simulation of Figure 16b (\(C_{Island}=\) 121 aF) provides a good match to the fitted simulation of Figure 15b (\(C_{Island}=C_{d}+C_{s}+C_{g}=\) 110 aF) and shows that fringing fields cannot be ignored for very small junctions. Figure 16: 3D simulation of the total island capacitance in a half-damascene geometry: (**a**) Dimensions of the island (horizontal grey line) and source and drain (vertical grey lines). The island is inlaid in thermal SiO\({}_{2}\) (\(\varepsilon=\) 3.9) and the source and drain are on top of the PEALD dielectric layer (\(\varepsilon=\) 3.9) surrounded by air (\(\varepsilon=\) 1); (**b**) Cross section of island inlaid in SiO\({}_{2}\) dielectric. The simulated total island capacitance \(C_{Island}\) is for 1 nm of PEALD SiO\({}_{2}\) (approximately the same thickness as 12 cycles of SiO\({}_{2}\), \(\varepsilon=\) 1). \(C_{\parallel}\) is the expected island capacitance using the parallel plate model of the two tunnel junctions for the given dimensions.