# An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA
## 4 Proposed 5G-NR Decoder Architecture
### Comprehensive Decoder Architecture  
The decoder is based on the first base graph (BG1). As previously mentioned, the entries of the base matrix vary within the range \(-1\leq\) Hp(i,j) \(\leq\) 383 [38; 39; 40]. The first 22 columns of BG1 entries correspond to the message bits and the following 46 correspond to parity bits. The rate matching determines how many parity bits should be added to the message bits to accomplish the decoding process by applications and their needed performance. Using the maximum expansion factor, and after the expansion of the matrix, this architecture affords the maximum information length in 5G-NR 8448-bits (22 \(\times\) Z) [41; 42]. A simplified schematic of the architecture is presented (see Figure 4). To provide the decoder with the channel's received LLRs during initialization in the first iteration, the control unit's In-Adr output sends a binary \"1\" to the \"2:1 Mux\" (see Figure 4). After the first iteration, In-Adr provides a binary \"0\" to the \"2:1 Mux\" for the subsequent decoding iterations of the processed frame, until the correction is carried out or a maximum number of iterations is achieved. The same process is repeated for the next frames coming from the channel. The second output of the control unit is the Lyr-Ctrl, which indicates the current processing layer for all the blocks. Figure 3: Structure of both base graphs according to the rate (R) and the number of message bits (K). After being supplied into the decoder, the received LLRs are separated using a read-network into treated and raw data corresponding to non \(-1\)s and \(-1\)s entries of the base graph, respectively, based on the current processes row (layer). The row weight dc deviates between dcmin = 3 and dcmax = 19; therefore, the treated data are passed using 19 \"Mp:1 Mux\" during each layer process. The raw data are simultaneously sent by several (Np-3) \"Mp:1 Mux\" directly to the write-network so that they can be concatenated with the processed data after the layer decoding is complete. Following the read network, the (19 \(\times\) Z) LLRs are handled by the dcmax shifting blocks. The construction of the shifting blocks is based on a new particular method that involves assembling a ('Z' by 'b') matrix of \"2:1 Mux\" with Z \(\leq\) 2b. The shifting blocks obtain the base graph entries through the input LC after they are converted to binary addresses using the binary conversion block. The matrix [Z \(\times\) b] \"2:1 Mux\" accomplishes the shifting of every 384 LLR sequence by addressing the \"2:1 Mux\" with the converted LC entries. Similar steps are taken for the shift-back blocks, while the multiplexers contained therein are managed by the minus circuit that subtracts the base graph's elements from the expansion factor (Z\(-\)Hp(i,j)). Before the shift-back blocks and immediately after the shifting blocks, the data proceed along their path to the processing units. The recorded check node output values of the same layer from the previous iterations are received from the MS-mem and subtracted from the current data values (received LLRs) via a tree of dcmax sub-units, each of which has Z subtractors. It must be noted that the data do not change throughout the sub-unit blocks during the first iteration since there is no data stored in memory. The internal architecture of the MINU block is discussed in the following subsection where the sub-unit blocks outputs take place to find the two minimums. According to MSA, the block yields the first min instead of all the other values and then replaces the first min value with the second min. Each block of the dcmax add-unit accommodates Z adders, so it calculates the summation of MINU and sub-unit outputs to determine the processed LLRs. The write-network collects both the processed and raw data along with two different demultiplexer trees  
Figure 4: Global architecture of the proposed decoder.