# Elliptic-Curve Crypto Processor for RFID Applications
## 2 Preliminaries
### PM Computation over \(Gf(2^{M})\)
\begin{table}
\begin{tabular}{l c c c c c} \hline \hline
**Device** & **Clk. Period (in ns)** & **Freq. (in MHz)** & **Latency (in \(\upmu\)s)** & **LUTs** & **FFs** & **Power (in \(\upmu\)W)** \\ \hline \hline \multicolumn{6}{l}{Utilization of schoolbook multiplier as sequential logic (high-performance results)} \\ \hline Kintex-7 & 1.1 & 909 & 2.88 & & & 647 \\ Artix-7 & 1.3 & 769 & 3.41 & 1786 & 1855 & 647 \\ Virtex-7 & 1.1 & 909 & 2.88 & & & 733 \\ \hline \multicolumn{6}{l}{Use of schoolbook multiplier as combinational logic (power-optimized results)} \\ \hline Kintex-7 & 4.4 & 227 & 11.57 & & & 161 \\ Artix-7 & 5.2 & 192 & 13.68 & 3561 & 1527 & 161 \\ Virtex-7 & 4.4 & 227 & 11.57 & & & 183 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Implementation results of the proposed ECP accelerator architecture on modern FPGA devices. Therefore, there is a trade-off among several 7-series devices in terms of frequency and power results. The design of the fabric for the Artix-7 is customized for low-cost while the Kintex-7 and Virtex-7 are tuned for high-performance [30]. #### 4.1.2 Integration of a Polynomial Multiplier as Combinational Logic

Table 1 reveals that the use of a schoolbook multiplier as a combinational logic results in a longer critical path which ultimately shows the decrease in the clock frequency (227 MHz on both Kintex-7 and Virtex-7 devices whereas a 192 MHz on Artix-7). Moreover, with the same clock cycles utilization, it takes two times more hardware resources in terms of FPGA LUTs (3561) as compared to the sequential multiplier circuit (where this value is 1786). Furthermore, on Kintex-7, Virtex-7, and Artix-7 FPGA devices, it requires 4 times more computational time (latency) for the execution of instructions shown in Algorithm 1. Despite all other parameters (i.e., hardware resources, clock frequency, and latency), the use of a combinational multiplier circuit in our proposed ECP architecture results in 4-fold decrease in power consumption (0.161 mW on both Kintex-7 and Artix-7 devices while 0.183 mW on a Virtex-7) as compared to the sequential multiplier circuit. In summary, the sequential logic results in a low critical path with an increase in the clock frequency. On the other hand, the combinational logic infers the longer critical path with a decrease in the operational frequency. Apart from this, the sequential logic for the polynomial multiplication results in higher power consumption as in the employed schoolbook multiplier where we have incorporated two \(m\)-bit registers. The first register is employed to perform a one-bit shift operation in one clock cycle while another register is utilized to accumulate a shifted result during the polynomial multiplication computation. In the combinational style, we have applied the dedicated circuit logic for implementation. On FPGA devices, with the expense of latency (computational time), more power can be reduced by utilizing a single shared buffer rather than three (as we used in this work--see Section 3.2). With use of one shared buffer, further power can be optimized through clock gating when running a synthesis for ASIC commercial nodes (as used in [21]). ### Comparison with State-of-the-Art

Before describing the comparison to the state-of-the-art, it is essential to note that we have provided our implementation results using a schoolbook polynomial multiplier (implemented with two different, i.e., sequential and combinational, logic styles). The sequential implementation of a schoolbook multiplier in our proposed ECP architecture allows us to achieve the objective of this paper (a low-latency (high-performance) and low-area architecture for RFID applications). Therefore, the performance comparison to the existing state-of-the-art is provided with our high-performance implementation results. The comparison with the state-of-the-art is shown in Table 2. The first column in Table 2 provides the reference solution (Ref. #). The targeted key length, i.e., \(m\) and the implementation devices are shown in column two and three, respectively.