## 5 The Effect of Concave and Convex Structures  
In terms of a vertical cross-section, 3D NAND flash memory involves depositing a gate dielectric and poly-Si channel after collectively etching channel holes, which can result in each WL having either a concave or convex structure [16]. Recent research has focused on maximizing memory characteristics by applying specific curvatures to the poly-Si channel. Based on studies showing that the shape of the poly-Si channel can alleviate program speed degradation in a channel structure with specific curvature, we analyzed memory window characteristics by applying concave and convex structures to each ON pitch reduction structure. Existing studies obtained significant results when the recess thickness, a variable related to channel curvature, was 3 nm or more [17]. Thus, in this study, the recess thickness was set to 3 nm for both convex and concave structures. The recess thickness is the physical parameter representing the curvature of the polysilicon channel layers. Additionally, to apply variables within a realistically applicable process range, the ON pitch was implemented by reducing Lg and Ls by 5 nm each in the reference device. Other doping and materials were set as identical to the simulation structures in Figure 1a-d. Figure 11a-d show the electron and hole-trapped charge after program and erase operations in the concave and convex channel structures when Lg/Ls is 20 nm. The results show dense e-trapped charges in the charge trap layer of the selected WL region in the convex structure. In comparison, concave channels have a more widely distributed charge, showing similar results to previous studies on curvature channels [17]. This is likely because, as explained in previous studies, the electric field confined to the center of the gate in the concave structure is reduced, causing the trapped charge to form more widely. Additionally, compared to e-trapped charges, hole-trapped charges also have a higher concentration in the lower gate area in the convex structure than in the concave structure. However, even in the convex structure, where the electric field concentration is high at the bottom of the WL, it is confirmed that a high concentration of e-trapped charges is mainly formed only at the bottom of the gate, whereas a high concentration of h-trapped charges is formed in the space region. This variation in CTL regional concentration between electrons and holes can significantly deteriorate data retention characteristics in the lateral direction [16]. Figure 11e confirms the improvement in the program and erase window when using the convex structure compared to the concave structure when scaling Lg and Ls. The results show that the improvement in the PE window is much higher during Lg scaling compared to Ls scaling. This is likely because the reduced gate-to-substrate capacitive coupling caused by Lg scaling is compensated for by strengthening the electric field at the bottom of the gate in the convex structure. Therefore, using an appropriate level of channel curvature change in the convex direction to compensate for PE window deterioration during Lg scaling can be considered a very effective strategy. Additionally, when applying the convex structure, the Z-interference degradation phenomenon can be further improved, as the electrons are confined only to the lower WL of the attack cell. However, if the convex structure is applied excessively, this may intensify the deterioration of retention characteristics, as described above. Therefore, considering the trade-off characteristics of the memory window and retention characteristics, it is essential to engineer a combination of Lg and Ls scaling to form an optimal reliability margin. Finally, since the various simulation results thus far are based on theoretical conditions, there may be some differences between the predicted results of this simulation and the actual outcomes due to process variability and material property uncertainties in the fabrication of 3D NAND devices.