# Embedded Bayesian Network Contribution for a Safe Mission Planning of Autonomous Vehicles
## 3 Methodology for an Automatic BN Generation and Its Embedded Implementation
### Design Flow for an Embedded Version of BN Diagnosis  
In this section, we give the basic of the dedicated design tool that we propose to friendly implement the BN monitors onto FPGA support. These works are detailed in previous publications [20; 21; 22]. We resume the main steps and we enlighten the FPGA implementation of these monitors through an example detailed in Section 5.  
For an efficient implementation of the diagnosis and the mitigation modules specified by Bayesian Networks from FMEA tables, we propose to target FPGA support. The different steps to generate an efficient bitstream are detailed in Figure 11. The main steps are:  
1. two kinds of high-level transformations: one dedicated to BN compilation and one more classical related to the structural (or hierarchical) decomposition and to the bitwidth optimization. The first category includes the compilation into an Arithmetic Circuit (AC) form, the evidence optimization. This step provides an C-code (C-HLS Compliant) that can feed HLS tool such as Vivado-HLS from Xilinx.
2. HLS directives proposal for the C-code in order to generate efficient implementation onto FPGA (C-HLS Compliant with directives). These directives are proposed to guide the management of the parallelism for the resource usage, the management of the memory and the management of SW/HW interface. These directives are defined in Pragma form using the Vivado-HLS tool [23].
3. Integration to HLS tool such as Vivado-HLS whose flow towards a FPGA-SoC board is illustrated in Figure 12. From the implementation on an hybrid FPGA-SoC, different types of interfaces can be used to import the evidence values from the sensors or the parameters of the BN (DMA interface or BRAM interface) via \(AXI-Bus\) (see Figure 24).  
Figure 11: Our design tool proposal for the FPGA implementation of BN monitors from FMEA-like tables (F2F BNTool).  
As inputs, we propose to describe the BN monitors by means of FMEA-like tables associated to three main patterns described in Section 2. These tables can vary in terms of types of error and in terms of error mitigation proposals. From these tables, we generate the BN structures according to the pattern used in the table. After generating the BN model of the monitors, we propose an Arithmetic Circuit (AC) description that can translate the inference computation of BN structures into trees including arithmetics operators (* and +). This AC description can also be directly generated from the BN pattern of the tables. The AC description is an internal form that can be optimized by propagating some evidences associated to sensor activities. Then we can map the code to specific libraries by proceeding to a structural decomposition. Other optimizations like bitwidth optimization can be applied to save resource and to improve performance and reduce energy consumption. This optimization tunes a floating point value to a fixed point one with a limited precision according to an acceptable accuracy. More details on this tuning are given in [22]. The result of the first group of transformations generate a C-description that is HLS compliant. From that point, we feed HLS tool with the C-description. In addition to the one, we can propose some appropriate HLS directives for the parallelism and memory management to provide a better FPGA implementation. Then the HLS tool (Vivado-HLS) is able to provide the embedded version onto the FPGA support. We place our proposal as a front end of commercial HLS tool by proposing the adequate parameters for the HLS directives, the C-code of the BN monitors, as well the adequate interface between the FPGA and the CPU with BRAM or DMA option. The adaptation with the HLS tool from Xilinx is shown in Figure 12.