# A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing
## 1 Introduction  
Many machine learning applications are migrating from the cloud to the edge, close to where data is collected so as to overcome several negative issues associated with data computing on the cloud (see Table 1). A major issue is the inference latency that results from the delay to communicate with the server. In some applications, like self-driving cars, a high latency results in a high risk and must be avoided. \begin{table}
\begin{tabular}{l l} \hline \hline
**Edge Computing** & **Cloud Computing** \\ \hline Low latency & High latency \\ Time-sensitive response & Not time-sensitive response \\ Low connectivity dependence & High connectivity dependence \\ Task specific processing & Application specific processing \\ Low cost & High cost \\ \hline Difficult to manage (distributed) & Easier to manage (central) \\ Difficult to debug (remote) & Easier to debug (local) \\ Low computing power & High computing power \\ Energy constrained & Not energy constrained \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Edge computing versus cloud computing. Running inference in edge devices allows custom machine learning optimizations that may be different for different edge nodes. Furthermore, running the inference in the cloud has a cost that may invalidate the applicability of the edge system due to high costs. Deep neural networks (DNNs) are computationally demanding and memory hungry so it is a challenge to run these models in edge devices. A number of techniques have been used to tackle this problem. Some approaches have minimized the size of neural networks and still keep the accuracy, like MobileNet [1], while others reduce the size or the number of parameters [2]. Another design option towards the implementation of deep neural networks in edge devices is the use of devices with better performance efficiency. Embedded GPUs (Graphics Processing Units), ASICs (Application Specific Integrated Circuits), and reconfigurable devices, like FPGAs (Field Programmable Gate Arrays), have already been explored as target devices for deep learning. ASICs have the best performance but have fixed silicon and thus are unable to follow the latest deep models due to long design cycles. On the other side, GPUs can follow the progress of deep models but are less power efficient than reconfigurable devices. Reconfigurable devices can be tailored for each specific model with a higher energy efficiency. Since the publication of AlexNet in 2012, many architectures have been proposed to accelerate deep neural networks [3; 4]. These works can be classified according within several dimensions (see Figure 1). Several different technologies are available for the execution of deep neural networks, namely reconfigurable devices, ASICs, GPUs, and CPUs, with different tradeoffs related to area, performance, cost, flexibility, energy, and others. Among the several deep neural network models (CNN--convolutional neural network, RNN--recurrent neural network, BNN--binary neural networks, etc. ), CNNs have attracted the attention of most accelerators [5] since they found more target applications among other models. Another research direction is determined by the reconfigurable computing (mainly FPGAs) design task. Since designing with FPGAs is a complex task requiring hardware expertise, some works have contributed with hardware blocks and design frameworks for deep learning implementation. Several frameworks have already been proposed to automatically implement DNN models from system-level specifications using high-level languages, like C, to specify the network model. Another dimension considers the set of optimizations over the network model and the hardware architecture to improve implementation efficiency [6]. The computing environment,  
Figure 1: Design space in the development of accelerators for deep neural networks. cloud, or edge, also determines the design of the network.