## 3 Related Work  
The origins of EH can be traced back to 1985 when [PERSON] et al. used GA to create compact symbolic circuit layouts [30], although the term \"EH\" was not used then. Subsequent studies, such as those by [PERSON] et al. [31] and [PERSON] et al. [32], employed GAs  
Figure 2: Code snippet taken from human-made circuit of proposed FSM with the state’s default assignments highlighted in blue colour. to optimally place components on circuit boards. In 1992, [PERSON] [9] pioneered the use of GP to develop complete circuits at the gate level. This involved a decomposition method where an 11-to-1 multiplexer was evolved using two 6-to-1 multiplexers, which evolved from 3-to-1 multiplexers. The term \"EH\" was first introduced by [33] in 1993, marking a significant step towards the practical implementation of the \"Darwin Machine\" [34], where combinational circuits were evolved. Considerable research has been conducted on the evolution of combinational circuits using various methods, including ES [35], Cartesian Genetic Programming (CGP) [36], and GE [16; 37; 38]. While significant work has been conducted on the evolution of FSMs or Deterministic Finite Automata (DFAs) [39; 40; 41; 42], there has been less research on evolving sequential circuits, explicitly from the perspective of FSMs [43; 44; 45; 46]. Notable examples include [47] and [17], where single-input, single-output SDs were evolved. [PERSON] et al. presented the first automatic solution for gate-level SD evolution using GA in 2004 [48]. They evolved a 4-bit SD ('1010') and a 6-bit SD ('01101') through a multi-stage evolutionary process, which was resource-intensive and did not directly produce the final solutions. The 6-bit SD combined two 3-bit SDs ('011'). The same circuits were re-evolved using GA, achieving more optimised solutions with reduced computational cost [49]. In 2007, [PERSON] et al. evolved a 3-bit SD ('110') using an incremental, evolutionary approach based on GA [50]. This approach involved developing basic module circuits via a greedy search to construct more extensive, complex circuits. However, the approach needed to be expanded in scope, targeting specific modules and thus limiting the search space, preventing the generation of generalised solution circuits. In 2009, [PERSON] et al. evolved an overlapping 3-bit SD capable of detecting sequences like '101' and '100', utilizing intrinsic evolution on an FPGA board [51]. They later demonstrated this system's real-life application in a cardiovascular system [52], evolving the same SD using intrinsic and extrinsic evolution methods based on GA, showcasing the system on an FPGA board. Both approaches were computationally expensive for a small 3-bit SD. In 2011, [PERSON] et al. [47] revisited the evolution of the circuits initially evolved by [PERSON] et al. [48] and [PERSON] et al. [49] using a GA. They claimed to have used fewer gates than the earlier work by [PERSON] et al., although they did not compare their results with [PERSON]'s work. [PERSON] et al. in 2012 evolved a 4-bit SD using GA and GP [53]. This incremental evolution process involved evolving basic circuits as modules before developing complex circuits from these modules. Using three evolutionary stages for a relatively simple 4-bit SD underscored the high computational cost. Previous research has primarily focused on the gate-level evolution of SDs using GA and GP. The first work on behavioural-level SD evolution was presented in [17], where 3, 4, 5, and 6-bit SDs were evolved using GE. This work successfully evolved behavioural-level HDL codes from the perspective of FSMs, with the 3, 4, and 5-bit SDs being evolved in a single evolutionary stage. However, due to its complexity, the 6-bit SD required a second evolutionary phase incorporating grammar encapsulation. In this phase, the grammar is provided with the best individual achieved so far, allowing the system to evolve further from that point (detail in the [17]).