# CMOS Fixed Pattern Noise Removal Based on Low Rank Sparse Variational Method
## 1 Introduced  
Compared with CMOS Image Sensor (CIS), CCD has the characteristics of high quantum efficiency, high sensitivity, low dark current, good consistency and low noise. However, in recent years, with the development of large-scale integrated circuit technology, the photoelectric characteristics of CIS have been greatly improved. In particular, sCMOS sensor is a composite technology which combines the advantages of CCD and CMOS. It also has the features of high quantum efficiency, high sensitivity and low dark current [1; 2]. However, CIS still lags behind CCD in the consistency of photoelectric response. This is mainly due to the apparent fixed pattern noise (FPN) in CIS relative to the CCD. However, CIS is also favored by many industries, due to its outstanding advantages in high acquisition rate and low cost. Technically speaking, the appearance of FPN is mainly caused by the structure of CIS. In order to reduce the readout noise and improve the signal-to-noise ratio, most CIS uses active pixel structures such as three transistors (3T), four transistors (4T), five transistors (5T). In each pixel, the electrons generated by the photoelectric response also need to pass the pixel amplifier and the column amplifier to reach the ADC and the digital processing unit finally. Due to the mismatch of pixel amplifier and column amplifier, the photoelectric characteristics of pixels and columns are inconsistent, which leads to the appearance of FPN. The reason for FPN generation is analyzed in detail, with the 3T structure in Figure 1 as an example. Due to the difference in the threshold voltage of different transistors, different output results can be obtained even under the same light conditions. For Figure 1b analysis, this is due to the inconsistency of A\({}_{\text{P}}\) magnification among different pixels. The noise caused by this A\({}_{\text{P}}\) inconsistency is called pixel fixed pattern noise (PFPN). It appears as a snowflake patch on the image. In general, PFPN can be suppressed to a great extent by using the related double sampling technique (CDS). The M4 load transistor, AC amplifier and Aout amplifier are output structures shared by each column pixel. Due to the mismatch between the bias voltage of each column amplifier, a noise called column fixed pattern noise (CFPN) is produced, which is shown as vertical stripes on the image. In summary, the fixed pattern noise can be made up of two parts: FPN = CFPN + PFPN, where FPN is the total fixed pattern noise, PFPN is pixel fixed pattern noise, and CFPN is column fixed pattern noise. The image with FPN noise is similar to Figure 2. To suppress FPN, CDS technology is generally used, but it can only eliminate PFPN component in FPN. CFPN caused by output stage amplifier A\({}_{\text{out}}\) cannot be effectively eliminated. For specific analysis, please refer to the literature [3,4]. After CDS, the output voltage can be described by Formula (1):  
\[ \begin{array}{ll}M&=G\cdot A_{p}A_{C}A_{out}\cdot\eta\cdot\frac{P_{d}}{k\cdot \eta}+G\cdot A_{out}\Delta V_{A_{out}}\\ &=G\cdot A_{p}A_{C}A_{out}\cdot N+G\cdot A_{out}\Delta V_{A_{out}}\\ &=k\cdot N+b\\ \end{array}  \tag{1}\]  
where \(G\) is the analog-to-digital conversion coefficient, unit: \(DN/v\), \(A_{p}\) is the equivalent comprehensive amplification factor composed of M2, M3 and M4, unit: \(v/v\)-, \(A_{c}\) and \(A_{out}\) are the amplification factors of buffer operation amplifier and output operation amplifier, respectively and \(\Delta V_{A_{out}}\) is the bias voltage of output amplifier. \(P\) is the incident light power, \(t\) is the exposure time, \(h\) is the Planck constant, \(V\) is the incident light wavelength, \(\eta\) is the CIS quantum efficiency. \(N\) is the number of incident electrons. \(k=GA_{p}A_{C}A_{out}\), \(b=A_{out}\Delta V_{A_{out}}\).