# FPGA-Based Pulse Compressor for Ultra Low Latency Visible Light Communications
## 7 Discussion  
In this paper, the possibility of employing the chirp coding in VLC has been investigated and the performance of different chirp codes has been compared. The experiments confirmed (see Figure 12) that the gain in communication distance achieved by different chirp temporal durations well fits the theoretical trend, given by (5). These results prove that the advantages of chirp modulation, which made this technique widely employed in other fields like radar and sonar, can be exploited in VLC as well. The SNR gain achievable by chirp modulation and pulse compression is related to the chirp temporal length, not to the chirp amplitude [22; 23]. Communications at increasing distances can be obtained by employing chirp at increasing lengths, or low-energy links can be obtained by reducing the chirp amplitude and compensating by increasing its length.  
However, for chirp modulation to have practical applications, it is necessary to demonstrate the feasibility of its real-time, low-latency implementation. In this work we shown an FPGA real-time implementation with a latency below 40 \(\upmu\)s, suitable to satisfy even the most severe requirements of the current and next-future applications, like for example the industrial environment [11] and motor control loops [30]. The high calculation requirements of the pulse compressor are satisfied in real-time and ultra-low-latency environments by FPGAs only. However, different approaches are possible. For example, a processor can execute the same calculations with a higher latency and a lower throughput. On the other  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Step** & **Time** & **Time Ref** \\ \hline Payload at FIFO input & 0 & 0 \\ \hline TX FIFO out & 0.16 \(\upmu\)s & T\({}_{1}\) \\ \hline Packet Formation & 0.48 \(\upmu\)s & T\({}_{2}\) \\ \hline Serializer & 0.48 \(\upmu\)s \(-\) 15.84 \(\upmu\)s & T\({}_{2}\)–T\({}_{5}\) \\ \hline Modulator Out & 0.80 \(\upmu\)s \(-\) 15.52 \(\upmu\)s + \(T\) & T\({}_{3}\)–T\({}_{6}\) \\ \hline Receiver input & 0.80 \(\upmu\)s \(-\) 15.616 \(\upmu\)s + \(T\) & T\({}_{3}\)–T\({}_{6}\) \\ \hline Compressor filter out & \(T\) + 1.024 \(\upmu\)s \(-\) \(T\) + 16.288 \(\upmu\)s & T\({}_{3}\)–T\({}_{7}\) \\ \hline Thresholds out & \(T\) + 16.304 \(\upmu\)s & T\({}_{8}\) \\ \hline Packet recog. out & \(T\) + 16.320 \(\upmu\)s & T\({}_{9}\) \\ \hline RX FIFO out & \(T\) + 16.336 \(\upmu\)s & T\({}_{10}\) \\ \hline \hline \end{tabular}
\end{table}
Table 4: FPGA delays in TX-RX data path.  
Figure 13: Delays (not to scale for clarity) in the TX and RX processing chain. The time-bars referrer to the output of the corresponding block.  
hand, the availability of the FPGA opens the possibility of applying in real-time, with a small latency cost, correction algorithms like Reed-Solomon [31], Viterbi [32], or others that can improve the robustness of the communication.  
The aim of the presented experiments was not to stress for the maximum achievable distance or data rate. The communication distance can be further improved, for example, by increasing the optical gain with a lamp deflector and/or a lens at the receiver [33]. On the other hand, in chirp modulation the bit rate is limited by the compressed pulse resolution W, that, in turn, is constrained by the chirp bandwidth. In these experiments we exploited all of the bandwidth available from the employed LED (about 1.8 MHz). Different LED technologies (e.g., non-phosphorous based) or the use of blue filters allow a higher bandwidth [34], but this is typically achieved at the detriment of the received power.