# Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation
## 3 Parameter Extraction for Circuit Simulation
\begin{table}
\begin{tabular}{c c c c} \hline \hline \multirow{2}{*}{**Parameter**} & \multirow{2}{*}{**Unit**} & \multirow{2}{*}{**Description**} & \multicolumn{2}{c}{**Value (\(T_{\text{ILD}}\))**} \\ \cline{3-4}  & & & **10 nm** & **100 nm** \\ \hline DLQ & m & Effective channel length offset CV & \(4\times 10^{-8}\) & \(4\times 10^{-8}\) \\ VFBO & V & Geometry-independent flat-band voltage & \(-\)0.175 & \(-\)0.26 \\ CTO & - & Interface states factor & 0.4 & 0.4 \\ CICO & - & Geometry-independent part of substrate bias dependence factor of & 0.2 & 0.2 \\ CFL & V\({}^{-1}\) & Length dependence of DIBL & 0.4 & 1 \\ UO & m\({}^{2}\)/V/s & Zero-field mobility & \(1.8\times 10^{-2}\) & \(3.5\times 10^{-2}\) \\ MUEO & m/V & Mobility reduction coefficient & \(1.5\) & 7 \\ THEMUO & - & Mobility reduction exponent & 0.1 & 0.2 \\ FETAO & - & Effective field parameter & 1 & 0 \\ PSCEL & - & Length dependence of short channel effect above threshold & 0.14 & 0.06 \\ THESATO & V\({}^{-1}\) & Geometry-independent velocity saturation parameter & 7 & 1 \\ AXO & - & Geometry-independent of linear/saturation transition factor & 6 & 0.5 \\ ALPL1 & - & Length dependence of CLM pre-factor ALP & 0.0002 & 0.002 \\ VPO & V & CLM logarithm dependence factor & 0.04 & 2 \\ CCGBVL & F & Oxide capacitance for gate-substrate overlap & 0 & \(14\times 10^{-16}\) \\ CFRW & F & Outer fringe capacitance & \(2.5\times 10^{-16}\) & \(2.2\times 10^{-16}\) \\ RSGO & - & Gate-bias dependence of RS & 0.2 & 0.5 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Summary of extracted LETI-UTSOI model parameters for the top N-type MOSFET (coupling/non-coupling). HSPICE simulation results also agree well with the total gate capacitance magnitude and trend within the error range. Figure 5 shows the voltage transfer characteristics (VTC) of M3 DINV both with and without the interface trap charge at \(T_{\text{ILD}}\) = 10 and 100 nm. The symbols and lines show the TCAD mixed-mode and HSPICE simulation results, respectively. The filled symbols (and solid lines) and empty symbols (and dashed lines) denote without and with the interface trap charge, respectively. The squares and triangles denote \(T_{\text{ILD}}\) of 10 and 100 nm, respectively. The HSPICE simulation results agree well with TCAD mixed-mode results. The switching threshold voltage \(V_{m}\) was shifted owing to the threshold voltage shift of the top/bottom MOSFETs by the interface trap charge. When the \(T_{\text{ILD}}\) is 10 and 100 nm, the \(V_{m}\) s shifts by 0.125 and 0.047 V, respectively. Figure 3: Current-voltage characteristics of the bottom P-type MOSFET and top N-type MOSFET with and without interface trap charges. (**a**) \(I_{\text{nls}}\)-\(V_{\text{pgs}}\) characteristics of the bottom P-type MOSFET at different \(V_{\text{pgs}}\) (with \(T_{\text{ILD}}\) = 10 and 100 nm), (**b**) \(I_{\text{nls}}\)-\(V_{\text{ngs}}\) characteristics of the top N-type MOSFET with \(T_{\text{ILD}}\) = 10 nm at different \(V_{\text{nls}}\), and (**c**) \(I_{\text{nls}}\)-\(V_{\text{ngs}}\) characteristics of the top N-type MOSFET with \(T_{\text{ILD}}\) = 100 nm at different \(V_{\text{nls}}\). Figure 4: Total gate capacitance-voltage characteristics of the bottom P-type MOSFET and top N-type MOSFET with and without interface trap charges. (**a**) \(C_{PSPS}\)-\(V_{PSs}\) characteristics of the bottom P-type MOSFET at different \(V_{puls}\) (and \(T_{\rm ILD}\) = 10 and 100 nm), (**b**) \(C_{ngg}\)-\(V_{PSs}\) characteristics of the top N-type MOSFET with \(T_{\rm ILD}\) = 10 nm at different \(V_{nds}\), and (**c**) \(C_{\rm ngg}\)-\(V_{\rm PSs}\) characteristics of the top N-type MOSFET with \(T_{\rm ILD}\) = 100 nm at different \(V_{nds}\). Figure 5: Voltage transfer characteristics of M3 DINV at \(T_{\rm ILD}\) = 10 and 100 nm. The symbols and lines denote TCAD mixed-mode and HSPICE simulation results, respectively. The filled symbols (and dashed lines) and non-filled symbols (and solid lines) denote models both with and without the interface trap charges, respectively.