# Prediction of a Two-Transistor Vertical QNOT Gate
## 3 Results and Discussion  
The proposed layout in Figure 1a is basically analyzed in our previous work on the vertical 3-D organic inverter, which focuses on the voltage-gain improvement by increasing the contact resistance of FETs [13]. Here, we demonstrate for the first time that a substantial increase in \(E_{b}\) at both FETs can dramatically transform the simple 2-level inverter into a fully functional QNOT gate, without any structural modification. Figure 1b shows the simulation results of the voltage-transfer characteristics (VTCs) of the circuit in Figure 1a, at \(V_{\text{DD}}\) = 5 V. The parametric variation of \(E_{b}\) was introduced with no change in electrode work function, but by energetically moving the semiconductor HOMO and LUMO levels together keeping the same bandgap (Figure 1b inset). The VTCs reveal that an initial departure  
Figure 1: (**a**) Cross-sectional illustration and driving configuration of the proposed inverter circuit. (**b**) Simulated voltage-transfer characteristics (VTCs) showing the evolution from binary to quaternary logic. Inset: the energy diagram defining \(E_{b}\) at each field-effect transistor (FET) (\(E_{F}\) is the source/drain metal Fermi level). (**c**) Normalized transfer curve of the p-type FET (PFET) at varying \(E_{b}\). from an ideal ohmic contact (\(E_{b}=0\) eV) to a blocking one (\(E_{b}=0.4\) eV) actually provides a sharper data transition from high to low \(V_{\text{out}}\)[13]. Surprisingly, it was found that an \(E_{b}\) of 0.6 eV substantially changes the shape of VTC, where the four data levels (\"0\", \"1\", \"2\", and \"3\") are clearly identifiable. To gain a first insight into its mechanism, we additionally performed simulations of individual FETs. As shown in Figure 1c, the normalized saturation-regime transfer curve of the PFET at a drain voltage (\(V_{D}\)) of \(-5\) V shows a quadratic shape with regard to gate voltage (\(V_{G}\)) when \(E_{b}=0\) eV, suggesting no contact resistance effects [15; 16]. In contrast, increasing \(E_{b}\) resulted in substantial deviation, exhibiting a quasi-linear behavior at \(E_{b}=0.4\) eV. At the \(E_{b}\) enabling the quaternary circuit, the drain current (\(I_{D}\)) showed an apparent kink (arrow in Figure 1c), which is generally considered as the consequence of a substantial contact resistance [17; 18; 19]. Albeit with different biasing, this abrupt slope change on the transfer curve in part rationalizes the QNOT behavior of Figure 1b; this in fact translates into the existence of two distinct regimes with different resistance distribution ratios on a single transistor, during its on-off scan by \(V_{\text{in}}\). As the second requirement for QNOT functionality (in addition to \(E_{b}\)), the absence of geometrical overlap between the gate (input) and source/drain electrodes is addressed. Figure 2a is the side-by-side comparison of the cases of no overlap (base structure) and the full overlap with an extended gate electrode. Clearly, there is no quaternary effect in the modified circuit with a full electrode overlap. To further our understanding of underlying mechanism, we extracted the charge-carrier distribution at each component device in a full simulated inverter (not from the individual transistor simulation such as that in Figure 1c). Especially, the focus was placed on visualizing the internal distribution at two newly developed data states, one at \(V_{\text{in}}=2\)V (level \"2\") and the other at \(V_{\text{in}}=3\) V (level \"1\") (in conjunction with Figure 1b). Comparing Figure 2b,c reveals one important difference, which is the apparent carrier pinch-off at the supply node (i.e., source electrode) indicated by the arrow in the no-overlap data of Figure 2b. This actually reminds us of the special property of the source-gated transistor (SGTs), whose operation largely relies on this source pinch-off rather than the drain pinch-off prevailing in traditional FETs [20].