# SDR-Based 28 GHz mmWave Channel Modeling of Railway Marshaling Yard
## 3 Software-Defined Radio-Based Channel Modeling  
### SDR mmWave Measurement System  
The SDR mmWave measurement system architecture is shown in Figure 5. The receiving and transmitting ends each use a USRP-2974 as the signal receiving and transmitting  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Detail Information** \\ \hline Length of the yard & 600 m \\ Width of the yard & 40 m \\ Number of tracks & 8 \\ Track gauge & 1.435 m \\ Distance between tracks & 5.05 m \\ Distance between Catenary poles & 31–47 m \\ High of Catenary poles & 10 m \\ Height of the building & canopy 7.5 m; building 10 m \\ Distance between the track and the building & 6 m \\ Size of the locomotive & Length \(\times\) Width \(\times\) Height (m) = \(26.6\times 3.105\times 4.433\) \\ \hline \hline \end{tabular}
\end{table}
Table 2: Parameters of corresponding scenarios.  
Figure 4: Building adjacent to the testing track.  
Figure 3: Locomotive on adjacent Track.  
main body. Both USRP-2974s are connected to the GPS antenna on their side, so the internal GPS disciplined oscillator (GPSDO) can receive the GPS signal, which is used to lock the internal clock, so that the USRP-2974 at each end can be synchronized. By using a phased-array antenna at the receiving and transmitting ends, the intermediate frequency of 2.8 GHz is moved to the 28 GHz frequency band to achieve the transmission and reception of mmWave signals.  
The compositions of the transmitting and receiving ends are shown in Figure 6.  
At the transmitting end, the REF reference clock locked by the GPSDO will be sent to the RF module of the USRP-2974 and output to the up-converter of the phased-array antenna to ensure system synchronization. At the same time, the GPSDO will send the pulse-per-second signal (PPS) to the FPGA of the USRP-2974 for timing triggering. A ZC sequence is generated by the USRP-2974 host and sent to the USRP-2974 FPGA. After IQ compensation and digital up-conversion, the FPGA sends the digital baseband data to the USRP-2974 RF module, where DA conversion and baseband up-conversion are completed, and the signal is up-converted to 2.8 GHz. At the phased-array antenna end, the 2.8 GHz signal is received and mixed with the local oscillator, whose frequency is 25.2 GHz, to generate the final 28 GHz mmWave RF signal, which is transmitted through the antenna array surface. In this system, the transmitting angle of the phased-array antenna is 0 degrees, which is the normal direction of the array surface.  
At the receiving end, the REF reference clock locked by the GPSDO will be sent to the RF module of the USRP-2974 and output to the down-converter of the phased-array antenna to ensure system synchronization. At the same time, the GPSDO will send PPS to the FPGA of the USRP-2974 for timing triggering. The antenna array will receive a 28 GHz mmWave signal, which will be mixed with the local oscillator, whose frequency is 25.2 GHz, and down convert it into a 2.8 GHz intermediate frequency signal. The RF module of the USRP-2974 will complete baseband down-conversion and baseband sampling and transmit the collected IQ data to the FPGA of the USRP-2974. After completing IQ compensation and digital down-conversion at the FPGA end, the data will be transmitted to the Host end. At the Host end, the same ZC waveform as the transmitter side will be generated and correlated with the received IQ data, and the correlated IQ CIR will be obtained. The IQ CIR will be converted from v to dBm to obtain the power delay profile (PDP); in the meantime, the original IQ waveform and PDP data will be recorded and stored on the disk.  
Figure 5: SDR mmWave measurement system architecture.  
Figure 6: Composition diagram of transmitting and receiving ends. (**a**) Transmitting end. (**b**) Receiving end.