## 4 A Survey on FPGA-Based Sensor Systems
### Multimedia Applications  
This section comprises research sensor nodes for image compression ([65; 66; 67; 68; 69]), audio processing ([70; 71]), image processing and task scheduling for multimedia applications via the FPGA ([71; 72; 73; 74; 75]). [PERSON] _et al_. [71] presented a hardware architecture of a sensor node based on an AVR ATMega microcontroller and an IGLOO FPGA (AGL600). The FPGA is utilized in order to perform a 512-points FFT. The communication between the FPGA and the microcontroller is done at 4 MHz in parallel (8-bit). Power consumption of the platform in standby is 35.97 mW and 13.26 mW in sleep. The FFT execution on the FPGA consumes 12.36 mW, far less than the power consumption on the processor (382.94 mW). In [65], the authors proposed Compressive Sampling (CS) in a Spartan-3 FPGA (XC3S400) in order to be used on WSNs. CS presents several advantages in comparison to traditional sampling methods, since it allows to reconstruct certain signals using a reduced number of samples. Recent works concerning the utilization of CS in WSNs appear promising in terms of energy efficiency [76; 77]. However, the power consumption of the aforementioned design was not provided by the authors. In [66], [PERSON] _et al_. presented the design of a sensor node with an FPGA coprocessor attached based on a Virtex-5 (XC5 VLX330T) that performs image compression via Loeffler DCT transform and controls an attached CMOS image sensor. At 100 MHz, the system consumes 364.85 mW. Moreover, the authors compared the power consumption with a similar implementation on a MICA2 sensor node, consuming 0.42 mJ _versus_ 37.826 mJ in the commercial node. [PERSON] _et al_. [67] presented a standalone sensor node based on an Altera Cyclone II FPGA (EP2C3) for image processing. The node is equipped with a 2.4 GHz NRF24L01 transceiver and a CMOS image sensor. The JPEG Baseline is implemented on the FPGA, in a SoC based on the Nios II soft-core. However, this implementation contains the same problems as those related in Section 4.1. JPEG Baseline could be better implemented in an IGLOO Board, consuming less power, and to be controlled by a low-power microcontroller coupled with a 802.15.4 transceiver. [PERSON] _et al._ presented an FPGA-based coprocessor for image compression in sensor nodes based on the Haar Wavelet Transform (HWT). The implementation was done in a Virtex 5 FPGA, requiring 1.09 mJ for image encoding at 139.49 MHz and 267 mW. In [70], the authors proposed a sensor node for optimized voice data transmission. The FPGA (Spartan-3, XC3S100E) implements the 802.15.4 MAC layer with a modification in the packet header, which gives priority to voice packets. An Atmel AT91 controls the audio sensor. However, the authors did not provide the energy consumption details of the platform. [PERSON] _et al_. [72] presented a sensor node for magnetic particles detection and classification in a liquid. The sensor node is based on the commercial platform SENTIO32 and an FPGA. The SENTNIO32 platform is a sensor node developed by the Mid Sweden University based on an AVR32 and a CC2520 802.15.4-based transceiver. The authors tested the low-cost Spartan-6 and the ultra low-power IGLOO FPGA. The FPGA performs background subtraction, object identification and extraction and TIFF compression. The FPGA processing consumes 5.93 mW (IGLOO). However, the SENTIO32 platform consumes 132 mW during transmission. Moreover, if all the image processing tasks are done in the microcontroller, it consumes 77.5 mW, 12 times more than on FPGA. In [75], the authors presented a sensor node where the image processing is executed on a Spartan-3 FPGA (XC3S1000). The Running Gaussian Average algorithm is implemented in order to perform background subtraction and object extraction. The FPGA consumes 8.57 mW at 137.44 MHz. Finally, [PERSON] _et al._ presented the design and implementation of an image processing core for a wireless capsule endoscopy (WCE) [69].