## 3 Design of Ternary Logic Circuits
### Conventional Design of Ternary Adder  
Adder is the most important arithmetic logical unit in a microprocessor, because all the mathematic operators and computations can be finally reduced into addition. Ternary logic decreases the requirement of components and interconnections by realizing more data transmission over an interconnection wire. Therefore, it is promising in high speed and high efficient data processing.  
There are several ternary adders which have been designed in the published literatures, which can be generally categorized into two types: Capacitive-based and transistors-based circuits. The capacitive-based design benefits low complexity and low device count [15], however it exhibits high variation sensitivity and high area-cost because of the existing of capacitor. Most of the previous works focused on the transistor-based circuits where various logic gates are utilized to process the input and output voltage information [11; 12; 13; 14]. In a conventional wisdom design of a transistor-based ternary ripple-carry adder, the two input numbers are summed together bit by bit, from the lowest address to the highest address. Though ternary intrinsically contains larger logic states densities, the existing designs of the ternary adder are not cost-efficient when compared to the binary adder. Figure 5 presents the conventional ternary half-adder design [11]. The ternary input A and B signals are firstly decoded by the ternary decoder (the two blue dashed box regions). Then they will be transferred to the next logic unit (red dashed box region) for computing. The output equations are given by Sum = (A2\(\cdot\)B0 + A1\(\cdot\)B1 + A0\(\cdot\)B2) + 1\(\cdot\)(A1\(\cdot\)B0 + A0\(\cdot\)B1 + A2\(\cdot\)B2) and Carry = 1\(\cdot\)(A2\(\cdot\)B1 + A2\(\cdot\)B2 + A1\(\cdot\)B2). Note that the output of the decoder has only two logic values, i.e., \"2\" and \"0\", corresponding to logic \"1\" and \"0\" in binary logic. Therefore, binary AND/OR gates can be used here (Note: The logic states are still named as logic \"2\" and logic \"0\" in those binary logic gates). Finally the calculated binary results will be re-transferred into a ternary signal as the output. Two ternary buffers are needed here, one for the sum1 result (A1\(\cdot\)B0 + A0\(\cdot\)B1 + A2\(\cdot\)B2) and the other one for the carry (A2\(\cdot\)B1 + A2\(\cdot\)B2 + A1\(\cdot\)B2), because the binary signal of sum1 and carry can only be \"0\" or \"1\", and will never be \"2\".  
Figure 4: (**a**) Design of the ternary decoder and ternary buffer. (**b**) Symbols of all the ternary logic gates discussed in this work. Note: The unlabeled logic gates represent the normal binary logic gate.  
Such ternary adder design has largely increased the circuitry complexity because it avoided the advantages of ternary logic. In fact, the main computation part is indeed made of binary logic gates. It has also largely increased the required transistors. For instance, a silicon-based, ternary half-adder requires 114 transistors and a 1-trit full-adder requires more than 200 transistors [5]. Meanwhile, a classical silicon CMOS binary only requires 28 transistors for the half-adder, and 62 transistors for the 1-bit full-adder. To simplify the circuit design and reduce the required transistors, we develop a mixed ternary-binary computation system where ternary cycling gates and the improved ternary adder algorithm are used.