# Hard SyDR: A Benchmarking Environment for Global Navigation Satellite System Algorithms +
## 2 Background and Motivation
### Moving Closer to Hardware  
Thanks to the improvements in computers and microelectronics over the last 25 years, algorithm developments in GNSS processing have slowly transitioned from hardware to software implementation [9]. While this has greatly simplified the development and verification of new algorithms, it has complicated realistically estimating the cost of using a specific algorithm within the processing chain. Relative comparisons between algorithms can still be achieved, assuming they are developed with a similar quality (e.g., optimized resource usage) and benchmarked over identical datasets. However, absolute estimates of  
Figure 2: Processing time results from SyDR (Python) for each processing stage inside a channel: average processing time (**left**) and total processing time (**right**).  
their energy consumption are not feasible, given the potential interference of concurrent operations running on the same processor.  
Consequently, we consider moving the algorithms back to hardware for more realistic estimates of their costs. Indeed, doing so not only permits the collection of additional KPIs related to resource consumption and timing, but it can also help pinpoint any potential challenges pertaining to the hardware implementation of an algorithm not immediately visible from the software perspective. While one may argue that these metrics are better collected from the type of platform that the algorithms are expected to be implemented in, i.e., ASICs, for ease of use, we choose FPGAs as the target hardware platform. We acknowledge that, owing to their reconfigurability, FPGAs are known to be slower, and less area- and energy-efficient than ASICs. Yet, the differences are well-established in the literature [27]. Hardware simulations of ASICs and FPGAs are feasible but unattractive due to long execution time and occasionally doubtful accuracy [28; 29].  
Using FPGAs for GNSS receiver development is not new and has been performed in several SDRs. We have summarized examples of such in a previous work [9]. However, all previous implementations focus on real-time processing and, therefore, use FPGAs for hardware acceleration (e.g., GNSS-SDR [6], Tiira [30]). We take a different approach and propose to review the applicability of reconfigurable platforms like FPGAs for power estimation and benchmarking.  
In the context of benchmarking, real-time processing is not a necessity, as it is more interesting to replay and post-process well-defined datasets to accurately compare algorithms. While post-processing can be carried out by a real-time processing system (i.e., using a Universal Software Radio Peripheral (USRP) to replay an RF signal), this approach over-complicates the software and overall system greatly with no added value to our analyses. This is the prime reason for developing SyDR instead of using a more advanced open-source tool, such as GNSS-SDR. However, our approach is not to be confused with GNSS-SDR [6], which used GNU-Radio to further replicate the behavior of a USRP using Python code. In our applications, we only target evaluating the energy efficiency of GNSS algorithms at the hardware layer and do not review any aspect of the hardware used for recording.  
Interoperability and usability have been major drivers for the development of SyDR from the start, as defined in [9]. Consequently, with Hard SyDR, we look into a way to move from software to hardware while retaining modularity. The present work is a proof-of-concept that probes the feasibility of such developments.