# Developing a Universal Mirror-mirror Laser Mapping System for Single Event Effect Research
## 3 Results
### Sensitivity Mapping for Regula_11T SRAM Structure  
Pulsed laser systems have been widely used in SEE research for SRAMs [16; 17]. The size of a single SRAM cell is always in the range of one micron with modern technologies. However, most studies on SRAM laser mapping are carried out in relatively large ROIs with the size of dozens or hundreds of microns.  
The SEE sensitivity laser mapping testing was applied on a single SRAM cell with a Regular_11T structure which was fabricated with a CMOS 65 nm bulk technology. The laser scanning step size was set to 0.18 \(\upmu\)m. Compared with the measured spot size of 2.7 \(\upmu\)m (by Mitutoyo Apo NIR 50X/0.65 objective), the step size was much smaller than the spot size.  
The SRAM chip and the testing system are shown in Figure 18.  
Sensitivity Mapping Laser Testing Result  
The Regular_11T structure of SRAM adopts a Cascade voltage switching logic (CVSL) design, with each of the four nodes, ABCD, driven by a pair of pull-up PMOS and pull-down NMOS transistors. The schematic and layout are shown in Figure 19.  
Figure 19: (**a**) Schematic of Regular_11T structure; (**b**) layout of Regular_11T structure.  
Figure 18: (**a**) Top & bottom sides of SRAM chip; (**b**) testing system profile.  
From circuit analysis, node A controls N2 & N4, node B controls P3 & N1, node C controls P2 & P4 and node D controls P1 & N3. Additionally, nodes A & C should be always complementary to nodes B & D. Consequently, there are two logic states for the Regular_11T storage pattern: 1010 (state'1) and 0101 (state 0).  
Due to this structure, when the stored data pattern is 1, which is 1010 for nodes ABCD, the circuit can restore the initial state if only one node has been hit by laser pulses. For example, if node A was hit by laser pulses and its state changes from 1 to 0, the transistors of N2 & N4 would be turned off correspondingly. At this moment, N2 & P2 and N4 & P4 are all in the 'OFF' state, so nodes B & C remain in their states. Consequently, the state of node A will eventually be pulled up by VDD through P1 and the whole SRAM cell restores to its initial state. The other three nodes can be analyzed by the same logic. However, if the stored data pattern is 0, which is 0101 for nodes ABCD. The situation is different. Here, when node A is hit by laser pulses, the state of SRAM will be changed and generate an error, while the other three nodes will restore their initial states if they were hit by laser pulses. For example, if node A is hit, its state changes from 0 to 1, the high-level voltage will turn on N2 & N4, which results in nodes B and D being pulled down. Consequently, the data pattern stored in A1A2A3 is changed from 011 to 100 and an error is generated.  
In actual testing, laser pulses with an energy of 90 pJ were injected into the Regular_11T SRAM cell with the data pattern of all 0 and 0/1. The results are shown in Figure 20. In the testing, the dimension of the ROI was \(1.90\times 1.30\)\(\upmu\)m and the step size was set to 0.18\(\upmu\)m.  
From the mapping results, the sensitive areas were all located at the left part of the SRAM cell, around node A region. This was consistent with the circuit analysis provided above. However, the result for '0/1' stored data pattern (Figure 20b) has a larger sensitivity area and it drifts slightly downwards. This may be due to the dynamic charging and discharging process at node A, which may make the current dissipation more unstable compared to all '0' data patterns. This could explain the larger sensitive area and spatial drift.