## 4 DC Fault Current Analysis of Hybrid MMC Considering FRT Control
### Voltage Control Mode  
Under DC voltage-regulated outer-loop operation, \(I_{dcrf}\) is expressed as follows:  
\[I_{dcrf}=k_{pv}\Big{(}U_{dcrf}-U_{dcpu}\Big{)}+k_{iv}\int\Big{(}U_{dcrf}-U_{ dcpu}\Big{)}dt \tag{17}\]  
where \(k_{pv}\) and \(k_{iv}\) parameterize the proportional and integral gains of the PI controller in the outer regulatory loop. Synthesizing (6)-(8) through complex frequency domain analysis yields the representation of hybrid MMC control (Figure 8), with \(U_{e}\) characterized by:  
\[U_{e}(s)=\bigg{[}\bigg{(}\frac{U_{dcrf}}{s}-\frac{U_{dc}(s)}{U_{dcn}}\bigg{)} \bigg{(}k_{pv}+\frac{k_{iv}}{s}\bigg{)}-\frac{I_{dc}(s)}{I_{dcn}}\bigg{]} \bigg{(}k_{pi}+\frac{k_{ii}}{s}\bigg{)}U_{dcn} \tag{18}\]  
Leveraging the configuration in Figure 8, the complex frequency domain representation of DC fault current is analytically extracted and documented in the Appendix A.2. The analytical expression of \(i_{dc}\) is discussed depending on different conditions.  
1. When \(\frac{(k_{pv}k_{ii}+k_{pi}k_{iv}+U_{dcn}k_{pi}/Ll_{dcn})^{2}}{4(1+k_{pv}k_{pi}) }<k_{iv}k_{ii}+\frac{U_{dcp}k_{ii}}{Ll_{dcn}}\), the fault circuit shows under-damped characteristic, and \(i_{dc}\) is obtained as follows: \[i_{dc}(t)=(\frac{k_{iv}P_{dcn}U_{dcrf}}{k_{iv}Ll_{dcn}+U_{dcn}}t+a)+B_{1}e^{-k_ {v}t}sin(\omega_{v}t+\theta_{v})\] (19)  
\[\left\{\begin{array}{l}B_{1}=\frac{1}{\omega_{v}}\sqrt{\frac{k_{iv}k_{ii}Ll_ {dcn  
\[\left\{\begin{array}{l}B_{2}=\frac{1}{2}[(I_{0}-a)-\frac{\delta_{x}}{\omega_{x}}(I _{0}+a)+b]\\ B_{3}=\frac{1}{2}[(I_{0}-a)+\frac{\delta_{x}}{\omega_{x}}(I_{0}+a)-b]\end{array}\right. \tag{22}\]
3. When \(\frac{(k_{ip}k_{ii}+k_{ip}k_{ip}+U_{dcrf}k_{ri}/Ll_{dcn})^{2}}{4(1+k_{ip}k_{ri}) }=k_{ip}k_{ii}+\frac{U_{dcrf}k_{ii}}{Ll_{dcn}}\), the fault circuit shows critical damped characteristic, and \(i_{dc}\) is obtained as follows: \[i_{dc}(t)=(\frac{k_{ip}l_{dcn}U_{dcrf}}{k_{ip}Ll_{dcn}+U_{dcn}}+a)+(I_{0}-a)e^{ -\delta_{x}t}\] (23)  
Similarly, the DC fault current is composed of steady component and transient component. When the \(U_{dcrf}\) is not equal to zero, the steady component is increasing with time. However, it must be noted that the control saturation is not considered in this case. In the practical application, the PI controller has a limit value. The voltage discrepancy between \(U_{dcrf}\) and \(U_{dc}\) drives progressive amplification of the outer regulatory hierarchy output until \(l_{dcrf}\) saturation occurs. The steady component in the practical application is obtained using \(l_{dcrf}l_{dcn}\), where \(l_{dcrf}\) is the limit value of the controller. Taking the underdamped case as an example, Figure 9 illustrates the fault currents under different \(U_{dcrf}\). The fault current rise rate exhibits proportionality to \(U_{dcrf}\). Parameterizing \(U_{dcrf}=0\) induces current zero-crossing behavior.  
Under \(U_{dcrf}=0\) conditions, Figure 10 depicts fault current profiles across varying regulatory coefficients of the DC voltage PI controller. Both the transient rise rate and peak magnitude exhibit inverse proportionality to PI parameter magnitudes. This phenomenon arises because elevated PI coefficients depress \(l_{dcrf}\), accelerating \(M_{dc}\) attenuation. Conversely, enhanced PI parameters diminish fault current decay rates, prolonging fault clearance duration. Consequently, a trade-off needs to be addressed between transient current suppression and fault clearance efficiency for future PI coefficient selection during FRT process.  
Figure 10: DC fault currents under parametric variation of (**a**) proportional and (**b**) integral gain in the PI controller with \(U_{dcrf}=0\).  
Figure 9: DC fault currents under different voltage reference values (underdamped characteristic case).