# Analysis of Six Active Power Control Strategies of Interconnected Grids with VSC-HVDC
## 3 Active Power Controller Design of VSC-HVDC  
The schematic diagram of the VSC-HVDC is illustrated in Figure 2. The widely used vector controller is applied in the VSC. Let the converter side impedance be simply modeled as a series-connected three phase inductor and resistor, and the AC grid in the \(abc\) frame is:  
\[\left[\begin{array}{c}v_{1}^{d}\\ v_{1}^{q}\end{array}\right]-\left[\begin{array}{c}v_{2}^{d}\\ v_{2}^{q}\end{array}\right]=R\left[\begin{array}{c}i_{d}\\ i_{q}\end{array}\right]+L\frac{d}{dt}\left[\begin{array}{c}i_{d}\\ i_{q}\end{array}\right]-\left[\begin{array}{c}-\omega Li_{q}\\ \omega Li_{d}\end{array}\right], \tag{4}\]  
where the \(v_{2}\) is the voltage at PCC and \(v_{1}\) is the voltage at the converter. In addition, \(R\) and \(L\) are the resistance and inductance, respectively, and \(i\) is the current flowing to the AC grid. Filter components prevent the generation of harmonic current by the converter, and they also affect the stability between the AC grid and the VSC.  
The reference voltage generated by the inner current control loop is transformed back into the \(abc\) frame and used for Pulse With Modulation (PWM) to produce the desired converter three-phase voltage. The voltage reference sent to the PWM is represented by:  
\[\left[\begin{array}{c}\Delta r_{2}^{d}\\ \Delta r_{2}^{q}\end{array}\right]=-\left[\begin{array}{c}A_{d}(s)\\ A_{q}(s)\end{array}\right]\left[\begin{array}{c}\Delta i_{d,ref}-\Delta i_{d} \\ \Delta i_{q,ref}-\Delta i_{q}\end{array}\right]+\omega L\left[\begin{array}{c} -\Delta i_{q}\\ \Delta i_{d}\end{array}\right]+\left[\begin{array}{c}v_{1}^{d}\\ v_{1}^{q}\end{array}\right], \tag{5}\]  
where \(A_{d}(s)\)_and \(A_{q}(s)=\frac{k_{p}s+k_{s}}{s}\).  
The PWM switching delay is then approximated by a first-order Pade approximation as follows:  
\[G_{PWM}(s)=\frac{1-\frac{1.5T_{d}s}{2}}{1+\frac{1.5T_{d}s}{2}}, \tag{6}\]  
where \(T_{d}\) is the switching delay in the PWM. Then, combining (5) and (6), the equation can be rearranged by the input terms as \(v_{2}^{dq}\) and \(i_{dq,ref}\), with \(i_{dq}\) as the output. The transfer functions of the inner controller are expressed by:  
\[i_{d}=A\cdot v_{2}^{d}+B\cdot i_{d,ref}, \tag{7}\]  
\[i_{q}=A\cdot v_{2}^{q}+B\cdot i_{q,ref}, \tag{8}\]  
where \(A=\frac{1-G_{PWM}(s)}{(R+Ls)+G_{PWM}(s)\cdot A_{d}(s)}\), \(B=\frac{G_{PWM}(s)\cdot A(s)}{(R+Ls)+G_{PWM}(s)\cdot A_{d}(s)}\).  
The q-axis current of the \(d\)-\(q\) frame is aligned with the AC system phasor based on the PLL, i.e., \(i_{q}=0\). Thus, the converter admittance is derived as \(i_{abc}/v_{2}\), which is obtained as follows:  
\[Y_{VSC}(s)=\frac{1-G_{PWM}(s)}{(R+Ls)+G_{PWM}(s)\cdot A_{d}(s)}. \tag{9}\]  
Depending on (9), the d-axis current flowing to the AC grid to control active power is represented in Figure 3. Following the block diagram, the stability between the AC grid and converter can be analyzed based on the initial operating point of the VSC. However, the detailed small signal analysis is not of interest in this paper, and the useful results were given with an impedance-based stability analysis theorem by References [23; 24].  
Figure 2: VSC control block diagram. PWM: Pulse With Modulation; PLL Phase-Locked Loop.  
Following the d-axis current response of the converter, the active power of the PGs is simultaneously activated with their own GVIF index. The incremental power of the PGs of area 1 is transferred to area 2, and its characteristic is adjusted by several active power control strategies, as illustrated in the following section.