# FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs
## 5 Performance Efficiency of FPGA-QNN  
Accelerators developed with three different quantization types for MLP and LeNet models were tested on three datasets of varying difficulty levels: MNIST, FashionMNIST, and CIFAR-10. Figure 15 presents the accuracy levels obtained from the ARM 9 CPU and Zynq 70 ZC020 FPGA on the PYNQ Z1. The MNIST and FashionMNIST datasets were tested with both MLP and LeNet models, while CIFAR-10 was evaluated only on the LeNet model. MNIST achieved high accuracy across CPU and FPGA, ranging from 94% to 99%, while FashionMNIST showed slightly lower rates due to its complexity, with MLP achieving up to 86% and LeNet up to 90% on CPU and FPGA. The CIFAR-10 dataset posed greater challenges, with accuracy ranging from 70% to 83% on CPU and 64% to 74% on FPGA, highlighting the impact of quantization levels. Despite this, the accuracy loss on FPGA was minimal (around 1%), demonstrating that folding levels had negligible effects on accuracy and that model performance is directly influenced by the number of quantization bits used. This underscores the dependency of accuracy on quantization strategies in hardware accelerators. The processing time of 10,000 MNIST images on the CPU, where no quantization or folding was applied, was observed as 18.2 s for LeNet and 3.6 s for MLP. However, with  
Figure 14: The blocks of the developed accelerator hardware. Figure 15: FPGA and CPU accuracy graph for MLP and LeNet models. W1A1 quantization and H folding level applied on the FPGA, the processing time was significantly reduced to 1.4 s for LeNet and 0.014 s for MLP, as illustrated in Figure 16. Additionally, the accuracy values shown in the graph indicate that LeNet achieves 95.4% accuracy on the FPGA and 98.3% on the CPU for the MNIST dataset, while MLP achieves 90.0% accuracy on the FPGA and 95.0% on the CPU. These results demonstrate that while there is a slight trade-off in accuracy when using FPGA optimizations, the reduction in processing time is substantial, making FPGA a highly efficient option for scenarios prioritizing speed over marginal accuracy loss. In this study, the FPGA operating frequency is 100 MHz. In the developed accelerators, the time between layers and DRAM reading and writing stages can be measured. The network metrics measured for the MLP W1A1 accelerator appear in the Table 3. Due to the simplicity of the MNIST dataset, which may not adequately represent the challenges of real-world image classification tasks, and the significantly low accuracy values observed for the CIFAR-10 dataset in initial experiments, the remainder of this study was conducted using the FashionMNIST dataset. This dataset provides a more challenging benchmark compared to MNIST while maintaining computational efficiency, making it suitable for evaluating the performance of the MLP and LeNet models. By focusing on FashionMNIST, the study ensures a balanced trade-off between complexity and resource efficiency, enabling a more meaningful analysis of the selected models under different conditions. Tables 4 and 5 aim to provide the resource utilization and processing time of six different accelerator hardware configurations trained with the FashionMNIST dataset. The results are analyzed according to two different folding parameters (L-H) and three quantization types (W1A1,W1A2,W2A2) applied to both the MLP and LeNet models. It is worth noticing that logical operations on the FPGA use LUT and FF resources, while memory operations use BRAM and LUTRAM resources. In MLP at L folding level, all resource consumption increases as the quantization level increases. BRAM utilization in W1A1 and W1A2 exhibits a similar trend, at H folding, but it is increased by approximately two times in W2A2. This indicates that memory usage is affected by the quantization of weights rather than the activation quantization. In LeNet at H folding level, both memory and logic resources vary in direct proportion to the quantization number of bits.