# A Review of Cell Operation Algorithm for 3D NAND Flash Memory
## 2 Program Algorithm
### Improvement of the Program Disturb
Due to the limited carrier mobility of poly-Si channel, the conventional BL pre-charge scheme is not strong enough to initialize the channel potential of an unselected string [23]. To enhance the pre-charging efficiency, the BL pre-charging voltage has to be increased, and thereby, the pre-turn on voltage of the upper select transistor is also increased [21]. In this paper, however, the pre-turn on the voltage of the upper select transistor is applied even as ground. This scheme demonstrates that program disturb can be improved by directly supplying holes into the channel by implementing an operation method similar to the GIDL current formation of the erase operation [3]. However, to implement this method, a high voltage gap of 4 V or higher must be applied between the BL and the select transistor because the GIDL current must be sufficiently generated [24]. In this case, it will be necessary to develop a page buffer circuit to drive a high BL bias and additional revision to compensate for the increased programming time due to a longer GIDL generation time. In addition, to reduce the trap-assisted BTBT current generated by grain boundary trap, a method of arranging a dummy WL bias between the select transistor and the main cell during program operation was proposed [12; 25]. By gradually adjusting their pass voltage during program operation, program disturbances caused by HCI were also reduced. Meanwhile, in respect to optimization of dummy WL operation during program, [PERSON]. [PERSON] et al. proposed a two-step pulse method [26] in which a low pre-voltage is first applied in the BL pre-charge period and then a relatively high dummy WL bias is applied  
Figure 2: (**a**) Four strings in a block and USP sequence. Reprinted/adapted with permission from Ref. [21], 2017, IEEE. (**b**) Cell distribution using USP sequence. Reprinted/adapted with permission from Ref. [21], 2017, IEEE. in the program pulse period, rather than simply applying a same bias to the dummy WL at once. This technique demonstrates that it is possible to control HCI program disturbance from the dummy WL, by reducing the transverse electric field between the dummy WL and the edge main WL. W.-L. [PERSON] et al. proposed a method of minimizing negative down-coupling by holding the pass voltage of unselected WLs after the verify operation [27]. Their programming algorithm consists of a sequence of a program operation followed by a verify operation to check if the target threshold voltage is reached; this process is repeated with increasing program voltages until all cells on the page have reached the target threshold voltage [28]. In 3D-NAND architectures, since the conductive path is not formed in the string except for BL and source line (SL), the channel potential can capacitively couple with WLs and drop to negative voltages when WL voltage falls during the verify operation [19]. In this approach, holding a pass voltage of unselected WLs without lowering it to the ground after the verify operation is finished is suggested. However, this method can lower the boosting efficiency during subsequent program operation, and so may cause soft programming disturb. Another recommendation is to softly turn on the WLn-1/n-2 cells before the program operation. This shares the channel potential of the down-coupled cell region with other regions so that subsequent high lateral electric fields are not applied, relieving the HCI disturbance; however, this pre-turn on condition consumes extra time, degrading program performance. Apart from the above circuit-level or chip-level hardware-based approaches, some software-based approaches can provide one part of the solution to mitigate the program disturbance. [PERSON] et al. proposed a programming method by dividing one physical block into two logical sub-blocks (referred to as reliable blocks) [29]. The selected pages to form a reliable block are not adjacent with each other. Thus, programming each page in a reliable block with interlaced mapping causes minimal disturbance to other pages in the same reliable block.