## 2 Fine-Timestamp Maker Design  
### Architecture and Circuit Design  
The fine-timestamp maker measures the time interval between the hit signal and the system clock's preceding rising edge; the complete circuit structure is shown in Figure 1a. It mainly contains two steps of time interpolation. First, one acceleration module primarily aims to reduce the maximal working time of the Vernier-measuring module and preliminarily interpolate the whole period of the system clock via four multi-phase clocks. However, the measurement result, called fine time, has a relatively lower resolution. Second, to achieve higher measurement precision, one Vernier-measuring module is investigated to interpolate fine time again for the ultimate resolution. It determines the highest measurement capabilities of the TDC in this design. When the Eoc (representing the end of conversion) signal becomes one, the time assembler combines the fine time and the ultra-fine time as the fine timestamp representing the time interpolation results. The entire process flows are shown in Figure 2. Additionally,  
Figure 1: The overall structure of the fine-timestamp maker showing (**a**) circuit composition and (**b**) time diagram. The four different colored dashed lines in figure (**b**) represent the four regions into which the clk_0 signal is divided. the multi-phase clock generator (via the phase-locked loops (PLLs) inside the FPGA) synthesizes the input clk signal (provided by a differential active crystal oscillator of 500 MHz) to generate four outputs (clk_0-clk_270) with the same frequency but at 90-degree phase shifts from each other, where clk_0 is the system clock signal of the whole TDC. The main principle of the acceleration module shown in Figure 3 is that the four phase-shifted clocks directly sample the hit signal simultaneously. When the rising edge of the hit signal arrives, one clock cycle of the system clock clk_0 is divided into four regions according to the results of Q1-Q4, as shown in Figure 1b. Therefore, if using these region boundaries to stop the Vernier-measuring module, its maximal process time could be reduced by a factor of four, thus, the performance of RMSE could be improved significantly for the same resolution goal. Using the method in [20], Q1-Q4 can be synchronized to the system clock clk_0 within three clock cycles, and the four-bit one-hot code can be converted into a two-bit binary code as the fine time, i.e., the first time interpolation is finished. However, its resolution is only in the unit of \(\frac{1}{4}\) of the system clock period. The composition details of the Vernier-measuring module are shown in Figure 4, which mainly consists of a ring oscillator (RO), an ultra-fine counter, and a coincidence circuit. This module exploits the single ring oscillator working in Vernier mode to generate  
Figure 3: Schematic diagram of the acceleration module. Figure 2: Flow chart of the bi-time interpolation scheme. the ultra-fine time representing the TDC's highest resolution. The RO is triggered by the hit signal to start oscillation (Osc). Instead of two ROs as used in [21; 22; 23], the system clock signal clk_0 is directly used as the reference clock signal, so that some factors incurring metastability risk can be avoided. In addition, as the structure of the Vernier-measuring module becomes simpler, it can save the resource consumption of one RO and the position dependence would also be reduced. The principle of the Vernier-measuring module requires the oscillation period to be different from the reference clock signal (clk_0), then the rising edge of the oscillation signal will gradually move from one region of clk_0 to an adjacent region. The coincidence circuit is designed to determine whether the rising edge of the oscillation signal crosses over any region boundaries of the clk_0 signal as shown in Figure 1b. After they become aligned, the coincidence circuit immediately issues the RO-RST signal to reset the RO and avoid the accumulations of the jitter.