# Atomic Layer Deposition (ALD) of Metal Gates for CMOS
## 2 ALD of the Metal Gates
### ALD of P-Type Metal Gate
The above early ALD studies to deposit TiN were targeted at the application of tungsten and Cu diffusion barriers. The first study on the ALD of the TiN for the metal gate application was reported in 2002 by [PERSON] [117]. In their work, the thermal ALD of TiN was carried out with TiCl\({}_{4}\) and NH\({}_{3}\) at 350 \({}^{\circ}\)C and annealed in forming gas at 420 \({}^{\circ}\)C for 30 min to passivate interface states. The flatband voltage (\(V_{fb}\)) was extracted from the C-V curve and used to calculate the _EWF_. It was found that the of the ALD TiN is comparable to that of the p-type poly-Si. The _EWF_ extracted is about 5.3 eV. In the same work, they compared the C-V curve of the ALD TiN with PVD TiN and found that the PVD TiN had a mid-gap work function. The p-type _EWF_ of the ALD TiN was explained as more N incorporated in the film. The processing details and growth mechanism were presented by [PERSON] et al. and [PERSON] et al. [118; 119]. [PERSON] et al. published a work on the ALD of TiN in the same year using the same precursor and reactant [120]. They studied the W/TiN/SiO\({}_{2}\)(3 nm)/p-Si MOS capacitors and demonstrated that the ALD-TiN has very low interfacial defect density on SiO\({}_{2}\). The comparison among the ALD, and CVD revealed that the ALD layer had lower level of Cl content. [PERSON] et al. studied the ALD of TiN on ALD HfO\({}_{2}\), using TDMAT and NH\({}_{3}\)[121]. The ALD of TiN was carried out at 180 \({}^{\circ}\)C, and gave out a layer with 27 at% Ti, 30 at% N, 37 at% oxygen and 6 at% carbon. Different from the _EWF_ reported by [PERSON] [117], this MOALD TiN showed a _EWF_ of n-types metal, \(\sim\)4.2 eV. This _EWF_ was attributed to the interfacial layer generated by incubation of the deposition. They detected an interfacial layer of \(\sim\)2 nm in the TiN, with remarkable Ti-rich composition. To confirm this, a follow-up study was done using the same ALD to investigate the impact of the TiN thickness to the _EWF_[122]. It was found that the flatband voltage of the TiN layer below 2 nm showed strong thickness dependence. After 2 nm, the flatband voltage approach constant. Thermal stability was the most important concern for the application of the TiN metal gate. In 2003, [PERSON] et al. studied the thermal stability of the ALD TiN with capacitors of Poly-Si/TiN/SiO\({}_{2}\)[123]. The capacitors were annealed in the temperature range of 400 \({}^{\circ}\)C to 1000 \({}^{\circ}\)C in steps of 100 \({}^{\circ}\)C in an RTP furnace in N\({}_{2}\) ambient for 30 s. In addition, some samples were annealed in nitrogen diluted with 10 at% oxygen at 400 \({}^{\circ}\)C for 30 s. It was found that the work function of the TiN could remain p-type up to 700 \({}^{\circ}\)C and would shift to midgap after annealing at temperatures higher than 800 \({}^{\circ}\)C. This was concluded, based on the requirement of gate first process, as a disappointing result for the application, as the p-type metal gate cannot survive from the source/drain activation annealing at 1050 \({}^{\circ}\)C. In 2010, [PERSON] [124] reported a study on the thermal stability of the TiN/HfO\({}_{2}\)/Si stack, where HfO\({}_{2}\) was deposited by ALD using HfCl\({}_{4}\) and water, and TiN by ALD using TiCl\({}_{4}\) and NH\({}_{3}\). The work focused on the chemical stability of the stack after annealing at 1000 \({}^{\circ}\)C and revealed unsatisfactory thermal stability again. It needs to be noted that the above thermal stability studies misfocused at a wrong temperature range, based on the assumption that a metal gate step must be processed before the activation anneal. Actually, if a gate last process employed, the thermal stability of the p-type \(V_{t}\) up to 700 \({}^{\circ}\)C is quite positive. In 2015, [PERSON] compared the electric properties of the TiN/SiO\({}_{2}\)/Si MOS capacitor (MOSCAP) and CMOSFETs of FDSOI with the TiN deposited by PVD and PEALD to trace the plasma damage to the dielectric [125].