## 3 Materials and Methods
### Real-Time Digitisation and Harmonics Extraction with Embedded Processing  
We present a novel harmonic extraction technique, aimed at higher accuracy and better temporal resolution, by leveraging more on-chip processing to minimise data transfer burden between the DAQ and the high-level processor. Figure 2 shows the architecture for the proposed harmonic extraction process. As shown, both in-phase and quadrature sinusoidal signals corresponding to both the first and second harmonics (i.e., \(R_{I,f_{m}}[n]\), \(R_{Q,f_{m}}[n]\), \(R_{I2f_{m}}[n]\), and \(R_{Q2f_{m}}[n]\)) are digitally generated on-chip using AMD's Direct Digital Synthesiser (DDS) IP, also known as Numerically Controlled Oscillator (NCO) [18]. The output frequency, \(f_{out}\), of the DDS IP is  
Figure 2: Block diagram of real-time lock-in. designed to be configurable, outputting multiple output modulation frequencies as desired. The governing relation for the output frequency of the DDS IP is  
\[f_{out}=f_{clk}\frac{\Delta\theta}{M} \tag{8}\]  
where \(f_{clk}\) is the input clock to the IP, \(\Delta\theta\) is the phase increment, and \(M\) is the modulus. \(f_{clk}\) was set as 125 MHz, and \(M\) was chosen as 1000. By setting the values of \(\Delta\theta\) to 1, the frequency of the first harmonics reference sinusoids, i.e., \(R_{1,f_{m}}[n]\) and \(R_{Q,f_{m}}[n]\) was obtained as 125 kHz, while \(\Delta\theta\) was set as 2 to obtain the frequency of the second harmonic reference sinusoids, i.e., \(R_{1,2f_{m}}[n]\) and \(R_{Q,2f_{m}}[n]\) as 250 kHz. After performing a sample-by-sample multiplication for each of the components, a low-pass filter (realised using an accumulation filter as shown) is used to remove high-frequency components to obtain the first and second harmonic in-phase and quadrature components: \(S_{1,f_{m}},\ S_{Q,f_{m}},\ S_{1,2f_{m}}\), and \(S_{Q,2f_{m}}\). It must be noted that to achieve complete filtering using an accumulation filter (AF), the filter taps must align to the modulation cycles. Specifically, the integer, \(N\), in Equation (7) must be a multiple of \(f_{s}/f_{m}\)[12], where \(f_{s}\) is the ADC sampling rate. For a sampling rate, \(f_{s}=15.625\) MSPs and a modulation frequency, \(f_{m}=125\) kHz, the number of samples accumulated, \(N\), must be 125 times \(C\), where \(C\) is the integer number of modulation cycles. For this implementation, we chose a case of \(N=250\), i.e., \(C=2\). To further reduce the amount of data transferred to the high-level processor, and to actualise a phase-insensitive demodulation, the first harmonics components are combined using  
\[A_{1f_{m}}=\sqrt{S_{1,\ f_{m}}^{2}+S_{Q,\ f_{m}}^{2}}, \tag{9}\]  
where \(A_{0,1,f_{m}}\) is the first harmonic background amplitude. Three components: \(S_{1,2f_{m}},\ S_{Q,2f_{m}}\), and \(A_{1f_{m}}\) are then transmitted in real-time using TCP/IP protocol over Ethernet to a high-level processor. Note that for full-bit resolution, the number of bits of these components is \(28+\log_{2}N\). For \(N=250\), the number of bits to be transferred is 36 bits. It is worth nothing that for practical systems, the lower bits are truncated due to constraints such as bandwidth and embedded processor architecture [17; 19]. However, bit truncation decreases the accuracy of the gas sensing system. We demonstrate in the result section that by increasing the on-chip processing, a better gas sensing accuracy is achieved. For our implementation, the computation of \(A_{1f_{m}}\) (and \(A_{0,1,f_{m}}\)) are performed using the full bits of the first harmonic components \(S_{1,f_{m}}\) and \(S_{Q,f_{m}}\). Hence, the accuracy of \(A_{1f_{m}}\) (and \(A_{0,1,f_{m}}\)) is enhanced. In addition, by minimising the number of components to be transferred to the high-level processor, less bit truncation is required compared to the standard I-Q method for a fixed system bandwidth.