## 1 Introduction and Motivation  
Today, integrated circuit (IC) systems can be found in the majority of electrical devices, from industrial to agricultural areas, from military to civilian use, and from underwater to outer-space fields. They have become an indispensable part of our lives. There are many metal-to-metal contacting surfaces in IC systems, including interfaces between area array packages/printed circuit boards, peripheral component interconnect (PCI) slots, dual-inline-memory modules (DIMM) slots, etc. Under high humidity and high temperatures, foreign materials such as corrosion products may form on those contacting surfaces and grow with time, resulting in electrical failure. This type of failure is typically referred to as temperature-humidity induced failure. Since hot humid environments are commonly used conditions, temperature-humidity (TH) induced failure mechanism (FM) is a factor that must be considered in the product validation process.  
There are many circumstances where TH induced FM is actually the first FM to appear and it therefore becomes the gating FM of the system's reliability. For example, the author has come across many scenarios where TH induced FM turned out to be the most vulnerable one among all possible FMs in the product development stage. Great efforts were made to improve the electrical performance under TH. These experiences sparked the author's interest in studying the mechanism of TH failure, the modulating factors that affect the performance, the possible solutions, etc.  
This paper focuses on central processing unit (CPU)/motherboard interfaces. The context of study is based on test vehicles (TVs) of Clarkdale processor package and of Ibex peak motherboard. First, the TH failures that occur during the product development is described and the FM is investigated. Secondly, some main modulating factors are identified, together with supporting theories and possible solutions. Additionally, a new methodology that correlates asperity spots and contact tip design with contact resistance is proposed. Thirdly, the design of experiments (DOEs) of modulating factors are described and test results are analyzed. It turns out that one of the modulating factors has no significant effect on the performance, while the other two modulating factors have a significant effect on the performance. Further, one of the effective solutions is typical but costly, and the other one has proven to be reasonably efficient and cost effective.  
Some experiments conducted give a general idea of the proposal that is put forward by the first author when she was working at Intel Corporation. Some other experiments are conducted and a more systematic model is proposed by the authors at Shenyang Jianzhu University with the support from the Overseas Expertise Introduction Project for Discipline Innovation. However, for clarity of the thought process, the experiments and the proposal are not described in chronological order, but in logical sequence.  
The main contents of study are as follows:  
1. Introduce the test device and low level contact resistance (LLCR) measurement method.
2. Develop enabling load TH test plan and perform TH test program.
3. Analyze TH test results and investigate TH failure mechanism.
4. Identify main modulating factors for TH failure mechanism.
5. Propose a new methodology which correlates contact tip design with contact resistance.
6. Describe TH DOE of modulating factors and discuss the test results.