## 3 Proposed Design Method for Dual-Mode PUF
### Circuit-Level Techniques
#### 3.1.5 Comparison of Different Reliability Enhancement Techniques  
The SRAM cells incorporated with the four aforementioned techniques were simulated to compare their effectiveness in improving the SNM. For WLM and DVS, the word-line and supply voltages were swept by \(\pm 20\%\) from 0.7 V to 1.1 V. For NBL, the BL voltage is swept from \(-0.2\) V to 0.2 V. For ABB, the SNMs were simulated with BB applied to only NMOS, only PMOS and both NMOS and PMOS transistors, respectively. Due to the non-linear relationship between \(V_{th}\) and BB voltage, the BBs were swept for a large range from \(-0.5\) V to 0.5 V. By representing the deviation of BB by \(\Delta V\), the BB voltages, \(V_{bn}\) and \(V_{bp}\), for NMOS and PMOS, respectively, are given by:  
\[\begin{split} V_{bn}&=\Delta V,\\ V_{bp}&=\text{SRAMVDD}+\Delta V.\end{split} \tag{7}\]  
Figure 11: SRAM cell with adaptive body bias.  
The SNM obtained by applying each circuit-level enhancement technique is shown in Figure 12. The efficiency is measured by the SNM sensitivity \(S\) as follows:  
\[S=\left|\frac{\partial V_{SNM}}{\partial V_{X}}\right|, \tag{8}\]  
where \(V_{X}\) is the word-line voltage for WLM, supply voltage for DVS, bit-line voltage for NBL, or body bias voltage for ABB.  
It can be seen that all these techniques have improved the cell stability by strengthening or weakening certain transistors. Even though the strengthening or weakening effect can be applied in the row (by modulating WL voltage) or column (by modulating bit-line or cell power supply voltages) direction, column-based approaches are preferred because they can blend well with column multiplexing and write masking [17]. A comparison of the functionalities of different adaptive techniques is shown in Table 1.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Technique** & **Column-Based** & **S(Read)** & **S(Write)** & **Other Drawbacks** \\ \hline WLM & \(\times\) & 0.325 & 0 & - \\ DVS & \(\surd\) & 0.323 & 0.006 & - \\ NBL & \(\surd\) & 0 & 0.908 & - \\ \hline ABB (NMOS only) & \(\times\) & 0.009 & 0.016 & \\ ABB (PMOS only) & \(\times\) & 0.026 & 0.006 & Triple-well process, Large area overhead \\ ABB (Both MOSFETs) & \(\times\) & 0.114 & 0.015 & \\ \hline WLM, DVS, NBL and ABB refer to Word-Line Voltage Modulation, Dynamic Voltage Scaling, Negative Bit-Line and Adaptive Body Bias, respectively. \(S\) refers to the SNM sensitivity. & & \\ \hline \hline \end{tabular}
\end{table}
Table 1: Comparison of different adaptive techniques.  
Figure 12: Static noise margins by applying different circuit-level techniques: **(a)** Word-Line Voltage Modulation (WLM); **(b)** Dynamic Voltage Scaling (DVS); **(c)** Negative Bit-Line (NBL); **(d)** Adaptive Body Bias (ABB) (NMOS only) **(e)** ABB (PMOS only); **(f)** ABB (both NMOS and PMOS).  
From the table, it can be seen that the four adaptive techniques improve the SNM in their own ways. WLM is not column-based, but it is the most efficient in increasing the read SNM. DVS is efficient in increasing the read SNM but is inefficient in increasing the write SNM. NBL cannot increase read SNM, but it is the most efficient in increasing the write SNM. ABB is not efficient in increasing either the read SNM or write SNM, but it can be used to mitigate inter-die variations. Although DVS and ABB may not improve write SNM efficiently, they have the potential to reduce write failures. This is because write SNM is not a strong indicator of dynamic write ability [21]. The latter is better analyzed by the relative strength of access transistors and pull-up PMOS transistors.