# A Low-Phase-Noise 8 GHz Linear-Band Sub-Millimeter-Wave Phase-Locked Loop in 22 nm FD-SOI CMOS
###### Abstract  
Low-phase noise and wideband phased-locked loops (PLLs) are crucial for high-data rate communication and imaging systems. Sub-millimeter-wave (sub-mm-wave) PLLs typically exhibit poor performance in terms of noise and bandwidth due to higher device parasitic capacitances, among other reasons. In this regard, a low-phase-noise, wideband, integer-N, type-II phase-locked loop was implemented in the 22 nm FD-SOI CMOS process. The proposed wideband linear differential tuning I/Q voltage-controlled oscillator (VCO) achieves an overall frequency range of 157.5-167.5 GHz with 8 GHz linear tuning and a phase noise of \(-113\) dBc/Hz @ 100 KHz. Moreover, the fabricated PLL produces a phase noise less than \(-103\) dBc/Hz @ 1 KHz and \(-128\) dBc/Hz @ 100 KHz, corresponding to the lowest phase noise generated by a sub-millimeter-wave PLL to date. The measured RF output saturated power and DC power consumption of the PLL are 2 dBm and 120.75 mW, respectively, whereas the fabricated chip comprising a power amplifier and an integrated antenna occupies an area of 1.25 \(\times\) 0.9 mm2.  
phase-locked loop; voltage-controlled oscillator; frequency divider; phase noise; sub-millimeter-wave 2023202  
detector (PFD) should also be performed at high frequency. However, there is a speed limitation of the PFD, which is based on digital blocks at mm-wave and sub-mm-wave frequencies. In this regard, it is necessary to use frequency division to bring down the VCO output signal frequency to the desired frequency suitable for the PFD operation. Nevertheless, conventional frequency division is performed by a current-mode logic (CML), which is limited in operating frequency and presents high non-linearity [8]. For these reasons, several recent mm-wave FSs use injection-locked frequency dividers (ILFDs) or Miller frequency dividers [1; 9]. Nevertheless, the implemented PLLs have narrow locking ranges, limiting their bandwidths and operating frequencies. Moreover, a CMOS-compatible spintronic-based signal generator was proposed in [10]. Although the proposed device size is in the nanoscale with two degrees of freedom tuning ability, it requires high-gain amplification to bring the output power closer to 0 dBm, therefore increasing the overall power consumption and non-linearities. Furthermore, an optical solution was proposed in [11] to design a low-phase-noise wideband-modulated waveform generator centered at 40 GHz for synthetic-aperture radars (SARs) applications. Besides its CMOS incompatibility, the designed oscillator presents a large footprint unlike integrated RF PLLs.  
In this work, a type II PLL with wide locking range operating in the sub-mm-wave frequency is implemented in the 22 nm FD SOI CMOS process. The frequency performance of the PLL is improved by the design of wideband quadrature VCO along with a wide locking range ILFD with PMOS input injection.  
The rest of this paper is organized as follows: Section 2 discusses the system architecture and the circuit implementation of the essential building blocks; Section 3 shows the measurement results; and Section 4 summarizes the work.