# Secure and Dynamic Memory Management Architecture for Virtualization Technologies in IoT Devices
## 7 Performance Analysis  
_ModelSim_ is a multi-language HDL (Hardware Description Language) simulation environment for the simulation of electronic circuits. _Verilog_, a hardware description language available in _ModelSim_ to model electronic systems, was used here for the simulation and verification of the correctness of the ASMI memory access operation. The following three Verilog modules constitute the memory access operations of ASMI in _ModelSim_.  
* _calculate_seg_ID:_ This module receives the physical address as input and calculates the segment ID.
* _data_memory:_ This module fetches the data from memory
* _compare:_ This module compares the given VMID value with the one in the VMIDR register.  
Memory was organized as \((2^{m})\times(n)\), where \(m\) is the address bus size and \(n\) is the data bus size. We used the \(m,n\), and \(segment\_ID\) sizes 8.8, and 4, respectively.  
_Xilinx_, an integrated synthesis environment (ISE) used for the synthesis of electronic circuits, was used to obtain the delay of different electronic modules simulated using _ModelSim_. This delay is the time difference between the output obtained and the input provided for the respective modules. From the synthesis, the time taken for the operation of each module of ASMI was obtained as follows.  
* _calculate_seg_ID:_ 7.045 ns;
* _data_memory:_ 5.835 ns;
* _compare:_ 8.627 ns.  
In normal memory access, only the _data_memory_ module operation exists. For ASMI, however, the other two additional module operations (calculate_seg_ID & compare) are added to the _data_memory_ operation. We analyzed the memory access operation in detail from the perspective of an operating system in three different environments. One was in a normal machine, another was in a virtual machine, and finally one in an ASMI-enabled virtual machine.  
A memory access operation on any operating system consists of an address translation function and a data fetch operation from memory. In a regular machine, address translation is a paging mechanism, where each address translation constitutes four memory access operations [33]. In a virtual environment, the address translation mechanism is a nested page table mechanism, where each address translation constitutes 24 memory access operations [33].  
The ASMI memory access operation replaces the nested page table mechanism with a standard page table mechanism with an additional verification function. The ASMI address translation function comprises four memory access operations. Additionally, the three modules mentioned above were used for verification. Hence, based on the simulation results, the time taken for memory access in normal, nested, and ASMI paging were as follows.  
* Normal Paging = 4 \(\times\) 5.835 ns = **23.34 ns*** Nested Paging = 24 \(\times\) 5.835 ns = **140.04 ns**
* ASMI Paging = 4 \(\times\) 5.835 + (7.045 + 8.627 + 5.835) ns = **44.847 ns**  
A graphical representation of the time taken by the three address translation mechanisms is shown in Figure 7. The ASMI memory architecture required less time for memory access compared to the nested paging memory access. This shows that ASMI architecture could provide better security and performance to virtual machines than the currently available architectures.  
The results of this preliminary analysis motivates further study on the applicability of the ASMI architecture in embedded processors. Based on the positivity of the obtained results, it is proposed to conduct a full-fledged simulation study of the performance of real programs running on the ASMI-enhanced MIPS virtualization architecture.