# A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR
## 4 Conclusions  
We have presented an energy-efficient, small-area 100 Gb/s quad-lane SerDes receiver with a PI-based quarter-rate all-digital CDR. The proposed PI-based CDR utilizes a multi-phase MDLL to achieve lower clock jitter, a smaller area, and a lower power consumption. The proposed digital CDR uses a new preamble-based initial tracking mode to achieve a fast lock time of less than 12 ns, which is suitable for use in burst-mode applications. The CDR uses a quarter-rate 2x-oversampling architecture and a new full custom PI controller with an adjustable update rate, resulting in a reduced dithering jitter. A new small-area low-power CTLE using an NG receiver was adopted to achieve a data rate of 25 Gb/s/lane. Implemented in 40 nm CMOS technology, the four-channel SerDes receiver achieves an aggregate data rate of 100 Gb/s and occupies an active core area of only 0.351 mm\({}^{2}\). It consumes only 241.8 mW and achieves a high energy efficiency of 2.418 pJ/bit.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Reference** & [5] & [28] & [29] & [32] & **This Work** \\ \hline Process and supply & 130 nm/1.2 V & 28 mW/1.0 V & 90 nm/1.0 V & 65 nm/1.2 V & 40 nm/1.0 V \\ Data rate (Gb/s) & 7 & 13 & 44 & 40 & 25 \\ CDR architecture & PI-based & PI-based & PI-based & PI-based & PI-based \\ Sampling rate & Baud-rate & Half-rate & Quarter-rate & Quarter-rate & Quarter-rate \\ DEMUXing ratio & 1:1 & 1:20 & 1:16 & 1:4 & 1:4 \\ Multi-phase generation & PLL & PLL & & & \\  & (LC-VCO) & (LC-VCO) & 8-phase DLL & 1/2 Divider & 8-phase MDLL \\ External reference clock & 150 MHz & N/A & 10 GHz & 20 GHz & 625 MHz \\ frequency & 13.7 & - & - & 159 & 34.2 \\ CDR power (mW) & 39.6 & 27 & - & 30 & 24.2 \\ Multi-phase gen. power (mW) & 53.3 & 59 & 230 & 189 & 58.4 \\ Energy efficiency (pJ/bit) & 7.6 & 4.53 & 5.74 & 4.7 & 2.34 \\ Lock time & - & - & - & - & 12 ns \\ \hline \hline \end{tabular}
\end{table}
Table 1: CDR performance summary and comparison.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Reference** & [5] & [22] & [28] & **This work** \\ \hline Process and supply & 130 nm/1.2 V & 65 nm/1.0 V & 28 m/1.0 V & 40 nm/1.0 V \\ CDR architecture & PI-based & PI-based & PI-based & PI-based \\ Equalization & CTLE & CTLE & CTLE + DFE & CTLE \\ Aggregate data rate (Gb/s) & 28 & 140.8 & 52 & 100 \\ Number of data channels & 4 & 22 & 4 & 4 \\ Data rate/channel (Gb/s) & 7 & 6.4 & 13 & 25 \\ Total Power (mW) & 271.5 & 635 & 155 & 241.8 \\ Energy Efficiency (pJ/bit) & 9.7 & 4.5 & 2.98 & 2.418 \\ Chip Area (mm\({}^{2}\)) & 2.41 & 2.96 & 0.226  & 0.351 \\ \hline \hline \end{tabular}
\end{table}
Table 2: SerDes receiver chip performance summary and comparison.  
**Author Contributions:** Conceptualization, J.K.; methodology, H.H.; validation, J.K. and H.H.: formal analysis, H.H.; investigation, J.K and H.H.; data curation, H.H.; writing--original draft preparation, J.K and H.H.: writing--review and editing, J.K.; supervision, J.K.; project administration, J.K.; funding acquisition, J.K. All authors have read and agreed to the published version of the manuscript.  
**Funding:** This research was funded and conducted under \"the Competency Development Program for Industry Specialists\" of the Korean Ministry of Trade, Industry and Energy (MOTIE), operated by Korea Institute for Advancement of Technology (KIAT). (No. N0001883, HRD program for N0001883). This work was also supported by National Research Foundation of Korea (NRF 2019R1A2C-1010017). The EDA tools were supported by IDEC.  
**Conflicts of Interest:** The authors declare no conflict of interest.