# Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation
## 4 Conclusions  
In this paper, we investigated the effect of interface trap charge distribution extracted from the experimental data of the M3 DIC fabricated by LETI [14] in terms of electrical characteristics and extracted the distribution with TCAD at two types of \(T_{\text{ILD}}\). To simulate the circuit considering the effect of the interface trap charge in M3 DICs, SPICE model parameters of P-type MOSFET (bottom) and N-type MOSFET (Top) in M3 DINV, including the interface trap charge distributions, were extracted by using TCAD simulation. To verify the validity of the extracted parameters in the SPICE M3 DINV model, the HSPICE simulation results were compared with the TCAD mixed-mode simulation, and they agreed well with the TCAD mixed-mode results. When the interface trap charges were considered, the current level decreased, the threshold voltage shifted, the \(SS\) became worse, and the total gate capacitance changed slightly. It was observed that the propagation delays of M3 DINV with the interface trap charges increased more than those without the interface trap charges owing to a reduced on-current level due to the interface trap charges. Using the extracted parameter model, the HSPICE simulation results of the FO3 ring oscillator considering the interface trap charges showed a 20% (and 25%) reduction in frequency and a 30% (and 36%) increase in propagation delay than those without the interface trap charges at \(T_{\text{ILD}}\) = 10 (and 100) nm. The propagation delays of the \(2\times 1\) MUX and D flip-flop with the interface trap charges were approximately 78.2% (and 92.1%) and  
Figure 9: Simulated butterfly curves of the 6T SRAM cell with M3 DINV. (**a**) The retention SNM and (**b**) read SNM at \(T_{\text{ILD}}\) = 10 nm. (**c**) The retention SNM and (**d**) read SNM at \(T_{\text{ILD}}\) = 100 nm. Symbols and lines denote the SRAMs both with and without interface trap charges, respectively.  
39.6% (and 64.2%) greater than those without the interface trap charges, respectively. The power consumption of the 2 \(\times\) 1 MUX and D flip-flop with the interface trap charges was approximately 31.4% (and 51%) and 13.1% (and 14.7%) greater, respectively, than those without the interface trap charges. The retention SNM of the SRAM increased by 16 mV (6.4%) and the read SNM of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The retention SNM of the SRAM increased 10 mV (3.6%) and the read SNM of SRAM decreased by 40 mV (55%) owing to the interface trap charge at \(T_{\text{ILD}}\) = 100 nm. For the coupling (\(T_{\text{ILD}}\) = 10 nm), the stage propagation delay and power consumption increased. The delays and power consumptions of M3D logics with \(T_{\text{ILD}}\) = 10 (coupling) and 100 nm (non-coupling) increased owing to the interface trap charges.  
Therefore, it is necessary to fully analyze the electrical performance (such as the delay, power, the integration of logic circuits, and the stability of the SRAM considering electrical coupling [11; 12] and interface trap charges) when designing M3 DIC and M3D memories.  
Conceptualization, T.J.A., S.K.L. and Y.S.Y.; methodology, T.J.A. and Y.S.Y.; investigation, T.J.A. and Y.S.Y.; data curation, T.J.A.; writing--original draft preparation, T.J.-A.; writing--review and editing, T.J.A., S.K.L. and Y.S.Y.; supervision, Y.S.Y.; project administration, Y.S.Y.; funding acquisition, Y.S.Y. All authors have read and agreed to the published version of the manuscript.  
This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2016R1D1A1B03932711 and NRF-2019R1A2C1085295).  
Not applicable.  
This work was supported by IDEC (EDA tool).  
The authors declare no conflict of interest.