# Small-Size Square Ring 1-Bit Reconfigurable Transmitarray Unit Cell for C-Band Applications
## 3 Switching States Approach  
The proposed unit cell provides either two opposite phase-shift states, marked as 0\({}^{\circ}\) and 180\({}^{\circ}\), depending on the connection of the U-shaped resonators placed at receiving and transmitting sides of the unit cell. The 180\({}^{\circ}\) phase shift is obtained by switching the feed point of the U-shaped resonator on one side of the transmitarray by using two p-i-n diodes, while at opposite sides of the unit cell U-shaped resonator is connected to the via hole by transmission line section (Figure 3a). The state is referred to as the 0\({}^{\circ}\) state when the resonators on both sides are connected in the same way so that the currents flowing in the antennas are codirectional. In the 180\({}^{\circ}\) state, the resonators are connected by opposite ends in such a way that currents flow in opposite directions. The two p-i-n diodes are connected in codirectional ways as shown in Figure 3b to provide p-i-n diodes opposite states operation. The forward biasing provides ON state for V\({}_{2}\) and OFF state for V\({}_{1}\) and vice versa. Depending on the sign of the bias voltage, the radiating current is in-phase or out-of-phase, which leads to a 1-bit differential phase shift. Figure 2: The dependence of the unit-cell insertion loss on cutout lateral size for different substrate thickness. Two AlGaAs flip-chip p-i-n diodes Macom MA4 AGP907 are integrated into the unit-cell. A single very thin bias line is used to apply biasing voltage to the p-i-n diodes and does not interact with the antenna elements. To provide a decoupling \(DC\) and microwave currents the inductors (12 nH) are used. The \(DC\) control voltage is applied through inductances \(L_{1}\), \(L_{3}\) (two identical inductances are used for scheme symmetry), while \(L_{2}\) is grounded. Typically, an additional bypass shunt capacitance in the biasing network improves isolation. Moreover, the additional bypass capacitance allows avoiding a mutual coupling between neighbour unit-cells arranged to an array. To minimize the number of surface-mounted device (SMD) components, the bypass capacitor is implemented as a parallel plate capacitor between two metalized planes in the middle of the structure by introducing a gap in one ground plane while keeping another one without a gap. The bypass capacitance value with considering parallel plate capacitance (\(C_{p}\)) and gap capacitance (\(C_{g}\)) is estimated as 60 pF. Such an approach simplifies the unit cell \(DC\) biasing circuitry. Additionally, a biasing line is connected to the distributed parallel plate capacitor away from resonant structures, which avoids the interaction of the biasing line with the patch antenna elements. Certainly, the p-i-n diodes bring additional loss to the transmission coefficient of the unit cell by reducing the unloaded Q-factor of the resonator (which is a patch antenna). Typically, an increased loss is associated with ohmic loss in an open state, the off-state isolation, and parasitic parameters in both states. Thus, p-i-n diodes were modelled with a serial resistance 3.6 Ohm for on-state, off-state capacitance 27 pF and serial parasitic inductance 0.31 nH for both states. The mismatching due to the contribution of parasitic parameters of the p-i-n diodes leads to higher overall insertion loss equal to 1.6 dB. To improve the passband loss and decrease mismatching caused by p-i-n diode parasitic parameters the size of patch antenna at one side of the structure has been changed. The results of the simulation of the unit cell scattering parameters modules are represented in Figure 4. The insertion loss is equal to 1.3 dB at 5.9 GHz in both states while the reflection coefficient does not exceed \(-\)20 dB within the passband. The 3-dB transmission bandwidth is equal to 200 MHz (3.4%). The phase error does not exceed \(\pm\)1\({}^{\circ}\) in the passband. Figure 3: The proposed reconfigurable 1-bit unit cell structure (**a**), \(DC\) biasing network design of the unit-cell (**b**).