# A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications
## 5 Simulations of the Proposed Fully Digital BPSK Demodulator  
Transient simulations were run using Cadence Virtuoso, in order to carry out parameters and the timing diagram, as reported in Figure 13. Corner simulations were executed to demonstrate the robustness of the proposed design against process variations, concentrating them around body temperature, \(T=37\)\({}^{\circ}\)C. Furthermore, the human-body thermometer range (i.e., \(T\in[30\)-\(50\)\({}^{\circ}\)C)) was chosen as the temperature investigation field in order to remark that system performances and functionalities are maintained against the temperature variations too. The performance parameters considered for the Corner simulations, as shown in Table 4, are: the oscillation frequency of the CSGRO, the time-delay between the rising edges (or falling-edges) of _MOD_ and _RX-BIT_ signals, the average overall power consumption, \(P_{DD}\), and the energy-per-bit, \(E_{b}\), defined as the ratio \(P_{DD}\)/Data Rate.  
Figure 13: Timing-Diagram of the simulatedFully Digital BPSK modulator.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline \multicolumn{2}{c}{**TSPC D-FF**} & \multicolumn{2}{c}{**XOR Gate**} \\ \hline \multirow{2}{*}{**Transistor**} & **Aspect Ratio** & \multirow{2}{*}{**Transistor**} & **Aspect Ratio** \\  & [\(\mu\)m/\(\mu\)m] & & **[\(\mu\)m/\(\mu\)m]** \\ \hline \(M_{1}\) & 0.32/0.9 & \(M_{1}\)–\(M_{4}\) & 0.64/0.6 \\ \(M_{4}\), \(M_{5}\), \(M_{7}\), \(M_{8}\) & 0.64/0.9 & & \\ \(M_{11}\) & 0.32/0.45 & & \\ \(M_{2}\), \(M_{3}\) & 1.92/0.9 & \(M_{5}\)–\(M_{8}\) & 1.92/0.6 \\ \(M_{6}\), \(M_{9}\) & 0.96/0.9 & & \\ \(M_{10}\), \(M_{12}\) & 0.96/0.45 & & \\ \hline \hline \end{tabular}
\end{table}
Table 3: Aspect ratios of TSPC D-FF and XOR transistors.  
In Figure 14 it is possible to observe a time-delay of about 5 ns between the pre- and post-layout signals, named \(V_{p2}\) and \(V_{p2}^{*}\), respectively. On the other hand, pulses presented in Figure 15 have different time durations, which suggests a spread of the oscillation frequency, \(f_{pulse}\). Such a difference can be ascribed to an increment of the loading capacitance associated to the output nodes of the ring oscillator core. However, to compensate this spread, the current \(I_{REF}\) can be raised up to 425 nA, in order to maintain the oscillation frequency about equal to the pre-layout value, thus 4 MHz (7). After post-layout calibration, corner transient simulations were run and the achieved results are reported in Table 5. It is possible to observe good robustness against PT variations, although a slight increment was introduced both in the bias current, \(I_{REF}\), and in the oscillation frequency, \(f_{OSC}\), as compared to the results in Table 2.  
Looking at the power consumption, it is mainly dominated by the CSGRO as understood by inspection of the power breakdown pie chart depicted in Figure 16. A remarkable total power consumption equal to \(P_{DD}\approx 3.3\,\upmu\)W was achieved.  
Finally, the entire layout top-view of the proposed fully Digital BPSK demodulator is shown in Figure 17. The silicon occupied area is estimated to be 1848 \(\upmu\)m\({}^{2}\). The Figure presents red dashed boxes to highlight the constitutive blocks of the circuit shown in Figure 6.  
Figure 16: Power consumption breakdown associated to each sub-block.  
Figure 15: Pre-Layout (\(V_{pulse}\)) vs. Post-Layout (\(V_{pulse}^{*}\)) transient simulation results.