## 8 Results
### Bit Error Rate  
Ultimately, the bit error rate of the link was measured for six different coil separation distances from 5 mm to 30 mm with a step size of 5 mm with the coil system of Figure 17; the circuits of Figure 16 are connected as transmitter and receiver. For each measurement configuration, \(3\times 10^{5}\) packets with a length of 64 bytes each (\(1.6\times 10^{8}\) bits), composed according to a pseudo-random bit sequence (PRBS-15), were transmitted and analyzed using five different receiver board samples. The input data were generated and injected by the microcontroller circuit of the test platform; transmitted and received data including their clock signals were captured and decoded by a _Saleae Logic Pro 8_ logic analyzer and a custom Python script comparing outgoing and incoming data. The bit error rate was also determined theoretically: For every coil separation distance, the mutual inductance was computed from (6), the comparator input voltage was obtained from the relation of Figure 19, and the BER was finally derived from the mathematical model presented in Section 6. The phase noise parameter \(\sigma_{\mathrm{P}}=2\pi\times 0.04\) was acquired from the single sideband spectrum of the FPGA's internal 13.56 MHz clock signal routed to an FPGA output, recorded by a spectrum analyzer and processed according to ([34], p. 46); the amplitude noise metric \(\sigma_{\mathrm{A}}=8\) mV was acquired from the spectral power density of the signal \(u_{\mathrm{c,in}}\) recorded by an oscilloscope without any incoming data signal. The results of both measurement and simulation are shown in Figure 22: The NFC interfaces achieves a bit error rate as low as  
\[\mathrm{BER}(d=10\;\mathrm{mm})\approx 2\times 10^{-7} \tag{41}\]  
for coil separation distances of up to 10 mm, and converges to the theoretical maximum of 0.5 at 30 mm. For a hysteresis of \(U_{\mathrm{H}}=20\) mV, the simulation delivers a suitable estimation of the system's bit-error rate for all coil distances. To characterize the receiver only, BER was analyzed versus the input voltage of the comparator stage. Here, hysteresis \(U_{\mathrm{H}}\) and noise parameters \(\sigma_{\mathrm{P}}\) and \(\sigma_{\mathrm{A}}\) are varied from the nominal values in simulation to show the impact of further system optimization. From the results shown in Figure 23, it can be noted that  
* a smaller hysteresis increases BER for large signals as noise can rather lead to the incorrect detection of the input signals, but lowers BER for smaller amplitudes, as a smaller hysteresis allows small signals to exceed the toggling thresholds. Figure 22: Bit error rate versus coil separation distance \(d_{34}\) in simulation and measurement to characterize the complete link. The simulated data are obtained from the mathematical description of this work and the parameters \(\sigma_{\mathrm{P}}=2\pi\times 0.04\), \(\sigma_{\mathrm{A}}=8\) mV and \(U_{\mathrm{H}}=20\) mV; the experimental values of the BER include the measurement with five different receiver PCBs and \(1.2\times 10^{8}\) bits of a PRBS-15 sequence each. * the best-case bit error rate for large signal amplitudes is limited by the standard deviation of phase noise. * the size of amplitude noise determines the BER's behavior in the transition region according to the behavior of the signal-to-noise ratio. A reduction of phase noise by appropriate modification of the oscillators and a reduction of amplitude noise by improved supply decoupling could therefore help to improve the system's reliability even further. Apart from improvements of the physical link, error-detecting codes such as cyclic redundancy checks or even error-correcting codes [35] can be utilized to improve the effective BER, but at the cost of additional data overhead reducing the effective data rate. Figure 23: BER vs. comparator input voltage for varying hysteresis, phase noise or amplitude noise parameters according to the model of Section 6.