## 5 Experimental Results and Analysis  
This study used SIMULINK-based simulation for verification. The input sine wave frequency was 53 MHz. The TIADC system consists of four ADCs. The simulation did not use over-sampling technology, so the conversion speed and sampling rate were the same; the overall sampling rate of the TIADC was set as 1 GHz, i.e., the sampling time interval of each ADC in TIADC system was 1 ns; the sampling rate of each internal ADC was set to 250 MHz; the resolution was set to 16 bit; and the range was \(\pm\)1 V. The time-domain figure of a single ADC with a nonlinear mismatch is shown in Figure 6.  
Figure 5: Overall error reconstruction and compensation structure of the TIADC. Figure 6: The time-domain figure of a single ADC with a nonlinear mismatch. According to the Nyquist sampling theorem, in the analog-to-digital conversion process, when the sampling frequency \(f_{s}\) is more than twice the highest frequency \(f_{max}\) in the continuous signal input, the digital signal after sampling can restore the original signal completely. Thus, this experimental analysis intercepted a sampling rate that was only half of the spectrum, namely from 0 MHz to 500 MHz, and the other meaningless part of the spectrum was discarded. After adding memory effect errors and nonlinear effect errors to the TIADC model, its time-domain figure is shown in Figure 7. As shown in the figure, due to the existence of mismatch error and noise, the output digital signal cannot effectively match the input continuous analog signal. Compared with a single ADC with memory nonlinear error in Figure 6, the output waveform distortion of the TIADC system with memory nonlinear mismatch is higher. Its spectrum is shown in Figure 8, where the input signal produces a peak spectrum at 53 MHz and the others are the spectra of noises generated by the mismatch error. According to the analysis in Section 2.3, the noise generated by the 0 th-order memory nonlinear mismatch error is located at 0 MHz, 250 MHz and 500 MHz. The noise generated by the first-order mismatch error is located at 197 MHz, 303 MHz and 447 MHz. The noise generated by the second-order mismatch error is located at 106 MHz, 144 MHz, 356 MHz and 392 MHz. The coefficients for each of the four channels are defined as: \(h_{1}=[47\times 10^{-5},-34\times 10^{-5},33\times 10^{-5},-26\times 10^{-5}, 79\times 10^{-6},-33\times 10^{-5},17\times 10^{-6},-42\times 10^{-7},-12\times 10^{-7 },1\times 10^{-7}]\), \(h_{2}=[43\times 10^{-5},42\times 10^{-5},-36\times 10^{-5},27\times 10^{-5},-91 0^{-6},-21\times 10^{-5},-28\times 10^{-6},-36\times 10^{-7},\ 23\times 10^{-7}]\), \(h_{3}=[33\times 10^{-5},-23\times 10^{-5},-33\times 10^{-5},-28\times 10^{-5},-77 \times 10^{-6},34\times 10^{-5},39\times 10^{-6},-47\times 10^{-7},13\times 10^{- 7},-9\times 10^{-7}]\), \(h_{4}=[43\times 10^{-5},37\times 10^{-5},44\times 10^{-5},\)\(39\times 10^{-5},62\times 10^{-6},43\times 10^{-5},-16\times 10^{-6},58\times 10^{-7},-26 \times 10^{-7},-13\times 10^{-7}]\). At this point, due to the influence of memory nonlinearity, the effective number of bits (ENOB) of this TIADC with 16 bits is only 10.06 bits. Its spurious-free dynamic range (SFDR) is 64.29 dB, and its signal-to-noise ratio (SNR) is 62.35 dB. After the first offline LS calibration, the second-order Volterra series kernel could not be effectively fitted by the LS method due to the small number of sampling points set, and divergence occurred in the fitting operation. Fortunately, since the ADC is a strongly linear system, the parameters that largely deviate from the standard linear system parameters can be easily excluded when applying the fitted parameters to the calibration structure. For the error parameters with small deviations that are not excluded, after a certain period of recursive operation, the system can also converge to the exact error parameter values. Figure 7: Time-domain figure of the TIADC model with memory nonlinearity mismatch.