## 2 Fine-Timestamp Maker Design
### Performance Evaluation  
One fine-timestamp maker was implemented on a homemade development board with a Xilinx Kintex-7 FPGA (xc7k325 tfgg900 made in U.S.A.). We conducted a code density  
Figure 10: Schematic diagram of the ring oscillator. Figure 9: Schematic diagram of the DU-IP-based RO. test via an arbitrary waveform generator to evaluate its various performances. Following this, the hit signals were generated with a frequency of 100.11 KHz to ensure there was no relation to the system clock and fed into the FPGA through the SMA connector. Hence, the time distance to be measured by the fine-timestamp maker is evenly distributed across one clock cycle. Accordingly, the bin widths in the fine-timestamp maker are proportional to the number of hit signals that fell into these bins. Let the actual bin width be \(W\), the total number of samples input in the code density test be \(N\), and \(n\) is the number of hit signals falling into these bins. Then,  
\[W=\frac{n\cdot\Delta T_{\text{max}}}{N} \tag{1}\]  
where \(\Delta T_{\text{max}}\) represents the maximum working time of a certain module. This code density test was conducted at an ambient temperature of 20 \({}^{\circ}\)C with a sample size of one million. Theoretically, the width of each bin should be the resolution of the TDC, but not all bin widths are equal due to some noise and jitter. Therefore, differential nonlinearity (DNL) error and integral nonlinearity (INL) is introduced to quantify these differences. The DNL is defined as the difference between actual bin width and standard bin width, and the INL is defined as the summation of the DNL from the first bin to the current bin. The performance evaluation of the fine-timestamp maker includes two parts: the acceleration module and the Vernier-measuring module. The DNL and INL of the acceleration module are shown in Figure 11, where the DNL ranges from \(-\)0.15 LSB to 0.14 LSB, and INL ranges from \(-\)012 LSB to 0.15 LSB. It seems that the measurement accuracy of the Vernier-measuring module could become better when a higher resolution is selected. However, since it will incur a larger  
Figure 11: Measured (**a**) DNL and (**b**) INL for the acceleration module. oscillation number and jitter accumulations for the same working time, the worsening RMSE could not be ignored. The RMSE value of the Vernier-measuring module is shown in equation [21]:  
\[\sigma=k\cdot\sqrt{\frac{\Delta T_{\text{max}}}{res}\cdot T_{cyc}}=k\cdot\sigma_{0} \tag{2}\]  
where \(k\) is a circuit-dependent constant factor only affected by the whole circuit noise. The \(res\) represents the resolution of ultra-fine time and \(T_{cyc}\) is the oscillation period of ROs. \(\sigma_{0}\) is the measurement error factor (the larger the value means the larger the measurement error under the same circuit). In this design, since the reference clock signal for the ring delay line is the system clock signal with a constant period of 2000 ps, then \(T_{\text{cyc}}\) = 2000 \(-\)\(res\). Accordingly, reducing the \(\Delta T_{\text{max}}\) for the same resolution goal plays a crucial role in the improvement of the measurement error factor \(\sigma_{0}\). For the conventional RO-based TDCs [21; 22; 23], the maximum working time for \(\Delta T_{\text{max}}\) to be measured by the Vernier-measuring module is the entire clock period of the system clock. In this study, with the help of the acceleration module, the clock period of the system clock could be divided into four parts (as shown in Figure 1b). The value of \(\Delta T_{\text{max}}\) is only \(T_{\text{clk}}/4\), and the \(\sigma_{0}\) of the Vernier-measuring module could also be reduced by half for the same res target. We could potentially select the double higher resolution without worrying about its RMSE exceeding 1 LSB. Previously, a more appropriate resolution was between 30 ps and 40 ps to ensure a reasonable RMSE [21]. Note that this resolution range will be reduced to 15-20 ps now.