# Improving Hardware in LUT-Based Mealy FSMs
## 6 Experimental Results
We think this is because (1) \(U_{3}\)-based FSMs have more flip-flops compared to the equivalent \(U_{2}\)-based FSMs and (2) the switching activity of flip-flops from \(U_{3}\) is significantly higher than it is for equivalent \(U_{2}\)-based FSMs. However, the application of our method allows reducing the power consumption compared to the FSM circuits based on auto (26.03%), one-hot (36.45%) and JEDI (6.26%). Let us point out that Table 18 shows the power consumption characteristics for FSMs as stand-alone units. If we consider an FSM as some part of a digital system, then the situation can change significantly in favor of our method. This conclusion can be made from the analysis of Table 17.  
So far, we have only discussed estimates for one of the FSM circuit characteristics. However, the quality of FSM circuits is often evaluated by integral estimates. One such assessment is that which shows how much chip area is used to achieve a certain cycle time. In the case of LUT-based FSM circuits, the required FPGA chip area is usually estimated by the number of LUTs used [12]. This approach is adopted in our article, and the results are shown in Table 19.  
As follows from Table 19, our approach provides an average gain of 7.17% compared to the equivalent \(U_{2}\)-based FSMs. The gain compared to other methods is even more significant: (1) 73.82% compared to auto; (2) 101.39% compared to one-hot and (3) 25.94% compared to JEDI. We do not provide here tables for each of the FSM groups. However, we conducted such a study, and its results showed the following. Our approach is an outsider for the group G0, where we lose (1) 32.45% compared to auto; (2) 3.79% compared to one-hot; (3) 33.96% compared to JEDI and (4) 2.04% compared to \(U_{2}\)-based FSMs. Winning starts with group G1. In this group, our method wins (1) 36.84% with respect to auto; (1) 75.98% with respect to one-hot; (1) 4.08% with respect to JEDI; and (4) 1.57% compared to the equivalent \(U_{2}\)-based FSMs. The greatest gain is observed for the most complex FSMs belonging to the groups G2-G4. For these groups, our method wins (1) 97.68% with respect to auto; (1) 120.88% with respect to one-hot; (1) 39.76% with respect to JEDI; and (4) 10.13% compared to the equivalent \(U_{2}\)-based FSMs. So, the gain from the application of our method increases as the FSM complexity increases. The power-time (power-delay) product shows how much energy is spent on the execution of one cycle of operation [62]. In case of discussed benchmarks, the cycle time is measured in nanoseconds. Since the power is measured in Watts, the resulting power-time products are presented in nanojoules (nI). These results are shown in Table 20.  
As follows from Table 20, the \(U_{3}\)-based FSMs have higher energy values than the equivalent \(U_{2}\)-based FSMs (the loss is on average 10.44%). We think this is because (1) \(U_{3}\)-based FSMs have more flip-flops compared to the equivalent \(U_{2}\)-based FSMs, and (2) the switching activity of flip-flops from \(U_{3}\) is significantly higher than it is for the equivalent \(U_{2}\)-based FSMs. However, \(U_{3}\)-based FSMs require less energy compared to FSM circuits based on auto (43.64%), one-hot (56.70%) and JEDI (8.29%). For a better understanding of the experimental results, we created Table 21. The first column of this table contains the total values for each of the studied characteristics. The remaining columns contain the values of these characteristics for each of the studied methods. The best values for each of the characteristics are shown in bold. The goal of our method is to reduce the number of LUTs without a significant decrease in frequency in relation to three-level \(U_{2}\)-based FSMs. Due to it, in the \"Gain\" column, we show the gain or loss (negative gain) of our method with respect to \(U_{2}\)-based FSMs. As follows from Table 21, our method allows reducing the LUT counts (the chip area occupied by FSM circuit) compared to equivalent \(U_{2}\)-based FSM having three logic blocks.