## 3 Proposed Instrumentation
### Test Setup and Instrumentation  
Figure 1 presents the proposed experimental setup. The system is composed of two main boards: a controller board, hosting an FPGA, and a test board, where the SRAM and measuring components were included. The test board was used to provide the electrical interface for the additional devices and facilitate a stable attachment of the controller board. This board includes the hardware for the load switches, current sensors, serial converters, and the DUT (SRAM) itself. We used dedicated digital current sensors, which allowed precise measuring and a convenient interface with the controller. The serial converters were used to provide the connection with a host computer through a robust protocol for receiving data and sending commands. The host computer continuously saves, manages, and displays the acquired experimental data. When required, the experiment operator can interact with the system using the host computer with a set of commands (e.g., start a specific test, stop a run, perform a functional test, change test parameters). Using this scheme, we achieved a compact, robust, and precise experimental setup, enabling tests in constrained spaces (e.g., the vacuum chamber used for heavy-ion irradiation) with enhanced observability and simplifying the test equipment.  
Figure 2 details the architecture of the proposed instrumentation. In the controller board, we implemented: a timing management module for synchronizing all internal modules; two serial interfaces for sending the test data to the host computer; an SRAM controller for handling the memory operations; a test engine to execute various test algorithms; and the necessary logic for handling the measurements and load switches. It is worth mentioning that the controller was implemented in a COTS flash-based FPGA, in which the configuration memory is more robust to radiation effects [22], and the design included Triple Modular Redundancy (TMR) in the most critical elements to ensure proper operation during the tests. Hence, the controlling loop used the test algorithms and current monitoring to define the execution throughout the experiment and trigger the SEL protection and reporting.  
This setup was proposed to allow flexibility, precise and coherent measurements, and functionally representative test stimuli. Since the experiments focus on SEL characterization, we designed a test board where current monitoring is carried out in the memory supply line and inputs/outputs (IOs). This is achieved by placing the current sensors in the supply lines of both the SRAM itself and the IO banks of the FPGA that interface to the memory. This additional IO monitoring and protection was used since these IOs contribute to thecurrent consumption of the memory (as later shown in Section 3.3) and could be important to properly suppress ongoing SELs. Thus, the power supply of the FPGA IO banks is cut, and its interface signals are put in high impedance during the cut time to ensure proper power cycling.  
With the controlling board simultaneously managing these measurements and the test algorithms, it allowed the coherent time stamping of two meaningful parameters during event occurrence, i.e., current variations and detected bit SEUs. In particular, this instrumentation is capable of reporting the actual current during an SEL, with the event ongoing. These features are essential to perform specific analyses that are detailed in Section 4.  
Figure 1: Proposed experimental setup: controller board (rear) and test board (front).  
Figure 2: Architecture of the proposed experimental setup.