## 1 Introduction and Problem Formulation
The newest academic synthesis tools of industry-standard strength are coupled with HDL compilers [67; 68; 69]. The latest algorithms also combine the advantages of AIG manipulation [69] and the representation of functions in the form of BDD [70]. There are also many approaches to the use of BDD that allow for multiple output functions to be represented. The most popular forms of describing multi-output functions are shared BDD (SBDD) and multi-terminal binary decision diagram (MTBDD) [71]. In conclusion, it should be pointed out that there exist plenty of decomposition methods, aimed at various goals to be achieved. One of them is the minimization of the number of blocks [45; 46; 47; 71; 72], while others are focused on the optimization of the number of logical layers [66; 73] or the reduction in the dissipated power [74; 75; 76; 77]. Moreover, proper optimization strategies may target both combinational and sequential circuits [78; 79]. Finally, the most important aspect lies in the adequate division of the system and effective decomposition of logic functions in order to reduce the number of utilized logic blocks (LUTs and FFs) of an FPGA. To summarize the discussion above, the following research gaps can be noticed in the design and optimization of a Petri net-based concurrent control system oriented toward implementation within FPGA devices. Firstly, as designs become complex, using adequate effective modeling techniques becomes extremely important. The method proposed in this paper involves Petri nets, which are intuitive and comfortable modeling tools, joining the graphical and mathematical representation of the system. Another serious bottleneck in the design of concurrent control systems refers to the scalability of the concurrent systems. Therefore, this paper focuses on the reduction of logic resources to ensure efficient FPGA utilization. Such an optimization involves effective decomposition techniques which are crucial in the proposed techniques. In conclusion, in this work, a novel technique oriented toward the adequate modeling and design optimization of the Petri net-based concurrent control system is proposed. The main aim of the presented method is to reduce the number of utilized logic blocks (LUTs and flip-flops) of the destination FPGA device. The main contributions are summarized as follows:  
* Proposition of a novel design technique of a Petri net-based concurrent control system oriented toward the reduction in the resources (logic blocks) of an FPGA. The presented prototyping flow applies an interpreted Petri net, and additionally permits conflict resolution in the modeled system;
* Proposition of a novel optimization technique of the Petri net-based design. The method includes both the functional decomposition of the combinational part of the system and the optimization of the sequential part of the system;Proposition of a photovoltaic control system as a case study of the presented prototyping flow. The applied system reflects the real-life concurrent control system further optimized and implemented within the FPGA device. * Experimental verification of the proposed technique and comparison to the existing functional decomposition methods from the literature. The Proposed Design Method of Petri Net-Based Concurrent Control System Oriented toward a Reduction in FPGA Resources  
This section presents the novel designing technique of Petri net-based concurrent systems aimed at the reduction in the resources of the destination device. The description is divided into four main parts and the whole process is shown in the form of flowchart in Figure 1. Firstly, the modeling rules of Petri net-based concurrent systems are presented. This subsection is supplemented by the main definitions and preliminaries related to the presented method. Subsequently, a transformation method of the Petri net-based model to the Verilog hardware language is explained. Such a description is an input for the proposed reduction (decomposition) technique.