# Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices
## 3 Results and Discussion  
To evaluate the control method, simulations of the model described in Simulink have been carried out. Firstly, the system with two inverters was tested; subsequently the algorithm has been revised to be used also on systems with a number N of inverters. In every simulation, circulating current, inverters output currents and PWM signals have been analyzed. Table 2 shows the configuration for each inverter module used in the tests and, specifically, the clock frequency and the clock delay with respect the first inverter. As mentioned before, the frequency and the phase delay of the clock signals are not identical  
Figure 6: Subsystem Field Programmable Gate Array (FPGA) in a system with two inverters. Figure 7: FSM generating the output PWM signal in the FPGA subsystem. in every FPGA. The clock frequency of the first inverter has been taken as the reference, while the phase delay of the other inverters has been settled randomly with a delay between 1 ns and 5 ns. In Figure 8, the results of the simulations conducted with two parallel-connected inverters are reported: the trend over time of the circulating current, the PWM and the output current for each inverter are shown. The graph reported in Figure 8a shows that the circulating current seen by the first inverter and the circulating current seen by the second inverter are equal to zero, confirming the quality of the proposed algorithm. Moreover, the PWM (drawn in blue) and the output current (drawn in red) are shown in Figure 8b. The PWM frequency is 50.668 kHz, a little higher with respect to the target frequency of 50 kHz due to the approximation and sensitivity of the comparators. The output currents are identical: they oscillate from 5.01 A to 6.49 A with a triangle waveform. The configurations of the inverters used in the tests are the same shown in Table 2: the clock of the FPGA that controls the first inverter has been set up to 100 MHz with an initial current operating point of 5 A. The clock of the second has been set 0.1% higher than the first, precisely at 100.1 MHz with a phase delay of 5 ns. The initial current operating point has been set at 5 A for the second inverter; so on the load, the initial current operating point was at 10 A. The comparator settings are those reported in Table 1. \begin{table}
\begin{tabular}{c c c} \hline \hline  & **fclk** & **\$** \\  & **[MHz]** & **[ns]** \\ \hline
**Inverter 1** & 100 & 0 \\ \hline
**Inverter 2** & 100.1 & 5 \\ \hline
**Inverter 3** & 100.1 & 3 \\ \hline
**Inverter 4** & 100.1 & 2 \\ \hline
**Inverter 5** & 100.1 & 1 \\ \hline
**Inverter 6** & 100.1 & 1 \\ \hline \hline \end{tabular} Note: \(\$\) represents the clock delay with respect the first inverter.  
\end{table} 
Table 2: Inverters configurations. Figure 8: Simulations with two parallel-connected inverters: (**a**) circulating current seen by the two inverters; the zero value obtained shows the validity of the algorithm; (**b**) PWM waveform and output current. Subsequent tests are aimed at verifying whether the proposed method was applicable to a more general solution with N inverters. In Figure 9, circulating currents are reported with four and six inverters, respectively. In the case of the four inverters, Figure 9a, the initial condition of the load current has been set to 10 A, as described for the previous case. This current is equally distributed among the inverters (each inverter has an initial output current of 2.5 A). The amplitude of the circulating current is reduced to a few tens of femtoampere (fA) and the output current of each inverter is now reduced due to the greater number of inverters. The PWM frequency was considered 51.365 kHz, slightly greater than the setpoint (50 kHz). This error is caused by the precision of the comparators (estimated to 10 mA) as described before. The waveforms represented in Figure 9b show the behavior of the circulating current in a system with six parallel-connected inverters.