## 1 Introduction
Alongside such advanced techniques, artificial intelligence and machine learning are extensively used for testing data analysis, where training from historical data allows for the automatic identification of performance issues or potential derivatives. These innovations not only advance the sophistication of chip grading but also improve its practicality [22], helping manufacturers meet market demands for high-performance and highly reliable chips. Domestic companies, such as SMIC and Huahong Semiconductor [23], are developing more advanced grading technologies using machine learning and artificial intelligence algorithms, increasing grading accuracy and data processing capabilities. This system has increased automation and processing, which has consequently raised operating and maintenance costs owing to its complexity and skill requirements [24]. Hai Guang Integrated Circuit Design Company [12] proposed a dynamic adjustment grading method where the final test result of packaged chips can be used as a grading scale. The method thus developed gives a good accuracy as well as consistency in grading by packaging and testing bare dies, but this also leads to increased complexity and testing time in the systems [25]. In the US, Europe, and Japan, companies such as Intel, Samsung, and TSMC use highly automated and integrated testing systems [11]. These include 3D X-ray microscopy, automated defect detection, high-speed electrical testing, and advanced image processing technologies that thoroughly characterize and classify chips [26]. Winbond uses sample classification methods to significantly reduce testing time, at the cost of compromising comprehensiveness. TSMC employs PCA-based methods that aim to optimize yield analysis and improve data-processing efficiency [27], although this requires complex data support. While grading precision and efficiency have indeed been very much improvedvia these techniques, their general uptake has been hampered because of high costs and technical complexity. Against this backdrop, researchers have introduced artificial intelligence algorithms, combined with traditional testing methods, for efficient chip grading [28]. The Parameter Parts Average Testing (PPAT) combined with Statistical Yield Analysis (SYA) allowed the real-time analysis of the defects present and dynamic adjustments to made to the allocation of resources in tests to optimize testing [29; 30]. By combining PPAT and SYA with artificial intelligence algorithms, it can optimize the allocation of testing resources, ensuring product quality and reliability. Additionally, regional PAT improves the stringency of product quality control by evaluating the proximity weights of bare dies and eliminating good bare dies around failed ones [31; 32]. However, these methods still have deficiencies in dynamic adjustments and real-time environmental adaptation, thus making it difficult to cope with inherent process variations and outlier occurrences during production. Traditional grading systems are riddled with excessive rigidity and poor accuracy. Existing machine learning and artificial intelligence algorithms show great dependence on extensive historical data that are not often available for real-time environments [33; 34; 35]. To tackle these setbacks, this paper proposes an innovative method for grading chips where grading is based on failure rates within a dynamically effective space and the effect of nearby chips is assessed through weighted failure rate, which autonomously modifies the grading span and precludes grading errors that had previously resulted from using the traditional method. It also uses an exponential decay function to avoid the interference of extreme values, as well as having the ability to dynamically adjust the failure rates of neighboring areas, which can more accurately handle the dies at the wafer edges.