## 4 Simulation and Experimental Results
This test does not present a stable inner loop regulation which is evidenced by the presence of high current peak perturbations. This peak would be destructive for the converter if an experimental frequency response analysis is performed (please see the temporary experimental results presented below). Experimental plots in Figure 6b show that the Tests 3 and 4 with \(K_{pv}=0.7\) provide a CF of 4 kHz and a PM of \(52^{\circ}\), while Test 2 with \(K_{pv}=0.35\) A/Vs, with smaller quantization perturbations (see Figure 5b), yields a CF = 2.16 kHz and PM = \(59.58^{\circ}\). Simulation tests were done using two voltage error measurement approaches shown in Figure 3. The conventional approach on the left side uses an ADC for sampling the voltage and then computes the voltage error. On the right side, the proposed method quantizes the voltage error by using an ADC in differential mode. Previously, it produces an analog voltage reference from the digital one. Through this last approach, it is possible to increase the error voltage resolution. The values of the analog control gains for the inner and for the external loop at different cross-over frequencies are shown in Table 2.  
The proportional gain for the outer control is selected using the expression \(K_{pv}=C_{o}2\pi f_{c}\) for different crossover frequencies (\(f_{c}=2\) KHz and \(f_{c}=4\) kHz) and with \(C_{o}=28\) uF. Then, the proportional gain for the inner control is adjusted using the expression (16) with \(K_{n}=0.35\), employing the Equation (17) for boost mode with an output voltage of \(V_{o}=300\) V in Equation (16). The statement \(K_{i}T=~{}K_{p}/10\) ensures to obtain a PM greater than \(50^{\circ}\) (see Figure 6), therefore \(K_{ip}T=~{}K_{pv}/10\) for the outer loop and \(K_{ii}T=~{}K_{pi}/10\) for the inner loop. The parameters for the different tests are listed in Table 3.  
Nonetheless, the condition for the inner loop is not fulfilled in this test, therefore the control variable \(u\) and voltage error \(e_{v}\) are not free of QIP effects as it is shown in Figure 5c. The simulated results of Test 4, in which both stability conditions are satisfied, are shown in Figure 5d, where the QIP perturbations have \begin{table}
\begin{tabular}{l l l l} \hline \hline
**Test** & \(e_{p}[\mathbf{n}]\) & \(f_{c}\) & **Condition** & **Condition** \\  & **Calculation** & **[kHz]** & (14) & (11) \\ \hline Test 1 & Conventional & 4 & X & X \\ Test 2 & Conventional & 2 & X & ✓ \\ Test 3 & Proposed & 4 & X & ✓ \\ Test 4 & Conventional & 4 & ✓ & ✓ \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Summary of the tests. \begin{table}
\begin{tabular}{l l} \hline \hline
**Quantization Tests 1 and 2** & **Value** \\ \hline \(v_{o}\) ADC quantization level \(q_{v}\) & 0.11 V \\ \(i_{L}\) ADC quantization level \(q_{i}\) & 5.86 mA \\ DPWM quantization \(q_{DPWM}\) & 0.002 \\ \hline
**Quantization Test 3** & **Value** \\ \hline \(v_{o}\) ADC quantization level \(q_{v}\) & 0.013 V \\ \(i_{L}\) quantization level \(q_{i}\) & 5.86 mA \\ DPWM quantization \(q_{DPWM}\) & 0.002 \\ \hline
**Quantization Test 4** & **Value** \\ \hline quantization level \(q_{v}\) & 0.22 V \\ quantization level \(q_{i}\) & 93.75 mA \\ DPWM quantization \(q_{DPWM}\) & 0.002 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: ADC quantization parameters controller design. disappeared from all signals. It is also noticeable that, in comparison with previous tests, the control effort has been also reduced, which is indicated by the small amplitude of control variable \(u\). These values are in good agreement with the simulated results in Figure 5(a). Despite the fact that Tests 2 and 3 do not satisfy all conditions, it is possible to operate the converter with these designs, obtaining a wider bandwidth using the proposed approach seen in Figure 3 for the Test 3. Additional experiments and simulations have been performed to observe the current waveforms during start-up together with about 12 ms of steady-state regimes.