# Low Power FPGA Implementation of a Smart Building Free Space Optical Communication System
## 4 Results
### Power Budget  
Establishing the low power feature of the proposed system, power calculations have been performed to validate the aspect. Starting with the FPGA processing part, the total power dissipated from the FPGA processing and modulation stage was analyzed, as shown in Table 5.  
Figure 19: The achieved data rate of the proposed system.  
Figure 20: Text Characters successfully received at the UART reception port.  
The maximum output power from the second transmitting stage comprising the laser driver circuit was 5 mW operating at around 16 mA, alternating downwards with the intensity modulation level required for each bit symbol transfer. At the receiving end, the photo-detection and demodulation circuit is powered up using a 3.7 V supply initiated to drive the BPW34 photo-sensor and the comparators needed to convert the received signal and decode it. For '11' bit symbol recognition, the optical signal power will be 100% reciprocating as 3.3 V powering the four comparing stages, which is the maximum power of the electrically reverted signal.  
The quality of the constructed communication link can be measured according to multiple parameters affecting the communication channel and internal infrastructure of the setup Here, all parameters will be summed up in a metric constant \(k\) that equals one, excluding the two hyper values that are monitored to evaluate the system: the data rate and total power consumed. This figure of merit can be summed up as shown in (3).  
\[G=k\frac{R_{B}}{P_{T}} \tag{3}\]  
In which  
* \(G\) is the figure of merit;
* \(k\) is the metric constant;
* \(R_{B}\) is the received bit rate;
* and \(P_{T}\) is the total power of the system.  
Since the optimal reached data rate of the proposed system is 115 kbps for OOK and 230 kbps for the IM/PWM technique, the power budget and the figure of merit can be calculated for both techniques. For OOK and output power of around 165 mW, the figure of merit can be written as (4). For IM/PWM and input power of around 180 mW, the figure of merit is calculated in (5).  
\[G=\frac{115\times 10^{3}}{165\times 10^{-3}}=698\ \times\ 10^{3}\,\mathrm{b/sW} \tag{4}\]  
\[G=\frac{230\times 10^{3}}{180\times 10^{-3}}=1.28\ \times\ 10^{3}\,\mathrm{b/sW} \tag{5}\]  
A remarkable note is that the figure of merit G represents a qualitative measurement of the communication system. As it increases, this would imply either a leap in the received data bits, which indicates an improved reception rate, or a decrease in the total power of the system, which indicates more energy efficiency. Figure 21 shows how an enhanced data rate improves the figure of merit at a constant overall system power, while Figure 22 shows that as the total power increases, the figure of merit decreases due to lowered efficiency at a fixed data rate.  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Summary** & **Power Consumed** \\ \hline Core Dynamic Thermal Power Dissipation & 1.56 mW \\ Core Static Thermal Power Dissipation & 98.54 mW \\ I/O Thermal Power Dissipation & 59.51 mW \\ Total Thermal Power Dissipation & 159.61 mW \\ \hline \hline \end{tabular}
\end{table}
Table 5: FPGA Power Consumption Summary.