# A Review of Sharp-Switching Band-Modulation Devices
## 5 Alternative Applications of Sharp Switching
### Dynamic Memory Cell: Operation as Capacitorless DRAM
The trigger voltage \(\mathrm{V_{ON}}\) shifts slightly to lower voltages as a consequence of the increased carrier energy, which eases the injection over the energy barriers [33; 38]. This enables the use of \(Z^{2}\)-FET cells with lower biasing conditions and power consumption. As a drawback, increasing the temperature augments the SRH generation-recombination, reducing the retention time [39]. Figure 18: \(Z^{2}\)–FET dynamic memory operation consisting of a E-R-W-R sequence. The hold operation (not indicated) is performed by default after any other operation. The cell drives current only for the ‘1’-state programming (W1) and readout (R1). **Reliability, noise, and variability**: Metrics such as the DC V\({}_{\text{ON}}\) and I\({}_{\text{ON}}\), the dynamic memory window, and the retention time for the Z\({}^{2}\)-FET were experimentally studied at high temperature (85 \({}^{\circ}\)C) for different cell geometries and accelerated stress conditions. The V\({}_{\text{ON}}\) voltage shifts up to 50 mV after long stress periods. It was also found that I\({}_{\text{ON}}\) is affected by bias-temperature instabilities (BTI) and random telegraph noise (RTN) fluctuations [44; 45]. Interface and oxide trapping effects are thought to be responsible. Experimental time-dependent dielectric breakdown (TDDB) analysis demonstrated lower breakdown variability for wider cells, but a shorter time to breakdown, indicating a trade-off between reliability and variability [44]. A series of 3D TCAD simulations were conducted to analyze the variability impact of fast states at each interface. Interface states play a fundamental role in the device sharp-switching behavior, through the carrier lifetime value [25; 46]. An excessive density of interface defects at the top of the ungated region degrades the capacitorless operation, increasing the V\({}_{\text{ON}}\) and the variability. This effect was found to be more critical as the cell was scaled down [47]. Nevertheless, a proper design strategy could alleviate the impact of high interface state densities in short cells and recover the sharp-switching capability at the expense of larger biasing voltages. **Scaling**: TCAD simulations predict that the gate of the device can be scaled down to 30 nm [26] with the aid of GP-bias tuning [48]. Unfortunately, to preserve good electrostatic control, the ungated region cannot be downscaled as aggressively. Nonetheless, the Z\({}^{2}\)-FET cell is comparable in terms of area per bit with advanced embedded DRAM that inherently includes a storage capacitor [48]. The geometric scaling enables enhanced oxide reliability, due to the dielectric surface reduction [44] but, as a drawback, it may degrade the retention time and the variability [47], demanding additional bias tuning to overcome this issue. **Matrix operation**: The operation of the Z\({}^{2}\)-FET cell in an array configuration was first studied through simulations [49] and later characterized experimentally in a two-by-two cell matrix, with and without, a pass selector transistor [50]. Single-cell and word-length operations were successfully demonstrated at low [51] and high temperature [52], with promising immunity to bitline or wordline disturbances and an easy-to-scale design. A prototype 1 Mbit memory chip, fabricated with FD-SOI technology, proved fully functional, with reliable performance.