## 3 Results and Discussion  
The minimum deviation (delta, \(\delta\) in Equation (3) is used to determine the chosen parameters. For example, the measured characteristic curve on the device denoted by W120L240 (fin width = 120 nm, channel length = 240 nm) at \(V_{\text{G}}\) = 1.0 V may be well fitted by choosing the three parameters \(V_{th}\) = 0.101 V, \(k_{N}\) = 1.09 \(\times\) 10\({}^{-4}\) A/V\({}^{2}\), and lambda = 0.139 in Equations (1) and (2) as shown in Figure 1a-c, where the minimum deviation value is found to be 3.79569 \(\times\) 10\({}^{-7}\) A. Therefore by using the same skill, all the parameters in Equations (1) and (2) are determined to fit the measured characteristic curves except the ones in Figure 2a,b. where the two transistors, denoted by W110L100 (Fin width = 110 nm, Channel length = 100 nm) and W110L120 (Fin width = 110 nm, Channel length = 120 nm), do not look like FET and are not worth fitting. All the other fitting results are shown in Figures 2c, 3a-c and 4a-c. The final minimum delta's at various \(V_{\text{G}}\)'s. range from 3.25 \(\times\) 10\({}^{-8}\) Ampere to 1.36 \(\times\) 10\({}^{-6}\) Ampere, which are engineering acceptable. Figure 1: Three parameters (\(V_{th}\), \(K_{n}\), lambda) at \(V_{G}\) = 1.0 V on W120L240 (fin width = 120 nm, and channel length = 240 nm) are determined through minimum deviation technique with the minimum deviation = 3.79569 \(\times\) 10\({}^{-7}\) A at **(a)**\(V_{th}\) = 0.101 V as in deviation versus \(V_{th}\), **(b)**\(k_{N}\) = 1.09 \(\times\) 10\({}^{-4}\) A/V\({}^{2}\) as in deviation verses \(k_{N}\), and **(c)** lambda = 0.139 as in deviation versus lambda. Figure 2: \(I_{DS}\)-\(V_{DS}\) characteristic curves and the corresponding fitting, including (**a**) W110L100, (**b**) W110L120, (**c**) W110L160. Figure 3: \(I_{DS}\)-\(V_{DS}\) characteristic curves and the corresponding fitting, including (**a**) W115L120, (**b**) W115L160, (**c**) W115L240. In addition, all determined \(k_{\rm N}\)'s may be specifically listed as in Tables 1-3 at different sizes and at different \(V_{G}\)'s [12]. In the modified conventional formula in Equations (1) and (2), \(k_{\rm N}\) is supposed to be inversely proportional to the channel length. And \(k_{\rm N}\) is also proportional to the channel width (\(W_{channel}\)) and, thus the width of the fin (\(W_{fin}\)), because  
Figure 4: \(I_{\rm DS}\)-\(V_{\rm DS}\) characteristic curves and the corresponding fitting, including (**a**) W120L110, (**b**) W120L160, and (**c**) W120L240. \(W_{channel}=(9+9+1)\)\(W_{fin}=19W_{fin}\). If \(k_{N}\) is plotted against \(W_{fin}\) or \(1/L_{channel}\), straight lines are then expected. Unfortunately, most of them fail the testing except on the devices with fin width = 120 nm at \(V_{G}\) = 1.0 V partly as found in Figure 5. Of course, at \(V_{G}\) = 0.0 V, the transistors, which are still on and may have pretty low threshold voltage or even negative one, are not discussed in this paper. So the applied voltages to Gates depleting the fin channels and making the devices less leaky draw much attention. In Figure 4a, the straight line proves the feasibility at \(V_{G}\) = 1.0 V with fin width = 120 nm, while the other two graphs, Figure 4b,c do not. The non-straight lines might be due to either over-depletion or under-depletion. Over-depletion means that the depletion regions from both sides of the fin overlap resulting to disturbing the blocking function. On the other hand, the depletion regions do not completely cover all the fin for under-depletion and the leakage current gets apparent. The three transistors with 120 nm fin width at \(V_{G}\) = 1.0 V provide valuable information, i.e., the whole fin may be totally depleted without interference from the other side of the applied bias. One or the other side of the applied Gate bias depleted 60 nm, which is a half of the fin width, as shown in Figure 6, where the energy band appears with 1.12 eV energy gap.