# Review of Ka-Band Power Amplifier
## 3 Topologies
### Stacked FET  
In the traditional power amplifier design, the output matching network needs to convert 50 \(\Omega\) to the optimal load impedance of the output transistor to obtain the maximum output power. According to engineering experience, for a lossy matching network, generally speaking, the greater the impedance transformation ratio, the greater the insertion loss of the matching network, and the more difficult it is to realize broadband impedance matching. Therefore, improving the optimal load impedance helps to reduce the loss of the output matching network, improve the output power and efficiency, and it is easier to achieve broadband output matching. Stacked power amplifiers can meet this demand. \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline
**Ref.** & **Tech** & **Frequency (GHz)** & **Gain (dB)** & **Psat (dB)** & **P1 dB (dBm)** & **PAEpeak (\%)** & **Area (mm\({}^{2}\))** & **Topology** \\ \hline
[48] & 180 nm CMOS & 24 & 7 & 14.5 & / & / & 1.26 &
\begin{tabular}{c} 2-stage \\ cascode \\ \end{tabular} \\ \hline
[49] & 65 nm CMOS & 28 & 22 & 14 & / & 21.8 & 0.53 &
\begin{tabular}{c} 3-stage CS \\ cascode \\ \end{tabular} \\ \hline
[52] & 65 nm CMOS & 34 & 13.8/10.5 & 19.9/17 & 17/14 & 25.8/22.8 & 0.365 &
\begin{tabular}{c} 2-stage \\ cascode \\ \end{tabular} \\ \hline
[54] & 40 nm CMOS & 28 & 20.1 & 20.3 & 18.3 & 25 & 0.214 &
\begin{tabular}{c} 2-stage \\ Differential \\ cascode \\ \end{tabular} \\ \hline
[55] & 130 nm SiGe & 28 & / & 14 & 12 & 25 & 0.14 &
\begin{tabular}{c} 1-stage \\ cascode \\ \end{tabular} \\ \hline
[34] & 65 nm CMOS & 31 & 18.9 & 20.3 & / & 38.2 & 0.345 &
\begin{tabular}{c} 2-stage \\ cascode \\ \end{tabular} \\ \hline
[57] & \
\begin{tabular}{c} 180 nm \\ SiGe BiCMOS \\ \end{tabular} & 25.5/37 & 20.5 & 14.6 & 13.1 & 35.8 & 0.3 &
\begin{tabular}{c} 2-stage CE \\ cascode \\ \end{tabular} \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Comparison of the measurement results with the coscode PA.  
Figure 10: (**a**) The 2-stage cascode PA in 60 nm CMOS [34] (**b**) 2-stage CE cascode PA in 180 nm SiGe BiCMOS [57]. In the traditional stacked FET structure, the source stage and drain of multiple transistors are connected sequentially. Figure 11 shows an n-layer stacked-FET structure. By adjusting the gate input and bias voltage of the transistor, ideally, the bias voltage between the drain stage and the source stage of each transistor can be the same. The external gate grounding capacitance makes the voltage between the drain stage and the source stage of each transistor the maximum voltage swing of the transistor. Each transistor is directly coupled, the total swing of the output voltage is n times that of the single-tube structure, and the output power is n times that of the single-tube structure. In addition, another advantage is that the optimal load impedance is also n times that of the single-tube structure, which provides the basis for broadband performance and low matching loss [58]. As described above, transistor stacking is a promising method to improve the output power and bandwidth of PAs in modern semiconductor technology, because although the breakdown voltage is low, it is still possible to obtain a high output voltage swing. However, due to the process error and load impedance design problems, the phase and amplitude of the output voltage of each layer of the transistor will have a certain deviation, which will affect the power synthesis efficiency and linearity of the stacked-FET amplifier. In [59], [PERSON] designed the 1-stage differential CS and 1-stage 2-stack PA in the same area (0.28 mm\({}^{2}\)) (see Figure 12a). Through the comparison of results, the 2-stack PA had higher gain and output power than the differential CS. The differential CS/2-stack achieved a gain of 10/13.6 dB, \(P_{\text{sat}}\) of 10.1/15.1 dBm and PAE of 36.5/43.5%. In 2016, an ultra-compact watt-level stacked-FET GaAs PA was reported [60]. The power amplifier has more than 33% PAE and 31.5 dBm output power, with an area of 2 mm\({}^{2}\).