# A Ku-Band GaAs Multifunction Transmitter and Receiver Chipset
## 3 Circuit Blocks of the Ku-Band Multifunction Chipset
### 4-Bit Digital Phase Shifter  
The phase shifter is designed with a passive switched topology to reduce the DC consumption and to facilitate the digital phase control. Four unit cells, each accomplishing phase shifts of 22.5\({}^{\circ}\), 45\({}^{\circ}\), 90\({}^{\circ}\) and 180\({}^{\circ}\), are connected in cascade for a full 360\({}^{\circ}\) shift. The 22.5\({}^{\circ}\), 45\({}^{\circ}\) and 90\({}^{\circ}\) cells adopt a bridged-T structure, as shown in Figure 5a. In the reference state, the transistors, M\({}_{\text{S}}\) and M\({}_{\text{P1}}\), are turned on while M\({}_{\text{P2}}\) is turned off, simplifying to the equivalent circuit of Figure 5b. The off-capacitance of M\({}_{\text{P2}}\) (C\({}_{\text{MP2}}\)) resonates with parallel-connected L\({}_{\text{P}}\) at the operation frequency, giving an open circuit. On the other hand, in the phase-shift state, M\({}_{\text{S}}\) and M\({}_{\text{P1}}\) are turned off while M\({}_{\text{P2}}\) is turned on, as shown in Figure 5c. Therefore, the off-capacitance of M\({}_{\text{P1}}\) (C\({}_{\text{MP1}}\)) and L\({}_{\text{S}}\) provide a designated phase shift. The component values are determined by the following equations [19]. \[\text{L}_{\text{S}}=\frac{\text{Z}_{0}}{\omega}\tan(\frac{\Delta\phi}{2}) \tag{1}\]  
\[\text{L}_{\text{P}}=\frac{1}{\omega^{2}\text{C}_{\text{MP2}}} \tag{2}\]  
\[\text{C}_{\text{MP1}}=\frac{\sin(\Delta\phi)}{\omega\text{Z}_{0}} \tag{3}\]  
\[\text{C}_{\text{MP2}}=\frac{2\text{L}_{\text{S}}}{\text{Z}_{0}{}^{2}} \tag{4}\]  
where \(\Delta\phi\) is the designated phase shift, Z\({}_{0}\) is the characteristic impedance and \(\omega\) is the operation frequency. It is noted that C\({}_{\text{MP1}}\) and C\({}_{\text{MP2}}\) become large as \(\Delta\phi\) increases to 90\({}^{\circ}\). The large off-capacitance requires a large-size transistor, which limits the operation bandwidth. Therefore, the 90\({}^{\circ}\) cell is implemented by connecting two 45\({}^{\circ}\) cells in cascade. In Figure 6a,b, the insertion loss and phase shift performance are compared, respectively, when a single 90\({}^{\circ}\) cell and two cascaded 45\({}^{\circ}\) cells are used. Obviously, the two cascaded 45\({}^{\circ}\) cells provide a wider bandwidth for 90\({}^{\circ}\) phase shift. Figure 5: (**a**) Bridged-T structure for 22.5\({}^{\circ}\), 45\({}^{\circ}\) and 90\({}^{\circ}\) unit cells, (**b**) equivalent circuit in the reference state, (**c**) equivalent circuit in the phase shift state, (**d**) high-pass-filter/low-pass-filter structure for 180\({}^{\circ}\) unit cell. A 180\({}^{\circ}\) cell is designed using the high-pass filter (HPF)/low-pass filter (LPF) structure shown in Figure 5d. The values of inductance and capacitance are calculated by the following equations [20]. \[\mathrm{L_{S}}=\frac{\mathrm{Z_{0}\Delta\tan\left|\frac{\Delta\Phi}{2}\right|}}{ \omega} \tag{5}\]  
\[\mathrm{L_{P}}=\frac{\mathrm{Z_{0}}}{\omega\Delta\sin\left|\Delta\Phi\right|} \tag{6}\]  
\[\mathrm{C_{S}}=\frac{1}{\omega\Delta\mathrm{Z_{0}}\cdot\tan\left|\frac{ \Delta\Phi}{2}\right|} \tag{7}\]  
\[\mathrm{C_{P}}=\frac{\sin\left|\Delta\Phi\right|}{\omega\Delta\mathrm{Z_{0}}} \tag{8}\]  
Figure 7 shows a complete schematic and micrograph of the 4-bit digital phase shifter. The placement order of each unit phase shift cell is optimized for a wide bandwidth and low insertion loss. The 4-bit digital phase shifter test cut occupies an area of \(2.6\times 1.1\) mm\({}^{2}\), excluding probing pads. The parameter value of each component is presented in Table 2.  
\[\text{L}_{\text{P}}=\frac{1}{\omega^{2}\text{C}_{\text{MP2}}} \tag{2}\]0 Performance comparison of two structures implementing 90\({}^{\circ}\) phase shift: (**a**) insertion loss, (**b**) phase shift. \[\text{L}_{\text{P}}=\frac{1}{\omega^{2}\text{C}_{\text{MP2}}} \tag{2}\]1 Schematic and chip micrograph of the 4-bit digital phase shifter.