# A 28-nm CMOS Low-Power/Low-Voltage 60-GHz LNA for High-Speed Communication
## 1 Introduction  
Wireless communications require increasing data rates that can be effectively achieved by exploiting the unlicensed industrial, scientific and medical (ISM) 60-GHz spectrum spanning from 57 GHz to 64 GHz [1]. However, the high atmospheric absorption in this frequency band limits the communication distance, thus enabling only short-range applications [2]. On the other hand, the wide 7-GHz bandwidth centered at 60 GHz guarantees wireless communications at Gbit/s data rates. As far as modulation is concerned, simple modulation schemes are preferred and, specifically, on-off keying (OOK) modulation is largely adopted in the literature since it is compatible with low-complexity circuits and low-power implementations [3, 4, 5, 6, 7]. Specifically, in the OOK architecture the receiver adopts non-coherent demodulation. As a result, the receiver does not require a local oscillator (LO), and the transmitter is not dependent on a phase-locked loop (PLL) to generate an exact frequency for the RF carrier [8]. Several interesting examples of 60-GHz OOK receivers have been published both in BiCMOS and CMOS technologies [9, 10]. The most common receiver (RX) architectureadopts a wideband low-noise amplifier (LNA) that drives an OOK demodulator, typically consisting of an envelope detector (ED) and a baseband limiting amplifier (LA), as depicted in Figure 1. The main design target is minimizing the energy per bit required for demodulation at the minimum input signal power (i.e., sensitivity). Typical values of energy per bit are around 10 pJ/bit with the best values below 5 pJ/bit. As far as sensitivity is concerned, common levels are between \(-35\) dBm and \(-25\) dBm with a bit error rate (BER) of \(\mathbf{10^{-12}}\). Finally, power consumption is highly related to the data rate with typical values of about 20 mW at Gbit/s data rates. The widespread design approach is mainly based on single-ended topologies for both the LNA and the demodulator to save power and silicon area and avoid single-ended-to-differential conversion at the millimeter-wave (mm-wave) input, while differential structures are more common in the baseband amplification stages. Multistage topologies (i.e., three, four and even five or six stages) are often proposed for the LNA to obtain a wideband gain at the expense of higher vulnerability to instability issues in a complete receiver [8; 10]. Moreover, \(g_{\text{m}}\)-enhancement techniques are also exploited to partially overcome the transconductance limitations of nanometer CMOS transistors at mm-wave frequencies, especially in bulk technologies. All the above-mentioned design approaches can hardly be adopted in an actual application that requires low power consumption, high rejection of common-mode noise interferences, and compatibility with implementation issues, such as electrostatic discharge (ESD) protection, especially at the mm-wave input/output. To overcome the above limitations, a 60 GHz LNA for high-data-rate mm-wave receivers is proposed here. Its pseudo-differential topology along with an effective power-efficient design strategy allows for simultaneous input/noise matching with extremely low power consumption, making the amplifier suited for low-power mm-wave applications while providing intrinsic ESD protection. The proposed LNA includes two amplification stages and an output buffer stage. The simple two-stage topology is suited for a flat gain with a wide frequency bandwidth in the order of several gigahertz. On the other hand, adding a buffer stage provides 50-ohm output matching for single-ended on-wafer measurements and integrated ESD protection. This paper is arranged as follows: Section 2 describes the architecture of the proposed LNA, and the adopted design approach is discussed in comparison with other state-of-the-art solutions. Section 3 introduces the adopted 28-nm CMOS technology and customized integrated passive components (i.e., integrated transformers and capacitors).