# Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor
## 5 Results  
All designs were described in VHDL and implemented in a Virtex-7 FPGA (-3 speed grade). The architecture was simulated, synthesized, placed and routed using Vivado 19.1 from Xilinx. The area of all implementations after place and route are presented in Tables 11 and 12. Multiplier 1 is the fastest while multiplier 2 is the smallest. These relations are determined by the multiples generators and the partial product generators. Multiplier 2 needs multiple 4\(\times\) that is harder to generate and has a critical path higher than the other multiples. This determines the higher critical path of the second multiplier. On the other side, the multiplexer of the partial product generator of multiplier 1 has three inputs. while the multiplexer of multiplier 2 has only two. This determines the smaller area of multiplier 2. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Block** & **Multiplier 1 (\#LUT6)** & **Multiplier 2 (\#LUT6)** \\ \hline MultGen(BCD) & 7\(N\) & 10N + 7 \\ MultGen(BCD/e6) & 8N + 1 & 10N + 7 \\ PPG & 8N\({}^{2}+11N\) & 6N\({}^{2}+8N\) \\ \hline PPR & 4\(\times(\frac{N}{2}\times[log_{2}N]+N^{2}-N)\) & \\ Converter (BCD) & 4\(N\) & \\ BCD Multiplier(BCD) & 12N\({}^{2}+18N+2N[log_{2}N]\) & 10N\({}^{2}+18N+7+2N[log_{2}N]\) \\ BCD Multiplier(BCD/e6) & 12N\({}^{2}+15N+1+2N[log_{2}N]\) & 10N\({}^{2}+14N+7+2N[log_{2}N]\) \\ \hline \hline \end{tabular}
\end{table} 
Table 10: Theoretical area of both decimal multipliers in number of LUT6. \begin{table}
\begin{tabular}{l c c c c c c} \hline \hline  & \multicolumn{3}{c}{**Multiplier 1**} & \multicolumn{3}{c}{**Multiplier 2**} \\ \hline
**Size** & **Model** & **Area** & **Delay** & **Model** & **Area** & **Delay** \\ \hline
2 \(\times\) 2 & 88 & 88 & 3.56 & 87 & 87 & 4.62 \\
4 \(\times\) 4 & 280 & 280 & 4.97 & 255 & 255 & 5.92 \\
8 \(\times\) 8 & 960 & 960 & 6.58 & 839 & 839 & 7.96 \\
16 \(\times\) 16 & 3488 & 3504 & 8.93 & 2983 & 3001 & 10.22 \\
32 \(\times\) 32 & 13,184 & 13,248 & 12.26 & 11,143 & 11,194 & 13.12 \\
34 \(\times\) 34 & 14,892 & 14,976 & 13.04 & 12,587 & 12,643 & 13.91 \\ \hline \hline \end{tabular}
\end{table} 
Table 11: Logic area (LUTs) and delay (ns) of both multipliers with BCD inputs and output for different number of digits in a Virtex-7 FPGA, speed grade -3. \begin{table}
\begin{tabular}{l c c c c c c} \hline \hline  & \multicolumn{3}{c}{**Multiplier 1**} & \multicolumn{3}{c}{**Multiplier 2**} \\ \hline
**Size** & **Model** & **Area** & **Delay** & **Model** & **Area** & **Delay** \\ \hline
2 \(\times\) 2 & 83 & 83 & 3.02 & 79 & 79 & 3.84 \\
4 \(\times\) 4 & 271 & 271 & 4.32 & 239 & 239 & 5.31 \\
8 \(\times\) 8 & 943 & 943 & 6.06 & 807 & 814 & 7.23 \\
16 \(\times\) 16 & 3455 & 3471 & 8.37 & 2919 & 2937 & 9.31 \\
32 \(\times\) 32 & 13,119 & 13,183 & 11.99 & 11,015 & 11,076 & 12.94 \\
34 \(\times\) 34 & 14,823 & 14,907 & 12.84 & 12,451 & 12,535 & 13.78 \\ \hline \hline \end{tabular}
\end{table} 
Table 12: Logic area (LUTs) and delay (ns) of both multipliers with BCD/excess-6 inputs and output for different number of digits in a Virtex-7 FPGA, speed grade -3. As can be observed from the results, multiplier 2 is 18% smaller than multiplier 1 for the 32 digit multiplier. This difference reduces for smaller multipliers. On the other side, multiplier 1 is 30% faster than multiplier 2 for the 2 digit multiplier. This difference reduces for larger multipliers (see Figures 8 and 9). Multiples generator of multiplier 2 occupies more area than those of multiplier 1, but the partial generator is smaller in multiplier 2. Since the area of the partial product generators reduces faster, the difference of the area of the proposed multiplier 2 to the multiplier 1 increases with the size of the multipliers. The difference in delay between the proposed multipliers is mostly due to the multiples generators. Therefore the absolute difference between both multipliers is almost constant. Therefore, the relative delay difference decreases with the size of the multipliers.