# Resource-Efficient FPGA Architecture for Real-Time RFI Mitigation in Interferometric Radiometers
## 2 Algorithm Description  
This section describes an RFI detection and mitigation algorithm optimized for interferometric radiometers with 1-bit digitization. The algorithm combines statistical analysis through kurtosis estimation with polarimetric measurements to identify and remove RFI contamination. It processes both time and frequency domains to provide with a wider range of detection opportunities. The detection strategy makes use of the non-Gaussian characteristics of RFI signals and their impact on signal polarization, allowing for effective identification even with highly quantized input data.  
The Hardware Design Language (HDL) architecture has been structured to minimize resource utilization to allow for multiple receivers to be instantiated in the same FPGA, while maintaining processing capabilities. The RFI Mitigation algorithm implementation is separated in three distinct processing stages (Figure 2), each addressing specific aspects of the detection and mitigation process: first, the Observable Generation stage produces the intermediate products necessary for RFI detection. This stage implements the theoretical framework described in [17], computing the time-frequency representations and polarimetric parameters while managing the strict resource constraints of space-grade FPGAs. The stage handles the critical 1-bit quantized input signals, processing them from the base sampling rate of 57.69375 MHz, through an overclocked Short-Time Fourier Transform (STFT), while preparing the data for subsequent analysis. Second, the RFI Detection stage processes the observables to identify interference in both time and frequency domains. This stage implements the multi-domain analysis approach, generating blanking masks at the sample level. The detection process incorporates both the statistical and polarimetric tests. Third, the PMS Blanking stage applies the generated masks to mitigate RFI in both the 1-bit quantized signals and the Power Measurement System (PMS) data. This final stage ensures the cleaned signals maintain proper synchronization for the subsequent correlation processing.  
The implementation adopts a modular architecture where these three processing stages are encapsulated in separate HDL blocks. The design enables controlled data flow management between processing stages, crucial for maintaining real-time processing capabilities. External buffering handles the 3-bit truncated STFT outputs and 1-bit polarization signals, ensuring proper synchronization with the correlator timing requirements. The buffering strategy optimizes memory usage while maintaining the necessary throughput for real-time operation. A key architectural decision involves processing each receiver independently. The design processes a single receiver's data path, allowing horizontal scaling through multiple instantiations of the RFI Mitigation block. The ability to scale horizontally by replicating processing blocks provides flexibility in adapting the implementation to different mission requirements and hardware constraints.  
Resource-intensive operations, particularly the Fast Fourier Transform (FFT) computation and wide-word divisions, have been specifically optimized. The FFT implementation employs serialization techniques and resource sharing strategies to minimize Digital Signal Processing (DSP) block usage while maintaining throughput requirements. Similarly, division operations are optimized through Automatic Gain Control (AGC) units that reduce the width of the operands. Memory management emphasizes the use of Block RAM (BRAM) over distributed memory and registers. This strategy reduces the overall logic element usage while providing the necessary storage capacity for intermediate results and processing buffers. The following sections provide detailed block diagrams and information for each processing stage, examining the specific optimization strategies employed to meet space implementation requirements while maintaining algorithm effectiveness.