## 2 Modeling
### Analysis of Power Switch Fault  
Owing to the topological characteristics of the T\({}^{2}\)3L inverter, each phase bridge arm can produce three distinct voltage states by combining power switches. When the output voltages of the bridge arm are \(+0.5\mathrm{U_{dc}}\), 0, and \(-0.5\mathrm{U_{dc}}\) respectively, it corresponds to the operating state [P], [O] and [N], as detailed in Table 2.  
When OC faults occur in single or multiple power switches, the inverter's outputs will be distorted to variable degrees. Such faults significantly degrade inverter performance and may compromise the operational safety of the entire system. In practical engineering scenarios, simultaneous OC faults involving three or more power switches are extremely rare. Considering the low frequency of this phenomenon, this section focuses on analyzing the single- and double-switch faults in phase a. Single-switch faults are further categorized into bridge-arm switch faults and midpoint switch faults. The current paths before and after fault occurrence are illustrated in Figure 2. Blue traces correspond to steady-state current distribution, whereas red traces delineate fault-induced abnormal conduction paths.  
(1) OC faults in the bridge-arm switches: Figure 2a demonstrates that during state [P] operation with \(I_{a}>0\), an OC fault occurring in \(T_{a1}\) alters the current path. The forward current flows through \(T_{a3}\) and \(D_{a2}\) instead of \(T_{a1}\), thereby maintaining freewheeling operation. At this point, the positive half-cycle of the current is significantly distorted, while voltage \(u_{ao}\) drops to zero. Under state [P] operation with \(I_{a}<0\), an OC fault in switch \(T_{a1}\) maintains the original current path and preserves pole voltage stability at \(+0.5\mathrm{U_{dc}}\). The fault has no negative influence on the circuit within a short period. As shown in Figure 2b, the faults in \(T_{a4}\) exhibit similar characteristics. When the OC fault occurs, the current's negative half-cycle becomes severely distorted, and the pole voltage also drops to zero.  
(2) OC faults in the midpoint switches: As shown in Figure 2d, during the inverter's operation in state [O], the OC fault develops in \(T_{a2}\). This changes the negative current path through \(T_{a2}\), forcing it to reroute via \(D_{a1}\) to facilitate freewheeling. At this time, the current's negative half-cycle shows slight distortion, while voltage \(u_{ao}\) rises to \(+0.5\mathrm{U_{dc}}\). The current paths before and after the OC fault in another midpoint switch (\(T_{a3}\)) are depicted in Figure 2e. Meanwhile, the positive half of the current is slightly distorted, and \(u_{ao}\) drops from 0 to \(-0.5\mathrm{U_{dc}}\).  
(3) OC faults in the positive/negative level switches: During the inverter's state [P] operation and \(I_{a}>0\), the positive-level switches (\(T_{a1}\) and \(T_{a3}\)) experience an OC fault, as illustrated in Figure 2c. The current flows through \(D_{a4}\) for freewheeling, with only state [N] of the inverter phase remaining normal. Consequently, the current conducts during the negative half cycle, and \(u_{ao}\) changes to \(-0.5\mathrm{U_{dc}}\). The current paths before and after the fault of the negative-level switches (\(T_{a2}\) and \(T_{a4}\)) are illustrated in Figure 2f. In this case, only state [P] of phase a is normal, restricting current conduction to the positive half cycle. Consequently, the pole voltage changes to \(+0.5\mathrm{U_{dc}}\).  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Switching State** & **Pole Voltage** & **Operating State** \\ \hline
1,0,1,0 & \(+0.5\mathrm{U_{dc}}\) & [P] \\
0,1,1,0 & 0 & [O] \\
0,1,0,1 & \(-0.5\mathrm{U_{dc}}\) & [N] \\ \hline \hline \end{tabular}
\end{table}
Table 2: Pole voltage and operating state.