## 4 Simulation Results
### SDRE Observer  
In the following, the performance of fault detection based on the SDRE observer is investigated. Weight matrixes W and V are considered as follows:  
\[\text{V}=10^{-4}\ I_{9},\ \ \ W=10^{6}\ \text{diag}(1,50,1,1,50,1,50)\]  
In the simulations of this section, it is assumed that a fault occurs at 1.5 s in the \(C_{1}\) capacitor and another fault in 3.5 s in the \(C_{4}\) capacitor. As shown in Figure 10, at this time, the \(C_{1}\) voltage decreased from 300 V to 10 V, and the voltage of the \(C_{4}\) capacitor decreased from 400 to 10 V, and correspondingly, in Figure 11, the output current of the PV system and the battery decreased. According to Figure 10, the fault detection time for the proposed SDRE method is 30 ms. Meanwhile, the fault detection system compares the actual system output with the output of the SDRE observer and formed a non-zero residual current, as shown in Figure 12, which, with the definition of the appropriate threshold--here the threshold is assumed 50 mA--makes it possible to detect the fault. As mentioned, among the most important issues in the field of fault detection is to not identify disturbances as faults. As shown in the previous section, despite the above-mentioned disturbances, Figure 11 shows that the fault occurrence system did not trip any of these times.  
Figure 8: Output current of the capacitor bank in the presence of SDRE controller.  
Figure 9: Dc bus voltage in the presence of SDRE controller.  
In order to show the proposed fault detection scheme's ability and its non-dependence on the fault location, a fault occurred at 2.5 s on the output of the \(C_{7}\) capacitor, and another in 4.5 s had occurred on the load bus. As shown in Figures 13 and 14, at a moment of 2.5 s, the capacitor voltage \(C_{7}\) decreased from 1000 to 500 V and the load bus voltage reduced from 1000 to 500 V. In this case, as shown in Figure 15, the capacitor-bank output current has increased. As it can be seen from Figure 16, the fault detection time for the proposed SDRE method is 30 ms. It is apparent in Figure 16, that the threshold was considered 50 mA which was feasible for fault detection.  
Figure 11: Inductance \(L_{3}\) and \(L_{6}\) voltages during fault occurrence.  
Figure 12: Residual currents of \(C_{1}\) and \(C_{4}\) capacitors during fault occurrence.  
Figure 10: Capacitance \(C_{1}\) and \(C_{4}\) voltage during fault occurrence.  
As noted, one of the most important problems in the field of microgrid protection is the detection of disturbance as a fault occurrence. As a result, the proper selection of threshold value has a significant effect on this goal. In order to investigate this issue, in the studied dc microgrid, it is assumed that the dc resistive load unexpectedly has suddenly disconnected at 0.2 ms and reconnected again. It is also assumed that the fault has occurred in the \(C_{1}\) capacitor within 0.4 ms. As can be seen from Figure 17, by selecting a threshold value of 50, the fault occurrence warning is not activated at this time.  
Figure 16: Residual current of \(C_{7}\) and \(C_{9}\) capacitors during fault occurrence.  
Figure 14: Capacitor output current during fault occurrence.  
Figure 13: Capacitor voltage during fault occurrence in capacitor \(C_{7}\).  
In fact, for the sake of generalization, we can say that the threshold value for the fault detection occurrence is chosen to be greater than the disturbances range. As can be seen, the maximum non-zero residual current of \(C_{1}\) is less than 3 mA in the disturbance condition, whereas the non-zero residual current of the \(C_{1}\) is about 700 mA when the fault occurs. As a result, in order to provide the margin of assurance of the performance of the protection system, the threshold value of the fault occurrence is considered as 50 mA, so that both the fault occurrence is quickly detected and the disturbance is not considered as a fault.