# A Roadmap for Gigabit to Terabit Optical Wireless Communications Receivers
## 4 Discussion
### Designing Application-Specific SiPMs  
The results show that any new application-specific integrated circuit (ASIC) designed to act as a receiver should have significantly faster output pulses than existing SiPMs. This emphasis suggests that the microcells in the ASIC might have a digital output. SiPMs with digital outputs have been integrated into receivers previously [29; 30]; however, both of the SiPMs used in these experiments were created on one chip. This meant that the digital logic circuits alongside each SPAD reduced the overall fill factor, and hence the PDE, of the SiPMs. Fortunately, since these SiPMs were manufactured the ability to stack two chips has been developed [31]. If one of these chips is used to create an array of APDs and the other  
Figure 13: The potential performance of a J30020 and combinations of 9 RB10010 SiPMs and 9 RB10020 SiPMs. These results were obtained using the same methodology as used to obtained the results in Figure 8. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Name**} & **Area** & **Pitch** & **Number of** & **Recovery** & **Maximum Count** & **PDE at 850** & **Fast Output** \\  & **(mm\({}^{2}\))** & **(\(\upmu\)m)** & **ucells** & **Time (ns)** & **Rate (Gcps)** & **nm** & **Pulse Width (ns)** \\ \hline RB10010 & 1 & 10 & 4296 & 12 & 162.7 & 0.07 & 2.3 \\ RB10020 & 1 & 20 & 1590 & 21 & 34.4 & 0.12 & 2 \\ RB10035 & 1 & 35 & 620 & 73 & 3.9 & 0.17 & 3.7 \\ \hline J30020 & 9 & 20 & 14,410 & 15 & 436.7 & 0.025 & 1.4 \\ J30035 & 9 & 35 & 5676 & 45 & 57.3 & 0.03 & 1.5 \\ J40035 & 16 & 35 & 9260 & 48 & 87.7 & 0.03 & 1.7 \\ J60035 & 36 & 35 & 22,292 & 50 & 202.7 & 0.03 & 3 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Key parameters for the two series of commercially available SiPMs manufactured by onsemi, including their PDE at 850 nm [22; 24; 25]. to create a matching array of ancillary circuits, then this technology avoids the trade-off between circuit complexity and fill factor. In addition, this technology means that the two chips can be made by using the manufacturing processes best suited to their function. These advantages mean that stacked systems, often known as SPAD arrays, have been created in which one of these chips contains an array of APDs and the other chip contains a matching array of quenching circuits as well as relatively sophisticated digital circuits [31]. The existing stacked SPAD arrays have been designed for applications such as LIDAR and low-light imaging; however, they contain components that could be used to create a receiver. The most important component which could be used in a receiver is the APDs in the first chip. These have been made by using a variety of manufacturing processes, and some include additional features that increase the PDE at some or all wavelengths. One feature used in some devices is a charge-focusing SPAD, in which the electric field in the APD guides photon-generated electrons into a central avalanche region [32]. This approach results in a fill factor of 100% and a PDE of approximately 40% at 405 nm. Furthermore, SPADs can be created with a 6.39 \(\upmu\)m pitch and in arrays of 2072 by 1548 [32]. A key function of the ancillary circuits in the second chip is to quench the otherwise self-sustaining avalanche processes. In order to reduce afterpulsing, this can be performed by combining a passive quenching process with an active reset (a combination known as PQAR). To achieve this, a MOSFET is connected in series with the APD to create a load that reduces the bias voltage across the APD when an avalanche occurs. The resulting change in the voltage across the APD is then detected by a digital circuit. This circuit is designed to hold the APD bias voltage below the breakdown voltage for a controlled time. During this time, any charge trapped in the APD can escape without creating an afterpulse; however, the cost of suppressing afterpulses is that the SPAD cannot detect a photon, and so this time is the dead time for the SPAD.