## 4 Case study Example--Beverage Production and Distribution Machine
### Experimental Validation of the Proposed Method  
This section presents the experimental validation of the proposed decomposition technique. The obtained model of the beverage production and distribution system was implemented in the real FPGA device. In particular, Nexys 4 DDR prototyping board with the FPGA device xc7a100 tcsg324-2 from Artix 7 family was used to perform hardware validation. Firstly, the decomposed modules were described in the Verilog hardware language. The applied encoding style is based on the rules shown in other authors' works, e.g., [7; 33]. In particular, each of decomposed SMCs is described as a sequential module. An exemplary description of \(S_{1}\) is shown in Listing 1. There are three main sections within this module. The first one triggers switching states in the system. It is described by an _always_ block, and it is activated by a positive clock signal (common oscillator for all components) or asynchronous reset. The second section prepares adequate switching values for the next state. It is also described by an _always_ block; however, the sensitivity list includes input signals (and the value of the current state). Finally, the last block associates outputs with particular states by continuous assignments. All the SMCs are controlled by the _top-level_ module. This module simply includes an instance of each component. Listing 2 shows the Verilog code for the presented beverage production and distribution machine. Note that the _top-level_ module contains twelve input and twelve output signals that are directly used in the modelled CPS. The internal signals (vector \(z\)) are applied to synchronise the decomposed components. Additional _clk_ and _reset_ signals are used for synchronisation (clock) and restarting the system, respectively. Figure 4: The decomposed CPS of production and distribution beverage machine. ```
// Description of S1 module s1 { output y3, y10, y11, y12, output z1, input x1, x4, x11, x12, input z2, z8, input clk, reset ); reg [2:0] state, next; parameter P1 = 3'b000, P4 = 3'b001, P7 = 3'b011, P10 = 3'b010, NOP1 = 3'b110, P19 = 3'b111, P20 = 3'b101; always @(posedge clk or posedge reset) begin if (reset) state <= P1; else state <= next; end always @ (state or x1 or x4 or x11 or x12 or z2 or z8) begin case (state) P1: next <= (x1)? P4 : P1; P4: next <= (x4)? P7 : P4; P7: next <= (x11)? P10 : P7; P10: next <= (z2)? NOP1 : P10; NOP1: next <= (z8)? P19 : NOP1; P19: next <= (x12)? P20 : P19; P20: next <= (1x4)? P1 : P20; default: next <= P1; endcase  end assign y3 = (state == P4)? 1'b1 : 1'b0; assign y10 = (state == P7)? 1'b1 : 1'b0; assign y11 = (state == P19)? 1'b1 : 1'b0; assign y12 = (state == P20)? 1'b1 : 1'b0; assign z1 = (state == P10)? 1'b1 : 1'b0; endmodule
```  
**Listing 1**Description of exemplary _S-component_ (S1) (actions performed by a trolley). ```
// Description of top-level module beverage_decomposed ( output [1:12] y, input [1:12] x, input clk, reset ); wire z[1:8]; s1 trolley (y[3],y[10],y[11],y[12],z[1],z[8],x[1],x[4], x[11],x[12],z[2],z[8],clk,reset); s2 container1 (y[1],y[4],y[6],z[3],z[4],x[1],x[2],x[5],x[7], z[5],z[6],z[7],clk,reset); s5 container2 (y[2],y[5],y[7],z[5],z[6],x[1],x[3],x[6],x[8], z[3],z[4],z[7],clk,reset); s6 container3 (y[8],y[9],z[2],z[7],z[8],x[9],x[10],z[1], z[3],z[4],z[5],z[6],clk,reset); endmodule
```  
**Listing 2**Description of the _top-level_ module. The modelled system was logically synthesised and implemented with Xilinx Vivado 2022.1.2 software. Table 3 presents the utilisation of an FPGA. The decomposed CPS consumes just a fraction of the device's resources. It requires 25 LUTs blocks (<1%) and 27 flip-flops (<1%). Moreover, the system utilises 12% of IO blocks (they are used for validation of the CPS). Finally, the functionality of the system was tested within the physical FPGA. The validation was performed with the use of switches and LEDs available on the Nexys 4 DDR prototyping board (Figure 5 right).