# A Software-Defined Radio for Future Wireless Communication Systems at 60 GHz
## 2 5G Testbed Overview
### FMC126/FMC230 Data Interface
It enables a rapid prototyping of very complex FPGA design by considering the _Mathworks_ model-based design environment, namely _Simulink_, with total abstraction of the chip-set complexity [24; 25]. In this context, OFDM TRX engine (testbed) was packed in SysGen into a customized IP to be integrated into the previously discussed transceiver firmware. However, to design and implement the aforementioned communication system, it is required to understand how a real-time data source engine would be integrated to the data interface of both ADC/DAC reference designs (eight parallel processing paths at 156.25 MHz). In this context, at the transmitter, a DSP interpolation filter is necessary, which would be capable of interpolating the sample rate of 156 MHz to the DAC sampling rate of 1.25 GHz. Such solution was implemented using Finite Impulse Response (FIR) filter banks (clocked at 156.25 MHz) by following the polyphase decomposition algorithm reported in [26]. This solution increases the sampling rate and attenuates the generated spectral images from the up-sampling process using a low-pass filter, which also shapes the transmitted signal bandwidth [5]. On the other hand, on the RX side, the counter part must be implemented. That is, ADC sampling rate is decreased using a down-sampling operation followed by a low-pass filter, removing undesired components that would otherwise overlap (aliasing) into the used band. These two operations together result in a decimation filter [5]. It is worth noting that for the I/Q up-/down- conversion 16 distributed FIR filters are necessary. A filter bank is characterized by a parallel arrangement of low-, band-, or high-pass filters, required to decompose the spectral content of a certain signal into multiple sub-bands [27]. When the filter bank is implemented based on a low-pass prototype filter, which corresponds to the 0 th  
Figure 9: Block diagram of the proposed digital IF RF transceiver architecture. band, the other uniform sub-bands are obtained by frequency shifting the prototype filter frequency response [28]. In this case, it is known as DFT filter bank and the graphical representation of its frequency response is illustrated in Figure 10.  
Furthermore, the polyphase decomposition algorithm [26] can be employed to enable an efficient real-time implementation of uniform filter banks, while ensuring the perfect-reconstruction of the analysis/synthesis process. Since eight parallel signal processing paths are required per I/Q path, eight analysis/synthesis FIR filters were carefully designed and implemented, considering the following procedure:  
1. **Filter response type**: It is well known that pulse shaping with raised cosine is characterized by a zero-Inter-Symbol Interference (ISI) [5]. That is, despite its impulse response extending over several other symbol periods, at the decision points, there is neither constructive nor destructive interference. Therefore, in this work, a square root raised cosine matched filter pair was considered, which have the same zero-ISI properties of the raised cosine [5]. 2. **Filter order and frequency specifications**: The interpolation/decimation filter was designed with the aid of the _Matlab_ FDAtool algorithm. In this tool, the normalized LPF cut-off bandwidth was set to 0.125, which is the relation between the clock rates of a single processing path and the DAC core. Moreover, both _Kaiser_ window Beta, and filter roll-off values were set to 2 and 0.25, respectively, since this configuration was found to be the best compromise between passband ripple, stop-band attenuation, and transition band. Finally, filter order was chosen to be 62, since it was also a compromise among system complexity, stop-band attenuation, and transition band. 3. **Distributed implementation of interpolation/decimation**: Both filter banks were implemented using multiple parallel FIR digital filters.