## 4 Experimental Results and Discussion  
Experimental measurements were performed with the implemented overall system operating at different data rates up to 128 Mbps employing a Pseudo-Random Bit Sequence (PRBS) of length 2\({}^{31}\)-1 (i.e., the data stream) generated by the FPGA board with an average number of pulses transmitted for each bit equal to 1.5 pulses/bit. Moreover, a 1.5 mm thick diffuser ED1-C20-MD (Thorlabs Inc., Newton, NJ, USA) was inserted between the VCSEL and the photodiode to emulate the presence of skin or tissue [11; 23]. For the considered distances between the VCSEL and the photodiode of only few millimetres, the diffuser reduces the laser power of about a factor 10. Furthermore, the transmission channel could be considered as a \"noisy channel\" and the BER has been directly evaluated through experimental measurements since it depends on the channel condition mainly related to the employed diffuser. More in detail, the BER has been evaluated through the FPGA board considering the system under different working conditions: variations of the laser pulse amplitude and duration as well as changes of the distance between the VCSEL and the photodiode. In particular, in the operating conditions at 128 Mbps, the bit period \(T\) is 7.8 ns and the laser pulse duration was reduced to about 800 ps corresponding to a duty-cycle \(T_{0}\) of 10%. This system set-up allowed us to achieve the optimum trade-off between data rate, BER and power consumption. In principle, for a fixed data rate, the duty-cycle \(T_{0}\) of the pulses (i.e., the laser pulse duration) can be reduced providing lower power consumptions at the expenses of an increase of the BER value. On the contrary, for achieving a minimum fixed BER value, it is possible to decrease the duty-cycle of the laser pulses providing a lower power consumption against a reduction of the data rate that, in some case, could imply a worst system power efficiency. In our case, at 128 Mbps transmission data rate and \(T_{0}\) = 10% laser pulse duty-cycle, the highest measured BER is less than \(10^{-9}\), achieved for a total maximum distance lower than 4 mm including the presence of the diffuser, with an estimated maximum total power consumption of the overall system of about 5 mW, the 10% of which is related to the coding and decoding digital systems. In this regard, any clock synchronisation mismatch affecting a correct data communication has been also taken into account in the evaluation of the BER since timing misalignments of the clock signal (i.e., clock synchronisation errors) provide bit errors in the decoding system. In addition, it is important to consider that in the proposed architecture, the coding system in the transmitter block does not include any error-correction process that further would improve the BER. In this sense, for example, Hamming and Golay error-correction codes could be considered as suitable solutions to be implemented by an additional low power circuitry enhancing the BER of few orders of magnitude with an additional energy consumption of only 3-4 pJ/bit [19; 20]. Figure 5 reports a picture of the overall implemented system together with the related block scheme of the experimental set-up showing its main components. In particular, the transmitter and the receiver blocks are connected to the FPGA board and the two XYZ translation stages allow us both to perform the optical alignment between the VCSEL and the photodiode and change their relative distance. Figure 6 shows an example of the main signals related to the transmitter and the receiver blocks operating at 128 Mbps. From top to bottom: the green trace is \(\mathrm{CLK}_{T}\), the yellow \(S_{T}(t)\), the purple \(U_{T}(t)\) and the blue \(S_{R}(t)\).