# Performance Analysis of Rate Splitting in Massive MIMO Systems with Low Resolution ADCs/DACs
## 4 Energy Efficiency Analysis  
In this section, we analyze the EE of the massive MIMO with low-resolution ADCs/DACs. The ADCs and DACs are one of the high power consuming components of the RF chains at the BS and the power consumption grows exponentially with the number of quantization bits. Although high-resolution ADCs and DACs enhance the SE, the EE suffers as a result of the high power consumption. Equipping the massive MIMO systems with low-resolution ADCs/DACs sacrifices the SE performance but the EE can be improved. Therefore, it is imperative to study the EE in the proposed RS massive MIMO system. From [35], the EE is defined as  
\[\mathsf{EE}=\frac{B\times R_{\mathsf{SE}}}{\mathsf{P_{total}}} \quad\text{bit}/\text{Joule}, \tag{31}\]  
where \(R_{\mathsf{SE}}\) and \(\mathsf{P_{total}}\) denotes the SE given by (18) and \(B\) represents the system bandwidth. We set a system bandwidth of \(B=20\) MHz. Moreover, \(\mathsf{P_{total}}\) is the total power consumption at the BS. We consider the power consumption model in [16; 22; 35]. The \(\mathsf{P_{total}}\) is expressed as  
\[\mathsf{P_{total}}= M[P_{\rm mix}+P_{\rm filt}]+2P_{\rm syn}\] \[+M[P_{\rm LNA}+P_{\rm mix}+P_{\rm IFA}+P_{\rm filter}]\] \[+M[(\zeta_{A}+\zeta_{D})P_{\rm AGC}+P_{\rm DAC}+P_{\rm ADC}], \tag{32}\]where \(P_{\rm PA}\), \(P_{\rm mix}\), \(P_{\rm filt}\), \(P_{\rm syn}\), \(P_{\rm LNA}\), \(P_{\rm FEA}\), \(P_{\rm filt}\), \(P_{\rmAGC}\), \(P_{\rm DAC}\), and \(P_{\rm ADC}\) denote the power consumption of the power amplifier (PA), the mixer, the active filters at the transmitter side, the frequency synthesizer, low-noise amplifier (LNA), the intermediate frequency amplifier, the active filters at receiver side, the automatic gain control (AGC), DACs, and ADCs, respectively [35]. Furthermore, \(\zeta_{A}\) and \(\zeta_{D}\) are the flags related to the bit resolution of the DACs and ADCs, respectively, where \(\zeta_{A}(\xi_{D})=0\) if \(b_{A}(b_{D})=1\) and \(\zeta_{A}(\zeta_{D})=1\) if \(b_{A}(b_{D})>1\). The power consumption of the DACs and ADCs are related to the bit resolution by [35]  
\[P_{\rm DAC}=\frac{1}{2}V_{\rm dd}I_{0}(2^{b_{D}}-1)+b_{D}C_{\rm p}(2B+f_{\rm cor })V_{\rm dd}^{2}, \tag{33}\]  
and  
\[P_{\rm ADC}=\frac{3V_{\rm dd}^{2}L_{\rm min}(2B+f_{\rm cor})}{10^{-0.1525b_{A}+ 4+8.838}}, \tag{34}\]  
where \(V_{\rm dd}\), \(I_{0}\), \(C_{\rm p}\), \(f_{\rm cor}\), and \(L_{\rm min}\) denote the power supply of converter, the unit current source corresponding to the least significant bit (LSB), the parasitic capacitance of each switch in the converter, the corner frequency of the \(1/f\) noise, and the minimum channel length for the given complementary metal oxide semiconductor (CMOS) technology, respectively [35]. In the simulation results, we set the following values to calculate the EE [35]: \(P_{\rm mix}\) = 30.3 mW, \(P_{\rm filt}\) = \(P_{\rm filt}\) = 2.5 mW, \(P_{\rm syn}\) = 50 mW, \(P_{\rm LNA}\) = 20 mW, \(P_{\rm FEA}\) = 3 mW, \(P_{\rmAGC}\) = 2 mW, \(V_{\rm dd}\) = 3 V, \(I_{0}\) = 10 uA, \(C_{\rm p}\) = 1 pF, \(f_{\rm cor}\) = 1 MHz, and \(L_{\rm min}\) = 0.5 uA, respectively.