# Latency-Aware Accelerator of SIMECK Lightweight Block Cipher
## 4 Implementation Results and Comparisons
### Results  
The proposed SIMECK design is implemented in a Verilog HDL using a Vivado IDE tool (v.2019.2). For Kintex-7, Virtex-7, and Artix-7 FPGA, the used devices are xc7k325t-2 ffg900c, xc7 vx485T-2 ffg1761, and xc7a200t-2 fbg676c. For the performance evaluation of our design in terms of various design constraints, i.e., area, clock cycles, latency, throughput, and power, we have provided a numerical flavor of the results in Table 2. Column one provides the implementation device. Columns two to five present the area information in look-up-tables (LUTs), Slices, flip-flops (FFs), and DSPs. Similarly, the timing information in clock cycles (CCs), provided period (PP), clock frequency (Freq in MHz), latency (Lat in us), and throughput (Thr in Mbps) are shown in columns six to ten. Finally, the last column provides the total consumed power. Note that the area information reported in Table 2 is obtained from the Vivado IDE tool after the post-place-and-route level. The clock cycles are calculated using Equation (4). The reciprocal of the provided time period to operate our circuit determines the operating frequency and is (also) obtained from the Vivado tool. The time to compute one encryption and decryption operation is the latency and is calculated using Equation (5). The ratio of one over latency is throughput and can be calculated using the following Equation (6). \[\text{Clock cycles}=\frac{\text{time for simulation end}-\text{time for simulation start}}{\text{Provided clock period}} \tag{4}\]  
\[\text{Latency (in $\upmu$s)}=\frac{\text{Clock cycles}}{\text{Clock frequency (MHz)}} \tag{5}\]In Equation (4), the time for simulation end and time for simulation start determines the total required time for our SIMECK architecture to encrypt/decrypt a block of plaintext. Moreover, the provided clock period determines the provided period to clock. _Designs running at higher circuit frequencies._ As shown in Table 2, on Kintex-7, Virtex-7, and Artix-7 devices, (i) the utilized FPGA Slices are 49, 51, and 50, (ii) the used LUTs are 157, 162, and 164. For all Kintex, Virtex, and Artix devices, the used FFs and DSP blocks are 89 and 2, respectively. Concerning the timing information, the proposed architecture takes 16 clock cycles to compute one encryption and decryption over 32-bit data. Moreover, we obtain the highest clock frequency of 388 MHz on Artix-7 FPGA. On Kintex-7 and Virtex-7 devices, the achieved clock frequency is 382 and 379 MHz (shown in column eight of Table 2). Instead of the clock cycles and the operational frequency, the minimum time (latency) of 0.041 \(\upmu\)s for one encryption and decryption computation is required for Kintex-7 and Artix-7 FPGA. A bit higher computation time of 0.042 \(\upmu\)s is needed for one encryption and decryption over Virtex-7 FPGA which is comparatively 1.02 (ratio of 0.042 with 0.041) times higher than Kintex-7 and Artix-7 implementations. Similar to latency results, the highest throughput of 24.39 is achieved for Kintex-7 and Artix-7 FPGA. A throughput of 23.80 is calculated for Virtex-7 FPGA. The consumed power of our proposed architecture is estimated and evaluated using a Vivado IDE tool. However, as shown in Table 2, the least consumed power of 172 mW is achieved for Kintex-7 FPGA while the highest 189 mW power we have obtained for Artix-7. For our architecture, one of the reasons to consume more power is the higher clock frequencies for parallel computation of small segments of key and data blocks. Using a serial architecture instead of the segmented design (as we employed in this work), the power consumption can be reduced but with latency overhead. Even if we are utilizing limited resources as an area, the serial design approach further reduces the hardware area of our design. In a nutshell, we are utilizing lower resources and achieving higher circuit frequencies with power overhead. Therefore, there is always a trade-off.