## 1 Introduction  
Cryptographic hardware circuits ensure efficient and secure communications for data exchange and signature generation or verification. These circuits require various arithmetic and logical operations to implement cryptographic protocols or algorithms. The arithmetic operations include addition, subtraction, multiplication, inversion, etc. Among these, polynomial multiplication stands out as a crucial task in the implementation of efficient cryptographic circuits, given its status as the most computationally intensive operation in cryptographic schemes, as highlighted in [1; 2; 3; 4; 5; 6]. Polynomial multiplication entails the multiplication of two polynomials, denoted as \(a\) and \(b\), to yield a resultant polynomial, represented as \(c\). The degree of the consequent polynomial is the sum of the degrees of the two input polynomials. As discussed in [1; 3], polynomial multipliers can be broadly structured into non-digitized and digitized designs. The non-digitized multipliers operate on bit levels, while the digitized multipliers consider different lengths of digits and segments. Non-digitized and digitized multipliers can further be classified into serial and parallel designs, as described in [7]. These serial and parallel designs can further be categorized into four branches: (i) bit-serial, (ii) digit-serial, (iii) bit-parallel, and (iv) digit-parallel. The non-digitized bit-serial multipliers, exemplified by Schoolbook and Booth, undertake polynomial multiplication on a bit-by-bit basis, generating a series of partial products. These partial products are subsequently combined through addition to form the resultant polynomial. Conversely, non-digitized bit-parallel multipliers divide the input polynomials into multiple segments and perform multiplication on these segments [1]. The inner product of these divided portions is calculated, and the resultant polynomial is derived through addition and subtraction operations. The Karatsuba multiplier is a renowned example of a bit-parallel multiplier [8]. On the other hand, digit-serial and digit-parallel multipliers split one polynomial into smaller segments [3] and consider each digit or segment for multiplication with another input polynomial in either serial or parallel fashions. Selecting appropriate serial and parallel designs of non-digitized and digitized multipliers depends on the targeted application. For example, wireless sensor nodes (WSNs), radio-frequency identification networks (RFID), autonomous systems, homomorphic encryption, secure multi-party computation, error-correcting codes like Reed-Solomon (RS), and signal-processing algorithms for filtering, convolution, and correlation demand are-optimized hardware accelerators of polynomial multiplication methods [9; 10]. Furthermore, applications like network servers demand high-speed polynomial multiplication architectures [2]. In addition, the current cryptosystems based on RSA and elliptic-curve cryptography (ECC) demand area-efficient and high-speed polynomial multiplication architectures [2]. Moreover, for ECC-based cryptosystems, the National Institute of Standards and Technology (NIST) recommends different prime and binary field lengths, further necessitating flexible multiplier architectures. Concerning the applications discussed above, it is clear that most applications demand area-optimized implementation of polynomial multipliers to realize the cryptographic algorithms (or protocols) on different implementation platforms [5; 11]. Moreover, polynomial multiplication is in critical demand in several cryptographic applications, and this frequent demand for polynomial multiplication necessitates flexibility. Regarding these demands, we have targeted a bit-serial Booth polynomial multiplier for our implementation. The Booth multiplier is selected because of the low resource utilization compared to the bit-parallel, digit-serial, and digit-parallel multiplication approaches.