# An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios
## 3 Baseband Modulator Architecture
### Top-Level Architecture  
From a top-level perspective, our design (Figure 7) makes use of the hybrid (HW/SW) nature of the Xilinx Zynq architecture that contains two sections: the Processing System (PS) and the Programmable Logic (PL). The PS comprises an ARM Cortex-9 processor and a 512 MB DDR memory controller. The ARM core manages and triggers reconfiguration procedures and sets up data transfers between the DDR memory and the PL. The PL section is then divided into three domains: the baseband processing domain, the DFS domain, and the DPR domain. The baseband processing domain contains the Reconfigurable Partitions (RPs) that can be dynamically reconfigured to implement different 5G waveform modulators. In this design, three independent RPs are considered: RP\({}_{1}\) implements OFDM modulation modes only; RP\({}_{2}\) implements FBMC and OFDM modulation modes; and RP\({}_{3}\) implements UFMC and OFDM modulation modes. At this stage, an alternative system partitioning strategy could consider an RP for each block in the datapaths or by identifying hardware modules common to all configurations and keeping them in the  
Figure 6: Example of a shift-and-add graph to implement a non-trivial multiplication by 0.90625. Figure 7: Top-level architecture. HPx: High Performance ports, GPIO: General Purpose I/O, RP, Reconfigurable Partition. system static part (outside the RPs). However, a higher reconfiguration resolution would enlarge the amount of partial bitstreams to store. The implementation of the whole modulators in a single RP also permits the global place-and-route optimization of the processing chain, contributing to an overall smaller reconfigurable area and, consequently, smaller reconfiguration latencies. When the system is started up, input data files are downloaded from an SD card to the DDR memory. Then, the operation cycle of the baseband processing domain consists of the following steps: (1) fetch input data from, the DDR and feed it to the baseband modulator(s); (2) perform baseband modulation and send the modulated data back to the DDR memory. In a real application, the reconfigurable baseband processor implemented in this work would be integrated with all-digital transceivers such as the ones proposed in [34]. The DMA controller alleviates the PS load related to data transfers to/from the DDR and thus improves baseband processing throughput. The baseband modulators were designed to run at a clock frequency of 100 MHz. However, through DFS, the clock frequency can be changed at run-time in order to adapt the system to different throughput requirements or power consumption constraints. The DFS implementation follows an approach similar to [23], comprising a Mixed-Mode Clock Manager (MMCM) primitive and a DFS controller engine. The MMCM provides access to the Dynamic Reconfiguration Port (DRP) that allows for writing configuration bits to change MMCM output clocks at run-time. A 100 MHz input reference clock signal provided by the PS (FCLK0) is used by the MMCM to generate an output clock signal for baseband processing purposes. Four MMCM output clock modes are considered: 100 MHz, 66.7 MHz, 33.3 MHz, and 16.7 MHz. The 100 MHz clock frequency was the reference frequency for implementation, while the other values were based on the 2\({}^{th}\) scaling of the LTE sampling frequency proposed for 5G systems [8]. Applying it to the sampling frequency for 10 MHz LTE channelization (15.36 MHz), we have \(2^{1}\times 15.36\,\mathrm{MHz}=30.72\,\mathrm{MHz}\) and \(2^{2}\times 15.36\,\mathrm{MHz}=61.44\,\mathrm{MHz}\). To change the baseband processing clock frequency, the PS defines the MMCM output clock mode through the DFS controller mode port and writes '1' to the en port. After the locked signal becomes active, the baseband modulators are ready for processing. The DPR implementation provides an infrastructure to access the FPGA configuration memory.