# Arrayable TDC with Voltage-Controlled Ring Oscillator for dToF Image Sensors
## 4 Analysis and Discussion of Simulation Results  
The TDC chip design is fabricated using the standard SMIC 180 nm BCD CMOS process, the overall area is shown in Figure 11, the TDC layout area is 70 \(\upmu\)m \(\times\) 88 \(\upmu\)m, and there are mainly preprocessing circuits, VCRO, encoders, counter, and a memory circuit, which do not include the peripheral circuits connected to the pin pad. At a supply voltage of 1.8 V and 25 degrees Celsius, the post-layout simulation results show an average current of 903.1 \(\upmu\)A and a power consumption of 1.625 mW. The test of static characteristics of TDC circuits includes dynamic range, time resolution, and nonlinear error [7]. The dynamic range and time resolution can be expressed by constructing the transfer characteristic curve, and the nonlinear error can be obtained according to the transfer characteristic curve. The specific test method of the transfer characteristic curve is as follows: firstly, the time interval between START and STOP is stepped at an interval of 500 ps of the coarse counting period, which is used to detect the dynamic range of the circuit measurement. Then a few critical times are selected as START points and stepped in the same way with a time length of 10 ps, and then the input time intervals corresponding to the jumps in the output results are recorded, and the time intervals between the two jump points are the actual time resolution. The statistical input time interval STARTs from 10 ps to 1.2 \(\upmu\)s, and the Monte Carlo simulation transfer curve of the TDC is shown in Figure 12. The measured input time interval and the measurement time interval can maintain a strong linear relationship, in which the nonlinear error is less than one resolution of 156 ps. Figure 10: Timing diagram of preprocessing circuit. Figure 9: Preprocessing circuit structure. In evaluating the nonlinearity error of the TDC system, differential nonlinearity (DNL) is shown in Figure 13, and integral nonlinearity (INL) curves were obtained as shown in Figure 14, based on all the data obtained from the 0 to 1.2 s resolution test. The results show that \(-0.98\) LSB \(<\) DNL \(<0.93\) LSB and \(-0.88\) LSB \(<\) INL \(<0.975\) LSB, which are both less than \(\pm 1\) LSB (1 LSB = 156 ps), indicating that the TDC circuits have a high degree of linearity and a small range of error fluctuations. Figure 11: TDC layout. Figure 12: TDC post-layout simulation. Table 1 summarizes the key performance metrics of the proposed TDC in comparison with existing techniques. A paper [1] presented in 2021 uses address latches to store the signals at the moment when STOP comes, which enables a single TDC to measure multiple events. Ref. [10] does this by combining a Union Reference Counter (URFC) with an interpolated delay line to obtain high accuracy and a wide dynamic range. However, its sampling circuit uses a D flip-flop, which has insufficient sensitivity and is prone to introducing nonlinear errors during high-frequency clock-phase sampling. One should adopt a comparator structure circuit to do the sampling, which effectively reduces the occurrence of sampling error and improves the linearity of the TDC, which also requires time correction processing, has a more complex structure, and the dual delay loop is susceptible to PVT. [PERSON]. [22] proposed a gated ring oscillator (GRO) architecture to reduce the area and power consumption. Nevertheless, it adopted a D flip-flop for the sampling with a resolution of 1.76 ns at 1 KS/s sampling frequency. There is also a paper [23] which used a D flip-flop to do the sampling; limited by the D-trigger, the minimum resolution was only 36.2 ps. With the phase arbiter circuit proposed in this paper, the resolution can be further improved. Compared with previous work, the TDC circuit designed in this paper achieves a large dynamic range with high linearity while maintaining a relatively  
Figure 14: TDC-measured nonlinear error INL. Figure 13: TDC-measured nonlinear error DNL. small-time resolution.