# Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers
## 3 Related Works
### Parallel Implementation of CTR Mode of Operation on the NEON Engine
#### 4.2.2 HIGHT-CTR Optimization
(Our Work 1: Proposed parallel implementation, Our Work 2: Proposed CTR mode optimization, and #Data parallelism: the number of encryptions performed simultaneously on NEON engine, Cpb: Clock per byte, and Improvement: Improved performance compared to previous work). **Author Contributions:** Writing--original draft, J.S. ; Writing--review and editing, S.C.S. Both authors have read and agreed to the published version of the manuscript. **Funding:** This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1F1A1058494). **Institutional Review Board Statement:** Not applicable. **Informed Consent Statement:** Not applicable. **Data Availability Statement:** Not applicable. **Conflicts of Interest:** The authors declare no conflict of interest. ## References

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