# Hardware Prototyping and Validation of a W-\(\Delta\)DOR Digital Signal Processor
## 3 W-\(\Delta\)DOR Hardware Implementation
### Experimental Results  
The W-\(\Delta\)DOR bread-board is composed of a 0.18 \(\upmu\)m ATMEL KaT ASIC (i.e., ATC18 RHA family) integrated in the TAS digital transponder platform [12; 15] and by an ALTERA FPGA Stratix II DSP development board implementing the W-\(\Delta\)DOR core. The SRAM memories, integrated in the TAS digital transponder platform, are shared between the ATMEL KaT ASIC and the FPGA through a common address and data bus. The KaT ASIC includes the LEON2-FT microprocessor that is devoted to the W-\(\Delta\)DOR core configuration and monitoring. The W-\(\Delta\)DOR signals, converted in the analog domain by the FPGA development board DAC, were characterized using a Keysight PSA E4440 spectrum analyzer (the TAS experimental setup is shown in Figure 5).  
The testbed is composed of:  
* FAT Digital module
* RF module that includes the RX section plus the TX section
* Up-link signal generation and modulation that includes: U/L signal generator Subcarrier and data generators BER meter  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**RESOURCES** & **USAGE** & **QUOTA** \\ \hline COMBINATIONAL ALUTS & 5720/143250 & 4\% \\ DEDICATED LOGIC REGISTERS & 13488/143520 & 9\% \\ ALMs: partially or completely used & 9075/71760 & 13\% \\ Total LABspartially or completely used & 1193/8970 & 9\% \\
1/O PINS & 79/743 & 11\% \\ \hline \hline \end{tabular}
\end{table}
Table 1: ALTERA Stratix II EP2S180 FPGA Resources utilization.  
The experiments were performed on different test cases corresponding to different sets of the configuration, provided in Table 2.  
The spectra obtained by simulation and from experimental measurements, illustrated in Figures 6 and 7 (Test Case 1) and in Figures 8 and 9 (Test Case 4), match well, excluding a gain bias due to the digital-to-analog conversion.  
In particular, Figure 6 shows the measured output spectrum achieved with the subcarrier 1 at frequency F1/2 and subcarrier 2 at frequency 2F1, both modulated with the PN code at chip rate F1/2. In this case, the modulation index is set to 1 rad-pk. The DAC sampling frequency is about 76 MHz,  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**PARAM.** & **TEST 1** & **TEST 2** & **TEST 3** & **TEST 4** & **TEST 5** \\ \hline subc1 freq. & F1/2 & F1/2 & F1/2 & F1/2 & F1/3 \\ subc2 freq. & 2F1 & 2F1 & 2F1 & 2F1 & 3F1/2 \\ ChipRate1 & F1/2 & F1/8 & F1/8 & F1/8 & F1/3 \\ ChipRate2 & F1/2 & F1/8 & F1/4 & F1/2 & F1/3 \\ ChipRate3 & F1/2 & F1/8 & F1/2 & F1/3 & F1/3 \\ \(\phi_{1}\) & 1 & 0.5 & 0.25 & 0.125 & 0.125 \\ \(\phi_{2}\) & 1 & 0.5 & 1 & 0.125 & 1 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Test cases configuration parameters.  
Figure 5: TAS W-\(\Delta\)DOR experimental setup.  
thus the Nyquist window from 0 to about 38 MHz is reported. In Figure 8, the measured output spectrum corresponding to Test Case 4 is reported. In this condition, the subcarrier 1 at frequency F1/2 is modulated by a PN code at F1/8, while the subcarrier 2 at frequency 2F1 is modulated with PN code at rate F1/2. This test also shows the ability of the W-\(\Delta\)DOR to independently set the amplitude of each subcarrier.  
Figure 6: Test case 1 measured.  
Figure 7: Test case 1 simulated.