# DRAM Retention Behavior with Accelerated Aging in Commercial Chips
###### Abstract  
The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market, posing a significant threat if employed in critical infrastructure. In this work, we look at the retention behavior of commercial DRAM chips from real-time silicon measurements and investigate how the reliability of DRAM cells degrade with accelerated aging. We analyze the retention-based errors at three different aging points to observe the design-induced variations, analyze the pattern dependency, and explore the impacts of accelerated aging for multiple DRAM vendors. We also investigate the DRAM chips' statistical distribution to attribute the vital wear-out effects present in DRAM. We see a continuous increase in retention error as DRAM chips age and therefore infer that the aged retention signatures can be used to differentiate recycled DRAM chips in the supply chain. We also discuss the roles of device signature in DRAM aging and aging-related security implication on DRAM row-hammer error. dynamic random access memory (DRAM); retention error; accelerated aging; bias temperature instability (BTI); time-dependent dielectric breakdown (TDDB) Article  
DRAM Retention Behavior with Accelerated Aging in Commercial Chips  
1  
DRAM Research Group, 1, 2012  
due to the cells' coupling effects, noise, and interference. Data analysis of early failure rate (EFR) leverages the impacts of aging phenomena to distinguish recycled counterfeit chips [1]. [PERSON] et al. [7] discussed a low-cost statistical method based on typical test results from production early failure rate (EFR) analysis, such as \(V_{min}\), \(F_{max}\), and \(I_{ddd}\) to train a one-class classifier using brand-new devices only. It is crucial to use trusted memory chips in order to ensure security in critical applications. Although there are a few works on detecting different recycled memory chips such as SRAM [8] or flash memory [9], no such experiment on DRAM aging is available. [PERSON] et al. [10] discuss the aging effects that degrade DRAM chips and explore its impact reliability of DRAM-based PUF but do not address its use in recycled chip detection. In [11], a technique to identify DRAM origin is presented that discusses a non-invasive scheme to verify individual DRAM specification by exploiting the DRAM latency variations. In [12; 13], effects of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are analyzed with SPICE simulation to show the increase in retention time as the device ages. This research is motivated by the desire to investigate DRAM reliability, name retention behavior with device aging, and develop a practical and effective technique to detect recycled DRAM memory. The main contributions of this article are as follows. * We experimentally demonstrate the retention-based error by violating the minimum retention time during the refresh operation on DRAM rows. We assess the reduced refresh rate's effects as increased soft errors on multiple DRAM memory modules for different patterns and timing parameters. * We utilize the design-induced variation of true cells and anti-cells on different modules to develop a scheme to ensure the maximum stress and wear-out effects during the accelerated aging test. * We highlight the significant observations in retention behavior with the accelerated aging process. * We examine the statistical distributions of retention error with aging and analyze its application to detect recycled DRAM chips. The rest of the paper is organized as follows. In Section 2, we briefly present the DRAM organization and operations as well as common wear-out mechanisms. In Section 3, we discuss the testing methodology for the DRAM retention test and accelerated aging. We describe the experimental setup and present the experimental results in Section 4.