## 5 Results and Discussion
### 1010 Limited Sequence Detector  
We assume that the limited sequence detector should recognize the fixed sequence 1010 appearing on the data input after startup, along with the next four rising edges appearing on clk. After such a sequence appears, the value 1 should appear at the output. For other sequences, the value 0 should appear in the output. We assume that what is important for us is the way the system operates until the first 6 rising edges appear on clk. We assume that the next course of action does not matter. During the experiments, a table describing the system composed of 16 sets of data was adopted so that each possible combination of the sequence of 4 possible values corresponds to one set of data. Only the data set that corresponded to the sequence 1010 contained the output value 1 when the last value from  
Figure 14: An example of a circuit obtained based on the table describing the circuit, part of which is shown in Table 8, using a set of JK, D, T flip-flops and AND, NOT, and OR gates. After reducing the \(number\_columnsCGP\) parameter to 6, only layouts fully compatible with this layout were obtained.  
Figure 13: An example of a system obtained on the basis of the table describing the system, part of which is shown in Table 8. This is a classic series–parallel register system.  
\begin{table}
\begin{tabular}{c c c} \hline
**Clk** & **Inputs** & **Outputs** \\ \hline
1 & 0 & 0 1 1 0 \\ \hline \end{tabular}
\end{table}
Table 8: Description of the serial–parallel register response.  
the sequence 1010 appeared. Table 9 shows only the data set containing the sequence 1010. The remaining data sets output only the values 0 and each of the possible remaining combinations of the four zeros or ones given successively to the input of the system during the first four rising edges given to clk. One of the obtained results (\(num\_columnsCGP=20\), set of functions: JK (function type 0), D (function type 1), T (function type 2), AND (function type 3), OR (function type 4), NOT (function type 5), NAND (type 6 function), NOR (type 7 function)) represents the genotype:  
*([1]0 0 0), ([2]0 1 0), *([3]1 1 1), *([4]6 3 0), *([5]7 1 3), ([6]5 5 0), *([7]2 4 1), *([8]0 0 7), ([9]7 7 3), ([10]0 6 1), ([11]3 10 3), ([12]3 6 11), ([13]4 8 7), ([14]5 8 5), ([15]0 6 3), ([16]4 5 4), ([17]3 14 6), ([18]3 17 11), *([19]3 5 8), ([20]4 14 19), 1 representing the system shown in Figure 15. As can be seen from the presented fragment of the table describing the system, the output states were determined only for the first 6 rising edges given on clk. Figure 16 shows another layout obtained using the same table and the \(number\_columnsCGP\) parameter and the set of functions left unchanged, which shows the following genotype:  
*([1]0 0 0), *([2]7 0 0), *([3]5 2 1), *([4]0 3 1), *([5]2 2 1), *([6]2 5 4), *([7]0 6 2), *([8]3 7 2), ([9]0 5 4), *([10]0 1 7), ([11]0 8 9), ([12]5 4 4), *([13]6 2 4), *([14]3 8 4), ([15]6 14 8), *([16]3 10 10), ([17]6 1 10), ([18]3 16 3), ([19]7 11 16), *([20]3 14 16), 20  
\begin{table}
\begin{tabular}{c c c} \hline
**Clk** & **Inputs** & **Outputs** \\ \hline
1 & 0 & 0 \\ \hline \end{tabular}
\end{table}
Table 9: Description of sequence detector responses.  
Figure 16: Another example of a sequence detector system obtained on the basis of the table describing the system, part of which is shown in Table 9.  
Figure 15: Example of a sequence detector circuit obtained from a table, a part of which is presented in Table 9, using a set of JK, D, T flip-flops and AND, OR, NOT, NAND, and NOR gates.