# Resource-Efficient FPGA Architecture for Real-Time RFI Mitigation in Interferometric Radiometers
## 1 Introduction
Field Programmable Gate Array (FPGA) implementations must balance complex tradeoffs between processing capabilities, resource utilization, and power consumption [19]. Real-time processing requirements necessitate careful optimization of data flow and computational resources, while space operation demands robust error handling and fault tolerance mechanisms [20]. These implementation challenges become particularly hard for interferometric radiometers, where numerous receivers must be processed simultaneously. Some examples of such implementations can be found in [13; 21; 22] for multi-bit inputs. Conventional approaches often rely on dedicated FPGAs for each receiver or receiver pair, leading to increased system complexity, power consumption, and mission costs. Space-grade FPGAs present additional constraints, typically offering fewer resources than their commercial counterparts while demanding more robust design practices and thorough  
Figure 1: Effects of 1-bit quantization on a 15,000 K chirp RFI signal with thermal noise. (**a**) Original unquantized spectrogram showing the chirp’s natural frequency progression. (**b**) After 1-bit quantization, revealing harmonic generation and aliasing effects, among others. validation procedures. Implementation considerations extend beyond basic resource allocation to encompass complex system-level challenges. Clock domain management and synchronization become critical when dealing with multiple data streams and processing stages. Fixed-point arithmetic must be carefully designed to maintain precision throughout the processing chain while minimizing resource usage. Memory bandwidth optimization requires strategic buffering and efficient data movement strategies. Pipeline design must balance throughput requirements against resource constraints, often necessitating creative approaches to resource sharing and operation serialization. The work presented herein addresses these implementation challenges, describing a practical realization of advanced RFI detection and mitigation algorithms specifically optimized for space-based interferometric radiometers explored in [17]. Through innovative approaches to overclocking, resource sharing, and operation serialization, the implementation achieves significant reductions in FPGA resource requirements while maintaining real-time processing capabilities. The design emphasizes reliability and flexibility, allowing parameter adjustment during mission lifetime while maintaining robust operation in the space environment. The following sections detail the development and validation of this implementation. Section 2 presents a comprehensive block design, examining the data flow architecture and processing stages. Section 3 explores implementation optimization strategies, detailing novel approaches to overclocking, serialization techniques, and resource utilization improvements. Section 4 describes the validation methodology, presenting results from synthetic data testing, hardware-in-the-loop validation, and performance measurements. Finally, Section 5 offers conclusions and examines potential pathways for future implementation improvements.