## 1 Introduction  
Fault vulnerability and protection immaturity constrain the development of the voltage source converter-based high-voltage direct current (VSC-HVDC) system, especially in terms of DC side fault at high power levels. Thus, reliability has become an important challenge in multilevel converter-based (MMC)-HVDC with long-distance transmission lines [1; 2]. The lack of a perfect fault isolation scheme and mature DC switchgear products are the primary issues [3]. However, the VSC-HVDC system has attracted worldwide attention and research interests due to its advantages with respect to control flexibility and interconnection feasibility. A related analysis of DC faults has been performed to enhance its fault ride through (FRT) ability under DC fault in the VSC-HVDC system [4; 5]. An overview of HVDC system protection mentions that the major limitation in development of VSC-HVDC is the inability to limit fault current, given the limitation of the DC circuit breaker (DCCB) in interruption capability and operation speed [6]. Moreover, limiting fault current can protect the semiconductor device from excessive electrical pressure, particularly insulated gate bipolar thyristor (IGBT) and freewheeling diode in a converter sub-module (SM). Furthermore, restriction of fault current can provide additional time for fault detection and operation delay. Therefore, limiting fault current development and propagation in the VSC-HVDC and multi-terminal HVDC (MTDC) systems is essential. State-of-the-art fault current-limiting (FCL) techniques can be classified into improved SM topologies [7; 8; 9; 10; 11; 12], auxiliary FCL circuits (FCLC) [13; 14; 15; 16; 17; 18; 19; 20], and fault current limiters [21; 22; 23; 24; 25]. The SM topology has been modified to reinforce its fault handling ability, because the classical half-bridge SM (HBSM) is likely to be destroyed under overcurrent if no proper protection scheme is applied, even if insulated gate bipolar translators (IGBTs)are blocked in a timely fashion [26]. Thus, several innovative improvements, including full-bridge SM (FBSM) [7; 8], clamp double SM (CDSM) [9], and hybrid SM, which combines FBSM and HBSM, have been conceived in the SM topology design [10]. Although the FBSM solution can ride through faults without blocking the converter, given its ability to output bipolar voltage, regardless of arm current direction [9], the doubled number and on-state loss of semiconductors are their main drawbacks. A CDSM solution only has 50% higher semiconduction than the HBSM to extinguish the DC arc by blocking IGBTs under nonpermanent fault [10]. However, the MMC converter has generally been regarded as the most appropriate static synchronous compensator to support alternating current (AC) grids in DC pole-to-pole fault scenarios [11]. Thus, enhancing the FRT capability without blocking the converter is crucial. A hybrid MMC topology requires each arm to have the same amount of FBSM and HBSM by considering their nature [10; 12]. Thus, the cost of semiconductor devices and conduction losses have been reduced in comparison with those in the FBSM. However, further research on control strategies in terms of dynamic characteristics and SM voltage balancing is required [2]. Overall, control complexity and high cost are the weaknesses of SM topology-based solutions. Another FCL technology relies on an auxiliary circuit, which consistently includes energy dissipation resistance and an FCL reactor. For example, a hybrid current-limiting circuit (Figure 1a) has been designed to restrain the DC line fault current in the MTDC system [13], which is settled at the end of the DC line between the DCCB and DC converter ports. The energy dissipation resistance \(R_{r}\) is equipped to share the stress on energy absorption element in the DCCB, and the fault current interruption speed is accelerated. However, the tradeoff between FCL performance and the extra cost of the resistor must be considered.