# Review of Ka-Band Power Amplifier
## 3 Topologies
### Power Combining
#### 3.4.3 Differential Amplifier  
The traditional differential circuit is one that can amplify the difference between two input voltages. The circuit structure is shown in Figure 20. The circuit is generally symmetrical, with two inputs and two outputs. The most important advantage of using a differential structure is that the maximum output power of PA can be improved. When the input \(\mathrm{U_{IN1}}\) and \(\mathrm{U_{IN2}}\) are signals of equal amplitude and opposite phase, the input mode is a differential mode input. The final differential output voltage swing is two times the output voltage swing of the single-ended PAs. However, most systems require single-port outputs, a balun transformer and a power combiner, which introduce additional losses. In Ref. [62], a 6-order LC input matching network was presented to expand the bandwidth. At the same time, [PERSON] and [PERSON] presented a 2-stage CS differential broadband PA based on a fourth-order magnetically coupled resonator (MCR) matching network (see Figure 21a) [88]. Compared with [62], both PAs cover the full Ka band, have similar gain and PAE, but the \(\mathrm{P_{sat}}\) and \(\mathrm{P_{1 dB}}\) of [88] and [62] are significantly different, which are 15.3/ 25.3 and 12.9/23.6, respectively. A fully integrated power amplifier with a capacitor-based neutralization technique and transformers and current-combining topology was proposed [89]. A transformer-based power synthesizer is used to combine two differential PA cells which consist of two CS to increase the output power. Fabricated in 28 nm CMOS process, the PA chip achieves \(\mathrm{P_{sat}}\) of 17.9 dBm, peak PAE of 40.7% and output power density of 513.8 mW/mm\({}^{2}\). Figure 21: (a) The 2-stage CS differential PA in 60 nm CMOS [88] (b) 2-stage cascode differential PA in 60 nm CMOS [90]. Figure 20: Differential amplifier circuit schematic diagram. At the same time, [PERSON] presented an inductive neutralization technique implemented in the differential PA in 90 nm CMOS [90]. Four cascode cells are combined as differential power cells. The inductance neutralization structure combined with capacitance neutralization can solve the overall stability problem of the system without reducing the output power. This paper also uses current-combining topology, but current-combining topology will cause a phase imbalance [91]. To solve this problem, a new type of asymmetrical transformers is designed to further compensate the phase imbalance (see Figure 21b). The measured results demonstrate P\({}_{\text{sat}}\) of 26 dBm, peak PAE of 34.1% at 28 GHz, and record output power density of 992.8 mW/mm\({}^{2}\). In [92], it is mentioned that the cold-FET-based interstage matching network can improve the linearization. In order to enhance the linearity and suppress sideband, cold-mode linearizer with additional transmission line was proposed. The PA, composed of 2-stage CS differential amplifiers, achieves 33.6% PAE and 19.7 dB gain while maintaining an output power higher than 16.8 dBm. A summary comparison with power combining PA measurements is given in Table 4.  
As can be seen from Table 4, the P\({}_{\text{sat}}\) of the power-combined PA is very high, especially in GaAs and GaN technologies. In the above data, the saturated output power of