## 3 Proposed Low-Latency Compact Baseband System for Wireless VR
### Baseband Processing with Block-Level Interleaved-BCH Codes
In contrast to the blocks in each CC being arranged in vertical order as in Figure 3, a FS is simply constructed by selecting the 60 blocks in the horizontal direction, taking a block per CC. Compared to the other wireless standards requiring complicated interleaving steps [6; 8], the block-level interleaving in this work is quite simple, remarkably reducing the hardware complexity of the wireless VR baseband system, which is discussed in the following subsection. After the block-level interleaving step, we finally transmit the data frame from FS\({}_{0}\) to FS\({}_{98}\), guaranteeing that consecutive transmitted blocks are always from different CCs. Figure 4 conceptually illustrates how the proposed baseband architecture in TX mode produces the transmitted data. For supporting a seamless data transaction, note that we utilize the doublebuffering scheme realized by adopting two frame-sized buffers, which is denoted as FB0 and FB1. After the de-serializer generates the 16-parallel data stream, which is firstly stored to the input FIFO (IFIFO), the proposed baseband system simply generates the encoded CCs in order by reading 18 bits from IFIFO at a time, as illustrated in Figure 4. Note that we utilize the 18-parallel BCH encoder to calculate 11 parity blocks whenever reading out 88 data blocks from IFIFO. Similar to the conventional systematic BCH encoder architectures in [28; 29], during the parallel encoding, the encoded user data blocks are directly moved to the following processing unit, i.e., the block-level interleaver, which immediately rearranges the input blocks to construct FSs in a round robin manner, as depicted in Figure 4. When the parallel encoder completely generates all the CCs in a data frame, as a result, all the FSs are also constructed and stored in a frame buffer. Then, the FSs are serially moved to the output FIFO (OFIFO), which is accessed by the serializer generating the high-speed bit stream for the 60 GHz RFIC. By utilizing the double buffering scheme, at the same time, the encoder starts to handle the next data frame, supporting a seamless data transaction, as illustrated in Figure 4.  
For the case of RX mode, the process of baseband processing is performed in a reverse order compared to that of TX processing, as depicted in Figure 5. More precisely, as illustrated in Figure 1, the 60 GHz RFIC provides a high-speed bit stream by demodulating the received signals, and the  
Figure 4: Proposed interleaving and buffering scheme for seamless data transaction. Figure 3: Construction of the proposed interleaved BCH codes. analog de-serializer in the proposed baseband system parallelizes it into 18-parallel data stream to serially deliver the received FSs to IFIFO at the digital baseband system in RX mode. Starting from the first data block at the first FS, the block-level de-interleaver directly scatters the received 18b blocks by changing the storing address of the frame buffer. In other words, as shown in Figure 5, the de-interleaver rearranges the received blocks in a round robin manner for reconstructing the received CCs. After transmitting a whole data frame, as a result, the frame buffer stores all CCs in order. The 18-parallel BCH decoder is then activated to correct the erroneous bits by sequentially accessing the CCs. Note that we only transfer the recovered data blocks from the parallel BCH decoder to OFIFO that can accept 18b data at a time.