# GPU@SAT DevKit: Empowering Edge Computing Development Onboard Satellites in the Space-IoT Era
## 3 GPU@SAT DevKit
### GPU@SAT DevBoard and Embedded Software  
The first part of the GPU@SAT DevKit is the integrated hardware and software system that composes the GPU@SAT DevBoard. Figure 2 illustrates the key elements of the system and their interconnections. The DevBoard is based on the Zynq UltraScale+ ZCU104 evaluation platform [61], which is well suited for high-performance computing tasks. Indeed, the ZCU104 platform features a quad-core ARM Cortex-A53 Central Processing Unit (CPU), providing the necessary processing power, and a 64-bit wide Double Data Rate 4 (DDR4) memory integrated within the FPGA's Processing System (PS), ensuring efficient data handling and storage. It also includes the GPU@SAT IP core with eight CUs operating at 250 MHz, within the FPGA's PL. The three components collaboratively form the hardware infrastructure for server operations. The CPU executes the embedded software and manages external communications to the client application via an Ethernet connection. It also coordinates the other components of the board, overseeing the accelerator and accessing the DDR4 memory. The GPU@SAT IP core handles computationally intensive tasks and can directly access memory through Direct Memory Access (DMA). Meanwhile, the memory serves as a shared data space between the CPU and the accelerator, enabling fast and efficient data exchange. The embedded software, responsible for managing the system and providing an abstract representation of its architectural functionality, runs on the CPU and consists of three distinct parts. First, a Linux kernel module offers a unified interface for configuring the GPU@SAT IP core and managing dedicated memory spaces (_buffers_) in the DDR4 memory. Second, a high-level C library provides Application Programming Interfaces (APIs) that simplify interaction with the kernel module. Lastly, the server application handles Transmission Control Protocol (TCP) communication, allowing the DevBoard to interface with the host PC via Ethernet. Overall, the system abstracts the functionality of the server and allows the client to perform the following tasks:  
1. **Configure the GPU@SAT IP core with OpenCL properties:** this involves setting up the necessary parameters for the kernel to be executed, ensuring that the hardware is prepared to handle the specific computational tasks. 2. **Load the binary code of the kernel:** the client can upload the executable binary code corresponding to the kernel, which is then run on the GPU@SAT IP core. Figure 2: Overview of GPU@SAT DevKit. 3. **Allocate memory buffers in DDR4:** the client can allocate shared memory spaces in the DDR4, which are used by both the CPU and the GPU@SAT IP core. 4. **Schedule and execute multiple kernels:** the client has the capability to queue multiple kernels for execution, managing the sequence in which they are run and ensuring that dependencies between kernels are handled efficiently. 5. **Measure and report statistics and performance metrics:** the system can collect and report various statistics related to the execution of the kernels, providing valuable insights into performance and helping to identify areas for optimization. Each of these mechanisms plays a crucial role in streamlining application execution. By configuring OpenCL properties (1) separately from the binary code (2), the same code can be reused across kernels with different configurations, minimizing memory usage and avoiding unnecessary duplication. The ability to allocate shared buffers (3) reduces the overhead associated with memory management and speeds up the execution of kernels that need to share data. Furthermore, by allowing multiple kernels to be scheduled and executed in succession (4), the system minimizes the need for continuous data transfer between the DevBoard and the host PC, significantly speeding up the processing of successive data-sharing kernels, such as those that constitute DL algorithms.