# FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs
## 5 Performance Efficiency of FPGA-QNN
Memory usage remains at the same level in W1A1 and W1A2 models at H folding, which is approximately doubled in the W2A2 model. Figure 16: Accuracy and timing analysis of FPGA and CPU platforms to observe the effects of precision and folding configurations. The results in the tables confirm that the processing time of the test images depends on the convolution factors, not the quantization bits. In MLP, the results point out the reduction in the processing time from approximately 10,000 ms to 14 ms when the folding factor increases in the full-connection layers, with no negative impact on resource usage. With high folding, the number of frames per second (FPS) increases from approximately 1000 to 723 K, corresponding to an acceleration improvement by 700 times. In LeNet, while 535 images can be processed per second in the L folding, this number increases to nearly 6800 in the H folding in all three quantization types. This shows that the LeNet model is accelerated by approximately 12 times with the folding factor H. Similarly to MLP, the processing time is reduced from about 18,600 ms to 1460 ms with H folding. Figure 17 presents the utilization of FPGA resources both in total and in detail across four key resource types. The graph provides a breakdown of usage percentages for different resource categories (e.g., LUTs, FFs) based on model type, precision, and folding parameters. When designing hardware on FPGAs, it is essential to consider that certain resources, such as LUTs and FFs, can often be used interchangeably or as complementary resources. While this flexibility enhances design adaptability, it also necessitates a broader perspective to \begin{table}
\begin{tabular}{l c c c c c c} \hline \hline
**Resource** & \multicolumn{2}{c}{**W1A1**} & \multicolumn{2}{c}{**W1A2**} & \multicolumn{2}{c}{**W2A2**} \\
**Cons.** & **L** & **H** & **L** & **H** & **L** & **H** \\ \hline LUT \% & 19.1 & 21.8 & 22.1 & 28.1 & 22.0 & 35.6 \\ LUTRAM\% & 6.4 & 7.4 & 6.5 & 8.1 & 6.6 & 7.4 \\ FF\% & 13.3 & 17.0 & 14.6 & 20.1 & 14.6 & 23.4 \\ BRAM\% & 5.0 & 9.6 & 5.3 & 9.6 & 8.2 & 18.2 \\ Time (ms) & 10,035 & 13.83 & 10,038 & 13.84 & 10,036 & 14.02 \\ FPS & 996 & 723,000 & 996 & 722,000 & 996 & 713,000 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: FPGA resource consumption for MLP-based accelerator model. \begin{table}
\begin{tabular}{l c} \hline \hline
**Network Metrics** & **Values** \\ \hline Runtime (ms) & 13,825 \\ Throughput (image/s) & 723,327 \\ DRAM in BW (MB/s) & 746.04 \\ DRAM out BW (MB/s) & 0.723 \\ Fclk (MHz) & 100 \\ Batch Size & 10,000 \\ Fold Input (ms) & 0.179 \\ Pack Input (ms) & 0.114 \\ Copy Input Data To Device (ms) & 48,553 \\ Copy Output Data From Device (ms) & 0.6058 \\ Unpack Output (ms) & 1.1074 \\ Unfold Output (ms) & 0.2057 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: MLP W1A1 accelerators network metrics. \begin{table}
\begin{tabular}{l c c c c c c} \hline \hline
**Resource** & \multicolumn{2}{c}{**W1A1**} & \multicolumn{2}{c}{**W1A2**} & \multicolumn{2}{c}{**W2A2**} \\
**Cons.** & **L** & **H** & **L** & **H** & **L** & **H** \\ \hline LUT \% & 19.87 & 35.77 & 22.87 & 50.63 & 22.29 & 83.43 \\ LUTRAM\% & 6.13 & 7.97 & 6.80 & 10.16 & 6.56 & 10.30 \\ FF\% & 10.79 & 22.40 & 12.47 & 25.14 & 11.87 & 41.45 \\ BRAM\% & 4.64 & 37.50 & 5.36 & 32.5 & 5.36 & 72.86 \\ Time (ms) & 18,677 & 1467 & 18,672 & 1468 & 18,674 & 1467 \\ FPS & 535 & 6816 & 535 & 6811 & 535 & 6816 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: FPGA resource consumption for LeNet-based accelerator model. evaluate the effective utilization of resources comprehensively. In this context, analyzing resource usage solely in a fragmented manner may not suffice for optimizing design decisions. Instead, adopting a holistic analytical approach that encompasses total resource utilization is crucial. The graph addresses this need by offering valuable insights into FPGA resource consumption from both a detailed and an overall perspective.