# Elliptic-Curve Crypto Processor for RFID Applications
## 2 Preliminaries
### PM Computation over \(Gf(2^{M})\)
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Ref. \#**} & \multirow{2}{*}{**m**} & \multirow{2}{*}{**Device**} & **Clock** & **Clock** & **Latency** & **Area** & **Power** \\  & & & **Freq.** & **Cycles** & **(in ms)** & **LUTs/FFs for FPGAs** & **(in \(\mu\)W)** \\  & & & **(in MHz)** & **(CCs)** & & **\# of Gates/mm\({}^{2}\) for ASICs** & \\ \hline \multicolumn{10}{l}{ASIC implementations of ECC, provided specifically for RFID applications} \\ \hline
[14] & \(GF(2^{163})\) & 0.13 \(\upmu\)m & 1.13 & 275,816 & 244 & 12,506/– & 36.63 \\
[19] & \(GF(2^{163})\) & 0.35 \(\upmu\)m & 13.56 & 430,654 & 31.8 & 15,094/– & – \\
[20] & \(GF(2^{163})\) & 0.18 \(\upmu\)m & 0.847 & 296,964 & 350.6 & 13,200/– & – \\
[21] & \(GF(2^{163})\) & 0.13 \(\upmu\)m & 0.400 & 219,148 & 547.8 & 11/20.2/– & 7.27 \\
[22] & \(GF(2^{163})\) & 130 nm & 200 & 500,000 & 2.50 & –/0.15 & – \\ This work & \(GF(2^{163})\) & Kintex-7 & 909 & 2627 & 2.88 \(\times\) 10\({}^{-3}\) & 1786/1855 & 647 \\ \hline \multicolumn{10}{l}{FPGA based ECC architectures for various constrained cryptographic applications} \\ \hline
[18] & \(GF(2^{163})\) & Virtex-7 & 369 & 3960 & \(10.7\times 10^{-3}\) & 2207 slices & – \\
[23] & \(GF(2^{163})\) & Virtex-5 & 359 & – & \(110\times 10^{-3}\) & 473 slices & – \\
[24] & \(GF(2^{163})\) & Virtex-7 & 383 & – & \(9.9\times 10^{-3}\) & 4162/1832 & – \\
[25] & \(GF(2^{163})\) & Virtex-5 & 288.5 & – & \(24.5\times 10^{-3}\) & 3122 slices & – \\
[26] & \(GF(2^{163})\) & Virtex-7 & 397 & – & \(10.5\times 10^{-3}\) & 4721/1886 & – \\ \hline \multicolumn{10}{l}{This Work} & \(GF(2^{163})\) & Virtex-5 & 571 & 2627 & 4.60 \(\times 10^{-3}\) & 2546/1858 & 821 \\ \multicolumn{10}{l}{Clock cycles for Ref \#[22] are calculated using the product of frequency to latency. FPGA slices for our Virtex-5 and Virtex-7 implementations are 637 and 447.} \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Comparison to state-of-the-art ECC-based accelerator architectures. our high-performance implementation results in more power consumption as compared to state-of-the-art solutions. Therefore, our high-performance implementation consumes 17.6 (ratio of 647 over 36.63) and 88.9 (ratio of 647 over 7.27) times higher power as compared to [14; 21] respectively. When comparing our power-optimized implementation with [14; 21], this figure reduced to 4.3 (ratio of 161 over 36.63) and 22.1 (ratio of 161 over 7.27). There is always a trade-off between several design parameters (i.e., performance, area, and power). For example, higher performance results in a higher power. As provided earlier in Section 4.1.2, further power consumption of our architecture on FPGA devices can be reduced with the expense of additional CCs by using a single shift register/buffer instead of three. #### 4.2.2 Comparison with Fpga Based Architectures

For a realistic comparison with the state-of-the-art, we have synthesized our proposed architecture in similar devices that have been utilized in recent state-of-the-art publications that include [18; 23; 24; 25; 26]. **Comparison on Virtex-5 [23; 25]:** Comparison in terms of clock cycles and power with [23; 25] is not possible as this information is not reported. Therefore, the proposed accelerator architecture is 1.59 (ratio of 571 over 359) times faster in terms of clock frequency as compared to the PM architecture, reported in [23]. This is due to the use of a faster register array in our work while a flexible memory is utilized in [23] to support multiple PM algorithms (Binary, Montgomery, and Frobenius map) in a single design. A larger memory size drives a longer critical path delay as compared to the memories having shorter size. The longer critical path delay(s) ultimately reduces the clock frequency. As compared to [25], the proposed architecture is 1.97 (ratio of 571 over 288.5) times faster as we have utilized an array of a faster register file whereas a BRAM (block read access memory) is employed in [25].