## 3 Broadband PA Implementation
### Interstage and Input Matching Network Design  
After replacing the OMN and the gate-side parallel RC stabilization network with their respective EM models, a 46 \(\times\) 8 \(\upmu\)m cell was added to perform source-pull simulations for the maximum PAE. The distribution of the resulting optimal source impedance can be characterized as a series RLC circuit, which serves as one end of the interstage matching network (ISMN), while the other end corresponds to the large-signal output equivalent circuit of a 46 \(\times\) 4 \(\upmu\)m cell, which is represented by the parallel \(R_{\text{opt}}\)C\({}_{\text{out}}\) network. Although the STN can be extended to higher-order configurations to introduce more resonance frequencies for broadband matching, its inherent topological characteristics render it unsuitable for an asymmetric ISMN. To determine the topology and component values of  
Figure 5: Reflection coefficients of the initial and adjusted STN.  
Figure 6: The transformation features of the optimized OMN from 22 to 32 GHz.  
the broadband ISMN, a parametric matching technique based on generalized parallel and series LC units is adopted, wherein the reactance of each series or parallel inductor \(L\) or capacitor \(C\) is correlated with the phase angle of its reflection coefficient, thereby mapping all possible values of \(L\) and \(C\) onto a finite and continuous open interval of radians (\(-\pi\), \(\pi\)) [10]. Such a mapping facilitates the use of CAD tools to swiftly search for the optimal parameter combinations and overcome convergence difficulties, with the optimization objectives set analogously to those in the OMN case. As for the input matching network (IMN), its primary target is to achieve conjugate matching between the transistor's input impedance and the 50 \(\Omega\) source to minimize the input reflection. Equally, it should also be capable of assisting in optimizing the gain flatness of the cascaded PA. Since the real part of the small-signal input impedance, as seen from the input side of the stabilized driver-stage transistor, shows little variation, while the imaginary part can be modeled as a series LC circuit, the design of the IMN is accomplished using an analytical approach based on a Chebyshev prototype network and the closed-form solutions supplied in [23].  
A schematic of the final PA and its corresponding layout, which passed the design rule check, are shown in Figures 7 and 8, respectively. To minimize the chip area, narrow microstrip lines with widths of 15 \(\upmu\)m for the OMN and 10 \(\upmu\)m for the other sections were employed. Additionally, the same type of bias supply is provided to both stages through a common square pad, with inductors incorporated to suppress potential signal crosstalk. On-chip bypass capacitors were placed near the power supply pads to mitigate unwanted signal interference and improve the circuit's stability. To reduce mutual coupling, the spacing between parallel microstrip lines was maintained at a minimum of three times the line width. Furthermore, all bends in the matching microstrip lines were implemented with 45-degree angles to decrease signal reflections. Specifically, double-layer metal was applied to the OMN and the drain bias lines of both stages to enhance the current-carrying capability and reduce the power dissipation and thermal issues caused by ohmic losses. The overall circuit dimensions are 1.4 \(\times\) 0.88 mm\({}^{2}\).  
Figure 7: A schematic diagram of the two-stage PA.