## 4 Metrics Used  
As is mentioned above, the main requirement of real-time systems is their predictability, i.e., all hard tasks [5] must meet their deadlines. This is the first and the strongest criteria of the design process. To make quantitative analysis possible, the appropriate model of a processed task is necessary. In [2] the following task model is proposed:  
\[T_{i}=\{C_{i},\ M_{i},\ D_{i}\} \tag{1}\]  
where:  
\(C_{i}\)--the number of instructions of the program to execute the \(i\)-th task (except \(M_{i}\));  
\(M_{i}\)--the number of memory access instructions of the \(i\)-th task; and  
\(D_{i}\)--the deadline of the \(i\)-th task. For a given system configuration another parameter, \(M\_{dur}\)[2], is defined. It reflects the worst-case delay time for the memory operations. \(M\_{dur}\) stands for the number of clock cycles necessary for memory operations and it is important in case of non-independent tasks, i.e., those threads that exchange data with one and other. From the task model (1) one can express the task frequency, \(TF\), factor that describes the processing rate for the \(i\)-th task:  
\[TF_{i}=\frac{C_{i}+M_{i}\cdot M\_{dur}}{D_{i}} \tag{2}\]  
Few algorithms presented in [2] show how to map tasks to available processing cores based on \(TF\) factors and meeting assumed design constraints (throughput, power, size, etc.). Of course, in the case of the simple architecture (Section 3.1), the task frequency multiplied by the number of the clock cycles corresponding to the instruction cycle (here, five) is equivalent to the minimum working frequency of the core processing the task. Meeting this requirement ensures the time predictability of the simple architecture. Figure 7: Multi-thread core architecture with pipeline processing and thread interleaving, wherein memory-gating mechanisms are implemented. In the case of MTP (multitasking processing cores) architectures, other issues need to be considered and worst cases need to be analyzed. For the multitask architectures analyzed in this paper, the following requirement for the deadline of the \(i\)-th task is used:  
\[D_{i}\leq\ \frac{C_{i}\cdot Min_{indistance}}{F_{sys}} \tag{3}\]  
where:  
\(D_{i}\)--the deadline of the the \(i\)-th task;  
\(F_{sys}\)--the operating frequency of the system; and  
\(Min_{indistance}\)--the minimal interleaving distance between pipeline stages of the same task. \(Min_{indistance}\), used in Equation (3), corresponds to the minimum number of steps that must separate successive instructions of the same task. For the pipeline processing, \(Min_{indistance}\) also equals the minimum number of clock cycles separating successive instructions of the program. This requirement is a condition for avoiding hazards in pipelined processing [11]. As to the operating frequency of the system \(F_{sys}\), its value depends on a few factors [2]: a core loading, i.e., how many tasks are mapped to it, the total sum of tasks' frequencies, and how many cores the overall system architecture consists of. Since the work presented here deals with energy optimization, it is also necessary to analyze the issues that affect the dissipated dynamic power. A commonly used equation [5] describing the relationship between the dynamic power consumed by the embedded systems and its parameters is as follows:  
\[P_{dynamic}=\alpha\cdot C_{L}\cdot V_{DD}^{2}\cdot F_{sys} \tag{4}\]  
where:  
\(\alpha\)--expresses the switching activity of the system (it can be controlled);  
\(C_{L}\)--a constant that denotes the switching capacitance; and  
\(V_{DD}\)--the value of the voltage supply. Formula (4) shows how the dynamic power consumed by the system can be controlled. In the case of programmable devices (FPGA) where voltage supply and capacitance usually cannot be changed, two factors can be modified: switching activity (\(\alpha\)) and the frequency of the system (\(F_{sys}\)).