## 6 Experimental Results and Discussions  
The design is implemented on a Xilinx Virtex-II pro FPGA [23] and is tested with a receiver test setup. The test setup includes Vector Signal Generators (VSG), Oscilloscope, FPGA board, spectrum analyzer and a PC with software as shown in Figure 15(a). Figure 15(b) shows the FPGA board with RF daughterboard. RF daughterboard is made using discrete components and works at center frequency of \(2.4\,\mathrm{GHz}\). Inputs are modulated RF and local oscillator signals. The RF input from signal generator is downconverted to IF and digitized before presenting it to the FPGA board. The FPGA does the further processing in the digital to extract the packet. Packet error and packet loss are measured inside the FPGA. This is done by transmitting a packet with 20 known symbols by triggering the VSG repeatedly. Demodulated symbols are compared with the stored sequence of symbols in the FPGA. The packet error counter (\(packet\_err\_count\)) is incremented with every packet error. For packet loss measurement, number of packet transmitted is counted and compared with the number of \(sync\_succ\) occurred, _i.e._, number of time synchronization is achieved. \begin{table}
\begin{tabular}{|c|c|c|} \hline \multicolumn{3}{|c|}{Blocks and Gate count in \%} \\ \hline IDSE & 16 & Tracking & 36 \\ \hline Match Filters & 19.8 & Acquisition & 5.7 \\ \hline PhEE & 4.95 & Demod & 4.83 \\ \hline ROM & 4.1 & FEE & 4 \\ \hline NCO & 2.4 & Detector & 1.2 \\ \hline Theta gen. & 0.86 & \\ \hline \end{tabular}
\begin{tabular}{|c|c|} \hline Designed for & IEEE 802.15.4-2006 \\ \hline Technology & UMC 130 nm CMOS \\ \hline Gate count & \(\sim\)606 K gates \\ \hline Area & \(\sim\)2.42 mm\({}^{2}\) \\ \hline Power & variable, 0.49–3.3 mW \\ \hline Frequency & variable, 1–30 Msps \\ \hline \end{tabular}
\end{table} 
Table 2: Estimated gate count and design summary from ASIC simulation. Figure 14: Power as a function of \(f_{s}\) and \(Q_{dig}\), Equation (1). Variation in power consumption of the design in seen to be \(85\)%. Figure 16 shows snapshot of the baseband signal after the low-IF to baseband downconverter from the experimental setup. The snapshot is taken from within FPGA using Chipscope [23]. Characteristic of the signal changes midway. First half of the snapshot shows the preamble duration. The signal has high dynamic range during this period, when synchronization and IDSE units are active. Second half of the signal has lesser dynamic range. It is the duration of the packet that contains the data. The data duration shown here is captured when the input to the receiver is 1-bit and sampled at 2 Msps. Figure 16: Baseband signal in the receiver during a packet reception from experimental setup. Figure 15: Experimental setup and RF board with FPGA. Figure 17 shows the amplitude _vs._ time of the signal during various instances of packet reception. Time is in micro seconds and amplitude is the digitally quantized signal. Figure 17(a) shows the baseband signal with frequency and phase error, corresponding to section labeled \"**A**\" in Figure 16. Figure 17(b) shows the baseband signal after frequency and phase error correction, corresponding to section \"**B**\" labeled in Figure 16. The signal shown here is very close to the ideal baseband signal inside the receiver, since input noise is low. The signal has very high resolution, as is evident from the smoothness of the sinusoid pulses. Smoother high resolution signals cause more switching and hence consume more power. Baseband signal during sampling frequency and bitwidth transition is shown in Figure 17(c). As can be seen, the smooth sinusoids transform to less dynamic low resolution signal. Content of registers in the datapath is discarded during this period. Figure 17(d) shows the baseband signal during data period of the packet. As evident from the figure, signal has low amplitude resolution and is not as smooth as signals captured in Figure 17(b).