## 3 Design and Development
### The FPGA Implementation Detail  
The FPGA implementation specifically uses the Xilinx XCZU15 EG evaluation board, with hardware synthesis developed and implemented on the Vivado HLS platform. Since the proposed IIR filter parameters are difficult to complete within the input range allowed by fixed-point arithmetic using FPGA's on-chip DSP slices and since implementing floating-point arithmetic on the FPGA incurs significant hardware overhead [29; 30], this part can be processed in real-time on the ESP32 MCU; therefore, the FPGA implementation does not include this section. The specific framework diagram of the FPGA implementation is shown in Figure 5.  
The module for extracting IMFs on the FPGA refers to references [31], as shown in Figure 6.  
Figure 4: Full evaluation setup. Figure 5: FPGA implementation block diagram. The traditional method of envelope extraction through CSI interpolation at extreme points is difficult and resource-intensive with high computational latency. Using linear interpolation plus a moving average filter can achieve similar accuracy while effectively solving this problem. Simulations of this method revealed a significant issue with low-frequency mode mixing, but in the application of detecting stones mixed into coffee beans, even without using the DC component, the final result remains unaffected, and ideally, IMFs should not contain DC components. From the IMFs and frequency spectra shown in Figure 2, it can be observed that the high-frequency components of each iteratively decomposed IMF gradually decrease, while IMF7 primarily contains information concentrated within a 60 Hz bandwidth. Therefore, directly downsampling the residual before inputting it into the next level [32], to half the original frequency rate; downsampling was attempted using both mean filtering and IIR filtering for signal preprocessing, but simulations did not show a better correlation in the frequency spectrum. Thus, it was decided not to perform signal preprocessing and to implement downsampling directly through extraction. Because the sampling rate of IMF7 output must ensure approximately a 60 Hz bandwidth, the signal's sampling rate should not be lower than 8 kHz to ensure the required IMFs can be correctly decomposed. Simulations of the mean squared error under different sampling rates, using 48 kHz as a reference, showed that for all sampling rates not lower than 8 kHz, the mean squared error of different results was less than 0.025, indicating that the impact of the sampling rate on false positives under normal conditions is negligible. Therefore, the sampling rate was selected as 8 kHz. In simulations of actual measurement samples, when the number of samples within the 60 Hz band after FFT reaches 20, a significant result can be obtained when a fault mode occurs. Therefore, after performing a 64-point FFT using Vivado FFT IP and discarding the DC and highest frequency components, the remaining 30 sample points are resampled to 20 sample points using linear interpolation for further processing. For the final downsampling to a sampling rate of 125 Hz, this introduces approximately a 0.5 s dead time after data begin to be input. Alternative steps, such as using a 32-point FFT interpolated to the same number of points or directly using 15 points after removing the DC component, were attempted to  
Figure 6: IMFs extraction design [31]. achieve shorter dead times, but these introduced more significant uncertainties in the result, thereby reducing the accuracy of small gravel detection. Therefore, a longer dead time with a 64-point FFT was chosen. After completing the FFT, energy normalization calculation and modulus operations are critical steps [33; 34]. To efficiently perform these calculations, the CORDIC (Coordinate Rotation Digital Computer) algorithm was employed. CORDIC is an iterative rotation-based algorithm that can perform square root and magnitude calculations without the need for multipliers, using a series of additions and shift operations [35; 36].