## 3 Digital Filters in the FFA
The block diagram of the proposed interfacing device includes the register where the initial number \(A\) is written, the \(2^{s/2}\) comparison schemes and the \(2^{s/2}\) memory devices. The proposed method of residue finding provides it for two modular cycles of the converter. The time of residue formation does not change with an increase in the bit width of the converted source numbers. The disadvantage of the proposed algorithm is that the hardware costs required for its implementation are high. In addition, the residue values repeat in the memory devices. This indicates an incomplete use of modular code ring properties. While researching the proposed algorithm of formation of a modulo residue it was found that the first values of residues in the subranges of expression (15) for the modules getting the values \(p_{i}<2^{s/2}\) change by a value  
\[C_{\rm s}=2^{s/2}-p_{i}, \tag{16}\]  
while for the modules getting the values \(p_{i}>2^{s/2}\), these values are constant and determined as  
\[C_{\rm s}=2^{s/2}. \tag{17}\]  
Using these properties, the algorithm of residue determination can be described as follows:  
\[\alpha_{i}=|R+C_{\rm s}|, \tag{18}\]  
where \(R\)--the number determined by the \(s/2\) lower bits of the number \(A\); \(C_{\rm s}\)--the value calculated using Equation (16) and written to the memory device (MD) by the address that gets the value in accordance with the upper \(s/2\) bits of number \(A\). The block diagram of the proposed converting device is provided in Figure 2.  
The developed algorithm provides the residue formation for three modular cycles of the interfacing device. Thus, we can conclude that the developed conversion method provides significantly better performance than the existing conversion methods considered in [10]. It should be noted that the algorithm provides operation in the conveyor mode, i.e., matching the speed of arrival of input data into the computing device of a DF and calculation of its output sample on the basis of FFA. The abovementioned method of data representation in the FFA codes meets the requirements of the real-time signal processing devices in terms of performance indicators. Application of the conversion device for data in the FFA codes complicates the overall filter structure, requires additional costs to synchronize the operation of its elements in the mode of calculations conveyor. The question arises about the possibility of excluding the conversion device from the structure of the computation channel of DF to improve the accuracy of the calculation of the output sample. Figure 2: The block diagram of the proposed converting device. In [15; 16] the models of calculation accuracy for output samples in a positional digital filter and in the filter operating on the basis of FFA are provided. The model of calculation accuracy in the positional DF considering that while calculating the output sample the intermediate results will be rounded off, can be represented as follows:  
\[e_{er\ com}(nT)=Q_{ADC}(nT)+\ e_{q\ coef}(nT)+\ e_{q\ is}(nT)+e_{ro\ out}(nT)+ \ e_{add}(nT), \tag{19}\]  
where \(e_{er\ com(nT)}\)--the common calculation error for the output sample; \(Q_{ADC}(nT)\)--the error of analog-to-digital converter (ADC); \(e_{q\ coef}(nT)\)--the error of coefficients quantization when they are represented in a computational digital filtering algorithm; \(e_{q\ is}(nT)\)--the error of input sample quantization when they are represented in a computational digital filtering algorithm; \(e_{ro\ out}(nT)\)--the error introduced by the intermediate results rounding off; \(e_{add}(nT)\)--the error resulting from the fact that the input of each subsequent stage will receive an intermediate sample, which already has an error that accumulates when the intermediate sample \"passes\" through the stages of the filter.