## 5 Realization of Multiplier-Free Modified Godard on Real-Time Platform  
To estimate the complexity of a hardware implementation, the multiplier-free modified Godard algorithm derived above was implemented in very high speed integrated circuit (VHSIC) hardware description language (VHDL) and tested with Xilinx Vivado and Mentor Graphics ModelSim. For  
Figure 10: BER over roll-off factor for a signal with roll-off factor 0.1 and modulation formats of QPSK (blue), 16 QAM (red), and 64 QAM (yellow) are shown. The results are plotted for an SNR of 100 dB and 9.8 dB, 16.5 dB, 22.5 dB, respectively; QPSK: quadrature phase-shift keying.  
Figure 9: BER over jitter for a signal with 16 QAM with different roll-off factors. The results for an SNR of 100 dB and 16.5 dB are shown.  
comparison to a pure time domain algorithm, we implemented the Gardner algorithm. The Gardner algorithm is seen as a candidate for next-generation receivers [19].  
The hardware design is realized for an oversampling of 4/3, a clock frequency of 250 MHz, 96 symbols per clock cycle (=24 Gbd), and 6 bit resolution. Table 1 compares the modified Godard hardware requirements of the implementation in Xilinx Vivado with a Gardner synchronization in the time domain.  
When compared to the frequency domain, the time domain adaptive FIR filter for timing correction requires 22 times more lookup tables, 6 times more flip-flops, and an additional 2016 DSP slices for multiplications. Additionally, to the estimate and correction, as listed in Table 1, roughly 36% of the lookup tables (LUT) and 18% of the flip-flops (FF) would be required for the transformation to the frequency domain and the transformation to polar coordinates. However, the DFT transformation is needed for CD compensation and other equalization stages anyway, and the polar transformation greatly simplifies the CD compensation as well.  
To test the performance of the timing synchronization loop, a signal with a certain timing error was generated in Matlab and sent to the test bench in ModelSim. To test the dynamic and the static response of the loop, the test signal was impaired for the first 8 us with a sampling frequency offset of 50 kHz, and for the following 8 us the sampling frequency offset was set to zero (red curve in Figure 11). From the line plotted in green, one can see how the modified Godard algorithm corrects the timing error. After 2 us settling time, the 50 kHz sampling frequency offset is tracked successfully. The offset between introduced and corrected error results from the latency between error estimation and correction. For all tested modulation formats (QPSK, 8 QAM, and 16 QAM, depicted as insets in Figure 11), the same synchronization loop behavior was observed. Therefore, the performance is independent of the modulation format.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Algorithm**} & \multicolumn{2}{c}{**Gardner**} & \multicolumn{2}{c}{**Modified Godard**} \\ \cline{2-5}  & **Estimation** & **Correction** & **Estimation** & **Correction** \\ \hline
**Lookup tables** & 1435 (<1\%) & 35,652 (8\%) & 694 (<1\%) & 1612 (<1\%) \\
**Flip-flops** & 1932 (<1\%) & 78,280 (9\%) & 871 (<1\%) & 11,641 (1\%) \\
**DSP** & 97 (3\%) & 2016 (56\%) & 0 (0\%) & 0 (0\%) \\ \hline \hline \end{tabular}
\end{table}
Table 1: Hardware requirements for Gardner and modified Godard algorithms (Percentages are given with respect to the Xilinx Virtex 7 xc7 vx690t board).  
Figure 11: ModelSim analysis of the timing correction (SNR = 10 dB, 16 QAM, \(n=4/3\), \(\beta=1/3\), sampling frequency offset 50 kHz). Insets show constellation diagrams with timing error and QPSK, 8 QAM, and 16 QAM after timing synchronization for a BER of \(10^{-3}\).