# FPGA-Based Pulse Compressor for Ultra Low Latency Visible Light Communications
## 5 Experimental Setup  
### The VLC System  
The transmitter and receiver described so far have been implemented in a VLC system based on the commercial MAX 10 FPGA development kit produced by Terasic Inc. (Hsinchu County, Taiwan) connected to a custom board designed in our laboratory. The commercial MAX10 kit integrates the 10M50 DAF484 FPGA produced by Intel/Altera, and, among other devices, it includes 128 MB of SDRAM, an Ethernet controller, and a HMSC expansion port. The FPGA board, through the HMSC port, is connected to the custom board, which integrates the VLC front-end. Once connected, these two boards represent the VLC system sketched in Figure 9.  
\begin{table}
\begin{tabular}{l c c c c c c c c} \hline  & \(N_{S}\) = 56 Sample & & \(N_{S}\) = 112 Sample & & \(N_{S}\) = 224 Sample & \\ \cline{2-9}  & **LCs** & **M9 ks** & \begin{tabular}{c} **DSPs** \\ **(18 \(\times\) 18)** \\ \end{tabular} & **LCs** & **M9 ks** & \
\begin{tabular}{c} **DSPs** \\ **(18 \(\times\) 18)** \\ \end{tabular} & **LCs** & **M9 ks** &
\begin{tabular}{c} **DSPs** \\ **(18 \(\times\) 18)** \\ \end{tabular} \\ \hline \multicolumn{9}{c}{**Transmitter**} \\ \hline Packet formation & 93 & 0 & 0 & 93 & 0 & 0 & 93 & 0 & 0 \\ \hline Serializer & 12 & 0 & 0 & 12 & 0 & 0 & 12 & 0 & 0 \\ \hline Modulator Chirp table & 1137 & 0 & 0 & 4127 & 0 & 0 & 8120 & 0 & 0 \\ \hline
**Sub-total** & 1242 & 0 & 0 & 180 & 0 & 0 & 0 & 0 \\ \hline \multicolumn{9}{c}{**Receiver**} \\ \hline Compressor FIR & 438 & 3 & 6 & 710 & 5 & 12 & 1226 & 9 & 24 \\ \hline Threshold & 5 & 0 & 0 & 5 & 0 & 0 & 5 & 0 & 0 \\ \hline Packet & 50 & 1 & 0 & 50 & 1 & 0 & 50 & 1 & 0 \\ \hline Sequencer & 20 & 0 & 0 & 20 & 0 & 0 & 20 & 0 & 0 \\ \hline
**Sub-total** & **513** & **4** & **6** & **785** & **6** & **12** & **1301** & **10** & **24** \\ \hline
**TOT** & **1755** & **4** & **6** & **5017** & **6** & **12** & **9526** & **10** & **24** \\ \hline
**\% (10M50)** & **3.5\%** & **2.2\%** & **4.2\%** & **10.1\%** & **3.3\%** & **8.4\%** & **19.1\%** & **5.5\%** & **16.8\%** \\ \hline \end{tabular}
\end{table}
Table 2: Resources of MAX10 FPGA employed by the transmitter and receiver.  
In transmission, the FPGA synthesizes the signal and drives a Digital-to-Analog converter (DAC) that features a 14-bit resolution and works up to 125 Msps. The converted signal feeds a transconductance amplifier capable of generating up to \(\pm\)1 A, similar to those employed in ultrasound [28]. This current is added to a constant current source of up to 1 A, and the resulting current powers an external LED.  
In reception, the custom board receives the signal from an external photodetector. A Low Noise Amplifier (LNA) processes the signal before it feeds an Analog-to-Digital converter (ADC) capable of 12-bit at 40 Msps that here is employed at 12.5 Msps. The input noise is minimized also by synchronizing the switching power supplies of the VLC system to the bit rate [29].  
The VLC system connects through the Ethernet link to a host PC where a MATLAB interface runs. This interface is used to set the working parameters and monitor the system during the experiments.