# FPGA Implementation of a Deep Learning Acceleration Core Architecture for Image Target Detection
## 3 Results and Discussion
### Performance Analysis of Deep Learning Acceleration Core Inference
In Table 7, although different literature uses different hardware platforms and implements other algorithmic models, the parameter Energy Efficiency allows normalizing the performance of different algorithms within the same evaluation system. Our proposed architecture can provide an arithmetic performance of 28.98 GOPS per unit power, which is 20.34% higher than the 2 nd place. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline \multirow{2}{*}{**Layer**} & **Data Loading** & **Data Storage** & \
\begin{tabular}{c} **Parameter** \\ **Loading** \\ **Time** \\ \end{tabular} &
\begin{tabular}{c} **Calculation** \\ **Time** \\ \end{tabular} & **Actual Time** \\ \hline FC17 & 0.02 ms & 0.00 ms & 5.35 ms & 1.33 ms & 6.68 ms \\ FC18 & 0.00 ms & 0.00 ms & 0.44 ms & 0.11 ms & 0.55 ms \\ FC19 & 0.00 ms & 0.00 ms & 2.50 ms & 0.63 ms & 3.13 ms \\ Total & 0.02 ms & 0.00 & 8.29 ms & 2.07 ms & 10.36 ms \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Calculation time for fully connected layers. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline \multirow{2}{*}{**Layer**} & \begin{tabular}{c} **Data** \\ **Loading** \\ **Time** \\ \end{tabular} & \begin{tabular}{c} **Data Storage** \\ **Time** \\ \end{tabular} & \
\begin{tabular}{c} **Parameter** \\ **Loading** \\ **Time** \\ \end{tabular} &
\begin{tabular}{c} **Calculation** \\ **Time** \\ \end{tabular} & **Actual Time** \\ \hline CONV1 & 0.67 ms & 1.33 ms & 0.00 ms & 3.01 ms & 3.01 ms \\ CONV3 & 0.33 ms & 0.67 ms & 0.00 ms & 3.01 ms & 3.01 ms \\ CONV5 & 0.16 ms & 0.33 ms & 0.00 ms & 3.01 ms & 3.01 ms \\ CONV7 & 0.08 ms & 0.16 ms & 0.03 ms & 3.01 ms & 3.14 ms \\ CONV9 & 0.04 ms & 0.08 ms & 0.12 ms & 3.01 ms & 3.13 ms \\ CONV11 & 0.02 ms & 0.04 ms & 0.49 ms & 3.01 ms & 3.50 ms \\ CONV13 & 0.01 ms & 0.02 ms & 1.96 ms & 3.01 ms & 4.97 ms \\ CONV14 & 0.02 ms & 0.02 ms & 3.93 ms & 6.02 ms & 9.95 ms \\ CONV15 & 0.02 ms & 0.02 ms & 3.93 ms & 6.02 ms & 9.95 ms \\ Total & 1.35 ms & 2.67 ms & 10.46 ms & 33.11 ms & 43.57 ms \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Calculation time for convolutional layers. Here we have to point out that since our proposed method utilizes a lot of hardware design tricks to optimize specifically for CNN-based models and FPGA structures, it has a good migration capability for algorithms of CNN-based models such as VGG, Multi-scale Residual Aggregation Network (MSRANet), GoogleNet, Inception, Faster R-CNN, etc. For other models, such as Recurrent Neural Networks (RNN) or Generative Adversarial Nets (GAN) models, there is only some optimization capability at the FPGA structure level. Further, since the performance gains in arithmetic power and speed of our proposed deep learning acceleration core rely on highly streamlined and parallelized processing of the hardware, this requires predictable behavior of the inference network because if a random operation interrupts this predictable behavior, such as a parameter update or a bus transfer failure, then all streamlined work has to be restarted, which often results in massive latency. For real-time tasks, this latency is often intolerable. The test result is shown in Figure 18.