# Silicon Integrated Nanophotonic Devices for On-Chip Multi-Mode Interconnets
## 2 Silicon Multi-Dimensional (De)Multiplexers
### Silicon Mode (De)Multiplexers
For this optimal design, the coupling length is as short as 50 \(\upmu\)m, while ultra-low crosstalk (XT \(<\) \(-\)30 dB), ultra-broad bandwidth (BW \(>\) 150 nm) and ultra-large fabrication tolerance (\(\pm\)50 nm) can still be ensured. From the above discussions, the structures based on MMIs, asymmetric Y-junctions and ADCs all show some degrees of advantages in achieving mode (de)multiplexing. However, all these mode (de)multiplexers are not scalable, which means that these designs can only support a few modes (typically two modes). The scalable mode (de)multiplexers are desired in the MDM systems, which can be built by successively connecting several Y-junctions [75; 76] or ADCs [77; 78; 79; 80; 81; 82]. Figure 5a shows the configuration of a typical four-channel mode (de)multiplexer using the cascaded asymmetric Y-junctions [75]. Three higher-order TE modes (i.e., TE\({}_{1}\), TE\({}_{2}\), TE\({}_{3}\)) can be independently excited by several different Y-junctions, while the fundamental TE mode, i.e., TE\({}_{0}\), is directly injected into the multi-mode bus waveguide. The arm widths are carefully chosen so that the mode-selective condition is satisfied for only one higher-order mode in each Y-junction. In [76], [PERSON] et al. reported a three-channel MDM with cascaded asymmetric Y-junctions on silicon. The experimental results exhibit crosstalk of XT \(\approx\) \(-\)10 dB for the first three TE modes (i.e., TE\({}_{0-2}\)). Nevertheless, the cascaded asymmetric Y-junction still seriously suffers from significant insertion losses (IL \(>\) 5 dB) and the small feature size at the junction's tip. In contrast, the cascaded ADCs are broadly considered as a more promising candidate for mode (de)multiplexing based on the best overall performances. In 2013, the first cascaded ADC-based silicon mode (de)multiplexer was reported by [PERSON] et al. [77], as illustrated in Figure 5b. In ADC #i, the phase matching is satisfied only between TM\({}_{0}\) and TM\({}_{i}\), so the input TM\({}_{0}\) mode can converted to TM\({}_{i}\) mode and multiplexed into the multi-mode bus waveguide, while the other higher-order modes (i.e., TM\({}_{j}\), j \(<\) i) will go through the coupling section with negligible losses. Additionally, TM\({}_{0}\) mode is directly launched from the multi-mode bus waveguide without evanescent coupling or mode conversion. In this way, a four-channel mode (de)multiplexer can be built by cascading three ADCs with adiabatic tapers as connectors in between. Compared with the cascaded Y-junctions, the proposed cascaded ADCs can provide a larger feature size (\(>\)300 nm), lower insertion losses (IL \(<\) 1 dB) and lower crosstalk (XT \(<\) \(-\)23 dB). However, the experimental results also show a relatively narrow working bandwidth (BW \(\approx\) 20 nm), which can be further improved (BW \(>\) 100 nm) by exploiting adiabatic coupling [39; 78; 79] or ultra-thin waveguides [80]. Moreover, recent research also shows that the crosstalk of cascaded ADCs can also be further mitigated by exploiting coherence detection [83]. In Table 1, we summarize the reported silicon mode (de)multiplexers. It can be seen that the various silicon mode (de)multiplexers have been realized with low losses, low crosstalk and a broad bandwidth. In theory, the mode capacity can be expanded at will by simply cascading more ADCs; however, an extremely long coupling length would be needed to achieve the conversion to a very high-order mode, which could lead to a large and complex device layout as well as increased crosstalk. The issue could be addressed by employing SWG waveguides with an engineered index [81; 82]. However, the fabrication of SWG is immature given its subwavelength feature size. To further expand the capacity, a more effective solution is the wavelength/polarization/mode hybrid (de)multiplexing that combines multiple dimensions of light. A discussion about silicon hybrid (de)multiplexers will be given in Section 2.2.