# Improving Hardware in LUT-Based Mealy FSMs
## 6 Experimental Results
Thus, the number of logic levels in the FD-based FSMs has increased, but still remains less than this number in the equivalent SD-based FSMs. The analysis of Table 15 shows that only \(U_{2}\)-based FSM circuits are a bit faster than the equivalent circuits based on our approach. This win is equal to 0.09%. However, our approach allows producing the faster circuits as compared with auto (15.38%), one-hot (15.6%) and JEDI (4.78%). Note that to compare different FPGA-based circuits of equivalent devices, such estimates as the number of flip-flops in the circuit, its power consumption, the product of the number of LUTs and the cycle time (the area-time characteristic), the product of the power consumption and the cycle time (the power-time characteristic) can be used. We also compared these characteristics of FSM circuits for the models used in the research. The numbers of flip-flops used in FSM circuits are shown in Tables 16 and 17. Table 18 contains information about the power consumption. The area-time characteristics are shown in Table 19. The power-time characteristics are shown in Table 20.  
As follows from Table 16, our method significantly loses in the number of flip-flops to all other methods (except for the one-hot approach). This is determined by the fact that the number of flip-flops is the same as the number of bits in the state codes \(K(a_{m})\). For the proposed FSM \(U_{3}\), the number of flip-flops is equal to twice the number of bits in the codes of COs. Due to it, our method loses an average of 39.37% to FSMs based on methods auto, JEDI and \(U_{2}\). However, this is not entirely true if we consider an FSM as a block of some digital system. It is known that the outputs of the Mealy FSM are not stable. They can change when the input signals change. The FSM inputs are the outputs of the remaining system blocks. This phenomenon can lead to malfunctions in the functioning of the digital system. To eliminate possible failures, an intermediate register is introduced into the system. The FSM outputs are recorded in this register after the end of transient processes in the remaining blocks of the system. So, to find the required number of flip-flops, it is necessary to add a value of N (the number of FSM outputs) to the value obtained from the Vivado reports. For example, there are 7 flip-flops in FSM _s1494_ for the model \(U_{2}\) and 16 flip-flops for the model \(U_{3}\) (Table 16). As follows from Table 7, there is N = 19 for FSM _s1494_. So, as a block interacting with other blocks of a digital system, this \(U_{2}\)-based FSM _s1494_ requires 26 flip-flops. Using the same approach, we can create Table 17.  
The proposed method does not require such an additional output register. This is due to the fact that the codes of COs are written to the registers. Therefore, for the model \(U_{3}\), the FSM outputs are stable after being written to the registers. So, when choosing an FSM model, the designer must add the number of outputs to all numbers from the Table 16 except for the numbers obtained for \(U_{3}\)-based FSMs. This fact explains the coincidence of information in columns \"Our approach\" of Tables 16 and 17. As follows from Table 17, our method allows the use of fewer flip-flops compared to other methods studied. The gain is 41.06% compared to methods auto, JEDI and \(U_{2}\) and 166.18% compared to the FSMs based on the one-hot approach. To estimate the power consumption, we also used Vivado. Vivado uses the value of maximum operating frequency achieved for each benchmark and calculates the value of power consumption basing on this frequency. To conduct the research, the core voltage (VCCINT) was set to 1.0V. The data in the Table 18 are taken from the Vivado Power Reports. As follows from Table 18, the \(U_{3}\)-based FSMs consume more power than equivalent \(U_{2}\)-based FSMs (the loss is on average 9.62%).