# Broadband Millimeter-Wave Front-End Module Design Considerations in FD-SOI CMOS vs. GaN HEMTs
## 2 Materials and Methods  
An example of a single-channel phased array transceiver that has one FEM driving a single antenna element is shown in Figure 1. Our focus lies on the PAs and antenna arrays within these systems since these components will dictate the number of channels/elements necessary for the phased array system to reach a minimum level of Tx EIRP for a given application.  
The various simulations we can perform to design our mm-Wave RFICs are shown in Figure 2. We can simulate some simple antenna array designs in Cadence AWR (v.22.1) to corroborate the values we calculate for the antenna gain and HPBW, which are mainly dependent on the array size. Since we are working at mm-Wave frequencies, EM and PEX simulations become increasingly important as parasitic inductances and capacitances can significantly alter the impedances, and thus, the performance of a circuit/system at the desired design frequency. To properly extract the layout parasitics with post-layout simulations in the Cadence Virtuoso design environment on our Si CMOS PAs, we use xACT to perform PEX near the FETs, and EMX for the EM characterization of passives further from the FETs. For the antennas and our GaN PAs, we use the AXIEM EM tool for PEX EM characterization in the AWR design environment. We run small- and large-signal continuous wave (CW) simulations on our designs and check the transient I-V waveforms at various locations to ensure the designs are behaving as we expect. The tests we employ to determine the stability of our PAs include the Rollet Stability Factor (K-factor) and B-factor at their input and output, and pole-zero analyses (e.g., Nyquist Stability Criterion, Stability Circles) at all the interstage locations using Gamma or S- probes [37; 38; 39; 40]. This is carried out because the K-factor and B-factor can determine unconditional small-signal stability at the input and output of a circuit [41] but is insufficient for detecting instabilities at interstage locations within a multi-stage design [42]. In the Cadence AWR Microwave Office design environment, we are able to simulate the K- and B-factors and perform interstage pole-zero analyses using S-probes through checks on the Nyquist Stability Criterion, which has been shown to be effective at mm-Wave frequencies [43]. We also like to test the stability of the devices as they are biased on, or as their gate voltage (\(V_{G}\)) is increased from the threshold voltage (\(V_{T}\)) up to the targeted quiescent biasing point (Q point) for the devices while their drain voltage (\(V_{D}\)) is left constant. We also have access to the COMSOL Multiphysics(r.6.2) for detailed chip temperature checking, but we have not needed to use this software for our PA designs yet.  
Figure 1: System diagram depicting a phased array transceiver system, with monolithic microwave-integrated circuit (MMIC) FEMs highlighted on the left.  
Measurements presented on the PAs are taken in our lab at TTU using a state-of-the-art probe station with continuous wave (CW) test equipment (e.g., cables, signal generator, spectrum analyzer, vector network analyzer, etc.) that are capable of taking measurements on devices up to 50 GHz.