## 3 General Strategies for Energy Efficient BSN Hardware
### Flexibility versus _Efficiency_
To demonstrate the performance of different hardware platforms in the context of BSN applications, we simulated a typical heart rate (R-R) extraction algorithm that calculates the heart rate of a user based on the raw data of an ECG, which was run on the three different platforms designed in the same technology operating at the same operating voltage (0.4 V) while targeting the same data rate. The results are shown in Table 1.  
We make two observations from Table 1. First, not only is ASIC \(>\) FPGA \(>\) GPP with respect to energy efficiency, but ASIC \(>\) FPGA \(>\) GPP in terms of potentially speed and performance capacity. The second observation is that there is a drastic improvement in efficiency (\(>\)100\(\times\)) between GPPs and FPGA/ASICs. Therefore, it makes sense to assign on-node processing to FPGA and ASIC platforms, while using GPPs strictly for control or rarely occurring operations. Given the large space of BSN nodes and their applications, there is no obvious optimal platform for all nodes. Though ASICs are extremely efficient in terms of energy minimization and computational capability, they are highly inflexible as their functionality is set. Thus, they must be revisited and \begin{table}
\begin{tabular}{l l l l l l} \hline  & **Energy per** & **Energy per** & **Delay per** & **Estimate Max** & **GOPS/W** \\  & **Instruction** & **Processed Sample** & **Sample** & **Achievable Data Rate** & **GOPS/W** \\ \hline GPP & 2.62 pJ & 210 pJ & 8 \(\upmu\)s (80 clock & 125 kHz & 4.76 \\ (from [7]) & & & cycles) & & \\ FPGA & N/A & 2.22 pJ & 94.5 ns & 10 MHz & 450 \\ (from [26]) & & & (1 clock cycle) & & \\ ASIC & N/A & 0.23 pJ & 6.18 ns & 150 MHz & 4348 \\  & & & (1 clock cycle) & & \\ \hline \end{tabular}
\end{table} 
Table 1: Comparison of different hardware platforms. redesigned whenever the functionality changes. This is a major drawback, as it leads to increased design time and design cost. Furthermore, ASICs are limited to a certain application space. Therefore, flexibility is another requirement for BSNs that must be examined during the design of a node for a specific application or set of applications. On the other end of the spectrum, GPPs offer a highly flexible option for on-node processing. Along with popular peripherals, such as the aforementioned floating point unit or multiplier, GPPs are able to perform almost any job and run any processing algorithm for the BSN node. Thus, they are useful in building most nodes, serving as a central controller for the node. The flexibility advantage is most noticeable in generic nodes, where the specific algorithm or signal processing requirements are not pre-determined, but coded into instruction memory. However, this advantage comes at the cost of energy efficiency. GPPs are highly inefficient because of unused logic components and resources within the GPP for each instruction executed. Also, given the instruction per cycle limitations of GPPs, programs cannot fully take advantage of instruction parallelism, resulting in greater latency and energy consumption per package of data processed. State-of-the-art low power COTS GPPs can meet energy and speed requirements for many BSN applications. For example, TI's MSP430 supports a wide range of applications, running on clock frequencies up to 25 MHz while consuming 165 \(\upmu\)A/MHz [27]. Custom GPPs will be even more efficient but will incur the development costs of an ASIC. In summary, increasing the flexibility of processing to cover more scenarios will sacrifice energy efficiency. This means that platforms encircling larger regions of Figure 2 will necessarily be less efficient than more targeted solutions, resulting in shorter lifetimes and/or larger form factors.