## 2 Fabrication Process and Filter Design  
### Fabrication Process  
The fabrication of our RF MEMS filter began with careful substrate selection to ensure optimal electrical performance. We utilized four-inch silicon wafers with exceptionally high resistivity values exceeding 60,000 \(\Omega\), a critical specification that minimizes RF signal attenuation through the substrate material. The high-resistivity silicon substrate has a relative permittivity (\(\varepsilon_{\mathrm{r}}\)) of 11.9 and a loss tangent (tan \(\delta\)) of approximately 0.004 at our operating frequencies, which are critical parameters for accurate RF simulation and performance. These high-resistivity wafers arrived with a standard thickness of 525 \(\upmu\)m, which we subsequently reduced to a precisely controlled 400 \(\upmu\)m thickness using Chemical Mechanical Polishing (CMP). This thickness reduction served two critical purposes. First, it allowed us to achieve a superior surface finish and planarity across the wafer, which is a fundamental requirement for the stringent surface-contact quality needed in the subsequent Au-Au thermocompression bonding step. Second, it optimized the efficiency of later processing steps, such as Deep Reactive Ion Etching (DRIE), by reducing etch times. The fabrication sequence, illustrated comprehensively in Figure 2, continued with the creation of via holes to establish vertical electrical connections between the top and bottom wafer surfaces. This critical step began with the application of a precisely formulated photoresist coating that defined the via hole patterns through photolithography. Following pattern development, we employed Deep Reactive Ion Etching (DRIE), a highly anisotropic etching process, to create cylindrical openings with 250 \(\upmu\)m diameters and nearly vertical sidewalls. This DRIE process was carefully optimized to achieve high aspect ratio features with minimal undercut, ensuring reliable electrical connections between wafer surfaces. After thorough photoresist removal using both plasma ashing and wet chemical processes, we proceeded to the metallization phase, which consisted of primary and secondary plating processes designed to create both the resonator bars and the necessary grounding patterns for the RF filter structure. A significant innovation in our approach was the use of Dry Film Resist (DFR) instead of conventional liquid photoresist for defining metallization patterns. DFR provided superior thickness uniformity, enhanced adhesion, and improved pattern fidelity, which is crucial for controlling the current density distribution during electroplating. To further ensure uniform layer deposition, particularly near corners and edges, the plating bath chemistry, temperature, and agitation were carefully controlled, and the pulsed current density was optimized to promote even metal ion distribution across the entire patterned area. The primary metallization process involved electroplating 7-8 \(\upmu\)m of copper (Cu) to form the core conductive elements of the filter structure. This was followed by a secondary electroplating step that deposited a precisely controlled 1-2 \(\upmu\)m layer of gold (Au) encapsulating the copper structures. This gold capping layer served multiple essential functions; it enabled subsequent gold wire bonding operations, enhanced metal surface adhesion for improved reliability, and provided oxidation resistance that preserved the electrical performance characteristics over the device lifetime. Following the completion of both plating processes, we meticulously removed the DFR using specialized solvents that preserved the integrity of the plated metal structures. Similarly, the seed layers were removed through a selective etching process that maintained the dimensional accuracy of the plated features while ensuring complete removal of conductive material from non-pattern areas. This careful processing resulted in precise resonator structures that matched our design specifications.