## 2 Principle of Operation
By repeating the process in the same manner, we can obtain the output from the AND gate in the fourth loop {0, 0, 0, 0, 1, 0, 0, 0, 0, 1}, where the logic \"1\" indicates the number and position of the complete targets {\(\pi\), 0, \(\pi\), \(\pi\)} and {0, \(\pi\), 0, 0} in the input BPSK data. In the proposed system, it can be noticed that these two reloaded signals are phase-locking during signal generation. Additionally, they transmit through the same NOLM, which ensures the same optical path length and the strong coherence between them during signal transmission. Thus, in the bit-recognition process, the accuracy of phase-locking is rigorously guaranteed by the generation and maintenance of a stable phase relationship. Compared with previous pattern recognition systems that have phase-locking issues, the scheme is feasibly deployable in practical scenarios. The proposed system performs differential encoding on the input data and the target through two Dis, respectively, and then completes signal reloading and pattern recognition. Hence, it can support the recognition of two bit-flip BPSK targets simultaneously, which improves the recognition efficiency. Moreover, the proposed system can process the input signal with tunable frequency, which is especially suitable for wavelength-division multiplexing (WDM) optical networks. For an input signal with different frequencies, the EDFA followed by the DI should be precisely adjusted. Due to the limited gain of EDFA, the frequency variation in the input signal is within a range, but not random. Furthermore, the proposed system can be extended to support the recognition of QPSK targets by substituting the DI with an all-optical format conversion that transforms QPSK signals into PAM4 signals. Specifically, the input QPSK data and the QPSK target are first converted into PAM4 signals using an all-optical format conversion device [16]. During the conversion process, it is necessary to maintain phase-locking and enable wavelength conversion. After transforming the phase-modulated signals into power-modulated signals, the PAM4 signals are reloaded to QPSK signals via the XPM effect in the NOLM. Similarly, since the counterclockwise carrier passes through the 50:50 coupler twice, it introduces a \(\pi\) phase deflection. Consequently, when the reloaded QPSK data and reloaded QPSK target exhibit a \(\pi\) phase difference, the input QPSK symbol and the target QPSK symbol have the same phase. This means that when no signal is generated at the output of the BPF, the input QPSK symbol matches the target QPSK symbol. Conversely, a pulse output from the BPF indicates a mismatch between these two symbols. The output of the BPF is then amplified by a fixed-power EDFA to amplify the pulse power to a specific value, enabling it to serve as the pump in the subsequent NOT gate. Thus, if the input QPSK symbol and the QPSK target symbol are in phase, a pulse indicating logic \"1\" will be output after passing through the NOT gate. Otherwise, no pulse, indicating logic \"0\", will be generated. Finally, the result is fed into the recirculating loop to complete the recognition and localization of the QPSK target within the input QPSK data. Compared with previous work, the proposed system can further improve flexibility and scalability, and accelerate the deployment of optoelectronic firewalls in optical networks.