## 2 Proposed Potentiostat Readout Circuit  
In [12], the FDDA used in the _FD_ potentiostat was implemented as shown in Figure 3.  
The FDDA was implemented in a two-stage amplifier, and common mode feedback (CMFB) was implemented using a switched capacitor. The balanced outputs of the FDDA are given in Equation (3), in which \(A_{O}\) is the open-loop gain of the FDDA, \(V_{pp}\) and \(V_{pn}\) are the non-inverting pairs, and \(V_{np}\) and \(V_{nn}\) are the inverting pairs. \[V_{op}=-V_{on}=A_{O}\big{[}(V_{pp}-V_{pn})-(V_{np}-V_{nn})\big{]} \tag{3}\]  
With the negative feedback loop, the two differential pairs of the FDDA become equal, as shown in Equation (4). \[V_{pp}-V_{pn}=V_{np}-V_{nn}\,;\,A_{O}\rightarrow\infty \tag{4}\]  
Therefore, the FDDA requires a very large open-loop gain for \(V_{cell}\) to track \(V_{src}\). However, the two-stage structure has a low open-loop gain, so \(V_{cell}\) cannot completely track \(V_{src}\). In addition, the switched capacitor increases the switching noise in the monitoring system, which requires high precision, thereby degrading the noise performance. Figure 3: FDDA used in _FD_ potentiostat. Since the monitoring system should be sensitive and linear to the target glucose concentration, the readout circuit should have a low noise characteristic. Chopping techniques are widely used to reduce low-frequency noise in the continuous time domain [13]. As shown in Figure 4, the chopping technique modulates and amplifies a low-frequency signal to a high-frequency band with more than 1/f corner noise using a chopper composed of four switches. Thereafter, through demodulation, the signal moves to a low frequency and the noise moves to a high frequency to obtain the low-noise amplified signal after passing through the low-pass filter (LPF). When using the chopping technique, the chopper switch and input parasitic capacitance determine the input impedance, so the chopper frequency and input transistor size should have appropriate values. In this paper, a low-noise potentiostat readout circuit with a chopper FDDA is proposed. The maximum signal swing can be realized using the rail-to-rail input and class-AB output stage, and a high open-loop gain is obtained through the cascode stage, allowing \(V_{\mathit{cell}}\) to track close to \(V_{\mathit{src}}\). In addition, the implemented Monticelli style class-AB output stage can increase the power efficiency. Further, the low noise characteristic was implemented by adopting a chopping technique. The top architecture of the proposed potentiostat readout integrated circuit (ROIC) is shown in Figure 5a. The proposed circuit implements a control unit that maintains a constant potential difference and a measurement unit that detects current changes by using only one FDDA. The three electrodes make current changes, and then, feedback resistors cause a voltage drop between the _OUTN_ and _OUTP_. The differential voltage between two differential signals can swings from \(-\)VDD to +VDD, and each of the positive and negative output voltages swings from the ground to the VDD. The feedback resistor can be adjusted to the value of the selected programmable resistor array through the serial peripheral interface (SPI) or connected to the external resistor. The bias circuit, timing generator, and SPI were on-chip. The structure of the FDDA control unit is shown in Figure 5b. The output of the FDDA and the input from the electrode form a negative feedback structure because the internal connection has a structure in which the current is merged between the positive input stage. Figure 4: (a) Chopper and driving clock and (b) chopping technique. A schematic of the proposed internal circuit of the chopper FDDA is shown in Figure 6. The proposed circuit uses the chopping technique at the input stage and the cascode stage to reduce low-frequency noise. The maximum signal swing was implemented using the rail-to-rail input stage, and the finite gain error was reduced by the high open-loop gain of over 110 dB.