# A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds
## 5 Conclusions and Future Work  
In this paper, the design, architecture and evaluation of a rapid reset 8T PUF utilising the power gating technique are presented. Its purpose is to enhance PUF stability and minimise the hardware penalty for error corrections. The design can apply on-off power cycles repeatedly to PUF clusters to facilitate fast multiple evaluations for extracting the bias probability of PUF cells. The ultra-fast speed enables TMV in different voltage and temperature corners or in the field. Dark-bit masking based on these extracted data can reduce the BER to close to zero in experiments. In the design, an SRAM-based 8T PUF cell with the ability to eliminate data retention is built, and a two-phase power gating method is devised and evaluated. Besides switching the power supply swiftly and saving  
\begin{table}
\begin{tabular}{l c c c} \hline \hline  & **String Length** & \(\mathbf{p}\)**-Value** & **Proportion** \\ \hline
**Frequency** & 2048 & 0.73856 & 64/64 \\
**Block Frequency** & 2048 & 0.91013 & 64/64 \\
**Cumulative Sums** & 2048 & 0.87698 & 64/64 \\
**Runs** & 2048 & 0.0204 & 11/64 \\
**Longest Run** & 2048 & 0.005 & 14/64 \\
**Rank** & 2048 & 0.44962 & 64/64 \\
**FFT** & 2048 & 0.18139 & 52/64 \\
**Approx. Entropy** & 2048 & 0.009 & 28/64 \\
**Serial** & 2048 & 0.18290 & 40/64 \\
**Linear Complexity** & 2048 & 0.63316 & 61/64 \\ \hline \hline \end{tabular}
\end{table}
Table 3: NIST analysis for 64 PUF groups.  
Figure 9: Golden bitmap of 2048 8T PUFs.  
power, the power-up process can be manipulated via varying the power gating method and parameters so as to decrease the interference between sensitive PUF cells and limit the in-rush current during power-up. Consequently, PUF stability and security are enhanced. In addition, the clean and fast reset makes it possible for swift and accurate PUF measurements either in simulation or in a fabricated silicon chip. The 8T PUF characteristics, including robustness, uniqueness and randomness, are thus qualitatively confirmed.  
Future work will include quantitative evaluations of the 8T PUF performance on various PVT corners and assessments of different power gating settings. The extracted unstable degrees of PUF cells will be post-processed and added to the PUF _Response_ to increase its entropy. In addition to this, a test chip is currently being fabricated. Afterwards, the fabricated test chip will enable on-chip statistical experiments, which serve as a platform to extract analogue secrets. Finally, the differences in the power-gated 8T PUF's entropy compared to its 6T-SRAM PUF counterpart will be assessed, measured and reported.  
Conceptualisation, A.B.; methodology, Y.Z. and A.B.; circuit design, Y.Z.; circuit simulation, Y.Z.; validation, Y.Z.; software, Y.Z.; formal analysis, Y.Z. and A.B.; resources, A.Y.; data curation, Y.Z.; writing--original draft preparation, Y.Z.; writing--review and editing, A.B and A.Y.; visualisation, Y.Z.; supervision, A.B. and A.Y. All authors have read and agreed to the published version of the manuscript.  
This research received no external funding.  
Not applicable.  
The authors declare no conflict of interest.  
The following abbreviations are used in this manuscript:  
8T 8-Transistor  
PUF  Physically Unclonable Function  
6T 6-Transistor  
SRAM  Static Random-Access Memory  
TMV  Temporal Majority Voting  
PVT  Process, Voltage and Temperature  
BER  Bit Error Rate  
ASIC  Application Specific Integrated Circuit  
IoT  Internet of Things  
IC  Integrated Circuit  
MCU  Microcontroller  
vddv  virtual power supply  
DPA  Differential Power Analysis  
FPGA  Field-Programmable Gate Array  
CRP  Challenge-Response Pair  
DRV  Data Retention Voltage  
WL  Word Line  
TT  Typical-Typical  
SS  Slow-Slow  
FF  Fast-Fast  
CMOS  Complementary Metal Oxide Semiconductor  
ACF  Applied Autocorrelation Function