# Free Space Optical Communication Networking Technology Based on a Laser Relay Station
## 3 Experiment and Analysis
In Figure 13, we control the amplitude of the received pulse voltage of receiver A to be about 2.055 V, that of receiver B to be about 1.527 V, and that of receiver C to be about 1.406 V. The yellow pulse signal represents the drive signal of LD at the transmitting end, with a pulse amplitude of 3.3 V. The blue signal represents the signal received by receiver A, the red signal represents the signal received by receiver B, and the green signal represents the signal received by receiver C. The 13-bit parallel ADC was used in this system. The highest bit represents the symbol bit, and the sampling voltage range is \(-5\) V\(\rightarrow\)5 V. After the ADC was calibrated, we set the threshold voltage of the system discrimination data to about 1.17 V.  
When the signal waveform at the receiving end was not ideal, we demodulated the received signal with ADC (ADC samples the signal and sends it to FPGA) and the signal directly with FPGA. When the signal was demodulated directly with FPGA, we directly sent the received pulse signal to FPGA to detect its edge and then used a counter to measure the pulse width to demodulate the data. Figure 14 shows the picture transmission and bit error rate of three receivers under three conditions. The ADC was used for demodulation, and the three receivers received the corresponding pictures accurately without error. When the FPGA was used to directly demodulate the signal when the voltage at the receiving end was 2.055 V, receiver A successfully received the picture and there was no bit error. When the voltage at the receiving end was 1.527 V, receiver B successfully received the picture, but the bit error rate was high, at about 0.37437600. There were many white dots in the picture, which is different from the original picture. When the voltage at the receiving end was 1.406 V, the bit error rate of receiver C was 0.99958403, and the picture could not be received, the receiving area was blank. At this time, the FPGA could not recognize the pulse signal, resulting in the failure of information transmission. Since the hardware circuit, mechanical structure and electronic components of the three receivers were almost identical, in order to further verify the impact of ADC demodulation on system stability, we conducted many experiments with receiver A. It can be seen from the experimental results in Table 2 that when the pulse amplitude voltage at the receiving end is between 1.661 V and 2.055 V (under the condition of a good communication environment), ADC sampling for demodulation and FPGA direct demodulation can accurately transmit data without bit error rate; When the pulse amplitude voltage at the receiving end gradually decreases from 1.585 V (in the case of poor communication environment), the bit error rate of the FPGA direct demodulation mode begins to appear, and with the gradual decrease in the pulse amplitude voltage at the receiving end, the bit error rate gradually increases,  
Figure 13: Waveform diagram of receiving terminal for changing receiving angle. and when the pulse amplitude voltage at the receiving end decreases to 1.413 V (under the condition of a harsh communication environment), the bit error rate of the FPGA direct demodulation mode reaches 100%; However, for the method of demodulation using ADC sampling, when the pulse amplitude voltage at the receiving end is reduced to 1.413 V, the system has a lower bit error rate, and when the pulse amplitude voltage at the receiving end is reduced to 1.007 V, the system has a bit error rate of 100%. Through experimental data, we can analyze that in the case of a good communication environment, the two demodulation methods are no different for this system; in the case of a poor communication environment, the ADC sampling method for demodulation can accurately transmit data. At this time, the FPGA sampling mode has a higher bit error rate, and the data transmission is inaccurate.