## 6 Local Oscillator Stability
We have met three challenges in this implementation:  
* An initial implementation was running on its own clock, independent of the clocks running the GPR timing circuitry. Due to the lack of synchronism between the rising edge of the reset signal defining the emitted pulse timing and the detection of this edge by the synchronous logic in the FPGA, a random delay between the emission and its detection was introduced. With an FPGA core clock of 50 MHz, such a jitter amounted up to 20 ns, an unacceptable variation with respect to the targeted sub-100 ps;
* the ProEx GPR is clocked by a 16-MHz core clock also distributed as a 1-MHz signal following division. Both clocks are readily available, and the 16-MHz clock is used to feed a direct digital synthesizer whose internal PLL (Phase Locked Loop) multiplies by 10 to reach a 160-MHz clock signal feeding the FPGA, synchronous with the reset signal. However, transmitting a 160-Hz signal to clock a circuit of a GPR operating with 100 or 200 MHz is a poor solution since the  
Figure 9: Comparison of the timing stability using the internal ramp generator provided by the receiver board in Malá’s ProEx control unit (blue) and when replacing this analog ramp generator with a Tektronix AFG3102 triggered by the reset signal provided by the GPR at the pulse repetition rate. Despite the 200 ps jitter announced in the AFG3102 documentation, the observed time delay standard deviation is close to the targeted 20 ps for 1 K temperature measurement resolution. receiver stage was picking up this clock signal, which quickly overwhelmed any small echo signal that should have been recovered by the receiver;
* The final solution was the use of an FPGA both with an internal PLL and able to use an input frequency as low as 16 MHz: Lattice's (now Microsemi) ICE40 met both conditions and was used, in conjunction with a fast digital to analog converter (AD9761), to generate the saw-tooth-shaped ramp by running a counter on the FPGA, reset by the signal that was used to trigger the analog switch. Due to excessive clock leakage, the output timing is noisier than its analog implementation, but does not exhibit significant drift over more than two-hour measurements (Figure 10). The AD9761 DAC was selected for its high speed and high resolution: sweeping the voltage range in 5 us with 10-bit resolution requires configuring the DAC every 5000/1024 = 4.9 ns or a refresh rate of 205 MS/s. Because the clock frequency of this particular DAC is limited to 40 MS/s, we have selected to reduce the resolution to eight bits by only keeping the most significant byte of the configuration word, generate a 40-MHz clock by multiplying the 16-MHz reference clock provided by the GPR (Figure 11 b) using the PLL internal to the FPGA: thus, the 256 steps are swept at a rate of 40 MHz or a ramp duration of 6.4 us. The DAC provides a digital low pass filter to reject the clock: the 43 clock cycle delay (lasting 1075 ns) introduced by this filter does not affect the equivalent sampling rate, but only the sampling start time, which is compensated for by tuning the voltage offset added at the DAC output. It is to be noted that the timebase drift exhibited by the commercial instrument cannot be reliably predicted: although associated with an excessive heating of an (AD843) operational amplifier reaching temperatures above 50 \({}^{\circ}\)C while the GPR control unit is kept at room temperature, heating thus the surrounding passive components, as well, the observed timebase drift is either positive (Figure 10a, green curve) or negative (Figure 11a, red curve), depending on the electronic board. The drift is always  
Figure 10: **(a)** Timing generator comparison. The time delay variation between two echoes separated by 300 ns is recorded by a ProEx GPR unit. The green curve results from the analog timing generator, the blue curve from the digital timing generator, with the digital to analog conversion performed using a discrete-component R-2R resistance network lacking clock filtering capability.