## 2 Methodology  
In recent years, noise-induced transient faults and circuit aging effects are two main mechanisms of VLSI circuit failure during its lifetime. These effects will change the timing and voltage levels of logic gates and can induce timing errors, voltage level distortion, or bit-flips when the influence accumulates to a certain degree. Most of the current transient fault analysis methods model the noise induced fault as a transient glitch and analyze the propagation characteristics of the glitch in the logic circuit. They focus on the timing errors of the circuit and apply the state-of-art statistical static timing analysis method to evaluate the timing effect. However, with respect to the voltage level, efficient analysis methods have not yet been studied in detail. In VLSI design, sequential logic circuits are typically partitioned into pipeline stages separated by latches, as shown in Figure 1.  
As shown in Figure 1, a noise-induced voltage transient (at the input port of NAND gate A) can become a voltage or timing fault only if it propagates to the end of one pipeline stage (at the input port of DFF2) and is stored in the latch. Thus, although hundreds of logic gates may exist in one pipeline stage, only the gates connected to the latch inputs are required to estimate the transient fault rates at the gates, and the computational complexity can be dramatically reduced. According to the characteristics of a CMOS logic circuit, the probability that a logic state is stored in the latch depends on the voltage level at the data input of that latch during the sampling time window. Because the noise-induced voltage transient arrives at the input of the latch at any point in the clock cycle with an equal probability, a high occurrence probability for the voltage transient will result in a high probability that the wrong logic state is captured by the latch. Therefore, the statistical analysis method proposed in this paper is applied to estimate the probability density function (pdf) of the voltage level at the end of one pipeline stage in the presence of noise effects. In a digital system, considering the low-pass characteristics of the logic gates and the central limit theorem, the effects of noise can be generally modeled as variations following a normal distribution in terms of the supply voltage and input signal of the pipeline stages, and MC simulation is commonly used to analyze these effects on circuit performance. However, the computational cost of MC is extremely high due to the complexity of the circuit. Some improved MC methods have effectively decreased the computational costs for transient fault rate analysis [19; 20] and have shortened the MC computation time. However, these methods do not consider the effects of some potential circuit characteristic changes in the analysis framework, such as aging effects, which undermine the accuracy of the analysis results during the lifetime of the circuit. Thus, in this paper, we propose a new NBTI-aware statistical analysis method to acquire accurate transient fault rates for different parts of the circuit to resolve the high computational cost problem of MC method. The design flow of the proposed method is shown in Figure 2.  
As shown in Figure 2, when the random effects of circuit characteristics are not considered, the input and output relationship of VLSI circuits can be determined by the conventional static voltage transfer characteristics (SVTC) method. However, the input signal and supply voltage of the logic circuits are random variables instead of static values due to the effects of environmental noise. Therefore, the SVTC method is not sufficient to accurately calculate the output of logic circuits, and a statistical analysis method based on probability voltage transfer characteristics (PVTC) is proposed. Figure 1: Pipeline stage structure of digital sequential circuits.