# Design of Shadow Filter Using Low-Voltage Multiple-Input Operational Transconductance Amplifiers
## 2 Proposed Circuit
### Mi-Ota
The ideal value of \(\beta_{i}\), assuming no parasitic capacitance effects, is given by the following:  
\[\beta_{i}=\frac{C_{Bi}}{\sum_{i=1}^{n}C_{Bi}} \tag{3}\]  
For \(n\) = 3, as in the given example, and assuming identical capacitances \(C_{Bi}\), \(\beta=1/3\). Figure 2: Proposed MI-OTA, (**a**) CMOS implementation, (**b**) MIBD MOST technique. To achieve optimal linearity, the coefficient \(m\) should equal 0.5 regardless of the biasing current Iset [33]. The small-signal transconductance \(g_{m}\) is expressed as follows:  
\[g_{m}=\beta\cdot\eta\cdot\frac{4m}{4m+1}\cdot\frac{I_{set}}{n_{p}U_{T}} \tag{4}\]  
Its value is \(1/\beta\eta\) times smaller compared to that of its single-input GD counterpart. This reduction arises due to the following:  
* The input capacitive divider (\(\beta\)), which attenuates the input signal. * The control of transistors M1 and M2 through their bulk terminals, in which the bulk transconductance is inherently \(1/\eta\) of the gate transconductance. The transconductance \(g_{m}\) is proportional to the biasing current Iset, allowing straightforward electronic tuning by adjusting Iset. It is important to note that signal attenuation at the input stage increases the input-referred noise of the circuit by a factor of \(1/\beta\eta\). This is due to the lower transconductance, which results from the combination of an input capacitive divider and the bulk-driven (BD) technique. However, since the linear range also increases by the same proportion, the dynamic range (DR) remains unchanged compared to the single-input gain-differential (GD) counterpart [33]. A detailed analysis of the noise performance of the MI-OTA is provided in [33]. It is worth pointing out, that, as long as the circuit operates in weak inversion, i.e., its transfer characteristic is described by (2), the linear range does not depend on Iset and transistors aspect ratios, provided that m = 0.5 = const., which ensures optimal linearity. On the other hand, provided that the transistor channel areas are sufficiently large, the dominant source of noise in the considered frequency range is thermal noise. For constant m, which is required for optimum linearity, assuming, for simplicity, identical slope factors for n- and p-channel transistors, n\({}_{\text{p}}\) = n\({}_{\text{n}}\) = n, the input referred noise of the circuit can be expressed as follows:  
\[\overline{v_{n}^{2}}\cong 2C\frac{q}{I_{set}}(nU_{T})^{2}\Delta f \tag{5}\]  
where C is a constant and q is the electron charge and \(\Delta\)f is the noise bandwidth. Consequently, the DR can be expressed in the following form:  
\[DR=\frac{V_{imm}}{nU_{T}}\sqrt{\frac{I_{set}}{2 Cq\Delta f}} \tag{6}\]  
where Vimm is the rms value of the input differential signal for the assumed nonlinear distortion, which, with m = 0.5, depends on the number of inputs but does not depend on the biasing currents and transistor aspect ratios. As can be concluded from (6), with the above assumptions, the DR is proportional to the square root of the biasing current Iset. However, since the specific value of Iset results from the required transconductance value, one can conclude that, for the given number of inputs and assumed transconductance, the DR of the circuit is constant and does not depend on other design parameters. The differential low-frequency voltage gain of the OTA can be approximated as follows:  
\[A_{VO}\cong g_{m}r_{out} \tag{7}\]  
where rout is the output resistance of the OTA, given by the following:  
\[I_{o}=g_{m}(V_{+1}+V_{+2}+V_{+3}-V_{-1}-V_{-2}-V_{-3}) \tag{1}\]0Note that this gain is also reduced by the input divider, which lowers the circuit's transconductance. However, the self-cascode composite transistors boost the output resistance and consequently the voltage gain to an acceptable level, sufficient for the intended application, without compromising the OTA's output voltage swing.