# Internal Backpressure for Onboard Crospoint-Buffered Switches with Port Multiplexing
## 2 Related Works  
Due to the limited resources onboard, it is difficult to use complex switching architecture such as the three-stage Clos network [22]. Therefore, a single-stage switching network [23] is the preferred architecture for onboard switching. Single-level crossbar switching networks are mainly divided into shared memory (SM) [24], the IQ switching network, the output queuing (OQ) switching network and the Crosspoint Queueing (CQ) [25] switching network. The SM structure uses a single memory to store data from all input ports. Its memory is shared by all ports, which maximizes memory utilization [26]. However, in each time slot, since memory must accommodate \(N\) concurrent write accesses and \(N\) concurrent read accesses, where \(N\) is the number of ports. This will lead to a gradual increase in the bandwidth of the switching structure and will therefore limit the size of the switch. In the output queued switching network, due to its simple control, good throughput, delay and QoS performance guarantee, it has been widely paid attention to, and a lot of research results have been achieved [23], as seen in Figure 2a. However, the output queued switched network requires the forwarding rate of the switched network and the access rate of the output buffer to be \(N+1\) times the line speed of the interface (\(N\) is the number of input ports in the switched network). And the development speed of the buffer access speed is much lower than the development speed of the router switching capacity and port rate, which is one of the biggest bottlenecks in the development of the switching network to attain high speed and large capacity. Therefore, it is impossible to use the output queued switching network in the high speed and large-capacity routing switching equipment, so the input queued switching network becomes the only choice. In order to overcome HOL problems caused by First-In-First-Out (FIFO) [27; 28; 29] Queuing, a Virtual Output Queuing (VOQ) [30] mechanism is proposed in the input queuing network. As shown in Figure 2b, VOQ means that each input port of the switching network divides the queuing buffer of cells into \(N\) sub-queues corresponding to \(N\) output  
Figure 2: (a) Output queuing switching structure. (b) Input queuing switching structure. (c) Crospoint buffered crossbar structure. ports of the switching network, and cells queue in the corresponding VOQ according to their destination ports. The crosspoint-buffered crossbar structure [31] is characterized by setting a specific number of buffers at each crossover switch position, as shown in Figure 2c. The current research on this structure mainly focuses on the switching network of CICQ. On the basis of IQ, CICQ adds a small amount of buffer to the cross node of the switching network to queue the group, and the input side organizes the queue by VOQ to eliminate the HOL problem. Because the number of crosspoint buffers is closely related to the hardware implementation process of the switching network, the current buffer capacity should not be too large. One study [32] proposed a load balancing architecture based on CQ switch to overcome the problem of the unsatisfactory performance of the CQ switch in the case of non-uniform traffic. In this structure, the load balancing phase is placed before the CQ phase. The input port in the second stage of load balancing converts the incoming non-uniform traffic into nearly uniform traffic and uses flow-based queues in each crosspoint buffer. The simulation results show that the proposed switch can achieve a similar delay performance to the OQ switch and much better throughput than a simple CQ switch under non-uniform traffic. It also achieves the same packet loss rate as CQ switches, while using only 65% of the buffer size of CQ switches. Another study [33] proposed a scheduling algorithm based on the CQ switch to achieve a flow-based performance guarantee. Each intersection accelerates two buffers and one buffer.