# A Crypto Accelerator of Binary Edward Curves for Securing Low-Resource Embedded Devices
## 5 Results and Comparison
### Performance Comparison
#### 5.3.1 Comparison on Virtex 4 Platform  
The study conducted by [16] explores the use of a digit parallel multiplier for applications with fewer resource constraints. However, when compared to our proposed non-pipelined architecture, their approach demonstrates higher hardware resource consumption and provides a lower throughput/area ratio. Similarly, when compared to our proposed two-stage pipeline architecture, their approach exhibits increased hardware resource utilization and significantly lower throughput/area. The proposed non-pipeline architecture offers significant optimizations when compared to the reconfigurable BEC design presented in [24]. It provides compelling benefits, including an impressive 86.2% reduction in hardware resource usage for point addition (PA) and point doubling (PD) computations while operating at a 1.91 times higher frequency. Furthermore, incorporating the point halving architecture, as proposed in [24], leads to 86.5% improvement in hardware resource utilization for PA and PD computations. In contrast to the architecture described in [24], the 2-stage pipelined architecture in this article employs 85.1% of the available resources, and when the point halving architecture is utilized, the resource usage is further reduced to 85.49%. Moreover, our architecture achieves 4.15 times higher frequency compared to the design in [24]. The work in [25] proposed two solutions. In the first solution, where the FF Gaussian-based multiplier is utilized, the proposed non-pipeline architecture achieves an impressive 3.52 times higher throughput/area compared to the existing architecture. Simultaneously, it utilizes only 89.7% fewer FPGA slices, showcasing its efficiency in resource utilization. Similarly, the proposed 2-stage pipelined architecture achieves an outstanding 5.12 times higher throughput/area while utilizing 88.9% fewer resources. Moving to the second solution presented in [25], the proposed non-pipelined architecture achieves a notable 3.41 times higher throughput/area, demonstrating its efficiency in computational performance. Furthermore, the proposed 2-stage pipeline architecture achieves an even more impressive 4.97 times higher throughput/area, further enhancing computational efficiency. Importantly, both architectures significantly reduce hardware resource utilization, utilizing 75.7% fewer resources for the non-pipelined architecture and 73.8% fewer resources for the 2-stage pipelined architecture, when compared to the architecture presented in [25]. The work in [29] has optimized the existing architectures for BEC by utilizing a hybrid algorithm combining Montgomery and double-and-add techniques. Comparing the proposed architecture with the non-pipelined architecture in [29], considerable improvements have been made. The proposed architecture utilizes 9.08% fewer hardware resources, operating at 2.13 times lower operational frequency, and achieves a 1.12 times lower throughput/area ratio. These optimizations indicate better resource utilization and improved efficiency in terms of hardware requirements and execution time. Furthermore, when comparing the pipelined architectures, the hardware resources used in the proposed two-stage pipelined architecture are 1.6% fewer than the existing hybrid architecture. Moreover, the proposed two-stage pipelined architecture operates at a 1.9% higher frequency and achieved a 1.29-times higher throughput/area ratio. These results suggest that theproposed architecture outperforms the existing hybrid architecture in terms of resource utilization, operating frequency, and overall throughput efficiency. The proposed non-pipelined architecture demonstrates superior performance compared to the digit serial pipelined multiplier architecture in [38]. It achieves remarkable optimizations by utilizing just 90.5% of the hardware resources required by the [38] architecture while achieving 3.56 times higher throughput. This significant reduction in resource usage showcases the efficiency of our design.