# FPGA Applied to Latency Reduction for the Tactile Internet
## 7 Results
For the kinesthetic feedback force, the variables \(M[F32](n)\) of the KFF-HMD module correspond to \(\tau_{1}^{HMD}[F32](n)\), \(\tau_{2}^{HMD}[F32](n)\) and \(\tau_{3}^{HMD}[F32](n)\). For the feedback force, the variables \(M[F32](n)\) of the FBF-HSD module correspond to \(F_{x}^{HSD}[F32](n)\), \(F_{y}^{HSD}[F32](n)\) and \(\Gamma_{z}^{HSD}[F32](n)\). Finally, in the MSE equation the \(M^{\text{SW}}[F32](n)\) corresponds to the same variables as the software-implemented model. Table 1 shows the mean square error between the software models and the hardware ones proposed in this paper. The obtained MSE-related results prove to be noteworthy, showing that the forward kinematics (FK-HMD and FK-HSD), inverse kinematics (IK-HSD), kinesthetic feedback force (KFF-HMD) and feedback force (FBF-HSD) modules had an acceptable response, even when using a hybrid representation, compared to the software model that uses a floating point representation. It can be observed that for the variables of the FK-HMD and FK-HSD modules the error was in the range of \(10^{-08}\), for the IK-HSD module the error was of \(10^{-06}\), for the variables of the KFF-HMD module the error was of \(10^{-07}\) and for the FBF-HSD module the error was in the range of \(10^{-16}\). These values demonstrate that the FPGA implementations presented an equivalent behavior to the software models. In a hardware implementation, it is important to analyze some requirements post-synthesis such as available hardware usage and the execution time. In the case of FPGAs, the resources are measured through the use of lookup tables (LUTs), Registers and Digital Signal Processors (DSPs) units, to name a few. After validating the hardware-implemented models, synthesis results were obtained using the implementation designed for an FPGA Xilinx Virtex 6 XC6 VLX240T-1 FF1156. The used Virtex 6 FPGA has 37,680 slices that group 301,440 flip-flops, 150,720 logical cells that can be used to implement logical functions or memories, and 768 DSP cells with multipliers and accumulators. The implementations and results used the Matlab/Simulink and the Xilinx System Generator. Table 2 presents the post-synthesis results related to FPGA resource utilization, sampling rate, and throughput for the modules FK-HMD, KFF-HMD, FK-HSD, IK-HSD, and FBF-HSD. The first column shows the name of the module, the next three columns called registers, LUTs and multipliers represent the amounts of resources used in the FPGA. The column register represents the number of flip-flops that were used, followed by the total percentage used. The column LUTs represents the number of LUTs that were used, followed \begin{table}
\begin{tabular}{c c c} \hline \hline
**Module** & **Variable** & **MSE** \\ \hline \multirow{4}{*}{FK-HMD} & \(x^{HMD}[F32](n)\) & \(2.333\times 10^{-8}\) \\  & \(y^{HMD}[F32](n)\) & \(8.316\times 10^{-9}\) \\  & \(z^{HMD}[F32](n)\) & \(1.656\times 10^{-8}\) \\ \hline \multirow{4}{*}{KFF-HMD} & \(\tau_{1}^{HMD}[F32](n)\) & \(1.467\times 10^{-7}\) \\  & \(\tau_{2}^{HMD}[F32](n)\) & \(5.207\times 10^{-9}\) \\  & \(\tau_{3}^{HMD}[F32](n)\) & \(3.350\times 10^{-7}\) \\ \hline \multirow{4}{*}{FK-HSD} & \(x^{ENV}[F32](n)\) & \(2.333\times 10^{-8}\) \\  & \(y^{ENV}[F32](n)\) & \(8.316\times 10^{-9}\) \\  & \(z^{ENV}[F32](n)\) & \(1.656\times 10^{-8}\) \\ \hline \multirow{4}{*}{IK-HSD} & \(\theta_{2}^{HSD}[F32](n)\) & \(3.731\times 10^{-6}\) \\  & \(\theta_{3}^{HSD}[F32](n)\) & \(2.847\times 10^{-6}\) \\ \cline{1-1}  & \(\theta_{3}^{HSD}[F32](n)\) & \(2.702\times 10^{-6}\) \\ \hline \multirow{4}{*}{FBF-HSD} & \(F_{x}^{HSD}[F32](n)\) & \(2.437\times 10^{-16}\) \\  & \(F_{y}^{HSD}[F32](n)\) & \(1.731\times 10^{-16}\) \\ \cline{1-1}  & \(F_{z}^{HSD}[F32](n)\) & \(3.360\times 10^{-16}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Mean squared error (MSE) results for floating-point implementation. by the total percentage used. In addition, the column multipliers represents the number of DPS48 internal multipliers that were used, followed by the total percentage used.