# Design and Implementation of a System-on-Chip for Self-Calibration of an Angular Position Sensor
## 4 Simulation and Experimental Results
### Experiment Based on FPGA and a CAPS  
An experiment is conducted to verify the prototype, and the primary experimental equipment is shown in Figure 15. A CAPS [3] is placed on the turntable (Aviation Industry Co., Beijing, China) and outputs a measurement signal during rotation. The sensitive petal-form electrodes of the CAPS are sine waves in polar coordinates spanning 1 cycles. The signal is demodulated and converted from analog to digital by the signal acquisition circuit. The digital signal is then self-calibrated on the ARM MPS2+ FPGA prototyping board [29] and the drive clock frequency is 25 MHz. The static measurement error of the turntable is about 0.0001 degrees and the dynamic measurement error is about 0.001 degrees, which meets the experimental requirements. In the self-calibration process, the turntable rotates at 18\({}^{\circ}\)/s and the sampling frequency is 250 Hz. The resolution of the acquired angle is 0.072\({}^{\circ}\) and the exact values are obtained through the turntable. Figure 16 shows the waveform of the collected signals. Figure 14: Arctangent operation error in the RTL simulation. Figure 15: Experimental equipment including a CAPS, signal acquisition circuit, and a Field Programmable Gate Array (FPGA) on which the SoC is implanted. In the experiment, the step factor of signal \(U\) is set to \(W_{1}=\left(0.2,0.2,0.2\right)^{T}\) and the step factor of signal \(V\) is set to \(W_{2}=\left(0.5,0.3,0.1\right)^{T}\). The angular error without calibration is shown in Figure 17. The peak-to-peak value and maximum absolute value of the error are \(43.3964^{\circ}\) and \(22.5154^{\circ}\), respectively. The angle values output by the SoC during the calibration process are also analyzed. The error results are shown in Figure 18, indicated by the angle error curve in demodulation mode for the evaluation of the accuracy of parameter calculations. The peak-to-peak value of the error is \(1.7189^{\circ}\), reduced to \(3.96\%\). The maximum absolute value of the error is \(0.9814^{\circ}\), reduced to \(4.36\%\). When the system is operating with angular input that is not continuous, stored parameter values need to be read, and the signal is calibrated using Equation (4). Under this circumstance, the system works in calibration mode. The values of an identified parameter are read through UART (Table 9). Figure 16: Waveform of the collected signals. Figure 17: Angular error without calibration in experiment. Figure 18: Angle error curves under different conditions. Figure 18 also shows the waveform of this angular error, indicated by the angle error curve in calibration mode. The peak-to-peak value of the error is 1.8683\({}^{\circ}\), reduced to 4.31%. The maximum absolute value of the error is 1.1630\({}^{\circ}\), reduced to 5.17%. In addition, the signal parameters in the calibration mode can also be obtained by other methods and written in the program; the reference signal frequency in the demodulation mode can also be written in the program to achieve closed-loop control of the frequency estimation. An experiment for another identification method is carried based on previous work [9], which processes the same error model and the operation is simple. Identification values are summarized in Table 10 and angular error is shown in Figure 18, indicated by the angle error curve after calibration with the method used in [9]. The peak-to-peak value of the error is 3.0617\({}^{\circ}\), reduced to 7.06%. The maximum absolute value of the error is 1.7284\({}^{\circ}\), reduced to 7.68%. The effect of the proposed scheme is not worse than the original work, and even has a better error suppression effect in the experiment. As for the analysis of execution time, the results are summarized in Table 11 for the proposed scheme and the method in [9], in which the parameter convergence time is defined as the total execution time. The device in the experiment is a Cyclone V FPGA with a clock frequency of 25 MHz. The algorithm in [9] is executed under the Windows 7 operating system.