## 2 Multi-Chip Interconnection Topology Design
### The Intra-Chip Interconnection Design Approaches  
Depending on the individual chips in the system, the intra-chip interconnection can be different and customized for the particular chips. For example, for small SoC chiplets with a few cores a bus-based interconnect mechanism might be sufficient. However, if each individual chip is large enough with several cores it might require a NoC for high performance and modular or scalable design. The intra-chip NoC should be carefully designed in a way that it avoids long multi-hop internal paths and therefore does not make the intra-chip network a bottleneck for the whole system. Therefore, it is desired to adopt an intra-chip topology that has small diameter with as well as high reliability. Keeping the small network diameter in mind, small-world architectures were proposed [31; 32] and evaluated for intra-chip NoCs. Small world graphs are a type of complex network where both short distance as well as long distance links create a connected graph. It has both high local connectivity as well short diameters which scales well with size. While irregular topologies have better connectivity and diameter properties, unequal wire lengths in irregular topologies such as small world networks [32] make design, implementation, and verification very challenging. Therefore, to avoid complexity in design, verification and manufacturing of general-purpose multicore processors adopt regular intra-NoC architectures such as mesh, torus and folded torus [1; 2]. As the performance of the multi-chip system also depends on the different traffic patterns, intra-NoC topology is chosen based on the support needed to handle such traffic. Therefore, for systems running memory intensive application a concentrated or hierarchical intra-chip topology is adopted to support multicast/broadcast-based cache coherent messages in the system. As a small amount of such broadcast traffic can significantly degrade system performance, adopting a concentrated, hierarchical or small-world topology for such traffic can improve the performance of the NoC compared to a regular mesh architecture [5; 33]. While the intra-chip topology can have a regular, irregular, or concentrated architecture, different chiplets can implement different intra-chip architectures depending on the specific task or applications they are designed for. In a homogeneous system, each chip has the same intra-chip interconnection architectures as well as core architectures. Whereas in the heterogeneous system the intra-chip interconnection or core can have different architectures in different chips. Figure 2: A conceptual view of a multichip system with inter-chip wireless communication. Various intra-chip NoC switch designs have been proposed to enable the variety of architectural needs of the intra-chip NoCs. These range from multi-cycle switch architectures [34] to low-latency single cycle ones [35]. Wide and ultra-wide switches enabling wide flit size for high throughputs have been investigated but are shown to be prohibitively power hungry for ultra-wide flit sizes of higher than 128 bits [36]. Heterogeneous, switch architectures altering between wide and low-latency designs are proposed for NoCs experiences heterogeneous traffic scenarios. Express virtual channels in switches have been proposed to bypass intermediate switches once path discovery has been accomplished with the help of routing have been shown to improve performance of NoCs [37]. A NoC router with power-gated WIs is proposed in [38] to reduce the power dissipation of the wireless transceivers when they are not used. However, as shown in [11] the contribution of the intra-chip interconnection for large multi-chip systems is marginal as throughput and latency of various architectures converge when the number of chips in the system increases. This is because when the system becomes large with many chips along with an increase in inter-chip traffic, the chip-to-chip interconnect becomes the main bottleneck instead of the intra-chip NoC.