# A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process
## 2 Proposed ADC Architecture and Pre-Quantization Timing
### Working Timing Strategy
#### 2.2.2 Pre-Quantization Timing  
PQT, including sampling, pre-quantization, and amplification phases, is presented in Figure 3. Compared with traditional timing, \(\phi_{1}\), \(\phi_{1e}\), \(\phi_{2}\), and \(\phi_{2e}\) are the same for both timing strategies. Different from traditional timing, pre-quantization is introduced to comparators. PQT focuses on the distribution of timing, which aims to optimize the sample and quantizationtiming, thus maximizing the amplifier's settling time. By dividing  
Figure 1: Block diagram of 1 GS/s 12-bit pipelined analog-to-digital converter (ADC). The proposed pre-quantization timing, including \(\phi_{1}\), \(\phi_{1e}\), \(\phi_{2}\), \(\phi_{2e}\), \(\phi_{3}\), \(\phi_{3e}\), \(\phi_{4}\), and \(\phi_{4e}\), is generated by a clock schematic. The clock schematic comprises a high-speed interface current mode logic (CML), a non-overlapping clock, and a DLL.  
half of the sampling phase to the comparator, PQT strategy can relieve the pressure on the operational amplifier's output-setting. During the sampling phase, the \(\phi_{\rm 3e}\) resets the comparator output to a high-level 100 ps early, and then the comparator works normally during 25% of the duty cycle of \(\phi_{\rm 3}\). The whole quantization is completed within about 250 ps.  
1. Sampling: The period of \(\phi_{1}\) or \(\phi_{2}\) is double to that of \(\phi\): when \(\phi_{1}\) or \(\phi_{2}\) are sampling clock signal, it is the square wave signal that controls the switched capacitor circuit to start sampling.
2. The bottom plate sampling: \(\phi_{\rm 1e}\) and \(\phi_{\rm 2e}\) are early shut-down clocks; the falling edge of \(\phi_{1}\) is earlier than that of \(\phi_{\rm 1e}\), and the falling edge of \(\phi_{\rm 2e}\) is earlier than that of \(\phi_{\rm 2}\), which are used to ensure the bottom plate sampling technology;
3. Pre-quantization: \(\phi_{\rm 3}\) and \(\phi_{\rm 4}\) are clocks for the comparator. The high voltages of \(\phi_{\rm 3}\) and \(\phi_{\rm 4}\) are at the half voltages of \(\phi_{\rm 2}\) or \(\phi_{\rm 1}\), respectively. The comparator occupies about  
Figure 3: Pre-quantization timing, including sampling, pre-quantization, and amplification phase. Detailed timing is provided for SHA, Stage1–Stage6. For Stage1, Stage3 and Stage5, \(\phi_{1}\), \(\phi_{\rm 1e}\), and \(\phi_{\rm 2}\) are provided to sample and amplify. For Stage2, Stage4, and Stage6, \(\phi_{\rm 3}\) and \(\phi_{\rm 3e}\) are designed for comparators. \(\phi_{\rm 2}\), \(\phi_{\rm 2e}\), and \(\phi_{\rm 1}\) are provided to sample and amplify. \(\phi_{\rm 4}\) and \(\phi_{\rm 4e}\) are designed for comparators.  
Figure 2: The traditional timing, including the sampling phase and the amplification phase. Detailed timing is provided for SHA, Stage1–Stage6. \(\phi_{1}\), \(\phi_{\rm 1e}\), and \(\phi_{\rm 2}\) are provided for Stage1, Stage3, and Stage5 to sample and amplify. \(\phi_{\rm 2}\), \(\phi_{\rm 2e}\), and \(\phi_{\rm 1}\) are provided for Stage2, Stage4, and Stage6 to sample and amplify. The green and purple parts represent quantization.  
250 ps of time to complete quantization. During the phases of \(\phi_{3}\) and \(\phi_{4}\), comparators reset the output to a high voltage 100 ps early.
4. Amplification: clock for amplification. \(\phi_{1}\) is the non-overlapping clock signal of \(\phi_{2}\) (\(\phi_{2}\) is the non-overlapping clock signal of \(\phi_{1}\)), used to control the op-amp to start amplifying at the high level.