# An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios
## 3 Baseband Modulator Architecture
### Baseband Modulation for 5G Waveform Candidates
The binary counter word length is eight bits (\(\log_{2}N^{\prime}-1+\lceil\log_{2}(\log_{2}N^{\prime})\rceil\), with \(N^{\prime}=64\)), as indicated in [33]. As in [29], the \(N^{\prime}\)-point IFFT is followed by upsampling. The upsampler introduces \(\frac{N}{N^{\prime}}-1\) zeros between consecutive IFFT output samples, and its implementation consists of an FSM alternating between output data and output zero states. Bandpass FIR filtering for each sub-band is carried by a Dolph-Chebyshev filter with filter length equal to the LTE CP length plus one (\(L=L_{CP}+1\)). A FIR filter architecture with a transpose structure was adopted because, unlike the direct FIR model, it does not require an extra input shift register, nor a tree of pipelined adders to achieve high throughput. For the UFMC numerologies from Table 1, the filter lengths are odd, and the coefficients are symmetric with a single center coefficient equal to one. The multiplications by the center coefficient can be ignored, as they do not affect the input value. However, the remaining \(L-1\) coefficients imply non-trivial multiplications. The amount of non-trivial multiplications per FIR filter can be halved (\(\frac{L-1}{2}\)) by exploiting the coefficient symmetry. As the sub-band signal to be filtered is complex-valued, both real and imaginary parts have to be filtered. Therefore, for each sub-band branch, we have two FIR filters that combine \(L-1\) non-trivial multiplications. In Xilinx FPGAs, non-trivial multiplications can be efficiently executed by DSP blocks, which are embedded into the logic fabric in a column arrangement. Cost-optimized devices have a smaller amount of DSP blocks, and their utilization should be carefully managed. For instance, the xc7z020 device has 220 DSP blocks, while the total amount of multiplications for FIR filtering in all three UFMC sub-bands (\(3\times(L-1)\)) is 108 for Mode 1 and 216 for Mode 2. The high DSP utilization and its sparse distribution within the logic fabric degrade the scalability of the UFMC modulator. Moreover, it also hampers the place-and-route tasks by EDA tools, affecting overall timing closure. In these circumstances, we adopted a multiplier-less architecture for FIR filtering where FIR coefficients in the Q1.5 format are represented using the Canonic Signed Digit (CSD) system with minimum non-zero bits. Multipliers are then substituted by shift-and-add graphs. As an example, for a coefficient equal to 0.90625, we have:  
\[ \begin{split} 0.90625_{10}&=0.11101_{2}\\ &=1.00\overline{1}01_{2,CSD}\\ &=(1-2^{-3}+2^{-5})_{10}.\end{split}  \tag{1}\]  
Figure 6 illustrates the shift-and-add graph to implement \(0.90625\times x\). This filter design eliminates the use of DSP blocks, but increases slice utilization. Yet, slices are the predominant resource type in the FPGA logic fabric (13,300 slices in the xc7z020 device), which makes our approach viable. After FIR filtering, it is necessary to shift the sub-band signal to the corresponding frequency band. The frequency shift module for each sub-band has a ROM memory to store the complex exponential values and a complex multiplier similar to the one used in the IFFT module. Thus, the overall DSP block  
utilization in the UFMC modulator consists of three DSPs in the IFFT and three DSPs in the frequency shift module per sub-band branch. Finally, the filtered sub-band responses are summed to create the aggregate UFMC signal.