## 3 Tests and Results
### Kitsuine Backplane Verification
#### 3.2.1 Ground Tests  
The main bus, as well as the SPATIUM-II CPLDs in the backplane, served as voltage followers. The input and output signals were compared during the board-level verification. The same test method as was used on the 3U backplane prototype was used. Table 6 lists the digital interfaces that were routed to the CPLD. The main bus CPLD routed four pairs of UART, two sets of SPI, and five DIO lines. The SPATIUM-II CPLD routed three pairs of UART, one SPI, and seven DIO lines. The data confirmed that the CPLD could route serial interfaces such as UART and SPI.  
\begin{table}
\begin{tabular}{c c c} \hline \hline \multirow{2}{*}{**Interfaces**} & \multicolumn{2}{c}{**No. of CPLD Pins**} \\ \cline{2-3}  & **Main Bus** & **SPATIUM-II** \\ \hline UART & 16 & 12 \\ SPI & 16 & 8 \\ DIO & 10 & 14 \\
**Total** & **42** & **34** \\ \hline \hline \end{tabular}
\end{table}
Table 6: Summary of digital interfaces routed through CPLD.  
Figure 12: Input and output signals on a CPLD.  
A functional test to check for bit errors was performed in the KITSUNE backplane, which is similar to the 3U backplane prototype. In the test, the Raspberry Pi module transmitted a data stream to the OBC/EPS every 300 ms, and the device then compared the signal received from the ADCS adapter board. When a difference between the two datasets was detected, the Raspberry Pi module displayed the number of bit errors. The test was conducted at temperatures ranging from \(-10\)\({}^{\circ}\)C to \(+70\)\({}^{\circ}\)C in a vacuum chamber. There was no recorded bit error during the entire 12 h test.  
Two backplane-related failures were observed during system integration. During the engineering model (EM) development, a line connecting an umbilical in the ADB to the EPS1 was accidentally routed through the main bus CPLD. It was found that the line was used to monitor the battery voltage. The CPLD was severely damaged due to the error, so the ICD was thoroughly reviewed before finalizing the design to prevent the incident from reoccurring. Another recorded failure was in one of the main bus SPI interfaces. The ADCS adapter board's microcontroller could not obtain data from the ADB's magnetometer placed on the ADB, and it was found that the memory input slave output (MISO) line's signal direction was incorrect. This issue was quickly resolved by updating the VHDL code and reprogramming the CPLD.  
The operation and performance of the flight model (FM) satellite were tested in various space environment conditions to demonstrate that the satellite could operate properly in low Earth orbit. A summary of the thermal vacuum and vibration tests is shown in Table 7.  
The telemetry reading from the thermal vacuum test (TVT) in Figure 13 shows that the main bus CPLD temperature was about 2 \({}^{\circ}\)C higher than that of the SPATIUM-II CPLD. This is because the main bus CPLD was placed right below the battery, which is a heat source, for the entire test duration. The TVT ran for two cycles, and the recorded minimum and maximum CPLD temperatures were \(-3\)\({}^{\circ}\)C and \(+50\)\({}^{\circ}\)C. There was no recorded anomaly in the performance of the backplane for the entire 87 h duration.  
\begin{table}
\begin{tabular}{c c} \hline
**Test** & **Information** \\ \hline
**Thermal Vacuum Test** & \\ Temperature range & \(-15\)\({}^{\circ}\)C to \(+60\)\({}^{\circ}\)C \\ Number of cycles & 2 \\
**Vibration Test** & \\ Acceleration level & 5.77 Grms \\ Duration & 2 min \\ \hline \end{tabular}
\end{table}
Table 7: Space environment test parameters.  
Figure 13: TVT CPLD temperature profile.