# A Review of Cell Operation Algorithm for 3D NAND Flash Memory
## 3 Read Algorithm
### Improvement of Read Disturbance  
To read the Vt of the selected WL from the 3D NAND array, the read voltage of the desired target level to the selected WL is applied and at the same time the pass voltage to the unselected WL is applied to cause current to flow through the entire string. Since the read voltage applied to the unselected WL is relatively approximately 3\(\sim\)4 V lower than the pass voltage used in the program operation, read disturbance does not occur during several read operations. However, in recent years, the users are demanding increased numbers of read operations; the already large block-size due to the increment of WL stacks and strings is also exponentially increasing the number of read pass voltages applied to individual cells. When read stress is applied hundreds of thousands of times, a soft programming read disturbance is generated by the potential difference between the poly-silicon channel and the gate, resulting in read failure [62]. A generally conceivable method to improve the soft programming read disturbance is to lower the read pass voltage: the string current of the cell is reduced and the sensing margin is also reduced, which deteriorates the read margin between the cell distributions, so this is not an appropriate engineering approach. In 2D NAND, a self-boosting read scheme has been adopted to alleviate the above read disturbance, and was quickly applied to 3D NAND [63], as shown in Figure 8. In this technique, the read pass voltage of the unselected WL rises and, at the same time, the poly-silicon channel is also boosted by turning off the upper and lower select transistors in the unselected string by capacitive coupling. This effectively reduces the potential between the gate and the channel, improving the soft programming read disturbance. However, if the channel boosting level is too strong, HCI-related read disturbance phenomenon occurs [64; 65]. As an example, the channel potential level of the unselected WL increases as the read pass voltage rises, whereas much lower read voltage or even a negative voltage (negative verify level) can be applied to the selected WL, so a strong transverse electric field is applied underneath the poly-silicon channel between selected WL and adjacent WLs. This accelerates BTBT tunneling current and generates electron-hole pairs, eventually inducing hot carrier injection toward the unselected WL. When the programed level is the highest in the selected WL, the worst HCI-related read disturbance can be provoked because the effective channel potential applied by the gate is the lowest. Figure 8: Read operation (**a**) with a conventional channel initialization. Reprinted/adapted with permission from Ref. [63], 2022, IEEE. (**b**) with the proposed unselected string boosting scheme. Reprinted/adapted with permission from Ref. [63], 2022, IEEE. To solve this problem, [PERSON] suggested a technique to apply shorter pulse widths to the upper and lower select transistors in the unselected string than the read pass pulses applied to unselected WLs, and to synchronizing both pulses at their rising edges [65]. With the proposed method, the channel boosting potential in the unselected string is drained, suppressing HCI-related read disturbance. In addition, to reduce the electric field between the selected WL and the adjacent WLs by the high boosting level during the read operation, a method of lowering the read pass voltage of the adjacent WL was also proposed [66]. However, in this method, since the adjacent WL bias during the verify and read operations can be different, there is a possibility that the Vt of the read operation is shifted compared to that of the verify operation or that cell distribution widening may occur, and so an additional circuit to control this difference will be needed. Meanwhile, [PERSON] et al.