# A Reconfigurable SRAM CRP PUF with High Reliability and Randomness
## 2 Conventional SRAM CRP PUF  
### Structure and Operation Principle  
Figure 1a depicts the conventional structure of the PUF cell as described in [22]. Here, an n-bit challenge input signal, C\(<\)_n_\(-\)_1_:0\(>\), is used to generate two opposing response outputs, _BL_ and _BL_. Other signals such as _PRE_ and _WL_ ensure that the circuit is controlled corresponding to each operation mode. This structure is based on the 6T SRAM structure  
with two outputs, _OUT_ and _OUT_B_. The core of this structure primarily comprises two inverter arrays positioned on the left and right sides. These two inverter arrays are interconnected to form a feedback loop, where the output of the left array connects to the input of the right array, and vice versa. Each array comprises _n_/4 identical inverters arranged in parallel. Each individual inverter within this array comprises a series of VDD pull-up transistors and a VSS pull-down transistor, which are activated by the challenge input. Thus, a 2-bit challenge input is applied to configure each inverter, an _n_/2-bit challenge input is applied to configure each inverter array, and an _n_-bit challenge input, _C_+_n_-_1:0_>, is applied to configure the PUF cell structure.  
Each inverter array must be precisely configured to achieve a balance in the relative strengths of the VDD pull-ups and VSS pull-downs. Essentially, the number of '0' bits in _C_+_n_/4_-_1:0_> and _C_+_n_/2_-_1:n_/4_> must be identical to ensure a balanced connection to VDD between the two arrays. Similarly, the number of '1' bits in _C_+_3_n_/4_-_1:n_/2_> and _C_+_n_-_1:3_n_/4_> must be identical to maintain balanced connections to the VSS between the two arrays. This configuration ensures that the response generated by the PUF cell depends on the physical mismatch inherent to individual transistors, rather than a predetermined voltage generated from the imbalance strengths of the two arrays.  
Figure 1(b) depicts the timing diagram for the PUF cell, which comprises two operating modes: \"Pre-charge\" and \"Configuration & Evaluation\". In the \"Pre-charge\" mode, the PUF cell outputs are reset to the initial value, VDD, before the PUF cell state is set to generate new output values in the \"Configuration & Evaluation\" mode. During the \"Pre-charge\" mode, each inverter's output voltages, _OUT_ and _OUT_B_, are charged to VDD when an active low signal is applied to the _PRE_ transistors. The bit-lines, _BL_ and _BL_B_, are  
Figure 1: (**a**) Unit cell schematic of conventional SRAM CRP PUF, (**b**) its operational timing diagram, and (**c**) Switching delay difference of challenge.  
also set to VDD. Simultaneously, the NMOS challenges, _C<n-1:n/2>_, and PMOS challenges, _C<n/2-1:0>_, are set to low and high logic levels, respectively, to disconnect both the inverter arrays from the power supply. Following the \"Pre-charge\" mode, the _PRE_ is high and the \"Configuration & Evaluation\" mode begins by applying an n-bit challenge input to configure the PUF cell while concurrently powering it up. Subsequently, the two cross-coupled inverter arrays compete with each other to determine the output logic level. The outputs are read to bit-lines when the word-line signal, _WL_, goes high.