# A Thermopile Device with Subwavelength Structure by CMOS-MEMS Technology
## 4 Experimental Results and Discussion  
Thermpile sensors are designed and fabricated by using the TSMC 0.35 \(\upmu\)m 2P4M CMOS-MEMS process, which is achieved after a series of anisotropic etching. As a thermopile is a device that uses a local temperature difference to measure thermal radiation, it is susceptible to environmental conditions. To avoid this problem, we configured several proposed thermopiles with various SWSs and a thermopile without an SWS in the same chip. Figure 5 shows the schematic diagram of the structure of TSMC 0.35 \(\upmu\)m 2P4M CMOS MEMS. The standard CMOS process in TSMC fabricates the array of thermocouples with CMOS materials of polysilicon and aluminum as in step 1. In step 2, the etching windows and active area are formed by some specific MEMS processes. There structures are fabricated with RLS and RLSSI processes which etch the Si\({}_{3}\)N\({}_{4}\)/SiO\({}_{2}\) layers and  
Figure 4: Simulation results of the normalized absorption difference with the target temperature for the thermopiles for the thermopiles with various SWS. Figure 5: Schematic diagram of the structure of TSMC 0.35 \(\upmu\)m 2P4M CMOS-MEMS process. Figure 3: Schematic top-view of the (**a**) rectangular-hole and (**b**) cylindrical-hole patterns for the SWS. silicon substrate subsequently. The patterns of the SWS are formed in the RLS process with RIE etching of the Si\({}_{3}\)N\({}_{4}\)/SiO\({}_{2}\) layers on the active area. By using the RLSSI process, the RIE etching of silicon substrate is proceeded under the membrane. Therefore, the sensing area is floated and filled with arrays of etching hole as the periodic refractive index waveguide. The silicon substrate beneath the cantilever beam is removed and only a thin structure layer with 7 \(\upmu\)m thickness is left on top. The structure of the thermocouples is designed with a strip of n-poly 20 \(\upmu\)m width and a length of 200 \(\upmu\)m. An aluminum wire with a width of 0.5 \(\upmu\)m was deposited on top of the n-type polysilicon. Finally, the thin cantilever beam was floating upon the etched cavity with a poor thermal conduction, which served as a sensing structure and a good platform for investigation and analysis of SWSs. To show the effect of the SWSs for the CMOS compatible thermopile, the thermopile without SWS was also simulated and fabricated. Figure 6a,b shows SEM images of a CMOS compatible thermopile, which can be compared to Figures 1 and 5. The active area filled with IPC is verified to suspend over a cavity of silicon substrate and the cantilever beam structure is well built under the processes. The thermocouples are patterned and embedded between the passivation oxide layers. Figure 6a,b shows the SEM of (a) RHT and (b) CHT subwavelength structures for the CMOS compatible thermopile. One can see that the structures of SWS are well fabricated for thermopile devices and both are successfully fabricated by the CMOS-MEMS process. It is worth noting that holes of RHT and CHT subwavelength structures are well defined, as in our design. The size of the design, \(3\times 15\)\(\upmu\)m for RHT after dry etching of active area deviated to \(3.27\times 15.15\)\(\upmu\)m in Figure 6a, and the diameter of design at 3.5 \(\upmu\)m for CHT after dry etching of active area deviated to an average of 3.82 \(\upmu\)m in Figure 6b. The cause of deviation may come from the over-etching of the undercut of the structure and error of tilt angle of SEM measurement. To investigate the absorption efficiency between our infrared thermopiles with SWS, thorough measurements for the output voltage of thermopiles with SWS were carried out. The setup of measurement was arranged as shown in Figure 7, consisting of a standard infrared radiation source and a modulated mechanical chopper system. The output signal of the thermopile is amplified with a chopper-amplifier AD8551 and the signal is delivered to a digital multi-meters (DMM).