# Research of Tri-State Optical Signal Detectors for Ternary Optical Computers
## 2 Materials and Methods
### Design of Three-State Optical Signal Detectors
#### 2.3.3 Layered Design of Tri-State Optical Signal Detector  
The hierarchical design idea for the tri-state optical signal detector is shown in Figure 7.  
The first layer is the light-sensitive layer. Each photosensitive sensor on the light-sensitive layer corresponds to the liquid crystal pixels of the optical processor and is mainly responsible for converting light signals into electrical signals. Considering the maintenance convenience and cost, we adopt the stitching idea proposed by [PERSON] [17]; that is,  
Figure 6: The 576-bit parallel decoder circuit.  
Figure 7: Layered design of the tri-state optical signal detector.  
16 photoreceptor circuits form a photoreceptor module with a small-scale integration degree, and then 36 photoreceptor modules are stitched together to form the whole photoreceptor layer. Therefore, if any component is damaged, you only need to replace the small module where the damaged component is located.  
The second layer is the voltage divider resistor layer; the purpose of this layer is to divide the current information obtained from the conversion of the photoreceptor layer and obtain the electrical signal corresponding to the light intensity information of the liquid crystal pixels. The third layer is the latch layer, where the latch-active LE and the output-active OE of the latch are connected in parallel and controlled by signals. After the LE receives a valid latch signal, the latch will simultaneously latch the electrical signal from the voltage divider resistor layer, and then output the latch \"1\" and \"0\" information after the OE receives a valid signal from the output. The fourth layer is the data conversion layer, the function of which is to convert the decoded raw data coming from the latch layer into the input of the optical encoder. If the decoding result is already finalized at this point, the final result is output directly to the electronic computer.  
Since the functions of the latch layer and data conversion layer can be performed by FPGA, the physical design of the three-state optical signal detector focuses on the first two layers. Considering the splicing problem, the two layers are subdivided into the photoreceptor layer, protective resistor layer, and voltage divider resistor layer, and the layers are connected by connectors, as shown in Figure 8.  
In Figure 8, the photoreceptor layer consists of 36 small photoreceptor modules, each of which is mounted to the protective resistive layer using pins. It should be noted that the photosensitive sensor on the photosensitive layer needs to be aligned with the liquid crystal pixels. The protective resistor layer and the voltage divider resistor layer are connected vertically, and there are more connection lines between the layers, so the connector used is a 288-pin memory slot. The memory slot is installed in the protective resistor layer, so the interface will be designed in the form of a memory stick when designing the voltage divider resistor layer. For subsequent installations, Figure 8 will be rotated 90 degrees counterclockwise for physical installations.