# Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices
## 2 Materials and Methods  
The system proposed is composed by N inverters connected in parallel as shown in Figure 1. The power section is based on the equivalent model presented in [38]. \(\overline{I_{1}}\), \(\overline{I_{2}}\) and \(\overline{I_{N}}\) are the output currents of the inverters, \(\overline{Z_{1}}\), \(\overline{Z_{2}}\) and \(\overline{Z_{N}}\) are the impedances of the units, \(\overline{Z_{0}}\) is the load impedance and \(\overline{V_{0}}\) is the load voltage. Each inverter module has its control logic (FPGA) and a BRIDGE module to convert the FPGA signal (0-3.3 V) to the output voltage (\(\pm\)300 V). The parallel connection of singular units could generate a circulating current that flows towards the inverters, due to the attempt to impose different voltages on the same output. To limit this current, a suitable control method, to be implemented on every single FPGA module, is proposed, to synchronize the inverter outputs. Comparators, implemented on the FPGAs, are introduced to detect if the module output current assumes values out of a predetermined range. If this situation occurs, an FPGA reset signal brings back to the  
Figure 1: Schematic of a general parallel-connected inverter system. ordinary operation by modifying the Pulse-Width Modulation (PWM) signal controlling the BRIDGE. The method just described implies the absence of intercommunication between the inverters differently from what has been seen in the literature, allowing the design of a scalable and easier system. Initially, to prove the validity of the approach, a simple structure with two inverters connected in parallel has been considered. The schematic of this structure is depicted in Figure 2. \(\overline{E_{1}}\) and \(\overline{E_{2}}\) are, respectively, the output voltages of the first inverter and the second inverter. As described in Figure 1, \(\overline{Z_{1}}\) and \(\overline{Z_{2}}\) are the impedances of the modules, \(\overline{Z_{0}}\) is the load impedance, \(\overline{I_{0}}\) is the load current and \(\overline{V_{0}}\) the load voltage. The simulated system includes 10 kW inverters, a 600 V DC-link and a PWM at frequency of 50 kHz. A unit line impedance with an inductive part of 250 nH and a resistive part of 1 m\(\Omega\) has been considered, together with an inductive load of a 1 mH in series with a resistance of 1 m\(\Omega\). In this paper, a Simulink model conceived to be exported via a Hardware Description Language (HDL) code to a vendor-independent code has been designed. A 100 MHz system clock frequency, usually implemented on medium-level FPGA boards (e.g., Xilinx Artix-7 XC7A100T FPGA), has been considered. After the simulation of the system composed of two inverters, a second set of simulations has been considered, extending the approach to a greater number of parallel-connected inverters. MATLAB and Simulink with Simscape and Stateflow add-ons have been used to simulate the system behavior and to develop the new control idea. MATLAB is a powerful tool that allows multidomain simulation, thanks to a vast variety of available tools. Simulink is a MATLAB-based graphical programming environment that is widely used for model-based design. In this work, Simulink has been utilized with Simscape, a MATLAB add-on employed to create models of physical systems. Specifically, Simscape Electrical provides component libraries for modelling and simulating electronic, mechantorics and electrical power systems. Stateflow is another important tool that is able to design and simulate Finite State Machine (FSM) and logical flowchart. All the MATLAB functions, Simulink models and Stateflow charts used in this work are compatible with HDL Coder (Hardware Description Language Coder), which allows for converting models in synthesizable VHDL and Verilog code automatically on an FPGA.