## 3 Prototyping of the Proposed CAPT Framework
### Optimizations
\begin{table}
\begin{tabular}{l l l l} \hline \hline
**RTL Ports** & **I/O** & **Bits** & **Protocol** \\ \hline \(\ldots\) & & & \\ \hline \(x\_\{1,2,\ldots,D_{\text{opt}}\}\_ADDRESS\) & O & \(2^{\text{\#}}\) (\(\text{\#}\in\mathbb{N}^{+}\)) & ap\_memory \\ \(x\_\{1,2,\ldots,D_{\text{opt}}\}\_\) & O & 1 & ap\_memory \\ \(x\_\{1,2,\ldots,D_{\text{opt}}\}\_\) & I & 32 & ap\_memory \\ \hline \(W1\_\{1,2,\ldots,D_{\text{opt}}\}\_ADDRESS\) & O & \(2^{\text{\#}+6}\) (\(\text{\#}\in\mathbb{N}^{+}\)) & ap\_memory \\ \(W1\_\{1,2,\ldots,D_{\text{opt}}\}\_\) & O & 1 & ap\_memory \\ \(W1\_\{1,2,\ldots,D_{\text{opt}}\}\_\) & I & 32 & ap\_memory \\ \hline \(\ldots\) & & & \\ \hline \hline \end{tabular}
\end{table} 
Table 2: \(x\) and \(W1\) ports of the optimized CAPT IP core: \(D_{\text{opt}}\) is the optimization depth index. Algorithm 4, and the new loop control is shown in Figure 4, whose size is reduced from 13 down to 9 states. We insert the \"pipeline\" directives into the loops of the optimized code (see Lines 6 and 13 of Algorithm 4) in order to accelerate the iterations. Finally, the code of Algorithm 4 is optimized at the instruction level depending on the symbolic expression manipulation strategies presented in [52]. In the original C++ code, the iterations of Line 5 have dependent relationships between each other, so they cannot be parallelized only via loop unroll. We therefore partially unroll the loops with a factor of \(D_{\text{opt}}\), and then re-specify the iteration information and body manually. As shown in Lines 5-10 of Algorithm 4, the loop body is repeated \(D_{\text{opt}}\) times during each iteration, and the iteration number is reduced by \(D_{\text{opt}}\) accordingly. The body operations are described in polynomial form:  
\[\mathbf{h1}=\sum_{k=i\times D_{\text{opt}}}^{(i+1)\times D_{\text{opt}}-1}\mathbf{x}(k )\times\mathbf{W1}(i,k) \tag{12}\]  
The re-specified code avoids the dependence between the loops, enabling parallelization of the operation schedule. Figure 5 compares the original and optimized loop body operation schedules at \(D_{\text{opt}}=4\). Despite higher hardware resource consumption, the optimizations achieve a speedup of 2.67\(\times\). It should be noted that in Figure 5, the time-cycle consumptions of each operation are equal, but the realities are not. The operators available for different devices are usually  
Figure 4: Diagram of the finite state machine of the optimized implementation: \(S*\) is the state of identification, \(L*\) is the line number of Algorithm 4, \(n=n1+n2\) and \(m\) are the iteration numbers. Figure 5: Comparison of the original and optimized loop body operation schedule at \(D_{\text{opt}}=4\). different. The speedup gain of this case \(G_{\text{opt}}\) is therefore formulated as the running time ratio of the original and optimized implementations:  
\[G_{\text{opt}}=\frac{T_{\text{ori}}}{T_{\text{opt}}} \tag{13}\]  
with  
\[ \begin{split}& T_{\text{ori}}=D_{\text{opt}}\times(T_{\text{RD}}+T_{ \text{FMUL}}+T_{\text{FADD}}+T_{\text{WR}})+T_{\text{ori}}^{\text{ctrl}}(D_{ \text{opt}})\\ & T_{\text{opt}}=T_{\text{RD}}+T_{\text{FMUL}}+(\log_{2}D_{\text{ opt}}+1)\times T_{\text{FADD}}+T_{\text{WR}}+T_{\text{opt}}^{\text{ctrl}}(D_{ \text{opt}})\end{split}  \tag{14}\]  
where \(T_{*}\) is the time cost of the operator \(*=\text{RD},\text{FMUL},\text{FADD}\) or WR (see Figure 5). \(T_{\text{ori}}^{\text{ctrl}}\) and \(T_{\text{opt}}^{\text{ctrl}}\) return the time cost values due to control operations of the original and optimized implementations at different \(D_{\text{opt}}\), respectively. The consumptions of the \(p\)-th device element for the optimized implementation are estimated as  
\[C_{\text{opt}}^{p}=\sum_{i=1}^{N_{\text{ope}}}C_{i}^{p} \tag{15}\]  
where \(N_{\text{ope}}\) is the operator number and \(C_{i}^{p}\) is the consumptions of the \(p\)-th element for the \(i\)-th operator. The final goal of this optimization is to maximize \(G_{\text{opt}}\) with resource constraints:  
\[