# Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection
## 2 Silicon Photonics for High-Speed Data Communications
### Silicon Photonics
By applying the same approaches presented in [49], low-loss photonic devices including waveguides, couplers, micro-ring modulators, and PDs can be successfully integrated with minimal modifications to the original CMOS process. Moreover, based on the micro-ring structures, 9-wavelength TX and RX DWDM macros are also realized as shown  
Figure 8: Block diagram of memory-processor optical link realized in [48]. Figure 9: Cross-section of photonic and electronic devices [49]. in Figure 10. The TX employs an internal pseudorandom binary sequence generator, a serializer, and a modulator driver, enabling electro-optic conversion by the carrier-depletion micro-ring modulator. At the RX side, a polysilicon-based PD utilizing absorption from defect states, combined with the resonant structure, provides an acceptable responsivity of 0.2 A/W. Similarly, the PD splitting technique in [46] is also employed to mitigate the timing margin. After the DDR-based receiver front-end, the data is further deserialized for the estimation of BER. In order to achieve a stable wavelength locking of the DWDM system, a heater and a digital logic controlling the heater are also implemented. Consequently, for a total aggregate data rate of 45 Gb/s, a 9-wavelength DWDM link sharing a single bus waveguide is successfully demonstrated. Silicon photonics based on bulk-Si substrate is also an attractive option for processor-memory interfaces, especially for cost-sensitive dynamic random-access memory (DRAM) applications [51]. Processor-memory interfaces are currently facing two challenging industrial requirements. The first requirement is the demand for higher bandwidth, according to which the next-generation DRAM (DDR5) standard requires the maximum per-pin data rate of 6.4 Gb/s. The other requirement is that the total memory capacity that a memory controller can handle should be maximized. However, the existing schemes, such as the multi-drop bus topology or the point-to-point bus topology, cannot satisfy the aforementioned requirements simultaneously. Fortunately, if an optical interconnection is applied to the multi-drop bus interface, the per-pin data rate can be increased significantly without degrading the total available memory capacity. The CMOS SOI platform can never be adopted in the DRAM interfaces where cost is a crucial factor. Samsung has presented several works based on the bulk-Si platform, which is different from the platform in [50] mainly in terms of waveguide-fabrication techniques. The schematic view of integrated EPICs is shown in Figure 11. Unlike in [50], the waveguides are formed through a local crystallization based on epitaxy. For that purpose, a trench is formed first and filled with silicon dioxide. Subsequently, amorphous silicon (a-Si) is deposited using LPCVD. After the deposition, a-Si is crystallized by solid-phase epitaxy (SPE) using the bulk-Si substrate near the edges of the trench as a crystal seed, thereby growing the crystal laterally toward the center of the trench. Finally, the waveguide is patterned using dry etching. Owing to the introduction of epitaxy, a higher quality of crystallization as compared with the previous works is obtained, exhibiting a waveguide loss of only 3 dB/cm. A further improvement can be achieved using a laser-induced epitaxial growth based on the liquid phase epitaxy method, resulting in an almost perfect crystallization, so that the grain size is comparable to that of the bulk Si. Using the waveguides formed by the SPE method, both the MZI and the micro-ring modulators are realized. Two types of PDs are also implemented by introducing Ge on Si: a surface-illumination type and a butt-coupled-waveguide type. Although the photonic devices alone exhibited good performance, overall performance degradation is observed when integrating the EIC and the PIC together with the combined process, which needs to be improved through process optimizations. Figure 10: Monolithically integrated DWDM optical link in bulk CMOS [50].