# A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications
## 4 The Proposed Fully Digital BPSK Demodulator  
The Binary Phase Shift Keying (BPSK) is the most famous PSK modulation, and the most widely adopted method to recover data from a BPSK signal is the Costas loop for coherent modulation schemes [36]. As explained in the Ref. [25], the above-cited loop consists of two parallel phase-locked loops (PLLs), where one is called the _in-phase loop_, _IPL_, and  
Figure 4: The experimental measurements setup used, including ballistic gel for the encapsulation of the two piezoelectric transducers. Figure 5: (**a**) The piezoelectric device, (**b**) BDV model with two resonance doublets, and (**c**) its equivalent Théveenin model assuming electric resonant conditions. Figure 3: TX-PZT and RX-PZT encapsulated in ballistic gel at a distance of about 1.0 cm and the RX-PZT device compared to a 10 cent coin. the other is called the _quadrature-phase loop, QPL_. Their phase error outputs are multiplied to control the frequency of the oscillator. The square term of the data stream makes the control signal proportional to the phase difference as the conventional PLL and, in the locked state, the output at the in-phase branch becomes the demodulated signal. Generally, a four-quadrant analog multiplier is adopted to realize the I/Q arm phase detector and the multiplier in the voltage-controlled oscillator (VCO) branch. Such complexity in terms of the needed circuitry constitutes the main drawback of the conventional _Costas loops_ for BPSK demodulators, limiting its use in practical applications. On the other hand, recent works have exploited digital architectures for BPSK demodulation [26; 28; 30; 31]. Many schemes have adopted a 1-bit Analog-to-Digital Converter (ADC) implemented with Schmitt's Triggers, a clock-recovery circuit and D-Flip-Flops (DFFs) whose role is as frequency dividers or as counters. However, it is important to underline that most of them present a _non-coherent_ demodulation scheme, since phase synchronization is not required with the source of the modulated signal. The system proposed in this paper falls within the last family. Figure 6 shows the simplified block diagram of the whole BPSK demodulator and its working principle is explained in the following, with the help of the timing diagram reported in Figure 7.  
1. The two input sinusoidal waves that come out from the _RX-PIEZO_ are firstly clamped out, and, consequently, they degenerate two semi-square waveform signals, namely \(V_{AC1,2}\), in Figure 6. When the phase modulation occurs, one of the two phases will present a doubled time duration. In this paper, just the negative sine phase, \(V_{AC2}\), is taken into account as the incoming modulation signal is high (i.e., _MOD_ in Equation (1) is high). 2. A non-overlapping phase generator is strongly required, since it allows to better separate and distinguish, from a temporal point of view, the two clamped-sine incoming phases and to detect the bit-start/end signals. Moreover, its output, \(V_{P2}\), is the resulting modulating phase. 3. A current-starved ring oscillator starts oscillating just when the enabling phase (\(V_{P2}\)) is high. 4. The core of the proposed demodulator is constituted by a 2-bit frequency divider and a CMOS XOR gate which allows to count the number of pulses generated by the ring oscillator, when enabled by \(V_{P2}\). Briefly, the changes in the output bit state happen when a doubling on the number of pulses of the oscillator occurs (i.e., two clock pulses are generated when _MOD_ goes high and, vice-versa, a single clock pulse when no modulation occurs). In such event, the two output states \(Q_{0}\) and \(Q_{1}\) will present different time durations, and this difference will be detected by the XOR gate. 5. The pulses generated by the XOR gate, \(XOR_{out}\), which are slightly delayed as indicated \(\Delta t\) in Figure 7, allows the reconstruction of the bit '1' from the modulator.