# Machine Learning Based Energy-Efficient Design Approach for Interconnects in Circuits and Systems
## 1 Introduction  
The emergence of the Internet of Things (IoT) demands low-power circuits to perform on-device data processing [1]. Hence, the IoT applications expect energy-efficient solutions at all design levels. On the hardware level, the interconnect acts as the communication channel between circuits that also consumes power. A typical data transmission that system includes driver, receiver, and interconnect is shown in Figure 1 below. Figure 1: Off-chip interconnect in a transceiver circuit. While most effort has been concentrated on the on-chip circuit and interconnects' optimization [2; 3; 4; 5; 6; 7; 8], the energy-aware off-chip interconnect optimization in the transceiver circuit has not been investigated thoroughly so far [9; 10]. The authors in [2; 3; 4] focused on energy-efficient on-chip interconnect design. The approach in [2] lessens power consumption based on an adaptive voltage scheme while the authors in [3; 4] proposed a design framework that models and optimizes the energy-efficient on-chip interconnect. On the other hand, authors in [5; 6; 7; 8] attempt to reduce power consumption by advanced circuit techniques. While the authors in [5; 6] diminish the power consumption by an efficient pre-emphasis transmitter, the proposed approach in [7] minimizes the power consumption by reducing voltage swing with a low-power forward error correction architecture. The authors in [8] suggest power analysis and optimization by trading off transmitter voltage swing and receiver gain. These works mentioned above attempt to reduce the transmitter voltage swing without considering its impact on the interconnect leading to two main drawbacks. Firstly, the interconnect has parasitic resistance and capacitance which play a significant role in power dissipation. Secondly, voltage swing reduction at the transmitter due to the signal loss and crosstalk always degrades the receiver signal quality at the receiver. On the other hand, the authors in [9; 10] are concerned with energy-efficiency evaluation for the off-chip interconnect, while the approach in [9] proposes an energy-aware analysis with analytical formulas using frequency-domain information. The authors in [10] provide a more comprehensive methodology to evaluate the energy efficiency of the I/O links. However, these works with the conventional design procedure lack an efficient methodology to investigate the immense design space thoroughly. Although the channel in these works is efficiently modeled by analytical approaches proposed in [11; 12], these approaches have difficulties modeling the complicated structures. The hardware design procedure including the interconnect design is an iterative process in a human manner. Recently, the rise of machine learning techniques exhibits the hope for an efficient design approach. Hence, many works focus on applying machine learning techniques to improve design efficiency. The approach in [13] proposes a fast and accurate high-speed channel modeling using an artificial neural network (ANN). Moreover, the genetic algorithm (GA) is utilized to optimize the design. However, this work employs the W-element model for the lossy multi-conductor extracted from the 2-D EM simulator. Hence, it may be inapplicable to the complex structure that requires 3-D EM simulation. Alternatively, the proposed approach in [14] predicts eye height and eye width based on the ANN model trained by S-parameter in frequency-domain. This approach provides a fast alternative solution in the time-domain. An extension of this approach in [15] illustrates general applicability with complex numerical examples. Furthermore, the authors in [15] demonstrates the superior of ANN by a comprehensive comparison. The authors in [16] enhance the ANN model performance in [15] with feature selection algorithms described in [17; 18]. On the other hand, the authors in [19] use the ANN model to model crosstalk in high-speed transmission lines.