# Elliptic-Curve Crypto Processor for RFID Applications
## 2 Preliminaries
### PM Computation over \(Gf(2^{M})\)
As far as the latency is concerned, the architectures of [23; 25] require 23.91 (ratio of 110 over 4.60) and 5.32 (ratio of 24.5 over 4.60) times higher computation time as compared to this work. The FPGA slices reported in [25] are 4.90 (ratio of 3122 over 637) times higher as compared to our architecture. When comparing FPGA slices to [23], the proposed accelerator utilizes 1.34 (ratio of 637 over 473) times more hardware resources as we have used three additional shift buffers. There is always a trade-off between computation time and area. **Comparison over Virtex-7 implementations [18; 24; 26]:** The required clock cycles as reported in a 2-stage pipelined architecture in [18] is 1.50 (ratio of 3960 over 2627) times higher as compared to this work. The power comparison is not possible. Similarly, the comparison over clock cycles and power is not possible with [24; 26] as this information is not available (see Table 2). Our architecture is 2.46 (ratio of 909 over 369), 2.37 (ratio of 909 over 383) and 2.28 (ratio of 909 over 397) times faster in terms of clock frequency as compared to the solutions that are described in [18; 24; 26], respectively. Moreover, the architectures of [18; 24; 26] require 3.71 (ratio of 10.7 over 2.88), 3.43 (ratio of 9.9 over 2.88) and 3.64 (ratio of 10.5 over 2.88) times higher computation time as compared to our architecture. For comparing the hardware resources, the 2-stage pipelined architecture of [18] utilizes 4.93 (ratio of 2207 over 447) times higher FPGA slices in comparison to this work. This is due to the use of a bit-serial FF multiplier in the datapath of the proposed architecture while a digit-parallel with digit size of 32-bit multiplier architecture is incorporated in [18]. Similar to [18], another 2-stage pipelined architecture is published in [24] where a digit-parallel multiplier with a digit size of 41-bit is employed in the datapath to reduce the required clock cycles. Consequently, a digit-parallel multiplier results 2.33 (ratio of 4162 over 1786) times higher hardware resources in terms of FPGA LUTs as compared to the bit-serial multiplier in the proposed architecture. An optimized PM accelerator architecture for \(\frac{throughput}{area}\) is described in [26] where a digit-serial multiplier is used to reduce hardware resources and clock cycles. Therefore, the architecture of [26] utilizes 2.64 (ratio of 4721 over 1786) times higher hardware resources in terms of FPGA LUTs as compared to this work. ## 5 Conclusions

This article has proposed a low-latency and low-area Elliptic-curve crypto processor architecture for an efficient use in RFID applications. The low-latency has been achieved by reducing the number of clock cycles in the datapath for loading the Elliptic-curve parameters. Furthermore, the same size of input/output interfaces has been used in other blocks of the architecture. The low area is preserved by using the same hardware resources for the squarer and multiplier operators. The proposed architecture has been validated by implementing it in state-of-the-art 7-series FPGA devices, i.e., Kintex-7, Artix-7, and Virtex-7. The obtained results indicate that the proposed accelerator utilizes 1789 LUTs and 1855 FFs in each of the Kintex-7, Artix-7 and Virtex-7 FPGA devices. However, differences in the achieved clock frequency, latency and power consumption have been recorded. For example, the achieved clock frequency and time to perform one PM operation on Kintex-7 and Virtex-7 are found to be 909 MHz and 2.88 \(\upmu\)s, respectively. However, the achieved clock frequency and latency on Artix-7 FPGA are 769 MHz and 3.41 \(\upmu\)s. From the power perspective, 647 \(\upmu\)W is achieved on Kintex-7 and Artix-7 FPGA devices while on a Virtex-7 FPGA, the achieved value is 733 \(\upmu\)W.

Conceptualization, S.Z.K. and M.R. ; data extraction, S.Z.K. and S.S.J. ; results compilation, M.R. and A.R.A. and A.A.; validation, M.R. and M.I. ; writing--original draft preparation, M.R. ; critical review, M.R. and S.Z.K. ; draft optimization, M.R. ; supervision, S.S.J.