# Multiple-Valued Logic Modelling for Agents Controlled via Optical Networks
## 3 Results
### Computing Aspects of AGA Functions
A further example is shown for the shortest designed versions of MIN, MAX operators possible, only without external memory addressing. **Fragments of the program for calculationof MAX(x,y) or MIN(x,y) in MC2**  
MINIMUM (#N1,#N2):  
chose smaller of two values  
INPUT  
#N1 \(\leftarrow\) Natural number  
#N2 \(\leftarrow\) Natural number  
MOV A,#N1  
MOV R7,#N2  
CLR C  
SUBB A,R7  
JNC MIN_N2  
JNC MAX_N1  
MOV R0,#N1  
MOV R0,#N2  
SJMP NEXT  
MIN_N2:MOV R0,#N2  
MAX_N1:MOV R0,#N1  
NEXT  
NEXT  
Results of microassembler modeling. * Microassembler 8-bit modeling of MVL operators and functions does not detect any additional problems in comparison with traditional microcontroller applications such as step motors or control or sensors, but the choice of agent architecture influences greatly on the time response and clocking. It should be chosen before the full-scale modeling of agent interaction;
* For test circuit board shown above, the calculation of basic operators for AGA function is slow enough as, e.g., \(k\ =\ 256\) truth levels \(n\ =\ 30\) variables the calculation will need \(\approx 210,000\) work cycles, which responds to 0.1 s at 24 MHz, as minimally possible parameters are \(\text{t}_{\text{MIN-MAX}}\approx 4\ \upmu\text{s}\) and \(\text{t}_{\text{Literal}}\approx 9\ \upmu\text{s}\). However, addressing of external memory devices can additionally enlarge the number of cycles, at least for \(\approx\)20-25%. That complicates the design of the universal PC's program for interaction with the hardware agent;
* FPGA, at for example 500 MHz, are more appropriate for practical work with AGA, as due to [88] its typical work cycle responds to four clocking cycles and calculations of the AGA function will take \[t\ =\ N_{truth\ levels}\cdot 4T_{work\ cycle}\cdot N_{operators\ MIN\&MAX}\] (13) and can be lowered to the \(\sim\)ms scale appropriate for real technical tasks. However, parallel schemes of AGA calculations are not investigated for such platforms. * In order to solve the problem of non-compatibility of instructions for computer and microcontroller platforms using the AGA logic ledger, a modern RISC-V platform [89] with open code seems to be the possible solution, as it proposes universal short instructions for devices with different throughput. For further conjugation of microassembler and PC procedures in MASs, one can use as the base the program for the computing of the AGA function given in C language, which was published as a supplement to the recent paper [30]. As for C++, since the standard ANSI C [90] does not define library functions corresponding to operators \(MAX(x,y)\) and \(MIN(x,y)\), then for the prototype stdlib.h traditional cycles or macro, \(max(\ )\) and \(min(\ )\) can be used for calculations of these operators. The program's main \(\{\ \dots\ \}\) part should then use instructions such as:  
_printf \"max/min of \(x\), \(y\) is %d\(\backslash n\)\", max/min \((x,y)\));_  
_return 0;_  
For such a design, the final architecture of the hardware agent should be chosen, as the data exchange in the distributed scheme directly emulating procedures for the proposed logic ledger will need high-capacity external memory chips, substantially modifying time response estimations.