## 3 Circuit Level Perspectives of JCRS RF Hardware
### Front-Ends
More details about the power, sensitivity, and operation modes are given in Section 4. In terms of front-end architecture, previous works [27; 28; 29] showed initial promising results, even though a unified framework for joint hardware usage will require a crisper definition of applications and related KPIs. [PERSON]. [27] utilized a FMCW radar front-end focusing primarily on radar KPIs and utilized the same radar for communication operations. [PERSON]. [28] used a common front-end with a novel radar-communication modulation scheme. Ref. [29] proposed a reconfigurable approach with a switched architecture. The front-end can act as a radar or communication front-end depending on the inputs to the receiver mixer from the transmitted signal via a splitter or directly from PLL. Such a reconfigurable architecture could be a key to hardware reuse if the individual blocks can also be made dual/multi-mode. Such an architecture is shown in Figure 5. However, additional switches or the inclusion of programmability may impact the performance, power, and area for the front-end chains, necessitating new ideas to build reconfigurable JCRS front-ends with impacting operations. Apart from the differences in working principles, there are differences in technology for communication and radar chipsets. In the last few decades, several communication systems have moved to complementary metal oxide semiconductors (CMOS) for the implementation of front-ends to address the baseband processing needs. Apart from bulk CMOS processes, in recent years, there have been significant development in fully depleted silicon-on-insulator (FDSOI) processes [30]. III-V semiconductor processes such as GaAs for realizing the power amplifiers are still used but have been replaced by CMOS power  
Figure 5: A representative reconfigurable JCRS front-end (short forms as defined in Figure 3). amplifiers in recent years. However, given the output power requirements and relatively simpler baseband processing needs, radar chipsets are not limited to CMOS. They can use GaAs process or Silicon Germanium (SiGe) heterojunction bipolar transistor (HBT) processes. A recent work [31] showed promising results in GaN for mmWave operations of radars and communications. However, cost plays a role in the choice of technology, while considering mass volume production. However, these gaps also reduce depending on whether on-package multi-chip architecture is used at mmWave with front-ends in one process and baseband in another process, as mentioned in [32]. The good news is that the front-end hardware will not be a bottleneck, as in the last decade, there has been a significant development in front-ends and BFs to support mmWave bands by academia and industry. For instance, wireless backhaul applications utilize the mmWave spectrum for communications. Similarly, 60 GHz bands have already been used for gesture recognition [33; 34]. The 60 GHz bands already have communication front-ends with BF capabilities [15]. Beyond 60 GHz bands, the 110-140 GHz frequency range [19] has also been identified for potential JCRS hardware. There are already several academic and industrial works in this range for radar [16; 35] and communications [36; 37; 38]. The potential usage of advanced nodes of CMOS (40 nm or below) for mmWave applications [17] and other processes for high performance devices (e.g., SiGe BiCMOS [16]) will ease the realization of low-cost JCRS hardware front-ends. There will still be challenges to solve in order to create a compact power-efficient hardware to support JCRS applications that are intended to enable tactile internet [39] and future consumer needs. In addition, antenna isolation may play an important role with reconfigurable front-ends in order to manage self-interference cancellation (SIC). The methods to achieve antenna isolation are covered in Section 3.2.