# Atomic Layer Deposition (ALD) of Metal Gates for CMOS
## 1 Introduction
### Metal Gate for FinFETs and GAA-FETs  
Gate leakage is not the only issue relative to the dimension scaling. Compared to a long channel MOSFET, the shrinking of channel length will reduce the gate control ability [46; 47; 48]. First, the current at \(V_{g}<V_{t}\) (subthreshold leakage) will increase along with the gate length shrinking, inducing so-called subthreshold swing, _SS_. Second, for short channel devices, \(V_{t}\) is also a function of the voltage between drain and source, \(V_{DS}\), certain charges are depleted by the \(V_{DS}\). As a result, the gate voltage required to form the channel is lowered by \(V_{DS}\). This is called drain induced barrier lowering (DIBL). Third, for short channel devices, the potential of source and drain will also impact the channel, making the channel formation at lower \(V_{t}\). The shorter is the channel, the smaller is the \(V_{t}\). This is referred to as \(V_{t}\) roll-off. All these short channel effects could be suppressed by changing the device structure from planar MOSFETs to FinFETs [49] and gate-all-around (GAA) FETs [50]. The FinFETs have become the mainstream logic devices for a few nodes [51]. The GAA nano-Si wire FETs and Si nano-sheets FETs have been reported by the research teams using industrial processing facility [52; 53; 54; 55; 56; 57]. The relation between \(V_{t}\) and the work function of the gate electrode for FinFETs with undoped channel is different to that for the planar MOSFETs. For planar devices, there are plenty of charges to form inversion. For undoped FinFETs, much less charges are available. As a result, an additional surface potential needed to reach the \(V_{t}\). [PERSON] summarized the relation of the \(V_{t}\) and work function of the gate electrode for low-power and high performance planar MOSFET and FinFETs in a schematically way as in Figure 9 [58]. The points in the top and bottom green rectangles give the \(V_{t}\) requirement of different low power devices and high performance devices, respectively. The points in the rectangle with yellow color give the work function requirement of bulk planer NMOSFETs and PMOSFETs. The points in the triangle give the work function requirement of FinFETs. For low power FinFETs, a metal with a work function of 4.6 eV in the midgap of Si can meet the requirement for both n-type and p-type devices. High performance devices desire low threshold, and thus two metals with work functions near the edges of the conduction band and valence band of Si are needed. Different from the metal gates for the planar CMOSFETs, which needs two metals with work functions 0.4 eV from the midgap, those for the FinFETs can use metals with work functions 0.2 eV from the midgap. The work function values of FinFET are about 4.4 eV and 4.85 eV for N metal and P metal respectively, while the values are about 4.2 eV and 5.0 eV for planar CMOSFETs. [PERSON] et al. [59] gave the other specifications include \(V_{t}\) stability (\(\sim\pm 10\) mV of unstressed film), Mobility \(\geq 95\%\) of that achieved with SiO\({}_{2}\), density of interface traps (D\({}_{\rm{it}}\)) \(\leq 5\times 10^{10}\) cm\({}^{-2}\)-eV, high frequency (100 kHz) CV hysteresis \(\leq 10\) mV, Reliability comparable to Poly-Si/SiO\({}_{2}\), and thickness uniformity (3 sigma) \(\leq 4\%\). For FinFETs and GAA FETs, the conformality of the metal gate is a new challenge. In a planar device, the metal film could be deposited top-down by sputtering. For FinFETs, it is very difficult to form conformal film on sidewall of the Fins using these anisotropic deposition techniques. CVD technique has much better isotropy than PVD and is most likely able to meet the requirement of FinFETs. For GAA FETs, however, both PVD and CVD will be phased out from the deposition of gate layers, replaced by ALD.