## 1 Introduction  
Digital control in dc-dc converters is of interest because its many potential advantages such as low power consumption and flexibility to program and design advanced control strategies to improve the system performance [1; 2; 3]. Therefore, the digital closed-loop configuration is increasingly being used in dc-dc converters [4; 5; 6]. Digital control depicts an important element of power converters for renewable energy systems [7], automobile industry [8], and industrial applications [9]. However, many works report disadvantageous quantization effects related to the existence of limit cycles in digitally controlled pulse width modulation (DPWM) converters. Static and dynamic models taking into account the quantization effects are derived and used to explain the origins of limit-cycle oscillations (LCO) for voltage single-loop digital control in [10; 11]. A DPWM resolution lower than ADC resolution usually causes LCO that affects the regulation of the controlled variable [12]. Therefore, DPWM with resolution higher than the ADC is usually implemented in order to reduce the effect of limit-cycle oscillations in voltage single-loop digital control, where the difference between the voltage reference and the output voltage is quantized to a digital number to represent the error signal [13; 14]. It is well known that cascade control of dc-dc converters generally offers better performance than single-loop control [15; 16]. Moreover, current control strategies are always needed to connect in parallel some converters to increase power management. Therefore, two-loop digital control structures have been extensively applied last teen years [17; 18; 19; 20; 21]. Analysis of LCO are given in [22; 23; 24] for digital current mode control. In these works, the resolution of the DPWM is also greater than the ADC resolution in the outer voltage loop. In [22], an estimation algorithm has been applied to the average current control of a buck converter in order to reduce quantization effects in the inductor current loop and, consequently, the presence of limit cycle oscillations. A method to design a two-loop digital control is developed in [23], where the current reference is dynamically adjusted to give a solution to the LCO problem. A technique to compute the steady-state duty cycle in real-time was considered in [24], where a time-to-digital converter translates the duty ratio information into a digital code using a moving average filter and an adjustable current loop sampling frequency. At steady-state, the strategy disables the current-loop sampling and the control computation. Then, a virtual open loop configuration is used to reduce oscillations of the inductor current. In order to improve the resolution of the DPWM in single-loop digital voltage controllers, some authors use sigma-delta modulation to eliminate the quantization noise and the LCO. In [12], a non-zero error method is used to encode the output voltage error improving the low resolution of the DPWM. A sigma delta modulation scheme and switching frequency modulation strategy are combined in [25] to increase the effective resolution of the DPWM. Nonetheless, there are not reported works that show the effects of quantization in dc-dc converter with a two-loop digital control having an integral term of its output voltage error. This paper presents design conditions to avoid the effects of the quantization in two-loop current controlled dc-dc switching converter. LCOs conditions presented in [10] are extended to a two-loop digital control in order to obtain restrictions associated with the gains of the control laws and the quantization resolution for each control loop. When the condition proposed for the external loop is fulfilled, simulation and experimental results verify that the QIP are suppressed from the current signals. Section 2 presents the conditions for each digital loop to observe the two-loop quantization effects. Section 3 describes the implementation of the digitally controlled buck-boost converter in order to validate the restrictions.