## 2 Background
### Schoolbook Strategy
\begin{table}
\begin{tabular}{l l l l l l} \hline \hline  & \multicolumn{2}{c}{**Area Utilization**} & \multicolumn{2}{c}{**Timing Details**} & \multicolumn{2}{c}{**Power Results**} \\ \cline{2-5}
**Operand Sizes (\(j\times k\))** & \multicolumn{1}{c}{**Slices/LUTs/FFs**} & \multicolumn{1}{c}{**CCs**} & \begin{tabular}{c} **Freq** \\ **(MHz)** \\ \end{tabular} & \
\begin{tabular}{c} **Lat** \\ **(\upmu\text{s})** \\ \end{tabular} &
\begin{tabular}{c} **D/S/TP** \\ **(mW)** \\ \end{tabular} \\ \hline \multicolumn{5}{l}{Operand sizes in powers of 2} \\ \hline
16 \(\times\) 16 & 28/70/82 & 8 & 666 & 0.011 & 17/323/340 \\
32 \(\times\) 32 & 63/134/163 & 16 & 645 & 0.024 & 30/323/353 \\
64 \(\times\) 64 & 104/260/323 & 32 & 617 & 0.051 & 59/323/382 \\
128 \(\times\) 128 & 195/522/649 & 64 & 591 & 0.108 & 114/324/437 \\
256 \(\times\) 256 & 358/910/1295 & 128 & 578 & 0.221 & 177/324/502 \\
512 \(\times\) 512 & 624/1819/2584 & 256 & 552 & 0.463 & 340/325/666 \\
1024 \(\times\) 1024 & 1434/2602/5167 & 512 & 523 & 0.977 & 600/327/927 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Results on Xilinx Virtex-7 device. CCs: clock cycles; Freq: operating frequency; Lat: latency or computation time; D and S: dynamic and static powers; TP: total power consumption of the Booth accelerator. #### 4.1.1 Booth Designs for Operand Sizes in Powers of Two

The trend in powers of 2 shows that with the increase in the operand size from 16 \(\times\) 16 to 1024 \(\times\) 1024, there is an increase in the slices, LUTs, and utilized FFs. This is evident in columns two to four of Table 1. The reason behind this is that the implemented Booth multiplier uses the four registers of _Reg-A_, _Reg-a_, _Reg-b_, and _Reg-c_. Our Booth accelerator is parameterized so that designers can target different operand lengths. Therefore, the increase in the operand sizes also increases the lengths of the four registers in our Booth accelerator and consequently leads to an increase in overall hardware resources. In addition to the hardware resources, column five reveals that when the operand lengths increase, the clock cycles for polynomial multiplication also increase. On the other hand, the operating frequency decreases with the increase in the operand size, as shown in column six of Table 1. As mentioned in this article, latency is a ratio of clock cycles with the circuit frequency; therefore, the increase in the operand size also increases the latency. For example, the required computation time or latency for a 16 \(\times\) 16 Booth implementation is 0.0119 \(\upmu\)s, while for the maximum considered operand size of 1024 \(\times\) 1024, this value goes up to 0.9779 \(\upmu\)s. This increase in computation time is 82.17 (ratio of 0.9779 with 0.119) times the 16 \(\times\) 16-implemented Booth design, and is expected as the operand size also increases. The power consumption of the implemented Booth multiplier also increases with the increase in the operand size, as presented in the last three columns of Table 1.

We provided throughput and throughput/area results of the parameterized Booth multiplier (only for operand sizes of powers of two) in Figure 3a and Figure 3b, respectively. We calculated throughput using Equation (3). Similarly, we computed throughput/area using Equation (4), using slices as area metrics. Note that it is also possible to use LUTs or FFs as an area for evaluation instead of slices. Therefore, Figure 3a,b show an exponential decrease in throughput and throughput/slices with increased operand length. These figures reveal that for shorter operand sizes of 16 \(\times\) 16 and 32 \(\times\) 32, the values for throughput and throughput/slices ratio are better with larger operand sizes such as 512 \(\times\) 512 and 1024 \(\times\) 1024. \[ \begin{split} Throughput\ =\ \frac{1}{Latency\ (\upmu)}\ =\ \frac{10^{6}}{Latency} \end{split}  \tag{3}\]

\[ \begin{split}\frac{Throughput}{Area}\ =\ \frac{Throughput}{Slices} \end{split}  \tag{4}\]