## 3 Circuit Implementation
### Cascade PA Power Cell  
IEEE 802.11 ax employs 1024 QAM modulation to boost data rate, which imposes stringent linearity requirements on power amplifiers. As a result, power amplifiers for WLAN applications are usually biased to Class AB to take a balance between linearity and efficiency. CMOS PAs usually use cascode devices to provide high output power and enhance reliability. In this design, PA needs to deliver an average power of 17 dBm for a 802.11 ax signal. Considering at least 10 dB PAPR (peak-to-average ratio) of the signal, the transistor sizes of the common source and common gate devices are set to 2.56 mm/100 nm and 4.8 mm/500 nm, respectively, so the PA can ideally deliver a maximum output power of 29 dBm under a 3.3 V supply.  
Figure 14: The complete schematic of the proposed power amplifier.  
Figure 13: S-parameter comparison with fixed transformer. (**a**) Same \(C_{inp}\). (**b**) Larger \(C_{inp}\) in fixed transformer.  
To reduce the distortion of the PA, we analyze the cause of the distortions. The most significant source of nonlinearity in power amplifiers arises from the drain current. In general, the drain current of transistors can be expressed by the power series and represented as  
\[i_{d}=g_{m}V_{gs}+g_{d}V_{ds}+g_{m2}V_{gs}^{2}+g_{d2}V_{ds}^{2}+g_{md}V_{gs}V_{ds}+ g_{m3}V_{gs}^{3}+\cdots \tag{13}\]  
The \(g\) terms represent the transconductance, drain conductance, and cross terms. In modern communication systems, nonlinear distortion is usually studied using a two-tone signal test. For simplicity, higher order nonlinearities are ignored. In addition, assuming that the optimum load impedance is a pure real value at the fundamental frequency due to the resonance of the imaginary part, the nonlinear lower and upper IM3 sof the output voltage can be derived and simplified as  
\[V_{ds}(2\omega_{2}-\omega_{1}) \approx R_{L}(\omega_{L})\Big{[}\tfrac{3}{4}g_{m3}A^{3}+\tfrac{1}{2}Z_{L}( \omega_{2}-\omega_{1})g_{m2}g_{md}A^{3} \tag{14}\] \[+\tfrac{1}{4}Z_{L}(2\omega_{c})g_{m2}g_{md}A^{3}\Big{]}\] \[V_{ds}(2\omega_{1}-\omega_{2}) \approx R_{L}(\omega_{L})\Big{[}\tfrac{3}{4}g_{m3}A^{3}+\tfrac{1}{2}Z_{L}( \omega_{1}-\omega_{2})g_{m2}g_{md}A^{3}\] (15) \[+\tfrac{1}{4}Z_{L}(2\omega_{c})g_{m2}g_{md}A^{3}\Big{]}\]  
where  
\[\omega_{c}=\frac{(\omega_{1}+\omega_{2})}{2}\approx\omega_{1}\approx\omega_{2 }=\omega_{L} \tag{16}\]  
where \(\omega_{1}\) and \(\omega_{2}\) are lower and upper two-tone input frequencies, respectively, and \(Z_{L}\) is the frequency-dependent load impedance. It can be seen that the IMD3 of the circuit is highly dependent on the third-order transconductance (\(g_{m3}\)) of the transistor. The third-order transconductance of the transistor exhibits a strong dependence on its bias voltage, as demonstrated in Figure 15. Notably, we can observe that there is a sweet spot for the third-order transconductance, where the IMD3 distortion can be minimized.  
To expand the sweet spot range of the third-order transconductance across the expected power range, this work divides the power cell into two sections, each with different bias voltages. By compensating for the nonlinear components produced by each power cell operating under different bias conditions, the overall power amplifier achieves a low  
Figure 15: \(g_{m3}\) vs. gate voltage.  
IMD3 distortion. Figure 16 compares the IMD3 performance of the circuit with and without using MGTR. It can be seen that after adopting MGTR technology, the circuit's IMD3 distortion can be effectively suppressed by choosing an appropriate combination of different bias voltages.