# All-Integer Quantization for Low-Complexity Min-Sum Successive Cancellation Polar Decoder
## 3 Related Work  
Polar codes have gained significant attention in modern communication systems due to their capacity-achieving properties, as well as their low-complexity construction and decoding. Considering future wireless communication systems, [7] highlighted the potential of polar codes as a candidate for 6G wireless networks, which demand ultra-low latency (100 \(\upmu\)s) and extremely high reliability (FER below \(10^{-6}\) to \(10^{-7}\)). In [15], polar codes were investigated as a replacement for Long-Term Evolution (LTE) turbo codes in narrowband Internet of Things (NB-IoT). With their proposed BP decoding for polar codes, the performance gap was reduced by 1.2 dB when compared to turbo codes. Additionally, the complexity of polar codes was shown to be lower than that of turbo codes. Recent studies [17] have explored the significant increase in NAND flash memory, which has led to data becoming more prone to errors, as well as an increased uncertainty in the channel. To address these issues, they proposed a polar code construction, which reduces the uncorrectable bit error rate by up to 90.5%. As polar codes continue to be explored in applications such as 6G, IoT, and NAND flash memory, optimizing their implementation becomes crucial. One key approach to achieving efficient decoding while maintaining performance is through quantization techniques, which balance computational complexity and error correction capability. In [2], the performance of quantized SC decoding was compared to that of a floating-point algorithm using fixed-point operations with five and six quantization bits. The study also demonstrated that higher quantization levels and longer code lengths lead to increased area usage in hardware implementations. A nonuniform-quantized SC decoder was proposed in [9] to reduce the bit precision level of quantization, as low-bit precision is beneficial for applications requiring low-energy transceivers. To observe the performance of a semi-parallel architecture for SC decoding, proposed by [21], the performance of SC decoding with quantization, where the input is limited to the range \([-2,2]\) before the quantization process, almost matches that of the non-quantized decoder with 5 bit precision. To design a fast low-complexity SC decoder, ref. [22] employed 6-bit quantization to represent internal LLRs while maintaining an error correction performance close to that of the floating-point representation. To implement a multi-kernel decoder based on the fast-simplified SC algorithm, ref. [23] employed a quantization scheme \(Q(Q_{i},Q_{c},Q_{f})\), where \(Q_{i},Q_{c}\), and \(Q_{f}\) represent the number of LLR quantization bits for internal, channel,  
Figure 2: A block diagram of polar coded system. and fractional bit sizes, respectively. With 5-bit quantization, the performance of their proposed SC decoder is very close to that of the floating-point scheme. Two novel processing element (PE) units for SC decoders were proposed in [24], where a 6-bit quantization scheme was chosen to balance the trade-off between BER performance and complexity. In [25], their method optimized hardware resource utilization by reducing memory usage. The implementation on a Virtex UltraScale-XCVU190 FPGA demonstrated a throughput of 2672 Mbps, with a 17% reduction in lookup table (LUT) usage and a 17.34% speed improvement for a code length of 128. The study also explored different quantization schemes, analyzing the trade-offs between integer and fractional bit precision in SC decoding. To reduce latency and energy consumption, a novel Fast-SSC decoder, proposed in [26], was designed using fixed-point operations with 5-bit uniform quantization to optimize memory usage in hardware. While these studies have explored and utilized various quantization strategies for SC decoding, most focus on achieving hardware efficiency while maintaining a performance close to floating-point implementations. However, there is limited investigation into the trade-offs between quantization precision and decoding performance.