# Design of a Digital Array Signal Processing System with Full Array Element
## 2 System Architectural Design
### System Software Architecture Design
#### 2.2.1 Multi-Channel Synchronous Design  
The design of multi-channel synchronization requires the synchronization of multiple RFSoC inter-chip transceiver channels on four transceiver modules. First, we synchronize the clock networks of each transceiver module so that the sampling reference clocks and SYSREF output from each clock network are synchronized. At the same time, under the premise of the sampling reference clock and SYSREF synchronization, RFSoC's inter-chip synchronization mechanism is used to achieve ADC/DAC converter synchronization. After converter synchronization, if the system adopts the HIF architecture to enable the internal digital up/down converter, it is necessary to reset the digital up/down converter NCO local oscillation phase in each transceiver module to finally realize the inter-chip transceiver channel synchronization. Compared with other acquisition/transmission systems, RFSoC uses its internal API function for synchronization. Through the internal synchronization mechanism and the system clock network, the synchronization process shown in Figure 9 is used to achieve multi-channel synchronization between multiple transceiver modules of the system. Figure 8: System software architecture. After multi-channel synchronization between multiple transceiver modules, we test the synchronization effect. To test the synchronization between multiple transmit channels of two transceiver modules, transmit channel 1 on transceiver module 1 is selected as the reference channel; transmit channels 2, 3, and 4 on transceiver module 1 are selected as test channels 2, 3, and 4; and transmit channels 1, 2, and 3 on transceiver module 2 are selected as test channels 5, 6, and 7. The test signal is a 2.4 GHz point frequency signal. Each channel is connected to a high-speed oscilloscope and the system is powered on and reset several times to compare synchronization between each test channel and the reference channel. The multichannel synchronization test results are shown in Figure 10. The left section of the diagram displays time-domain waveforms of individual channels, while the right section illustrates the distribution of delays of each channel relative to the first channel. This distribution is obtained through statistical analysis of multiple test results and effectively reflects synchronization and stability among the various channels. The delay distribution between channels can visually reflect the delay between each channel and the reference channel after synchronization, and the delay between channels is \(\pm\)5 ps. The extreme difference in the inter-channel delay distribution represents the maximum delay jitter of the channel, and the maximum delay jitter of each channel is controlled within 2 ps. From the results, we can see that the multi-channel between multiple transceiver modules has excellent synchronization and stability. To achieve multi-channel synchronization at sampling rates of up to 10 GSPS, it is necessary to place high requirements on the system clock. Next, the impact of system clock skew and clock random jitter on synchronization are analyzed. The synchronization clock network is shown in Figure 11.  
Figure 9: Synchronization processes. The clocks in Figure 11 are, from top to bottom, the sampling reference clock \(Clk_{r1}\) of transceiver module 1, the sampling reference clock \(Clk_{r2}\) of transceiver module 2, the synchronous SYSREF clock \(Clk_{s1}\) of transceiver module 1, and the synchronous SYSREF clock \(Clk_{s2}\) of transceiver module 2. \(Clk_{r1}\) and \(Clk_{r2}\) have clock random jitter \(Tj_{r11}\) and \(Tj_{r12}\), and there is clock skew \(Ts_{r1r2}\) between the sampling reference clocks of the modules due to the different clock paths. The SYSREF clock also has clock jitters \(Tj_{s11}\), \(Tj_{s12}\), \(Tj_{s21}\), and \(Tj_{s22}\), and clock skew \(Ts_{s1s2}\). During synchronization, the sampling reference clock of each transceiver board captures the synchronous SYSREF clock.