# Capacitor-Less Low-Power Neuron Circuit with Multi-Gate Feedback Field Effect Transistor
## 1 Introduction  
Existing digital systems, such as computers, have been developed through computation using semiconductors and the integration of logic and memory devices. Digital systems based on the Von Neumann structure, which are based on the signal exchange between processing/logic devices and memory devices, have been used very successfully to date. Recently, there has been a surge in demand for processing numerous data at once, such as big data and Artificial Intelligence (AI), but the Von Neumann computing structure creates a bottleneck between computing units and data storage, leading to overall system performance degradation. Therefore, a new concept of a computing system for high energy efficiency and excellent performance is required to overcome the problems of existing Von Neumann computing systems. Various studies are being conducted with a different approach than used before, and among them, Spiking Neural Network (SNN) technology is a research technology that is inspired by biological principles to implement neural networks through it [1; 2; 3; 4; 5; 6; 7; 8; 9]. SNN is a technology that directly combines neurobiological mechanisms in neuroscience into AI and is known as the third-generation Artificial Neural Network (ANN) technology that utilizes time-based information encoding and time-based information processing, one of the main functions of the brain. SNN-based neuromorphic computing aims to efficiently mimic biological spiking neural network mechanisms by distributing synaptic operations and information storage through an event-based asynchronous spike motion mechanism across a number of relatively simple computing devices, neurons. These hardware-based spiking neural networks consist of numerous neuron circuits, and each neuron circuit plays the same role as a real biological neuron. Therefore, most of the power consumption is consumed when neurons make spikes. Therefore, it is important to reducethe power consumption of each neuron in order to reduce power consumption. However, most analog neuron circuits accumulate input signals using membrane capacitors. Additionally, most of the power is consumed in the first inverter step. The reason is that in the analog neuron circuit, the voltage of the capacitor increases only when the input signal is received, and the voltage of the first inverter increases slowly. If the voltage increases slowly, the time when the PMOS and NMOS are turned on simultaneously increases, and thus, a short circuit current (Isc) continues to flow from Vdd to ground. In addition, when the membrane capacitor is charged up to the switching voltage of the inverter, short-circuit current continues to flow through the first inverter without spikes, which can consume more power than when neurons discharge the capacitor after generating spikes. That is, conventional analog neuron circuits require many transistors and large capacitors to integrate neuron signals, which are problematic in scale. Additionally, whenever an input pulse is applied for a long time, the membrane potential gradually increases, generating Isc before threshold voltage (Vth) and consuming most of the energy in the first inverter step [10; 11]. To solve these problems, a device with excellent steep switching characteristics and capable of replacing the role of a membrane capacitor should be used in neuron circuits. In this study, we adopted the FBFET as the device. The FBFET has a steep switching characteristic; therefore, it can suppress leakage current [12; 13]. Additionally, the mechanism is similar to that of a transistor; therefore, it has excellent endurance characteristics and can be processed by a typical CMOS process. In addition, the device can replace the role of the membrane capacitor by storing electric charges in the floating body. By applying FBFET with these characteristics, we design a neuron circuit that can significantly reduce power consumption.