## 4 A Survey on FPGA-Based Sensor Systems
### Proof of Concept Designs  
In this section, general designs of research sensor nodes are scrutinized. We describe the implementations and results of standalone platforms based on SoC from [61; 62; 63; 64].  
In [62], [PERSON] _et al._ presented a sensor node based on SoC. Such SoC is based on the OpenRisc 1200 processor and executes the \(\mu\)/OS II RTOS and Wishbone bus. The SoC consists of three main components: an acquisition unit that is fed from a digital thermometer coupled to the FPGA, the OpenRisc firmware that processes the temperature and a logic block that interfaces a ZigBee transceiver based on RS-232 (SHUNCOM SZ05-STD). The utilized FPGA is an Altera Cyclone II (EP2C70). The system consumes 221 mW. We note that the power consumption during transmission and reception was not detailed. Nevertheless, given that the FPGA only interfaces several components (digital thermometer and ZigBee transmitter), it seems to be an overkill, since its inner embedded resources are not used and the same task can be performed using a low-power microcontroller. Also, [61] has the same problem. This sensor node is based on an Altera Cyclone I (EP1C6) that transmits the information via Bluetooth. Nevertheless, the authors did not provide information about the energy consumption of their platform. Moreover, Bluetooth is ill-suited in WSNs usage, since the IEEE 802.15.4 has a better approach for low-distance/low-power communications and has been adopted by the Zigbee Alliance for sensing applications.  
The authors of [63; 64] presented other standalone platform based on FPGA for a sensor node, where the Zefant XS3-2000 platform based on a Spartan-3 (XC3S2000), CPLD and 128 Mb FLASH memory connected to a Xemics radio transceiver is used. However, information about the used CPLD is notprovided. The implementation is based on the LEON2 32-bit processor. This platform was proposed in order to prototype smart sensor nodes with advanced processing capabilities and with extended debugging capabilities in the FPGA. Moreover, the FPGA allows to interface different types of sensors as well as to implement different MAC protocols. According to the authors, the platform consumes between 0.7 W and 1.1 W at 11 MHz, running the LEON2 SoC. A Reconfigurable Function Unit (RFU) was attached to the LEON2 system. The RFU consists of optimized modules to perform Galois Field (GF) arithmetic and inversion operations. The RFU is used from the processor through special implemented instructions.  
The authors measured different implementations of algorithms in both software and custom logic. Implementations of CRC-8, AES key generation and encryption, and Broadcast Channel (BCH) decoding showed that custom logic reduce the energy consumption and execution time. Hence, AES encryption consumed 104.9 nJ (plus 43.1 nJ during the FPGA reconfiguration) _versus_ 640.6 nJ in the processor. Furthermore, BCH decoding required 1,208.7 nJ in software in comparison to 245.5 \(\mu\)J in hardware (plus 43.4 nJ during reconfiguration).  
However, despite the reduction of power consumption by executing algorithms in the RFU instead of the processor, the advantages that provide a combination of low-power microcontroller and FPGA are twofold. First, the FPGA can be turned off when not needed in order to save power. Second, the FPGA can run independently at a different frequency than the microcontroller, which allows to turn it on during a shorter interval, searching for a balance between power consumption and speed. Consequently, the microcontroller can run at a lower frequency and the FPGA utilization can be optimized. Nevertheless, the reconfiguration time cannot be negligible in platforms based on a combination of microcontroller and FPGA, since external configuration of the FPGA requires more time [41] as well as data transmission between the FPGA and the microcontroller.