# Error Mitigation Methods for FSM Using Triple Modular Redundancy
## 5 Experimental Results  
A number of experiments have been carried out to compare different methods of mitigating FSMs' error effects. The aim of this comparison is to determine the best solutions in terms of the number of LUT blocks, the number of logic levels, and, especially importantly, the dynamic power consumed. The most popular set of benchmarks describing FSMs [59] was used. Based on the benchmarks described in kiss2 format, descriptions of the transition functions and outputs were extracted and converted to Verilog HDL. These HDL descriptions are supplemented by flip-flops. Their number depends on how the internal states are encoded. Since most often the internal states in the kiss2 format are represented in symbolic form, the one-hot coding was adopted as the most universal and most common for FPGAs. In one case (s27), the encoding was already imposed on the kiss2 format. In this situation, the authors decided to leave the original encoding in place. Moreover, the description of each benchmark is supplemented by TMR voters. The way they are included is determined by one of five models, where Model 0 is an FSM completely devoid of TMR voters (Figure 1) and Models 1-4 are presented in Sections 3.1-3.4, respectively. The academic synthesis tool ABC [60] targeting LUT blocks with four inputs (\(k=4\)) was used for the experiments. The benchmark parameters, i.e., the number of inputs, the number of outputs, and the number of internal states of the FSM, are presented in Table 3. The results obtained are summarized in the form of Table 4. The number of flip-flops 'FF', the number of LUT blocks 'LUT', and the number of logic levels 'LI' were determined. In addition, the value of 'Power' obtained from the ABC system, associated with switching activity (dynamic power for constant values of frequency and supply voltage), is shown. The last row contains the values of the sums of the individual quantities summarized in the table. These are shown as graphs in Figure 13.  
Comparing the results obtained, the number of LUT blocks (Figure 13a) utilized for triplication of combinatorial blocks (Models 2, 3 and 4) shows a significant increase in the use of logic resources, which seems natural. It can also be seen that Model 4 uses lower resources than Model 3. This means that replicating entire FSM is more efficient in terms of the number of LUT blocks than deep interference with the architecture, as in Model 3. Taking the model without redundancy (Model 0) as the reference model, the utilization of logic resources can be determined against this model. Relating this to the number of FFs, it can be seen that in all other models, there is a tripling of the number of FFs. In contrast, the number of LUT blocks is, respectively, 1.41 (Model 1), 2.61 (Model 2), 3.08 (Model 3), and 2.80 (Model 4) relative to Model 0. When comparing the results obtained in terms of the number of logical levels (Figure 13b), it is difficult to draw clear conclusions. It can be seen that the use of TMR voters increases the number of logical levels, which is in line with expectations. In the case of power (Figure 13c), it is easy to see the similarity to the graph of Figure 13a--Model 4 performs better than Model 3. The authors additionally performed experiments in the commercial Vivado system (AMD). The synthesis was targeted at the logic blocks of 7-series FPGAs (Artix-7). The results are summarized in Table 5.  
Table 5 is organized similarly to Table 4 except that only the number of LUT blocks 'LUT' and the dynamic power 'Power' expressed in watts are given for each model. These parameters were read from the respective reports after the synthesis and implementation process. The values of the totals are presented as graphs in Figure 14.