# A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures
## 5 Pseudo-Random Pattern Generator DT-LFSR-TPG for LBIST Circuits with the STUMPS Architecture
Some supplementary details, separated with commas and related to structures of DT-LFSR-TPG units feeding the specific number of scan paths, are provided in Table 8, which has exactly the same layout as Table 7 but slightly different content. These details are the \(Z\) number of DT-LFSR registers with the D\({}^{n-t}\)T\({}^{t}\) structure incorporated into the test pattern generator as well as the number of \"redundant\" flip-flops of the D and T types present in the structure of the DT-LFSR-TPG unit. The term \"redundant\" flip-flops refers to the flip-flops of both the D and T types with outputs that are not connected to any scan paths (not used to feed any scan path). On the other hand, these flip-flops are indispensable to design \(Z\) properly operating DT-LFSR registers with the D\({}^{n-t}\)T\({}^{t}\) structures and incorporated as components of the DT-LFSR-TPG unit. The maximum operational frequency of the DT-LFSR-TPG unit in the testing mode is the same as for DT-LFSR registers included as components of the unit and equals 994 MHz. However, the interleaving technique may be necessary for the topology of the unit to achieve the maximum possible operation frequency of the DT-LFSR registers (see Figure 14). Eventually, it leads to long interconnections in the layout of the DT-LFSR-TPG unit between SO outputs of preceding DT-LFSR registers and SI inputs of subsequent registers. It is why the operating frequency of the TPG unit may be slightly lower in the seeding mode (serial shift) than in the testing mode. Figure 14: Topology layout for a 20-bit DT-LFSR register with the D\({}^{3}\)T\({}^{17}\) structure and designed by means of the interleaving technique. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**No.** & \(t\) & \(n\) & **Total Cost** & **Cost Per Channel** \\ \hline  
\hline \hline \end{tabular}
\end{table} 
Table 6: Results of the logic synthesis for selected registers of the DT-LFSR type. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline
**No.** & \(t\) & \(n\) & \multicolumn{6}{c}{**Number of Scan Paths**} \\ \cline{4-9}  & & & **128** & **256** & **512** & **1024** & **2048** & **4096** \\ \hline  
\hline \hline \end{tabular}
\end{table} 
Table 7: Implementation costs for test pattern generators of the DT-LFSR-TPG type. Figures provided in Table IX of [34] were used to calculate implementation costs and maximum operational frequencies for test pattern generators of the LFSR + PS types, where each test pattern generator of that type is made up of an LFSR register with a phase shifter connected to its outputs. The calculation results are summarized in Table 9. The investigations were dedicated to LFSR + PS test pattern generators with LFSR registers, where feedback loops of these registers are defined by means of the following primitive polynomials [34]:  
\(\bullet\)\(h_{1}(x)=x^{32}+x^{31}+x^{5}+x^{4}+1\)  
\(\bullet\)\(h_{2}(x)=x^{48}+x^{31}+x^{22}+x^{5}+1\)  
\(\bullet\)\(h_{3}(x)=x^{64}+x^{53}+x^{23}+x^{12}+1\)  
\(\bullet\)\(h_{4}(x)=x^{80}+x^{70}+x^{13}+x^{3}+1\)  
\(\bullet\)\(h_{5}(x)=x^{96}+x^{82}+x^{49}+x^{35}+1\)  
\(\bullet\)\(h_{6}(x)=x^{128}+x^{29}+x^{27}+x^{2}+1\)  
Each polynomial was investigated for two options of a linear register designed according to that polynomial, namely an LFSR register with an external feedback loop (type I LFSR [34]) and an LFSR register with an internal feedback loop (type II LFSR [34]). The numbers of scan paths fed from a test pattern generator of the LFSR + PS type are listed in the first column of Table 9. For each test pattern generator, the table contains two numbers, one above the other. The first number stands for the implementation cost of an LFSR + PS test pattern generator, expressed as the number of equivalent two-input NAND gates and comprises both the cost of a phase shifter and the one of an LFSR register. The second number is the maximum operating frequency of a TPG unit expressed in megahertz (MHz).