## 2 Materials and Methods
### Experiment Design and Setup  
In this paper, an IC from the 110 nm technology node has been studied, mounted on a quad-flat package. A custom test board has been specifically designed to minimize the effect of the PCB on the conducted and radiated emission, see Figure 5. A multilayered structure has been adopted, where the package pins are directly connected to vertical vias, and then routed in inner layers. In this way, no trace is routed on the upper side of the board, so avoiding indirect radiation. The power traces (\(V_{dd}\) and \(V_{ss}\)) are routed in different layers with respect to the signal traces, to avoid any effect of coupling between power and signal subsections. In addition, the signal traces connected to adjacent package pins are routed in different layers, in order to mitigate the high-frequency crosstalk effect. Specifically, in the board used for the conducted emission test, additional traces are routed independently to the board surface to provide contact points for the current probes. In the board used for radiated emission,  
Figure 4: Details for the model of radiated emission from IC: (**a**) a loop of current flowing from the IC into the package; and (**b**) the reference system for the far-field emission from a loop current (magnetic dipole).  
addition bottom layers are included, where no signal is routed and no via is connected. The presence of blind vias and of electromagnetically-decoupled bottom layers minimize the contribution to the emitted field possibly related to parasitic cavity resonances.  
The block diagrams of the experimental setups used for evaluating the conducted and radiated emissions is schematically reported in Figure 6. For both cases, the test board is terminated on a load simulating a buffer that exchanges data with the IC, so that the emission analysis is performed while the equipment is operating in nominal conditions, as requested by the EMC norms [24; 25; 26]. To this end, a signal generator (Keysight, US: model N9310A, bandwidth 9 kHz-3 GHz) was connected, with an internal impedance of 50 \(\Omega\) in the considered range, in parallel to a 40 pF capacitor representing a buffer. As for the conducted emission test, the currents have been acquired at the test board pads by a current probe (Lecroy D410-A-PS, bandwidth 4 GHz), then sent to an oscilloscope (LeCroy, Korea: model WavePro 7 Zi-A oscilloscope, bandwidth 6 GHz, 40 GS/s). The adopted measurement chain accounts for a maximum measurement uncertainty of \(\pm\)2.5 dB on the considered frequency range.  
With reference to the radiated emission test, the far-field electrical field has been collected by a broadband receiving antenna (a biconical-log antenna HL, Czech, model HL-1000, bandwidth 30 MHz-1 GHz) connected to an EMI receiver (R and S ESPC, bandwidth 9 kHz-2.5 GHz). Additionally, in this case, the maximum measurement uncertainty in the considered frequency range is \(\pm\)2.5 dB. Specifically, a 3 m-radiated test was performed in a semi-anechoic chamber, according to the CISPR 16-4 standards for the radiated emission, in the frequency range from 30 MHz to 1 GHz [25]. A preliminary measurement with the device off has been performed to estimate the background noise and remove it from the results. The device under test was made by the IC mounted in its test board, connected to a signal generator through shielded cables, to avoid unwanted emission from interconnects.  
Figure 5: Stack layer of the designed test-board for the IC emission tests: the power traces are routed in separate layers, as well as signal traces coming from adjacent pins.  
Figure 6: Schematics of the setup blocks for conducted and radiated emission test.