###### Abstract
However, each interconnect technology has some challenges associated with them. The inability of the pitch scaling makes the adoption of photonic interconnects challenging for high complexity scalable multi-chip systems. Moreover, thermal tuning of on-chip electro-optic modulators can be power hungry and unreliable with thermal variations of the dies. In 3D integration of ICs, complex thermal management techniques are required to address the higher power dissipation densities in 3D ICs due to smaller footprints. These thermal management techniques vary from dynamic power management methods such as Dynamic Voltage Frequency Scaling (DVFS), temperature-aware task migration [17] or microfluidic cooling channels for better heat circulation [18]. Microfluidic channels, while very effective at cooling chips, need fluid intake pipes through the packaging making the whole system complex. Moreover, die thinning for fabrication of Through-Silicon-Vias (TSVs), particularly if co-existing with microfluidic channels, result in low yields. The use of silicon-interposers, which are themselves large dies with abundant wiring resources seem to emerge as a low-cost and high-yield alternative to photonic or monolithic 3D integration. However, the interposer-based integration methodology still engages metallic wires, which can incur high latency and power consumption over long distances affecting the scalability of the system [19]. To demonstrate the impact of increase in number of chips in a multi-chip system we have considered an example where, a total of 64 cores in the system are disintegrated into multiple multicore chips. The 64 cores are equally distributed among all the chips in the system resulting in three configurations with four 16-core chips, eight 8-core chips and sixteen 4-core chips. The cores within each multicore chip are interconnected with a 4 \(\times\) 4 mesh and the inter-chip communication happens through a silicon interposer creating an extended mesh topology by connecting the switches on the boundaries of adjacent cores as shown in Figure 1a. Four DRAM stacks implementing a distributed memory subsystem is also considered. Each switch implements wormhole switching [20] with dimension order routing and is considered to have 4 Virtual Channels (VCs) per port and a buffer depth of 4 flits per VC. The wired link characteristics in each chip as well as in the interposer are modeled from global wire models with 0.2 pF/mm parasitic capacitance [21]. The switches are characterized from post-synthesis models using 65 nm technology node [22]. Cycle-accurate simulations for these systems, with a 20% memory access probability by all cores and an 80% uniform random traffic between all cores in all chips, are performed following the methodology outlined in detail in Section 5. All packets are broken down into flow control units (flits) and in our simulations each packet is considered to have 16 flitswhere each fit is 64 bits wide. In Figure 1b we present the throughput per core and packet energy dissipation of an interposer-based multi-chip system with increasing number of multicore chips. It can be observed that the throughput per core decreases and packet energy increases with increase in the number of multicore chips. This indicates the need for an efficient inter-chip interconnection fabric. In addition, all these interconnect systems require physical links with wires or waveguides which require complex place and route algorithms for optimal designs. Moreover, photonic waveguides and rigid interposer platforms limit the range of motion between the individual ICs in the system. Wireless inter-chip interconnection systems will not have these limitations related to laying out waveguides or wired interconnects. Therefore, the wireless interconnect will enable system integration on flexible substrates for wearable electronic system. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects can establish radio communications within as well as between multiple chips.