# Design of a Digital Array Signal Processing System with Full Array Element
## 2 System Architectural Design
### System Software Architecture Design
#### 2.2.1 Multi-Channel Synchronous Design
In Figure 11, the sample reference clock of transceiver board 1 arrives at time \(T0_{r1}\). To ensure that the sampling reference clock successfully  
Figure 11: Synchronous clock network. Figure 10: Channel synchronization test: (**a**) Channel 1, 2, 3, and 4 synchronization test; (**b**) Channel 1, 5, 6, and 7 synchronization test. captures the synchronous SYREF clock, time \(T0_{s1}\) of \(Clk_{s1}\) arriving at the transceiver board needs to satisfy the conditions in Equation (2). \[\left\{ \begin{array}{l}T0_{s1}\leq T0_{r1}-Tsetup-Tj_{s12}-Tj_{r11}\\ T0_{s1}\geq T0_{r1}-T_{r}+Thold+Tj_{s11}+Tj_{r12}\end{array} \right. \tag{2}\]  
Similarly, time \(T0_{s2}\) of \(Clk_{s2}\) arriving at the transceiver board needs to satisfy the conditions shown in Equation (3):  
\[\left\{ \begin{array}{l}T0_{s2}\leq T0_{r1}+Ts_{r1r2}-Tsetup-Tj_{s22}-Tj_{r21 }\\ T0_{s2}\geq T0_{r1}+Ts_{r1r2}-T_{r}+Thold+Tj_{s22}+Tj_{r21}\end{array} \right. \tag{3}\]  
where \(Tsetup\) is the setup time to be satisfied by the sample reference clock of the transceiver board, \(Thold\) is the hold time during which the input signal needs to remain stable to ensure accurate signal sampling and transmission, and \(T_{r}\) is the sample reference clock period of the transceiver board. Equations (2) and (3) show that the synchronization of the system is mainly associated with sampling reference clock period, setup/hold time, and clock random jitter. The smaller the sampling reference clock frequency and the larger the period, the easier it is to synchronize; hence, synchronization at sampling rates of up to 10 GSPS is particularly difficult. The smaller the setup/hold time required for the sample reference clock, the better the system synchronization. The system setup/hold time is associated with RFSoC device characteristics and cannot be controlled. The smaller the jitter of the sampling reference clock and the synchronous SYSREF clock, the easier it is to satisfy Equations (2) and (3), and the more favorable it is to synchronize the system. Therefore, for system multi-channel synchronization at high sampling rates, controlling the reference clock jitter and synchronous SYSREF clock jitter is a key factor for successful synchronization. However, the clock with jitter is usually associated with the system hardware and cannot be controlled. When the transceiver module clock jitter is large and cannot meet the synchronization conditions, the system clock network described in Section 2.1.3 can be used to achieve a precise delay of each transceiver module synchronous SYSREF clock to meet the synchronization constraints and achieve synchronization. Subsequently, the delay and jitter between each channel after synchronization are analyzed. The inter-channel delay and jitter are associated with the phase random jitter of the sampling reference clock, which comes from the random noise of the clock circuit, including thermal noise, flicker noise, and other kinds of superimposed independent noises. Regardless of the probability distribution of individual noise sources, the total noise obeys a Gaussian distribution according to the central limit theorem; therefore, the probability distribution of delay jitter between channels is shown in the approximate Equation (4) [17; 18; 19; 20]. \[p(x)=\frac{1}{\sigma\sqrt{2\pi}}e^{-\frac{(x-p)^{2}}{2\sigma^{2}}} \tag{4}\]  
Figure 12 shows the delay distribution between two test channels and the reference channel of the high-speed oscilloscope test. From the figure, it can be seen that the delay distribution between the channels is consistent with the above analysis and approximates a Gaussian distribution. Based on the Gaussian distribution characteristics, the skew \(Ts_{r1r2}\) in Figure 11 is associated with the mean difference of the different channel delay jitter distributions. The smaller the mean difference, the smaller the reference clock skew between channels. The reference clock's jitters \(Tj_{r11}\) and \(Tj_{r12}\) are associated with the variance in the Gaussian distribution.