# A Review of Cell Operation Algorithm for 3D NAND Flash Memory
## 3 Read Algorithm
### Improvement of Read Performance  
Next, looking at the read algorithm and its relation to read performance improvement, the first step is to reduce the sequence and duration within one read operation cycle by optimizing the read operation conditions; the second step is to modify the chip architecture and cell design; and the third step is to improve the number of read operations through revision of the read retry algorithm. First, to decrease the period of one read cycle, a method to reduce the BL pre-charge time has been proposed [50], increasing the BL pre-charge efficiency by permitting a continuous current flow in the page buffer circuit. Moreover, concurrent program sensing scheme  
Figure 9: (**a**) The reference and proposed signal timing diagrams of the read operation. Reprinted/adapted with permission from Ref. [62], 2017, IEEE. (**b**) WL waveform of conventional and the proposed scheme. Reprinted/adapted with permission from Ref. [44], 2016, IEEE. has been proposed to reduce the sequence of read operations [63]. In conventional TLC NAND flash memory, two or three read voltage levels are applied and sensed within one read cycle, and BL pre-charge-evaluation-recovery operations are sequentially performed each time. In this paper, it is demonstrated that the total read time can be reduced by omitting the BL recovery operation of the second sensing operation and starting the second sensing operation with the first sensing, thereby retrieving the very long second evaluation time. Meanwhile, [PERSON] et al. showed that the read noise can be improved by applying ground level to the adjacent BL when sensing the selected BL to improve cell distribution by reducing coupling noise caused by the adjacent BL [68]. However, in this case, an additional read time budget should be considered. Second, there are several methods to improve the read performance by changing the chip architecture. For further read performance enhancement, parallel operation technology should be secured along with the aforementioned read period reduction within one read cycle. In 2D NAND, a two-plane architecture with 8 KB page size used to be the mainstream; however, as the field moved to 3D NAND, a two-plane architecture with 16 KB page size was adopted [47]. Currently, cell under array (CuA) technology has secured space for more page buffer circuits and sense amplifiers, and so four-plane architecture with 16 KB is applied to most 3D NAND products [30, 31, 46, 63], as shown in Figure 10a; this parallel technology contributes to higher read and program performance [70]. For further improvement, an independent multi-plane read operation is proposed, in which each group of two or four planes can perform read operations independently and asynchronously on any block/page address, thereby improving system level read and write performances [69, 71, 72], as shown in Figure 10b. In addition, [PERSON] et al. proposed a center-XDEC architecture and half-plane activation method [46]. Compared to the conventional edge-XDEC, the source of each local WL (referred to as global WL) is placed at the center of each plane for the center-XDEC. The local WL is activated by a bypass transistor, which is controlled by a block enable signal. This technique cuts the WL capacitance in half and reduces the WL RC loading, thereby decreasing WL settling time and increasing the random read performance. Third, it is a method to reduce the read time overhead through revision of the read retry algorithm. Retrying a read can extend the lifetime of a NAND Flash memory; however, a performance degradation due to repetitive read operations is inevitable [73]. In 3D NAND, a cell distribution shift occurs over time due to repeated program/erase cycling and retention loss. In this case, when data are read at the previously fixed read level, the read margin is reduced, and thereby, the read failure rate is rapidly increased due to the above shift of cell distribution.