## 4 Hardware Security  
Edge devices are highly distributed and exposed to numerous threats, including physical tampering, data breaches, and remote cyberattacks. These devices lack standard security practices, deploy heterogeneous communication technologies, and have scalability issues [193]. Thus, strong security measures are required at the hardware level to secure sensitive data and to restrict unauthorized access [194]. Hardware security threats can infiltrate edge devices at any stage of the semiconductor lifecycle, from specification and fabrication to recycling. These threats may arise from unintended design flaws, system side effects, or deliberate malicious modifications during the design process [195]. Both hardware- and software-based mitigation techniques are used to reduce or randomize the vulnerable signal footprints [196]. A widely used authentication technique for edge devices is challenge-response protocols, mostly based on cryptographic primitives and secret keys. However, implementing these protocols on resource-constrained IoT devices remains a  
Figure 14: Types of anomaly IDS. challenge, and the probability of physical threats like direct probing and side-channel attacks is high. Subsequently, a new security primitive, known as PUFs, arrived that offers secure key storage and lightweight authentication [197]. Hardware attacks can be placed into two distinct categories: non-invasive and invasive attacks, based on the level of physical impact on the device [198]. Common hardware security protocols utilize encryption techniques like the Advanced Encryption Standard (AES) and Elliptic Curve Cryptography (ECC) that can be placed under private and public-key encryption. A Hardware Trojan (HT) is a malicious alteration during the chip fabrication stage that might compromise its functionality or spy on encryption keys and forward sensitive chip data to unauthorized devices. HT detection techniques are placed under destructive or non-destructive approaches. Destructive detection includes reverse engineering techniques, such as dismantling IC architecture with Chemical Mechanical Polishing (CMP) and Scanning Electron Microscopy (SEM). However, non-destructive methods analyze IC during the pre-silicon or post-silicon stages. Pre-silicon analysis benchmarks the IC against a fully defined model, while post-silicon analysis includes logic testing and side-channel analysis [199]. The IC supply chain faces security challenges in addition to HT at various stages, including IP piracy, IC cloning, hardware backdoors, and counterfeit chips. On-chip aging sensors can pick counterfeit chips while split manufacturing mitigates IC overproduction and IP piracy issues [200]. Figure 15 lists a broad classification of hardware security threats and corresponding countermeasures available. Reverse engineering (RE) analyzes and decomposes edge devices' design and behavior by extracting confidential data or intellectual property [201]. RE is accomplished by examining various design formats, such as RTL, netlist, layout (GDS-II), mask, or fabricated ICs [195]. It is viable to reverse-trace and fabricate the design, which can be further reused or enhanced [202]. To restrict RE in IC design, hardware obfuscation is the preferred technique that conceals its functionality by placing the logic elements in a random fashion, irregular routing, varying doping concentrations, manipulating dielectric properties, and more [203]. Camouflaging is another option that enables two functional modules to appear identical at the layout level [204]. The adversaries do not physically damage the IoT devices in Side-Channel Attacks (SCAs) nor intervene with or modify the system's operation. SCAs passively monitor specific parameters from sensors or networks, like power consumption, the timing of cryptographic operations, electromagnetic emissions, or acoustic signals [205]. The mitigation techniques against passive SCAs are classified into two groups: hiding and masking.