# A Novel Cross-Latch Shift Register Scheme for Low Power Applications
## 1 Introduction  
The shift register has been commonly used in various digital circuits for decades. This circuit block can be applied in conversion between serial and parallel interfaces during data transmission, and it can be used as a delay circuit too. The shift register is a key component in digital circuits and is generally used in active-matrix displays, sensors, memories, communication receivers, and real-time image processing chips [1, 2, 3, 4, 5, 6, 7, 8]. The shrinking feature size of process technology has enhanced the potential performance of electronic devices, and the capacity of shift registers has increased significantly. Therefore, asking for less overhead integrated circuitry layout area [9, 10, 11, 12] and less power consumption [9, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] in the shift registers design then becomes more important with the capacity increasing [27].  
The conventional architecture of a shift register consists of \(N\)-bit flip-flops connected in series. Circuit implementation in such architecture is fast and efficient. However, requesting less overhead layout area and less power consumption still cannot be fulfilled. Additionally, in master and slave (MS) latch architecture, the same data are stored in two latches during one clock cycle. Hence, the MS latch tends to exhibit redundant area and dissipate more electric power. Obviously, if shift registers are implemented by MS latches without a compensation circuit, the data will be transmitted to multiple outputs at the same time and may result in a malfunction. Recently, [PERSON] proposed a shift register that employed a pulse-latched methodology to solve this issue [27]. The concept behind this reported shift register is using a sub-shift register with an \(N\)-bit latch and using an \(N+1\)-bit clock pulse generator to generate an \(N+1\) non-overlapping clock in one clock cycle to avoid data duplication. Although in this work, the author employed one additional latch in each sub-register to store 1-bit temporary data to solve the timing problem between pulsed latches; however, the circuitry complexity was increased as well. The adoptionof multiple non-overlap delayed pulsed clock signals limits the circuit operating clock frequency. Moreover, this shift register uses \(N\) sub-shift registers to increase the number of latches at the same time. In [27], the author proposed a latch controlled by a pulse generator. This is similar to the behavior of a trigger flip-flop, and the area can be decreased by sharing a pulse generator so that it is suitable for high-speed application. However, the pulse width is difficult to control due to the process variations. Based upon the above discussions, the simultaneous requests for the elimination of the integrated circuit layout area and the reduction of electrical power consumption still could not be realized in the reported work. To solve that issue, in this study, a cross-latch scheme combined with a flip-flop design is proposed to achieve area saving under low operation voltage.  
To overcome the current drawbacks of the conventional MS latch design, in this paper, we propose a novel cross-latch shift register (CLSR) scheme. The proposed CLSR requires only one latch to perform the same functions as those of the MS latches in a conventional shift register. Thus, the proposed CLSR consumes less power and occupies less layout area by reducing the number of transistors.  
Details of the proposed configuration are explained in the next section. In Section 2, the principle of the proposed cross-latch shift register (CLSR) is discussed. Experimental validation and a mechanism depiction for the proposed CLSR are presented in Section 3.