## 4 Implementation Results  
Based on the proposed compact digital baseband architecture for wireless VR systems, we integrated all the baseband processing units including the analog serializer and de-serializer as a prototype design in 65 nm CMOS technology. The die-photo of the prototype baseband system is depicted in Figure 9 where there are four frame buffers, as we utilized two identical baseband systems for supporting both BPSK and QPSK modulations at the 60 GHz RF circuits. To show the impact of the proposed interleaved-BCH ECC solution, we also realized the baseline (106,940, 95,040, 700) BCH codec. Note that the baseline ECC covers a whole data frame with the single code while having the same code rate as the proposed work. Table 1 compares the implementation results of two ECC codec units. By reducing the order of GF dimension, the proposed interleaved-BCH ECC drastically reduces the hardware complexity of both the encoder and decoder architectures. Note that the baseline BCH encoder and decoder necessitate more than 13 M gates, which are impractical to be used for the wireless VR solution. On the other hand, the proposed codec requires only 1.2 M gates, reducing the hardware costs by more than 91%. Figure 8: Block diagram of the proposed one-lane BCH encoder (**a**) and decoder (**b**) architecture. To provide the quantitative comparisons, we summarize the error-correcting performances and the implementation results for different ECC decoding architectures, as depicted in Figure 10 and Table 2, respectively. Compared to the proposed interleaved-BCH code, it is noticeable that the low-rate ECCs for the existing wireless communications, i.e., the 0.5-rate polar code for 5G systems [23] and the 0.5-rate LDPC code for WiGig standards [11; 12], provide superior correcting powers, as depicted in Figure 10. However, the baseband systems based on these soft-decision ECCs normally include complicated processing steps associated with high-resolution ADCs, drastically increasing the transmission latency and the energy consumption, as shown in Table 2. Considering the observed channel condition for the wireless VR scenario, as shown in Figure 2, the proposed interleaved-BCH still achieves an attractive UBER of less than \(10^{-40}\), which can be considered as the error-free communication. As reported in [24; 25; 26], the high-rate ECCs for the storage applications may offer alternative options by achieving a similar error-correcting performances compared to the proposed work. However, in general, the high-rate codes for storages usually adopt the long codewords associated with the iterative decoding operations and multi-level coding schemes in order to lower the error bounds. Therefore, as shown in Table 2, the decoder architectures for storage solutions normally consume a huge amount of energy, which cannot be used for lightweight HMD devices. Allowing the compact and non-iterative ECC architecture, the proposed work definitely provides cost-effective results in terms of silicon area, processing throughput, and even power consumption. More precisely, our architecture consumes only 5.53 pJ for processing a single bit, which is five times less than the previous state-of-the-art ECC solution for near-field wireless system [11]. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Component** & **Baseline BCH** & **This Work** \\ \hline
**BCH codec (total)** & 13,388 K (1.00) & 1211 K (0.09) \\ BCH encoder & 818 K & 98 K \\ BCH decoder (total) & 12,570 K & 1113 K \\ Syndrome calculation & 1061 K & 16 K \\ Key equation solver & 4673 K & 64 K \\ Chien search & 4492 K & 44 K \\ Buffers & 2344 K & 989 K \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Hardware complexity comparison of BCH codec blocks. Figure 9: The die-photo of the prototype baseband processor. Figure 11 shows the FPGA-based testing platform connected through the high-speed test I/O pins and also depicts major features of the prototype design.