# Compression-Assisted Adaptive ECC and RAID Scattering for NAND Flash Storage Devices
## 5 Conclusions  
The density of flash memory devices has increased by moving to smaller geometries and storing more bits per cell; however, this generates a lot of data errors. The typical approach to check these increasing errors is the use of well-known ECCs; however, the current state of the ECC scheme it not on the same level with the evolution of errors of the current state of flash memory. The RAID technology can be employed for flash storage devices to enhance their reliability. However, RAID has inherent parity update overhead.  
In this paper, we propose the enhancement for ECC ability for inside the page and RAID parity management for outside the page, with the help of lossless data compression. The compressed data are encoded with adaptively reduced source length, which increases the recovery ability of the ECC module. The adaptive ECC method can reduce the size of a source length in proportion to the compression ratio. As this reduces the source length to be encoded, the effect of lowering the code rate increases the error-correction rate. For the perspective of outside the page, the compressed data are placed at a specific position in the page. As the unused area in the page generated by compression can be used as a non-overlapping area in RAID scattering, it is effective during the RAID recovery stage. The unused area is spread out within the parity cluster, which reduces the error coverage range due to the possible skipping pages that are not overlapping with the error-occurred page. The experimental results show that adaptive ECC can enhance the ability of error recovery. Furthermore, the RAID-scattering scheme achieves a high reliability at the same RAID stripe level. As the next step of this study, we will apply compression, ECC, and RAID scattering modules as hardware modules to evaluate the actual overhead and performance impact. Therefore, a more rigorous comparison of the performance of the propose  
Figure 13: Result of the number of parity writes per request according to the change in the average request size, for each stripe size four, eight, 16, respectively.  
scheme versus others could be an important task to improve the completeness of the proposed scheme. Consequently, we set the more rigorous performance evaluations as our further work.  
Conceptualization, S.-H.L. and K.-W.P.; methodology, S.-H.L. and K.-W.P.; software, S.-H.L.; validation, S.-H.L.; formal analysis, S.-H.L. and K.-W.P.; investigation, S.-H.L. and K.-W.P.; resources, S.-H.L. and K.-W.P.; data curation, S.-H.L. and K.-W.P.; writing-original draft preparation, S.-H.L. and K.-W.P.; writing-review and editing, S.-H.L. and K.-W.P.; visualization, S.-H.L. and K.-W.P.; supervision, S.-H.L. and K.-W.P.; project administration, S.-H.L. and K.-W.P. All authors have read and agreed to the published version of the manuscript.  
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean Government (MSIT) (NRF-2019R1F1A1057503). This work was supported by Hankuk University of Foreign Studies Research Fund. Also, this work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean Government (MSIT) (NRF-2020R1A2C4002737).  
The authors declare no conflict of interest.  
The following abbreviations are used in this manuscript:  
\begin{tabular}{l l} ECC & Error Correction Code \\ RAID & Redundant Array of Independent Disks \\ SLC & Single-level cell \\ MLC & Multi-level cell \\ TLC & Triple-level cell \\ OOB & Out-of-Band \\ BCH & Block Hamming Code \\ LDPC & Low-Density Parity Check \\ SSD & Solid-State Disks \\ GC & Garbage Collection \\ FTL & Flash Translation Layer \\ LPN & Logical Page Number \\ PPN & Physical Page Number \\ SG & Stripe Group \\ BER & Bit Error Rate \\ RBER & Raw Bit Error Rate \\ UBER & Uncorrectable Bit Error Rate \\ NVRAM & Non-Volatile Random Access Memory \\ GC & Garbage Collection \\ \end{tabular}