# FPGA-Based Frequency Tracking Strategy with High-Accuracy for Wireless Power Transmission Systems
## 3 Frequency-Tracking Control System  
### Frequency-Tracking System Design  
Figure 6 shows a block diagram of the frequency-tracking control proposed in this paper. It mainly consists of a voltage acquisition circuit, a current acquisition circuit, over-zero comparisons, a digital phase locked loop, a frequency measurement module, a dead zone, and an inverter drive module. Figure 5: Voltage and current waveforms when the system is capacitive: (**a**) \(R_{\text{L}}=5\)\(\Omega\), coil distance of 25 cm; (**b**) \(R_{\text{L}}=15\)\(\Omega\), coil distance of 15 cm. In Figure 6, the current acquisition circuit collects the current \(i_{1}(\theta)\) in the emitter loop. The voltage acquisition circuit acquires the system's input voltage \(u_{\text{in}}(\theta)\). The over-zero comparison circuit converts the collected current \(i_{1}(\theta)\) into a square wave signal \(u_{\text{i}}(\theta)\) of the same frequency and phase. The phase-locked loop module tracks the real-time input signal \(u_{\text{i}}(\theta)\) frequency and regulates the output signal \(u_{\text{out}}(\theta)\) frequency and phase angle. It should be ensured that the system is always under a resonating state and has a fixed input phase angle transmitting side. The frequency measurement module obtains the relationship value \(N\) between the frequency of the \(u_{\text{i}}(\theta)\) signal and the system clock frequency \(f_{\text{s}}\) in real-time. The dead time and inverter drive module convert the received \(u_{\text{out}}(\theta)\) signal into a drive signal \(V_{\text{GS}}\) with dead time. The \(V_{\text{GS}}\) signal drives the high-frequency inverter circuit to output the voltage signal \(u_{\text{in}}(\theta)\). Figure 7 is a control strategy block diagram of the digital PLL module in Figure 6. It consists of a digital phase discriminator, digital loop filter, increase or decrease pulse counter, dynamic frequency divider module, frequency measurement module, dynamic phase control module, and phase compensation module. The digital phase discriminator performs a phase comparison between the input signal \(u_{\text{i}}(\theta)\) and the signal \(u_{\text{o}}(\theta)\) fed back from the dynamic divider module. The phase lead signal  
Figure 6: Block diagram of the frequency-tracking system control. Figure 7: Block diagram of frequency-tracking control strategy based on transmitter current and voltage–current phase difference. _ah_ is high when the signal \(u_{\rm o}(\theta)\) is ahead of the signal \(u_{\rm i}(\theta)\), and the phase lag signal _be_ is high when it lags behind. The function of the digital loop filter is to filter out the interference of noise and burr during the transmission of digital signals. It consists of two parts: an add and a subtract counter. The _ah_ signal is high, and the add counter begins to count. When the count is equal to the set value, the emptying counter and the carry signal _inc_ is output. The _be_ signal is high, and the subtract counter begins to count. When the count value is 0, the count value is reassigned, and the borrow signal _dec_ is output. When the _inc_ or _dec_ signal is not received, the increase or decrease pulse counter will divide the system clock by two. When the _inc_ signal is received, the pulse of the output signal increases. When the _dec_ signal is received, the pulse of the output signal decreases. This ensures that the phase difference between the output signal and the signal \(u_{\rm i}(\theta)\) is zero and completes the phase-locking process. The dynamic frequency divider module divides the frequency of the received signal, and the output signal \(u_{\rm o}(\theta)\) feeds back to the digital phase discriminator. The signal \(u_{\rm o}(\theta)\) frequency is determined by the received frequency division factor \(N\). The frequency measurement module consists of a synchronization signal, frequency counting, and 0.1 ms update.