## 4 Hardware Implementation
### Address Generator  
The address generator generates the physical address (i.e., row address, column address and bank address) of the data through the address-mapping rules described in Section 3 and outputs it this address to the MIG IP core to complete the data reading / writing operation, as shown in Figure 16. The calculation method for the address-mapping rules is very complicated--if each data address is calculated with a complete formula, this will produce a large delay, which will affect the real-time performance of the hardware system. In order to solve the above problems, in the address generator, the address generation processing can be simplified by using the physical address change rules for the data in the matrix, and the address generation operation can be accomplished efficiently by simple judgment, addition and subtraction. The module consists of two sub-modules: the address initialization module and the address update module.  
The address initialization module calculates the physical address of the starting position by the parameters provided in the register manager, and calculates the intermediate parameters required for subsequent address generation in the range or the azimuth working mode. The address update module includes a range direction address update module and an azimuth direction address update module that continuously updates the physical address to be accessed and feeds it into the MIG IP core based on the starting physical address calculated by the address initialization module and the required intermediate parameters. Due to the difference between the range direction and azimuth direction in the address calculation method, it is necessary to build two corresponding sub-modules. The process of address generation can be represented by pseudo-codes, as shown in Algorithm 1:  
Figure 16: The architecture of the address generator.  
\begin{table}
\begin{tabular}{c c c c} \hline
**Bit** & **Meaning** & **Type** & **Definition** \\ \hline
0 & work state & read only & 0 = idle; 1 = work \\
1 & start enable & read/write & 0 = wait; 1 = start \\
2 & writing operation & read/write & 0 = invalid, 1 = valid \\
3 & reading operation & read/write & 0 = invalid, 1 = valid \\
4 & range direction & read/write & 0 = invalid, 1 = valid \\
5 & azimuth direction & read/write & 0 = invalid, 1 = valid \\
20 downto 6 & start position (\(x\)) & read/write & 15-bit binary numbers represent the starting position (\(x\)) \\
35 downto 21 & start position (\(y\)) & read/write & 15-bit binary numbers represent the starting position (\(y\)) \\
63 downto 36 & reading/writing length & read/write & 28-bit binary numbers represent the read/write length \\ \hline \end{tabular}
\end{table}
Table 3: Bit definition of the register.  
```
1:\(Address\_initial calculate row\_addr, col\_addr, bank\_addr, subrange\_cnt, subazimuth\_cnt;
2:\(If\ mod=range,then\)
3:\(Address\_initial calculate range\_parameters;\)
4:\(Else\ if\ mod=azimuth,then\)
5:\(Address\_initial calculate azimuth\_parameters;\)
6:Endif
7:\(If\)gen\_en=1,then //gen\_en is an address request signal
8:\(If\ mod=range,then\)
9:\(Address\_update\ row\_addr, col\_addr, bank\_addr;\)
10:\(Else\ if\ mod=azimuth,then\)
11:\(Address\_update\ row\_addr, col\_addr, bank\_addr;\)
12:\(End\)if
13:Endif
```  
**Algorithm 1** The address generation algorithm.