# Greening the NetFPGA Reference Router
## 5 Experiments
### Combined with Other Green Techniques  
Dynamic frequency scaling provides an active performance scaling feature to achieve energy proportional routing, which is the appropriate energy saving approach for network routers given that their connections have to be always on to keep a heartbeat to deal with routing protocols and \begin{table}
\begin{tabular}{c c c} \hline \hline
**Type** & **Average Power (W)** & **Power Savings (\%)** \\ \hline RR & 11.750 & 0\% \\ FSR with STP & 10.565 & 10.09\% \\ FSR with DTP & 10.568 & 10.05\% \\ FSR with PLAP & 10.569 & 10.04\% \\ FSR with DFS, GTEand EPS & 6.321 & 46.04\% \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Average power consumption for the day. DFS, dynamic frequency scaling. Figure 16: Power consumption corresponding to the traffic trace in Figure 14. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Frequency**} & \multicolumn{2}{c}{**STP**} & \multicolumn{2}{c}{**DTP**} & \multicolumn{2}{c}{**PLAP**} \\ \cline{2-7}  & **Time** & **Ratio** & **Time** & **Ratio** & **Time** & **Ratio** \\ \hline
125 MHz & 4 h 29 m & 18.7\% & 4 h 43 m & 19.7\% & 4 h 49 m & 20.1\% \\
62.5 MHz & 9 h 58 m & 41.5\% & 9 h 56 m & 41.4\% & 9 h 47 m & 40.8\% \\
31.3 MHz & 5 h 46 m & 24.0\% & 5 h 47 m & 24.1\% & 5 h 50 m & 24.3\% \\
15.6 MHz & 3 h 17 m & 13.7\% & 3 h 09 m & 13.1\% & 3 h 12 m & 13.3\% \\
7.8 MHz & 0 h 30 m & 2.1\% & 0 h 25 m & 1.7\% & 0 h 22 m & 1.5\% \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Aggregate duration in each frequency mode. PLAP, packet loss-aware policy. unpredictable traffic (e.g., core routers). However, the energy efficiency improvements from dynamic frequency scaling are usually less than those from the Ethernet port shut-down. There are challenges to applying Ethernet port shut-down in core routers because, compared to active performance scaling, it takes more time and power to transition between the on and off state. Predicting the off period and adapting to the appropriate state is still difficult. The end routers, such as home routers, on the other hand, usually follow human behaviour, and Ethernet ports can be shut down when people sleep to achieve more power savings. As indicated in our previous work [25; 30], more power consumption can be saved by re-routing traffic to other ports when traffic on a port is low and turning off the port. Disabling each port can save around 1 W, and turning off the ports at both ends of the connection can result in an overall savings of around 2 W. For the NetFPGA router, turning off all four Ethernet ports can save around 4 W, while scaling down the frequency from 125 MHz to 7.8 MHz while keeping all four Ethernet ports active can save a maximum of only around 2.2 W. Thus, traffic re-routing through network-wide energy-aware traffic engineering coupled with disabling Ethernet ports is a more effective way to reduce power consumption. An Ethernet port shut-down module is integrated into the FSR to disable an Ethernet port when there is no traffic going through the port for a period of time. With this module, the router can save significant power compared to leaving Ethernet ports fully on all of the time. In the Ethernet port shut-down module, several byte counter modules are introduced to count the number of bytes passing through each Ethernet FIFO queue. For a period of time, if there is no traffic to handle for an Ethernet port, the port is disabled until new packets come in. This module provides a way to locally control the Ethernet ports. The Ethernet ports can be also controlled by a network level power management technique. Energy-efficient traffic engineering is a promising network level technique to manage the routing path and to disable as many Ethernet ports as possible without significant packet delay and loss. If a network level technique is involved, network-wide coordination, such as the green abstract layer (GAL) [31], is compulsory. The GAL provides advanced power management capabilities to decouple distributed high level algorithms from heterogeneous hardware.