## 3 Design of Ternary Logic Circuits
### Our Optimized Design of Ternary Adder  
Firstly, for the ternary cycling gates, as we have discussed before, they can operate the increment function (output = input + 1) or decrement function (output = input - 1) which are especially suitable for the ternary adder. However, it requires more than 20 extra transistors to build such a cycling gate in the current existing ternary technology [11], therefore it is not cost-efficient to be applied into the ternary adder. Whereas, in our design, we can generate the ternary decrement cycling logic function by using only two transistors, as discussed in Figure 2e. Hence the DCI can be used in the half-adder to replace the original required AND gates, as shown in Figure 6a. The red dashed box presents our ternary computation method. If the input A = 0, the sum of A + B is B. If the input A = 1, the sum of A + B is B + 1 which needs one ICI gate (or two DCI gates). If the input A = 2, the sum of A + B is B + 2 = B - 1 which needs only one DCI gate. The calculated results are controlled by the transmission gate (1 enhancement-mode N-type transistor) and summarized in a ternary OR gate. Figure 5: Conventional design of ternary half-adder. The ternary input (**A**, **B**) signals are firstly decoded by the ternary decoder (the two blue dashed box regions). Then the signals are transferred to the logic computation unit (red dashed box region). Finally the calculated results are re-transferred to be a ternary signal (green dashed box region) as output. Note: The unlabeled logic gates represent the normal binary logic gate. Next, note that the logic state of carry in the ternary adder (Figure 6c) can only be \"0\" or \"1\". For example, the carry of 0 + 0, 0 + 1, 0 + 2 and 1 + 1 is \"0\", and only the carry of 1 + 2 or 2 + 2 is \"1\". Therefore, it is not necessary to use the full ternary decoder. The improved ternary half adder is presented in Figure 6b. When C is \"0\", the sum is A; when C is \"1\", the sum is A + 1. While the carry is always C1 + A2. Finally, the two as-designed half-adders can be combined into a 1-trit ternary full-adder, as shown in Figure 7a. The operating principle can be explained as follows: Step 1, the input A and B are summed up in the half-adder 1 (blue dashed box) and they then generate the result of AB_sum and AB_carry. Step 2, the AB_sum and the input carry of C\({}_{\text{in}}\) are summed up in the half-adder 2 (red dashed box). The generated result of SUM will be the final summation of A, B and C\({}_{\text{in}}\). Step 3, the two generated carry trits, AB_carry from the half-adder 1 and ABC_carry from the half-adder 2, will be sent into an OR gate, and will generate the final CARRY, which will be a new C\({}_{\text{in}}\) to the next series of full-adder. In Figure 7b, we present the design block diagram of the 19-trit ripple-carry adder, in which A18A17... A1A0 is a ternary number of A input, B18B17... B1B0 is a ternary number of B input,  
Figure 6: (a) Ternary half-adder Design 1, with the cycling DCI gate as the computation part. (b) Ternary half-adder Design 2, with the improved ternary adder algorithm, that the carry of the ternary adder can only be logic “0” or logic “1”. (c) Truth tables of the half adder. S18S17... S1S0 is the output summation result, C18C17... C1 is the Carry, C0 is always 0 and Cout is the overflow bit. By taking advantage of the ternary cycling inverter and the improved ternary adder algorithm, we present a mixed ternary-binary system where ternary gates are used for the calculation of SUM, and binary gates are used for the CARRY. Such design has largely decreased the required number of transistors, in which there are only 72, and 25 transistors are involved in half-adder 1 and half-adder 2, respectively. The total number of transistors in a full-ternary-adder is 99, which is much lower than that of the existing ternary circuits.