# Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers
## 3 Related Works
### Proposed Data Parallelism Technique
#### 4.1.2.1 HIGHT Optimization  
In HIGHT, since the round function operates in units of 8-bit, the lane of the vector register is set to 16-bit to efficiently parallelize in units of 1-byte within 128-bit. Through the above process, 16 encryptions can be performed simultaneously in a total of eight vector registers. In the existing work [10], only 24 encryptions were processed simultaneously on the NEON engine, but we process 48 encryptions simultaneously by efficiently utilizing all vector registers. Figure 9 shows register scheduling for the proposed parallel implementation of HIGHT. The \(v0\)-\(v23\) vector registers are vector registers that store 48 plaintexts, and 16 plaintexts are stored per eight vector registers. The \(v24\)-\(v27\) vector register are Temp registers that store the intermediate values. Finally, the \(v28\)-\(v31\) vector registers maintain round keys. Unlike LEA and revised CHAM, HIGHT performs operations in byte-wise, so it is difficult to remove transpose operations in the overall process. We present an optimized transpose operation. Algorithm 2 is the optimized transpose operations used in the proposed parallel implementation for HIGHT. For the rest of the encryptions, we efficiently interleaved the instructions by minimizing the pipeline stall. Steps 1-14 are the transpose operation performed before encryption, and Steps 15-28 are the transpose operation performed after encryption. In Steps 1-2, the transposed plaintexts are loaded into four vector registers through \(LD4\) instruction. For example, in the \(v0\) vector register, each 0-th and 4-th index word of 8 plaintexts among 16 plaintexts are stored, and in the \(v4\) vector register, each 0 th and 4 th index word from the remaining eight plaintexts are stored. Step 3 is the process of storing the intermediate value, and, in Step 4, each 0 th word of 16 plaintexts is efficiently stored in the \(v0\) vector register through \(TRN1\) instruction. In Step 5, each 4 th word from 16 plaintexts are efficiently stored in the \(v4\) vector register through \(TRN2\) instruction. A total of three more iterations of the above process complete the transpose operation for 16 plaintexts. From Step 15, it is the transpose operation that is performed after encryption is completed and before storing the ciphertexts in memory, and proceeds in the reverse order of Steps 1-14. After the transpose operation is completed, the ciphertexts are stored in memory through \(ST4\) instruction. ```
1:v0-v7(Plaintexts)
2:v0-v7(Ciphertexts)
3:Transpose operation to be performed before encryption
4:LD4 {v0.16b-v3.16b}, {v0}, {v64}
5:LD4 {v4.16b-v7.16b}, {v0}, {v64}
6:MOV v24.16b, v0.16b
7:TRN1 v0.16b, v0.16b, v4.16b
8:TRN2 v1.16b, v1. Algorithm 3 is a round function to which a data parallelism technique is applied in HIGHT. In the HIGHT optimization of [10], both task and data parallelism technique are applied, but Algorithm 3 applies only a data parallelism technique. Our contribution of Algorithm 3 is a data parallelism technique for HIGHT. As data parallelism technique is applied, Algorithm 3 shows a one round function of processing 16 encryptions. The rest of the encryptions were processed using the Temp register through interleaving the NEON instructions. Step 1 loads the round keys required for one round function into vector registers. Steps 3-11 and Steps 27-35 perform \(F_{1}\) Function. Steps 12-14 and Steps 37-38 perform an \(XOR\) operation and then a modular addition by \(2^{8}\), and Steps 25-26 and Steps 49-50 perform a modular addition by \(2^{8}\) and then an XOR operation. Finally, Steps 15-23 and Steps 39-47 perform \(F_{0}\) Function.