## 2 Background
### Organizational Basics of 3D Vertical Nand Flash Memory  
Figure 3 illustrates an organizational difference in a NAND block between 2D NAND flash and 3D NAND flash memory. Although the architecture of 3D NAND flash memory is conceptually described as if multiple 2D NAND flash layers are stacked in a vertical direction [25], the inner organization of 3D NAND flash memory is quite different from this logical explanation. In the example shown in Figure 3, the 2D NAND flash memory has a _2D matrix_ structure in which four WLs and three bitlines (BLs) intersect at 90 degrees. On the contrary, the 3D NAND flash memory has a _cube-like_ structure. The 3D NAND flash block consists of four vertical layers (v-layers) on the y-axis, where each v-layer has four vertically stacked WLs separated by select-line (SSL) transistors. As shown in Figure 3, when the 2D NAND flash block is rotated by 90\({}^{\circ}\) in a counterclockwise direction using the x-axis as an axis of rotation (i.e., if the WLs are set vertically), it corresponds to a single v-layer. Similarly, the 3D NAND flash block can be described as having four horizontal layers (h-layers) stacked along the z-axis, and each horizontal layer consists of four WLs. In order to increase the capacity of a 3D flash chip, the most effective approach is to increase the number of h-layers in 3D NAND flash memory (i.e., stacking more h-layers along the z-axis). As the number of h-layers increases, the block size increases as well (the advanced  
3D NAND flash memory has more than 200 layers, and the capacity of one flash chip reaches 1 Tb [26]).  
To achieve a vertical architecture, the 3D NAND device employs a new revolutionary flash cell structure called charge trap (CT)-type flash cell. Figure 4 shows a flash cell in 3D NAND flash memory. Compared to the flash cell of 2D NAND flash memory shown in Figure 1, the most noticeable innovation is the switch from a floating gate (conductor) to a charge trap layer (non-conductive material) as the space for storing electric charges. The working principles of both cell types are relatively similar, but in a charge trap (CT)-type cell, the trap layer is an insulator (usually silicon nitride, SiN), significantly reducing the electrostatic interference between neighboring cells. (In 2D NAND flash memory, the scaling-down process for achieving a high-capacity NAND flash memory inevitably narrows the physical distance between flash cells, which considerably increases the cell-to-cell interference effect. Since the cell-to-cell interference causes additional bit errors by widening \(V_{th}\) distribution, it is one of the key factors limiting the continuous shrink in 2D NAND flash memory.) This charge trap cell is now the base of most commercial 3D NAND flash memory.  
The channel is created by etching a hole through the stack layers and then forming the transistor structure with the deposition of three layers in order, such as tunnel oxide, charge trap layer (SiN layer), and blocking oxide. After that, the poly-silicon channel fills in the middle of the hole. Finally, the cell gates are constituted by the poly-silicon horizontal  
Figure 3: Illustration of organizational difference between 2D and 3D NAND flash memory.  
Figure 2: \(V_{th}\) distributions of \(2^{m}\)-state multi-level cell NAND flash memory.  
layer (or metal-like composite of tungsten) surrounding the vertical channel forming a Gate-All-Around (GAA) structure, which looks like a macaroni structure.