# Atomic Layer Deposition (ALD) of Metal Gates for CMOS
## 1 Introduction
### Metal Gate and Effective Work Function (EWF)
\[V_{t}=V_{fb}+\frac{|Q_{s}|}{C_{i}}+2\psi_{B}=V_{fb}+\frac{\sqrt{2\varepsilon_{ s}qN(2\psi_{B})}}{C_{i}}+2\psi_{B} \tag{7}\]  
where the \(Q_{s}\) is substrate charge density corresponding to the substrate surface potential of inversion mode (\(2\psi_{B}\)), \(N\) the substrate doping concentration, \(C_{i}\) the gate oxide capacitance, \(\varepsilon_{S}\) the substrate permittivity. The single metal gate is the most straightforward solution, favorable to the CMOS processing. However, this approach is not favorable in device performance. The midgap work function induces high \(V_{t}\) and poor operation channel current. It has to be pointed out that the above conclusion on the single metal solution is true only for planar CMOS using bulk Si substrate. For the devices such as undoped FinFETs and FD-SOI FETs, it is more complex [30; 31]. For the dual-metal gate CMOSFETs, the \(\Phi_{M}\) of the gate electrode for nMOS is expected to be \(\sim\)4 eV and that for pMOS \(\sim\)5 eV [32]. Since the EWF vacuum work function could not be used as the screening criteria, the study of metal gate properties needs to be done in a real gate stack with selected high-\(\kappa\) material and carefully designed stack structure. To reach threshold voltage (\(V_{t}\)) target, extreme care needs to be taken, because \(V_{t}\) is so sensitive to interfacial states that any slight difference in chemical composition, defects and polarization will induce \(V_{t}\) shift. Figure 8: Flatband conditions of MOS structure for n-type substrate. Figure 7: Work function of metals. The thermal stability of the metal gate had been regarded as a fateful technical block for the industrial application of high-\(\kappa\)/metal gate stack. The harshest thermal process in CMOS production is the annealing for dopants activation in the area of source and drain. In most cases, a rapid thermal annealing (RTP) between 900-1100 \({}^{\circ}\)C is employed. The work function of most metals will shift back to midgap after this annealing. This is why the metal gates studied in the early explorations all have good refractory. They include elemental metals, their oxides, silicides, nitrides, carbides or alloys of more than two of them. Most of them, when being in contact with the selected high-\(\kappa\), could not keep stable at high temperature. After the activation annealing, the _EWF_ shifts. To bypass the thermal instability problem, a new processing flow, the gate-last approach, has been developed [25]. In such a process, the high-\(\kappa\) is first deposited, followed by the conventional poly-Si gate process to form a poly-Si \"dummy\" gate. This conventional flow continues until the activation anneal is finished. Then, the poly-Si gate is removed before the deposition of the metal gate layer, capping layer and filling metal. In such a \"replacement gate\" regime, the source/drain activation anneal is carried out before the metal gate deposition and thus successfully avoids the \(V_{t}\) shift related to the activation anneal. In the 45 nm node, the first generation of the high-\(\kappa\)/metal gate technology for mass production, dual metal/single high-\(\kappa\) stack was used. The metal gate for nMOS was TiAl, and that for pMOS was TiN, integrated with HfO\({}_{2}\) dielectric by a gate last process [25; 33] The TiAl and TiN were deposited in the trench on the bottom after the replacement gate removal. To fill the gap, a conductive metal such as Al or W was deposited. TiN in the stack with HfO\({}_{2}\) has a _EWF_ range between 4.4 and 4.9 eV, depending on processing technique used and the metal layer thickness [34; 35] and meets the requirement for pMOS. TiN is a widely used material in conventional IC process, so induces no contamination risk. Its deposition, etching and cleaning techniques are well developed using industrial standard equipment. During 2003-2006, a lot of works presented at device conferences on the integration technology used high-\(\kappa\)/TiN metal gate stack, where TiN were deposited by PVD or CVD [36; 37; 38; 39; 40; 41; 42].