# A Multi-Channel Data Simulator Based on the Time Unification System
## 6 Conclusions  
In this study, a multi-channel data simulator based on a time unification system is proposed. The proposed simulator has programmable input and output interfaces for multi-channel protocols, allowing for the simulation and storage of high-speed and low-speed data and control signals. The proposed simulator has two working modes: storage mode and real-time mode. In the storage mode, the simulated data on the host computer are transmitted to the simulator's storage before simulation. Each interface channel sends data streams and control signals to the target system according to the time reference generator, while the simulator simultaneously stores the results output by the target system. In the real-time mode, the host computer generates simulated data and outputs them through the simulator in real time, based on the results of the target system. The data simulator proposed in this study can achieve 4.2 Gbps of simulated data transmission and 1.6 Gbps of data reception and storage, with a closed-loop delay of 39.9 us.  
However, the host computer requires a certain amount of time to generate simulated data. In future work, in order to meet the needs of low-delay data generation, some of the simulated data generation steps of the host computer can be deployed to the simulator to reduce the delay in data generation. Moreover, using a real-time operating system such as RT-Linux in the host computer could reduce the effect of background tasks on the UDP packet parsing delay in the real-time mode.  
J.Y.: data curation, formal analysis, investigation, methodology, software, validation, and writing--original draft; R.D.: conceptualization, funding acquisition, methodology, and writing--review and editing; X.W.: writing--review and editing; J.X.: writing--review and editing; J.L.: writing--review and editing; N.W.: visualization and writing--review and editing; L.L.: supervision and writing--review and editing. All authors have read and agreed to the published version of the manuscript.  
This work is supported by National Science and Technology Major Project (2021 ZD0109801), National Natural Science Foundation of China (62334008, 62274154, U21A20504) and Youth Innovation Promotion Association Program Chinese Academy of Sciences (2021109).  
Not applicable for studies not involving humans or animals.  
Not applicable for studies not involving humans.  
The original contributions presented in the study are included in the article; further inquiries can be directed to the corresponding author.  
The authors would like to thank the anonymous reviewers for their valuable comments and suggestions.  
The authors declare no conflicts of interest.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Item** & **[PERSON]** & **[PERSON] et al. [8]** & **[PERSON] et al. [9]** & **[PERSON] et al. [11]** & **[PERSON]** **et al. [14]** \\ \hline High-speed output bandwidth & \(3\times 1.6\) Gbps & \(6\times 1.6\) Gbps & \(6\times 1.6\) Gbps & \(2\times 300\) Mbps & \(6\times 6.25\) Gbps \\ High-speed input bandwidth & \(1\times 1.6\) Gbps & - & - & \(8\times 400\) Mbps & \(6\times 6.25\) Gbps \\ Simulated data storage & \(2\times 5\)ATA3,0 & NI-8261 & DDR4 & DDR4 & - \\ Storage capacity & MAX 8 TB & MAX 2.9 TB & 4 GB & 4 GB & - \\ Closed-loop delay & 39.9 μs & - & - & - & 400 us \\ Host computer interface & PCIe +10 GbE & PXle & PCIe & PXle & PXle \\ Time synchronization & Yes & No & No & No \\ \hline \hline \end{tabular}
\end{table}
Table 1: Performance comparison of the simulator.