## 2 Materials and Methods  
### Circuital Model for Evaluating the Conducted Emission  
In order to provide to the designers simple and effective tools for simulating the impact of an IC on the EMC performance of a complex system made by an IC, package, and PCB, suitable equivalent circuital models have been proposed over the years. A first attempt to provide an IC circuit model was the so-called IBIS model, based on the \"_Input/output buffer information specifications_\", hence, on the characterization of the electrical performance at the terminal pins of an IC [13]. This model has the advantage of simplicity, but shows major drawbacks coming from the lack of inclusion of main phenomena, such as the switching noise and the load effect of the PCB. An enhanced circuital model for the IC conducted emission has been proposed, for instance, in [14], based on the so-called \"_linear equivalent circuit and current source_\" model. More recently, the International Electrotechnical Commission proposed the so-called Integrated Circuit Emission Model (ICEM), with the purpose to accurately take into account the internal activity of the ICs [15; 16]. The ICEM model has been successfully used over the years to carry out performance analysis of ICs, in terms of emission, immunity, jitter, and so on [9; 17; 18]. The limitation of this model in terms of maximum operating frequencies can be easily removed, as recently shown in [8], by taking into account the effects of the loads (specifically the transmission lines of the PCB) with a distributed model. This paper adopts the latter approach to derive a circuit model in the frame of the ICEM standard. Specifically, the high-frequency behavior of the PCB is described by exploiting its S-parameter characterization. The conceptual scheme of the adopted approach is reported in Figure 1, showing the overall circuit as composed of four main subparts: the first subpart (internal activity, IA) describes the core and the I/O buffers, the second one describes the package, whereas the third one refers to the printed circuit board (PCB). The final subpart represents a generic load that simulates a buffer that exchanges data with the IC. The above subdivision is based on the features of the circuit models to be adopted for the different subparts: for the IA the circuit is active and lumped, for the IC it is passive and lumped, whereas for the PCB it is passive and distributed. According to the ICEM model [16], the first subpart is modelled as in Figure 2, where the core activity is represented by an equivalent current source \(I_{core}\), and the parasitic of the supply rails are given by series impedance R-L, \(Z_{dd}\) and \(Z_{ss}\), which also separates the decoupling into two contributions: \(C_{d}\), between \(V_{dd}\) and \(V_{ss}\), and \(C_{b}\), close to the current generator \(I_{core}\). The core model is coupled to the I/O buffer, which is described here by means of an IBIS model [13]. In the IC analyzed in this paper, the core supply and the I/O supply are separated and, thus, according to the ICEM rules [16] the coupling model must contain a substrate impedance \(Z_{sub}\), and an additional decoupling capacitor \(C_{I/O}\). The \(V_{dd}\) and \(V_{ss}\) pins at the left and right side of Figure 2 are connected to the corresponding pins of the package. Each I/O pin is connected to the corresponding signal interconnect at the package and the PCB level, as shown in the circuit model in Figure 3, which also reports the parasitics for the package interconnects and the equivalent circuital models for the PCB traces. In this paper, as specified in Section 3, the IA circuit model has been obtained from a transistor-level simulation. Alternatively, a characterization based on measurements can be carried out, following the standards set in [19]. The advantage of this approach is that no internal description of the IC is required, but the main disadvantages are the need to de-embed the text-fixture and the impossibility to directly measure the current \(I_{core}\).