# Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection
## 4 CMOS Transimpedance Amplifier (TIA)
### Common-Gate-Based TIA  
As discussed in the previous section, a resistor-based TIA suffers badly from the gain-bandwidth tradeoff, which results in a limited achievable SNR. In order to overcome the disadvantage, a common-gate (CG) topology has been widely used.  
The basic CG amplifier as a TIA is illustrated in Figure 22. Assuming a dominant pole is located at the input, the gain, \(R_{T}\), and the bandwidth, \(f_{-3 dB}\), are expressed as follows:  
\[R_{T}=R_{1} \tag{8}\]  
\[f_{-3 dB}=\frac{g_{m1}}{2\pi C_{PD}} \tag{9}\]  
Note that the gain-bandwidth tradeoff is now completely eliminated, indicating that the gain can be improved without degrading the bandwidth significantly.  
Even if the SNR can be enhanced by employing the CG TIA, a direct tradeoff between the bandwidth and the power consumption exists, which limits the use of the CG TIA in the present  
Figure 21: Simple implementation of TIA using single resistor.  
Figure 22: Common-gate TIA.  
configuration. Alternatively, a regulated-cascode (RGC) TIA shown in Figure 23 can further improve the bandwidth by lowering the input resistance [71]. The gain of the RGC TIA is the same as that of the CG TIA and the bandwidth is given by (with the same dominant-pole condition):  
\[f_{-3 dB}=\frac{g_{m1}(1+g_{m2}R_{2})}{2\pi C_{PD}} \tag{10}\]  
With linearly increasing \(I_{B}\), \(g_{m}\) and thus \(f_{-3 dB}\) are increased approximately by the square of \(g_{m}\), thereby alleviating the direct tradeoff between bandwidth and power consumption. Owing to their clear advantage, many TIAs based on the RGC topology have been proposed. The bandwidth of the RGC TIA can be further enhanced by combining a shunt-shunt feedback [72] and a differential RGC TIA can also be configured [73]. Recently, RGC-based TIAs have been successfully demonstrated with operating speed higher than 25 Gb/s [54; 56; 74].  
Despite the advantages of the RGC TIA, it is not suitable in the recent CMOS trend wherein the supply voltage is aggressively scaled down, because it suffers from a small voltage headroom due to stacking of the two NMOS transistors. Specifically, the output voltage, \(V_{out}\), in Figure 23 has to accommodate the gate-source voltage of M\({}_{2}\), the drain-source voltage of M\({}_{1}\), and the voltage across R\({}_{1}\). The output of the common-source (CS) amplifier, \(V_{2}\), also has to accommodate the gate-source voltages of M\({}_{1}\) and M\({}_{2}\), and the voltage across R\({}_{2}\). These conditions render the RGC TIA inapplicable to sub-1 V CMOS technologies.  
As an alternative, a CG-feedforward TIA illustrated in Figure 24 is proposed in [75], achieving a wider bandwidth and relaxing the voltage headroom simultaneously. Furthermore, the gain of the CG feedforward TIA is approximately the same as that of the CG and the RGC TIA. The bandwidth can be calculated as:  
\[f_{-3 dB}=\frac{g_{m1}(1+g_{m2}g_{m3}R_{2}R_{3})}{2\pi C_{PD}} \tag{11}\]  
The bandwidth is significantly enhanced than the RGC TIA and the voltage-headroom problems are also greatly mitigated. By employing this topology, the work in [75] achieves a considerably high bandwidth of 20 GHz in the standard CMOS platform.  
Figure 23: Regulated-cascode TIA.