## 3 System Design with Simulation and Experimental Results
### System Simulation and Experimentation
#### 3.3.2 Experimental Test  
Based on the above analysis and the BER simulation results in Section 3.3.1, this paper implements a UV communication system incorporating optimized 4 FSK modulation algorithm and LDPC error-correcting code. The system block diagram is shown in Figure 9.  
At the TX side, a low-pressure mercury lamp is employed as the optical source, and the TX-PC generates information and performs LDPC encoding on the data. At the RX side, the H10720-113 photomultiplier tube (PMT) from Hamamatsu Photonics (Hamamatsu, Japan) acts as a photodetector, converting ultraviolet (UV) light signals into electrical signals. The PMT output is processed through a transimpedance amplifier circuit, which converts the current signal to a voltage signal and amplifies it. The signal is then digitized by an analog-to-digital converter (ADC) module, which transmits the sampled data to an xc7k325 ffg-676 FPGA chip (XLINX, San Jose, CA, USA). FPGA implements threshold-based photon pulse detection by comparing sampled data against predefined thresholds, performs pulse counting, and executes channel estimation and cross-correlation calculations for data demodulation. The demodulated data are transmitted via UART to the receiving PC, where LDPC decoding is completed by the RX-PC module. Figure 8: BER of different systems under different noise levels: (**a**) \(\lambda_{b}=0.0003\); (**b**) \(\lambda_{b}=0.00015\); (**c**) \(\lambda_{b}=0.00001\). During the experiment, we first characterize the signals of the transmitter and receiver using an oscilloscope, as shown in Figure 10. In Figure 10, subplot (a) displays the carrier signal output from the FPGA of the transmitter. Subplot (b) presents the carrier signal output from the modulation circuit of the transmitter. Subplot (c) illustrates multiple electrical pulse signals at the receiver circuit output. By analyzing Figure 10a, it is observed that when the FPGA outputs a logic '1', the receiver circuit generates discrete electrical pulses; conversely, when the FPGA outputs a logic '0', the received pulses become negligible. Subplot (d) shows a single electrical pulse from the receiver, revealing a pulse duration of approximately 20 ns. To evaluate the communication performance of the system, field tests were conducted. These tests were divided into non-line-of-sight (NLOS) and line-of-sight (LOS) scenarios, with Table 1 presenting the experimental parameters. Figure 10: Different signal tests: (**a**) carrier signal from FPGA; (**b**) carrier signal from modulation circuit; (**c**) signal from PMT amplifier circuit; (**d**) single-photon pulse. Figure 9: Block diagram of UV communication system based on 4 FSK modulation and LDPC optimization. During NLOS testing, the transmitter and receiver were separated and placed on opposite sides of the obstacles, including vehicles and trees, such that communication could only be established through UV light scattering. The experimental equipment and test scenario are shown in Figure 11.  
In Figure 11, UV-TX represents the entire transmitting system, and UV-RX represents the entire receiving system. TX-PC and RX-PC are the computers at the transmitting end and the receiving end, respectively. The DC power supply is a direct-current power supply, which is responsible for generating the voltage and current required by the system. The portable power bank is a mobile power source that supplies power to the DC voltage source. The distance between the transmitter and the receiver was 60 m in the NLOS communication test. The elevation angle of the receiver was fixed at 45\({}^{\circ}\), while transmitter elevation angles were sequentially adjusted to 10\({}^{\circ}\), 20\({}^{\circ}\), 30\({}^{\circ}\), and 45\({}^{\circ}\) to evaluate system performance under different beam orientations. To investigate the optimization effect of LDPC code, the BER comparison test between the 4 FSK system and the 4 FSK-LDPC system were conducted.