# Compensation of Limited Bandwidth and Nonlinearity for Coherent Transponder
## 2 Principle  
Figure 1 shows a typical coherent IQ transmitter which consists of the digital signal processing (DSP) application specific integrated circuit (ASIC) and the analog coherent optics (ACO). The layer of forward error correction (FEC) adds the overhead error correction. Next, an FIR filter in the tap-and-delay structure compensates the limited bandwidth. The FIR filter is \(T_{s}\)/2 spaced, where \(T_{s}\) is the symbol period. A high-speed DAC converts the output of the FIR filter from the digital domain to the analog domain. It is also possible to implement a nonlinear equalizer like the Volterra filter to mitigate the nonlinearity. The analog electrical signal goes through the traces on the radio-frequency (RF) print circuit board (PCB), the pluggable interface (if applicable), the linear RF amplifiers and then are finally applied to the MZM. The DAC, the RF trace on the PCB, the pluggable connector, the RF electrical amplifier, and the MZM contribute to the limited bandwidth. The intrinsic transfer function of MZM in the form of sinusoidal function and the nonlinear amplitude response within the data path contribute to the nonlinearity. Also, an onboard random-access memory (RAM) can be implemented in the DSP ASIC for testing and diagnosis. During the initial calibration, one can load RAM with the desired data pattern, and set the output of the DAC according to the content in the RAM. After the initial calibration, one can switch back to the regular data path. We utilize this feature to demonstrate our technique. Initially, during the power-up, we load the RAM with a sinusoidal stimulus to one tributary at a time and write 0 to the other tributaries. Thus, the output is from the tributary with the stimulus. Then, we can apply the following equation  
\[P_{out}=P_{stdy}\cos^{2}\Bigl{(}0.5\pi(V_{swing}/V_{\pi}+V_{bias}/V_{null}) \Bigr{)}, \tag{1}\]  
here \(P_{out}\) is the output from the IQ transmitter, monitored by a low-speed photodiode (PD). \(P_{stdy}\) is the steady-state power of the tributary under stimulus, \(V_{swing}\) is the voltage applied to the MZM, \(V_{\pi}\) is the voltage achieving \(\pi\) phase shift, \(V_{bias}\) is the bias voltage applied to MZM, \(V_{null}\) is the bias voltage required for the null point (corresponding to \(\pi\)/2 phase shift), \(cos^{2}()\) is the intrinsic transfer function of the MZM. \(V_{DAC}\) is the maximum output voltage of the DAC, \(IL_{RF}\) is the insertion loss of the RF traces, \(Gain_{AMP}\) is the gain of the RF amplifier, \(BW_{MZM}\) is the bandwidth of the MZM. The parameters above are frequency-dependent and thus contribute to the limited bandwidth. \(N_{sig}\) and \(\omega\) are the amplitude and frequency of the sinusoidal stimulus. \(Bit_{DAC}\) is the number of bits of the high-speed DAC, where the first bit is a sign bit. Consequently, \(V_{swing}\) can be expressed as the following:  
Figure 1: The block diagram of the coherent IQ transmitter and the DSP ASIC. PS: phase shifter, Pol-Rot: polarization rotator. DAC input can be switched between RAM and regular path. \[ \begin{array}{l}V_{swing}=N_{sig}\sin(\omega t)*V_{DAC}(\omega)*IL_{RF}(\omega)\\ *Gatin_{AMP}(\omega)*BW_{MZM}(\omega)/2^{(Bit_{DAC}-1)}\end{array} , \tag{2}\]  
Furthermore, we define the normalized signal amplitude \(x\), the bandwidth factor \(\alpha\), the bias factor \(\beta\), and the MZM phase shift \(\varphi_{MZM}\). The output from the MZM is expressed as  
\[ \begin{array}{l}x=N_{sig}/2^{(Bit_{DAC}-1)},x\in[0,1),\\ \alpha_{\omega}=V_{DAC}*IL_{RF}*Gatin_{AMP}*BW_{MZM}/V_{\pi},\\ \beta=V_{bias}/V_{null}\\ \phi_{mzm}=0.5\pi\alpha_{\omega}x\sin(\omega t),\\ P_{out}(\omega,x)=P_{stdy}\cos^{2}(\phi_{mzm}+0.5\pi\beta)\end{array} , \tag{3}\]  
The nonlinear amplitude response is not included in Equation (3). In [15; 16], the nonlinear response is treated as a quadrature term in \(x\).