# The Eye-Opening Arbiter-PUF FPGA Implementation with Auto Error Detection
## 3 Eliminating Deterministic FPGA Routing Delays to Avoid EoA-PUF Bias
### Source of Entropy--Delay Element Design on FPGA  
The entropy source of arbiter-, RO-, and EoA-PUFs consists of two identically routed paths of multiple SDEs, each featuring a nominally identical delay, which must only differ by mismatch, not deterministically by design. On FPGAs, this becomes especially challenging if cross-coupling (needed for strong PUFs and CRPs) is required. Thereby, it is practically impossible to find crossing wires with nominally identical and therefore symmetrical delay. To overcome this problem, the internal structure of FPGA Lookup Tables (LUTs) is used to switch two individual delay elements between two delay paths. The implementaton of the crossing path of the SDE in Figure 1a, replicated in Figure 4a, is challenging on FPGAs. In [15; 22], routing for cross-coupling in weak PUF-cells was presented, with almost identical delay. Nevertheless, for some wires, a remaining difference up to 48 ps was reported [22]. In an oscillating architecture like the EoA-PUF, such a difference would sum up with every oscillation, leading to a bias in the final response. In [10] the authors exploited internal delay differences of LUTs, arranged in two parallel paths, to design an arbiter-PUF without crossing connections in the entropy source. Therefore, inspired by the work of [10], the crossing paths are split into two identical parallel paths with two switchable delays each; see Figure 4b. Instead of swapping the delay elements between paths, each path swaps internally between two mismatched delay elements, which we will call half-SDEs (H-SDEs). Due to a following multiplexer, the challenge signal can still select which element is currently evaluated. As LUTs are used in FPGAs to implement buffers, the internal structure of these LUTs is adopted to simplify the hardware realization. This is visualized in Figure 4c. The input to the SDE selects the output value along paths through the LUT, while the challenge input, connected to the last multiplexer, selects which mismatched path to use. The LUTs, implementing the SDEs, can be connected identically in the parallel delay chains in Figure 1. The same principle was used in [10; 20]. This comes with the additional advantage that the architecture can be easily ported to other FPGAs. Meanwhile, [22] (Table 1) reported that, by switching to a different FPGA, the expected delay of their symmetric routing increased by up to a factor of 43, rendering it an asymmetric switching; by using the proposed H-SDE-elements, such delay will alter the expected delay in both paths by the same amount, canceling them out. In order to validate this SDE implementation based on LUTs, 64 H-SDEs (see Figure 4c) were realized and connected as ROs at 40 different locations on an exemplary ZYNQ board. Then, challenge input vectors were applied to the H-SDEs, which differed only in one bit, to the vector they are compared with, and thus changed the internal delay path of a single element at a time. Then, the resulting mean frequencies were measured and the delay difference was extracted. The distribution of 10,000 evaluated measurements, each repeated 500 times to average out noise, is displayed in Figure 5. Two observations can be derived from these measurements. First, it can be seen that the change in a single challenge bit from 0 to 1 on average speeds up the propagation of a single RO. It seems reasonable to assume that this deterministic difference is caused by internal LUT layout asymmetries as the 7 ps is clearly a deterministic offset value. Process variation, on the other hand, is not likely to cause this deviation because the offset must be closer to 0 ps due to statics. However, since the manufacturer does not provide any information about the internal structure or layout, no final explanation can be found. Second, the delay difference by flipping a single challenge bit follows the expected Gaussian distribution.