# Online Signature Verification Systems on a Low-Cost FPGA
## 5 Experimental Results  
### Speed Processing  
The execution times, expressed in clock cycles, for the three implementations are experimentally obtained and shown in Table 2 at each of the stages of the algorithm. These results represent the average execution time obtained from all the available signatures of a single user. The execution times are not dependent on the presented signature, except a slight variation in the features extraction stage due to the different warping paths used to compute the pseudo-distances, which is negligible in the total execution time. Between brackets, the speed-up factors of the last two implementations are reported when compared with the embedded system. The table also shows the execution time in milliseconds at the clock frequencies used in the implemented systems, according to the synthesis results. The total execution time is clearly dominated by the DTW stage since it requires both calculations on large matrices and square root operations. Experimental results show that the speed-up factors are \(\times\)7.6 and \(\times\)201 for the FPBA and custom system, respectively. The acceleration of the custom DTW circuit is very noticeable due to the high throughput achieved when calculating \(g(i,j)\) (one computation per clock cycle). As stated in Section 1, there is a lack of online signature systems on FPGAs. However, we can compare the acceleration of the execution time of our custom DTW circuit against other DTW-based FPGA accelerators in Table 3. The 3D-DTW accelerator [3] for action recognition is designed to be connected to the ARM microprocessor embedded in the target Zynq-7000 device, a high-performance SoC from Xilinx. The core running at 100 MHz \begin{table}
\begin{tabular}{c c c c} \hline \hline  & \begin{tabular}{c} **MicroBlaze** \\ **Embedded System** \\ **40 MHz** \\ \end{tabular} & \
\begin{tabular}{c} **FPBA and** \\ **Embedded System** \\ **40 MHz** \\ \end{tabular} &
\begin{tabular}{c} **Custom** \\ **System** \\ **50 MHz** \\ \end{tabular} \\ \hline \multirow{2}{*}{Pre-processing} & \(\begin{array}{c}236.80\times 10^{3}\\ 5.92\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}36.47\times 10^{3}\) (\(\times\)6.5) \\ 0.91\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}1.38\times 10^{3}\) (\(\times\)171.6) \\ 0.028\mathrm{\ ms}\end{tabular} \\ \hline \multirow{2}{*}{DTW} & \(\begin{array}{c}4786.80\times 10^{3}\\ 119.7\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}632.64\times 10^{3}\) (\(\times\)7.6) \\ 15.8\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}21.87\times 10^{3}\) (\(\times\)218.8) \\ 0.437\mathrm{\ ms}\end{tabular} \\ \hline \multirow{2}{*}{Features extraction} & \(\begin{array}{c}15.15\times 10^{3}\\ 0.38\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}2.92\times 10^{3}\) (\(\times\)5.2) \\ 0.073\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}1.76\times 10^{3}\) (\(\times\)8.6) \\ 0.035\mathrm{\ ms}\end{array} \\ \hline \multirow{2}{*}{GMM} & \(\begin{array}{c}146.26\times 10^{3}\\ 3.66\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}11.54\times 10^{3}\) (\(\times\)12.7) \\ 0.29\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}0.75\times 10^{3}\) (\(\times\)195) \\ 0.015\mathrm{\ ms}\end{array} \\ \hline \multirow{2}{*}{Total} & \(\begin{array}{c}5185.01\times 10^{3}\\ 129.6\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}683.57\times 10^{3}\) (\(\times\)7.6) \\ 17.1\mathrm{\ ms}\end{array}\) & \(\begin{array}{c}25.76\times 10^{3}\) (\(\times\)201.3) \\ 0.515\mathrm{\ ms}\end{array} \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Execution times, expressed in clock cycles (speed-up factor) and milliseconds. can accelerate the execution time \(\times 40\) times faster than the software counterpart. A closer comparison can be achieved with the 2D-DTW accelerator for embedded platforms [26]. As the previous accelerator, it is designed to be connected to an ARM microprocessor on a Cyclone V device from Altera, achieving a \(\times 7.5\) speed-up running at 60 MHz.