# High-Efficiency, Low-Power, Fully Integrated Neural Electrical Stimulation Circuit
## 5 Conclusions  
This paper presents a low-power, high-efficiency, high-voltage (12.69 V) neural electrical stimulation circuit implemented solely using low-voltage devices under the standard CMOS process. A negative-voltage-based series-parallel charge pump was proposed to generate high voltage for the stimulation system. Compared to conventional charge pumps, this structure achieves higher voltage gain with fewer stages and a smaller area while maintaining high power efficiency. Additionally, compared to other high-voltage-generation circuit structures used in neural stimulation circuits, it exhibits a lower output voltage ripple. A stacked transistors structure was used to implement the output driver circuit. Utilizing the different output voltage levels from the high-voltage-generation circuit, the devices of the output driver circuit were ensured to operate within their voltage limit. Simulation results show that at a maximum current load of 1 mA, the efficiency of the high-voltage-generation circuit is 74.9%, and the output voltage ripple is 0.244%. The output voltages are 4.20, 7.02, 9.86 and 12.69 V. The standby power consumption of the entire simulated system is 66 pW. High-voltage output functionality can be achieved through the output driver. The maximum efficiency of the entire system is 59.5%.  
The designed neurostimulation circuit can be used in practical applications to form a completed brain-computer interface system by working with multiple systems, such as wireless charging circuits. Implanted in the brain, the circuit can be used to inhibit neurological disorders such as epilepsy by injecting a specified amount of electrical charge into the neural tissue to stimulate a physiological response.  
Conceptualization, Y.W.; Methodology, Y.W.; Software, Y.W.; Validation, Y.W.; Formal analysis, Y.W.; Investigation, Y.W.; Resources, Y.W.; Data curation, Y.W.; Writing--original draft, Y.W.; Writing--review & editing, Y.W. and J.C.; Visualization, Y.W.; Supervision, J.C.; Project administration, C.L.; Funding acquisition, C.L. All authors have read and agreed to the published version of the manuscript.  
This research is supported by Lingang Laboratory Key Project LG-GG-202402-05-02.  
Not applicable.  
The original contributions presented in the study are included in the article, further inquiries can be directed to the corresponding author.  
Author [PERSON] was employed by the company MTRIX Corporation. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.  
\begin{table}
\begin{tabular}{l l l l l l} \hline  & **This Work** & [19] & [20] & [21] & [22] \\ \hline Vout & 12 V & N/A & 12.5 V & 11 V & 12.3 V \\ \hline Stimulation current & 4 \(\mu\)A–1 mA & \textless{}10 mA & 2.1 mA & 160 \(\mu\)A & 0.2–3 mA \\ \hline Standby power & 66 pW & N/A & N/A & 20.3 \(\mu\)W & N/A \\ \hline Stimulator peak efficiency & 59.5\% & 68\% & 48\% & 11\% & 56\% \\ \hline CMOS technology & 0.18 \(\mu\)m & 0.18 \(\mu\)m & 0.18 \(\mu\)m & 65 nm & 0.18 \(\mu\)m \\ \hline \end{tabular}
\end{table}
Table 2: Performance summary of proposed neural stimulation system.