## 3 Results and Discussion
Figure 7: An exemplary thermal image of NGB8207 BN transistors soldered in a batch oven. As was assumed, the reason for the increase in \(R_{th}\) could be the increase in voids in the solder joints. Empty spaces in a metal structure could act like insulation. However, interestingly, the voids ratio did not correspond to the results of \(R_{th}\) measurements. The highest \(R_{th}\) values were observed for the samples soldered in a VPS oven and manually with hot air. It suggested that the voids ratio in the solder joint, up to a threshold of 30%, was not a crucial parameter affecting the thermal management of the IGBTs. The worst VPS results were not caused by the limiting effect of the vapour on the possibility of effective flux outgassing during the soldering process, as was suspected. The increase in \(R_{th}\) values was probably caused by the microstructure changes in the solder joint. Typically, the SAC solder joints are composed of the \(\beta\)-Sn matrix and intermetallic compounds (IMCs), such as Cu\({}_{6}\)Sn\({}_{5}\), Cu\({}_{3}\)Sn, and Ag\({}_{3}\)Sn [23]. IMCs presented both in the solder bulk as isolated dissolved islands and as an IMC layer (typically Cu\({}_{6}\)Sn\({}_{5}\)) between Cu pad and solder alloy. The microstructure, especially IMC presence, changed the thermal and electrical parameters of solder joints. \begin{table}
\begin{tabular}{c c} \hline \hline
**Soldering** & **Average Void Ratio (\%)** \\ \hline Batch oven & 6.9 \(\pm\) 1.5 \\
3-zones tunnel oven & 12.8 \(\pm\) 6.7 \\
4-zones tunnel oven & 30.9 \(\pm\) 4.9 \\ Vapour phase oven & 11.2 \(\pm\) 4.6 \\ Hot air soldering & 3.6 \(\pm\) 2.2 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Voids percentage area. Figure 8: X-ray images of the solder joints under the IGBT: (**a**) batch oven, (**b**) 3-zones tunnel oven, (**c**) 4 zones tunnel oven, (**d**) vapour phase oven, (**e**) hot air soldering. The structure of the solder joints can be seen in Figure 9. It can be described \"a sandwich\" structure, with upper and bottom parts. The upper part meant the interface between the component (transistor) and the solder joint, the bottom part corresponded to the interface between the solder joint and the FR4 substrate. According to the statistical evaluation, the thickness of the solder joints was 122.1 \(\pm\) 12.6 \(\upmu\)m. Both interfaces contained a Cu layer, which takes part in the formation of IMC layers. The microstructural analysis of the solder joints can be seen in Figure 10. Generally, the microstructure of the solder joints was similar, but some differences also occurred. The IMC layer was the thickest in the case of the batch oven (Figure 10a). It reached 3 \(\upmu\)m at the upper side of the solder joints; in the other cases, the typical thickness was under 2 \(\upmu\)m on both sides of the solder joint. A high amount of agglomerated Ag\({}_{3}\)Sn was found at \(\beta\)-Sn grain boundaries in the case of the 4-zones tunnel oven (Figure 10c). This is unusual in the case of a low-Ag content solder alloy. In the other cases, only evenly distributed Ag\({}_{3}\)Sn dots are visible at the Sn grain boundaries. According to the distribution of the Ag\({}_{3}\)Sn IMCs, the size of the \(\beta\)-Sn grains can be approximated (since the Ag\({}_{3}\)Sn IMCs are located at the grain boundaries [14]). The \(\beta\)-Sn matrix was the finest (<20 \(\upmu\)m) in the case of the 3-zones tunnel oven. Soldering in the batch oven and the hot air soldering resulted in an average grain size of around \(\sim\)20 \(\upmu\)m. The largest grains (>40 \(\upmu\)m) were observed for the samples soldered in a 4-zones tunnel oven and with vapour phase soldering. The number of dispersed Cu\({}_{6}\)Sn\({}_{5}\) islands was the highest in the case of the batch oven and the hot air soldering. In the case of the hot air soldering, Kirkendall voids were found in the lower interface of the Cu base and the IMC layer, which could have formed due to the rapid heat flow into solder joints (Figure 3).