# A Multi-Channel Data Simulator Based on the Time Unification System
## 4 The Design of the Multi-Working Mode  
The simulator needs to adopt different operating modes for simulation testing depending on the phase of the whole system's development process. In the early stages of the development of the target system, it is necessary to verify the system's operational timing. The system's operational timing can use the stored simulated data to for verification. In the later stages of the target system's development, it is necessary to change the input data in real time based on the target system's output. The simulator has a real-time operation mode, which enables it to perform the complete closed-loop verification of the system's operation. Figure 4: The simulator’s time-unified structure in the real-time mode. The simulator requires unified clocking and multi-channel interface processing. The use of a Field-Programmable Gate Array (FPGA) can effectively achieve the data synchronization and conversion of multiple ports. The FPGA structure of the simulator is shown in Figure 5. It includes DMA modules, PCIe control modules, PPS control modules, data FIFO modules, data switching modules, UDP protocol modules, and PPS, PCIe, 10 GbE, DDR, SATA, input and output interface modules. The DMA module handles data transfer between PCIe, SATA, data FIFO, and DDR, achieving the reading and writing of simulated and result data. The PCIe control module controls the DMA transfer according to the control commands from the host computer and configures the parameters of the PPS control module, enabling the sending of simulated data with variable cycles and delays. The PPS control module controls the data FIFO module's data transmission timing and outputs the PPS signal to the target system and host computer. The data FIFO module sends simulated data in a fixed sequence under the control of the PPS control module. The data FIFO also buffers the received result data and waits for the DMA to write them into the SATA solid-state storage. The data switching module gates different data transmission and reception paths under different operating modes of the simulator. The UDP protocol module implements the ARP and UDP protocols, enabling UDP communication with the host computer, receiving and sending simulated and result data in real time, and sending fixed UDP data packets triggered by the PPS. In storage mode, the host computer first uses the PCIe interface to ping-pong write the data to be transmitted to the DDR and then writes the data from the DDR to the SATA solid-state storage. When sending simulated data, the simulator reads the data from the SATA solid-state storage into the DDR and controls the period and delay of the DDR output to the high-speed output interface through the time reference signal input from the internal timer or external PPS interface, achieving a stable simulated data output. When receiving result data, the input interface receives the high-speed result data generated by the target system; it then ping-pong buffers the result data into the DDR and writes the data from the DDR into the SATA solid-state storage. When the host computer needs to use the result data, the simulator reads the stored data from the SATA solid-state storage into the DDR and then uploads them to the host computer via the PCIe interface. In real-time mode, the simulator first triggers the 10 GbE interface to send fixed UDP packets to the host computer through the time reference signal input from the PPS interface. After receiving the UDP packets corresponding to the PPS, the host computer sends  
Figure 5: The FPGA design structure of the simulator. simulated data in parallel through different UDP ports. Upon receiving the data packets, the simulator parses the UDP packet information and then outputs the simulated data within the packets to the target system through the output interface. After the simulator input interface receives the result data from the target system, it packages the data into UDP packets and then sends them to the host computer through the 10 GbE interface.