## 3 DC Link Capacitance Sizing  
In order to assure correct functionality of the converter in Figure 2,  
\[\left|\overset{\rightarrow}{v}_{RST}(t)\right|\leq v_{DC1,2}(t) \tag{12}\]  
must hold instantaneously due to boost AC-to-DC (or buck DC-to-AC) topology of the latter. Combining the expressions of \(R\)-phase voltage (cf. (1)) and split DC-link voltage (cf. (7)), boundary condition satisfying (12) is given by  
\[0.5V_{DC}^{*}-\Delta V(\varphi)\cos(3\omega t+\alpha(\varphi))=V_{M}\sin( \omega t). \tag{13}\]  
Figure 3: Positive split DC link capacitance voltage and AC-side phase voltage for three values of \(\cos\varphi\) employing corresponding minimum values of split DC link capacitances.  
Equation (13) poses a challenge for obtaining an analytical solution in its original form yet may be solved numerically using any available computational software package. Nevertheless, it is possible to approximate the solution analytically by decomposing both sides of (13) into corresponding second-order Taylor series expansions, resulting in the following quadratic equation,  
\[\begin{array}{l}\left(\frac{\varphi}{2}\Delta V(\varphi)+\frac{V_{M}}{2} \right)\left(\omega t\right)^{2}-\left(3\Delta V(\varphi)\cdot\left(2\pi+\alpha (\varphi)\right)+\frac{\pi V_{M}}{2}\right)\left(\omega t\right)+\\ +\frac{V_{DC}^{*}}{2}+\Delta V(\varphi)\left(\frac{\left(2\pi+\alpha(\varphi) \right)^{2}}{2}-1\right)-V_{M}\left(1-\frac{\pi^{2}}{8}\right)=0.\end{array} \tag{14}\]  
Figure 3 illustrates the accuracy of approximation (14). Since Taylor series expansions are carried out around corresponding peak points, the minimum error occurs when the power factor is zero and leading, while the maximum error arises when the power factor is zero and lagging. For a given range of expected power factors, the capacitance value of split DC link capacitors should be determined according to the lowest leading power factor (or the highest lagging power factor in case inductive-only operation is expected). Such a sizing approach guarantees correct performance within the whole operational power factor range while the proposed approximation provides a reliable method for calculating the minimum required capacitance value.  
Boundary condition (13) is attained when the quadratic Equation (14) determinant equals zero, yielding a single solution (see [36] for additional details). Solving, minimum split DC link capacitance value is obtained as (cf. (9) and (10))  
\[C_{DC}=\frac{288\cdot S\cdot E_{AC}^{pu}}{V_{DC}^{*}\left(36V_{DC}^{*}+V_{M}(4 \alpha^{2}+4\alpha\pi+\pi^{2}-80)+\sqrt{\Delta}\right)} \tag{15}\]  
with \(\Delta\) given by  
\[\begin{array}{ll}\Delta=&\begin{array}{l}1296\left(V_{DC}^{*}\right)^{2}+ V_{DC}^{*}V_{M}(288\alpha^{2}+288\alpha\pi+72\pi^{2}-4608)+\\ +V_{M}^{2}(16\alpha^{4}+32\alpha^{3}\pi+24\alpha^{2}\pi^{2}+8\alpha\pi^{3}+ \pi^{4}-640\alpha^{2}-640\alpha\pi-160\pi^{2}+4096).\end{array}\end{array} \tag{16}\]  
On the other hand, additional requirement should be established in practice in order to bound the maximum value of a split DC link capacitor voltage according to its voltage rating as follows. Denoting the voltage rating of a split DC link capacitor as \(V_{R}\), the maximum value of a split DC link capacitor voltage should be limited to \(kV_{R}\) with \(k<1\) in order to provide a safety margin for prolonging the device lifetime. Consequently, the following equation is formed (cf. (8))  
\[0.5V_{DC}^{*}+\Delta V(\varphi)=kV_{R}, \tag{17}\]  
satisfied by a capacitor valued as (cf. (9))  
\[C_{DC}=\frac{S\cdot E_{AC}^{pu}(\varphi)}{0.5V_{DC}^{*}(kV_{R}-0.5V_{DC}^{*})}. \tag{18}\]  
Combining (15) and (18) into  
\[\frac{288}{36V_{DC}^{*}+V_{M}(4\alpha^{2}+4\alpha\pi+\pi^{2}-80)+\sqrt{ \Delta}}=\frac{2}{kV_{R}-0.5V_{DC}^{*}}. \tag{19}\]  
and solving provides the required reference voltage value \(V_{DC}^{*}\). Then, minimum split DC link capacitance value \(C_{DC}\) may be obtained by substituting \(V_{DC}^{*}\) into (15) or (18).