## 2 DC Fault Current Analysis
### DC Fault Analysis of the Test System
#### 2.2.1 Submodule Capacitor Discharging Period  
At the beginning of the PPF, the capacitor in every inserted SM discharges and bridge arm current surges. Figure 3 depicts the fault current circuit, in which the capacitor discharging current flows through the IGBT of the inserted SMs and the anti-parallel diode of the removed SMs in each converter unit. The fault occurs at point A and point B, which are connected with dashed line in Figure 3. Considering that converter includes six arms with same topology, hence, only the upper arm of phase A is shown with insert SMs and removed SMs due to the space of figure and simplicity. All the IGBT can be turned off as the bridge arm current reaches the threshold value to protect the IGBT from overcurrent damage. The voltage cross converter unit \(v_{conv}\) decreases with SM capacitor discharging until the IGBT is blocked. In contrast to the two-level VSC-HVDC system under the PPF, in which a large capacitor connected to the DC side discharges to zero, even if IGBT is blocked (assuming the resistance in fault circuit \(R_{eq}<2\sqrt{L_{eq}/C_{eq}}\) ), the voltage of the SM capacitor is normally maintained given the blocked IGBTs in the MMC-HVDC system. If \(v_{conv}\) is higher than the AC grid line voltage \(v_{sj\_line}\) (j indicates phases a, b, and c), then the AC grid current cannot be fed in the fault current loop. If \(V_{conv}\) is lower than the AC grid line voltage, then the AC grid begins to feed the AC current \(i_{ij}\) (j indicates phases a, b, and c) into the fault current loop. In Figure 3, the red dashed line indicates the  
Figure 2: Topology structure of the MMC. fault currents \(i_{sj}\) fed from the AC grid; these fault currents are equally divided into an upper arm current \(i_{pj,ac}\) and a lower arm current \(i_{nj,ac}\) (not marked in the figure due to complexity). The blue dashed-dotted line represents the capacitor discharging path, and \(i_{cj}\) expresses the discharging arm currents. Both AC feeding current in red and SM capacitor discharging current in blue flow through inserted SMs and removed SMs in each arm. Specifically, the fault current flows through freewheeling diode in removed SMs and capacitor and on-state LGBT in inserted SMs, shown in Figure 3. The equivalent circuits of the two fault current paths are exhibited in Figure 4a,b. However, the AC feeding current can be ignored in comparison with the capacitor discharging current during this period. The equivalent phase capacitor \(C_{eq}\) demonstrated in Figure 4b is normally considered \(\frac{2C_{0}}{N}\) in the existing references [5,6,15,17]. However, Reference [36] proposed that the calculation value of the fault current with \(C_{eq}=\frac{C_{0}}{N}\) is close to the simulation value. Furthermore, \(C_{eq}\) is obtained as \(\frac{1.4~{}C_{0}}{N}\) for the optimal approximation of the discharging current via a tracing point method [37]. Consequently, Reference [38] verified that \(C_{eq}\) of the three converter units depends on the fault time \(t_{f}\) and modulation ratio \(m\), as expressed in Equation (1). Thus, the selection of fault time \(t_{f}\) and modulation ratio \(m\) should be reconsidered in this paper. Based on equivalent capacitor expression in Equation (2), the relationship between discharging coefficient \(\sigma\) and time is shown in Figure 5, given the preset modulation ratio \(m\) (0.93) of test system. From the perspective of fault protection, the most serious situation must be considered in selecting \(t_{f}\). According to the red curve in Figure 5, the maximum discharging coefficient \(\sigma\) is obtained when \(t_{f}=\frac{\kappa m}{3}\), \(k=0,1,2\ldots\).