# Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology
## 6 Performance Analysis and Comparison
Figure 13: Layout area measuring model. (**a**) Conventional transistor layout; (**b**) 3D MTJ and control transistor layout. We now consider how to measure path delay in a FPGA device. Typically, the total signal path delay in an FPGA device is divided into two components: intra-cluster delay and inter-cluster delay [38], which correspond to the delay due to logic blocks and the routing delay from Interconnect network, respectively. Furthermore, we define average net delay for a placed and routed design as the geometric average of all its pin-to-pin net delays, not including LB delay. As in [14], we first use RC models for the interconnect segments and more delay to optimize the connection and switch box device sizes as well as the number and sizes of the buffers for the HEX-3 and HEX-6 segments for a given FPGA array size in each technology node. We then use a modified version of the VPR delay calculation function to compute net delays. The delay across a typical stochastic-based logic block, as shown in Figure 14, can be divided into five segments. Table 1 presents our measurements for all these delay segments. The intra-cluster delay contains delay from A \(\rightarrow\) C, which is delay from local buffer and routing muxes, and random sample generation module. In the Table 2, the delay of local buffer and routing muxes is calculated with cluster size \(N=4\), and LUT size (\(m\), \(n\)) = (5, 2). By increasing cluster size of \(N\) or LUT size (\(m\), \(n\)), the total delay due to muxes will increase because more output muxes are needed. However, this delay increase is completely negligible when compared with the delay due to random sample processing. This is because that the stochastic Taylor expansion utilizes random bit streams, the processing delay of A \(\rightarrow\) C strongly depends on and grows almost linearly with the number of random bits in each stream. The stochastic multiplication is implemented by fully parallel AND gates, thus, the delay of AND gate C \(\rightarrow\) D(ps) is added. The large fan-in addition employs large input muxes. The of muxes \(\mathrm{D}\rightarrow\mathrm{E}(\mathrm{ps})\) is also determined by the number cluster size \(N\) and LUT size K. The delay of the analog integrator is also examined using a high speed module in SPICE. The results are shown in Table 2.  
We now compare the performance of our SPGA against three of other FPGA architectures using the 45 nm CMOS technology node and the Perpentidular Magnetic Anistrophy (PMA) MTJ Compact model [22]. In total, we consider three performance metrics: delay, energy consumption, and transistor count or chip area. The first FPGA is a typical 2D island-style architecture implemented with 45 nm CMOS technology. The second work [39] utilizes MTJ device to replace SRAM for constructing LUT. The third architecture is based on the work in [10; 40], where a nano crossbar architecture is used to replace the conventional NVFM for high density and lower power consumption. The fourth FPGA is a 3D rFPGA first presented in [41] that utilizes high-density resistive memory (RRAM) to build FPGA components. Different from the existing CMOS-nano hybrid circuits that use crossbars, the proposed rFPGA structures consist of mainly 1T1R structures (1 CMOS transistor is integrated with a two-terminal resistive nanojunction) that can be fabricated using a CMOS-compatible process. Our software tool chain is mostly based on the well-know VPR package from University of Toronto and a modified version of ABC from UC Berkeley. In particular, our power analysis is carried out through the power evaluator, fpgaEvaLP2 [42]. Twelve benchmark circuits from MCNC are used for all measurements and all results are listed in Table 3. Not surprisingly, the conventional FPGA based threshold logic in the 45 nm device technology consumes the highest power mainly because of the routing interconnects and programmable switches. Secondly, the relatively low utilization rate (\(\sim\)12%) of conventional FPGA logic fabric significantly reduces its efficiency.