# Convolution Accelerator Designs Using Fast Algorithms
## 4 Implementation Results  
All the designs were evaluated using the Xilinx kintex-7 325t FPGA. The designs were simulated and implemented in Vivado 2014.3 using Verilog, all the data used 16-bit fixed-point precision, and the FPGA implementation was performed at 100 Mhz. We simulated our designs using the Vivado Simulator with the same input feature maps and kernels and recorded the time consumptions to compare their processing performances, as shown in Table 1. The time consumption counts from the first to the last output pixels. We can see from Table 1 that all the designs require almost the same time to complete the same matrix convolution. That is, these designs have the same processing performance. Table 2 provides a detailed description of the resource utilizations. The table shows that the design based on the Strassen algorithm uses fewer resources than the conventional design. The design based on the Winograd algorithm requires less than half of the Digital Signal Processors (DSPs) required by the conventional design, but more than the other resources, like registers and look up tables(LUTs). Based on the utilization rate of the resources, the Winograd algorithm is observed to improve the \begin{table}
\begin{tabular}{c c} \hline \hline \multicolumn{2}{c}{**Time Consumption**} \\ \hline Conventional & 125.48 \(\mathrm{\SIUnitSymbolMicro s}\) \\ Strassen & 125.49 \(\mathrm{\SIUnitSymbolMicro s}\) \\ Winograd & 125.49 \(\mathrm{\SIUnitSymbolMicro s}\) \\ Strassen–Winograd & 125.50 \(\mathrm{\SIUnitSymbolMicro s}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Time consumption records for the different designs. Figure 10: Architecture of the matrix convolution based on the Strassen–Winograd algorithm. overall resource utilization. Though more DSPs have been added in recent FPGAs, the DSP is still a limiting resource in most cases, except for the Winograd algorithm. Compared to the Winograd algorithm, the design based on the Strassen-Winograd algorithm requires even fewer resources. Xilinx provides the Vivado Power Analysis for power estimations. It provides accurate estimations because it can read the exact logic and routing resources from the implemented design and presents the power report from different views. The power consumption of the FPGA consists of the static and dynamic power, the latter accounting for most of the total power consumption. Dynamic power consists of the clock power, signal power, logic power and the DSP power. The detailed power consumption is recorded in Table 3 and Figure 11.  
Table 3 and Figure 11 give detailed descriptions of the power distribution. We can see from the table that the DSP power occupies a large portion of the dynamic power consumption of the FPGA. The total dynamic power of the design based on the Strassen algorithm is 4% less than that of the conventional design. However, the signal and logic powers of the design based on the Strassen algorithm are higher than those of the conventional design. This is because the Strassen algorithm increases the signal rate. The total dynamic power of the design based on the Winograd algorithm is 20.5% less than that of the conventional design. The total dynamic power of the design based on the Strassen-Winograd algorithm is 21.3% less than that of the conventional design. Similarly, since the Strassen algorithm increases the signal rate, the signal and logic powers of the design based on the Strassen-Winograd algorithm are higher than those of the Winograd algorithm-based design. \begin{table}
\begin{tabular}{c c c c c} \hline \hline  & **Slice Registers** & **Slice LUTs** & **Slices** & **DSP48E1s** \\ \hline Available & 407,600 & 203,800 & 50,950 & 840 \\ Conventional & 5780 & 4635 & 2248 & 288 \\ Strassen & 5543 & 4642 & 2041 & 252 \\ Winograd & 9544 & 7752 & 3049 & 128 \\ Strassen–Winograd & 8751 & 7396 & 2713 & 112 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Device utilization summary. Figure 11: Power consumption of designs based on different algorithms.