# A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow
## 1 Introduction
In the latter case, digital gates are used as basic blocks to design analog functions, with the goal of exploiting both the automatic place-and-route steps of the digital design flow and, in particular, a fully automatic synthesis flow of the analog part together with the digital one. On the one hand, different approaches to mimic the behavior of the OTA through digital-based architectures have been proposed, such as the VCO-based OTA [37; 38] and the fully-digital OTA (DIGOTA) [39; 40; 41] approaches. On the other hand, several inverter-based OTA architectures [42; 43; 44] have been proposed in the literature to allow operation at low supply voltages [15; 16; 17; 22; 45; 46; 47; 48; 49; 50]. The design of standard-cell based OTAs [29; 33; 40; 51; 52] is the direct evolution of this approach, with some added constraints due to the fact that optimization at the transistor level is not allowed. Differently from custom-designed inverters, the standard-cell inverter is typically optimized for digital operation, e.g., to achieve symmetrical slew rate, and this results in a systematic offset in the dc transfer function [52; 53]; moreover, as pointed out in several papers, the performance and even the operation of standard-cell-based analog circuits are severely impaired by PVT and mismatch variations, resulting in incorrect bias, large offsets, and significant performance variations [46; 47; 53; 54; 55; 56; 57]. To cope with these issues, approaches that exploit body biasing of the standard-cells, together with a custom-designed body bias generator, have been proposed in the literature [45; 58; 59]. However, these solutions require the availability of the body terminals: this is common in modern technologies, where body biasing is exploited to compensate for PVT variations in digital circuits [60; 61], but it is not compatible with older technologies often used for analog designs. Moreover, the limited gain of the body input could require control voltages beyond the supply rails to cope with large bias point variations. A different solution has been proposed in [52], which presents a basic amplifier cell where an auxiliary inverter or one input of a two-input logic gate is driven by a fully-standard-cell replica bias loop to stabilize the bias point. In this work, we present improvements to two analog building blocks that have been previously presented in [33; 52]. More specifically, we propose a novel standard-cell-basedbasic voltage amplifier cell that exploits the same biasing strategy as in [52], based on a replica loop to control the output dc voltage, but exhibits a gain approximately equal to an integer factor \(k\) (i.e., the number of inverters in parallel) and a low output impedance. We also present a modified version of the D2S introduced in [33], in which a novel error amplifier topology is adopted in the feedback loop. A further contribution of the present paper is the OTA architecture, which combines all of these building blocks into a multi-stage fully synthesizable amplifier. The paper is structured as follows: Sections 2-4 present the proposed improved standard-cell-based analog building blocks, while the OTA architecture and design guidelines are reported in Sections 5 and 6, respectively. Simulation results are presented in Section 7, a comparison against other ULV OTAs taken from the literature is presented in Section 8, and finally some conclusions are reported in Section 9.