# A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
## 3 Experimental Results
### Implementation with Cyclone IV E FPGA  
Altera Cyclone IV E series FPGAs, which were issued in 2009, have been widely used in many research fields for their very low cost and low power consumption. The Cyclone IV E FPGA embed four PLLs which can be used to generate periodical signals in conventional and proposed Vernier DTCs, since the resolution of both conventional and proposed Vernier DTCs is determined by the performance of PLLs. The block diagram of the PLL in Cyclone IV E FPGA is depicted in Figure 7[16]. PLL parameters are shown in Table 1[16; 17]. Figure 6: Computation unit for counters and PDL in the proposed DTC. Figure 7: Block diagram of phase locked loop (PLL) in Cyclone IV E and Stratix III field programmable gate arrays (FPGAs) [16]. According to the measurement, the maximum working frequency of our design implemented with Cyclone IV E series FPGAs is limited to 200 MHz. To pursue a higher working frequency, it needs more complex logic implementation and optimized place and route at the expenses of complexity and reliability. For Vernier FPGA-DTCs, the rising edge of the reference clock is set as the phase coincidence of two periodical signals. Thus, the output signals of two PLLs should be integer times of reference clock. Moreover, the input frequency range of PLLs is 5-474 MHz. To ensure the PLL outputs have the same phase at every rising edge of reference clock, the PLLs should work at integer-N mode. Therefore, the finest frequency resolution is 5 MHz and the highest time resolution of traditional Vernier DTC with 200 MHz working frequency can be obtained as:  
\[\Delta\mathrm{T}=\frac{1}{195 MHz}-\frac{1}{200 MHz}\approx 128.2 ps \tag{10}\]  
Besides, the resolution of conventional Vernier DTC will be much worse with lower working frequency, since the minimum reference frequency of Cyclone IV E and Stratix III is 5 MHz, and the input frequency from crystal frequency is 50 MHz. Thus, D is chosen as 10 to obtain the minimum frequency step size. Moreover, as analyzed in Section 2, when the multiple factor design is \(2^{\mathrm{M}}-1\) the logic computation circuit is simplest. Therefore, we choose the working frequency to be around 155 MHz for the trade-off between resolution and design complexity. According to the tuning range of the voltage controlled oscillator (VCO) integrated in the FPGAs, the tools will suggest several values of N and C. We choose the minimum value of them for the lowest phase noise performance. With overall considerations of stability, complexity, timing constraint and resolution, we set the input frequency to 50 MHz (crystal frequency in DE2-115 system), D (input divisor) to 10, N (feedback divisor) to 120/124/128 and C (post scale counter) to 4 on Cyclone IV E: EP4 CE115 FC7 FPGA. Therefore, the theoretical resolution of Cyclone IV E FPGA DTC is 13.4 ps, as calculated in Equation (11). \[\left\{ \begin{array}{l}T_{F}=\frac{1}{50+10\times 128+4 MHz}=6.25 ns\\ T_{M}=\frac{1}{50+10\times 124+4 MHz}\approx 6.451613 ns\\ T_{S}=\frac{1}{50+10\times 120+4 MHz}\approx 6.666667 ns\\ \Delta T=T_{F}+T_{S}-2T_{M}\approx 13.44 ps\end{array} \right. \tag{11}\]  
The actual performance of the proposed Cyclone IV E FPGA DTC is measured from \(\Delta\mathrm{T}\) to \(2\mathrm{T}_{S}\) for validating fine, medium and coarse resolution. The reference clock was generated by the crystal oscillator embedded on DE-2 115 system. The output interval width of the proposed DTC was accurately measured by a digital oscilloscope (TEK DPO71604C) with 50 GS/s real-time sample rate. The measured and post-synthesis simulated differential nonlinearity (DNL) and integral nonlinearity (INL) of the proposed Cyclone IV E FPGA-DTC are shown in Figures 8 and 9, respectively. The effective resolution is obtained from the measured results. The time difference between START and STOP is nominal to zero when the input value is zero. The measured time interval is 13.392 ns when the input value is 992. The effective resolution is defined as 13.392 ns/992 \(\approx\) 13.5 ps.