## 3 Design and Development
### Innovation and Improvements in Module Reuse  
From the methods, it is evident that, due to the downsampling design, the load on each IMF processing stage in the pipeline decreases progressively. The total load of the IMF modules from the second to the seventh stage is even less than that of the first IMF module, resulting in unnecessary waste of logic resources. To address this, module reuse can be employed to fully utilize the idle processing capacity of the modules [43; 44]. Module reuse in a pipeline is not typically considered a wise design choice, as ensuring that each stage of the pipeline is correctly processed requires adding many registers to store the state and data of each stage, making it difficult to reduce logic resource consumption as expected [45; 46]. Additionally, introducing more complex logic during this process can lower the maximum allowable clock frequency [47], and the clock cycles required to process each data unit may be significantly higher than ideal. Moreover, due to the difficulty in modular design for reused parts, this approach has poorer maintainability and scalability. However, because the current design requires processing data at extremely low rates and is not as sensitive to the increased delay and reduced clock frequency, and because the IMF modules have significantly unbalanced loads, the approach is discussed and designed in this paper. As shown in Figure 7, module reuse employs a clock divider to obtain divided clock signals at 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, and 1/128 times the clock frequency and uses these divided clock signals to select the current IMF stage being processed to balance the load. The selection signals correspond to BRAM and state registers, and data register addresses, to match the IMF extraction stages.  
The divided clock signals generate an idle clock every 128 th clock cycle, which ideally could be used to determine whether each pipeline stage has data to be processed and to more reasonably reinitialize the position of the clock divider to reduce possible maximum delay. However, in practice, it is difficult to correctly handle this process without lowering the clock frequency, so this design was not implemented in this paper. The selection signals generated by the divider are delayed through a series of delays and distributed to the IMF extraction and BRAM read phases to ensure pipeline efficiency. Since the envelope extraction through interpolation causes blocking, the subsequent moving average filter and local mean calculation are treated as the beginning of the pipeline. Each subsequent processing stage uses the selection signal for the corresponding IMF iteration stage delayed by the appropriate clock cycles to handle and store until the next envelope interpolation stage. BRAM data are read out on the falling edge of the clock 0.5 clock cycles before each stage's selection signal to ensure BRAM read/write does not affect the maximum clock frequency. When the local mean of IMF7 is generated, it is sent to the IMF calculation module to calculate the difference with the previous stage's mean, outputting IMF7 and generating a data-ready signal. The IMF7 extraction with module reuse can still operate at a 200 MHz clock frequency, with overall fault detection delay increased to 0.008 ms, which is still within acceptable limits. Meanwhile, 41% of LUTs, 39% of Registers, 82% of CARRY8, 71% of BRAM, and 86% of DSPs are saved.