## 1 Introduction
[40] came up with a concurrent error detection scheme based on linear arithmetic code (LAC), and applied it to systolic implementation of MD. As shown in Figure 1, the scheme consists of a main function module (MFM) and an error detection module (EDM). The former is responsible for the MD computation, and the latter for error detection of the MFM, using the LAC. The EDM involves three sub-modules, namely, actual check part generator (ACPG), check part predictor (CPP), and comparator (CMP). Among them, the ACPG accepts the results of each iteration from the MFM, and generates their actual check parts; the CPP predicts the check parts of iterative results; the CMP compares the actual check parts with the predicted ones--if the two parts are consistent in each iteration, then no fault has been injected in the MFM, and the system will continue to run; otherwise, the architecture will issue an alarm about the probability of fault attacks in the MFM. The MD output is regarded as valid, if and only if the actual and predicted check parts of any iteration are equal to each other. On the upside, the scheme in [40] can detect errors accurately with limited area and time overheads. On the downside, this scheme cannot report the detected errors in real-time because it takes the entire n-bit iterative result as the detection cell so that the system cannot output the iterative detection result until the last word of the iteration result is valid. Neither could this scheme locate the detected errors. Inspired by the concurrent error detection scheme for the MD in [40], this paper proposes a novel MD architecture capable of effectively detecting and locating erroneous processing elements, and applicable to related cryptographic implementations, laying the basis for prevention of natural faults and fault attacks. The contributions of this paper are as follows:  
1. This paper extends our work in [40] to present a new secure MD architecture that can not only detect, but also locate, the error. 2. Twelve combinations of four word-oriented systolic implementations of MFM and three error-detecting schemes with different LAC values were explored to seek the best tradeoff between area, time overheads, and error detection capability. These combinations were modeled using Verilog language and synthesized using Synopsys Design Complier with the TMSC (Taiwan Semiconductor Manufacturing) 90 nm CMOS (Complementary metal-oxide-semiconductor) standard cell library. Their functions were also verified using Modelsim. 3. Random fault injections were simulated using the C++ program and the simulation result shows that the proposed architecture can detect single-bit error (SBE) with 100% accuracy and locate the erroneous processing element (PE). The detection capability of single-PE error (multiple-bit error is injected into one PE) and multi-PE error vary with the value of LAC. However, it reaches 99.898% when the number of erroneous processing elements is three or more. 4. In addition, the proposed architecture can greatly shorten the delay in error reporting. The remainder of this paper is organized as follows: Section 2 briefly reviews the MD algorithm and the LAC; Section 3 sets up our architecture and describes its algorithm; Section 4 analyzes the error detection and location capabilities of our architecture; Section 5 presents the application-specific integrated circuit (ASIC) implementation results of our architecture, and compares them with those of existing schemes; Section 6 puts forward the conclusions of this research.