## 3 MMPD Design for DB PAM4
The logical expression of the Data Sampler logic gate circuit is:  
\[d_{n}[2] =D_{n}[7] \tag{1}\] \[d_{n}[1] =D_{n}[7]D_{n}[6]D_{n}[3]D_{n}[2]\overline{D_{n}[0]}+D_{n}[7]D_{ n}[5]D_{n}[3]D_{n}[2]\overline{D_{n}[0]}\] \[+D_{n}[6]D_{n}[5]D_{n}[1]+D_{n}[1]\overline{D_{n}[0]}+D_{n}[3]D_{n}[ 1]+D_{n}[2]D_{n}[1]\] \[+D_{n}[7]D_{n}[1]\] \[d_{n}[0] =(D_{n}[6]D_{n}[5]D_{n}[4]D_{n}[3]\overline{D_{n}[2]D_{n}[1]D_{n} [0]}+D_{n}[7]D_{n}[3]\overline{D_{n}[2]D_{n}[1]D_{n}[0]}\] \[+D_{n}[7]D_{n}[6]D_{n}[4]D_{n}[3]D_{n}[1]+D_{n}[7]D_{n}[6]D_{n}[5]D _{n}[3]D_{n}[1]\] \[+D_{n}[7]\overline{D_{n}[6]D_{n}[5]}D_{n}[2]+D_{n}[5]D_{n}[4]D_{n} [2]D_{n}[0]+\overline{D_{n}[3]}D_{n}[2]\overline{D_{n}[0]}\] Figure 4:0 Figure 4:1  
According to the logic expression, the logic gate circuit of the Data Sampler is shown in Figure 4:2  
The Waveform Selector consists of a Comparator and a Selector. The Comparator inputs two consecutive sets of data sampling results to obtain the comparison result \(\mathbb{S}_{n}[20]\). The logic gate circuit expression of the Comparator is: \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Reference** & **Modulation** & **Mode** & \
\begin{tabular}{c} **Classification** \\ **Number** \\ \end{tabular} &
\begin{tabular}{c} **Phase-Detection** \\ **Density** \\ \end{tabular} \\ \hline
[8] & NRZ & MM & 3 & \(1/2\) \\
[11] & PAM-4 & MM & 3 & \(7/16\) \\ This paper & PAM-4 & MM & 5 & \(1/2\) \\ This paper & DB PAM-4 & MM & 5 & \(21/32\) \\
[16] & DB PAM-4 & BB & 4 & \(1/4\) \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Phase-detection density comparison. Figure 6: Logic gate circuit of Data Sampler. \[ \begin{split} S_{n}[1]&=d_{n-1}[2]\overline{d_{n-1}[0]d_{n}[2] d_{n}[1]}+d_{n-1}[2]\overline{d_{n-1}[0]d_{n}[1]}d_{n}[0]\\ &+d_{n-1}[2]d_{n-1}[1]d_{n-1}[0]\overline{d_{n}[2]d_{n}[1]}+d_{n- 1}[2]d_{n-1}[1]\overline{d_{n-1}[0]d_{n}[1]}d_{n}[0]\\ &+\overline{d_{n-1}[0]d_{n}[2]d_{n}[0]}+d_{n-1}[1]\overline{d_{n} [2]}d_{n}[0]+d_{n-1}[1]\overline{d_{n-1}[0]}\\ S_{n}[0]&=\overline{d_{n-1}[2]d_{n-1}[1]d_{n}[2] \overline{d_{n}[0]}+\overline{d_{n-1}[1]}d_{n-1}[0]d_{n}[2]\overline{d_{n}[0]}} \\ &+\overline{d_{n-1}[2]d_{n-1}[1]d_{n}[2]d_{n}[1]}+\overline{d_{n- 1}[1]}d_{n-1}[0]d_{n}[2]d_{n}[1]\\ &+\overline{d_{n-1}[2]d_{n-1}[0]\overline{d_{n}[0]}+\overline{d_ {n-1}[2]}d_{n-1}[0]d_{n}[1]}+d_{n}[1]\overline{d_{n}[0]}\end{split}  \tag{2}\]  
According to the logic expression, the logic gate circuit of the Comparator is shown in Figure 7.  
The selector obtains the working mode of the phase detector based on the preset waveform sifting logic, and the logic gate circuit expression of the Selector is:  
\[ \begin{split} mode[2]&=\overline{S_{n}[1]S_{n}[0]S_{ n-1}[1]S_{n-1}[0]}+\overline{S_{n}[1]S_{n}[0]}S_{n-1}[1]\overline{S_{n-1}[0]}\\ mode[1]&=\overline{S[1]}_{n}S_{n}[0]\overline{S_{n-1}[1 ]S_{n-1}[0]}+\overline{S_{n}[1]S_{n}[0]S_{n-1}[0]}\\ mode[0]&=S_{n}[1]\overline{S_{n}[0]S_{n-1}[1]S_{n-1}[0] }+\overline{S_{n}[1]S_{n}[0]S_{n-1}[1]}\end{split}  \tag{3}\]  
According to the logic expression, the logic gate circuit of the Selector is shown in Figure 8.  
The error sampler give the error conclusion by compared the data with the error boundary. The error boundary is +V\({}_{ref}\) and \(-\)V\({}_{ref}\) centered on seven levels, 12 in total, as in Figure 9. This error boundary V\({}_{ref}\) is set in the form of a digital signal Ref[7:0] with an accuracy of 8 bit, which can adjust according to the degree of channel loss. The output error information is 3 bit and consists of the upper boundary information errup, the lower boundary information errlow, and the error information errdata. The working principle is as follows: the corresponding level signal V[7:0] is obtained by d\({}_{n}[2:0]\); when  
Figure 8: Logic gate circuit of Selector. Figure 7: Logic gate circuit of Comparator. D\({}_{n}\)[7:0] \(>\) V[7:0] + Ref[7:0], errup = 1 otherwise errup = 0; when D\({}_{n}\)[7:0] \(<\) V[7:0] \(-\) Ref[7:0], errlow = 1 otherwise errlow = 0, the signal errup and errlow are dissociated to get the error information errdata.