## 2 Background
### Schoolbook Strategy
### Comparisons

We compare our results with existing hardware implementations of various non-digitized bit-serial polynomial multiplication approaches in Table 2. Column one provides the reference implemented design. The name of the multiplication algorithm or method is shown in column two. We provide the implementation device in column three. The operand length is shown with \(j\times k\) in column four. Columns five and six give the circuit frequency (in MHz) and latency (in \(\upmu\)s), respectively. The computation time is the latency, which can be calculated using Equation (2). The last column shows the area cost in slices and LUTs. We use \"-\" in Table 2 where the corresponding information in the reference designs is unavailable. In comparison to the radix-2 Montgomery-based hardware accelerator of polynomial multiplication of [4], our accelerator on Virtex-6 for an operand size of 1024 \(\times\) 1024 achieves 71.5 MHz, while this value in the reference design is 53.23 MHz, which is comparatively 1.34 (ratio of 71.5 with 53.23) times lower. Similarly, our accelerator is 1.34 (ratio of 71.5 with 53.23) times faster in computation time (or latency). Instead of the circuit frequency and latency comparison, our accelerator achieves 2429 LUTs while the design of [4] utilizes 2566 LUTs, which is comparatively 1.05 times higher than this work. Probably this is due to the use of a Schoolbook technique for partial product generation in this work. On the Virtex-5 FPGA, the Montgomery-based polynomial multiplier design of [13] for an operand size of 1024 \(\times\) 1024 achieves a maximum frequency of 400 MHz, which is comparatively 10.16 (ratio of 400 with 39.35) times higher than the operating frequency achieved in this work (i.e., 39.35 MHz). This higher operating frequency in the reference design of [13] results in a lower computation time than our Booth hardware accelerator, as shown in column six of Table 2. Indeed, our Booth hardware accelerator needs more \begin{table}
\begin{tabular}{l l l l l l l} \hline \hline
**Ref.** & **Implemented Algorithm** & **Platform** & **Operand Sizes (\(j\times k\))** & **Freq (MHz)** & **Lat (\(\upmu\)s)** & **Slices/LUTs** \\ \hline
[4] & Radix-2 Montgomery & Virtex-6 & 1024 \(\times\) 1024 & 53.23 & 19.26 & -/2566 \\
[13] & Montgomery & Virtex-5 & 1024 \(\times\) 1024 & 400 & 0.88 & 6105/- \\
[14] & PCA & Virtex-II & 163 \(\times\) 163 & 177.8 & 0.91 & 225/- \\
[17] & radix-4 Booth & Spartan-6 & 32 \(\times\) 32 & 100 & - & -/278 \\
[18] & radix-4 Booth & Kintex-7 & 16 \(\times\) 16 & - & - & -/110 \\ \hline  & & Virtex-6 & 1024 \(\times\) 1024 & 71.5 & 14.32 & -/2429 \\  & & Virtex-5 & 1024 \(\times\) 1024 & 39.35 & 13.01 & 4113/- \\ This Work & Booth & Virtex-4 & 163 \(\times\) 163 & 131 & 1.24 & 565/- \\  & & Virtex-7 & 32 \(\times\) 32 & 645.161 & 0.0248 & 30/323 \\  & & Kintex-7 & 16 \(\times\) 16 & 678.358 & 0.0117 & 30/69 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Comparison to existing bit-serial multiplier accelerators. Freq: circuit frequency; Lat: latency or computation time; PCA: programmable cellular automata. computation time than the reference design; conversely, our accelerator is more efficient in hardware area cost. Specifically, our design utilizes 4113 slices, while the reference accelerator used 6105 slices on a similar Virtex-5 FPGA. A programmable-cellular-automata-based bit-serial polynomial multiplier accelerator is implemented on a Virtex-II FPGA in [14]. Virtex-II is a Xilinx family introduced in January 2001 on 150 nm process technology [31]. Xilinx introduced the Virtex-II Pro family in March 2002 on 90 nm process technology [32]. Both these families are considered legacy devices and are not recommended for use in new designs, although Xilinx still produces them for existing designs. The equivalent 90 nm process technology is Virtex-4 [33], which we used to compare our hardware accelerator of the Booth multiplier with the reference implementation of [14].