# A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer
## 2 Proposed Delta Sigma Modulator with Coarse-Fine Input Buffer
### Second-Order Incremental Cascade of Integrator Feedback  
The DSM circuit is designed as a second-order cascade of an integrator with feedback (CIFB). Figure 8a shows the block diagram of the secondary CIFB circuit. Figure 8b shows the schematic of the modulator. The OSR in the secondary modulator circuit is assumed to be 512. Moreover, the sampling frequency was set to 125 kHz, and the passband frequency was given to 122.07 Hz. From the assumed parameters, the noise transfer function (\(NTF\)) and signal transfer function (\(STF\)) are expressed as follows:  
\[NTF=\frac{(z-1)^{2}}{(z^{2}-1.225z+0.4415)} \tag{1}\]  
\[STF=\frac{0.21637}{(z^{2}-1.225z+0.4415)} \tag{2}\]  
The coefficients \(a_{1}\), \(a_{2}\), \(b_{1}\), and \(c_{1}\) are designed to satisfy the following relationship (3) when the supply voltage of the circuit (\(V_{dd}\)) was at 1.8 V:  
\[a_{1}=\frac{C_{1}V_{dd}}{C_{2}},\ a_{2}=\frac{C_{4}V_{dd}}{C_{5}},\ b_{1}= \frac{C_{1}V_{dd}}{C_{2}},\ c_{1}=\frac{C_{3}}{C_{5}} \tag{3}\]  
The coefficients are calculated using the MATLAB behavioral model and approximated according to the design rule of the metal-insulator-metal (MIM) capacitors. The coefficients are summarized in Table 1.  
The amplifier used in the DSM integrator is shown in Figure 9. The circuit was designed as a fully differential amplifier (FDA) with rail-to-rail input and output to maximize the voltage input and output. A Miller compensation capacitor was used to stabilize the frequency band of the circuit. A gain-boosting technique was used to optimize the voltage gain. In the folded cascode amplification circuit, electrical signals are input from the sources of M\({}_{\text{P6}}\) and M\({}_{\text{P7}}\), and of M\({}_{\text{N6}}\) and M\({}_{\text{N7}}\). The amplified electrical signal is then outputted to the gates. M\({}_{\text{P12}}\), M\({}_{\text{P13}}\), M\({}_{\text{P14}}\), M\({}_{\text{P15}}\), M\({}_{\text{N13}}\), and M\({}_{\text{N14}}\) were used as common-mode feedback circuits.  
Figure 10 shows the loop gain simulation of the FDA used as an integrator. The DC gain, unit gain bandwidth, and phase margin are 180 dB, 1.8 MHz, and 60\({}^{\circ}\), respectively. The FDA draws approximately 210 \(\upmu\)A at a voltage supply of 1.8 V.  
Figure 7: Transient simulation result of the buffer’s enable timing diagram.  
Figure 8: (a) Block diagram; (b) Schematic of second-order delta-sigma modulator.  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Coefficient** & **Ideal Value** & **Real Value** \\ \hline a1 & 0.1125 & 0.1112 \\ a2 & 0.18 & 0.1776 \\ b1 & 0.1125 & 0.1112 \\ c1 & 0.45 & 0.4365 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Comparison of simulated ideal coefficients and actual coefficients designed with MIM capacitors.  
Figure 9: Fully differential amplifier for integrator.  
The PMOS and NMOS gain-boosting circuits are shown in Figure 11a,b, respectively. These circuits are used for \(G_{mn}\) and \(G_{mp}\) in Figure 9. The \(G_{mn}\) and \(G_{mp}\) are designed using a folded-cascode amplifier configuration. The \(G_{mn}\) and \(G_{mp}\) provide the boosted gain of Equations (4) and (5), respectively.  
\[G_{mn}=g_{mn1}(r_{on1}\mid\mid r_{op1})(g_{mp3}r_{op3})\mid\mid(g_{mn8}r_{on4}) \tag{4}\]  
\[G_{mp}=g_{mp2}(r_{op2}\mid\mid r_{on1})(g_{mn3}r_{on3})\mid\mid(g_{mp6}r_{op6}r_{ op4}) \tag{5}\]  
Figure 11: Gain boosting amplifier of \(G_{mp}\) (**a**) and \(G_{mn}\) (**b**).  
Figure 10: FDA loop gain simulation result in integrator.  
The two-stage comparator at the end of the modulator stage is shown in Figure 12. The pre-amplifier stage is designed using the PMOS input stage and the gain-enhanced positive feedback NMOS loads (M\({}_{\text{N2}}\) and M\({}_{\text{N3}}\)) and diode-connected loads (M\({}_{\text{N1}}\) and M\({}_{\text{N4}}\)). The second stage is designed using the dynamic latch and the following SR-latch.