# Design and Simulation of Low-Orbit Satellite Broadcast Signal Receiving and Processing Terminal
## 3 Key Technologies
### FFT Fast Acquisition Method Introducing Bit Synchronization Loop  
The pseudo-code rate of Beidou B2a and B3I signals is 10.23 Mcps, and the pseudo-code period before scrambling is 1023, so one pseudo-code period is 100 us. The symbol rate is variable from 2 K to 256 Kbps [7; 8; 38; 39; 40; 41; 42; 43], which poses a huge problem for fast acquisition algorithms that information symbol rates must be an integral multiple of the pseudo-code rate. How to achieve high real-time and high sensitivity acquisition requirements and how to solve the problem of aligning the symbol rate and spreading code during acquisition is of great research significance. If the acquisition module of the front spreading code avoids the problem of misalignment between the symbol rate and the spreading code, in exchange for reducing the calculation time cost, this problem needs to be solved in the tracking module [44; 45; 46; 47; 48]. The time domain parallel frequency domain FFT fast acquisition method (hereinafter referred to as \"FFT fast acquisition method\") can be implemented on the Xilinx corporation's (San Jose, CA, USA) Zynq 7030 chip using only 40% of the logic resources. The simulation parameters are compared using the FFT frequency domain acquisition method and the FFT fast acquisition method when doing 256-point FFT. The results of the comparison and the simulation analysis are shown in Table 1[8; 42]. Figure 5: Implementation block diagram of time–frequency domain notch technology based on FFT. Based on the above analysis, this design proposes the FFT fast acquisition method that combines the time domain and frequency domain, which can achieve signal acquisition without aligning the symbol rate with the spreading code [47; 48; 49]. This design plans to use a Zynq 7030 chip as the basis of the signal capture module. With its low cost and small size, it can fully meet the resource implementation of fast acquisition algorithms [44; 46; 50]. The FPGA design diagram of the fast acquisition algorithm is shown in Figure 6. The beam-synthesized data are sent to the data buffer, then sent to 64 parallel correlators in parallel. The correlation results are sent to the buffer. The correlation length of each correlator is dynamically configurable and can support a minimum of 16 chip periods, thereby supporting a maximum symbol rate of 256 Kbps and a maximum Doppler frequency shift of 250 kHz. The length of the 64 buffers is 512, thus supporting coherent accumulation of four pseudo-code periods. Considering the spectrum leakage problem of FFT, it can obtain a gain of approximately 4.7 dB. After the correlation results are buffered, the FFT executes a 256-point complex FFT, performs a frequency domain search, calculates the SNR, and determines whether the threshold is reached. When the threshold is exceeded, the code phase and Doppler value at that moment are recorded and sent to the subsequent tracking module [51; 52; 53; 54]. To complete the search for the entire code phase, more than 1023 \(\times\) 2/64 = 32 operations are required. Each correlation time is four pseudo-code periods. Therefore, the search and acquisition time to complete one code period is 128 pseudo-code periods, which is approximately 12.8 ms. In order to speed up the calculation time of FFT, this solution uses two 256-point complex FFTs executed in parallel, and the actual capture time is measured to be 32.8 ms [47; 48; 49; 54; 55]. In order to solve the demodulation problem when the information symbol rate is not an integer multiple of the pseudo-code rate, the tracking module needs to introduce a third