# Design of True Time Delay Millimeter Wave Beamformers for 5G Multibeam Phased Arrays
## 2 Beamforming Networks Design
### Tree Type Beamforming Network Architecture
Our goal is to design a beamforming network that can introduce Chebyshev distribution at the antenna ports. To achieve the Chebyshev distribution, asymmetric power dividers have to be designed by appropriately distributing the power at their ports and throughout the network. Conventional unequal power division Wilkinson power dividers can achieve the unequal power split by introducing an asymmetry in the characteristic impedance of their two branches. This way excellent performance is achieved in relatively small power division ratios. As the power division ratio increases, however, the characteristic impedances of the branches acquire very large or very small values, which are unrealizable in microstrip or stripline technology. Large characteristic impedance lines tend to be very thin and sometimes outside of the manufacturing tolerances, while small characteristic impedance lines are very wide, introducing large parasitic capacitances, thereby making them inappropriate for our application. Therefore, unequal power division Wilkinson power dividers are not suitable for our design due to the different power ratios that we need to achieve. Specifically, Figure 14 shows the power divider used in this work. This unequal power divider is based on the design introduced in [56], which is capable of utilizing 50 \(\Omega\) lines and introducing the desired asymmetry in the electrical length of its corresponding transmission lines. In our case, a 21 dB SLL Chebyshev amplitude distribution is excited among the elements. Therefore, the ratio of power arriving at the elements located at the edge of the array over the ones in the middle is 5.15 dB. Figure 12: Schematic of the hierarchical true time delay tree beamformer: (**a**) 1 to 4; and (**b**) 1 to 8. Tree Topology Design Methodology  
A tree beamforming network is comprised of delay lines and power dividers. Similar to any other beamforming network design methodology, we first start by defining the number of desired output elements \(N\) and beams \(M\). Since the tree network is capable of introducing only a specific time delay, steering the beam towards only one specific angle, for each beam direction \(m\in[1,M]\), a different tree network has to be designed. In our proposed design, as we are implementing a multi-layer topology, each beam is produced by a different layer of our network. \(N\) by default can only be a power of two \(N=2^{\
u}\), with \(\
u\) denoting the number of stages used to implement the tree network. Figure 15 shows one layer of a general schematic for the tree type network implemented with \(\
u\) stages and \(N\) outputs. Figure 14: Layout of unequal power divider. Figure 13: Multilayer tree topology layout. Aiming to steer the beam at a specific angle, the phase difference \(\Delta\phi\) between the adjacent output-ports, corresponding to a frequency independent delay of \(\tau\) as in Equation (1). Thus, a \(\Delta\phi=\omega_{0}\tau\) at the center frequency \(\omega_{0}\), is chosen, following the array theory [51]. In addition, as the tree topology offers us the ability to apply any tapering distribution we desire, the appropriate amplitude coefficients at the output ports are chosen. Herein, a Chebyshev array with a predefined \(SLL=21\) dB is employed. These are achieved by appropriately choosing the power division through the network's cascaded power dividers. The whole design philosophy is deployed as we move from stage 1 (left) to stage \(\
u\) (right), as depicted with different colors in Figure 15. Assuming that \(P_{n}\) is the power arriving at each output port, the first stage power divider (in Figure 15, it is denoted with purple color) is designed to have a power division ratio of:  
\[C_{1}=\frac{\sum_{i=1}^{N/2}P_{i}}{\sum_{i=N/2+1}^{N}P_{i}} \tag{6}\]  
Note that, when the amplitude tapering is symmetric, this ratio is equal to one. In addition, the electrical length of the first stage delay line is \(\Delta\phi_{1}=(N/2)\Delta\phi\).