## 2 Materials and Methods  
Figure 1a shows the top view of a fabricated two-finger AlGaN/GaN HEMT. The extension of the gate structure is provided with a lower square contacting pad (G), and the center upper pad is a drain electrode (D). The drain electrode is enclosed between two source electrodes (S). The inset is a magnified cross-sectional SEM image of the dotted region showing the conventional T-shaped gate structure. The AlGaN/GaN heterostructure was grown on a (111) silicon substrate by metal-organic chemical vapor deposition. It consists of a 2-um-thick acceptor-doped GaN buffer layer, a 100-nm-thick i-GaN layer, and a 25-nm-thick i-AlGaN barrier layer with a nominal 25% Al composition. Because of a large lattice mismatch and thermal expansion coefficient between Si and the AlGaN/GaN layer, a C-doped GaN buffer was employed as an insertion layer. To fabricate AlGaN/GaN HEMTs, a 200-nm-thick mesa isolation was performed by Cl\({}_{2}\)/BCl\({}_{3}\)-based inductively coupled plasma reactive-ion etching (ICP RIE). The AlGaN/GaN mesa etching was performed at a flow rate of 18/3 sccm for the Cl\({}_{2}\)/BCl\({}_{3}\), a process pressure of 5 mTorr, an RF power of 100 W, and an ICP power of 300 W. The source and  
-drain ohmic contacts were made by evaporating Ti/Al/Ti/Ni/Au (30/150/20/30/100 nm) metal stack via e-beam metal evaporation. A Ti/Al-based structure was used as diffusion layer to form TiN or AlTi\({}_{2}\)N layers, and the Ti/Ni layers were used as diffusion barriers for Au in the following rapid thermal annealing process. The rapid thermal annealing temperature was 400 for 150 s, 700 for 30 s, and 820 for 30 s. The measured values of specific contact resistivity and sheet resistance were 5.2 \(\times\) 10\({}^{-6}\)\(\Omega\cdot\)cm\({}^{2}\) and \(\sim\)700 \(\Omega/\square\), respectively. A 50-nm-thick protective Si\({}_{3}\)N\({}_{4}\) passivation film was deposited via plasma-enhanced chemical vapor deposition (PECVD) at a deposition rate of 150 A/min. The conditions were: SiH\({}_{4}\)/NH\({}_{3}\)/He of 2.8/8/80 sccm, a pressure of 35 mTorr, an RF power of 100 W, and a substrate temperature of 250 \({}^{\circ}\)C. To expose the AlGaN layer surface, an etching window was opened with photolithography, and the Si\({}_{3}\)N\({}_{4}\) was etched using a CF\({}_{4}\)/O\({}_{2}\)-based ICP RIE process at CF\({}_{4}\)/O\({}_{2}\) condition of 110/5 sccm, a pressure of 45 mTorr, and an RF power of 100 W. The etch rate was 110 A/min. Afterward, a Ni/Au (40/100 nm) Schottky gate electrode was fabricated by photolithography followed by e-beam metal evaporation. Finally, the T-shaped gate was formed on the Si\({}_{3}\)N\({}_{4}\) passivation layer. Similarly, a second Si\({}_{3}\)N\({}_{4}\) passivation layer was deposited using PECVD at the same above-mentioned deposition and etching conditions, followed by the contact pad opening. To ensure data reliability, a cross-sectional schematic of a basic device structure is shown in Figure 1b. The unit device structure of one-finger was used in the modeling. Other geometrical parameters of the device are listed in Table 1. For convenience, FP length, gate foot length, gate head length, source gate length, gate drain length, and source drain length are designated as L\({}_{\text{FP}}\), L\({}_{\text{G-foot}}\), L\({}_{\text{G-head}}\), L\({}_{\text{SG}}\), L\({}_{\text{GD}}\), and L\({}_{\text{SD}}\), respectively. \begin{table}
\begin{tabular}{c c c} \hline
**Device Parameters** & **Units** & **Values** \\ \hline L\({}_{\text{FP}}\) & \(\upmu\)m & 0.0–2.1 \\ L\({}_{\text{G-foot}}\) & \(\upmu\)m & 0.5 \\ L\({}_{\text{G-head}}\) & \(\upmu\)m & 1.0 \\ L\({}_{\text{SG}}\) & \(\upmu\)m & 1.45 \\ L\({}_{\text{GD}}\) & \(\upmu\)m & 3.55 \\ L\({}_{\text{SD}}\) & \(\upmu\)m & 5.0 \\ Si\({}_{3}\)N\({}_{4}\) passivation layer & nm & 50 \\ AlGaN layer & nm & 25 \\ GaN channel layer & nm & 50 \\ GaN buffer layer & \(\upmu\)m & 2.0 \\ Gate head thickness & nm & 250 \\ \hline \end{tabular}
\end{table} 
Table 1: Device geometrical parameters.