## 5 Experimental Results  
The proposed architecture has been described using VHDL language. The complete design flow, including synthesis, place and route has been performed with Synopsys Design Compiler and Cadence Encounter on a 90 nm CMOS standard cell technology with 9 levels of metal and supply voltage equal to 1 V. Post place and route simulations was run to obtain accurate capacitances and switching activities [33], which are necessary for estimating the power consumption. Area and power consumption results for the three codes analyzed in Section 4 with \(p_{S}\in\{5,6\}\), \(p_{R}\in\{3,4\}\) and \(f_{clk}=20\) MHz are shown in Table 1.  
It is worth noting that it is difficult to make a fair comparison of the proposed architectures with other solutions proposed in the literature because the target applications are different. However, for the sake of completeness in Table 2 several LDPC decoder architectures are compared with the most area demanding and power consuming solution among the proposed ones (\(N=576\), \(p_{S}=6\), \(p_{R}=4\), last row of Table 1). As it can be observed, most solutions proposed in the literature address partially parallel architectures designed for wireless communications and broadcasting applications. As a consequence, they are sized to obtain throughput of hundreds of Mb/s or even Gb/s with large blocks of data. On the contrary, the proposed serial architecture is specifically tailored for WSN applications where throughput and block length are much smaller, we assume here \(T\leq 250\) kb/s and \(N\leq 576\). Since the considered architectures have been designed on different technologies, we scale them all to the 90 nm technology node (\(A_{90}\)) for the sake of fairness. The scaling is obtained multiplying the area (fifth column in Table 2) by \((\mathcal{F}/90)^{2}\), where \(\mathcal{F}\) is the feature size shown in the fourth column of Table 2. As expected, the proposed architecture is about one order of magnitude smaller than the other ones (fifth and sixth columns in Table 2). On the contrary, partially parallel architectures consume less energy per bit and energy per bit per iteration than \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{\(\mathbf{N}\)} & \multirow{2}{*}{\(\mathbf{p_{S}}\)} & \multirow{2}{*}{\(\mathbf{p_{R}}\)} & **Area** & \(\mathbf{P_{dec}}\) \\  & & & **[\(\mathbf{\mu}\)m\({}^{2}\)]** & **[\(\mathbf{\mu}\)W]** \\ \hline
96 & 5 & 3 & 66,046 & 359 \\
96 & 5 & 4 & 67,994 & 373 \\
96 & 6 & 3 & 67,752 & 363 \\
96 & 6 & 4 & 69,720 & 379 \\
204 & 5 & 3 & 86,165 & 445 \\
204 & 5 & 4 & 88,670 & 458 \\
204 & 6 & 3 & 88,283 & 448 \\
204 & 6 & 4 & 90,613 & 459 \\
576 & 5 & 3 & 125,257 & 648 \\
576 & 5 & 4 & 131,681 & 670 \\
576 & 6 & 3 & 128,146 & 663 \\
576 & 6 & 4 & 133,934 & 674 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Post place and route area and power consumption of the proposed architecture. serial solutions (eleventh and twelfth columns in Table 2). Assuming that area and energy consumption are the most important metrics to choose a decoder architecture for WSN applications, we introduce two figures of merit. The first one is the normalized area \(\Phi_{A}(k)=A_{90}(k)/\min_{k}\{A_{90}(k)\}\) where \(A_{90}(k)\) is the area of the \(k\)-th architecture scaled to the 90 nm technology node. The second one is the normalized energy per bit per iteration \(\Phi_{E}(k)=E_{I}(k)/\min_{k}\{E_{I}(K)\}\). These two figures of merit represent how far an architecture is from the minimum area and minimum energy per bit per iterations ones respectively. Assuming that \(\Phi_{A}\) and \(\Phi_{E}\) are equally important, their product shows which architecture is more suited for WSN applications among the compared ones. As shown in the last column of Table 2 the proposed architecture is the one with minimum \(\Phi=\Phi_{A}\cdot\Phi_{E}\).