# Programmable Deterministic Zero-Copy DMA Mechanism for FPGA Accelerator
## 1 Introduction  
Currently, the throughput of data-center networks has reached the terabit level, traffic is tending to diversity, and scalable and easy-to-develop microservices are gradually replacing the tightly coupled and large monolithic application architecture code base. As one of the most usual ways to implement microservices, serverless networks pose new challenges to traditional network equipment in terms of asynchronous concurrency, burst unpredictability, component-independent deployment expansion, and rapid development iteration. Commercial NICs have struggled to meet serverless's high throughput, customizable, and deterministic latency data transmission requirements [1] due to hardware design and software driver limitations, which can be summarized as follows. 1. Programmability. Typically, serverless network nodes need to handle a diverse set of requests. Whereas ASIC-based fully customized network devices are complicated to program, commercially available FPGA-based devices often cannot modify device configurations directly. The hardware design closure severely limits researchers' utility and flexibility in developing new network request features. 2. Determinism. With the rise of the Industrial Internet of Things (IIoT), many services require precise control of end-to-end latency and jitter, which commercial NIC-based \"best-effort\" Ethernet cannot meet. Therefore, we need a new generation of network devices that can provide \"on-time, accurate\" transmission quality of service with deterministic latency, deterministic jitter, and accurate transmission control. 3. Data Copying. The frequent data copying between NIC and an Application limits the high-performance data processing of network nodes. When a packet arrives, theNIC copies packets to a ring buffer in the host memory via the PCIe bus with DMA (direct memory access). It then generates a hardware interrupt to notify the CPU of receiving a packet (one interrupt per packet). The CPU allocates a socket buffer (skb) for sending packets to the kernel for layer-by-layer parsing. The application thread eventually taps into the kernel space via the socket's recv() interface and copies the data from the kernel to user space for processing. The host performs the sending process in reverse order. The process above requires 1 DMA copy and 1 CPU copy each. Research studies show that CPU copying of a packet consumes 500-2000 clock cycles (depending on packet size) [2], and frequent CPU copying consumes excessive computational and memory resources. To construct a microservice network node with high processing efficiency to overcome hardware design and software processing limitations, this paper proposes a serverless-oriented programmable deterministic DMA zero-copy FPGA accelerator. At the hardware level, 1000 hardware queues are instantiated. A hardware clock-based deterministic sending mechanism is designed to achieve precise timing control for multiple queues. At the device driver level, a multi-queue-based zero-copy [3] mechanism is introduced to eliminate the CPU cost caused by frequent copying. In addition, to enhance the scalability and flexibility of the service in the serverless scenario, we add a rule-based distribution module to the traditional RSS [4] functionality to enhance the diversity and flexibility of services in the serverless model. This module extends the flow-based distribution for the emerging transport protocol QUIC [5; 6; 7]. Users can program the forwarding behaviour by modifying the flow table through a remote server. In the experimental evaluation section, we simulated the serverless environment. Furthermore, a multi-node packet forwarding topology was designed to test the prototype's throughput rate and forwarding latency under different queue numbers and packet length conditions. This paper presents the design, implementation, and evaluation of a programmable multi-queue FPGA accelerator, which breaks the shackles of existing commercial NIC, whose main innovations can be summarized as follows:  
1.