# Balancing the Leakage Currents in Nanometer CMOS Logic--A Challenging Goal
## 4 Our New Strategy
* **Step 1:** First we simulate the leakage current of a classic NAND gate for all input combinations and calculate the difference between \(I_{L_{00}}\) and \(I_{L_{10}}\). \[\Delta_{0}=I_{L_{00}}-I_{L_{10}}\] (1)
* **Step 2:** If \(\Delta_{0}<0\), we need to increase the static leakage current for \(A=0\), otherwise the current for \(A=1\). In the former case we add either TCB\({}_{1}\) or TCB\({}_{2}\), depending on the magnitude of \(|\Delta_{0}|\), and in the latter case either TCB\({}_{3}\) or TCB\({}_{4}\) are added, again depending on the magnitude of \(|\Delta_{0}|\). In more detail, if \(|\Delta_{0}|<I_{\text{TCB}_{1}}\) or \(|\Delta_{0}|<I_{\text{TCB}_{3}}\) choose TCB\({}_{2}\) or TCB\({}_{4}\) respectively, otherwise choose TCB\({}_{1}\) or TCB\({}_{3}\). It may be necessary or beneficial to add a combination of TCBs to model the complemented static power \(\Delta_{0}\) as accurately as possible. The optimal width and combination of the additional transistors is determined by HSPICE's optimization feature. The additional transistors are incorporated into the gate by connecting signal \(A\) to their drain terminal (and source terminal in the case of TCB\({}_{2}\) or TCB\({}_{4}\)). At the end of this step, we expect \(I_{L_{00}}\approxeq I_{L_{10}}\). * **Step 3:** Next we calculate the average of the new values for \(I_{L_{00}}\) and \(I_{L_{10}}\). \[\left.\begin{aligned} &\left.\begin{aligned} &\left.  
Then we calculate difference \(\Delta_{1}\) as follows. \[\Delta_{1}=Avg_{|_{B=0}}-I_{L_{01}}\] (3)
* **Step 4:** If \(\Delta_{1}<0\), we need to increase the static leakage current for \(B=0\), otherwise the current for \(B=1\). In the former case we add either TCB\({}_{1}\) or TCB\({}_{2}\), depending on the magnitude of \(|\Delta_{1}|\), and in the latter case either TCB\({}_{3}\) or TCB\({}_{4}\) are added, again depending on the magnitude of \(|\Delta_{1}|\). In more detail, if \(|\Delta_{1}|<I_{\text{TCB}_{1}}\) or \(|\Delta_{1}|<I_{\text{TCB}_{3}}\) choose TCB\({}_{2}\) or TCB\({}_{4}\) respectively, otherwise choose TCB\({}_{1}\) or TCB\({}_{3}\). It may be necessary or beneficial to add a combination of TCBs to model the complemented static power \(\Delta_{1}\) as accurately as possible. The optimal width and combination of the additional transistors is determined by HSPICE's optimization feature. The additional transistors are incorporated into the gate by connecting signal \(B\) to their drain terminal (and source terminal in the case of TCB\({}_{2}\) or TCB\({}_{4}\)). At the end of this step, we expect \(I_{L_{00}}\approxeq I_{L_{10}}\approxeq I_{L_{01}}\), which means that the leakage current is close to constant for \(OUT=1\). * **Step 5:** Next we calculate the average of the three input states that lead to \(OUT=1\). \[Avg_{|_{OUT=1}}=(I_{L_{00}}+I_{L_{10}}+I_{L01})/3\] (4) Then we calculate the last difference \(\Delta_{2}\) as follows. \[\Delta_{2}=I_{L_{11}}-Avg_{|_{OUT=1}}\] (5)
* **Step 6:** If \(\Delta_{2}<0\), we need to increase the static leakage current for \(OUT=0\), otherwise the current for \(OUT=1\). In the former case we add either TCB\({}_{1}\) or TCB\({}_{2}\), depending on the magnitude of \(|\Delta_{2}|\), and in the latter case either TCB\({}_{3}\) or TCB\({}_{4}\) are added, again depending on the magnitude of \(|\Delta_{2}|\). In more detail, if \(|\Delta_{2}|<I_{\text{TCB}_{1}}\) or \(|\Delta_{2}|<I_{\text{TCB}_{3}}\) choose TCB\({}_{2}\) or TCB\({}_{4}\) respectively, otherwise choose TCB\({}_{1}\) or TCB\({}_{3}\). It may be necessary or beneficial to add a combination of TCBs to model the complemented static power \(\Delta_{2}\) as accurately as possible. The optimal width and combination of the additional transistors is determined by HSPICE's optimization feature. The additional transistors are incorporated into the gate by connecting signal \(OUT\) to their drain terminal (and source terminal in the case of TCB\({}_{2}\) or TCB\({}_{4}\)).