## 7 Results and Analysis  
We implemented a testbench in Verilog HDL to check system timing. Table 8 shows the time consumption of the system in all cases. Since the two subtries always exist (in real-life routing tables) in Level 1, where the total number of potential subtries is \(2^{1}\), and Level 1 has no false positives, the special case of the default prefix matching is not shown. In the following, we denote the subsystem before two FIFO buffers (including the CBHF, Bitmap Lookup, and PR-Trie Lookup modules) as \"Phase \(1\)\", and the following subsystem as \"Phase \(2\)\", which can be seen in Figure 5. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Resource**} & \multirow{2}{*}{**Available**} & \multicolumn{2}{c}{**1 k**} & \multicolumn{2}{c}{**5 k**} & \multicolumn{2}{c}{**25 k**} \\ \cline{2-7}  & & **Used** & **Utilization (\%)** & **Used** & **Utilization (\%)** & **Used** & **Utilization (\%)** \\ \hline LUT & 433,200 & 2506 & 0.58\% & 2505 & 0.58\% & 2778 & 0.64\% \\ FF & 866,400 & 2510 & 0.29\% & 2524 & 0.29\% & 2538 & 0.29\% \\ BRAM & 1470 & 26 & 1.77\% & 42 & 2.86\% & 135.5 & 9.22\% \\ IO & 850 & 89 & 10.47\% & 89 & 10.47\% & 89 & 10.47\% \\ BUFG & 32 & 1 & 3.13\% & 1 & 3.13\% & 1 & 3.13\% \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Hardware resource utilization. \begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline  & \multicolumn{2}{c}{**1 k**} & \multicolumn{2}{c}{**5 k**} & \multicolumn{2}{c}{**25 k**} \\ \hline Total on-chip power (W) & 0.397 & 0.435 & 0.463 \\ Worst negative slack (ns) & 2.518 & 2.413 & 2.310 \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Worst negative slack and power consumption. \begin{table}
\begin{tabular}{c c c c c c c c c c c} \hline \hline \multirow{2}{*}{**Routing**} & \multicolumn{2}{c}{**CBHF**} & \multicolumn{2}{c}{**Bitmap**} & \multicolumn{2}{c}{**IMG. Root**} & \multicolumn{2}{c}{**Total FIFOs**} & \multirow{2}{*}{**Total BRAMs**} \\ \cline{2-2} \cline{6-9}  & **(\# of Blocks)** & & **(\# of Blocks)** & & **(\# of Blocks)** & & **(\# of Blocks)** & & **(KB)** & **(\%)** \\ \cline{2-9}
**Prefix Set** & **18 kb** & **36 kb** & **18 kb** & **36 kb** & **18 kb** & **36 kb** & **18 kb** & **36 kb** & **(KB)** & **(\%)** \\ \hline
1 k & 3 & 1 & 1 & 18 & 0 & 1 & 6 & 1 & 117 & 1.77\% \\
5 k & 2 & 2 & 1 & 32 & 0 & 2 & 5 & 2 & 189 & 2.86\% \\
25 k & 2 & 5 & 1 & 117 & 1 & 7 & 5 & 2 & 609.25 & 9.22\% \\ \hline \hline \end{tabular}
\end{table} 
Table 5: On-chip memory requirement in hardware implementation. As shown in Table 8, for the worst case, in which there is a false positive in each filter except Level 1, the number of subtrie accesses is 4, and the time consumption in Phase 1 is 14 clock cycles (clks). Similarly, in other cases, the results are also obtained. Since there is a pipelining design between two phases, the lookup time of the system (\(T_{\text{sys}}\)) is the maximum in two phases. Hence, the theoretical throughput (\(X\)) can be calculated as follows:  
\[X=\frac{F}{T_{\text{sys}}}\cdot(E_{\text{p}}+E_{\text{s}}+E_{\text{fmin}}+E_{ \text{i}}). \tag{20}\]  
The meanings and values of notations used in Equation (20) are shown in Table 9. In addition, using Equation (16), we also obtain the average system throughput for each testing routing prefix set, which is shown in Table 10.  
In order to evaluate the system throughput more objectively, we constructed the relevant hash tables and linear tables for each routing prefix set (in conditions of different system configurations) offline. Then, we randomly tested 100 k IP addresses for each routing prefix set. Table 11 reports their average time per lookup and their system throughput. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline  & \(\mathbf{1\,k}\) & \(\mathbf{5\,k}\) & \(\mathbf{25\,k}\) & \(\mathbf{Average}\) \\ \hline Average lookup & & 49 & 49 & 50 & 49.333 \\ time (ns) & & & & & \\ System & & & & & \\ throughput & 13.714 & 13.714 & 13.440 & 13.623 \\ (Gbps) & & & & & \\ \hline \hline \end{tabular}
\end{table}