# Low-Power Wireless Data Transfer System for Stimulation in an Intracritical Visual Prosthesis
## 3 System Architecture
### Reducing Receiver Clock Frequency  
The role of the reset generator module in the implanted receiver (see Figure 2) is to provide a reset signal to reset the edge detector at a time after the detection of the current edge \(t=0\). This needs to be done at a time \(0.5T_{psk}<t<T_{psk}\) to avoid the transition point between symbols, where \(T_{psk}\) is the period of the carrier signal. To achieve this, it uses an asynchronous counter to count from a time of current edge detection \(t=0\) to a time \(0.5T_{psk}<t<T_{psk}\). We determine the frequency of the clock, which is essentially the frequency of the oscillator, as follows. With a count-up number \(N\), the following inequalities must be satisfied. To reset after the transition point between carrier symbols, we have:  
\[(N-1)T_{osc}>0.5T_{psk}, \tag{1}\]  
and to ensure that there is no reset after the next edge, we get:  
\[NT_{osc}<T_{psk}, \tag{2}\]  
Therefore, the range for the clock frequency is given by:  
\[Nf_{psk}<f_{osc}<2(N-1)f_{psk}, \tag{3}\]  
where \(f_{psk}=\frac{1}{T_{psk}}\) is the carrier frequency and \(f_{osc}\) is the oscillator frequency. A practical reset timing constraint relates to the presence of realistic inductive links, in which the phase transition is sometimes not instantaneous. For flexibility in the reset timing, we write in a more general form:  
\[\frac{N}{c_{upper}}f_{psk}<f_{osc}<\frac{N-1}{c_{lower}}f_{psk}, \tag{4}\]  
Figure 4: Ideal channel response.  
where \(c_{upper}\) and \(c_{lower}\) are the set limits on the reset timing. It is observed that a higher count-up number \(N\) is needed if the range is to be made finer. This implies higher clock frequency.  
The power consumption of the digital demodulator is proportional to the clock frequency. Since the carrier-to data ratio is below one due to bandwidth limitations, in the digitized received signal, there will be repeated bits, since more than one cycle of the carrier-waveform will represent a data symbol [17]. The clock frequency can be reduced by skipping a few periods \(p\) during the non-coherent demodulation. The reduction in clock frequency, in turn, will reduce power consumption. The carrier-to-frequency ratio is inversely proportional to the number of bits that will be repeated in the digitized received signal. For reducing the receiver clock frequency by skipping \(p\) periods, we get modified versions of Equations (1) and (2):  
\[(N-1)T_{osc}>(c_{lower}+p)T_{psk}, \tag{5}\]  
and  
\[NT_{osc}<(c_{upper}+p)T_{psk}. \tag{6}\]  
The resulting clock frequency is given by:  
\[\frac{N}{c_{upper}+p}f_{psk}<f_{osc}<\frac{N-1}{c_{lower}+p}f_{psk}. \tag{7}\]  
For instance, circuit simulation shows that at a data rate of 1.25 Mbps, a carrier frequency of 10 MHz and count-up number of \(N=16\), the clock frequency of the digital demodulator can be reduced from 23 MHz to 5.8 MHz when \(p=2\) periods are skipped. This reduces the power consumption from 0.29 mW to 0.15 mW for the non-coherent digital demodulator sub-block. Although generally, the overall power consumption is technology dependent, there is always a reduction in power consumption brought about by reducing the clock frequency by skipping redundant bits.