## 2 Modeling
### Hybrid Logic Dynamic Model of the T\({}^{2}\)3L Inverter  
The topology of the T\({}^{2}\)3L inverter is shown in Figure 1. U\({}_{\text{dc}}\) denotes the DC side voltage, where \(C_{1}\) and \(C_{2}\) are the DC-link capacitors. Point \(O\) represents the midpointof the DC bus, serving as the neutral point. Each phase of the inverter consists of four power switches \(T_{xi}(x=a,b,c;\ i=1,2,3,4)\) along with their corresponding anti-parallel diodes. Where \(T_{x1}\) and \(T_{x4}\) are connected to the positive and negative terminal of the DC bus respectively, referred to as bridge arm switches; \(T_{x2}\) and \(T_{x3}\) connect the neutral point \(O\) and the output point \(x\), referred to as midpoint switches. The inverter's output current is filtered through inductor \(L\) before being delivered to the resistive load. The unique topology of the T\({}^{2}\)3L inverter creates a pronounced asymmetry in voltage stress distribution. Specifically, the bridge-arm switches withstand the full DC-link voltage (U\({}_{\text{dc}}\)), while the neutral-point switches are subjected to only half the voltage (0.5U\({}_{\text{dc}}\)). During positive/negative voltage output generation, its single-device conduction mechanism significantly reduces conduction losses. This advantage contrasts sharply with conventional NPC inverters, which require multiple series-connected devices for the same operation. However, the high voltage rating of the arm switches introduces substantial switching losses. This issue is particularly pronounced under high-voltage operating conditions, significantly degrading the system's overall efficiency. Consequently, the T-type topology demonstrates efficiency advantages primarily in low-voltage applications. In such scenarios, the optimized conduction losses effectively offset the penalties from switching losses. Depending on Figure 1, the system's state equation can be expressed as:  
\[ \begin{cases}u_{\text{an}}=R\dot{u}_{\text{a}}+L\dfrac{\text{d}\dot{u}_{\text{a }}}{dt}\\ u_{\text{bn}}=R\dot{u}_{\text{b}}+L\dfrac{\text{d}\dot{u}_{\text{b}}}{dt}\\ u_{\text{cn}}=R\dot{c}_{\text{c}}+L\dfrac{\text{d}\dot{c}}{dt}\end{cases}  \tag{1}\]  
where \(u_{\text{an}}\),\(u_{\text{bn}}\), \(u_{\text{cn}}\) are the three-phase voltages of the inverter. According to [PERSON]'s voltage law and the Y-connection, the three-phase voltage takes the form:  
\[ \begin{bmatrix}u_{\text{an}}\\ u_{\text{bn}}\\ u_{\text{cn}}\end{bmatrix} =\dfrac{1}{3} \begin{bmatrix}2&-1&-1\\ -1&2&-1\\ -1&-1&2\end{bmatrix}\begin{bmatrix}u_{\text{ao}}\\ u_{\text{bo}}\\ u_{\text{co}}\end{bmatrix}  \tag{2}\]  
Figure 1: T\({}^{2}\)3L inverter topology. Define \(S_{xi}\) as the switching signal for switch \(T_{xi}\), where \(S_{xi}=1\) indicates the on-state of the switch, whereas \(S_{xi}=0\) indicates the off-state. The positive direction of the specified current is defined as flowing from the DC side to the AC side of the inverter, represented as \(\sigma_{x}=1\), while the reverse direction is represented as \(\sigma_{x}=0\). Using phase as a representative case, Table 1 delineates the relationship between switching signals and output voltage under normal inverter conditions. Here, \(u_{c1}\) and \(u_{c2}\) represent the terminal voltages of capacitors \(C_{1}\) and \(C_{2}\). Under normal operating conditions, \(u_{ao}\) is derived from the logical relationship among switching states, current direction, and pole voltage, expressed as:  
\[u_{ao}=\sigma_{a}(S_{a1}u_{c1}-S_{a1}S_{a3}u_{c2})-\bar{\sigma}_{a}(S_{a4}u_{c 2}-S_{a2}S_{a4}u_{c1}) \tag{3}\]  
Similarly, the pole voltages of the remaining two phases are given by:  
\[ \begin{split} u_{bo}&=\sigma_{b}(S_{b1}u_{c1}-S_{ b1}S_{b3}u_{c2})-\bar{\sigma}_{b}(S_{b4}u_{c2}-S_{b2}S_{b4}u_{c1})\\ u_{co}&=\sigma_{c}(S_{c1}u_{c1}-S_{c1}S_{c3}u_{c2})- \bar{\sigma}_{c}(S_{c4}u_{c2}-S_{c2}S_{c4}u_{c1})\end{split}  \tag{4}\]  
According to Equations (2)-(4), the expression for the three-phase voltage is converted to:  
\[\left[ \begin{array}{c}u_{an}\\ u_{bn}\\ u_{cn}\end{array} \right]=\frac{1}{3}\left[