## 3 Results and Discussion
### Electrochemical Studies
The semicircle intercept near the high-frequency region gives the series resistance (R\({}_{\text{s}}\)), the semicircle radius gives an estimate of the charge transfer resistance (R\({}_{\text{ct}}\)), while Cp and W indicate the pseudocapacitance value and Warburg resistance, respectively, which are estimated from the line inclination in the low-frequency region [14]. Table 2 shows the Nyquist plot fitting equivalent impedance parameters before and after 10,000 cycles at a frequency range of 100 kHz to 0.01 Hz at 0.1 bias voltage. Even after a huge 10,000 GCD cycling, it shows an almost similar impedance parameter, which illustrates the better mechanical stability and non-degradation of the INS-based electrode materials. Furthermore, the Ragone plot (Figure 5g) estimates the operational and practical utility of the as-prepared electrode samples. The high-power density is a measure of faster charging, while the energy density measures the amount of energy that can be stored in the electrode. This clearly gives an idea for estimating the form factor of the SSC device for a particular application. The sample INS5 has a decent energy density of 26 Whkg\({}^{-1}\) at a power density of 431 Wkg\({}^{-1}\). Lastly, the long-term stability was evaluated by GCD cycling up to 10,000 cycles (Figure 5h), which showed that the electrode material INS5 maintained 97.79% of its starting capacity (significantly higher than bare INS0-82.44% and higher than sample INS1-88.81%), proving its excellent long-term endurance. The inset in Figure 5h shows a schematic of an INS5 robust structure with SWNT integration to provide reinforcement and keep the structure stable in the face of electrochemical reactions, resulting in high endurance. The inset of Figure 5h shows how the SWNT reinforces the INS5 electrode material, which leads to a robust nanostructure and ensures long-term stability. Another important performance factor to consider when evaluating the suitability of SCs for potential implementation is their self-discharge (SD) behavior, and voltage-holding (VH) capability. The loss of the charged potential without any load at OCP (open circuit potential) is referred to as the SD of an SC. However, VH refers to the ability to maintain a constant voltage for a specified period. The current leakage in INSC is evaluated at the VH test. For all prepared SSC devices from samples INS0, INS1, INS2, and INS5, Figure 6a-d show four continuous cycle measurements of GCD (100 cycles), followed by a 2 h VH test, and thereafter, an SD test for all fabricated SSC devices. For each cycle, the GCD cycle was performed at 1 Ag\({}^{-1}\) in the potential window ranging from 0 to 1.0, while the VH test was performed for 2 h at constant supply 1.0 V, and the SD test was performed at OCP (no potential). The leakage current measured during the voltage holding test is critical in determining the fabrication errors in the device [56]. The leakage current of an SSC is caused by irreversible side reactions between the electrodes and electrolytes directly related to the device architecture. The leakage current value is preferably less because the high value indicates that the separator has shorted the connection between the two electrodes [57]. The leakage current (Figure 6e-h) drops abruptly in the range of 5-25 uA in this measurement, which occurs at the start of the 1.2 V holding test. It gradually shifts into the constant mode for the 2 h VH test duration. A four-cycle VH \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Sample**} & **Series Resistance** & **Charge Transfer Resistance Rct (f)** & **Warburg Resistance W (f)** & **Capacitance Cp** \\ \hline Before 10,000 & 0.526 & 2.13 & 0.915 & 1.230 \\ Cycle & & & & \\ \hline After 10,000 & 0.723 & 3.043 & 0.934 & 1.163 \\ Cycle & & & & \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Estimated impedance parameters from the Nyquist plot of sample INS1. test, performed continuously over a period of two hours, reveals virtually no internal resistance under device-level performance [58].