# FPGA Applied to Latency Reduction for the Tactile Internet
## 7 Results
The \(t_{s}\) column represents the sampling rate in nanoseconds that was obtained for each hardware module. Finally, the \(R_{s}\) column displays throughput (\(R_{s}=\frac{1}{t_{s}}\)) values in mega-samples per second for the hardware modules. The synthesis results presented in Table 2 show that the resources used for the FK-HMD and FK-HSD modules were the same. This means that each module, individually, used a percentage of 1.01% which is equivalent to 3041 of the available hardware resources for the registers, was used 5.31% with LUTs, and 1.43% for embedded multipliers DSP48. The IK-HSD module had a hardware percentage consumption of 1.04% for registers, 9.36% for LUTs and 3.52% for multipliers. The KFF-HMD module had a consumption of 1.03%, 8.13% and 6.25% for registers, LUTs and multipliers, respectively. Finally, the FBF-HSD module used a percentage of 0.11% for registers, 0.82% for LUTs and 1.17% for multipliers. Based on data presented in Table 2, the HMD modules (FK-HMD and KFF-HMD) that is associated with the MD device has consumed 6154 (2.04%) for register, 20,259 (13.44%) for LUTs and 59 (7.68%) for multipliers. In the case of hardware associated with the SD device, the HSD modules (FK-HSD, IK-HSD and FBF-HSD) had consumed 6513 (2.16%) for register, 23,351 (15.49%) for LUTs and 47 (6.12%) for multipliers. The hardware resources consumed by the HMD hardware modules and the HSD hardware modules were very low. Even if all modules are implemented in single hardware, the consumption remains low. The total sum of hardware resources used in the FPGA by all modules (FK-HMD, KFF-HMD, FK-HSD, IK-HSD and FBF-HSD) was: 12,667 (4.20%) for register, 43,610 (28.93%) for LUTs and 106 (13.80%) for multipliers. The low hardware resources consumption demonstrates that the proposed implementations take up little hardware space in the FPGA which allows other separate implementations to be used concomitantly. As per Table 2, the throughput values, \(R_{s}\), obtained were significant. Values of 21.27 MSps for the FK-HMD and FK-HSD modules, 4.58 MSps for the IK-HSD module, 14.28 MSps for the KFF-HMD module and 47.61 MSps for the FBF-HSD module were achieved. These results enable critical applications that demand strict time constraints, as is the case with tactile internet applications. The times presented in Table 2 show the critical path (path in the entire design with the maximum delay) on FPGA. In Table 3, it is possible to see the speedup obtained about latency time constraints. The first column shows the latency constraints for 1 ms and 10 ms [9; 10; 11; 12]. The second column shows the minimum latency values required for the application to function normally (these values are the estimates obtained by Equation (71) for both time constraints). The third column shows the latency related to the hardware implementation presented here. The speedup, fourth column, is calculated using the values of minimum time, Latency Limit, for each constraint and the time of the proposed hardware. It is worth mentioning that this is an estimate to guide the calculations. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Module** & **Registers** & **LUTs** & **Multipliers** & \(t_{s}\) & \(R_{s}\) \\
**Name** & **(Flip-Flops)** & & **(DSP48)** & **(ns)** & **(MSps)** \\ \hline FK-HMD & 3041 (1.01\%) & 8008 (5.31\%) & 11 (1.43\%) & 47 & 21.27 \\ KFF-HMD & 3113 (1.03\%) & 12.251 (8.13\%) & 48 (6.25\%) & 70 & 14.28 \\ FK-HSD & 3041 (1.01\%) & 8008 (5.31\%) & 11 (1.43\%) & 47 & 21.27 \\ IK-HSD & 3149 (1.04\%) & 14,107 (9.36\%) & 27 (3.52\%) & 218 & 4.58 \\ FBF-HSD & 323 (0.11\%) & 1236 (0.82\%) & 9 (1.17\%) & 21 & 47.61 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: FPGA resource utilization, sampling rate and throughput results for floating-point format. The 1 ms restriction corresponds to the maximum latency limit of 37.5 \(\upmu\)s for acceptable hardware performance.