## 5 Results and Discussion
### Resources' Consumption  
To reduce PAPR in OFDM transmitted signal, in [29], the authors proposed another alternative solution based on Adaptive Neuro-Fuzzy Inference System (ANFIS). To map inputs to the membership functions, the proposed ANFIS [29] uses a Gaussian membership function based on an exponential function as shown in Figure 20, where \(C\) and \(\sigma\) are, respectively, the center and the variance of the Gaussian membership function. To implement the exponential function, in [30], the authors proposed a new approximation method based on Taylor series. Altera provides also in their intellectual property core (IP core) library a floating-point exponential function (ALTF_EXP) [31]. Table 4 provides a comparison of consumed resources between the triangular function presented in Figure 7, ALTF_EXP and the proposed approximation in [30]. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Solutions** & **FPGA Chip** & **ALUT** & **DSP Blocks** & **Memory** & **Max. Freq. (MHz)** \\ \hline Triangular function & Stratix II & 42 & 0 & 0 & 370 \\ Proposed approximation in [30] & Stratix II & 154 & 28 & 0 & 280 \\ ALTF\_EXP & Stratix II & 1177 & 35 & 232 & 274 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Resource consumption of Tribas versus Exponential functions. Figure 19: BER of the implementations for a CM4 channel. Figure 20: Gaussian membership function. From Table 4, we can easily notice that the implemented triangular function is faster and consumes less FPGA resources (for example less adaptive lookup tables (ALUT)) than the implemented exponential functions. For these reasons, in this article, we opted for neural networks' architecture with triangular activation function instead of ANFIS architecture or any other architectures based on exponential functions. Among the hardware solutions, we quoted the GC1115 proposed by Texas Instruments (Dallas, TX, USA) [32]. It operates on a maximum of 32 MHz bandwidth and allows the reduction of the Crest Factor (CF) in the Wideband Code Division Multiple Access (WCDMA) and OFDM signals. The drawback of this type of solution lies in the fact that it requires a hardware implementation and therefore the total modification of the electronic circuit. To overcome this disadvantage, the two competitors Xilinx and Altera offer software defined solutions that can be implemented on FPGA chips. In fact, Xilinx integrates in its Intellectual Property Core (IP Core) library a kernel named Peak Cancellation Crest Factor Reduction (PC-CFR) [33], which reduces the crest factor of the following communication standards: CDMA2000, WCDMA, WiMAX and LTE, while Altera offers in its library the Crest Factor Reduction (CFR) module [34] destined to the same standards. Unfortunately, these two solutions are subject to very costly licenses. As long as all these solutions allow processing in the time domain, a comparison with the time-domain NN is covered out. This comparison will allow us to estimate the resources exploited on different FPGA chips as well as the maximum frequency supported by each solution. Tables 5 and 6 show the results of this comparison. From these tables, we can conclude that our solution based on time-domain NN is much less resource-consuming than former solutions and implementations. In the case of an implementation on Xilinx chips, we note that the number of DSP blocks is zero. This is justified by the fact that all the multiplication operations are realized by logical elements. With regard to the use of the Look-Up Tables (LUT), the time-domain NN allows for 60%, 53.7% and 55% reductions, respectively, for Virtex-5, Spartan-6 and Virtex-6. Since all weighting coefficients and biases are stored directly on the FPGA logic circuits, our solution does not use any memory blocks, which impacts the resources consumption and the operating frequency directly.