# Inferring TLB Configuration with Performance Tools
## 3 Results
### Analysis Results  
1. Intel Xeon CPU DTLB: The analysis for the gradient plot for the event dtlb_load_misses.stlb_hit aligns with our expectations. As illustrated in Figure 2b,'sets' 16 experiences an increase after 'ways' 4, characterized by an increasing slope. The red, purple, and brown lines increase in the same 'ways', but the red line is the first to show an event increase and has the highest rate of change. Although this plot could be employed independently to deduce the DTLB configuration, this technique needs support from Tables 1-3 to yield consistent results across other TLB levels or CPU ISA. The analysis of the heatmap results also aligns with our expectations, as anticipated in [14, 15]. In Figure 2a, observing dtlb_load_misses.stlb_hit, we discern a clear pattern: it starts with a low number of misses (indicated by dark blue), and as 'ways' increase, the number of misses rises (shown by lighter colors). Without prior knowledge of the TLB configuration, one would examine the heatmap to identify the lowest 'ways' that exhibit an increase in misses. The lowest such 'ways' is 4, occurring at'sets' 16, 32, and 64. Since we aim to identify the smallest combination, we select'sets' 16 and 'ways' 4, which aligns with Table 1.  
ITLB: The analysis of the gradient methodology for itlb_load_misses.stlb_hit, shown in Figure 3b, reveals that sets 16, represented by the red line, experience a quicker increase compared to other data series in the plot, specifically the purple and brown lines, suggesting a method to identify the configuration. Following the process that the lowest'set'-ways' combination is the correct configuration, the red line confirms that'sets' 16 and 'ways' 8 constitute the ITLB configuration. This contradicts Table 1, as can also be observed in the heatmap. Employing the heatmap reveals a discernible pattern, as shown in Figure 3a, yet it does not align with the data presented in Table 1. We expected the minimal ways showing an increase in events, specifically 8, to indicate the correct configuration. This increase, however, is observed at'sets' 16 and 'ways' 8. Contrary to the specifications provided by the manufacturer, which in the past have shown to be inaccurate as indicated in [15], this study concludes that the correct configuration is indeed'sets' 16 and 'ways' 8. STLB: The second stage is more challenging, primarily because it does not utilize a linear mapping function for selecting'sets', making the probing of addresses significantly more difficult. This study concludes that the STLB employs an XOR-7 mapping with 128'sets'. To infer the STLB configuration, the gradient method needs to be used in conjunction with the size of the STLB, known to be 1536. Figure 4b reveals that a change in the gradient is only noted when the set count is 128, XOR-7, offering no clear indicators or patterns that would assist in determining the number of 'ways'. In this instance, the gradient plot serves as one part of the puzzle, providing the'sets' count of 128. The other piece is the size of 1536. The 'ways' can be found by dividing the size by the'sets', which results in 'ways' of 12. Thus, an XOR-7 mapping with 1536 entries suggests a 12-way configuration. Contrary to the official data, which indicates 256'sets' and 6 'ways', the heatmap distinctly shows activity only in the scenario of XOR-7, as shown in Figure 3(a). Figure 3: _Cont_. Figure 2: Intel Xeon DTLB heatmaps and gradient plots are shown. In Figure (**a**), the red square highlights the configuration of 16 ’sets’ and 4 ’ways’. In Figure (**b**), the red line for 16 ’sets’ distinctly shows an increase at 4 ’ways’. Figure 4: Intel Xeon STLB heatmaps and gradient plots. Figure (**a,b**) indicate that the STLB employs an XOR-7 mapping function. Figure 3: Intel Xeon ITLB heatmaps and gradient plots are shown. In Figure (**a**), the red squares highlight two potential configurations. The methodology confirms that the configuration of 16 ‘sets’ and 8 ‘ways’ is the correct one.