## 2 The Proposed Converter Topology  
In the HESS, the rated energy capacity (REC) of the SC is defined considering an ideal SC that can be fully discharged as:  
\[\text{EC}=\frac{1}{2}\;\text{C}\;\text{V}_{\text{max}}^{2} \tag{1}\]  
where C and Vmax are the rated capacity and the maximum voltage of the SC, respectively. However, due to the difficulty to fully discharge the SC and the extremely high current required to handle a given power share at low voltage levels, the sizing of the SC is usually performed considering the utilized energy capacity (UEC), which is defined as:  
\[\text{UEC}\;=\frac{1}{2}\;\text{C}\left(\text{V}_{\text{max}}^{2}-\text{V}_{ \text{min}}^{2}\right) \tag{2}\]  
where Vmin is the selected minimum voltage of the SC. Therefore, the utilization level of the REC of the SC is determined by its allowed maximum and minimum voltages, which are determined by the interfaced converter capabilities. Figure 2a illustrates the effects of the selected maximum and minimum voltages (as relative to a constant bus voltage Vo) of the SC unit on the utilized energy capacity for the SC cells within the unit in one hand and the maximum current for the SC unit on the other hand. As can be observed, considering a simple boost converter for interfacing the SC limits its Vmax to be around the bus voltage (Vo), and hence the UEC can be enhanced only by minimizing Vmin, which in turn maximizes the current stress of the SC (Imax) and occurs at the selected Vmin and the current rating of the converter. Point A in the graph represents common designs of Vmax for the SC at Vo and Vmin at 0.5 Vo, which results in utilizing only 75% of the REC of the SC-cell whilst Imax is twice the load current (Io). Increasing the UEC of the SC under this topology is possible by applying more reduction in Vmin, which requires the converter to operate at a large duty cycle reducing its efficiency, and significantly increasing Imax compared to Io as depicted by point B in the graph at which 93.75% of the REC utilization can be achieved (25% increase in utilization compared point A) by setting Vmin at 0.25 Vo but at the cost of increasing Imax to four times the load current (Io). Reasonable efficiencies for the converter at such low levels of Vmin can be achieved by using other boost converter topologies such as the topologies proposed in [17; 18], which can achieve a high boosting ratio at sufficient efficiency, but at the cost of the increased number of semiconductor switches and passive elements in addition to the increased current stress of the converter and SC. Figure 2: (**a**) Variation in UEC of SC-cells with different design choices for maximum and minimum voltages of SC unit as relative to the constant bus voltage; (**b**) schematic diagram for the proposed MPC topology. Implementing a buck-boost converter for interfacing the SC to the DC-bus instead of the boost converter can enable a significant increase in the UEC of the SC by allowing V\({}_{\text{max}}\) to be increased above Vo and hence extend the voltage range of the SC whilst maintaining V\({}_{\text{min}}\) at a reasonable level to limit I\({}_{\text{max}}\). Accordingly, designing V\({}_{\text{max}}\) of the SC at 2 Vo and V\({}_{\text{min}}\) at 0.5 Vo can result in utilizing 93.75% of the REC (as deprecated by point C in the graph), which is the same utilization level at point B but at a reduced I\({}_{\text{max}}\) (50% compared to point B). Increasing V\({}_{\text{max}}\) beyond 2 Vo increases the utilization level REC but at a less significant rate (at point D, only 3.7% increase in the utilization of the REC compared to point C that corresponds to a 50% increase in V\({}_{\text{max}}\)). Many buck-boost converter topologies can be implemented for this purpose such as those proposed in [20; 23]; however, this also in the cost of the increased number of semiconductor switches and/or passive elements.