# DRAM Retention Behavior with Accelerated Aging in Commercial Chips
## 2 Background and Motivations
### DRAM Organization and Operation  
A modern DRAM system is organized into a hierarchy of channel, rank, bank, DRAM chips, DRAM cells, and memory controller, as illustrated in Figure 1. Memory commands, address space, and data are driven between the memory controller and DRAM modules by the memory channel. Depending on the memory requirement, there might be one or multiple DRAM modules. DRAM modules are divided into one or multiple ranks. A rank consists of several DRAM chips (generally 4/8/16) and provides a wide data-bus (usually 64 bits) together.  
To support the parallelism, each DRAM chip consists of multiple banks. In a memory bank, the DRAM cells are placed in a two-dimensional array. The memory address is divided into a row address and column address, which are decoded by a row and a column decoder during a read or write operation to find the corresponding cell. The rows of the DRAM are known as wordlines (or pages). The columns are known as bitlines, and the chip density determines the total number of rows. The bitlines are connected to the row-buffer, which is a row of sense-amplifier. A DRAM cell consists of two components: an access transistor and capacitor to hold a charge. The charging state of the capacitor determines the stored value. The access transistor is used to access the stored value. A fully charged capacitor represents logic '1', and an empty capacitor represents logic '0'. The access transistor connects the capacitor with a bitline and is controlled by the wordline. The DRAM content (i.e., the state of charge in the capacitor) is read or overwritten by activating a wordline. A \(V_{dd}\) to the wordline makes a path between the capacitor and bitline. The bitlines also connect the DRAM cell to the sense amplifier (i.e., row-buffer).  
Initially, in the precharge state, all bitlines are precharged to \(V_{dd}/2\). In the next state, the wordline is activated by raising the value of the wordline to \(V_{dd}\). Once the pass-transistor of the DRAM cell is ON, the charge flows between the capacitor and the respective bitline. The charge moves from the bitline to the capacitor if the stored value is '0' and vice-versa. In the last stage, the sense-amplifier attached to the bitline amplifies the bitline voltage to strong logic '1' (or '0'). Cell data are then read or written by sensing or driving the voltage of the corresponding bitlines. DRAM cells lose data over time as the cell capacitors discharge gradually and need to be replenished periodically. This operation is known as refresh operation, and the time required is the retention time (\(t_{ret}\)). The voltage change due to capacitor discharge is known as voltage perturbation. The data stored on the DRAM cell are lost when the sense amplifiers cannot reliably differentiate the perturbation from noise. Traditionally, DRAM cells are required to have a retention time equal to or greater than 64 ms to preserve data integrity. Recall that sense amplifiers drive each bitline fully to \(V_{dd}\) or 0 V when a row is activated. Consequently, the activated row's cell capacitor is fully charged to \(V_{dd}\) or 0 V.