## 3 Tests and Results
### 3U Backplane Verification  
The four CPLDs in the backplane served as multiplexers, allowing the 13 mission boards to access the bus system's digital interfaces. Each CPLD's code was generated using very high-speed integrated circuit description language (VHDL). Lattice ispLEVER Classic was the design environment tool used to complete device design, including concept, synthesis, and simulation, as well as to generate the device joint electron device engineering council (JEDEC) programming file. Lastly, the JEDEC file was loaded into Lattice Diamond Programmer to program the CPLD via its JTAG pins. Figure 9: KITSUNE configurable backplane (**top** and **bottom** sides). The backplane board's functionality was validated by comparing the input and output signals of the OBC/EPS and mission board interfaces. To pass the functionality test, the two signal waveforms must be identical. The combination of logic levels on the four select pins determined which mission board had access to the bus interfaces. For example, in Figure 10, the select pins (9-12) were set to 0001. This combination allows Mission 1 access to the bus. The Digilent Digital Discovery instrument was used in the test as both a pattern generator and a logic analyzer. The instrument generated a 1 MHz clock as input to the OBC/EPS board, and the output signal from Mission 1 was compared to the input clock using the logic analyzer function. According to the waveforms, the output signal followed the logic values of the input signal. The same test was run on each of the 13 mission boards, and no differences were found. A bit error test was also performed to further validate the functionality of the backplane. For this test, a data stream was sent to the OBC/EPS digital interface and received by a mission through a CPLD. The data received from the mission were then compared to the data transmitted to check for possible bit differences. As illustrated in Figure 11, the Raspberry Pi module transmitted a bit array every 300 ms, and it reported the number of bit errors when it detected differences between transmitted and received data. This method was repeated for three different baud rates, such as 1 Mbps, 2 Mbps, and 4 Mbps, on each  
Figure 10: Functional test setup. mission board. While all mission boards had no bit differences recorded, the findings demonstrated the reliability and integrity of the backplane. One important note from this test is that the time difference between the transmission and reception of the data stream does not represent the transmission delay, which is explained next. The transmission delay, defined as the time it takes for the data packet to arrive at the mission board, is another validated parameter. A significant delay may result in errors in the received data. Figure 12 shows the input and output signals as observed in the oscilloscope. The right photo shows that the two signals were identical. The waveforms were zoomed in for accurate delay measurements. All mission boards had their measurements taken, and Table 5 summarizes the measured transmission delay. The measured values were grouped based on the number of CPLDs through which the signal passed. In addition, the delay was measured twice for each mission board using different signal input sources--a Digilent Analog Discovery pattern generator (Test 1) and a function generator (Test 2). According to the results, the transmission delay of a single CPLD was approximately 5.0 ns. When a signal was transmitted through all four CPLDs, the transmission delay was measured as approximately 20.0 ns. Lastly, it is concluded that the measured transmission delay could not produce bit errors in data arrays. Lastly, the power consumption of the backplane board was investigated since the available power for a small satellite platform such as CubeSats with limited resources determines survivability in orbit as well as the ability to support multiple payloads. The current consumption was measured at the 3.3 V input to the voltage regulator under two conditions as idle mode and active CPLDs.