## 5 Results and Discussion  
The simulation results of the proposed converter with various PWM schemes are clearly explained in this section. The parameters chosen for the simulation are given in Table 2. From Figure 10, we can see that the converter is operated with a modulation index (MI) of 0.5 from t = 0.8 s to t = 1.2 s, and it is operated with M = 0.95 from t = 0.8 s to t = 1.2 s. It is observed from Figure 10a,k that the THD in line voltage of the converter with d-q control and SPWMLSC is 2.58% at 50 Hz. respectively. In addition, from Figure 10b,m, the THD in line voltage of the converter with d-q control and SPWMPSC is 1.63%. Similarly, the  
Figure 8: General pulse width modulation classification based on switching frequency. Figure 9: Modulation schemes conducted on this converter. (**a**) Sine PWM with level-shifted carrier (SPWMLSC); (**b**) Sine PWM with phase-shifted carrier (SPWMPSC); (**c**) Sine with third harmonic injected level-shifted carrier (STHILSC); and (**d**) Sine with third harmonic injected phase-shifted carrier (STHIPSC). THD in line current with d-q control and SPWMLSC is 12.20% and with SPWMPSC is 6.64% at 50 Hz, as shown in Figure 10c,l, respectively. Figure 10e,g shows the capacitor voltages of upper arm phase-a SM-1 and lower arm phase-a SM-1 with SPWMLSC modulation scheme. Figure 10f,h shows the capacitor voltages of the upper arm phase-a SM-1 and lower arm phase-a SM-1 with SPWMPSC modulation scheme. Figure 10i,j shows the transformer primary and secondary phase-a currents for both PWM techniques, respectively. Further, the converter's dynamic performance is analyzed when there is a step-change from time t = 1 s to t = 1.2 s in the current magnitude of I = 7.25 A to I = 17.5 A at 50 Hz \begin{table}
\begin{tabular}{c c} \hline \hline
**Number of Cells in Each Arm** & **3** \\ \hline Ac line inductor & 3 \(\mu\)H \\ \hline Carrier frequency & 1 KHz \\ \hline Transformer resistance & 74 m-ohm \\ \hline Transformer inductor & 3.48 mH \\ \hline Cell capacitance & 1000 \(\mu\)F \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Simulated converter parameters. Figure 10: Change in modulation index. (**a**) Line voltages of converter with d-q control and SPWMLSC, (**b**) line voltages of converter with d-q control and SPWMPSC, (**c**) Line currents of converter with d-q control and SPWMLSC, (**d**) line currents of converter with d-q control and SPWMPSC, (**e**) SPWMLSC implemented upper arm phase-a SM-1 capacitor voltage, (**f**) SPWMPC implemented upper arm phase-a SM-1 capacitor voltage, (**g**) SPWMLSC implemented lower arm phase-a SM-1 capacitor voltage, (**h**) SPWMPSC implemented lower arm phase-a SM-1 capacitor voltage, (**i**) primary and secondary phase-a transformer currents when SPWMLSC is implemented, (**j**) primary and secondary phase-a transformer currents when SPWMPSC is implemented, (**k**) SPWMLSC implemented line voltage THD, (**l**) SPWMLSC implemented line current THD, (**m**) SPWMPSC implemented line voltage THD, and (**n**) SPWMPSC implemented line current THD. frequency. It is observed from Figure 11a,k that the THD in line voltage of the converter with d-q control and STHILSC is 1.26% at 50 Hz, respectively, and from Figure 11b,m the THD in line voltage of the converter with d-q control and STHILSC is 1.18%. Similarly, the THD in line current with d-q control and STHILSC is 10.26% and with STHILSC is 8.84% at 50 Hz, as is shown in Figure 11c,l and Figure 11d,n respectively. Figure 11e,g shows the capacitor voltages of upper arm phase-a SM-1 and lower arm phase-a SM-1 with STHILSC modulation scheme. Figure 11f,h shows the capacitor voltages of upper arm phase-a SM-1 and lower arm phase-a SM-1 with STHILSC modulation scheme. Figure 11 ij shows the transformer primary and secondary phase-a currents for both STHILSC and STHIPSC PWM techniques, respectively. Now, the performance of the MMC is analyzed when it is operating in open and short circuit conditions.