## 2 Conventional DC Fault Modeling Methods of the Hybrid MMC  
This section categorizes existing methodologies for hybrid MMC equivalent modeling during DC fault transients into three distinct paradigms, while critically examining limitations of established analytical approaches in fault current characterization.  
Figure 1 depicts the configuration and submodule topologies of the hybrid MMC. The first methodology employs an RLC circuit representation for hybrid MMC equivalence during DC faults [21, 22], illustrated in Figure 2a. Conventional fault mitigation involves converter blocking [8, 21, 31], wherein de-energized FBSMs generate reverse electromotive forces to interrupt current flow. Post-blocking capacitor discharge paths for FBSMs and HBSMs, determined by fault current polarity, are depicted in Figure 2a. This yields the arm equivalent circuit with capacitance \(C_{0}/N_{FB}\), where \(C_{0}\) denotes SM capacitance, and \(N_{FB}\) signifies FBSM count per arm. Aggregating three phases derives the DC-side model (Figure 2a), incorporating DC inductance \(L_{dc}\) and resistance \(R_{dc}\) (encompassing current-limiting reactors). However, this blocked-converter paradigm fails to capture FRT control response.  
To characterize SM capacitor-DC fault current interdependencies under FRT control, [15] advances an enhanced modeling paradigm representing the MMC as an RL circuit serially coupled with a time-variant capacitor (Figure 2b). Theoretically, per-phase inserted SM counts range within [0, 2\(N\)]. The DC-side equivalent topologies corresponding to fully inserted/bypassed SM states are illustrated in Figure 2b. Given continuous SM capacitor switching dynamics governed by MMC control, an averaged circuit model is derived from these discrete states (Figure 2b), where duty cycle \(D\) quantifies temporal partitioning between operational modes during switching periods, effectively modeling SM capacitor discharge behavior. This framework enables FRT control impact analysis through parametric \(D\) variation. Nevertheless, \(D\) assignment remains arbitrary without the explicit characterization of control system-fault current relationships. Furthermore, per-phase aggregate capacitance exhibits temporal dependency during FRT transients. The inherent nonlinearities in control loops impede quantitative capacitor variation determination and analytical solution derivation for the circuit's differential equations.  
The third paradigm represents the hybrid MMC as an RL circuit coupled with an invariant voltage source [8; 23] (Figure 2c). Within this topology, parameter \(\beta\in\) [0,1] scales the rated DC voltage \(U_{dcn}\), with \(\beta\) magnitude contingent upon FBSM proportion per arm. This representation inherently presumes static \(\beta\) assignment to characterize maximum fault current limitation capability. Crucially, during FRT transients, nonlinear DC voltage attenuation governed by a controller induces time-variant \(\beta\) behavior. Furthermore, the functional relationship between \(\beta\) and control parameters remains obscured.  
In summary, extant methodologies have advanced hybrid MMC equivalent modeling frameworks for DC fault current analysis. Nevertheless, persistent theoretical gaps regarding quantitative correlations between fault current characteristics and control parameters necessit  
Figure 1: Configuration and submodule topologies of hybrid MMC [30]. (HBSM: half-bridge submodule; FBSM: full-bridge submodule).  
Figure 2: Conventional hybrid MMC equivalent circuit topologies under DC fault conditions: (**a**) RLC network representation. (**b**) RL series configuration with time-dependent capacitive element. (**c**) RL series path incorporating constant voltage source.