## 5 Experimental Results  
### Experimental Settings  
In order to verify the effectiveness of our proposed technique, data-centric screen methodology based on the combination of pattern-based and stress-based screen methodology, we have performed comprehensive evaluations using real 160 48-layer 3D TLC flash chips. (We also confirmed the effectiveness of our technique in 3D MLC flash chips and obtained similar evaluation results. Therefore, our technique can be extended to all types of 3D NAND flash memories, including advanced 3D QLC and xLC NAND flash memories.) To minimize the potential distortion of the evaluation results from process variations, we evenly selected 120 test blocks from each chip at different physical locations and tested a total of 11,520,000 pages (i.e., 3,840,000 WLs) in our evaluations. By using an in-house custom test board (equipped with a flash controller and a thermal controller), we performed various test scenarios and measured the reliability and performance of the test flash blocks. The test program was written in the programming language of Visual C++ on a Linux-based computing system. The test scenario comprised a mixture of NAND operations that have different patterns and modified internal operating conditions. Since flash memory vendors provide the low-level NAND flash memory interface function, we can access the current settings of internal NAND flash memory (including modifications of operating voltage) and check the current BER value of each WL after program operation (e.g., Set/Get-Features) [30]. In addition, the flash reliability was measured while varying the number of P/E cycles and the data retention time. A long-term lifetime test can be performed using an accelerated lifetime test. For example, to emulate a 12-month retention time condition, we baked the flash chips at 85 \({}^{\circ}\)C for 13 h, which is equivalent to 1 year at 30 \({}^{\circ}\)C by the Arrhenius's law [31].  
All our test procedures follow the JEDEC standard, which is the common industry practice for flash products. The industrial JEDEC standards [32,33] specify the test methodology (e.g., a sample size or test conditions) and qualification criteria for evaluating NAND flash memory. To ensure the confidence of reliability tests, these standards recommend that more than 39 flash chips from three different wafers should be tested. Since we have used a total of 160 flash chips from five wafers for evaluations, we believe that our sample size is sufficient to obtain statistically meaningful results. Figure 10 shows test equipment and the overall test procedure. Remember that due to erase-before program constraints explained in Section 2, an erase operation should always proceed a program operation.  
In this section, to validate our proposed technique, we focus on three criteria: The first is how to accurately distinguish a channel hole defect compared to a normal channel  
Figure 10: Schematics of test infra and the overall test procedure.  
hole (i.e., _detection accuracy_). The second is whether the reliability and performance of flash cells are degraded during the test procedures (i.e., _side effects_). The last is whether the time required for the test can be tolerable for mass production (i.e., _test time overhead_).