# Charge-Line Dual-FET High-Repetition-Rate Pulsed Laser Driver
## 2 Foundation of Charge-Line Pulsed Laser Driver
### Circuit Timing  
The circuit in Figure 2 requires synchronized clock sources responsible for the triggering of Q\({}_{1}\) and Q\({}_{2}\). There are common approaches that incorporate either an adjustable delay obtained with the use of either the Direct Digital Synthesis (DDS) circuit (Figure 3a) [10; 11; 12] or an analogue approach based on the ramp source and a programmable comparator (see Figure 3b) [10; 11; 12]. The analogue solution is relatively inexpensive; however, several drawbacks of an analogue delay line may decrease the functionality of the laser driver. The first drawback results from the temperature influence on the parameters of component parameters (i.e., capacitance, intrinsic propagation delays, and threshold voltages). Therefore, a thermal compensation of the circuit is necessary. The second drawback results from the noise processes affecting the relative position of the delayed clock slopes. On the contrary, the digital solutions based on the DDS ensuring sub-nanosecond resolutions are expensive or require high clock speeds. Modern Field-Programmable Gate Array (FPGA) devices offer advanced clocking resources like a Phase Locked Loop (PLL) or a Digital Clock Manager (DCM) [13]. They allow the obtaining of various frequencies, clock delays, and phase shifts within the FPGA device, with the use of just a single external clock source. In the proposed solution we have utilized a modern Xilinx Spartan 6 FPGA device (XC6 SLX16), in which the DCM is implemented as a programmable delay line depicted in Figure 4.  
Figure 2: Simplified schematic of charge line dual-Field Effect Transistors (FET) laser diode driver. The principle of operation of the device in Figure 4 is based on the phase loop, in which the phase detector alters the delay of the delay chain formed of delay blocks by the adjustment of the multiplexer (MUX). Therefore, the DCM offers both a relatively small jitter and a high resolution (low step). The single-cycle jitter measured with the Agilent 53,200 counter/timer for the XC6 SLX16 device used in the proposed laser driver did not exceed 20 ps, whereas the resolution (interval between subsequent steps) was \(\delta_{\mathrm{r}}=18\) ps. These parameters decide on the overall performance of the circuit proposed in Figure 2; however, further system measurements (see Section 4) show that they are sufficient for our driver's implementation. In order to ensure total independence from the external circuitry of our driver, we have to use the same circuit as the one in Figure 4.  
Figure 4: Block diagram of the Digital Clock Manager (DCM) delay block. Figure 3: Two popular methods for the generation of a variable delay: (**a**) With the use of DDS, and (**b**) voltage-time conversion. solution, we used a 100 MHz crystal clock connected to the global clock source (GCK) of the FPGA. The 100 MHz source was used as the input for the DCM device, which produces an adjustable delay within the 0-2 ns range at the CLK0 output (see Figure 5). This output acted as a timing of a simple digital subcircuit formed of two D flip-flops (DFFs) that was responsible for the repetition frequency limitation of our driver. The GCK and delayed CLK0 clock signals from the DCM were used as the timing sources at the clock inputs of the DFFs. The phase-shifted rising slope (edge) at the clock inputs together with constant positive supply at the data input (D) of the DFF enforce a delayed appearance of logical '1' at the DFF Q outputs. This way we are able to obtain a phase delay (8) of the rising edges at DFFs outputs (denoted as Q in Figure 5). On the other hand, the Chip Enable (CE) inputs of DFFs allowed us to periodically disable the signal at Q outputs of DFFs. The low logical level at CE inputs disables the laser pulse for a single GCK and CLK0 period, and, as a result, decreases the laser average pulse repetition rate. Therefore, the driver is able to decrease (control) the number of pulses available at Trg1 and Trg2 outputs, which activate the switching transistors (and the laser).