## 3 Performance-Wise Comparison with Existing Topologies
For calculation purposes, the connected load is assumed resistive. It can be observed that the peak breakover voltage of the switching devices in the proposed topology is 160 V while in [24], it is 320 V that is almost double. In the same way, the chopping or switching voltage in [24] is also double. The conversion losses in the suggested architecture only come from the conduction and switching losses while in [24], along with these losses, core losses contribute much of the conversion losses. In one PWM switching interval, there is a conduction of two transistors and two diodes, so conduction and switching losses of the proposed topology are computed as  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]0  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]1  
Similarly, for the architecture in [24], there is the conduction of only one transistor and diode, so their switching and conduction losses are calculated as,  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]2  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]3  
The switching losses of both architectures are the same although there is a switching of one transistor in [24] instead of two as in the suggested topology. This is due to the double chopping voltage. But the conduction losses of the power converting architecture in [24] is almost half if equal internal voltage and resistance of the switching devices are considered. But practically, these values increase with an increase in the maximum breakover and chopping voltage. It has already been pointed out that the cost and conversion losses of the suggested architecture are low due to the absence of a low-frequency transformer. As far as the power quality is concerned, the input current in the suggested architecture is non-distorted; its power factor is high and the harmonic factor is low. But the power converting architecture reported in [24] has two secondary windings and each secondary winding is connected in series with the diode, transistor, and load. Hence it behaves as a half-wave rectifier circuit. With these characteristics, the input current of each secondary of the transformer is distorted and contains unwanted harmonics including dc component-one of the major power quality issues. This component not only contributes to the power losses but also leads to the undesirable core saturation issue. With Fourier theory, the input dc, RMS, RMS current at the required frequency and its displacement angle is computed as  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]4  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]5  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]6  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]7  
Here \(I_{m}\) is the peak value of the output or input current. It can be noted here that the dc component in the input current is compared to the total input RMS current. The numerical value of the dc component is also greater than the RMS value of the required current component. So, this component increases the core saturation potency with heavy-duty loads. With these values, the power and harmonic factor of each secondary is calculated as  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]8  
\[V_{br(proposed)}\ =\ V_{m} \tag{16}\]9The comparison of the suggested converter and power converting topology in [24] in terms of performance indices with resistive load is also explored in \[V_{br([24])}\ =\ V_{m}\ =\ 2V_{br(proposed)} \tag{17}\]0  
In summary, there is no problem with core saturation and core losses as the developed topology needs not to employ the input transformer. The intermediate inductor ensures the elimination of the shoot-through issue. The current interruption problem of the inductor is tackled by establishing two current loops in each operating mode. The developed topology may be attractive to produce multiple types of output with simplified switching schemes. Along with this, the maximum breakover and switching voltage and harmonic factor are low and the power factor is improved. These attractive features increase its workability over the converter in [24].