# 0.5-V High-Order Universal Filter for Bio-Signal Processing Applications
## 2 Proposed Circuit  
### Mi-Ota  
The circuit symbol of the MI-OTA is shown in Figure 2. The OTA has two inverting and two non-inverting inputs. In an ideal case, its voltage-to-current transfer characteristic is described by the following equation:  
\[I_{o}=g_{m}(V_{+1}+V_{+2}-V_{-1}-V_{-2}) \tag{1}\]  
Here, \(I_{o}\) represents the output current \(V_{+1}\), \(V_{+2}\) are the non-inverting input voltages \(V_{-1}\), \(V_{-2}\) are the inverting input voltages, and \(g_{m}\) denotes the transconductance gain. Thus, the output current \(I_{o}\) is proportional to the difference of two sums of signals applied to the non-inverting and inverting inputs, respectively, where \(g_{m}\) is the circuit transconductance. The simple CMOS realization of the MI-OTA proposed in this work is shown in Figure 3. The circuit is composed of two BD non-symmetrical differential pairs (M\({}_{1}\)-M\({}_{2}\) and M\({}_{3}\)-M\({}_{4}\)), biased by the current sources M\({}_{5}\) and M\({}_{6}\) and loaded by the current mirror M\({}_{7}\)-M\({}_{8}\), composed of self-cascode (SC) transistors for larger output resistance and DC voltage gain. The non-symmetrical differential pairs allow increasing the linear range of the OTA. The linearization principle was adopted from [41], where a bipolar and generalized (multiple-pair) version of this circuit was described. In [42], a GD CMOS version of the circuit was presented. Using the formula provided in [42] and replacing the input differential voltage at the gates by the input differential voltage at the bulks, the DC transfer characteristic of OTA, operating in weak inversion, can be expressed as:  
\[I_{o}=\frac{I_{D5,6}}{2}tanh\left(\eta\frac{V_{BD}}{2n_{p}U_{T}}+\frac{lnm}{2} \right)+\frac{I_{D5,6}}{2}tanh\left(\eta\frac{V_{BD}}{2n_{p}U_{T}}-\frac{lnm} {2}\right) \tag{2}\]  
where \(V_{BD}\) is the differential voltage between bulk terminals of M\({}_{1}\) and M\({}_{3}\), \(n_{p}\) is the subthreshold slope factor for a p-channel MOS, \(\eta~{}=\left(n_{p}-1\right)=g_{mb}/g_{m}\) is the bulk-to-gate transconductance ratio at the operating point, \(U_{T}\) is the thermal potential and \(m=(\mathrm{W}/\mathrm{L})_{1}/(\mathrm{W}/\mathrm{L})_{2}=(\mathrm{W}/ \mathrm{L})_{3}/(\mathrm{W}/\mathrm{L})_{4}\) is the ratio of aspect ratios of M\({}_{1}\) and M\({}_{2}\) (M\({}_{3}\) and M\({}_{4}\)). The linear range of OTA depends on coefficient m. By equaling the second derivative of (2) to zero, the optimal linearity is achieved for \(m=2+\sqrt{3}\) or \(m=1/\left(2+\sqrt{3}\right)\). This result is independent of the biasing currents \(n_{p}\) and \(U_{T}\). In the optimal case, the linear range of this transconductor, determined for 1% variation \(g_{m}\), is nearly four times larger than the one for the classic BD differential pair operating in weak inversion. Figure 2: Symbol of MI-OTA. In the proposed MI structure, a BD-MI technique, which was first experimentally verified in [43; 44], has been applied to increase the number of its inputs. The BD transistors M\({}_{1}\) and M\({}_{3}\) have been replaced by BD-MI composite transistors. Their symbol and circuit implementation are shown in Figures 4a and 4b, respectively. The M\({}_{\text{s}}\) were realized using a capacitive divider/voltage summing circuit composed of capacitors \(C_{Bi}\). In order to properly bias the bulk terminals of M\({}_{1}\)-M\({}_{4}\) for DC, the capacitors are shunted by large resistances \(R_{MOSi}\), realized as an anti-parallel connection of MOS transistors operating in the cut-off region with \(V_{GS}=0\), as shown in Figure 4c. This approach allows avoiding the use of additional transistors (input stages); namely, it simplifies the structure and allows saving power. Moreover, the voltage attenuation introduced by the input capacitive divider further expands the linear range of the OTA.