Modeling and Fabrication of a Reconfigurable RF Output Stage for Nanosatellite Communication Subsystems  
[PERSON]  
1 Engineering and Applied Technology, Autonomous University of Zacetecas, Zacetecas 98000, Mexico; [EMAIL_ADDRESS] (J.A.C. ); [EMAIL_ADDRESS] (V.I.R.-A.) 2 Mechanical and Electrical Engineering Faculty, Universidad de Colima, Colima 28040, Mexico; [PERSON]DDRESS] (C.R.-A.) 3 Catedras CONACYT, Autonomous University of Zacetecas, Zacetecas 98000, Mexico; [EMAIL_ADDRESS] (C.R.-A.) 4 CINVESTAV-IPN, CINVESTAV Guadalajara, Jalisco 45019, Mexico; [EMAIL_ADDRESS] (C.R.-A. ); [EMAIL_ADDRESS] (V.I.R.-A. ); [EMAIL_ADDRESS] (V.I.R.-A. ); [EMAIL_ADDRESS] (V.I.R.-A.) [PERSON]  
1 Engineering and Applied Technology, Autonomous University of Zacetecas, Zacetecas 98000, Mexico; [EMAIL_ADDRESS] (J.A.C. ); [EMAIL_ADDRESS] (V.I.R.-A.) 2 Mechanical and Electrical Engineering Faculty, Universidad de Colima, Colima 28040, Mexico; [PERSON]DDRESS] (C.R.-A.) 3 Catedras CONACYT, Autonomous University of Zacetecas, Zacetecas 98000, Mexico; [EMAIL_ADDRESS] (C.R.-A.) 4 CINVESTAV-IPN, CINVESTAV Guadalajara, Jalisco 45019, Mexico; [EMAIL_ADDRESS] (C.R.-A.) This challenging implementation interconnects several external subsystems that use an SoC for improving performance, costs, and volume. In [4], an SDR architecture is proposed. In that work, to solve the reconfiguration challenges of the transmitter and the receiver, the SoC device is combined with a programmable radio frequency (RF) transceiver from Analog Devices(r). It involves using and implementing COTS such as the FMCOMMS3 (the AD9361 IC for the RF stage) and a ZYNQ 7020 from Xilinx(r), among other devices. [PERSON] et al. in [5] designed and implemented an AD9361-based platform for software radio exclusively for the receiver stage and a ZC706 applied to the digital baseband processing module of SoC. A COST-based SDR architecture applied to the ground segment is presented in [6]. It develops the Digital Down Converter (DDC) stage using the hardware descriptive language VHDL and other baseband processes such as channel coding and data interleaving. The disadvantage of that proposal is that the IP-Cores involved are Xilinx(r) intellectual property and the transmission rates achieved are relatively low: 1.2 to 19.2 Kbps. The authors in [7] concluded that hardware reuse is a novel approach in implementing SDR systems to better the performance of communications schemes. In [8], for both the reception and transmission stages, a design of an RF front-end for a nanosatellite is presented, using low-cost commercial components such as the CC2510 IC. However, this IC works in a narrow bandwidth of 2.400 to 2.483 GHz. In [9], the stage of the baseband processor (BBP) of the communication system was implemented on a Zynq 7020. Nevertheless, the RF stage was just simulated. In [10], for scenarios of next-generation communications satellites, an FPGA application is described to implement an onboard processor and couple it through reconfiguration. As pointed out in the literature, several satellite communication subsystem proposals are based on digital implementations using SDR systems and others are offered as COTS components. Regardless, the RF Analog Back-End remains partially unexplored and represents a research opportunity. Finally, it should be mentioned that there are companies in the market that offer satellite communications subsystems based on SDR, such as the one commercialized by [11], which can be reconfigured to use different frequency bands such as L, S, or K. Nevertheless, it has the drawbacks of both being expensive and proprietary architecture. This work describes the modeling, implementation, and testing of a low-cost reconfigurable satellite communications subsystem prototype called the Reconfigurable Analog Back-End (RABE). This development is intended to be placed in the space segment, complying with the CubeSat standard for future applications. The proposed RABE consists of two stages.