# A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
## 2 Operation Principle of the Proposed DTC  
### Principle of Vernier DTC  
The Vernier principle has been widely used for time-to-digital converter design in previous researches [13]. It is firstly introduced to FPGA-DTC in [11]. The typical timing diagram of Vernier FPGA-DTC is shown in Figure 1. \(\mathrm{S_{F}}\) and \(\mathrm{S_{S}}\) represent two periodic signals, with frequencies quite close to each other. Fast counter (CNTF) and slow counter (CNTS) are the down counters clocked by \(\mathrm{S_{F}}\) and \(\mathrm{S_{S}}\). After the coincidence of the rising edge between \(\mathrm{S_{F}}\) and \(\mathrm{S_{S}}\), the counters CNTF and CNTS start to count \(\alpha\) and \(\beta\) cycles, respectively. \(\alpha\) and \(\beta\) are the fine and coarse counting values of Vernier DTC. The generated time width between START and STOP signals can be expressed as:  
\[\mathrm{T_{x}}=\alpha(T_{S}-T_{F})+\beta T_{S}=\alpha\Delta T+\beta T_{S} \tag{1}\]  
The resolution of Vernier DTC is determined by the period difference between \(\mathrm{S_{F}}\) and \(\mathrm{S_{S}}\). Therefore, the frequency resolution of PLLs on FPGAs limited the performance of Vernier FPGA-DTC. For instance, \(\mathrm{8T_{S}}\) = \(\mathrm{9T_{F}}\), thus the resolution of this DTC is (1/9)\(\mathrm{T_{S}}\), as shown in Figure 1. Now we suppose that we can get three signals which have approximate periodical signals, \(\mathrm{S_{F}}\) (fast), \(\mathrm{S_{M}}\) (medium) and \(\mathrm{S_{S}}\) (slow). The relationship of their period is \(\mathrm{8T_{S}}\) = \(\mathrm{9T_{M}}\) = \(\mathrm{10T_{F}}\), as shown in Figure 2. The time difference \(\Delta\mathrm{T1}\), \(\Delta\mathrm{T2}\) and \(\Delta\mathrm{T}\) are defined as:  
\[\Delta T_{1}=T_{M}-T_{F} \tag{2}\]  
\[\Delta T_{2}=T_{S}-T_{M} \tag{3}\]  
Figure 1: Timing diagram of Vernier digital-to-time converter (DTC).  
For a common case, \((n-1)T_{S}=nT_{M}=(n+1)T_{F}\), where \(n\) is a positive integer. In this case, the resolution of DTC is \(2T_{S}/(n(n+1))\). It is much higher than two delay lines Vernier DTC with the same \(n\) (\(n>>2\)). The detailed timing diagram of 3D Vernier DTC is shown in Figure 2. The down counter CNTM starts to count \(2\alpha+\beta\) cycles after the phase coincidence (Phase Coincidence 1) of \(\mathrm{S_{F}}\) and \(\mathrm{S_{M}}\). The phase of slow clock \(\mathrm{S_{S}}\) coherent with \(\mathrm{S_{F}}\) after \(\alpha T_{F}\) (Phase Coincidence 2). At this moment, the counter CNTs starts to count \(\alpha+\beta+\gamma\) cycles. The output time width becomes:  
\[\mathrm{T_{x}}=\alpha(\Delta T_{2}-\Delta T_{1})+\beta\Delta T_{2}+\gamma T_{S }=\alpha\Delta T+\beta\Delta T_{2}+\gamma T_{S}=\alpha\frac{2}{n(n+1)}T_{S}+ \beta\frac{1}{n}T_{S}+\gamma T_{S} \tag{5}\]  
For the DTC output continuously varying in step size \(\Delta\)T, \(\Delta\)T\({}_{2}\) should be integer multiples of \(\Delta\)T. It means that (n + 1)/2 should be a positive integer. In other words, \(n\) should be an odd positive integer number. To generate a given time width \(\mathrm{X\Delta T}\) which is equal to \(\alpha\Delta T+\beta\Delta T_{2}+\gamma T_{S}\), we have:  
\[\gamma=\left\lfloor\frac{2X}{n(n+1)}\right\rfloor,\beta=\left\lfloor\frac{X- \gamma\frac{n(n+1)}{2}}{n}\right\rfloor,\ \alpha=X-\ \gamma\frac{n(n+1)}{2}-\beta n \tag{6}\]  
where \(\lfloor x\rfloor\) denotes the largest integer number less than or equal to \(x\). Usually, the odd integer number \(n\) is designated as several decades to get a much higher resolution. The generation time from changing input value to STOP enable can be expressed as:  
\[T_{G}=\alpha T_{M}+\ (\alpha+\beta+\gamma)T_{S} \tag{7}\]