# A Software-Defined Radio for Future Wireless Communication Systems at 60 GHz
## 2 5G Testbed Overview
### FMC126/FMC230 Data Interface  
It is well known that operating FPGA logic at GHz clock frequencies is impractical, since very low rising interval times result into failing design timing requirements and data integrity is not ensured. Looking at current solutions, the FPGA clock performance barrier is around the 500 MHz. Hence, 4 DSP adopted a parallel data path architecture in both original FMC230/FMC126 firmwares, which reduces significantly the required data clock frequencies to MHz. For example, from the FMC230 functional block diagram (see Figure 7), two parallel data DDR interface paths come from the FMC connector (\(DAC0\_p0\_p/DAC0\_p0\_n\) and \(DAC0\_p1\_p/DAC0\_p1\_n\)--operating at \(fDACCLK/4\)),  
Figure 6: Illustration of the I2C communication towards VC707’s FMC1 and FMC2. and are then multiplexed into a single data stream by the assembler entity, which is clocked at \(fDACCLK/2\), where \(fDACCLK/\) represents the DAC sampling rate value (\(F_{\mathrm{s}}\)). A detailed block diagram of the FPGA data connectivity with DAC's firmware is depicted in Figure 8. In the figure, it is verified that data source is generated in the \(Ad9129\_wfm\_inst0\) entity, driven by the \(wfm\_out\_data\) bus signal (16 words of 16 bits each) clocked at \(txclkdiv8\). Such clock value is equal to \(DAC0\_dco\) value divided by 4 or DAC \(\frac{F_{\mathrm{b}}}{16}\). Since AD9129 bit resolution is 14 bits, the two most significant bits are then discard in the \(Ad9129\_io\_buf\_v7\_inst0\) entity. In this entity, the 256 data bit bus (\(Odata\_reg\)) is serialised, using two sets of fourteen parallel to serial structures of Oserdeses2 (high-speed source-synchronous output fabric interfaces) operating in DDR mode. This results in two buses of 14 bits (\(DAC0\_p0\_p/DAC0\_p0\) and \(DAC0\_p1\_p/DAC0\_p1\)), clocked at \(txclkdiv2\) clock, which are then connected to the FMC230 board through the FMC1 pin-out connection (see Figure 7). Figure 7: Detailed FMC230 functional block diagram. The data interface of the FMC126 with FPGA is rather similar to the FMC230 ones, but here eight parallel data paths are considered instead. That is, data go to the FMC230 on a 256 bit bus, whereas data come from the FMC126 on a 128 bit bus. This leads to a mismatch of the clock value in both DAC and ADC firmware channel paths. For example, considering a target sampling rate of 1.25 GHz, buses are clocked at 78.125 MHz and at 156.25 MHz for FMC230 and FMC126, respectively. To overcome this issue, the number of data paths in the FMC230 firmware were reduced to 8 (matching the ones from the FM126), and thus entities, namely, \(ad9129\_mmcm\_isnt\), \(ad9129\_phy0\_dac0\_inst0\), and \(ad9129\_io\_buf\_v7\_isnt0\), have been updated accordingly, where \(txcldiv8\) value is now given by \(\frac{F_{k}}{8}=Dac\_aci/2\). The proposed communication transceiver prototype is based on the digital IF architecture shown in Figure 9. Such architecture offers more flexibility when compared to traditional RF architectures, and is not sensitive to DC offset, LO leakage and flicker noise. Moreover, since I/Q up-conversion/down-conversion is digitally performed in an IF stage, negative effects induced by IQ imbalances, critical in advanced modulation techniques, are therefore limited. Note that both Digital Up-Conversion (DUC) and Digital Down-Conversion (DDC) stages are performed to relatively low  
Figure 8: Block diagram of the data interface between the FPGA and FMC230 for the DAC0. center IF frequencies (limited by the sampling rate of both DAC/ADC); however, up-conversions to mmWave can be accomplished by an external analog mixer, as discussed in Section 2.6. As previously stated, the testbed data source is modulated with a real-time OFDM Transceiver (TRX) engine, which was developed in _Xilinx_ System Generator (SysGen) environment. SysGen is the state-of-the-art tool for the design, testing, and implementation of high-performance DSP algorithms on FPGAs.