# Real-Time Method and Implementation of Head-Wave Extraction for Ultrasonic Imaging While Drilling
## 3 Hardware Design
### Overall Design  
The hardware principle of the echo head-wave real-time extraction is shown in the dotted line box in Figure 2. In this approach, FPGA is used as the processor of the echo digital signal processing. The remaining modules are used for pre-processing the echo signal reception and provide a high-SNR signal for FPGA to carry out the subsequent digital signal processing work.  
As the main controller of real-time head-wave extraction, FPGA realizes the following functions: (1) it extracts the head waves of the echo signal, (2) it sends the gain control command to the front-end control module in response to the amplitude information of the head wave, (3) it controls the AD conversion module to convert the echo analog signal into a digital one, which is then entered into the FPGA, and (4) it communicates with other transmission and storage units, such as DSP and Flash.  
The amplitude limitation protection module has two Zener diodes in a series that form a bidirectional limiting circuit. This module uses high-power resistors to limit the current and avoid the impact of transmitting high-voltage pulses on the receiver circuit. The programmable gain amplification module amplifies the echo signal to a reasonable range to anticipate potentially notable variations in the echo amplitude waveform recording  
Figure 1: Effect comparison between the STA/LTA and improved STA/LTA methods.  
Figure 2: Diagram of the principal hardware used for head-wave real-time extraction.  
due to different downhole conditions. The programmable gain control is then completed by the front-end control module, which uses CPLD as its controller. The gain of the programmable amplifier circuit is adjusted by the front-end control module based on the main control command from FPGA. A Butterworth filter was selected as the band-pass filter module, and a Sallen-key structure was used as the design unit, whose aim was to reduce the low-frequency environmental noise caused by drill collars and the high-frequency electromagnetic interference in the electronic circuit, respectively. The AD conversion module converts the filtered echo analog signal into a digital signal under the control of FPGA, which is then fed into the FPGA for the extraction of the head wave.  
Figure 3 shows the design scheme of the analog band-pass filter circuit. In the actual circuit, in order to achieve the optimal filtering effect, three second-order filters are interactively cascaded with the amplifier circuit as independent design units, and the cascaded mode is resistance-capacitance coupling.  
The resonant frequency of the transducer used in the ultrasonic imaging logging tool is 250 kHz, and the signal sampling frequency is 2.5 MHz. Consequently, the band-pass filtering circuit is designed with a center frequency of 250 kHz, and the band-pass spans from 180 kHz to 320 kHz, with a bandwidth of 140 kHz. After the band-pass frequency is determined, the R (resistance) and C (capacitance) parameters in the filter circuit are calculated. The calculation results of the parameters are shown in Figure 4.