## 1 Introduction  
Transistors are the miniature of devices of automatic control that allow or disallow current to flow and convey signals or power. Power-discrete transistors concern a high breakdown voltage and a high current. Transistors that are responsible for signal communications continuously shrink for the requirement of faster speed. Unfortunately, continuous channel length shrinkage causes short channel effects. Short channel effects result in unwanted noticeable leakage current, which is successfully suppressed through a halo implant or a pocket implant on, e.g., planar MOSFET with a 0.18 \(\mathrm{\SIUnitSymbolMicro m}\) or 90 nm long channel, in which the gate caps on the top of the channel. Unfortunately, the implant process fails to effectively stop leakage current at, e.g., 20 nm. Instead, FinFET sustains the capability of suppression of outrageously leaky current by using a Gate over 90% surrounding the 3-D slim channel for down to 3 nm process technique. GAAFET replaces the role of FinFET using the Gate completely surrounding the whole channel for 2 nm process technique. For one thing, the suppression of leakage current is due to creating a depletion region in thin epi-taxial silicon which blocks the leakage current by building up a hill high potential barrier. However, the trend of shorter channels promotes the speed of transmitting signals via carriers and makes artificial intelligence (AI) possible, where the non-linear problem-sorting deep neural network (DNN), image-sorting convolution neural network (CNN), and speech-recognizing recurrent neural network (RNN) become available [1; 2; 3; 4; 5; 6]. Epi-silicon is tremendously important for its nearly identically flawless pure silicon that allows no enhancement of leakage current. Thicker epi-silicon films, such as tens of \(\upmu\)m or a hundred \(\upmu\)m, even play roles of power discrete with high sustainable voltage bias. Thinner epi-silicon, such as 10 \(\upmu\)m, is expected on an integrated circuit (IC) though. Looking like an emerging 3-D \"I\" with two ends of source and drain, FinFET uses Gate poly-silicon crossing over the channel to conduct current between the source and the drain by applying a bias to the Gate. Simultaneously, the Gate bias depletes the whole slim channel and builds up a barrier that blocks the leakage current. The achievable function of the process is mostly due to the good conformality (step coverage) of chemical vapor deposition, in which SiH\({}_{4}\) (silane) is controlled at a chosen flow rate and the ambient is sustained at an appropriate temperature and at certain pressure to achieve a good deposition rate in the kinetic regime [7; 8; 9; 10; 11; 12; 13; 14; 15]. Somehow, the electrical performances of transistors are mainly manifested in current-versus-voltage characteristic curves. Those curves are necessarily parameter-extracted in the model, which is useful to develop the circuit design. Therefore, the as measured I-V curves are thought to be well fitted to determine predominant parameters. An advisable algorithm using the \"modified\" conventional I-V characteristic curve formula along with kink effects generates fitting data to minimize the deviations from the measured ones. The as-determined parameters are promising, such as the threshold voltage (Vth), lambda (\(\lambda\)), and k\({}_{\text{N}}\), which is mainly proportional to the mobility. In this study, the fabrication of FinFET is roughly described and devices are randomly selected on the wafer level and measured as mentioned in Section 2.1. In Section 2.2, the two-regime modified formulas are proposed to fit current-voltage characteristic curves following the procedures or specific algorithm in Section 2.3. Results, including the determined parameters and fitting graphs mainly on I\({}_{\text{DS}}\)-V\({}_{\text{DS}}\) at various V\({}_{\text{GS}}\), are presented in Section 3, since I\({}_{\text{DS}}\)-V\({}_{\text{GS}}\) at various V\({}_{\text{DS}}\) share the same formula. The results are analyzed and discussed in Section 4.