# A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow
## 7 Simulations of the Proposed Standard-Cell-Based ULV OTA
#### Simulations in the Different PVT Conditions  
The main performance parameters of the proposed ULV standard-cell-based OTA have been simulated in the different process corners, and results are summarized in Table 2. The total harmonic distorsion (THD) has been evaluated by using transient simulations  
Figure 11: Transient response to a rail-to-rail input pulse in unity–gain configuration: output voltage in blue and input voltage in orange. Figure 10: Frequency response of the proposed OTA: open-loop differential gain in blue, open-loop common mode gain in green, and closed-loop gain in unity–gain configuration in orange. and exploiting the \"THD\" function in the Cadence Virtuoso environment for a sinusoidal input with a frequency of 100 Hz and an amplitude of 240 mV (i.e., 80% of the rail-to-rail input swing). As it can be observed, both the differential and the common mode gains, as well as the offset and the phase margin, are stable with respect to the different corners. The worst case common mode gain degradation is in the cross corner FS and is probably due to variations in the dc operating points not completely compensated by the replica-bias loop in the FS corner. Since bias currents are not accurately set (current sources are not available in a standard-cell flow), the power consumption varies in accordance with threshold voltage variations of PMOS and NMOS devices of the inverter, resulting in not very stable GBW, SR, and power dissipation \(P_{D}\), which all are strongly dependent on the bias current of the inverters. The OTA has also been tested under voltage and temperature variations, and results are reported in Table 3. Similar considerations as for Table 2 can be made in this case as well. Indeed, PVT variations have an impact on the \(GBW\), the \(P_{D}\), and the \(SR_{p,m}\). At this point, we want to remark that one intrinsic limit of the standard-cell approach is that, as discussed in the literature [33, 52], it does not allow us to accurately set dc currents without additional custom circuitry (see [59]) operating at a higher supply voltage. Thus, performance parameters that depend on the bias current vary in accordance with threshold voltage variations over PVT fluctuations. However, we want to remark that, despite variations with respect to nominal conditions, the proposed OTA can work over all PVT corners, guaranteeing a gain always greater than 48 dB, a reasonable offset voltage, and also a good phase margin. These results confirm the limits of standard-cell-based OTAs [33, 51, 52] which, even if allowed to aggressively scale the supply voltage [34, 64, 65], to strongly reduce the silicon area footprint, and to allow an automatic layout flow (thus shortening the time-to-market), end up somewhat sensitive to PVT variations, especially if compared with ULV full-custom-designed amplifiers [10, 11] which, on the other hand, exhibit a larger area, longer design \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Parameter** & **TT** & **FF** & **SS** & **FS** & **SF** \\ \hline \(A_{V_{0}}\) [dB] & 50.33 & 46.38 & 53.72 & 50.58 & 49.4 \\ \(A_{V_{c}}\) [dB] & 7.45 & 8.27 & 8.36 & 25.51 & 13.11 \\ \(GBW\) [MHz] & 10.4 & 16.45 & 6.84 & 10.65 & 9.73 \\ \(m\varphi\) [deg] & 56.33 & 63.6 & 49.46 & 56.38 & 59.39 \\ \(P_{D}\) [\(\mu\)W] & 12.09 & 26.21 & 6.23 & 13.44 & 12.41 \\ \(Offset\) [mV] & \(-\)2.2 & \(-\)3.7 & \(-\)1.93 & \(-\)10.72 & 6.32 \\ \(SR_{p}\) [\(V\)/ms] & 631.4 & 1.044 k & 396.5 & 425.6 & 863.7 \\ \(SR_{m}\) [\(V\)/ms] & 811.3 & 1.407 k & 504.2 & 1.008 k & 569.6 \\ \(THD\) [\%] & 0.24 & 0.28 & 0.26 & 0.99 & 0.95 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Performance of the proposed OTA in the different process corners.