# Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor
## 6 Conclusions and Future Work  
We have proposed a new decimal adder/subtractor and two new partial product generators for parallel decimal fixed-point multiplication on 6-input LUT FPGAs. The result was two decimal multipliers with different tradeoffs between area and performance. The partial product generators are based on different sets of multiples, namely {2A, 5A, 10A} and {2A, 4A, 5A}. The first set of multiples is easier to generate but the partial product generator occupies more area than that using the second set of multiples. The inputs and output of the multipliers can be represented in BCD or BCD/excess6 formats. The results were compared with the best state-of-art implementations of a parallel decimal multiplier in FPGA. One of the proposed multipliers achieves the best area and delay for all operand sizes, except the smallest one, \(2\times 2\), when compared to the state of-art. The second multiplier further improves the area but at the cost of an increase in \begin{table}
\begin{tabular}{c c c c c c c c c c c c} \hline \hline  & [41] * & [43] * & [42] * & [44] & & & **Multiplier 1** & **Multiplier 2** \\ \hline
**Size** & **LUTs** & **Delay** & **LUTs** & **Delay** & **LUTs** & **Delay** & **LUTs** & **Delay** & **LUTs** & **Delay** \\ \hline \(2\times 2\) & 82 & 4.2 & — & — & — & — & 91 & 4.2 & 88 & 3.56 & 87 & 4.62 \\ \(4\times 4\) & 300 & 5.3 & 450 & 5.6 & 365 & 5.6 & 301 & 5.4 & 280 & 4.97 & 255 & 5.92 \\ \(8\times 8\) & 1128 & 6.9 & 1850 & 8.1 & 1197 & 7.5 & 1065 & 7.0 & 960 & 6.58 & 839 & 7.96 \\ \(16\times 16\) & 4336 & 9.5 & 6843 & 11.9 & 4088 & 11.5 & 3954 & 8.9 & 3504 & 8.53 & 3001 & 10.22 \\ \(32\times 32\) & 16,928 & 13.4 & — & — & 13,257 & 18.1 & 15,146 & 14.0 & 13,248 & 12.26 & 11,194 & 13.12 \\ \(34\times 34\) & 19,197 & 14.2 & — & — & — & — & 17,135 & 14.9 & 14,976 & 13.04 & 12,643 & 13.91 \\ \hline \hline \end{tabular}  
* remapped to Virtex-7 speed grade -3 technology for a fair comparison.  
\end{table} 
Table 13: Comparison of the proposed decimal multipliers with state of the art works for different number of digits. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline  & **Multiplier 2** & & **Binary** & & **Comparison** \\ \hline
**Size (Digits)** & **LUTs** & **Delay (ns)** & **Size (bits)** & **LUTs** & **Delay (ns)** & **Area Ratio** & **Delay Ratio** \\ \hline \(2\times 2\) & 87 & 4.62 & 7 & 46 & 2.59 & 1.89 & 1.78 \\ \(4\times 4\) & 255 & 5.92 & 14 & 190 & 3.62 & 1.34 & 1.63 \\ \(8\times 8\) & 839 & 7.96 & 27 & 720 & 5.11 & 1.16 & 1.56 \\ \(16\times 16\) & 3001 & 10.22 & 54 & 2899 & 6.88 & 1.04 & 1.49 \\ \(32\times 32\) & 11,194 & 13.12 & 13.1 & 11,866 & 9.84 & 0.94 & 1.33 \\ \hline \hline \end{tabular}  
* Small decimal multipliers are relatively expensive compared to the binary multiplier, but the proposed \(16\times 16\) decimal multiplier 2 has an area only 4% higher than the area of the binary multiplier and the proposed \(32\times 32\) decimal multiplier 2 is smaller than the binary multiplier. The area ratio reduction has to do with the overhead associated with the generation of the multiples which are amortized as the multiplier size increases. The delay of the decimal multiplier is always worse but the relative difference also decreases with the operand size for the same reasons.  
\end{table} 
Table 14: Comparison of the proposed decimal multipliers with state of the art works for different number of digits. delay. Compared to a binary multiplier, the larger multipliers have a comparable area, but the worst delay. Both area and delay ratios decresse with the operand size. As future work, the proposed multiplier will be used to implement decimal floating-point multiplication and fused multiplication-addition. Conceptualization, M.P.V. and H.C.N. ; methodology, M.P.V. and H.C.N. ; software, M.P.V. and H.C.N. ; validation, M.P.V. and H.C.N. ; formal analysis, M.P.V. and H.C.N. ; investigation, M.P.V. and H.C.N. ; resources, M.P.V. and H.C.N. ; data curation, M.P.V. and H.C.N. ; writing--original draft preparation, M.P.V. and H.C.N.