# Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity
## 2 Related Work
### 3D Network-on-Chip  
The evolution of SoC design to the third dimension offers many opportunities, such as the integration of inhomogeneous cores, which results in several challenges, including optimal inhomogeneous NoC topologies, router architectures and application mapping techniques [27]. A 3D router has a larger area and power consumption than a 2D router with similar architectures [28]. Particularly, the seven-port symmetric router has an area and power overhead of 36% and 158%, respectively, compared to a conventional five-port router [29]. [PERSON] et al. [30] proposed to replace the large seven-port symmetric 3D routers with the six-port NoC-Bus hybrid 3D routers. However, the hybrid router requires an additional central arbiter per each vertical pillar in the NoC. Moreover, the hybrid router still has a large crossbar and energy consumption. [PERSON] et al. [31] have demonstrated that the area overhead of TSVincreases with the increase in the number of 3D layers. Particularly, the area overhead of the TSV for a four-layer 3D NoC with five million gates can reach as high as 10%. Similarly, [PERSON] et al. [1] presented a study of the area, power and performance trade-off of combining 2D and 3D routers in 3D mesh and torus topologies. [PERSON] et al. [32] performed an evaluation of the impact of reducing the number of TSVs to half and a quarter on the performance of 3D NoCs. Their proposed architectures, quarter/load half/lo (quarter/hand half/hi), aim at generating inhomogeneous 3D NoC with 2D routers placed as close to (far from) 3D routers as possible in each layer. [PERSON] et al. [33] used partition islands of routers to constitute regions for sharing the same TSV pad for inter-layer communication controlled by serialization logic. However, serialization along the TSV bundle causes the average packet delay to increase exponentially as the number of routers per TSV bundle increases. Moreover, the TSV pads have no direct connection to the processing cores, which is a waste of chip area compared to our proposed architectures. Furthermore, the genetic algorithm and simulated annealing employed in [34] for the selection and placement of different TSV patterns (sharing regions) in 3D NoCs have an exponential complexity with a large design exploration space. Similarly, [PERSON] [35] proposed a serialization technique for reducing the number of TSVs where the link size of TSVs at selected nodes is reduced by a fraction. Thus, if the number of TSVs exceeds a threshold, serialization is adopted to reduce the bandwidth of some TSVs. However, due to the reduced bandwidth of the  
Figure 2: Dimension-sliced router with single-cycle switch traversal (ST) + link traversal (LT) capability. TSVs and serialization logic, such architectures have high average packet latencies. Moreover, due to the higher overhead of the serialization receiver and transmitter logic compared to the TSV reduction, such architectures have even higher power consumption compared to the homogeneous 3D mesh. Based on the serialization methodology, [PERSON] (2016) proposed a 3D NoC synthesis framework; their approach adopt routers that have several local ports, which have high power consumption due to the increased number of ports and high data rates across the crossbar. On the other hand, existing inhomogeneous architectures (Figure 3a) [1; 2; 32; 33; 37; 38; 39; 40; 41; 42] do not consider the dynamics of application traffic load in their inhomogeneous architectures. Applications in such 3D NoCs are not optimized, as communication bandwidth and performance constraints of the applications were not considered in the architecture generation. To resolve this, a systematic approach for generating inhomogeneous 3D NoC architectures where the TSV and buffer utilization of the given application are exploited is proposed in [3]. Though inhomogeneous 3D NoC architectures reduce the number of power (up to 67%) and area hungry 3D routers, as well as the number of TSVs, they inhibit the total performance of the NoC.