# Dynamic Single-Electron Transistor Modeling for High-Frequency Capacitance Characterization
## 1 Introduction  
Thanks to the advances in nanofabrication technology, it is possible to make single-electron transistors (SETs) small enough to realize room-temperature operation [1; 2; 3]. As a result, the values of source, drain and gate capacitances can be in the order of attofarad, which leads to subpicosecond intrinsic time constant even though the tunnel junction resistance is lower bounded by the resistance quantum, \(h/e^{2}\) about 25.8 k\(\Omega\). Such a possibility of high-speed or high-frequency operation of SETs has been discussed before simply based on this small intrinsic time constant [4; 5], but now that the fabrication technology has advanced, it is worthwhile to analyze the high-frequency dynamic behavior of the SET in more detail.  
For this purpose, an understanding of the capacitance components inside the SET is crucial. For example, the Miller effect caused by the feedback capacitance largely affects the frequency response of amplifiers [6]. Recently, charge detection for qubit readout is attempted by observing the gate input capacitance [7; 8; 9; 10], which also requires SET models with capacitance analysis capability.  
Historically, high-speed and high-frequency performance of SET-based circuits have been studied with models based on steady-state master equation [11; 12; 13; 14; 15; 16; 17], under the assumption that the external load capacitance is much larger than the internal one, but the intrinsic high-frequency response of SETs cannot be assessed by the steady-state models. Even with such a model, it is still possible to derive the capacitance components such as terminal capacitances and transcapacitances inside the SET [13], but the frequency dependence of capacitances cannot be evaluated.  
Black-box models [18] and macro models [19] have similar features as long as they just provide an output current instantaneously as a function of terminal voltages.  
Monte Carlo (MC) method [20; 21; 22] can simulate the dynamic or transient behavior of the intrinsic SET. Since the charges in the gate and source/drain tunnel capacitors are explicitly calculated, terminal capacitances and transcapacitances can also be derived from the simulation result. Actually, reference [23] discussed the input capacitance of SETs in conjunction with the electrometer sensitivity. However, MC method is usuallynot compatible with the standard circuit simulator such as SPICE and has difficulties in analyzing frequency-dependent behavior of SET itself or circuits including SETs and other circuit elements.  
SET models based on time-dependent master equations that are capable of analyzing the dynamic behavior have been developed by many researchers [11; 24; 25]. Since the source/drain current can be directly expressed, implementation of the models to SPICE circuit simulator [26; 27] is also straightforward. Once the model is implemented to SPICE circuit simulator, it is possible to analyze the performance of SET circuits including FETs and other circuit elements. Moreover, the MC analysis capability of SPICE allows us to study the variability issue that has become serious in nanometer-scale devices including SETs [28]. However, to the best of our knowledge, there has been no model that can properly describe the terminal capacitances and transcapacitances.  
Considering the above-mentioned background, we have proposed a SET model based on the time-dependent master equation, taking the gate current into account. Our model can not only analyze the high-frequency dynamic behavior of SETs, but also can represent terminal capacitances and transcapacitances. Since this model is implemented in the SPICE circuit simulator, it can be used to evaluate the high-frequency characteristics of various SET-based circuits such as amplifier, oscillator, detector, etc.