## 3 Technologies: Internet of Medical Things  
### Technologies for IoMT Edge Devices  
For years, the CMOS transistor was the subject of aggressive scaling. The aim was to reduce the feature size of the transistor to gain performance, lower power consumption, and increase the circuit complexity, among other benefits. Let \(S\) be the scaling factor. According to [PERSON]'s scaling law, as clock frequency increases by \(S\), the switched power dissipation and the area per gate decreases by \(S^{2}\). For decades, [PERSON]'s law has been used as a guideline to scale the supply voltage for the CMOS technology. According to the ITRS roadmap, 2009 edition, the scaling factor \(S\) was 1.44 per technology cycle. Per contra, the scaling of the supply voltage and the threshold voltage for a gate length below 90 nm do not scale at the same speed as the gate length [16]. In sub-nanometer design, the planar bulk CMOS reached a dead-end [17; 18]. The known factors that led to the dispensing of bulk CMOS block are the short-channel effect and leakage current. In the 70 nm channel length, the active mode leakage current is responsible for over 40% of the total power consumption [19]. Dark silicon has emerged as a design challenge in the nanometer regime. Several design techniques to circumvent the dark silicon issues have been elaborated upon in [20; 21]. The FinFET transistor has been proposed as a substitute for the bulk CMOS transistor [22]. In the double-gate FinFET, the channel length is controlled by two gates. The gates can be independent (IG-FinFET) or shorted (SG-FinFET). Faster logic gates are constructed using SG-FinFET, whereas low-power devices are designed using IG-FinFET. The micro-controller is the core technology for both low-end and middle-end devices [23]. For the high-end device, the single board device is dominant technology. The market survey shows that ARM's 32-bit processor, Cortex-M3, is the leading technology for the development of low-end devices. Table 4 summarizes the processor/microcontroller family, manufacturer, and target application using the cortex-M3 core. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Survey Work** & **Hardware Technology** & **Low-Power VLSI Design** & **Energy Harvesting** & **User Requirements** \\ \hline
[8; 10; 12; 13; 14; 15] & - & - & - & - \\ \hline
[7; 9] & - & - & \(\checkmark\) & - \\ \hline
[11] & \(\checkmark\) & - & - & - \\ \hline This work & \(\checkmark\) & \(\checkmark\) & \(\checkmark\) & \(\checkmark\) \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Comparison between state-of-the-art survey papers. The processor manufactured using 28 nm technology consumes 8 uW/MHz. The reported efficiency of the processor was 3.34 CoreMark/MHz. The Cortex-M3 can be deployed at various levels in the IoT chain (end-device, gate-ways, and cloud services). The Cortex-M3 is based on Armv7-M architecture, using a secure and open-source operating system, _mbed_. The security of the mbed is instured using a multilayer security architecture: hardware, software, communication, and life-cycle. Furthermore, mbed supports the following short-range and long-range connectivity: Bluetooth low-energy, Wi-Fi, Ethernet, cellular, NFC, RFID, LoRa LPWAN, and 6 LoWPAN Sub-GHz Mesh. The Cortex-M3 architecture allows for the integration of a crypto-accelerator. Crypto-algorithms can be implemented using dedicated accelerators or using the instruction set (software implementation). A number of wearables have been designed using cortex-M3 technology [24]. Traditionally, at the onset of the cloud computing era, data collected from IoMT devices are processed by cloud servers using computationally intensive tasks like machine learning algorithms and big data analytics [25]. However cloud-based computing is an energy-inefficient solution, incurs extra latency and puts user privacy at risk. To circumvent these shortcomings, fog-based computing has been advocated (Figure 3). Edge devices in the fog computing paradigm can process, store, and transmit data.