## 5 Hardware Implementation of Modified Modular Projection Method with MLD  
The original [19] and modified modular projection methods for correcting multiple errors in modular codes (Section 4) have the identical error detection stage. For both methods equally, the implementation variability of this stage lies in choosing an appropriate algorithm for calculating the weighted characteristic of the corrected number. The hardware implementation and comparative analysis of such algorithms were presented in [31]. Let us compare the efficiency of error localization and correct data restoration in a WNS. Using various computing devices for implementing methods and algorithms is often dictated by the need to adapt them to the architectural features of a given hardware base. Support of calculations in the ring of integers is a characteristic feature of FPGA computing devices that increases speed but severely restricts the class of executed tasks. The original method [19] can be implemented on FPGA without any restrictions. The modified method contains operations with fractions and, therefore, requires adaptation when implemented on FPGA. Equations (12)-(14) are used for passing to integer calculations. This transition is illustrated by an example in Appendix C (See, Example A3). The result of this example coincides with that of an example in Appendix B. Therefore, the transition to integer calculations by Equations (12)-(14) is correct. The efficiency of the original [19] and modified methods for correcting multiple errors in modular codes was compared by their implementation in the Very High SpeedIntegrated Circuits Hardware Description Language (VHDL) using Xilinx Vivado 2019.1, a software tool for the design and analysis of HDL structures. For testing, we used a Kintex-7 FPGA (core Xilinx xc7k70 ftbg676-2) of a sufficient area without DSP blocks. This software-hardware base has hardware parallelization at the level of blocks implementing individual procedures and functions and, moreover, at the level of operations within these blocks. Figure 2 shows the schemes for parallelizing the compared methods at the block level: vertical lines separate parallel executed blocks, whereas horizontal lines indicate the synchronization of upper blocks. The schemes in Figure 2 specify the corresponding schemes in Figure 1, considering their hardware implementation. The original method [19] contains no parallel blocks (Figure 2a); however, calculations for each modular projection are performed in parallel within each block, except for the first and the last ones. In the modified method, calculations for each modular projection are also performed in parallel within each block, except for the first and last ones; in addition, there is parallelism at the block level (Figure 2b). Let us consider the hardware implementation of each block in Figure 2.  
Original modular projection method with MLD [19] is presented in Appendix D.  
_Modified Modular Projection Method with MLD_  
Block \(X^{\prime}\). When an error is detected, this block receives at the input \(n\) remainders representing the distorted number \(X^{\prime}\) in the \((n,\ k)\)-RRNS. Block \(X^{\prime}_{i}\). This block constructs modular projections. It is implemented in \(C^{t}_{n/2}\) parallel computational threads, where \(t=(n-k)/2\). Each thread corresponds to a modular projection and receives at the input \(k\) remainders of the distorted number \(X^{\prime}\) (the outputs of the block \(X^{\prime}\)) obtained by the modular projection algorithm [29]. Block \(F(X^{\prime}_{i})\). This block calculates the extended weighted characteristics of modular projections \(X^{\prime}_{i}\) in the WNS. According to (12), it is implemented by \(k\) parallel multiplications of the remainders (the outputs of the block \(X^{\prime}_{i}\)) by constants modulo \(M\) and a \(k\)-operand adder [31]. Block \(r_{X^{\prime}_{i}}\). This block calculates the ranks for each modular projection \(X^{\prime}_{i}\).