# SGXDump: A Repeatable Code-Reuse Attack for Extracting SGX Enclave Memory
## 7 Discussion  
Side-channel attacks can be used to leak code and data from higher-privileged execution environments (e.g., an OS kernel, a hypervisor, an SGX enclave, or a trusted OS in the Secure World). Among these secure execution environments, Intel SGX has become widely \begin{table}
\begin{tabular}{l l l} \hline \hline
**Gadgets** & **Function** & **Offset** \\ \hline add cl, byte ptr [rax \(-\) 0x77]; ret; & \_IO\_wstr\_seekoff & 0x77 fb1 \\ add exa, exc; ret; & \_fifota\_word & 0x422 cd \\ add exc, dword ptr [rax + 0x29]; ret; & \_int\_free & 0x85521 \\ add rax, rx; ret; & \_memchr\_see2 & 0x963a8 \\ add rax, rsi; ret; & \_memchr\_see2 & 0x96 bcc \\ mov qword ptr [rdi + 8], rax; ret; & \_IO\_switch\_to\_main\_get\_area & 0x806b6 \\ mov qword ptr [rdx], rax; ret; & \_GI\_ctype\_init & 0x32c4c \\ mov rax, qword ptr [rax]; ret; & \_GI\_res\_state & 0x11a258 \\ movz exa, byte ptr [rax]; ret; & \_getc\_unlocked & 0x7d352 \\ pop rax; ret; & \_mblen & 0x3 cdb8 \\ pop rcx; pop rbx; ret; & \_getopt\_internal & 0 xe2 bea \\ pop rdi; ret; & init\_cacheinfo & 0x25522 \\ pop rsi; ret; & strip & 0x25e42 \\ pop rsp; ret; & check\_one\_fd & 0x25c1a \\ shl rsi, 4; lea rax, [rdi + rsi + 8]; ret; & inet\_rth\_getaddr & 0x11654b \\ sub esp, ed; dec dword ptr [rax + 0x39]; ret; & \_tzfile\_read & 0 xbac9d \\ xchg exa, edi; ret; & strfromd & 0x3 ff8e \\ xchg exa, esi; ret; & check\_node\_accept & 0 xd65d9 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Gadget list used in Graphene-SGX. \begin{table}
\begin{tabular}{l l l r r r} \hline \hline
**Attacks** & **Type** & **Victim** & **Bit per Sec** &
\begin{tabular}{l} **Number of** \\ **Attempts** \\ \end{tabular} & **Noise** \\ \hline MemJam [36] & m-arch contention & Data & 0.42 & 2,000,000 & Yes \\ CopyCat [9] & Ctrl channel & Control flow & 102 & 39,400 & Yes \\ SGXDump (mbedTLS-SGX) & Ctrl channel & Code and data & 2730 & 1 & No \\ SGXDump (Graphene-SGX) & Ctrl channel & Code and data & 682 & 1 & No \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Evaluation result. used because it helps developers easily implement their own code on top of TEE. Owing to this growing popularity, attackers are starting to pay more attention to compromising SGX enclaves via side-channel attacks. Table 4 summarizes the side-channel attacks that can be made against Intel SGX. In the same way as conventional side-channel attacks, we classify side-channel attacks against Intel SGX into three different categories according to the data acquisition channels: page table, branch prediction unit, and cache attacks. Page table side-channel attacks are relatively convenient because the attacker can detect when the victim memory is accessed (e.g., enclave memory or the probe array in SGXDump) via architectural faults or via bit changes in PTE. Thus, many previous works have leveraged the access bit and present bit in PTE [10; 12]. The access bit is used to determine a given page's eviction for cache management by the OS. Since a change in the PTE's access bit does not create an architectural fault, an adversary is required to keep polling this bit to detect memory access. On the other hand, a change in the PTE's present bit raises a page fault exception so that an attacker can detect a memory access event in a noise-free manner. As a variant of page table based-attack, Off-Limits [37] uses the segmentation carried out by Intel CPUs, which is applicable only in the x86 mode. A segmentation unit issues a general protection fault when a victim process accesses the memory area beyond the segmentation limit stored in the descriptor table. Modern CPUs have branch prediction units that consist of a branch target buffer and the directional predictor. BranchScope [38] and BlueThunder [39] leverage 1-level and 2-level predictors in the directional predictor for recording whether previous branch instructions are carried out. They generate intentional collisions with the directional predictor in the same physical core to disclose the result of executed branch instructions. [PERSON] et al.