# Error Mitigation Methods for FSM Using Triple Modular Redundancy
## 6 Conclusions  
This paper presents a performance comparison of error effects mitigation methods for FSMs using triple modular redundancy, implemented in FPGAs. The methods focus on the ability to recover from SEE effects by introducing system redundancy, with various aspects related to the additional logic part utilization. The paper does not consider the effects of the total dose effect, and omits aspects related to the protection of the voter itself, or the configuration memory of the FPGA chip. The experiments carried out included synthesis in academic and commercial environments. \begin{table}
\begin{tabular}{c c c c c c c} \hline
**Benchmarks** & **Model 0** & **Model 1** & **Model 2** & **Model 3** & **Model 4** & **Model 1–4 Mean** \\ \hline dk15 & 1.424 & 1.424 & 0.221 & 1.424 & 0.347 & 0.854 \\ lion & 0.092 & 0.092 & 0.062 & 0.092 & 0.073 & 0.080 \\ mc & 0.219 & 0.219 & 0.347 & 0.219 & 0.135 & 0.230 \\ s8 & 0.101 & 0.097 & 0.151 & 0.101 & 0.112 & 0.115 \\ tav & 0.637 & 0.637 & 0.106 & 0.639 & 0.235 & 0.404 \\ train4 & 0.063 & 0.063 & 0.058 & 0.063 & 0.063 & 0.062 \\ bbara & 0.167 & 0.179 & 0.211 & 0.186 & 0.26 & 0.209 \\ bbtas & 0.102 & 0.103 & 0.126 & 0.1 & 0.095 & 0.106 \\ beecount & 0.933 & 0.839 & 0.3 & 0.93 & 0.787 & 0.714 \\ dk14 & 1.165 & 1.156 & 0.329 & 1.161 & 1.072 & 0.930 \\ dk17 & 0.591 & 0.591 & 0.201 & 0.592 & 0.256 & 0.410 \\ dk27 & 0.026 & 0.026 & 0.07 & 0.026 & 0.087 & 0.052 \\ e\(\varsigma\) & 0.048 & 0.056 & 0.191 & 0.048 & 0.14 & 0.109 \\ e\(\varsigma\)6 & 3.89 & 3.89 & 4.532 & 3.89 & 4.083 & 4.099 \\ e\(\varsigma\)7 & 0.058 & 0.049 & 0.183 & 0.058 & 0.143 & 0.108 \\ lion9 & 0.281 & 0.425 & 0.094 & 0.281 & 0.144 & 0.236 \\ s27 & 0.314 & 0.314 & 0.349 & 0.349 & 0.343 & 0.339 \\ shiftreg & 0.506 & 0.5 & 0.08 & 0.506 & 0.123 & 0.302 \\ dk512 & 0.052 & 0.052 & 0.202 & 0.057 & 0.138 & 0.112 \\ train11 & 0.158 & 0.151 & 0.039 & 0.158 & 0.202 & 0.138 \\ bbsse & 0.325 & 0.325 & 0.582 & 0.378 & 0.85 & 0.534 \\ cse & 0.222 & 0.229 & 0.823 & 0.619 & 0.717 & 0.597 \\ sse & 0.196 & 0.196 & 0.954 & 0.216 & 0.662 & 0.507 \\ e\(\varsigma\)2 & 0.067 & 0.067 & 0.204 & 0.076 & 0.148 & 0.124 \\ keyb & 0.225 & 0.225 & 0.743 & 0.244 & 0.76 & 0.493 \\ s1 & 0.349 & 0.349 & 0.667 & 0.862 & 1.035 & 0.728 \\ tma & 0.235 & 0.228 & 0.391 & 0.231 & 0.536 & 0.347 \\ \hline B-mark mean & 0.461 & 0.462 & 0.452 & 0.500 & 0.502 & 0.479 \\ \hline \end{tabular}
\end{table} 
Table 7: Power [W] results for the Vivado system. Figure 16: Comparison of power results (mean values) in the Vivado system. Considering safety, two models come to the fore: where transition block \(\delta\) together with state register DFF is triplicated and transition block \(\delta\) is triplicated and independently registered (Model 2 and Model 3, respectively). Considering the results from the academic ABC system, Model 2 is superior to Model 3 for area utilization (LUT), number of logic levels, and power dissipation. However, it should be noted that in Model 3, there is an embedded TMR for the output block, so these results are expected. In many test cases, differences in logic occupancy or power dissipation are negligible. The simplest mitigation model (Model 4) is based on triple redundancy of entire FSMs on a black box basis. Clearly, the results in relation to Model 2 and Model 3 are not very different, but it should also be made clear that this model requires resetting the system after an error (or at least setting the correct state in an erroneous FSM). Otherwise, errors can accumulate, as this structure has no auto-correction properties. Described methods may be taken into account for safety-critical FPGA-based designs. Conceptualisation, M.K. and R.C. ; methodology, M.K. and R.C. ; software, M.K. ; formal analysis, M.K. and R.C. ; investigation, M.K. and R.C. ; resources, M.K. and R.C. ; data curation, M.K. ; writing--original draft preparation, M.K. and R.C. ; writing--review and editing, M.K. and R.C. ; visualization, M.K. and R.C. ; supervision, M.K. ; funding acquisition, M.K. and R.C.