## 3 General Strategies for Energy Efficient BSN Hardware
### Flexibility versus _Efficiency_  
The tradeoff between flexibility and efficiency in hardware is well known and very prominent in a comparison of conventional hardware paradigms [17, 18]. The most flexible category of hardware is general purpose processors (GPPs). GPPs exhibit poor energy efficiency due to the overhead of fetching and decoding the instructions that are required to perform a given operation in the datapath. For low power embedded applications like BSNs, general purpose computation is generally performed in fairly simple microcontrollers [7, 19, 20, 21]. Sophisticated operations like a fast Fourier transform (FFT) or data processing algorithm will thus require numerous instructions in the simple core. For example, several sub-threshold processors provide energy per instruction nearing 1 pJ per operation, but they also tend to use small instruction sets and thus result in more instructions to run an operation [7, 19, 20, 21]. The most efficient hardware is hardwired to do its specific task or tasks (e.g., ASIC). ASICs achieve very efficient operation, but they can only perform the function for which they were originally defined. Examples of hardwired implementations in sub-threshold circuits include [22, 23, 24, 25]. Different types of hardware in sub-threshold systems reveal a similar trend as their above-threshold counterparts. Microcontrollers like the one in [19] consume as low as 2.6 pJ/instruction and provide excellent flexibility since they can be reprogrammed for arbitrary tasks. The ASIC implementation of a JPEG co-processor in [24] consumes 1.3 pJ/frame for VGA JPEG encoding. The numbers for energy/operation are similar, but the individual operations on the microcontroller (e.g., instructions) are simple integer computations like addition. Executing a complete JPEG encoding would take many (100s or 1000s) instructions on such a light weight processor, making the total energy per frame much higher than on the ASIC. Of course, the GPP can perform a much broader range of tasks than the JPEG encoder, so this comparison exemplifies the tradeoff between energy efficiency and flexibility. Some BSN nodes may be implemented as complete ASICs like the JPEG processor, but more commonly, ASICs may appear in BSNs as auxiliary hardware accelerator modules, performing commonly occurring functions in the context of a larger system on chip (SoC). Good examples of hardware acceleration are multipliers, floating point units, or FIR filters. These operations can take several instructions over many clock cycles to complete using a GPP, consuming a large amount of energy and time. A hardware accelerator can process data quickly and efficiently. Here, these commonly used components take advantage of the energy and computational efficiencies of the accelerators, whilst their designs need not change. Hardware accelerators provide an opportunity to process data in very specific ways more efficiently than on accompanying programmable hardware. Microprocessor operations are largely inefficient, as we described above. Field Programmable Gate Arrays (FPGAs) are reprogrammable hardware that provide an intermediate choice between ASICs and processors in terms of flexibility and efficiency. An FPGA is configured to act like specific hardware, similar to an ASIC, but the configuration can be changed an arbitrary number of times. The cost of this flexibility is that FPGAs consume 10-100 times more energy than an ASIC due to energy overhead from interconnects, which may account for 85% of the total energy consumption. Most commercial FPGAs target high performance applications to compete with processors, but a sub-threshold FPGA [26] demonstrates that custom FPGA implementations can offer a good tradeoff for flexibility and energy efficiency for energy constrained applications like BSNs.