## 4 Experimental Results and Comparison  
The experimental results obtained using the proposed structure of multifunction modulo (\(2^{n}\pm 1\)) multipliers based on radix-4 Booth encoding, as explained in Section 3, are discussed in this section. The term'merge circuits' is used to represent the incorporated circuits that can support two different types of modular multiplication functions adopted by the modulo (\(2^{n}-1\)) [1] and modulo (\(2^{n}+1\)) [2] multipliers. The proposed multifunction modulo (\(2^{n}\pm 1\)) multipliers can support the aforementioned modular multiplication functions in the same circuit hardware. Table 1 compares the operation ranges of the proposed method and other reported methods. The operation ranges of the multiplicand and multiplier of the proposed modulo (\(2^{n}+1\)) and modulo (\(2^{n}-1\)) multipliers are \(\{0,2^{n}+1\}\) and \(\{0,2^{n}\}\), respectively; these ranges are wider than those of [PERSON] and [PERSON]'s [8] reported hardware structure. The integration of the single modulo functions of the modulo (\(2^{n}+1\)) multipliers and modulo (\(2^{n}-1\)) multipliers into a multifunction modulo (\(2^{n}\pm 1\)) multiplier can save up to 52.59% (\(n=16\)) of the hardware area, as shown in Table 2. As shown in Table 3, compared with that of the original single circuit performing the function of the modulo (\(2^{n}-1\)) multiplier [1] or modulo (\(2^{n}+1\)) multiplier [2] exclusively, the delay time of the proposed method slightly increased for \(n=8\) and \(16\) but slightly decreased for \(n=32\). The delay time of the proposed method is considerably lower than that of [PERSON] and [PERSON]'s [8] method. For the merged circuits, as shown in Table 3, it should be noted that the merged delay time of the modulo (\(2^{n}-1\)) [1] and modulo (\(2^{n}+1\)) [2] multipliers would be selected to be the worst case for the two of them. As Table 4 shows, the dynamic power consumption of the proposed study can be reduced by 44.19% (\(n=8\)) to 49.05% (\(n=16\)). As Table 5 shows, the ADP can be reduced by 38.90% (\(n=8\)) to 50.92% (\(n=32\)). As Table 6 shows, the PDP can be reduced by up to 50.02% (\(n=32\)). It should be noted that the aforementioned ADP and PDP of the merged circuits are defined as the sums of the individual ADPs and PDPs, respectively, of the modulo (\(2^{n}-1\)) [1] multipliers and modulo (\(2^{n}+1\)) [2] multipliers. In Tables 1-6, it is clear that the proposed modulo (\(2^{n}\pm 1\)) multiplier based on radix-4 Booth encoding outperforms other modified Booth methods by exhibiting a wider operation range, lower power consumption, faster operation, better area efficiency, and lower ADP and PDP. The hardware area, power consumption, and delay time are simulated, synthesized, and verified using Verilog HDL and Xilinx FPGA Vivado tools. The Xilinx Artix-7 XC7A35T-CSG324-1 FPGA chipset is adopted. The operating clock frequency, voltage and junction temperature in the simulation are 100 MHz, 3.3 V and 25.4 \({}^{\circ}\)C, respectively. \begin{table}
\begin{tabular}{c c c c c c c c} \hline  & & \multicolumn{2}{c}{**Merged Circuits**} & \multicolumn{2}{c}{**Modulo (\(2^{n}\pm 1\))**} & \multicolumn{2}{c}{**Proposed Work**} \\ \cline{3-8}  & **Item** & \multicolumn{2}{c}{**Modulo (\(2^{n}-1\))**} & \multicolumn{2}{c}{**Modulo (\(2^{n}+1\))**} & \multicolumn{2}{c}{**Modulo (\(2^{n}-1\))**} & \multicolumn{2}{c}{**Modulo (\(2^{n}+1\))**} & \multicolumn{2}{c}{**Modulo (\(2^{n}-1\))**} & \multicolumn{2}{c}{**Modulo (\(2^{n}+1\))**} \\ \hline Operation & Multiplicand & \([0,2^{n}-1]\) & \([0,2^{n}+1]\) & \([0,2^{n}]\) & \([1,2^{n}+1]\) & \([0,2^{n}]\) & \([0,2^{n}+1]\) \\ \cline{2-8} Range & Multiplier & \([0,2^{n}-1]\) & \([0,2^{n}+1]\) & \([0,2^{n}]\) & \([0,2^{n}]\) & \([0,2^{n}]\) & \([0,2^{n}+1]\) \\ \hline \end{tabular}
\end{table} 
Table 1: Comparison of operation ranges of the proposed method and other methods.