## 2 Coding and Decoding Algorithms for LDPC Codes  
LDPC codes are a class of linear block codes, characterized by a very sparse \(M\times N\) parity-check matrix **H** where valid codewords \(x\) satisfy \(\textbf{H}\cdot(x)^{\prime}=0\) and \((\cdot)^{\prime}\) represents the transposition operator. Each LDPC code can be represented as a bipartite graph, known as Tanner Graph [10], containing two sets of nodes: Variable Nodes (VNs) and Check Nodes (CNs). VNs are associated to the \(N\) bits of the codeword, whereas CNs correspond to the \(M\) parity-check constraints. Edges in the graph correspond to ones in the **H** and most of decoding algorithms imply the exchange of information along the edges of the Tanner graph. The most common algorithm to decode LDPC codes is the _Belief Propagation_ (BP) algorithm. The VNs receive the intrinsic information \(\lambda\) (likelihood functions _i.e._, probabilities) from the channel and update it depending on the results of the parity check equations computed at the CNs. This process is iterated several times until either the maximum number of iterations is reached, or a convergence criterion is met. This criterion may be that a codeword was successfully decoded. There are two main scheduling schemes for the BP [11]: two-phase scheduling and layered scheduling [12]. The latter nearly doubles the convergence speed as compared to two-phase scheduling. In a layered decoder, parity-check constraints are grouped in layers, each of which is associated to a component code. Then, layers are decoded in sequence by propagating extrinsic information from one layer to the following one [12]. When all layers have been decoded, one iteration is complete and the overall process can be iteratively repeated up to the desired level of reliability. Let \(S_{j}\) represent the Log-Likelihood-Ratio (LLR) of the bit in column \(j\) of **H**. Bit LLR \(S_{j}\) is initialized to the corresponding received soft value. Then, for each parity constraints \(m\) in a given layer, the following operations are executed:  
\[Q_{mj} =S_{j}^{\rm(old)}-R_{mj}^{\rm(old)} \tag{1}\] \[A_{mj} =\sum_{n\in\mathcal{N}_{m},n\
eq j}\Psi(Q_{mn})\] (2) \[s_{mj} =\prod_{n\in\mathcal{N}_{m},n\
eq j}\mathrm{sgn}(Q_{mn})\] (3) \[R_{mj}^{\rm(new)} =-s_{mj}\cdot\Psi(A_{mj})\] (4) \[S_{j}^{\rm(new)} =Q_{mj}+R_{mj}^{\rm(new)} \tag{5}\]  
\(S_{j}^{\rm(old)}\) is the extrinsic information received from the previous layer and updated in Equation (5) to be propagated to the succeeding layer. Term \(R_{mj}^{\rm(old)}\), pertaining to element (\(m\),\(j\)) of **H**, is used to compute Equation (1); the same amount is then updated in Equation (4), \(R_{mj}^{\rm(new)}\), and stored to be used again in the following iteration. In Equations (2) and (3) \(\mathcal{N}_{m}\) is the set of all bit indices that are connected to parity constraint \(m\). Unfortunately, the computation of Equations (2) and (4) is complex, as \(\Psi(\cdot)\) is a non-linear function. According to [13], Equation (2) can be simplified with a limited Bit-Error-Rate (BER) performance loss as  
\[R_{mj}^{new}\approx-s_{mj}^{\prime}\cdot\min_{t\in\mathcal{N}_{m}\setminus j} \left\{|Q_{tj}|\right\} \tag{6}\]  
usually referred to as _normalized-min-sum_ approximation, where \(s_{mj}^{\prime}=\sigma\cdot s_{mj}\) and \(\sigma\leq 1\). For further details the reader can refer to [8, 10]. A key concern in the design of high throughput LDPC code decoders comes from the communication structure that must be allocated to support message passing among VNs and CNs. Three approaches can be followed in the high level organization of the decoder:  
1. Fully Parallel Architectures (FPA): separate processing units are allocated for each VN and CN and all messages are passed in parallel along dedicated routes. 2. Partially Parallel Architectures (PPA): more processing units work in parallel, serving all VNs and CNs within a number of cycles; suitable organization and hardware support is required to exchange messages. 3.