# Review of Physical Layer Security in 5G Wireless Networks
## 3 Literature Review
In paper [31], the Supersingular Isogeny Key Encapsulation (SIKE) Round 3 method is implemented more quickly using a number of strategies suggested in this research for ARM Cortex-M4 processors. Compression, pre-computation, and hardware acceleration are among the suggested methods. The research analyzes the performance of the suggested strategies on several ARM Cortex-M4 processors and demonstrates that the suggested techniques can result in considerable speedups, up to 10\(\times\) in some circumstances. The presented methods can be utilized to implement the SIKE Round 3 scheme on ARM Cortex-M4 processors with great performance, according to the paper's conclusion. Paper [32] shows that using a combination of software and hardware acceleration approaches, the compact implementations of the Kyber post-quantum key exchange protocol on 64-bit ARM Cortex-A processors are based. The usage of pre-computed tables and the use of optimized code are two examples of software acceleration strategies. Utilizing unique hardware accelerators is one of the hardware acceleration strategies. On a Xilinx Zynq UltraScale+ MPSoC, the suggested implementations were put into operation and demonstrated to deliver speedups of up to 10 times over the prior state-of-the-art implementation. On 64-bit ARM Cortex-A processors, compact Kyber implementations were made; a 64-bit general-purpose ARM Cortex-A processor, which is used in this paper, was used. On this CPU, the study suggests an innovative implementation of the Kyber post-quantum key exchange protocol. Paper [33] highlights that a 32-nm CMOS technology is used to implement the Ed25519 curve-based cryptographic accelerator for digital signatures, which has a throughput of up to 100 million signatures per second. The accelerator is made to be used in many different applications, such as cloud computing, embedded systems, and mobile devices. The accelerator uses a variety of strategies, such as pipelining, parallelization, and the usage of unique hardware accelerators, to attain its high performance. Application-specific integrated circuits are used in this paper. A specialized circuit created for a particular application is known as an ASIC. The research suggests a brand-new Ed25519-based cryptographic accelerator for digital signatures. [PERSON] et al. [34] present a new approach for identifying faults in finite field multipliers in the study \"Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography\" (2022). The technique, which is based on CRC codes, can be used to find single-bit errors in a data stream. The proposed method has been tested on a number of finite field multipliers and has proven to be highly effective at spotting faults. The finite field multiplier is not significantly burdened by the approach, which is also effective. The lightweight stream cipher Pomaranch, which is made for devices with limited resources, can have its fault resistance improved using the suggested technique. The Pomaranch encryption is vulnerable to fault attacks, but the suggested technique can be used to find mistakes in the Pomaranch cipher's finite field multipliers. The cipher has the option to stop and restart if an error is found. The fault resilience of the Pomaranch cipher can be increased by employing the suggested way. An FPGA (field-programmable gate array) is used in this paper. An FPGA is a programmable semiconductor that may be set up to carry out various tasks. The research suggests a novel CRC-based error detection scheme for finite field multipliers. The authors of article [35] review state-of-the-art lightweight hash functions and assess how well they perform on various IoT devices. The Grostl hash function, a compact hash function created for devices with limited resources, is the main topic of this study. On a variety of IoT devices, the Grostl hash function has been assessed and confirmed to be effective and secure.