## 5 CAD Tools and Simulation Environment  
In this section, we will discuss the requirements and progress towards creating simulation environments for inter-chip wireless interconnections. Simulations are important to enable proof-of-concept, initial performance analysis and early design decisions. Infrastructure development at mm-wave frequencies is a very expensive enterprise making simulations even more important. However, simulation of wireless interconnection requires amalgamation of multiple simulation tools. At the physical layer, finite element methods need to be adopted to estimate channel characteristicsor design on-chip antennas. ANSYS High Frequency Structural Simulator (HFSS) [85] is among the most popular simulator used for simulation of channel characteristics and transmission characteristics of antennas. The transmitter and receiver circuits require Electronic Design and Automation (EDA) tools such as Cadence for design and simulations. RF design kits are required to model the mm-wave circuit components. Routers and interconnection network switches can be designed also using similar tools using RTL-level designs and extracting post-synthesis performance parameters using either ASIC design flows such as Synopsys or FPGA flow such as Xilinx. Using the characteristics of the antenna, channel, transceiver circuits and routers, system-level simulators need to be used to capture the performance of the wireless inter-chip interconnection system. System-level simulators such as Gem-5 [86] or Multi2 Sim [87] can be used to simulate multicore parallel systems even with heterogeneous processors and memory subsystems integrated with a pre-defined interconnection network. In case the data transport mechanism and switching protocol in the multi-chip system is same as that of an intra-chip NoC to create a seamless interconnection a NoC simulator can be extended to evaluate such multi-chip systems. A NoC simulator models the data flow by considering various simulation parameters and settings required for a specific system architecture. Although several NoC simulator exist [88; 89; 90], they have limited ability to model and evaluate wireless interconnection fabrics. A wireless NoC (WiNoC) simulator is available in the public domain [88]. In addition to implementing data flow and estimating various network performance metrics such as throughput, packet latency and packet energy WiNoC simulators have special features to simulate a system with specific applications. In [11] a cycle accurate WiNoC simulator has been used that characterizes the multi-chip architecture and models the progress of the flits over the switches and links per cycle accounting for those flits that reach the destination as well as those that are stalled. The WI is modeled as a port connected to the network switches where they are deployed. In [88] the author presented a configurable, extendible NoC simulator developed in system C that can analyze the performance and power figures of the both conventional wired NoC as well as emerging WiNoC architectures. The simulator not only supports synthetic traffic but also supports running application specific benchmarks under proper mapping. The simulator also supports basic routing algorithm and provide the flexibility to incorporate new algorithm from users. Figure 14 captures the interaction between simulators at various levels of abstraction. Using the above described simulation flow a wireless inter-chip interconnection fabric is evaluated for application specific traffic. We consider a wireless multi-chip configu  
Figure 14: WiNoC simulation flow. processor chips and 4 DRAM memory stacks. The cores are considered to be out-of-order cores with 32 KB of L1 and 512 KB of L2 cache running a Directory-based MOESI cache coherency protocol. The memory stacks are considered to be 3D stacks with 4 layers on top of a logic layer responsible for memory addressing. The logic layer in each stack is equipped with a WI which can communicate with the WIs in the multicore chips.