# Design and Simulation of Low-Orbit Satellite Broadcast Signal Receiving and Processing Terminal
## 3 Key Technologies
### FFT Fast Acquisition Method Introducing Bit Synchronization Loop
\begin{table}
\begin{tabular}{c c c} \hline
**Compared Items** & **FFT Frequency Domain Acquisition Method** & **FFT Fast Acquisition Method** \\ \hline Symbol rate & Can only be an integer multiple of the pseudocode period & Arbitrary proportional relationship \\ \hline Pseudocode and symbol alignment & Necessary & Unnecessary \\ \hline Accumulation method & Incoherent & Coherent \\ \hline Cumulative length & Generally, 4 cycles & 4–8 cycles \\ \hline Maximum value of Doppler frequency & \(\pm\)100 kHz & \(\pm\)250 kHz \\ \hline Capture time & About 1 s & About 60 ms \\ \hline \end{tabular}
\end{table} 
Table 1: Comparison results between FFT fast acquisition method and traditional FFT frequency domain capture method. Figure 6: Fast acquisition algorithm FPGA design diagram. loop, named a bit synchronization loop, to achieve tracking and demodulation of signals containing large Doppler shift and pseudo-code asynchronous signals in satellite downlink signals [47; 48]. In this scheme, the carrier loop uses the COSTAS loop, the pseudo-code loop uses the DDLL loop, and the bit synchronization loop uses the classic DTTL loop [56]. The detailed design of the three loops of the tracking module is shown in Figures 7-9, respectively. It includes (1) three DDSs, which drive the carrier tracking loop, the pseudo-code tracking loop, and the bit synchronization tracking loop, respectively; (2) lead-lag timely correlators, of which there are four in parallel, which correlate different code phases to support RAKE reception; (3) pseudo-code phase error detection, carrier and phase error detection, SNR estimator, and data edge jump detector; (4) three LPF low-pass filters to track Doppler and Doppler acceleration. The precise tracking of the code chip is divided into two steps: (1) First, the code chip tracking loop uses the non-coherent envelope correlation delay lock loop to perform a rough measurement of the code chip delay. Under the premise of ensuring the normal tracking of the code delay lock loop, the narrowest possible correlation interval is used, and the accuracy of the code chip delay estimation is limited to one code chip; (2) Then, the carrier-assisted technology is used to estimate the carrier phase through the detection algorithm, and the change value of this carrier phase in the code delay lock loop data update interval (also called differential phase) is fed back to the digital control oscillator of the code loop, and the code delay offset caused by the Doppler effect is corrected by fine-tuning the code NCO. On the basis of ensuring the reliable tracking of the code delay  
Figure 8: FPGA design of code tracking loop. Figure 7: FPGA design of carrier tracking loop. lock loop, a narrow loop bandwidth, and a smaller correlation interval are used to obtain the required accurate code chip delay estimation value. This system uses carrier-assisted technology, that is, the carrier phase change is used to assist the code delay loop in tracking. Because the noise that causes carrier loop jitter is much smaller than the noise that causes code loop jitter, appropriate signal estimation technology can be used in highly dynamic environments. While the carrier tracking loop accurately tracks the carrier phase change, it can extract accurate chip delay correction to assist the code delay loop in tracking. If the chip delay change is continuous, the bandwidth of the DDLL loop can be made very narrow to suppress noise. The essence of this method is that the carrier tracking loop provides accurate chip delay changes, and the code tracking loop DDLL improves the measurement accuracy of chip delay by adopting a narrower loop bandwidth and a smaller correlation interval.