## 2 Background
### Basics of NAND Flash Memory  
**NAND Flash Organization**  
The NAND flash memory consists of flash cells, which store data, and peripheral circuits, which support flash commands such as read, write, and erase. Flash cells are grouped into a page, and multiple pages form a block. Figure 1 illustrates a typical flash block organization (i.e., conventional 2D NAND device). There are \(n\) word lines (WLs) in this block, and each WL has \(m\) flash cells. The common WL\({}_{i}\) signal from the row decoder module is shared by the flash cells on the same WL, and they are read or programmed together as a unit. A WL can store more than one page (up to four pages) depending on how many bits can fit into a single flash cell. All flash cells along the same column are connected in series to form a bit line (BL\({}_{i}\)). BLs are shared by all of the blocks in a flash chip and connected to the page buffer module, which is used for off-chip data transfers through the data-in/out circuit. The source select line (SSL) and ground select line (GSL) of a block are also composed of two select transistors, one at the top and one at the bottom of a BL. We can activate the flash block for flash operations by supplying proper voltages on the gate of GSL and SSL transistors. Although the flash cell, shown in Figure 1, is structurally similar to a normal MOS transistor, it is unique in that it can adjust its threshold voltage \(V_{th}\) by injecting electrons into (or ejecting electrons from) the floating gate. Depending on the amount of electrons in the floating gate, therefore, the flash cell may work as an off switch or an on switch under a given control gate voltage, thus effectively storing bit data. For example, we can assign '0' state when the flash cell has a high \(V_{th}\) and '1' state when the flash cell has a low \(V_{th}\). **NAND Flash Operation**  
NAND flash memory has three basic operations to act as non-volatile memory. The program operation, which increases \(V_{th}\) of selected flash cells, transfers electrons from the substrate into the floating gates of the selected flash cells using FN tunneling [24] by applying a high voltage (>20 V) to WL gates. On the other hand, to erase programmed cells, a high voltage (>20 V) is applied to the substrate (while WL gates are set to a low  
Figure 1: An overview of a conventional 2D NAND flash block. voltage such as 0 V) to remove electrons from floating gates, which decreases the \(V_{th}\) of the flash cells. Since the program operation can only change the bit value of a flash cell from '1' to '0', all the flash cells of a page should be erased to program data on the page (_erase-before-program_). The erase operation works in a block granularity because the high voltage is applied to the entire substrate that underlies the flash blocks, enabling a high erase bandwidth. In order to read the stored data from flash cells, the \(V_{th}\) level of the flash cells on the selected WL is probed by using a read reference voltage \(V_{ref}\). In Figure 1, when WL\({}_{k}\) is selected for read (since other WLs (e.g., WL\({}_{k+1}\) or WL\({}_{k-1}\)) should not affect the read operation of WL\({}_{k}\), all the flash cells in other WLs should behave like pass transistors, and therefore, their gate voltage is set to \(V_{READ}\) (>6 V) which is much higher than the highest \(V_{th}\) value of a flash cell), if \(V_{th}\) of the \(i\)-th flash cell in WL\({}_{k}\) is higher than \(V_{ref}\), the \(i\)-th flash cell turns off, so the cell current of BL\({}_{i}\) is blocked (i.e., the flash cell is identified as '0'). On the other hand, if the \(V_{th}\) of the \(i\)-th flash cell is lower than \(V_{ref}\), the \(i\)-th flash cell turns on, so the cell current can flow through BL\({}_{i}\) (i.e., the flash cell is identified as '1'). By sensing BL\({}_{i}\)'s from the selected WL\({}_{k}\), the stored data are read out to the page buffer.