## 1 Introduction
Nevertheless, there is still a lack of chip-level experimental verification for the application of 2D materials, and it is a great challenge to produce 2D materials with large-area and high-quality growth. To achieve large-scale parallel and efficient brain-like computing in devices, strict requirements are put forward for the uniformity, reliability, and stability of device performance. Memory integration and uniformity are the primary conditions, while endurance and retention are the key factors. Optimizing the application characteristics of memristor devices (such as switching energy and speed, retention, and endurance) helps to maximize the computing area, energy efficiency, and memory capacity of memristor-based neural networks. [PERSON] et al. reported a random dynamic artificial neuron based on a diffusion-type memristor device, which can realize unsupervised synaptic weight update and pattern classification of integral memory convolution neural network using artificial neurons and break through the limitation of silicon-based CMOS neural morphology computing chips [4]. Yet, most related research on neuromorphic computing focuses on a single device or a small array. Still, the problems of sneak path current and wire resistance also challenge the realization of a large-scale and high-density crossbar array. The introduction of third-generation neural networks-spike neural networks has promoted deep-learning networks to develop a series of new logical structures and algorithms and filled the gap between neural science and machine learning, which provides the possibility for the construction of large-scale neural networks. Although deep-learning algorithms show excellent performance in many fields, they need to consume a lot of storage and computing resources when performing data calculation and analysis and must have competitive advantages in training ability, speed, and algorithm accuracy [5]. This also reflects the urgent need for non-Von Neumann-architecture-based chips. [PERSON] et al. improved the tolerance of algorithms, training speed, and power of machine learning on large-scale artificial neural network chips based on nonvolatile synaptic devices [6]. However, this research does not improve the data-transmission ability between neural network modules. [PERSON] et al. proposed a design of synaptic unit cells to simulate DNN training. By combining a hardware array with circuit simulation through software and hardware mixed experiments, it was estimated that its efficiency and throughput were 280 times and 100 times higher than those of the latest GPU, respectively, providing a reference for training on neuromorphic chips [7]. Although network-level research on applications such as neuromorphic devices, crossbar arrays, and neuromorphic systems is booming, there is still an urgent need to obtain knowledge from neuroscience research. The purpose of this Special Issue on \"Deep Learning and Neuromorphic Chips\" is to provide corresponding research opportunities to solve the \"memory wall\" and \"power wall\" problems in the Von Neumann architecture in terms of new materials, new device characteristics, new algorithms, and integration technologies to achieve brain level computing capabilities and ultra-low power consumption, as well as support the rapid development of artificial intelligence and other fields. I believe that the above research will inspire the development of deep learning and the application of neuromorphic chips. This research was funded by the Young Scientists Fund of the National Natural Science Foundation of China [grant number: 62204219]. The authors declare no conflict of interest.