# FPGA Applied to Latency Reduction for the Tactile Internet
## 6 Implementation Description
### Forward Kinematics (FK-HMD and FK-HSD)  
As illustrated in Figure 4, both the hardware associated with the master device (HMD) and the hardware associated with the slave device (HSD) implement forward kinematics through the FK-HMD and FK-HSD modules, respectively. These modules have the same FPGA-implemented circuit, differing only in the input and output signals. They are designed to work with three input signals, one for each component of the angular positioning of the device's joints, and three output signals, one for each component of the the positioning of the device's tool in the Cartesian system. The input signals are \(\theta_{1}[F32](n)\), \(\theta_{2}[F32](n)\) and \(\theta_{3}[F32](n)\) and the output signals are \(x[F32](n)\), \(y[F32](n)\) and \(z[F32](n)\). For FK-HMD, the input signals represent the \(\theta_{1}^{MD}[F32](n)\), \(\theta_{2}^{MD}[F32](n)\) and \(\theta_{3}^{MD}[F32](n)\) signals, and the output signals represent the \(x^{HMD}[F32](n)\), \(y^{HMD}[F32](n)\) and \(z^{HMD}[F32](n)\) signals. In the case of the FK-HSD module, the input signals represent the signals \(\theta_{1}^{SD}[F32](n)\), \(\theta_{2}^{SD}[F32](n)\) and \(\theta_{3}^{SD}[F32](n)\) and the output signals represent  
Figure 5: Proposed circuit for calculating trigonometric functions—TFB. the signals \(x^{ENV}(n)\), \(y^{ENV}(n)\) and \(z^{ENV}(n)\). At every \(n\)-th instant all the computation performed in order to calculate the forward kinematics are executed in parallel. Based on Equation (15), the algorithm used for calculating \(x[F32](n)\) was implemented in FPGA through the generic circuit illustrated in Figure 6. The circuit was designed to work with three input signals \(\theta_{1}[F32](n)\), \(\theta_{2}[F32](n)\) and \(\theta_{3}[F32](n)\) and one output signal. These signals are forwarded to TFB sub circuits where sine and cosine calculations are performed. For this process the constants \(L_{1}\) and \(L_{2}\), three multipliers, one inverter and one adder are used. The calculation of \(y[F32](n)\) based on Equation (16) was implemented in FPGA through the generic circuit shown in Figure 7. The circuit was designed to work with two input signals \(\theta_{2}[F32](n)\) and \(\theta_{3}[F32](n)\) and one output signal. These signals are routed to TFB sub circuits to perform sine and cosine calculations. In the process flow four multipliers, two adders, one inverter and the constants \(L_{1}\) and \(L_{2}\) are used. The generic circuit illustrated in Figure 8 was implemented in FPGA to perform the calculation of \(z[F32](n)\) and it is based on Equation (17). The circuit is designed to work with three input signals \(\theta_{1}[F32](n)\), \(\theta_{2}[F32](n)\) and \(\theta_{3}[F32](n)\) and one output signal. These signals are routed to TFB sub circuits in order to perform sine and cosine calculations. In the process flow four multipliers, two adders, one inverter and the constants \(L_{1}\), \(L_{2}\) and \(L_{4}\) are used. Figure 6: Proposed forward kinematics circuit for obtaining the \(x[F32](n)\) spatial coordinate (Equation (15))—FK-HMD and FK-HSD. Figure 7: Proposed forward kinematics circuit for obtaining the \(y[F32](n)\) spatial coordinate (Equation (16))—FK-HMD and FK-HSD.