# Security Implications for Ultra-Low Power Configurable SoC FPAA Embedded Systems
## 3 Low-Power Context-Aware FPAA Architectures  
The need for low average power consumption requires that higher power devices, like wireless transceivers and even embedded \(\upmu\)P, must be shut down most of the time. Digital communication typically dominates the overall energy consumption [11]. These devices should be active only in those rare cases where they are needed, such as when messages need to be passed between nodes. Similarly high power sensors and actuators (e.g., acoustic speaker) needs to be shut down except when it is being used.  
The FPAA enabled sensor node (Figure 1) classifies (e.g., [3]) and learns from original sensor signals, performing all of the computation, classification, and learning required, and operating the entire system in its real-world application environment. FPAA devices allows the user to investigate many physical computing designs within a few weeks of time. The alternative for one design would require years of IC design by potentially multiple individuals.  
Figure 3 shows the comparison of energy required at each level, as well as the computational power available at each stage for different computing block types. The always-on computation in stage one requires being physical computation, both because of its computational power as well as its close proximity to sensor inputs. FPAAs enable small ultra-low power physical computing devices capable of computational-intensive (>10 MMAC(/s)) context-aware processing. This approach requires low-power components, continuously operating or operating frequently, that can decide when to wake up the expensive hardware components.  
Figure 3: Opportunities for low-power physical computing sensor nodes. Context-aware processing using some continuously-on analog computation and classification enables significant opportunities for small, wireless sensor nodes. The typical sensor node is estimated in terms of computational capability and required energy for each stage. The factor of \(\times\)1000 improvement in energy efficiency turns these sensor nodes from simple acquisition elements to full computational devices with more real-time computation than most laptop computers. Communication occurs only when absolutely necessary.  
Physical computing in context-aware architectures enables potential energy harvesting opportunities, but further constraining potential device security techniques. Figure 4 shows the typical breakdown for a context-aware node computation with a 100 \(\upmu\)W power budget. The node requiring 100 \(\upmu\)W average power could operate for a several months on a single battery. These physical computing components are enabled by the \(\times\)1000 energy improvement (and x100 area improvement). Most energy harvesting devices supply \(\approx\)10 \(\upmu\)W of power per cm\({}^{2}\) except in unusual environments. Figure 4 shows the device lifetime (due to average power consumption) for a single coin cell battery (0.1-0.5 Ah). A 10 cm\({}^{2}\) energy harvesting device could supply 100 \(\upmu\)W of average power, a manageable area for an embedded sensor node. Energy harvesting requires a number of straight-forward regulators and circuits [12], infrastructure mostly built on the SoC FPAA IC [3].