# Method and System for Heart Rate Estimation Using Linear Prediction Filtering +
## 3 Results  
The main code for LPC computations was tested in a MATLAB v24.1 function using excerpts of signals from the MIT or PhysioNet databases [37, 38], and the obtained results were quite plausible. For example, Figure 11 displays a test with a bigemy-affected ECG excerpt from the MIT database. Notice the presence of a DC level in the ECG signal for this case. The algorithm successfully captured the instantaneous heart rate, as evident in the stem plot of heartbeat events. Next, we test an example of an ECG with arrhythmia containing substantial noise. The result is displayed in Figure 12, and again, one can see the LPC approach's effectiveness in tackling this kind of artifact. Finally, the algorithm was tested with a signal containing an evident motion artifact. As in the preceding tests, one can see in Figure 13 that the approach is robust to various signal acquisition disturbances. The developed hardware is based on the block diagram shown in Figure 14. The system consists of an ESP32 microprocessor module that reads the signal from the AD8232 ECG signal conditioning module, executes the LPC algorithm to determine the heart rate, presents the data on an LCD, and saves the data to an SD card, in addition to a charge control module for 18650 lithium-ion batteries and a voltage source of 3.3 and 5 volts. Capacitors of 2.2 uF and 10 uF were placed near the power pins of the ESP32 and AD8232 modules to eliminate possible 60 Hz noise. During processing, the hardware consumption is a current of 175 mA at a voltage of 5.5 V, that is, a maximum power of 0.96 W, and a minimum autonomy with uninterrupted processing of approximately 14 h.  
Figure 10: Arbitrary function generator. The developed firmware was based on the actions in the block diagram in Figures 15-17. Figure 15 provides an overview of the code produced. The sequence of initial configurations of internal and external peripherals used, of parallel processing in two cores, and of digital filters is shown in Figure 16.  
Figure 11: Bigemy-affected ECG and estimated heart rate with LPC filtering. Figure 12: Typical arrhythmia in a noisy ECG and estimated heart rate with LPC filtering. The Acquisition and Processing block of Figure 15 is detailed in Figure 17. Core 0 was reserved for future processing of the Wi-Fi communication, and the other tasks were executed in Core 1. The ECG signal acquisition and filtering activities were assigned to a parallel processing task executed within a time interval of 4 milliseconds, providing a sampling rate of 250 samples per second. A 60 Hz digital notch filter and a second-order low-pass digital filter with a cutoff frequency of 500 Hz are applied to the signal. Upon reaching 600 acquired samples, another task is enabled from a semaphore, and the transfer of these samples from the acquisition buffer to another begins, avoiding overwriting of this buffer during the processing of the heart rate determination algorithm. The LPC algorithm for estimating the heart rate with order \(p=4\) and displaying it on an LCD is only executed after enabling a semaphore at the end of the buffer sample transfer task. The flow control of the parallel processing was executed using the Free RTOS real-time operating system. The firmware and variables require 361,205 bytes (27%) of program storage space and 39,824 bytes (12%) of dynamic memory, respectively. Figure 14: Hardware block diagram (simplified). Figure 13: ECG signal affected by motion artifact and estimated heart rate with LPC filtering. Figure 16: Peripheral configuration. Figure 17: Acquisition and processing. Figure 10:0 ESP32 firmware overview. The ECG signal emulated by the function generator at a set of frequencies, 30, 60, 120, and 180 beats per minute, was used as excitation to the developed system.