# Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs
## 5 Evaluation of DNN Accelerators under Delta-Based MINs  
Implementation of the DNN accelerators is fit for application, particularly with ASIC or FPGA designs. In the present section, we highlight the importance of introducing the Interconnection process into machine learning operations, in conformity with the exponential growth of parallel computation on chip. Figure 8 illustrates a sample example of Neural Network architecture dubbed _LeNet-5_. Designed to recognize handwritten digits, the scheme has been used by several banks to identify hand-written numbers on checks. Every number is digitized into 32 \(\times\) 32 pixel grey scale input images. This neural network is managed on a seven-level convolutional network. The subsequent section provides an extensive account of the evaluation process for the DNN accelerators within the framework of our hybrid Delta MINs. This involves incorporating the main modules into a NoC-based NN accelerator. To the best of our knowledge, we have undertaken a comprehensive investigation, focusing especially on the necessary steps required to conduct the experiments and perform an in-depth analysis. This analysis involves conducting a comparison between the Delta MIN design and a parallel Mesh topology. Experimental analyses are performed on a number of the NoC architectural characteristics, including the topology and scale of the network, to assess the impact of Neural Network inference on latency end energy levels of the chip-based communication. In the context of interconnected architecture, a node can be a processing element (PE), or a memory (M). The PE plays a fundamental role in the performance of the computational  
Figure 8: NeuralNetwork LeNet 5 Design. Figure 7: Performance Evaluation of Hybrid Delta MIN for table-based (TT) traffic for 32, 64, and 128 cores. engine used in the NoC-based DNN accelerator. Indeed, it is heavily deployed at the level of the three main layers of the DNN, more specifically, the (conv., max/aver, and fully conn.) layers. The special mapping process of each layers will be specified in the NoC, along with the relevant identification of the data flows. We will also provide a detailed explanation of the flowing process of two main data paths: intra-NoC or data flows between the DNN and NoC-based processors, as well as the off-NoC or data flows maintained between the DNN-NoC and the main memory. At the level of the convolutional layer, a set of filters and the input feature map represent the inputs of the convolutional layer. Figure 9 outlines a convolution layer flow using six filters. In this example context, a 4 \(\times\) 4 Mesh is applied as an NoC configuration involving a single shared Memory and fifteen PEs. At the first step level, the input feature map loading process is being drawn from the main memory. The MI is allotted the task of sending the input feature map to the PEs required at this layer's level. The filters are loaded from the main memory at the second step level and then sent to a particular PE. After getting all the necessary filters, each PE undertakes to compute an output feature map channel. In the ultimate step, every PE encloses all the filters to undertake the computing process of a fit channel out of the output feature map to be stored back in the main memory. The output feature map would stand as the input feature map for the next neural network-associated layer. Both the average pool and max pool are considered for a pooling layer. We consider a 1 : \(n\) mapping, binding the processing elements (PEs) and the feature map channels. It is worth specifying, at this level, that a PE is able to operate several feature map channels, i.e., every PE receives the input feature map channel that is currently stored in its local memory. Thus, no PE-to-PE traffic would persist. As already stated, the fetch of the feature map channel could be completed at the level of the main memory if the local storage element is not large enough.