# Constrained Optimization of FPGA Design for Spaceborne InSAR Processing
## 3 Design of System and Structure
### Matrix Transposition Based on AXI  
Matrix transposition is an essential step in the 2D FFT calculation of coarse registration. The efficiency of matrix transposition significantly affects the total time of coarse registration. The burst length of the native interface in DDR3 SDRAM is 8 [36], yet the burst length of the AXI can reach 1024 data. The schemes [36; 37; 38; 39; 40; 41; 42; 43; 44] of existing research on matrix transposition are built on the native interface, which could not be used in the SoPC system directly. However, the existing matrix transposition schemes could shed light on the research on the AXI matrix transposition. Inspired by a previous study [37], we found out that the key to efficient matrix transposition data access lay in the balance of two-dimensional data: the number of range and azimuth data were the same. Therefore, the azimuth and range data in the design structure occupied half of the continuous data. The matrix block structure, including the reading and writing process, is shown in Figure 5.  
We took the transfer of 256 data of 64 bit at a time as an example to illustrate the reading and writing process. For the 512 \(\times\) 512-point data to be registered, 16 lines of data were buffered. After that, we rearranged the data to take 16 range data in each row, then put the 256 data from 16 rows into a line. Then, the new array containing 32 lines was placed into DDR3 SDRAM in the direction of the arrows in Figure 5, until the writing process was completed. When data was read from the storage s  
Figure 4: The graduated registration. “Base_Row” represents the initial row address in DDR. “Base_Col” means the initial column address in DDR. Both “Base_Row” and “Base_Col” are base addresses. “\(y\)-axis” and “\(x\)-axis” denote the offset addresses.  
Figure 5: Reading and writing process of matrix transposition.  
the entire row of the DDR3 SDRAM according to different row addresses to form an array. The array corresponded to 16 columns that were the transposed data.  
When the burst length of AXI changed, the efficiency would be different, and the matrix transposition structure would be different. Among the achievable solutions, the burst length could be selected as 1024, 256, 64, and 16; correspondingly, 32, 16, 8, and 4 pieces of data needed to be buffered and transposed. It could be seen that as the burst length increased, the efficiency gradually increased, and the corresponding storage resources increased. In this paper, the coarse registration dealt with 512 \(\times\) 512 floating-point complex images. If the most efficient transfer was achieved, the burst length was 1024, with 32 lines of image data buffered in the RAM. Considering both the reading and writing process, the storage space was at least 2 \(\times\) 512 \(\times\) 32 \(\times\) 64 bit = 2 Mb.  
Under the condition that the image size remained unchanged, the higher transmission efficiency led to more BRAM resources being occupied correspondingly. This also reflected the contradiction between the processing capacity and resources in the FPGA design. The limited amounts of resources would inevitably limit the processing capacity. Faced with this conflict, it was necessary to make a balance and trade-off from the system design perspective so that the used resources could maximize the processing performance. To analyze and solve this problem, the following section examines the two-dimensional constraints of processing capacity and resources from a systematic perspective.