# DC Converter with Wide Soft Switching Operation, Wide Input Voltage and Low Current Ripple
## 3 Principles of Operation  
The variable switching frequency related to input voltage and load conditions is used to adjust load voltage. \(S_{ac}\) is kept at on or off state according to the low (\(V_{in,\,min}\)-\(2V_{in,\,min}\)) or high (\(2V_{in,\,min}\)-\(4V_{in,\,min}\)) input voltage mode. Figures 2 and 3 illustrate the PWM signals for low and high input voltage modes. The studied \(LLC\) converter has six effective operating steps if the series resonant frequency (\(f_{r}\)) is greater than the switching frequency (\(f_{sw}\)). For low input voltage mode (Figure 1b), ac switch \(S_{ac}\) is in the on-state. \(L_{1}\), \(L_{2}\), \(S_{1}\)-\(S_{4}\) and \(C\) are operated as two interleaved boost converters to accomplish input current ripple-free. The boost capacitor voltage \(V_{C}=2V_{in}\) due to the duty ratio \(d_{S1}=d_{S2}=d_{S3}=d_{S4}=0.5\). Components \(S_{1}\)-\(S_{4}\), \(L_{r}\), \(C_{r}\), \(T\), \(D_{o1}\) and \(D_{o2}\) are operated as a full-bridge structure \(LLC\) converter. Figure 2a gives the pulse-width modulation waveforms and Figure 2b-g show the circuits for six operating steps. Under the low input voltage mode, the voltage gain of the full-bridge structure \(LLC\) converter is \(G_{L}=nV_{o}/V_{in,L}\), where \(V_{in,L}\) denotes \(V_{in,min}<V_{in}<2V_{in,min}\) and \(n\) denotes the transformer turns ratio. **Step 1 [\(t_{0}\leq t<t_{1}\)]:** At \(t_{0}\), \(v_{C2S}\) and \(v_{C3S}\) are decreased to zero voltage and \(D_{S2}\) and \(D_{S3}\) become on due to \(i_{S2}(t_{0})<0\) and \(i_{S3}(t_{0})<0\). Active semiconductors \(S_{2}\) and \(S_{3}\) are turned on after time \(t_{0}\) to realize zero-voltage switching. The boost inductor voltages \(V_{L1}\) equals \(V_{in}\) and \(V_{L2}=V_{in}-V_{C}\approx-V_{in}\). \(i_{L1}\) is increasing and \(i_{L2}\) is decreasing. Voltage \(V_{C}\) connects to \(L_{r}\), \(C\), and \(L_{m}\). Due to \(D_{o2}\) is conducting, it can obtain \(v_{Lm}=-nV_{o2}=-nV_{o}/2\). Components \(C_{r}\) and \(L_{r}\) are resonant with the resonant frequency \(f_{r}=1/2\pi\sqrt{L_{r}C_{r}}\). **Step 2 [\(t_{1}\leq t<t_{2}\)]:** Because of \(f_{r}>f_{sw}\), \(i_{Lm}\) equals \(i_{Lr}\) at time \(t_{1}\). Therefore, \(D_{o2}\) is reverse biased. \(L_{m}\), \(C_{r}\), \(L_{m}\) and \(L_{r}\) are resonant in step 2 with the other resonant frequency \(f_{p}=1/2\pi\sqrt{(L_{m}+L_{r})C_{r}}<\)\(f_{r}\). \(i_{L1}\) is still increasing and \(i_{L2}\) is decreasing in step 2. **Step 3 [\(t_{2}\leq t<t_{3}\)]:** At half of switching cycle (\(t_{2}=T_{sw}/2\)), switches \(S_{2}\) and \(S_{3}\) turn off. Since \(i_{L1}(t_{2})-i_{L1}(t_{2})\) is greater than zero current and \(i_{L1^{\prime}1}(t_{2})+i_{L2}(t_{2})\) is less than zero current, capacitors \(C_{S1}\) and \(C_{S4}\) will be discharged at time \(t_{2}\). After time \(t_{2}\), \(i_{Lr}>i_{Lm}\), \(D_{o1}\) is forward biased and \(v_{Lm}=nV_{o1}=nV_{o}/2\). **Step 4 [\(t_{3}\leq t<t_{4}\)]:** At \(t_{3}\), the voltages \(v_{C51}\) and \(v_{C54}\) are decreased to zero voltage. Owing to the fact that \(i_{S1}(t_{3})\) and \(i_{S4}(t_{3})\) are both less than zero, \(D_{S1}\) and \(D_{S4}\) become on. After \(t_{3}\), \(S_{1}\) and \(S_{4}\) turn on with  
Figure 1: Proposed wide voltage range LLC (inductor–inductor–capacitor) converter with input current ripple-free (**a**) circuit diagram, (**b**) equivalent circuit under low input voltage mode, (**c**) equivalent circuit under high input voltage mode. zero-voltage switching. In this step, \(i_{Lr}>i_{Lm}\) so that \(D_{o1}\) conducts and \(v_{Lm}=nV_{o}/2\). \(L_{r}\) and \(C_{r}\) are resonant with resonant frequency \(f_{r}\) in this step. Inductor voltages \(v_{L1}=V_{in}-V_{C}\approx-V_{in}\) and \(v_{L2}=V_{in}\). Thus, \(i_{L1}\) and \(i_{L2}\) are decreasing and increasing. **Step 5 [\(t_{4}\leq t<t_{5}\)]:** Owing to \(f_{sw}<\)\(f_{r}\), \(i_{Lm}\) equals \(i_{Lr}\) at time \(t_{4}\) so that \(D_{o1}\) is reverse biased. \(i_{L1}\) and \(i_{L2}\) decrease and increase, respectively.