# Real-Time Simulator for Dynamic Systems on FPGA
## 6 Conclusions  
The work in this article proposes an embedded solution in FPGA, for real auditory simulations for dynamic systems, here called RTSDS-FPGA. A pallet comprised a main control module (MCM) and a set of auxiliary hardware modules, called DAM and SGM. A prototype was developed for a model of a longitudinal vehicle, unable to perform real-time simulations in various scenarios. The prototype was implemented using Matlab/System Generator, with the kit Virtex-6 (XC6 VLX240T) ML605, as MCM. The results obtained for all scenarios explored showed that the RTSDS-FPGA can be used as a tool for the development of real-time control systems. With the developed prototype, the RTSDS-FPGA performed well, since, for a period of 1 ms, its actions were executed at approximately 210 ns, remaining idle the rest of the time. With this analysis, it is possible to observe the simulation of the system in real time and to execute simulations with models more complex than those in the literature. On the other hand, it can be seen that the RTSDS-FPGA can also be used as a tool to accelerate simulations of systems with slow dynamics. The RTSDS-FPGA was developed with four differential equation resolution methods (Euler, improved Euler, and third- and fourth-order Runge-Kutta methods), which operate in a completely parallel way, using dynamic system reply and allowing a choice of methods, which distinguishes this implementation from presentations in the literature. Precisely for this reason, one approach utilized approximately 53% of the total structures of the development platform. Last but not least, one can make use of RTSDS-FPGA in the academic field, as a teaching tool for research and teaching, both for undergraduate and graduate levels. The primary limitation of the proposed methodology lies in the need for a high degree of customization for very specific or non-standard use cases, even with the modular design that covers a wide range of applications. This can increase development time and complexity. Therefore, while the methodology is robust for many real-time simulation tasks, it may require additional refinements to meet the specific requirements of advanced applications.  
All authors have contributed in various degrees to ensure the quality of this work (e.g., S.N.S. and M.A.C.F. conceived the idea and experiments; S.N.S. and M.A.C.F. designed and performed the experiments; S.N.S., M.A.S.d.S.G., L.M.D.d.S. and M.A.C.F. analyzed the data; S.N.S., M.A.S.d.S.G., L.M.D.d.S. and M.A.C.F. wrote the paper; M.A.C.F. coordinated the project). All authors have read and agreed to the published version of the manuscript.  
Coordenacao de Aperfeicoamento de Pessoal de Nivel Superior-Brasil (CAPES)-Finance Code 001.  
**Data Availability Statement:** No new data were created or analyzed in this study. Data sharing is not applicable to this article.  
**Acknowledgments:** The authors would like to express their gratitude to the Coordenacao de Aperfeicoamento de Pessoal de Nivel Superior (CAPES) for providing financial support.  
Figure 27: Hardware configuration for series RL circuit simulation using RTSDS-FPGA.