# Burst Channel Error Reduction Based on Interleaving for Efficient High-Speed Wireless Communication
## 6 Conclusions  
This research introduced an efficient helical interleaver and a novel FRF interleaver for OFDM systems to increase wireless communication reliability and data throughput. The proposed approach enhances the (FFT/DWT)-OFDM BER performance. The BER performance of the FFT-OFDM system was compared to that of the DWT-OFDM system for numerous wavelet families. The AWGN, multipath Rayleigh fading with exponential power delay spread and no Doppler influence, SUI-2, SUI-3, SUI-6, and vehicular A channel models have all been considered to assess the performance of the suggested approach. Finally, experimental findings indicate that higher-order \(M\)-QAM offers high data rates despite a weaker resilience to errors. The DWT-OFDM outperforms the traditional FFT-OFDM for all wavelet families. In addition, it is observed that the Haar wavelet is the best choice for DWT-OFDM implementation. Furthermore, according to the simulation results, it has been observed that the proposed FFT-OFDM system with FRF interleaving outperforms that with helical interleaving in terms of BER, as the FRF interleaver has better randomization capabilities than the helical interleaver. On the other hand, the proposed DWT-OFDM system with the FRF interleaver provides approximately the same BER performance as that of the DWT-OFDM system with the helical interleaver. As a result, our recommendation is to use the proposed FRF interleaver for the FFT-OFDM system. Finally, the proposed FRF interleaver is more complex than the helical interleaver, but the FRF interleaver can improve the throughput and energy efficiency of critical systems, where their power consumption is essential, compared with the others. The simulation results have shown that the performances of the proposed FRF and helical interleavers have noticeable improvements compared to that of the conventional (FFT/DWT)-OFDM. Finally, the proposed FRF interleaver is more complex than the helical interleaver. One possible future focus of this paper is a deep investigation of the performance of conventional interleavers compared to our proposed FRF interleaver.  
Figure 14: Total number of logic elements required for the FPGA implementation of the FRF and helical interleavers of size 128 \(\times\) 128.  
Figure 15: Total number of memory bits required for FPGA implementation of FRF and helical interleavers of size 128 \(\times\) 128.  
**Author Contributions:** Conceptualization, F.H.E.-F. and R.A.R.; methodology, F.H.E.-F. and R.A.R.; software, F.H.E.-F.; validation, F.H.E.-F. and R.A.R.; formal analysis, F.H.E.-F. and F.E.A.E.-S.; investigation, F.H.E.-F. and M.K.; resources, A.J.A. and J.S.A.; writing--original draft preparation, F.H.E.-F. and R.A.R.; writing--review and editing, F.H.E.-F., R.A.R., A.J.A. and J.S.A.; visualization, F.H.E.-F. and F.E.A.E.-S.; supervision, F.H.E.-F. and R.A.R.; project administration, F.H.E.-F.; funding acquisition, R.A.R., A.J.A., M.K. and J.S.A. All authors have read and agreed to the published version of the manuscript.  
This research was funded by the Scientific Research Deanship at the University of Ha'il, Saudi Arabia, through project number RG-20019.  
The authors declare no conflict of interest.