# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 4 Saving Power by Clock-Gating and FSM Decomposition
This idea leads to the structural diagram shown in Figure 12.  
The following sets can be obtained from Figure 12: sets of inputs \(X1\) and \(X2\) which can have common elements; sets of outputs \(Y1\) and \(Y2\) which can be disjoint; disjoint sets of IMFs \(\Phi 1\) and \(\Phi 2\); disjoint sets of state variables \(T1\) and \(T2\); sets of internal control signals (ICSs) \(SC1\) and \(SC2\). These last sets are the following: \(CS1=\{EO1,EN1,\ NS1\}\) and \(CS2=\{EO2,EN2,\ NS2\}\). Using the ICS \(EN\), FSM1 may disable both RGX2 and RG2. The signal \(EO1\) determines the required state of FSM2. The same function is executed by FSM1 using outputs \(EO2\). The signals EN1 and EN2 disable the registers of FSM2 and FSM1, respectively. Also, the signal EN1 disables the loading of inputs \(x_{l}\in X2\) into \(RGX2\). In [3], the authors show results of experiments conducted using the CAD system SIS [36] and library [82]. The results show that the \"impressive power savings correspond to larger FSMs (for example, 79.5% for the benchmark planet)\". There is no gain for small FSMs. This can be explained by adding some circuitry and two extra states. For example, around 30% of the area is added to the FSM circuit implementing the benchmark planet. Each FSM of a decomposed circuit can be treated as a superstate (SS). For example, the structural diagram from Figure 12 corresponds to the STG shown in Figure 13.  
We divided the sets \(X1\), \(X2\subseteq X\) into two subsets each. For example, the set \(X11\subseteq X1\) causes transitions inside FSM1 with the generation of outputs \(y_{n}\in Y1\). The set \(X12\subseteq X1\) causes transitions into the RESET state of FSM2. These transitions are accompanied with  
Figure 12: Structural diagram of a decomposed FSM [75]. Figure 13: State transition graph with two superstates. the generation of ICSs from set \(SC1\). Because the transitions are determined by FSM states and inputs, then it makes sense to use clock gating for both states and inputs. As shown in [70], the approach similar to [71] has two drawbacks:  
1. The decomposed network always includes only two FSMs. 2. The blocks of clock logic are synchronized, and _Clock_ pulses enter these blocks. As a result, the CL blocks consume a lot of power. In [70], an approach is proposed that has the following advantages:  
1. The decomposed FSM is represented by \(K\) submachines FSM1,..., FSM\(K\), where \(K\geq 2\). 2. The blocks of clock logic are asynchronous. Summarizing the results [70], it is possible to represent an FSM as a network including \(K\) interrelated partial FSMs. Each of them includes its own synchronization circuit of CL. The circuits \(CL_{1}-CL_{K}\) are interrelated (Figure 14). Special signals \(g_{0k}(k\in\{1,\dots,K\})\) point to the machine FSM\(k\) that should be active in the next cycle of _Clock_. Using this signal, blocks \(CL_{k}\) generate signals \(act_{k}(k\in\{1,\dots,K\})\). Only one of these signals are equal to one. This determines the particular active sub-FSM. The ABD gates help to implement the synchronization for sub-FSMs:  
\[C_{k}=act_{k}\&Clock\ (k\in\{1,\dots,K\}). \tag{13}\]  
In [71], the clock signal enters the circuits of clock logic. This is the signal with the highest switching activity among all other signals such as FSM inputs, outputs, and state variables. If the pulse _Clock_ enters the circuits of CL, then the power consumption is increased as compared with the case discussed in [70]. As shown in [70], there are three operating modes for clock logic blocks. During a transition between different sub-FSMs (hand-over mode), all CL blocks are active. In this mode, the maximum amount of power is consumed by these blocks. If \(act_{k}=0\), then the block \(CL_{k}\) is in the disable mode. It means that the power is consumed only by AND gate. The third mode is connected with enabling the block \(CL_{k}\) (\(act_{k}=1\)). The circuits of clock logic are passive; no power is consumed. Of course, switching AND gates requires some power.