## 3 Circuit Design
### Manchester-Coded FSK Modulator
* The VCO phase noise, which mainly determines the phase noise of the whole synthesizer at a frequency offset larger than the PLL loop bandwidth, has to be sufficiently lower in order not to worsen the Signal-to-Noise-Ratio (\(SNR\)) of the modulated signal. This can be evaluated as Single-Sideband to Carrier Ratio, _i.e._, as the ratio of the power in a \(1\) Hz bandwidth at an offset \(\omega_{m}\) from the fundamental angular frequency \(\omega_{0}\) and the power of the carrier, giving [31]: \[SSCR\left(\omega_{m}\right)=\frac{kT}{C}\frac{\omega_{0}}{Q}\frac{1}{\omega_{ m}^{2}}\frac{1+F}{A_{0}^{2}}\] (24) where \(F\) is the noise factor of the transconductor (\(F\cong 1\)). From behavioral simulations, the phase noise at \(1\) MHz offset from the carrier has to be lower than \(-120\) dBc/Hz to not to degrade the frequency modulated signal. * A resonant filter (at twice the oscillation frequency) connected to the source of the NMOS differential pair transistors (see Figures 10 and 11) can be added to reduce flicker noise up-conversion into phase noise, which can severely limit the VCO performance [29]. For \(I_{BIAS}=400\)\(\mu\)A, \(C\) in the \(6\)-\(11\) pF range and \(Q\cong 70\), the excess gain is approximately \(2\) and the oscillation amplitude is larger than \(2\) V, preventing the tail current generator to enter the ohmic region and avoiding a phase noise degradation. Moreover, these choices ensure that the phase noise is not an issue being better than \(1\)-\(50\) dBc/Hz at \(1\) MHz frequency offset. The VCO is followed by a cascade of a divide-by-\(2\) dynamic logic prescaler and a static modulo-\(10\) CMOS counter, which further divides the frequency by \(10\). The PLL reference is the same \(20\) MHz master clock, allowing the loop to set the oscillation frequency at \(20\) times the reference clock, _i.e._, \(400\) MHz. The PLL also includes a phase-frequency detector with a charge-pump driving an \(RC\)-\(C\) off-chip filter (see Figure 10), which sets the loop bandwidth to \(50\) kHz. Excluding the VCO, the power consumption is mainly due to the high-frequency prescaler, which draws more than \(200\)\(\mu\)A. The current consumption of the whole synthesizer is about \(700\)\(\mu\)A. The synthesizer frequency is modulated in an open-loop mode by the data at \(1.25\) MHz, _i.e._, at \(1.25\) Mbit/s rate with Manchester encoding. Thus, the loop is open for the frequency modulation since the PLL bandwidth is significantly lower than the bit-rate. This prevents the PLL to filter out the induced frequency modulation. The only purpose of the loop is to fix the central oscillation frequency in order to avoid frequency drift due to temperature and power supply variations. To limit the occupied bandwidth, a frequency deviation of about \(\pm 400\) kHz was adopted. Considering a modulation frequency of \(1.25\) MHz, this value corresponds to a modulation index of \(0.64\). The bandwidth of the transmitted signal is determined by the Carson rule [32]:  
\[BW=2\cdot(\Delta f+f_{m})\cong 3.3\text{ MHz} \tag{25}\]  
where \(\Delta f\) and \(f_{m}\) are the peak frequency deviation (\(400\) kHz) and the frequency modulation (\(1.25\) MHz), respectively.