# RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool
## 1 Introduction  
As the integration of VLSI (Very Large Scale Integrated Circuit) chips increases over time, the cost of producing chips is increasing significantly, not only in the manufacturing process but also at the design stage. In particular, the testing cost for the verification of the designed circuit during the design stage is very large due to the complexity of the circuit, high-level simulation, design changes, and repetitive testing. In terms of test costs, it is time-consuming and staff-intensive to design and run HDL (Hardware Description Language) simulations but, above all, commercial software for testing designed circuits entails a high cost per simulation. The most practical way to solve the cost problem of testing is to perform simulations using open-source HDL tools such as Icarus Verilog and Verilator, but there is a problem in developing additional features to have a verification level comparable to commercial tools. Develop costs are more expensive than paying for using commercial tools for complex reasons [1]. The hardware description language is characterized by the need for designers to use low-level languages that greatly limit design productivity. Functional validation methodologies for hardware description languages require complex learning processes to mathematically prove circuit properties and avoid error conditions. So far, many methodologies have been proposed, including advanced synthetic tools such as AutoESL and open-source tools with complex simulations, to reduce the difficulty of hardware design and apply higher levels of abstraction [2; 3]. DEVS (Discrete Event System Specification) is widely used in modeling and simulation to design, validate, and implement complex response systems. DEVS provides a robust format for system design using event-driven state-based models with explicitly defined time information. FD-DEVS(Finite-Deterministic DEVS) are based on the concept of deterministic finite automata, an extended H-DEVS (Hybrid DEVS) environment capableof simultaneously performing discrete and continuous events, and Cell-DEVS developed for the simulation of communications and networks demonstrate the potential to scale as hardware modeling and simulation tools. The DEVS format provides a format specification for a state-based system that integrates both event-based and time-based behaviors. The hierarchy within DEVS is supported by atomic model and coupling model descriptions. The atomic model specifies the behavior of each component, and the combined model specifies the interface between the component instances. DEVS-based DHMIF (DEVS-based Hardware Model Interchange Format), a DEVS-based hardware model exchange format, cannot perform simulations directly, but it has already been proven that the DEVS format is compatible with Verilog HDL or VHDL (VHSIC Hardware Description Language) [4, 5]. Simulating the RTL (Register Transfer Level) circuit using the DEVS format has the advantage of enabling simulation through a simplified form before full-scale design and simulation using commercial tools. Simulator design based on the DEVS format can also be a means of overcoming the functional limitations of open-source software. If hardware designers can extend the capabilities of simulation libraries that are not supported by open-source RTL simulation tools by replacing them with alternative software, passing input/processing/output work specifications to computer software developers can save money and time compared to developing branch versions of open-source RTL simulators. To achieve this complex purpose, there are also attempts to solve it using Python [6], the most widely used language for research and development, from the design of RTL to the provision of simulation and FPGA (Field Programmable Gate Array) tools such as PyMTL3.