# Physical Layer Latency Management Mechanisms: A Study for Millimeter-Wave Wi-Fi
## 3 Latency-Inducing Receiver Digital Baseband
### Performance Figure Derivation
#### 3.2.3 Symbol Demapper  
The described RX DBB employs one of three demapping algorithms. All of them convert a single received symbol into a sequence of log-likelihood ratio (LLR) values. These represent the probability that the corresponding bit in the symbol constellation is a one or a zero. The length of the output LLR sequences is equal to the modulation rate. The three algorithms and their performances for 16 QAM are listed in Table 3, where \(\delta^{2}\) is the noise variance, \(M\) the constellation size, and \(r\) the received symbol. The \(i\)-th constellation point where the \(k\)-th LLR is either 0 or 1 is represented by \(C_{i,0}\) or \(C_{i,1}\), respectively. The first equation represents the exact LLR calculation algorithm. Since the authors used a field-programmable gate array (FPGA) for the purpose of their study, the throughput has been increased by a factor of 3.2--the average increase in application throughput when migrating from an FPGA to an application-specific integrated circuit (ASIC) imple  
Figure 5: Task execution flow in the channel and noise estimation block. Vertical task stacking represents parallel execution. \begin{table}
\begin{tabular}{l l l l} \hline \hline
**Name** & **Throughput (\(\frac{MLLR}{s}\))** & **Demapping Algorithm** & **Ref.** \\ \hline Exact & 800 & \(\begin{array}{l}LLR[k]=ln\frac{\sum_{i=0}^{2u-1}\ exp(-\frac{1}{2\alpha^{2}} \cdot\|r-c_{i,1}\|^{2})}{\sum_{i=0}^{2u-1}\ exp(-\frac{1}{2\alpha^{2}}\cdot\|r- c_{i,0}\|^{2})}\end{array}\) & [36] \\ Approximative & 3030 & \(\begin{array}{l}LLR[k]=\frac{1}{2\alpha^{2}}\cdot[\min(\|r-c_{i,0}\|^{2})-\min (\|r-c_{i,1}\|^{2})]\end{array}\) & [37] \\  & \(\begin{array}{l}LLR[0]=\frac{1}{2\alpha^{2}}\cdot\operatorname{Re}(r)\\ LLR[1]=\frac{1}{2\alpha^{2}}\cdot(2-|\operatorname{Re}(r)|)\end{array}\) & [38] \\ Decision threshold & 6640 & \(\begin{array}{l}LLR[2]=\frac{1}{2\alpha^{2}}\cdot\operatorname{Im}(r)\\ LLR[3]=\frac{1}{2\alpha^{2}}\cdot(2-|\operatorname{Im}(r)|)\end{array}\) & [38] \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Throughput performance metrics and demapping algorithms associated with the three different demapper instances. The throughput applies to five parallel demappers, as described in the corresponding references. All throughput values and the set of demapping equations in the last row correspond to 16 QAM mapping. mentation [39]. This is the only time when the normalization factor was applied, as all other component performance figures correspond to ASIC-based designs. The difference in process nodes between the demappers was not compensated due to the lack of an explicit scaling factor. Note should be taken that the approximative demapper is implemented in 90 nm technology, and its implementation using a 65 nm process could increase transistor density [40] and decrease propagation delays [41]. Consequently, the approximative demapper latency results should be assessed with some reserve since a 65 nm implementation could increase the component's throughput. The opposite is true for the exact demapper, deriving its throughput from a 28 nm implementation. Next from top to bottom is the approximative algorithm. Although simplified, the algorithm still needs to iterate over all the constellation points for every received symbol. Lastly, the decision threshold algorithm simplifies the demapping procedure by grouping constellation points into clusters and working only on the basis of those. This makes it the fastest of the three. In the studied demapper implementations, only the throughput delay is considered since it is the main performance metric noted in [36; 37; 38]. The delay manifests itself as the time between the processing of consecutive input symbols. Consequently, a symbol rate higher than the demapper's throughput will cause symbols to start piling up at the demapper's input. This would prevent the RX DBB from processing input symbols at the standardized 1.76 Gsps rate. Therefore, the simulated RX DBB uses 5 demappers in parallel.