## 5 Modulators  
### Conventional Modulators  
The L3 MATRIX integrated transmitter includes electro-optic (E/O) modulators that must be simultaneously compact, high-speed, and ultimately low power to match the ASIC's output voltage. Moreover, the fabrication process must be kept simple and robust,  
Figure 14: The epitaxial structure of the optimized QD laser stack with a total III–V thickness of 236 nm and room temperature PL. For the InAs QDs layer thickness, ML denotes monolayers. ensuring that the design rules of a standard CMOS platform, providing commercial electronic integrated circuits (EICs), are met. For these reasons, the active modulator region is a vertical pn junction (Figure 15) that produces a larger effective index change than horizontal (lateral) ones [40]. In addition to their versatility, vertical designs are less sensitive to fabrication variations than conventional ones [41]. L3 MATRIX modulators also benefit from the high tolerance to mask alignment inaccuracies because their fabrication depends on the implantation energy rather than lithography resolution. Early vertical pn junctions were based on doped polysilicon deposition [42], which is readily available in standard CMOS processing lines. It is, however, a lossy material. More recently, a \"U-shaped\" pn junction was demonstrated [43], exhibiting high modulation efficiencies of 4.6 V.mm and 2.6 V.mm at a low voltage at a \(-\)0.5 V bias. However, its formation relies on several low-medium energy implantation steps that must be precisely aligned with respect to one another, increasing the overall cost of the process. Moreover, implantation at 0\({}^{\circ}\) tilt (instead of 7\({}^{\circ}\)) dramatically increases Boron channeling and, hence, decreases the control on the vertical positioning of the junction, which may affect the robustness of the process when the number of fabricated devices scales up. The modulator fabrication was entirely performed in the AMS CMOS foundry (Figure 6) with 248 nm DUV lithography. Most notably, the 1.2 \(\upmu\)m wide pn junction was formed with only one mask, reducing simultaneously the cost and the impact of potential alignment errors. Phosphorus (P) was implanted with an energy of 150 keV and a dose reaching \(5\times 10^{13}\) cm\({}^{-3}\) to form the n-type region. BF\({}_{3}\) (BF\({}_{2}\)+) implantation, at 100 keV energy and \(4\times 10^{13}\) cm\({}^{-3}\) dose, was used for the p-type region to benefit from its shallow implantation profile. The p++ and n++ regions were formed with a shallow 20 keV implant with a 1e15 cm\({}^{-3}\) dose. The wafer was then annealed for 10 s at 1000 \({}^{\circ}\)C in an inert argon (Ar) environment. The high-speed electrodes consist of standard CMOS stacked bi-layers of 500 nm aluminum and 150 nm TiN (anti-reflective coating) (M1 and M2 in Figure 15a,b) interconnected with tungsten (W) vias. The Metal (TiN liner, W)-semiconductor (Ti-Si) silicidation together with the heavily doped p++ and n++ regions led to very low contact resistance, making high-speed operation possible. The travelling wave electrodes design was carried out with HFSS to maximize the overlap and relative speeds of the co-propagating optical and electrical signals. Optimal ohmic contacts between the W vias and the SOI region were achieved using a \(1\times 10^{15}\) cm\({}^{-3}\) dose and a shallow 20 keV implant to form the p++ and n++ regions. The travelling wave modulators were electro-optically characterized as standalone devices in DC and AC (Figure 16) using a bit pattern generator (SHF BPG 44E) delivering a non-return-to-zero pseudo-random bit sequence (NRZ PRBS\({}^{-1}\)) of the length 231-1, with 1.6 V\({}_{\text{PP}}\), 2.3 V\({}_{\text{PP}}\) and 3.2 V\({}_{\text{PP}}\) applied in a push-pull (differential) manner. The symmetric nature of the modulators makes their operation less wavelength-dependent than their asymmetric counterparts.