# _Ku_-Band CMOS Power Amplifier with Three-Stack Power Stage to Enhance Output Power and Efficiency
## 4 Design of the Proposed Power Amplifier  
In this work, we designed the power amplifier operating in the \(Ku\)-band using a 65-nm RF CMOS process that provides nine metal layers to verify the feasibility of the proposed power amplifier structure. Figure 3 shows the designed power amplifier's schematic. The input and output matching networks were completed using transformers and capacitors serving as Balun. All resistors used the same value of 5.5 k\(\Omega\).  
The designed power amplifier's driver stage has a common-source structure, and a neutralization capacitor was applied between a gate and a drain of the differential structure to ensure the stability of the power amplifier. Since the driver stage has a common-source structure, the power supply voltage was set to 1.0 V in consideration of the breakdown voltage of the transistor.  
In this study, the power stage was designed in a stack structure to ensure high output power. The number of transistors forming the stack structure depends on the operating frequency and the target output power. In order to obtain an output power of at least 20 dBm in the \(Ku\)-band, a stack structure was formed of three transistors, and a matching network, including a resistor and a capacitor, was connected to the gate of the stacked transistor so that voltage drops in each transistor were the same. Because the power stage has a stacked structure and voltages are divided and applied to three transistors, a high-power voltage of 2.6 V was used to facilitate and ensure a high output power.  
Figure 4 shows the load-pull results in the power stage. As a result of the load-pull simulation, at an operating frequency of 15 GHz, the maximum output power is 24.5 dBm, and the maximum PAE is 40.4%. For power matching, the output matching network was composed of a transformer and an additional MIM capacitor. As shown in Figure 4, the input impedance of the output matching network at an operating frequency of 15 GHz is designed to be located between the maximum output power and the maximum PAE points. In the load-pull simulation, the output power and PAE contour lines have an interval of 0.5 dB and 2%, respectively. Therefore, assuming that there is no power loss in the matching network under the selected load impedance condition, as can be observed in Figure 4, the output power and PAE are higher than 24.0 dBm and 38.4%, respectively.  
Figure 5 shows the simulation results of the S-parameters. The power amplifier was designed to have the highest gain at an operating frequency of 15 GHz. The output matching network of the power amplifier was designed with the power matching technique. Figure 6 shows the simulation results of the power gain and PAE depending on the output power in slow, typical, and fast corners. A corner simulation was performed to design the power amplifier optimized for a typical corner. Figure 7 shows the simulation results of the power gain and PAE depending on the output power at operating temperatures \(-\)20 \({}^{\circ}\)C, 25 \({}^{\circ}\)C, and 80 \({}^{\circ}\)C. As can be observed in Figure 7, Psat and PAE show similar results depending on the temperature.  
Figure 4: Load–pull simulation results.  
Figure 3: Schematic of designed power amplifier.  
Figure 5: Simulation results: S-parameters.  
Figure 6: Simulation results: gain and PAE according to output power in slow, typical, and fast corners.  
Figure 7: Simulation results: gain and PAE according to output power at operating temperatures \(-20\)\({}^{\circ}\)C, \(25\)\({}^{\circ}\)C, and \(80\)\({}^{\circ}\)C.  
Figure 8 shows the simulated current at the driver and power stages at an operating frequency of 15 GHz. Figure 9 shows simulated saturation power (P\({}_{\rm sat}\)), gain, P1 dB, and PAE according to the frequency at an operating temperature of 25 \({}^{\circ}\)C. As can be observed in Figure 9, the power amplifier was optimized at an operating frequency of 15 GHz.