# Balancing the Leakage Currents in Nanometer CMOS Logic--A Challenging Goal
## 4 Our New Strategy  
In this section, we introduce our new approach, called _improved Balanced Static Power Logic (iBSPL)_. We made sure to avoid the design issues of BSPL which we have pointed out in the previous section. In particular, we have taken care that all our developed cells produce balanced rise and fall times and ensured that all transistors follow the typical bulk connections (PMOS to VDD, NMOS to GND). Furthermore, instead of using the pass-transistor XOR logic from [27] we have based our new XOR cell on a complementary gate that is commonly used in standard cells (The 12-transistor design is used for example by TSMC and ON Semiconductor (formerly AMI) as shown here: [[https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/](https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/)]([https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/](https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/)), accessed date 25 July 2021). Our approach essentially works like this. To convert a standard CMOS logic cell to its leakage-balanced iBSPL version we first identify which combinations of input signals cause a larger and which cause a smaller static power consumption. Then, by systematically adding always-off transistors to carefully chosen input, output or intermediate signals, we raise the static leakage caused by the input combinations which originally resulted in a smaller leakage current to the higher levels. We can exploit the HSPICE optimization feature to determine the optimal width of the added transistors so that the manual effort is comparably low. By following this procedure, we achieve logic gates whose static power \begin{table}
\begin{tabular}{l l l l l} \hline
**Transistor State** & **AB = 00** & **AB = 01** & **AB = 10** & **AB = 11** \\ \hline \multirow{2}{*}{off + not bridged} & 3 \(\times\) PMOS & 3 \(\times\) PMOS & 3 \(\times\) PMOS & 3 \(\times\) PMOS \\  & 1 \(\times\) NMOS & 1 \(\times\) NMOS & 1 \(\times\) NMOS & 1 \(\times\) NMOS \\ \multirow{2}{*}{off + bridged} & 2 \(\times\) NMOS & 1 \(\times\) NMOS & 2 \(\times\) NMOS & 3 \(\times\) PMOS \\  & & 2 \(\times\) PMOS & 1 \(\times\) PMOS & \\ \multirow{2}{*}{on} & 3 \(\times\) PMOS & 1 \(\times\) NMOS & 2 \(\times\) PMOS & 2 \(\times\) NMOS \\  & & 1 \(\times\) PMOS & & \\ \hline \end{tabular}
\end{table} 
Table 1: Transistor states in a BSPL NAND gate for different inputs. consumption is very close to constant. Of course, the approach increases the average static power consumption of the gates. However, we believe that this is the best option to keep the original logic function and the performance of the gate intact (as much as possible) while providing additional security against SPSCA attacks. Figure 7 shows all four possible biasing states of PMOS and NMOS transistors which ensure that they are always off, but also cause a leakage current and have the standard bulk connections necessary to be included in a common standard cell (PMOS to VDD, NMOS to GND). We call these transistors _Tiny Consuming Blocks (TCBs)_ in the following and use them to balance the static power consumption of CMOS logic gates. We have listed the leakage currents caused by each of the TCBs in Table 2. Those static currents are consumed when the TCBs are instantiated as shown in Figure 7 with minimum width and height in 40 nm and 65 nm CMOS technology respectively. By increasing their width, we can adapt the leakage current of each of those building blocks liberally. In the following we explain the procedure to convert a standard CMOS logic gate to its leakage-balanced iBSPL version step by step using the NAND gate as an example. Please note that during the explanation of the design procedure we denote the leakage current of a logic gate for a certain input combination \(AB\) by \(I_{L_{AB}}\). For example, if input \(AB=00\) is given, the corresponding leakage current is denoted by \(I_{L_{00}}\).