## 2 Architecture and Operation of Proposed RO PUF  
Figure 1 illustrates the architecture of the proposed 9-stage RO PUF. It basically consists of one LFSR counter, one reconfigurable current starved RO and one bidirectional counter. The key component is the reconfigurable current starved RO. Its oscillation frequency is determined by the delay \(t_{d}\) of its current starved inverter stage. Here \(t_{d}\) is given as:  
\[t_{d}=\frac{C_{0}V_{dd}}{i_{D}} \tag{1}\]  
where \(C_{0}\) is the load capacitance, \(i_{D}\) is the average charging/discharging current and \(V_{dd}\) is the power supply voltage. The key component in the proposed RO PUF is the MUX based current starved RO with reconfigurability. The delay cell in the RO is the current starved inverter. As shown in Figure 2, two additional bias transistors are added into the regular inverter to realize the current starved inverter. In the current starved inverter, the output capacitance is charged/discharged by the maximum drain current \(I_{D}\) of the pull-up/pull-down transistor initially, which is decreased during the transition. Without considering the leakage and short-circuit current, the average current \(i_{D}\) is equal to \(\eta I_{D}\), where the fraction \(\eta\) is fixed for a given device. The current starved inverter can be made to work in the sub-threshold region by biasing the voltages \(V_{p}\) and \(V_{n}\). The maximum current \(I_{D}\) is formulated by [13]:  
\[I_{D}=\mu C_{OX}\frac{W}{L}(\frac{\kappa_{B}T}{q})^{2}(n-1)e^{\frac{q(V_{GS}-V_ {p})}{\kappa_{B}T}}(1-e^{-\frac{qV_{D}}{\kappa_{B}T}}) \tag{2}\]  
\[n=\frac{1+(C_{S}+C_{tt})}{C_{OX}} \tag{3}\]  
where \(\kappa_{B}\) is the Boltzmann constant; \(C_{S}\), \(C_{tt}\) and \(C_{ox}\) are the capacitances associated with the semiconductor, fast surface states and gate oxide, respectively. From (2), the current is controlled by the \(V_{GS}\) of each transistor. Therefore, the power and oscillation frequency of the RO can be tuned by \(V_{p}\) and \(V_{n}\). It should be noted that two multiplexors are placed in each inverter stage: one at the gate outputs, the other one at the gate inputs. The multiplexors are realized with transmission gates to reduce their delay and transistor count as shown in Figure 3. It is difficult to model the temperature dependency of the multiplexors as the transistors can operate in several regions [14]. What is more  
Figure 1: Architecture of the proposed ring oscillator (RO) PUF. Figure 2: Schematics of (**a**) regular inverter and (**b**) current starved inverter. feasible is to increase their transistors' width to make their contribution to the timing variation of the RO negligible relative to the inverters. Each response bit of this PUF is produced by comparing two randomly selected ROs' frequencies. The operation of the proposed PUF is explained as follows. The LFSR counter is firstly fed with an 8-bit challenge \(C\) through \(Serial\_In\) port by setting the signal _Mode_ high. \(EN\) in the RO is set to low to disable the oscillation. After \(C^{\prime}\) from the LFSR counter settles down, \(EN\) is set to high. Then a rising edge of \(Rst\) is applied to reset the bidirectional counter, which can record the RO's output frequency. Suppose the RO selected by \(C\) is \(RO_{A}\). Its oscillation frequency \(f_{A}\) is measured by the bidirectional counter with \(Up/\overline{down}\) equal to high for a specific time of \(t\). Similarly, another challenge \(C^{\prime}\) is generated by shifting \(C\) in the LFSR counter with \(N_{clk}\) (\(N_{clk}<2^{8}\)) cycles. The frequency \(f_{B}\) of the new RO \(RO_{B}\) is recorded by the bidirectional counter with \(Up/\overline{down}\) set to low for the time of \(t\). Finally, the recorded value in the bidirectional counter represents the frequency difference of the RO pair (i.e. \(RO_{A}\) and \(RO_{B}\)). The most significant bit (MSB) of the bidirectional counter is used as the PUF's output bit.