## 1 Introduction  
As the 5G system demands broadband and high data rates, the system configuration becomes more complicated. A typical 5G system utilizes a multi-antenna MIMO structure for beamforming operation, and thus, it requires analog/digital control circuits to change the RF (radio frequency) gains and phases of multiple channels by compensating the performances with temperature and corner variations [1; 2; 3]. In general, it can be achieved by dynamic and static digital control circuits, respectively. The RF signal on a real-time basis is controllable through the dynamic digital control. Static case can help to find an optimal value through tuning work to increase the efficiency of the system. They have been implemented with advanced CMOS technology to enable fast operation with low power consumption that is strongly required especially for 5G systems application. Recently, it reaches the boundary of minimum utilized structure limitation, although the physical feature size scaling of CMOS transistor has been aggressively reduced. And the fabrication cost is still one of the critical problems. For this reason, many mm-wave circuits and systems are still being developed using sub-micron processes integrated with digital, analog, and RF block, which have cost advantages. The 28 nm CMOS technology is a state-of-the-art process based on planar type MOSFET, and widely used in recent 5G/mm-wave systems because of the high transition frequency (\(F_{t}\)) and the low minimum noise figure (\(NF_{min}\)) performances. And a lot of researches is still being studied to optimize the CMOS process itself [1; 2; 3; 4; 5; 6; 7; 8; 9; 10; 11; 12; 13; 14; 15; 16; 17; 18]. The previously reported papers, reducing circuit leakage by implementing high-K technology through a single-metal-gate fabrication for low power [4], power amplifier with a stacked technique with triple-well structures to overcome low voltage and transconductance, which are limited in circuit design [5], the bias optimization technique of transistor to overcome the limit of frequency maximum (\(F_{max}\)) [6], and low-noise amplifier with good performance using reduced noise figure of CMOS process [7], were reported. In addition, the analog to digital converter (ADC) and digital to analog converter (DAC) circuit, which must operate digitizing signals with GHz-wide bands, must be designed by efficient structure or optimized circuit to avoid the increase in current consumption [8]. In digital control circuits for 5G applications, the power saving technique by sharing the common blocks according to operation mode is important. In more detail, in static digital control, a main design point is to reduce dc-current consumption using a simple control method to avoid massive analog connections [9]. The series-to-parallel (S\({}^{2}\)P) converter is as digital circuit that feed the input data serially, and read the output in parallel fashion. Thus, it has the advantage of being easily controlled by a simple circuit and leads to provide specific optimum condition to circuit [10]. For this reason, it is widely used in low-speed peripheral integrated circuits for data communications from a USB or a STAT hard disk driver including processors or microcontrollers [10]. Furthermore, it can also adapt to digitally controlled RFICs for finding optimum conditions, for examples variable capacitor bank to compensate the bandwidth according to process-voltage-temperature (PVT) variation in attenuation circuit of mm-wave systems, the fine-tuning circuit of voltage gain amplifier, phase shifter to reduce the mismatch effects, and transmitter and receiver module (TRM) control for array block [11; 12; 13; 14; 15]. In this paper, we firstly showed the successful demonstration of a series-to-parallel (S\({}^{2}\)P) converter circuit design using 28 nm CMOS process for 5G system that was capable of 160-bit control. To reduce power consumption, 160-bit consists of 20 bytes and each byte is directly assigned 20 address A [19:0] in our design.