## 6 Results  
Currently, most of the training of neural network models is carried out on CPU or GPU. This design uses a hardware approach to train a neural network model. The overall performance of the three types of platforms is shown in Table 4, where the network training and inference times are measured using the time function provided by each hardware platform during the actual operation. It does not include image preprocessing and the import time. The vertical comparison shows that the proposed LeNet-2.2 network structure is much better than the proposed LeNet-3.3 network structure in terms of training efficiency, and the pooling layer significantly reduces the network parameters to improve the training efficiency. Therefore, the performance of each platform running the LeNet-2.2 network is mainly compared next. A horizontal comparison shows that the MPSoC used in this design does not have an advantage in terms of price, but the average power consumption of this device is only 3.02 W, which is 6.86% CPU power consumption and 4.03% GPU power consumption. Moreover, the compact size of MPSoC devices is more in line with the requirements of lightweight deployment. The training time for a single image in the PL of the MPSoC is only 78.03% of the training time of the GTX1050 and 55.98% of the training time of the Intel i5-4300U. Therefore, the HA-SoC-based PL implementation is not less efficient than the GPU for training neural network models, but it has the disadvantage that it sacrifices flexibility in algorithm deployment and has a slightly longer development cycle. After validation on 1000 images on the test set, the inference time of the LeNet-2.22 model on \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multicolumn{2}{c}{**Equipment**} & **CPU** & **GPU** & **MPSoC** \\ \hline \multirow{4}{*}{\begin{tabular}{c} Overview \\ Information \\ \end{tabular} } & Type and & \multirow{2}{*}{Intel i5-4300U} & \multirow{2}{*}{GTX1050} & \
\begin{tabular}{c} ZYNQ \\ UltraScale + \\ MPSoC (PL) \\ \end{tabular} \\ \cline{2-2} \cline{5-5}  & Selling price & X & 929 \% & 2600 \% \\ \cline{2-5}  & Working & \multirow{2}{*}{2.5 GHz} & \multirow{2}{*}{1455 MHz} & \multirow{2}{*}{100 MHz} \\  & frequency & & & \\ \hline \multirow{4}{*}{
\begin{tabular}{c} LeNet-3.3 \\ \end{tabular} } & Average power & \multirow{2}{*}{44 W} & \multirow{2}{*}{75 W} & \multirow{2}{*}{3.22 W} \\  & consumption & & & \\ \cline{1-1} \cline{2-2} \cline{5-5}  & Training time/image & & & \\ \cline{1-1} \cline{2-2} \cline{5-5}  & Inference time/image & & & \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Overall performance comparison. ZYNQ UltraScale+ MPSoC is 0.65 ms for a single frame image. On the Intel i5-4300U CPU and GTX1050 GPU, the processing time for a single frame is 2.01 ms and 0.78 ms, respectively, and the average inference speed is 3.09 and 1.2 times. As shown in Table 5, the PL implementation trained in HA SoC converges faster, which is consistent with the GPU and CPU effects. As shown in Figure 12, the final accelerator IP kernel achieves an average recognition accuracy of 95.697% on the empirical set of MNIST handwritten digits, which is consistent with the performance of this model on a computer. The following screenshots show some of the experimental results:  
Figure 12: Recognition results of the accelerator on the MNIST data set.