## 1 Introduction  
Power dissipation in a digital CMOS chip is given as:  
\[P=N_{a}\left(aCV_{DD}^{2}f+I_{leak,a}V_{DD}\right)+N_{i}I_{leak,i}V_{DD} \tag{1}\]  
where \(N_{a}\) and \(N_{i}\) are the total number of gates in active and asleep logic blocks respectively, \(a\) is the activity factor, \(C\) is the average capacitance of the net associated with the output of a gate, \(f\) is the operation frequency, and \(V_{DD}\) is the supply voltage. \(I_{leak,a}\) and \(I_{leak,i}\) are the leakage currents per gate of active and asleep logic blocks respectively. For the active logic blocks, the first term within brackets is the dynamic power due to the capacitances charging and discharging and the second term is the leakage power of all the cells connected to the power supply. The asleep logic blocks are disconnected from the power supply to substantially reduce their leakage currents \(I_{leak,i}\), as compared to \(I_{leak,a}\).  
Typically, the chip is designed to accommodate the peak computation requirements, even under the worst case process and temperature conditions. The peak computation throughput in combination with the architecture (the types of macro blocks like processing cores and memories and their interconnection scheme) and the micro-architecture (cycle level pipelining and parallelism) determines the peak operating frequency, \(f\). The physical design of the chip with actual gate choices, their placement and wiring layout, is done to meet the frequency \(f\) at worst case process and temperature conditions. This finally determines the total number of gates (and memory cells), the switching capacitances (from gate sizes and wiring parasitics), the leakage currents and the supply voltage \(V_{DD}\) in Equation 1. The activity factor, \(a\), is largely determined by the situation at run-time, \(i.e.\), on the kinds of computation being done and the actual data that is being worked on.  
There has been intense research over the past two decades on various aspects of compilation and synthesis for low power [1]. Many architectural optimizations like re-configurable architectures, custom ASIC approaches, programmable multi-cores, \(etc.\) have been explored. Micro-architectural techniques like parallelism and pipelining, power and clock gating have become commonplace now. Circuit techniques for low voltage operation, standby current reduction, optimal gate sizing have also been explored and are available for use by a designer [2].  
Most of these optimization techniques are static techniques which are applied during design time. In the recent past, dynamic power management techniques have emerged, where the power consumption is continuously adjusted during run time of the system [3, 4]. This is motivated by the fact that since the chip is designed to meet the most demanding application throughput requirements under worst case operating condition, it leads to an excess margin or wastage of power under typical operating conditions. In the next section, we will review some commonly used techniques like dynamic power switching and dynamic and adaptive voltage scaling. We will also describe some recent research in dynamic voltage and threshold scaling. We will then discuss techniques which have been recently explored to adapt to varying computation needs via adapting the hardware parallelism or changing the number of operations performed dynamically.