## 4 Hardware Security
### Physical Unclonable Functions (PUFs)  
Authentication, authorization, and privacy are three essential requirements in an IoT network. Physical Unclonable Functions (PUFs) exploit the inherent randomness created during manufacturing to offer a unique \"digital fingerprint\" for authentication and secret key storage. Each chip has its fingerprint like those in humans, which is created during the fabrication processes. PUF circuits are triggered by a sequence of input bits known as challenges (\(C_{x}\)) and respond with a sequence of output bits called responses (\(R_{x}\)). No two chips generate identical responses for a common challenge. The combination of an input challenge and its corresponding response is known as a challenge-response pair (CRP) [212]. The process variations during the manufacturing processes of the PUF circuit have a unique silicon fingerprint. Thus, even common input challenges as shown in Figure 16 result in unique challenge-response pairs (CRPs) for the edge devices [213]. PUF carries out an authentication process for an unknown device in two stages, i.e., enrollment and verification. The PUF module receives the challenge bits from the server and the corresponding response bits are stored back into the server by the PUF circuit during the authentication phase. During the verification stage, the server sends the previously stored challenge bits to the IoT device, and the PUF circuit embedded into the device generates response bits. The generated response bits are compared and matched with the CRP look-up table entries for the authentication of the IoT devices. Also, the response bits are used to extract the secret key to ensure confidentiality during data exchanges [214]. Figure 16: Uniqueness of challenge–response pair (CRP) [215]. Figure 15: Hardware security threats and countermeasures [210; 211]. PUFs are classified based on their security capabilities, fabrication methodology, physical characteristics, and delay characteristics. Many researchers have presented a taxonomy of PUF under categories like fabrication process and security as illustrated in Figure 17. PUFs are categorized into two types, strong PUFs (SPUFs) and weak PUFs (WPUFs), depending on the number of CRPs. The number of CRPs in SPUFs scales exponentially and linearly in WPUFs with increasing PUF cells. WPUFs are used in storing secret keys or serve as a seed in a random sequence generator [216], while SPUFs can be used for authentication, ID, or key generation [217]. Arbiter PUFs fall under SPUFs, whereas SRAM PUF and butterfly PUF are WPUFs [218]. However, the responses of SPUFs are inherently correlated and highly susceptible to ML attacks, including modeling techniques like Logistic Regression (LR), support vector machines (SVMs), artificial neural networks (ANNs), and ANN-based approximation attacks [219]. The variations in the manufacturing process result in silicon and non-silicon PUF types. The fundamental physical properties of silicon PUFs give rise to three types: analog electronic PUFs, memory-based PUFs, and delay-based PUFs [220]. Non-silicon PUFs create unique characteristics by extracting keys from light beams or lasers, as well as magnetic field strength and radio frequencies, while avoiding the use of electronic signals [221; 222]. An arbiter PUF is a delay-based strong PUF that belongs to silicon PUFs. Figure 18 illustrates an N-stage arbiter PUF made up of n pairs of 2-to-1 multiplexers, with each pair in a stage controlled by identical challenge bits. The output, referred to as the \"Response\", is determined by the differences in path delays. In a standard N-stage arbiter PUF, a rising edge signal travels through one of the \(2^{N}\) possible paths, guided by the N-bit \"Challenge\" inputs. An arbiter generates the final response, typically implemented with a D-latch, which decides the output based on the first signal to arrive [223; 224]. Optical PUFs have an  
Figure 17: Classification of PUFs.