An Optimized Core Distribution Adaptive Topology Reconfiguration Algorithm for NoC-Based Embedded Systems  
[PERSON]  
1 College of Computer and Control Engineering, Northeast Forestry University, Harbin 150040, China; [EMAIL_ADDRESS] (B.H. ); neftaxl@enfue. processor cores, storage units, and other functional modules. NoC offers superior communication bandwidth, reduced latency, and enhanced scalability, thereby markedly improving the system's overall performance compared to the traditional bus-sharing mechanism [6; 7]. Concurrently, the rapid evolution of integrated circuit processes and modern computer technology has positioned multicore processors as a pivotal trend in computer architecture. These processors enhance computational power and parallel processing efficiency by consolidating multiple processing cores onto a single chip [8; 9]. However, the increasing number of cores complicates inter-core communication and data exchange, exacerbating the challenge of core failures within the NoC--a critical component of inter-core data exchange. Core failures can severely degrade system performance and stability, making the effective management and repair of such failures a focal point of current research. To address this challenge, researchers have introduced a range of core-level fault-tolerant techniques and algorithms, with topology reconfiguration identified as a pivotal strategy [10; 11]. Topological reconfiguration refers to the dynamic modification of interconnects and computational resources within a network-on-chip (NoC) architecture to maintain functionality under faulty conditions. This process involves rerouting data paths, reallocating processing elements (PEs), or adjusting network hierarchies to circumvent both core-level failures (e.g., malfunctioning PEs or memory units) and link-level failures (e.g., broken interconnects or routing channels) [12]. Faults in NoC systems may manifest as permanent (irreversible hardware defects) or transient (temporary disturbances caused by electromagnetic interference or voltage fluctuations) [12]. Notably, the definition of \"fault\" remains context-dependent: while some studies refer to deadlocks and starvation as faults [13; 14], some studies use stricter definitions. Fault tolerance mechanisms extend beyond topological reconfiguration, operating concurrently at three levels:  
1. Routing Algorithms: Adaptive protocols such as self-organizing and neighbor-aware routing [12] dynamically bypass faulty nodes/links, while goal-oriented classifications optimize path selection under degraded conditions [15];
2. Coordinate Systems: Circulant virtual coordinate frameworks decouple logical addressing from physical failures, enabling resilient rerouting independent of defective components [16];
3. Topology Design: Architectural redundancy through spare cores or reconfigurable interconnects preemptively mitigates fault propagation [17]. A holistic fault tolerance strategy must integrate these complementary approaches to address the heterogeneous nature of NoC failures, balancing latency, energy overhead, and hardware complexity. Core-level redundancy enhances system stability and performance by integrating spare cores into the NoC, allowing failed cores to be replaced seamlessly. Widely adopted in the industry, this approach has also become a prominent focus of research in NoC fault tolerance. Meanwhile, topology reconfiguration algorithms utilize core-level redundancy to adapt the physical topology, effectively mitigating the core failure issue in NoCs and ensuring the continued functionality of NoC systems [18]. Network-on-chip (NoC) architectures employ diverse topologies to optimize performance and scalability. Torus topologies, characterized by circular interconnects, minimize wiring complexity but exhibit constrained bisection bandwidth, limiting scalability in large-scale systems [19].