## 2 Multi-Chip Interconnection Topology Design
### The Inter-Chip Wireless Communication Topology  
To alleviate the limitations of traditional inter-chip interconnects, WIs need to be deployed in the multicore chips to realize the inter-chip wireless interconnects. Deployment of the WIs in a wireless multicore multi-chip system is performed by answering two major questions namely, what are the appropriate locations of the WIs and what is an appropriate number of WIs for optimum performance? In the context of intra-chip WiNoCs, several approaches have been taken to deploy WIs optimally. Two-step nested optimization approaches were adopted in [39] where, in the first step, the location of the WIs were optimized for a varying number of WIs by using heuristics such as Simulated Annealing to optimize the average hop-count between cores in the NoC. In the second step, the throughput of each configuration corresponding to the specific number of WIs with optimal location was compared to choose the best performing configuration. Alternatively, optimizing Minimum Average Distance (MAD) of the WiNoCs to achieve optimal WI deployment was proposed in [40]. A Voltage-frequency Island (VFI)-aware wireless NoC design is proposed in [41]. In [42] a framework for using Machine Learning to deploy WIs in the intra-chip NoC is envisioned. The key idea is to deploy the WIs in the chips in the multi-chip system in such a way that we achieve wireless deployment density that avoids long multi-hop paths between the internal cores and the WIs. For this purpose, we define the _wireless density_ as the number of cores within each multicore chip that are serviced by a single WI. However, the exact WI deployment density is a function of various factors. One of the major factors is the choice of the physical layer and associated Medium Access Control (MAC) layer. For example, if non-interfering channels are possible by MAC mechanisms such as Frequency Division Multiple Access (FDMA) on separate non-interfering channels then it may be suitable to deploy a WI density to fully utilize all the channels possible using the specific physical layer technology. However, if a single frequency channel is shared among the WIs through MACs such as Time Division Multiple Access (TDMA) or Code Division Multiple Access (CDMA) then the WI density needs to be optimized. The optimization metric can be a metric of interest such as throughput, latency, or energy consumption. This optimization is necessary as a higher WI density will improve the connectivity of the fabric, which is expected to improve the performance. However, it will reduce the access time or share of the bandwidth for each WI due to more WIs sharing the channel. Further discussion on the dependence of the performance on the MAC and physical layers can be found later in Section 4.2. In case of mm-wave wireless inter-chip interconnects, the shared mm-wave physical layer can use a form of TDMA to obtain access to the shared wireless channel. Therefore, the WI density needs to be optimized such that each WI has a fair share of the channel access while providing a low average diameter or average hop-count between communicating cores. Figure 3,which shows the peak achievable bandwidth and average packet energy as the WI density increases in a homogeneous 16-chip multi-chip system with each chip having 16 cores connected in a regular mesh topology. The intra-chip packet transfers occur through the intra-chip mesh wireline links whereas, the inter-chip data transfer utilizes the inter-chip mm-wave wireless links. The simulations for the optimization are performed considering both the intra-chip data transfer latency from the cores to the WIs as well as the latency between the WIs for the inter-chip transfer. The details of obtaining these models are described when discussing the simulation methodology in Section 5. The characteristics of the wired links are modeled from global wire characteristics [21] whereas the mm-wave inter-chip are adopted from [11] in 65 nm technology node.