## 5 FPGA Implementation
### Architecture Description  
Figures 12 and 13 show the architectures for Modes 1 and 2, respectively. Both architectures contain two channels, with each composed of:  
1. Section A: This section contains the arithmetic operations.
2. Section B: This section controls the operations in Section A to synchronize the pipeline operations.  
The design of the architecture consists of three blocks:  
1. The trigonometric base.
2. Linear combination of the elements of the base.
3. Control module.  
Trigonometric base: The counterX module performs the following three fundamental actions through its four least-significant bits:  
1. Acts as an 8-bit selector control in the 16-to-1 multiplexer.
2. Increments the consecutive value from 1 to 16 for the resolution.
3. Synchronizes the addressing and reading of the ROM memory.  
To evaluate the functions \(cos(\theta)\) and \(sin(\theta)\) and address the ROM memory, a latency of two cycles is used. This maintains synchronization between the DDS module and the ROM memories.  
Linear combination of the trigonometric base: The following latencies are required for different operations:  
1. A two-cycle latency for the DDS module to reflect the sine and cosine values on the data bus and for the ROM memory module to reflect the coefficients simultaneously on the data bus. Both modules work in parallel.
2. A one-cycle latency for each operation (product and sum). These operations are performed in series.
3. A one-cycle latency to store the result in the accumulator.
4. A latency of 16 cycles to obtain \(g(\theta)\).  
Thus, a new value of \(g(\theta)\) is calculated every 16 cycles. With the main clock of the used FPGA operating at 100 MHz, each point in the partition has an output frequency of 6.25 MHz.  
Construction of the control section: The control section, shown in Section B of Figures 12 and 13, corresponds to the synchronization of the algorithm. Its design allows for efficient use of throughput, which provides the amount of data processed in each clock cycle. The pipeline plays a crucial role in this section, as input phase-generation data must be synchronized to get output data, which correspond to new values of \(g(\theta)\). Output data are generated in this form, which must be aligned. The processing stages of the control section must be applied in each clock cycle.  
The control section is utilized to manipulate phase shifts of the main clock to ensure overall synchronization of the architecture. The design operates using two clock signals generated by the digital clock manager block. The signal _sys_clk_ is used for constructing both the _trigonometric base_ and the _linear combinations of the trigonometric base_ sections. To maintain synchronizations of the accumulator and shift register elements, _ssys_clk2_ must be twice as fast as _ssys_clk_. The multiplexer array _ssys_clk_2 serves as a control element for resetting the accumulator content, clock signal, and bypass signal. The bypass signal allows for passing on sum results to shift the register, which results in obtaining the first phase sum.  
We developed two architectures, labeled Mode 1 and Mode 2, which are identical in the case of a single channel. For multiple channels, the Mode 2 architecture takes advantage of the characteristics of the algorithm to reduce hardware consumption. This reduction can be observed in Section A of Figure 13, where the generation of the functions \(\sin kx\) and \(\cos kx\), where \(k=1,2,\dots,\) is shared across different channels. The control module, shown in Section B, is shared by both architectures. The Mode 1 architecture allows for operation at different speeds, which is beneficial when working with either fast or slow signals. The Mode 2 architecture reduces resource consumption by exploiting the characteristics of the source identification algorithm.