# Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions
## 3 Device Characteristics
Moreover, the p-TFET shows higher on current I\({}_{\text{on}}\) than n-TFET, corresponding to an I\({}_{\text{on}}\) of 2.41 mA/\(\upmu\)m for p-TFET and 0.78 mA/\(\upmu\)m for n-TFET respectively, at V\({}_{\text{ds}}\) = V\({}_{\text{on}}\) = V\({}_{\text{g}}\) - V\({}_{\text{off}}\) = \(-\)0.5 V for an I\({}_{\text{off}}\) = 1 nA/\(\upmu\)m. The reason that n-TFETs show lower current could be due to the broader tunneling junction caused by faster B diffusion. For further analysis, Figure 4c,d shows the corresponding output characteristics I\({}_{\text{d}}\)-V\({}_{\text{ds}}\) for p- and n-TFET. The p-TFET shows very good current saturation and more importantly a linear onset. On the other hand, the n-TFET still shows a super-linear onset. Due to the higher diffusion coefficient of boron in silicon in comparison to phosphorus, annealing at 550 \({}^{\circ}\)C for 10 s is still not optimal for n-TFETs. Thus, Set 3 of TFETs was fabricated with the aim to optimize the super-linear onset of n-TFET. In this case, 1 \(\times\) 10\({}^{15}\) cm\({}^{-2}\) P\({}^{+}\) ions at 3 keV and 1 \(\times\) 10\({}^{15}\) cm\({}^{-2}\) B\({}^{+}\) ions at 0.8 keV both without tilt (in normal direction) were implanted for source and drain, respectively. The dopants were activated at 500 \({}^{\circ}\)C for 10 s. This combination of implantation tilt, energy, and activation were chosen to achieve steeper boron junctions. Figure 5a,b shows the transfer and output characteristics of the  
Figure 4: Measurement results of Set 2 devices: transfer characteristics I\({}_{\text{d}}\)-V\({}_{\text{g}}\) for p-TFET (**a**), and n-TFET (**b**); Output characteristics I\({}_{\text{d}}\)-V\({}_{\text{ds}}\) for the corresponding devices (**c**,**d**). The p-TFET device shows a linear onset, indicating higher concentration of the n\({}^{+}\)/channel junction. n-TFET device. The output characteristics show very good linear behavior by increasing \(\rm V_{ds}\) as well as excellent current saturation. The latter is a key performance parameter for analog applications, for example, a current mirror. Moreover, the on current was also improved compared to the Set 2 devices, showing \(\rm I_{on}=15~{}\mu A/\mu m\) at \(\rm V_{ov}=V_{gs}-V_{off}=0.5\) V with an \(\rm I_{off}=1~{}nA/\mu m\). The average SS was also improved to \(76~{}mV/dec\) over 4 orders of drain current \(\rm I_{d}\). The minimum SS is still above \(60~{}mV/dec\), which could be attributed to the undesired effect of trap-assisted tunneling (TAT) caused by interface traps [14; 15]. Figure 5c presents the \(\rm I_{d}\)-\(\rm V_{gs}\) characteristics for the p-i-n diode forward biased with various \(\rm V_{d}\), as illustrated in the inset. The curves show typical forward p-i-n diode behavior--much higher currents than TFET and the current decreases with decreasing absolute \(\rm V_{d}\). This also provides evidence of the TFET operations for the results shown in Figure 5a,b. Table 1 summarizes the fabrication parameters and the device performance. Figure 5: Measurement results of Set 3 devices: (**a**) Transfer characteristics \(\rm I_{d}\)-\(\rm V_{g}\) of the optimized n-TFET, (**b**) corresponding output characteristics \(\rm I_{d}\)-\(\rm V_{ds}\) of the fabricated device showing good saturation and linear onset. The device shows very high on-currents of \(15~{}\mu A/\mu m\) at \(\rm V_{dd}=0.5\) V. (**c**) Forward biased \(\rm I_{d}\)-\(\rm V_{gs}\) characteristics of the p-i-n diode, showing typical forward I-V curves for the diode.