## 1 Introduction  
In the last few years, it is hard for the performance of CPU to get a bigger boost with IC transistor integration density approaching threshold value. Compared to CPU, DSP and GPU, FPGA has traits of high-speed processing, low power and hardware reprogramming [1]. FPGA is dozens of times faster than the CPU because the advantage of parallel processing. Hence, in the field of high-performance computing (HPC), system on chip architectures composed of instruction set processor and reconfigurable logic have become popular [2]. The current FPGA architecture supports dynamically reconfigure part of hardware resources on the device at different times without affecting the working state of other logic circuits, i.e., different logic circuit regions on the device can work independently without affecting each other. We call it dynamic partial reconfiguration technology. Dynamically partially reconfigurable (DPR) technology achieves the time and space reuse of FPGA resources by dividing multiple reconfigurable regions on FPGA and executing different tasks at the same time. Due to dynamic time-multiplexing, finite space resources can be extended indefinitely in the time domain, which enables the reconfigurable system to execute applications with greater resource requirements on the chip system of finite resources. This technology can divide FPGA resources into multiple logic regions, so that the execution process between different regions does not affect each other, realizing parallel processing of tasks. With the advent of 5G and the big data era, machine learning has been widely applied in various fields [3]. There are lots of practical applications such as image processing [4], computer vision [5]. Those applications have higher requirements on computing efficiency. The computing efficiency of heterogeneous processing system combining FPGA and CPU is greatly improved compared with that of single CPU system. FPGA's parallel processing and reconfigurable ability and low power consumption compared with GPP make it play an important role in the field of HPC. Some Internet giants utilize FPGA to accelerate search efficiency and launch FPGA cloud to provide acceleration solutions for enterprises. SRAM-based FPGA allow the configuration of the FPGA to be modified by loading part of the configuration file to change the function of regions during running time without affecting the execution of other regions. The DPR system utilizes execution time to hide reconfiguration time and takes advantage of the parallelism of execution to greatly improve the execution efficiency of applications in FPGA [6]. At present, Early Access Partial Reconfiguration (EAPR), the DPR design flow of Xilinx, supports region-based reconfiguration. The FPGA is divided into several rectangular regions which is defined as the reconfigurable region. Each region can be time multiplexed. This paper studies the partitioning and scheduling of the DPR system, i.e., the resources virtualizing, partitioning the reconfigurable regions, determining the size of the reconfigurable regions and the scheduling order of each task, and mapping the tasks to the reconfigurable regions. The dynamically partially reconfigurable system partitioning and scheduling problem is the NP problem [7], and the solution of the NP problem mainly includes constructing ILP/MILP model, branch and bound, A* algorithm, heuristic search method and so on. ILP based methods are popular as a result of accuracy. However, its time complexity is proportional to the number of variables and constraints in the model, so the solving efficiency is inefficient. Generally, the heuristic method can solve the approximate optimal solution with a low time complexity. If properly designed, the obtained approximate optimal solution is similar to the global optimal solution. Within this context, we may summarize our contribution as follows:  
1. We jointly solve the problem of resource partitioning and application scheduling and consider many physical constraints;
2.