## 4 Adopted Design Flow
### Nisc Abstraction Level  
The first step towards design development is to describe the datapath of the proposed architecture. The datapath is captured in (GNR). Using HDL description (i.e., Verilog), all basic components, such as multiplexers, adders, subtractors, multipliers, registers and converters, are first defined. In GNR, basic components are simply described by indicating their types, ports, parameters and aspects. Hierarchical modules (such as computational unit, multiplexing unit, storage unit and the _EquaNisc_ module in the equalizer architecture; and Euclidean distance unit, the a priori LLR summation unit, inter-subtraction unit, minimum finders unit, output unit and the _DemaNlSC_ module in the demapper architecture) are built in GNR. A hierarchical module can be composed of basic component(s) and/or module(s) of lower hierarchical level. Figure 8 presents the GNR description of a minimum finder block used in minimum finders unit (MFU) of the _DemaNlSC_ module (Figure 5a). The figure illustrates the construction of the \"MinFinder\" module from basic blocks, such as multiplexers, subtractor, registers and logic gates, in addition to its internal netlist. The module has seven ports and is parametrized by three parameters (_BIT_WIDTH_, _Mid_WIDTH_ and _Initial_), which are used as internal specifications and are defined by higher hierarchical level components. In each architecture, all required components and modules are allocated, and their attributes and interconnections are assigned. The automatic completion of the GNR description is exploited to reduce the datapath modeling. In addition, syntax checking and rule validation, which are provided by the tool set, are used to quickly detect and fix connection errors. Figure 7: Adopted design flow. The following step after datapath description is to declare pre-bound functions defining the functionality of the _EquaNiSC/DemanNiSC_ module. All control values that should be applied to control ports of hardware resources in a definite clock cycle are enumerated in a specific pre-bound function. All independent operations are merged into single pre-bound function in order to maximize the exploitation of hardware resources and to decrease the execution time. Figure 9 shows a pre-bound function sample, which merges several operations (four data transfers (move), one data loading from _ChMem_ and setting a new address) into one pre-bound function \"_PreBoundSample_\". As shown in the figure, in addition to scheduling information, all required control values of all incorporated resources and ports are specified explicitly. When all pre-bound functions are described, the _PreboundCGenerator_ tool is utilized to process the structural description of all pre-bound functions and to generate their corresponding C definitions. A C code application is easily developed by listing the sequence of C definitions related to all pre-bound functions involved in MMSE equalization/Max-Log-MAP demapping. Figure 10 presents the list of C definitions that are related to pre-bound functions defining the functionality of the _DemanNiSC_ module. Figure 10 shows the GNR description of the pre-bound function \"_QPSK1_\", which declares the control values that should be applied at the first  
Figure 8: “MinFinder” module generic netlist representation (GNR) hierarchical description. step of demapping for the QPSK modulation scheme. The C application is verified by checking the code syntax and the availability of used C definitions of pre-bound functions. The last step in NISC abstraction level is to compile the datapath and the C code application. The tool set compiler is used to generate the control words, which are arranged automatically in the output memory file. The RTL generator in the tool set produces the HDL code, which describes the whole design architecture benefiting from the compiler information and the datapath structure.