# Research on Clock Synchronization of Data Acquisition Based on NoC
## 3 The Proposed Design Clock Synchronization Scheme  
### Overall Design  
The performance of data transmission relies heavily on the on-chip network architecture, which not only significantly affects network latency, throughput, area, and power consumption, but also plays a crucial role in the mapping from cores to network nodes. This paper applies on-chip networks to high-speed data acquisition, mapping analog-to-digital converter (ADC) chips and high-speed transmission interfaces to network on-chip resource nodes (IP cores). In the distribution of IP cores, each data acquisition routing node connects to one ADC resource node IP core. Each router has an independent asynchronous  
Figure 4: The sequence chart of DDMTD. clock, using the router's clock as the sampling clock for the ADC, thereby ensuring that the sampling clocks of ADCs are also independent of each other. Regarding data communication, ADC resource nodes only communicate with high-speed transmission interface resource nodes. That is, communication between IP cores is singular. An excessive number of routing nodes in the communication path between source and destination nodes will result in significant data transmission delays. Therefore, in the design, the transmission distance between ADC resource nodes and high-speed transmission interface resource nodes should be kept as short as possible to meet the low-latency requirements of data transmission. This paper adopts a time-interleaved sampling scheme with six ADCs, each with a sampling rate of 250 MHz and a resolution of 8 bits, resulting in an input bandwidth of 2 Gbps per ADC. The overall sampling rate of the system is 1.5 GSPS, with a total input bandwidth of 12 Gbps, as shown in Figure 5. Each high-speed interface has an output bandwidth of 6.6 Gbps, resulting in a total system output bandwidth of 19.8 Gbps. Taking into account some resource consumption for data encapsulation and packaging, each high-speed interface resource node can simultaneously receive and process data from two ADC resource nodes. Thus, it is possible to design the system in a grouped manner, with two ADC resource nodes and one high-speed interface resource node forming a group for expansion. The ADC chips connected by routers in the left and right columns collect data in a time-interleaved manner. The collected data are then packaged and transmitted through the resource network interface to the connected router. Subsequently, the data are sent to the routers in the middle column, and finally, transmitted to the host computer via high-speed interfaces. This setup ensures that the distance between data collection and data transmission is only one hop, resulting in minimal transmission latency. NoC has the characteristics of multi-task parallel communication and global asynchronous and local synchronous clock distribution [27]. The clock of each routing node is  
Figure 5: Network on-chip data acquisition topology. Each router connects to a resource node IP core. The left and right columns are data acquisition nodes, connected to ADC chips. The routers in the middle column are data transmission nodes, connected to high-speed transmission interface IP cores. The red links transmit clock synchronization messages, while the blue links are responsible for transmitting the collected data across the entire network. This topology is simple and easily scalable, allowing for the expansion of multiple ADC acquisition nodes and data collection nodes according to actual needs. supplied by an external independent clock oscillator, which is output to the router after the PLL frequency doubling and the frequency difference is eliminated, and is used as the sampling clock of the ADC after the clock synchronization is completed. The sampling clock of the TI-ADC channel needs high-precision synchronization to ensure the performance of data acquisition. The White Rabbit protocol can realize sub-nanosecond-level synchronization, so it is applied to the NoC in this paper, and it is also improved to implement clock synchronization between routers.