# Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL
## 2 System-Level Design of PLL and Passive Filter Sizing
### PLL Modeling in \"Advanced Design System\" Environment  
A phase domain model has been firstly built to analyze the PLL bandwidth and stability. There, all the blocks are linearized: the PFD/CP and the FD have constant gains of \(\mathrm{I_{cp}}/2\pi\) and 1/\(N\), respectively, while the VCO is modeled as an integrator with gain \(\mathrm{K_{VCO}}\). The transfer functions for the open, Equation (1), and closed, Equation (2), loop models are the following:  
\[H_{ol}=\frac{\mathrm{I_{cp}}}{2\pi}Z(s)\frac{K_{VCO}}{s}\frac{1}{N}\;, \tag{1}\]  
\[H_{cl}=\frac{\frac{\mathrm{I_{cp}}}{2\pi}Z(s)\frac{K_{VCO}}{s}}{1+\frac{ \mathrm{I_{cp}}}{2\pi}Z(s)\frac{K_{VCO}}{s}\frac{1}{N}}, \tag{2}\]  
with an \(\mathrm{I_{cp}}\) of 40 \(\mathrm{\SIUnitSymbolMicro A}\), \(N\) of 40, and:  
\[\mathrm{K_{VCO}}=12.57*10^{9}\;rad/(V*s), \tag{3}\]  
\[Z(s)=\frac{1}{s(C1+C2)}\frac{1+sR1C1}{1+sR1\frac{C1C2}{C1+C2}}. \tag{4}\]  
Figure 1: Block schematic of the Charge Pump Phase-Locked Loop (CP-PLL).  
Figure 2: Loop Filter’s schematic view.  
Figure 3 shows the results obtained using an AC simulation. As expected, R1, introducing a zero, increases the stability of the loop. In contrast, C2, introducing a pole, reduces the Phase Margin; therefore, its value has been selected to maximize the latter. The main results of the simulations are a unity gain frequency of 3.31 MHz with 50.9\({}^{\circ}\) of Phase Margin, and a 5.37 MHz closed loop bandwidth.  
Secondly, to evaluate the noise and lock performances, a behavioral model of the closed loop PLL, as shown in Figure 4 together with the model of the VCO alone, has been built to perform simulations in time and frequency domains. Since all the blocks of the model are noise-free, the block labeled NoiseVCO is added to consider the VCO contribution to phase noise. It is a voltage noise source that approximates with a piecewise linear curve the simulated phase noise of the VCO designed in [16], and starting from it, it generates the equivalent input noise. Regarding the Loop Filter, the noise model provided by ADS has been used for the analysis. Figure 5a shows the PLL lock behavior, which presents a lock time of 555.6 ns for a locking error below 0.01%. The peaks in Figure 5a, due to the resistor of the Loop Filter, are not seen when the PLL is locked because the CP model is ideal. However, since the real CP will be affected by non-idealities, the second capacitor is needed to attenuate these peaks. Instead, Figure 5b shows that the phase noise is well below \(-\)80 dBc/Hz. However, the reference and CP contributions have not yet been considered in this simulation, since this represents a preliminary analysis (the PFD and CP contributions to Phase Noise are analyzed in Section 3.1.3). As expected from the theory [19], the loop has a band-pass response with respect to the Loop Filter noise and a high-pass response with respect to the VCO noise.  
Figure 3: Results of the AC analysis performed on the phase domain models: magnitude on the left and phase on the right of (**a**) the open loop model and (**b**) the closed loop model.