# Application of Surge Arrester in Limiting Voltage Stress at Direct Current Breaker
## 5 Experimental and Simulation Results
Figure 10 depicts the simulated currents in the 280 V and 500 V tests. The upstream, downstream, and surge-arrester currents are illustrated. It is observed that the upstream current takes a longer time to diminish than the downstream current, i.e., 4.5 ms in the 280 V test and 9.6 ms in the 500 V test compared to 3.9 ms and 4.0 ms, respectively. Thus, the surge arrester alleviates the excessive voltage rise. Figure 10 also depicts the switch (and capacitor) and DCCB input-terminal voltages as well as the redirecting diode currents. Since SW2 operates faster (1.5 ms) than SW1 and the surge-arrester voltage drops meanwhile, diode D1 only turns on for a very short time. The surge-arrester blocking voltage and the diodes operation are in good agreement with the hardware results. Some discrepancy is natural due to the random behavior of the arc, as well as series resistances that could not be accurately modeled here. The actual series resistance seems to be slightly higher in the hardware experiment, providing better damping characteristics. This is in part due to the electromagnetic effects of the large coils on the coil resistances during the high fault currents (skin effect), as well as the diode and surge-arrester V-I characteristics. Table 2 compares the current zero-crossing time of the experimental and simulation results with those calculated using Equation (9). By comparing the experimental, simulated and calculated results from Table 2, the average time for the current zero-crossing is 4.5 milliseconds. However, the zero-crossing time in the experimental results for the voltage level of 500 V is almost 9.5 milliseconds, due to the existence of an arc at the beginning of the contact separation of both switches (SW-1 and SW 2). Some of this time, which is around 8 milliseconds, relates to the arc that causes the hardware results to deviate from the calculated and simulated ones. Second, the selected breaker in the hardware test is recommended for 240 VDC and thus is overburdened when used at 500 V. Using a faster breaker will diminish the arc in a much shorter time, causing the experimental results to match those simulated and calculated. Figure 9: V-I characteristics of the surge arrester [24]. Case 5. Simulated distributed system  
Next, the breaker is tested for a distribution system in MATLAB Simulink. A 10 km distribution line is considered, with an inductance of 3.33 mH and a resistance of 33 m\(\Omega\) (0.33 mH/km and 3.3 m\(\Omega\)/km [23]). A 13.8 KVDC supply is used with a nominal load current of 2000 A (Figure 11). Then, 300 \(\mu\)F bypassing capacitors are used parallel to the switches based on a fault current of 20,000 A and \(C>\frac{I_{fault}}{80\times 10^{8}}\) (= 250 \(\mu\)F), as explained earlier. The surge arrester is rated at 15 kV and \(I_{ref}=20000\ A\). To test the effectiveness of the surge arrester, the breaker is placed at two different locations along the power line, namely at one-third and two-thirds of the distance from the source, with the fault occurring at the end of the line. We issue a trigger signal when the fault current reaches 20 kA. The delay between the operation of switches SW2 and SW1 is set at 500 \(\mu\)s.  
When the breaker is placed at one-third of the distance from the source with the fault location at the end of the line, the proposed breaker has a smaller value of upstream impedance (1.11 mH and 11 m\(\Omega\)). Figure 12 compares the current and voltage waveforms with and without the surge arrester. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Voltage** & **Experimental** & **Simulation** & **Calculation** \\ \hline
**280 V** & 4.53 ms & 4.37 ms & 4.48 ms \\ \hline
**500 V** & 9.54 ms & 4.18 ms & 4.83 ms \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Current Zero-Crossing Time.