# A Review of Advanced CMOS RF Power Amplifier Architecture Trends for Low Power 5G Wireless Networks
## Advanced RF PA Architectures
### Outphasing RF PA (LINC PA)  
The outphasing modulation technique was invented by [PERSON] in 1935 in order to improve both efficiency and linearity of AM-broadcast transmitters. Substantially later, its application was extended up to microwave frequencies under the name LINC (linear amplification using nonlinear components). An outphasing transmitter, presented in Figure 4, operates as a linear PA system for amplitude-modulated signals having a linear transfer function over a wide range of the input signal levels by combining the outputs of two nonlinear PAs that are driven with signals of constant amplitude but different time-varying phases corresponding to the envelope of the input signal [31]. PAs should be designed to offer the highest possible power efficiency at saturation through the selection of their biasing and impedance matching circuits. This leads to the use of switch-mode class which is highly nonlinear but very efficient. While amplifiers may operate highly efficiently, it is the remaining available power at the output of the combiner that will determine the overall efficiency of the LINC system [32]. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline
**Ref.** & **Process** & \(\boldsymbol{V_{\text{DD}}}\)**, V** & \begin{tabular}{c} **Frequency,** \\ **GHz** \\ \end{tabular} & \begin{tabular}{c} **\(\boldsymbol{P_{\text{linear}}}\)** \\ **dBm** \\ \end{tabular} & \
\begin{tabular}{c} **Overall** \\ **PAE, \%** \\ \end{tabular} &
\begin{tabular}{c} **_EVM, \%** \\ **BW, MHz** \\ \end{tabular} \\ \hline
[23] & 350 nm _SiGe_ BiCMOS & 4.2 & 2.4 & 24.3 & 43 & 5 & 5 \\
[24] & 350 nm _SiGe_ BiCMOS & 3.7 & 0.7 & 26.5 & 42 & 3.5 & 10 \\
[25] & 320 nm _SiGe_ BiCMOS & 4.2 & 2.4 & 24.3 & 42 & 5 & 5 \\
[26] & 320 nm SOI CMOS & 3.4 & 0.837 & 25.9 & 42.3 & - & 10 \\
[27] & 280 nm SOI CMOS & 3.4 & 0.837 & 25.5 & 42.2 & 2.32 & 40 \\
[28] & 180 nm CMOS & 4.7 & 1.7 & 28.5 & 36.6 & 3 & 10 \\
[29] & 180 nm CMOS & 3.3 & 2.535 & 28.3 & 48 & 2.1 & 20 \\
[18] & 150 nm CMOS & 5 & 2.5 & 27.6 & 46 & - & 5 \\
[20] & 130 nm CMOS (ET) _SiGe_ HBT (PA) & 3.3 & 1.88 & 27.8 & 45 & 2.98 & 5 \\
[30] & 90 nm CMOS & 2 & 0.93 & 26 & 17 & 5.6 & 3.84 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Summary of reviewed ET/EER PAs in CMOS and BiCMOS processes. Theoretical outphasing PA efficiency comes close to 100% whereas the practical _PAE_ with load compensation can be expressed as  
\[\eta_{PAE}=\frac{2\cos^{2}\phi}{\sqrt{\left(2\cos^{2}\phi\right)^{2}+\left(\sin 2 \phi-\sin 2\phi_{comp}\right)^{2}}} \tag{2}\]  
where \(\phi\) is the outphasing angle and \(\phi_{comp}\) is the compensation angle. A summary of papers reporting outphasing PA research results and parameter improvement solutions in CMOS process is presented in Table 3. Similar to ET/EER and DPA, the outphasing PA is narrowband. The output power and supply voltages are in the range of portable device specs with the overall system _PAE_ varies depending on which class (linear or nonlinear) PA is used and is in the range of 16-62%. Moreover, system efficiency greatly depends on the organization of the DSP algorithm, therefore basic information, such as the process, PA class and frequency, is not sufficient enough to fully describe system _PAE_. Outphasing architecture advantages:  
1. Architecture simplicity. An outphasing PA only consists of a signal component separator, two parallel amplifiers and a power combiner;
2. Efficiency can be increased without hardware changes by means of improving DSP algorithms;
3. Predistortion techniques are applicable in order to enhance overall system linearity;
4. Possible integration in a single ASIC. The main bottleneck is the power combiner. Outphasing architecture disadvantages:  
1. Narrow bandwidth. The main bottleneck is the power combiner;
2. High synchronization precision between parallel RF paths required for maximum efficiency;
3. Practical efficiency, compared to the theoretical, is highly reduced due to losses in passive components;
4. Specific power combiners required.