# Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs
## 3 Related Works
The effectiveness provided by this integration process rests on its accounting for various network-associated features such as routing and scheduling strategies, node partitioning, data packetization, buffer sizes, QoS, and others. To achieve an effective adequation between the reconfigurability features and performance constraints, the accelerators need to be coupled with a structural network mapping. Moreover, by deploying parallelized multicore, the speed of operations over the chip could be improved even more. In this respect, several studies have attempted to explore the deployment of Deep Neural Network (DNN) in order to achieve highly efficient on-chip interconnects. For this purpose, crossbar communication is commonly used owing to the regularity and scalability of DNN operations [39; 40]. Mesh, tree, and Clos networks have also been implemented with DNN accelerators to improve chip performance through efficient memory access, low-latency multicast communication, power efficiency, and computing flexibility [41; 42; 43]. Regarding reconfigurable architectures, studies have suggested replacing the crossbar with wire switchers in experimentation. Different types of interconnections, such as optical, wireless, or 3D networks, have recently been proposed and applied in DNN computing [44; 45]. Another mapping algorithm tested for its effectiveness has also been put forward in ref. [46], while a communication-on-chip system focused on topology reconfiguration has been advanced in ref. [47]. As already stated, one could well note that the Multistage Interconnection Networks (MINs), classified into regular, scalable, and reconfigurable topologies, do not seem to be treated in terms of chip communication improvement purposes through wireless nodes, and appear to be exclusively evaluated through the perspective of applying Deep Neural Networks accelerators. In recent research, Network-on-chip can be used as a communication backbone for chip multiprocessors, to improve the computational performance of neural network accelerators by dissociating communication and computing data. NoC features namely, scalability,efficiency, reliability, and modularity, that enable computing components to exchange a huge amount of data, ultimately achieving enhanced energy efficiency and performance.In this context, the integration of CNNs or DNNs on NoC platforms have been illustrated so far [45; 48; 49; 50; 51; 52; 53; 54]. Several hybrid parameters have to be carefully considered in the mapping process. First, the clustering of layers on computing elements (PEs) is managed by mapping algorithms. On the other hand, the NoC is specified by its topology, which defines the placements of routers and links, routing algorithm, and memory scheduling. Consequently, according to this mapping process, computation is executed on PEs as they routed over the NoC following an adapted DNN dataflow. In ref. [55], [PERSON] et al., propose a simulator, baptized NN-Noxim. This tool details several constraints, such as classification precision, energy, and transmission delay, based on a hybrid configuration related to the DNN mapping model and NoC parameters. Neuron computation and data communication in the fully connected layers have been simulated and evaluated. This simulator has been extended in ref. [56] to integrate convolution and pool layers. However, these developed tools only support static NoCs, such as the mesh topology. In the following section, we present our envisioned novel design of the Delta MIN-based NoC that incorporates wired and/or wireless interconnection. We also provide a relevant performance evaluation process. The assessment procedure has actually proven the noticeable benefits brought about by the idea of integrating radio hub nodes into the process of ensuring resilient and adaptative communication among the Delta MINs different incorporated stages [48].