## 3 Results and Discussions  
Figure 2 shows the transfer characteristics of the MOSFET, planar TFET (Figure 2b), DG TFET (Figure 2c), and EHBTFET (Figure 2d) when the drain voltage (V\({}_{\text{D}}\)) is 0.5 V and source voltage (V\({}_{\text{S}}\)) is 0 V. The metal grain profiles of the gate area were randomly generated by the randomization algorithm provided in the Sentaurus tool, depending on the TiN grain orientation. Thirty samples with uniquely randomized metal gate grain profiles for each structure were used for the simulation and the WFV effect analysis in this research. In the case of the EHBTFET in Figure 2c, a voltage of \(-0.67\) V was applied to the SG to transport the holes from the source region to the channel region near SG and generate BTBT between the MG and the SG. For a comparison of the WFV effects, the average and standard deviation of V\({}_{\text{th}}\), SS and I\({}_{\text{on}}\) for each structure were obtained and are summarized in Table 2. The V\({}_{\text{th}}\) of MOSFET is defined as the gate voltage when V\({}_{\text{D}}\) is 0.5 V and the drain current is \(10^{-12}\) A. Instead of V\({}_{\text{th}}\), the turn-on voltage (V\({}_{\text{turn-on}}\)) of TFETs is defined as the gate voltage when BTBT starts to occur at the source junction and the drain current increases compared to the leakage current, and is extracted when V\({}_{\text{D}}\) is 0.5 V and the drain current is \(10^{-18}\) A. In this research, V\({}_{\text{turn-on}}\) was used for the WFV analysis instead of V\({}_{\text{th}}\), because the drain current of TFETs is much lower than that of MOSFETs, \begin{table}
\begin{tabular}{c c} \hline
**Parameter** & **Value** \\ \hline Gate length (L\({}_{\text{G}}\)) & 70 nm \\ Channel width (W) & 70 nm \\ Equivalent oxide thickness (EOT) & 2 nm \\ Channel length (L\({}_{\text{CH}}\)) & 90 nm \\ Channel thickness (T\({}_{\text{B}}\)) & 10 nm \\ Drain underlap (L\({}_{\text{UD}}\)) & 20 nm \\ Source underlap (L\({}_{\text{US}}\)) & 20 nm \\ MOSFET source/drain doping concentration & \(10^{20}\) cm\({}^{-3}\) \\ TFET \(p\)-type source doping concentration & \(10^{20}\) cm\({}^{-3}\) \\ TFET \(n\)-type drain doping concentration & \(10^{18}\) cm\({}^{-3}\) \\ Gate work function & 4.6 eV (60\%) \\  & 4.4 eV (40\%) \\ \hline \end{tabular}
\end{table} 
Table 1: Device parameters of devices used for the technology computer-aided design (TCAD) simulation. Figure 1: Basic schematics and major parameter definitions of the (**a**) metal-oxide-semiconductor field-effect transistor (MOSFET), (**b**) planar tunnel field-effect transistor (TFET), (**c**) double-gate (DG) TFET, and (**d**) electron-hole bilayer TFET (EHBTFET) used in this research. the definition of Vth in TFETs is controversial [50; 51], and the SS variation effect of TFETs is large [33]. SS is defined as an average swing when the drain current is increased from \(10^{-12}\) to \(10^{-10}\) A (MOSFET) or \(10^{-18}\) to \(10^{-16}\) A (TFET). Ion is defined as the drain current when VG is average Vturn-on (average Vth in MOSFETs) + 0.6 V and VD is 0.5 V. As shown in Figure 2 and Table 2, the \(\sigma\)Vturn-on of the planar TFET has the largest value (20.1 mV). In the case of the DG TFET, \(\sigma\)Vturn-on is reduced by \(-26.4\%\) in comparison to the planar TFET. Moreover, in the EHBTFET, the \(\sigma\)Vturn-on is drastically reduced to \(-80.1\%\) compared to the planar TFET, showing the smallest \(\sigma\)Vturn-on among the three types of TFET structures. The \(\sigma\)SS and normalized \(\sigma\)Ion also show the same tendency as \(\sigma\)Vturn-on. The reduction in the WFV effect on the DG TFET and EHBTFET compared to the planar TFET can be interpreted as a result of an increase in the number of metal grains that affect Vturn-on determination. It is known that as the number of metal grains affecting Vturn-on increases, the WFV effect is suppressed by a higher averaging effect [52; 53; 54]. When the number of grains changes, the variance of the WF