## 5 Conclusions  
In the present study, a delay/area performance comparison of the array, Wallace tree, and radix-4 Booth multipliers was presented. Several multipliers were successfully designed using Alliance tools. The synthesized output data were analyzed using 11-, 16-, 24-, 32-, 53-, and 64-bit multipliers. These findings indicate that the area and delay significantly increase with the size of the array multiplier. In particular, the Wallace multiplier increases smoothly in a quadratic manner, whereas stepwise linear growth occurs with radix-4 in delay performance. In addition, the Wallace multiplier exhibited the lowest latency for the 11-, 16-, and 24-bit multipliers. However, for the 32-, 53-, and 64-bit multipliers, Wallace had almost the same delay as the radix-4 Booth multiplier.  
Using the 11-bit Wallace multiplier with the lowest delay as a reference, the delays of the 24-bit and 53-bit Wallace multipliers increased by 137% and 190%, respectively. Compared with the radix-4 Booth multiplier, the delay of the 24- and 53-bit multipliers is increased by 165% and 185%, respectively. Thus, depending on the application, either the Wallace tree or the radix-4 Booth multiplier can be used in single- and double-precision floating-point multiplications.  
Designers of digital circuits may use this study to choose an optimal architecture of fixed- or floating-point multipliers for VLSI implementation, considering their design constraints. For future possibilities, the scope of this paper suggests that we could perform a comparison between Alliance and commercial EDA tools.  
Conceptualization and writing--original draft preparation, A.J.; formal analysis and writing--review and editing, A.M.; data curation and validation A.J. All authors have read and agreed to the published version of the manuscript.  
This work was published with financial support from the Instituto de Innovacion y Competitividad de la Secretaria de Innovacion y Desarrollo Economico del Estado de Chihuahua (2022-2028) and the Universidad de Guadalajara through the 2025 PROSNII program. The authors express their gratitude for the partial economic assistance provided to cover article processing charges.  
Not applicable.  
Data  
supporting this study are openly available on Google Drive at [[https://drive.google.com/drive/folders/1A4](https://drive.google.com/drive/folders/1A4) UQ8 ffPzqW797 LHuTk1 LrbxBkfortoTg?usp=sharing]([https://drive.google.com/drive/folders/1A4](https://drive.google.com/drive/folders/1A4) UQ8 ffPzqW797 LHuTk1 LrbxBkfortoTg?usp=sharing), accessed on 20 February 2025.  
The authors express their gratitude to Universidad Autonoma de Ciudad Juarez for granting access to the laboratory facilities at the Centro de Investigacion en Ciencia y Tecnologia Aplicada ([[https://www.uacj.mx/IIT/C1](https://www.uacj.mx/IIT/C1) CTA/]([https://www.uacj.mx/IIT/C1](https://www.uacj.mx/IIT/C1) CTA/), accessed on 10 February 2025) and to Universidad de Guadalajara for its facility support. They also extend their thanks to the Secretaria de Ciencia, Humanidades, Tecnologia e Innovacion (SECIHTI) for providing the research fellowship.  
The authors declare no conflict of interest.  
The following abbreviations are used in this manuscript:  
\begin{tabular}{l l} VLSI & very-large-scale integration \\ CMOS & complementary metal-oxide-semiconductor \\ VHDL & VHSIC hardware description language \\ FAs & accurate full adders \\ GDI & gate diffusion input \\ EDA & electronic design automation \\ RTL & register-transfer level \\ \end{tabular}