# Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices
## 3 NAND Flash Memory Reliability  
From a general standpoint, the reliability of a product is related to its capability to continue to work as expected as a function of time. Reliability is enhanced by screening, testing and qualification and, eventually, by error management procedures. In all these respects, Flash memories are peculiarly different from other semiconductor devices, as they intrinsically operate under high-field conditions that other devices purposely avoid. Moreover, reliability is usually extrapolated from accelerated tests, that should replicate as close as possible the real operating conditions. Unfortunately, the development of such tests is complicated by the many different patterns of program/erase and read cycles under which Flash memories usually operate.  
As a matter of fact, there are a number of failure modes and mechanisms that are specific to Flash, not to mention error-management procedures that are put forward by the manufacturers to increase reliability and yield. These depend on the type of failure, which can be recoverable (i.e., it can be fixed by erase and reprogram) or not. Recoverable errors are usually dealt with via error-correction codes (ECC). Initially, when SLCs were prevalent, simple Hamming algorithms were employed, which could correct single-bit errors and detect two-bit ones. Later, more efficient BCH (Bose, Ray-Chaudhuri and Hocquenghem) algorithms were implemented in the Flash controller [41]. However, as Flash capacity continued to rise and MLCs gave way to TLCs, more efficient ECCs were needed, resulting in a transition to soft decoding schemes. Low-density parity-check (LDPC) ECCs [42; 43; 44; 45] are gaining traction in modern SSDs, while concatenated codes for NAND Flash have been also proposed [46; 47; 48; 49].  
Non-recoverable errors, or errors exceeding the ECC capabilities, result in _bad blocks_[50], i.e., blocks that are excluded from the memory operation and are replaced by available valid blocks. A small number of initial bad blocks is allowed, which can increase with use. Eventually, when the number of bad blocks exceeds the device specifications, the entire chip fails. It is worth mentioning that both ECC and bad blocks management require extra cells/blocks, thereby contributing to an increase of the cell effective area as discussed in Section 2.1, i.e., a reduction in the array efficiency.  
Reliability specification by the manufacturers typically includes the number of bad blocks, the endurance and retention properties of the array and the number of error-correction code bits. In the following, however, we will go beyond the manufacturer specifications and look at the basic physical mechanisms at the heart of the reliability issues. Since this is an extremely large field, we restrict our discussion to issues that develop with memory usage, neglecting for example defect-related issues, time-zero problems such as \(V_{T}\) placement, cell-to-cell interference and many others, for which we refer the reader to other overviews of Flash memory reliability that are available in the literature, leaning either toward a device/technology [51; 52; 53; 54; 55; 56; 57; 58; 59] or user [60; 61; 62] viewpoint.