# A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier
## 4 Amplifier Design and Simulation Results
### Simulation Results  
The circuit has been simulated in the Cadence Virtuoso environment to test both open-loop and closed-loop performance. Figure 5 reports the magnitude and phase of the open-loop differential gain: a 64.6 dB dc gain with a 3.58 kHz unity gain frequency and a phase margin of about 54\({}^{\circ}\) are achieved in typical conditions. The amplifier has been simulated in a unity-gain buffer configuration to test closed-loop performance. Figure 6a shows the dc input-output characteristic of the buffer, highlighting a rail-to-rail output swing. The bias control loop is able to keep the common mode current of the input stage constant under input common mode variations, as shown in Figure 6b, thus improving common mode rejection and linearity. The CMRR is approximately 61 dB as shown in Figure 7. Supply rejection is around 27 dB, and the amplifier power dissipation is only 11.4 nW.  
The slew rate has been evaluated simulating the response to a full swing (300 \(mV_{pp}\)) input step, shown in Figure 8: The positive slew rate is 1.7 V/ms, whereas a much lower negative slew rate of 0.14 V/ms is achieved, limited by the current source \(M_{6}\). Total harmonic distortion (THD) for a 300 \(mV_{pp}\) input signal at 10 Hz is 0.84%. To give more detailed informations about linearity performance, the THD versus the peak-to-peak input voltage is shown In Figure 9a, whereas the differential voltage gain (in dB) as a function of the input common mode voltage is reported in Figure 9b to demonstrate the almost rail to rail input voltage range of the proposed amplifier. Finally the equivalent input referred noise is depicted in Figure 10 showing a spot noise at 100 Hz of about 2.69 \(\mu V/\sqrt{Hz}\).  
An area footprint of the amplifier of about 0.0064 mm\({}^{2}\) has been estimated by using the Cadence Layout XL tool.  
To assess the robustness of the proposed design, PVT and Monte-Carlo simulations have been carried out. Table 2 reports the simulated performance under different process corners, highlighting a very good stability of the amplifier performance. The amplifier's robustness has been tested also under supply voltage and temperature variations. Main amplifier parameters under supply voltage variations from 0.24 to 0.36 V are reported in Table 3, whereas simulation results under temperature variations in the range from \(-10\)\({}^{\circ}\)C to \(110\)\({}^{\circ}\)C are shown in Table 4.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline  & **W [\(\mu\)m]** & **L [\(\mu\)m]** & **I\({}_{\text{D}}\) [nA]** & **g\({}_{\text{m}}\) [nS]** & **g\({}_{\text{mb}}\) [nS]** & **r\({}_{\text{ds}}\) [G\(\Omega\)]** \\ \hline \(M_{1}\),\(M_{2}\),\(M_{6}\), \(M_{b7}\) & 6.63 & 10 & 5 & 152.1 & 25.44 & 1.864 \\ \(M_{3}\),\(M_{4}\),\(M_{1\ell 2}\),\(M_{1\ell 3}\),\(M_{b4}\),\(M_{b4}\),\(M_{b5}\) & 0.9 & 10 & 5 & 131.8 & 23.68 & 0.667 \\ \(M_{b1}\) & 6.63 & 10 & 10 & 304.3 & 50.89 & 0.932 \\ \(M_{6}\) & 20 & 7.53 & 4 & 121.8 & 20.78 & 2.229 \\ \(M_{9}\) & 10 & 7.53 & 4 & 121.8 & 20.78 & 0.037 \\ \(M_{5}\),\(M_{7}\) & 0.73 & 10 & 2 & 55.65 & 50.89 & 0.93 \\ \(M_{8}\) & 1.47 & 10 & 4 & 111.3 & 23.5 & 0.85 \\ \hline \end{tabular}
\end{table}
Table 1: Nominal transconductance, sizing and output resistance of transistors.  
Figure 5: Open-loop differential gain frequency response: magnitude (**a**) and phase (**b**).  
Figure 6: DC transfer charachterisitc (**a**) and DC bias current of the input stage vs. input common mode voltage (**b**).  
Figure 7: Magnitude of common mode rejection ratio (CMRR).  
Figure 8: Response to a full swing input step.  
Figure 10: Equivalent input noise.  
Figure 9: Total harmonic distortion (THD) vs. input signal amplitude (**a**) and differential gain vs. input common mode voltage (**b**).