# Hardware Acceleration of Satellite Remote Sensing Image Object Detection Based on Channel Pruning
## 2 Related Work
### FPGA Acceleration of CNN  
In recent years, researchers have focused their attention on how to deploy CNNs on hardware acceleration platforms. On the one hand, CNN has a large amount of calculation and a large amount of data. How to optimize the network algorithm for hardware deployment has become a research hotspot. Some researchers have optimized the computational data flow of CNNs to take advantage of the parallelism of the algorithm. [PERSON] et al. [38] proposed an algorithm framework of CBFF-SSD, based on SSD, using lightweight MobileNet as the feature extraction network of the algorithm model. At the same time, a deep learning processing hardware architecture supporting parallel processing of feature maps was designed, and the deployment of the model was completed on Xilinx XC7Z100. [PERSON] [39] and others developed a highly optimized new HyperLCA algorithm for the limited power consumption budget and low-bandwidth downlink of remote sensing platforms such as drones, and used Xilinx (San Jose, CA, USA) Zynq-7000 seriousips to complete the FPGA Heterogeneous acceleration. This design scheme can achieve real-time detection effect in real-life hyperspectral application engineering. Compared with the three GPUs of Jetson Nano, Jetson TX2, and Jetson XavierNX, their FPGA solution is lower in price and higher in performance, and has the lowest power consumption, being just over 3 W. [PERSON]. [40] proposed the design scheme of deploying SSDLiteM2-MobileNetv2 on Xilinx ZC706, and realized the 8-bit fixed-point quantization of SSDLiteM2-MobileNetv2 through the quantization scheme. The experimental scheme reached a detection speed of 65 frames per second, meeting the requirements of real-time detection need. [PERSON] et al. [41] completed the deployment of the improved YOLOv2 network model on Xilinx (San Jose, CA, USA) ZYNQ xc7z035, and the power consumption was only 5.96 W. Based on the YOLOv-s network model, [PERSON] et al. optimized its core convolution module. At the same time, they designed a three-way prefetch cache queue to make full use of the on-chip data reuse model to solve the external DDR bandwidth in the multi-level cache process. The cache bottleneck problem is solved and the model inference performance is improved. The design architecture achieves an average throughput of 399.62 GOPS, and the computing efficiency of DSP reaches 97.56%. Compared with other researchers' designs, resource utilization has been greatly improved. [PERSON] et al. [42] proposed a scheme to automatically deploy CNN on FPGA. A series of hardware-oriented CNN improvements are proposed to reduce the model complexity. Based on this, a reconfigurable array of processing engines and an efficient convolution computing architecture are designed as hardware accelerators. At the same time, a compilation tool chain is also introduced to realize the automatic conversion of CNN models to hardware instructions, which facilitates the deployment of various network models on hardware. Finally, the deployment of the improved models of VGG16 and YOLOv2 on FPGA was  
Figure 2: Weight sharing. realized, and the power consumption on Xilinx AC701 (San Jose, CA, USA) is 6.77 W and 6.51 W, respectively. This solves the problem that most FPGA acceleration solutions can only target specific network models, and meet the low power consumption requirements of airborne or spaceborne platforms. [PERSON] [43] proposed an FPGA deployment scheme based on network pruning and subgraph fusion, which reduces the number of model parameters by 11 times and achieves 9-10 times inference acceleration while sacrificing part of the detection accuracy of the model. On the other hand, numerous researchers are leveraging the Vitis AI development environment offered by Xilinx to accelerate artificial intelligence computations and explore optimal neural network architectures for specific applications. Vitis AI offers a comprehensive development platform for efficiently deploying deep learning models on Xilinx FPGAs and SoCs.