## 2 System Description and Its Mathematical Modeling
### Differential Peak Current Mode Control  
The difference between \(i_{1}\) and \(i_{2}\) (scaled by a sensing resistance \(R_{sL}\)) is controlled using a conventional peak CMC by comparing the signal \(R_{sL}(i_{1}-i_{2})\) to the signal \(R_{sg}i_{\text{ref}}\). A ramp compensator is added to the current signal to avoid subharmonic oscillation for all the operating range of duty cycle. The comparison of the signals \(R_{sL}(i_{1}-i_{2})+v_{\text{ramp}}\) with the signal \(R_{sg}i_{\text{ref}}\) by using a comparator and a S-R flip-flop generate the high and low values of the pulses driving the switches as shown in Figure 3  
Figure 1: The concept of building a differential inverter using two DC–DC converters.  
Figure 2: Single-stage grid-connected PV-fed differential boost inverter.  
which represents the block diagram of the inner current control together with the outer voltage control. The reference current for the difference between the two inductor currents is provided by an external grid loop controlling the AC grid current. The activation of the switches Q\({}_{1}\), Q\({}_{2}\), Q\({}_{3}\) and Q\({}_{4}\) is carried out as follows: the signal \(R_{sL}(i_{1}-i_{2})+v_{\text{ramp}}\) is connected to the inverting pin of the comparator whereas a sawtooth signal \(v_{\text{ramp}}\) is applied to the non inverting pin. The output of the comparator is applied to the reset input of a set-reset (SR) latch and a periodic clock signal is connected to its set input as shown in Figure 2 in such a way that the switches Q\({}_{2}\) and Q\({}_{4}\) are on at the beginning of each switching cycle and are turned off whenever \(R_{sL}(i_{1}-i_{2})+v_{\text{ramp}}=R_{sL}i_{\text{ref}}\). The state of the switches Q\({}_{1}\) and Q\({}_{3}\) are complementary to the switches Q\({}_{2}\) and Q\({}_{4}\) respectively.  
The voltage reference \(V_{\text{MPP}}\) is to be provided by an MPPT algorithm. The error voltage \(v_{\text{pv}}-V_{\text{MPP}}\) is the input signal to a voltage controller.  
The DC-AC inverter stage is responsible for injecting a sinusoidal grid current \(i_{g}\) in phase with the grid voltage \(v_{g}=V_{g}\sin(2\pi f_{g}t)\). For this, another control loop strategy is used where the input DC-link voltage controller provides the reference grid current amplitude \(I_{\text{gref}}\) for the inner current controller. This amplitude is multiplied by a sinusoidal signal synchronized with the grid voltage \(v_{g}\), using a phase-locked loop (PLL), to obtain the time varying current reference \(i_{\text{gref}}=I_{\text{gref}}\sin(2\pi f_{g}t)\). The current controller is conventionally a PI regulator that aims to make the grid current \(i_{g}\) to accurately track \(i_{\text{gref}}\) hence making the reactive power close to zero. This loop is responsible for DC-link voltage regulation by adjusting the amplitude of the sinusoidal current reference. A low-pass filter with a cut-off frequency at the grid frequency is also usually added to the voltage controller with the aim to reduce the harmonic distortion introduced by second harmonic of the grid frequency. The error between the grid current and its desired reference is processed by the grid current controller.  
As shown in Figure 3, the grid current loop is mainly constituted by the grid current, its reference, which is obtained from the PLL, and the grid voltage and the type-III current regulator whose output is connected to one of the inputs of the PWM. Namely, the input to this controller is the grid current error \(i_{\text{gref}}-i_{g}\) scaled by the grid current sensor \(R_{sg}\). The PV DC voltage loop is mainly formed by the PV voltage, its desired value given by the MPPT controller, a low pass filter and the PI voltage regulator. The MPPT input is constituted by the PV current and the PV voltage from which the PV power is calculated and sampled at the MPPT sampling period.