# FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs
## 2 Related Work  
This section introduces the recent studies carried out with CNN models on FPGA platforms. FP-BNN, a binarized neural network (BNN) acceleration system design based on FPGA, has been proposed with the aim of significantly reducing the hardware requirements while maintaining an acceptable accuracy level [24]. FP-BNN employs the resource-aware model analysis (RAMA) strategy to calculate the resource expense in terms of arithmetic operations and memory units. The purpose of this step is to achieve an efficient tiling process that maps the entire goal onto the constrained resources. The performance accuracy of the FP-BNN was tested with a binarized AlexNet using the ImageNet dataset with a 64-channel accelerator architecture. A delay performance of 1.16 ms was achieved on a Altera Stratix-V 5 SGSD8 FPGA platform, in addition to compressing the weights and parameters by applying dynamic quantization to the input. Another FPGA-based accelerator study, called QEGCN, aims to quantize graph convolutional networks (GCNs). It is a well-known and popular DL model that learns through graph data [25]. QEGCN makes use of quantization-aware training (QAT) techniques to enable quantization in the training phase. QEGCN offers a similar performance accuracy, with 8-bit quantization over 32-bit floating-point numbers. An underlying characteristic of QEGCN is its edge-level parallelism working principle, which permits the execution of operations in a pipeline manner. The performance observations, using a Xilinx VCU128 FPGA, revealed superior speedup and energy efficiency when compared with existing similar studies. Figure 1: A view of entire system. FlowAcc is a fresh FPGA accelerator specifically designed for deep neural network (DNNs)-based optical flow estimation [26]. It utilizes a pipelined hardware style to process real-time consecutive images, resulting in an accurate pixel-wise correspondence. Similarly, FlowAcc operates a BNN architecture for a feature extraction process in a hardware-friendly way. Extensive performance evaluations show higher accuracy for an Altera Stratix-V FPGA on the Middlebury dataset. FracBNN is based on an FPGA-efficient operation, with a BNN structure benefiting from fractional activations [27]. A prominent attribute of FracBNN is its ability to binarize the floating-point input layer by novel thermometer encoding. It basically runs a dual-precision activation strategy through an extra computation of sparse binary convolutions if the relevant convolution layer has a direct impact on the accuracy. The binarization of the input layer with negligible performance degradation is reached by enriching the channels in the input layer. The proper process of a fractional convolution is executed by fetching the 2-bit feature maps and the 1-bit weights from the particular memory. To monitor the accuracy of FracBNN in a resource-limited case, an implementation on Xilinx Ultra96 v2 FPGA (AMD, Santa Clara, CA, USA) with the ImageNet dataset verifies its superiority in terms of accuracy and demonstrates its capability of real-time image classification. A new learning structure with a QNN architecture, namely n-BQ-NN [28], was proposed to handle deficiencies in resources and bandwidth on FPGAs. The proposed QNN model constrains the weights to the power of two, diminishing the necessary bandwidth for loading the weights. n-BQ-NN makes the inference on FPGAs more convenient by utilizing the shift operation instead of MAC operations. Additionally, a shift vector processing element (SVPE) array is developed to completely alter 16-bit multiplications within convolution operations on FPGAs. Performance evaluations reveal that ResNet, DenseNet, and AlexNet, when quantized by the proposed learning model, reach a similar performance accuracy to full-precision models. Practical evaluations on the Xilinx ZCU102 platform present a 2.9 times more rapid operation in inference as well as better energy consumption property.