# DFT-Low-Latency Bit-Slice Design of Discrete Fourier Transform
## 1 Introduction
Some studies have focused on FFT designs that achieve a trade-off between accuracy and performance by making a bit-width selection during each computational stage [13]. Two different procedures for word-length modification under a specific error margin have been proposed. They perform an approximated FFT evaluation, with the aim of implementing an area-limited design and a high operating frequency. The authors verified that those results without significant losses in quality are reached by applying these strategies to speech recognition when an appropriate word-length combination is achieved for all stages. Furthermore, a word-length adjustment strategy is used in [14] for the design of an FFT processor that can support up to 128k point operations. A fixed-point number design scheme is selected to reduce the requirements in terms of chip memory and logic resources, while still providing real-time performance of data processing. Improvements in efficiency are obtained in [15] by increasing the throughput per logic cell through the design of a circuit characterized by a high clock speed and a reduced number of clock cycles for FFT evaluation. The implemented structure has a systolic distributed-memory-based architecture, which was designed by adopting a true space-time mapping tool to obtain an optimal latency solution. Approximate arithmetic computation appears to be an effective solution for systems that exhibit an intrinsic error tolerance. In fact, in [16], a reduction in power consumption and in number of logic slices is obtained by adopting energy-efficient approximate multipliers and adders in the butterfly kernel. Furthermore, a low-power and reduced-area FPGA, a reconfigurable fixed-point implementation of FFT/IFFT, is indicated by [PERSON] et al. [17]. A good trade-off among area occupancy, power consumption, and throughput was obtained in [18] by adopting arithmetic-optimization techniques and complex approximate multipliers for the radix-2 butterflies implementation. Approximate half adders, approximate full adders, and approximate compressors are used for designing 8- and 16-point FFT/IFFT core processors that are suitable for multiple inputs and multiple outputs for orthogonal-frequency-division-multiplexing-based applications. Two CORDIC-based FFT/IFFT processors, which adopt one butterfly unit and are based on radix-2 and radix-4 architecture are designed. An in-place memory assignment is used for reducing the memory scheme complexity. Furthermore, an in-place architecture for computing the FFT of real-valued biosignals is indicated in [19] and compared with a fully pipelined, single-processing-element-based architecture for the FFT evaluation through the decimation in time radix-2 algorithm. A multiplication-free design of an efficient FFT architecture based on the radix-2 decimation in frequency method is indicated in [20]. The complex twiddle factors are replaced by the uniform Montgomery algorithm, which performs shift/addition operations instead of multiplications. A reduction in adders at the price of growth in the memory elements (as compared to the single-path delay feedback) characterizes the single-stream FPGA-optimized feedforward architecture conceived in [21], which performs the FFT through a radix-2 pipeline architecture. The authors outlined that their structure is suitable for FPGA implementation in short-pipeline FFT processors. A comparison among three pipelined FFT architectures, which implement radix-8, radix-4 single-path feedback and radix-4 single-path delay commutator, is indicated in [22]. The choice of which structure to adopt depends on the most strict requirement that needs to be meet. In fact, radix-4 single-path delay commutator is characterized by the lowest use of logical elements and memory bits, while radix-8 structure has the lowest average thermal power dissipation. Conversely, [PERSON] et al.