## 1 Introduction  
A portable electrocardiogram (ECG) monitoring system allows for the long-term identification of an individual's heart condition for the early detection of cardiovascular disease, such as cardiac arrhythmia and heart failure. In a conventional ECG measurement configuration with three or more electrodes, an additional reference electrode or the driven-right-leg (DRL) technique is widely used to reduce power line interference (PLI) [1; 2], however, in portable or wearable applications, a two-electrode configuration is preferred because of its portability and its long-term ECG monitoring ability [3; 4; 5; 6]. The main drawback of a two-electrode configuration is that the human body is severely affected by PLI when the floated body lacks a grounded electrode [7]. The frequency range and dynamic range of an ECG signal are approximately from 0.05 to 100 Hz and from 1 to 10 mV, respectively [8]. Considering that PLI has a frequency component of 50-60 Hz, over a few volts, the PLI can lead to serious problems in ECG monitoring. The generation of PLI and the saturation effect of the electrostatic discharge (ESD) diode is shown in Figure 1. The PLI is mainly generated by a displacement current, \(\mathrm{I_{PL}}\), through a capacitive coupling between a human body and the power line. Since the PLI can be more than a few volts, depending on the mismatch of skin-electrode contact impedance, the ESD diode of an input/output (I/O) pad can be put into a turned-on state by the PLI. A turned-on ESD diode makes an input CM signal reach the supply and ground level, which means that input CM voltage is out of the saturation range of the input transistor of the ECG amplifier. In this case, the ECG amplifier cannot amplify the raw ECG. To solve this problem, a discrete-time PLI reduction circuit was previously reported [9]. However, raw ECG signal processing prior to amplification in the discrete time region requires a wider bandwidth of the ECG amplifier, which has more than a few kHz. In terms of power consumption, a wider bandwidth feature leads to a shorter battery time. When the long-term use of a portable ECG monitoring device is required, this power consumption problem must be solved. The ECG amplifier is one of the key building blocks of the current consumption, common-mode rejection ratio (CMRR), input-referred noise, and gain in an entire ECG monitoring system. For long-term monitoring of an ECG, ultra-low current consumption is essential to maintaining the function of ECG measurement. To achieve accurate ECG signal acquisition, a low enough input-referred noise and high CMRR is demanded. An instrumentation amplifier (IA) is suitable for the ECG amplifier. A capacitively coupled IA (CCIA) is widely used for high-power efficiency and low noise [10; 11; 12]. In particular, the current-reused CCI can achieve a good noise efficiency factor (NEF) [13]. However, the CCI has a low input impedance, which can lead to excessive PLI and a lower CMRR. Since this problem degrades the ECG signal, the ECG amplifier demands a high input impedance while having low noise, a high CMRR, and ultra-low current consumption. This paper presents a PLI reduction technique with a current-reused current-feedback IA (CFIA) for ECG recording. To prevent exceeding the saturation range of an input transistor of the current-reused CFIA by PLI, the proposed circuit implements a continuous-time input CM current-feedback loop. Figure 1: Generation of power line interference (PLI) and the saturation effect of the electrostatic discharge (ESD) diode. The continuous-time input CM current-feedback loop consists of a CM detector, a window comparator, and current sinking and sourcing blocks. The continuous-time input CM current-feedback loop can clamp the input CM voltage to the saturation region of the input transistor of the current-reused CFIA. After the clamping procedure, the clamped input signal is amplified by the current-reused CFIA.