# A Fully Integrated Low-Power Multi-Mode RF Receiver for BDS-3/GPS
## 1 Introduction  
The completion of the BeiDou navigation satellite system-3 (BDS-3) in July 2020 marked a major milestone for China's satellite navigation system. BDS-3 is designed to provide global coverage, with 35 satellites in orbit, and it offers a range of positioning, navigation, and timing (PNT) services. The system is intended to offer a more reliable and accurate alternative to GPS and several advanced features, such as anti-jamming and anti-spoofing capabilities [1]. The ongoing application development, such as BeiDou+ and +BeiDou, is expected to drive the BDS industry growth further.  
With the broad deployment of the Internet of Things (IoT) systems, there is a growing need for navigation terminals/receivers capable of operating for extended periods with low power consumption and device costs. Currently, there are many receivers designed for the global positioning system (GPS), global navigation satellite system (GLONASS), the Galileo system, and so on [2; 3; 4; 5]. However, they are all incompatible with BDS-3 due to the different bandwidth requirements, operating frequencies, and demodulation algorithms. Until now, few CMOS-integrated receiver designs for the BDS-3 system have been reported on [6; 7; 8; 9].  
This paper presents a low-power, area-efficient receiver that is suitable for both BDS-3 and GPS in the L1 band (with a carrier frequency of 1575.42 MHz). Satellite signals from the two systems can be received simultaneously to improve localization speed and accuracy. Specifically, as BDS-3 does not have strict requirements on linearity and image rejection ratio (IMRR) in [10]; this work focuses more on the receiver performance regarding power optimization and area minimization. A simplified RF receiver system of this design is shown in Figure 1, which consumes only 4.8 mA with a small area of 0.345 mm\({}^{2}\) fabricated in a standard 55 nm CMOS technology. To achieve this performance, the major considerations are listed below.  
In the on-chip low-noise amplifier (LNA), the source inductor and gate inductor with high Q-value are realized using copper bonding wire. This improves in-band noise performance and saves space. LNA adopts a cascode amplifier structure with the LC resonant network as the load and features reused current, improving the gain and reducing power.  
Adopting the active balun amplifier (ACTBA) instead of the traditional passive balun to convert the single-ended signal into the differential signal not only improves the RF front-end gain but also reduces the gain-realization difficulty of the later-stage circuit, which is beneficial for achieving high gain and conserving system space. ACTBA employs current reuse to reduce power consumption.  
A GMT circuit is modified, which can save the intermediate frequency (IF) direct current (DC) blocking capacitors to reduce the insertion loss and area.  
Image suppression is realized by bandpass filter (BPF), and the later circuits only need to amplify and convert the in-phase channel signals, saving nearly half of the IF layout area.  
The rest of this paper is organized as follows. Section 2 analyzes the GPS and BDS-3 signal properties to check the feasibility of receiving both signals simultaneously, as well as the receiver requirements for the BDS-3 system. Section 3 describes the target specification of each sub-circuit of the receiver system, including cascaded gain, dynamic range, noise figure, linearity, and filter order. Section 4 elaborates on the architecture of the receiver and the circuit implementation. Section 5 shows the measurement results, followed by a conclusion in Section 6.