## 1 Introduction  
Reliability issues have become a vital concern for Very Large Scale Integration (VLSI) design due to the continued scaling of VLSI technology and supply voltage. Among these reliability issues, transient faults caused by environmental effects, such as electrical noise, particle strikes, and electromagnetic coupling, are primary failure mechanisms [1]. In contrast to permanent faults, transient faults are temporary deviations of a circuit's state from its correct or reference state. The occurrence of transient faults has certain random characteristics; therefore, statistical analysis methods are required to accurately analyze the effects of such faults on circuit performance [2]. In the past, environmental induced transient faults used to be a concern only in regarding memory because of the following two reasons. Firstly, the density of memory circuits is much higher than logic circuits, which makes the memory circuits contain the largest number and density of bits susceptible to transient fault. Secondly, the three masking factors affect the propagation of a transient fault through combinational circuit, which include logical masking, electrical masking and latching-window masking. However, in the last decade, supply voltage continues to diminish in value with current scaling trends, causing a decrease in the impact of these masking factors on logic circuits [3; 4]. Furthermore, the high density and high speed of VLSI circuits also make the digital logic circuit more susceptible to transient faults induced by noise [5]. This trend will become more severe as the feature size of Complementary Metal Oxide Semiconductor (CMOS) devices approaches 22 nm, or even smaller scales, in the near future. Therefore, it is critical to model, analyze, and mitigate the impact of transient faults on VLSI circuits. Existing transient fault mitigation methods can be generally classified into two categories: fault avoidance and fault correction methods. The first category generally exploits device fabrication processes to reduce the transient fault occurrence. These methods include the silicon-on-insulator process [6], the gate resizing strategy [7], and various other methods. The second category of methods functions at the circuit level or system level of abstraction to alleviate transient fault effects. Partial duplication [8], redundancy addition/removal [9], Delay Filtered Dual Interlocked storage Cell (DF-DICE) [10], and algorithmic noise tolerance (ANT) [11] are some typical methods used to address this issue. All of the above techniques suffer from area and energy overhead; therefore, to effectively and efficiently implement these mitigation methods, circuit designers require an accurate and fast transient fault modeling and analysis method to identify the part of a VLSI circuit that is most sensitive to transient faults. However, transient fault analysis has been difficult to implement due to the random characteristics of circuit design specifications, such as supply noise and input signal distribution. Therefore, statistical estimation methods are required to encapsulate all of these design conditions. Monte Carlo (MC) simulation is often applied to accomplish this task. However, the MC method suffers from an impractical computation cost due to the size of the circuits, and more efficient analysis methods are required. In addition to transient faults, aging effects, such as hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB), electro-migration (EM), and negative bias temperature instability (NBTI), are also major causes of VLSI reliability issues. Among these aging effects, NBTI is the main mechanism of circuit failure when the feature size approaches the 65 nm scale. NBTI occurs when positive-channel Metal Oxide Semiconductor (pMOS) transistors are negatively biased, which causes a shift in the threshold voltages (Vth) [12]. The reaction-diffusion (R-D) model is a widely used physical model for NBTI effect [13].