# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 6 Replacing LUTs by Embedded Memory Blocks  
As we have shown before, even a single EMB can replace a lot of LUTs and interconnections (Figure 5). To optimize the resulting FSM circuit, it is necessary to find a configuration \(\langle S_{A^{\prime}}^{*},t_{F}^{*}\rangle\) which allows us to obtain a single-level EMB-based FSM circuit. In this case, there are very important relations among the EMB characteristics (\(S_{A^{\prime}}^{*},t_{F}^{*}\)) and FSM parameters (L, N, and R). The LUT count of a LUT-based FSM circuit is not important for replacing LUTs by EMBs. An EMB is a coarse-grained element compared to a LUT. Thus, the transition from LUT-based FSMs to EMB-based FSMs is a transition from fine-grained to coarse-grained elements. This is similar to the transition from radio components (transistors, capacitors, resistors, inductors, and so on) to integrated circuits. Such a transition improves the final product quality (reducing the size, increasing the performance, reducing the power consumption, increasing the reliability) by reducing the number of interconnections. Also, there is a simplification of complex tasks such as the mapping, placement, and routing. Thus, we can expect the same effect from replacing LUTs by EMBs. All EMB-based FSM design methods originate in microprogram control units (MCUs). The idea of MCUs was proposed in 1951 by [PERSON] [132; 133]. The MCUs have been used to control the process of program execution in computers. The MCU design methods depend on the approach used for addressing the microinstructions (MIs). One of the first addressing methods is compulsory addressing [134; 135]. To design an MCU circuit, it is necessary to represent an initial STG as a microprogram. A microprogram is an ordered set of microinstructions kept into a special control memory (CM). A microinstruction location into CM is determined by its address. A format of an MI with compulsory addressing includes four fields [134]. The field \(FY\) includes a code of the collection of outputs (COs) executed in a particular cycle of MCU performance. The field \(FX\) includes a code \(K(x_{l})\) of an FSM input \(x_{l}\in X\) to be checked for determining the transition address. The field \(FA0\) includes a transition address for the case when \(x_{l}=0\). The field \(FA1\) includes a transition address for the case when \(x_{l}=1\). For unconditional transitions, the field \(FX\) is empty; in this case, the next address is determined by the contents of \(FA0\). The following rule determines the next microinstruction address:  
\[A^{t+1}=\left\{ \begin{array}{ll}[FA0]^{t}&\text{if}&[FX]^{t}=\emptyset;\\ [FA0]^{t}&\text{if}&x_{e}^{t}=0;\\ [FA1]^{t}&\text{if}&x_{e}^{t}=1.\end{array} \right. \tag{16}\]  
In (16), \(t=0,1,2,\dots\) is a cycle time, \(A^{t+1}\) is the next address (an address of an MI executed in the cycle \(t+1\)), \([FX]^{t}\), \([FA0]^{t}\), \([FA1]^{t}\) are the contents of the corresponding fields in the current operation cycle, \(x_{l}^{t}\) is a value of an FSM input determined by the field \([FX]^{t}\). The unconditional transition is determined by the first line of (16). The following blocks represent the circuit of an MCU with compulsory addressing: block addressing (BA), register of microinstruction address, RG, control memory, and control flip-flop (TF). A structural diagram of an MCU is shown in Figure 23.  
Figure 23: Structural diagram of an MCU. The MCU (Figure 23) operates in the following manner. If \(Start=1\), then (1) the first address of the microprogram is loaded into RG and (2) \(Fetch:=1\). If \(Fetch=1\), then the current MI is read from the CM. At the instant \(t\), a microinstruction \(MI^{t}\) is fetched from CM. Its field \(FY\) is transformed into outputs \(y_{n}\in Y\). They enter other blocks of the digital system. The address part of MI (fields FX, FA0, FA1) enters the BA, together with new values of FSM inputs. According to (16), BA generates variables \(T_{r}\in T\) representing an address of the MI to be executed in the next cycle of MCU operation.