# Charge Carrier Distribution in Low-Voltage Dual-Gate Organic Thin-Film Transistors
## 3 Results and Discussion
This excellent control of carrier density in the DG system should contribute to obtaining the steeper \(SS\) than those from the single-gate system. \begin{table}
\begin{tabular}{c c c c c c c} \hline
**Device** & \(\mu_{\text{sat}}\) **(cm\({}^{2}\)/Vs)** & \(V_{\text{TH}}\) **(V)** & \(I_{\text{ON}}\) **(\(\mu\)A)** & \(SS\) **(V/dec)** & \(\mu_{\text{lin}}\) **(cm\({}^{2}\)/Vs)** & \(I_{\text{ON}}\) **(nA)** & \(SS\) **(V/dec)** \\
**Structure** & \multicolumn{4}{c}{\(V_{\text{DS}}=-5\) V, V\({}_{\text{GS}}>-5\) V} & \multicolumn{4}{c}{\(V_{\text{DS}}=-0.1\) V, V\({}_{\text{GS}}>-2\) V} \\ \hline BG & 0.012 \(\pm\) 0.002 & 1.5 \(\pm\) 0.1 & 0.23 \(\pm\) 0.04 & 0.5 \(\pm\) 0.3 & 0.012 \(\pm\) 0.002 & 6.4 \(\pm\) 0.8 & 1.6 \(\pm\) 0.3 \\ TG & 0.038 \(\pm\) 0.005 & 0.68 \(\pm\) 0.06 & 1.5 \(\pm\) 0.2 & 1.4 \(\pm\) 1.0 & 0.032 \(\pm\) 0.003 & 19 \(\pm\) 1 & 1.4 \(\pm\) 0.2 \\ DG & 0.050 \(\pm\) 0.013 & 0.42 \(\pm\) 0.04 & 1.9 \(\pm\) 0.2 & 0.3 \(\pm\) 0.1 & 0.047 \(\pm\) 0.011 & 24 \(\pm\) 2 & 0.4 \(\pm\) 0.1 \\ \hline \end{tabular}
\end{table} 
Table 2: Electrical Properties of the Fabricated OTFTs. Figure 3: Transfer characteristics of (a) bottom-gate, (b) top-gate, and (c) dual-gate OTFTs obtained from the experimental and numerical simulation at \(V_{\text{DS}}=-0.1\) V. The channel dimensions were \(W/L=740\)\(\mu\)m/7 \(\mu\)m.  
Figure 2: Transfer characteristics of fabricated (a) bottom-gate (BG), (b) top-gate (TG), and (c) dual-gate (DG) OTFTs at \(V_{\text{DS}}=-5\) V. Output characteristics of fabricated (d) bottom-gate, (e) top-gate, and (f) dual-gate OTFTs. Gate-source voltages were from 0 to \(-5\) V in \(-0.5\) V step. The channel dimensions were \(W/L=740\)\(\mu\)m/7 \(\mu\)m.  
We note that the difference in threshold voltage between three device structures needs to be taken into account: however, it is well known that the determination of threshold voltage from experimental transfer characteristics is not always accurate in organic field-effect transistors [27]. On the other hand, in this simulation, the flat band gate voltages, which has a similar implication of threshold voltage, were \(-0.2\) V for all three device structures: the comparison of carrier density at a same gate voltage is reasonable in this simulation. Moreover, the charge carrier distributions at on/off state were visualized in Figure 4d-i. It is clear that DG device could control the carrier density well, as opposite to single-gate devices. For all the gate structure devices, the accumulation channel whose thickness was estimated to be about 2-nm-thick [28] was formed at on-state. In particular, for the DG device, the channel was formed at both bottom- and top-gate side, and carrier density of this dual-channel was estimated to be <3.8 \(\times\) 10\({}^{23}\) m\({}^{-3}\), which was higher density than that of single-gate devices (<2.5 \(\times\) 10\({}^{23}\) m\({}^{-3}\)). This dual-channel obviously flow current more than the single-channel, while \(I_{\text{ON}}\) for the DG devices (\(I_{\text{ON}}\)DG) was approximately equivalent to the sum of \(I_{\text{ON}}\) for the BG devices (\(I_{\text{ON}}\)BG) and \(I_{\text{ON}}\) for the TG devices (\(I_{\text{ON}}\)TG), \(I_{\text{ON}}\)DG\(\approx\)\(I_{\text{ON}}\)BG\(+\)\(I_{\text{ON}}\)TG, according to Table 2.  
For a discussion about the reason why mobility for the DG devices was higher than that of the single-gate devices, potential in the channel were simulated, as shown in Figure 5a,b. Potential in the source and drain region was pinned at 0 V and \(-0.1\) V, respectively. Gate voltage affected the slope of the channel potential and voltage drop at source/channel interface and channel/drain interface.