## 4 System Implementation and Simulation Results
### Efficiency Analysis  
To analyze the efficiency of the converter, its behavior is studied by varying the load, output voltages, and operating temperature. The values of the input active power (\(P_{i}\)), converter losses (\(P_{DC-DC}\)), overall system efficiency (Tot.Eff. ), and the efficiency of the converter alone (DCDC.Eff) were calculated using Equations (8)-(11). The input power is \(P_{i}\), i.e., the sum of the load power \(P_{o}\) plus the loss power of the LC filter (\(P_{fLC}\)), gate-drivers (\(P_{G.Driver}\)), and the converter losses (\(P_{DC-DC}\)). Then, we have the following:  
\[P_{i} =P_{fLC}+P_{G.Driver}+P_{DC-DC}+P_{o} \tag{8}\] \[P_{DC-DC} =P_{Cond.}+P_{Sw.} \tag{9}\]  
Two efficiencies are analyzed in this paper, \(Tot.Eff\) and \(DCDC.Eff\). Thus, we have the following:  
\[Tot.Eff =100\frac{P_{o}}{P_{i}} \tag{10}\] \[DCDC.Eff =100\frac{P_{o}}{P_{i}-P_{fLC}-P_{G.Driver}} \tag{11}\]The graphs in Figure 9 are obtained by varying the load for an output voltage of 12 V and a temperature of 25 \({}^{\circ}\)C. These graphs show that the maximum efficiency is 86.6% with a load of 120 mA, and with a load of 300 mA, the efficiency is 84.83%. At this operating point of 300 mA, the power consumed by the gate drivers accounts for 1.58% of the input power. The total static power loss in the power transistors amounts to 13.57% of the input power, with 9.93% attributed to \(M_{1}\) conduction loss, 2.35% to \(M_{1}\) switching loss, 1.14% to \(M_{2}\) conduction loss, and 0.15% to \(M_{2}\) switching loss, as shown in Figure 10. This indicates that the on-resistances of the PMOS transistors contribute most significantly to the losses. The greater loss contribution from \(M_{1}\) is explained by their lower hole mobility and therefore their higher on-resistance, despite consuming a much greater area. Also, Figure 2 shows that the drain-source current in \(M_{1}\) is positive, and hence, non-negligible switching losses appear. In the case of \(M_{2}\), the drain-source current is negative during conduction, which means that the switching losses due to the body diode are negligible. Figure 8: Steady-state of relevant input and output signals for a single channel. (**a**) Drain-source currents for \(M_{1}\) and \(M_{2}\) (**top left**), inductor current (**top right**), gate-source and drain-source voltages of \(M_{2}\) (**bottom left**), and gate-source and drain-source voltages of \(M_{1}\) (**bottom right**). (**b**) Input and output voltages. Next, by sweeping the output voltages while holding a load of 300 mA, in Figure 11, it can be observed in the graph that, as the output voltage decreases, both the output power and efficiency also decrease. Thus, the operating point with the best performance is at a 12 V output voltage. Figure 10: Power loss breakdown in power transistors and gate driver circuit, representing a total of 15.15% of the input power. Figure 9: Operation point \(V_{o}=12\) V, \(T=25\,^{\circ}\)C; (**a**) efficiency versus current (**left**), input and output power versus current (**middle**), gate driver losses versus current (**right**). (**b**) Losses versus current of \(M_{2}\) (**left**), and \(M_{1}\) (**right**). The temperature analysis of the graph in Figure 12 illustrates the converter's performance under three different scenarios during the temperature analysis. The first scenario involves adjusting the dead times (\(AdjDT\)) dynamically according to the operating temperature. The second scenario features fixed, asymmetric dead times (\(AsymDT\)) maintained consistently across the entire temperature range. The third scenario examines fixed, symmetric dead times (\(SymDT\)) that also remain constant throughout the temperature spectrum. This analysis is crucial in reducing converter losses caused by body diode conduction in \(M_{2}\)[48; 49] due to the dead time.