# Research on Clock Synchronization of Data Acquisition Based on NoC
## 4 The Implementation of Clock Synchronization
### The Implementation of Ddmtd
\[phase_{sample}=\frac{(i-1)*A*0.667}{T_{clk}} \tag{11}\]  
(2) Phase shift of slave clock  
After obtaining the phase value adjust_value that the slave clock needs to be shifted by, the changes to the phase of the slave clock are made by using the CMT, a clock management unit in the above-mentioned series of FPGA. The clock management module includes the mixed-mode clock manager (MMCM) and the PLL [35]. MMCM can produce a clock with high precision and low jitter, and can also dynamically adjust the clock phase. It has the following two phase-shift modes:  
Figure 11: The phase relationship between master (M) and slave (S) clocks. The first scenario is that the phase of the master clock is in front of that of the slave clock. The second one is that the phase of the slave clock is in front, and the third one is that the master and slave clocks are in the same phase. Static phase-shift (SPS) mode  
VCO can provide eight phase-shift clocks with a 45-degree phase interval. All these clocks are independent and programmable. The higher the frequency of VCO, the higher the accuracy of its phase-shift resolution, as shown in Equation (12). In Equation (12), \(f_{vco}\) represents the frequency of the VCO, \(f_{in}\) represents the frequency of the input clock from the crystal oscillator, and period represents the period of this frequency. \(M\) and \(D\) are two multi-bit counters, as shown in Equation (13). The frequency of the VCO can be calculated by designing the ratio of \(M\) and \(D\) and knowing the frequency of the input clock \(f_{in}\). \[SPS=\frac{1}{8f_{vco}}*period=\frac{D}{8*m*f_{in}}*period \tag{12}\]  
\[f_{vco}=f_{in}*\frac{M}{D} \tag{13}\]  
IFPS mode has linear phase shift, and its phase-shift resolution only depends on the VCO frequency. In this mode, the phase shift can be cycled by a linear increment in \(\Delta\Phi_{step}\). Its \(\Delta\Phi_{step}\) satisfies Equation (14):  
\[\Delta\Phi_{step}=\frac{1}{56f_{vco}} \tag{14}\]  
Assuming the frequency of VCO is 1000 MHz, then the phase-shift resolution \(\Delta\Phi_{step}\) is 17.8 ps. The phase offset can be configured as a fixed value, or the phase can be dynamically incremented or decremented in the application after the configuration is complete. But in fixed phase-shift mode, dynamic phase-shift port cannot be used. In addition, the dynamic phase shift of the module is controlled by psen, psincdec, psclk, and psdone. psen represents the enabling signal that controls the phase shift; psincdec represents a signal that controls an increasing or decreasing phase; psclk represents the driver clock used for phase-shift control signal; psdone represents the phase-shift completion marker signal. The clock output of the MMCM is dynamically increasing or decaying from the initial phase or the phase executed before. The psen, psincdec, psclk, and psdone signals are synchronized, and the signal timing is shown in Figure 12.  
The workflow is as follows: if there is a psen pulse signal in a psclk cycle, the phase shift will be started. The phase moves forward (increasing). or backward (decreasing), when psincdec is at the low or high level, with each phase shift \(\Delta\Phi_{step}\) being 1/56 of the VCO frequency. When the phase shift is completed, psdone outputs a high pulse for one clock cycle, and then, produces the next phase shift enabling psen pulse. It takes 12 psclk cycles to complete a phase shift. After receiving the adjust_value sent from the master-slave clock verifier, the IFPS mode of the MMCM is adopted to implement the phase shift of the slave clock. When the  
Figure 12: MMCM dynamic phase-shift timing. crystal oscillator clock of the router is 50 MHz, the frequency of the VCO is 1000 MHz, and the stepping length of the clock phase shift is 17.8 ps. The MSB of adjust_value is assigned to psincdec to indicate forward or backward movement of the phase, and the falling edge signals (neg_s or neg_m) of the mixed output signals are assigned to psen as phase-shift-enabling signals.