# Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA
## 2 ECC Background over \(GF(2^{m})\)
## 3 Proposed Flexible Crypto Accelerator

The architecture of our proposed elliptic-curve processor over \(GF(2^{571})\) is shown in Figure 1. The critical building-blocks are curve parameters, a memory unit, an arithmetic unit and a dedicated control circuit. The red dotted lines determine the control signals generated by the control unit. A blue dotted line shows the scalar multiplier, i.e., \(k\), value inputted from outside to the processor. A KeyReg is a 571-bit buffer that holds the scalar multiplier (or a secret key) value to execute the Algorithm 1 for PM computation. Before describing the architectural units of our proposed PM design, we have described the I/O pins and control signals of our PM design in Table 1. Then, in the following text, we have provided the architectural details of the building-blocks of our proposed accelerator. Figure 1: Our large field-size elliptic curve cryptographic processor. ### Curve Parameters Unit

The objective of the curve parameter unit is to load the curve parameters and constants to implement the PM operation of ECC. Moreover, the flexibility in our architecture is achieved using the curve parameters unit. The flexibility means that the users can load different curve parameters and a scalar multiplier to our proposed processor for PM computation. The internal architecture of our curve parameter unit includes three 571-bit registers (i.e., \(x_{p}\), \(y_{p}\) and \(b\)) to load the coordinate of initial point \(P\) and a curve constant value as the input from outside. Moreover, the output of the curve parameter unit depends on a \(3\times 1\) multiplexer (not shown in Figure 1) to select an appropriate operand for the arithmetic unit as input. The corresponding values for \(x_{p}\), \(y_{p}\) and \(b\) buffers are selected from the standardized NIST document [9]. ### RegFile

It is essential to mention that the curve parameter and RegFile units are utilized for different purposes. Previously, we (already) described that the curve parameter unit loads the curve parameters and constant values for the Weierstrass model of ECC. These buffers never need to modify during the entire computation. Hence, these initial values can be used (at any time) during the entire PM execution. On the other hand, the objective of RegFile is to keep the initial, intermediate and final generated outputs. It means that the RegFile is mandated to update during the PM computation. Therefore, we used an \(8\times m\) size of a register array (RegFile). The internal design of the RegFile unit contains two \(8\times 1\) sizes of multiplexers and one \(1\times 8\) size of a demultiplexer. The multiplexers allow us to read two 571-bit operands from the register array and a demultiplexer updates the value of the specified register for writing back. For read/write operations, the related control signals are the responsibility of the control unit to generate. ### Arithmetic Unit

An arithmetic unit is mandated to implement modular finite field operations such as addition, multiplication, square, reduction and inversion. As observed in Figure 1, the arithmetic unit consists of three routing multiplexers (M1, M2 and M3), an adder (ADD), a polynomial multiplier (MULT) and a square (SQE) unit. The design details of these circuit components are as follows. _Routing multiplexers (M1, M2 and M3)._ The routing multiplexers select the right operand for the modular arithmetic operators and RegFile block. The multiplexers M1 and M2 select an appropriate operand as the input to adder, multiplier and square units. The multiplexer M3 selects the outputs of these modular operators to be written back on the RegFile. The control unit generates the control signals to operate multiplexers M1, M2 and M3. _Modular addition (ADD)._ The realization of a modular adder over \(GF(2^{m})\) field is simple. It needs bitwise exclusive (OR) gates for implementations. Therefore, for two 571-bit operands, two-input 571 exclusives (OR) gates are needed [14; 15; 21]. It takes one clock cycle for implementation.