## 3 Current Status of the Circuit Component in the MMW Regime
### Power Amplifier (PA)  
In these two decades, the published works about MMW PAs are mainly about enhancement of output power and gain with power combining, reduction of passive components and neutralization of the parasitic capacitances with inductive components like transmission line, and the improvement of efficiency by linearization techniques [63; 64; 65; 66; 67; 68; 69; 70; 71; 72]. The power handling capability decreases with the downscaling of the advanced CMOS technologies owing to the reduction in breakdown voltage of the CMOS transistors. This leads to the significant decrement in output power. In order to achieve higher output power, the transistors can be combined by direct shunt combining 3-dB couplers and transformers [73; 74; 75; 76; 77; 78; 79; 80; 81]. Direct shunt combining is the simplest combining architecture to combine the current of each PA cell, in turn; the output power is enlarged. However, it is more difficult to match the output with a number of combined transistors owing to lower impedance. The lower output impedance at the output of PA, the more difficult to match with the system impedance (50 \(\Omega\)). A solution for this issue is to design the pre-matching network behind the combined transistors but the area is huge while the combining number is high. At MMW frequencies, binary combining is popular because the phase of each transistor should be equal to maximum the output power. An effective mechanism to double the output power is to exploit 3-dB coupler with the same PA units and 3-dB couplers. In-phase 3-dB couplers (e.g., Wilkinson coupler) and 90\({}^{\circ}\) 3-dB couplers (e.g., Lange coupler, branch-line couplers, and a pair of 3-dB coupled-lines with 90\({}^{\circ}\) electrical length) are successfully adopted in PA combining to gain high output power even with multilevel 3-dB couplers. Wilkinson coupler [82], which can divide input power equally in-phase into the input ports of two amplifiers and combine the output power at the two output ports. It is one simplest structure, which is composed of two quarter-wavelength lines and one isolation resistor, in turn, results in a good phase and amplitude balance at input and outputs. A common way to form a quadrature coupler is to use two adjacent quarter-wavelength transmission lines. For example, in CMOS technology, broadside coupled transmission lines are usually adopted owing to the multilevel dielectric and metal layer environment above the lossy silicon substrate. Thus, broadside-coupled quadrature couplers can be implemented using two metal layers with the thin dielectric between them. Broadband 3-dB coupler is achieved by  
Figure 4: Measured minimum noise figure of the recent published MMW SiGe LNAs. Data taken from [58; 59; 60; 61; 62]. adjusting the overlap area of the coupled lines. A balanced amplifier [83] takes advantage of the quadrature couplers to achieve good input and output return losses. The aforementioned combing techniques have some limitations. The chip size is at least doubled because the identical PA units are used. In addition, the losses of the couplers become severe when multi-stage PA units are utilized. Since the quarter-wavelength lines are exploited, the 3-dB couplers usually have large size. Currently, transformers are popular in MMW PA design [64, 72, 81, 84] since dc voltage can be fed to the transistors via this transformer, bypass capacitors or RF chokes can be eliminated as well as RF grounding can be achieved with the virtual ground. By using transformer combing, a large number of on-chip components are eliminated. Consequently, the PA can be realized with a compact size; the higher output power can be achieved. One issues for transformer combining is that the optimum load impedance for high output power will be very low when a lot of transistors are combined. Another is the higher insertion loss due to the multi-mental layers, especially in CMOS technologies. The top metal layer is thicker and hence the lower loss it has compared with the other metal layers in CMOS technologies.