## 2 Architecture of Proposed SSPLL
### Loop Analysis  
A linear phase-domain model of the proposed SSPLL system is shown in Figure 2. We can treat this model as a time-continuous system if the bandwidth (BW) of the PLL \(f_{BW}\) is an order of magnitude smaller than that of the reference clock frequency \(f_{REF}\)[28] (called \"Gardner's Limit\").  
Figure 1: Conceptual architecture of proposed hybrid dual path SSPLL.  
Unlike the traditional SSPLL, the proposed system has two paths as mentioned above. The relationship of these two paths determines the stability of the loop and phase noise performance of the system. Hence, we need to analyze the transfer function first.  
In the P-path, to simplify the calculation, a single-end structure of the MSSF is analyzed in Figure 3, where \(C_{VAR}\) is the capacitance of the varactor in the VCO.  
As a continuous-time approximation, since the Gardner's Limit is assumed to be satisfied, the switched capacitor \(C_{1}\) can act as a series-equivalent resistor \(R_{1}\):  
\[R_{1}=\frac{1}{f_{REF}\cdot C_{1}} \tag{2}\]  
where \(f_{REF}\) is the reference clock frequency. The gain of the MSSF in s-domain is given as Equation (3).  
\[F_{1}(s)=\frac{sR_{2}C_{VAR}+1}{s^{3}R_{1}R_{2}^{2}C_{2}C_{VAR}^{2}+s^{2}R_{2}C _{VAR}(2R_{1}C_{2}+R_{1}C_{VAR}+R_{2}C_{VAR})+s(R_{1}C_{2}+R_{1}C_{VAR}+2R_{2} C_{VAR})+1} \tag{3}\]  
where we choose \(C_{1}\) = 64 fF, \(C_{2}\) = 16 fF, \(C_{VAR}\) = 10 fF and \(R_{2}\) = 21 k\(\Omega\) to push the poles and zeros far away from \(f_{BW}\) and the gain of the MSSF can be approximated as 1. Thus, the open-loop gain of the P-path is obtained as follows:  
\[G_{PP}(s)\approx A_{VCBUF}\cdot 1\cdot\frac{K_{VCO,P}}{s} \tag{4}\]  
where \(A_{VCBUF}\) is donated as the amplitude of the output signal from the voltage-controlled buffer.  
Then, in the I-path, we can get the gain of the SSCP directly from the introduced modeling in the traditional SSPLL [22]:  
\[\beta_{SSCP}=A_{VCBUF}\cdot g_{m}\cdot\frac{\tau_{PULL}}{T_{REF}}=A_{VCBUF} \cdot g_{m}\cdot K_{T} \tag{5}\]  
where \(g_{m}\) is the transconductance of the input transistor of the SSCP, \(\tau_{PULL}\) is the pulse width of the pulser, \(T_{REF}\) is the period of the reference clock. Moreover, the transfer function of the I-path low pass filter (LPF) can be easily acquired:  
\[F_{2}(s)=\frac{sR_{int}C_{int2}+1}{s^{3}R_{int}^{2}C_{int1}C_{int2}^{2}+s^{2}R_ {int}C_{int2}(2C_{int1}+C_{int2})+s(C_{int1}+C_{int2})} \tag{6}\]  
Figure 3: Single-end structure MSSF.  
Figure 2: Linear model of the proposed SSPLL.  
where \(C_{int1}\) is the integral capacitor, and \(R_{int}\) and \(C_{int2}\) are the low pass resistor and capacitor, respectively. We choose \(C_{int1}\gg C_{int2}\) and \(1/2\pi R_{int}C_{int2}\gg f_{BW}\) to get \(F_{2}(s)\approx 1/sC_{int1}\). Hence, the open-loop gain of the I-path is given as:  
\[G_{IP}(s)\approx A_{VCBUF}\cdot g_{m}\cdot K_{T}\cdot\frac{K_{VCO,I}}{s^{2}C_{ int1}}. \tag{7}\]  
If we set \(K_{VCO,P}=K_{VCO,I}=K_{VCO}\), the system open-loop gain is:  
\[G_{SSPLL}(s)=G_{PP}(s)+G_{IP}(s)=\frac{A_{VCBUF}\cdot K_{VCO}}{s}\cdot\left(1+ \frac{g_{m}K_{T}}{sC_{int}}\right) \tag{8}\]  
where a zero appears at \(f_{z}=g_{m}K_{T}/2\pi C_{int1}\).  
In order to ensure the stability of the SSPLL, the zero needs to be smaller than \(f_{BW}\). In other words, \(g_{m}K_{T}\) should be much smaller than \(sC_{int1}\) around the angular frequency of the reference \(\omega_{BW}\), which means that \(G_{PP}(s)\gg G_{IP}(s)\). Hence, \(f_{BW}\) is determined by the P-path.