## 4 Evaluation and Implementation
### Hardware Implementation  
The proposed AV-ASA-based SFIR is implemented using VHDL and synthesized with Synopsys design complier (DC) using the SMIC 90 nm library, shown as Table 1. The bipolar scheme [6] and two-line scheme [2] are also listed as a comparison with 64 filter taps and 256-length bit stream. Furthermore, the binary fix-point FIR filter is also synthesized with the same CMOS technology and listed in Table 1.  
\begin{table}
\begin{tabular}{l c c c c c c c} \hline \hline \multirow{2}{*}{**SFIR Schemes**} & **Bipolar** & **Two-Line** & \multirow{2}{*}{**MUX SFIR**} & **Binary** & \multirow{2}{*}{**ASA-SFIR**} & **AV-ASA-SFIR** \\  & **SFIR** & **[**2**]** & **[**12**]** & **(Fix-Point)** & & **(This Work)** & **(This Work)** \\ \hline CMOS Tech. & 90 nm & 90 nm & 90 nm * & 90 nm & 90 nm & 90 nm & 90 nm \\ Filter Tap & 64 & 64 & 64 & 64 & 64 & 64 & 64 \\ Bit Stream Length (bits) & 256 & 256 & 256 & – & 256 & 256 & 16 \\ Fix-Point Width (bits) & – & – & – & 9 & – & – & – \\ SNR (dB) & \(-4.41\) & 17.21 & – & 23.51 & 31.38 & 37.40 & 25.64 \\ Error (\(\times 10^{-2}\)) & 34.42 & 2.8 & 2.38 & 1.5 & 0.39 & 0.2 & 0.85 \\ Clock (MHz) & 800 & 750 & – & 200 & 750 & 750 & 750 \\ Area (um\({}^{2}\)) & 18,304 & 44,800 & \(\approx\)14,000 ** & 229,452 & 49,286 & 59,121 & 59,121 \\ Power (mW) & – & – & – & 2.40 & 1.913 & 2.31 & 2.31 \\ Latency (ns) & 320.00 & 341.32 & – & 5.00 & 341.32 & 341.32 & 21.33 \\ Throughput (MSample/s) & 3.13 & 2.92 & – & 200.00 & 2.92 & 2.92 & 46.88 \\ Hardware Efficiency & 0.17 & 0.07 & – & 0.87 & – & – & 0.79 \\ \hline \hline \end{tabular}  
* Original 45 nm results is converted to 90 nm technology by \(\times 4(90/45)^{2}\) according to [19] for a fair comparison. ** Only 4, 8, 16, 32, 33, 100, 300-tap FIR filters are reported in [12], the area consumption of 64-tap filter is derived approximately.  
\end{table}
Table 1: Implementation results comparison.  
Firstly, all of the stochastic filters take lower area cost compared with the binary filter due to the simple hardware architecture. The Bipolar, Two-Line, MUX, and AV-ASA schemes show 92%, 80%, 94%, and 74% area reduction compared to binary scheme, respectively. However, the processing latency is much higher than that of binary filter, which is caused by the long bit streams. Using the adaptive scaling algorithm and antithetic variable method, the proposed AV-ASA-SFIR scheme (16 bit stream length) achieves comparable hardware efficiency with respect to binary FIR filter, where the hardware efficiency is defined as throughput-to-area ratio as  
\[\text{Hardware Efficiency(MS/s/mm}^{2})=\frac{\text{Throughput(MS/s)}}{ \text{Area(mm}^{2})}. \tag{19}\]  
Among the SFIR schemes, the two-line scheme greatly improves the SNR performance from \(-4.41\) dB to \(17.21\) dB, with \(2.4\) times chip area consumption overhead, compared with the bipolar scheme. The main hardware cost lies on the two-line stochastic adder (TSA) module. The proposed ASA-SFIR scheme gains \(14.17\) dB on SNR performance compared with the two-line scheme, with only \(10.01\%\) more hardware cost. Benefitting from the simple architecture of the SM and RSM module, the proposed design does not increase the critical path delay, achieving the same clock frequency as the two-line scheme. Moreover, combining the ASA and AV method, the AV-ASA-SFIR scheme gains \(20.19\) dB on SNR compared with the two-line scheme, with \(32\%\) area consumption overhead. Due to the significant improvement on accuracy, the proposed design require much shorter bit stream length compared with the existing stochastic FIR filters and shows advantages on processing latency. Note that the hardware architecture of the proposed design requires no change when modifying the bit stream length to achieve a trade-off between accuracy and latency.