# All-Digital Computing-in-Memory Macro Supporting FP64-Based Fused Multiply-Add Operation
###### Abstract
Techniques for performing in-situ arithmetic in SRAM arrays create efficient data mapping and reduce data movement. The Neural Cache architecture is capable of fully executing convolutional, fully connected, and pooling layers in-cache, which reduces power consumption by 50% over CPU. Ref. [21] presented an energy-efficient ping-pong CIM macro enabling simultaneous computing and weight update operations. The digital-predictor-assisted adaptive 0/2/4b ADC is employed to support accurate inference on practical datasets. A set-associate block-wise zero-skipping architecture is adopted, which skips zero-valued activations and weights to reduce power, storage, and execution time. Ref. [22] presented a 64 kb digital CIM macro using a one-read and one-write (1R1W) 12T bit-cell. The digital CIM macro can realize simultaneous MAC and write operations and wide- range dynamic voltage-frequency scaling due to the 12T cell's 1R1W functionality and low-voltage operation. By optimizing the circuit architecture and layout topology, this macro obtains further improvements in power-performance-area (PPA). Recently, digital CIM-based floating-point (FP32) arithmetic has received wide attention. Ref. [23] presented a 28 nm reconfigurable floating-point/integer digital CIM processor, which is designed based on an in-memory alignment-free floating-point MAC pipeline that interleaves exponent alignment and integer mantissa. Both inputs and weights are pre-aligned to their local maximum exponents, which makes CIM focus on only MAC acceleration. A bitwise in-memory both multiplication architecture is designed with partial-product recoding in the CIM processor to reduce cycle counts and bitwise multiplications by nearly 50%. The CIM processor implements hierarchical and reconfigurable in-memory accumulators to enable flexible support of brain floating-point (BF16)/single-precision floating-point (FP32), and integer 8/16 (INT8/16) in the same CIM processor. The results of [23] proved that the digital CIM supporting floating-point arithmetic is competent in MVM accelerators for hyperscale scientific computing. However, there is currently no digital CIM accelerator that can support FP64 arithmetic due to its computing complexity. Targeting the above limitations, this work proposes an all-digital CIM macro DCIM-FF. Different from the analog circuit structure of [11; 12], DCIM-FF adopts a digital circuit structure without extra overhead caused by ADC/DAC, and thus has a higher signal-to-noise ratio. Moreover, [22] can only support multiplication and addition operations of fixed-point numbers, while DCIM-FF can support floating-point fused multiply-add operation with a wider range of calculations. Compared with [23], DCIM-FF can support floating-point arithmetic with higher precision, and the feature of supporting complicated floating-point operations combined with the low power consumption characteristics of CIM makes DCIM-FF more suitable for scientific computing. This paper presents a novel all-digital CIM macro **DCIM-FF** to complete a FP64-based fused multiply-add (FMA) operation for the first time. The power consumption of floating-point FMA operation is mainly determined by the multiplication of integer mantissa. This work proposes an improved FMA algorithm that can match the CIM macro perfectly to accelerate the integer mantissa multiplication in FP64-based FMA operation. **DCIM-FF** is able to provide correct rounded implementations for normalized/denormalized inputs in round-to-nearest-even mode and round-to-zero mode, respectively.