# Frequency-Bounded Matching Strategy for Wideband LNA Design Utilising a Relaxed SSNM Approach
## 5 MMIC Implementation  
To demonstrate the practical application of the relaxed SSNM condition and the design strategy outlined in Section 3, a three-stage LNA MMIC operating in the Ka-band (28-34 GHz) was designed. The circuit structure, shown in Figure 12, utilised ideal microstrip lines initially, which were then replaced by equivalent components available  
Figure 11: Design-methodology flow chart for a three-stage LNA MMIC.  
in the WIN PQ07-0C GaAs process. The PQ07-0C process, provided by WIN, features 0.15 \(\upmu\)m GaAs PHEMT transistors available in both E-mode and D-mode. E-mode HEMTs are optimised for single-supply LNAs and PAs, whereas D-mode devices are primarily intended for PA and switch applications. Reliability testing recommends operating the PQ07-0C process at 4 V. Deep UV lithography enables the fabrication of high-voltage \(f_{\mathrm{T}}\) transistors suitable for various markets and applications. The process supports two metal layers, dielectric crossovers, precision resistors (50 \(\Omega\)/sq and \(>\)4 k\(\Omega\)/sq), PN diodes for electrostatic discharge (ESD) protection, and options for high-performance packaging, including hot vias and Cu-pillar bumps. These features contribute to a moisture-robust platform.  
Source degeneration inductors, shown in Figure 12, were replaced with equivalent transmission line models provided by the foundry. This approach helps reduce the area and unwanted parasitic losses, while still achieving the desired feedback performance.  
For this LNA MMIC, E-mode PHEMT transistors with a gate geometry of 4 \(\times\) 25 \(\upmu\)m were selected due to their low noise figure characteristics. The first two stages are optimised for minimum noise and biased with gate voltages of 0.6 V and 0.65 V, respectively. The third stage is designed for high gain, with a gate bias set to 0.7 V.  
Figure 13 shows a microphotograph of the fabricated MMIC chip. The layout adheres to best practice for mm-wave design in the 0.15 \(\upmu\)m GaAs process, featuring compact transistor placement, carefully routed matching networks, and well-designed RF input/output pads for on-wafer probing. The chip footprint measures approximately 2.5 \(\times\) 3.4 mm\({}^{2}\), demonstrating the integration of the wideband relaxed SSNM design approach in a practical MMIC.  
The MMIC's performance was evaluated under the specified biasing conditions to ensure it met the design goals and aligned with simulation results. On-wafer S-parameter measurements were performed across the 20 to 40 GHz frequency range with 100 MHz increments, utilizing an HP8510C Vector Network Analyzer. Calibration of the measurement setup was carried out using the standard Short-Open-Load-Thru (SOLT) technique. For noise figure characterization, an Agilent E4448A Spectrum Analyzer was used, with the noise signal amplified beforehand by two low-noise amplifiers: a MACOM MAAM-011109 and an HP83051A. Measured outputs of the MMIC are presented in the following section.  
Figure 12: Circuit schematic of the three-stage wideband LNA MMIC showing transistor sizes, biasing, and matching elements.