## 4 Hardware Accelerator Design  
### Overall Hardware Architecture  
In the hardware implementation, we used both pipeline and parallel designs. These designs help to optimize the processing speed and resource utilization. The overall architecture is shown in Figure 6.  
Figure 6: Overall hardware architecture. By adopting a pipeline design, we split the task into four phases so that each phase can work independently. This allows the data to be processed in one phase while other phases can process different data in parallel. The requirements of the algorithm in this paper include background-suppression operations and target-enhancement operations. This naturally provides the conditions for hardware parallel implementation. Consistent with the algorithm, the overall hardware architecture of this paper is also divided into two independent computing paths. The primary task of the first computation path is to generate \(LUM(i,j)\). Its core function is to realize background suppression to reduce the interference of background noise during target detection. At the same time, the second computation path synchronously generates \(EW(i,j)\). Its main function is target enhancement based on background suppression. Through parallel design, the demand for memory access is effectively reduced, thus reducing the pressure on storage resources. In the design proposed in this paper, the computational complexity of the first line is higher than that of the second line. To solve this problem, we inserted a buffer after the calculation of the second line. By temporarily storing the calculation result, the second line can wait for the first line to complete the calculation of \(LUM(i,j)\). In the first stage of pipeline processing, the input image is scanned. This design realizes the filtering of different kernels through the reuse of the Imfilter module. In the first stage, we use Imfilter_0 to achieve filtering without extra precision. Among them, the mean filter is realized by using the mean filter kernel. At the same time, the Gaussian filter is realized by using the Gaussian filter kernel. In the first stage, we also use the Ordfilt2 module for filtering. The maximum filtering is implemented using the maximum filtering kernel. In the second stage of the pipeline, combined with the data obtained in the first stage, we continue to scan the image. In the parallel algorithm background-suppression circuit, this design adopts the special Consis_eval module to achieve the component consistency measurement. This module includes the multiplication operation and the division operation, allowing us to calculate \(LC(i,j)\). Then, we use Imfilter_1 to achieve double-precision filtering. We use the Imfilter_1 module to filter the previous \(LC(i,j)\) through the cumulative kernel. In the parallel algorithm of the target-enhancement line, this design first runs the Imfilter_1 module. In the Imfilter_1 module, the results of the Gaussian filtering obtained in the first stage are filtered again; that is, the decentralized mean filtering. Then, the Gain_max module is designed to realize the energy-maximum calculation. The Gain_max module includes subtraction and comparison operations to calculate \(EW(i,j)\)  
In the third stage of the pipeline, we only execute the background-suppression algorithm. Firstly, the Lc_Block_div module is designed. The Lc_Block_div module is used to compute the confidence assignment function, including the division operation. We then import the result of the resulting confidence assignment function into the Entry_log module. The Entry_log module is used to calculate the mutation entropy operator, including multiplication and division and comparison and log operation, which needs to be called the Cordic IP core. In the second stage of the pipeline, the target-enhancement algorithm is implemented. Therefore, in the third stage, we only pass the result of the second stage through the buffer and wait for the end of the background-suppression algorithm to ensure the continuity of the entire pipeline processing.