# Constrained Optimization of FPGA Design for Spaceborne InSAR Processing
## 5 Experimental Results and Discussion
### Verification of Matrix Transposition Schemes  
The matrix transposition schemes' theoretical resource requirement and efficiency were pointed out in Section 4.4 of Section 4. Now that the test results of interferogram generation and coarse registration were ready, this section focused on verifying matrix transposition schemes on FPGA. To facilitate the comparison with the theoretical analysis, the thread of interferogram generation and coarse registration was set as 4 (scheme \(c\)) and 1 (scheme \(e^{\prime}\)), respectively. Different matrix transposition schemes had varying efficiency, influencing coarse registration processing time \(T_{c}\), as shown in Table 10.  
The comparison between the measured value \(\
abla G_{T}\) (calculated from Table 10. Test results of matrix transposition schemes under the condition of \(c^{\prime}\) and \(e^{\prime}\)) and the theoretical value \(\
abla G_{B}\) (calculated from Table 6) is displayed in Figure 10. It can be seen that \(\
abla G_{T}\) of \(\Delta g\)'\(h^{\prime}\) was above 8 while \(\
abla G_{T}\) of \(\Delta h\)'\(i^{\prime}\) was below 2, which confirmed the theoretical analysis that scheme \(h\) was more balanced than schemes \(g\), \(i\), \(j\). Due to the loss of efficiency,  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Scheme** & \(R_{i}\) & \(R_{\text{BRAM\_36K}}\) & \(R_{i}/R_{\text{BRAM\_36K}}\) (\%) & \(T_{c}\) (ms) & \(T_{g}\) (ms) & \(T_{i}\) (ms) \\ \hline \(g^{\prime}\) & 260 & 1470 & 17.69 & 9.24 & 186 & 195.24 \\ \(h^{\prime}\) & 132 & 1470 & 8.98 & 11.16 & 186 & 197.16 \\ \(i^{\prime}\) & 68 & 1470 & 4.63 & 16.28 & 186 & 202.28 \\ \(j^{\prime}\) & 36 & 1470 & 2.45 & 39.75 & 186 & 225.75 \\ \hline \hline \end{tabular}
\end{table}
Table 10: Test results of matrix transposition schemes under the condition of \(c^{\prime}\) and \(e^{\prime}\).  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Scheme** & **Thread** & \(R_{i}\) & \(R_{\text{DSP}}\) & \(R_{i}/R_{\text{DSP}}\) (\%) & \(T_{c}\) (ms) & \(T_{g}\) (ms) & \(T_{i}\) (ms) \\ \hline \(e^{\prime}\) & 1 & 288 & 3600 & 8 & 9.24 & 164.7 & 173.94 \\ \(f^{\prime}\) & 2 & 576 & 3600 & 16 & 4.72 & 164.7 & 169.42 \\ \hline \hline \end{tabular}
\end{table}
Table 8: Test results of coarse registration with different threads.  
the measured time \(T_{g}\) and \(T_{1}\) was longer than the theoretical value. As a result, the actual value (\(\
abla G_{T}\)) was above the theoretical value (\(\
abla G_{B}\)), which, in turn, caused an increase in the relative error. Yet, the relative error was still lower than 10%.  
It can be proved that under the same resource condition, if the relative error between the measured value (\(T_{c\_inst,T_{g\_inst}}\)) and the theoretical value is within 20%, that is, 0.8 \(T_{c}\leq T_{c\_test}\leq 1.2\)\(T_{c}\) and 0.8 \(T_{g}\leq T_{g\_test}\leq 1.2\)\(T_{g}\), then the relative error of \(\
abla G\) will also be within 20%. From the perspective of engineering, when the \(\
abla G_{gate}\) is set (e.g., 3) and the relative error range is set (e.g., 20%), the two-dimensional constraint problem of resources and processing capacity could be solved using the theoretical analysis of FPGA proposed in this paper, thus shortening the system optimization time.  
We analyzed the influence on the system when the thread of the interferogram generation was 4. When the thread of the interferogram generation changed from 4 to 1, the results are shown in Figure 11. \(\
abla G_{T}\) of either \(\Delta a^{\prime}\_g'h'\) or \(\Delta a^{\prime}\_h'i'\) was above 3, which meant schemes \(h'\) and \(i'\) were more balanced than the others. We can see that when the requirement of system processing capacity changed, the balanced scheme would change accordingly. Such a changing relationship could be dynamically reflected by the index \(\
abla G\) proposed by this paper.