# A Flexible FPGA-Based Stochastic Decoder for 5G LDPC Codes
## 5 Design Flow  
For instance, a QC LDPC code with a codeword length of \(N=3808\) and a code rate of \(R=1/3\) that complies with the 5G NR standard has a BGM \(H_{b}\) with the dimensions \(46\times 68\). This BGM has 308 non-'-1' entry values, which is equal to 68 \(\times\) 4.52, and an average variable node degree of 4.52. The BGM \(H_{b}\) forms the basis for the representation and construction of the PCM \(H\). Therefore, the calculation for non-zero entries in the PCM is determined by multiplying 308 by 56, which equals 17,248, where \(Z_{c}=56\) is the lifting size or expansion factor. Consequently, this results in twice the 17,248 interconnections that exist between the variable and check nodes of the decoder, which makes the structure extremely complicated. Modelling these thousands of interconnections in hardware description language (HDL) takes at least thirty minutes. This modelling is extremely time-consuming when dealing with a partially parallel architecture. The process of simulating and debugging the hand-coded HDL model is both extremely challenging and time-consuming, respectively. The process of modelling the decoder with a different code length turns out to be an activity that is both unproductive and repetitive. Because of this, automating the design flow to remove repetitive and redundant tasks requires an efficient design methodology. The above-mentioned problems were solved by creating an automation tool in MATLAB using the C++ programming language; the tool takes less than a minute to generate connections between the nodes of the proposed decoder.  
Figure 6: Block diagram of SVNPU with high \(w_{v}=6\).  
This section outlines the suggested design flow, which enables the automated flexibility in design and creates an optimal FPGA-based stochastic LDPC decoder for a selected set of 5G QC LDPC codes. The flowchart in Figure 7 depicts the design flow. In the first step, the construction of the required code rate BGM set is based on the user inputs like message length, code rate, and lifting sizes of the 5G LDPC code. The second step has two tasks: The first task entails determining the decoder's parameters, such as the maximum of the matrix dimensions and weights, namely \(N_{b}\), \(M_{b}\), \(Z_{c}\), \(W_{v}\), and \(W_{c}\), which describe the chosen set of supported BCMs. Based on lifting size \(Z_{c}\), it is possible to determine the parallelism factor \(\eta_{p}\) from these. For the \(N=3808\) LDPC code rate set, the maximum values are \(N_{b}=68\), \(M_{b}=46\), \(Z_{c}=56\), \(W_{v}=30\), and \(W_{c}=19\). Another task is to extract the positions and shift values of the non-\({}^{\prime}-1\)' entries in each BGM and arrange them consistent with the ROMs. Considering the parameters derived in the earlier step, the design flow utilizes a high-level synthesis (HLS) tool [30] to produce the hardware description language (HDL) SystemVerilog code for the suggested architecture written in the high-level language C++. After register transfer level (RTL) modelling of the decoder, it is synthesized using the Xilinx synthesis tool to measure the hardware requirements of the decoder. The bit error rate (BER) simulations have been implemented on the FPGA test setup.