# Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM
## 3 Design of an Adaptive Fault Tolerance Mechanism
### Methodology  
First, we will describe the general methodology followed to make the microprocessor adaptive. Then, we will focus on the particular case study implemented, where the system is able to detect intermittent faults and adapt its behavior. Making the microprocessor adaptive affects three elements of the Plasma model (see Figure 1):  
1. The size of internal memory was augmented in order to store data bits together with their corresponding code bits. Considering that the ECCs used have redundancy of \(r\) bits, the \(512\times 32\) original RAM was changed to a \(512\times(32+r)\) RAM. 2. Consequently, the data bus length also grows in \(r\) bits. 3. The \"Memory Controller\" module that we have renamed as \"Adaptive Memory Controller\" in the adaptive version. The mission of this component in the original (non-fault-tolerant) Plasma core is to manage the access to the internal RAM from the CPU. In the adaptive version, the memory controller will also: * support the ECCs implemented, * detect changes in the error condition, and * manage the adaption process. Figure 1: Block diagram of an adaptive version of the Plasma microprocessor (Plasma_ADAPTIVE) core. The first step to make the memory controller fault-tolerant is to provide some FTM. As based on ECCs, it would require:  
* Adding r code bits to data from the CPU (to be written in memory), or _encoding_ operation;
* Removing the r code bits from data read from memory (to be sent to the CPU). In addition, in case of existing errors, data should be corrected (if errors are covered by the active ECC). This operation is called _decoding_. Remark that the encoding and decoding circuits are intimately related to the particular ECC used. Hence, far, this scheme matches any fault-tolerant ECC-based mechanisms. In our case, we intend to design a component able to detect changes in the error conditions and, if possible, to replace encoding and decoding circuits with others corresponding to a new ECC able to tolerate the new error condition. We call this operation _monitoring_. An important premise of our proposal is the fact that all the ECCs used must have the same redundancy. The reason is to keep the same memory (and data bus) size in every system evolution, thus reducing the complexity gap between different operating versions of the system. The block diagram of the adaptive version of the Plasma microprocessor (Plasma_ADAPTIVE core) can be seen in Figure 1; Figure 2 shows the block diagram of the \"Adaptive Memory Controller\" module. The colored elements are those added or modified with respect to the original model. For a later understanding of how the AFT proposed works, we will now describe how memory read and write operations work in the Plasma model (where \"ECC Encoder\" and \"ECC Decoder\" modules in Figure 2 are not present). The RAM is asynchronous, and the memory controller is implemented as a state machine. Both operations are started by the memory controller and the last  
Figure 2: Block diagram of the “Adaptive Memory Controller” module implemented in Plasma_ADAPTIVE core. clock cycle. Regarding reading operation (see Figure 3a), during the read cycle: (1) The memory controller sets the memory address and the read signal (with a delay t\({}_{\rm d}\)). (2) The memory returns the contents of the indicated address (after t\({}_{\rm access}\)). Then, the data can be buffered and delivered to the control unit (3), respecting both the buffer setup time (t\({}_{\rm su}\)) and the memory read hold time (t\({}_{\rm rh}\)). In the write cycle (see Figure 3b): (1) The memory controller sets the data to be written, the memory address and the write signal (after a delay t\({}_{\rm d}\)). (2) The data are written in the indicated address (respecting the memory write setup and hold times, t\({}_{\rm wsu}\) and t\({}_{\rm wh}\)). Obviously, the minimum system clock period must be equal to max(T\({}_{\rm r(cyc)}\), T\({}_{\rm w(cyc)}\)).