# Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies
## 4 Circuit Topologies for Low-Voltage Operation of RF/mm-Wave Blocks
In this case, only low-voltage circuit topologies (as shown in Figure 5) can be adopted. However, the achieved output power is not sufficient for the application. Integrated transformers can further increase the output power of an RF/mm-wave PA by exploiting the power-combining technique at the output stage [46; 47; 48; 49; 50; 51; 52; 53; 54; 55; 56]. Transformer-based PAs have the following benefits, especially when differential topologies are mandatory:  
* Implement single-ended-to-differential and differential-to-single-ended conversions, providing inherent virtual ground for differential operations;
* Transform impedance for impedance matching and output power matching;
* Provide simple DC biasing of power devices via the center tap, avoiding the use of RF chokes and DC blocks. Moreover, transformers can easily combine the output power of two devices, thus nearly doubling the overall power (if the losses of the combining network are negligible). Power combining can be obtained by using voltage-combining transformers (VCTs) or current-combining transformers (CCTS), which are also known as series or parallel combining, respectively. Figure 7 depicts a two-way implementation for voltage- and current-combining techniques, by using integrated transformers with a 1:N turn ratio. The voltage-combining technique is aimed at summing the voltage produced by each PA unit by exploiting stacked secondary windings, in order to increase the output voltage and, thus, the delivered power of low-voltage CMOS PAs. On the other hand, the current-combining technique is aimed at gathering the current of each PA unit by exploiting the parallel-coupled secondary winding to increase the overall current, thus boosting the output power. By extending these techniques to \(M\) PA units, the output power can be theoretically boosted up to \(M\) time, either by using series or parallel combining. Physical implementations of power combining are greatly influenced by the specific application and adopted integration technology. An important limitation is caused by the integrated transformers, whose losses have to be properly minimized to preserve the power-combining advantage with reasonable silicon area consumption. Figure 8 depicts the simplified layout of an example of a series-combining transformer for the voltage-combining topology in Figure 7a. The transformer exploits only two metal layers (i.e., the upper and thicker metal layers) for both windings, which are coupled by means of an interleaved configuration. Figure 6: Double-balanced mixer topologies: (**a**) traditional Gilbert cell mixer; (**b**) TC Gilbert cell mixer; (**c**) CC Gilbert cell mixer. Unfortunately, both series- and parallel-combining techniques have practical design limitations on the maximum number of PA units that can be profitably combined. Specifically, in the voltage-combining technique, the number of PA units is limited by the optimal impedance of each power device, \(R_{\text{OPT}}\), and is equal to the following:  
\[R_{\text{OPT}}=\frac{R_{\text{LOAD}}}{2\cdot M_{\text{S}}\cdot N^{2}} \tag{2}\]  
where \(R_{\text{LOAD}}\), \(M_{\text{S}}\), and \(N\) are the load resistance, the number of PA units and the transformer turn ratio, respectively. Indeed, according to Equation (2), when \(M_{\text{S}}\) increases, \(R_{\text{OPT}}\) reduces, thus requiring larger power transistors with lower maximum available gain, due to the RLC parasitics. Therefore, voltage combining is not used for an \(M_{\text{S}}\) higher than four. On the other hand, in the current-combining technique, \(R_{\text{OPT}}\) is equal to the following:  
\[R_{\text{OPT}}=\frac{M_{\text{P}}}{2\cdot N^{2}}R_{\text{LOAD}} \tag{3}\]  
where \(R_{\text{LOAD}}\), \(M_{\text{P}}\), and \(N\) are the load resistance, the number of PA units and the transformer turn ratio, respectively.