## 5 Performance Evaluation
### Computation Overhead  
Different approaches can be used to evaluate the computation overhead of a communication protocol. Some studies, like [14; 30], tested the cost of elliptic curve operations and hash functions on desktop processors and then deducted the overall timing cost from their proposed protocols. On the other hand, the studies in [28; 29] calculated the overall timing cost by adopting the timing of those operations and functions from other works. These methods can only present a relative timing cost without considering the overhead of a system architecture, like bus interfaces and memory transactions. Therefore, we evaluated the proposed protocol by developing a hardware system. The primary purpose of this approach was to precisely assess the workload of executing the protocol on an embedded system suitable for sensor nodes. The open-source RISC-V processor was utilized to measure the computing performance by implementing two micro-architectural configurations. The RISC-V architecture offers a performance counter that can be accessed through the control and status registers (CSRs). Hence, the measurement metric extracted from the CSRs provides information about the actual clock cycle executed by the processor. This data can be used to derive the timing cost based on the operating clock frequency of the system. By analyzing this information, it is possible to gain insight into the costs associated with different architecture designs and identify areas for further architecture optimization. The current options for processors in IoT devices include ARM, x86, and RISC-V. With the open-source instruction set architecture (ISA), RISC-V ISA provides a high flexibility in customization for a specific application compared with its counterparts. RISC-V enthusiasts have extended the processor with additional instructions and accelerators to enhance the computing efficiency and provide security and low-power design for IoT devices. Rocket is a variant of the RISC-V processor that allows for modifications at the system and micro-architecture levels. Its architecture is suitable for evaluating the performance of the proposed protocol. The performance data can be used to tailor the Rocket core further to realize the practicality of the protocol for resource-constrained IoT nodes. The software version of the proposed protocol was implemented on a RISC-V system with a Rocket core, which is a variant of the RISC-V core that can be scaled down for low-power sensor nodes. The RISC-V system was synthesized on an Arty A7-100T Xilinx FPGA to evaluate the computation cost regarding a number of clock cycle counts. Instead of using pseudo- or software-based primitives, the RISC-V system integrated the physical hardware implementation of a true random number generator and a physical unclonable function, as shown in Figure 3. \begin{table}
\begin{tabular}{l c c} \hline \hline \multirow{2}{*}{**Protocol**} & **Number of** & **Total Message** \\  & **Messages** & **Size (Bytes)** \\ \hline Ours—level 2 & 3 & 160 \\ Ours—level 1 & 1 & 40 \\
[14] & 4 & 168 \\
[28] & 3 & 316 \\
[29]—Protocol \#1 & 4 & 420 \\
[29]—Protocol \#2 & 2 & 142 \\
[30] & 3 & 332 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Communication cost comparison. Table 4 shows the notation of computations applied in the proposed protocol and some related works in key establishment based on ECC with an authentication property. Table 5 compares the computation overheads of the protocol at the sensor nodes and the server separately. The proposed protocol aimed to minimize the operations of the sensor nodes as much as possible. The protocol allowed for establishing a level 1 secure channel with the least computational cost (\(2T_{sm}+T_{a}+2T_{h}\)). The protocol in [14] yielded the same cost in computing; however, the material to establish a share key was quadrupled. With level 2 security, the computation cost was less than [29; 30]. However, the application of the protocol needed to take both the computation and communication of the handshake into consideration.