## 3 Experimental Set-Up
### Capturing and Processing Data  
The diagram in Figure 6 illustrates the steps followed from data reception to the determination of the receiver's position and orientation, highlighting the key points in signal processing and decision making. The next section will present a detailed discussion of the fundamental blocks and the main aspects considered during its development. Several considerations were evaluated during the data capture, starting with the sequential methodology in which the transmitters send information and the frame time defined by each transmitter (60 ms). Specifically, the proposed scheme captures frames at 300 ms intervals, ensuring that all four frames, one from each optical transmitter, are received at least once within the established interval. The received signal is digitized through the ADCs of the TM4C1294 NCPDT microcontroller. The proposed microcontroller provides the necessary number of ADCs (nine) with appropriate sampling frequencies, permitting the storage of 6000 samples per ADC module, assuming a reception period of 300 ms at a sampling frequency of 20 kHz. Ethernet communication is used to transmit the data stored in the ADC buffers and to collect the resulting dataset on the computer. Once the data are digitized and received on the computer, the first step is to apply a digital high-pass filter. Despite employing an analog filter during implementation, the high power of standard luminaires compared to transmission LEDs prevents the complete elimination of the interference with a first-order filter. The 100 Hz sinusoidal noise signal is visible in the signal shown at the top of Figure 7, overlapping with the desired signal. Given that the frequency components of the signal to be recovered are at 1 kHz and 2 kHz, a cutoff frequency of 900 Hz is established. This approach allows for preserving the signal of interest while effectively removing unwanted noise, as shown in the second signal of Figure 7.  
Figure 5: PCB design. Figure 6: Implemented processing flow. Once the signal is filtered, it is normalized by comparing it to 0 V, assigning a value of 5 V to values greater than 0 V and 0 V to values less than or equal to 0 V. This simplifies the decoding process by reducing the voltage levels to a standardized range of 0 V to 5 V. This transformation process is shown in the third signal of Figure 7.  
Without information about the start or end times of each frame transmitted, the frame is segmented into 1 ms intervals. This approach enables a detailed analysis of each millisecond and limits the time offset relative to the bit time to a maximum of one-fifth of this interval. In each 1 ms interval, the number of rising and falling edges in the signal is counted. If the sum of edges is 3 or more, the data are interpreted as 0; otherwise, they are defined as 1. As a result, there is a total of 300 points representing the sequence transmitted over a 300 ms frame. The detected dataset is then expanded to 6000 points by replacing each point with 20 identical values. To identify and eliminate disturbances that may impact decoding, the methodology concentrates on detecting and removing pulses smaller than 50 units, which is half the duration of a bit following interpolation. The frame detection process begins with identifying the headers, which consist of five consecutive bits of value 1, easily distinguishable from the data bits. Since one bit corresponds to 100 points in the frame and accounts for phase errors or disturbances, it is compared with a value of 450 consecutive values of 1 across the entire frame to locate the start of the transmitted frames. Once the header start positions are identified, the average value from 100 values per bit in each frame is calculated, resulting in a set of detected information frames, each six bits long, for each identified header. On the other hand, when a header is detected, the RMS value of the filtered sampled signal is measured within the same interval.