## 3 Study of the Communication System
### Experimental Setup  
The prototype was tested for additive white Gaussian noise (AWGN) resistance in direct channel and in two-path signal propagation emulation scenario. Both mathematical model simulations and FPGA experiments of FM-ACSK system were conducted. Simulation was performed using Matlab script using Simulink model with Bernoulli random bit generator, AWGN channel, and bit error ratio (BER) counting function, saving BER and SNR data into the text file with each iteration of simulation. Experiment on the FPGA prototype, however, required some more preparation, which is explained further. Cyclone V has more capabilities than FPGA itself, as it is System-on-Chip (SoC) device which has Hard Processing System (HPS) with Arm Cortex-A9 Microprocessor Unit (MPU) and peripheral controllers. This extends operating possibilities for Cyclone V employment and allows us to interconnect FPGA signal processing and software program that uses MPU and runs in the dedicated Linux environment. Additionally, as the prototype is designed using Arrow SocKit Development Board, Cyclone V has access to all the connected peripherals, such as clocks, buttons, switches, LEDs, SDRAM memory, and USB-to-UART bridge, used in the experimental setup. An overview of the experimental setup is shown in Figure 11. Green blocks refer to specifically designed FPGA modules for the FM-ACSK prototype BER testing experiment, while blue modules are FPGA Altera/Intel Intellectual Property (IP) cores from the Quartus library. Red blocks are HPS modules integrated into Cyclone V SoC, while yellow blocks are external Integrated Circuits (ICs) on the Arrow SocKit Development Board and Highspeed AD/DA Daughter Card. White blocks refer to various unclassified external units. Overall, FM-ACSK transmitter module generates chaotic symbols (8192 samples long for 1 modulating data bit) according to the pseudorandom input data sequence. This output is transformed into analog signal by DAC, sent over a 62 cm long coaxial cable to ADC, and transformed back to digital 14-bit signal. As converters do not support signed alternating signal, most significant bit (MSB) is inverted before the DAC input and after ADC output, thus transforming common Binary Two's Complement (BTC) bit coding schemes into Bipolar Offset Binary (BOB) coding scheme and back. Delay between DAC input and ADC output is equal to 10 samples (at 50 MHz clock) and gain is 0.3506703 (these values are used in Simulink model in place of ADC-DAC for approximate consistency). After ADC, the received signal gets white noise applied to it and processed in the FM-ACSK receiver module. Recovered data bits are used for BER estimation, as explained further. Figure 10: Simulink schematic of received data bit detection module. The arrows at the clock inputs indicate which clock edges serve as a trigger condition. In addition to the previously described FM-ACSK base system (essentially, transmitter and receiver modules), the following FPGA modules (see Figure 11) were designed for experimental setup: Data Bit Timing, LFSR (Linear Feedback Shift Register), AWGN Controller, BER Controller, and BER-to-DMA. Data Bit Timing module is a simple 13-bit free-running counter that outputs \"1\" once per 213 = 8192 clocks, which is equal to the desired timing of the data bit/symbol (T\({}_{\text{b}}\)) that is getting transmitted using FM-ACSK digital communication system. The LFSR (Linear Feedback Shift Register) module generates a pseudorandom bit sequence, using a 16-bit Maximum Length Fibonacci LFSR, with the feedback polynomial x16 + x14 + x13 + x11. It ensures good approximation of the average random data transmission scenario, and this sequence is also used for BER counting, as explained further. AWGN Controller module has two main functions: adding noise to the received signal and controlling the signal-to-noise ratio (SNR).