# Flexible Wearable Heart Rate Monitoring System and Low-Power Design: A Review
## 3 Design of the Flexible Wearable Heart Rate Signal Acquisition Module
### Hardware-Algorithm Co-Design of Flexible Wearable Heart Rate Signal Acquisition Module  
Hardware-algorithm co-design is one of the important methods to achieve low-power design of flexible wearable heart rate signal acquisition modules. This method can be used to realize efficient heart rate signal acquisition and compressed sampling functions, and it also plays a key role in achieving low-power system design. [PERSON] et al. [80] reported the signal acquisition module in a low-power flexible wearable heart rate monitoring system is realized through hardware-algorithm co-design, as shown in Figure 3c. In this collaborative framework, the system employs an nRF52832 chip as the control and Bluetooth module, configured to execute a VLC-based Huffman compression algorithm [83; 84; 85] once per second. When the compressed data size exceeds the original, the system directly transmits the uncompressed data to avoid inefficient computations, thereby reducing power consumption. The compression algorithm minimizes computational complexity through reference vector methods and byte grouping, adapting to the MCU's processing capabilities. Concurrently, the ADS1293 front-end chip (It is manufactured by Texas Instruments Incorporated, with its headquarters located in Dallas, TX, USA) is set to a 400 Hz sampling rate to meet the algorithm's requirements for high-resolution signals, enabling 3-channel lead acquisition to reduce the hardware channel count. At a 400 Hz sampling rate, the average power consumption of the system is 13.468 mW, representing a 16.5% reduction compared to systems without compression algorithms; it outperforms similar single-lead devices. Similarly, [PERSON] et al. [63] developed a low-power signal acquisition module in a flexible wearable system through hardware-algorithm co-design. The ASIC in this system measures \(4.0\times 2.5\) mm\({}^{2}\). The system starts with an LED driver, which is connected to a photodiode (PD) through a current path. The current generated by the photodiode is converted into a voltage signal by a transimpedance amplifier (TIA). The voltage signal then passes through a low-pass filter (LPF) to remove high-frequency noise. The filtered signal enters an analog-to-digital converter (ADC) to convert the analog signal into a digital signal. Finally, the digital signal is processed by a digital baseband engine (DBE), and the PPG reading is output. Specifically, the analog front-end (AFE) of the system dynamically adjusts the gain and bandwidth through 16 digital input/output pins to meet the sparse sampling requirements of the compressive sensing algorithm and ensure the retention of signal features. The compressive sensing algorithm reduces the sampling rate to 4 Hz, significantly reducing the amount of hardware data processing and avoiding the need for high-frequency operation of the ADC. In addition, the LED drive circuit controls the current through a 4-bit analog switch and adjusts the compression ratio of the compressive sensing algorithm to dynamically optimize the light intensity for power reduction. The heart rate extraction algorithm omits the signal reconstruction step and directly outputs 8-bit heart rate data, thereby reducing the requirements for transmission bandwidth. Finally, the algorithm controls the microcontroller to enter low-power mode according to the operating state of compressive sensing and cooperates with Bluetooth Low Energy (BLE) to transmit data every 40 s, optimizing the total system power consumption to 1.66 mW. In summary, as demonstrated by the case studies of [PERSON] et al. and [PERSON] et al., hardware-algorithm co-design is a crucial approach to achieving low-power heart rate signal acquisition. [PERSON] et al. 's research illustrates how dynamic compression algorithms and sampling rate adaptation form a closed-loop optimization, while [PERSON]'s study proves the effectiveness of sparse sampling and cross-layer parameter tuning in reducing power consumption.