## 3 The State-of-the-Art of AC-DC Converters
Figure 14: Hybrid two-path architecture of the power recovery circuit proposed in [44]. Reproduced with permission from [PERSON], IEEE Journal of Solid-State Circuits; published by IEEE, 2015. Figure 13: The voltage doubling pretulator proposed in [43]. Reproduced with permission from [PERSON], IEEE Proceedings; published by IEEE, 2015. In [45], a PMIC is presented that adopts a full-wave CMOS rectifier (NMOS active diode and cross-coupled PMOS) to convert AC to DC voltage and a newly developed multi-ratio switched-capacitor DC-DC regulator to provide a regulated output voltage. However, this solution works on an input voltage range of 1.9 V to 3.5 V.  
The solution proposed in [46] consists of the dual-mode rectifier, shown in Figure 16, to work well on wide range of input AC voltage and many blocks to improve PCE. This topology solves the problem during start-up and for low input power with a cross-coupled passive rectifier for high input power an active diode rectifier is used. Figure 16: Dual-mode rectifier for PE transducer proposed in [46]. Reproduced with permission from [PERSON], IEEE Journal of Solid-State Circuits; published by IEEE, 2015. Figure 8:0 Power recovery circuits in the main power path [44]: (**a**) active full-wave rectifier and the comparator used in the active PMOS diode; (**b**) high-frequency voltage doubler; (**c**) LDO circuit and generation of the POR signal; (**d**) Push-pull voltage doubler circuit used in the auxiliary power path; (**e**) Over-voltage protection circuit for \(V_{DC2}\) rail. Reproduced with permission from [PERSON], IEEE Journal of Solid-State Circuits; published by IEEE, 2015. The system works for a wide range of input voltage, with a minimum value equal to 1 V. However, the large number of ancillary blocks need additional input power. In [47], it is presented a half/full wave rectifier (Figure 17) based on a maximum selector, which is based on bulk-driven comparator. This technique is very low-power, nevertheless it works under several ten of kilohertz. A half-wave active rectifier is proposed in [48]. Figure 18 shows the circuit diagram of the single-stage half-wave active rectifier made up of a start-up rectifier, a half-wave rectifier, a comparator, a buffer and a power switch. The active rectifiers exploit a fast comparator to directly control the gate of PMOS transistors to reduce reverse current leakage from the output load to the input. In standard cross-coupled topology, full-wave input voltage is applied between the gate and source of all transistors. Consequently, PMOS and NMOS transistors will turn on/off roughly at the same time which creates a leakage path from load to source. To prevent leakage currents rectifier should only turn on when the input voltage is higher than the load voltage. For this reason, ref. [41] proposes a rectifier topology (Figure 19) where the turn on/off voltage level of rectifier is controlled by applying independent bias voltage to the NMOS transistors. At the same time, this solution requires high-input voltage (from 1.6 V to 3.6 V). Figure 8:1 BD-WTA half-wave (**a**) and full-wave rectifier (**b**) proposed in [47]. Reproduced with permission from [PERSON], Microelectronics Journal; published by Elsevier, 2013. Figure 8:2 Circuit diagram of the single-stage active rectifier realized in [48]. Reproduced with permission from [PERSON], IEEE Transactions on Biomedical Circuits and Systems; published by IEEE, 2014. Work in [49] presents an active rectifier with SAR-assisted coarse-fine adaptive digital delay compensation technique for biomedical implantable devices. Both on- and off-delay are compensated by adjusting the comparator offset. In order to achieve accurate zero-voltage switching against process, voltage, and temperature variations (PVT), a two-step coarse-fine digital tuning method is introduced.