# All-Digital Computing-in-Memory Macro Supporting FP64-Based Fused Multiply-Add Operation
###### Abstract  
Recently, frequent data movement between computing units and memory during floating-point arithmetic has become a major problem for scientific computing. Computing-in-memory (CIM) is a novel computing paradigm that merges computing logic into memory, which can address the data movement problem with excellent power efficiency. However, the previous CIM paradigm failed to support double-precision floating-point format (FP64) due to its computing complexity. This paper presents a novel all-digital CIM macro-**DCIM-FF** to complete FP64 based fused multiply-add (FMA) operation for the first time. With 16 sub-CIM cells integrating digital multipliers to complete mantissa multiplication, **DCIM-FF** is able to provide correct rounded implementations for normalized/denormalized inputs in round-to-nearest-even mode and round-to-zero mode, respectively. To evaluate our design, we synthesized and tested the **DCIM-FF** macro in 55-nm CMOS technology. With a minimum power efficiency of 0.12 mW and a maximum computing efficiency of 26.9 TOPS/W, we successfully demonstrated that **DCIM-FF** can run the FP64-based FMA operation without error. Compared to related works, the proposed **DCIM-FF** macro shows significant power efficiency improvement and less area overhead based on CIM technology. This work paves a novel pathway for high-performance implementation of an FP64-based matrix-vector multiplication (MVM) operation, which is essential for hyperscale scientific computing. digital computing-in-memory; floating-point arithmetic; fused multiply-add; scientific computing; matrix-vector multiplication +
Footnote †: journal: Applied sciences  
in high-performance scientific computing. For example, [11] presented a CIM macro that supports MVM operation of 64 \(\times\) 4b inputs with 16 \(\times\) 4b weights in a single computation cycle. The proposed CIM macro was built with a standard two-port compiler using foundry's 8T SRAM bit-cell. The number of read word-line pulses is used to represent the 4b input, while 4b weight is realized by charge sharing among binary-weighted computation capacitors. The chosen 8T SRAM bit-cell provides sufficient noise margin compared to 6T SRAM and ensures stable multi-word activation for CIM operation at the expense of 30% bit-cell area overhead. Ref. [12] presented a hardware-efficient CIM accelerator with improved activation reusability and bit-scalable MVM for convolutional neural network acceleration. The cyclic-shift weight duplication exploits a third dimension of receptive field depth for sliding-window weight mapping to reduce the memory access for activations, improving the array utilization. The parasitic-capacitance charge sharing is employed to realize high-precision analog MVM in order to reduce the ADC cost. Compared with conventional designs, this CIM accelerator with parallel processing of nine sliding window operations achieves 56.6-58.8% alleviation of memory access pressure. Meanwhile, when configured with 8-bit ADC, it saves 92.53-94.53% ADC energy consumption. However, the research methods proposed by [11; 12] are not suitable for applications requiring floating-point precision due to the limited precision of ADC/DAC. In fact, most of the existing analog CIM accelerators are not suitable for accelerating high-precision floating-point MVM in scientific computing [13; 14; 15]. On the other hand, digital CIMs that directly integrate bitwise digital multiply-accumulate (MAC) units into memory arrays so that all rows and columns are activated to develop parallel computing can meet the precision requirements. Compared with analog CIMs, digital CIMs can make full use of the memory array without loss of accuracy, and have higher power and area efficiency, as well as better process and voltage scalability [16; 17; 18; 19]. For example, ref. [20] presented the Neural Cache architecture, which repurposes cache structures to transform them into massively parallel computing units capable of running inferences for deep neural networks.