# Real-Time Simulator for Dynamic Systems on FPGA
## 4 Development of the Prototype and Results
### Methodology  
In the process of obtaining the results, some parameterizations were adopted as a way to gain greater control. Two sets of results were obtained:  
* Simulation of the dynamic system using Matlab/Simulink in comparison with the dynamic system using Matlab/System Generator;
* Simulation of the dynamic system using RTSDS-FPGA. The test sets have a difference because their numerical configurations are distinct, but they do not make the results unfeasible. The output value for Matlab/Simulink is represented in a 64-bit floating-point format, and the same output value in Matlab/System Generator is represented with a signed 32-bit fixed-point format, 16 of which are used for the representation of the fractional part. Thus, the two scenarios were configured as follows:  
* Scenario 1: The input of the dynamic system with constant values;  
Figure 16: In detail, the circuit responsible for the rolling resistance force. Figure 14: Prototype of the circuit for the DS of the vehicle. Figure 15: In detail, the circuit responsible for the aerodynamic friction force. * Scenario 2: The input of the dynamic system with variable values. The dynamic system has set solution methods for ODE. Thus, for each of the cases discussed above, tests were performed with each of the methods described below:
* Improved Euler;
* Third-order Runge-Kutta;
* Fourth-order Runge-Kutta. The implementation was carried out in a completely parallel way, allowing the choice of methods and differentiating from the models implemented in the literature. The angle of inclination varies according to the graph shown in Figure 17, and the torque value varies according to the graph shown in Figure 18.  
In order to analyze the reliability of the obtained results, we used error measures among the obtained data. The analyses are based on mean error, mean square error, and error variance. The statistical calculations have as reference the value of floating-point simulation acquired with the simulation performed in Matlab/Simulink. The calculation of the mean error is shown below. \[M_{e}(X)=\frac{1}{N}\sum_{i=0}^{N-1}(X(i)-Y(i)), \tag{28}\]  
where \(M_{e}(X)\) is the value of the mean error, \(X(i)\) is the value of the i-th collected sample, and \(Y(i)\) is the value of the simulation in the software for the same instant. The calculation for the mean square error is defined as  
\[M_{se}(X)=\frac{1}{N}\sum_{i=0}^{N-1}(X(i)-Y(i))^{2}, \tag{29}\]  
where \(M_{se}(X)\) is the value of the mean square error, \(X(i)\) is the value of the i-th collected sample, and \(Y(i)\) is the value of the simulation in the software for the same instant. For the error variance, the statistical variable that aims to demonstrate how much the samples vary around their mean value is demonstrated by  
\[\sigma^{2}(M_{se})=\frac{1}{N}\sum_{i=0}^{N-1}(M_{se}(i)-\overline{M}_{se})^{2}, \tag{30}\]  
Figure 17: Theta inclination angle variation signal. Figure 18: Torque variation signal. where \(\sigma^{2}(M_{se})\) is the mean error variance, \(M_{se}(i)\) is the value of the i-th collected sample, and \(\overline{M}_{se}\) is the mean of the analyzed variable. Comparative analyses were performed, among the results obtained in each of the methods presented for each of the exposed scenarios. At the end of the tests and simulation results, an analysis of occupation and use of the platform is performed, highlighting points of use, such as Look up Tables (LUTs), memories, registers, and multipliers, in addition to revealing the maximum frequencies obtained in each of the implementations. In order to perform the real-time tests, it was necessary to divide the clock to a value less than 1 ms (1 KHz), in order to work with the system in time, since the platform works with an internal clock of approximately 200 MHz (5 ns). Otherwise this would result in an acceleration for the current working system (vehicle). Figure 19 illustrates the design workflow for FPGA project development using MATLAB Simulink. This design utilizes hardware libraries and automatic HDL code generation.