# Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions
## 1 Introduction
### Coarse-Grained and Fine-Grained Reconfigurable Logic  
The idea of the Reconfigurable Computing (RC) [2] paradigm is to adjust hardware architecture to fit application requirements. Instead of decomposing a function into a series of basic operations performed on fixed hardware, custom temporary data-paths optimized specifically for this purpose are generated. In theory, such an approach combines performance and energy efficiency of hardware with flexibility of software.  
Field Gate Programmable Arrays (FPGAs)--the most popular reconfigurable platforms, use fine-grained Look-Up Table (LUT) based reconfigurable logic that allows for the definition of independent custom formulas and connections for individual bits. As a result, FPGAs can be used to emulate virtually any digital circuit. However, this incredible flexibility comes at a cost. Each reconfigurable component introduces area and energy consumption overhead compared to non-reconfigurable counterparts. The complexity ofhardware with multiple configuration options for all primitives is drastically increased, which requires reducing clock frequency to achieve timing closure. Moreover, considering that not only functionality but also placement and routing of each individual gate-level operation is determined independently, both logical and physical synthesis of FPGA designs are difficult and time-consuming tasks. Furthermore, having more configuration options leads to larger configuration data size and consequently longer reprogramming times. The introduction of partial reconfiguration [3], which allows modifying functionality of some components while preserving the configuration of the rest, helped to mitigate this problem. There is however another issue: since many applications consist mostly of arithmetic operations, the flexibility of fine-grained logic often cannot be fully exploited. In order to achieve better efficiency for byte- or word-based computations, modern FPGAs combines fine-grained logic with interwoven coarser blocks such as DSPs and RAMs. For arithmetic calculation intensive applications, reconfigurable platforms based solely on such blocks can be even a better fit.  
CGRAs (Coarse-Grained Reconfigurable Architectures) is a loosely defined group of programmable devices with processing elements (PEs) of coarser spatial granularity operating on larger arguments (e.g., 32-bit words) rather than individual bits. The architectures proposed over the years vary in purpose, degree of reconfigurability, granularity level, construction of functional units, and interconnection types. As a result of the transition to a smaller number of more complex processing elements, common functionality changes for entire operands, and bus-based connection routing, CGRAs sacrifice flexibility but offer different advantages: superior performance for arithmetic operations, reduced energy consumption, and faster reconfiguration. What is more, the higher abstraction level and simplified architecture can be much more convenient for reconfigurable systems end users, especially if they lack hardware background.