# High Precision Control System for Micro-LED Displays
## 3 Experiment and Results  
In this study, a glass-based micro-LED display was fabricated using a circuit made of LTPS TFT. The pitch is designed to be 0.6 mm, and the size of the LED is 76.2 \(\times\) 152.4 \(\upmu\)m. The current-to-voltage characteristics of RGB micro-LED are shown in Figure 11.  
The materials of red, blue and green LEDs are AlGaInP and InGaN/GaN. The voltage required for the R LED is approximately 1.8 V, which is lower than that of the G and B LED counterparts, which require 2.5 V. Then, the RGB micro-LED components are mounted on the panel with the mass-transfer machine, as shown in Figure 12.  
Figure 11: The current-to-voltage curves of RGB micro-LED. The control board is designed using four pieces of FGPA, DAC, ADC and SPDT, the power conversion chip and other components. In order to confirm the efficacy of the proposed method, we use the XC7A200T FPGA to present a new architecture to implement the micro-LED displays. The FPGA core board is shown in Figure 13. As the FPGA core board has access to a total of 180 I/O pins, and given that we require a total of approximately 730 I/O pins, we determine that we will require four FPGA core boards to both manage and operate the micro-LED displays effectively. We employ 10-bit DAC and ADC to obtain grey-scale voltage. With 1024 grey levels, the minimum driving voltage is about 7.8 mV. The supply voltage is 5 V, meaning that we use the power conversion chips to supply the FPGA power and panel power. Then, the micro-LED panel is connected to the control board through a flexible printed circuit, as shown in Figure 14.  
The control signals and 1-6 columns of RGB data for the micro-LED displays are generated by the master FPGA. The remaining columns of RGB data voltage (7-12, 13-18 and 19-24) are generated by the FPGA_2, FPGA_3 and FPGA_4, respectively, to enable complete control of the displays. Various control signals are obtained through FPGA programming according to the timing relationship in Figure 13. The simulation waveform of the whole control system was obtained through Verilog programming, as shown in Figure 15. The actual waveform that was obtained through an oscilloscope measurement is shown in Figure 16.  
Figure 12: The micro-LED panel. Figure 13: FPGA core board. Figure 12.0 _Cont._  
Figure 12.1 The control board. Figure 12.2 The simulation results. The master FPGA generates signals with specific frequencies that are then transmitted to the SPDT. The SPDT is loaded with voltage to obtain various pulse signals, including CLK1, CLK2, IN, NM and EM. As can be seen from Equation (1), the display duration and grey levels of the display are dependent on the SWEEP's variation precision. Therefore, the 12-bit DAC is used in this work to increase the accuracy of the SWEEP's ramp performance. The SWEEP has a voltage range of 0 to 9 V divided into 4096 steps, with every step's amplitude reduced by 2.2 mV. While RGB data voltage vary from 0 to 8 V, which is divided into 1024 steps according to the 10-bit grey-scale, and the voltage variation in each step is 7.8 mV. Therefore, the SWEEP's precision meets the 10-bit RGB data output demand. The SWEEP and PWM obtained via oscilloscope measurement are shown in Figure 12.3  
To demonstrate the real-time system for micro-LED displays, the video is conveyed through HDMI to the control board. And then the video data are processed by FPGA and sent to the panel. Considering that the TFT writing time is about 3 us and the regulation of time-slice dispersion from Figure 10, the values of N and M can be set as N = 7 and M = 5. From the Equations (4) and (5), it can be deduced that the high grey-scale refresh rate is 2100 Hz, and the low grey-scale refresh rate is 300 Hz. The power consumption of the 24 \(\times\) 46 array is about 0.8 W. Figure 18 shows the picture of the micro-LED. Figure 12.4 The frequency, period, rise time, fall time, maximum value, minimum value of (**a**) CLK, (**b**) IN, (**c**) NM and (**d**) EM.