## 4 Discussion  
Previous studies on NPFG transistors have demonstrated advantages such as multi-level synaptic weight representation and an extended memory window. The NPFG device previously fabricated by our group also exhibited comparable performance [25]. However, it faced limitations in terms of reproducibility. The primary factors contributing to reduced reproducibility are the non-uniform distribution of nanoparticles (NPs) and the challenges associated with size control. To address these issues, this study proposes Mesh-FGT to achieve a more uniform floating gate pattern.  
In the proposed structure, individual floating gates with dimensions of 3 \(\upmu\)m \(\times\) 3 \(\upmu\)m were arranged in a mesh pattern using a contact aligner, facilitating uniform pattern formation. Furthermore, the size of the floating gates can be readily adjusted through a fabrication process involving IR lithography, sputtering, and lift-off techniques. The memory window was observed to be 2.4 V initially and sustained a value above 1.8 V over a duration of 2880 min.  
Despite these advancements, the present design has certain limitations. The individual floating gates implemented in this study have a dimension of approximately 3 \(\upmu\)m \(\times\) 3 \(\upmu\)m,  
Figure 7: Retention, a characteristic of device behavior. Two days of changes in (**a**) threshold voltage and (**b**) drain current.  
posing challenges in forming an effective mesh pattern in transistors at the nanometer scale. Moreover, the current architecture is based on a single transistor, limiting its scalability for neuromorphic applications that require large-scale parallel computation.  
To overcome these limitations, future research will proceed in two main directions:  
First, future work will focus on reducing the size of individual floating gates to the nanometer scale. Specifically, a 10 nm \(\times\) 10 nm floating gate mesh structure will be fabricated using electron beam lithography (E-beam lithography). As the floating gate size decreases, the feasibility of Mesh-FGT in nanoscale transistor environments will improve. Additionally, an increased number of floating gates is expected to enhance charge storage capacity, enabling finer synaptic weight representation. These advancements are anticipated to expand the memory window and improve multi-level performance, while also reducing the overall gate area of the device.  
Second, building upon the characteristics of the single Mesh-FGT studied here, future research will explore its scalability to an array-based architecture. By constructing 2 \(\times\) 2, 3 \(\times\) 3, and 4 \(\times\) 4 Mesh-FGT arrays, the feasibility of parallel computation in neuromorphic systems will be examined. This expansion aims to assess the potential of Mesh-FGT as a fundamental component in large-scale neuromorphic computing beyond its role as an isolated device. To support this, further studies will involve array-based structural scaling as well as statistical analysis using multiple devices, ensuring reproducibility and consistency across larger systems.  
By addressing these research directions, Mesh-FGT has the potential to overcome the reproducibility challenges associated with NPFG transistors, enable integration into nanoscale transistor environments, and serve as a critical element for neuromorphic computation.