# Elliptic-Curve Crypto Processor for RFID Applications
## 2 Preliminaries
### PM Computation over \(Gf(2^{M})\)
The input to the demultiplexer is from the arithmetic unit (\(wdata\)) while the outputs are connected to each particular register in the employed register array. For each read/write operation, one clock cycle is required. A single red color line in Figure 2, from the command controller to register array, indicates the corresponding control signals (total three, one for the write and the remaining for the read) for the read/write operands. ### Shift Buffers/Registers

The purpose of this block is to keep/store the coordinates of point \(P\) and a constant parameter (i.e., \(b\)) of ECC. As shown in Figure 2, the proposed architecture constitutes three \(m\)-bit shift registers, i.e., \(xp\), \(yp\), and \(b\). Moreover, it contains one \(3\times 1\) multiplexer (not given in Figure 2) to select an appropriate ECC parameter using \(rdata\) for the arithmetic unit. The \(wdata\) with the corresponding control signal (shown with red color in Figure 2) is input to shift buffers/registers block from the command controller to write on a particular register with an 8-bit shift. Whenever the ECP is activated by setting the \(start\) signal, 8-bits

Figure 2: Proposed Hardware Accelerator Architecture of ECP. from LSB (least significant bit) to MSB (most significant bit) of either \(x\) or \(y\) coordinates of the initial point, \(P=(x_{p},y_{p})\) are loaded into the corresponding \(xp\) or \(yp\) shift register. With the same \(m\)-bit operand length and shift register size, \(\frac{m}{g}\) clock cycles are required. Therefore, our architecture deals with 163-bit; however, 21 additional clock cycles are required to load a 163 bit operand into a shift register. At the beginning (when start becomes 1), we have loaded (serially) the required ECC parameters and coordinates of point \(P\) into a corresponding shift register with an expense of 63 (\(3\times 21\)) clock cycles. It allows us to use the coordinates of point \(P\) and ECC parameters directly from the shift registers, instead of re-loading externally, during the implementation of Algorithm 1. ### Arithmetic Unit

The arithmetic unit of the proposed ECP accelerator architecture consists of an (i) adder, (ii) multiplier, (iii) square, (iv) controller (AU-controller as shown in Figure 2) and a routing multiplexer. The shaded portion with a gray color in Figure 2 determines the polynomial inversion with a combined use of squarer and multiplier blocks. The description of these arithmetic operators (adder, multiplier, squarer, reduction and inversion) and additional arithmetic unit blocks (Au-controller, routing multiplexer) is given as follows:

* **Adder (ADD) and Squarer (SQR):** The adder and squarer blocks require only one clock cycle for the computation. Therefore, the adder inputs two \(m\)-bit operands and gives one \(m\)-bit output after performing bitwise the Exclusive (OR) operation. On the other hand, the squarer inputs an \(m\)-bit operand and results a \(2\times m-1\)-bit output. In \(GF(2^{m})\), a squarer is simply implemented by inserting 0's after two successive data bits. * **Multiplier (MUL):** The performance of the entire crypto architecture is dependent on the performance of the utilized multiplier. Therefore, there are several approaches to perform polynomial multiplication, i.e., bit-serial, bit-parallel, digit-serial, and a digit-parallel. A comprehensive comparison over these multiplication approaches is presented in [28]. Comparatively, the bit-serial multipliers are more useful for low-area and low-power applications while for high-speed applications, a bit-parallel and digit-parallel approaches are more convenient. The digit serial multipliers are more beneficial where high-speed and low-area parameters are required to consider at the same time. Moreover, in bit-serial multipliers, the low-area and low-power values can be achieved with an additional cost on clock cycles. For example, for multiplication over two \(m\)-bit operands length, \(m\) clock cycles are required.