# A g\({}_{m}\)/I\({}_{\rm D}\)-Based Low-Power LNA for Ka-Band Applications
## 2 Design Procedure
\[Z_{in}=r_{g}+s(L_{G}+L_{S})+\frac{1}{sC_{g}s}+\frac{g_{m}L_{S}}{C_{g}s} \tag{4}\]  
\[Re[Z_{opt}]\approx\sqrt{\frac{r_{g}}{2g_{m}}}\times\frac{f_{T}}{f} \tag{5}\]A total device width close to 50 \(\upmu\)m is determined to satisfy the condition of an Z\({}_{opt}\) with a real part close to 50 \(\Omega\). To provide some insights into the impedances defined in (4) and (5), a graphical representation is more clearly reflected in Figure 4. Proper choice of the source inductor value can ensure that Z\({}_{opt}\) and Z\({}_{in}\)\({}^{*}\) are approximately equal for maximum power transfer. Then, a single gate inductor can be used to cancel the capacitive component at the gate of M\({}_{CS}\) in Equation (4). For the selected technology and the transistor employed, the total width value is determined to be 50 \(\upmu\)m. The design approach consists of selecting a certain IC value that accommodates the specifications of the LNA. To decide which IC should be used, consider the following discussion. The transit frequency f\({}_{T}\) limits the frequency of operation and factors such as the achievable gain and NF [38]. The f\({}_{T}\) is closely related to the IC, as shown in Figure 3b. If the transistor's f\({}_{T}\) is too close to 28 GHz, the LNA may not achieve a reasonable performance (low gain and high NF), but it may have low power consumption, as the lower the IC, the lower the drain current needed to bias the device. On the other hand, if the f\({}_{T}\) is very high (\(n\) times the operating frequency), the LNA will offer very high performance (high gain and low NF), but with high power consumption. The advantage of using the g\({}_{m}\)/I\({}_{D}\) methodology is that the designer can access the LUTs and produce several sets of values to perform several designs. As an example to carry on with the design, consider three values: f\({}_{T1}\) = 44 GHz, f\({}_{T2}\) = 98 GHz, and f\({}_{T3}\) = 175 GHz. Since the value of f\({}_{T}\) is approximately given by (6) for a MOSFET and g\({}_{m}\) increases as does I\({}_{DS}\), the f\({}_{T}\) increases as the IC is augmented. The moderate inversion region is targeted for 44 GHz, the moderate-strong inversion region for 98 GHz, and the strong inversion region for 175 GHz. Operation in weak inversion results in a very high aspect ratio (W/L), and, therefore, the device presents significant capacitance with low drain current, resulting in poor high-frequency operation. The proof-of-concept design process is conducted for these f\({}_{T}\) values to make a comparison and select the best performance compromise. From Figure 3b, the value of IC is deduced, which is needed to obtain the DC operating point from the LUTs. In the case of the 44 GHz frequency, the corresponding IC\({}_{1}\) value is 0.48. For 98 GHz, IC\({}_{2}\) has a value of 1.58, and for 175 GHz, IC\({}_{3}\) has a value of 4.92. The next step is to calculate the values of threshold voltage (V\({}_{TH}\)) and effective gate-source voltage or overdrive voltage (V\({}_{GSeff}\) or V\({}_{ov}\)) to properly bias the MOSFET. These parameters are plotted as a function of IC, as illustrated in Figure 5a,b. \[f_{T}=\frac{g_{m}}{2\pi(C_{gs}+C_{gd})} \tag{6}\]  
The required V\({}_{GS}\) voltage for the transistor to operate with the desired IC can be deduced from the previous figures and is given by Equation (7). V\({}_{GS}\) sets the desired current flowing through the FETs, and thus, the higher the IC, the higher the V\({}_{GS}\) needed to bias the device with the desired drain current. For the 44 GHz f\({}_{T}\) case, V\({}_{GS1}\) has a value of 182.41 mV to obtain a drain current of 0.67 mA; for the 98 GHz case, V\({}_{GS2}\) is 255 mV for I\({}_{D}\) = 2.2 mA; and for the 175 GHz case, V\({}_{GS3}\) = 360 mV to set an I\({}_{D}\) of 6.8 mA. Figure 4: Schematic used to obtain the input and optimal NF impedances.