## 3 Analysis of the Switching Transients
### Turn-On Switching Transients
\[E(\text{II})_{sw,g2}=\int_{t_{1}}^{t_{2}}i_{ch}v_{ds}dt \tag{14}\]  
_Stage 3 [12, 13, 14] voltage falling time I_: As the current is transferred to the SiC MOSFET, the SiC Schottky Diode (SBD) becomes capable of blocking the voltage; Figure 4c shows the equivalent circuit of this stage, and the drain-source voltage \(v_{ds}\) drops dramatically at the same time, if the _case I_ occurs in the previous stage. The gate-source voltage \(v_{gs}\) is maintained at the Miller Plateau, because the gate current \(i_{g}\) is completely absorbed by the drain-source capacitance \(C_{ds}\) without flowing to the gate-source capacitance \(C_{gs}\). Although SBD features zero reverse recovery current, the drain current id continues to increase since the charging current of junction capacitance \(C_{f}\) of the SiC SBD. Therefore, (11) is replaced by (15), and the rest remains unchanged. A resonant period begins in this moment, which induced by the oscillations between \(L_{p}\) and \(\text{C}_{f}\). This stage ends when drain-source voltage \(v_{ds}\) decreases to \(v_{gs}-V_{th}\). Figure 4:0  
There are five independent state variables: the drain current \(i_{g}\), the drain current \(i_{d}\), the gate-source voltage \(v_{gs}\), the drain-source voltage \(v_{ds}\) and the free freewheeling diode voltage \(v_{f}\). The state equations at this stage are shown in Appendix A Equation (A4). During this period, the two type of switching loss calculation as following:  
Figure 4:1  
Figure 4:2  
Stage 4[13; 14; 15; 16; 17] voltage falling time II:When the drain-source voltage \(v_{ds}\) decreases to \(v_{gs}-V_{th}\), the SiC MOSFET will come out of the saturation region and get into the ohmic region. As shown in Figure 4d, the channel is equivalent to a nonlinear resistance (also called on-state resistance) in this stage. Therefore, (10) is replaced by (18). The gate-source voltage \(v_{gs}\) breaks out of the Miller Plateau and begins to increase again. The drain-source voltage \(v_{ds}\) drops slightly in this period, and the drain current id drops back to \(I_{DD}\) simultaneously. The oscillations in the power loop will be damped by the stray resistance resulting from the PCB traces. In order to specify this point, a lumped resistance \(R_{stray}\) is added in the equivalent circuit, as same as the stray inductances, to compensate for the active power consumption and (9) should be replaced by (19). Once the drain-source voltage \(v_{ds}\) decreases to \(i_{d}\cdot R_{on}\), this stage ends and the channel can be seen as completely conductive. Figure 4:3  
Figure 4:4  
The independent state variables at this stage remain unchanged and the state equations are shown in Appendix A Equation (A5). The switching loss in this period can be calculated as:  
Figure 4:5  
Figure 4:6  
Stage 5[14; 15; 16; 17] On-State Operation:The gate current \(i_{g}\) still continues to charge the gate-source capacitance \(C_{gs}\) until the gate-source voltage \(v_{gs}\) reaches the positive drive voltage \(V_{GG}\). The state equations and the equivalent circuit are the same as the previous stage, while the loss at this stage is considered as conduction loss \(E_{cond}\) and can be calculated as:  
Figure 4:7