# Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology
## 6 Performance Analysis and Comparison  
Using the 45 nm CMOS technology node and the In-plane Magnetic Anistrophy (IMA) MTJ Compact model [22], we compare the delay, energy consumption, and transistor count between a baseline island-style FPGA and our stochastic-based spin-programmable gate array (SPGA). Specifically, the MTJ device parameters include: \(I_{\mathrm{d0}}=0.1\) nA, \(n=2\), the critical current \(I_{\mathrm{c0s}}=50\)\(\mu\)A, the characteristic resistance \(R_{\mathrm{P}}=1\) K\(\Omega\), \(R_{\mathrm{AP}}=2\) K\(\Omega\), \(E/k_{\mathrm{B}}T=60\), the relaxation time \(t_{\mathrm{relax}}=50\) ps, and the attempt time \(t=1\) ns. The 45 nm CMOS technology is modelled with the Berkeley Predictive Technology Model (BPTM) [36] for both devices and interconnects. As in [14], we assume an island-style FPGA as the baseline architecture, referred to henceforth as _baseline FPGA_, for our performance comparison. It comprises a 2D array of logic blocks (LBs) interconnected via programmable routing. We assume each LB comprises four logic slices, each consisting of two 4-input Lookup Tables (LUTs), two flip-flops (FFs), and programming overhead. The routing fabric comprises horizontal and vertical routing channels each having sets of Single, Double, HEX-3, and HEX-6 interconnect segments. We classify the interconnects into two groups, _short_, which includes Single and Double FPGA tile width interconnects, and _long_, which includes HEX-3 and HEX-6 interconnects. The segments can be connected to the inputs and outputs of the LBs via _connection boxes_ and to each other via _switch boxes_. We assume the MUX-based switch box design described in [37]. For the SPGA architecture, we choose four benchmark circuits to first determine the input number \(m\) and output number \(n\) for each stochastic-based logic block. The logic synthesis and technology mapping for a given benchmark was conducted with a modified version of the ABC tool based on computing the full covering with (\(k\), \(l\))-cuts as discussed in Subsection 5.1. As shown in Figure 12, with the output number of SLBs increasing, for all four benchmarks, the total number of SLBs will decrease significantly. Not surprisingly, when we increase the input numbers, the total number of SLBs also decreases. However, just as in the case of island-style conventional FPGA, there exists a trade-off between logic block granularity and average net/critical-path delay, in the case of SPGA architecture, there is an additional trade-off between the output number and the total delay performance. This is because, as the output number increases in SLB, the number of total random samples required to compute logic function also increases, therefore prolonging the processing time. In this study, we choose (\(m\), \(n\)) = (5, 2) for all measurements. To accurately measure the chip area of all FPGA architectures we compared, we adopted two different methodologies. For the 2D island-style FPGA, we used the area modelling method at the transistor level, which was first developed in [28; 38]. The based FPGA is first decomposed into components including SRAM based LUTs, flip-flops, intra-cluster muxes, inter-cluster routing muxes and switches. The chip area of each of these components is then estimated by counting the total number of minimum-width transistors used. Figure 13 depicts this simple transistor area model. For the SPGA implemented with the hybrid MTJ-CMOS technology, we have to account for its \"3D effect\". Figure 12: The logic synthesis of large fanin and multiple fanout Loop-Up table is shown and simulated through logic synthesis tool ABC. The 4 benchmark circuits are taken into consideration. In this Figure, we can see to deceasing trends, one is with Look-Up table size increasing, another is with output increasing. The results show that with the Look-Up table size and output number increasing. The number of nodes in logic network is significantly decreasing. The ratio of decreasing is trending slow, since the small input and output node is decreasing.