# A Reconfigurable Radio-Frequency Converter IC in 0.18 \(\upmu\)m CMOS
## 3 System Architecture
### Frequency Synthesizer  
The input RF signals oscillate in the range from 470 MHz to 1000 MHz; then, they need to be up-converted to 1350 MHz of the pass band of the SAW filter that performs channel selection; and, finally, down-converted to the 470 MHz to 868 MHz input range of television sets. Considering the above figures, it can be obtained that the LO must provide frequencies at least up to 2.35 GHz. Nevertheless, because the operation frequency of integrated gigahertz oscillators suffers from process, voltage and temperature (PVT) variations, the oscillator in this work has been designed to provide frequencies up to 2.7 GHz. On the other hand, because this application demands a very high frequency resolution and low phase noise, the oscillator is based on two independent, complementary _LC_-tank voltage-controlled oscillators (VCOs) with a 7-level capacitor bank for a dense coarse frequency tuning, which are placed in an integer-N PLL with an 8/9 dual-modulus prescaler with current-mode-logic (CML) dividers to operate at the required  GHz speed. To achieve the frequency resolution required for the application in this work (1 MHz), the reference frequency for the synthesizer is obtained dividing a 20 MHz reference from a TCXO by 20. The frequency synthesizer in this work needs to provide an oscillating signal with a frequency up to 2.7 GHz, which means that it needs to cover independently a range from 1.35 GHz to the desired 2.7 GHz, as lower frequencies can be generated by frequency division. Figure 5a shows the block diagram of the frequency synthesizer. The target application of this work requires the signal generated by the synthesizer to be stable and feature a low phase noise, well below the \(-100\) dBc/Hz at a 1 MHz offset from the carrier in all the tuning range. For this reason, a resonant LC-tank-based voltage-controlled oscillator (LC-VCO) has been used at the core of the synthesizer, based on the implementation in [16]. Although LC-VCOs achieve a much better phase noise performance than their ring-VCO counterparts, care needs to be put into their design so that they can be correctly incorporated in frequency synthesizers. The main reason for this is two-fold [17]. On the one hand, the frequency tuning of an LC-VCO is done modifying the capacitance of an MOS varactor, whose variation is around 10% of its nominal value; this translates into a 5% variation in the oscillating frequency, a value that is typically not enough to encompass PVT variations. Figure 4: Block diagram of the reconfigurable RF converter RFID-II, formed by two variable frequency synthesizers, two passive mixers, and auxiliary circuitry. On the other hand, a wide frequency variation is not desirable either because the phase noise of a PLL shows a tight dependency on the frequency tuning gain (\(K_{VCO}\)) of the VCO so that an increase in \(K_{VCO}\) makes any ripple at the VCO control voltage produce large frequency variations on the VCO output signal, and thus increase the phase noise of the PLL. To increase the tuning range of the oscillator without harming the performance of the PLL, a bank of binary weighed switched capacitors has been added in parallel to the MOS varactor. In this widely used solution, the variation of the varactor capacitance yields the fine frequency tuning of the oscillator and the connection/disconnection of the binary weighed capacitors from the bank, using a digital word, yields its coarse frequency tuning. Finally, the frequency synthesizer in this work, and thus the oscillator, needs to cover a wide frequency range of over 1 GHz. Using only one LC-VCO for this purpose would have caused serious difficulties in the design and management of the switched capacitor bank because it would require a very large ratio between the size of the largest and smallest capacitors in the bank to achieve the full tuning range.