## 6 Experimental Results
In this experiment, CS is implemented using first-order differential equations as shown in \(M_{Proc}\) model of Figure 8. The simulation execution time is analyzed by changing the time step size. The result is displayed in Figure 11. The hardware condition of this experiment is 16 CPU cores and four GPUs. We change the step size for computing a CS from 0.1 to 0.0001. As the time step size changes from  
Figure 10: Execution time of simulation according to the number of cells. \begin{table}
\begin{tabular}{c c c c} \hline
**Hardware Configuration** & **Without the CUDA MPS** & **With the CUDA MPS** & **Reduction Rate** \\ \hline
16 cores + 1 GPU & 2.206 s & 1.227 s & 44.369\% \\
16 cores + 2 GPUs & 1.289 s & 0.704 s & 45.339\% \\
16 cores + 3 GPUs & 0.951 s & 0.565 s & 40.571\% \\
16 cores + 4 GPUs & 0.666 s & 0.537 s & 19.354\% \\ \hline \end{tabular}
\end{table} 
Table 3: Reducing execution time of the GPU by using the CUDA MPS. 0.1 to 0.0001, the difference between the simulation time using only the CPU and the simulation time in the CPU-GPU heterogeneous architecture increases from 0.05 times to 3.1 times. In addition, each execution time of the 16 CPU cores, such as in case 4, has a significant difference. The difference between CPU-only simulation time when using a 0.1 step size and a 0.0001 step size is 3.7 times. However, at the same time step condition, the simulation time difference of the proposed structure, especially in case 8, is only 0.02 times. The results reveal that all of the execution times of the proposed CPU-GPU framework-based simulation are similar and the result shows that the proposed architecture is very efficient in terms of simulation time when simulating a large-scale system that includes multiple floating-point calculations such as CS. We also analyze our approach in terms of additional memory usage by the GPU, as shown in Table 4 and detailed the execution time for analyzing the bottleneck when copying data between the host and the device. The table shows that each GPU requires about 680 MB of additional memory; in particular, case 8 requires 2.5 GB of additional memory. Although additional memory is used, we discover that the execution time is dramatically improved by using the proposed heterogeneous simulation architecture. We compare the maximum power consumption and the simulation execution time for eight hardware cases to find out the efficiency, as depicted in Figure 10(b). The power consumption of the CPU is obtained theoretically, and the power consumption of the GPU is obtained using the _nvidia-smi_ tool. The experiment condition follows: 2,880,000 cells, 0.0001 step size, and eight hardware configurations. The result shows that the two values of the power consumption and the execution time are inversely related to each other as expected. When high power is consumed in the simulation, high-performance results can be obtained in terms of the execution time. Among the results obtained by the configuration of eight hardware devices, case 4 and case 5, which have similar power consumption, is analyzed as follows. The maximum power consumption of case 5 and case 4 is 405 Watts and 353 Watts, respectively, and the result of case 5 is about 14% higher than that of case 4. However, regarding the execution time \begin{table}
\begin{tabular}{c c} \hline \hline
**Hardware Configuration** & **Memory Usage in GPU** \\ \hline
4 cores + 1 GPU & 686 MB \\
8 cores + 2 GPUs & 1308 MB \\
12 cores + 3 GPUs & 1938 MB \\
16 cores + 4 GPUs & 2552 MB \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Additional memory usage. Figure 11: (a) Execution time of simulation according to the step size of differential equations; (b) maximum power consumption according to the hardware configurations. of both simulations, case 5 is about 30% faster. That is, the simulation execution time is further reduced compared to the additional power consumption.