## 4 PAU-RAD Design, Development and Integration
### PAU-RAD Hardware Description  
The hardware involves the design of the RF-IF receiver, analog-to-digital converters set [11], digital design and FPGAs, power management and thermal insulation and control. The thermal control part consists of a commercial Proportional Integrative Derivative (PID) control using a 100 Platinum Resistance Thermometer (PT100) sensor, offering an excellent accuracy over a wide temperature range. The control uses an H-bridge to drive enough current to eight 2 A Peltier cells, which are the active part of the control. Each Peltier cell is assembled with fans and heat sinks to ensure an efficient thermal system. PAU-RAD is thermally insulated by using expanded polystyrene foam (EPS) boards, which has a high thermal resistivity [26] of about 28 mK/W. Moreover, internal fans are used to obtain a good temperature homogenization. With this thermal control system, a previously tested demonstrator [11] has achieved an internal temperature variation of \(\Delta\mathrm{T}_{\mathrm{internal}}<0.2\)\(\mathrm{\SIUnitSymbolCelsius}\). The radiometer's core (Figure 8) consists of an analog part, that performs the RF-IF down-conversion from 1.57542 GHz to 4.039 MHz, and a digital part, that performs the DBF and the correlation radiometer. The RF-IF receivers (Figure 2) are the most sensitive parts of the analog part and they have been specially designed to avoid channel cross-talk, EMC problems, and to achieve a frequency response of at least 30 dB attenuation in the rejected band (Figure 9). Figure 7: PAU sub-systems. (Top left) opened RF-IF dual-polarization receiver with four channels. (Top right) dual-channel ADC sub-system. (Bottom) processor terrace that is placed in the middle of the instrument (Figure 6) and contains the CNS, clock distribution, ADC set, clock reference, clock distribution, and FPGA where the digital hardware and the software algorithms are implemented. As discussed in Section 3, the DBF implies strong hardware calibration requirements. The RF front-end was designed with these _a priori_ specifications. Two switches at the RF section of each receiver, allow the selection of the input from three different ports: (a) The antenna signal, for radiometric measurements; (b) the correlated noise signals, for phase and amplitude calibration purposes; and (c) the uncorrelated noise signals, for offset calibration purposes. The antenna signal  
Figure 8: Analog and digital hardware block diagram. Note that each I/Q down-converet has its own Numerical Controlled Oscillator (NCO). Figure 9: Typical frequency response of a RF-IF receiver. The test receiver has been driven with a CW input of \(-\)130 dBm at f\({}_{\text{GPS-L1}}\) = 1,575.42 MHz. The output is a tone with a \(-\)19.52 dBm at f\({}_{\text{IF}}\) = 4.309 MHz. The rejected-band has a \(>\)40 dB of attenuation with respect to the pass-band. input is connected directly to the patch antenna, while the uncorrelated noise input is connected to an internal matched load. The most relevant input port is the correlated noise one, which is connected to the CNS (Figure 10) through a 1:16 power splitter for calibration purposes (Section 3.2) for all the system receivers. The CNS consists of a temperature controlled box with a very stable noise source (NC346, \(\mathrm{ENR}=17.5\) dB at 1.5 GHz, 0.009 dB/K and 0.002 dB/% V), a variable attenuator, and a mechanical switch connected to the variable attenuator and to a matched load. With this hardware configuration (CNS + power splitter) and properly choosing the attenuators, it is possible to have a common signal of 450, 370 or 300 K at the input of each receiver. Receivers' response is linear within these three values and they are separated enough to ensure a correct performance of the differential calibration (Section 3.2). The digital part, embedded inside the FPGA, has been designed in two parts for simplicity (Figure 11).