## 2 Materials and Methods
### Controller Design  
To implement the described voltage-regulation strategy, a low-level control system for the grid-interfacing power electronic converter is developed. The whole system and its control block scheme are depicted in Figure 3. It is assumed that the energy storage in the form of a battery or super-capacitor bank is connected through the DC-DC converter to the DC-link capacitor of the grid converter. It operates in closed-loop DC voltage control mode; therefore, the grid converter is free to exchange active and reactive power with the network, within its capacity. Figure 2: Voltage regulation: (**a**) using reactive power and (**b**) using active and reactive power with minimal current. The control structure designed for the shunt compensator with energy storage is based on a closed-loop local grid voltage control. The control is based on the transformation of three-phase quantities to the Dual Synchronous Rotating Frame (DSRF) [32]. It is based on a two-coordinate system (\(dq\) frames), rotating counterclockwise with angular speed corresponding to voltage frequency. After decoupling, positive and negative voltage sequences appear as DC components in their respective frames. Finally, the DSRF algorithm estimates positive and negative voltage sequences (\(u_{d}^{+}\), \(u_{d}^{-}\), \(u_{q}^{+}\), \(u_{q}^{-}\)) from \(u_{PCC}\) measurements. A conventional Synchronous Reference Frame Phase-Locked Loop (SRF-PLL) synchronizes the rotating frame with the positive voltage sequence to produce the phase angle \(\theta\) for all reference frame transformations used within the control structure [33]. There is no separate PLL for the negative sequence voltages, as their value is controlled to be zero. Phasor representation of voltage amplitude and unbalance is represented by phasors, as shown in Figure 4.  
Figure 4: Phasor representation of voltages in DSRF. Figure 3: Block scheme of the proposed shunt-conditioner control system (* denotes reference values). Details of the voltage controller are shown in Figure 5. Negative voltage sequence components \(u_{q}+\) and \(u_{q}-\) are given as errors to the proportional-integral (PI) controllers. For the positive sequence, the difference between voltage set point \(u_{N}\) and voltage module \(u_{d}+\) is used as a controller error (quadrature component \(u_{q}-\) is neglected, as it is regulated to zero by PLL). The estimated grid impedance \(Z_{k}\) parameters are used in the voltage control loop. Its modulus is used for controller tuning, while its phase angle \(\varphi_{k}\) allows to determine active and reactive current components, which satisfy the minimum compensator current criterion explained in Section 2.2. Reference currents generated by the negative sequence controller are then summed up and transformed from negative to positive Synchronous Reference Frame (SRF), to create the final current reference (\(i_{d}^{*}\), \(i_{q}^{*}\)) for the compensator. In this way, the positive (magnitude) and negative (unbalance) fundamental components are controlled simultaneously. The current controller operates in the positive rotating SRF. Here, a negative sequence appears as oscillating components with double grid frequency. Typically, applied PI controllers do not provide a dynamic response high enough to control this oscillating component. To overcome this problem, a resonant path is added in parallel to the controller, as shown in Figure 6. Tuning this path to the double grid frequency results in cancellation of the steady-state error for oscillations representing negative current sequence. Gains of current PI controllers used in the algorithm are tuned using symmetrical optimum method, while gains of voltage PI controllers used in the algorithm are tuned using magnitude optimum method. Figure 5: Voltage controller operating in DSRF (* denotes reference values). Figure 6: Current controller with resonant path (* denotes reference values). Finally, Space Vector Modulation (SVM) is used to generate switching patterns for the converter transistors.