## 3 Design of the Wirelessly Activated Node
### Top Layer Radiative Part for Wireless Energy and Data Transfer  
With reference to Figure 4c, the multi-layer arrangement with optimized locations of the two antennas has been implemented as follows: the top layer consists of the radiating elements designed to operate in the presence of metal plates; for this purpose, a miniaturized square patch antenna (Figure 4a) has been chosen for WPT. The bottom layer, which is isolated by the top one by means of the ground plane, hosts the RF-to-DC rectifier, the radio, and the baseband subsystems for power managing purposes, except for the two energy storage capacitors that are located on the top layer to reduce the overall node thickness.  
We will focus now on the description of the custom patch antenna designed explicitly for the node. The shorting-pin (seven pins, in this case) technique has been adopted to reduce the antenna dimensions (a 55% reduction was obtained), allowing total node dimensions of only 2.50 \(\times\) 3.00 \(\times\) 0.32 cm\({}^{3}\), including substrate and metallization. In particular, two laminates of RO4350B (thickness: 1.524 mm, \(\epsilon_{\rm r}\) = 3.48, tan (8) = 0.0037) have been held together with a prepreg FR-4 film (thickness: 0.120 mm, \(\epsilon_{\rm r}\) = 4.5) with the aim of maximizing the realized gain (1.84 dBi), the radiation efficiency (74%), and the bandwidth (35 MHz). It is worth noting that these features have been obtained with an antenna whose dimensions are halved with respect to a traditional coaxial fed patch antenna without shorting pins.  
Finally, a plated through-hole has been designed to connect the patch with the rectifier input, located in the node's bottom layer (Figure 4b).  
The mutual position of the two antennas has been designed, with the aid of EM simulations of the whole radiating layer, to establish the maximum patch antenna substrate size reduction, to host the chip antenna, and to minimize the EM coupling and the radiation degradation of both. For these reasons, the chip antenna has been placed at the edge of one of the non-radiative sides of the patch.  
In particular, three different antenna configurations have been considered: #1 represents a full 3 \(\times\) 3 cm\({}^{2}\) antenna substrate, perfectly overlapping the bottom layer of the node, whereas #2 and #3 correspond to a 0.5-cm cut of the substrate and the ground plane in correspondence with the non-radiative and radiative side edge, respectively. This analysis has been conducted to evaluate how substrate dimensions' modifications affect the antenna  
Figure 4: (**a**) Picture of the top layer of the tag, in which it is possible to notice the shorted patch antenna for WPT, the metal-mounted chip antenna, and the storage capacitors; (**b**) bottom layer of the node, with the highlight of the main components and the RF-to-DC rectifier; (**c**) stack-up of the whole sensor node, with the antennas and the capacitors placed on the top layer, the RF and baseband components on the bottom, and the plated through-hole (PTH) connecting patch and rectifier.  
performance in order to create a location in the top layer able to host the two storage capacitors and the SMT chip antenna.  
The simulation results show that a significant performance degradation (realized gain: 0.64 dBi) occurs while cutting along the patch antenna radiative side, whereas no significant variations are observed while cutting along the non-radiative one (realized gain: 1.84 dBi). Ultimately, choice #2 (represented in Figure 4a) has been chosen, digging a 3.2 mm-thick inset on the left side of the antenna substrate to host the three above-mentioned components without increasing the overall node thickness.  
The resulting mutual decoupling between the two antennas has also been tested by measurement and it is shown in Figure 5, in terms of the transmittance parameter (S\({}_{21}\)) of the resulting two-port antenna: it is possible to notice that an isolation better than 20 dB has been obtained.