## 2 Single-Phase NPC Converter Structure and Conventional MPC Approach
### Common-Mode Voltage Term for Capacitor Voltage Balancing
They are summarized in \[v_{ref}^{b}(k+1) = v_{diff}^{b}(k+1)+v_{comm}(k+1). \tag{25}\]0  
On the basis of Table 2, one can obtain  
\[v_{ref}^{b}(k+1) = v_{diff}^{b}(k+1)+v_{comm}(k+1). \tag{25}\]1  
Using Equations (30) and (31), the polarity of the common-mode voltage can be derived as a function of the sign of the capacitor voltage difference, the source current, and the \(a\)-phase difference-mode reference voltage as:  
\[v_{ref}^{b}(k+1) = v_{diff}^{b}(k+1)+v_{comm}(k+1). \tag{25}\]2  
The amplitude of the common-mode voltage, because the phase voltage of the converter should be confined by the dc-link voltage, is determined as:  
\[v_{ref}^{b}(k+1) = v_{diff}^{b}(k+1)+v_{comm}(k+1). \tag{25}\]3  
In this paper, the magnitude of the common-mode voltage is, for fast NP voltage balancing operation, determined as:  
\[v_{ref}^{b}(k+1) = v_{diff}^{b}(k+1)+v_{comm}(k+1). \tag{25}\]4  
The common-mode voltage, which should be added to decrease the difference between the two capacitor voltages at the next step, is summarized in \[v_{ref}^{b}(k+1) = v_{diff}^{b}(k+1)+v_{comm}(k+1). \tag{25}\]5 The proposed method developed for the single-phase NPC converters can be applied to the three-phase NPC converters and other multilevel converters by modifying the common-mode voltages for appropriate converter structures. Figure 5 shows the overall structure of the proposed MPC method. The difference-mode reference voltages, \(v_{diff}^{a}(k+1)\) and \(v_{diff}^{b}(k+1)\), are in charge of controlling the source current and, thus, the actual source current can track the reference current. The common-mode voltage, \(v_{comm}(k+1)\), calculated by the voltage difference between the two capacitors, drives the NP voltage balance. As a result, the reference voltages, \(v_{ref}^{a}(k+1)\) and \(v_{ref}^{b}(k+1)\), can balance the two capacitor voltages as well as generate a five-level converter voltage waveform for source current control by simply combining the difference-mode reference voltage and the common-mode voltage. \begin{table}
\begin{tabular}{c c c c c} \hline \hline \(S_{a}\) & \(S_{b}\) & \(S_{poly}\) & \(v_{diff}^{a}\) & \(v_{comm}\) \\ \hline \(1\) & \(0\) & \(1\) & \((+)\) & \(  
Figure 6 shows a flow chart of the proposed algorithm. In the flow chart, the difference-mode reference voltage and the capacitor voltage difference are calculated on the basis of the measured source current and capacitor voltages. Using the difference-mode reference voltage and the direction of the source current, the common-mode reference voltage can be obtained. By adding the difference-mode and the common-mode voltages, the reference voltages in each phase of the converter are calculated. Once the reference voltages are obtained, the cost function is used to select an optimal switching state through repetitive operations. \begin{table}
\begin{tabular}{c c c c} \hline \hline \(\mathbf{v_{c(gap)}}\) & \(\mathbf{v_{diff}^{a}}\) & \(\mathbf{i_{s}}\) & \(\mathbf{v_{comm}}\) \\ \hline \multirow{4}{*}{\(v_{c(gap)}\geq 0\)} & \(v_{diff}^{a}\geq 0\) & \(i_{s}\geq 0\) & \(v_{diff}^{a}-\frac{V_{s}}{2}\) \\  & \(v_{diff}^{a}<0\) & \(i_{s}<0\) & \(-v_{diff}^{a}+\frac{V_{s}}{2}\) \\  & \(v_{diff}^{a}<0\) & \(i_{s}\geq 0\) & \(v_{diff}^{a}+\frac{V_{s}}{2}\) \\  & & \(i_{s}<0\) & \(-v_{diff}^{a}-\frac{V_{s}}{2}\) \\  & \(v_{diff}^{a}\geq 0\) & \(i_{s}\geq 0\) & \(-v_{diff}^{a}+\frac{V_{s}}{2}\) \\  & \(v_{diff}^{a}<0\) & \(i_{s}\geq 0\) & \(-v_{diff}^{a}-\frac{V_{s}}{2}\) \\  & & \(i_{s}<0\) & \(v_{diff}^{a}+\frac{V_{s}}{2}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Offset voltage to be injected to decrease the difference between two capacitor voltages at the next step. Figure 5: Control diagram of the proposed MPC method.