# Hybrid LLC Converter with Wide Range of Zero-Voltage Switching and Wide Input Voltage Operation
## 3 Circuit Analysis and Principle of Operation
Figure 3: _Cont._  
When \(\rm V_{in}\) is in medium voltage region (\(\rm V_{in-M}\): 100 V-200 V), \(\rm S_{ac1}\) and \(\rm S_{ac2}\) turn off. The full bridge LLC circuit and low secondary turns are used in Figure 2c. The FM scheme is used to control \(\rm S_{1}\)-\(\rm S_{4}\). The converter has gain \(\rm V_{o}\)/\(\rm V_{in-M}=2G_{ac}(f_{sw})n_{s}\)/\(\rm n_{P}\). The PWM signals and the corresponding circuits are illustrated in Figure 4 for medium voltage input condition. **Mode 1 [t\({}_{0}\), t\({}_{1}\)]:** This mode starts at t\({}_{0}\) if the drain voltages \(\rm v_{S4,d}=v_{S1,d}=0\). \(\rm i_{Lr}\) flows through \(\rm D_{S4}\) and \(\rm D_{S1}\) so that \(\rm S_{4}\) and \(\rm S_{1}\) can turn on with ZVS operation. Since \(\rm i_{Lr}(t_{0})>\rm i_{Lm}(t_{0})\), it can observe that \(\rm D_{3}\) conducts, \(\rm v_{Lm}\approx(n_{P}V_{o})/(2n_{s})\). The resonant frequency by passive elements \(\rm L_{r}\) and \(\rm C_{r}\) in mode 1 is \(\rm f_{r}=1/[2\pi\sqrt{\rm L_{r}C_{r}}]\). The load current \(\rm I_{o}\) discharges \(\rm C_{o2}\) and \(\rm i_{D3}\) charges \(\rm C_{o1}\). **Mode 2 [t\({}_{1}\), t\({}_{2}\)]:** If \(\rm f_{sw}>f_{r}\), \(\rm D_{3}\) will naturally turn off at t\({}_{1}\). This mode ends at t\({}_{2}\) and \(\rm i_{Lm}(t_{2})\approx(n_{P}V_{o})/(8n_{s}Lm_{f_{sw}})\). **Mode 3 [t\({}_{2}\), t\({}_{3}\)]:** At t\({}_{2}\), \(\rm S_{4}\) and \(\rm S_{1}\) turn off. \(\rm i_{Lr}(t_{2})\) discharges \(\rm C_{S3}\) and \(\rm C_{S2}\). Since \(\rm i_{Lm}(t_{2})>\rm i_{Lr}(t_{2})\), the diode \(\rm D_{4}\) is forward biased. To realize ZVS turn-on of \(\rm S_{3}\) and \(\rm S_{2}\), the current \(\rm i_{Lm}(t_{2})\) must be greater than \(\rm V_{in,M}\sqrt{\rm C_{oss}/(L_{m}+L_{r})}\). **Mode 4 [t\({}_{3}\), t\({}_{4}\)]:** At t\({}_{3}\), \(\rm C_{S3}\) and \(\rm C_{S2}\) are discharged to zero. \(\rm i_{Lr}(t_{3})\) is positive so that \(\rm D_{S2}\) and \(\rm D_{S3}\) are conducting. Thus, the zero-voltage switching of \(\rm S_{3}\) and \(\rm S_{2}\) can be achieved after time t\({}_{3}\). Owing to \(\rm i_{Lm}(t_{3})>\rm i_{Lr}(t_{3})\), \(\rm D_{4}\) conducts, \(\rm v_{Lm}\approx-(V_{o}n_{P})/(2n_{s})\) and \(\rm i_{Lm}\) decreases. \(\rm C_{o2}\) is charged. **Mode 5 [t\({}_{4}\), t\({}_{5}\)]:** Since \(\rm f_{r}>f_{sw}\), \(\rm D_{4}\) will naturally turn off at t\({}_{4}\). The current \(\rm i_{Lm}(t_{5})\) is equal to \(-(n_{P}V_{o})/(8n_{s}Lm_{f_{sw}})\). **Mode 6 [t\({}_{5}\), \(\rm T_{sw}\) + t\({}_{0}\)]:** At t\({}_{5}\), power devices \(\rm S_{3}\) and \(\rm S_{2}\) are turned off. Since \(\rm i_{Lr}(t_{5})<0\), \(\rm C_{S4}\) and \(\rm C_{S1}\) discharge in this mode. To realize ZVS turn-on of \(\rm S_{4}\) and \(\rm S_{1}\), the current \(\rm i_{Lm}(t_{5})\) must be greater than \(\rm V_{in,M}\sqrt{\rm C_{oss}/(L_{m}+L_{r})}\). The mode 6 ends at time \(\rm T_{sw}+t_{0}\) when \(\rm v_{CS1}=v_{CS4}=0\). Figure 3: Presented converter under high voltage input region (**a**) pulse-width modulation (PWM) signals (**b**) mode 1 equivalent circuit (**c**) mode 2 equivalent circuit (**d**) mode 3 equivalent circuit (**e**) mode 4 equivalent circuit (**f**) mode 5 equivalent circuit (**g**) mode 6 equivalent circuit. If 50 V \(<\) V\({}_{\text{in}}\) \(<\) 100 V (low voltage region, V\({}_{\text{in-L}}\)), S\({}_{\text{ac1}}\) turns off and S\({}_{\text{ac2}}\) turns on. The LLC circuit and 2N\({}_{\text{s}}\) secondary turns are used in Figure 2d. For low voltage input region, the converter has gain V\({}_{\text{o}}\)/V\({}_{\text{in-L}}\) = 4G\({}_{\text{ac}}\)(f\({}_{\text{sw}}\))n\({}_{\text{s}}\)/n\({}_{\text{p}}\). It can observe the proposed converter under low voltage input region has the largest voltage gain compared to the high and medium voltage regions. Figure 5 illustrates the PWM signals and the corresponding mode circuits. 1. **Mode 1[t\({}_{0}\), t\({}_{1}\)]:** At time t\({}_{0}\), v\({}_{\text{CS4}}\) = v\({}_{\text{CS1}}\) = 0. D\({}_{\text{S4}}\) and D\({}_{\text{S1}}\) turn on due to i\({}_{\text{Lr}}\)(t\({}_{0}\)) \(<\) 0.