## 3 Results and Discussion
Although the variation was smaller with no offset (0.4 \({}^{\circ}\)C and 0.3 \({}^{\circ}\)C for the five- and nine-via cases, respectively), it increased significantly even with slight misalignment, reaching 0.9 \({}^{\circ}\)C and 1.0 \({}^{\circ}\)C, respectively at an offset of (0.1 mm, \(-\)0.1 mm). This trend deviates from the more uniform temperature distributions observed in the pitch variation results (Figures 6 and 7), where configurations with more vias generally showed better thermal uniformity. This implies that the effective area occupied by the via array, rather than via density, plays a dominant role in determining misalignment tolerance. Figure 8: The trend of LED and substrate temperature with varying pitches of thermal vias. \(T_{\text{LED}}\), \(T_{\text{sub}}\), \(\Delta T_{\text{LED}}\), \(\Delta T_{\text{sub}}\) as a function of the pitch of thermal vias for (**a**) five thermal vias and (**b**) nine thermal vias. Figure 10 shows a comprehensive comparison between the two configurations. For the five-via case, \(T_{\text{LED}}\) increased from 75.8 \({}^{\circ}\)C (no offset) to 76.3 \({}^{\circ}\)C, 76.6 \({}^{\circ}\)C, and 78.1 \({}^{\circ}\)C as the offset increased (Figure 10a). A similar trend was observed for the nine-via configuration, where \(T_{\text{LED}}\) rose from 70.9 \({}^{\circ}\)C to 71.8 \({}^{\circ}\)C, 72.4 \({}^{\circ}\)C, and 73.9 \({}^{\circ}\)C (Figure 10b). The overall \(T_{\text{LED}}\) value was smaller in the nine-via configuration due to the higher number of vias. However, the rate of \(\Delta T_{\text{LED}}\) increase was more noticeable in the smaller pitch configurations. In both cases, even slight misalignments, as small as 0.1 mm, significantly degraded thermal performance. Such levels of misalignments fall within the typical tolerance range of surface mount technology processes considering factors such as slippage during placement, solder  
Figure 4.0 Thermal analysis of the LED module with varying positions of thermal vias. (**a**) Schematic diagrams of simulation models with five thermal vias and (**b**) corresponding temperature distributions on the LED surface (Monitor 1). (**c**) Schematic diagrams of simulation models with nine thermal vias and (**d**) corresponding temperature distributions on the LED surface (Monitor 1). In (**b**,**d**), solid lines indicate isothermal contours, and dashed circles indicate the positions of thermal vias. The labeled values indicate the lowest temperature represented in the isothermal contours. flow, or thermal expansion during reflow. In such cases, increasing the number of vias can provide a buffer against fabrication tolerances despite the accompanying complexity. It is also important that the effective working area of the via array closely matches the footprint of the LED chip to ensure efficient thermal conduction. Misaligned vias, particularly those placed outside the heat-generating area, resulted in greater degradation of temperature uniformity. This thermal nonuniformity induces asymmetric temperature distributions across the substrate, concentrating thermal stress in localized regions. In addition, thermal shock in the presence of such uneven temperature distributions can significantly elevate local mechanical stress [47]. Consequently, degradation mechanisms such as solder joint fatigue, delamination, or component detachment may be accelerated [48]. It has also been reported that vias with inner void structures due to partial filling exhibit higher sensitivity to such thermal localization [46].