## 4 Testing of DF in the FFA  
Let us evaluate the proposed solutions experimentally. Evaluation of the efficiency of the proposed conversion method is conducted based on the comparison of its conversion time with the existing methods. Evaluation is made considering the number of operation cycles of comparable devices. It is provided in Table 1.  
Figure 4: The structure of digital receiver by intermediate frequency. Figure 5: The structure of the computational channel of DF operating based on the FFA. Figure 3: The structure of digital receiver by radio frequency. The data provided in Table 1 allows concluding that the proposed method for data conversion is efficient and can be used to build DF operating in the FFA codes. The existing methods for data conversion from the positional representation to the FFA code are based on the sequential bitwise conversion of the source number. To get the modulo residue the arithmetic operations with the number bits are conducted. The type and the number of arithmetic operations depend on the conversion method. It determines the number of operation cycles for the conversion device (see Table 1). Let the base system be given \(p_{1}=5\), \(p_{2}=9\), \(p_{3}=13\). The range of the processed data in this case is \(p=585\). In the case of this implementation, the DF structure will include three computational channels (see Figure 1). Each computational channel, except the computational device implementing the filtering algorithm, includes the data conversion device (see Figure 2). In the considered case, when the conversion device is excluded from the structure of the calculation (Figure 5), in the memory device for the input sample, for example, modulo \(p_{2}=9\), the residue values for \(p=585\) will be recorded in the form of Table 2.  
Let us consider an example of a calculation of residue value for the number \(X=32\),015 modulo \(p=17\) for the method \"Lowering the bit width with the parallel adder\" (Table 1). Representing the number \(X=32\),015 in binary code and dividing it into blocks of 4 bits we obtain  
\[X=32015=0111101000111,\] \begin{table}
\begin{tabular}{c c c c} \hline \hline \multirow{2}{*}{**Conversion Method**} & \multicolumn{2}{c}{**Number of Operation Cycles**} & \multirow{2}{*}{**Benefit in Performance,**} \\  & & **of Conversion Device** & \\ \cline{2-3} \cline{5-5}  & **Bit Width of Initial Data, Bit** & & **Times (Of the** \\  & & **16** & **32** & **Developed Method to** \\  & & **16** & **32** & **the Existing Methods)** \\ \hline Lowering bit & Serial adder & 19 & 31 & 6.3/10.3 \\ width [18] & Parallel adder & 9 & 9 & 3/3 \\ \hline The method based on the block adders residue [19] & 12 & 18 & 4/6 \\ \hline The method based on the hierarchical neural & \multirow{2}{*}{24} & \multirow{2}{*}{36} & \multirow{2}{*}{8/12} \\ network of finite ring [20] & & & \\ \hline The method based the distributed arithmetic and & \multirow{2}{*}{15} & \multirow{2}{*}{15} & \multirow{2}{*}{15} & \multirow{2}{*}{5/5} \\ the parallel neural network [20] & & & \\ \hline The enhanced method based on the distributed & \multirow{2}{*}{11} & \multirow{2}{*}{11} & \multirow{2}{*}{3.7/3.7} \\ arithmetic and the parallel neural network [20] & & & \\ \hline The developed method based on the & \multirow{2}{*}{3} & \multirow{2}{*}{3} & \multirow{2}{*}{-} \\ determination of subranges & & & \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Comparative evaluation of performance of existing and developed conversion methods.