## 1 Introduction  
A millimeter-wave (mm wave) single-pole double-throw (SPDT) switch is a crucial component in mm wave phased-array transceivers. It is used in switching between the transmit (TX) mode and receive (RX) mode of each array element [1; 2; 3; 4; 5; 6; 7; 8; 9; 10; 11; 12; 13]. The requirements of an SPDT switch include low insertion loss (IL), good TX-to-RX isolation in the TX mode, good antenna-to-TX isolation in the RX mode, and decent power handling capability (evaluated via the input 1 dB compression point (P\({}_{\text{1 dB}}\))) in the TX and RX modes [3; 4; 5; 6; 7; 8; 9; 10]. CMOS processes have the advantages of high integration and relatively low cost. Recently, several mm wave CMOS SPDT switches have been reported [3; 4; 5; 6]. However, their overall performance still has room for improvement. For instance, [3] demonstrates a 21-38 GHz SPDT switch using body-floating resistance (R\({}_{\text{B}}\)) and negative body bias (V\({}_{\text{B}}\)) for the NMOS switch transistors in a 0.18 \(\upmu\)m CMOS. A high P\({}_{\text{1 dB}}\) of 25.6 dBm at 28 GHz is achieved. However, its IL of 3.6-5.9 dB is not low enough due to the high loss of the \(\pi\)-matching CLC-network at the input port (port 1) and the travelling-wave matching CLCL-networkat the output ports (ports 2 and 3). The author of [4] reports a symmetrical 25-39.5 GHz SPDT switch using a switched inductor in a 65 nm CMOS. A low IL of 0.89-1.5 dB is achieved. Yet, its isolation of 18.2 dB and P1 dB of 12.55 dBm are not satisfactory because the on-state channel resistance (R\({}_{\text{on}}\)) of the switch transistors is not low enough, and the off-state impedance (R\({}_{\text{off}}\)) of the switch transistors is not high enough. In [5], an asymmetrical 25-30 GHz SPDT switch with matching network and body-floating resistance, R\({}_{\text{B}}\), in a 65 nm CMOS is demonstrated. It achieves a low IL of 0.74-1.16/0.96-1.1 dB in the RX/TX mode and a high P1 dB of 31.8 dBm in the TX mode. However, an isolation of 16.4 dB and P1 dB of 5.2 dBm in the RX mode indicates that there is still room for improvement. This is mainly because the R\({}_{\text{off}}\) of the series switch transistor in the TX path is not high enough. In [6], an asymmetrical 20-25 GHz SPDT switch with matching network and body-floating resistance, R\({}_{\text{B}}\), in a 65 nm CMOS is reported. It achieves a low IL of 1.5-2/1.8-2.1 dB in the RX/TX mode and a high P1 dB of 32.5 dBm in the TX mode. However, its P1 dB of 4.7 dBm in the RX mode is not good enough because of the poor open circuit of the TX path due to the poor ground of the parallel stack-transistor at the TX node. The body-floating transistor technique, i.e., an NMOS transistor with large body-floating resistance, R\({}_{\text{B}}\), connected to the ground or a negative bias voltage (denoted as NMOS-R), is effective in substrate leakage (I\({}_{\text{B}}\)) suppression [3]. Therefore, it is widely used in SPDT switches for a high P1 dB [14] and in LNAs for low noise [15]. Due to threshold voltage (V\({}_{\text{th}}\)) reduction, the on-state dynamic threshold MOSFET (DTMOS), i.e., the gate connected to the body, and then, connected to a positive bias voltage, is useful in low-voltage and power circuits [16]. For a high-power-operated SPDT switch, I\({}_{\text{B}}\) suppression is crucial for a low IL and a high P1 dB. Large body-floating resistance, R\({}_{\text{B}}\), (refer to Figures 1 and 2), normally 2-10 k\(\Omega\), can be included in the DTMOS (denoted DTMOS-R) for on-/off-state I\({}_{\text{B}}\) suppression. This can be explained in more detail as follows: In the on-state, the body-to-source (B-to-S) junction of the DTMOS-R is forward-biased due to the connection of the body and gate, corresponding to a smaller threshold voltage (V\({}_{\text{th}}\)), and hence, a lower R\({}_{\text{on}}\), i.e., a better on-state. This leads to a lower IL of the SPDT switch due to the better on-state of the series DTMOS-R.