# High-Performance Garbage Collection Scheme with Low Data Transfer Overhead for NoC-Based SSDC
## 4 Evaluation  
### Experimental Setup  
We first extracted trace files from an SSD for various workloads using tools such as ftrace [19], blktrace, and blkparse [20]. Next, we modeled an eight-channel SSD system in C and measured its performance across these workloads.  
Figure 5: Configuration of dual task queue.  
For trace extraction, we used a 1 TB Samsung T5 Portable SSD, running on a host system with an Intel(r) Core(tm) i7-9700K CPU and 32 GB of RAM. The operating system was Red Hat Enterprise Linux Workstation release 7.9, with Linux kernel version 3.10.0-1160.59.1.el7.x86_64. Table 1 summarizes the key features of our SSD model configuration, which are adapted from previous studies on GC [4; 21; 22; 23; 24].  
Table 2 summarizes the delay parameters for one page read or write with the SRAM, the flash memory, and the interconnect used in our SSD model. For SRAM, we extracted delay information from single-port 16-bit SRAM from a Xilinx Spartan-7 FPGA (model xc7s100 fga676-1), manufactured by AMD, located in Santa Clara, California, USA, using Xilinx Vivado 2021.2. The delay information of NAND flash memory is from Micron MT29F4G08 ABADAH4 NAND flash model [25].  
In order to identify a realistic interconnect delay, we designed a 16 \(\times\) 8 interconnect using Verilog HDL for the eight-channel SSD and measured the timing from the synthesis results. Each task queue for a channel requires an interconnect port, similar to the DMA controllers for NAND flash memories and DRAMs, which is why we chose an interconnect dimension of 16 \(\times\) 8. We synthesized the Verilog HDL targeting the Xilinx Spartan-7 FPGA from which we extracted SRAM delay parameters. According to the synthesis report, the critical path delay between two neighboring slices is 87 ns.  
To calculate the total interconnect delay for transmitting one page between the host and NAND flash memory, we use the following formula:  
\[1\;page\; interconnect\;delay=\left(\frac{2^{15}}{4}+13.5-1\right)\times 87\;ns, \tag{1}\]  
Here, (\(2^{15}/4\)) represents the number of movements required to transmit one page. Since a page is 4 KByte and 1 byte equals 8 bits, a single page contains \(2^{15}\) bits. By dividing one page by the data transmission unit of 4 bits, we obtain the number of movements required to transmit one page. Additionally, 13.5 is the average number of slices a data transmission unit passes through, calculated by considering all possible cases. The reason for subtracting one at the end is that the actual number of movements is one less than the number of slices. Therefore, the total delay for transmitting one page across the interconnect is 8204.5 \(\times\) 87 ns, which equals approximately 714 \(\upmu\)s.  
As stated before, the bit error rate of MLC ranges from 1 \(\times\) 10\({}^{-9}\) to 1 \(\times\) 10\({}^{-4}\). In our simulation, the probability that the GC target page has errors is set to 1 \(\times\) 10\({}^{-4}\).  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Features** & **Value** \\ \hline Number of Channels & 8 \\ Planes per Channel & 4 \\ Blocks per Plane & 512 \\ Pages per Block & 64 \\ Page Size (KB) & 4 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Parameters of SSD configuration.  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Delay** & **Value** \\ \hline SRAM read (\(\upmu\)s) & 12 \\ SRAM write (\(\upmu\)s) & 12 \\ NAND read (\(\upmu\)s) & 25 \\ NAND write (\(\upmu\)s) & 200 \\ NAND erase (\(\upmu\)s) & 700 \\ Interconnect (\(\upmu\)s) & 714 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Delay of SSD components for one page read or write.