# Repeater Insertion for Multi-Walled Carbon Nanotube Interconnects
## 3 Repeater Insertion  
As shown in Figure 1, a long MWCNT interconnect is divided into \(k\) segments of by repeaters. Here, the inserted repeaters are assumed to be equispaced CMOS inverters, whose on resistance and input capacitance are obtained from the ITRS projection (see Table 1) [2]. In Figure 1, \(L\) is the interconnect length, and \(h\) is the ratio of the driver/load size to the minimum gate size. As aforementioned, each segment of the MWCNT interconnect can be modeled as an ESC model. The 50% propagation delay of one segment can be calculated by [27]  
\[T_{seg}=T_{\text{rc}}+(T_{\text{rlc}}-T_{\text{rc}})\cdot M \tag{10}\]  
where \(M=1/\sqrt{1+0.005\Big{\{}\cos\Big{[}9\text{acos}\frac{(a_{1}+a_{2})^{0.294}}{ 1.2-0.0498\delta_{3}}\Big{]}\Big{\}}^{2}}\), \(T_{\text{rc}}=T_{\text{f}}\cdot[0.4a_{1}+0.7(a_{2}+a_{1}a_{3}+a_{2}a_{3})]\), and \(T_{\text{rlc}}=T_{\text{f}}\cdot[1+a_{3}\big{(}0.342+0.397a_{2}+0.229a_{1}^{2.34}+0.642a_{1}^{13}a_{2}^{1.35}\big{)}]\), and the three basic coefficients \(a_{1}\), \(a_{2}\), and \(a_{3}\) are the normalized ratios defined as follows [28]  
\[a_{1}=\frac{\text{line resistance}}{\text{characteristic impedance}}=\frac{1}{Z_{0}} \bigg{(}R_{c}+\frac{rL}{k}\bigg{)} \tag{11}\]  
\[a_{2}=\frac{\text{driver output resistance}}{\text{characteristic impedance}}=\frac{R_{tr0}}{hZ_{0}} \tag{12}\]  
\[a_{3}=\frac{\text{load capacitance}}{\text{line capacitance}}=\frac{hK_{g0}}{cL} \tag{13}\]  
where \(R_{tr0}\) and \(C_{g0}\) are the output resistance and input capacitance of the minimum size gate, respectively, \(Z_{0}=\sqrt{l/c}\) is the characteristic impedance, and \(T_{\text{f}}=\sqrt{l}cL/k\) is the time-of-flight [28]. Based on the circuit model of a driver-interconnect-load (DIL) system in Figure 4, the accuracy of expression of the propagation delay can be examined. The driver and load are assumed to be 50 times the minimum sized gate for the intermediate-level interconnects, i.e., the driver resistance and load capacitance are \(R_{d}=R_{tr0}/50\) and \(C_{L}=50C_{g0}\), respectively. Figure 5 shows the 50% propagation delays of the intermediate-level Cu and MWCNT interconnects at the 14 nm and 7 nm technology nodes. The solid lines are obtained analytically from (10), while the dashed lines denote the simulated \begin{table}
\begin{tabular}{c c c c} \hline \hline  & **Technology Node** & **14 nm** & **7 nm** \\ \hline \multirow{4}{*}{Intermediate} & Width \(\mathbf{W}\) (nm) & 14 & 7 \\  & Aspect ratio \(\mathbf{AR}\) & 2.1 & 2.3 \\  & Dielectric thickness \(\mathbf{t_{\text{ex}}}\) (nm) & 26.6 & 13.3 \\  & Cu resistivity \(\mathbf{\rho_{0}}\) (\(\upmu\Omega\cdot\)cm) 1  & 7.43 & 11.41 \\  & \(\mathbf{c_{E}}\) for Cu (\(\text{pF}/\upmu\)m) & 130.8 & 110.3 \\  & \(\mathbf{c_{E}}\) for MWCNT (\(\text{pF}/\upmu\)m) & 115.8 & 92.4 \\ \hline \multirow{4}{*}{Global} & Width \(\mathbf{W}\) (nm) & 21 & 11 \\  & Aspect ratio \(\mathbf{AR}\) & 2.34 & 2.34 \\  & Dielectric thickness \(\mathbf{t_{\text{ex}}}\) (nm) & 31.5 & 16.5 \\  & Cu resistivity \(\mathbf{\rho_{0}}\) (\(\upmu\Omega\cdot\)cm) & 6.11 & 8.97 \\  & \(\mathbf{c_{E}}\) for Cu (\(\text{pF}/\upmu\)m) & 143.6 & 115 \\  & \(\mathbf{c_{E}}\) for MWCNT (\(\text{pF}/\upmu\)m) 2  & 124.2 & 99.7 \\ \hline \multirow{2}{*}{Minimum sized gate} & Output resistance \(\mathbf{R_{tr0}}\) (\(\upmu\Omega\)) & 30.3 & 69.7 \\  & Input capacitance \(C_{g0}\) (fF) & 0.22 & 0.13 \\ \hline \multicolumn{3}{c}{Relative permittivity of the ILD \(\mathbf{\epsilon_{r}}\)} & 2.0 & 1.6 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Geometrical and physical parameters at the 14 nm and 7 nm technology nodes. results using a commercial circuit simulator (e.g., Keysight ADS). It can be seen that the analytical and simulated results agree well with each other. With the technology node advanced, the propagation delay increases significantly due to the increased resistivity. Moreover, it is known that an MWCNT has an extremely long mean free path, which is usually several micrometers and much larger than that of Cu wire (approximately 40 nm).