# Harnessing FPGA Technology for Energy-Efficient Wearable Medical Devices
## 2 Background
### FPGAs in Wearable Medical Devices
#### 2.3.3 Low-Power FPGA Families  
The power consumption of FPGAs is primarily due to static and dynamic power consumption. Static power consumption occurs when the FPGA is powered on but not performing any active tasks, mainly due to leakage currents and depending on the underlying technology. Dynamic power consumption is associated with the switching activity within the FPGA and varies significantly based on clock frequencies and application complexity. To reduce power consumption, some manufacturers focus on technology shrinkage, while others have utilized flash-based technology to avoid the power consumption associated with SRAM technologies. Additionally, some have adopted a hybrid approach by incorporating on-chip flash configuration memory in SRAM-based FPGAs. AMD (Xilinx) Spartan-7 and Artix-7 Families: These families are known for their optimal balance between performance and power efficiency. These FPGAs utilize the 28 nm high performance-low power process, which incorporates high-K metal gate technology to significantly reduce transistor leakage by 50% compared with previous generations. This process supports voltage scaling with two operating modes--high-performance mode at a core voltage of 1.0 V and low-power mode at 0.95 V--resulting in 10% dynamic power savings and up to 40% static power savings. This technology shrinkage allowsfor reductions in both the core voltage and capacitance, achieving 40% dynamic power saving when the core voltage is scaled to 0.95 V. Additionally, power gating extends to block RAMs, reducing the overall static power, as block RAM leakage accounts for nearly 30% of total device leakage. Designers can also gate clocks at global, regional, and local resources using a clock enable, which helps reduce switching power loss in the logic core. Furthermore, the series offers partial reconfiguration capabilities, allowing users to time-slice FPGA portions to fit more IPs into smaller devices, thereby saving both power and cost. A detailed comparison is given in Table 1.  
Intel (Altera) Cyclone-V and Max-10 Families: Cyclone-V and Max-10 FPGAs are designed for low-power and cost-sensitive applications, making them suitable for wearable devices. The Max-10 series utilizes 55 nm technology with an embedded SRAM + Flash process, resulting in a maximum power consumption of approximately 1.362 W for the Max10M08 device, which provides ample logic resources. It also includes a sleep mode to significantly reduce standby power and is suitable for edge computing. In contrast, the Cyclone-VE series is based on 28 nm low-power process technology, which reduces power consumption by 40% compared with the previous Cyclone-IV generation. This series also supports partial reconfiguration and includes numerous hard intellectual property (IP) blocks. Further details are provided in Table 1.  
Lattice iCE40 and MachXO2 Families: These FPGAs are tailored for low-power applications. The iCE40 series, known for its use in portable and battery-powered devices, is constructed using 40 nm SRAM technology and includes on-chip non-volatile memory for configuration storage. The iCE40 UltraPlus model is capable of implementing neural networks for pattern recognition, enabling continuous intelligence at the edge. It typically consumes 1-10 mA of active current. It offers three power-saving modes--standby, sleep, and power off--which help extend battery life by allowing the application processor to enter sleep mode. The iCE40-LP family also includes two low-power modes (iCEGate and PLL) to address both static and dynamic power needs, making it suitable for ultra low-power mobile applications like handheld devices. On the other hand, the MachXO2 family is built on 65 nm technology and supports an ultra low-power standby mode. In this mode, various subsystems can be configured to shut down automatically or enter a low-power state to conserve energy.