# An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System
## 5 Experiments and Results
### Experiment Setting  
For the integrity of the experiment, the \"CPU + FPGA\" heterogeneous SAR imaging processing MPSOC system platform consisting of a host computer and two hardware development boards, namely Zynq UltraScale+ MPSoC ZCU106 and Virtex-7 VC709, is utilized. The host computer is responsible for the downlink transmission of SAR raw echo data. AZCU106 includes Zynq UltraScale+ XCZU7 EV-2 FFVC1156 MPSoC, equipped with quad-core ARM Cortex-A53 application processor, dual-core Cortex-R5 real-time processor and a large number of programmable logic resources [40]. The development board is \begin{table}
\begin{tabular}{l l l l} \hline \hline
**Register** & **Register** & **Access** & **Description** \\
**Name** & **Address** & **Type** & **Description** \\ \hline DDR3\_op\_conf\_register & 14\({}^{\text{T}}\)h40 & W & Operation Flow Control Register \\ DDR3A\_state\_register & 14\({}^{\text{T}}\)h44 & R & DDR3A Status Register \\ DDR3B\_state\_register & 14\({}^{\text{T}}\)h48 & R & DDR3B Status Register \\ DDR3\_main\_state\_register & 14\({}^{\text{T}}\)h4C & R & DDR3 Operation Status Flag Register \\ DDR3\_start\_x\_register & 14\({}^{\text{T}}\)h50 & W & x Coordinate Start Configuration Register \\ DDR3\_start\_y\_register & 14\({}^{\text{T}}\)h54 & W & y Coordinate Start Configuration Register \\ Granularity\_Conf\_Register & 14\({}^{\text{T}}\)h58 & W & Data Granularity Configuration Register \\ \hline \hline \end{tabular}
\end{table} 
Table 4: DDR3_TOP module register information table. \begin{table}
\begin{tabular}{l l l l} \hline \hline
**Register** & **Register** & **Access** & **Description** \\
**Name** & **Address** & **Type** & **Description** \\ \hline Dline\_Buf\_op\_conf\_register & 14\({}^{\text{T}}\)h80 & W & Operation Flow Control Register \\ Dline\_BufA\_state\_register & 14\({}^{\text{T}}\)h84 & R & Dline BufA Status Register \\ Dline\_BufB\_state\_register & 14\({}^{\text{T}}\)h88 & R & Dline BufB Status Register \\ Dline\_Buf\_main\_state\_register & 14\({}^{\text{T}}\)h8C & R & Dline Buf Operation Status Flag Register \\ Buffer\_points\_Conf\_Register & 14\({}^{\text{T}}\)h90 & W & Data Buffer Points Configuration Register \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Dline_Buf module register information table. shown in Figure 15, equipped with two SFP Cages for data streaming from heterogeneous platforms and four PL-side Micron MT40A256M16 GE-075E DDR4 SDRAM memories with a total capacity of up to 2 GB. We deployed the superscalar pipeline data storage and exchange engine hardware architecture on the Xilinx Virtex-7 FPGA VC709 development board, which is equipped with Xilinx XC7 VX690T FPGA chip and two Micron MT8 KTF51264 HZ-1G9 DDR3 SDRAM memory modules [41], as shown in the Figure 16. Each DDR3 SDRAM has a storage capacity of 4 GB with storage unit data width of 64 bits. The SAR two-dimensional matrix data granularity is 16,384 \(\times\) 16,384, with a data width of 64 bits, composed of the concatenation of the real and imaginary parts in single-precision floating-point format. The experimental software platform used was Vivado 2020.2 and Vitis HLS 2020.2 version. Vivado 2020.2 is mainly used for the hardware design of ZCU106 and VC709 development boards to build an SoC hardware processing platform. Vitis HLS 2020.2 is  
Figure 16: Physical picture of Xilinx Virtex-7 FPGA VC709 development board. Figure 15: Physical picture of Xilinx Zynq UltraScale+ MPSoC ZCU106 development board. mainly used for software design in addition to the hardware platform, and Vitis can be used to control the development application of ARM application processors in ZCU106. This experimental project is developed and deployed using integrated circuit hardware description language (VHDL). The Zynq UltraScale+ MPSoC core version v3.3 is employed in the ZCU106 development board, along with AXI Chip2 Chip Bridge IP core version v5.0 and Aurora 64B66B IP core version v12.0. Additionally, the MIG IP core version v4.2 and Block RAM IP core version v8.4 are employed in the VC709 development board.