# Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation
## 1 Introduction  
Due to the rapid increase of data volume, the next-generation very high-throughput optical communication has attracted wide interest [1; 2; 3; 4; 5]. It also requires the system to have a quite low bit error rate (BER) to ensure the high reliability of communication, and thus advanced channel codes must be used [6; 7; 8]. Similarly, the very low BER is also required in the next-generation high-density storage systems [9]. The low-density parity-check (LDPC) code is well known to approach Shannon limit when the code length becomes very large [10; 11; 12]. It has the potential to meet the requirement of the high throughput for very high speed communication systems using parallel iterative decoding. However, due to the suboptimal property of the iterative decoding algorithm and the intrinsic error-prone substructures in the LDPC structures, the error floor phenomenon exists when LDPC codes operate in the high signal-to-noise ratio (SNR) region [13; 14; 15]. This phenomenon limits the application of LDPC codes for these high-throughput optical communications [13]. In order to satisfy the very low BER requirements, the approaches for reducing the error floor can be divided into two categories. One is to optimize the structure of LDPC codes or to improve the LDPC decoding algorithm, but the additional complexity brought by these two approaches is higher [16; 17; 18]. The other is to construct concatenated codes or product codes [19; 20; 21; 15]. Constructing concatenated codes requires that the outer code has great error correction capability due to the presence of abundant residual error bits in LDPC codewords, which causes the code rate loss of concatenated codes and further affects the overall performance. The product code has the potential to match the error characteristic of LDPC codes for high throughput and good error correction performance [20]. According to the analysis of the residual error characteristic of LDPC codes, product codes which use the LDPC code as the inner code and use the algebraic code whose code rate is close to 1 as the outer code are designed to achieve extremely low BER in [21]. Therefore, the overall code rate of the product code is very close to the code rate of the inner code. The performance of the product code with various component codes can be further improved using the iterative decoding algorithm [22; 23]. In this paper, an iterative decoding scheme between the inner and outer codes is proposed to further improve the performance of the product code proposed in [21]. The scheme updates the prior probability information of LDPC codes in the following iteration process according to the decoding results of the outer code, reducing the residual errors after LDPC decoding, and further makes the outer code correct the residual errors better. We demonstrate that the performance of the proposed iterative decoding scheme obviously surpasses the performance of decoding scheme without iteration. Furthermore, considering software simulation is limited by time and equipment due to the requirements of longer code length and lower error floor, and the quantization method is an important factor for the performance of iterative decoding [19; 24], the corresponding hardware decoder and the overall evaluation platform of the product code are implemented to further verify the proposed iterative decoding methods. Hardware experiment results show that the designed codec structure achieves a good trade-off between hardware complexity and throughput and thus effectively accelerates the performance evaluation. The implemented iterative codec verifies that the product codes under finite precision implementation can achieve significant performance gain and presents the good trade-off of complexity and performance. The rest of this paper is organized as follows. Section 2 presents a type of product codes and the analysis of the residual error characteristics of LDPC codes. Section 3 details the iterative decoding scheme of LDPC-based product codes and presents the performance verification.