# Low Power QC-LDPC Decoder Based on Token Ring Architecture
## 4 Experimental Results  
The proposed architecture of the QC-LDPC decoder based on Token Ring with a distributed control system and clock gating has been implemented in the Altera (Intel) Cyclone V FPGA devices, for a number of different parity check matrices \(\mathbf{H}\) of QC-LDPC codes. The obtained implementation and power loss testing results are presented in Table 2. The presented results concern decoders with 4-bit data quantization of decoder messages and the Min-Sum computation algorithm. Table 2 contains characterizations of the parity check matrices \(\mathbf{H}\), where \(I\) refers to an irregular matrix and the \(R\) refers to a regular matrix. Two variants were implemented and analyzed for each \(\mathbf{H}\): \"Without Token Ring\", which does not include clock gating and token forwarding, and a \"With Token Ring\" variant, which includes a distributed control system, an architecture based on a Token Ring with token passing and clock gating. It is worth noting a significant reduction of the \(P_{d}\) (dynamic energy consumption) for the architecture based on a Token Ring (on average by 40%), with a simultaneous slight increase in the demand for ALM units (on average by 9%). It is worth noting also that the architecture based on a Token Ring does not increase the demand for memory bits (Mem). Besides the reduction of power in the Token Ring solution, several other observations can be made from the results in Table 2. Since an important decision in the LDPC coding system design is the choice between regular and irregular codes, it is valuable to compare the energy consumption for these two cases. We have observed a clear difference in energy consumption for regular and irregular decoders in the proposed implementation. In Table 3, we emphasize results for two selected matrices, regular and irregular, which are direct counterparts; that is, they have the same size and the overall number of nonzero elements (\(Z=3072\)). In this table, we also include \(L_{c}\)--the number of GCLK ticks needed to perform one complete decoding iteration and \(E_{d}\)--the average dynamic energy per iteration. As can be seen, a QC-LDPC decoder of a regular code requires slightly more clock cycles \(L_{c}\) than an irregular counterpart. This is due to the possibility of faster execution of computations through their parallelization, resulting from a different construction of both matrices \(\mathbf{H}\) in the form of QC: irregular column weights allow for faster computations for a portion of rows or columns. Due to the different values of \(L_{c}\), it is improper to compare the two decoders on the basis of \(P_{d}\); and it is valuable to determine the average dynamic energy \(E_{d}\). Comparing \(E_{d}\) reveals that the decoder based on an irregular matrix is characterized by a much higher energy consumption (more by 168%) compared to the decoder based on the regular matrix. Table 3 also shows an increased hardware demand for ALM units (44% more) in irregular codes decoder. This shows a tradeoff between coding performance (favorable for irregular codes) and energy consumption (favorable for regular codes). We have also determined the power loss in particular decoded elements. The results are shown in Table 4. They allow for a comparison of \(P_{d}\) in regular and irregular decoders. Significant differences can be seen, in particular for the control node computing units, bit node computing units and the clock tree being the power loss of the clock tree designed in the QC-LDPC decoder (for each FPGA device). In relation to the above, it can be concluded that especially regular matrices decoded in a Token Ring architecture can be perceived as an energy-saving QC-LDPC decoding framework. The dynamic power loss \(P_{d}\) and the hardware utilization (ALM and Mem) are also dependent on the size \(P\) of the submatrix. Table 5 presents a comparison of the decoders for the same matrix \(\mathbf{H}\) size but different values of \(P\).