## 1 Introduction  
Nowadays, the advent of applications in technical fields like augmented/virtual-reality, artificial-intelligence, automotive communications, data-centers for cloud-computing triggers a widespread demand for high computational power. Therefore, trends in computation processes are fostering the development of Chip-Multicore-Processors/High-Performance-Computing architectures, where many cores are integrated together to meet the request for the continuous performance growth [1].  
In this framework, chips with up to one thousand cores have been envisaged as expected outcome of this new many-core era [2]. Nevertheless, providing the cores with mutual interconnections poses several challenges related to layout design, communication latency/bandwidth, and power consumption, with increasing complexity as the number of cores grows up [3,4].  
In spite of its simplicity, traditional bus architectures cannot easily scale up to a large number of processing elements due to limitations in bandwidth and latency [1], and are likely to be discarded in favor of Networks-on-Chip (NoC), where wires and routers are embedded on the same chip with cores and cache banks [3,5]. Although NoC scalability is better compared to bus solutions, it is nevertheless still limited, as propagation delays and losses of electrical wires do not scale down at the same rate as transistors [6]. Optical interconnect can improve propagation issues, but on the other end Optical-Network-on-Chip (ONoC) may suffer from additional losses due to imperfect coupling with off-chip laser and/or electro-optical conversion, as well as from extra power-expenditure for the resonance frequency tuning of optical devices like micro-rings [6]. Furthermore, cross-talk risks threaten (O)NoC design, to an extent that becomes harsher as the number of processing elements increases and the network deployment becomes more tangled. 3D integration, where the vertical dimension is also exploited to stack different circuit components, can be a viable solution in some specific situations [7], but fabrication issues limit the implementation of on-chip multi-planar layouts on the mainstream technologies as Silicon Photonics.  
In order to overcome the bottleneck of physical interconnections, Wireless Network on Chip (WiNoC) are being considered an interesting solution [3, 4, 5,8]. Since millimeter-wave antennas undergo obvious problems of on-chip integration, Optical Wireless Networks-on-Chip (OWiNoC) have been recently investigated [9,10], aiming at keeping the main benefits of WiNoC (short latency, simpler network design) but using the antenna integration process. As wireless communications on-chip are expected to complement wired solutions, rather than to replace them [2,11], OWiNoC also benefit from full compatibility with optical, physical networks which may be also deployed on the same chip.  
The design of OWiNoC encompasses several challenging tasks, spanning from optical antenna design and wireless channel modeling to management and mitigation of interference issues, which always rise up as the wireless propagation channel is inherently shared among simultaneous wireless communications. This paper aims at providing a comprehensive insight into these different aspects, with special attention to the impact of noise and interference on bit-error-probability and maximum achievable distances by means of simulations carried out in some reference, study cases. The main topic under investigation is the on-chip wireless optical communication in point-to-point links, and therefore any network optimization feature is simply not taken into account so far.  
The paper is organized as follows: after a survey on previous studies and activities on networks-on-chip provided in Section 2, the main features of on-chip wireless links at optical frequency are outlined in Section 3. Interference issues and performance assessment in OWiNoC are addressed in Section 4, whereas the results of the simulations are discussed in Section 5. Some conclusions are finally drawn in Section 6.