# Research and Implementation of High-Efficiency and Low-Complexity LDPC Coding Algorithm
## 5 Design and Implementation of the Codec
### Decoder Design and Implementation
#### 5.3.1 Decoder Design
During the simulation process, the channel is set as an additive Gaussian white noise channel, and the signal-to-noise ratio is set to 3 dB. The MATLAB simulation waveform is shown in Figures 13 and 14. 2 FPGA Implementation Results  
The correctness and feasibility of the decoder design process were verified through MATLAB simulation implementation. On the basis of software simulation implementation, first, according to the decoder implementation schematic, we performed Verilog HDL  
Figure 14: MATLAB simulation results of codec. Figure 13: MATLAB simulation results of decoder. programming on each module in Vivado2018.2; then, we called each module through the top-level file to complete the hardware design of the decoder; and, finally, through functional simulation and board level testing, the implementation of a decoder that meets the performance requirements of the project was completed. The performance indicators during the decoder testing and verification process were as follows: the input data transmission rate was 2 Mbps and the system clock frequency was 150 MHz (the highest operating frequency of the system is 250 MHz). The functional simulation diagram during the hardware design and implementation process of the LDPC decoder is shown in Figures 15 and 16 and Table 5.  
Figure 16 shows the RTL-level simulation results of the encoder and decoder, and Table 5 shows the resource usage report of the bit encoder and decoder. Figure 16 shows the simulation test results of the decoder. The decoder was designed using the minimum sum decoding algorithm, with 8 decoding iterations and (4,2) uniform quantization method. The system clock frequency clk was 150 MHz--over is the end of decoding processing flag, and a high level indicates the end of decoding processing; \(\text{Cnp}_{\text{-}}\) The on enable signal determines whether the next state is variable node update processing or verification node update processing, \(\text{vnp}_{\text{-}}\)Fnish is the identification signal for the completion of variable node update processing, \(\text{cnp}_{\text{-}}\)Fnish is the completion signal of the verification node update processing, \(\text{last}_{\text{-}}\)Iteration marks the signal for the last iteration, indicating the last iteration cycle, and prompts the variable node processor to output the decoding result after, processing_Num is the number of decoding iterations, and  
Figure 16: Hardware test results of codec. Figure 15: RTL-level simulation results of codec and decoder. the maximum number of iterations for the designed decoder is 8; AP_Rst_N is the system reset signal, with high-level reset; AP_Done outputs the enable signal for the decoding result, and llr_V_TDATA [7:0] is the 1024 bit initialization data input to the decoder. The number of iterations during the decoder design and implementation process is set to 8, and the output is_R_TDATA [7:0] is the 1536 bit decoding data output after decoding is completed. From research on and analysis of the LDPC code verification matrix used, combined with the decoding simulation results of the decoder, it can be seen that the decoder needs to take 5632 clock cycles to complete the decoding process of a frame of data. During the decoding implementation process, each variable node and verification node need to be calculated one by one. The input and output data of the decoder are consistent with the MATLAB simulation results, verifying the correctness and feasibility of the decoder hardware design.