# Research on Clock Synchronization of Data Acquisition Based on NoC
## 2 The General Scenario
### The Principle of White Rabbit  
The traditional White Rabbit clock synchronization protocol is a distributed timing technology that developed from the synchronous Ethernet [18] (Sync-E), precision time protocol (PTP/IEEE1588v2) [19] and digital dual-mixer time difference (DDMTD), which can achieve multi-node sub-nanosecond clock synchronization [20] over a long distance [21; 22]. Sync-E ensures the same clock frequency throughout the system by passing the clock [23]. The clock is embedded in the data and sent to each node by Ethernet, and each child node recovers the clock from the data link and eliminates clock jitter generated in the recovery link through an internal phase-locked loop (PLL). The clock recovered from each child node serves as the system clock of the node and the reference clock of the next child node, and so on. The whole system works at the same clock frequency, so as to achieve the clock synchronization of the whole system. The PTP protocol, based on the principle of delayed response mechanism, adopts the master-slave clock propagation mode and achieves clock synchronization of the whole system through the interaction of clock message information with timestamps. The synchronization accuracy can reach the level of nanoseconds [24]. Moreover, the PTP protocol provides three basic types of time nodes, named the ordinary clock (OC), boundary clock (BC), and transparent clock (TC). The OC and BC can be configured as master or slave clocks, while the TC does not keep synchronization with the other clock nodes. The TC forwards PTP protocol messages of master and slave nodes, and it also calculates and forwards their residence time. Master-slave clock synchronization is implemented through the interactive clock message between master and slave nodes. The synchronization principle is shown in Figure 2.  
According to the synchronization principle in Figure 2, t1, t2, t3, and t4 are obtained from the slave clock node. Then, according to Equations (1) and (2), the clock offset and link delay between the master and slave nodes can be calculated. \[offset=\frac{(t_{2}-t_{1})-(t_{4}-t_{3})}{2} \tag{1}\]  
\[delay=\frac{(t_{2}-t_{1})+(t_{4}-t_{3})}{2} \tag{2}\]  
Figure 1: Data acquisition based on NoC system scheme. (**a**) The data acquisition module. (**b**) Data storage and forwarding module. (**c**) This module is a data transmission block. Since the frequency of \(f_{vco}\) is close to that of \(clk_{a}\) and \(clk_{b}\), the two D flip-flops output the low-frequency signals Q1 and Q2, respectively. The phase difference between Q1 and Q2 is the amplified phase difference of the original signal. Therefore, the phase difference between \(clk_{a}\) and \(clk_{b}\) can be calculated through pulse shaping and counting, as shown in Figure 3.  
Figure 3: The principle of DDMTD. **(a)** Overall diagram. A high-precision clock signal \(f_{vco}\) is generated by the combination of external DAC (digital to analog converter) and VCO (voltage-controlled oscillator), and the frequency of \(f_{vco}\) is close to the detected signal (\(clk_{a}\) and \(clk_{b}\)). **(b)** Interior design diagram. In the chip, \(f_{vco}\) is used as the clock input of the D flip-flop, and clka and clkb are the input signals of the D flip-flop. Figure 2: The principle of PTP. t1, t2, t3, and t4 are the times when the information reaches the corresponding node. ‘Offset’ indicates the clock offset of the primary and secondary nodes. ‘Delay’ is the time spent on a line. As shown in Figure 4, The frequency \(f_{clk}\) of the auxiliary clock \(f_{vco}\) and the measured signals \(clk_{a}\) and \(clk_{b}\) meets the relation of Equation (3), where \(M\) and \(N\) are both positive integers, and the frequency of \(f_{vco}\) depends on the ratio between \(M\) and \(N\)[25; 26]. The frequency \(f_{Q}\) of output signal Q1 (or Q2) from the D flip-flop satisfies Equation (4).