# Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol
## 3 Proposed ECDH Architecture
### Pipeline Registers and Scheduling  
The inclusion of pipeline registers increases clock frequency and reduces the critical path of the proposed ECDH architecture. There are several choices for the inclusion of pipeline registers in the proposed ECDH architecture (given in Figure 3). For example, one pipeline register after \(M_{1}\), \(M_{2}\), \(M_{3}\), \(D_{RA}\), \(M_{4}\), \(MemoryBlock\) and \(M_{5}\) resulting a five-stage pipeline architecture. With this register placement, instruction read is performed in three clock cycles. Two cycles are needed to perform instruction execution and write back operations. As one can see, the instruction read takes three clock cycles which is not an optimal choice. With this observation, we decrease the number of pipeline stages from five to four. The synthesis results show a similar clock frequency as compared to five-stage pipelining. We repeated this process until a two-stage pipelining is reached (It is important to note that the inclusion of more pipeline registers (i.e., from two-stage to three-stage and so on) is no longer beneficial in our architecture. More than two-stage pipelining results in a significant increase in the hardware resources but with a minor increase in the clock frequency). Therefore, in our proposed ECDH architecture (shown in Figure 3), we have included two pipeline registers (only) on the inputs of the ALU (one after \(M_{4}\) and another after \(MemoryBlock\)). It requires reading ([R]) in one clock cycle and both executing and writing back ([EWB]) in another cycle.  
The instructions for \(PAdd\) and \(PDbl\) functions of Algorithm 1 in a two-stage pipelining are shown in Table 1. Column one provides the clock cycles (CCs). The original instructions for \(PAdd\) and \(PDbl\) functions of Algorithm 1 are shown in column two. Columns three to five provide the status of instructions for \(PAdd\) and \(PDbl\) functions in a two-stage pipelining without the proposed scheduling. Finally, the last three columns (six to eight) provide the proposed scheduling for the instructions of \(PAdd\) and \(PDbl\) functions in a two-stage pipelining.  
Table 1 shows that the instructions of \(PAdd\) and \(PDbl\) functions of Algorithm 1 requires 22 CCs. Moreover, in two-stage pipelining, there are read-after-write (RAW) hazards when executing these instructions. It implies that the execution of the current instruction is stopped until the write-back of the previous instruction is finished. For example, in the first clock cycle, operands of \(PAdd_{Inst_{1}}\) are fetched from the memory unit. In the next cycle, operands for \(PAdd_{Inst_{2}}\) are fetched while the execution and write-back of \(PAdd_{Inst_{1}}\) are completed. In clock cycle three, \(PAdd_{Inst_{3}}\) can not be fetched because it depends on the result of previous instruction (\(PAdd_{Inst_{2}}\)). This is termed the RAW hazard. In total, seven RAW hazards (shown in column five of Table 1) are occurred when the instructions of \(PAdd\) and \(PDbl\) functions are executed sequentially.  
To reduce the RAW hazards or to reduce the total number of clock cycles, an efficient scheduling technique is presented for the instructions of _PAdd_ and _PDbl_ functions. The proposed scheduling is shown in the last three columns of Table 1. We can observe in column six that the operands for \(PDbl_{Inst_{1}}\) are fetched from the memory unit in clock cycle three. It allows reducing the clock cycles (total 17) for the execution of one _PAdd_ and \(PDbl\) operation. To summarize, the instructions for _PAdd_ and \(PDbl\) functions of Algorithm 1 require \(22\times m\) clock cycles in a two-stage pipelining when no scheduling is considered for executions. Here, \(m\) is the key length (233 in this work). However, with the proposed scheduling, the required number of clock cycles for the execution of one _PAdd_ and \(PDbl\) functions are \(17\times m\). Therefore, the proposed scheduling scheme reduces \(5\times m\) clock cycles.