## 2 Buck Converter Modeling
In a similar fashion, \(K2C\) and \(K2L\) are multiplied by \(1/2\) and fed to the next cycle for calculation of \(K3C\) and \(K3L\) and multiplied by \(2\) and summed to the existing value of \(\Delta v_{C}\) and \(\Delta i_{L}\), respectively. The next cycle delivers \(K3C\) and \(K3L\) values, which are also accumulated in \(\Delta v_{C}\) and \(\Delta i_{L}\) after multiplication by \(2\) and used directly as input for the last cycle, which delivers \(K4C\) and \(K4L\). These are added to the existing value of \(\Delta v_{C}\) and \(\Delta i_{L}\), and then multiplication by \(1/6\) is performed. This yields the definitive value for \(\Delta v_{C}\) and \(\Delta i_{L}\) and is then used for calculating the following value of \(v_{C}\) and \(i_{L}\). Figure 8 shows the structure of these calculations. Figure 8: Pipelined fourth-order Runge–Kutta calculation using the generic K-calculator. The outputs of each cycle multiplied by the necessary factors are used as inputs for the next cycle for calculating the following \(KnC\) and \(KnL\) values and used for accumulating into \(\Delta vC\) and \(\Delta iL\). The inputs on the left are identical during the four cycles. ### Synthesis Results

The fixed-point pipelined implementation in VHDL code was synthesized for the XC7A35 TCSG324-2 device, part of the Xilinx Artix-7 family of FPGAs, using Xilinx Vivado HLx edition 2018.3. This device has 5200 configurable logic blocks with four Look-Up Tables (LUTs) and eight flip-flops each (which gives a total of 20,800 LUTs and 41,600 flip-flops), as well as 90 Digital Signal Processor (DSP) slices, and Block RAM Blocks that provide a total of 1800 kb. The resource utilization of Algorithm 4 lies within the device limits: 16.8% of the LUTs, 2.8% of Flip-Flops, and 66.7% of DSPs are used. Table 6 summarizes this. A clock period of down to 40 ns can be achieved according to the synthesis tool. Therefore, real-time calculation can be performed in 25 cycles, as mentioned above, which gives a time step of 1 \(\upmu\)s. This is the minimum achievable dt with the proposed architecture based on fourth-order Runge-Kutta method, K-calculator blocks, semistep calculation during deadtimes, and the selected device. In the literature, some references can be found that reach smaller simulation steps for simple converters--such as boost and buck topologies--by using simpler methods like Euler [15; 27]. However, this paper uses fourth-order Runge-Kutta which leads to a much more accurate model, as the order of the solver is \(\mathcal{O}(dt^{4})\), and fixes the detected issue not only for simple buck converters but to other topologies that are based on half-bridge modules. In addition, the high accuracy makes the method suitable for integrating an FPGA-based model in a commercial HIL system. These systems typically have integration times on the order of 1 \(\upmu\)s. A Euler-based method with such integration time would be unsuitable due to the larger inherent error. In order to allow the circuit designer to perform a trade-off between accuracy and speed, the initial Algorithm 2 was also implemented and synthesized. The starting point was the same pipelined architecture where the cycles for substep calculations were removed. This architecture performs these actions:

1. Fetch status of \(S1\) and \(S2\), initialize values. 2. Successively calculate \(K1C\) and \(K1L\) to \(K4C\) and \(K4L\) and accumulate the state variable increments \(\Delta i_{L}\) and \(\Delta v_{C}\) at each step. 3. Set \(i_{L}\) to zero if the new \(i_{L}\) value creates a zero-crossing during the deadtime. 4. Assign the new value of state variables. Resource utilization is expected to be lower, since no division is needed and the fourth-order Runge-Kutta calculation is performed only once, whereas it was performed three times with Algorithm 4. This also implies that fewer cycles will be necessary. Instead of 25 cycles, only 7 cycles are necessary to perform one calculation. Table 7 shows the resources needed for implementing Algorithm 2 in the same device.