# A Forwarding Latency Optimization Method for Software Data Plane Based on Spin-Polling
## 4 Model Analysis
In this case, we have \(m=N\), and we reasonably assume that \(\sum_{i=1}^{m}B_{i}\ll\theta_{Tx}\), which means that we can ignore the time it takes for the data plane to process these few packets. Figure 7 is a schematic diagram of packet arrivals and data plane behavior when the packet arrival rate is very low. The packets are mainly forwarded under the timeout flush mode. We use another timeline to describe the behavior of the data plane. The green arrow indicates that the data plane checks one Rx queue, and the red arrow indicates that the data plane sends packets. The residence time of \(b_{ij}\) follows the formula:  
\[RT_{ij}\leq N\tau,\text{ when }m=N,\sum_{i=1}^{m}B_{i}\ll\theta_{Tx} \tag{3}\]  
Therefore, when the packet arrival rate is very low, the upper limit of the average latency of packets is also \(N\tau\). The increase in the packet arrival rate will change the packet forwarding mode of the data plane from the timeout refresh mode to the regular burst mode. We note that, in the experiments in Section 3.2, when the packet arrival rate is in the [1, 8] Gbps interval, the average packet latency decreases with the increase of the packet arrival rate. This seems somewhat counter-intuitive. The experimental result is related to the packet generation of our packet generator. We know that reducing the interval of packet batches and increasing the size of packet batches both can increase the packet arrival rate, and our packet generator obviously chose the former. When the number of packet batches in \(N\) rounds of polling increases, but the number of packets is still relatively small, the average latency may decrease slightly. The experimental results reflect the characteristics of the packet generator and have little guiding value for the actual scene. The increase in the packet arrival rate will significantly increase the number of packets received by the CPU in one poll, thereby increasing the time required for the CPU to process packets. The effect of the significant increase in CPU processing time for packets is twofold. The first is that the time for the CPU to check the next Rx queue is significantly delayed, which directly increases the queuing time of incoming packets in the Rx queues. If the Rx queue length reaches the upper limit, packet loss will occur. Second, the earlier packets arrive, the longer they need to wait in the Tx queues. We use Figure 8 to illustrate the characteristics of regular burst mode. \(B_{1}\) is the number of packets received by the data plane at the moment \(t_{1}\), and \(B_{2}\) is the number of packets received by the data plane at the moment \(t_{2}\). \(T_{1}\) is the time taken by the CPU to process \(B_{1}\) packets, and \(T_{2}\) is the time taken by the CPU to process \(B_{2}\) packets and send \(B_{1}+B_{2}\) packets (In fact, in order to achieve higher throughput, the data plane will only send \(\theta_{Tx}\) packets, and the remaining packets will wait in the Tx queues). If \(T_{1}\) becomes larger, \(B_{2}\) will likely become larger, and the waiting time for \(B_{2}\)'s packets will also be longer. On the other hand, when the data plane  
Figure 7: Schematic diagram of data plane behavior under low packet arrival rate. receives \(B_{2}\) at time \(t_{2}\), \(B_{1}\)'s packets are already in the Tx queue, and they need to wait for \(T_{2}\) before being sent, while \(B_{2}\)'s packets do not need to be queued in the Tx queue. In Figure 8, the sum of the number of packets polled twice by the CPU exceeds \(\theta_{Tx}\), which is a situation where the packet arrival rate is relatively high. We try to discuss the more general case. According to Formula (2), the residence time of \(b_{ij}\) in regular burst mode can be represented by the following formula:  
\[ \begin{split} RT_{i\bar{j}}&=QR_{i\bar{j}}+P_{i}+ QT_{i}\\ &=QR_{i\bar{j}}+P_{i}+\sum_{k=i+1}^{m}P_{k}\\ &=QR_{i\bar{j}}+\sum_{k=i}^{m}P_{k}\end{split}