## 2 Existing Works  
The fundamental principle of PUF based on ring oscillators has been know since 2002 [14], and since then, it has been implemented by differentiating each device's specific characteristics based on its unique frequency. Since then, many researchers have developed the concept of RO-PUF. [PERSON] et al. proposed the first aging-resistant RO-PUF design, which they referred to as ARO-PUF. Over time, the PUF proved to produce more reliable output [15]. Next, an improvement of RO-PUF's uniqueness and reliability parameters by manipulating the structure of ROs was developed. The authors provided an algorithm that can dismiss the systematic variation effect on RO-PUF and, in turn, enhances the security and reliability of the RO-PUF [12]. The low power RO-PUF using dynamic style feedthrough logic (FTL) to enhance reliability was carried out in 90 nm CMOS technology in 2020 [16].  
Other research projects into RO-PUF include a novel current-controlled CRO PUF (CCRO-PUF) in which inverters of RO use different logic styles for security improvement. The idea is to use static CMOS and FTL. Simulations were carried out in the Cadence Virtuoso environment using SPECTRE SPICE using a library from UMC foundry of CMOS 90 nm process [17]. Subsequently, a crossover RO PUF to improve flexibility and reliability and reduce hardware overheads was also published. The basic idea was to implement one-to-one input-output mapping with a lookup table (LUT)-based interstage crossing structure in each level of inverters [18]. [PERSON] et al. proposed the frequency signature-based PUF (FS-PUF), an essential mechanism for authentication and identification of digital devices based on ROs immunized to working conditions and aging [19].  
However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. Firstly, most proposed RO-PUF requires a massive area where the number of RO placed on a chip is considerable. An additional area is required to realize the challenge-response pairs' (CRP) generation and other controlling circuits [20; 21; 22]. Secondly, there exist unstable ROs in the FPGA [14; 15; 17; 18], leading to degraded reliability. Thirdly, the routes created by the Electronic Design Automation (EDA) might cause an imbalance in routing density in some locations. [PERSON] et al. discussed the routing issue that affects the RO performance, specifically reducing uniqueness [23]. The issue was later discussed further by [PERSON] al. by showing that the RO signal frequency is reduced due to interference by other signals [24; 25].  
Therefore, it is required that an RO-PUF be realized with a lesser area, which will result in good randomness and resistance upon environmental variation. This work proposes a modified RO-PUF design that connects ROs to counters directly. The proposed design can generate more response bits than the previous designs while using a smaller on-chip area. Typically, in most RO-PUF designs, the actual frequency of each RO differs because of physical variation. However, in nanoscale technology, diversity is becoming less and challenging to detect. Moreover, the routing delay is dominant compared to the logic delay itself. Therefore, upon realizing the FPGA chip, the vast difference in routing density in every RO would affect the performance. This work aims to find the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements in forming RO are tested to extract frequency differences over various routing densities. Then, the scenarios that narrow range routing density are designed, and ROs with a close value of routing density will be considered. Additionally, this work estimates the minimum runtimes of RO to avoid error and bit-flip.