# A Low-Complexity Start-Stop True Random Number Generator for FPGAs
## 3 The Quality of Bit Streams Produced by the Proposed Generator
\begin{table}
\begin{tabular}{l c c c c c c c} \hline \hline \multirow{2}{*}{**Test**} & \multicolumn{4}{c}{**Raw Data**} & \multicolumn{4}{c}{**Raw Data + SHA1**} \\ \cline{2-9}  & \multicolumn{2}{c}{**WT7**} & \multicolumn{2}{c}{**WT2D**} & \multicolumn{2}{c}{**WT7**} & \multicolumn{2}{c}{**WT2D**} \\ \cline{2-9}  & \(R_{\beta}\) & \(P_{T}\) & \(R_{\beta}\) & \(P_{T}\) & \(R_{\beta}\) & \(P_{T}\) & \(R_{\beta}\) & \(P_{T}\) \\ \hline
1. Frequency & **0.958** & **0.000** & **0.918** & **0.000** & 0.986 & 0.196 & 0.987 & 0.745 \\
2. Block frequency & **0.428** & **0.000** & **0.910** & **0.000** & 0.989 & 0.169 & 0.989 & 0.326 \\
3. Cumulative sums & **0.949** & **0.000** & 0.991 & 0.534 & 0.987 & 0.081 & 0.991 & 0.721 \\
4. Runs & 0.993 & 0.435 & 0.980 & 0.114 & 0.992 & 0.426 & 0.989 & 0.982 \\
5. Longest run & **0.000** & **0.000** & 0.910 & 0.000 & 0.990 & 0.998 & 0.983 & 0.872 \\
6. Rank & 0.990 & 0.175 & 0.986 & 0.094 & 0.992 & 0.890 & 0.989 & 0.739 \\
7. DFT & 0.995 & 0.771 & **0.974** & 0.007 & 0.990 & 0.249 & 0.991 & 0.494 \\
8. Non overlapping template & **0.000** & **0.000** & **0.037** & **0.000** & 0.987 & 0.699 & 0.992 & 0.133 \\
9. Overlapping template & 0.983 & 0.046 & **0.004** & **0.000** & 0.988 & 0.473 & 0.993 & 0.220 \\
10. Universal & **0.000** & **0.000** & **0.808** & **0.000** & 0.991 & 0.152 & 0.991 & 0.173 \\
11. Approximate entropy & **0.000** & **0.000** & 0.991 & 0.004 & 0.989 & 0.684 & 0.991 & 0.957 \\
12. Random excursions & **0.938** & **0.000** & **0.955** & **0.000** & 0.988 & 0.188 & 0.986 & 0.012 \\
13. Random excursions variants & **0.961** & **0.000** & 0.998 & 0.012 & 0.993 & 0.000 & 0.996 & 0.077 \\
14. Serial & **0.000** & **0.000** & **0.007** & **0.000** & 0.992 & 0.465 & 0.992 & 0.159 \\
15. Linear complexity & 0.990 & 0.028 & 0.998 & 0.167 & 0.989 & 0.697 & 0.990 & 0.420 \\ \hline \hline \end{tabular} The worst cases were shown. Bold denotes the results that do not pass the test.  
\end{table} 
Table 6: The values of proportion \(R_{\beta}\) and the values of \(P_{T}\) for raw data and after their processing for WT2D and WT7,\(f_{L}\) = 10 MHz. \begin{table}
\begin{tabular}{l c c c c c c c} \hline \hline \multirow{2}{*}{**Test**} & \multicolumn{4}{c}{**Raw Data**} & \multicolumn{4}{c}{**Raw Data + SHA1**} \\ \cline{2-9}  & **WT2** & **WT3** & **WT4** & **WT2D** & **WT2** & **WT3** & **WT4** & **WT2D** \\ \hline
1. Frequency & — & — & — & Y & Y & Y & Y \\
2. Block frequency & — & — & — & — & Y & Y & Y & Y \\
3. Cumulative sums & — & — & — & Y & Y & Y & Y \\
4. Runs & — & — & — & — & — & Y & Y \\
5. Longest run & — & — & — & — & Y & Y & Y \\
6. Rank & — & Y & Y & Y & — & Y & Y \\
7. DFT & — & — & — & — & Y & Y & Y \\
8. Nonoverlapping template & — & — & — & — & — & — & Y \\
9. Overlapping template & — & — & — & Y & Y & — & Y \\
10. Universal & — & — & — & — & Y & Y & Y \\
11. Approximate entropy & Y & — & — & Y & Y & Y & Y \\
12. Random excursions & — & — & — & Y & Y & Y & Y \\
13. Random excursions variants & — & — & — & — & — & — & Y \\
14. Serial & — & — & — & — & Y & Y & Y \\
15. Linear complexity & Y & Y & Y & Y & Y & Y & Y \\ \hline \hline \end{tabular}
\end{table} 
Table 5: The final results of statistical tests described in SP 800-22,\(f_{L}\) = 1 MHz. 3. The authors declare that the generator produces sequences that pass the randomness tests described in NIST 800-22, so that the proportion of \(R_{\beta}\) of strings that pass the test is within the limits set by NIST for all tests and subtests, and so that the distribution of \(p\)-values is uniform. IV. The authors have specified the FPGA resources for the proposed TRNG. The criteria selection reflects users' current expectations regarding the methodology and quality of random number sequence generation for cryptographic purposes. The first criterion enhances security by eliminating the necessity to transmit random sequences to the FPGA from an external circuit, which could be more susceptible than the FPGA itself.