# High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip
## 1 Introduction  
A digital-to-time converter (DTC) is similar to a digital-to-analog converter (DAC), except that DTC converts digital values to time interval signals. DTCs are widely used in atomic frequency standards, high-precision positioning [1, 2], time-correlated single-photon counting instruments (TCSPC), and measurement instruments [3, 4, 5, 6] such as the very large scale integration (VLSI) functional tester [7].  
The counting method is a widely used DTC method, which is realized by counting periods of a reference clock. The counting method is simple in implementation and large in dynamic range. However, its resolution is limited to several nanoseconds, which is determined by the frequency of the reference clock. Taking advantage of the technique of the Application Specific Integrated Circuit (ASIC), DTCs implemented in ASIC devices (ASIC-based DTCs) have been proposed [1, 2, 3, 4, 7]. The best resolution of the ASIC-based DTC is better than 1 ps [3], which is realized by combining the ASIC technique and the capacitor charging principle. However, these DTCs are sensitive to variations in temperature and voltage owing to the use of analog devices. Moreover, DTCs implemented in ASIC devices is high in cost and long in time to market.  
With the development of commercial integrated circuits, DTCs implemented in FPGA (field programmable gate array) devices (FPGA-based DTCs) have attracted an increasing amount of research interest in recent years. Compared with ASIC-based DTCs, FPGA-based DTCs have the advantage of a low cost and a short time to market. Many DTCs implemented in the FPGA are realized by phase shifting [6, 8, 9], and the obtained resolution is about 8 ps. FPGA-based DTCs are mostly based on a Vernier delay line, a tapped delay line [10], and a Vernier ring oscillator [5]. A DTC with a resolution of 11 ps was implemented in a Xilinx Kintex-7 FPGA device based on a tapped delay line [10]. A DTC based on a Vernier ring oscillator and the Altera Stratix-III FPGA device was proposed [5], whose theoretical resolution was 1.58 ps.  
DTCs with high resolution are mainly implemented in ASIC devices, which have the advantages of fully customized circuits and reasonably precise control of the internal propagation delay. However, it is difficult for FPGA-based DTCs to obtain high resolutions due to the additional delay introduced by the unpredictability of the routing strategy. Therefore, FPGA-based DTCs with a 1 ps resolution are very valuable for practical applications, but also very challenging for research.  
In this paper, a novel realization of a DTC based on an FPGA device is proposed and tested. The obtained resolution is 1.02 ps, and the dynamic range is 590 ns. The proposed DTC benefits much from the coarse and fine Vernier delay line constructed by PDLs, which ensures a high performance delay. Meantime, the control module of PDL (programmable delay line) adopts a programmable close-loop feedback mechanism to adjust the tap delay of the delay lines, which improves the nonlinearity and stability of the DTC. Compared with the normal DTCs implemented in FPGA/ASIC devices, the proposed DTC achieves a higher resolution and improved nonlinearity and stability.  
The remainder of the paper is organized as follows. Section 2 describes the principle and structure of the proposed DTC. Section 3 presents the realization of the DTC system. Section 4 shows the experimental results, and Section 5 summarizes the paper.