2.78 \(\upmu\)W. Moreover, the proposed ASIC achieved an outstanding capability of predicting the arrhythmia up to 3 h before the onset. [PERSON] et al. [22] presented a complete beat-to-beat arrhythmia classification SOC (system-on-chip) implemented on a custom ultra-low-power microcontroller. It includes a single-channel AFE (analog front-end) circuit for ECG signal acquisition and a digital back-end processor to execute the support vector machine classification software with a Cortex-M4 CPU. The classification software reaches a sensitivity of 82.6% and 88.9% for supraventricular and ventricular arrhythmias, respectively, on the MIT-BIH arrhythmia database. The SOC occupies a die area of 3.1 mm\({}^{2}\) and consumes 13.1 \(\upmu\)W on average from a 1.8-V supply. While these algorithms exhibit remarkable accuracy in arrhythmia detection, their implementation frequently demands substantial computational resources and hardware infrastructure. Furthermore, given the reliance of biomedical wearable and implantable devices on batteries with restricted energy capacity [23], the meticulous design of dedicated hardware architectures, incorporating ultra-low-power VLSI (very large scale integration) techniques, becomes essential for processing biomedical algorithm kernels at the edge. In general, those ECG processors consist of three main stages: R-peak detection, feature extraction, and classification [24]. Feature extraction plays a vital role in ECG signal classification, as it reduces the signal's dimensionality and extracts the most relevant information for classification. One widely used method for feature extraction is the discrete wavelet transform (DWT) [25]. DWT is particularly suitable for ECG feature extraction because it is robust against noise and can extract various features from ECG signals, including time-domain, frequency-domain, and morphological features. To keep computational complexity low, many researchers [26; 27; 28] have chosen the Haar wavelet, the simplest wavelet function, for use in low-power embedded systems. Conventional classification systems typically employ an \"always-on\" architecture, consuming significant time and energy by processing unimportant events. Especially for ECG arrhythmia detection, difficult-to-classify samples are much rarer than easy-to-classify ones [29]. Spending significant time and energy on easy-to-classify samples in long-term monitoring scenarios is particularly problematic for ECG processors. Consequently, recent studies have focused on the development of hybrid multi-stage wake-up architectures [30; 31; 32]. These systems feature:  
1. Pre-classification circuits are specifically designed to efficiently discern and handle readily classifiable samples. 2. A high-performance classifier that performs computationally intensive tasks for precise classification of challenging samples is activated by pre-classification circuits when encountering ambiguous samples beyond their discrimination threshold. This paper presents an energy-efficient ECG processor for arrhythmia detection, which primarily comprises three modules: the ECG R-peak detection engine, the feature extraction engine, and the hybrid ECG classifier. The Hilbert transform-based R-peak detection engine is responsible for R-peak detection and R-R interval calculation. The Haar DWT unit is responsible for feature extraction. The hybrid ECG classifier architecture, comprising a linear pre-classifier (LPC) and a non-linear support vector machine (NLSVM) classifier, is employed to achieve a great power reduction with negligible detection performance loss. Our work primarily focuses on the hardware implementation of the algorithms in an area-energy-efficient manner, with the premise of sacrificing acceptable performance. Our contributions presented in this paper are as follows:  
1. An R-peak detection algorithm based on the Hilbert transform with some adjustments to make it more suitable for hardware implementation;
2.