## 2 Device Fabrication  
For the device explained in this study, based on the combination of SOI and FinFET technologies, the SOI FinFET devices are produced based on other existing bulk silicon devices. Thus, one novel device structure is shown in Figure 1.  
Figure 1: Device diagram.  
This structure shown in Figure 2 is basically an SOI FinFET device with three independent gates, composed of gate1 on one side of the channel side wall, gate2 on the top of the middle of the fin channel, and gate3 on the other side of the channel side wall. Gate1 and gate3 have similar structures. Generally, the three gates are isolated from each other by an isolation dielectric layer. The FinFET device has multiple independent gate structures. In terms of the process, the SOI substrate should first be prepared, followed by the main structure (FinFET), by following the general process. Subsequently, the dielectric inter-gate isolation layer is gradually adopted in the subsequent processes to form three independent gates.  
The specific steps are shown in Figure 3. As can be seen, this structure can reduce the process loss and complexity. The basic dimensions are listed: H\({}_{\text{fin}}\) = 30 nm, W\({}_{\text{fin}}\) = 10 nm, Lg = 12 nm. By directly introducing the relevant inter-gate isolation process steps in the gate oxide layer stage, the self-aligned isolation can be effectively completed, possible interference between different adjacent steps can be avoided, the isolation quality can be guaranteed, and the process can be completed in one composition. Moreover, the device composition process is based on the existing process, avoiding complexity and reducing the process cost. Thus, it is more suitable for the current mainstream FinFET process. As shown in Figure 3:  
1. The SOI substrate is first prepared as the basis for the next steps;
2. The p-well is formed by doping p-type impurities, and boron is used for the p-type impurities here. In this step, the process is similar to the conventional process;
3. The fin structure is fabricated using repeated photolithography and step-wise etching;
4. Subsequently, the gate oxide layer deposition stage follows. Following the deposition of the relevant gate oxide, the chemical mechanical polishing step is used to flatten the surface and facilitate the development of the subsequent steps;
5. The relevant masking layer is deposited to prepare for the next photolithography etching step. Photoresists are used as the masking layer in the process;
6. The gate oxide layer at the specified scale is formed through another photolithography and etching;
7. The implantation masking layer is deposited again to pre-treat the subsequent source-drain doping;  
Figure 2: Device structure diagram.  
* The ion implantation doping stage dopes the n-type impurities, and phosphorus is used for the n-type impurities. Consequently, the impurity ion implantation at the source-drain end is completed;
* Thus, the structure of the total gate is constructed and the preliminary structure of the gate is completed through the relevant deposition and photolithography steps;
* Next, the masking layer of the photoresist deposition step is performed again to prepare for the subsequent lithography and etching;
* Photolithography and etching are again performed to construct a self-aligned position hole for the subsequent gate isolation dielectric layer;
* The deposition of the relevant isolation dielectric finally forms the multi-gate isolation structure with an independent gate;
* The electrode contact of the back channel is formed.  
Through the aforementioned detailed introduction of the construction process, the construction of the target device in this study is completed based on the mainstream process, which can reflect the universal and effective application of the process, simplify the relevant steps, and facilitate the implementation for large-scale industrialization and rapid production and application.