# WRTU-16T: Write-Enhanced Low-Power Radiation-Tolerant SRAM for Space Applications
## 1 Introduction  
The advancement of integrated circuit technology has dramatically improved the performance of satellite communication systems, and as a result, its application scope is expanding in the space industry. Static random access memory (SRAM) is used as a core memory, from small satellites to large-scale satellite networks, due to its advantage of a high operation speed [1]. However, in space, high-energy particles continuously collide with memory cells, posing a great threat to the reliability of SRAM. Radiation-induced errors such as SEU (Single-Event Upset) or SEMNU (Single-Event Multiple Node Upset) can corrupt stored data or cause system malfunction. As the physical size of sensitive nodes decreases due to the continuous miniaturization of CMOS processes, SRAM is becoming more vulnerable to SEU. Previously, methods such as TMR (Triple Modular Redundancy) or ECC (Error Correction Code) were used to alleviate these problems. However, these methods have the disadvantage of significantly increasing the area or power consumption or increasing the circuit delay, making them unsuitable for systems with limited cost or power budget. Therefore, the demand for more efficient and reliable radiation-hardened SRAM structures suitable for space environments is increasing. The We-Quatro [2] cell has two pairs of NMOS access transistors that connect directly to two storage nodes and two inner nodes. These features provide low Write Access Time (WAT) and Read Access Time (RAT) for fast operation. The primary issue with this design is the high Hold Power (HPWR) because of its short NMOS paths. The RRHS-14T [3] radiation-hardened cell has four NMOS access transistors and is designed with an optimized cell ratio (CR) of 2:1 for writing ability. The design's best feature is its highest WAT and Word Line Write Trip Voltage (WWTV) while exhibiting the lowest critical charge (Qc) among comparison cells. And also, the lack of internal feedback paths fails to restore data in radiation environments. The RHSCC-16T [4] is unique in that it has two storage nodes and four inner nodes. When one of the six nodes is affected by SEU or SEMNU, it can be restored to the correct logic value through the feedback loop structure of the unaffected node. The use of feedback RHSCC-16T achieves high Qc. As a trade-off, those complex structures cause additional circuit latency, leading to high WAT and RAT. A 16T radiation-hardened SRAM with eight NMOSs and eight PMOSs, SUR-16T [5], incorporates two PMOS access transistors influencing transistor stacking to reduce the HPWR. However, this cell operates with excessive delays with high WAT and RAT, as well as a small Read Static Noise Margin (RSNM) because of PMOS access devices. The structure of S8P8N-16T [6] has four access transistors, two PMOSs connecting inner nodes, and two NMOSs related to storage nodes. S8P8N-16T has a low HPWR by using relatively more PMOSs than other cells for the stacking effect. Additionally, inner nodes are surrounded by NMOS, and storage nodes are surrounded by PMOSs for low WAT and high WWTV. However, one pair of PMOSs creates the parasitic capacitance reason for low RSNM. Although several radiation-hardened SRAM cells have been proposed recently, many of them are effective only under certain conditions or do not properly balance read stability, write latency, and power consumption. Some cells are robust to single-node errors, but are still vulnerable to multi-node inversions or have excessively high leakage power. In this paper, we propose a radiation-hardened SRAM cell, WRTU-16T, to overcome these limitations. This structure combines a'read separation' structure that separates read operations from storage nodes and a 'charge-sharing suppression' technique that suppresses the phenomenon of charges being distributed across multiple nodes. This isolates the storage nodes from the direct effects of radiation, reduces the possibility of SEMNU occurrence, and enables the structure to recover quickly even when SEU occurs.