# A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits
## 9 Diagnosis of SDD and HDD  
Diagnosis is the process of narrowing down the probable sites of defects in a logic circuit that fails a test [73]. The failure information obtained from the delay test can be used to find the defect location that causes the delay. The principal aim of a diagnostic algorithm is to improve its diagnostic resolution, i.e., to identify the possible defect location that causes the failure, with high accuracy. If the defect locations identified by the diagnostic algorithm contain more candidates, it takes a long time to locate the exact delay defect location under the microscope in the industry. This affects the time to market demand. Hence, a diagnostic algorithm with better resolution is required to detect the delay defect location and the  
Figure 10: ATPG generation flow through CA test for small delay faults.  
bounds of the delay defect size. Initially, the diagnosis is performed without any timing information. The need for SDD and HDD diagnosis increases as the technology node shrinks, hence the timing information of the circuits is necessary to improve diagnosis accuracy and reduce the number of fault candidates.  
The use of timing information in the diagnosis yields a better resolution than those with non-timing aware diagnosis [74; 75; 76]. The SDD diagnosis [75] is performed by using timed seven valued simulations and injecting delay size of minimum detectable delay value found from the statistical delay quality model (SDQM) [16]. But the delay distribution for the particular technology node is not always available. Moreover, since the STA is used for diagnosis guidance, the results obtained will not correlate accurately with the real chips because of the process variations.  
Generating patterns for improving the diagnostic resolution is another method for enhancing the SDD diagnosis [77]. This method will generate additional patterns to target each candidate separately and observe the output response. But at the production site, it is difficult to implement such pattern generation, especially for large industrial circuits.  
The next major problem is the test response compaction, which is done to reduce the storage in the tester's memory [78]. The diagnosis of compacted response is a challenging task, especially for SDD and HDD. A six-valued fault-free simulation is compared with the faulty compressed signature to backtrace through the circuit to find the SDD candidate list [79]. From the generated SDD candidate list, a fault of a particular size is injected and timing simulated to obtain the response. The response is then compared with the failed response from the failure log information. The fault that provides the most comparable result is finalized as the defect location. A Graphical Processing Unit (GPU) accelerated timing simulator is used for timing simulation to cope with the long run time [80]. But the major problem is that the inject and validate timing simulation is done for the nominal delay values. This may not match the real defects that occur in chips because of the process variation. The variation aware method addresses this issue to predict the SDD candidate that fails the test accurately [80]. But if the pattern used has a low diagnostic resolution, it affects the diagnosis performance. In [81], the first diagnosis of HDDs is reported. It is done similarly to that of [79]. But the uncompressed response is used for diagnosis rather than the compressed response, as in [79]. Since FAST is used for HDD detection, the diagnosis is performed at different capture times. The diagnosis of SDDs and HDDs has only become a field of research in the past decade. It can be eye-opening to researchers looking to improve the diagnostic resolution further.