## 2 Feasible Design Space for ET Operation
### PA Implementation and Test  
To verify optimum fundamental load impedance proposed above, the load-pull simulation was carried out, and the PA circuit was fabricated. In the simulation, the optimum fundamental load impedance is determined by analyzing output power and PAE contours at different drain supply. Figure 5 shows that there is a feasible solution space to provide high PAE (79.5%) and proper output power at both 15 V and 30 V drain bias, which is of benefit to ET operation. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & & & & & & \\ \cline{2-6}
**PA Mode** & \(\mathbf{V_{ds}}\) & \(\mathbf{Z_{1\_Igen}}\) & \(\mathbf{Z_{1\_pkg}}\) & **Ideal \(\mathbf{\eta}\)** & \(\mathbf{L_{min}}\) \\ \hline Class-B & 15 V & 36 & 15.8 + 9.3j & 78.5\% & 0.35 \\ Class-B & 20 V & 36 & 20.0 + 9.7j & 78.5\% & 0.35 \\ Class-B & 30 V & 36 & 24.5 + 9.1j & 78.5\% & 0.35 \\ Class-B/J & 15 V & 36 \(-\) 8.2j & 19.7 + 10.7j & 78.5\% & 0.04 \\ Class-B/J & 20 V & 36 + 0.7j & 19.6 + 9.7j & 78.5\% & 0.04 \\ Class-B/J & 30 V & 36 + 8.3j & 19.7 + 10.7j & 78.5\% & 0.04 \\ Hybrid continuous modes (HCM) & 15 V & 41.6 \(-\) 4.9j & 16.9 + 12.3j & 89.9\% & 0 \\ HCM & 20 V & 41.2 + 6.5j & 16.9 + 12.3j & 89.5\% & 0 \\ HCM & 30 V & 36.6 + 14.4j & 16.9 + 12.3j & 79.7\% & 0 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Calculated results of power amplifier (PA) design parameters. Figure 4: Normalized drain voltage and current waveforms of HCM PAs. The calculated \(Z_{1\_pkg}\) in Section 2.3 is also presented in Figure 5, as a comparison with the simulated results, which proves the validity of the proposed design strategy in this work. Additionally, the harmonic load impedance in this work is chosen to the edge of the Smith chart with the constraints of high efficiency and high power regions, and optimum fundamental source impedance is picked out with resorting to source pull simulation. The input and output matching network schematic of the proposed PA circuit is shown in Figure 6a. The input fundamental matching network, considering the stability by adding a serial resistor-capacitor and parallel resistor, is matched to optimum fundamental source impedance. For the purpose of designing a broadband matching network conveniently, conventional multiple sections of transmission line topology are used in the input matching circuit. In addition, the optimum load impedance \(Z_{1\_pkg}\) at fundamental frequency can be matched by using the output matching network. To optimize efficiency and output power of the proposed PA, the second harmonic control circuit, which is constituted of the quarter wave transmission line S2 and matching transmission line T8, is adopted to restrict the second harmonic impedance roll-off to the edge of the Smith chart. The matching networks are implemented on substrate RO4350B from Rogers Inc. (Chandler, AZ, USA), with a dielectric constant of 3.66 and thickness of 0.508 mm. The matching network layout of the proposed PA circuit is illustrated in Figure 6b. Figure 5: Simulated fundamental load–pull contours of the output power and power added efficiency (PAE) under different drain biases. Figure 6: _Cont._  
The measured gain and PAE at various supply voltages as a function of output power together with the statistical PDF of the modulated signal are shown in Figure 7. The blue dots on the gain and PAE curves represent the gain trajectory and PAE trajectory of the ET operation. The maximum drain supply is set to 27.5 V, and the corresponding output power is about 42 dBm. The minimum drain supply is set to 5 V, and the corresponding peak output power is about 24 dBm. Note that the peak PAE exceeds 70% when drain supply is set from 12.5 V to 27.5 V. That means the proposed PA provides high PAE over a wide range of output powers. This behavior ensures high overall efficiency for the ET architecture. The performances of the demonstrated PA are listed in Table 2, in comparison with the state-of-the-art ET PAs in the literature.