## 1 Introduction  
The golden ratio (commonly referred to as the golden section or golden mean, and denoted by the Greek letter Phi) is noteworthy for a variety of reasons: firstly, it can be observed in many naturally occurring patterns, artistic works, and mathematical phenomena; and secondly, in more recent years, the literature has uncovered specific nanoscale symmetry concealed within solid state matter, which reflects aspects of the golden ratio [1]. Despite the availability of numerous studies that have sought to measure natural instances of the golden ratio, a publication has yet to emergence addressing the effect that Phi has on the central parameters and performance of nano transistors, including gate all around (GAA) nanowire transistors (NWTs) [2]. As illuminated in studies such as [3,4], GAA NTWs constitute a promising device architecture that are anticipated to be used for technological advancement in the domain of nodes. In particular, owing to their favorable property of electrostatic integrity, GAA NTWs have been marked as one of the successors of Fin field effect transistor (FinFET) technology in the 5-nm technology node. It is possible to establish an ideal compromise between leakage currents and GAA NTW performance by engineering device structures. In fact, the literature indicates that the nanowires' cross-sectional shape strongly affects NWTs' gate capacitance and mobile charge [5, 6, 7]. As a case in point, for an NWT characterized by <110> channel orientation, as well as an extended elliptical cross-section (where the long diameter is parallel to the surface of the silicon wafer), it is associated with the greatest mobile charge for a certain gate voltage. It is noteworthy that one of the key determinants of device performance has been established as the ratio of the major axis to the minor axis (namely, cross-section aspect ratio or AR). Nevertheless, industrial players have tended to only manufacture NWTs in two different versions: circular cylinder (or elliptical) NWTs [8; 9] and nanosheet (or nanoslab) FETs [10]. Each version has its own trade-offs; however, the key difference between these two versions is the cross-sectional AR. Several critical design questions, including the optimal NWT cross-sectional aspect ratio, remain unanswered. To answer this question, the AR of a GAA NWT is changed while the cross-sectional area is kept constant; surprisingly, the signatures of the isotropic/anisotropic charge distributions are observed as showing the same attributes as the golden ratio. The immediate aim of the present research is to examine the distinctive structural and dimensional features of the transistors associated with 5-nm Si CMOS technology, thereby illuminating the quantum mobile charge to gate capacitance ratio [5; 7], where the indicator of the intrinsic speed of the NWT is the intrinsic delay (\(\tau\)) [11]. For the purpose of heightening the degree to which the obtained results are realistic, the simulations take into consideration the effect of quantum confinement, non-equilibrium transport, and contact resistance for such ultra-scaled NWTs. An examination of the correlation between the golden ratio and 5 nm NWT performance is also made to take into account the effect of the main sources of statistical variability (SV) [12]. The early successes of fabrication of vertically stacked lateral NWTs may help resolve degradation of the drive current per footprint while shrinking the contacted gate pitch at the 5 nm node [9; 10]. The vertically stacked NWTs have also been included in the international technology roadmap for semiconductors (ITRS) roadmap [13]. In an attempt to determine the performance of vertically stacked of NWT with golden AR, the quantum correction achieved by Poison-Schrodinger was used together with non-equilibrium transport to calibrate the drift-diffusion of a single NWT [14; 15]. The calibrated drift diffusion (DD) was then used to simulate the vertically stacked lateral NWTs.