## 2 Materials and Methods  
To investigate the applicability of ALD to tunnel barrier formation, we fabricate \"cross-tie\" SETs, as illustrated in Figure 1. The process involves fabrication of two metal layers defined by electron-beam lithography (EBL, Vistec, Jena, Germany) with ALD dielectric in between. The general approach for fabrication of SETs in the cross-tie geometry is outlined below, while more fabrication details are given within the results subsections. In the first step, the bottom metal layer defining the source and drain electrodes (20-40 nm thick, 50 nm wide) is deposited by electron beam evaporation through the EBL-defined mask on 500 nm of thermally grown SiO\({}_{2}\), as shown in Figure 1a. After liftoff and cleaning, the dielectric barrier is deposited using ALD (Figure 1b). Finally, the top metal layer forming a cross-tie island (20-50 nm thick) is defined by evaporating the metal through the EBL-defined mask and liftoff (Figure 1c). In cross-tie SETs, inert metals such as platinum (Pt) and palladium (Pd) were studied as electrode materials to avoid the influence of native metal oxides in the MIM junctions. The resulting structures feature two nominally identical junctions, the capacitance of which can be estimated from a parallel-plate approximation \(C_{d}=C_{s}=\varepsilon\varepsilon_{0}A/d\) where \(\varepsilon_{0}\) and \(\varepsilon\) are the vacuum permittivity and the dielectric constant of a chosen ALD dielectric, A is the junction area defined by the overlap between the island and each lead, and d is the thickness of the barrier. For a 1 nm thick SiO\({}_{2}\) (Al\({}_{2}\)O\({}_{3}\)) tunnel barrier with a junction area of \(\sim\)4000 nm\({}^{2}\) (Figure 1d), the parallel plate model gives a capacitance value of \(\sim\)180(350) aF (using bulk values of \(\varepsilon\) = 3.9 for SiO\({}_{2}\) and \(\varepsilon\) = 9 for Al\({}_{2}\)O\({}_{3}\)). The charge population of the island is controlled by an electrostatic gate situated 0.5 to 5 um away from the island (shown in Figure 1d) resulting in an experimentally determined capacitance of 0.1 to 30 aF. Assuming a gate capacitance much smaller than the junction capacitance, the total island capacitance for device is, therefore, \(\sim\)350-400 aF for an SiO\({}_{2}\) barrier and \(\sim\)700-900 aF for an Al\({}_{2}\)O\({}_{3}\) barrier. This sum of the capacitances \(C_{\Sigma}\) defines the figure of merit for an SET, the charging energy \(E_{C}=e^{2}/2C_{\Sigma}\)[10], where \(e\) is electron charge, the calculated value of which is \(\sim\)0.2 meV for an SiO\({}_{2}\) barrier or 0.1 meV for Al\({}_{2}\)O\({}_{3}\). Thus, the chosen design enables observation of well-developed Coulomb blockade at an experimentally attainable temperature \(T\) = 0.3 K \(<<E_{C}/k_{B}\) where \(k_{B}\) is the Boltzmann constant. A modification of this process, known as \"half damascene\" fabrication, is used to decrease the overlap of the source and drain with the island by fabricating an island inlaid in the substrate dielectric (Figure 2) [11]. This lowers the capacitance of the junctions by narrowing the width of the island and avoiding the side overlap always present in cross-tie design and thus raises the maximum operating temperature of the device. To fabricate the inlaid island devices, the pattern of the island is etched into the oxide in an inductively coupled plasma (ICP, Oxford, Abingdon, UK) etcher [12] (Figure 2b). Metal is deposited by e-beam evaporation to fill the trench in the SiO\({}_{2}\) (Figure 2c) and chemical mechanical polishing (CMP, Logitech, Glasgow, UK) is then used to remove any residual metal on the oxide field, while leaving the island trench filled with metal (Figure 2d). CMP enables a very significant decrease in the junction area and can be used to fabricate a full-damascene metallic SET [13]. Next, ALD is used to form the tunnel barrier over the island (Figure 2e). Finally, the source and drain are defined using the same process as for the cross-tie devices (Figure 2f).