## 2 Circuit Design
The effect of L\({}_{\rm P}\) can be cancelled by C\({}_{\rm m}\) (=M/[\(\omega_{0}^{2}\)L\({}_{\rm L}\)(L\({}_{\rm L}\) - 2M)]) in Figure 3. The \(\pi\)-network comprised of C\({}_{\rm P2}\), L\({}_{\rm S1}\), and C\({}_{\rm P3}\) introduces a phase delay of 90\({}^{\circ}\), while the T-network comprised of C\({}_{\rm S1}\), L\({}_{\rm P1}\), and C\({}_{\rm S2}\) (or the \(\pi\)-network comprised of L\({}_{\rm P2}\), C\({}_{\rm S3}\), and L\({}_{\rm P3}\)) introduces a phase lead of 90\({}^{\circ}\). This is the way to achieve balun operation of the device. Shown in Figure 4a is the simplified layout and chip photo of the first test balun, balun-1. A spiral layout is used for L\({}_{\rm S1}\) and L\({}_{\rm P1}\) in order to achieve a compact size. Balun-1 occupies a chip area of only 0.225 \(\times\) 0.148 mm\({}^{2}\), i.e., 0.033 mm\({}^{2}\). Figure 4b shows the simplified layout of the RF and the LO baluns (i.e., dual balun-2) of the down-conversion mixer in this work. A symmetrical layout is crucial for the differential mixer core to attain good port-to-port isolation and overall performance. Therefore, the dual-balun-2 layout  
Figure 3: Illustrative diagram of the power-divider-based balun. Figure 2: (**a**) Schematic diagram, and (**b**) chip photo of the down-conversion mixer. in Figure 4b is used to fit the symmetrical layout of the mixer core. The dual balun-2 occupies a chip area of 0.089 mm\({}^{2}\). According to our previous experience, measured results of mm-wave passive devices are consistent with the simulated results of the EM simulator HFSS and ADS Momentum [13]. To expedite the realization of the down-conversion mixer, tape-out of the mixer is conducted based on the EM-circuit cosimulation result of the layout, i.e., post-layout simulation result, via ADS Momentum. Therefore, tape-out of the test device of dual balun-2 was not performed. The measured reflection coefficients (S\({}_{11}\), S\({}_{22}\), and S\({}_{33}\)), isolation between the outputs S\({}_{32}\), and gain (S\({}_{21}\) and S\({}_{31}\)) of balun-1 are shown in Figure 5a. Balun-1 achieves a local minimum S\({}_{11}\) of \(-21.6\) dB at 32 GHz and S\({}_{11}\) better than \(-10\) dB from 26.2 GHz to over 50 GHz. The corresponding \(-10\) dB input, matching the bandwidth (f\({}_{10\text{dB}}\)), is wider than 23.8 GHz. Balun-1 achieves a local minimum S\({}_{22}\) of \(-19.5\) dB at 32 GHz and S\({}_{22}\) better than \(-10\) dB from DC to 36.7 GHz, equivalent to an f\({}_{10\text{dB}}\) of 36.7 GHz. Balun-1 achieves a minimum S\({}_{33}\) of \(-23.4\) dB at 32 GHz and S\({}_{33}\) better than \(-10\) dB for 25.7-39.7 GHz, equivalent to an f\({}_{10\text{dB}}\) of 14 GHz. Moreover, balun-1 attains a local minimum S\({}_{32}\) of \(-25.7\) dB at 33 GHz and S\({}_{32}\) better than \(-10\) dB from DC to over 50 GHz, equivalent to a \(-10\) dB isolation bandwidth (f\({}_{10\text{dB},\text{iso}}\)) wider than 50 GHz. Balun-1 achieves S\({}_{21}\) of \(-4.441\) dB at 32 GHz and S\({}_{21}\) better than \(-5\) dB for 26.3-36.7 GHz, close to the measured S\({}_{31}\) (\(-4.131\) dB at 32 GHz, and better than \(-5\) dB from 25.5 GHz to over 50 GHz). Figure 4: (**a**) Layout and chip photo of balun-1. (**b**) Layout of dual balun-2. Figure 5: Measured (**a**) S-parameters, and (**b**) AI and PD of balun-1. Figure 5b shows the measured amplitude imbalance AI (equal to \(\rm S_{21}(dB)-S_{31}(dB)\)) and phase deviation PD (equal to \(\rm S_{21}(degree)-S_{31}(degree)-180^{\circ}\)) of balun-1. Balun-1 achieves the best AI of \(-0.127\) dB at 28 GHz and AI within \(\pm 1\) dB for 22.2-36.7 GHz, as well as the best PD of \(-0.08^{\circ}\) at 35 GHz and PD within \(\pm 5^{\circ}\) for 28.6-40.3 GHz. Compared to that with the commonly used Marchand balun with poor \(\rm S_{22}\), \(\rm S_{33}\), and \(\rm S_{32}\) (of \(-6\) dB in theory) [8], better overall performance is achieved. Figure 6a shows the simulated AI and PD of balun-2.