# A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis
## 2 TSV Metrology
### Electric-Field (E-Field) and Keep-Out Zone (KOZ)  
The increase in the number of silicon vias (TSVs) per unit area results in electrical channels in adjacent semiconductor devices being closer to the depletion zone induced by the electric field (E-field) surrounding the TSVs. Given these negative effects, a keep-out zone (KOZ) is required to ensure proper operation of three-dimensional integrated circuits (3-D ICs) using TSVs. All logic cells must be placed where the carriers within the PMOS/NMOS channel are not affected by the electric field (E-field) around the TSV [38]. There are several ways to determine the no-go zone (KOZ) of 3-D ICs. [PERSON]'s research show that for an accurate KOZ, the charge carriers in the depletion zone and the charge type defects in the TSV must be considered [39] (Figure 7). In this work they developed a KOZ determination method for TSV by solving [PERSON]'s equation (Equation (1)). It is worth noting that, especially for transistors, stress changes the carrier mobility and, thus, the performance of the transistor. As such, the size of the KOZ also depends on the size of the TSV [40]. Equations (1)-(3) are as follows:  
\[W_{\text{Koz}}(\varphi_{s}\
eq 0)=r_{1}\Bigg{\{}\exp\Bigg{(}\Bigg{(}1+\frac{ \varphi_{s}+{r_{1}}^{2}\tau_{s}(\varphi_{s})}{\sqrt{{\varphi_{s}}^{2}+2{r_{1} }^{2}\eta_{s}(\varphi_{s})}}\Bigg{)}^{-1}\Bigg{)}-1\Bigg{\}} \tag{1}\]  
\[\tau_{s}(\varphi_{s})=-\frac{qN_{a}}{\varepsilon_{Si}}\bigg{(}\exp\Big{(}- \frac{q\varphi s}{KT}\Big{)}-1+\frac{{n_{i}}^{2}}{{N_{a}}^{2}}\bigg{)} \tag{2}\]  
\[W_{\text{Koz}}(\varphi_{s}=0)=r_{1}\Bigg{\{}exp\Bigg{(}\Bigg{(}1+\sqrt{1+{r_{1 }}^{2}\frac{qN_{a}}{\varepsilon_{Si}}\frac{q}{KT}}\Bigg{)}^{-1}\Bigg{)}-1 \Bigg{\}} \tag{3}\]  
where \(N_{a}\) is the doping concentration in p-type Si, \(\varepsilon_{Si}\) is the permittivity of Si, \(\varphi_{s}\) is the surface electrical potential, \(n_{i}\) is the intrinsic carrier concentration of Si, \(q\) is the electron charge, \(K\) is the Boltzmann constant, and \(T\) is the absolute temperature.  
Therefore, an insulating dielectric liner needs to be deposited after the silicon via etch is complete to increase breakdown voltage and reduce leakage current. In high aspect ratio TSVs, liner, barrier, and seed deposition technologies are critical for process integration and reliability. The reliability of the liner is studied by applying a negative voltage to the  
Figure 7: Charge-type imperfections, which include mobile oxide charges (Q\({}_{\text{m}}\)), oxide trap charges (Q\({}_{\text{ot}}\)), fixed oxide charges (Q\({}_{\text{t}}\)), and interface trap charges (Q\({}_{\text{it}}\)) in a TSV (adapted from [39]).  
TSV (known as the copper closed mode). In this stress mode, the copper ions of TSV are attracted by the voltage source and are not injected into the pad during the test. This makes it possible to study the inherent liner characteristics. The barrier performance is studied by comparing the measurement results in the copper closed mode with the measurement results obtained when a positive voltage is applied to the TSV (later known as the copper drive mode). In the latter stress mode, copper ions are pushed into the liner in the case of barrier defects. The large difference in TDDB data between the two modes may indicate poor barrier characteristics (Figure 8) [20; 41].