# Low Power QC-LDPC Decoder Based on Token Ring Architecture
## 6 Future Work  
The results of the work presented in the article encourage further research. We plan to perform similar experiments first for several other FPGA families, both from Intel and Xilinx. We hope that they will allow us to confirm the thesis about the universal nature of the proposed solutions and their suitability for a wide range of programmable systems.  
Figure 8: Influence of the \(P\) value on the \(E_{d}\) value for a QC-LDPC decoder with an architecture based on Token Ring.  
The second area of research will be the search for a way to use the reconfiguration of the programmable structure in order to optimize the parameters of the low-power LDPC decoder. The modern FPGA system can not only be statically reconfigured but also reconfigured during its operation, called dynamic reconfiguration. Such a decoder implementation, in which the circuit structure would be adapted to the currently decoded information, would make it possible to adapt the hardware solution to the specificity of the decoded information, providing application-appropriate correction parameters. Multi-context systems, i.e., those that have the ability to adapt their hardware structure to the currently performed task, are the object of research in various areas of application of programmable systems. It cannot be denied that the implementation of the multi-context LDPC code decoder, probably currently possible, is a real challenge. This challenge is behind our planned scientific and research work that we intend to conduct in the near future.  
Conceptualization, M.K., W.S. and D.K.; methodology, M.K., W.S. and D.K.; software, M.K., W.S. and D.K.; validation, M.K., W.S. and D.K.; formal analysis, M.K., W.S. and D.K.; investigation, M.K., W.S. and D.K.; resources, M.K., W.S. and D.K.; data curation, M.K., W.S. and D.K.; writing--original draft preparation, M.K., W.S. and D.K.; writing--review and editing, M.K., W.S. and D.K.; visualization, M.K., W.S. and D.K.; supervision, M.K., W.S. and D.K.; project administration, M.K., W.S. and D.K.; funding acquisition, M.K., W.S. and D.K. All authors have read and agreed to the published version of the manuscript.  
The work reported in the paper is partially supported by the European Social Funds; project no POWR.03.02.00-00-1007/17-00 \"CyPhis--the program of modern PhD studies in the field of Cyber-Physical Systems\" and financed with university funds (BKM).  
The authors declare no conflict of interest.  
The following abbreviations are used in this manuscript:  
ALM Adaptive Logic Module  
BER Bit Error Rate  
BP Belief Propagation  
CPM Circulant Permutation Matrix  
FER Frame Error Rate  
FPGA Field Programmable Gate Array  
GALS Globally Asynchronous Locally Synchronous  
GCLK Global Clock Signal  
LAN Local Area Network  
LCLK Local Clock Signal  
LDPC Low-Density Parity-Check  
LLR Log-Likelihood Ratio  
MS Min-Sum  
NMS Normalized Min-Sum  
QC-LDPC Quasi-Cyclic Low-Density Parity-Check  
VLSI Very Large Scale Integration  
The following notations are used in this manuscript:  
\(:=\) symbol means \"becomes\"  
\(K\) number of information bits  
\(M\) number of redundant code bits  
\(N\) the sum of the number of information bits and redundant code bits (block length)  
\(R\) code rate  
\({\bf H}\) low density parity check matrix  
\(X\) decoded vector