# Review of Ka-Band Power Amplifier
## 3 Topologies
### Power Combining
#### 3.4.1 Corporate Combiner  
Generally speaking, when other external conditions remain unchanged, the output power of microwave power amplifier is directly proportional to the gate width of the transistor or FET. Theoretically, the output power can be increased by adding a single transistor, but this method will cause difficulties in matching and the problem of reducing the cut-off frequency in practical application, because the input and output impedance of the transistor is too low. When a single transistor cannot meet the output power index of microwave power amplifier, the most common method is to use binary arrangement to improve the output power. However, after inserting the power synthesizer, the efficiency and working bandwidth of the amplifier will be reduced. Ref. [72] showed that under the condition of multi-tube synthesis, the PAE of the power amplifier is reduced to about half of that of a single tube.  
Figure 13: Three-way power amplifier circuit schematic diagram.  
Corporate combiner is a form of parallel (or current) combining. In general, the corporate combiner is a binary arrangement, which is most common in III-V technology, and also used in Si and SiGe. Generally, the power synthesis technology using binary mode has a wide range of applications and can flexibly select the number of channels to be synthesized. Therefore, it is the preferred way to realize high power output in commercial chips. The general corporate combiner power amplifier topology is shown in Figure 14.  
In 1986, [PERSON] et al. proposed the first monolithic microwave integrated circuit (MMIC) PA on 44 GHz [73]. The output power of 17.8 dBm and the power density of 0.2 W/mm were achieved by using the parallel combination of single-ended transistors with a gain of over 10 dB.  
In 2000, [PERSON] proposed a power amplifier in 0.35 nm GaAs FETs, consisting of four fully matched parallel MMIC with an output power of more than 30 dBm [74]. The measured results demonstrate that Psat is 34.8 dBm at 28 GHz, which proves that multi-MMIC chip combined technology topology is valid.  
In [75], [PERSON] presented a 3-stage PA MMIC in 150 nm GaAs pHEMT (see Figure 15). Sixteen parallel \(8\times 50\) um FET were used for the output stage to improve the thermal properties and performance. The PA achieved 30% PAE and 23 dB gain while maintaining an output power higher than 37.2 dBm.  
Figure 14: Corporate combiner power amplifier circuit schematic diagram.  
Figure 15: The 3-stack 16-combined PA150 nm GaAs pHEMT [75].  
The 3-stage combined PA is common in power combining topologies, where desired performance can be achieved under an appropriate area. In [76; 77; 78], the 3-stage amplifiers composed of different unit amplifiers were presented, among which the maximum output power reaches 40 dBm [77] and the area is 15.75 mm\({}^{2}\).  
In [80], three PA MMICs in 100 nm GaN HEMT at Ka-band were reported. In order to evaluate the performance of GaN HEMT process, a single-stage PA (MMIC1) made up of a single HEMT is designed. The second PA (MMIC2) consists of two parallel MMIC1. Finally, a 2-stage power combination PA is designed (MMIC3), the input stage is two parallel HEMT drive output stage, which consists of 2 \(\times\) 2 parallel HEMTs (see Figure 16a). The measured results of MMIC1/MMIC2/MMIC3 demonstrate that PAE and P\({}_{sat}\) are 41%/33%/28% and 31.5/33.8/36.7 dBm, from 29 to 31 GHz.  
Ref. [81] also demonstrated the method of combining two identical MMIC2 in parallel to form a new MMIC1, with an output power of 40 dBm and a PAE of 36%, respectively. In 2016, [PERSON], [PERSON] proposed a method of placing isolating backvia wall (IBVW) between input stages to increase isolation and improve the stability of the system (see Figure 16b) [82]. Fabricated in the 100 nm GaAs pHEMT process, the compact-size wide-band PA chip achieves P\({}_{sat}\) and peak PAE of 37 dBm and 26%, respectively.