# Reliability Prediction of Mixed-Signal Module Based on Multi-Stress Field Failure Mechanisms
## 5 Electro-Thermo-Mechanical Multi-Physics Coupling Analysis
### Power Consumption Analysis and Thermal Simulation of the Communication Module
The power consumption distribution of the FPGA is obtained through modeling analysis, while the SRAM power consumption is set at 50.08 mW. The Quartus II 13.1 Chip Planner function is used, as shown in Figure 15, to map the power consumption results to the FPGA layout and routing diagram, allowing for the identification of specific locations. This article analyzes FPGA units with power consumption no lower than 0.05 mW. Given the complexity of the FPGA solder joints, the Mesher-HD method is used for meshing. Since both FPGA and SRAM are small in size, they are treated as separate assemblies for meshing, and a separate assembly is created for the solder joint array. A mesh sensitivity analysis is conducted to evaluate the impact of the mesh size on simulation accuracy, ensuring a balance between computational efficiency and result precision. The final model contains 764,972 elements and 807,266 nodes. \begin{table}
\begin{tabular}{c c c} \hline
**Parameter Type** & **Parameter Value** &
\begin{tabular}{c} **Proportion of Total** \\ **Power Consumption** \\ \end{tabular} \\ \hline Total power consumption & 108.56 mW & 50.04\% \\ Core dynamic power consumption & 8.32 mW & 3.84\% \\ Core static power consumption & 48.49 mW & 22.35\% \\ I/O power consumption & 51.57 mW & 23.77\% \\ \hline \end{tabular}
\end{table} 
Table 2: FPGA power consumption analysis results. \begin{table}
\begin{tabular}{c c c c c} \hline
**Unit Type** & \begin{tabular}{c} **Total Power** \\ **Consumption (mW)** \\ \end{tabular} & \begin{tabular}{c} **Unit Dynamic Power** \\ **Consumption (mW)** \\ \end{tabular} & \
\begin{tabular}{c} **Routing Dynamic Power** \\ **Consumption (mW)** \\ \end{tabular} &
\begin{tabular}{c} **Unit Static Power** \\ **Consumption (mW)** \\ \end{tabular} \\ \hline PLL & 6.61 mW & 6.61 mW & 0.00 mW & N/A \\ Combinational cell & 0.04 mW & 0.03 mW & 0.01 mW & N/A \\ Clock control block & 0.78 mW & 0.00 mW & 0.78 mW & N/A \\ Register cell & 0.89 mW & 0.84 mW & 0.05 mW & N/A \\ I/O & 31.77 mW & 0.35 mW & 0.00 mW & 31.42 mW \\ \hline \end{tabular}
\end{table} 
Table 3: FPGA unit power consumption analysis report. After constructing the thermal simulation model for the communication module, a transient thermal simulation analysis is performed for 14,400 s, covering four temperature cycles. Upon completion of the analysis, the temperature distribution at the end of the high-temperature phase of the fourth cycle (at 12,480 s) is selected. This includes the temperature cloud diagrams of the FPGA chip, solder joint array, and SRAM pins, as shown in Figure 16.  
It can be observed that the upper part of the FPGA solder joint array experiences significant heating, corresponding to the heating position of the chip. On the board, the simulation results show that the SRAM is influenced by the FPGA's heat, leading to severe heating of the left-side pins. By analyzing the temperature variation of the FPGA and SRAM, the highest temperature solder joint is selected to plot the temperature curve, as shown in Figure 17, showing that the temperatures of both stabilize and are similar during the fourth cycle. The average temperature of the FPGA solder joints is 26.7602 \({}^{\circ}\)C, while the average temperature of the SRAM solder joints is 25.7766 \({}^{\circ}\)C. Additionally, the average temperature of the FPGA chip die is 26.7643 \({}^{\circ}\)C, and the average temperature of the SRAM chip die is 26.074 \({}^{\circ}\)C.  
Figure 16: Temperature distribution cloud maps of communication module parts (12,480 s). Figure 15: Chip planner layout and routing diagram, darker colour means higher power density.