## 2 Background and Motivation
### Effect of NUMA Access  
Modern main memory systems consist of dual inline memory modules (DIMMs) that contain DRAM chips. These DIMMs are combined to form the total main memory capacity of the system. As parallelism continues to increase in multicore and multi-processor nodes within clusters, distributed memory banks and buses with varying access costs have become prevalent. This approach, known as non-uniform access (NUMA), assigns separate memory banks to each processor, distributing memory and CPUs across different nodes. This mitigates the performance impact caused by multiple processors or cores accessing the same memory simultaneously. Processors within the same node have faster access to their local memory while accessing remote memories on other nodes incurs higher latency. This distinction in memory access speed contributes to overall performance improvements.  
Today, high-performance servers commonly utilize non-uniform memory access (NUMA) architectures, which feature intricate memory hierarchies. This adoption of NUMA by computer architects allows for accommodating numerous cores within a single computer. The cores are organized into nodes, with each node sharing the last-level cache (LLC) and memory. However, traditional assumptions regarding memory, such as access time and memory stall, no longer hold true in these machines. NUMA machines often experience longer memory stalls, and designing accurate data structures to optimize performance becomes more challenging in such environments [24].  
Therefore, in order to achieve high performance, it is essential to design indexing structures that effectively leverage the benefits of NUMA. These designs need to prioritize efficient time complexity, minimize the synchronization overhead, and ensure cache-efficient memory access patterns. The latency and bandwidth in NUMA systems vary based on the nodes involved in data access and storage. Extensive research has been conducted on NUMA optimizations, which primarily revolves around strategically placing threads and data across nodes to minimize latency and maximize bandwidth [25; 26; 27; 28; 29]. The performance of a system is influenced by both hardware and software design choices that take into account the memory system architecture. In multicore processors, for instance, the cores share on-chip memory systems' resources such as memory controllers, last-level caches, and pre-fetcher units. These shared resources play a crucial role in determining the overall system performance. When there is competition for the utilization of these resources, it can result in a decline in performance [30; 31]. The operating system scheduler plays a vital role in mitigating contention issues related to shared last-level caches. Addressing problems associated with data locality can be achieved through either profile-based or dynamic memory migration techniques [30]. The performance of non-volatile file systems can be significantly impacted by the challenges of accessing non-local memory (NUMA effects) [32]. Introducing NUMA-aware interfaces to file systems that utilize non-volatile memory modules can alleviate these issues. There is ongoing research focused on enhancing NUMA locality, with some proposing the redesign of data structures to incorporate NUMA awareness, allowing for optimal utilization of the internal features of these structures [33; 34; 35; 36].  
Optimizing memory allocation in NUMA systems is crucial for maximizing system performance. Furthermore, the selection of efficient NUMA-aware file systems significantly impacts overall performance [37]. With the introduction of Optane DIMMs, there is a growing body of research focused on redesigning storage systems to fully leverage their potential [16; 38].