# HERMES CubeSat Payload Thermal Balance Test and Comparison with Finite Volume Thermal Model
## 3 Test Procedures
### Test Configuration  
This section describes the PL test preparation. Due to its configuration, the PL needs to be integrated \"upside down\" with the SDD and crystals facing downward, as shown in Figure 5. During this process, the electronics support boards of the detector, namely, the FEE lateral boards, are disconnected from the back end electronic board BEE and kept in place by two integration supports, shown in Figure 5a. For more information on the PL boards the reader can refer to [20,21]. The temperature sensors, used in the TVAC test to monitor the PL, are placed during the DM integration phase. A thermocouple (TC) is fixed at the bottom of the crystal box (Figure 5b) while a second thermal sensor is placed on the FEE lateral wing as shown in Figure 5c. As the FEE wings are the main heating path toward the SDDs, the latter TC is included to monitor the heat flow toward the most sensitive part of the assembly, with the aim to obtain a finer estimation of the thermal interfaces, needed to refine the design and to further limit the heat flow to the SDDs. Type T thermocouples ([[https://it.rs-online.com/web/p/termocoppie/3630266](https://it.rs-online.com/web/p/termocoppie/3630266)]([https://it.rs-online.com/web/p/termocoppie/3630266](https://it.rs-online.com/web/p/termocoppie/3630266)) (accessed on 2 November 2022)), produced by RS and with an accuracy of \(\pm 1\,^{\circ}\)C have been adopted for this test. Each TC is fastened with one layer 0.127 mm thick Kapton tape and covered with aluminum tape to provide shielding from infrared radiation [35]. The list of the thermocouples adopted in the test campaign, together with the relative nomenclature and the references to correspondent figures is summarized at the end of this section. Figure 4: TVAC main components. Heaters are mounted on the BEE and PSU before their integration to provide the correct heat dissipation. The model of the heaters is Arcol HS10 ([[http://www.arcolresistors.com/](http://www.arcolresistors.com/)]([http://www.arcolresistors.com/](http://www.arcolresistors.com/)) resistors/hs10-aluminium-housed-resiso/ (accessed on 2 November 2022)), compliant to both Military (MIL) and International Electronic Commission (IEC) standards. They are strategically placed on electronics to reproduce heat generation due to specific active components actually not functional in the PL Demonstration Model: a heater is mounted on the BEE, in place of the FPGA (Figure 5(a)); a second heater is located on the PSU on the dummy DC/DC converter (Figure 5(b)), and a third is placed on the PDHU [36] on the SD card slots (Figure 5(c)). Heaters are held in place by an adhesive film plus one layer 0.127 mm thick Kapton tape strip. A TC is placed close to each heater to directly monitor its temperature. TC positions near the heaters are shown in Figure 6(a) for the BEE-PCB and in Figure 6(b) for the PSU-PCB. Figure 5: FEE and crystal box thermocouples. Figure 6: Heaters positions. Heaters are the ones connected with wires in the pictures. At this point, the PL integration is completed by removing the FEE integration supports, leaving the wings free to be folded along the lateral faces. The remaining electronics are inserted in position, and the bottom structural rib is locked to hold the full stack in place (Figure 8a). Wires are routed between the PDHU-PCB (i.e., the PCB at the bottom of the PL) and the structural rib (Figure 8b), thus the last heater is placed on the PDHU-PCB with the respective TC, as shown in Figure 8c. As last step, payload side panels are integrated, and the assembly is connected with the mechanical support that provides the correct interface with the TVAC cold plate. Two thermocouples are located on the interface, as shown in Figure 9a: one of them is selected as reference for the TVAC controller, enabling direct control of the PL thermal interface, while the second is used for monitoring purposes.