# A Scalable Bidimensional Randomization Scheme for TLC 3D NAND Flash Memories
## 4 Experimental Validation  
The experimental validation of a randomization scheme requires the assessment of the memory reliability according to the data pattern written within. In this work, this activity took place by characterizing the RBER of an off-the-shelf \(N\) (\(N<100\)) layers TLC 3D NAND Flash technology featuring \(M\) (\(M<16\)) wordlines per layer, where its input data were supplied either by a Horizontal Centric (HC) randomizer (i.e., a randomizer that  
Figure 8: When applied to a \(N_{p}\) = 256 \(\times\)\(N_{B}\) = 217 memory block, the data provided by an 8-bit ALFSR consist of a sequence of 256 \(\times\) 255 arrays. Figure 9: Possible schemes used to reconstruct data read from a memory page. (**a**) At any clock cycle \(c\) the read data is XORed with the last register bit \(Y_{i-1}(c)\) to provide \(d(c)\); (**b**) \(k\) clock pulses are applied to ALFSR\({}_{2}\), then the register content is XORed with \(k\) data read and the procedure is repeated until all page data are read. does not properly control the vertical randomization) or by our proposed method. The RBER characterization has been performed in two well-defined corners of the memory lifetime, namely after an endurance stress test (i.e., repeatedly writing and erasing the memory blocks) and after a data retention test at high temperatures. The standards adopted for endurance stress and data retention were chosen according to the JEDEC tests specifications for the 3D NAND Flash enterprise qualification procedure [19], resulting in 3000 Program/Erase cycles (that is the technology rated endurance) at a temperature of 61 \({}^{\circ}\)C for 500 h cycle time and a retention stress test performed on cycled devices for 3 months at 40 \({}^{\circ}\)C.  
The experimental setup described in [20] has been exploited for both characterizations. To rule out any topological artifacts in the measurements, we disabled any error correction functionality of the chip, and we did not apply any modification to the standard working voltages of the devices and no special test modes were exploited to filter the RBER. We also ruled out the presence of on-chip randomizer circuitry that could alter the findings. The data analysis was performed on all the wordlines within a memory block considering all the TLC page types. The size of a page is 16 kB, along with the parity left for error correction code purposes, divided into 4 kB chunks, which are the minimum units read during tests by the characterization system. The testing lasted several months. Figure 10 shows the Complementary Cumulative Distribution Function (1-CDF) as a function of the TLC page type of the RBER in a 3D NAND Flash block programmed with an HC randomizer (cases \(a\) and \(c\)) or with our proposed method (cases \(b\) and \(d\)). For the endurance stress cases we observe that an HC randomizer could dangerously induce an RBER close to the error correction capacity of many advanced schemes (we refer here to the case of a 100 b/1 kB that is a maximum allowable RBER of 1.1 \(\times\) 10\({}^{-2}\)) [21; 22], whereas with our proposed method, we still have a sufficient margin with respect to that reliability limit. In the HC randomizer, we remember that there is neither a control of the patterns of ones and zeros achieved along the bitline (i.e., vertical dimension) nor an upper bound to their maximum length. This can result in some fortunate patterns (as observed in these experiments for the CSB pages), where the RBER appears as the best; however, this is at the expense of inducing the worst patterns on the other TLC pages (i.e., LSB and MSB). From the statistical standpoint, we observe an imbalanced situation where the optimal patterns are concentrated only in one TLC page type. With our proposed methodology, we guarantee a good pattern balancing among the TLC pages, thus significantly reducing the worst RBER case and homogenizing the behavior of all the 3D NAND Flash memory locations.