# Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division
## 3 Predict-Correct Algorithm for Division
### Choice of Parameters \(m\), \(t\), and \(n\) in Predict-Correct Algorithm  
As stated in Section 3.2, the proposed Predict-Correct algorithm generates \(m\times t-t+n-1\) bits per clock cycle. Change of Parameter \(m\), \(t\), or \(n\) leads to different guaranteed bits per cycle. Discussions about choice of parameters \(m\), \(t\), and \(n\) adopted in FP division hardware architecture are as follows.  
Table 1 lists five options of Parameter \(n\) from \(1\) to \(5\). It can be seen from Table 1 that as \(n\) increases, the number of possible quotients increases exponentially. When \(n>3\), increase in guaranteed bits of quotient per cycle cannot make up the foreseeable extra cost of subsequent selectors accompanied with more possible quotients in Step 6. Compared with Parameter \(n=2\), Parameter \(n=3\) brings about one more guaranteed bit of quotient with only four more subsequent selectors needed. Compared with Parameter \(n=3\), Parameter \(n=4\) takes eight more subsequent selectors. One more guaranteed bit of quotient can apparently not overweight the follow-up computational burden of eight more selectors. To sum up, Parameter \(n\) in the Predict-Correct Algorithm for FP division is chosen to be \(3\).  
When \(t\geq 5\), the increase in guaranteed bits of quotient per cycle is at the cost of pre-computation of the terms in the approximation \(B\). Pre-computation of the terms in \(B\) will definitely add more clock cycles, which is not friendly to low-precision division. When \(t=1\), the Predict-Correct algorithm becomes classical reciprocal method. Therefore, \(t=2\), \(3\), \(4\) will be discussed.  
Table 2 lists different patterns of Parameter \(m\) and \(t\) when \(n=3\). Since this paper mainly focuses on high-precision FP division, so column clock cycles in Table 2 is analyzed based on quadruple precision FP division. When it comes to column clock cycles, the former figure represents the number of iterations in \(113\)-bit mantissa division; the latter represents the number of cycle(s) needed in the pre-computation of the approximation \(B\). In the case of Row 1 in Table 2, \(\lceil 113/20\rceil=6\); \(t=2\) means that at least one cycle is needed to pre-compute the approximation \(B=1/Y_{h}-\Delta Y/Y_{h}{}^{2}\). It can be seen from Table 2 that the listed patterns of Parameter \(m\) and \(t\) have 6 or 7 clock cycles. As Parameter \(m\) increases from 10 to 11, data width of entries in look-up table (LUT) increase by 512. As Parameter  
\begin{table}
\begin{tabular}{c c c} \hline \hline \multirow{2}{*}{**Parameter \(n\)**} & **Additional Digits of** & **2\%** **Kinds of Possible** \\  & **Quotient** & **Quotients** \\ \hline
1 & 1 & 2 \\
2 & 2 & 4 \\
3 & 3 & 8 \\
4 & 4 & 16 \\
5 & 5 & 32 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Options of Parameter \(n\).  
\(m\) increases from 11 to 12, data width of entries in LUT increase by 1024. Apparently, the sharp increase in data width of LUT entries will bring about considerable area. Moreover, the increase in Parameter \(m\) seems to be no benefit to clock cycles. Hence, the patterns of Parameter \(m=12\) are not considered.  
Therefore, the left four patterns are more rational: \(m=10\), \(t=3\); \(m=10\), \(t=4\); \(m=11\), \(t=3\); \(m=11\), \(t=4\). Achieved bits per cycle of patterns \(m=10\), \(t=3\) and \(m=10\), \(t=4\) are 116 and 114. Error may occur in the rounding of the iterated 116-bit or 114-bit quotient to the desired 113-bit normalized quotient. The two patterns are removed from consideration. As for patterns \(m=11\), \(t=3\) and \(m=11\), \(t=4\), the former pattern has more achieved bits per cycle than the latter pattern with the same clock cycles. In all, this paper takes Parameter \(m=11\), \(t=3\) and \(n=3\).