# A Low-Power Read-Decoupled Radiation-Hardened 16T SRAM for Space Applications
## 2 The Proposed LDRH16T Cell and Its Operation  
### Basic Operation  
The schematic of the proposed LDRH16T cell is shown in Figure 1, and its corresponding layout is illustrated in Figure 2. The cell consists of six PMOS and ten NMOS transistors in total. It incorporates two storage nodes (Q and QB), two internal nodes (S1 and S0), and two word lines, WL and WWL. The word line WL controls the access transistors N9 and N10, which connect the internal nodes S1 and S0 to their respective bit lines, BL and BLB. Similarly, the storage nodes Q and QB are connected to the bit lines through the access transistors N7 and N8, which are controlled by WWL. For the purpose of explanation, the LDRH16T cell is assumed to store logic '1', such that the nodes Q, QB, S1, and S0 hold '1', '0', '1', and '0', respectively. Based on this assumption, the basic operations and soft-error recovery behavior of the proposed cell are described in the following sections.  
Figure 1: Schematic of the proposed LDRH16T cell.  
(1) Hold Operation: In the hold mode, both WL and WWL are deactivated. During this state, the bit lines BL and BLB are pre-charged to VDD to reduce wake-up latency. Specifically, transistors N2, N4, N5, P2, P3, and P6 remain ON to maintain the logic '1', while the remaining transistors remain OFF to preserve the logic '0'. As shown in Figure 3, the LDRH16T cell, including its storage nodes, maintains its original data reliably and without disturbance during the hold mode.  
(2) Read Operation: At the beginning of the read operation, the bit lines BL and BLB are pre-charged to VDD, and the word line WL is activated by connecting it to VDD. In contrast, WWL is held at GND to remain inactive, ensuring a disturbance-free read [20]. As a result, BLB discharges through transistors P6, N4, and N2, while BL remains at VDD because P5 and N3 are turned OFF. When the voltage difference between BL and BLB reaches 50 mV, the sense amplifier detects the stored data and completes the read operation. During this process, the access transistors N7 and N8 remain OFF, thereby isolating the storage nodes Q and QB from the bit lines.  
(3) Write Operation: During the write operation, the bit line BL is discharged to GND, while BLB is driven to VDD in order to overwrite the data stored in the cell. Both word lines, namely WL and WWL, are activated simultaneously, turning ON all access transistors  
Figure 3: Operation of the proposed LDRH16T cell.  
Figure 2: The layout of the proposed LDRH16T cell.  
connected to the nodes. As BLB is held at VDD, the nodes QB and S0 are charged through transistors N8 and N10, respectively. As the voltages at QB and S0 rise, the pull-down path for node Q and the pull-up path for node S1 are, respectively, strengthened and weakened, accelerating the discharge of node Q. Once the voltage at Q falls sufficiently, the pull-down transistors N2 and N4 connected to QB and S0 turn OFF, allowing these nodes to be charged more rapidly. As a result, as shown in Figure 3, all nodes are successfully flipped to the target values with the aid of their corresponding access transistors. The simultaneous update of the storage and internal nodes through dedicated access transistors enhances the write speed of the proposed cell.