## 3 Modeling the Inverter in the Frequency-Domain
### PR-Based Current Control Method  
The block diagram of a typical PR based current control single-phase inverter [23] is illustrated in Figure 5. The DC bus supplies power to the full bridge circuit with the voltage vdc. The output voltage of the full bridge circuit is u, i is the inverter output current. The full bridge circuit connects to the grid (v) through an inductive filter (L). The single-phase inverter obtains the phase angle of the grid voltage through a phase-locked loop in order to generate reference current i\({}^{*}\) with the output from the DC voltage regulator i*m. The current loop controller is a quasi-PR regulator, which may robustly track the sinusoidal waveform without a static error, its transfer function is expressed in Equation (6). \[\mathrm{G_{PR}(s)}=\mathrm{K_{P-PR}}+\frac{2\mathrm{K_{P-PR}}\omega_{c}}{\mathrm {s}^{2}+2\omega_{c}+\omega_{0}^{2}} \tag{6}\]  
where \(\mathrm{K_{P-PR}}\) is the proportional coefficient; \(\mathrm{K_{R-PR}}\) is the resonance coefficient; \(\omega_{c}\) is the control bandwidth; \(\omega_{0}\) is the resonant frequency. The output of the regulator is modulation the signal u*. The transfer function of the modulation signal u* to the output voltage of the full bridge circuit u is KPWM. The dynamics on the DC side are neglected here due to the large time constant on the DC side. The small signal model of the system is illustrated in Figure 6.  
In Figure 6, the grey box groups the hardware system of the inverter, the rest represents the controller system. \(\mathrm{Y_{0}(s)}\) is the output admittance of the inverter hardware, \(\mathrm{G_{id}(s)}\) is the transfer function from the output voltage of the full bridge circuit u to output current i. \(\mathrm{T_{PLL}(s)}\) is the transfer function from the grid side voltage v to the normalized current reference. The controller transfer function \(\mathrm{G_{PR}(s)}\) is expressed in Equation (6), \(\mathrm{G_{d}(s)}\) is the transfer function for the time delay in the digital control. The delay time consists of the calculation time in the controller and PWM modulation time. In this case, it is 1.5 times that of the sampling period [24; 25]. Figure 5: The block diagram of a typical PR (proportional resonance) based current control inverter. The output admittance of the inverter hardware \(\mathrm{Y_{0}}\) can be derived by assuming the inverter output is zero; \(\mathrm{G_{id}}\) can be derived by assuming the grid voltage is zero, as expressed in Equation (7). \[\left\{ \begin{array}{l}\mathrm{Y_{0}(s)=-\frac{1}{Ls}}\\ \mathrm{G_{id}(s)=\frac{1}{Ls}}\end{array} \right. \tag{7}\]  
Without considering the effect of the PLL on the inverter, according to Figure 6, the transfer function from reference current i* to inverter output current i can be obtained, as expressed in Equation (8). \[\mathrm{i=\frac{G_{PR}(s)G_{d}(s)K_{PWM}}{G_{PR}(s)G_{d}(s)K_{PWM}+Ls}i^{*}- \frac{1}{G_{PR}(s)G_{d}(s)K_{PWM}+Ls}v} \tag{8}\]  
As shown in Figures 5 and 6, the dynamics of the PLL will affect the performance of the inverter control, so the PLL also needs to be considered in the modeling of the inverter. The block diagram of a typical single-phase synchronous rotation frame (SRF) PLL is shown in Figure 7.  
The operation principle of a single-phase SRF PLL is that by a bandpass-filter, two orthogonal grid voltages \(\mathrm{v_{\alpha}}\) and \(\mathrm{v_{\beta}}\) will be obtained. Then the \(q\)-axis component of the grid voltage \(\mathrm{v_{q}}\) can be calculated by performing a dq transformation on the grid voltage. Let vq become 0 through the closed  
Figure 6: The small signal model of a typical PR based current control inverter. Figure 7: The block diagram of a typical SRF (synchronous rotation frame) PLL. (**a**) Block diagram of a typical single-phase SRF PLL; (**b**) Small signal model of SRF PLL. loop control.