# PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs
## 5 Implementation and Evaluation
### Synthesis Result  
The router was implemented by Verilog. Each router was synthesized with Synopsys Design Compiler using the TSMC 12 nm standard cell to extract the timing and area information. The clock frequency was 3 GHz. For the real application scenario, the bandwidth was set to 263 bits (256 bits data and 7 bits for control). The synthesis results are listed in Table 4. It is worth mentioning that the area is the logic circuit overhead excluding the overhead metal connection wire.  
In order to compare different methods, we configured the interface bitwidth to 49 bits. Due to the different processes used in different studies, we refer to the method in [46] to normalize the silicon area to 65 nm for comparison. Our work is compared with two hybrid switching NoCs CTN [31] and VCS [7] and three packet switching NoCs MRBS [9], namely, MRCN [8] and SmartFork [14]. Our proposal resulted in a decrease in area of 5.6% and 56.5%, respectively, compared with CTN [31] and VCS [7]. This is because we used the same interface to handle packet switching and circuit switching, and only increased the additional bandwidth of the 7 control bits. Compared with PS NoC, the area used by our proposal is reduced by 88.4%, 88.1%, and 67.9% compared with MRBS [9], MRCN [8], and SmartFork [14], respectively. Compared with PS NoC, the proposed method saves the storage overhead of the re-order buffer and virtual channel. The results of different studies are listed in Table 5.  
Additional simulation was conducted using the energy estimation function provided by Noxim. The power estimation function of Synopsys Design Compiler and the power model of the TSMC 12 nm Design Kit were applied in Noxim. The simulation was conducted using an 8 \(\times\) 8 mesh NoC and an injection rate of 0.03 for variable control. Three different traffic models (uniform random, CTG-based, and Rent's Rule) were used to drive the NoC. The simulation time was 100,000 cycles. Our proposed work uses the energy-delay product (EDP) to measure comprehensive performance, where the energy is the total energy consumption of the cores and the delay is the amount of time required to execute applications. SmartFork [14], HOECP [16], MRBS [9], and MRCN [8] were set as references, and the results were normalised to Smartfork. Figure 16 illustrates the EDP for different works under the three different traffic models. The average gain in EDP achieved by four techniques is observed as 38%, \(-\)6%, 23%, and 75% for HOECP, MRBS, MRCN, and PCCNoC compared with SmartFork [14]. These results show that our proposal has better comprehensive performance compared with related works.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline \multicolumn{1}{c}{**Bandwidth (bits)**} & \multicolumn{1}{c}{**Area (\(\mu\)m\({}^{2}\))**} & \multicolumn{1}{c}{**Combinational Area (\(\mu\)m\({}^{2}\))**} & \multicolumn{1}{c}{**Noncombinati-**} & \multicolumn{1}{c}{**Power (mW)**} \\ \hline PCCNoC & 263 & 3180.81 & 1406.78 & 1774.03 & 3.2 \\ \hline \hline \end{tabular}
\end{table}
Table 4: PCCNoC router synthesis result.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline \multicolumn{1}{c}{**Research**} & \multicolumn{1}{c}{**Bandwidth (bits)**} & \multicolumn{1}{c}{**Technology (nm)**} & \multicolumn{1}{c}{**Frequency (GHz)**} & \multicolumn{1}{c}{**Area (\(\mu\)m\({}^{2}\))**} & \multicolumn{1}{c}{**Normalized Area (\(\mu\)m\({}^{2}\))**} & \multicolumn{1}{c}{**Power (mW)**} \\ \hline CTN [31] & 48 & TSMC 65 & 2.8 & 44,157 & 44,157 & 29 \\ VCS [7] & - & TSMC 45 & 2 & 46,000 & 95,975 & 17.1 \\ MRBS [9] & 34 & SAED 32 & 0.5 & 87,753 & 362,066 & 11.8 \\ MRCN [8] & 34 & SAED 32 & - & 85,616 & 353,249 & 8.5 \\ SmartFork [14] & - & 45 & 1 & 62,370 & 130,130 & 5.58 \\ Our work & 49 & TSMC 12 & 3 & 1421 & 41,692 & 1.4 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Synthesis result comparison with other studies.