# Marine Diesel Engine Fault Detection Based on Xilinx ZYNQ SoC
## 3 Results
### Convolutional Neural Network in the PL of ZYNQ
#### 3.2.5 Results Analysis and Comparative Validation  
We evaluated the overall classification ability of five types of fault detection models, i.e., how many samples were correctly classified relative to the total sample set. However, the discrimination for some specific categories was not sufficiently precise. Refer to Table 6.  
According to Table 6, the accuracy of the algorithm for the G3 fault condition reached 100%, while for conditions G1 and G4, the accuracies were 81.82% and 83.41%, respectively. These two conditions might be areas that require improvement. For the other two conditions, the performance reached a very satisfactory level. Thus, it can be validated that the improved CNN presented in this paper possesses excellent diagnostic performance.  
Compared to directly using machine learning models (such as SVM) without adopting a feature extraction algorithm, the diagnostic accuracy was below 50%. The reason is that the dataset used in this study is high-dimensional. CNNs excel at feature extraction, whereas SVM might require complex computations and substantial memory for high-dimensional spaces, which does not adapt well to extensive computations.  
In the SDK, the computation time for the fully connected layer is obtained through a time acquisition function, yielding the total running time of the CNN with FPGA acceleration. This time is then compared with the CNN running solely on the ARM side. As shown in the in Table 7, the results averaged over multiple experiments indicate that with FPGA hardware acceleration, the ARM's completion time is improved by 2.1 times compared to the non-hardware-accelerated scenario. This demonstrates that hardware acceleration can indeed reduce running time while maintaining accuracy.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Optimization Algorithm** & **CNN Accuracy** & **SVN Accuracy** & **Sample Quantity** \\ \hline G1 & 0.8182 & 0.3636 & 440 \\ G2 & 0.9091 & 0.6455 & 440 \\ G3 & 1.0000 & 0.5455 & 440 \\ G4 & 0.8341 & 0.2727 & 440 \\ G5 & 0.9591 & 0.3636 & 440 \\ AVG/Tot & 0.9041 & 0.4381 & 2200 \\ \hline \hline \end{tabular}
\end{table}
Table 6: Comparative accuracy of CNN and SVN algorithms across different fault conditions.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Structure** & \
\begin{tabular}{c} **Before Optimization** \\ **(Clock Cycles)** \\ \end{tabular} &
\begin{tabular}{c} **After Optimization** \\ **(Clock Cycles)** \\ \end{tabular} & **Improvement (\%)** \\ \hline convolutional & 120,566 & 4630 & 96.15 \\ pooling & 15,831 & 144 & 99.26 \\ fully connected & 48,402 & 356 & 99.09 \\ \hline \hline \end{tabular}
\end{table}
Table 4: Performance improvement in convolutional neural network layers before and after optimization.  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Platform** & **Recognition Accuracy (\%)** & **Run Time (ms)** \\ \hline ARM & 91.15 & 42.30 \\ FPGA + ARM & 90.12 & 20.67 \\ \hline \hline \end{tabular}
\end{table}
Table 7: CNN running time on ARM and FPGA + ARM platforms.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Structure** & \begin{tabular}{c} **DSP48E** \\ **Utilization (\%)** \\ \end{tabular} & \
\begin{tabular}{c} **FF** \\ **Utilization (\%)** \\ \end{tabular} &
\begin{tabular}{c} **LUT** \\ **Utilization (\%)** \\ \end{tabular} \\ \hline convolutional & 83 & 14 & 35 \\ pooling & 0 & 4 & 22 \\ fully connected & 5 & 1 & 3 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Resource utilization of FPGA logic in convolutional neural network layers on ZYNQ.