###### Abstract  
A multi-modulus architecture based on the radix-8 Booth encoding of a modulo (\(2^{n}-1\)) multiplier, a modulo (\(2^{n}\)) multiplier, and a modulo (\(2^{n}+1\)) multiplier is proposed in this paper. It uses the original single circuit and shares many common circuit characteristics with a small extra circuit to carry out multi-modulus operations. Compared with a previous radix-4 study, the radix-8 architecture can increase the modulation multiplication encoding selection from three codes to four codes. This reduces the use of partial products from \(\lfloor n/2\rfloor\) to \(\lfloor n/3\rfloor+1\), but it increases the operation complexity for multiplication by three circuits. A hard multiple generator (HMG) is used to address this problem. Two judgment signals in the multi-modulus circuit can be used to perform three operations of the modulo (\(2^{n}-1\)) multiplier, modulo (\(2^{n}\)) multiplier, and modulo (\(2^{n}+1\)) multiplier at the same time. The weighted representation is used to reduce the number of partial products. Compared with previously reported methods in the literature, the proposed approach can achieve better performance by being more area-efficient, being faster, consuming low power, and having a lower area-delay product (ADP) and power-delay product (PDP). With the multi-modulus HMG, the proposed modified architecture can save 34.48-55.23% of hardware area. Compared with previous studies on the multi-modulus multiplier, the proposed architecture can save 22.78-35.46%, 4.12-11.15%, 12.59-24.73%, 27.88-38.88%, and 20.49-27.85% of hardware area, delay time, dissipation power, ADP, and PDP, respectively. Xilinx field programmable gate array (FPGA) Vivado 2019.2 tools and the Verilog hardware description language are used for synthesis and implementation. The Xilinx Artix-7 XC/A3 ST-CSG324-1 chipset is adopted to evaluate the performance. s 2024 13 311 10.10000 10000 00000 000000 000000 0000000 0000000 00000000 0000000000 000000000000000000  
The traditional modified Booth-encoded multiplier is also called a radix-4 Booth-encoded multiplier [20; 25; 26], which uses a three-code interpretation. A 0 is added after the least significant bit (LSB), and a 0 is also added in front of the most significant bit (MSB) of the multiplier, which then encodes it in groups of three bits, so that only \(\lfloor n/2\rfloor\) are needed for partial products with \(n\) bits. This leads to a reduction in the use of full adders and greatly reduces the circuit area and delay time. Compared with the previous radix-4 research, the radix-8 [20; 22; 23; 24] architecture can increase the modulation multiplication encoding selection from a three-code to a four-code interpretation, which reduces the use of partial products from \(\lfloor n/2\rfloor\) to \(\lfloor n/3\rfloor+1\). As the three-code interpretation (radix-4 multiplier) increases to a four-code interpretation (radix-8 multiplier), the partial product is reduced from half of the traditional multiplier to one-third, which further improves the circuit area and delay time. The radix-4-based multiplicand in the three-code interpretation is only multiplication by 1 (\(\times 1\)) and multiplication by 2 (\(\times 2\)). Through the carry-free principle in the RNS, the multiplication by 2 (\(\times 2\)) multiplicand only needs to return the original multiplicand once (shift left by one bit). However, for the radix-8 multiplier, there will be an additional multiplication by 3 (\(\times 3\)) and multiplication by 4 (\(\times 4\)) operations to be processed. The multiplication by 4 (\(\times 4\)) operation can use the same carry-free principle in the RNS to return twice (shift left by 2 bits). However, multiplication by 3 (\(\times 3\)), which is processed by the hard multiple generator (HMG), needs to be obtained by adding multiplication by 1 (\(\times 1\)) and multiplication by 2 (\(\times 2\)) of the original multiplicand. This increases the cost of the hardware area, delay, and power consumption.