# Adaptive Regression Prefetching Algorithm by Using Big Data Application Characteristics
## 4 Evaluations
### Performance Evaluation
#### 4.3.1 Optimal Size of Hybrid Main Memory  
This section provides a comprehensive analysis and comparison of the performance of our proposed prefetching model with traditional model and other state-of-the-art prefetching models in the context of hybrid main memory. The main objective is to assess and evaluate the effectiveness and efficiency of our proposed prefetching methods and to demonstrate their superiority over existing models.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameter** & **DRAM** & **PCM** & **HDD** \\ \hline Write latency & 20–50 ns & 1 ns & 5 ms \\ \hline Read latency & 20–50 ns & 50 ns & 5 ms \\ \hline Write energy & 1.2 J/GB & 6 J/GB & 65 J/GB \\ \hline Read energy & 0.8 J/GB & 1 J/GB & 65 J/GB \\ \hline Idle power & 100 mW/GB & 1 mW/GB & 10 W/TB \\ \hline Density & 1\(\times\) & 4\(\times\) & N/A \\ \hline Cost & 4\(\times\) & 1\(\times\) & N/A \\ \hline \hline \end{tabular}
\end{table}
Table 4: Simulation Parameters.  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Processor** & **Quad-Cores, 4 GHz** \\ \hline L1 Instruction Cache (per core, private) & 32 KB, 8-way set associativity, 64-byte cache line size, \\  & LRU replacement \\ \hline L1 Data Cache (per core, private) & 32 KB, 8-way set associativity, 64-byte cache line size, \\  & LRU replacement \\ \hline L2 Unified Cache (per core, private) & 256 KB, 4-way set associativity, 64-byte cache line \\  & size, LRU replacement \\ \hline L3 Cache (LLC) (per processor, shared) & 8 MB, 16-way set associativity, 64-byte cache line \\  & size, LRU replacement \\ \hline DRAM Buffer & 16 MB, fully associative, 4 KB page size (managed \\  & page-granularity), LRU replacement \\ \hline DRAM & 128 MB, fully associative, 4 KB page size (managed \\  & as pagegranularity), LRU replacement \\ \hline PCM & 2 GB, fully associative, 4 KB page size (managed \\  & page-granularity), LRU replacement \\ \hline \hline \end{tabular}
\end{table}
Table 3: Graph Processing Workloads.  
To obtain the optimal size of the mixed main memory, a scalability evaluation was performed. Four different sizes of DRAM (64, 128, 256, and 512 MB) and four different sizes of PCM (1, 2, 3, and 4 GB) were mixed and evaluated, but the size of the prefetch buffer was fixed as 15 MB.  
Figure 7 displays the results of our evaluation regarding the execution times for different configurations of DRAM and PCM sizes. As the size of the PCM and ratio to DRAM buffer increases, the execution time decreases. Nonetheless, when the capacity of the PCM was changed from 1 to 2 GB, it showed the largest reduction in execution time compared to other hybrid main memory configurations. When holding the PCM capacity constant, the execution time exhibited a decrease with increasing DRAM size. However, as the capacity increases, the execution time reduction rate of the DRAM is significantly lower than that of the PCM. Therefore, according to the change in the PCM capacity, the execution time showed the greatest reduction rate.  
The 2 GB PCM capacity of the recommended model with the largest reduction in execution time rate was selected. In the above experiment, considering the cost of DRAM (4\(\times\)) compared with PCM and the ratio of DRAM size to PCM size, the 128 MB DRAM capacity of the recommended model was selected. Therefore, the capacity of the 128 MB DRAM and 2 GB PCM was finally selected as the optimal mixed main memory size for the performance evaluation of the proposed model.