# A 5 Gb/s Optoelectronic Receiver IC in 180 nm CMOS for Short-Distance Optical Interconnects
## 1 Introduction  
The growing demand for high-speed, energy-efficient data communication has led to significant advancements in CMOS-based optoelectronic receivers, particularly targeting short-distance optical interconnect applications [1]. These interconnects, which leverage the advantages of optical signaling--such as wide bandwidth and low latency--are increasingly being deployed in environments requiring high data throughput and reliability, including data centers, high-performance computing (HPC) clusters, and server farms [2, 3]. Compared to traditional electrical links, optical interconnects offer superior scalability in terms of bandwidth density and energy efficiency, which are essential for meeting the demands of next-generation computing workloads.  
Recent research efforts have focused on integrating photodetectors with an analog front-end circuitry in a single CMOS chip to enhance bandwidth and reduce power consumption simultaneously [4, 5, 6, 7]. These monolithic solutions eliminate the need for discrete optical components and reduce the parasitic effects introduced by the unavoidable interconnect and packaging, thereby enabling compact, cost-effective implementations. Particularly, co-design strategies involving on-chip photodetectors and equalization circuits such as CTLEs have demonstrated promise in extending the data rate while maintaining low power budgets [8]. However, realizing such designs in a standard CMOS process without compromising noise performance, signal integrity, and linearity poses severe circuit-level challenges.  
In this paper, we propose a novel optoelectronic receiver architecture optimized for short-range optical interconnects, called 'CMOS-based optoelectronic receiver integrated circuit (CORIC)', which comprises an on-chip avalanche photodiode (APD), a cross-coupled differential transimpedance amplifier (CCD-TIA), a 3-bit programmable continuous-time linear equalizer (CTLE), and an \(f_{T}\)-doubler, as shown in Figure 1. In particular, the CCD-TIA employs cross-coupled active loads that enhance the gain and stabilize the output swing while providing low input-referred noise and efficient current-to-voltage conversion [9]. The CTLE dynamically compensates for the channel-induced frequency-dependent losses by adaptively tuning its resistance (Rs) and capacitance (Cs), thereby preserving the signal fidelity across varying operating conditions. In addition, the \(f_{T}\)-doubler serves as a high-bandwidth output buffer (OB), hence boosting the circuit's overall drive capability for subsequent digital processing blocks.  
Conventional optical receivers mostly rely on external photodiodes--either p-i-n photodiodes or APDs--which necessitate off-chip interconnects using bond wires and include integrated electrostatic discharge (ESD) protection circuits. However, these external components introduce significant parasitic inductance and capacitance, which not only restrict the achievable bandwidth, but also degrade the overall signal-to-noise ratio (SNR) and thus increase jitter. Moreover, the use of discrete APDs significantly raises the packaging complexity and cost especially for multi-channel optical array systems where high integration density is critical. To alleviate these limitations, this work integrates on-chip APDs in a standard 180 nm CMOS platform, hence eliminating the need for external optical detectors and their associated parasitic elements. This monolithic integration strategy simplifies the receiver architecture, and also enhances the performance metrics such as bandwidth, noise efficiency, and cost per channel, making it highly suitable for scalable optical interconnect solutions.