# Soft Error-Tolerant and Highly Stable Low-Power SRAM for Satellite Applications
###### Abstract  
As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. This has led to a reduction in the critical charge of sensitive nodes, making the SRAM cells more susceptible to soft errors. When high-energy particles in space strike the sensitive nodes of an SRAM cell, a single-event upset (SEU) can occur, altering the stored data. Additionally, the charge-sharing effect between transistors can cause single-event multi-node upsets (SEMNUs). To address these challenges, this paper proposes a radiation-hardened 16T SRAM cell optimized for stability and power, referred to as RHSP16T. The performance of the proposed RHSP16T cell was compared with other radiation-hardened SRAM cells, including QUC-CE12T, WE-QUATRO, RHBD10T, RHD12T, and RSP14T. Simulation results indicate that the proposed RHSP16T cell exhibits higher read and write stability, along with lower-leakage power consumption. compared with all other cells. This demonstrates that RHSP16T ensures high reliability for stored data. Furthermore, EQM results show that the RHSP16T cell outperformed the compared designs in overall SRAM cell performance. The proposed integrated circuit was implemented in a 90 nm CMOS process and operated on 1 V supply voltage. c 2025 15 375 17 November 2024 15 December 2024 15 December 2024 15 December 2024 15 December 2025 15 December  
nodes simultaneously [4]. These phenomena can significantly reduce the reliability of the data stored in SRAM, necessitating the design of radiation-hardened SRAM cells that can withstand both SEUs and SEMNUs. Researchers have proposed various solutions to address the issues of single-event upsets (SEUs) and single-event multiple-node upsets (SEMNUs), including triple modular redundancy (TMR), error correction codes (ECCs), and radiation-hardened by design (RHBD) technologies. First, the TMR approach uses two additional redundant bit cells for a single bit cell and determines a data value through majority voting among the three cells [5]. Second, the ECC approach mitigates SEUs by utilizing encoding and decoding circuits [6]. Third, RHBD technology is a design methodology aimed at enhancing the resilience of SRAM bit cells against radiation by strengthening redundant nodes and improving the feedback mechanisms between the nodes [7]. However, TMR requires the inclusion of two additional redundant cells per SRAM bit cell, and ECCs necessitate supplementary circuits based on error detection codes. These requirements result in relatively larger area and power penalties compared to RHBD methods, rendering TMR and ECCs less suitable for space applications [8; 9]. Therefore, RHBD technology is considered a more appropriate approach for designing radiation-hardened SRAM cells. With the advantages of RHBD technology, over the years, researchers have developed various SRAM cells that can recover from soft errors [9; 10; 11; 12; 13; 14]. However, the previously proposed cells will only provide partial immunity against soft errors, exhibit poor read or write stability, or suffer from high power consumption. For instance, the QUATRO10T cell proposed in [9] can recover from an SEU during a transition from '1' to '0'. However, it cannot recover from an SEU during a transition from '0' to '1' and has demonstrated high write failure rates. The WE-QUATRO cell, proposed in [10], is an improved version of QUATRO10T and has shown better write performance. Nevertheless, it still cannot recover from SEU during a transition from '0' to '1' and suffers from poor read stability. The QUCCE12T cell proposed in [11] demonstrated recovery capabilities against SEUs but could not recover from SEMNUs and exhibited poor read stability. Similarly, the RHBD10T cell proposed in [12] improved read and write delay characteristics but lacked recovery capabilities against SEMNUs. In [13], the RHD12T cell, which can recover from SEMNUs, was proposed,. However, it failed to recover from an SEU during a transition from '0' to '1' and suffered from poor read stability.