# A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation
## 2 System Requirement
### System Architecture  
The transceiver architecture of the proposed system is shown in Figure 3[15]. It is a super-heterodyne transceiver with two stages of frequency conversion. The sufficiently high intermediate frequency (IF) helps the low-noise amplifier (LNA) and power amplifier (PA) to suppress the image components by their bandwidth characteristics. This architecture also requires only one phase-locked loop (PLL) synthesizer to complete all frequency conversions and achieve low power consumption.  
In the receiver chain, a sub-harmonic mixer is used as the first stage of the down-conversion mixer. The input signal is mixed with a local oscillator at 4/5 of the RF frequency to generate the down-converted IF signal to 1/5 of the RF frequency. The second stage is a quadrature I/Q mixer to further down-convert the IF signal to the quadrature baseband. A 90\({}^{\circ}\) hybrid is utilized to generate the orthogonal LO signal. Finally, the I/Q mixer's output passes through a low-pass filter and a dB-linear digital variable-gain amplifier (DVGA) before passing through the digital baseband for further processing. The amplitude imbalance can be compensated by fine-tuning the gain of the baseband DVGA, and the matched hybrid minimizes the phase imbalance across the frequency bands of interest. The overall variable gain in the receiver chain is from 23 dB to 58 dB. The saturation output power of the baseband DVGA in the receiver chain is \(-\)16 dBm for both the I and Q paths. The input power range for the receiver should be chosen between \(-\)74 dBm and \(-\)39 dBm.  
The transmitter chain of the proposed system is an inverse frequency conversion scheme as the receiver. It shares the same LO sources as the receiver from the on-chip PLL synthesizer. The input baseband signal should be less than \(-\)16 dBm, and the baseband DVGA may attenuate or amplify the baseband input for the quadrature mixer. A programmable IF amplifier (IFA) amplifies the IF signal in the transmitter chain. This IFA provides a gain of 5 dB to 20 dB with good linearity for a wideband modulated signal with  
Figure 3: A block diagram of the proposed transceiver SoC.  
a 3 dB bandwidth up to 7 GHz. The transmitter is suitable for a variable power range, with good linear modulation performance.  
The transceiver frequency synthesizer can generate frequencies from 22.5 GHz to 26.2 GHz, with a 400 Hz frequency resolution step size. This corresponds to LO frequencies from 56.25 GHz to 65.5 GHz, to fully cover all four channels in the 802.11 ad wireless standard. A 108 MHz crystal is selected as an external reference for the PLL. The divider chain in the PLL can be operated in the integer mode for better phase noise. The PLL employs a fractional frequency divider chain and can also support other reference frequencies between 33 MHz and 40 MHz or 100 MHz and 120 MHz [15]. To provide the mode switch between the different operation types, the LO network with a high-efficiency switch supports the LO power distribution to the transmitter chain, receiver chain, or both. In the FDD and FD operation modes, the LO power feed to the transmitter chain drops by half compared to the HD mode, and the output power of the transmitter drops at the same time.