# Research on Clock Synchronization of Data Acquisition Based on NoC
## 1 Introduction  
The development of data acquisition techniques shows a trend towards high sampling rates and high resolution, which gives rise to time-interleaved analog-digital converters (TI-ADCs) [1, 2]. TI-ADCs can break the limitations of the ADC sampling rate and resolution caused by semiconductor process technology [3, 4]. TI-ADCs use many ADCs with the same parameters to implement parallel data acquisition, and thus, can improve the sampling rate while preserving the resolution. However, the traditional system-on-chip-based (SoC-based) TI-ADCs rely on a bus architecture, and thus, have various limitations on communication bandwidth, clock synchronization, and scalability, etc. [5]. Such problems can be solved by incorporating the network-on-chip (NoC) technology into TI-ADCs [6], so that the sampling rate can be further improved [7].  
To ensure data correctness, the clock phases of adjacent TI-ADCs' sampling channels should be strictly synchronized [8, 9]. Higher sampling rates call for higher synchronization accuracy and lower phase errors between the sampling clocks. Since NoC-based high-speed data acquisition takes the router clock as the ADC sampling clock, high-precision synchronization of ADC sampling clocks can be achieved as long as the router clocks are precisely synchronized [7].  
(BETS) algorithm was introduced in [14], which uses synchronization error compensation to reduce message interaction in clock synchronization and satisfies the resource constraints of wireless sensor networks. A distributed clock synchronization protocol based on an intelligent clustering algorithm was presented in [15], which allocates different synchronization frequencies according to the established cluster, in order to avoid excessive network access contention. This protocol also uses outlier detection and a second-order regression model to predict potential malicious nodes. Its superiority over other synchronization protocols was proven by simulations on synchronization performance and fault node detection. In [16], with the basic WR network structure of single principal and single subordinate, the test synchronization accuracy could be limited within 200 ps, and even as low as 21 ps.  
According to the characteristics of NoC, the improvement in the White Rabbit clock synchronization protocol is applied to the ADC sampling clock synchronization to solve the NoC data acquisition sampling clock synchronization problem. The simulation results show that the mean absolute error of the time-interleaved sampling clock is less than 20 ps. Our main contributions are as follows:  
* Based on the NoC, it has the characteristics of multi-task parallel communication such as multi-resource nodes and multi-routes. In this paper, we propose a high-sampling-rate data acquisition scheme in an NoC system by using multiple low-sampling-rate ADC chips after time interweaving.
* The multiple clock domains of NoC need to processes clock synchronization. We improve the White Rabbit clock synchronization protocol and improve the synchronization precision of the time-interleaved channel sampling clock as well as guaranteeing the performance of high-speed data acquisition. The mean absolute error of the time-interleaved sampling clock is less than 20 ps.
* We improve the PTP protocol to determine the offset of the master clock and slave clock and realize coarse synchronization of the master clock and slave clock. DDMTD is designed to determine the phase of the master-slave clock. According to the phase value of PLL IP in the Xilinx FPGA dynamic phase shift, the phases of the master clock and slave clock are corrected to achieve their precise synchronization.  
The organization of this paper is as follows: Section 2 presents NoC data acquisition and the principles of White Rabbit. Section 3 provides the proposed clock synchronization scheme. In Section 4, the implementation of the clock synchronization is presented. Section 5 presents verification of the clock synchronization of the NoC data acquisition. Section 6 presents concluding remarks.