## 4 Simulation and Discussion  
The proposed **MDCIM** macro model is described using Verilog-A language while large amount of test data was used to simulate and validate the functions designed in the model. FP64 can be converted to the scientific notation representation of decimal numbers, with defined ranges for its exponent and mantissa. Therefore, during the process of generating random inputs, we constrain the range of the data's exponent to cover the decimal number exponent range that FP64 can represent, while the mantissa is generated using the rand function defined in the stdlib.h header file of C99. In this manner, we tested two million sets of data covering all ranges in FP64. Due to the pseudorandom distribution nature of the rand function, the random test inputs used in this study follow a normal distribution. Table 1 shows some data examples used to test the function of digital circuits. We use hexadecimal numbers starting with 0x to represent 64b operands. At the set of normalized numbers, a is 0x40454d4a9a95352a, which is approximately 42.60383922849208 in decimal representation; x is 0x40425f44 be897d13, which is approximately 36.74428540910062 in decimal representation; b is 0x408073 cc6798 cf32, which is approximately 526.4748069704276 in decimal representation; and d is 0x40a057d8496a0647, which is approximately 2091.9224351055777 in decimal representation. Tests have shown that the output of the DMCIM macro is consistent with the standard reference, with code coverage reaching 100%. In order to evaluate the model, we synthesized the **MDCIM** macro using CMOS 55 nm technology and measured the relevant parameters. At a working frequency of 150 MHz \begin{table}
\begin{tabular}{c c c c} \hline \hline  & **Input** & & **Output** \\ \hline a & x & **b** & **d** \\ \hline
0x40454d4a9a95352a & 0x4042544 be897d13 & 0x408073 cc6798 cf32 & 0x40a057d8496a0647 \\ (42.60) & (36.74) & (526.47) & (2091.92) \\ \hline
0x402b9 cf739 ee73 dd & 0x4045124e249c4939 & 0x4081a05840b08161 & 0x4091e7931 bfd1a3 \\ (13.81) & (42.14) & (564.04) & (1145.89) \\ \hline
0x4019d4b3a96752 cf & 0x404265e8 cbd197a3 & 0x407 edc24b8497093 & 0x4086 db06849 fa665 \\ (6.46) & (36.80) & (493.76) & (731.38) \\ \hline
0x4056764 ede6 dbd4 & 0x40304 aa015402a80 & 0x407726f04 de09 bc1 & 0x4040 faecacac57 ff \\ (89.86) & (20.04) & (370.43) & (217.34) \\ \hline
0x40580 ee81d903b20 & 0x40585 af4b5e96 bd3 & 0x407766118c3f187e & 0x40c30 da89 eda44c6 \\ (96.23) & (97.42) & (380.38) & (9755.32) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Some data examples used to test the function of digital circuits. Figure 8: The bit density and write times of different memory arrays. and a power supply voltage of 1.08 V, the macro's power consumption is 0.62 mW. The power efficiency of **MDCIM** can reach 26.9 GOPS/W. We also drew and measured the layout of the memory array and peripheral circuits, with an area of 51,814 \(\upmu\)m\({}^{2}\), achieving a power density of 0.322 GOPS/mm\({}^{2}\). As shown in Table 2, we compared **MDCIM** with other works supporting floating-point calculation. Ref. [24] is quite representative among them, as it designs an architecture capable of executing FP32 MAC operations. Ref. [24] also adopts the FMA computational philosophy. Initially, it performs the multiplication of the mantissas, then identifies the maximum exponent, completes the shifting for both the product and the addend, and finally carries out the accumulation uniformly. Since the mantissa of FP32 only has 23 bits, the author did not perform segmentation operations on the multiplication of mantissas, but instead allocated sufficient space for both the multiplier and adder. In order to fairly compare the energy efficiency and energy density of different works, we normalized the metrics, as shown in Table 2, to make them equivalent to the scenario of processing FP64. Upon comparison, the energy efficiency of our proposed **MDCIM** macro: 26.9 GOPS/W/FP64, has already surpassed that of a majority of studies of the same kind, including Ref.