## 3 Proposed Sensor Design Method  
Through the analyses of questions 1 and 2, we can see that the ranging deviations are related to the phase of the 10.23 MHz. Therefore, we must establish the phase relationship between \(f_{c}\) and the 10.23 MHz. A design of the phase detection and compensation sensor based a digital phase-locked loop (PLL) for ranging deviations is herein presented. According to literature [22], an \(N\) order phase-locked loop can accurately track signals, whose phases change with respect time to the power of \(N-1\) or lower. Because the 10.23 MHz phase adjustment is equivalent to the phase step excitation, the frequency adjustment is equivalent to the frequency step excitation. Therefore, a second-order phase-locked loop can accurately track the phase changes after the FPA. The system function is [22]  
\[H(z)=\frac{T_{s}\left(b_{0}z^{-1}{+}b_{1}z^{-2}\right)}{\left(1-z^{-1}\right)^ {2}+T_{s}\left(b_{0}z^{-1}{+}b_{1}z^{-2}\right)}, \tag{4}\]  
where  
\[\left\{ \begin{array}{l}b_{0}{=}2\xi\omega_{n}{+}\frac{T_{c}}{2}\omega_{n}{}^ {2},\\ b_{1}{=}-2\xi\omega_{n}{+}\frac{T_{s}}{2}\omega_{n}{}^{2}.\end{array} \right. \tag{5}\]  
Here, \(T_{s}\) is the data rate input to the loop filter, \(b_{0}\) and \(b_{1}\) are the loop filter parameters, \(\omega_{n}\) is the system natural frequency, and \(\xi\) is the damping coefficient. With the 10.23 MHz phase-locked loop, we can accurately locate the 10.23 MHz phase at the sampling time, \(t^{\prime}{}_{2}\). Assuming that the system's 1 PPS falls at the 10.23 MHz phase, \(p_{0}\) and at a phase, \(p^{\prime}{}_{0}\), after a time-frequency equipment boot. It falls at a phase, \(p_{1}\), through the ISL payload \(f_{c}\)'s sampling, and \(p_{0}\), \(p^{\prime}{}_{0}\), and \(p_{1}\) are expressed as digital phases with bit widths of \(N\). We then obtain:  
\[p_{compensate}=p_{1}-p_{0}, \tag{6}\]  
where \(p_{1}\) is  
\[p_{1}=p^{\prime}_{0}+\Delta p. \tag{7}\]  
If the 1 PPS falls in the 10.23 MHz skip area, i.e., the region of one \(f_{c}\) clock cycle (because the indefinite range of \(\Delta p\) is an \(f_{c}\) clock cycle) to the left of the \(2\pi\) (digital phase: \(2^{N}\)) phase of the 10.23 MHz, as shown in Figure 4 and if the 10.23 MHz has a phase deviation from \(f_{c}\), the phase sampled at the rising edge of \(f_{c}\) will be greater than \(2^{N}\). However, when the sum of the digital phase accumulator exceeds \(2^{N}\), it overflows and then accumulates from zero. Figure 4: Skip area of the 10.23 MHz. Therefore, if the 10.23 MHz is tracked by the PLL directly, the clock phase, \(p_{1}\), of the 10.23 MHz at the sampling time, \(t^{\prime}{}_{2}\), is  
\[ \begin{split} p_{1}&=rem\left(\frac{p^{\prime}{}_{0}+ \Delta p}{2^{N}}\right)\\ &=\left\{\begin{array}{l}p^{\prime}{}_{0}+\Delta p,\quad p^{ \prime}{}_{0}+\Delta p<2^{N},\\ p^{\prime}{}_{0}+\Delta p-2^{N},\quad p^{\prime}{}_{0}+\Delta p\geq 2^{N}. \end{array}\right.\end{split}  \tag{8}\]  
With the FPA of the 10.23 MHz, \(\Delta p\) has a phase uncertainty of \(2^{N}10.23e6/f_{c}\). According to Equation (8), when \(p^{\prime}{}_{0}+\Delta p\) is greater than \(2^{N}\), the locked phase, \(p_{1}\), output at time \(t^{\prime}{}_{2}\) will move up and down around the \(2^{N}\) phase of the 10.23 MHz. As per Equation (6), \(p_{compensate}\) will thus have a phase error of \(2^{N}\), namely, a 10.23 MHz clock period. To avoid this error, we first divide the 10.23 MHz by \(n\) to obtain a frequency, \(f_{n}\), by a direct digital synthesizer (DDS), yielding  
\[f_{n}=\frac{10.23e6}{n}. \tag{9}\]  
Thus, the phase change of the 10.23 MHz is \(n\) times the phase change of \(f_{n}\), which is,  
\[\phi_{f_{n}}=\frac{\phi_{10.23 MHz}}{n}. \tag{10}\]  
Then, we preset the initial phase, \(\phi_{0}\), between the 10.23 MHz and \(f_{n}\) by the DDS, whose activation must be triggered by the 1 PPS or any other signal directly associated with the 1 PPS.