# A Novel ASIC Implementation of Two-Dimensional Image Compression Using Improved B.G. Lee Algorithm
## 3 ASIC Implementation of 2D DCT/IDCT Based on B.G Lee DCT Algorithm
### Architectural Design for [PERSON] DCT Algorithm  
The concepts of pipelining and approximate computing are applied to enhance the data of [PERSON]'s eight-point algorithm for DCT and IDCT computations. The operations involved in each cycle are further simplified, and the performance is improved by using shift and add operations to reduce the multiplications. The eight-point DCT design utilizing the [PERSON] algorithm in conjunction with pipelining is shown in Figure 7. A pipelined method of eight stages is employed, where only a single mathematical computation is performed in each stage. Four adders and four subtractors are utilized to add and subtract the inputs x\({}_{0}\)-x\({}_{7}\) in the first stage. The signed error-tolerant adders proposed in our work in [23] execute the arithmetic operations. The results of the first stage are stored in registers. The decimal values of the cosine coefficients are converted to their hexadecimal equivalents, which are stored as constants. In the second stage, these cosine constants are used in the multiplication process using the proposed fixed-point signed multiplier. The remaining multiplications of the second stage are accomplished utilizing shift and additions. Registers are utilized to store the results. The third stage results are obtained using four addition and four subtraction operations. In the fourth stage, fixed-point signed multipliers are used to multiply the cosine constants with the subtractor results of the third stage. Alternate addition and subtraction operations are carried out in the fifth stage. The subtractor results obtained in the fifth stage are multiplied with cosine constants in the sixth stage. Four adders are used to carry out the addition operations in the seventh stage. Finally, in the eighth stage, the final DCT output is obtained by shifting the results of the seventh stage by one bit to the right to accomplish division by 2. The cosine constant factors used in Figure 7 are given in Table 1.  
The multiplication operation is carried out using the proposed signed 16-bit fixed-point multipliers that are designed using shift and add operations. The most significant 8 bits represent the integer part, and the fraction part is represented by the least significant 8 bits of the multiplier and the multiplicand. Figure 8 illustrates the design of the eight-point IDCT using the [PERSON] algorithm in conjunction with pipelining. The coefficients obtained after DCT y\({}_{0}\) to y\({}_{7}\) are used as input to the IDCT structure. The different stages transition from 1 to 8 as the reverse operation of DCT. The input data x\({}_{0}\) to x\({}_{7}\) applied to the DCT are obtained as output after IDCT. Figure 6: Transpose implementation for each 8 \(\times\) 8 image segment. The input registers \(x_{0}\) to \(x_{7}\) in Figure 7 reflect the eight-point input pixel data. Clocks from 1 to 8 indicate the eight stages of the pipelined DCT/IDCT design. Eight clock cycles are needed to compute the 1D DCT/IDCT for an 8 \(\times\) 8 image segment. The [PERSON] algorithm's DCT transformation involves four clock cycles for each row of pixels, making it idle for the next four clock cycles before taking the next pixel row. The redistribution of the input data and the incorporation of pipelining to uniformly distribute the arithmetic operations over the various stages is achieved in the proposed method. The DCT/IDCT operation is carried out for eight clock cycles by the inclusion of registers in such a way that the number of clock cycles is 1000. Figure 8: Incorporation of error-tolerant adder and fixed-point multipliers in eight-point IDCT using [PERSON] algorithm. Figure 7: Incorporation of error-tolerant adder and fixed-point multipliers in eight-point DCT using [PERSON] algorithm. only one addition or multiplication operation is included in each clock cycle. Tables 2 and 3 depict the input data flow of the [PERSON] eight-point DCT/IDCT algorithm.