## 4 Validation  
In order to support the developed analytical split DC capacitor sizing framework experimentally, grid-connected LC-filter-based, three-phase three-level T-type AC-DC converter prototype depicted in Figure 3(a) was employed. Corresponding system parameters are summarized in Table 1. The converter was run at switching/sampling frequency of 50 kHz by means of the Texas Instruments control card based on the TMS320F28335 Digital Signal Processor. During the experimental framework, the T-type AC-DC converter was fed by a DC source (generating a constant-valued DC voltage \(v_{DC}\)) while supplying a live three-phase AC grid with a set of balanced three-phase currents (cf. (1)) with controlled magnitudes and phase shifts. Figure 4: System used for methodology verification. The corresponding block diagram of the control system is shown in Figure 4b. In order to create in-phase unity-magnitude signal templates, grid voltages are sampled, Clarke-transformed into \(\alpha\beta\) domain and finally divided by grid voltage vector magnitude \(V_{M}\) (obtained using amplitude detection block AD). The resulting unity-magnitude templates are multiplied by the desired grid current magnitude \(I_{M}^{*}\) and then delayed in order to impose the desired phase shift \(\varphi\) to create \(\alpha\beta\) domain current references \(i_{a}^{*}\), \(i_{B}^{*}\). On the other hand, grid currents were sampled, Clarke-transformed into \(\alpha\beta\) domain and subtracted from \(\alpha\beta\) domain current references \(i_{a}^{*}\), \(i_{B}^{*}\). Corresponding tracking errors were then processed by PI controllers. The outputs of \(\alpha\beta\) domain PI controllers were added to normalized \(\alpha\beta\) domain voltages (created by dividing \(\alpha\beta\) domain voltages \(v_{a}\), \(v_{\beta}\) by \(0.5\,v_{\text{DC}}\)). The results were inverse-Clarke-transformed to create the first modulation signals term (at the right-hand side of (5)). Zero-sequence term \(m_{0}\) (i.e., the second term at the right-hand side of (5)) was generated by processing the difference between sampled split DC link voltages \(v_{DC1}\), \(v_{DC2}\) by a P + Notch controller employing a constant proportional gain \(K\) followed by a 150 Hz centered notch filter \(NF_{150}\) possessing unity DC gain aimed to suppress the triple-mains-frequency ripple (cf. (8)) in order to satisfy the DC-only zero sequence component constraint [35]. The experimental prototype is depicted in Figure 4c. Upon system start-up, the converter is synchronized with the AC grid and then grid-connected with zero-current reference. Then, the desired values of \(I_{M}^{*}\) and phase shift \(\varphi\) are imposed by the control system in order to bring the converter to the desired operating point. Measurements are performed when the system settles, and steady-state is attained. Considering the range of power factors (both leading and lagging) given by  
\[|PF|\geq 0.5, \tag{20}\]  
split DC link capacitances must be sized considering the lowest expected leading power factor (namely \(PF=-0.5\) or \(\varphi=60^{\circ}\), as discussed in the previous chapter and shown in Figure 3). Simultaneous solution of (15) and (18) with (9) and (10) (employing the values given in Table 1) yields the following values of split DC link voltage reference (19) and split capacitances, respectively. Corresponding graphical solution is depicted in Figure 5 for demonstration purposes. The'minimum voltage-imposed value' curve corresponds to Equation (15), while the'maximum voltage-imposed value' curve corresponds to (18). The values obtained in (20) are employed in both simulation and experimental frameworks as follows. \[C_{DC1,2}=440\;[\mu F],\;\;\;\;\;V_{DC1,2}^{*}=355[V] \tag{21}\]