# A 37-40 GHz 6-Bits Switched-Filter Phase Shifter Using 150 nm GaN HEMT
## 3 Fabrication and Measurement  
Figure 4 illustrates the input and output return loss (S11 and S22) of the fabricated STPS for various phase steps of each bit. The input return loss (S11) pertains to the input of the 11.25-degree phase shifter, while the output return loss (S22) pertains to the output of the 45-degree phase shifter. These results reveal that the return loss remains better than 10.7 dB across different phase states. Figure 5 displays the insertion loss (S21) of STPS for various phase states, including the insertion loss when delay paths from 0 to 180 degrees are added. Notably, as all phase shifters are transitioned into the delayed state, the insertion loss decreases, approaching a level closely resembling the simulation results. This behavior is primarily attributed to two factors.  
Firstly, the significant insertion loss, caused by the 90-degree and 180-degree bit bypass transistors, is a key contributor. This limitation stems from the utilization of smaller transistors in the 90-degree bit bypass circuit. Furthermore, the 180-degree bit comprises two 90-degree bits, amplifying its impact. Secondly, the modeling from the Process Design Kit (PDK) appears to have played a role. It is worth noting that we employed the transistor model provided by the PDK, initially designed up to 26.5 GHz, with discrepancies becoming more pronounced at higher frequencies. Additionally, the capacitors used in the delay circuit were based on the PDK model.  
Figure 4: Return loss of n260 phase shifter: (a) Input; (b) Output.  
Figure 3: Photomicrograph of fabricated phase shifter.  
However, the inductor, crucial for generating delay, was reasonably well-simulated through electromagnetic (EM) simulation. Moreover, since the delay circuit was constructed as an LCL network, the influence of the inductor was relatively significant. Consequently, the results obtained for the delay path closely aligned with the simulation. Figure 6a displays the measured phase response of the STPS across 64 phase steps. Figure 6b presents the simulated input 1-dB compression points for various phase steps of each bit. The simulation demonstrates an IP1 dB exceeding 10 dBm within the operating frequency band. Notably, a substantial variation in IP1 dB is observed in the 37-38 GHz. Figure 7a reveals that the measured and calculated RMS gain error falls within the range of 1.69 to 3.21 dB. Notably, it becomes evident that the variation in insertion loss is more significant at 37 GHz compared to 40 GHz, depending on the phase state. In Figure 7b, it is evident that the RMS phase error for the measured STPS is limited to less than 5.36\({}^{\circ}\). Analyzing Figure 6a, it becomes apparent that each phase aligns after 38 GHz within the operating band. However, a notable observation is the non-constant phase spacing at 37 GHz. Considering the results presented in Figures 5-7, it suggests that the fabricated phase shifter shifted to a higher frequency band than initially targeted.  
Figure 5: Insertion loss due to delay.  
Figure 6: (a) Measured phase response; (b) Simulated P1 dB of n260 phase shifter.