## 3 Results
### Devices Featuring Ni-ALD Dielectric-Ni Junctions
#### 3.2.1 SET Devices with Ni-SiO\({}_{2}\)-Ni Tunnel Junctions  
As discussed above, two issues must be addressed in order to successfully fabricate MIM SETs using an ALD process: the unavoidable oxidation of metals and determination of the appropriate number of cycles to form a pinhole-free tunnel barrier with desired transparency (\(R_{Q}<R_{f}<10^{4}\)\(R_{Q}\)). For that purpose two types of test structures were fabricated on an oxidized Si wafer: (1) single layer nanowires covered with PEALD SiO\({}_{2}\); and (2) liftoff-based cross-tie devices made of Ni-SiO\({}_{2}\)-Ni tunnel junctions (as described earlier). The PEALD of SiO\({}_{2}\) was performed using Bis(diethylamino)silane and oxygen plasma with a nominal growth rate of 0.09 nm/cycle. For cross-tie devices, reference structures (\"metal short circuits\") with no PEALD dielectric and without any associated oxygen plasma exposure were first fabricated and exhibited conductance of \(G\approx 400\) uS, which is comparable with the conductance of a Ni nanowire with similar dimensions. However, devices with only two cycles of SiO\({}_{2}\) PEALD (\(\approx\)0.2 nm) displayed a conductance below \(G\approx 5\) nS. This value is about four orders of magnitude smaller than the expected value \(G\approx 50\) uS based on the Simmons approximation for 0.2 nm of uniform SiO\({}_{2}\)[31]. Furthermore, at low temperatures, strong suppression of conductance at \(V_{ds}=0\) mV along with a significant decrease of conductance over a broad range of \(V_{ds}\) was observed (Figure 8), which contradicts orthodox Coulomb blockade theory for MIM SETs [16]. This behavior is, as it was in the case of Pt-Al\({}_{2}\)O\({}_{3}\)-Pt devices, consistent with a parasitic NiO layer (or a granular metal NiO-Ni mix; we will refer to it as NiO for short) in series with the tunnel junctions (i.e., [Ni-NiO]-SiO\({}_{2}\)-[NiO-Ni] instead of Ni-SiO\({}_{2}\)-Ni), as it modifies the overall barrier for electron transport and leads to a thermal activation of conductance at low bias [5]. The oxygen plasma step in PEALD has been previously reported to oxidize the surface of the substrates [32; 33; 34]. Measurements of the decrease in conductance in single layer nanowires after being covered with 10 cycles of PEALD SiO\({}_{2}\) (\(\sim\)0.9 nm) indicate that the NiO layer is about 2 nm thick. Fortunately, NiO can be reduced to Ni by annealing in hydrogen at moderately high temperatures \(\geq\)300 \({}^{\circ}\)C [35; 36; 37]. We have found that a forming gas anneal (FGA) at 400 \({}^{\circ}\)C for 2 min in 5% H\({}_{2}\)-95% Ar causes the conductance of the cross-tie structures with two cycles of PEALD SiO\({}_{2}\) to increase from \(G\approx 5\) nS to \(G>600\) uS [11], while a 30 min FGA is required to increase the conductance of the Ni nanowire covered by \(\sim\)1 nm of SiO\({}_{2}\) back to that of the as-deposited nanowires [11; 38]. This is consistent with hydrogen-promoted reduction of the parasitic NiO to Ni: H\({}_{2}\) + NiO = H\({}_{2}\)O + Ni; the H\({}_{2}\)O is removed during annealing [11; 38]. Further measurements of cross-tie devices by TEM and EDX revealed that in addition to the oxide formation on the bottom Ni layer, the top Ni electrodes, deposited on the PEALD SiO\({}_{2}\), are likewise oxidized and that a second annealing step is required to reduce the parasitic NiO at the lower interface of the top Ni layer [11]. Based upon our observations, all cross-tie devices with less than 12 cycles of SiO\({}_{2}\) (<1.1 nm) subjected to two FGA steps ((1) for bottom electrode NiO reduction: 30 min, 400 \({}^{\circ}\)C and (2) for top electrode NiO reduction: 10 min, 300 \({}^{\circ}\)C both in 5% H\({}_{2}\)-95% Ar) exhibited fairly high conductance, \(G>50\) uS \(>1/R_{Q}\). This is most likely due to non-uniformities in the deposited SiO\({}_{2}\), which lead to \"pinholes\" short-circuiting the top and bottom Ni electrodes [39].