# Bluetooth Communication Leveraging Ultra-Low Power Radio Design
## 3 BLE Radio Design Trends and Considerations
### Receiver Design Trends
This results in higher power consumption for demodulation. On the other hand, simple modulation schemes like OOK and FSK are suitable for ultra-low power designs. All sub-\(\upmu\)W receivers utilize non-coherent modulation schemes. Additionally, simple modulation combined with low data rate allows the implementation of bit-level duty-cycling to further reduce the power consumption as reported in [26]. Thus, decent sensitivity levels at low average power consumption can be achieved at the expense of the data rate. Fully-compliant BLE receivers tend to consume several mWs of power. This is expected due to the stringent requirements on sensitivity at high data rates, adjacent channel interference rejection, GFSK modulation error and center frequency deviation. To achieve these specifications, power-hungry circuit blocks as high-gain LNAs, high-selectivity active filters, high-performance PLLs and accurate and fast-startup reference oscillators are required. The survey also provides a holistic overview of the common receiver architectures and circuit techniques followed in ULP radio design as summarized in Figure 7. Since the power consumption scales with frequency, RF gain and selectivity consume a large portion of the receiver power profile. Since RF power consumption dominates the power budget, employing passive RF front-ends significantly decreases the overall RX's power consumption. In sub-\(\upmu\)W receivers, RF envelope detectors (ED), e.g., diodes, preceded by high-Q transformers are commonly used with moderate sensitivity performance [20]. In such architectures, the interference rejection techniques are mostly focused on continuous wave tones which are not an accurate assumption since wireless communication is packetized, resulting in discontinuous interference. In addition, many modulation formats result in amplitude variation making those techniques inefficient in real-world scenariosdue to multipath fading. ED-based receivers are adequate mainly at low frequency ranges because of their large parasitic capacitors [27]. Mixer-first receivers are another attractive solution to avoid power-hungry active RF gain [28; 29; 30; 31; 32; 33]. Passive N-path mixers are utilized as a first stage and are matched to the antenna. However, mixer-first architectures exhibit higher noise figure compared to LNA-first receivers, limiting their sensitivity. Nevertheless, mixer-first architectures can still achieve decent sensitivity levels through passive gain provided by matching networks in sub-mW receivers [34]. In such architectures, the major part of power is consumed by the LO generation and buffers used to drive the mixer switches. Different techniques are proposed to decrease the power of LC-based LO generation including utilizing high-Q low profile off-chip inductors which can be integrated with the radio in the same package. This solution results in a 75% power saving compared to on-chip LC oscillators at the expense of integration level [35]. Alternatively, ring-oscillators (RO) can be exploited for low-power LO generation especially in advanced CMOS nodes. The main challenge becomes improving the frequency stability and phase noise performance of the RO to avoid the degradation in the sensitivity and/or selectivity of the receiver [16]. Figure 7: Common architectures of low power receivers: (**a**) energy-detector first; (**b**) energy-detector + LNA first; (**c**) mixer-first without PLL; (**d**) LNA-first architectures. Table 1 summarizes the trade-off between power and other performance metrics in BLE receivers. The table shows the performance of back-channel BLE receivers in comparison with fully-compliant BLE receivers [36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47].