# EXPRESS: Exploiting Energy-Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage
## 2 Background  
### Fundamentals of 3D NAND Array  
Traditional 2D NAND flash technology reached its fundamental scaling limits around 2015. In response, the flash memory industry has transitioned to 3D NAND flash memory \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Proposed Methods** & **Energy Saved [\%]** & \begin{tabular}{c} **Bit Error Rate** \\ **Range [\%]** \\ \end{tabular} & **Methodology** & \
\begin{tabular}{c} **Layer Variation** \\ **Consideration** \\ \end{tabular} &
\begin{tabular}{c} **Applicable to** \\ **COTS Chips** \\ \end{tabular} \\ \hline Half-wits & \textless{}34 & 5 to 11 & Experiment & \(\times\) & \(\times\) \\ \hline Dynamic scaling & \textless{}45 & 2 to 19 & Experiment & \(\times\) & \(\times\) \\ \hline Data encoding & \textless{}33 & Not reported & Simulation & \(\times\) & \(\times\) \\ \hline Approximate Storage & \textless{}40 & 2 to 4 & Simulation & \(\times\) & \(\times\) \\ \hline EXPRESS & \textless{}52 & \textless{}1\% & Experiment & \(\surd\) & \(\surd\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Comparison of EXPRESS method with existing works. technology. Continual advances in this technology have resulted in several generations of 3D flash memory chips, each featuring an increasing number of stacked layers, from early 32-layer to contemporary 128-layer designs. These advances promise to extend the incredible growth of the bit density over the next decade [21; 22; 23]. Figure 1a shows the device structure of a 3D NAND flash memory cell. It is essentially a floating-gate metal oxide semiconductor field effect transistor (MOSFET), with a gate-all-around cylindrical channel structure. In several 3D NAND flash memory implementations, the floating-gate (FG) layer, made of conductive polysilicon, is replaced with a charge-trap (CT) nitride layer, which acts as an insulator. The FG/CT layer is electrically insulated from the transistor's terminals by the channel and gate oxide layers, and it can trap the charge, thereby holding information even when the power is turned off. The trapped negative charge on the FG/CT effectively increases the transistor's threshold voltage (\(V_{t}\)), relative to the case when there is no charge trapped. Thus, a flash memory cell stores information in the form of charges (electrons). The cell is in a programmed state (logic '0') if there are enough electrons on the FG/CT so that \(V_{t}>V_{REF}\) (the transistor is off), whereas it is in an erased state (logic '1') if there are no electrons on the FG/CT so that \(V_{t}<V_{REF}\) (the transistor is on). To change the state of a cell, two operations are performed: program and erase. These operations require high voltages on the transistor terminals and are conducted through the oxides via the Fowler-Nordheim (FN) tunneling mechanism. The program operation charges the FG/CT with electrons, whereas the erase operation removes the charges from the FG/CT. An erase operation has to be performed to change the state of the flash memory cells from the programmed state to the erased state. The program and erase operations wear out the oxide layers, thus limiting the lifetime of a flash memory cell to \(\sim\)3000\(-\)100,000 program-erase cycles, depending on the type of flash memory. Figure 1b shows the physical structure of the 3D NAND flash memory array. The green layers are the word lines (WL\({}_{0}\)-WL\({}_{33}\)), and the vertical pillars are the memory holes that contain the channel of the flash memory cells. Figure 1c shows the circuit diagram of the NAND flash memory array that corresponds to a single flash memory block. Each memory block consists of a fixed number of memory pages. The cells in each memory page are electrically connected through a metal word line (WL) that acts as their control gate. Each column (or string) of cells in a block is connected to a bit line (BL). The memory _read_ and _program_ operations are performed at the page-level granularity, whereas the erase operations are performed at the block-level granularity.