# A Wideband Hybrid Envelope Tracking Supply Modulator with Slew-Rate-Enhanced Linear Amplifier
## 2 Circuit Design
### LA Design with an SRE Structure
#### 2.2.1 The Proposed SRE Circuit
Then, in the second stage of the SRE circuit shown in Figure 5b, the primary SRE currents, \(I_{SR1}\) and \(I_{SR2}\), are amplified k times by current mirrors. Subsequently, they are subtracted to yield the output SRE currents, \(I_{SRP}\) and \(I_{SRN}\), as shown in Equation (11). \[I_{SRP}=I_{SRN}=k(I_{SR1}-I_{SR2}) \tag{11}\]  
By substituting Equations (8) and (10) into Equation (11), we obtain the complete expression of the output SRE currents:  
\[I_{SRP}=I_{SRN}=\left\{ \begin{array}{l}\frac{k}{2}(\frac{1}{\sqrt{\frac{1}{ \pi_{P}C_{\text{var}}(W/L)_{1\text{IP}}}{+}}}(V_{INN}-V_{INP})+\sqrt{2I_{B2}}) ^{2},V_{INP}-V_{INN}<-V_{A}\\ \frac{2k\sqrt{2I_{B2}}}{\sqrt{\frac{1}{\pi_{P}C_{\text{var}}(W/L)_{1\text{IP} }}{+}}}(V_{INN}-V_{INP}),-V_{A}\leq V_{INP}-V_{INN}\leq V_{A}\\ -\frac{k}{2}(\frac{1}{\sqrt{\frac{1}{\pi_{P}C_{\text{var}}(W/L)_{1\text{IP} }}{+}}}(V_{INP}-V_{INN})+\sqrt{2I_{B2}})^{2},V_{INP}-V_{INN}>V_{A}\end{array} \right. \tag{12}\]  
Therefore, we can draw the corresponding curve of the output SRE currents, \(I_{SRP}\) and \(I_{SRN}\), respectively, in Figure 6b. When the slew rate of the input signal at node 1 in Figure 5 is small, the input voltage difference, \(V_{INP}-V_{INN}\), is small. From Equation (12) and Figure 6b, we notice that when \(V_{INP}-V_{INN}\) is small, which satisfies \(|V_{INP}-V_{INN}|\leq V_{A}\), the SRE currents, \(I_{SRP}\) and \(I_{SRN}\), linearly increase with \(V_{INP}-V_{INN}\). Especially when \(V_{INP}-V_{INN}=0\), we have \(I_{SRP}=I_{SRN}=0\). In this case, the SRE circuit does not modify the operating point of the remaining LA. When the slew rate of the input signal becomes large, the LA converts from the linear amplification state to the transition state, and the input voltage difference \(V_{INP}-V_{INN}\) grows, due to the difficulty of input signal tracking. The corresponding SRE currents, \(I_{SRP}\) and \(I_{SRN}\), will quadratically grow with the enlarged input voltage difference. These additionally injected SRE currents can effectively increase the slew rate of the output voltage while maintaining a low quiescent current level. Figure 6: SRE current vs. the input voltage: (**a**) primary: \(I_{SR1}\) and \(I_{SR2}\). (**b**) Output: \(I_{SRP}\) and \(I_{SRN}\). The operating conditions of the transistors and the current flow during the transition state are shown in Figure 7. When \(V_{INP}<V_{INN}\), as shown in Figure 7a, the differential pair transistor \(M_{1a}\) is turned off, and all of the tail current \(I_{B1}\) flows through transistor \(M_{1b}\). Additionally, the current \(I_{2b}\) running through transistor \(M_{2b}\) reaches its maximum value \(I_{B1}\), while transistor \(M_{2a}\) is turned off with no current passing through. The current \(I_{2b}\) is split into two parts: \(I_{2 BP}\) charges compensation capacitor \(C_{1}\), and \(I_{2 bN}\) discharges compensation capacitor \(C_{2}\). Then, the gate voltages of the push-pull output stage's transistors \(V_{GP}\) (at node 3) and \(V_{GN}\) (at node 4) increase, causing the output voltage \(V_{OUT}\) to decrease. Because the change in \(V_{OUT}\) is much greater than the changes in \(V_{GP}\) and \(V_{GN}\), the charge and discharge rates of \(C_{1}\) and \(C_{2}\) will determine the slew rate of the output voltage \(V_{OUT}\). The proposed SRE circuit injects additional nonlinear SRE currents, \(I_{SRP}\) and \(I_{SRN}\), into nodes 3 and 4, respectively, which effectively enhances the slew rate. When \(V_{INP}>V_{INN}\), as illustrated in Figure 7b, a similar situation occurs.