# An Equal Precision Programmed Cymometer Design Using Low-Power Technique
## 4 Results and Discussion
### Function Verification  
The simulation results of the FPGA circuit module of the frequency meter are shown in Figures 8-12.  
Figure 8 shows the main functions of the frequency meter. Among them, when CLRTRIG = 0, the system is cleared and set. Herein, the CNT is started when the CLRTRIG is at the rising edge, where the pulse width test count is performed until the ENDD flips to a high-level count. The selection of self-calibration and frequency measurement modes is determined by the CHOICE signal. FINPUT can be provided by CHKF or FSTD. When START = 0, the counter is closed as a preset gate. When START = 1, the preset gate is opened, and the counter begins to work. Meanwhile, when START = 1 and 0, the positive and negative pulse widths are measured separately to obtain the duty cycle. Finally, SEL reads the selected count value and controls the data entering the microcontroller for processing and display. Through the choice of working mode in Figure 8, the circuit can be flexible, switching between self-calibration and frequency modulation modes, thereby improving the circuit sensitivity. When the measured frequency meets the requirements, the self-calibration frequency is in a closed state, which is beneficial to reduce power consumption.  
Figure 9 shows the work case of the counting module. To initialize the test circuit state, a positive pulse signal is applied to the CLR end of the circuit, resulting in Q becoming low. When the CLR is recovered to a negative pulse, the Q-terminal begins to count. This process verifies the correctness of the counter circuit and meets the design requirements.  
Figure 10 calculates the pulse width by capturing the rising and falling edges of signal FIN. Similarly, a positive pulse signal is applied to the CLR end in the CONTROLL2 circuit, and then the test circuit enters the state initialization phase. After that, when the input START of the D flip-flop is set as high and the rising edge of the FIN signal is detected, the PUL side of the CONTROLL2 outputs a high level. As a result, the standard frequency signal enters the counter CNT to complete the pulse width measurement. At the same time, the ENDD is set as high to complete the pulse width measurement.  
to send the signal to the FOUT. In the case of a mismatch of the measurement frequency, the circuit stability and flexibility can be improved by real-time switching operation.  
Figure 12 shows the switching between the frequency acquisition and pulse width measurement. When the input START of the D flip-flop is set as high, FIN is turned on to transmit the signal to CLK1, and FSD is turned on to transmit the signal to CLK2 under the condition of the rising edge of FIN. After completing the above process, EEND is set to a high level as a symbol. When the input START of the D flip-flop is set as low, the data links of FIN \(\rightarrow\) CLK1 and FSD \(\rightarrow\) CLK2 are cut off under the condition of a rising edge of FIN. This process performs mode switching by configuring the high level of the START signal and tests the data link gating in time, which is helpful to verify the functional reliability of the circuit.