## 3 Proposed Communication Hardware  
### Proposed Communication Hardware Configuration  
Figure 3 shows this paper's proposal: the three-level communication hardware. Three-level communication hardware enables full-duplex communication in a two-wire communication approach. Communication transmission signals occur depending on the on/off status of switches \(Q_{1}\) and \(Q_{2}\). When both \(Q_{1}\) and \(Q_{2}\) are switched off, the output is high impedance status and cannot function at the communication line. When \(Q_{1}\) is turned on and \(Q_{2}\) is turned off, it transmits the binary serial communication value \"1\", at which point \(V_{s}\) becomes \(V_{dc}\). Conversely, when \(Q_{1}\) is turned off and \(Q_{2}\) is turned on, the serial communication binary value \"0\" is sent and \(V_{s}\) is set to zero. However, the \(V_{L}\) voltage appears in three levels by output impedance resistance and the output level of the counterpart device. Figure 4 shows the three-level communication hardware configuration for two-way communication. It is assumed that on the proposed topology, the impedance of the communication line is ignored because the output impedance is bigger than that of the communication line. The received voltages \(V_{L1}\) and \(V_{L2}\) of Module 1 and 2 are not determined by the transmit-side voltage or the receive-side voltage, but by each other's transmission-side voltage and the receive-side voltage status. In other words, if the two transmit-side voltages are equal, when the transmit voltage is detected, and if the two transmit-side voltages are different, the voltage equivalent to half of the transmit voltage is detected. Due to this logic structure, the output voltage of the receiver appears to be three levels depending on the transmission information of the transmitter and receiver.  
Therefore, the received information can be obtained by combining the receiving and transmitting information with the three-level voltage formed according to the transmission status of the transmitter and the receiving side.  
Figure 5 shows a circuit diagram for obtaining incoming information from the generated three-level voltage. As shown in the figure, the signal \(V_{HL}\) is generated first through the exclusive logic of \(V_{H}\) and \(V_{L}\). In addition, the generated \(V_{HL}\) and the transmission signal of the transmitting side module will be configured again as an exclusive logic so that the final incoming data RX can be entered.  
Figure 2: Load sharing diagram through serial communication. (**a**) Power converter configuration for load sharing; (**b**) Modbus communication cycle.  
Figure 6 shows the waveform when operating in full-duplex communication mode of Module 1 and Module 2 using the 3-level communication hardware shown in Figure 4. In order to clarify the interpretation, the two transmission signals, \(V_{s1}\) and \(V_{s2}\) are expressed as having a \(90^{\circ}\) phase difference as shown. In this case, as discussed earlier, the transmission side voltage and the receive side voltage will be displayed at different levels by the other side's information. \(V_{L1}\) generated by the transmission voltages \(V_{s1}\), \(V_{s2}\) of Module 1 and 2 is shown in Figure 6. \(V_{HL}\) signals generated through the exclusive logic of \(P_{1}\) and \(P_{2}\) signals are obtained through a photo-coupler which will be in the form of twice the transmission frequency. When the generated \(V_{HL}\) signal and the transmission signal \(V_{s1}\) of Module 1 are taken with exclusive logic, the transmission signal TX of Module 2 is finally extracted.  
Figure 4: Hardware configuration for three-level communication for bidirectional communication.  
Figure 5: Reception information extraction circuit.  
Figure 3: Proposed three-level communication hardware.