# Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology
## 1 Introduction  
Emerging spintronic devices, such as spin-valves and domain-wall magnets (DWM), have rekindled significant research interests in novel circuit and architecture design methodologies [1; 2]. Sharply deviating from CMOS device technology, spintronic devices use spin transfer torque, instead of charge, as the medium of information processing, therefore offering not only ultra-low critical current (e.g., \(\leq\)100 \(\mu\)A at 65 nm), simple switching scheme, and ultra-fast-speed, but also many fascinating probabilistic-related physical properties [3; 4; 5; 6]. In particular, as shown in Figure 1a, Magnetic Tunnel Junctions (MTJ), the cornerstone of spintronic devices, can be densely embedded into CMOS logic circuits and fabricated with extremely small footprint on top of the metal layers and occupy almost \"zero\" chip area. Therefore, a hybrid MTJ-CMOS chip is considered by many as a potentially powerful solution that brings non volatility, instant on/off, and low standby power to today's integrated circuit technology. Recently, in the arena of FPGA research, studies on exploiting Spin Transfer Torque Magnetisation (STTM) switching devices have surged. For example, newly emerging memristor devices have been investigated to replace SRAM as the storage of elements in CMOS-based FPGA [8]. More recently, the nano crossbar architecture has been touted [9; 10; 11]. as an even more superior alternative to the conventional non-volatile phase-change memory due to its high density and lower power consumption [12; 13]. Another conceptually appealing approach to directly applying MTJ-CMOS devices is to stack the programming overhead of an FPGA on top of the logic blocks and interconnect layers that would be implemented in a state-of-the-art CMOS technology. This approach resembles the monolithically stacked 3D-FPGA architecture, as depicted in Figure 1b, which achieves significant performance benefits [7; 14]. Besides the obvious benefit of higher logic density, vertical stacking with a hybrid MTJ-CMOS device can potentially reduce interconnect length, hence reducing signal path delay and power consumption and offers a possible route to closing the performance gap between FPGAs and cell-based ASICs. However, the vast majority of these studies have focused on using spintronic devices as storage elements and configuration memory bits, therefore achieving low power dissipation and high speed without making significant changes to the conventional FPGA architecture and circuit design. In this study, we attempt to directly use the inherent quantum-induced stochastic property of spintronic devices, not merely as memory storage, but for logic computation. Together with other researchers [15; 16], we strongly believe that, without more innovations in FPGA architecture, the advance in device technology alone can not fully shrink the significant performance gap between FPGA and ASIC devices. The major motivation behind our study is to solve the following two well-known FPGA architecture design challenges, which can _not_ simply be tackled by replacing conventional SRAM-based memory bits in a modern FPGA chip with the emerging spintronic devices, such as MTJs (Magnetic Tunnel Junction). The first major challenge in FPGA architecture design is to determine the granularity of logic blocks in an FPGA. All prominent FPGAs [17; 18; 19; 20] today have fixed and uniform logic granularity for each logic block. From the architecture point of view, coarse-grain blocks have much less stress on the placement and routing but often result in long internal logic delays and under-utilization for designs in small size, whereas fine-grain logic blocks can achieve shorter internal delay but often requires excessive amount of routing resource in order to successfully route a circuit.