# RT Engine: An Efficient Hardware Architecture for Ray Tracing
## 5 Conclusions  
In this article, we present an efficient ray tracing hardware architecture RT engine by analyzing relevant literature, algorithms, and RTL level implementations. We adopt three optimization strategies to improve the system efficiency for memory access, branching, and significant computation in ray tracing. Multiple stacks are used to store ray traversal information. The three-phase break method is used to perform the loop break earlier and approximate the method for the reciprocal to achieve hardware optimization and performance improvement. Based on these three optimization strategies, we use the chip agile development method to implement the RTL level, verify the accuracy of system functions and evaluate performance through simulation. We use the synthesis tool to assess the chip area. The experimental results show that the performance/area (MRPS/mm\({}^{2}\)) of our architecture is about 2.4\(\times\) higher than the best reported results of other academic research. These results indicate that our architecture can achieve efficient ray tracing.  
Writing--original draft, review and editing, R.Y.; Conceptualization, L.H.; hardware, H.G.; software, Y.L.; investigation, L.Y. and N.X.; analysis, L.S. and Y.W.; validation, M.L. All authors have read and agreed to the published version of the manuscript.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline  & **Clock Rate** & \begin{tabular}{c} **Acceleration** \\ **Structure** \\ \end{tabular} & \begin{tabular}{c} **Performance** \\ **(MRPS)** \\ \end{tabular} & \begin{tabular}{c} **Area (mm\({}^{2}\))** \\ \end{tabular} & \begin{tabular}{c} **Process (nm)** \\ **(mm\({}^{2}\))** \\ \end{tabular} & \begin{tabular}{c} **Performance/** \\ **Area (MRPS** \\ **/mm\({}^{2}\))** \\ \end{tabular} \\ \hline \begin{tabular}{c} T\&I engine \\ SIGGRAPH\({}^{1}\)11 \\ [17] \\ \end{tabular} & 500 MHz & Kd-tree & 198 & 9.04 & 65 & 21.90 \\ \hline \begin{tabular}{c} SGRT \\ SIGGRAPH\({}^{1}\)13 \\ [18] \\ \end{tabular} & 500 MHz & BVH & 184 & 7.2 & 65 & 25.56 \\ \hline \begin{tabular}{c} RayCore \\ TOG’14 [19] \\ \end{tabular} & 500 MHz & Kd-tree & 193 & 18 & 28 & 10.72 \\ \hline \begin{tabular}{c} Two-AABB \\ SIGGRAPH’14 [21] \\ \end{tabular} & 500 MHz & BVH & 297.6 & 6.82 & 28 & 43.63 \\ \hline \begin{tabular}{c} HART \\ TVCG’15 [20] \\ \end{tabular} & 500 MHz & BVH & 602 & 7.68 & 65 & 78.39 \\ \hline \begin{tabular}{c} STRaTA \\ CGF’15 [22] \\ \end{tabular} & 1 GHz & BVH & 365.6 & 57.1 & 65 & 6.40 \\ \hline \begin{tabular}{c} MBVH \\ SIGGRAPH’16 [23] \\ \end{tabular} & 500 MHz & BVH & 88 & 3.12 & 45 & 28.21 \\ \hline \
\begin{tabular}{c} Dual Streaming \\ HPC’17 [24] \\ \end{tabular} & 1 GHz & BVH & 345.6 & 57.1 & 65 & 6.05 \\ \hline
\begin{tabular}{c} Mach-RT \\ TVCG’20 [25] \\ \end{tabular} & 2 GHz & BVH & 284.25 & 52 & 65 & 5.47 \\ \hline RT engine & 850 MHz & BVH & 92.74 & 0.48 & 28 & 193.21 \\ \hline \hline \end{tabular}
\end{table}
Table 7: Performance comparison against previous approaches.  
**Funding:** This research is supported by the National Natural Science Foundation of China (No. 61872374/62102433).  
**Institutional Review Board Statement:** Not applicable.  
**Informed Consent Statement:** Not applicable.  
**Data Availability Statement:** The data that support the findings of this study are available from the corresponding author upon reasonable request.  
**Acknowledgments:** The authors would like to thank everyone who contributed to the realization of this research, either academically or through financial support.  
**Conflicts of Interest:** The authors declare no conflict of interest.