## 3 Results and Discussion
### Operation Characteristics of FE-TCMOS  
Prior to the evaluation of FE-TCMOS, the voltage transfer characteristics (VTC) of conventional TCMOS and CMOS were first verified. Figure 5a shows the VTC of TCMOS and CMOS where it can be confirmed that TCMOS is stably operated with VDD = 1 V as a ternary CMOS with the third Vout state. Then, FE-TCMOS and FE-CMOS were embodied by reflecting the calibrated ferroelectric material parameters to the gate stack. To evaluate the electrical characteristics of FE-TCMOS and FE-CMOS, a 7-stage inverter chain was configured in mixed-mode device and circuit simulations as shown in Figure 5b. The input pulse, which has the transition from 0 V to VDD (1 V) with 1 ms rising time, was applied, and the average propagation delay of Vout was extracted as the switching time from each inverter stage. Figure 5c demonstrates the switching time as a function of the number of inverter stages. It is found that the FE-TCMOS has the slower switching speed than the FE-CMOS. It has been reported that the tunneling-based TCMOS has the slower (usec order) switching speed compared to that (psec order) of the CMOS [1], because the switching delay of an inverter is proportional to the driving current of n/p-type transistors. That is, TNMOS/TPMOS not only have the low I  
Figure 4: **(a)** The transfer characteristics of conventional TNMOS/TPMOS and FE-TNMOS/TPMOS. The higher ION and the steeper SS are shown in FE-TNMOS/TPMOS. **(b)** The SS of conventional TNMOS/TPMOS and FE-TNMOS/TPMOS with respect to drain current. In the entire drain current range, FE-TNMOS/TPMOS have a lower SS. Figure 3: **(a)** The schematic diagram of tunneling layer and doping concentration in case of TNMOS. The band-to-band tunneling generation rate at tunnel junction with respect to drain voltage. The drain voltages are **(b)** 0.05, **(c)** 0.5, and **(d)** 1.0 V, respectively. The band-to-band tunneling generation rate becomes larger with the higher drain voltage. due to the high V\({}_{t}\), but 0 V to half V\({}_{DD}\) and V\({}_{DD}\) to half V\({}_{DD}\) transitions are formed by the IOFF. Considering the 250 ns ferroelectric relaxation time (namely, polarization switching time) obtained in the previous study [15], if the ferroelectric layer is introduced to the CMOS, the boosted I\({}_{ON}\) and the steeper SS cannot be achieved since the switching speed of the CMOS inverter is much faster than the polarization switching. This means that a ferroelectric material having a faster switching speed (sub-psec polarization switching) than the CMOS switching is required to apply the ferroelectric layer to conventional CMOS. In contrast, the operating speed of the tunneling-based TCMOS is slower than the polarization switching of the ferroelectric material. Therefore, the ferroelectric layer can effectively play a role as a current booster in the TCMOS. Subsequently, the switching speed is compared between FE-TCMOS and TCMOS with respect to the number of inverter stages. Figure 6a shows that the switching delay difference between them is negligible, because the switching speed is determined by the IOFF and both devices have almost the same IOFF. The static noise margin (SNM) of FE-TCMOS was investigated from the butterfly curves with various V\({}_{DD}\)s (0.5 V, 0.7 V, and 1.0 V), and the SNMs were compared with those of TCMOS. Figure 6b indicates that the FE-TCMOS has the sufficient SNM even at low V\({}_{DD}\). Additionally, Figure 6c shows the SNM comparison between FE-TCMOS and TCMOS. The improvement of the SNM is extracted as the increase of the SNM in percentage with respect to V\({}_{DD}\). It is observed that the FE-TCMOS has the larger SNM and the SNM becomes improved further at the lower V\({}_{DD}\), implying that the FE-TCMOS is more advantageous as V\({}_{DD}\) decreases. These results can be understood better by the steeper SS and the larger I\({}_{ON}\) of FE-TNMOS/TPMOS than by conventional TNMOS/TPMOS.