# Radiation Hardened Read-Stability and Speed Enhanced SRAM for Space Applications
###### Abstract  
With the advancement of CMOS technology, the susceptibility of SRAM to single node upset (SNU), double node upset (DNU), and multiple node upset (MNU) induced by radiation has increased. To address this issue, various cutting-edge solutions, such as radiation hardened sextuple cross coupled (RHSCC)-16T and DNU-completely-tolerant memory (DNUCTM) cells, have been proposed. While the RHSCC-16T cell is robust against SNU, it may be vulnerable to DNU. The DNUCTM cell is resistant to both SNU and DNU, but it remains susceptible to MNU. In this paper, we propose a radiation hardened read-stability and speed enhanced (RHRSE)-20T SRAM, which is immune to all potential cases of SNU, DNU, and MNU. Additionally, the proposed design demonstrates improvements in read and write delays compared to conventional SRAM designs. Experimental results confirm that the RHRSE-20T SRAM maintains stability under various charge levels for SEU, DNU, and MNU. The proposed integrated circuit is implemented in a 90-nm CMOS process and operates on a 1 V supply voltage, offering significant advantages for next-generation radiation-hardened memory applications. CMOS; integrated circuit; memory; radiation; static random-access memory +
Footnote †: journal: _Sci_  
0000-0001-5000-0000-0000-0000-0000-0000-0000-0000-0000-0000-0000-0000-0000-00000-0000-00000-00000-00000-00000-00000-00000-0  
Various radiation-hardened SRAM designs have been proposed to mitigate the soft error issues caused by radiation effects. For example, the We-Quatro SRAM employs additional negative feedback paths to improve the data stored in nodes affected by radiation [6]. However, this design is not fully immune to all cases of SNU and faces issues with write failures at low voltages. The radiation hardened sextuple cross coupled (RHSCC)-16T cell, which uses two storage nodes and four internal nodes, is fully immune to SNU but not entirely immune to DNU [7]. The QUCCE12T, composed of four cross-coupled input-split inverters, forms a large error-tolerant feedback loop to robustly maintain the stored value, but it also cannot withstand all cases of DNU [8]. The DNU-completely-tolerant memory (DNUCTM) design uses six access transistors, resulting in a relatively low read/write delay. Additionally, by spacing specific nodes apart in the layout, it is fully immune to DNU. However, because all nodes are sensitive, it does not fully recover from MNU despite the layout techniques [9]. The quadruple cross-coupled SRAM (QCCS) design demonstrates low read/write delays by using access transistors for both storage nodes and internal nodes, but it is not entirely immune to DNU. The sextuple cross-coupled SRAM(SCCS) can self-recover from all cases of DNU, but due to the use of many internal nodes, it is not fully immune to MNU [10]. The RSP14T improves SEU immunity and reduces leakage power but still struggles with high leakage [11]. To address SEMNU resistance, the RHD12T was proposed as a cell which can recover from SEMNU in specific internal node pairs [12]. However, it still cannot recover SEUs at nodes storing '0' and has a higher leakage power compared to other designs. In an effort to minimize SEMNU, the RHPD14T was introduced, using a polar design to make certain nodes less vulnerable to SEU [13]. Despite its improved write performance, this design has the highest leakage power and the lowest read stability among the discussed cells. In this paper, we propose the radiation hardened read-stability and speed enhanced (RHRSE)-20T design to address several challenges. The key contributions of this study are as follows. First, the proposed RHRSE-20T is resistant to various cases of single-node upsets (SNU) and, through advanced layout techniques, significantly enhances its immunity to dual-node and multi-node upsets (DNU and MNU), representing a major improvement over existing designs.