## 2 The Normal-Mode Helical Antenna Design Considerations
### LNA Design and Implementation  
The JFET (BF256B) common-drain amplifier (CDA) was utilized with a negative feedback inductor loop, serving as the initial stage of the LNA [21] and the BJT common-emitter amplifier (2N2222) as the LNA's final stage for signal amplification [22] as illustrated  
Figure 4: The measured impedance of the helical across the frequency range 20–30 MHz. Figure 3: The load mismatch attenuation of the helical antenna. in Figure 5. Internal capacitors C6, C7, and C10 are included in the schematic of Figure 5 solely for simulation purposes using Multisim 14.0 software [23]. Notably, the average gain of the cascade LNA was measured in the laboratory as \(-1\) dB at 50 \(\Omega\), accounting for the internal capacitances of both two-stage amplifiers. This negative gain ensures stability against oscillations and minimizes the Miller effect at the input and output of the final stage [24]. A \(-1.5\) dB attenuator at the output of the LNA isolates the Miller capacitance of the final stage to minimize the effect of the load impedance, particularly the phase specifications of the beamformer discussed in Section 3. The output attenuator is designed around a pi resistor network consisting of R10, R11, and R12, with an equivalent Thevenin resistance of 47 \(\Omega\). This confirms that the output impedance, calculated using the superposition theorem as the equivalent circuit of the resistor R7 parallel to capacitor C10, is approximately 50 \(\Omega\) throughout the desired operating frequency range. The importance of the initial stage of the LNA cannot be overstated, as it has a direct impact on the signal-to-noise ratio of the received signals. For instance, due to its high input impedance, the amplifier presents a minimal load to the helical antenna, consequently preventing signal attenuation at the input of the LNA. This characteristic is crucial for minimizing losses, especially when the antenna operates away from its resonant frequency, where its impedance is significantly high, as depicted in Figure 4. In contrast, incorporating a low-impedance traditional amplifier as the first stage of the LNA results in high received signal attenuation due to the potential divider between the high impedance of the helical antenna and the low impedance of the amplifier, thereby significantly degrading the signal-to-noise ratio (SNR), regardless of the gain of the subsequent stages. Hence, the detailed analysis of the JFET CDA, following its upgrade, is further discussed below. According to theory, the input impedance of a JFET common-collector linear amplifier is ideally very high (in the order of M\(\Omega\)) [25]. However, in real-world conditions, this impedance is reduced to around 300 \(\Omega\) at 25 MHz, which is relatively low due to the effect of the internal parasitic capacitances of the JFET, as shown in Figure 6. According to the superposition theorem, the gate-drain and gate-source internal capacitances of the JFET appear in parallel with the input gate resistor RG. Consequently, the input impedance of the amplifier is low at high frequencies [25]. To mitigate this, the input parasitic capacitances should be neutralized by installing a negative feedback inductor, which appears in parallel with the input of the amplifier. Figure 5: High-impedance two-stage low-noise amplifier circuit. To substantiate the aforementioned approach, the input impedance of the common-drain amplifier (CDA) was measured using a vector network analyzer (NANO VNA-F V2) without neutralizing the internal capacitance. The measured values are given in Table 1 below. According to Table 1, the input impedance of the CDA is reduced due to the internal high capacitive reactance. As can be justified from the magnitude of the input impedance of the CDA, plotted in Figure 7, the input impedance of the JFET source follower amplifier is inversely proportional to frequency due to the effect of the internal capacitive reactance, already discussed.