# A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow
## 3 A Standard-Cell-Based Amplifier Cell with Stable Voltage Gain and Well-Defined DC Output Voltage  
In this section, we introduce a novel standard-cell-based analog building block that can be easily designed to exhibit a voltage gain, approximately equal to an integer number  
Figure 1: Control loop to generate the control voltage. \(k\), which remains stable over PVT variations. Additional requirements of this basic voltage amplifier are to exhibit a well-defined output static voltage to allow easy cascadability and to provide a low output impedance. The schematic of the proposed standard-cell-based basic voltage amplifier is depicted in Figure 2 and is made up of three inverters, \(I_{0,1,2}\), implemented by a certain number of reference inverters. Symbols '1' and '\(k\)' in the left part of Figure 2 indicate the number of instances of the reference standard-cell inverter connected in parallel. In particular, the gain is set by inverter \(I_{0}\), composed of \(k\) reference inverters in parallel, and the diode-connected inverter \(I_{1}\), which is a single instance, whereas inverter \(I_{2}\) (also a single instance) is exploited to set the static output voltage through the replica-bias loop of Figure 1. The overall voltage gain \(V_{om}/V_{ip}\) of the cell is thus approximately \(-k\), hence we adopt for it the symbol in the right part of Figure 2, where the label \(-k\) indicates the voltage gain and where the pin \(Ctrl\) is the bias control input. We would like to point out that one important feature of the proposed standard-cell-based basic voltage amplifier is that its gain is set (at least as a first order approximation) by the number of reference inverters in parallel used to implement the inverter \(I_{0}\) in Figure 2, and it is therefore technology independent. The proposed basic voltage amplifier can be analyzed by referring to the small-signal equivalent circuit reported in Figure 3, where:  
\[Gm_{i}=gm_{0}; \tag{1}\]  
\[Ro_{i}=\frac{1}{gm_{2}+gds_{2}+gds_{0}+gds_{1}}; \tag{2}\]  
\[Ci_{i}=C_{gs_{0}}+C_{gd_{0}}\cdot\frac{gm_{0}}{gm_{2}}; \tag{3}\]  
\[Co_{i}=C_{gd_{0}}+C_{gd_{1}}+C_{gd_{2}} \tag{4}\]  
are the transconductance, the output resistance, the input capacitance, and the output capacitance of the amplifier, respectively. Small-signal parameters \(gm_{0,1,2}\), \(gds_{0,1,2}\), \(C_{gd_{0,1,2}}\), and \(C_{gs_{0,1,2}}\) of the inverter gates are expressed as in [52]. Figure 3: Small-signal equivalent circuit of the proposed standard-cell-based basic voltage amplifier. Figure 2: Standard-cell-based basic voltage amplifier with stable gain and well-defined static output voltage. Remembering that \(I_{0}\) is implemented as \(k\) instances in parallel in the reference inverter and \(I_{1}\) is a single instance of the reference inverter, we can write:  
\[gm_{0}=k\cdot gm_{1}\ =k\cdot gm \tag{5}\]  
\[gds_{0}=k\cdot gds_{1}=k\cdot gds; \tag{6}\]  
Figure 1.0  
Figure 1.1  
where \(gm\), \(gds\), \(C_{gs}\), and \(C_{gd}\) denote the transconductance, the output conductance, the gate-source capacitance, and the gate-drain capacitance of the reference inverter, respectively. Now, considering the small-signal equivalent circuit in Figure 3 and assuming a generic load capacitance \(C_{L_{i}}\) at the output of the amplifier, the transfer function of the proposed basic amplifier can be expressed as:  
Figure 1.2  
It has to be remarked that the proposed amplifier shows a low output impedance \(Ro_{i}\) whose value is approximately determined by \(Gm_{2}\). The voltage gain of the amplifier is given by \(Av(0)=Gm_{i}\ Ro_{i}\) and can be written as:  
Figure 1.3  
Assuming \(gm_{2}\gg gds_{2}+gds_{0}+gds_{1}\), \(|Av(0)|\) can be expressed as:  
Figure 1.4  
This condition can be considered true until \(k\) is not high enough to compromise the assumption \(gm_{2}\gg gds_{2}+gds_{0}+gds_{1}\).