## 2 Simulations Results  
In ref. [9] we have presented the circuit of Figure 1 used to perform an analysis on the failure mechanisms of GaN power HEMT in short circuit operations. The circuit consists of two GaN devices (Q1, Q2) connected in a single-leg inverter configuration. The two isolated drivers (U4, U6) allow separate switching of the two devices through the Hc and Lc signals generated by an FPGA-based control circuit. The printed circuit board was designed to minimise parasitic inductance in the power stage and gate branches to minimise drain overvoltages and gate oscillations triggered by very fast transients. The stray inductance of the drain path measured with a vector network analyser was 8 ns. With the same instrument, we also measured the stray inductance of resistive shunt that was about 3 nH. The output current was measured as the voltage drop across a shunt resistance RSH = 11 mf\(\Omega\) obtained as the parallel of three 33 mf\(\Omega\) resistors. This voltage is fed to the input of oscilloscope through the resistor R28 = 50 \(\Omega\), used to match the output impedance of the circuit with the input impedance of the cable and oscilloscope. Figure 2 shows the typical waveforms of gate voltage and drain currents obtained during a 10 us short circuit test. The tested device was a commercially available 7.5 A-650 V GaN  
Figure 1: Test circuit used for the short circuit measurements. The transient starts at about 4 us when the gate voltage V\({}_{\text{CS}}\) is raised to 6 V. The current increases up to about 30 A and subsequently decreases due to the occurrence of thermal phenomena related to strong negative temperature feedback of the DUT conductivity [8; 12]. However, the trend of the current during its fast variations can be largely altered when using the resistive shunt measurement technique due to the stray inductance which derives from the non-ideality of the resistors. This issue can be analysed by using PSpice simulator. Using the simulator allows us to evaluate the effective current in the device and to highlight the effect of the parasitic parameters on the measurement. Figure 3 shows the simulated circuit to reproduces the pulsed tests. The circuit presents two devices in series each with their own driver circuit. The devices used are two 650 V enhancement-mode GaN transistors marketed by GaNSystem. Spice models supplied by the manufacturer were used for the simulations without taking thermal effects into account. Finally, the parallel of the shunt resistors used for measuring the current has been replaced by a single resistor with a series stray inductance of 3 nH. The two 50 \(\Omega\) resistors account for the impedance matching between the test circuit and the oscilloscope. Figure 3: Test circuit to observe the pulse characteristics. Figure 2: Gate voltage (red) and drain currents were measured during the short circuit test at V\({}_{\text{CC}}\) = 200 V (green) and V\({}_{\text{CC}}\) = 50 V (blue). The circuit was used to simulate a 1-\(\upmu\)s short circuit test. In Figure 4 the waveforms of the drain voltage and drain current obtained with \(\mathrm{V_{DS}}\) = 100 V and \(\mathrm{V_{GS}}\) = 6 V are reported. In blue we report the actual current, \(\mathrm{I_{d}}\), circulating in the device. In green, the current \(\mathrm{I_{sh}}\) which would result from the measure of the voltage across the shunt resistor considering the attenuation factor is reported. As can be seen, due to the stray inductance of the resistors, the current \(\mathrm{I_{sh}}\) presents an overshoot lasting a hundred nanoseconds during which it reaches a value of almost an order of magnitude higher than the steady-state value. Since we have not considered any thermal effect, this behaviour is to be attributed exclusively to the presence of parasitic elements on the measurement circuit.