# A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs
## 5 Conclusions  
A simple yet effective self-calibration method was presented and verified through simulations and measurements. It was shown that the capacitor mismatch error can be minimized by adding a couple of switches to the conventional SCA and reusing the rest of the pipeline stages. A detailed explanation on the design of the main circuits in the MDAC was also presented. In order to minimize the finite-gain error of the op-amp, a gain-boosting amplifier was adopted in the op-amp and the detailed circuit diagram was presented. The resulting DC gain of the op-amp was more than 90 dB for all corner conditions. The settling behavior of the op-amp in the SCA was analyzed and the required time constant to achieve the target resolution was derived from the first-order approximation of the SCA transfer function. The bandwidth of the op-amp was then determined based on the analysis and optimized by using transient simulations. The effect of MOS switches on the input sampling and design of the sampling switch were also presented. A 12-bit 30 MS/s pipeline ADC comprising eight 1.5-bit stages, followed by a 4-bit flash ADC, was fabricated in a 180 nm CMOS process. After calibration, the measured DNL and INL improved from \(+0.82/-0.75\) and \(+1.12/-1.79\) to \(+0.45/-0.41\) and \(+0.47/-0.91\), respectively. Furthermore, calibration significantly improved the dynamic performance. For an input frequency of 2.09 MHz, the measured SFDR and SNDR improved from 69.3 dB and 63.9 dB to 84.1 dB and 68.9 dB, respectively, resulting in an ENOB of 11.1 bits. The ADC consumed 35 mW from an 1.8 V supply, and the resulting FOM was 512 fJ/conversion stage. Further improvement of the ADC linearity and power efficiency can be made by employing multi-bit per stage architectures such as 2.5-bit, 3.5-bit, etc. This can relax the settling requirement for the op-amp and capacitor mismatch error in the front stages.  
Conceptualization, D.-H.S.; methodology, D.-H.S. and J.-G.K.; validation, D.-H.S.; formal analysis, D.-H.S. and S.C.; writing--original draft preparation, D.-H.S. and S.C.; writing--review and editing, B.-G.L.; supervision, B.-G.L. All authors have read and agreed to the published version of the manuscript.  
This work was supported in part by the National Research Foundation of Korea (NRF) Grant through the Korean Government (MSIT) under Grant 2021R1A2C22013480, and in part by the National Research and Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT under Grant NRF-2022M3H4A1A01009658.  
Not applicable.  
\begin{table}
\begin{tabular}{c c c} \hline Process [um] & 0.18 & \\ \hline Supply [V] & 1.8 & \\ \hline Resolution [bit] & 12 & \\ \hline Sampling Frequency [MHz] & 30 & \\ \hline ADC Area [mm\({}^{2}\)] & 0.351 & \\ \hline \multicolumn{3}{c}{Before Calibration} & After Calibration \\ \hline SFDR [dB] @ Fin = 2.09 MHz & 69.2 & 84.1 \\ \hline SNDR [dB] @ Fin = 2.09 MHz & 63.9 & 68.9 \\ \hline ENOB [bit] & 10.3 & 11.1 \\ \hline DNL [LSB] & \(+0.82/-0.75\) & \(+0.45/-0.41\) \\ INL [LSB] & \(+1.12/-1.79\) & \(+0.47/-0.91\) \\ \hline Power Consumption [mW] & 35 & 35 \\ \hline FoM\({}_{w}\) [fj/conv-step] & 911 & 512 \\ \hline \end{tabular}
\end{table}
Table 1: Performance summary.  
Data Availability Statement: The data presented in this study are available on request from the corresponding author. The data are not publicly available due to nondisclosure agreement of the supporting project.  
The authors declare no conflict of interest.