# A Novel Decomposed Optical Architecture for Satellite Terrestrial Network Edge Computing
## 3 Decomposed Optical Network for STN Edge Computing  
The satellite-terrestrial edge computing network is shown in Figure 1a with a decomposed optical network. The satellite system receives the requests from user terminals and transfers corresponding instructions to terrestrial decomposed computing architecture via downlink. The decomposed optical computing architecture consists of diverse resource pools such as processor, memory (Mem), and GPU, which can be flexibly configured based on application requirements. The hardware-to-NOS interconnection is divided into two parallel parts: optical packet sending plane and control plane. In the packet sending plane, the NOS switch port is linked to hardware cubes for sending optical payloads; while, in the packet control plane, the packet tag from the hardware cube is processed by the switch controller to forward/block optical payloads and reduced optical packet contention. It is significant for the scalability of the decomposed network to implement an NOS with large port count. The schematic of NOS is depicted in Figure 1b. There are \(N\) hardware cubes in total, split into \(M\) groups and \(F\) hardware cubes in each group. Leveraging distributed processing modules, the NOS can process multiple optical packets from different hardware cubes in parallel. When the FPGA-implemented switch controller analyzes the packet tag from the control-path channel, the packet payload from the data-path channel is broadcasted to SOA-based gates of the 1 \(\times\) F switch using a splitter. The hardware cube grouping can scale the port count of the NOS utilizing multiple 1 \(\times\) F switch with smaller port counts. SOA  
Figure 1: (**a**) Satellite terrestrial network with decomposed computing architecture; (**b**) Schematic of nanoseconds optical switch. gates can provide nanoseconds switching time and compensate the splitting power loss. The number of cells \(N_{cell}\) that a packet payload occupied in TX is calculated as follows:  
\[N_{cell}=[L_{p}/L_{b}] \tag{1}\]  
where \(L_{p}\) and \(L_{b}\) are the length of packet and each buffer unit, respectively. After the \(1\times\) F switch, one F \(\times\) 1 Arrayed Waveguide Gratings (AWG) gathers \(F\) different optical wavelengths from the same group and sends packets to the corresponding receiver. According to the packet destination information in the packet tag, the controller switches the corresponding SOA gate on and rest optical gates off, then the packet payload is forwarded to the target hardware cube. Taken the group that wavelength \(\lambda_{i}\) of the hardware cube \(n\) (\(1\leq n\leq F\), \(1\leq I\leq M\)) destine to as \(d\). When \(M\) is equal to or larger than \(F\), a feasible wavelength mapping rule is shown in the following formula:  
\[d=(i+1-n)\bmod M \tag{2}\]  
Due to the processing delay of the switch controller in the control-path channel, hardware cubes send out optical packets with the respective delay. To guarantee the alignment of the tag and packet, there is a periodic calibration in the control-path channel. The switch controller is also responsible for solving potential contentions among optical packets. If packet contention occurs, the optical payload with higher priority is transmitted at first, while the rest of the packet payloads sent in the same time slot are blocked by switching corresponding SOA gates off. The switch controller then sends the acknowledgment signals to the corresponding hardware cubes for successfully forwarding the packet (ACK) or re-transmitting the packet (NACK) [26]. Benefiting from the structure of the distributed modules and nanoseconds switching time of SOA gates, the NOS can provide a scalable network with the minimal network latency and high aggregation bandwidth for the decomposed hardware cubes interconnection. More details about the NOS can be found in [27]. Each hardware cube has three kinds of components: on-board resource, resource management module, and network interconnect module. The functional diagram of the processor cube is illustrated in Figure 2a.