###### Abstract  
In the domain of digital wireless communication, flexible design implementations are increasingly explored for different applications in order to cope with diverse system configurations imposed by the emerging wireless communication standards. In fact, shrinking the design time to meet market pressure, on the one hand, and adding the emerging flexibility requirement and, hence, increasing system complexity, on the other hand, require a productive design approach that also ensures final design quality. The no instruction set computer (NISC) approach fulfills these design requirements by eliminating the instruction set overhead. The approach offers static scheduling of the datapath, automated register transfer language (RTL)synthesis and allows the designer to have direct control of hardware resources. This paper presents a complete NISC-based design and prototype flow, from architecture specification till FPGA implementation. The proposed design and prototype flow is illustrated through two case studies of flexible implementations, which are dedicated to low-complexity MIMO turbo-equalizer and a universal turbo-demapper. Moreover, the flexibility of the proposed prototypes allows supporting all communication modes defined in the emerging wireless communication standards, such LTE, LTE-Advanced, WiMAX, WiFi and DVB-RCS. For each prototype, its functionality is evaluated, and the resultant performance is verified for all system configurations. N ISC; flexible implementation; application-specific processor; prototype flow; FPGA; MIMO; iterative; equalization; demapping +
Footnote †: This paper is an extended version of our paper published in IEEE International Symposium on Rapid System Prototyping (RSP), 16–17 October 2014, as M.  
and low error-rate performance. These facts motivate exploiting design and prototype flows that are capable of providing high design quality, as well as increased design productivity. In addition, wireless digital communication standards are developing continuously. Consequently, the applications are becoming increasingly complex and diverse. Wireless digital communication standards, such as DVB-RCS [1] for digital video broadcasting, 802.11 (WiFi) [2] and 802.16 (WiMAX) [3] for wireless local and wide area networks and LTE and LTE-Advanced [4] for mobile phones, support a variety of system configurations related to channel coding type, modulation type, mapping styles and antenna dimensions for multiple-input multiple-output (MIMO) transmission techniques. In order to cope with the various configurations, flexible architecture designs comprise a key trend in implementing different components of the transmission scheme. This work concerns the design and the implementation of flexible and high performance application-specific processors dedicated to the equalizer and the demapper modules of the turbo-receiver. In contrast to a non-iterative receiver, an iterative receiver is characterized by the existence, in addition to forward paths, of feedback paths through which constituent units can send the information to previous units iteratively. On every new iteration, each block generates soft information depending on channel information and on received a priori soft information generated by other blocks in the previous iteration. The concept of turbo equalization allows improving communication system performance by iteratively exchanging information between the soft-input soft-output (SISO) equalizer and the SISO channel decoder. It was initially introduced in [5] to alleviate the destructive effects of inter-symbol interference (ISI) for wireless digital transmission, which is protected by convolution codes. In modern communication systems, the use of MIMO raises co-antenna interference at the receiver side. Nowadays, to combat against ISI, orthogonal frequency-division multiplexing (OFDM) is mainly utilized.