# Low-Power Two-Phase Clocking Adiabatic PUF Circuit
## 1 Introduction  
The emerging Internet of Things (IoT) technology has simultaneously introduced challenges and opportunities for engineering-related fields. IoT is used to create smart interconnected and resilient communication systems (e.g., smart home security systems, smart health, smart cities, smart transportation, smart factories, smart grids, etc.) through the internet to improve the quality of people's lives. IoT devices include smartphones, smart cards, biomedical devices, radio frequency identification (RFID) tags, and many other cryptographic devices that require security characteristics, such as authenticity, integrity, and confidentiality in performing their tasks [1, 2]. IoT interconnected devices transmit sensitive data that can be targets of cyber-attacks [3]. In addition, typical countermeasures include cryptographic methods, often based on random numbers, which are necessary to generate public and private keys. Therefore, a physical unclonable function (PUF) plays a key role in authentication and secure key generation [4, 5]. The taxonomy of PUF in a study stated that a PUF is a hardware security fundamental that translates an input challenge into an output response through a physical system in a manner that is specific to the exact hardware instance (unique) and cannot be replicated (unclonable) [6]. An advantage of employing a PUF in a cryptosystem is its nonvolatile memory-based key storage feature, as the PUF generates keys on demand during stimulation. The characteristic of a PUF include unpredictable response (R) of the system owing to intrinsic variations, which are stimulated by the input challenge (C). The challenge-response system is modeled as a black box; hence, the PUF input-output relation is described as R = f(C), where f(.) is an unknown internal parameter influenced by the intrinsic variations of the device [4, 7]. Many studies on PUF cell level have been conducted, such as investigations on the arbiter PUF [8; 9; 10], ring-oscillator (RO) PUF [11; 12; 13; 14; 15], [PERSON] et al. employed RO in field-programmable gate array for transform-coding [16], be-stable ring PUF [17], glitch PUF [18], dynamic random access memory (DRAM) PUF [19; 20], and static random access memory (SRAM) PUF [21; 22]. In addition, many studies on low-power PUF circuits have been conducted, such as robust digital response and low-power current-based PUF [23], as well as the SRAM-based PUFs over a wide range of supply voltages from the super-threshold voltage regime down to the near-threshold voltage (NTV) regime [24]. The IoT devices are mostly battery-powered embedded devices and operate in low frequency ranges, which cause security issues and low power consumption. All PUF cells presented in [8; 9; 10; 11; 12; 13; 14; 15; 16; 17; 18; 19; 20; 21] undergo high-power consumption and voltage ramp-up time adaptation for a reliable PUF circuit. In this study, we have attempted to address these two issues. For low-power and low-frequency applications, the adiabatic switching technique [25] is considered to be an appropriate logic design approach for cryptographic circuit implementation [26; 27; 28]. In 2016, the first low-power adiabatic SRAM PUF cell was introduced, which was a quasi-adiabatic logic-based PUF (QUALPUF) [29]. The security measures of 128-bit QUALPUF were further investigated thoroughly in [30], and the 4-bit QUALPUF LSI was implemented in a 0.18 \(\upmu\)m standard CMOS process with 1.8 V nominal supply voltage along with post-layout and chip measurements in [31; 32]. The merit of the QUALPUF is an energy-efficient computation platform, which used adiabatically time-ramp voltage to improve the reliability of a PUF cell. In this study, we designed an ultra-low-power PUF cell based on the adiabatic switching principle to generate a reliable cryptographic key for IoT embedded devices. The proposed adiabatic PUF circuit is based on an SRAM cell in which the PUF response is stimulated by a challenge bit via a static CMOS circuit.