## 1 Introduction and Problem Formulation
### Transformation of the Petri Net-Based Description into Verilog HDL Code
For example, place \(p_{3}\) (line 8) is active (holds a token) if its output transition \(t_{3}\) is not enabled (by holding up the current state), or, if its input transition \(t_{10}\) is executed. Similarly, the description for place \(p_{7}\) involves the following: p[7]&-t[5]&-t[6]&-t[7]|t[1]|t[3]. This means that \(p_{7}\) becomes active if one of three conditions is fulfilled if either all its output transitions (\(t_{5},t_{6},t_{7}\)) are not enabled or one of its input transitions (\(t_{1}\) or \(t_{3}\)) is executed. Note that in the above descriptions, procedural assignments are used; thus, the values of particular places are registered. Such place registers strictly refer to the current state of the system. The third block refers to the binary outputs of the system. The proposed description mixes continuous and procedural assignments, according to the designer's needs. Typically, continuous assignments are used. Such a situation is more common when the modeled system controls objects by sending signals. However, outputs can be also registered in order to maintain the value. This can be especially useful if the particular output should be activated in the particular state and deactivated with the other marking. Recall Petri net \(\mathcal{N}_{1}\). Output \(y_{1}\) is activated by place \(p_{1}\) and deactivated by \(p_{9}\). Therefore, this particular signal is described by procedural assignment, as shown in Listing 3 (lines 1-7). All the remaining outputs are described by continuous assignments [41,43]. ```
01:always@(posedge clk or posedge reset)
02:begin
03:if(reset) p<=10'b0010110000;
04:else
05:begin
06:p[1]<=p[1]&t[1]|t[5];
07:p[2]<=p[2]&t[3]|t[2];
08:p[3]<=p[3]&t[3]|t[10];
09:p[4]<=p[4]&t[3]|t[4];
10:p[5]<=p[5]&t[2]|t[3];
11:p[6]<=p[6]&t[4]|t[3];
12:p[7]<=p[7]&t[5]&t[6]&t[7]|t[1]|t[3];
13:p[8]<=p[8]&t[8]|t[6];
14:p[9]<=p[9]&t[9]|t[7];
15:p[10]<=p[10]&t[10]|t[8]|t[9];
16:end
17:end
```  
Listing 2: Place equations for the concurrent control system modeled by \(\mathcal{N}_{1}\). ```
01:always@(posedge clk or posedge reset)
02:begin
03:if(reset) y[1]<=1'b0;
04:else
05:if(p[1]) y[1]<=1'b1;
06:else if(p[9]) y[1]<=1'b0;
07:end
08:assign y[2]=p[4]|p[5];
09:assign y[3]=p[6];
10:assign y[4]=p[8];
```  
**Listing 3**Output equations for the concurrent control system modeled by \(\mathcal{N}_{1}\). It should be noted that the transformation process can be automated. There exist tools that permit the conversion of a Petri net-based description to hardware description languages, either VHDL (e.g., _IOPT-Tools_[83]) or Verilog (e.g., _Hippo_ tool [19; 20; 88]). Therefore, the designer is not forced to know technical details nor advanced mechanisms in regard to the particular hardware language. To conclude the discussion presented above, let us underline that the HDL model is essential for the further functional reduction (described in the next subsection). All three blocks included within Verilog code are based on the logic equations. Therefore, the adequate realization (implementation) of such functions within an FPGA is extremely important in the context of utilized logic blocks. The next subsection proposes a novel decomposition technique of logic equations. The main aim of the presented solution is the reduction in the FPGA resources.