## 2 Proposed Wheatstone Bridge Readout IC with Chopper-Stabilized Multipath Operational Amplifier
### Top Architecture of the Wheatstone Bridge Readout IC  
Various types of IAs that can be implemented to properly amplify small input signals; capacitively coupled IAs (CCIAs), current feedback IAs (CFIAs), and three-operational amplifier IAs are the most popular types. The conventional architecture of CCIAs is shown in Figure 1(a); the output voltage is given as  
\[V_{out}=\frac{C_{in}}{C_{fb}}V_{in} \tag{1}\]  
The CCI has high power efficiency, but the input stage is composed of capacitors, so the input impedance is lower than other IAs. To solve this issue, a circuit that can increase the input impedance, such as a positive feedback loop (PFL), is required [28].  
The CFIA has high input impedance, but gain accuracy is limited by a mismatch between the input and the feedback transconductance [28]. A block diagram of the CFIA is shown in Figure 1(b), and the output voltage is expressed as  
\[V_{out}=\frac{R_{1}+2R_{2}}{R_{1}}V_{in}. \tag{2}\]  
The three-operational amplifier IA has low power efficiency owing to the use of two low-noise input amplifiers, but achieves high input impedance and excellent linearity. The conventional block diagram of the three-operational amplifier IA is shown in Figure 1(c).  
Figure 2: _Cont._  
In this paper, we implement the three-operational amplifier IA architecture to acquire excellent linearity and a comfortably adjustable gain. The top architecture of the proposed Wheatstone bridge readout IC, including the three-operational amplifier IA, is shown in Figure 3. The output offset of the three-operational amplifier IA is adjustable using a digital-to-analog converter (DAC) connected to the input of the fully-differential amplifier A\({}_{2}\). The transfer function of the three-operational amplifier IA, including the DAC operation, is expressed as  
\[(V_{out+}-V_{out-})=\bigg{(}1+\frac{2R_{2}}{R_{1}}\bigg{)}\bigg{(}\frac{R_{4}} {R_{3}}\bigg{)}(V_{in+}-V_{in-})+R_{4}(I_{P}+I_{N}) \tag{3}\]  
The structure of the Wheatstone bridge sensor is simulated by a single-element varying structure; the variable resistance is modeled using Verilog-A. The proposed three-operational amplifier IA is comprised of a first stage, consisting of A\({}_{1\text{A}}\) and A\({}_{1\text{B}}\), and a second stage, consisting of A\({}_{2}\). The gain of each stage is determined by the variable resistors, R\({}_{1}\) and R\({}_{3}\). These resistors are designed as 5-bit programmable resistors. The two single-ended amplifiers A\({}_{1\text{A}}\) and A\({}_{1\text{B}}\) at the input stage produce low noise by using the proposed chopper-stabilized multipath operational amplifier, consisting of an HFP and LFP. In addition, the fully-differential amplifier A\({}_{2}\) applies the chopping technique; its schematic is shown in Figure 4. Chopping is applied at the input stage and at the folded cascode stage of the fully-differential amplifier. The input range is extended by employing the  
Figure 3: Top architecture of the proposed Wheatstone bridge readout IC.  
Figure 2: Conventional architecture: (**a**) Block diagram of a CCIA; (**b**) Block diagram of a CFIA; (**c**) three-operational amplifier IA.  
The output of the three-operational amplifier IA, which amplifies the input small signal, passes through the LPF and buffer, and is then converted into a digital signal by a 12-bit SAR ADC. The LPF adopts a Sallen-key topology, and the simulation results indicate that the cutoff frequency is 840 Hz. The 12-bit SAR ADC employs a resistor-capacitor hybrid structure that diminishes the area by 16 times compared to a capacitor-only DAC. An offset calibration technique is implemented for the comparator in the 12-bit SAR ADC to achieve high linearity and low offset.