# Low Power FPGA Implementation of a Smart Building Free Space Optical Communication System
## 3 Implementation  
This section is divided into two parts: software and hardware. The software part of the system is encapsulated in the processing done on the ALTERA FPGA Cyclone IV DE2-115 board that has a RISC-V processor software version installed for input data management. RISC-V is an open specification platform that allows designers to use open-source cores, utilized at low power mode, unlike ARM, Intel, and AMD processors, which need licensed products, owned IP, and use complex instruction set computer (CISC) technique, hence, they have high power consumption. Newly intriguing computing methodologies and integrating engineering applications acquire the presence of robust simulation and testing kits that can stimulate the process of innovation in both software and model-ware forms, which are capable of supporting and validating the design flow. Model-ware, often known as Model-Driven Development (MDD), is a broad area that supports a variety of technologies by increasing software development productivity. With highly defined software isolation domains that are continuously up to date, developers can frequently upgrade their designs and ensure the security of data [25]. It is highly used for multimedia applications and file compressions, thus an optimum processing option for the proposed design. The communication between the FPGA and the computer is obtained via a Universal Asynchronous Receiver Transmitter (UART) RS232 cable for transmission and a Universal Serial Bus (USB) for the reception. The proper modulation technique is selected according to the required data rate and mapped to be performed by the software interface (Quartus Prime 18.0) of the FPGA. Higher-level Intensity Modulation (IM) was the item of choice, controlling the illumination of the laser beam accordingly. Four power levels were given as the constellations of data required to be transmitted. The levels were represented as 0%, 33%, 66%, and 100% of the power. Tera Term and Putty user interfaces were used to test the data sent in a text form, while MATLAB was the test bench used for audio data. The modulated signal is fed from the FPGA General Purpose Input Output (GPIO) into a laser driver circuit where it is amplified using a common emitter configuration amplifier manifesting the selection of a TIP31C power transistor that boosts the transmission into a 650 nm Visible Light (VL) red laser source. The FPGA input signal is directed to the base of the transistor while the output signal is taken from the collector to the laser source, as shown in Figure 5. The emitter is connected to a 3.3 V supply. If the o/p of a collection of circuits linked as a system reaches a fixed value in a finite time, it is said to be stable. A system is considered to be unstable if its o/p rises with time rather than stabilizing. Multiple ways are used to determine the stability of a circuit. For BJT stability, the rate of change of collector current with respect to the reverse saturation current can be the metric of stability measurement. The maximum collector-base voltage in saturation mode is 1.2 V at a collector current I\({}_{C}=3\) A, while the transit frequency for  
Figure 5: Laser Driver Circuit. current gain is f\({}_{\rm T}\) = 3 MHz at I\({}_{\rm C}\) = 500 mA [26]. The operating margin for the BJT is ensured, and a consistent current flows via R1 and is supplied into the laser module since the circuit is run in low power mode, with V1 continually 3.3 V plugged out of the DC port on the FPGA board and Vin dependent on the set character voltages from the PC. Hence, the input current to the laser module is constantly stabilized in the range of milli Ampere. The optimal transistor was chosen based on the power amplifying specifications required to transfer the optical signal at the greatest possible distance. After experimentations, the application of the TIP31C transistor became apparent.