## 3 Proposed Method
### Buffer-Based Dependency Avoidance for Adaptive Pipelining  
The implementation of the proposed method described in Section 3.3 is described in this part. In the previous section, it was mentioned that dependencies between loops in the Parallelized Sum pooling method are not eliminated but can be ignored under certain conditions. First, Algorithm 2 shows a pseudo-code that implements the structure described in Section 3.3 for the HLS tool. HLS is an abbreviation for High Level Synthesis. Verilog or VHDL languages are less productive in the hardware design process. Using higher abstraction-level languages, such as C/C++, has several advantages in terms of productivity. HLS is a tool that automatically generates RTL-level code just as a compiler compiles when C/C++ codes used for algorithmic technology, rather than Verilog/VHDL, which was traditionally used in hardware design. Parallelization techniques using HLS tools are already well researched due to their high productivity and portability [27]. The iterations for the output's width and output's height are moved to the lowest level, and a buffer equal to the size of the height multiplied by the width is placed under the top loop. The buffer in line 2 will serve as a buffer to store as many results as there are features in the output of one channel. Next, in Algorithm 2, the pipelining directive is placed on line 10, so it will attempt to pipeline lines 12 through 18. However, in this synthesis, the  
Figure 3: Proposed CNN computation structure with sum-pooling.  
Figure 2: CNN computation structure with conventional sum-pooling.  
dependency on the accumulating sum in line 13 is determined to be valid, so pipelining does not proceed. Therefore, the directive in line 11 explicitly removes the dependency on the result. In this process, lines 12 through 18 are pipelined and can be parallelized.  
\begin{tabular}{l l} \hline \hline
**Algorithm 2** & **The Proposed Parallelized Sum Pooling Method** \\ \hline \multirow{4}{*}{Input} & conv\_in[] \\  & conv\_weight[], conv\_bias[] \\  & input's height, width, channel \\  & kernel size \\  & output's height, width, channel \\ Output & conv\_out[] \\ \hline
1. & **for i = 0-output\_channel** \\
2. & float result [output\_width \(\times\) output\_height] = 0; \\
3. & **for x = 0-input\_channel** \\
4. & **for y = 0-kernel\_size** \\
5. & **for z = 0-kernel\_size** \\
6. & **Calculate weight\_idx** \\
7. & float temp = conv\_weight \\
8. & **for j = 0-output\_width** \\
9. & **for k = 0-output\_height** \\
10. & **#Pi Pipeline II = 1** \\
11. & **\#ignore dependence variable = result** \\
12. & **Calculate** in\_idx \\
13. & result += conv\_in[in\_idx] \(\times\) conv\_weight[weight\_idx] \\
14. & **Calculate** out\_idx \\
15. & **Calculate conv\_out[out\_idx]** \\
16. & **If**(conv\_out[out\_idx] \(\Leftarrow\) 0) \\
17. & Conv\_out[out\_idx] = 0; //ReLU \\
18. & **end** \\
19. & **end** \\
20. & **end** \\
21. & **end** \\
22. & **end** \\
23. & **end** \\
24. & **end** \\ \hline \hline \end{tabular}  
For deep and complete pipelining, it is necessary to analyze the execution time of lines 12 to 18. If the latency of 12 to 18 exceeds the size of the buffer, deep and complete pipelining is not possible because the dependencies between the data become valid again. In this context, deep and complete pipelining means that the Initiation Interval is equal to 1. This condition is defined as follows:  
\[C_{com}\leq buffer_{size} \tag{2}\]  
In this application, the execution cycle _Com_ for lines 12-18 is 14 clocks, which means that implementing a buffer of 14 clocks or more will allow for deep and complete pipelining.