## 1 Introduction  
The strongly growing markets of power electronics [1] and opto-electronics, e.g., laser modules and solid-state lighting (SSL) [2], share the same problem of high thermal losses across small areas, which have to be reliably dissipated to avoid lifetime-reducing overtemperatures. For power electronics, most crucial components are switches (e.g., metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs)) and diodes [3], generating power losses in the form of heat due to switching and conductive losses. In SSL, critical components are laser diodes and power-LEDs (referred to as just LED in the following) with limited efficiency while converting electrical to optical power. As different as both electronic segments may be, the semiconductors are the most critical components, and the concept of heat management is also similar. The concept is described in Figure 1 in a general manner and is used for most (a) power electronics and (b) SSL applications. Heat is induced at the junction of the semiconductor and transferred downward through the chip to the large-area interconnect 1, which is responsible for not only electrical but also thermal connection. Typical for interconnect 1 is soldering or sintering. A distinction can be made between single electrical contact interconnects (die bonds), e.g., for bare die chips with wire bonds to realize all other electrical connections in (a), and multi electrical contact interconnects, e.g., for packaged LEDs where all electrical contacts are realized by large-area solder pads with small gaps in between on the backside in (b). From interconnect 1, the heat flows through the substrate, realizing an electrical circuit with copper structures and traces. For thermally critical applications, mostly direct bonded copper (DBC) substrates (set-up: 0.15-0.8 mm copper/0.25-1.0 mm ceramic/0.15-0.8 mm copper) [4] or insulated metal substrate printed circuit boards (IMS-PCB) (set-up: 0.018-0.105 mm copper, 0.05-0.2 mm deictic, 0.3-3.0 mm aluminum or copper core) [5] are used. Inside the substrate, the heat is spread in the horizontal direction, reducing the thermal resistance by increasing the heat transfer cross-section. The substrate is attached with the full-area interconnect 2 to the heat sink, where the heat is passively, e.g., via convection of cooling fins, or actively, e.g., via forced convection by fans or liquid cooling, dissipated to the ambient. Typical for interconnect 2 are soldered and adhesive interconnects or thermal interface materials (TIM). In some applications, an additional metal base plate is used between the substrate and heat sink to increase thermal mass and improve mechanical stability [6]. For good thermal performance and long lifetimes of new power electronics or SSL products, the thermal concept must be verified by calculations and simulations in the development process to keep the maximal operation temperature of the semiconductors within a noncritical range. However, due to production failures (e.g., incomplete printing or dispensing, improper component placement, contamination and volatile process parameters) or material degradation over years in operation (e.g., cracks and delamination), the thermal performance might be reduced. To avoid or at least minimize thermal failures, manufacturers use different nondestructive testing methods (NDTs) for qualification. Most popular and well established in power electronics and SLL development and production is X-ray inspection to detect inhomogeneities in metal structures, e.g., voids and nonwetted areas in soldered interconnects [7], even at production speed, allowing for in-line automated inspection. However, X-ray is limited for sintered interconnects and adhesives, since porosity of sintered interconnects is too small for the resolution of X-ray images [8], and adhesives have a very low density for detection between the surrounding high-density metal components [9].