# Supply-Scalable High-Speed I/O Interfaces
## 1 Introduction
RX slicers are used to decide whether the received analog signal is '1' or '0' by sampling the signal at the timing when the signal-to-noise ratio (SNR) is maximized. A variable-gain amplifier (VGA) can be preceded by the slices to amplify the input signal for better sensitivity. Since it is important to sample the received signal when the SNR is maximized, finding the optimum sampling timing is one of the utmost tasks of the receiver. The clock and data recovery (CDR) circuit collects such timing information from edge slicers (bang-bang CDR) or error slicers (baud-rate CDR), and based on the collected information, it adjusts the sampling timing by using a phase interpolator (PI) [20]. A multi-phase generation circuit such as a delay-locked loop (DLL) or an injection-locked oscillator (ILO) is widely used to provide a high enough number of phases for the PI. On the other hand, a decision-feedback equalizer (DFE) is used to fully compensate the residual ISI. The basic concept of the DFE is to utilize the previously received data stream to help the decision of the currently received bit to compensate the ISI. Unlike the FFE or continuous-time linear equalizer (CTLE), the DFE does not degrade the SNR, so nowadays, it has become a very essential building block of the receiver. Finally, the recovered data is de-serialized to the parallel stream. Figure 1: Example block diagram of input/output (I/O) transceiver. As mentioned before, introducing wide-range operation results in significant overhead on design complexity and an energy/area efficiency penalty as well. For example, because it is not easy to cover the entire frequency range with a single PLL or a single voltage-controlled oscillator (VCO), multiple PLLs (or VCOs) are frequently implemented together and are selected with respect to the operating frequency. In addition, most of the building blocks needs to be designed to work properly at the highest rate. It leads to a significant impact on the energy efficiency at a lower data rate. For better understanding, Figure 2 shows a simple example of a CMOS inverter. The delay (\(\tau_{d}\)) and rise/fall time (approximately \(2\tau_{d}\)) of a CMOS inverter is proportional to the fan-out of the inverter, which is a ratio of the gate output capacitance over the gate input capacitance. To retain a full rail-to-rail CMOS swing and to reduce jitter generation, the rise/fall time must be fast enough for given operating frequency. As a rule of thumb, \(\tau_{d}\) should be no larger than one-fourth of bit period (\(T_{bit}\)) [21; 22]. It implies that the fan-out has to be low enough to sustain a proper operation at the highest frequency. On the other hand, the dynamic switching power consumption of a CMOS inverter chain whose final output load is \(C_{L}\) is given as  
\[P\ =\ \frac{FO}{FO-1}C_{L}V_{DD}^{2}f_{clk} \tag{1}\]  
where \(FO\), \(V_{DD}\), and \(f_{clk}\) represent the fan-out of the chain, the supply voltage, and the switching frequency, respectively [23]. That means that if the fan-out is set for the optimum operation at the highest frequency, then in fact, it is overkill and causes unnecessary power consumption at a lower frequency. In addition, there are also overheads to make circuits work at a low frequency, which makes the efficiency at high frequency worse (i.e., capacitors). These observations can be proven from the survey of wide-range and supply-scalable transceivers shown in Figure 3, where the energy efficiencies of transmitters, receivers, and transceivers in [15; 16; 22; 24; 25; 26; 27; 28; 29; 30; 31; 32; 33; 34; 35] are marked in the scatter plot with respect to how wide the operating range is (highest data rate/lowest data rate). Note that the energy efficiencies depicted in the Figure 3 are measured at the highest data rate of each design. It is observed that the energy efficiency becomes worse as the range widens, which proves the overhead of the wide range.