## 3 Results and Discussion  
### Model Parameter Fitting  
The temperature variation inside the device is simulated using the analytic thermal resistance network model to obtain the relationship between \(\Delta T\) and the dissipated power \(P_{disp}\). While \(P_{disp}\propto V_{ds}*l_{ds}\), the drain/source current is modeled by the power-law model \(I_{ds}\propto B(V_{gs}-V_{th})^{n}\). The parameters B and n are obtained from the literature [13], and n is approximated as 1. If we divide \(P_{disp}/I_{ds}\) by \(I_{ds}/V_{gs}\), we can obtain the self-heating parameter \(\Theta\). Figure 8a shows the relationship between thermal resistance and the number of fins obtained using the thermal resistance network model. Figure 8b shows the relationship between the temperature change due to self-heating and the dissipated power obtained from the analytical model simulation, and the extracted self-heating coefficients are labeled in the figure. The results can be corroborated with the coefficients from the literature [14], which are about 60 in both cases. The device structure parameters and thermal conductivity parameters used in the analytical modeling are shown in Tables 1 and 2, respectively. For the established compact model, parameter extraction was carried out using data from the literature [17]. In this literature, 16/14 nm bulk FinFETs were used to measure the HCI degradation under different voltage stress levels. The extraction of the HCI parameters was performed step by step. We first used Equation (17) to extract the parameters mentioned in it. Cross-validation was used to ensure the stability of the parameters, and to avoid the overfitting phenomenon, using four sets of data under different experimental conditions. \[\Delta V=V_{m,i}\times\left[1-\exp(-AR\cdot t^{n})\right]+V_{m,ox}\times\log( 1+c\cdot t) \tag{17}\]  
Then, the parameters \(n_{1}\), \(n_{2}\), \(H_{1}\), \(H_{2}\), A, and B were extracted in order in the form of (18) and (19). The final fitting results are shown in Figure 9. Figure 9a,b show the curves \begin{table}
\begin{tabular}{c c c} \hline \hline
**Fin Width (nm)** & **Fin Height (nm)** & **Channel Length (nm)** \\ \hline
10 & 30 & 20 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Bulk FinFET structure key parameters. Figure 8: (**a**) Thermal resistance \(R_{th}\) versus \(N_{fin}\); (**b**) temperature rise caused by SHE versus power density. of threshold voltage degradation over time for different \(V_{gs}\) and \(V_{ds}\) values, measured in the SVE region. Figure 9c,d show the threshold voltage degradation in the MVE region for varying \(V_{gs}\) and \(V_{d}\) over time. The fitted parameters for the two different energy regions are listed in Table 3. Some of the parameters in the table contain the process variation \(\delta\), which is a fuzzy parameter that needs to be specifically extracted in different processes. \[AR_{i}=A\cdot\left(V_{gs}-V_{T0}\right)^{n_{1}}\cdot\exp\left(-\frac{H_{1}}{V_{ ds}-\eta V_{dsat}}\right)\cdot\exp\left(-\frac{E_{ak}}{k_{B}T}\right)\cdot\exp \left(\frac{1}{W_{eff}}\right)^{a_{n}} \tag{18}\]  
\[V_{m,ox}=B\cdot\left(V_{gs}-V_{T}\right)^{n_{2}}\cdot\exp\left(-\frac{E_{ak}}{k _{B}T}\right)\cdot\exp\left(-\frac{H_{2}}{V_{ds}-\eta V_{dsat}}\right)\cdot \left(\frac{1}{W_{eff}}\right)^{a_{n}}\cdot\exp\left(\alpha_{i}V_{b}\right) \tag{19}\]  
The relevant parameters related to substrate voltage and width were extracted using data from the literature [16] containing a FinFET device with HKMG at the 45 nm node, which had a total fin height of 30 nm and a width of around 10 to 25 nm. The fitted parameters \(a_{n}\) and \(\alpha_{i}\) are also shown in Table 3. The fitted curves compared with raw data are presented in Figure 10.  
Figure 9: Comparison of fitted \(V_{t}\) shift–stress time curves and raw data (**a**) under different \(V_{gs}\) in SVE region; (**b**) under different \(V_{ds}\) in SVE region; (**c**) under different \(V_{gs}\) in MVE region; and (**d**) under different \(V_{ds}\) in MVE region.