## 5 Experimental Results and Comparison
### Comparison  
This section presents a systematic analysis and discussion of the research findings. First, the evaluation criteria and specific parameters employed in this study are outlined. These metrics provide an objective basis for assessing the performance of the methodology. Figure 12: Test data example 2. The targets are highlighted with red boxes. Figure 13: Test data example 3. The targets are highlighted with red boxes. Subsequently, based on these criteria, a detailed evaluation of the ELUM framework proposed in this paper is conducted, followed by a comprehensive comparison with existing methods to verify its superiority. The evaluation criteria and methods used in this study are described below. LUT resources are defined as the configurable logic blocks within an FPGA that implement combinational logic functions. Each LUT can perform any logic operation by programming its inputs and outputs. LUT utilization reflects the flexibility and efficiency of hardware design in implementing complex logic functions and serves as a critical metric for assessing the design logic density and resource optimization. The LUT count is a key indicator of how efficiently a design uses the FPGA's logic capabilities and can directly influence the overall performance and scalability of the system. Throughput is defined as the volume of data processed or transmitted by the hardware within a given time interval. It reflects the system's capacity to handle large quantities of data efficiently and serves as a critical performance metric. Throughput is a key indicator of the system's ability to manage data flows and its operational capacity. In this paper, throughput is represented by the number of infrared image pixels processed per unit time, as expressed by the following:  
\[Throughput=Resolution\times FPS \tag{43}\]  
We implemented the hardware design of the ELUM architecture on a Xilinx Kintex-7 series FPGA and conducted a comprehensive performance comparison with other existing designs. Table 2 presents the implementation results of our design after placement and routing, alongside the results of some recently proposed designs. The ELUM design is configurable to accommodate input images of varying resolutions by adjusting its parameters. Table 3 presents the processing speed of the proposed design at different input image resolutions. The design was proven to achieve a resolution of 3112 \(\times\) 2048 pixels at a frame rate of 30 fps, ensuring that the system maintains a sufficient processing speed while preserving high image quality. Given that other designs handle images with varying resolutions, we use the previously mentioned throughput as a unified metric for comparison. Among all the FPGA implementations listed in the table, our design achieves the highest throughput, reaching up to 199,950,336 pixels per second, which represents a significant improvement over other hardware designs. From the perspective of logical resources, specifically LUTs, the algorithm proposed in this paper requires only 5301 LUT6s \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Ref** & **Resolution** & **FPS** & **Throughput (Pixels/s)** & **LUT** & **DSP** & **Power (mW)** \\ \hline
[4] & 320 \(\times\) 240 & 25 & 1,920,000 & 2587 & & \\
[5] & 500 \(\times\) 500 & 104.2 & 26,050,000 & 8440 & 54 & 372 \\
[7] & 256 \(\times\) 256 & 56 & 3,670,016 & 35,573 & & 48.7 \\
[1] & 320 \(\times\) 240 & 204.1 & 15,674,880 & 19,401 & 4 & \\
[6] & 640 \(\times\) 480 & 30.3 & 9,308,160 & 24,936 & & \\
[25] & 760 \(\times\) 576 & 25 & 10,944,000 & 28,848 & & \\ our & 256 \(\times\) 256 & 3051 & 199,950,336 & 5301 & 38 & 292 \\ \hline \hline \end{tabular} Note that our pixel depth is 8-bit.  
\end{table} 
Table 2: Implementation results. \begin{table}
\begin{tabular}{c c} \hline \hline
**Resolution** & **FPS** \\ \hline
256 \(\times\) 256 & 3051 \\
1920 \(\times\) 1080 & 96 \\
2560 \(\times\) 1440 & 54 \\
3112 \(\times\) 2048 & 30 \\
4096 \(\times\) 3112 & 15 \\ \hline \hline \end{tabular}
\end{table}