# Multilevel Bipolar Electroforming-Free Resistive Switching Memory Based on Silicon Oxynitride
## 3 Results and Discussion
### Resistive Switching Mechanism  
A log(I)\(-\)log(V) plot of the 10-nm-thick SiO\({}_{\text{x}}\)N\({}_{\text{y}}\)-based device and current conduction process in the HRS, IRS, and LRS are shown in Figure 3.  
The log(I)\(-\)log(V) characteristics of the device in the HRS and IRS can be clearly divided into different regions which are marked as R-1, R-2, and R-3. It follows the trap-controlled space charge-limited conduction (SCLC) mechanism [35; 36]. On the other hand, in the LRS, which is marked as R-4, the log(I)\(-\)log(V) characteristics show an ohmic behavior with a slope of one, which follows the filamentary conduction. The characterization reveals that the resistive switching from the IRS to LRS is caused by controllable transformation from charge trapping/detrapping to filamentary conduction in the SiO\({}_{\text{x}}\)N\({}_{\text{y}}\)-based RRAM device. The area-dependent current characteristics of Au/Ni/SiO\({}_{\text{x}}\)N\({}_{\text{y}}\)/p\({}^{+}\)-Si memory devices is shown in Figure 4. The current of LRS does not depend on the area, which implies that the current conduction in LRS is dominated by the filamentary conduction. It also shows that the resistance switching mechanism between LRS and IRS is the formation and rupture of filaments. On the other hand, area-dependent I\({}_{\text{HRS}}\) and I\({}_{\text{IRS}}\) support that the current conduction in HRS and IRS is dominated by a trap-to-trap hopping process. [37; 38]. Figure 2: Typical I-V characteristics of an Au/Ni/SiO\({}_{\text{x}}\)N\({}_{\text{y}}\)/p\({}^{+}\)-Si memory device with I\({}_{\text{COMP}}\) = 0.25 mA. Based on analysis of the current conduction mechanism by \(\log\) (I) \(-\) log (V) plot and fitting, the total resistive switching mechanism of the device is proposed below, and the schematics are shown in Figure 5. For a detailed understanding of the switching mechanism, the switching from the HRS to IRS was named SET1 and IRS to LRS was named SET2. Similarly, the switching from the LRS to IRS was named RESET1 and IRS to HRS was named RESET2. The as-prepared Au/Ni/SiO\({}_{x}\)N\({}_{y}\)/p\({}^{+}\)-Si memory device contained a certain number of defects in its active SiO\({}_{x}\)N\({}_{y}\) layer (Figure 5a). As positive bias voltage is applied, the SCLC is controlled by defects. The representative log(I)-log(V) characteristics of the SCLC usually involves two different regions. Ohmic conduction (\(I\)\(\propto\)\(V\)) is found in the low-voltage region (R-1). As soon as the voltage goes beyond the trap-filled limit (R-2 region), the log(I) \(-\) log(V) plot follows [PERSON]'s square law (\(I\)\(\propto\)\(V^{2}\)). For further increase in voltage (R-3 region), the Pool-Frenkel emission helps the trapped electrons go to the conduction band by field-enhanced thermal excitation. As the positive voltage reaches the SET1 voltage (V\({}_{\text{SET1}}\)), the switching from the HRS to IRS takes place. The conduction path originates from the charge-trapping process of the electronic carriers through nitride-related traps in the bulk of the SiO\({}_{x}\)N\({}_{y}\) layer from the bottom electrode to the top electrode (Figure 5b) [35]. The traps are deep enough to store the trapped carriers for a sufficiently long time under repeated read operations. The potential barriers of the traps in the bandgap of the  
Figure 4: The area dependent current characteristics of Au/Ni/SiO\({}_{x}\)N\({}_{y}\)/p\({}^{+}\)-Si memory devices. Figure 3: \(\log\) (I) \(-\) log (V) characteristics of an Au/Ni/SiO\({}_{x}\)N\({}_{y}\)/p\({}^{+}\)-Si memory device with I\({}_{\text{COMP}}\) = 0.25 mA. switching oxide must be asymmetric with respect to the bias polarity or different levels of discrete trap states. As a result, the trapped carriers respond differently to the applied bias. The electroforming-free resistive switching can be ascribed to the abundant initial nitride-related defects in the PECVD-deposited SiO\({}_{\mathrm{x}}\)N\({}_{\mathrm{y}}\) layer [17; 30].