# A Wireless EEG System for Neurofeedback Training
## 3 System Architecture of the EEG Device
### Transmission Module  
#### 3.2.1 Analog-to-Digital Convertor Module  
The main focus was on the choice of the analog front-end (AFE), which supports a maximum number of channels with a high resolution for measurements of EEG and electrocardiogram (ECG) signals and good noise reduction capabilities. The AFE design enables the initial acquisition of analog biosignals by electrodes and their digital conversion (Figures 1 and A1).  
A conventional board for EEG data acquisition was founded on high-precision modules (ADS1298/9) to convert the data from analog to digital format [26]. The ADS129x enabled the elaboration of size-reduced medical systems with scalable characteristics and low power and total cost. The ADS129x AFEs were used in a multi-channel, battery-powered EEG system with significantly reduced board space compared with alternative EEG AFEs that provided fewer channels [18] and required additional external components such as anti-aliasing RC filters [26] and a high-Q active notch filter [18] for noise reduction. The choice of ADS129x in the EEG scheme implemented in the current study was mainly guided by the requirement of minimum power consumption when collecting weak electrophysiological signals (Figure 1 in [26]). The ADS129x AFEs were ADC chips programmable by configuring their registers. An on-chip internal reference circuit (right-leg-drive (RLD) amplifier) provided reference voltages to the device. The power supply module could be configured to 3.3 V, 0 V, or 5 V. The low-consumption device could be powered by 3.3 V, which was suitable for the battery power. Including more than one Wilson central terminal amplifiers reduced the total noise because of the noise averaging from the passive summing network at the output of these amplifiers. The capabilities of the right-leg-driving (RLD) circuit better reduced the noise and counteracted general interference, such as from power  
Figure 1: **(A)** View of 16 channel device. **(B)** Average input reference noise \(\mathrm{\SIUnitSymbolMicro V}_{\mathrm{PP}}\) of channel at sampling frequencies Fs of 250–16,000 Hz and gain PGA of 1–12 (common-mode rejection ratio (CMRR)) at said sampling frequencies.  
lines, and electromagnetic radiation from various radio transmitters and cells in mobile phones and routers. All in-phase LCD circuits were significantly reduced.  
For our development, we chose implementation in the Thin Quad Flat Packages (TQFP) build. The connection to multiple devices was applied as shown in the technical overview of the ADS129x (Figure 45 in [26]). A \"daisy chain\" configuration was applied to connect the ADS1298 devices (Figure A2). Communication with the microcontroller was conducted via an SPI port (Figure A1). Most functions of ADS129x were implemented through five pins, such as configuration and control through the registers, the transfer of digital data, and leading out to a header for a convenient wireless connection (Figure A1). When multiple devices were used, all devices in the chain operated in the same register setting, and DIN was shared, reducing the SPI communication signals to four regardless of the number of devices (Figure A2). This architecture allowed a faster SCLK rate speed.