# CUDA-Optimized GPU Acceleration of 3 GPP 3D Channel Model Simulations for 5G Network Planning
## 5 Channel Emulator Acceleration on GPU
This work demonstrates the feasibility and benefits of using GPU-based hardware acceleration for 5G NR channel model simulations, and provides a valuable tool for network designers and researchers. Future work could include extending the channel model to support more propagation scenarios and antenna configurations, as well as integrating the channel model with other components of the 5G simulation stack, such as physical layer and link layer models. Conceptualization, N.A.S., L.L. and M.T.L. ; Methodology, N.A.S. ; Software, N.A.S. ; Validation, N.A.S. ; Formal analysis, N.A.S. ; Resources, N.A.S. ; Data curation, N.A.S. ; Writing--original draft, N.A.S. ; Writing--review & editing, L.L. and M.T.L. ; Visualization, N.A.S. ; \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Platform** & **Precision** & **Memory (\%)** & **SM (\%)** & **DSP (\%)** \\ \hline \multirow{2}{*}{**FPGA**} & DP & 13.14 & N/A & 17.24 \\  & SP & 6.25 & N/A & 8.05 \\ \hline \multirow{2}{*}{**GPU**} & DP & 40.89 & 63.61 & N/A \\  & SP & 32.28 & 42.09 & N/A \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Resource utilization of accelerated designs. Supervision, R.Q., L.L. and M.T.L. ; Project administration, L.L. ; Funding acquisition, R.Q. All authors have read and agreed to the published version of the manuscript. This work was partially supported by the European Union under the Italian National Recovery and Resilience Plan (NRRP) of NextGenerationEU, partnership on \"Telecommunications of the Future\" (PE00000001--program \"RESTART\"). Not applicable. The authors declare no conflict of interest. ## Abbreviations

* 2D two-dimensional
* 2D-SCM two-dimensional spatial channel model
* 2G second-generation
* 3D three-dimensional
* 3 GPP 3 rd Generation Partnership Project
* 5G NR fifth-generation new radio
* ASIC application-specific integrated circuit
* CIR channel impulse response
* CPU central processing unit
* CTA cooperative-thread-array
* CUDA compute unified device architecture
* FIR finite impulse response
* ITU International Telecommunication Union
* DP double-precision
* DRAM dynamic RAM
* DSP digital signal processing
* FPGA field programmable gate array
* GPU graphics processing unit
* GSCM geometry-based stochastic model
* HLS high level synthesis
* LOS line-of-sight
* MIMO multiple-input multiple-output
* NLOS non-LOS
* SIMD single-instruction-multiple-data
* SM streaming multiprocessor
* SSP single-precision
* SSP small-scale parameter

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