## 5 Results and Discussion
### RO-PUF Metric  
This study examines the RO-PUF metric in terms of uniqueness, reliability, and uniformity. The uniqueness is calculated according to the difference in responses bits among FPGA boards (chips) using hamming distance (_HD_) calculated by Equation (1) [46], where \(c\) is the number of the chip, \(r_{b}\) is the number of response bits, \(R_{u}\) and \(R_{v}\) are the response bits of \(u\) and \(v\) boards being compared, \(HD(R_{u},R_{v})\) is a hamming distance between the response bits. \[Uniqueness=\frac{2}{c(c-1)}\sum_{u=1}^{c-1}\sum_{v=u+1}^{c}\frac{HD(R_{u},R_{v}) }{rb}\times 100\%, \tag{1}\]  
Digital circuit performance is influenced by environmental factors such as temperature, supply voltage, noise, etc. In this study, the performance of RO-PUF subsequent to temperature changes will be observed. The frequency of RO decreases when the temperature is increased [20; 47; 48]. Therefore, this work calculated reliability based on the consistency of pulses at different temperatures according to Equations (2) and (3), where \(k\) is the number of experiments on the same chip, \(R_{s}\) is the response bit from chip \(i\) at low temperature, \(R_{s,t}\) is the \(t\)-th sample of \(R^{\prime}\)s response bit from chip \(i\) at a higher temperature. \[HD\ Intra=\frac{1}{k}\sum_{t=1}^{k}\frac{HD(R_{s},R^{\prime}s_{t})}{rb}\times 1 00\%, \tag{2}\]  
\[Reliability=100\%-HD\ Intra, \tag{3}\]  
Uniformity is used to measure the ratio between \"1\" and \"0\" in a series of bit responses that determine the randomness of a specific chip's responses. The ideal uniformity is 50%, which means the number of \"1\" and \"0\" in a series of response bits is equal. This work calculated the uniformity by comparing the hamming weight (_HW_) of \"1\" on the same \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline  & **Scenarios** & **Pattern-1** & **Pattern-2** & **Pattern-3** & **Pattern-4** & **Pattern-5** \\ \hline Freq. range (MHz) & All ROs & 128.98 & 37.36 & 81.33 & 130.05 & 120.43 \\ (Smaller is better) & WR1 & 102.01 & 35.95 & 40.48 & 66.38 & 51.38 \\  & WR2 & 101.75 & 29.95 & 37.36 & 66.38 & 40.99 \\  & RH1 & 102.01 & 35.95 & 81.33 & 71.83 & 51.38 \\  & RH2 & 99.06 & 34.07 & 81.33 & 71.83 & 39.70 \\ \hline Standard Deviation (MHz) & All ROs & 37.18 & 10.42 & 19.57 & 23.90 & 23.73 \\  & WR1 & 38.92 & 10.00 & 11.55 & 15.98 & 14.22 \\  & WR2 & 40.64 & 9.66 & 11.72 & 16.99 & 13.32 \\  & RH1 & 37.80 & 9.91 & 18.67 & 16.95 & 13.31 \\  & RH2 & 38.34 & 9.64 & 20.32 & 19.56 & 12.43 \\ \hline Uniqueness (\%) & All ROs & 34.58 & 52.71 & 46.90 & 44.32 & 41.31 \\  & WR1 & 30.77 & 53.87 & 52.68 & 46.67 & 49.11 \\  & WR2 & 37.66 & 54.58 & 53.24 & 48.87 & 49.60 \\  & RH1 & 35.96 & 53.32 & 48.40 & 48.62 & 38.85 \\  & RH2 & 41.12 & 52.51 & 50.18 & 37.58 & 42.34 \\ \hline Reliability (\%) & All ROs & 99.47 & 98.93 & 99.15 & 99.04 & 99.12 \\  & WR1 & 99.37 & 98.64 & 98.95 & 98.88 & 99.18 \\  & WR2 & 99.51 & 98.21 & 98.76 & 99.18 & 98.85 \\  & RH1 & 99.28 & 98.74 & 98.61 & 98.99 & 98.63 \\  & RH2 & 99.20 & 98.56 & 98.34 & 98.75 & 98.58 \\ \hline Uniformity (\%) & All ROs & 38.82 & 46.22 & 47.55 & 43.81 & 58.59 \\  & WR1 & 34.05 & 45.91 & 46.65 & 33.39 & 54.66 \\  & WR2 & 33.78 & 43.04 & 41.85 & 41.32 & 47.02 \\  & RH1 & 34.86 & 47.13 & 45.77 & 44.48 & 58.19 \\  & RH2 & 33.12 & 42.08 & 43.64 & 33.93 & 62.98 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Statistical properties and RO-PUF metrics of logic arrangements and scenarios. chip, according to Equation (4), where \(R_{s,l}\) is the \(l\) bit from the sequence of response bits of a particular chip. \[Uniformity=\frac{1}{rb}\sum_{l=1}^{rb}R_{s,l}\times 100\%, \tag{4}\]  
This work generates response bits by providing all possible pairs' challenges where the maximum number of pairs is determined by a combination of 2 among \(n\) = 30 ROs, which results in \(r_{b}\) = 435 bits response. The differences in responses at low (25 \({}^{\circ}\)C) and high (50 \({}^{\circ}\)C) temperatures are used to determine reliability.