# Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices
## 1 Introduction
In [29], the authors discussed a different approach of the droop control for parallel-connected inverters based on active and reactive currents: handling active and reactive current instead of active and reactive power has the advantage that, in case of short circuiting, the control of active and reactive currents avoids the risk of an infinite current due to any non-zero active or reactive powers. Another example of application can be found in [30], in which the authors use a dynamic phasor-based model and a SOGI-FLL (Second-Order Generalized Integrator Frequency-Locked-Loop) to implement a droop-controlled parallel-connected inverter system. The master-slave control is composed of a master inverter that operates in a voltage-controlled mode while all the other inverters, the slaves, operate in a current-controlled mode. In [31], a master-slave application with a wireless communication and current sharing control among the inverters is described: it is a centralized technique in which all the inverters share information about the current shared among them. In [32], the parallelism control is applied to a UPS-based system. In [33], the authors analyzed a method to suppress the cross-circulating current based on virtual impedance. In [34], the authors presented a new wireless load-sharing control method that is designed to improve the performances of the parallel-connected inverters. They also defined the circulating current and proposed an adaptive droop-control method. Another type of control is presented and discussed in [35]; the authors realized a system controlled by local hardware managers and a central application manager connected with an optical fiber. Some approaches based on FPGA devices have also been studied: in [36], a controller developed on DSP (Digital Signal Processor) and FPGA for paralleling multiple inverters is presented. The controller is shared among the units and a synchronization scheme exploiting UPP (Universal Parallel Port) protocol is introduced to eliminate the synchronization delay. Moreover, in [37], an FPGA innovative control is proposed. The presented approach does not require communication among units, and it is applied to a system with only two parallel inverters. In this paper, a new approach to solve the several inverters parallelism problems and minimize the circulating current is presented. A new control method has been studied with the main purpose of controlling the system without any type of communication among the inverters and without introducing other structures such as a PID controller, as is typically described in literature [21; 34; 35]. For this purpose, the advantages of FPGA devices have been exploited: while conventional controllers operate sequentially, FPGAs are parallel processing devices, allowing the execution of complicated tasks in reduced time. Moreover, the FPGA hardware structure is not fixed, but can be reprogrammed by the user, adapting it to the application. In this scenario, FPGAs only control their own inverter and do not care about the operation mode of the other inverters (that can be operative or not) connected to the network. The proposed control method exploits high FPGA clock frequency to react to the circulating current as fast as possible. This feature allows for limitation of the circulating current peaks to prevent the damage of the devices. Moreover, the absence of communication between the inverters reduces the system complexity and costs, avoiding the realization of a dedicated communication line and protocol. The proposed control method permits one to realize scalable systems where modules, each one including an FPGA and an inverter, can be simply connected or disconnected to the system. The system has been developed and simulated with a model-based design approach compliant with automatic code generation.