# A Novel Decomposed Optical Architecture for Satellite Terrestrial Network Edge Computing
## 5 Scalability and Discussion
### Network Performance under Larger Network Scales  
Due to the limitation of the hardware amount, it is not easy to experimentally evaluate the network performance of the implemented computing prototype with decomposed hardware cubes at larger scales. Thus, exploiting the experimental measurements (like the NOS switching time and processing time of processor/memory cubes), we numerically assess the network performance of optical computing architecture with decomposed hardware in this part. The discrete event simulator OMNeT++ is applied to model the NOS-based flat interconnect network and decomposed hardware cubes. Scaling the decomposed computing architecture, the network topology in [26] is applied in the assessment to interconnect hardware cubes. Four different network scales and NOS with a corresponding port count are considered in this evaluation: 64 hardware cubes (eight-port NOS), 256 hardware cubes (16-port NOS), 1024 hardware cubes (32-port NOS), and 4096 hardware cubes (64-port NOS). As analyzed in Section 3, the grouping number \(M\) is configured as 4, while each group includes two to 16 hardware cubes. Considering the network performance and cost, the TRX bandwidth in each hardware cube is configured as 40 Gb/s based on numerical investigation in [25]. Benefiting from the local memory in the processor cube and on-board resource in the memory cube, no packet loss can be measured in the experimental demonstration. Therefore, the end-to-end access latency is used as performance criterion in the assessment. To study the end-to-end access latency of the NOS-based computing architec  
Figure 7: (**a**) Received ONSR of decomposed hardware under various operation currents; (**b**) Power compensation for none-error transmission ranging from four-port to 64-port NOS. ture with decomposed hardware, the Memory Cube Access Ratio (MCAR) is defined as the ratio of required memory size in memory cubes and the overall memory size required by processor cubes. The access instruction is sent from the processor cubes following existing computing structures [32]. Based on the spatial and temporal characteristics of data access, long-tailed Pareto distribution is applied to generate access instruction. Same as the experimental investigation, each network packet is configured as 512 bit-length. While a memory cube processes the data access instruction, the target cache line is first fetched to the processor cube. Then, the remaining data of the same data page (4096 bytes) are fetched to source the processor cube to avoid repeat remote memory cube access [33]. In the assessment, the network packets carrying target data are assigned with higher priority. Figure 8a reports the end-to-end access latency of the target data line with different network scales and different locations of decomposed hardware cubes. There are two kinds of locations: the source processor cube and destination memory cube are located inside the same rack (intra-rack) and across different racks (inter-rack). It is illustrated that, with the MCAR of less than 0.9, the intra-rack and inter-rack locations perform similar end-to-end access latency with four different scales. With a network scale of 4096 decomposed hardware cubes, intra-rack access latency of 130.8 ns and inter-rack access latency of 240.9 ns are obtained. When the MCAR is larger than 0.9, the end-to-end access latency dramatically increases scaling the optical computing architecture with decomposed hardware cubes. However, while increasing decomposed hardware from 64 cubes to 4096 cubes, the intra-rack end-to-end access latency increases by 12.6% with the MCAR of 0.9 (148.5 ns for 4096 decomposed hardware cubes), compared with 15.8% more access latency for inter-rack interconnection (265.7 ns for 4096 decomposed hardware cubes). Besides the target data line access, the end-to-end access latency for data page access is also numerically investigated as shown in Figure 8b.