## 3 Proposed LDPC Architecture
### Co-Design of the Proposed Architecture  
Our work leverages a hardware-software co-design approach for the proposed 5G-NR LDPC decoder. We describe VHDL's decoder hardware for efficient implementation on an FPGA by AMD/Xilinx from San Jose, California, USA. The software stores the communication channel logic, allowing for future modifications and adaptations through software updates. This separation of concerns optimizes both hardware performance and software maintainability.  
Our design verification leveraged both ModelSim SE 10.6 software and Vivado 2020.2. We prefer Vivado due to its hardware-aware co-simulation capabilities, which are specifically optimized for Xilinx FPGA and SoC designs. Vivado facilitates the creation of a shared library containing the simulation kernel, enabling its execution directly within the Simulink environment. This eliminates the need for a separate ModelSim process during co-simulation, resulting in faster execution. The shared library and in-context execution contribute to Vivado's performance advantages.  
Figure 5 illustrates the Simulink-generated block representing the proposed 5G-NR LDPC decoder. This block interacts with an HDL Design DLL (Dynamic-Link Library). The DLL is a shared library that contains our decoder's compiled VHDL model. We use Simulink's \"From Workspace\" blocks (Shamt, R_LLRs, Lyr_Ctrl, In_adr) to assign input values from the MATLAB workspace to the DLL, facilitating seamless data exchange during co-simulation. The LDPC decoder stores the output of the VHDL design in Lyr_RAM within the VHDL code, represented by the Up_LLR's port. Before assigning this data to the MATLAB workspace for further processing (decision and interpretation), it must undergo reshaping.  
Figure 5: HDL Design DLL generated by Simulink for co-simulation process.  
We co-simulated the decoder for two code rates, \(1/3\) and \(2/3\), aligned with BG1. The simulation results are presented in Figure 6. We also compare our findings with the work in [13; 14; 15].  
The proposed LDPC decoder architecture exhibits significant advancements in decoding complexity and communication channel robustness compared to prior works.  
A gain of up to 0.2 dB in SNR for a BER of \(10^{-3}\) is achieved based on the rate \(1/3\), which is better than what was reported in [13], and a gain of 0.1 dB for a BER of \(10^{-5}\) is seen in Figure 6b. This reduction in decoding complexity allows for lower power consumption and potentially higher decoder throughput.  
It is important to acknowledge that previous studies [14; 15] haven't explored the code rate of \(2/3\) with the maximum expansion factor of 384. Therefore, we present an estimated comparison based on the available data.  
Typically, the code rate of \(1/2\) employed by reference [14] is expected to outperform the rate of \(2/3\) in terms of error correction capability. Our design, which uses a \(2/3\) code rate, achieves an SNR gain of up to 0.12 dB at a BER of \(2\times 10^{-3}\) (Figure 6a). Furthermore, compared to reference [15], which utilizes a \(2/3\) code rate with an expansion factor of \(Z=104\), our design achieves a superior SNR gain of 0.59 dB for the same BER. These results highlight the capacity of our decoder, even with a higher code rate and potentially lower error correction capability.  
Furthermore, we observe a remarkable reduction in decoding iterations. Our design requires only 6 iterations, compared to 15 and 20 iterations reported in [14; 15], respectively.