## 4 Results and Discussion  
The metrics used to evaluate and assess the architecture's performance are estimated by calculating the reconstructed image's Peak Signal-to-Noise Ratio (PSNR), Structural Similarity Index (SSIM), and Compression ratio (CR). The power, delay, area, PDP, and PSNR of various architectures based on DCT architectures are also assessed in this section. Implementation of the Proposed Architecture for Image Processing ApplicationThe implementation adopts standard-cell-based ASIC or semi-custom design built on preassembled library cells. Custom-designed standard cells are included in the library after being created. A few standard cells are available as a file in the IEEE library format. Through \"place and route\" Computer Aided Design (CAD) tools, these cells are subsequently used in the design by being arranged in rows and wired together. These cells are arranged physically and validated for specific process nodes. The Verilog HDL is used for the functional design in the RTL, which is mapped through a logic synthesis process into preassembled cells. The designs proposed and from the literature are verified for their functionality by applying random inputs and examining the actual and anticipated results. It was observed that the anticipated and actual results matched for each design. The RTL verification of the design was performed using Cadence's incisive tool. The toggle information of all inputs and outputs is captured by a Value Change Dump (VCD) file generated during the design's functional verification. The VCD file is given as one of the inputs to the logic synthesis process. Logic synthesis is the process that transforms the technology-independent RTL into a technology-specific gate-level netlist optimized for a set of predefined constraints by using the process library. Logic synthesis starts with the RTL design, standard cell libraries, and design constraints. It completes with a gate-level netlist, mapped to the standard cell library that is efficient in terms of power, delay, and area. The RTL defines how the design functions. The process library describes the logic gates' physical, electrical, and logical information. The logic synthesis Electronic Design Automation (EDA) tool converts the RTL into an optimized netlist. The process library serves to map this netlist into a technology-specific netlist. The Genus tool of Cadence with gpdk 90 and 45 nm standard cell libraries is used for the logic synthesis of the designs  
Figure 16: Decoding block of IDCT Image Compression. proposed and from the literature. On completion of the logic synthesis, the next step of the ASIC design flow is physical design. The 16-bit integrated computational units are designed, implemented, and synthesized using 45 nm gpdk technology libraries. The statistical parameter PSNR, as defined in Equation (2), calculates the ratio of the image strength to the noise power that affects the image quality. \[PSNR=10\ log_{10}\frac{Max^{2}}{MSE} \tag{2}\]  
where \(Max\) is the maximum value of the image pixel. \(MSE\) denotes the Mean Squared Error (MSE) defined by Equation (3). \[MSE=\frac{1}{mn}\sum_{x=0}^{m-1}\sum_{y=0}^{n-1}[I_{o}(x,y)-I_{r}(x,y)]^{2} \tag{3}\]  
where m and n denote each output image's number of rows and columns and \(I_{o}\) = Original image and \(I_{r}\) = reconstructed image. A PSNR of higher value indicates that the reconstructed image is of better quality. The SSIM that predicts the reference and noisy image quality is another quality metric that is used in this research denoted by Equation (4).