# Area and Performance Estimates of Finite State Machines in Reconfigurable Systems
## 2 Related Works
### Estimates of FSMs
#### 3.2.3 Other Estimates for FSMs
[CrossRef]
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* (7) [PERSON]; [PERSON] VersaPower: Power estimate for diverse FPGA architectures. In Proceedings of the International Conference on Field-Programmable Technology, Seoul, Republic of Korea, 10-12 December 2012; pp. 229-234. [CrossRef]
* (8) [PERSON]; [PERSON] Optimized Sequential State Encoding Methods for Finite-State Machines in Field-Programmable Gate Array Implementations. _Appl. Sci._**2024**, 14, 5594. [CrossRef]
* (9) [PERSON]; [PERSON]; [PERSON]; [PERSON] MIS: A multiple-level logic optimization system. _IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst._**1987**, 6, 1062-1081. [CrossRef]
* (10) [PERSON]; [PERSON]; [PERSON] A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs. In Proceedings of the 33 rd annual Design Automation Conference, Las Vegas, NV, USA, 3-7 June 1996; pp. 730-733. [CrossRef]
* (11) [PERSON] [PERSON]; [PERSON]; [PERSON] ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. _IEEE Trans. Very Large Scale Integr. (VLSI) Syst._**2000**, 8, 392-400. [CrossRef]
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* (13) [PERSON]; [PERSON] [PERSON]; [PERSON] [PERSON]; [PERSON] Enhancing Delay-Driven LUT Mapping with Boolean Decomposition. _IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst._**2024**, _in press._ [CrossRef]
* (14) [PERSON]; [PERSON] A symbolic RTL synthesis for LUT-based FPGAs. In Proceedings of the 12 th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, Liberec, Czech Republic, 15-17 April 2009; pp. 102-107. [CrossRef]
* (15) [PERSON]; [PERSON]; [PERSON] Area estimate of LUT based designs. In Proceedings of the International Conference on Electrical, Electronic and Computer Engineering (ICEEC'04), Cairo, Egypt, 5-7 September 2004; pp. 39-42. [CrossRef]
* (16) [PERSON]; [PERSON]; [PERSON]; [PERSON] Optimal implementation of combinational logic on look-up tables. In Proceedings of the Ph.D. Research in Microelectronics and Electronics, Istanbul, Turkey, 22 June 2008; pp. 153-156. [CrossRef]* (17) [PERSON] Balanced Power, Performance and Area Transformation Procedure for Finite State Machines. In Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics (SMC), Prague, Czech Republic, 9-12 October 2022; pp. 2313-2318. [CrossRef]
* (18) [PERSON]; [PERSON]; [PERSON]; [PERSON] A unified approach for FSM synthesis on FPGA architectures. In Proceedings of the Twentieth Euromicro Conference. System Architecture and Integration, Liverpool, UK, 8 September 1994; pp. 660-668. [CrossRef]
* (19) [PERSON]; [PERSON]; [PERSON] A technology mapping of FSMs based on a graph of excitations and outputs. _IEEE Access_**2019**, \(7\), 16123-16131. [CrossRef]
* (20) [PERSON] _Logic Synthesis and Optimization Benchmarks User Guide_; Version 3.0; Microelectronics Center of North Carolina (MCNC): Research Triangle Park, NC, USA, 1991. Available online: [[https://ddd.fit.cvut.cz/www/pri/Benchmarks/LGSynth91.pdf](https://ddd.fit.cvut.cz/www/pri/Benchmarks/LGSynth91.pdf)]([https://ddd.fit.cvut.cz/www/pri/Benchmarks/LGSynth91.pdf](https://ddd.fit.cvut.cz/www/pri/Benchmarks/LGSynth91.pdf)) (accessed on 13 December 2024). * (21) [PERSON]; [PERSON] Synthesis of multiple level logic from symbolic high-level description languages. In Proceedings of the IFIP International Conference on VLSI, Munich, Germany, 16-18 August 1989; North-Holland: New York, NY, USA, 1989; pp. 187-196. **Disclaimer/Publisher's Note:** The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s).