# An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder
## 3 The Proposed Decoder Architecture  
The layered HOMS algorithm presented in Algorithm 1 is used to implement the suggested QC-LDPC decoder architecture for 5G New Radio (NR) communication systems. In this work, we consider the BG1 matrix of size \(m_{b}\times n_{b}=24\times 46\) and the code rate of \(1/2\). The expansion factor \(Z=192\) corresponds to a PCM \(\mathbf{H}\) of size \(M\times N\), with \(M=Z\cdot m_{b}=192\cdot 24=4608\) and \(N=Z\cdot n_{b}=192\cdot 46=8832\). As mentioned before, the 5G LDPC decoder is irregular [9] and the check node degree in the BG1 changes widely from 3 to 19. Let \(d_{\text{cmax}}\) indicate the maximum check node degree. Since each column of \(\mathbf{H}\) contains precisely one non-negative element in each layer, we further define one row of \(\mathbf{B}\) within one decoding layer. It should be noted that BG1 is constructed such that \(\mathbf{B}\) can be separated into \(L=m_{b}\) horizontal decoding layers. The decoder's parallelism level is equal to the expansion factor \(Z\). The architecture of the proposed LDPC decoder is depicted in Figure 1. Its architecture consists of a network of multiplexers (MUXes), a large number of Variable Node Units/A Posteriori Blocks (VNUs/APBs), Check Node Units (CNUs), and two memory blocks for AP information (\(\tilde{\gamma}_{n}\)) and CTV messages (\(\beta_{m,n}\)). The MUX block's task is to select between channel intrinsic messages (\(\gamma_{n}\)) and AP messages (\(\tilde{\gamma}_{n}\)) updated from the preceding layer. It is important to understand that intrinsic messages are only used during the initialization stage. The intrinsic signals of \(\tilde{q}\)-bits quantization are buffered before being stored in the AP Memory Block (AP-MB). The detail of the AP-MB will be discussed in a later subsection. There are \(n_{b}\) simultaneous outputs of the AP-MB, each representing \(Z\) values of \(\tilde{q}\)-bits. The decoded bits are read from the AP-MB when the maximum number of iterations is reached. AP messages are read from the AP-MB and then delivered to the Read Permutation Units (Read-PUs) at each decoding layer. There are \(n_{b}\) parallel Read-PUs that are used to reorganize the data according to the processed layer, ensuring processing by the appropriate following processing units. The Read-PUs select \(d_{\text{cmax}}\) AP combinations among \(n_{b}\) inputs, which depend on the positions of the non-negative entries of the BG1 matrix's current layer. For example, the first four layers of the BG1 matrix have \(d_{\text{cmax}}=19\) non-negative elements, and the fifth layer has only four non-negative elements, thus, (\(d_{\text{cmax}}-4\)) elements are set to zero. In order to enhance the operating frequency, we apply the pipeline technique at Read-PU outputs. The Write Permutation Units (Write-PUs) perform the reverse operation of Read-PU. One layer is executed in two consecutive clock cycles, and each clock cycle involves the processing of two layers in the base matrix by the two pipeline stages. After pipelining, Read-PU output data are transferred into Read-Shifter Blocks (R-SBs). R-SBs should be used to design the data flow in circular shifts (cyclic) in line with the relevant shift factors. In the proposed architecture in Figure 1, we use \(d_{\text{cmax}}\) R-SB blocks in parallel, enabling high-processing throughput. Each of them has \(Z\) inputs and \(Z\) outputs. Figure 2 illustrates the detailed working of right-shifting by the two positions rule of R-SB block with 60 elements of \(\tilde{q}\)-bits. The Write-Shifter Blocks (W-SBs) perform a reverse function compared to the R-SBs. VTC messages \(\alpha_{m,n}\) are computed or AP values \(\tilde{\gamma}_{n}\) can be updated via Variable Node Units/A Posteriori Blocks (VNUs/APBs). How these blocks work in detail will be mentioned in the next subsection. The output message values of the VNUs/APBs are transmitted in parallel \(\tilde{q}\times Z=1152\) bits updated for the next layer and saturating to \(q\)-bits.