## 6 Results and Comparison
### Results Comparison  
#### 6.4.1 Equalizer Module  
Table 5 presents a comparison in terms of utilized resources and the performance of the proposed equalizer architecture with relevant state-of-the-art implementations, which provide complete solutions to generate estimated symbols. It is worth noting that most published works present partial implementations of MIMO equalization (for example, limited only to matrix inversion). The implementations of [24] and [25] are dedicated for \(2\times 2\) pre-coded and \(4\times 4\) spatially-multiplexed (SM) MIMO systems, respectively. In [26], a specific instruction set processor (ASIP) dedicated to MIMO MMSE-IC equalization is introduced. Compared to our proposed architecture, the ASIP architecture so-called _EquASIP_ has identical computational resources and supports the same flexibility parameters as our design. In order to make a fair comparison, our design has been synthesized with the same target technology in the implementation being compared. \begin{table}
\begin{tabular}{c c c} \hline \hline \multirow{2}{*}{**Modulation Type**} & \multicolumn{2}{c}{**Throughput (Mega LLRsper Second)**} \\ \cline{2-3}  & **FPGA @ 293 MHz** & **ASIC @ 520 MHz** \\ \hline QPSK & 195.5 & 347 \\ \hline
16-QAM & 234.6 & 416 \\ \hline
64-QAM & 195.5 & 347 \\ \hline
256-QAM & 138 & 244.7 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Throughput results of the proposed NISTC-based demapper architecture. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**System Configuration**} & \multirow{2}{*}{**Reference**} & \multirow{2}{*}{**Target Device**} & \multirow{2}{*}{\begin{tabular}{c} **Operating** \\ **Frequency** \\ **(MHz)** \\ \end{tabular} } & \multicolumn{2}{c}{**FPGA Resources**} & \multirow{2}{*}{\
\begin{tabular}{c} **Clock** \\ **Multipliers** \\ \end{tabular} } & \multirow{2}{*}{
\begin{tabular}{c} **Throughput \\ **Cycles** \\ \end{tabular} } \\ \cline{3-4} \cline{6-7}  & & & & 140 & & 14166 & 103 & 388 & 17.31 \\ \cline{3-4} \cline{6-7} Block Fading & **This work** & & 91 & 4604 & 12 & 784 & 5.57 \\ \hline
4 \(\times\) 4 SM & [26] & Virtex-V & 130 & 3174 & 11299 & 14 & 13 & 10 \\ \cline{3-4} Block Fading & **This work** & & 146 & 2029 & 6536 & 12 & 13 & 11.23 \\ \hline
4 \(\times\) 4 SM & [26] & Virtex-V & 130 & 3174 & 11299 & 14 & 234 & 0.56 \\ \cline{3-4} Fast Fading & **This work** & & 146 & 2029 & 6536 & 12 & 173 & 0.84 \\ \hline
2 \(\times\) 2 & [24] & & 60 & 817 & 2715 & 60 & 1 & 120 \\ \cline{3-4} Precoding Quasi-Static & This work & & 146 & 2029 & 6536 & 12 & 3.25 & 45 \\ \hline
2 \(\times\) 2 SM & [26] & Virtex-V & 130 & 3174 & 11299 & 14 & 89 & 1.46 \\ \cline{3-4} Fast Fading & **This work** & & 146 & 2029 & 6536 & 12 & 63 & 2.32 \\ \hline
2 \(\times\) 2 SM & [26] & Virtex-V & 130 & 3174 & 11299 & 14 & 8 & 16.25 \\ \cline{3-4} Block Fading & **This work** & & 146 & 2029 & 6536 & 12 & 7 & 20.86 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Comparison summary of the proposed equalizer with relevant state-of-the-art implementations. Starting with the architecture design in [25], which implements a \(4\times 4\) MIMO SM detector for the 802.11n standard with a throughput of 17.3 M vectors, when comparing with our work, its throughput outperforms by 3.1-times. However, this increased throughput comes at the cost of more than three-times more FPGA slices and 8.6-times more multipliers. Moreover, in contrast to our architecture, the design in [25] is not flexible for variable antenna dimensions, channel selectivity and iterative equalization. In [24], 2 \(\times\) 2 MIMO equalization includes the pre-coding stage, where the channel coefficient matrix is converted into the 4 \(\times\) 4 matrix. Applying this technique using our architecture imposes more operations and, hence, lessens the computing speed of the equalization coefficients. Indeed, for the quasi-static channel, where coefficients are computed once for a data frame, the throughput is not greatly affected.