# A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits
## 7 Challenges of FAST
### On-Chip Clock Generation for FAST  
FAST is essential for HDD and SDD detection. But in the case of automatic test equipment (ATE), the test clocks of higher frequency may be subject to change because of probe resistance, tester skew, etc. [50], thus affecting the accuracy of the clock frequency. The delay between the launch and the capture clock edge is the clock cycle period that is used for at-speed testing. The shift clock cycle can be a slow-speed clock and does not affect the testing performance. This is because the shift mode only initializes the flipflop values. The transition is launched and propagated from the source scan cell by pulsing the launch clock and captured at the destination scan cell by pulsing the capture clock. If the circuit works fine, the transition will reach the destination flip flop in time, and the correct value will be captured. Hence it is enough for the launch and capture cycle alone to be in operating frequency to validate the delay test. Moreover, if the shift clock frequency is high, it will lead to unnecessary yield loss. This is because, during shift operation, all the scan cells are configured in shift mode and will toggle together. The combinational logic also toggles along with them. This leads to IR drop, and the circuit may malfunction during shift mode, and correct values may not be shifted properly. Hence slow speed clock is used for shifting operation. Providing a high-precision launch and capture clock forat-speed testing from the tester equipment requires a high cost. This disadvantage can be eliminated by using on-chip clocks. The PLL-based on-chip clock generation generates a higher clock frequency, which can be used for FAST testing [51; 52]. But this isn't easy to implement because the PLL has to be reset before applying each pattern, and this slows down the testing and is unsuitable for large industrial designs. Also, it generates only specific multiples of the PLL output frequency. In [53], the pulse programmable selection generator and multiplexer are used to create the desired launch and capture cycle. But the disadvantage here is the huge overhead area. The launch and capture clock generation (LCCG) method is proposed to overcome the difficulties faced in PLL. This architecture consists of a delay control stage that can be embedded anywhere in the scan chains [54]. The required frequencies are obtained by sending the control information with the test patterns. Also, the delay control stage consists of two different delay units such that one delay unit has more delay than the other, and a reference signal is taken as an input. The difference in the delay between the two delay units is used to generate the required launch and capture clock. This supports LOC and LOS-based test applications and produces the needed frequencies for the FAST test, unlike the PLL-based [51] clock generation. But the problem here is that the delay control stage may be subjected to PV or have SDDs, causing frequency inaccuracies. The oscillator controller, along with the LCCG circuits, is used to address this issue [55]. Here, the generated clock from the enhanced LCCG circuit is measured for accuracy before it is used for testing applications by the oscillator circuit. Though the error percentage for generating the expected clock signal in the presence of process variations is lower than in the LCCG technique, a more accurate clock generation is required to reduce the maximum percentage error, which could be a future research direction. On-Chip Clock Generation for Asynchronous Circuit  
The need to handle massive data as the internet grows necessitates power-efficient processors. The asynchronous design is preferred for not wasting much power on switching activity and handling clock tree power. An asynchronous or self-timed processor called AnARM was developed for this purpose. These asynchronous circuits must also meet the timing constraint in order to function properly. Because of the diverse design style of the asynchronous circuits, it is difficult to test the circuit.