# Towards Large-Scale Fast Reprogramable SOA-Based Photonic Integrated Switch Circuits
## 7 Discussion  
The projected performance of recently realized medium-scale InP photonic fast switching circuits have been presented. This helps in defining the strategies towards large-scale InP photonic integrated circuits (PICs) switches in relation to figures like connectivity, physical layer performance, power consumption, distributed on-chip monitoring, and interconnectivity. High-radix 4 \(\times\) 4 SOA-based switch elements have been efficiently configured in multistage networks to enable high connectivity with a limited number of stages, including 2 \(\times\) 2 SOA-based switches at the input and at the output. Three switch stages provide a good compromise between optical wiring complexity, signal integrity, and control complexity. By using active-passive multi-stage SOA monolithic integration we have enabled switching matrices with up to 480 components, connecting 16 inputs to 16 outputs [24] (Figure 1a). This can potentially route massive bandwidth signals independently of signal wavelength and in a number of multiplexed wavelength channels. We have demonstrated that orders of magnitude increases in reconfigurability is possible when the use of wavelength division multiplexing is combined with on-chip wavelength selective routing: The \(8\times 8\) InP integrated cross-connect provides a connectivity of up to 64 input and output channels [27] (Figure 2a). Further increases in connectivity are possible but require careful design of the chain of cascaded SOAs and losses per stage. Also, reduced losses at the input of the first SOA stage must be provided for low signal degradation. Complementary approaches for achieving large-scale integrated optical switch matrices require a complex mesh of interconnection which is not well supported by single layer waveguides as conceived so far. Further scaling motivates more sophisticated optical wiring. Two strategies for achieving higher connectivity are here highlighted. The InP-Membrane-On-Silicon (IMOS) platform is a photonic integration researching InP-based membranes on top of silicon chips [48]. This approach represents a valid example of how to shrink size, while retaining gain and enabling future integration on complementary metal-oxide semiconductor (CMOS) circuitry, through a low thermal conductivity polymer layer. Also, monolithic multi-layer InP integration can be used to enable three-dimensional connectivity for large-scale photonic integrated circuits, potentially offering a step change in optical circuit connectivity and removal of crosstalk at the top-bottom waveguide intersections [49; 50]. As the data throughput is not directly linked to the actuation energy, such broadband switches are expected to enable considerable energy savings as the line-rate increases [28]. The involved electrical input energy for chip reconfiguration is of the order of a few watts [24], but further electrical power reduction is desirable. New architectures and technologies must be conceived that provide packet-scale switching functionality while being power efficient. The combination of SOA technology and InP electro-optic effect offers the opportunity of achieving potentially low power consumption and fast switching in photonic integrated circuits based on ring resonators: the first InP third-order ring resonator-based switch matrix fabricated on active-passive integrated InP platform [45] is characterized by an on-state electrical power consumption of only tens of \(\mu\)W per switch element, which is four order of magnitude lower than in a conventional forward bias SOA-gate. The worst case 6 dB losses between the paths are expected to be dominated by the off-state losses which may be reduced with further building block optimization.