## 2 Device Setup and Mechanism  
The proposed HEMT device was generated on a conventional GaN-on-Silicon wafer with an AlGaN/GaN heterojunction on the top. The configuration details of this wafer can be found in Reference [22] and also in Figure 1a. Figure 1: The schematic (**a**) cross-section of proposed high-electron-mobility transistor with a local charge compensation trench (LCCT-HEMT) and (**b**) illustration of local charge compensation (red arrow represents electric field (E-field)). The specification of the proposed device is listed in Table 1. It should be noted that besides the conventional source, drain, and gate, the device owns a special LCCT just adjacent to the gate. This LCCT could be formed by a typical etching process during which the ion bombardment injects extra negative charges into the Silicon Nitride (SiN). In the meantime, the recessed SiN relieves piezoelectric stress itself, leading to a further reduction of polarization charges in AlGaN. This procedure brings equally more negative charges into the SiN, whereas the precise negative charge distribution in SiN layer is hard to tell. However, the etching speed can be stabilized properly, which means the negative charge is introduced at a constant speed with a constant introducing rate. Thus, for simplification, a uniform distribution of such charges is assumed in this research, which is reasonable according to the Reference [26] but still requires further study. Besides, other charges and trap settings in each layer could be found in the original works of UTB-HEMT, extracted from experiments [22; 23]. The fabrication process of the proposed LCCT-HEMT is schematically depicted in Figure 2. The whole procedure could commence with a UTB wafer. Thereafter, the ohmic contacts could be formed by the physical vapor deposition (PVD), followed by the gate etching process. Here, the etching rate of the AlGaN barrier could be easily distinguished from the rate of SiN passivation layer, meaning the etching hurt could be minimized by properly designing the etching recipe. Then, the gate dielectric and gate metal could be deposited by atomic layer deposition (ALD) and PVD, respectively. Finally, the LCCT could be fabricated by elaborately etching the passivation layer to introduce the negative charges. Furthermore, some other materials that could introduce negative charges into the structure, such as ALD-grown oxide, could alternatively be chosen. \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Value and unit** \\ \hline Device length & \(L_{\text{D}}\) = 19 μm \\ Device width & \(W_{\text{D}}\)= 50 μm \\ Device height & \(H_{\text{D}}\)= 3.4 μm \\ Polarization charge & \(\sigma_{\text{P}}\) = \(2.8\times 10^{12}\) cm\({}^{-2}\) \\ SiN interface positive charge & \(\sigma_{\text{SiN}}\) = \(1.4\times 10^{12}\) cm\({}^{-2}\) \\ SiN height & \(H_{\text{SiN}}\) = 80 nm \\ LCCT length & \(L_{\text{T}}\) = 0 to 10 μm \\ LCCT depth & \(D_{\text{T}}\) = 0 to 80 nm \\ Gate length & \(L_{\text{G}}\) = 2 μm \\ Gate height & \(L_{\text{W}}\) = 90 nm \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Device specifications. Figure 2: The E-field distribution along the channel in LCCT-HEMT when the drain voltage is 800 V.  
In this sense, compared with the conventional UTB HEMT, the proposed LCCT-HEMT exhibits the capability of E-field redistribution in a high drain bias, thus enabling higher BV of the device, as shown in Figure 3a,b. Furthermore, a longer and/or deeper LCCT offers higher capability of E-field redistribution, resulting in a smoother depletion region and higher BV, as shown in Figure 3c. As shown in Figure 1b, the recessed LCCT exerts two main effects.