## 1 Introduction  
The deployment of High Performance Switches and Routers (HPSRs) capable of managing huge aggregated bandwidth is becoming mandatory to address traffic growth-rate projections [1]. An HPSR is composed of one or more racks, each one containing a set of Line Cards (LCs). Each LC hosts an HPSR bidirectional port that connects the node to an outer link towards another node of the network. The LCs also host the hardware implementing low-layer functions (transceiver, framer, _etc._) and other network-processing functions (address lookup, packet classification, buffer management, scheduling, _etc._). Internally to the HPSR, LCs are interconnected via a backplane [2]. The bandwidth of the internal LC-to-LC connections supported by the backplane should be roughly equal (except for some small extra bandwidth due to internal signaling) to the line speed of the LCs: in this paper we consider 10 Gbit/s line-speed and, thus, also backplane bandwidth. The backplane can be static, connecting LCs to a separated switching-fabric module, or it can be dynamic, performing the function of a switching fabric itself. We are interested, in this work in the dynamic switching-backplane case. (In some cases some LCs, instead of having a single 10 Gbit/s port, may be equipped by multiple smaller-bandwidth physical ports (e.g., 4 \(\times\) 2.5 or 10 \(\times\) 1 Gbit/s, _etc._). This usually does not have an impact on the backplane, since traffic grooming of low-granularity tributaries into high-granularity flows is usually managed within the LCs.).  
In order to overcome current electronic-backplane limitations, Optical Interconnections (OI) represents an attractive alternative: attenuation does not increase at high bit-rates; optical transmission lines do not suffer the crosstalk impairment, _etc._ Generally speaking, OI can be deployed between racks (rack-to-rack), between line-cards inside a rack (card-to-card or backplane), between chips of a line-card (chip-to-chip), or even between the different cores of a single chip (on-chip). In this context, we decided to investigate the card-to-card OI. Literature presents some proposals of all-optical backplane interconnection fabrics with Semiconductor Optical Amplifiers (SOAs) and Arrayed Waveguide Gratings (AWGs) as implementation technologies [3]. In this study, we deal with Ring-Resonators [4] (RRs), typically used for filtering and routing [5], as the basic switching element for LCs interconnection. In [6], authors propose different RR-based backplane fabrics focusing on a power-budget scalability analysis. In our work, (1) we propose a backplane fabric made of a cascaded RR; (2) we introduce a new methodology for scalability analysis based on accurate transfer function evaluation; and (3) we confirm the feasibility of the architecture via analysis of the bit error rate (BER) for transmission of an On-Off Keying (OOK) Non-Return-to-Zero (NRZ) signal at 10 Gb/s. This work is an extension of [7], in which BER analysis was not available. Our procedure goes beyond the simple power budget and Cross-Talk (XT) analyses since it accounts for waveguide dispersion effects, which may have a non-negligible impact in all-optical backplanes.