# Fourier Singular Values-Based False Data Injection Attack Detection in AC Smart-Grids
## 4 Case Studies
### Simulation Results of Assumed Case Studies
The simulation outcomes of the mentioned state are explicated in Figure 4:6  
In this section, Figure 9 displays the output voltage of the ISMG. Loads current is depicted in Figure 4:7 Figure 9 shows FSVs of signal in the proposed expression and via choosing a threshold as 40, it is able to observe that the declared mechanism can successfully identify the cyber-attack. Response time of the expressed scheme at the time of FDI attack is depicted in Figure 4:8 As shown, the speed of the proposed scheme is allowable and can detect the attack less than 10 ms from the time which the FDIA has occurred. **Case study VI: Instability stems from manipulating the load's current reference waveform (manipulating shared current between unit II and III)**  
In this case, the efficiency of the FSVs in FDIA detection is considered by manipulating the load's current reference signal to simulate the FDIA (manipulating shared current between unit II and III). At t = 0.5 s, FDI attack began and at t = 1 s, FDI attack eliminated. To simulate the attack, 20% of amplitude of current is increased in reference signal in the controller by the cyber-attack. The simulation results are demonstrated in Figure 4:9  
In this case, Figure 10a displays the output voltage of the ISMG. Loads current is explicated in Figure 10b. Figure 10c-e display the DG\({}_{1}\), DG\({}_{2}\) and DG\({}_{3}\) current, respectively; it has been shown that the generation current of any unit increased during the attack but the load is constant. Figure 10f illustrates FSVs of signal in the proposed expression and by choosing a threshold as 40, it is able to observe that the declared mechanism is able to successfully identify the attack. Response time of the expressed scheme at the time of FDI attack is depicted in Figure 10g. As shown, the speed of the proposed scheme is allowable and can detect the attack less than 10 ms from the time which the FDIA has occurred. Figure 5:0 Instability stems from manipulating a voltage signal that is measured by smart sensor (ISMG’s voltage increased): (**a**) ISMG’s voltage; (**b**) Loads current; (**c**) FSVs of signals; (**d**) Time response of FSV’s scheme (FDIA is initiated at t = 0.5 s and is omitted at t = 1 s). Figure 5:1 Cont. Figure 5:2 _Cont._  
**Case study VII: Instability stems from manipulating current signal that is measured by smart sensor**  
Manipulating shared current between unit II and III. In this case, the efficiency of the FSVs in FDIA detection is considered via injecting malicious data on current waveform that is measured by smart sensor (manipulating shared current between agent II and III). At t = 0.5 s, FDI attack began and at t = 1 s, FDI attack eliminated. To simulate the attack, the measured current of the ISMG, which is measured by sensor, changed in sensor by the cyber-attack, and amount of current is shown less/more of the real value. The simulation results are represented in Figure 5:3 In this case, Figure 11 displays the ISMG output voltage. Loads current is exposed in Figure 11b. Figure 11c-e display the DG\({}_{1}\), DG\({}_{2}\) and DG\({}_{3}\) current, respectively; it can be seen that the generation current of DG\({}_{2}\) increased during the attack but the load is firm and DG\({}_{1}\) produced current against the attacked current to omit more current that generated via DG\({}_{2}\). Figure 11f shows FSVs of waveform in the proposed expression and via choosing a threshold as 40, it is able to observe that the declared mechanism is able to successfully detect the attack. Response time of the expressed scheme at the time of FDI attack is represented in Figure 11g. As shown, the speed of the presented scheme is allowable and can detect the attack less than 10 ms from the time which the FDIA has occurred.