# Automatic Configurable Hardware Code Generation for Software-Defined Radios+
## 6 Hardware Model Using Finite State Machines
### FSM Optimizations
#### 6.2.1 First Optimization
In the example, \(SG=0\) therefore the FSM does not have \(s_{sg}\) and it will transition directly from \(s_{0}\) to \(s_{k}\) state type. The \(s_{k}\) has \(ET(v)\) sub-states (i.e., denoted in a dotted transition line between \(s_{k}\) and \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**State Type** & **Time Delay** & **Multiplicity** & **Has Transition Loop?** & **Condition for Next State Transition** \\ \hline \(s_{0}\) & \((i|CP_{i,c}=1)+1\) & \([1..^{*}]\) & Yes & \(v=1\) \\ \(s_{sg}\) & \(SG\) & \([0..^{*}]\) & Yes & \(sgc=SG\) \\ \(s_{k}\) & \(ET(v)\times RV(v)\) & \(1..1\) & No & \(jc<RT(v)\) or \(jc=RV(v)\) \\ \(s_{fg}\) & \(FG\) & \([0..^{*}]\) & Yes & \(fgc=FG\) \\ \(s_{ig}\) & \(IG\) & \([0..^{*}]\) & Yes & \(igc=GC\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Types of states used for iterative optimization. where \(k=\{0...ET(v)-1\}\)) which repeat \(RV(v)\) times. The last sub-state \(s_{et-1}\) of state type \(s_{k}\) can use one of the two transitions, the first one leads to state type \(s_{fg}\) that creates time delay of \(FG\) and the second transition directs the FSM to \(s_{ig}\) where it delays execution for \(IG\) clock cycles. In our example, the \(s_{k}\) type undergoes \(ET(y)\times RV(y)=5\times 2=10\) sub-states without any firing gaps (i.e., \(FP=0\)) while only experiencing time delays created by iteration gaps (i.e., \(IG=2\)). When described in hardware as shown in the VHDL process in Listing 4, the optimized FSM \(M_{opt1}\) is reduced to seven states in comparison to a classical FSM \(M\) in Figure 7. The startup phase only has a single state (i.e., \"000\") followed by the periodic phase with the six states where the first four states are of type \(s_{sk}\) (i.e., \"001\", \"010\", \"011\", \"100\", \"101\"). The count register _xInst_ylInst_ch1_jc_ which is initially set to zero, increments until it reaches \(RV(y)=2\) where it moves the FSM from \(s_{sk}\) state type to \(s_{ig}\) state type. The iteration gap is realized in state type \(s_{ig}\) (i.e., \"110\") with the count register _xInst_ylInst_ch1_jgc_ that has a threshold of 2. ```
1 xInst_ylInst_ch1_proc : process(rst, clk)
2 begin
3 ifrst = '1'then
4..._~resetprocessregisters
5 elsif clk'EVENT and clk = '1'then
6..._~hiddencode
7 casexInst_ylInst_ch1_state is
8 whenb\"000\" >>
9 xInst_ylInst_ch1_re <= '0';
10 xInst_ylInst_ch1_state <= b\"000\";
11 ifxInst_vld_o = '1'then
12 xInst_ylInst_ch1_re <= '1';
13 xInst_ylInst_ch1_state <= b\"010\";
14 endif;
15 whenb\"001\" >>
16 xInst_ylInst_ch1_re <= '1';
17 xInst_ylInst_ch1_state <= b\"010\";
18 whenb\"010\" >>
19 xInst_ylInst_ch1_re <= '0';
20 xInst_ylInst_ch1_state <= b\"011\";
21 whenb\"011\" >>
22 xInst_ylInst_ch1_re <= '1';
23 xInst_ylInst_ch1_state <= b\"100\";
24 whenb\"100\" >>
25 xInst_ylInst_ch1_jc <= '0';
26 xInst_ylInst_ch1_jc <= '0';
27 xInst_ylInst_ch1_jc <= 0;
28 xInst_ylInst_ch1_state <= b\"110\";
29 endif;
30 whenb\"110\" >>
31 xInst_ylInst_ch1_re <= '0';
32 xInst_ylInst_ch1_state <= b\"110\";
33 xInst_ylInst_ch1_jc <= '1';
34 xInst_ylInst_ylInst_ch1_jc <= '1';
35 ifxInst_ylInst_ch1_jc <= 0;
36 xInst_ylInst_ch1_jc <= 0;
37 xInst_ylInst_ch1_jc <= 0;
38 xInst_ylInst_ch1_jc <= b\"110\";
39 endif;
40 whenothers=>null;
41 endcase;
42 endif;
43 endprocess;
```  
**Listing 4**. The process implementation of the second optimization FSM \(M_{opt1}\) for hardware design in Figure 5.  
Figure 8: The generic optimized composite FSM \(M_{opt1}\) as constructed using FSMs \(M_{X}\), \(M_{FF}\) and \(M_{Y}\) by using the computed 1-periodic schedule in Figure 2. Each node is the state type which may consists of sub-states which are defined by a sequence of one or two-dimensional vectors in lower half of the state type.