## 2 Materials and Methods  
### Schottky Diodes  
As a crucial component in THz multipliers and mixers, GaAs Schottky barrier diodes SBDs were developed first. In this paper, the 12-\(\mu\)m-thick GaAs monolithic integrated technology was jointly developed by the University of Electronic Science and Technology of China (UESTC) and Hebei Semiconductor Research Institute, Shijiazhuang. The main physical and electrical diode parameters for the 0.34 THz triplet and the 0.34 THz mixer are listed in Tables 1 and 2, respectively. Typical cut-off frequency (\(f_{T}\)) is also given, which is defined as 1/(2\(\pi\)R\({}_{\mathrm{s}}\)C\({}_{\mathrm{j}0}\)), where \(R_{\mathrm{s}}\) and C\({}_{\mathrm{j}0}\) represent series resistance and zero-bias junction capacitance of the Schottky-barrier diode, respectively. A detailed description is given about the process and design of the 4-die diode chip for the triplet, and that of the anti-parallel diode chip for the mixer was similar. Active layers (\(n^{-}\) GaAs epitaxial layer and the highly doped \(n^{+}\) GaAs buffer layer) were built on the semi-insulating (SI) GaAs substrate with a thickness of 12 \(\mu\)m. The doping concentration of the GaAs buffer layer was 5 \(\times\) 10\({}^{18}\) cm\({}^{-3}\), which created conditions for the ohmic contact between the cathode and the active layer. The thickness of the buffer layer was 3.5 \(\mu\)m, which was slightly larger than the skin depth at the operating frequency. The thickness of the epilayer was set to 0.3 \(\mu\)m, which was slightly larger than the thickness of the depletion layer under the reverse breakdown voltage to avoid introducing more series resistance. The cylindrical anode was formed on the epitaxial layer, resulting in the Schottky contact. The anode radius was 1.8 \(\mu\)m (corresponding to an area of 10.8 \(\mu\)m\({}^{2}\)), which is a key parameter for designing triplet and will be discussed later. The SiO\({}_{2}\) layer was deposited on the epitaxial layer to protect the epilayer. The SiO\({}_{2}\) passivation layer introduced parasitic parameters, and the smaller the thickness, the smaller the parasitic parameters introduced. According to the process conditions, the thickness of the oxide layer was determined to be 0.5 \(\mu\)m. The cathode pad and the metal layer of the transmission line were realized and connected by electroplating with a thickness of 1 \(\mu\)m. A straight surface channel was etched to lower parasitic capacitance, as shown in Figure 1. The spacing between the two straight mesas was 8.5 \(\mu\)m, which is elaborated later in this paper. In addition, the overall size of the 4-die diode chip was 224 \(\mu\)m in length, 28 \(\mu\)m in width, \begin{table}
\begin{tabular}{l l c} \hline \multicolumn{1}{c}{**Physical Parameters**} & \multicolumn{1}{c}{**Electrical Parameters**} \\ \hline Epilayer doping = 2 \(\times\) 10\({}^{17}\) cm\({}^{-3}\) & Junction potential (\(V_{j}\)) & 0.9 V \\ Epilayer thickness = 0.3 \(\mu\)m & Zero-bias junction capacitance (C\({}_{\mathrm{j}0}\)) & 16 fF \\ \hline N+ layer doping = 5 \(\times\) 10\({}^{18}\) cm\({}^{-3}\) & Series resistance per anode (\(R_{S}\)) & 6 \(\Omega\) \\ N+ layer thickness = 3.5 \(\mu\)m & Reverse saturation current (\(I_{sat}\)) & 2 \(\times\) 10\({}^{-17}\) A \\ \hline Anode radius = 1.8 \(\mu\)m & Reverse breakdown voltage (\(V_{br}\)) & \(-\)9.6 V \\ SiO\({}_{2}\) layer thickness = 0.5 \(\mu\)m & Reverse breakdown current (\(I_{br}\)) & \(-\)10 uA \\ \hline Substrate thickness = 12 \(\mu\)m & Ideality factor per anode (\(\eta\)) & 1.2 \\ \hline Chip length = 224 \(\mu\)m & Grading coefficient (M) & 0.5 \\ Chip width = 28 \(\mu\)m & Typical cut-off frequency (\(f_{T}\)) & 1.5 THz \\ \hline \end{tabular}
\end{table} 
Table 1: Physical and electrical diode parameters of the 0.34 terahertz (THz) triplet.