## 2 Power Scalable Digital Baseband
### Proposed Architecture and Functioning  
Figure 2 shows the architecture of the power scalable receiver. It includes synchronization units (acquisition, tracking, phase error estimator, frequency error estimator), CORDIC based NCO (Numerically Controlled Oscillator), FIR matched filters, decimator, demodulator, _etc._ Other than these units, the proposed receiver has units that make it adaptive. As shown in figure, it has an interference detector and an SNR estimator (IDSE), and an adaptivity control unit that decides the \(Q_{dig}\) and \(f_{s}\) of different sections of the receiver. For every packet the receiver starts off with the highest resolution and sampling frequency settings during the packet preamble. Synchronization (Timing, Frequency, Phase) is done with the highest settings and simultaneously, the interference and signal levels are estimated. By the end of the preamble, a LUT containing optimal values is consulted and the optimum \(Q_{dig}\) and \(f_{s}\) is used for the rest of the packet reception. All sections of the receiver in Figure 2 except the VGA and ADC are implemented in HDL for power estimation. Figure 2: Proposed Adaptive Receiver. \(f_{s}\) is sampling frequency and \(Q_{dig}\) is word length. Figure 3 shows the state diagram of the receiver with seven states. Timing synchronization is achieved over Acquisition and Tracking. The Frequency Error Estimator (FEE) estimates the error between carrier frequency of the desired signal and frequency of the local oscillators that down-converts the signal. Similarly, Phase Error Estimator (PhEE) estimates the error in phase of input signal and down-converting signals. These estimates are used to correct the errors in frequency and phase to allow coherent demodulation of the signal. Start-Frame-Delimiter (SFD) check provides a means to check if the synchronization achieved is reliable to further demodulate the data. As shown in the figure, _acq_success_, _track_success_, _FEE_success_ and _PhEE_ cause transition of states during synchronization. The synchronizing units work in tandem. _sync_succ_ signifies completion of synchronization and preamble of the packet. Detailed architecture of these synchronization units can be found in [12, 13, 14]. The decimator, demodulator and detector work in two different settings of \(Q_{dig}\) and \(f_{s}\). The first setting as shown in the Figure 3 (\(30\,\)Msps, \(8\)-bit) is the setting of word length and sampling frequency for the receiver during preamble of the packet. The second setting (\(Q_{dig}\),\(f_{s}\)) applies for rest of the packet, _i.e._, PHY service data unit (PSDU). The preamble is a sequence of symbol \"1\" followed by two SFD symbols as shown in the Figure 4. The figure shows a typical packet structure and the average time taken by various synchronization steps during the preamble when SNR\({}_{FE}\) is high. The synchronization designed for this receiver works on the continuous flowing sampled data from ADC. Figure 5(a) shows the typical buffered implementation of a receiver. Here, various signal processing blocks inside the receiver access the data from the buffer. This  
Figure 3: State Diagram of Receiver. STATES: (1) Acquisition; (2) Tracking; (3) Frequency error estimation (FEE); (4) Phase error estimation (PhEE); (5) Decimate, demodulate and detect at \(Q_{dig1}\) and \(f_{s1}\); (6) Start-Frame-Delimiter (SFD) check; (7) Decimate, demodulate and detect at \(Q_{dig2}\) and \(f_{s2}\). allows the receiver algorithms to reuse the data and gives better convergence performance. However, our approach for the receiver design does not use any buffer to save area and power. Figure 5(b) shows the non-buffered approach. Here, besides passing information regarding completion of its functioning as discussed above, every module passes a sample index to the subsequent module. For, e.g., acquisition unit passes _acq_success_ and a count _track_address_ to the tracking block once acquisition is done. The tracking unit initiates a counter when _acq_success_ is received.