# Revisiting the High-Performance Reconfigurable Computing for Future Datacenters
## 4 Revisiting the FPGA Virtualization
### Resource Level Virtualization  
#### 4.1.1 Overlays  
Overlay architectures are diverse based on application and respective requirements. Overlays provide another higher abstraction layer on lower level fabric of FPGA, as depicted in Figure 2. The primary objective is to enhance the ease of programming for the software programmer. The reduced compilation time is an added advantage, given that the computer-aided design part to generate an accelerator is left out in the compilation process. With respect to the ability of functional units, overlays are categorized in spatially-configured and time-multiplexed architectures. [PERSON] et al. compiled a comprehensive account of time-multiplexed overlays in a recent survey [45]. However, overlays are often discussed with respect to their implementation architectures in most of the literature that divides them into processor-based and coarse-grained reconfigurable architectures (CGRAs). A complete review of CGRAs can be found in [PERSON]'s doctorate thesis [46]. Processor-based comes in a variety of soft processor, either single-issue or multi-issue or multithreaded. They all add value to programmability, but the limited throughput is not suitable for the very high speed applications. Processor-based comes with a parallel processor as \begin{table}
\begin{tabular}{c c c} \hline \hline
**Abstract Classification** & **Sub-Class** & **Work Examples References** \\ \hline \multirow{2}{*}{Resource Level} & Overlays & [45; 46; 47; 48; 49; 50; 51; 52; 53; 54; 55; 56; 57; 58; 59; 60; 61; 62; 63; 64; 65; 66; 67; 68; 69; 70; 71; 72; 73; 74; 75; 76; 77; 78; 79; 80] \\  & Input Output (I/O) Virtualization & [4; 75; 76; 77; 78; 79; 81; 82; 83; 84] \\ \hline \multirow{3}{*}{Node Level} & Virtual Machine Monitors & [81; 82; 83; 84] \\  & Shells & [4; 41; 75; 76; 77; 85; 86; 87; 88; 89; 90; 91; 92; 93; 94; 95; 96; 97; 98; 99; 100; 101; 102; 103; 104; 105; 106; 107; 108; 109; 100; 109; 110; 111; 111; 111; 112; 113; 114; 115; 116; 117; 118; 119; 120; 121; 122; 123; 124; 125; 126; 127; 128; 129; 130] \\  & Scheduling & [82; 89; 98; 101; 102; 103; 104; 105; 106; 107; 108; 109; 1112] \\ \hline \multirow{3}{*}{Multi Node Level} & Custom Clusters & [113; 114; 115; 116; 117] \\  & Frameworks & [77; 103; 118; 119; 120; 121; 123] \\ \cline{1-1}  & Cloud Services & [4; 40; 124; 125; 126; 127; 128; 129; 130] \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Classification of FPGA Virtualization adopted from [6]. well, either in the form or multithreaded or VLIW or soft vector processor or soft GPU. One form of the soft-core processors is [47], and similar solutions [48; 49] are available from industry. Other forms include soft vector processors [50; 51; 52; 53; 54]. CGRAs offer higher performance and scalability with lower power consumption, the very characteristics FPGAs are used for. CGRAs exist in the form of processing arrays or coarse to medium grained processing elements, where operations are performed at the processing element level. Examples of connected arrays of processing elements with programmable interconnects are [55; 56; 57; 58; 59]. Some CGRAs are kept dynamic by programming the processing elements and interconnect logic [60; 61; 62; 63], while other architectures are kept static in spatial-configuration, as in [56; 57]. Frequently appearing interconnect topologies in CGRAs are the nearest neighbor [55; 56] and island model [57; 58; 59]. NoC are also found abundantly in CGRAs, some examples are [64; 65; 66; 67]. NoC based architectures offer flexibility at the cost of higher implementation cost, but some works, like Hoplite soft NoC [67] and hard NoC [22], offer resource-efficient fast interconnects. Although an effort to reduce the cost by mapping the overlay look-up tables and multiplexers to the FPGA fabric has been achieved in [68]. Table 4 summarizes time-multiplexed CGRA overlays. Overlays are opted only to meet the requirement of rapid functionality change, where partial reconfiguration fails to cope with the speed of change, due to the sizable cost of implementation.