## 2 Materials and Methods
### Layout and Integration  
The layout of the SALT is presented in Figure 8. It has dimensions of 10.90 mm\(\times\) 4.75 mm, where the horizontal dimension is driven by the pitch of the input pads (80 \(\upmu\)m) matching  
Figure 7: Triple Modular Redundancy (TMR) procedure applied in the SALT.  
the UT silicon sensor pad pitch. Inside the chip, signals are processed from the input pads (top in Figure 8) towards the serialiser and data drivers, placed near the back side (bottom in Figure 8). The top part of the layout contains 128 readout channels, oriented vertically, with analogue front-end and ADC, while the bottom section is almost purely digital, including the PLLs (3 rectangles at bottom-right) and DLL (rectangle at centre-left) circuits. The central vertical area is left nearly empty to accommodate the power rails for the analogue blocks.  
One of the most important issues concerning a multi-channel ASIC is the uniformity of analogue parameters in the front-end and ADC blocks. Apart from an unavoidable statistical spread arising from the ASIC production process, a systematic spread may also occur. Its main source originates from the voltage drop across the channels, due to the resistivity of the power rails. To minimise this spread, the power supply is typically delivered symmetrically from two sides of the ASIC. Unfortunately in case of SALT, due to space limitation on the printed circuit board (hybrid) hosting the ASICs, a different approach is taken. In the UT detector two types of hybrids are required, one containing four SALTs (shown in Figure 9) and another with eight SALTs chips, called 4-chip and 8-chip hybrids, respectively. Both hybrids have the same width, which has to (approximately) match the width of the sensor. The 8-chip hybrid is required to match the larger channel density in the high occupancy regions of the detector. Due to the dimensional constraints on the hybrid, there is insufficient space to make wirebonds between the ASICs and the hybrid in the region between the ASICs. Since it was decided to use one ASIC design for both hybrid types, the SALT layout must support two power supply schemes. For 4-chip hybrid the power supply is delivered symmetrically from the left and right sides (see Figure 8), while for 8-chip hybrid only from the back side. To keep a similar level of symmetry in both cases, the analogue part of the chip is divided into two 64-channel blocks, and the power supply is delivered centrally from the back side through the digital part of the chip and distributed in a star-like connection between the blocks.  
The power supply scheme proposed for 8-chip hybrid can be very risky in a multi-channel ASIC with an ADC in each channel, due to long supply rails which can not be well simulated. This is because standard design tools provide only the extraction of parasitic resistance and capacitance, but not inductance. However, the mutual inductance between long adjacent rails belonging to different power domains, that is, analogue, ADC and digital, becomes critical--and in extreme cases--may lead to instability of the entire system. To eliminate the inductive coupling between the analogue front-end and ADC blocks, the power supply of the latter was transferred to the digital domain (where a two-layer supply mesh with interleave is used) leaving the central part of the layout only for front-end power rails. Moreover, to reduce the sensitivity to pick up disturbances by the ground network of input transistors, dedicated insulating layers and guard rings were added [37].  
Figure 8: Layout of SALT ASIC; the die size is \(10.905\,\mathrm{mm}\times 4.75\,\mathrm{mm}\).