## 2 Designed NISC-Based Architectures  
### Equalizer Architecture  
The designed NISC-based architecture, which is dedicated to MMSE equalization, is basically made of a control unit and the equalizer module called _EquaNISC_, which is the main core of the design. To meet with the demanded requirements of flexibility, the hardware resources are instantiated carefully and shared among different computations. Adequate hardware operators are implemented to perform all required computations taking into account the requirements of flexibility, efficiency and performance. Fixed-point arithmetic is adopted rather than floating-point arithmetic in order to reduce the implementation costs, while ensuring sufficient accuracy and negligible performance loss. Floating-point arithmetic is generally used to conduct performance evaluation studies of algorithms. This is typically limited to theoretical performance evaluation in terms of communication quality and error rates. For a practical implementation perspective, using fixed-point arithmetic instead of floating-point reduces significantly the implementation costs in terms of area occupation and energy  
Figure 2: Transition from the application-specific instruction set processor (ASIP) to the no instruction set computer (NISC) design approach.  
consumption. In fixed-point architectures, the memory and bus widths are smaller, leading to a definitively lower cost and power consumption. Moreover, floating-point operators are more complex, having to deal with the exponent and the mantissa, and hence, their area and latency are greater than those of fixed-point operators [16]. All operands that are involved in MMSE computational operations are quantized in the 16-bit two's complement representation according to carefully-determined precisions [17]. Temporal parallelism using a pipeline is applied to improve the performance and to increase the throughput. The designed architecture is shown in Figure 3, which presents the constituent units, as well as the input/output interface. The equalizer architecture receives input data from the soft mapper, the look-up table \(\frac{1}{x}\) LUT and channel and control memories, which are called _ChMem_ and _CMem_, respectively. _ChMem_ stores the constant data of the channel, and _CMem_ stores the control words generated statically by the NISC compiler. The \(\frac{1}{x}\) LUT is used to replace the inversion operations, which are computationally demanding, in order to avoid undergoing expensive computations. The LUT uses memory instead of large numbers of computational elements. It includes all 16-bit inverse values, which are possibly used in the inversion process. These values are pre-computed and stored such that the value \(x\) intended to be inverted is used directly as the LUT index (address) to retrieve the inverse value \(\frac{1}{x}\). When using LUT, both resource utilization and propagation delay are reduced at the cost of accuracy. A detailed analysis and long numerical simulations have been conducted for different configurations to find the required data width and accurate precisions for the fixed-point representation of the involved values. Moreover, the size of the LUT adds additional overhead. However, the required memory space in this application is reasonable since the LUT depth is limited to \(2^{16}\). To reduce the size of the LUT, the segmentation approach may be used by storing one inverse value, the median of the group, in the LUT to represent the results of \(\frac{1}{x}\) for a group of consecutive values of \(x\)[18]. Other memory size reduction technique are achieved by storing only positive values in the LUT. In this case, the LUT depth is reduced from \(2^{m}\) to \(\frac{2^{m}}{2}\), where \(m\) is the number of bits representing the positive number.  
Figure 3: Proposed equalizer architecture.