# FPGA Implementation of ECT Digital System for Imaging Conductive Materials
## 5 System Implementation
### Hardware Implementation  
In order to increase the performance gain, energy efficiency, and fewer hardware resources, the IR algorithm is realized with the fixed-point representation, where the word length is chosen to be 32-bits in the simulation to preserve similar precision of its floating-point counterpart. Inside the Simulink model and by utilizing the HDL Workflow Advisor tool of the HDL coder, we have generated the HDL IP core for the IR unit, and the interface logic to the software part mapped to the ARM processor. Typically, the IP interface logic is abstracted as a software interface model with the AXI4 interface to the ARM processor.  
The design involves a computation of image \(H\) using \(S^{T}xC=H\), where \(S^{T}\) is a matrix of size \(6\times 256\), vector \(C\) has size \(1\times 6\) and the size of matrix \(H\) is \(1\times 256\). It is essential to develop a library of arithmetic matrix operations such as transpose, multiplication, and subtraction. Using HDL Workflow Advisor tool of the HDL Coder toolbox, the HDL-code as an IP-core for the image reconstruction subsystem is generated. In the same process, the IP interface logic as well as its abstract software interface model to the ARM processor is automatically generated according to the AX14 interface.  
The iteration loop is controlled either by the iterations number or a predefined error. The number of iterations controls the quality and accuracy of the reconstructed images. Hence, the optimal number of iterations has to be carefully chosen. There is a trade-off between increasing the iteration number to enhance the accuracy and computational time, especially for dynamic applications. Another way to stop the iteration loop is reaching the difference between the actual and estimated measurements a predefined value \(E\). Figure 5 shows the execution of the ILBP algorithm on the software processor.  
The memory interfaces play a vital role in the design of the ECT system. The Altera FPGA internal RAM memory blocks are used as the system's memory. The word size of the memory block is set to be 256 (16-bit). During the communication process between the processor and the memory, the memory read/write operations are issued by the processor controller. These operations allow reading and storing the transferred information and intermediate results from and to the memory. In addition, the interface of the memory has logic for the generation of various memory control signals.  
In order to boost the code of signal processing, a fixed-point matrix arithmetic library containing basic operations such as an adder, subtractors, and multipliers is implemented. Arithmetic modules of 8, 16, and 32 bits were developed using HDL to adapt the requirements of the reconstruction algorithm. The bitmaps created from these modules were effectively verified after downloading it the FPGA platform. Conclusively, the functions' flow diagrams were translated into HDL code. Functional calls representing the arithmetic operations are established to decrease the number of arithmetic unit instantiations.