# PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs
## 1 Introduction  
It is expected that CMOS will be the mainstream digital integrated circuit technology within the next 20 years. The clock frequency of CMOS digital systems tends to remain at a reasonable rate instead of significantly improving due to the saturation of Moore's Law [1]. Thus, parallel architecture and parallel computing are introduced to improve system performance The homogeneous parallel system on chip (SoC) can provide sufficient flexibility and performance for general applications, but its ability is inadequate for some specific domains such as high-speed real-time embedded systems (e.g., wireless communication baseband processor). Heterogeneous multi-core architectures have been introduced to improve performance in dedicated domains, and have gradually become the hotspot of the market [2]. The characteristics of heterogeneous multi-core real-time SoC are as follows: (1) specially designed for stable application software in a specific application domain; (2) ultra-high computing performance requirements. Heterogeneous multi-core real-time SoC needs a characteristic network on chip that can provide relatively predictable and stable data flow. The heterogeneous multi-core real-time SoC needs a particular on-chip connection method which could provide a relatively predictable and stable data flow. the connection method shall at least meet the following requirements: (1) extremely wide bus width with hundreds of bits; (2) concurrent multiple data flow transmission; (3) ultra-short setup time; (4) stable and orderly data transmission; (5) low overhead non-disordered transmission without cache; (6) negligiblylow power consumption compared with the power consumption of the computing and storage; (7) flexible and dynamic connection capability; (8) enough nodes and ports to provide full connection; (9) scalable and reconfigurable distributed connections; (10) a reliable and deadlock-free network. When the number of processor cores is relatively small, bus and crossbar are traditional interconnection methods [3]. All processing elements (PEs) share the transmission medium when using shared bus as shown in Figure 1a. When the number of PE connected to the bus increases, the bus traffic will quickly reach the saturation state, and the system is difficult to obtain higher bandwidth, which cause the poor scalability of the bus. The shared bus has relatively low transmission efficiency because it doesn't support parallel data transmission, but it requires relatively low power consumption. Crossbar provides fully connections between all PEs with multiplexers as depicted in Figure 1b. Although crossbar can solve the transmission parallelism problem, its scalability is poor due to the area overhead and power consumption with the increase of the PE number. As more and more cores are integrated on a single chip, traditional interconnect architectures hit the bottleneck, and the NoC interconnection architecture emerges [4; 5]. The NoC architecture perfectly solves the defects of traditional interconnect schemes. The advantages of NoC are mainly reflected in the following three aspects. First, NoCs provide enough concurrency for communication between PEs on chip. Second, compared with the bus and crossbar architecture, the NoC architecture has strong scalability, and can easily expand the topology distribution according to the rules of the original topology. Third, the latency of NoC communication is low. The existing NoC architectures are mainly divided into two categories: packet switching (PS) NoC and circuit switching (CS) NoC. PS NoC transmits data packets through dynamic routing, and the receiver of PS NoC may have to reorder the packets. CS NoC transmits and receives data by establishing a circuit-based data path [6]. The characteristics of existed PS NoCs are as follows: (1) the data transmitted at one time is divided into several small flits (Flow control unIT), and each flit carries the active status, destination addresses and data information (such as the order and length of the packets).