# A Method for Synthesizing Ultra-Large-Scale Clock Trees
## 2 IB-KSR Algorithm
### Balanced Split
In large-scale clock tree synthesis scenarios constrained by buffer fan-out limitations, IB-KSR maintains practical nearest-neighbor parameter configurations (\(k\)-value \(<\) 1 k), while conventional KSR implementations must process exhaustive node traversals-potentially involving millions of nodes. This fundamental architectural difference results in KSR's memory footprint scaling to terabyte-level requirements (1000\(\times\) greater than IB-KSR). Although terabyte-capacity servers exist, from a cost-performance perspective, KSR proves fundamentally impractical for ultra-large clock tree implementations. Moreover, its runtime latency could extend beyond 10 h (1000\(\times\) slower), further compromising operational efficiency. ## 5 Conclusions

To address the challenges of computational resource limitations and buffer fan-out bottlenecks in ultra-large-scale clock tree synthesis, this paper improved and extended the KSR algorithm, proposing the IB-KSR clustering algorithm. This algorithm retains the advantages of low power consumption and low latency inherent in the KSR algorithm while enhancing adaptability to ultra-large-scale clock trees through optimized synthesis processes. It significantly improves computational efficiency and resource utilization. Experimental results demonstrate that compared to the GSR algorithm, IB-KSR exhibits significant advantages in clock skew control, achieving a 43.4% reduction in maximum skew and a 34.3% improvement in average latency. Despite handling clock trees with hundreds of thousands of nodes, IB-KSR maintains its runtime within a manageable range, fully showcasing its efficiency in ultra-large-scale clock tree synthesis. In summary, the IB-KSR algorithm not only preserves the superior low power consumption and low latency characteristics of KSR but also introduces a highly efficient and scalable synthesis solution by design optimizations tailored for ultra-large-scale clock trees. By effectively addressing the technical challenges of computational resource limitations and fan-out bottlenecks, the algorithm provides a practical and feasible approach to achieving efficient ultra-large-scale clock tree synthesis. Additionally, the algorithm's unified framework can be integrated as a modular component into existing EDA platforms and supports standard data formats. Its scalability and efficiency make it suitable for both small-scale and large-scale designs, reducing the need for multiple specialized tools. Conceptualization, Z.L. and C.Z. ; methodology, Z.L. ; software, Y.W. ; validation, Z.L. and Y.W. ; formal analysis, J.C.; investigation, C.Z. ; resources, B.C. ; data curation, J.L. ; writing--original draft preparation, W.W.; writing--review and editing, B.C. ; visualization, J.L. ; supervision, B.C. ; project administration, Q.L. ; funding acquisition, H.L. All authors have read and agreed to the published version of the manuscript. This work was funded by the Wuhan Key Research and Development Plan (Grant No. 2024050702030134), China-Sudan Joint Laboratory of New Photovoltaic Ecological Agriculture (Grant No. 2023 YFE0126400) and College Student Innovation and Entrepreneurship Training Program (202310500013). Data Availability Statement: The raw data supporting the conclusions of this article will be made available by the authors on request. ## Conflicts of Interest: The authors declare no conflict of interest. ## References

* (1) [PERSON]; [PERSON]; [PERSON] Register Clustering Methodology for Low Power Clock Tree Synthesis. _J. Comput. Sci. Technol._**2015**, _30_, 391-403. [CrossRef]
* (2) [PERSON]; [PERSON]; [PERSON]; [PERSON] _VLSI Physical Design: From Graph Partitioning to Timing Closure_, 1 st ed. ; Springer: Berlin/Heidelberg, Germany, 2011. * (3) [PERSON]; [PERSON]; [PERSON]; [PERSON] Zero skew clock routing with minimum wirelength. _IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process._**1992**, _39_, 799-814. [CrossRef] [PubMed]
* (4) [PERSON]; [PERSON]. Dim Sum: Light Clock Tree by Small Diameter Sum.