## 2 Edge Computing
### PUF-Based Authentication Mechanism
#### 2.2.1 Arbiter PUFs  
An APUF is a delay-based PUF circuit that derives its output response bits from the time delay differences between two identical signal propagation paths. A race condition is created by simultaneously launching a common signal through both paths. The path that completes first determines the output response bit. These path-to-path delay variations arise due to device-specific manufacturing imperfections, yielding unique and effectively unpredictable responses for each chip [77]. Figure 3 illustrates signal propagation through two symmetrical paths consisting of switching elements, such as multiplexers, ultimately reaching an arbiter circuit that determines the output based on the race result. If the delay in the upper path exceeds that of the lower path, the response is '0'; otherwise, it is '1' [78]. An APUF consists of n delay stages, each containing two input multiplexers that switch the signals based on the applied challenge bits. An arbiter at the end evaluates the response bit based on which signal arrives first--either on the top or bottom line. The signals propagate through the two delay paths, competing to reach the end first. The output is set to '1' if the signal reaching the latch's data input (D) is faster; otherwise, the output is '0'. The delay differences of the individual APUF stages combine additively, meaning the total delay difference between the two signals is the sum of the delay differences across all stages. A challenge bit \(c_{i}=-1\) swaps the two signals and can be modeled by multiplying the delay difference \(\delta(i)\) at stage \(i\) by \(-1\). In this way, a recursive formula, as shown in Equation (1), can be constructed to model the delay difference \(\delta(i)\) at stage \(i\). \[\delta(i)=\delta(i-1,c)\cdot c_{i}+s_{i}(c_{i}) \tag{1}\]  
where \(s_{i}(c_{i})\) is the delay difference introduced at stage \(i\) for challenge \(c_{i}\). The sign of the final delay difference \(\delta(n)\) at stage-n then defines the response bit. Challenge inputs \(C=\{c_{1},c_{2},\ldots,c_{n}\}\in\{0,1\}^{n}\) decide the propagation path of the signal through the circuit. Two signals race through the circuit, and a D-flipflop or a D-latch finally determines the 1-bit response 'r' \(\in\{0,1\}\). The input at the top propagates to the top output, whereas the bottom input comes out from the bottom output for \(c_{j}=0\), and the top input comes out from the bottom output and vice-versa in the case of \(c_{j}=1\). Figure 2: Unique CRP of PUFs [32]. For stage \(j\):  
\(\delta_{j,0}:\) top path delay for \(c_{j}=0\);  
\(\delta_{j,1}:\) top path delay for \(c_{j}=1\);  
\(\delta_{j,2}:\) bottom path delay for \(c_{j}=0\);  
\(\delta_{j,3}:\) bottom path delay for \(c_{j}=1\). The above delay variations differ significantly from device to device due to inherent manufacturing variations. The total delay difference \(\delta\) at the \(n^{\text{th}}\) stage is expressed as a linear combination of the delay differences at each stage. The output response of the APUF is determined by the sign of \(\delta\), as shown in Equation (2), where  
\[\delta=\sum_{j=1}^{N}w_{j}\phi_{j} \tag{2}\]  
A feature vector \(\phi_{j}\) in Equation (3), derived from the challenge bits, is typically defined as  
\[\phi_{j}=\prod_{j=k}^{N}(1-2c_{j}) \tag{3}\]  
\(w_{j}\) in Equation (4) is a weight representing the delay difference for stage-j, which is a function of the physical variations:  
\[w_{j}=\frac{(\delta_{j,0}-\delta_{j,1})+(\delta_{j,2}-\delta_{j,3})}{2} \tag{4}\]  
The response r given in Equation (5) is determined by the sign of the delay difference [79]\(\delta\), i.e.,  
\[r= \begin{cases}1,&\delta\geq 0\\ 0,&\delta<0\end{cases}  \tag{5}\]  
Studies have demonstrated that APUFs can be compromised by machine learning (ML) attacks using a relatively small set of CRPs. This vulnerability stems from the fundamentally linear and additive characteristics of the mathematical model of the PUF.