# Generating Airborne Ultrasonic Amplitude Patterns Using an Open Hardware Phased Array
## 3 Hardware Design
A field-programmable gate array (FPGA) receives the phases to be emitted from a computer, they are stored on a double buffer and constantly output. The FPGA multiplexes 8 channels into one line so that only 32 output pins are needed. There are 32 blocks of shift registers, being able to drive a total of 256 emitters. The shift and the latch clock are generated by the FPGA. The shift clock controls when the shift registers shift data in, the latch clock determines when the data that were shifted should be output. The shift clock operates at 10.24 MHz (8 multiplexed channels \(\times\) 40 kHz \(\times\) 32 divisions per period), whereas the latch clock operates at 1.28 MHz (40 kHz \(\times\) 32 divisions per period). The number of divisions per period (i.e., the resolution in phase or amplitude) could be doubled to 64, but the shift clock would operate slightly above 20 MHz, which would require better filtering and traces on the PCB. Once the digital signal for each channel has been demultiplexed, it is amplified from 5 V up to 20 V using a dual Metal-oxide-semiconductor field-effect transistor (MOSFET) driver (e.g., TC4427a or MIC4127 from MT). After testing different electronic components for amplifying the signals (e.g., L293D or BJT transistors), MOSFET drivers were found to efficiently drive the ultrasonic transducers. Dual Mosfet Drivers can amplify two channels and have a small footprint; larger components would not fit on the integrated board. Subsequently, the output of the drivers is fed into the ultrasonic emitters (a comparison of suitable transducers can be found in the supplementary information of TinyLev [42]). Given the narrowband nature of the emitters, it is possible to use a half-square wave to drive them without generating a significant amount of harmonics [41]. This technique is widely employed for airborne ultrasonic phased arrays, because generating a digital square signal is less complex than creating an analog sinusoidal signal, they are also easier to amplify. We present two models of the ultrasonic array. In the first one, the electronic components (i.e., shift registers, drivers, and decoupling capacitors) are surface mounted device (SMD) and the ultrasonic emitters have a diameter of 10 mm (Figure 3). The second model uses emitters of 16 mm diameter and through-hole (TH) components (Figure 4). The first model is more compact and faster to assemble if SMD equipment is available (e.g., stencils, solder paste, and a reflow oven). The TH model is larger and it takes more time to assemble, but it can be done with entry level electronics equipment (i.e., a soldering iron). Throughout the paper, we focus our experiments on the SMD board, since we think that it will be employed more often in the scientific community. The program synthesized for the FPGA delegates the phase calculations on an external computer, thereby the cost of the board itself can be kept low. A UART reader block gets the bytes coming from the external computer [49]. A distributor block stores the current channel and sets the phases on the 256 signal generator blocks, each generator block outputs a digital signal of 40 kHz. Each generator block stores two phases, the one to be emitted and the previously read phase. The generator blocks have an internal amplitude  
Figure 2: At the left, the FPGA blocks in charge of generating the signals are presented, 8 phaseLine blocks (signal generators) are multiplexed into one digital line to reduce the required number of output pins. At the right, the circuit schematic represents a shift register that demultiplexes the signal into 8 channels that get amplified by four dual Metal–oxide–semiconductor field-effect transistor (MOSFET) drivers and fed into the ultrasonic emitters. counter that represents the number of divisions that the output should be HIGH, there is a global counter (from 0 to 31) that reaches all of the blocks, when the phase of a generator block coincides with the global counter, the internal amplitude counter is set to the target amplitude.