## 3 Results and Discussion
It is imperative that this layer acts as a robust barrier to prevent undesirable charge injection  
from the gate, necessitating both considerable thickness and superior material quality to ensure the effective insulation of the channel [19]. However, an excessively thick blocking layer might inadvertently diminish the efficacy of the electric field between the gate and channel, thus impeding the device's functional efficiency [22]. The formation of the trapping layer, particularly in environments with reduced oxygen levels, leads to a higher density of traps compared to those created in conditions with higher oxygen availability. This situation presents a clear division: increasing the number of traps can improve the memory's ability to store charge, but achieving the best conditions for sputtering without causing too many defects or leakage paths is a difficult challenge. Therefore, if the trapping layer is excessively thin, it may weaken the device's ability to prevent leakage currents, which could potentially jeopardize the stability of the entire system. After thorough deliberation, a configuration of thicknesses measuring 5/20/30 nm  
Figure 4: The retention characteristics of memory devices at **(a)** room temperature and **(b)** 100 \({}^{\circ}\)C.  
Figure 5: **(a)** Variations in threshold voltage for devices exposed to positive gate biases from 11 to 13 V and negative biases from \(-\)12 to \(-\)14 V over a period of 5 ms, along with the anticipated changes in threshold voltage after a decade of retention, considering layers with different thickness configurations. The configuration comprising tunneling, charge trapping, and blocking layers with thicknesses of 5 nm, 20 nm, and 30 nm, respectively, demonstrated the most optimal performance. **(b)** Threshold voltage shifts in both the devised and comparative control devices under the same conditions of positive and negative gate biases for 5 ms, with projections of these shifts after 10 years of retention, showcasing the enduring efficacy of the proposed device structure. was identified as the optimal choice, delivering the most harmonious performance across the device's array of operational requirements. To highlight the benefits of the memory device proposed in this research, a comparative analysis was conducted against a reference model composed of layers of 5 nm HfZrO/20 nm SiN/30 nm HfZrO. Silicon nitride (SiN) was chosen due to its proven efficacy as a charge trapping material in charge trap memory (CTM) applications [2; 23]. As depicted in Figure 5b, experimental evidence supports that our proposed configuration either matches or exceeds the reference model in terms of functional performance. This comparison not only validates the advanced memory device's adept programming capabilities but also its exceptional charge storage capacity. Typically, films created in environments with lower oxygen partial pressures, thus being oxygen-deficient, tend to exhibit higher rates of defects. Although these imperfections slightly decrease the amount of current that leaks, they also encourage the formation of conductive pathways or filaments caused by the presence of oxygen vacancies. Moreover, the specific arrangement of trap energy levels in HfZrO, which are concentrated at important locations, has a significant impact on its ability to support multiple storage levels. This enhances the usefulness of HfZrO as a charge trapping medium with unique benefits. Regarding the impact of gate bias on electron behavior, the ease with which electrons in the IGZO channel's accumulation layer migrate into the charge storage layer through F-N tunneling under a positive bias is noteworthy. This process effectively secures and retains positive charges within the layer. In contrast, the intrinsic properties of a-IGZO as an n-type semiconductor complicate the dynamics of charge under negative bias; the depletion of the channel obstructs the conversion of the a-IGZO channel to the p-type [24].