# A Survey of of Side-Channel Attacks and Mitigation for Processor Interconnects
## 2 Interconnect and Network-on-Chip  
In integrated circuits (ICs), interconnects refer to the structures that electrically connect two or more circuit elements, such as transistors. The design and layout of these interconnects are crucial for the normal operation, performance, power efficiency, reliability, and manufacturing yield of ICs. On a chip, components need to communicate with each other through these interconnects. To facilitate this communication, designers have developed on-chip communication subsystems based on network principles, commonly referred to as Network-on-Chip (NoC) in certain digital circuit categories [27]. NoC is most commonly found among modules in System-on-Chip (SoC). Modules on ICs are typically semiconductor IP cores that systematize various functionalities of computer systems and are designed to be modular in a network science sense. NoCs are packet-switched networks based on routers between SoC modules. With advancements in chip manufacturing technology, computer architects have been able to integrate an increasing number of processors and other heterogeneous components onto the same chip. Early SoC architectures were based on buses and crossbars. In this traditional bus architecture, each signal has a dedicated line for point-to-point transmission. Early SoC had fewer heterogeneous modules, making this simple and easy-to-implement bus architecture cost-effective. Buses were utilized in many mature architectures, with typical examples including ARM's AMBA (Advanced Microcontroller Bus Architecture) bus [28] and IBM's CoreConnect [29]. In contrast, buses struggled to adapt to architectural changes or effectively leverage advancements in silicon technology, leading this architecture to become a critical bottleneck in SoC performance as the number of SoC modules and interconnect complexity increased. This is primarily because buses cannot classify activities based on their characteristics; for example, buses cannot categorize transactions, transfers, and physical layer behaviors. Additionally, bus architectures exhibit significant disadvantages in scalability, power consumption, and reusability, along with drawbacks such as unstable line delays and rapidly increasing verification costs. In pursuit of more complex SoC, researchers, inspired by the internet, proposed the concept of Network-on-Chip as an alternative to bus architectures. NoCs are miniature versions of wide-area networks consisting of routers, packets, and links, proposed as a new solution for inter-module communication in highly complex SoC modules [30; 31]. This new paradigm describes a communication method between IPs, including routing protocols, flow control, switching, arbitration, and buffering, offering higher scalability, resource reuse, and overall performance, while also reducing costs, design risks, and time to market. Leveraging these advantages, NoCs have successfully replaced buses as the solution for complex SoCs requiring scalable interconnect architectures. Cores and non-core units inside CPUs are connected via a ring or mesh interconnect, constituting an NoC as well. Additionally, different CPUs are also connected via an interconnect known as Ultra Path Interconnect (UPI) [32]. While these interconnects offer significant advantages in terms of latency and bandwidth in multi-core CPUs, they may leak information about program memory access patterns due to time differences caused by congestion on the interconnects. Figure 1 shows the mesh interconnect architecture of an Intel 16-core processor as an example, consisting of multiple processing elements interconnected by routers and wires (links). Processing elements can be any components such as microprocessors, specialized integrated circuits, or intellectual property blocks performing specific tasks. In the context of processors, processing elements are typically processor cores or non-core components such as integrated memory controllers, UPI controllers, I/O units, etc.