## 1 Introduction
\[\mathrm{LER}\leq\frac{1}{\mathrm{N_{L}}\times\mathrm{F}\times\mathrm{T}} \tag{8}\]  
where \(\mathrm{N_{L}}\), F, and T represent the number of logic gates in a chip, the number of operations per second, and the guarantee period, respectively. For example, the LER should be less than \(3\times 10^{-26}\) for a circuit with \(10^{8}\) logic gates, \(10^{9}\) Hz operations, and a 10-year (\(3\times 10^{8}\) s) operation period, and then the S/N (\(\mathrm{A_{S}/\sigma}\)) ratio should be greater than 26.5 dB (21.1). Figure 1: Logic error rate as a function of S/N and A/\(\sigma\) ratios. For example, we consider signal electrons required from a no error operation. Figure 2 shows (a) Variation in the number of electrons as a function of the number of signal electrons. (b) Logic error rate as a function of the number of signal electrons. When a signal is constructed by a constant number of electrons (N\({}_{\text{e}}\)), the standard deviation of the number of electrons is (N\({}_{\text{e}}\))\({}^{1/2}\), and then the A/\(\sigma\) ratio is (N\({}_{\text{e}}\))\({}^{1/2}\). As a result, the number of electrons must be greater than 445 to maintain an S/N (A\({}_{\text{S}}\)/\(\sigma\)) ratio of 26.5 dB (21.1). If the number of signal electrons is 1, the LER must be equal to 0.3. Then, such a system produces the wrong output once every three calculations. The electronic circuit will be influenced by noise, such as thermal noise, quantum noise, and flicker noise. The noise voltage (v\({}_{\text{nf}}\)) in 1/f noise is defined by the following equation. \[\text{v}_{\text{nf}}=\sqrt{\frac{\text{K}_{\text{F}}}{\text{C}_{\text{OX}} \times\text{L}\times\text{W}}\ln\left(\frac{\text{f}_{\text{H}}}{\text{f}_{ \text{L}}}\right)} \tag{9}\]  
where K\({}_{\text{F}}\) represents the flicker noise coefficient, f\({}_{\text{L}}\)-f\({}_{\text{H}}\) is the frequency period for device operation, C\({}_{\text{OX}}\), L, and W represent the gate oxide capacitance, gate length, and gate width of a MOSFET, respectively. Noise increases with device shrinkage because v\({}_{\text{nf}}\) is inversely proportional to \(\sqrt{\text{C}_{\text{OX}}\text{L}}\)[11; 12; 13; 14]. It has been pointed out that 1/f noise may influence not only analog devices, but also digital devices when device shrinkage and the decreasing signal voltage are moved on [15]. Random telegraph noise (RTN), another low-frequency noise also affects electronic devices, such as CMOS image sensor [16; 17; 18; 19; 20; 21], static random access memory (SRAM) [22; 23; 24; 25], dynamic random access memory (DRAM) [25], and flash memory [26; 27; 28; 29; 30; 31; 32]. Low-frequency noise, such as 1/f noise and RTN, have high variability [33; 34] because they must be statistical phenomena by nature, and statistical analysis is required to fully understand this phenomenon. The conventional evaluations of the noise in MOSFETs have performed with a few sample numbers, and then we could understand only typical noise characteristics of MOSFETs having relatively large noise. However, we need statistical information of the noise for the design of LSI. Then, low-frequency noise statistical evaluation methods and evaluation results are described in this study.