# A Novel ASIC Implementation of Two-Dimensional Image Compression Using Improved B.G. Lee Algorithm
###### Abstract
An eight-point DCT based on the Loeffler algorithm using pipelining was proposed in the work presented by [PERSON] et al. [9]. The implementation was optimized by using 2D Algebraic Integer (AI) encoding and the computations were minimized using shifters and adders instead of multipliers. [PERSON] et al. [10] proposed two FPGA architectures for high-performance processors to perform 2D DCT computations using Distributed Arithmetic for arithmetic computations. The DCT operation was implemented on 8 \(\times\) 8 image blocks, and the row-column arithmetic realization was utilized in the design. [PERSON] et al. [11] proposed a 1D DCT computation algorithm based on algebraic integer encoding. The Arai DCT algorithm was used for the 8 \(\times\) 8 DCT transform computation in 2D. The real-time implementation of the algebraic integer DCT was designed using an area-efficient architecture that showed a performance improvement compared to the architecture using four channels. [PERSON] et al. [12] focused on using algebraic integers to perform the DCT algorithm computation. The Loeffler algorithm was used to implement the eight-point DCT design with error-free operation up to the last step. Further, the final reconstruction step (FRS) algorithm was implemented using the newly proposed digital architecture. [PERSON] et al. [13] presented an architecture for a multiplier-less DCT suitable for capsule endoscopy applications. The application of three approximating methods such as threshold setting, approximate adders, and coefficient optimization was used in the design of the multiplier-less DCT algorithm. [PERSON] et al. [14] introduced a novel approximation technique for an eight-point DCT requiring just 14 additions with no multiplication operations. Compared to the existing DCT approximations, the computational and algorithm complexity was less. The separability property of 2D DCT was utilized to implement the proposed designs by successively calling the 1D DCT architecture. [PERSON] et al. [15] proposed an architecture design for inexact adders to implement DCT without multipliers. The utilization of the proposed inexact adders resulted in power and area savings due to the tolerance of errors by the DCT computations. The main inferences observed from the analysis results were a noticeable reduction in computational complexity while maintaining an acceptable PNSR. [PERSON] et al. [16], in their work, explored and analyzed the impact of approximate addition while performing image compression. The DCT implementation in an Application Specific Integrated Circuit (ASIC) design environment was carried out using both accurate and approximate adders. A considerable reduction in the size of the compressed images was observed when DCT was implemented using approximate adders. Compared with the carry look ahead adder, the approximate adders exhibited reduced power, area, and delay when implemented using standard cells. Their work focused on obtaining the best possible approximate adder design for image compression applications in the digital domain. [PERSON] et al. [17] designed a framework using inexact computing addressing a few difficulties linked with DCT compression. The processing of the framework proposed involved three different stages. The first stage encompassed eradicating floating-point computations and designing the DCT using additions and logical left and right shift operations. Further data reduction was accomplished in the second stage by filtering the frequencies the human eye cannot detect. The third stage introduced inexact adders to compute DCT to minimize delay and power. A reduction in the delay and energy with acceptable accuracy was achieved with the proposed framework for image processing applications. In their work, [PERSON] et al. [18] designed a CORDIC-based DCT/IDCT unified architecture. An additional mode controller was required to decide whether to use a DCT or IDCT operation in contrast to the existing architectures. This reduced the total hardware resources required for the unified architecture.