## 4 Discussion  
In Section 3, Table 4 evaluates the bandwidth change with the B1 rate and B2 rate. The B1 rate represents the impact of interconnect spacing changes on bandwidth. The B2 rate represents the bandwidth improvement ratio before and after the hardening design. Through the simulation, the B1 rate increases with the decrease of spacing, which means that although the frequency decreases with the decrease of interconnect spacing, the bandwidth  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline  & **Original** & **0.9 Spacing** & **0.8 Spacing** & **0.7 Spacing** & **0.6 Spacing** & **0.9 Length** & **0.8 Length** & **0.7 Length** \\ \hline Delay & 874 & 946 & 1036 & 1156 & 1316 & 709 & 560 & 430 \\ \hline G6 Delay & 701 & 752 & 821 & 909 & 1036 & 566 & 447 & 338 \\ \hline G6. Freq & 0.457 & 0.423 & 0.396 & 0.346 & 0.304 & 0.564 & 0.714 & 0.930 \\ \hline G5. Freq & 0.570 & 0.532 & 0.487 & 0.440 & 0.386 & 0.707 & 0.895 & 1.183 \\ \hline B1 rate & 0 & 0.026 & 0.054 & 0.080 & 0.107 & 0.233 & 0.561 & 1.032 \\ \hline B2 rate & 0.247 & 0.258 & 0.262 & 0.270 & 0.272 & 0.252 & 0.253 & 0.272 \\ \hline \hline \end{tabular}
\end{table}
Table 6: SSTC SPICE simulation and bandwidth change on 28 nm node.  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline
**Bit Error Rate/\%** & 0.5 & 1.04 & 2 & 3 & 4 & 4.5 & 5 & 5.21 \\ \hline
**Collision Possibility/\(\%_{\text{ee}}\)** & 0.1 & 1.9 & 6.5 & 14 & 28.2 & 33.4 & 46.5 & 50.2 \\ \hline \hline \end{tabular}
\end{table}
Table 7: Possibility of (20,16) CRC collision.  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline
**Bit Error Rate/\%** & 0.1 & 0.3 & 0.5 & 1.04 & 2 & 3 & 4 & 4.5 \\ \hline
**Average Sending Times** & 1.0178 & 1.049 & 1.086 & 1.174 & 1.341 & 1.511 & 1.704 & 1.803 \\ \hline
**Effective Throughput** & 0.983 & 0.953 & 0.921 & 0.852 & 0.746 & 0.662 & 0.587 & 0.555 \\ \hline \hline \end{tabular}
\end{table}
Table 8: Average sending times of different error rates.  
of interconnects increases with the decrease of spacing. The B2 rate decreases with the decrease of spacing, which means that the bandwidth improvement ratio of the hardening design decreases. The reliability design guarantees the accuracy of signal transmission and allows the decrease of the interconnection distance while maintaining the original frequency. The bandwidth is increased by tolerating a part of the crosstalk error with the reliability design. With the decrease of the interconnection spacing, the improvement of this method become lesser.  
For NoC design, we hope that each IP has enough bandwidth allocation. In fact, the area of a chip is limited, which leads to the limitation of the wiring area and bandwidth for each IP. The current digital integrated circuit design, especially regarding router design with large traffic, often adopts a lower frequency and smaller interconnection spacing in order to pursue greater bandwidth. However, the premise of adopting this method in the stage of layout is to change the NoC design from an isomorphic design to a heterogeneous design, which increases the complexity of router design.  
In this paper, a BFRS is proposed to formulate the relationship between bandwidth and interconnect parameters, which determines the chip area with the IP area. By using the proposed model in the analysis stage of the integrated circuit library, an evaluation model for length, spacing, working frequency and bandwidth could be established. The length and spacing of the interconnects between each route are determined by combining the area size and bandwidth demand analysis of the IP selected.