## 1 Introduction  
The rapid evolution of 5G New Radio (NR) has significantly transformed wireless communication by enabling higher data rates, lower latency, and improved spectral efficiency. A key component of this advancement is Frequency Range 1 (FR1), spanning from 410 MHz to 7125 MHz, which serves as the backbone for early 5G deployment [1, 2, 3]. The FR1 spectrum offers notable advantages due to its favorable propagation characteristics, compatibility with existing cellular infrastructure, and support for multiple duplexing schemes, including Frequency Division Duplex (FDD) and Time Division Duplex (TDD) [4]. As wider bandwidths and higher operating frequencies become increasingly important, the design of high-performance RF front-end circuits faces new challenges, necessitating the development of compact, tunable, and power-efficient components. Inductive elements are fundamental building blocks in RF front-end circuits, playing critical roles in applications such as low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), impedance matching networks, and tunable filters. While passive spiral inductors have traditionally been favored for their simplicity, they present several drawbacks, including large silicon area requirements, limited tunability, and significant Q-factor degradation due to substrate losses [5]. These limitations become more pronounced at higher frequencies, making passive inductors less suitable for 5G NR (FR1) applications. To address these issues, recent research has increasingly focused on inductor-less architectures [6]. In this context, active inductors have emerged as promising alternatives, offering wide tunability, high inductance density, and improved integration with standard CMOS processes. However, practical deployment of active inductors is hindered by challenges such as low Q-factors, increased noise, and higher power consumption. In the literature, a wide range of active inductance simulators has been proposed, classified based on their active/passive component configurations and whether they generate grounded or floating inductances. Examples include:  
* Current-feedback operational amplifiers (CFOAs) [7; 8; 9];
* Current differencing transconductance amplifiers (CDTAs) [10];
* Voltage differencing differential input-buffered amplifiers (VD-DIBAs) [11; 12];
* Differential voltage current conveyors (DVCCs) [13];
* Differential current conveyors (DCCIIs) [14];
* Fully differential current conveyors (FDCCIIs) [15];
* Second-generation current conveyors (CCIIs) [16];
* Third-generation current conveyors (CCIIs) [17];
* Differential difference current conveyors (DDCCs) [18; 19; 20];
* Four-terminal floating nullors (FTFNs) [21];
* Operational transconductance amplifiers (OTAs) [22; 23], among others [24]. Among these, OTA-based active inductors, often implemented using gyrator-C topologies, have gained particular prominence due to their low transistor count, simplified architecture, and favorable high-frequency characteristics [23]. Several studies have proposed techniques to enhance the performance of gyrator-C-based active inductors. Negative resistance compensation [25] is one such method, improving the Q-factor by offsetting resistive losses using negative impedance converters (NICs) or cross-coupled transistors, without significant power overhead. Another widely adopted approach is the cascode topology [26], which improves linearity, frequency response, and circuit stability by stacking transistors to increase output impedance, thus enhancing bandwidth and the Q-factor. Feedback-based techniques, including shunt and series feedback, are also employed to enhance inductance and the Q-factor while maintaining low power dissipation [27; 28]. Additionally, advancements in fabrication technologies, such as FinFET [29], silicon-on-insulator (SOI) [30], and gallium nitride (GaN) [31], have reduced substrate losses and parasitic effects, further improving performance.