# LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems
## 6 Conclusions  
In this paper, we proposed a dual-mode LDPC decoder for 5G NR systems. This design can support the rate-11/13 BG 1 and rate-5/7 BG 2 matrices. We adopted the layered decoding schedule with 64 parallelisms for hardware implementation to reach the throughput requirement of the 5G standard. Additionally, the sorter in the CNU was replaced by a grouping search to reduce the critical burden of the CNU. This saves half of the comparator demand at the same calculation speed, with a decline in the decoding capability. To alleviate the decline in the decoding capability, we proposed a compensation scheme to revise the probabilistic second minimum using the first minimum and proportion fixing. Compared to the SMA-MA, the proposed compensation scheme is more complete and exhibits a better decoding performance. The proposed INPMSA also achieves the same decoding capability as the rExMin algorithm and accelerates operations at the comparator stage. Finally, the post-layout implementation of the proposed dual-mode LDPC decoder was achieved using the TSMC 40 nm CMOS process at an operating frequency of 294.1 MHz, a core area of 3.24 mm\({}^{2}\), and power consumption of 313.3 mW. The decoding throughput can reach at least 10.86 and 5.84 Gb/s when the mode is BG 1 and BG 2, respectively. The throughput does not consider early termination, so the higher throughput can be achieved at a higher SNR.  
**Author Contributions:** Conceptualization, C.-H.L. and C.-X.W.; methodology, C.-H.L. and C.-X.W.; software, C.-X.W.; validation, C.-H.L., C.-X.W. and C.-K.L.; formal analysis, C.-H.L. and C.-X.W.; investigation, C.-H.L. and C.-X.W.; resources, C.-X.W.; data curation, C.-X.W.; writing--original draft preparation, C.-H.L. and C.-X.W.; writing--review and editing, C.-H.L. and C.-K.L.; visualization, C.-H.L. and C.-K.L.; supervision, C.-H.L. and C.-K.L.; project administration, C.-H.L.; funding acquisition, C.-H.L. All authors have read and agreed to the published version of the manuscript.  
**Funding:** This research was supported in part by Ministry of Science and Technology, Taiwan, under grants MOST 108-2221-E-155-046 and 109-2221-E-155-006.  
**Acknowledgments:** The authors would like to thank Taiwan Semiconductor Research Institute (TSRI) for the technical support.  
**Conflicts of Interest:** The authors declare no conflict of interest.  
\begin{table}
\begin{tabular}{c c c c c} \hline
**Decoders** & **This Study** & [24] & [23] \\ \hline Implementation & Post-layout & Post-layout & Post-synthesis \\ Standard & 5G NR & 5G NR & 5G NR \\ Technology \(S\) (nm) & 40 & 28 & 65 \\ Voltage \(U\) (v) & 0.9 & 0.9 & 1.0 \\ Algorithm & INPMSA & NMSA & CMSA \\ Decoding schedule & Layered & Layered & Layered \\ Parallelism & 64 & N/A & 56 \\ Quantization (bit) & 8 & 5 & 4 \\ Core area (mm\({}^{2}\)) & 3.24 & 1.97 & 1.49 \\ Frequency (MHz) & 294.1 & & 556 & 750 \\ Code rate & 11/13 (BG 1) & 5/7 (BG 2) & 1/3 (BG 1) & 1/2 (BG 2) & 1/3 (BG 1) \\ Max. code length (bit) & 9984 & 5376 & 25,344 & 19,200 & 3808 \\ Iteration & 6 (Max.) & 6 (Max.) & 5 (Avg. \%) & 4.92 (Avg. \%) & 10 (Max.) \\ Throughput (Gb/s) & 10.86 & 5.84 & 6.64 & 7.92 & 3.04 \\ Avg. power (mW) & 313.3 & - & 232 & - & 259 \\ NAE \(\&\) (bits/mm\({}^{2}\)) & 11.40 & 6.13 & 2.97 & 3.54 & 7.18 \\ NEE \(\$\) (pl)/bit) & 28.85 & - & 49.91 & - & 42.47 \\ \hline \end{tabular} \(\&\) Normalized area efficiency (NAE) = Throughput/(Area \(\times\) Frequency) \(\times\) Normalized area factor (=(S/40)\({}^{2}\)). \(\$\) Normalized energy efficiency (NEE) = (Power/Throughput) \(\times\) Normalized energy factor (=(40/5) \(\times\) \((0.9/U)^{2}\)). \(\$\) Average iteration is achieved using the early termination scheme.  
\end{table}
Table 3: Chip comparison of QC-LDPC decoder ASICs for 5G NR systems.