## 3 Experimental System-Level Setup
### Measurement Procedure  
In accordance with the measurements obtained, a setup with a realistic operation of a base station is realized as shown in Figure 1. At the transmitter/receiver, the signals are first frequency shifted by a digital intermediate frequency (IF) set at 76.8 MHz using dual channel 16-bit digital-to-analog converters (DACs) with a synchronization clock set at 307 MHz. The IF-to-RF up-conversion path uses an IQ modulator driven by a local oscillator (LO) that is used at 2 GHz to be mixed with the baseband signal. The main program structure is created through MATLAB that is connected to the FPGA and can download/upload data frame from/to the synchronous instantiated ROM memory on the FPGA. The signals are generated in MATLAB, stored to RAM instantiated memories, and processed by FPGA (Arria V GX-360 KLE) on the board. The FPGA controls all the signal sequences, feeds the DAC board (TI transmitter TSW30H84) with baseband signals, and acquires the digital samples from the analog-to-digital converter (ADC) board (TIfeedback/receiver TSW1266 with a dual-channel ADC ADS5402). In the DAC board, two 32-bit numerically controlled oscillators (NCOs) are configured to shift the two transmitted signal to IF frequencies \(\omega_{\text{IF,Tx}_{1}}\) and \(\omega_{\text{IF,Tx}_{2}}\), respectively, which are then modulated by a selected radio frequency carrier \(\omega_{\text{RF,C}}\).  
At the mixing process, the signal is up-sampled with a factor 4 filter interpolation using a sampling rate of 1.2 GHz in the up-conversion. Note that the local oscillator power of \(-11\) dB also contributes to the output power, a calibration procedure is given in order to set an adequate input level at the \(P_{in}\), and then the resulting signal is amplified through a predriver (Mini-Circuits ZRL-2300+). A 30 dB attenuator is placed at the PA output simplification to perform PA characterization and measurements of a medium-high PA (Mini-Circuits ZHL-42W+). Given the FPGA design, it is identified that low-voltage differential signaling (LVDS) serializer/deserializer (SERDES) circuitry introduces the most prominent latency across the channel Tx/Rx. A time alignment is jointly performed from a cross-correlation simultaneously from the real-time at the Tx/Rx data, in concordance. Moreover, during the experiments to provide fair comparisons with the DPD methods, a wide-band receiver is used to acquire the PA output at a sampling rate of 614 Msps, which is twice the transmission bandwidth: 307 MHz.  
Table 1 shows the main electrical characteristics of the PA NXP Semiconductors 10 W, at 2.34 GHz, and Table 2 show that of the device ZHL-42W+ at 2000 MHz 32.24 dBm under test; they contain the biasing and main setting established during the performed device measurements.  
\begin{table}
\begin{tabular}{c c} \hline \hline \multicolumn{1}{c}{**PA NXP 10 W @ 2.34 GHz**} \\ \hline
**Parameter** & **Values** \\ \hline Gain & 12.26 dB @ 2.34 GHz \\ PA input Power & 23.84 dBm \\ PA output Power & 36.10 dBm \\ Device biasing & V\({}_{\text{DS}}\) = 50 V, I\({}_{\text{DS}}\) = 54 mA \\ \hline \hline \end{tabular}
\end{table}
Table 1: Features of the NXP 10 W PA.  
Figure 1: Experimental measurement testbed setup based on ARRIA V Board for a radio frequency power amplifier (RF-PA).