# An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System
## 5 Experiments and Results
### Experimental Results and Performance Evaluation  
#### 5.2.1 Superscalar Pipeline Data Storage and Exchange Engine  
We verified the bandwidth and access efficiency of the proposed hardware architecture through the use of an FPGA. The theoretical bandwidth of the two off-chip DDR3 SDRAMs of the processing board with 64 bit storage bit width and 800 MHz operating clock frequency is:  
\[B=800\;\mathrm{M}\times 64\;\mathrm{bit}\times 2\times 2=25\;\mathrm{GB/s} \tag{13}\]  
Figure 17: Schematic diagram of experimental testing platform and process. After considering loss of efficiency caused by row activation, pre-charging, etc., the actual DDR3 read and write bandwidth is:  
\[B_{\eta}=B\times\eta \tag{14}\]  
where \(\eta\) is the access efficiency. When we use the above formula to calculate the access efficiency, we can obtain Table 6 indexes by recording the actual measured range and azimuth access bandwidth. Recent SAR imaging processing implementations on FPGA platforms are also compared in this section. Table 7 shows how the hardware implementations of the data storage and exchange method proposed in this paper and a few other recent hardware implementation schemes compare in terms of how well they perform. The range and azimuth access bandwidths in this table show the maximum bandwidth of data storage access in this direction. \"Matrix Transposition Time\" refers to the time interval from the start of writing DDR3 in the range direction to the completion of reading DDR3 data in the azimuth direction, which can be calculated from the access bandwidth of range and azimuth. \"Number of RAM buffer\" refers to the data buffer RAM number for a single Chip DDR3. The data storage and exchange engine of the SAR imaging system in this paper is implemented based on superscalar pipeline. Compared with non-pipeline and scalar pipeline design, superscalar pipeline design has certain performance improvements in terms of pipeline throughput rate, efficiency, and speedup ratio. Subsequently, a comparison of the pipeline performance of the superscalar pipeline designed in this paper and the tradi \begin{table}
\begin{tabular}{c c c c c} \hline  & **Range** & **Range** & **Azimuth** & **Azimuth** \\  & **(Read)** & **(Write)** & **(Read)** & **(Write)** \\ \hline Theoretical Bandwidth & 25.0 GB/s & 25.0 GB/s & 25.0 GB/s & 25.0 GB/s \\ Measured Bandwidth & 16.6 GB/s & 16.0 GB/s & 20.0 GB/s & 18.3 GB/s \\ Access Efficiency & 66\% & 64\% & 80\% & 73\% \\ \hline \end{tabular}
\end{table} 
Table 6: The read and write bandwidth performance of the data storage exchange engine based on superscalar pipeline proposed in this paper. \begin{table}
\begin{tabular}{c c c c c c c} \hline  & **Ours** & **[35]** & **[34]** & **[42]** & **[33]** & **[43]** \\ \hline Data Granularity & 16,384 \(\times\) 16,384 & 16,384 \(\times\) 16,384 \(\times\) 16,384 & 16,384 \(\times\) 16,384 \(\times\) 16,384 & 16,384 \(\times\) 16,384 & 8192 \(\times\) 8192 \\ FPGA & Xilinx & Xilinx & Xilinx & Xilinx & Xilinx & Xilinx \\  & XC7 VX690T & XC7 VX690T & XC7 VX690T & XC6 VLX315T & XC6V5X760T & XC7 VX330T \\ DDR3 channel & 2 & 2 & 2 & 1 & 1 & 1 \\ number & 16.6 GB/s & 10.24 GB/s & 8.3 GB/s & 4.8 GB/s & 6.0 GB/s & - \\ Range accs & 20.0 GB/s & 10.24 GB/s & 9.62 GB/s & 4.8 GB/s & 2.37 GB/s & - \\ Efficiency & 66\% & 80\% & 69\% & 74\% & 93.75\% & - \\ Azimuth access & 80\% & 80\% & 80\% & 74\% & 74\% & - \\ efficiency & & & & & & \\ Matrix & & & & & & \\ transposition & 0.225 s & 0.43 s & 0.45 s & 0.83 s & 1.18 s & 0.33 s \\ time & & & & & & \\ Buffer RAM & 8 & 4 & 4 & 4 & 8 & - \\ number & & & & & & \\ Superscalar & & & & & & \\ pipeline & Yes & No & No & No & No & No \\ supported or not & & & & & & \\ \hline \end{tabular}
\end{table} 
Table 7: Table of the performance comparison between the hardware implementation of the data storage and exchange method proposed in this paper and the recent scheme. tional non-pipeline and scalar pipeline will be conducted.