# A Model-Based Engineering Approach for Evaluating Software-Defined Radio Architecture
## 4 Architecture Definition
### Application of the Architecture Definition Process for the Development of Alternative Archeteure 1  
The development of the SDR-MM architecture was performed in three steps, as outlined in the architecture definition section. The _transfer analog to digital_ function is decomposed into 11 Level 1 subfunctions. Then, some of the level 1 subfunctions are further broken down into lower-level functions at level 2, as illustrated in Figure 7. Only two essential functions are highlighted in this work: managing heat and transferring the analog RF signal to digital data. Figure 8 illustrates not only the interaction and interfaces between level 1 functions but also shows the functional allocation to the conceptual elements of the SDR-MM. The functions _manage heat_ and _provide structural support for SDR-MM elements_ are allocated to an enclosure while _down convert analog RF signals to analog IF frequencies, digitize the IF signal, convert the analog IF signal to real digital IF samples_, and _convert real digital IF signal to complex digital baseband data_ are allocated to an RF tuner, an ADC, and an FPGA, respectively. The elements and structure of this architecture are illustrated in Figure 9. Architecture 1 does not include a heat sink, as shown in Figure 9, and using the simulation capabilities of the MBSE tool, the module was tested under different signal performance scenarios with varying numbers of NB outputs. Figure 4a illustrates that with a single FPGA configuration, the total power dissipation can reach up to 70 W with a maximum of 30 W coming from the FPGA. Based on the assumption that each NB output can dissipate 6 W, a single FPGA can handle 3 outputs. However, due to heat constraints, this architecture can only support one NB output, as shown in Figure 4b, with the maximum temperature reaching 129 \({}^{\circ}\)C.  
The resulting Architecture 1 is limited by its heat dissipation capabilities, despite meeting CONOP with a 1 \({}^{\circ}\)C margin. As previously mentioned, the _manage heat_ function is performed by an enclosure, making a sensitivity analysis on enclosure parameters crucial in testing the possibility of improving heat dissipation capabilities. Figure 10a,b depict the SDR-MM operating at different FPGA loads and at the given CEAE characteristics (convection transfer coefficient and air temperature). The results indicate that material thermal conductivity and enclosure thickness alone are not enough to enhance heat dissipation, as there is no significant impact on AEST. A sensitivity analysis was also performed on the CEAE characteristics and showed that power dissipation can be improved by higher heat transfer coefficients or a colder environment. However, since we are designing the SDR-MM, not the CEAE, a passive or active thermal solution could enhance heat dissipation. Figure 7: Functional breakdown of Architecture 1 using SysML activity decomposition map. Figure 8: SDR-MM system behavior of Architecture 1 captured with activity diagram. Figure 9: Internal block diagram (IBD) of Architecture 1 depicting SDR-MM elements and structure. Due to the proprietary nature of SDR-MM, it can be challenging to determine the breakdown of costs and mass. An estimation method was used to overcome this, which involved looking at similar modules developed by other vendors for similar CONOP. The electronic COTS hardware, assembly, and SW programming for Architecture 1 with a single channel (a single FPGA) were estimated to cost USD 10,000. Additionally, the Enclosure was estimated to cost USD 80, using the DFMA tool [27], and this cost was added to the total. Similarly, the mass of all the SDR-MM elements was estimated to be 0.5 kg, and the Enclosure mass was estimated to be 1.38 kg. Application of the Architecture Definition Process for the Development of Alternative Architecture 2  
The steps outlined in the architecture definition section are also implemented to develop this architecture. The main function is broken down into twelve subfunctions.