## 3 HPLDDC Control Loop
### Constant-Current Source Driving and CLC Using PIAP Control  
A circuit configuration diagram of CLC using the PIAP control is depicted in Figure 9. In Figure 9b, during Phase I, the HPLDDC is dominated by the VLC and the soft-start module of the SBBC controller, and then \(V_{o}\) can slowly increase to avoid the voltage overshoot occurrence. When the \(I_{o}\) increase has reached a current value of \(I_{1}\), a switch, st, (Figure 9a) connects to the position, s\({}_{1}\); thus, the CLC can implement P control during Phase II (Figure 9b), hence, the response speed of CLC can be promoted to mitigate the start-up current spike. In Phase III, \(I_{o}\) has reached the target CC \(I_{cc}\), the st connects to the position, s\({}_{2}\), and then the CLC uses the PI control to regulate the HPLD driving current in the CC state. The aforementioned three CC control methods can be compared and are listed in Table 1.  
The transfer function (TF) of the duty cycle to the SBBC output current for the buck or boost operation can refer to studies [20; 21]; both models have been derived based on a PWM switch model technology from previous studies [16; 22; 23]. Therefore, the SBBC transfer function is defined as follows:  
\[G_{kt}(s)=\widetilde{i}_{o}/\widetilde{d}=k_{con}(nu_{2}s^{2}+nu_{1}s+nu_{0})/ (de_{2}s^{2}+de_{1}s+de_{0}). \tag{11}\]  
According to the buck or boost operation of SBBC, these parameters in (11) are listed in Table 2. In Table 2, \(r_{c}\) represents the capacitor's ESR. \(r_{L}\) represents the inductor's wire-wind resistance. \(r_{hpld}\) represents the HPLDs' equivalent dynamic resistor, which can be calculated as:  
\[r_{hpld}=3(V_{LD2}-V_{LD1})/(I_{LD2}-I_{LD1}), \tag{12}\]  
where \(V_{LD1}\) and \(V_{LD2}\) are HPLDs' operating forward voltages, and \(I_{LD1}\) and \(I_{LD2}\) are HPLDs' operating forward currents. Figure 8: HPLDDC’s voltage-loop controller (VLC) and current-loop controller (CLC) control loops. The current-loop control block diagram of FSBBC is illustrated in Figure 10. In Figure 10, the FSBBC gain is \(G_{tt}\), the FSBBC controller gain is \(G_{ctlr}\), the CLC gain using the P control is \(G_{cca(P)}\), the CLC gain using the PI control is \(G_{cca(P)}\), and a feedback gain is a constant, \(k_{c}\). In addition, the soft-start function would affect the start-up current spike, hence, it should be considered; \(G_{ss}\) represents the soft-start control gain. Despite whether the SBBC controller implements the buck or boost control, a linear polynomial of the \(d\)-\(v_{cca}\) characteristic is expressed as follows:  
\[d=k_{cca}v_{cca}+r, \tag{13}\]  
where \(d\) is the PWM duty cycle that incorporates the large-signal, \(D\), with the small-signal, \(\vec{d}\). \(v^{\prime}{}_{cca}\) is the CLC output voltage that incorporates the large-signal, \(V^{\prime}{}_{cca}\), with the small-signal, \(\vec{v}^{\prime}{}_{cca}\). Both \(k_{cca}\) and \(r\) are constants. Substitution of \(d=D+\vec{d}\) and \(v^{\prime}{}_{cca}=V^{\prime}{}_{cca}+\vec{v}^{\prime}{}_{cca}\) into Equation (13), results in the SBBC controller TF being expressed as follows: \begin{table}
\begin{tabular}{c c c c} \hline \hline
**CC Control Technology** & **Driver Output Mode** & **Driving Current Compensation** & **Start-up Current Spike Mitigation** \\ \hline CC Sink & CVOM & N/A & N/A \\ \hline CC Source Using & & & \\ Proportional-Integral (PI) Control & CVOM \& CCOM & PI compensation & N/A \\ \hline CC Source Using & & & \\ Proportional-Integral Associating & CVOM \& CCOM & P and PI compensations & Effectual \\ Proportional (PIAP) Control & & & \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Three constant-current (CC) control methods.