## 5 The Hardware Implementation of the Dual-Axis-Based Solar Tracking System
### Main and Modified Versions of the BILBO Architecture  
The BILBO is an embedded and offline BIST architecture because it employs existing flip-flops (FFs) from the CUT to deploy the test pattern generator (TPG) and output response analyzer (ORA) units. The CUT is therefore divided into groups of FFs and groups of combinational logic. Each group of FFs is enlarged with additional logic to ensure multiple modes of operation. When the BILBO functions as a TPG, it provides pseudo-random test patterns by operating as an LFSR. When the BILBO functions as an ORA, it performs multiple-input signature analysis by operating as a multiple-input signature register (MISR). The application of a BILBO to a CUT in its simplest form is depicted in Figure 6 where the FFs at the primary inputs and outputs are used to deploy two BILBOs. The BILBO at the primary inputs generates pseudo-random test patterns as a TPG, while the BILBO at the primary outputs operates as a MISR-based ORA, thus performing test vector compression. Consequently, the BILBO is a test-per-clock BIST method since a new test pattern is applied to the CUT and a new output response is compacted during each clock cycle of the BIST sequence [77]. The additional gates added to the existing flip-flops to create the BILBO (as it was originally proposed) are illustrated in Figure 7 for a 4-bit BILBO implementation. For each FF, one exclusive OR gate, one AND gate, and one NOR gate are added [78]. For each BILBO, one multiplexer, one inverter, and one or more exclusive OR gates (needed to construct a primitive characteristic polynomial) are added. As can be observed in Figure 7, the LFSR mode of operation uses an external feedback implementation for the characteristic polynomial expressed in Equation (5):  
\[P(x)=x^{4}+x+1 \tag{5}\]  
There are two control leads used to switch the modes of operation of the BILBO. During BIST operation, the MISR mode is used for output data compaction. To provide a TPG during BIST, the Z inputs to the BILBO must be held at a constant logic 0. This forces the MISR to now operate as an LFSR generating a maximum length sequence of pseudo-random test patterns. This requires additional logic and/or additional control inputs to the BILBO. For example, additional AND gates can be added to the Z inputs to force all Z inputs to logic 0 under the control of a third control input, when the BILBO is to operate as an LFSR-based TPG. Alternatively, each of the two-input AND gates at the  
Figure 6: BILBO architecture comprising a combinational circuit and latch structure. Figure 7: The conventional BILBO architecture is implemented with NOR blocks and a multiplexer. Z inputs, shown in Figure 7, can be expanded to three-input AND gates driving the third input. An alternate approach is to provide independent control of the multiplexer using an additional control input (as shown in parentheses in Figure 7) [78]. Therefore, the BILBO as originally proposed was not directly capable of operating as a TPG. A final modification to the BILBO overcomes the TPG mode of operation problem discussed above with minimum area overhead and without the need for the third control input. This modification is illustrated in Figure 8 for a 4-bit implementation where the architecture makes use of NAND gates instead of NOR gates. The modes of operation for this version of the BILBO are given as a function of the two control inputs, and the BILBO is initialized using the scan mode of operation. This version of the BILBO has been more frequently used in applications since the mid-1980s than the original version of the BILBO. Regarding the BILBO evolution stages, the original implementation required pin B1 to control both TPG and MSIR modes during operation. Moreover, forcing logic 0's on Z inputs caused MISR to function as an LFSR device for test pattern generation, while the LFSR could only operate with external EXOR gates. The later BILBO implementation added a control signal B3 to control the TPG and MISR modes more effectively.