# Research on Clock Synchronization of Data Acquisition Based on NoC
## 4 The Implementation of Clock Synchronization  
### The Implementation of PTP  
(1) The implementation of the master node  
According to Figure 6, master clock node R5 includes master clock, master clock timestamp, and master clock PTP. The master clock PTP module is responsible for generating sync, follow_up, and delay_resp messages and sending them to each slave node, as well as receiving delay_req messages sent by each slave node. In this paper, a state machine is adopted to implement the receiving and sending of the PTP clock message, and its state transition diagram is shown in Figure 9.  
After power-up reset, the state machine enters the IDLE state. In IDLE state, once the master clock is stable, a pulse signal sync_start is generated to enter the SYNC state. In SYNC state, the sync message is encapsulated according to the format of the sync message, and then, the request signal req_to_x (e/s/w/n) is sent to the east, south, west, and north directions. After the master node receives the feedback signal gran_from_x from each direction, it sends the sync message to the four ports, records the sending time as T1, and saves it, and then, generates the sync_end pulse signal to enter the FOLLOW state. \begin{table}
\begin{tabular}{c c c c c} \hline  & **[33-31] bit** & **[30-8] bit** & **[7-4] bit** & **[3-0] bit** \\ \hline Sync & 3’b001 & 23’b0 & 1111 (dest) & 0101 (source) \\ Follow\_up & 3’b010 & T1 (23 bit) & 1111 (dest) & 0101 (source) \\ Delay\_req & 3’b011 & 23’b0 & 0101 (dest) & Slave\_addr (source) \\ Delay\_resp & 3’b100 & T4 (23 bit) & Slave\_addr (dest) & 0101 (source) \\ \hline \end{tabular}
\end{table} 
Table 1: Improved PTP protocol format. Figure 9: State transition diagram of the master node. In the FOLLOW state, the follow_up message is encapsulated in the format of follow_up message, which carries the T1 timestamp. Then, the req_to_x (e/s/w/n) request signal is sent to the east, south, west, and north. After receiving the grant_from_x signal, the encapsulated follow_up message is sent to the four ports, and the follow_end pulse signal is raised to enter the DELAY_REQ state. In the DELAY_REQ state, the request signal req_from_x (e/s/w/n) is received from four directions, and the response signal grant to_x (e/s/w/n) is given back. Each delay_req message sent from the slave node is then received and the arrival time of delay_req message is recorded as T4_x (1/3/4/6/7/9) according to the address of the corresponding source node in the message. In addition, a node pulse signal T4_x_end is generated upon receipt of each delay_req message from the slave node, which is then encapsulated in the delay_resp message format as delay_resp_x (1/3/4/6/7/9). When the package is completed, it is sent to the slave node and the corresponding delay_resp_x_flag is raised until delay_req_end goes high. Then, the delay_resp_x_flag signal is changed to the low level, and the state machine returns to the IDLE state. So far, the master-slave node clock message interaction is completed. The implementation of the transparent node  
Transparent clock nodes are responsible for forwarding clock messages, such as node 2 and node 8 in Figure 4. They communicate with neighboring nodes in the NoC clock synchronization system and forward clock messages. For example, if clock messages are sent to each other from slave node 1 and master node 5, the clock messages need to be sent to node 2 after a successful handshake with transparent clock node 2, and then, node 2 will communicate with the corresponding node by handshake and forward clock messages to it. This communication mode makes the clock message stay on the forwarding node for only 1 clock cycle. When the master clock node sends sync and follow_up messages to each slave clock node, since slave clock nodes 4 and 6 are directly connected to the master clock node, the message does not need to be forwarded, but slave clock nodes 1, 3, and 7, 9 need to be forwarded through transparent clock nodes 2 and 8, respectively.