## 3 Analysis of the Switching Transients
### Turn-Off Switching Transients  
It is known that the turn-off switching transients are a reversely symmetrical process of the turn-on switching transients, in which the channel can also be equivalent to a nonlinear resistance, voltage-controlled current source, or an open circuit. Therefore, some repeated equations are omitted in the derivation of the stage equations for the turn-off switching transients. Stage 6[16; 17; 18] Turn-Off Delay Time:Before the gate source voltage \(v_{gs}\) reduces to the Miller Voltage \(V_{miller}\), which is governed by (23), the SiC MOSFET power device operates in the ohmic region. It is assumed that the drain current \(i_{d}\) remains unchanged (\(i_{d}=I_{DD}\)) at this stage. As shown in Figure 5a,the gate-source capacitance and the gate-drain capacitance are being discharged through \(R_{g}\) and \(L_{s}\). The circuit equations are shown from (24) to (26):  
\[V_{mil}=\frac{I_{o}}{g_{f}}+V_{th} \tag{23}\]  
\[V_{SS}=R_{SS}i_{g}+L_{g}\frac{di_{g}}{dt}+v_{gs}+L_{s}(\frac{di_{d}}{dt}+\frac{ di_{g}}{dt}) \tag{24}\]  
\[i_{g}=(C_{gs}+C_{gd})\frac{dv_{gs}}{dt}-C_{gd}\frac{dv_{ds}}{dt} \tag{25}\]  
\[i_{s}=\frac{v_{ds}}{R_{on}}+C_{gs}\frac{dv_{gs}}{dt}+C_{ds}\frac{dv_{ds}}{dt} \tag{26}\]  
where \(R_{SS}=R_{g\_off}+R_{g\_int}\). As with the stage 1, there are three independent state variables: the drain current \(i_{g}\), the gate-source voltage \(v_{gs}\) and the drain-source voltage \(v_{ds}\), and the state equations derived from the above equations  
Figure 5: Equivalent circuits for the turn-off transients. (**a**) Stage 6 and Stage 7. (**b**) Stage 8. (**c**) Stage 9. (**d**) Stage10. are shown in Appendix A Equation (A6). Since the device is still activated, the loss during this period is conduction loss \(E_{cond}\), which can be calculated as:  
\[E_{cond2}=\int_{t_{5}}^{t_{6}}\dot{t}_{d}^{2}R_{on}dt \tag{27}\]  
Stage 7[17; 18; 19; 17] Voltage Rising Time IDuring this stage, the power device still works in the ohmic region until the drain-source voltage \(v_{ds}\) reaches \(v_{gs}-V_{th}\). Therefore, the drain current \(i_{d}\) stays constant at \(I_{DD}\) and the gate-source voltage \(v_{gs}\) (almost) remains at the Miller voltage. The equivalent circuit and equations during this period are the same as the previous one, while the loss during this period is regarded as the switching loss \(E_{sw}\) and can be calculated as:  
\[E(\mathrm{I})_{sw\_\_\_\_\_\_}\mathcal{T}=\int_{t_{6}}^{t_{7}}i_{d}v_{ds}dt \tag{28}\]  
\[E(\mathrm{II})_{sw\_\_\_\_}\mathcal{T}=\int_{t_{6}}^{t_{7}}i_{ch}v_{ds}dt \tag{29}\]  
Stage 8[18; 19; 19; 19] Voltage Rising Time IIWhen the drain-source voltage \(v_{ds}\) reaches \(v_{gs}-V_{th}\), the device begins to operate in saturation region. Therefore, the channel is equivalent to a voltage-controlled current source, as shown in Figure 5b. The drain-source voltage \(v_{ds}\) continues to increase until the forward voltage \(v_{f}\) of the SBD decreases to the forward voltage \(-V_{f}\). The voltage slew rate will be faster than in the previous stage, since the value of junction capacitance significantly decreases with the increase in drain-source voltage \(v_{ds}\). A part of \(I_{DD}\) will be flowing through the freewheeling diode to discharge the \(C_{f}\), which will be causing the drain current id drop. During this period, the channel current \(i_{ch}\) is also governed by (6). Hence the drain current id expression is changed to (10) and the rest of the circuit equations are the same as the stage 4 and the state equations are shown in Appendix A Equation (A8). During this period, the switching loss \(E_{sw}\) is given by (30) and (31).