## 2 SPDT Switch Design  
The SPDT SW1 is designed via a 1P9M 90 nm CMOS process. Figure 3 shows a cross-sectional illustration diagram of the 90 nm CMOS process. The interconnection lines and the TL inductors are placed on the 3.4 \(\upmu\)m thick topmost metal (MT\({}_{9}\)) to minimize the resistive loss. The bottom-most metal (MT\({}_{1}\)) with a pattern density of 70% is used as the ground plane of the TLs. The distance (D) between MT\({}_{9}\) and MT\({}_{1}\) is 6.085 \(\upmu\)m. To avoid performance degradation, the space between the TLs is at least 5 times that of D (i.e., 30.425 \(\upmu\)m) to control the mutual coupling and parasities [17; 18; 19; 20]. The RX path is an L-network constituting a series impedance (of a parallel inductance L\({}_{1}\) and a DTMOS-R M\({}_{2}\)) and a parallel DTMOS-R M\({}_{3}\). This leads to high linearity in the RX mode and decent isolation in the TX mode. Moreover, the TX path is a \(\pi\)-network consisting of a parallel DTMOS-R M\({}_{1}\), a series \(\lambda\)/8 TL, and a parallel capacitance, C\({}_{\rm ant}\). A low IL in the TX mode and good isolation in the RX mode are achieved since the series \(\lambda\)/8-TL in conjunction with the parallel C\({}_{\rm ant}\) and parasitic capacitance of the DTMOS-R transistors M\({}_{1}\)/M\({}_{2}\) constitute an equivalent \(\lambda\)/4-TL with a characteristic impedance (Z\({}_{\rm C}\)) of 50 \(\Omega\). The gate width of transistors M\({}_{1}\)/M\({}_{2}\) (96-/125 \(\upmu\)m for SPDT SW1) is determined according to the required parallel capacitance, C\({}_{\rm P}\) (in Figure 4), to constitute a \(\lambda\)/8-TL-based \(\lambda\)/4-TL in the TX path. A DTMOS-R transistor, M\({}_{3}\), with a relatively large gate width (168 \(\upmu\)m for SPDT SW1) is adopted to achieve a better TX-to-RX isolation in the TX mode. The cost is a slight increase in IL in the RX mode due to lower off-state parallel resistance R\({}_{\rm off3}\). In other words, a trade-off exists between the TX-to-RX isolation in the TX mode and the IL in the RX mode. The reason why the L-type network (in both the RX path and TX path) of the SPDT switch can achieve high linearity and decent isolation in both the RX and TX modes can be explained in more detail as follows. Ideally, in the RX mode, transistors M\({}_{1}\) and M\({}_{2}\) are in the on-state (i.e., short circuit) and M\({}_{3}\) is in the off-state (i.e., open circuit). The \(\lambda\)/8-TL, parallel C\({}_{\rm ant}\), and parallel capacitance of M\({}_{1}\)/M\({}_{2}\) constitute an equivalent \(\lambda\)/4-TL, leading to an infinite input impedance \(Z_{\rm in}\) (i.e., open circuit) looking from the antenna node to the TX node since a short-circuit-loaded \(\lambda\)/4-TL exhibits an infinite \(Z_{\rm in}\). That is, ideally, perfect  
Figure 2: Circuit diagram and chip photo of the SPDT switch in a 0.18 \(\upmu\)m CMOS (SPDT SW2). (antenna-to-TX) isolation in the RX mode is achieved. And perfect IL, linearity, and \(Z_{\text{in}}\) matching (at the RX and antenna nodes) are also achieved. Moreover, ideally, in the TX mode, transistors M\({}_{1}\) and M\({}_{2}\) are in the off-state (i.e., open circuit) and M\({}_{3}\) is in the on-state (i.e., short circuit). Inductance L\({}_{1}\) and the off-state capacitance C\({}_{\text{ds2,off}}\) of M\({}_{2}\) are in parallel resonance (i.e., open circuit) at an operation frequency of 28 GHz, leading to an infinite \(Z_{\text{in}}\) (i.e., open circuit) looking from the antenna node to the RX node. The \(\lambda\)/8-TL, parallel C\({}_{\text{ant}}\), and parallel capacitance of M\({}_{1}\)/M\({}_{2}\) constitute an equivalent \(\lambda\)/4-TL with a \(Z_{\text{C}}\) of 50 \(\Omega\). That is, ideally, no IL in the TX mode is achieved due to the lossless equivalent \(\lambda\)/4-TL with a \(Z_{\text{C}}\) of 50 \(\Omega\) in the TX path and an open circuit of the RX path. And perfect (TX-to-RX) isolation, linearity, and \(Z_{\text{in}}\) matching (at the TX and antenna nodes) are also achieved.