## 3 System Design
### Acquisition in High-Sensitivity Mode
#### 3.4.3 Implementation
The algorithm then searches the time-Doppler frequency grid for the peak value of the computed GPDIT iteration, obtaining the peak value along with an estimation of the Doppler frequency and code phase \(\{S_{max},f_{i},\tau_{j}\}\). Finally, it evaluates a Generalized Likelihood Ratio Test (GLRT) function \(\Gamma_{\text{GLRT}}\), and determines whether the searched signal is detected. If positive, the algorithm declares successful acquisition; otherwise, it returns to the main loop to compute the next successive CAF and the next GPDIT iteration. If a total of 7 GPDIT combinations are computed and the signal is not detected, then the algorithm declares negative acquisition. ```
1: Set the total number of GPDIT iterations \(N_{nc}=7\)
2: Buffer 700 ms worth of samples: \(x_{IN}[0],x_{IN}[1],\ldots,x_{IN}[N\cdot N_{nc}]\)
3: Set the current GPDIT iteration \(n_{nc}=1\)
4: While \(n_{nc}\leq N_{nc}\) do
5: Take the next 100 ms worth of samples from the acquisition buffer: \(x[n]=\{x_{IN}[(n_{nc}-1)\cdot N],x_{IN}[(n_{nc}-1)\cdot N+1],\ldots,x_{IN}[(n _{nc}-1)\cdot N+N-1]\}\)
6: For \(f_{d}=f_{min}\) to \(f_{d}=f_{max}\) in \(f_{step}\)
7: Perform Doppler wipe-off: \(x_{d}[n]=x[n]\cdot e^{-j2\pi f_{d}nT_{s}}\), for \(n=0,\ldots,N-1\)
8: Compute \(X_{d}[k]=FFT_{N}(x_{d}[n])\)
9: Compute \(Y[k]=X_{d}[k]\cdot C[k]\), for \(k=0,\ldots,N-1\)
10: Compute \(R_{n_{nc}}(\tau,f_{d})=\frac{1}{N^{2}}\,1 FFT_{N}(Y[k])\)
11: Compute \(Z_{\text{GPDIT}}(\tau,f_{d})=\sum_{k=1}^{n_{nc}}|R_{k}(\tau,f_{d})|^{2}+2|\sum _{k=2}^{N_{nc}}R_{k}(\tau,f_{d})R_{k-1}^{*}(\tau,f_{d})|\)
12: End for
13: Search the peak value and its indices in the search grid: \(\{S_{max},f_{i},\tau_{j}\}=max_{f,\tau}Z_{\text{GPDIT}}(\tau,f_{d})\)
14: Compute input signal power estimation \(\hat{P}_{IN}=\frac{1}{N}\sum_{n=0}^{N-1}|x[n]|^{2}\)
15: Compute the GLRT function with normalized variance \(\Gamma=\frac{2 NS_{max}}{P_{IN}}\)
16: If \(\Gamma_{\text{GLRT}}>\gamma\) (Compare with threshold value)
17: Declare positive acquisition and provide \(f_{a_{eq}}=f_{i}\) and \(\tau_{acq}=\tau_{j}\)
18: Break;
19: Else
20: If \(n_{nc}=N_{nc}-1\) (last GPDIT iteration)
21: Declare negative acquisition
22: End if
23: End if
24: End while
```  
**Algorithm 1** High-sensitivity acquisition  
The acquisition algorithm is executed collaboratively by the FPGA and the embedded processor, with each component handling a distinct portion of the process. The FPGA is responsible for capturing the samples from the analog front-end and computing the successive CAFs using the captured samples. Concurrently, the embedded processor executes the GPDIT iterations and the CFAR detector. Even though the FPGA manages the majority of the computational workload related to the acquisition process, the embedded processor is actively involved in the acquisition tasks. The embedded processor can simultaneously handle the acquisition process and the other tasks required for the baseband software processing engine. These tasks include the control of the FPGA tracking multicorrelator hardware accelerators, the execution of the telemetry decoders, the computation of GNSS basic measurements, and the derivation of the navigation solutions. The Zynq UltraScale+ XCZU9 EG-2 FFVB1156 All-Programmable MPSoC [28] used to demonstrate the proposed design, features a quad-core embedded processor. Therefore, even if one processor core is devoted to the acquisition process, the other three processor cores remain available for the other tasks, enabling the real-time processing of GNSS signals. Figure 6 shows a detailed view of the FPGA acquisition hardware accelerator depicted in Figure 3. The PL DDR4 memory component shown in Figure 6 is the same as the one shown in Figure 3. The acquisition hardware accelerator comprises two modules: the Sample Capture module and the CAF computation module. When performing acquisition in high-sensitivity mode, the Sample Capture module collects 700 ms worth of samples from the analog front-end and stores the samples into the PL DDR4 memory component.