## Materials and Methods  
The devices were fabricated on (100) surface-oriented silicon-on-insulator (SOI) substrates. One set of substrates had a 20 nm top Si layer and a 102 nm buried SiO\({}_{2}\) (BOX) layer, while the second set of substrates had a 50 nm top Si layer with a 110 nm BOX layer. SiNWs were fabricated using electron beam lithography (EBL) and inductively-coupled plasma (ICP) etching. EBL was performed with a Raith e-Line Plus system at an acceleration voltage of 10 kV, 1200 \(\upmu\)C/cm\({}^{2}\) dose, 30 \(\upmu\)m aperture size, and with 2 nm area beam step size using the negative tone EBL resist, hydrogen silsesquioxane (HSQ) from Dow Corning (X-1541). HSQ is known to have sub 5 nm resolution and high etch resistance [51]. The original 6% HSQ solution was diluted to 2% concentration in methyl isobutyl ketone (MIBK) and spin coated at 2000 rpm for 30 s to yield a 40 nm thick HSQ layer. Then the samples were baked at 90 \({}^{\circ}\)C for 2 min and exposed using the EBL tool. After EBL, the samples were developed with a high-contrast tetramethylmonium hydroxide (TMAH) based development process [52] and dried with a N\({}_{2}\) gun. The HSQ patterns were transferred into the top SOI layer using a SENTECH's ICP-Reactive Ion Etcher SI 500. The parameters of the etching process were: ten standard cubic centimeters per minute (sccm) SF\({}_{6}\), 20 sccm C\({}_{4}\)F\({}_{8}\), 5 sccm O\({}_{2}\), 0.9 Pa chamber pressure, 400 W ICP power, and 12 W RF power. After the SiNW fabrication, a second EBL-based patterning was performed for Ni contact formation using a positive tone resist, ZEP520A (ZEON Corporation, Tokyo, Japan). The exposure parameters were: A total of 10 kV acceleration voltage, 10 \(\upmu\)m aperture size and area dose of 40 \(\upmu\)C/cm\({}^{2}\). The development was performed in n-amyl acetate solution (ZED-N50, ZEON Corp.). This was followed by baking at 200 \({}^{\circ}\)C for 5 min to smoothen the side walls of the patterned structures. Prior to Ni sputtering, the Si native oxide was etched away from NWs using 1% buffered hydrofluoric acid (BHF) solution and then the samples were transferred into the sputtering chamber. The sputtering was performed at 10 keV with a Gatan 681 High-Resolution Ion Beam Sputter Coater. The sample holder was rotated at a speed of 40 rpm for uniform deposition of Ni at a rate of 1.3 \(\pm\) 0.2 A/s. The thickness of Ni was varied between 35 and 50 nm according to the requirements of the experiments. After the sputtering step, lift-off was carried out in N-methyl-2-pyrrolidone (NMP) at 50 \({}^{\circ}\)C for 10 min. The samples were then rapid thermally annealed (RTA) at 450 \({}^{\circ}\)C in forming gas atmosphere (a mixture of 10% H\({}_{2}\) and 90% N\({}_{2}\)) for silicidation of the NWs. The annealing time was varied in order to control the axial diffusion length of Ni into the SiNW. The role of the Ni pads was two-fold: Firstly, they acted as a Ni reservoirs for silicidation of NWs, and secondly, they served the purpose of a contact electrode. To investigate silicidation of nanowires covered with an oxide shell, the samples were thermally oxidized. The oxidation process started with removal of the native oxide from the samples by dipping them in 1% BHF for 15 s. This was followed by an immediate transfer of samples in a pre-heated (875 \({}^{\circ}\)C) rapid thermal oxidation chamber. The samples were kept in the chamber for 10 min in the presence of an oxygen flow of 10 standard liters per minute (slm). Subsequently, the samples were annealed at 875 \({}^{\circ}\)C in a nitrogen environment for 5 min. This was followed by annealing in forming gas atmosphere. The oxidation process generates heavy stress in the nanowire due to the volume expansion. This impacts the oxygen diffusion in Si and the surface reaction rate at the Si-SiO\({}_{2}\) interface drops. Therefore, the oxidation process is self-limited [53; 54] (i.e., the stress generated by the oxidation process prevents further oxidation of the nanowires).