## 3 Results
(**a**) Stack structure used for extracting \(C_{ox}\). (**b**) Capacitance-voltage curve for \(C_{ox}\) extraction. (**c**) Stack structure for F–N tunneling analysis. (**d**) Log I-V curve (**e**) \(\ln(I/V^{2})-1/V\) curve. Figure 2: Basic operation through transfer curves and output curves. Threshold voltage calculation of (**a**) full erase state and (**b**) full program state. Output curve of (**c**) full erase state and (**d**) full program state. Gate leakage current measurement of (**e**) full erase state and (**f**) full program state. erase (ERS) operations. In a flash transistor, the charge stored in the floating gate modulates the channel conductivity by shifting the Vth. This charge is injected or removed through F-N tunneling during the PGM and ERS operations. The stack structure shown in Figure 3c served as the basis for the F-N tunneling evaluation, with Figure 3d,e presenting the corresponding electrical measurements. From the log I-V curve in Figure 3d, it can be observed that F-N tunneling occurs between 4.9 V and 8 V. Beyond this range, dielectric breakdown is evident. This implies that the PGM and ERS operations are feasible within this voltage window, while voltages outside this range are likely to result in device failure or non-operation. Figure 3e, along with the following F-N tunneling Equation (2), was used to closely examine whether the voltage range from 4.9 V to 8 V corresponds to the expected F-N tunneling behavior. \[ln\left(\frac{I}{V^{2}}\right)\propto-\frac{1}{V}\left(\frac{8\pi d\sqrt{2m^{*} \Phi^{3}}}{3 he}\right) \tag{2}\]  
_d_: tunnel oxide thickness [units: m];  
_m\({}^{*}\)_: effective mass of electron [units: kg];  
_\(\Phi\)_: barrier height [units: eV or J];  
_h_: [PERSON]'s constant [units: J\(\cdot\)s]. From the linear fitting, a negative slope of -80.27 was obtained within the specified voltage range, confirming that the data follows the proportional relationship characteristic of F-N tunneling. Therefore, it can be concluded that the dominant charge transport mechanism in the device is Fowler-Nordheim tunneling. Furthermore, the operating voltages listed in Table 1 (PGM: +6 V, ERS: -6 V) are within a stable range that does not induce dielectric breakdown, indicating reliable device operation. The synaptic weight of the device is examined by analyzing the changes in Vth and drain current (I\({}_{\text{ds}}\)) during ERS and PGM operations. During ERS, the increase in current indicates synaptic potentiation, while the decrease in current during PGM reflects synaptic depression [34]. These phenomena are attributed to Fowler-Nordheim (F-N) tunneling, suggesting stable device operation [35; 36]. Figure 4a,b demonstrate multi-level synaptic potentiation and depression over 40 cycles, with clear Vth changes. Figure 4c shows that the synaptic connection strength can be adjusted from \(-\)0.02 to 2.14 V, highlighting the potential of this device as an artificial synapse. In particular, a noticeable Vth shift is observed during the first PGM and ERS operations, which is attributed to the long voltage pulse duration (1-10 s) that induces significant initial charge injection and removal in the floating gate. To improve control over gradual synaptic weight changes, future experiments will adopt microsecond-scale pulse measurements using the B1500A system. The distribution of Vth was analyzed using Figure 4d, confirming that it follows a Gaussian distribution [37; 38; 39]. For the ERS state, we can see that the changes in Vth were smaller than for the PGM state, indicating a more centralized distribution. This suggests that the Vth in the ERS state exhibits better reproducibility compared to the PGM state. The Vth in the ERS state exhibited a Gaussian distribution with a mean (\(\upmu\)) of 0.063 V and a standard deviation (\(\upsigma\)) of 0.100 V. In the PGM state, the Vth showed a mean of 1.810 V with a standard deviation of 0.190 V. The broader Vth variation in the PGM state is attributed to charge trapping during repeated operations.