## 4 Simulations and Discussions  
Based on the circuits shown in Figures 3 and 4, the proposed VC-DFF and VC-SRFF are designed and evaluated using a 40 nm CMOS design kit. The parameters of the VC-SOT MTJ and variables are summarized in Table 1.  
Figure 5 presents the transient simulation waveforms of the VC-DFF. As shown in Figure 5a,b, the VC-DFF begins with a normal mode (writing process and reading process), which is consistent with the description in Section 3.1.1. During the writing process, since Cr is always set to \"0\" and the PCSA circuit remains in the pre-charging stage, resulting in OUT+ = OUT- = \"1\". The output value Q changes accordingly with D. When performing a write operation, Vbia and Vsat need to apply a positive pulse voltage (pulse width of 1 ns and 1.2 ns, respectively). As shown in Figure 5a, when D = \"0\" and Vsat and Vbia apply a positive pulse voltage, the magnetization direction of the MTJ device in Mdata  
Figure 4: Circuit structure of the proposed VC-SOT MTJ-based VC-SRFF: (**a**) configuration during CLK = “1”; (**b**) configuration during CLK = “0”. transitions from the AP to P state, completing nonvolatile storage of data \"0\". When D changes from \"0\" to \"1\", the magnetization direction of the MTJ device in M\({}_{\text{data}}\) changes from P to AP state, completing the nonvolatile storage of data \"1\". The main difference between Figure 5a and b lies in the difference in the initial data stored in M\({}_{\text{data}}\). From Figure 5b, it can be seen that when the written data are consistent with the original data, the magnetization direction of MTJ does not change. The simulation results show that the write delay of the MTJ device is 4 ns. The states of M\({}_{\text{data}}\) and M\({}_{\text{ref}}\) are always complementary. During the read process, CLK is set to \"0\" and Cr is set to \"1\". The output Q during the reading process depends on the latest written data (\"1\") from the previous writing process. During the reading process, when D changes, the output result remains unchanged. The VC-DFF does not require any additional operations when the system cuts off the module power to save energy or encounters an unexpected power o \begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameter** & **Description** & **Default Value** \\ \hline K\({}_{\text{i}}\) & Interfacial anisotropy density & 1.005 \(\times\) 10\({}^{-6}\) KJ/m\({}^{2}\) \\ M\({}_{\text{S}}\) & Saturation magnetization & 1.2 \(\times\) 10\({}^{6}\) A/m \\ S & Voltage control coefficient & 75 fJ/V\(\cdot\)m \\ D & Diameter of the free layer & 80 nm \\ t\({}_{\text{OX}}\) & Oxide layer height & 1.5–2.5 nm \\ t\({}_{\text{FL}}\) & Free layer thickness & 1.1 nm \\ l\({}_{\text{J}}\)w\(\cdot\)d & Heavy metal dimension & 100 nm, 100 nm, 3 nm \\ \(\alpha\) & Magnetic damping constant & 0.02 \\ \(\theta\) & Spin Hall angle & 0.3 \\ rho & Heavy metal resistivity & 200 \(\mu\Omega\)\(\cdot\) cm \\ Hex & Exchange bias field & \(-\)7956 A/m \\ T & Temperature & 300 K \\ V\({}_{\text{dd}}\) & Voltage & 1.2 V \\ T & Gyromagnetic ratio & 2.21276 \(\times\) 10\({}^{5}\) m/(A-s) \\ \(\mu_{0}\) & Permeability in free space & 1.2566 \(\times\) 10\({}^{6}\) H/m \\ k\({}_{\text{B}}\) & Boltzmann constant & 1.38 \(\times\) 10\({}^{-23}\) J/K \\ e & Elementary charge & 1.6 \(\times\) 10\({}^{-19}\) C \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Parameters and variables of the VC-SOT-MTJ model. Figure 5: Transient simulation waveforms of our proposed VC-DFF: **(a)** simulation results when the initial state of M\({}_{\text{data}}\) is AP I; **(b)** simulation results when the initial state of M\({}_{\text{data}}\) is P.  
The recovery mode essentially performs a reading operation of the resistance state stored in \(\mathrm{M_{data}}\) by the PCSA circuit. As shown in Figure 5a, when the state of \(\mathrm{M_{data}}\) is AP, the output value Q during the recovery process is \"1\".