# A Survey on Open Radio Access Networks: Challenges, Research Directions, and Open Source Approaches
## 5 O-RAN Alliance Architecture
### O-Dui  
RLC, MAC, and high physical layers are hosted in the O-DU logical node [58; 62]. Data segmentation/integration, scheduling, multiplexing/demultiplexing, and other baseband processing are in O-DU. In general, O-DU is divided horizontally into two parts: O-DU high and O-DU low. O-DU high handles the layer 2 (L2) functional blocks, which are the RLC and MAC layer, while O-DU low covers the layer 1 (L1) functional block or the high physical. The functional application platform interface (FAPI) standard interface specified by SCF is used so that these two parts can communicate with each other. Other interfaces  
Figure 13: O-CU architecture. related to the O-DU are the E2 interface, F1 interface, O1 interface, and open FHI (O-FHI). O-DU's architecture and interfaces to other components can be seen in Figure 14.  
In the H release of OSC, the 5G O-DU High component is divided into eight different threads as shown in Figure 15, each identified by a different color. The first thread is responsible for managing the overall O-DU High functionality, including the O-DU utility and common functions. The second thread, known as DU_APP, handles the configuration handler, DU manager, UE manager, and ASN.1 codecs. The third thread is dedicated to managing the Evolved-GPRS Tunneling Protocol (EGTP). The fourth thread covers the Stream Control Transmission Protocol (SCTP). The fifth thread is focused on the O1 module. The sixth thread is responsible for the 5G NR RLC UL. Notably, there is a separate block for MAC_SCH, indicating its detachment from the 5G NR SCH (Scheduling). The seventh thread manages the 5G NR RLC DL and most 5G NR MAC functions, including the 5G NR scheduler (SCH) functions. However, the lower MAC handler operates within a different thread, specifically the eighth thread. Figure 14: O-DU architecture. Figure 15: O-DU high architecture in H release. Since O-DU Low handles the high physical, it is constructed mostly by L1 processing blocks as shown in Figure 16. For the shared and control channel processing, we can see that the downlink (DL) and uplink (UL) are each handled by a separate block, which totals to 4: Physical DL Control Channel (PDCCH), Physical DL Shared Channel (PDSCH), Physical UL Control Channel (PUCCH), and Physical UL Shared Channel (PUSCH). Both Physical Broadcast Channel (PBCH) and Physical Random Access Channel (PRACH) have independent blocks. The task scheduling is divided into two blocks: one for UL and one for DL. Task scheduling will manage all queued tasks and begin the processing operations correspondingly. Then, we have the L2 FAPI processing block to handle the FAPI protocol L2 interface request/response. On the O-RU side, we have the FHI procedure block. We also have the forward error correction (FEC) acceleration processing to handle FEC operations such as passing FEC requests to hardware and invoking callback function on acceleration processing completion. Last, we have the timing events processing block to handle timing-related operations. Ref. [62] shows details of each processing blocks. The O-RAN Alliance architecture adopts the Functional Split 7.2x for the lower layer split between the O-DU and the O-RU [58; 63]. This split is carried out between the resource element mapping and FFT/iFFT stacks [64]. Figure 17 shows the location of split 7.2x and introduces the concept of precoding, using PDSCH as an illustrative example. Precoding is a physical layer technology that supports multi-layer transmission in multi-antenna wireless communications. In O-RAN Alliance split 7.2 specification WG4, it can be implemented in DU or RU. There are two variations of this Split 7.2x, which differ depending on whether \"7.2a\" precoding is performed in O-DU or \"7.2b\" precoding is performed in O-RU. This split is chosen by the O-RAN Alliance while considering the trade-offs in RU complexity and interface throughput. The details of the trade-offs are studied in [11; 28; 64; 65]. Figure 16: O-DU low processing blocks. Figure 17: PDSCH in lower layer split 7.2x.