## 1 Introduction  
The discrete wavelet transform (DWT), as a multi-resolution analysis tool, is commonly used for image analysis, image compression and digital signal processing. To reach a high compression ratio, the input image is usually required to be decomposed by multi-level DWT. For hardware implementation of multi-level 2-D DWT, how to reduce the hardware consumption and improve the system performance becomes the hot research topic of structural optimization. The existing DWT architectures can be classified into the lifting scheme and convolution-based scheme. Compared with the convolution-based scheme, the lifting scheme has been popularly researched because of lower computation complexity and less memory requirement. In order to optimize the lifting scheme, [PERSON] [1] proposed a two-input/two-output pipelined architecture by rearranging with the expressions to reduce the critical path delay (CPD) to \(Tm\), where \(Tm\) is the delay of a multiplier, and limit the size of the temporal memory to \(4N\). A dual-scan parallel flipping architecture of high hardware utilization efficiency was presented in [2], which can be folded to minimize the CPDto \(Tm\). [3] introduced the overlapping scanning method and decreased the temporal buffer to \(3N\) by overlapping one pixel. Also, the overlapping scanning method is seen in [4; 5; 6; 7]. By overlapping one pixel, three pixels and five pixels, it can economize the temporal memory of \(N\), \(2N\) and \(3N\), respectively. Nevertheless, the consumption of external memory will largely increase. For multi-level DWT, which is usually used in the main application environment. Large demand of the frame memory that stores the low-low (LL) sub-band result for the folded architecture or complex data adjustment for the unfolded architecture is generally needed. [PERSON] [8] proposed a block based high-throughput structure of 1-level 2-D DWT. Folded architecture based on this method needs 5N2/16 frame buffer words. Thus, to reduce the consumption of hardware resources, the unfolded multi-level 2-D DWT structure is more widely researched. [PERSON] and [PERSON] [9] presented a line-based parallel lifting structure without line and frame buffers. However, its CPD is \(Tm+2 Ta\), where \(Ta\) is the delay of an adder. Later, [10] proposed a parallel convolution architecture, using more computing resources to reduce the memory demand for multi-level 2-D DWT. Consequently, high-throughput and less memory requirement is achieved at the expense of more area. Then, a block-based architecture was proposed to [11], which achieves lower demand for external memory access and higher energy efficiency. Furthermore, [12] presented a scalable parallel architecture of multi-level 2-D DWT based on lifting scheme. Temporal memory of this architecture is reduced to zero in the first level, by overlapping seven pixels. A creative processing method of different levels is used to decrease the temporal RAM to 3\(N\). However, the control logic of the architecture is complicated. Besides, [13] discussed different data scanning methods and optimized the scanning sequence to decrease the area of the frame memory for the unfolded structure. Recently, [PERSON] [14] introduced the CSD multiplier to decline the critical path to Ta. Nonetheless, multi-clock control system is necessary. [15] used an innovative block based \(Z\) types memory scanning method of their own way for reducing the total processing time, but it's not a multi-level architecture. The authors of [16] proposed bit-serial Distributed Arithmetic (DA) based VLSI architectures of 1-D/2-D DWT, which makes the designs Multiplierless and consumes less area, but the article does not mention the architecture's throughput rate. In [17], the authors proposed a look-up-table (LUT) based structure of high-throughput implementation of multilevel lifting DWT. The proposed structure can process one block of samples to achieve high-throughput rate.