# Supply-Scalable High-Speed I/O Interfaces
## 4 Survey on State-Of-The-Art Supply-Scalable I/O
The pioneer works of supply-scalable parallel [24] and serial I/Os from Stanford University [22], utilize DC-DC converters to scale the on-chip supply voltages. They take the control voltages of analog delay-locked loop [24] and analog ring-PLL [22], which can be a benchmark of operating frequency because they intrinsically track the operating frequency, as already discussed in the Section 2, as a reference voltage of the DC-DC converters. As a result, the supply voltages can scale automatically with no off-chip control. In [25], Intel presents the voltage calibration scheme using a calibration VCO that replicates the critical path in the transmitter, and it achieves an energy efficiency of 2.7-5.0 pJ/bit in 65-nm CMOS technology, which is approximately a 10\(\times\) improvement over [24] and [22]--however, without on-chip supply scaling. Intel also presents [16], which achieves 32 Gb/s with a complete set of equalizers, on-chip PLL, and CDR, with an energy efficiency of 3.25-6.41 pJ/bit. [31] incorporates the combination of a DC-DC converter and LDO regulators to achieve high conversion efficiency (DC-DC) as well as to protect supply-noise-sensitive circuits from the noisy output of a DC-DC converter, while achieving 3.6-7.24 pJ/bit efficiency with a 3-10 Gb/s range with supply scaling. In addition, [31] combines the scalable supply technique with burst-mode operation, lowering the minimum effective data rate of 16 Mb/s with 34 pJ/bit. \begin{table}
\begin{tabular}{c} **F6M (pl/h)** \\ **@Max Rate** \\ \end{tabular} \\ \hline
[24] & 350 & 0.2 & 0.8 & Open drain & None & Half rate & External & DC-DC & 1.3 & 3.2 & 0.1-0.15 & N/A & N/A & 26.875 \\ \hline
[22] & 250 & 0.65 & 5 & Current & None & 1/5 rate & 1 & DC-DC & 0.9 & 2.5 & 0.1-0.3 & N/A & 8.5 & 43.3 \\ \hline
[25] & 65 & 5 & 15 & Current & 3-4p FFE & Half rate & External & External & External & 0.68 & 1.05 & 0.1-0.72 & 0.033 & 1.5 & 2.3 \\ \hline
[26] & 45 & 5 & 25 & Voltage & None & Half rate & External & External & 0.75 & 1.1 & 0.082-0.36 & 0.077 & N/A & N/A \\ \hline
[15] & 32 & 2 & 16 & Voltage/ current & 3-4p FFE & Quarter rate & External & External & 0.6 & 1.08 & 0.36-0.5 & 0.014 & 0.47 & 1.56 \\ \hline
[27] & 65 & 4.8 & 8 & Voltage & None & Quarter rate & External & External & 0.6 & 0.8 & 0.1-0.2 & 0.027 & 0.34 & 0.44 \\ \hline
[16] & 22 & 8 & 32 & Voltage & 3-4p FFE & Quarter rate & 1 & External & 0.72 & 1.07 & 0.1-0.6 & N/A & 2.19 & 1.97 \\ \hline
[31] & 65 & 3 & 10 & Current & 3-4p FFE & Half rate & 1 & DC-DC & 0.7 & 1.4 & N/A & N/A & 2.7 & 4.8 \\ \hline
[12] & 65 & 5 & 32 & Voltage & 2-4 pFE & Quarter rate & 1 &
\begin{tabular}{c} DCC-DC \\ + LDO \\ \end{tabular} & 0.7 & 1.4 & N/A & N/A & 2.7 & 4.8 \\ \hline
[34] & 65 & 3 & 16 & Voltage & PWM &
\begin{tabular}{c} Quarter rate \\ rate \\ \end{tabular} & External & External & 0.5 & 0.9 & N/A & N/A & 1.04 & 2.42 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Survey of supply-scalable transmitters. FFE: feed-forward equalizer, FoM: figure-of-merit, LDO: low-dropout, PLL: phase-locked loop. \begin{table}
\begin{tabular}{c c c c c c c c c c c c c c} \hline \hline  & \begin{tabular}{c} **Process** \\ **(nm)** \\ \end{tabular}  & \begin{tabular}{c} **Min.** \\ **Rate** \\ **(Cs/s)** \\ \end{tabular}  & \begin{tabular}{c} **Max.** \\ **Rate** \\ **(Cs/s)** \\ \end{tabular}  & \begin{tabular}{c} **Equalizer** \\ **Coloking** \\ \end{tabular}  & \begin{tabular}{c} **Clock/Deskow** \\ **(UD)** \\ \end{tabular}  & \begin{tabular}{c} **CBR/Deskow** \\ **(UD)** \\ \end{tabular}  & \begin{tabular}{c} **Seply** \\ **Selling** \\ \end{tabular}  & \begin{tabular}{c} **Min.** \\ **Supply** \\ **(V)** \\ \end{tabular}  & \ \begin{tabular}{c} **Max.** \\ **(V)** \\ \end{tabular}  &
\begin{tabular}{c} **Area