## 4 Hardware Design  
We have designed a hardware architecture for the above-described MIMO detector utilising four transmit and four receive antennas, which can be seen in Figure 6. The architecture of  
Figure 4: BER performance of detectors over 4 \(\times\) 4 MIMO system and using Binary Phase Shift Keying (BPSK) modulation scheme. Figure 5: SNR performance gap in dB from the ML detector to attain a BER of \(10^{-5}\) of the K-Best and ELR K-Best detectors for a variable number of transmit and receive antennas. Figure 6 is based on the ELR-aided K-Best algorithm for a MIMO system utilising QAM and \(K=2\). We first developed a software model of the decoder using MATLAB, which was used for functional verification of the implementation and also used to produce the BER results in the previous sections. Then, we implemented the proposed architecture in \"System Verilog\". The operation principles of the design are as follows. First, the decoder takes \(\mathbf{y}\) and \(\mathbf{H}\) as inputs, where in the considered \(4\times 4\) MIMO system, \(\mathbf{y}\) is a \(4\times 1\) vector of complex numbers and \(\mathbf{H}\) is a \(4\times 4\) matrix of complex numbers. Therefore, in order to simplify the mathematical matrix operations in the hardware implementation, \(\mathbf{y}\) and \(\mathbf{H}\) are converted to a real vector and real matrix, respectively, using the YC2R and HC2R modules in Figure 6. After the complex-to-real matrix conversion shown in Figure 6 the matrix \(\mathbf{C}=(\mathbf{H}^{\mathbf{H}}\mathbf{H})^{-1}\) is produced, which is then followed by the ELR operation shown in Table 1. We have implemented a pipeline of three functional blocks shown in Figure 6, namely the ELR block which produces the matrix T, followed by a matrix inversion and then matrix transpose (TSPS) stage. This pipelining approach has helped to improve the throughput of this block and made it easier to test and debug its functionality. Afterwards, the received signal \(\mathbf{Y}\) and the ELR-aided channel matrix \(\mathbf{\widetilde{H}}\) are scaled and shifted as described in Section 3 and as shown in Figure 6. Then, QR decomposition is applied as described in Section 3, where the QR decomposition transforms a matrix \(\mathbf{A}\) into the product of an orthogonal matrix \(\mathbf{Q}\) and an upper right triangular matrix \(\mathbf{R}\). The QR decomposition is typically achieved using the Given Rotations algorithm [30]. In the proposed decoder, the QR decomposition is implemented using a systolic array of 36 elements of CORDIC operations. CORDIC stands for Coordinate Rotation Digital Computer and is an algorithm used to implement trigonometric functions in hardware. This is done by either CORDIC vectors or rotations. The main idea is to keep rotating a given vector by a reducing angle over and over again up to a certain accuracy [31]. For example, in the first iteration, the vector can be rotated by 45 degrees clockwise. If this overshoots, then the next rotation would be 22.5 degrees counterclockwise, otherwise if no overshooting occurs then 22.5 degrees are applied clockwise. This is repeated for a number of times specified by the designer. For the purposes of this project 15 stages were used to achieve higher accuracy. After the QR decomposition, the decoder performs the K-Best detection based on a breadth-first tree search algorithm, which expands a fixed number of K nodes at each level. This can be implemented using a pipelined architectures. More details on this can be found in [17]. To reduce the complexity  
Figure 6: Hardware Architecture of Element-based Lattice Reduction aided K-Best Detector. of the K-Best block, \(K\) was set to 2, which mean at each level of the tree search 2 out of 8 nodes are explored and this is shown to produce satisfactory results as shown in Section 3. Higher \(K\) values may improve the accuracy of the K-Best algorithm but at the expenses of more computational power and longer execution time.