# Low Power QC-LDPC Decoder Based on Token Ring Architecture
Also, while reviewing methods to reduce energy consumption, the method of local voltage reduction was considered. Reducing the supply voltage allows to significantly reduce energy consumption by adjusting the supply voltage of individual system elements at the expense of deteriorating dynamic parameters. Power gating enables great energy consumption reduction according to (Kang et al., 2004). Clock gating can be used in FPGAs, unlike power gating, which is not applicable there. Clock gating allows for the greatest reduction in dynamic energy consumption. However, there are other methods of reducing energy consumption that are worth mentioning. These methods were not used in the presented article due to the insufficient energy-saving in relation to additional elements increasing the hardware demand of the decoder. The first interesting method is a preliminary calculation of the state of outputs (precomputation logic), which consists of adding a circuit, the purpose of which is to determine the state of the outputs one clock signal period earlier (Kang et al., 2004; Wang et al., 2005; Wang et al., 2006). The second interesting method is determining the kernel (Kang et al., 2004; Wang et al., 2005; Wang et al., 2005), consisting of determining the dominant states of the sequential system from a subset of all states, and then implementing a separate, smaller element performing operations only for dominant states systems. The third interesting method is the implementation of the system in the Globally Asynchronous Locally Synchronous (GALS) architecture [32; 33; 34], involving decomposition of a locally synchronous system through which data are exchanged via an asynchronous bus, and the clock frequency of each module is individually adapted to the needs of this module. The aim of the paper is to implement an energy-saving LDPC decoder characterized by non-deteriorated dynamic parameters compared to a decoder without mechanisms limiting energy consumption. For this reason, and taking into account the limitations resulting from the use of FPGA, the article proposes an LDPC decoder architecture based on Token Ring oriented clock gating. The second chapter presents a theoretical introduction describing the most important issues concerning the energy-saving QC-LDPC decoder. The third chapter presents the implementation of the QC-LDPC decoder based on Token Ring architecture with clock gating, which was then tested and the results are presented in the fourth chapter. The article ends with chapter five, which summarizes the obtained results and then indicates further work. Therefore, the following list of contributions within the framework of the article can be formulated:  
1. General idea of technology mapping of the proposed QC-LDPC decoder in LUT-based FPGA oriented to clock gating (Section 2). 2. Development, implementation and testing of a new QC-LDPC decoder architecture based on Token Ring (Sections 2 and 3). 3. Proposal and design of original architecture low power QC-LDPC decoder oriented to a reduction in dynamic power into LUT-based FPGA (Section 3). 4. Performing experiments and presenting results confirming the effectiveness of the proposed solutions (Section 4).