# Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications
## 4 All-Digital Frequency Synthesiser for Multiband Transceivers  
The structure of all-digital synthesiser for the multiband wireless transceiver, which meets the requirements defined in the previous chapter, is suitable for IoV and IoT applications shown in Figure 7. This structure is based on structure which is presented in reference [25], but is modified for a wide tuning range of output signal and ensures high resolution of TDC. Wide tuning range is achieved by using multicore DCO. In this structure it is shown as multiple parallel-connected DCOs, because in the general case, there can be \(n\) DCO cores used in synthesisers, but simultaneously only one core is operating. Each core has its own normalisation coefficient \(K_{\text{DCO}}\), therefore, general DCO's normalisation coefficient is a set of coefficients of each core \(K_{\text{DCO}}\) = \(|K_{\text{DCO1}}\), \(K_{\text{DCO2}}\),..., \(K_{\text{DCOn}}\)). Each core is normalised individually, therefore there are \(n\) normalisation blocks. The purpose of normalisation is to eliminate the transfer coefficient of the DCO (\(K_{\text{DCO}}\)) and make a tuning of DCO linear--if transfer coefficient of the DCO is estimated correctly (i.e., normalisation transfer coefficient \(K_{\text{NORM}}\) is equal to \(K_{\text{DCO}}\) and ratio \(K_{\text{DCO}}/K_{\text{NORM}}\) = 1), due to normalisation, change of one bit of integer oscillator tuning word (LSB) changes the output frequency of DCO by \(f_{\text{REF}}\) hertz. Figure 7: Phase domain model of all digital frequency synthesiser for multiband transceiver. Physical implementation of multicore DCO in 0.18 \(\upmu\)m CMOS technology is presented in our previous work [26] and shown in Figure 8. It made of two LC tank DCO cores, decoupling stage, differential to single ended converter, tri-state buffers and frequency divider. It is a partial case of a multicore oscillator, where two DCO cores are used, but this structure is scalable to use different a number of cores to satisfy operating frequency and tuning range requirements. However, the penalty of adding more cores is a rapidly increasing area of silicon. Both cores of LC DCO have the same configuration. Main components of the DCO are a high-quality factor inductor, negative impedance cross-coupled transistor pair and two switched-capacitor arrays. Frequency of DCO is tuned by using 6-bit coarse tuning and 3-bit fine tuning binary words. Together with DCO frequency divider it is used to increase available frequency values. A divider is made of eight divide-by-2 cells connected in a daisy chain, thus division values range from 2 to 256. In this partial case 4.3-5.4 GHz frequency tuning range of DCO is achieved. When the highest operating frequency is set, phase noise at output of DCO is \(-116.4\) dBc/Hz at 1 MHz offset from 5.44 GHz carrier and \(-134.0\) dBc/Hz at 10 MHz offset from 5.44 GHz carrier. When working at the lowest frequency, phase noise at output of DCO is \(-117.6\) dBc/Hz at 1 MHz offset from 4.3 GHz carrier and \(-138.0\) dBc/Hz at 10 MHz offset from 5.44 GHz carrier. Oscillator's component of this DCO's phase noise can be approximated by following equation:  
\[\mathcal{L}_{\text{Osc,DCO}}(f)=\frac{10^{5.07}}{f^{3}}+\frac{10^{-0.29}}{f^{2 }}+\frac{10^{-6.7}}{f}+10^{-16}. \tag{11}\]  
Without tuning nonlinearity, mentioned above and alleviated by normalisation of DCO, there are capacitance mismatches in tuning banks, common to all DCOs. Ideally, all unit-weighted capacitors have same capacitance values. But in reality, these values will vary. If the synthesiser is in frequency tracking mode, these capacitors will be constantly switching on/off and due to variation of capacitance, output frequency will also vary--it will be slightly different from expected frequency and will degrade phase noise performance. One of the basic techniques to alleviate such mismatches is dynamic element matching (DEM) [14; 15]. The main idea of DEM is to dynamically rearrange (e.g.