## 3 Results and Discussion
The leading factor contributing to the low mobility and large electrical non-uniformity reported here is attributed to graphene's underlying surface roughness of the Al gate electrode that can also be observed from AFM, Raman spectroscopy, and SEM imaging. It has been previously reported that the underlying surface roughness has a great effect on the mobility of graphene [66]. The random and non-uniform nature of the roughness results in carriers that are more prone to scattering effects traveling through defect sites in the graphene channel. In order to show the impact of traps on the variation and non-uniformity of the fabricated buried top-gated graphene FETs, forward and backward V\({}_{\text{GS}}\) sweeps with a staircase scheme and different bias stress conditions prior to the acquisition of the measurement data were performed. The Supplementary Materials show the results of this analysis for low, high, and medium devices, while the data presented here correspond to an additional device with high current level. The stress was set by applying V\({}_{\text{GS}}\) pulses of 0 V and \(-10\) V before measuring the drain current within a pulse of 500 \(\upmu\)s duration. The total device resistance curves obtained under such conditions are shown in Figure 7. Data obtained with the 0 V pulse reveal a slight improvement in the hysteresis window with respect to the staircase, i.e., no pulse, scheme, whereas the case with higher stress (\(-10\) V pulse) reduces the impact of traps. A hysteresis window is the result of trap charges on the gate dielectric interface. It is inherent to graphene field-effect transistors due to traps within channel, substrate, and high-k dielectric materials, as well as the interfaces between them. Technological efforts, such as encapsulation within two-dimensional dielectrics [67], additional costly processes [68], and high-quality interface between the graphene and the dielectric [33], have shown success in reducing trap charges and, thus, mitigating hysteresis. A pre-charging condition of the traps benefits the reproducibility conditions of devices with high-k dielectrics such as GFETs [69]. A well-known unipolar resistance GFET model [59] has been used to describe the experimental data in Figure 7 toward obtaining key device parameters such as the contact resistance and low-field constant mobility. The model accurately describes the data at each unipolar region, as observed in Figure 7; hence, parameters for p- and n-type regions were obtained for each measurement condition, as reported in Figure 7.  
As shown in the data of Table 1 and Tables S1-S3 in the Supplementary Materials, the extracted contact resistance values have a smaller variation than the extracted mobility values for each particular device when comparing each of the test conditions. This indicates that the traps along the channel have a minimum impact for device variation and non-uniformity. On the other hand, there is large variation in the contact resistance values and the mobility observed between the devices. For example, high- and low-current devices have an extracted p-type contact resistance of 1.4 k\(\Omega\) and 4.2 k\(\Omega\), respectively, as well as a  
Figure 6: Atomic force microscopy (AFM) images with color scale bar indicating measured data of (**a**) graphene on Al\({}_{2}\)O\({}_{3}\)/Al gate electrode with arithmetic mean height (R\({}_{\text{a}}\)) of 16.19 nm, (**b**) graphene on Al\({}_{2}\)O\({}_{3}\)/SiO\({}_{2}\) source and gate gap with R\({}_{\text{a}}\) of 4.06 nm, and (**c**) bare Al\({}_{2}\)O\({}_{3}\)/SiO\({}_{2}\) with R\({}_{\text{a}}\) of 1.06 with no graphene present in region. hole mobility of 185 cm\({}^{2}\)/V\(\cdot\)s and 315 cm\({}^{2}\)/V\(\cdot\)s and an electron mobility of 240 cm\({}^{2}\)/V\(\cdot\)s and 445 cm\({}^{2}\)/V\(\cdot\)s, respectively. As shown in other reports [70], contact resistance can be affected by the defect density of the graphene layer, as it is more favorable to contact the graphene edge than the top surface.