## 1 Introduction
### Related Work  
The efficiency of point multiplication operations on BECs utilizing FPGAs has improved significantly in the last several years. In this regard, one of the initial works is presented in [14], where a reconfigurable cryptoprocessor is designed. The system operates at a frequency of 48 MHz. However, it heavily utilizes hardware resources, consuming 21,816 slices. This resource utilization increases to 22,373 slices when performing BEC operations with halving. It ultimately limits its suitability for resource-constrained embedded devices. Consequently, a compromise between computational efficiency (latency) and area utilization is required.  
A pipelined digital-serial multiplier is presented in [15] for a better compromise between computational efficiency and area utilization, and the corresponding performance figures are presented for the Virtex-5 platform. As a result, the latency of the point multiplication operation is reduced to 11.03 microseconds with the utilization of 8875 slices. Another architecture, targeting the optimization of latency and area, is presented in [16]. The authors introduced two architectures that leverage a comb Parallel Multiplier (PM) technique. The first architecture targets low complexity and achieves enhancements of 62%, 46%, and 152% for \(GF(2^{233})\), \(GF(2^{163})\), and \(GF(2^{283})\), respectively. The second architecture targets low latency and achieves improvements of 55%, 44%, and 76% for \(GF(2^{233})\), \(GF(2^{163})\), and \(GF(2^{283})\), respectively.  
The work in [17] is based on a modular radix-2 interleaved multiplier. The objective is to reduce the computing time, the required number of clock cycles, and area requirements. To achieve this, the architecture employs the Montgomery ladder algorithm. However, the authors did not specify the curve parameters where their hardware design presents the best and worst performance. It implies that performance results are not presented for different curve parameters. Similarly, the work in [18] focuses on the optimization of throughput and area at the same time. It introduces two architectures. The first is tailored for general BECs, while the second is specifically designed for special BECs. The optimizations are based on advanced finite field multiplication techniques. Therefore, a trade-off between area and computational efficiency is obtained. The architecture employs three parallel multipliers for better computational efficiency but at the cost of increased hardware resources. Specifically, for curve parameters \(d_{1}\) and \(d_{2}\) equal to 59, the area is reduced to 4454 slices. To optimize the area even further, the architecture is modified, employing only two multipliers. Consequently, the area is reduced to 3521 slices while maintaining acceptable latency levels.  
In the context of area optimization, authors in [19] optimize the architecture by introducing a digital-serial multiplier. This leads to the utilization of 2138 slices for the Virtex-6 platform and 2153 slices for the Virtex-5 platform. While this architecture achieves area optimization, it compromises the speed of the system. The work in [20] also focuses on resource optimization. The architecture incorporates a digital parallel least significant multiplier. Along with the effective multiplication, point multiplication instructions are carefully organized. The synthesis results are presented across multiple platforms. The limitation is the lack of a thorough analysis of the results regarding computational speed, leaving the potential for additional investigation in this area.  
Finally, the authors in [21] propose a hybrid algorithm for the optimization of BEC computations. The hybrid technique combines Montgomery and double-and-add techniques. Moreover, clock cycles are optimized by utilizing a modular Montgomery radix multiplier. The limitation is the absence of adaptability. It implies that the architecture is not explored for various security requirements and multiple complex scenarios.