# Application of Surge Arrester in Limiting Voltage Stress at Direct Current Breaker
## 2 The Proposed Mechanism  
The two-switch bipolar hybrid DC breaker introduced in [11], depicted in Figure 1a (excluding the surge arrester), uses capacitors to bypass the fault current and facilitate the opening of the mechanical switches minimizing the arc. The capacitors must have very small resistance and inductance for the scheme to operate. They undergo an overvoltage along with the connecting parallel mechanical switches. The use of the redirecting diodes [11] prevents the overvoltage while imposing a negative voltage on the path inductance and sends part of the fault current back to the supply. Consequently, an improved current zero-crossing time is achieved, and the arc energy is reduced when the proposed breaker is used close to the DC source. With the presence of parasitic path inductance upstream of the breaker, this mechanism is disturbed, causing an overvoltage at the terminals of the DC breaker during fault current disruption. This paper presents a modification to the two-switch hybrid bipolar DC breaker [11], as shown in Figure 1. A surge arrester is added to the input terminals of the DC breaker, providing a return path for the fault current that flows in the upstream path inductance. This still causes a voltage rise at the breaker's input terminals, but it is much smaller than the case without the surge arrester. The surge arrester, however, is directly exposed to the source voltage, leading to relatively high values of leakage current, even in the breaker's open state. To resolve this problem, a normally open mechanical switch is placed in series with the surge arrester to prevent the leakage current. The switch closes upon the opening of the circuit breaker to increase the reliability and lifetime of the surge arrester. The operation of the modified breaker is explained next. As an overcurrent fault is detected, the mechanical switches start to separate contacts, followed by the generation of an arc between the contacts. Subsequently, the fault current is rerouted to the parallel capacitors, causing the arc to disappear and the capacitor voltages to rise. The capacitors' voltage rise imposes a high voltage on the surge-arrester terminals, dropping its path resistance and allowing the reverse downstream current to flow. Concurrently, the upstream inductance is subject to a negative voltage and a decaying current due to the raised surge-arrester terminal voltage. Also, the capacitors' voltage rise turns on the diodes, causing the capacitor voltages to be clamped at the surge-arrester voltage. At this stage, the downstream fault current partially returns to the surge arrester in a decaying fashion that generates a zero-crossing and fault-current interruption. The modified DC breaker operation comprises seven stages, which are subsequently explained and are depicted in Figures 2 and 3. Figure 2: A sample current and voltage waveform during breaking. Stage 1: This is a pre-operation of the proposed mechanism, where the fault current is established but the breaker has not operated. Both the mechanical switches (SW1 and SW2) are conducting, and the surge arrester is in its blocking state (see Figure 1b). Stage 2: In this stage, a trip signal is issued to both the switches; however, due to their internal mechanical properties, one mechanical switch operates first (ex., SW2). The fault current redirects to the parallel capacitor path flowing through SW1 and C2, raising the C2 voltage in an RLC circuit, and thus rapidly decays. The surge arrester is in block mode initially due to its low terminal voltage, and \(I_{upstream}=I_{downstream}\), with \(I_{downstream}\) being the downstream inductor current. The fault current raises the C2 voltage, causing the surge-arrester terminal voltage to rise until it reaches the conduction mode at the end of this stage (See Figure 3a). Stage 3: Upon the surge arrester conducting, a further increase in the C2 voltage will turn on diode D1, clamping the SW2 voltage (and \(V_{\text{C2}}\)) at the surge-arrester voltage.