# A Low-Power Read-Decoupled Radiation-Hardened 16T SRAM for Space Applications
## 3 Simulation Results and Analysis
### Read and Write Access Time Comparison  
Read access time (RAT) is defined as the time interval between the point at which the word line (WL) reaches 50% of the supply voltage (VDD) and the moment a voltage difference of 50 mV develops between the bit lines BL and BLB [22]. During the read operation, the voltage at the node storing logic '0' may rise due to a voltage division effect between the access transistor and the pull-down path. This voltage rise reduces the drive strength of the access transistor due to the body effect, thereby increasing the RAT. Consequently, a higher cell ratio (CR) generally results in a shorter read access time. Additionally, excessive use of access transistors increases bit line capacitance compared to designs using a single access transistor, thereby lengthening the RAT. On the other hand, having additional read paths can help reduce the RAT. As shown in Figure 5, the proposed LDRH16T cell exhibits the longest read access time among the compared designs. Despite having a cell ratio of 2.5, only the access transistors connected to the internal nodes are activated during the read operation, leading to higher bit line capacitance than in cells with a single access transistor. Furthermore, LDRH16T includes a PMOS device in the read discharge path and only one effective discharge path, which further increases the RAT [9]. Lastly, excessive transistor stacking in the pull-down path causes the voltage at the '0'-storing internal node to rise, resulting in the longest RAT among all evaluated cells.  
Write access time (WAT) is evaluated as the time interval between the point at which the WL reaches 50% of VDD and the moment the voltages of storage nodes Q and QB intersect [9]. It is generally observed that applying simultaneous influence to both the storage and internal nodes during a write operation leads to a reduction in write access time (WAT). According to Figure 6, LDRH16T achieves the second fastest WAT among the compared designs. Since the proposed cell includes two additional access transistors connected to the internal nodes, both the internal and storage nodes are flipped simultaneously during a write operation, reducing the overall WAT. As a result, the LDRH16T outperforms RHBD10T, SIS10T, EDP12T, and SEA14T, which rely on only one access transistor. Moreover, in both LDRH16T and SAW16T, the logic '1' is stored through an NMOS pull-up path, which creates a weaker '1'. This makes it easier to discharge during a write operation, thereby reducing the WAT due to a smaller voltage swing between nodes. Among all designs, SAW16T exhibits the shortest WAT. This is attributed to its positive feedback structure formed by the pull-down transistors, where the change in one storage node accelerates the change in the complementary node, resulting in faster write completion. Additionally, LDRH16T uses separate WL and WWL signals to control its two pairs of access transistors. This separation may introduce timing mismatch during the write operation, potentially delaying the initiation of write feedback [9]. In contrast, SAW16T controls both pairs of access transistors using a single WL signal, enabling more synchronized activation and thereby achieving a faster WAT.