# PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA
## 3 Proposed P4-Programmable Parser
### Software Overview
#### 3.1.2 P4 Compiled JSON File
Each of the seven Protocol Investigators in the control unit requires a 1-bit _Enable_ signal and a 2-bit _Select_ signal to choose any 2-byte segment from the 64-bit input. This means that, for each cycle, \(7\times(1+2)=21\) bits are essential to control all Protocol Investigators. Considering that the maximum number of distinct directions for various paths is determined to be four, there are \(4\times 21=84\) bits routed to the third prism multiplexer before the bitmap match. Given that the longest path in our graph is parsed over nine clock cycles, the cumulative number of control set bits directed to the second multiplexer of the prism controller amounts to \(9\times 4\times 21=756\) bits. Additionally, four sets of 10-bit protocol bitmap sets are linked to the first multiplexer of the prism controller. Considering the nine clock cycles required for parsing, this results in a total of \(9\times 4\times 10=360\) bits. Combining these two values yields a total of 1116 bits. Tables 1-3 showcase our design outcomes using Vivado 2022.2 to synthesize the RTL code for an Alveo U280 board. Table 1 presents performance metrics and resource utilization, contrasting the programmability methods and the time taken to transition from a P4 code modification to hardware compared to other studies. Our design consumes 1028 LUTs and 1873 FFs and operates at 237.69 MHz. This frequency leads to a throughput of 15.2 Gb/s for a bus size of 64 bits per clock cycle. Table 2 presents the results of area and throughput for different bus sizes for the overlay design. Finally, Table 3 demonstrates and compares the results of the pipeline design with similar approaches in state-of-the-art works. ### Base Block Design Performance

In terms of performance, our proposed design achieves the highest frequency at 237.69 MHz and the highest throughput at 15.2 Gb/s. This is a significant improvement over other designs, such as [22], which operates at 125 MHz with a throughput of 8 Gb/s, and [18], which achieves a frequency of 173.4 MHz and a throughput of 11.1 Gb/s. Ad

Figure 8: (**a**) Simple firewall graph. (**b**) Access Gateway Function flow graph. ditionally, our design maintains a maximum latency of nine cycles, matching the lowest latency observed among the compared works. Resource utilization is another area where our proposed design excels. It uses only 1028 LUTs and 1873 FFs, considerably lower than the 3538 LUTs and 1447 FFs used by [22]. This efficient resource usage is further highlighted by the total logic usage, which is 2901 in our design, compared to 4029 in FPGA_paper. This demonstrates that our design not only delivers high performance but also does so with optimal use of hardware resources. Regarding programmability, our design utilizes a register file for storing the configuration, similarly to other high-performance designs, ensuring low latency and fast reconfiguration. The configuration time for our design is in the order of seconds, which is significantly faster compared to [22], which requires hours for configuration. The quick reconfiguration capability, combined with our design's efficient resource usage and high performance, makes it highly adaptable and efficient for dynamic network environments. Our proposed design offers superior performance, resource efficiency, and programmability compared to existing works. It achieves the highest throughput and frequency with minimal latency and resource utilization. It is an excellent choice for modern network environments that demand high-performance and scalable packet parsing solutions. ### Pipeline Design Performance

The proposed pipeline design demonstrates excellent performance and resource efficiency compared to other works. Our design achieves a frequency of 282.32 MHz and a throughput of 144.55 Gb/s with a data bus size of 512 bits. Additionally, with a data bus size of 1024 bits, our design reaches a throughput of 289.10 Gb/s while maintaining the same frequency. The maximum latency observed is 31.87 cycles.