## 3 State of the Art of RoT-Based Trusted Environments
It is responsible for creating, monitoring, and maintaining the security environment, including managing the boot process, initializing security-related mechanisms, monitoring the system for any suspicious activity, and implementing an appropriate response. The PSP consists of an ARM microcontroller, cryptographic coprocessors, local memory, local registers, and interfaces to interact with the system memory, IOs, and configuration registers. The primary function of the PSP is to protect the main AMD core and to provide the hardware RoT; the PSP is in charge of the boot sequence using its own ROM and SRAM using the Unified Extensible Firmware Interface (UEFI) Secure Boot process. The communication mechanism between the PSP and the main CPU is implemented by interrupts: the PSP processor can generate interrupts to the CPU using PCI-compliant messages and the main CPU can raise interrupts to the PSP as well. This is accomplished via a PSP-CPU mailbox mechanism. The CryptoManager Root-of-Trust (CMRT) [35; 36] is a family of hardware-based RoT IPs developed by Rambus. It includes a 32-bit RISC-V processor, a ROM unit, and hardware resources dedicated to accelerating the security algorithms and managing the security assets. It also features private buses and interfaces for the integration of One-Time Programmable (OTP) memories and SRAMs within the Trusted Environment. It was developed to assist general-purpose processing units for Internet-of-Things (IoT), automotive, connectivity, and sensor applications. Another commercial solution for hardware RoT is the Synopsys tRoot Hardware Security Module (HSM) [37]. The tRoot HSMs are designed to be integrated into SoCs, and the architecture can be customized depending on the application. The tRoot includes a CPU with secure instructions and data controllers for external storage, hardware key management and protection, hardware accelerators for cryptographic functions, and different interfaces (e.g., UART, GPIO, etc). The main goal of the tRoot is to provide a TEE to protect sensitive information and processing and implement security-critical functions such as secure boot, storage, debugging, anti-tampering, and key management. For what concerns academic solutions, the work in [38], named Basion architecture, is a hardware-software architecture for protecting security software modules in an untrusted software stack. At the hardware level, Basion features dedicated instructions and registers inside the CPU, dedicated registers external to the CPU for storing hash values and keys, and dedicated engines for encryption, hash functions, and random number generation. The strategy in the Basion architecture is to provide direct hardware protection of the hypervisor before employing it to protect the operating system and application modules. A similar solution has been proposed in [39], where the authors present an architecture named HyperWall to provide hypervisor-secure virtualization through hardware support. Also in this case, the solution of [39] proposes a hardware extension applied to a standard processor rather than dedicated and isolated hardware for security. The hardware extension includes new instructions, dedicated registers for the virtualization and key materials, and crypto-engines for random number generation, encryption, and hash functions. Other academic solutions can be found in [40; 41; 42]. The review of the state-of-the-art commercial solutions for TEEs is summarized in Table 1.