# Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs
###### Abstract  
In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research team has already designed, verified and evaluated Multistage Interconnection Networks (MIN) in this field. With respect to the present work, we consider proceeding with further exploring our thoughts on this research area. Firstly, we propose the design and performance evaluation of a hybrid (wireless/wired) MIN, analysing how this augmented network can potentially improve not only the average delay, but also energy consumption. Secondly, we continue with examining the implementation of our advanced DELTA-based MIN architecture on Deep Neural Network (DNN) accelerators, while accounting for its potential regularity and scalability in simultaneously maintaining an effective power efficiency and lower latency throughout the DNN operating process. In this context, several metrics have been evaluated in regard to three DNN application cases through implementation of their main respective modules.  
Network-on-chip; wireless/wired NoC; Multistage Interconnection Network; DNN accelerators +
Footnote †: journal: Applied sciences  
0000-0001-4000-0000-0000-0000-0000-0000-0000-0000-00000-0000-00000-0000-00000-00000-0000-00  
In the domain of massive parallel applications, Deep Neural Networks (DNNs) have been utilized in various fields such as pattern recognition, prediction, and computer vision [16; 17; 18]. These accelerators have traditionally been deployed via ASIC or FPGA designs. However, the performance of artificial neural networks is often constrained by significant communication overheads and storage requirements. For the purpose of improving the reducing interconnection complexity, a regular and scalable NoC stands as a convenient applicable mechanism fit for implementation [19; 20; 21]. Owing to their noticeable data computation and communication distinguishing capacities, DNN accelerators are liable to provide rather effective computational flexibility, design simplicity, and high scalability advantages. Most of the recently elaborated research works have been predominantly focused on exploring efficient NoC topologies likely to minimize power consumption and maximize bandwidth performance through the incorporation of DNN computing. By integrating accurate core mapping and robust routing algorithms, these NoC designs turn out to be capable of maintaining highly flexible communication among PEs, enabling the handling and processing of diverse DNN models with varying data flows by means of a single architecture. Moreover, the system's computational power and performance features could be adjusted to match and cope with the underlying DNN models. Hence, the present work is intended to enrich the relevant literature by providing a twofold contribution. On the one hand, it puts forward a novel Delta-MIN-based design of a hybrid (wired/wireless) NoC. On the other hand, it serves to maintain an effective performance evaluation of DNN accelerators by integrating them within the Delta MIN framework.  
The remainder of this paper is organized as follows: Section 2 provides a general overview of Multistage Interconnection Networks (MINs), along with their respective properties and implementation process. Section 3 explores the review of the related literature in this cross-topic area. Section 4 presents the design of the advanced Delta MIN-based hybrid Network-on-chip. Section 5 examines the implementation procedure of the NOC developed on the Deep Neural Network accelerator. As to the final section, it is devoted to depicting the major conclusions that are drawn.