## 5 Results  
This section presents the results obtained from applying our LET-TDMA method in the dual-core Arm Cortex processor with 4 MB of Flash, 128 KB of Work Flash, and 512 KB of SRAM. An external 16 MHz crystal oscillator drove the internal clocks from both cores. The application core hosts an AUTOSAR 4.0.3-compliant OS, with Scalability Class 1. This OS features fixed priority-based scheduling, handling of interrupts, and start-up and shutdown interfaces. Table 1 shows the configuration parameters for the clocks, the memory type used for the buffers, and the number of configured tasks. To output the measurement times of the read (\(T_{R}\)) and write (\(T_{W}\)) operations, the Instrumentation Trace Macrocell (ITM) hardware available in the Cortex M4 core was used, together with I-jet debugger hardware from IAR Systems and the IAR Embedded Workbench Integrated Development Environment. The two processing cores implemented an event chain with a producer task on the main core and a consumer task on the application core. The consumer task was set as a non-preemptive AUTOSAR basic \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**Core**} & **Clock** & **Prescaled** & **Scheduler** & **Base** & & **Buffer** & **Shared** & **Buffer** \\  & **Frequency** & **Frequency** & **Handler** & **Tick** & **Tasks** & **Memory** & **Buffers** & **Sizes (Bits)** \\ \hline Cortex M0+ & 80 MHz & 1 MHz & ISR & 10 ms & 1 & SRAM & 3 & 8, 16, 32 \\ Cortex M4 & 160 MHz & 1 KHz & AUTOSAR OS & 1 ms & 2 & SRAM & 3 & 8, 16, 32 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Configuration parameters for the Traveo II CYT2B75 Dual-Core Microcontroller. Figure 10: This figure illustrates the measurement of the age latency (L2F), reactive latency (F2F), and maximum age latency (L2L). Additionally, the tasks (\(\tau_{t}\)) performed by the reader (\(T_{R}\)) and writer (\(T_{W}\)) are represented in relation to the synchronization times \(P_{W,R}^{n}\) and \(Q_{W,R}^{n}\). priority, while the producer task was set as a simple function called by an ISR-driven basic scheduler. The dataset to be transferred was designed to represent a simple ramp with a slope of 1, with a task cycle time set to 10 ms. Figure 11 shows the timing of write and read operations for the data values of the slope with a buffer size of 16 bits. Compared to the simulated scenario depicted in Figure 1, it is possible to see that latency in the data transfer has very low variability. Measurements for both 8-bit and 32-bit buffers yielded similar results. The datasets generated for buffer sizes of 8, 16, and 32 bits during the experimentation are accessible in the public repository at [[https://github.com/acmos25/LET-TDMA](https://github.com/acmos25/LET-TDMA)]([https://github.com/acmos25/LET-TDMA](https://github.com/acmos25/LET-TDMA)), accessed on 8 June 2024. Specifically for the configurations of the LET (ISR Core 0 with AUTOSAR Core 1, and ISR Core 0 with ISR Core 1) and LET-TDMA (ISR Core 0 with AUTOSAR Core 1) implementations. Through the experiments, the execution time, accuracy, and latency were evaluated. Comparative analyses were conducted between different system configurations to assess the impact of buffer sizes on system performance. Table 2 shows the behavior of this scenario, including data samples from the write operations on the main core and the read operations on the application core. Tables 3-5 provide samples of the times for data written (\(T_{W}\)) and the times for data read (\(T_{R}\)). These times are crucial for maintaining an operational sequence and ensuring effective coordination between concurrently operating components. Offsets \(\phi_{W}\) and \(\phi_{R}\) were applied to these temporal records to synchronize operations between tasks that require coordinated interaction despite being independent.