# Research and Implementation of High-Efficiency and Low-Complexity LDPC Coding Algorithm
## 5 Design and Implementation of the Codec
### Coder Design and Implementation  
#### 5.2.1 Coder Design  
The coder structure (Figure 5) designed and implemented using the high-efficiency and low-complexity coding algorithm comprises an input/output random access memory (RAM) module, vector adder (VA) module, matrix-vector multiplier (MVM) module, CW generator (CWG) module, cache module, forwarder replacer (FS) module, and control module [28; 29; 30; 31; 32; 33; 34; 35].  
1. Input/output RAM module  
During the encoding process, in order to continuously process the data and reduce the time complexity of operations, the ping-pong pipeline method shown in Figure 6 is used to store the data. The input RAM and output RAM are both dual-port RAM. By using the ping-pong operation, not only can data be seamlessly and continuously processed, but storage space can also be saved, and hardware implementation is easy.  
2. Matrix Multiplier (MVM) Module  
The multiplier in the encoder is executed in parallel, consisting of a cyclic shifter and a modulo two adder. Its structural principle diagram is shown in Figure 7. The high 4 bits of the register store the row number of the check matrix, the middle 4 bits store the column number of the check matrix, and the low 7 bits store the circularly shifted value. By performing a cyclic shift operation on the vectors in the corresponding information  
Figure 5: Functional block diagram of coder implementation.  
Figure 6: Principle diagram of Table Tennis Pipeline Mode.  
bits, a non-zero element and information bit multiplication operation can be completed. Then, the operation of multiplying the entire row of the matrix by the information bits can be performed, that is, multiplying all non-zero elements in this row by the information bits. Finally, performing the modulo 2 addition operation can complete the multiplication operation of the matrix.  
In the design and implementation process of the encoder, how to effectively store the information of the verification matrix and how to effectively reduce the storage amount are the core issues of the research topic. From Figure 7, it can be seen that the elements of each row in the base check matrix are stored as 15 bits in a fixed row, which not only saves a lot of storage resources but also facilitates hardware implementation. For the LDPC code studied in the project, using traditional methods to store the verification matrix requires \(4.42\times 10^{5}\) bits resource space, whereas using the above methods only requires \(8.38\times 10^{3}\) bits resource space.  
\(\lx@sectionsign\)  Forward Displacer (FS) Module  
In the design process of the encoder, the forward displacement method was used to solve \(f_{3}=T^{-1}f_{1}\), and the calculation process can be completed using XOR operation. It has the characteristics of low computational complexity, low resource consumption, and easy hardware implementation. The calculation process is as follows:  
Set up \(f_{1}=(v_{1},v_{2},\cdots,v_{m_{b}-1})\), \(f_{3}=(c_{1},c_{2},\cdots,c_{m_{b}-1})\), There are:  
\[f_{3}=T^{-1}f_{1}\Rightarrow Tf_{3}=f_{1}\Rightarrow\left\{\begin{array}{l}c _{1}=v_{1}\\ c_{1}+c_{2}=v_{2}\\ c_{2}+c_{3}=v_{3}\\ \vdots\\ c_{m_{b}-2}+c_{m_{b}-1}=v_{m_{b}-1}\end{array}\right.\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\Other modules  
In addition to the modules discussed above, the encoder consists of a vector adder module (VA), a control module (Control), and a cache module (Cache). The function of the VA module is to perform addition operations between vectors; the function of the control module is to generate the control signals required during the encoding process; and the function of the cache module is to coordinate with the next step of data synchronization.