# Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
## 4 Performance Comparison of Proposed Structures
### Comparison of Noise Margin for a Single Bit-Cell  
Noise margin is a critical parameter in digital circuit design, particularly in memory structures like SRAM, as it defines the maximum allowable range of electrical noise within which a signal can still be interpreted correctly. This metric represents the tolerance of the circuit to electrical fluctuations or disturbances, which may arise from environmental  
Figure 12: (**a**) Power comparison in read operation and (**b**) power comparison in write operation.  
factors or inherent circuit noise. A larger noise margin indicates greater robustness, as it allows the circuit to maintain data integrity under noisy conditions or at lower operational voltages. In SRAM cells, a high noise margin is essential for stable data storage, as it reduces the likelihood of unintended data flips or errors during read and write operations. Therefore, a larger noise margin directly translates to enhanced stability and reliability of the data stored within the SRAM cells, especially under low-voltage or energy-constrained operating conditions.  
Figure 13 presents a comparison of the read noise margin (RNM) and write noise margin (WNM) between the 8T SRAM structure proposed in this study and the modified low power 8T SRAM structure depicted in Figure 11b. This comparison provides insight into the noise resilience of each design and demonstrates the improvements achieved in the proposed structure. In Figure 13a, we observe that the RNM of the 8T structure from Figure 11b is measured at 192.64 mV. This value reflects the tolerance of the prior design to noise during read operations; however, it may be insufficient in environments with significant noise interference or in low-power applications where the risk of noise-induced errors is higher. In contrast, the RNM of the proposed 8T SRAM structure is significantly higher, measured at 393.68 mV. This increase of approximately 104.38% in RNM indicates that the proposed design has more than doubled its resilience to noise during read operations, which greatly enhances its suitability for stable data retrieval in various environmental conditions.  
Figure 13b illustrates a similar comparison for the write noise margin (WNM). The WNM of the 8T structure from Figure 11b is measured at 434.84 mV, indicating its noise tolerance during write operations. Although this margin is adequate for conventional applications, it may not provide sufficient robustness in applications requiring stringent noise immunity. The proposed 8T SRAM structure, however, exhibits a WNM of 561.26 mV, reflecting a substantial increase of 29.07% over the compared structure. This improvement in WNM suggests that the proposed design is more capable of withstanding noise during write operations, reducing the likelihood of data corruption and enhancing overall data stability. This higher noise tolerance in both read and write operations results in a clearer distinction between signal and noise, thus reducing the risk of operational errors and  
Figure 13: (**a**) Read noise margin and (**b**) write noise margin comparison graph.  
allowing the circuit to maintain functionality even in the presence of variable noise levels and environmental disturbances.