## 4 Measurement Results  
The proposed receiver front-end was designed in TSMC 45 nm CMOS technology. The proposed receiver front-end was simulated with SpectreRF from Cadence and the electromagnetic effects of critical interconnect lines were considered by Advanced Design System (ADS). The fabricated chip was encapsulated in a quad flat no leads (QFN) package for connecting dc pads and IF output. The RF and LO signals were applied using on-wafer probing to reduce the losses and mismatches. Keysight N5234A as used for S-parameter measurement and Keysight N9010A-544 was used for spectrum analysis and noise figure measurement. The chip photograph of the implemented receiver front-end is shown in Figure 11. The total area of the chip is 0.42 mm\({}^{2}\), and the core circuits occupies 0.21 mm\({}^{2}\). The entire circuit consumes 96 mW with 1.2 V power supply. Figure 12a shows the input reflection coefficient (S\({}_{11}\)). The target level was chosen as \(-\)10 dB for stable power transfer. There was a little frequency shift in S\({}_{11}\) due to the un-accounted parasitics in the interconnect line, but the broad impedance matching performance with S\({}_{11}<\)\(-\)9 dB was achieved within the 30-40 GHz frequency range. Figure 12b shows the conversion gain and double-sideband NF over the 10 GHz IF frequency range of the implemented receiver front-end. The measured conversion gain was 10.3-16.5 dB. We measured a maximum conversion gain of 16.5 dB at 50 MHz IF frequency. Measured NF integrated over a 10 GHz IF bandwidth was 5.9 dB, whereas the simulated NF over the same integration bandwidth was 5 dB. Linearity performance is shown in Figure 12c. The measured IIP3 was around \(-\)11 dBm, based on the two tone input injection tones at 35 GHz and 35.1 GHz. A large signal linearity performance was measured with a 1 dB compression point as shown in Figure 12d. The implemented receiver front-end showed \(-\)19 dBm of 1 dB compression point (P1 dB). Measured P1 dB and IIP3 showed an 8 dB difference, close to the theoretical discrepancy between the two [18]. Table 2 summarizes the performances and compares the performances with other recent works. It is clear that the proposed front-end exhibits the largest RF and IF bandwidth while having a small die area, moderate power consumption, and comparable performance to previous studies. Therefore, it is proven that the proposed front-end is suitable for the various Ka-band applications as well as channelization receiver systems.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Specification** & **This Work** & **TMTT 12 [19]** & **IMS 15 [20]** & **JSSC 17 [7]** & **TICAS-II 19 [21]** \\ \hline RF Frequency [GHz] & 30–40 & 20–30 & 18.2–21.4 & 28–32 & 33.6–36.3 \\ IF Bandwidth [GHz] & 10 & 0.3 & 1.35 & 4 & 2.3 \\ Gain\({}_{max}\) [dB] & 16.5 & 18.7 & 49 & 10.5 & 30.9 \\ NF [dB] & 5.9 1 & 7.1–14.2 & 5.25–6.25 & 5.6–8.6 & 5.9–7.5 \\ IIP3 [dBm] & \(-\)11 & \(>\)\(-\)7.6 & \(>\)\(-\)33.5 2 & \(>\)\(-\)10.6 & N/A \\ P\({}_{1\text{dB}}\) [dBm] & \(-\)19 & \(>\)\(-\)17.9 & \(>\)\(-\)43.3 3 & \(>\)\(-\)16.8 & \(-\)23 \\ P\({}_{consumption}\) [mW] & 96 & 5.2 & 80 & 136.5 & 135/27.6 4  \\ Technology & CMOS 45 nm & CMOS 180 nm & SiGe 180 nm & SiGe 130 nm & CMOS 65 nm \\ Area [mm\({}^{2}\)] & 0.42/0.21 5 & 0.18 & 0.4/0.24 5 & 1.08 & 2.16 6  \\ \hline \hline \end{tabular}
\end{table}
Table 2: Performance comparison.