# Design and Implementation of DSLMS Algorithm Based Photoelectric Detection of Weak Signals
## 4 DSLMS Adaptive Filter  
FPGAs (Field Programmable Logic Gate Arrays) excel in parallel processing power, fast data computation, on-demand reconfigurable flexibility, and strong customization adaptability, which make them an ideal hardware platform for implementing efficient and complex DSLMS algorithms [31,32]. The LMS algorithm requires many matrix and vector operations, and the FPGA's ability to perform multiple computational tasks, weighted updates, and error calculations in parallel ensures smooth processing of the data stream through the filter design, significantly accelerating the data processing rate [33]. In addition, the reconfigurability of FPGAs allows researchers to tailor the hardware logic to the LMS filter requirements, which not only helps to optimize the computational tasks but also allows the logic to be adjusted to the characteristics of the input data, which in turn improves the processing efficiency [34]. For the DSLMS algorithm proposed in this paper, FPGAs can achieve precise and rapid step-size adjustments, thus enhancing the stability and performance of the algorithm. Given these significant advantages of FPGAs, this study chooses to use them as the platform for DSLMS filter design. In this design, the filter is divided into four modules: a filter fir module, an error calculation (error_n) module, a step size update (mu_update) module, and a weight update (w_update) module, which realizes filter coefficient updating, error data updating, and filter calculation functions. With these four modules, the following five-step operation is realized:  
1. Filter calculations: \(\mathrm{dy_{j}}=\mathrm{w_{j}}\times\mathrm{x_{j}}(\mathrm{j}=0\,\sim 11)\). 2. Calculate the filter result and output \(\mathrm{yout}=\sum_{\mathrm{j}=0}^{11}\mathrm{dy_{j}}\). 3. Calculation of errors: \(\mathrm{e_{j}}=\mathrm{d_{j}}-\mathrm{yout}\). 4. Calculation of new weights: \(\mathrm{dw_{j}}=2\mathrm{u_{j}}\times\mathrm{e_{j}}\). Updating weights: \(\mathrm{w_{j}}=\mathrm{w_{j-1}}+\mathrm{dw_{j}}\). In the data filtering module, after receiving the signal pulse, the weighting of the input data is performed, and the results are truncated for output. Due to the feedback mechanism in the DSLMS algorithm optimized for noise correlation characteristics, the filtering process can lead to an overflow of computation results. Proper decimal point alignment will be ensured in the addition module to prevent computational errors due to overflow. In the face of integer bit-width mismatches, sign bit padding is performed on shorter-bit-width digits to match longer-bit-width digits; zero padding is performed on decimal bit-width mismatches to align them. In the module design, the saturation truncation strategy is implemented before the module outputs the results to ensure the accuracy of the calculation results, avoid data overflow, and retain as many valid bits as possible for the critical weight. For the error calculation module, the module summarizes the filtering results from the previous stage and performs eight rounds of addition operations. After completing these operations, a saturation truncation process is applied, and the computed results are compared with the target signal to calculate the difference. Such a process aims to ensure computational accuracy while reducing distortion caused by numerical limits. In the weight update module, a 16-bit multiplier with 16-bit multiplication calculates the weight update, producing a 32-bit result. This result then needs to be combined with the existing filter coefficients, which involves a truncation process to accommodate the bit width of the coefficients. To deal with this bit-width mismatch and avoid data overflow, a saturated truncation method is used in the system design, whereby when the multiplication result exceeds the maximum value that the target bit width can represent, the output is limited to the maximum value that can be defined, thus maintaining the validity of the result.