# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 3 Methods of Reducing Power Consumption in CMOS Integrated Circuits  
The CMOS technology uses metal-oxide-semiconductor (MOS) field-effect transistors to create gates, flip-plops, and memory blocks such as RAM and ROM, and so on [60]. Each gate uses complementary and symmetrical pairs of p-type and n-type transistors. For example, it requires two MOS transistors to implement the circuit of a NOT gate (Figure 2a). The NOT gate operates in the following manner. If the voltage \(V_{in}=\) \"0\", then the equivalent electrical circuit is shown in Figure 2b. The transistor T\({}_{A}\) is open; its resistance \(R_{A}=0\). At the same time, the transistor T\({}_{B}\) is closed, and its resistance R\({}_{B}\) is close to infinity. It means that the following relation takes place: \(V_{out}=V_{dd}=\) \"1\". If \(V_{in}=\) \"1\", then T\({}_{A}\) is closed (its resistance is close to infinity) and T\({}_{B}\) is open (its resistance is close to zero). It gives \(V_{out}=GND=0\) (Figure 2c). This situation is common: if one of transistors is open, then the second transistor of the pair is closed. Of course, there is an ideal mode of operation shown in Figure 2. In this ideal case, there is no current between \(V_{dd}\) and \(GND\). Thus, the so-called leakage current \(I_{leak}\) is absent. But in reality, the resistance of a closed transistor is far from infinity, and the resistance of an open transistor is greater than zero. This means that a small leakage current still exists. This current is responsible for the static power consumption of a CMOS gate in its stable state. There is parasitic load capacitance between the wires \(V_{out}\) and \(GND\). It is responsible for a dynamic power consumption of a gate. Obviously, it takes some time to charge (from \"0\" to \"1\") or discharge (from \"1\" to \"0\") the parasitic capacitor \(C_{par}\). Until the final stable voltage (either \"0\" or \"1\") is established at the gate output, some power is consumed. When a gate is switched, there is a very small instant of time when both transistors are open. It means that during that time, there is a short circuit current \(I_{sc}\) between the voltage source \(V_{dd}\) and the ground, \(GND\). Therefore, there are two categories of power consumption in CMOS gates: static and dynamic. The static power \(P_{st}\) is connected with the existence of the leakage current \(I_{leak}\). The static power is determined as follows [61; 62]:  
\[P_{st}=I_{leak}V_{dd}. \tag{9}\]  
Figure 2: CMOS-based NOT gate (**a**) and its stable states (**b**,**c**). The dynamic power \(P_{dyn}\) is connected mostly with the charging and discharging of the capacitor \(C_{par}\). It is determined by the following expression [63]:  
\[P_{dyn}=\alpha C_{par}V_{dd}^{2}f_{op}. \tag{10}\]  
In (10), the symbol \(\alpha\) stands for a switching activity, \(f_{op}\) is an operating frequency. Up to this point, we have analyzed 64 articles and monographs. Summarizing the analysis of these sources, we can list some reasons showing the importance of reducing power consumption. They are the following:  
1. A lot of devices are mobile and/or autonomous. They receive energy from batteries. To prolong the lifetime of these devices, it is necessary to consume as little energy as possible. If we diminish the power consumption, then we reduce the degree of heating of a chip. In turn, we are able to use smaller power supplies and reduce heat-dissipation overhead. Most importantly, it reduces the cost, weight, and size of devices. This is especially important when implementing embedded systems [64]. 2. The lower the operating temperature, the higher the reliability and the longer the lifetime of the device. As shown in [1], the device failure rates are increased by up to a factor of two, if there is a 15 degree Celsius rise in temperature. Thus, the heat dissipation should be reduced to make CMOS-based systems more reliable. 3. The improvement of CMOS technology results in a growth of the on-chip transistor densities and in diminishing the delay.