# A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit
## 5 The Experimental Results  
The proposed four-phase all-digital DLL with a de-skew circuit is fabricated in a 0.13 \(\upmu\)m CMOS process. Considering the frequency range and phase accuracy requirements of the onf protocol, this paper chooses \(N_{CDU}=N_{MDU}=16\) and \(N_{FDIU}=8\). The micrograph of the test chip is shown in Figure 12 with a core area of 0.072 mm\({}^{2}\). The testbench and printed circuit board (PCB) are shown in Figure 13. The arbitrary waveform generator (M8190A, Keysight) provided an input clock with a frequency range of 26 MHz to 1.55 GHz for the test chip, and the power supply provided a 3.3 V DC voltage to the PCB, which was converted by the low dropout regulator (LDO) to 1.2 V for the chip. The multi-channel high-frequency signals were captured with the digital signal analyzer (DSAV334A, Keysight). Figure 11: The delay paths of the proposed parallel-cascaded configuration. Figure 12: The test chip micrograph. Figure 14 shows the delay range and unit delay of sub-lines in the de-skew circuit under different PVT conditions, from which three inferences can be drawn. First, the \(T_{MDL,max}\) can cover the \(t_{CDU}\) and the \(T_{FDL,max}\) can cover the \(t_{MDU}\), even in the case of PVT variations. These relationships are consistent with Equations (7) and (8), which indicates that the de-skew circuit can cover the required frequency range. Second, according to Equation (6), for the case that the duty cycle distortion factor is 10, the delay path length \(T_{DCDL,max}+t_{int}\) cannot be lower than 18.2 ns to meet the ONFI 5.0 requirements for \(f_{min}=33\) MHz. The data show that \(T_{DCDL,max}+t_{int}\) is greater than 18.2 ns under different PVT conditions, so this design can cover the \(f_{min}\) of 33 MHz. Third, considering the \(N_{FDU}=8\), the phase accuracy of the de-skew circuit is \(T_{step}=t_{FDU}=T_{FDL,max}/N_{FDU}=130\) ps/\(8\approx 17\) ps. Figures 15 and 16 show the comparative results of the four-phase DLL without de-skew circuit and four-phase DLL with de-skew circuit, respectively. It can be seen from Figure 15 that CLK90, CLK80, CLK270 and CLK360 are the exact four-phase outputs based on CLK0 instead of SCLK. This is because the unpredictable clock skew exists between  
Figure 14: The delay range and unit delay of sub-lines under different PVT conditions. Figure 13: The testbench of proposed DLL. CLK0 and SCLK, causing the four-phase outputs to be offset from SCLK. In Figure 16, since the embedded de-skew circuit eliminates clock skew, CLK90, CLK180, CLK270 and CLK360 are the exact four-phase outputs based on SCLK. In addition, with \(f_{clock}\) = 1.25 GHz and a 40% duty cycle as shown in Figure 16, the proposed FPA can correctly adjust the clock phase in the case of duty cycle distortion. Figures 17 and 18 show the chip testing results, where the proposed circuit has an alignment error of 15.51 ps at \(f_{clock}\) = 26 MHz with 46.8% duty cycle and 2.42 ps at \(f_{clock}\) = 1.55 GHz with 50.9% duty cycle. They also show that the operating frequency ranges from 26 MHz to 1.55 GHz and the typical alignment error is about 17 ps, which fully meets the requirements of the ONFI 5.0 protocol for NAND Flash high-speed interfaces. Moreover, due to the advantages of the high portability and stability of the ADDLL, the circuit easily achieves higher operating frequencies by porting the advanced process to meet the updates of the ONFI protocol. Table 1 compares the performance of DLLs. It can be seen that the proposed DLL supports both four-phase clock outputs and clock skew elimination and achieves a wide frequency range while maintaining high accuracy and low power consumption, which is suitable for NAND Flash high-speed interfaces. Figure 16: The locking process of four-phase DLL with de-skew circuit at \(f_{clock}\) = 1.25 GHz. Figure 15: The locking process of four-phase DLL without de-skew circuit at \(f_{clock}\) = 1.25 GHz. Figure 17: The chip testing results of proposed four-phase DLL with de-skew circuit at \(f_{clock}\) = 26 MHz.