# Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices
## 4 3D NAND Reliability
### Disturbs  
In the 3D NAND architecture of Figure 34, strings are vertically aligned while control gates run over parallel planes [28], meaning that read and program/pass disturbs are much more complex with respect to a planar layout, as different pages now share the same WL. Moreover, the onset of disturbs is strongly related to the actual array architecture and internal subdivision as well as operation mode; therefore, extreme care should be taken before generalizing the following results. A schematic of the different types of program disturb is reported in Figure 41[294; 354]: an \(x\) mode for cells on the same selector line but different BLs, analogous to conventional 2D arrays, a \(y\) mode for cells on the same BL, and a mixed \(xy\) mode for all other cells sharing the programmed WL. The modes differ for the BL bias (selected cell and \(y\) mode disturb = 0; \(x\) and \(xy\) modes = high) and the drain selector bias (selected cell and \(x\) mode disturb = high; \(y\) and \(xy\) modes = 0), meaning that different boosting levels are achieved. As a matter of fact, the channel is first precharged to a high voltage in \(x\)-mode disturb before being boosted, while it is boosted from ground level during \(y\) mode, resulting in a lower potential (i.e., increased disturbs) in the latter case, as shown in Figure 42 (left) [355].  
Figure 40: RTN complementary cdf for vertical poly-Si channel transistors having different channel diameter (**left**) and poly-Si grain size (**right**) [334], © 2012 IEEE.  
The boosting efficiency of 3D NAND is affected by different factors, such as the coupling coefficient and the leakage current. A high coupling coefficient is expected in 3D NAND because of the floating channel lacking a silicon substrate [356]. On the other hand, the worse subthreshold slope of 3D polysilicon devices with respect to planar devices increases the leakage current that discharges the boosted channel potential [294; 354]. Clever device optimization, including selector design and insertion of dummy cells to relieve edge WL disturbs, eventually leads to much alleviated program disturbs, as shown in Figure 42 (right) [354]. Other optimization schemes such as an initial channel precharge phase [357] and selector doping [358] have been also proposed. In analogy with planar devices, suitable management schemes for 3D NAND have been also proposed [359; 360]. Similar considerations apply to vertical-gate structures, in which channel arrays are horizontally stacked with vertical WLs [361; 362].  
A study of read disturb in 3D NAND was presented in [363], highlighting an enhanced disturb on unselected cells due to channel boosting. A related effect was discussed in [364], where it is shown that the trailing edge of the WL bias at the end of a read phase can draw the channel potential negative, as it becomes floated when high-\(V_{T}\) cells along the string are turned off. This can become an issue if the read operation is followed by a program one, as in program-verify steps: the channel of program-inhibited cells will now reach a lower boosted potential, resulting in increased program disturbs. Suitable program schemes must therefore be adopted to avoid this issue.