## 3 Results  
A study of sequential techniques for encoding FSM states was conducted using benchmarks from the Microelectronics Center of North Carolina (MCNC) [28], with FSM implementation on the Cyclone 10 LP FPGA family utilizing the Quartus design tool version 23.1. Initial experimental investigations revealed that methods constructed using the max_P mode did not yield satisfactory solutions; hence, they will not be further explored. The MCNC benchmarks are described in the KISS2 format [22; 28], a standardized textual representation that is easily parsed by software tools. This format offers a clear and concise way to represent FSMs, consisting of a header section and detailed transition descriptions. The header section provides essential information about the FSM, including the number of inputs, outputs, states, and transitions. Following the header, the KISS2 format outlines the state transitions in a structured manner. Each transition is described on a new line, specifying the input combination, current state, next state, and output combination. Table 1 presents the basic parameters of the FSM test examples sourced from the MCNC benchmark dataset which were utilized in our research. This research involved the development a specialized application called sequential_state_encoding, which is part of the ZUBR university package for digital device design [29]. This application was engineered to encode the FSM states based on various state and code selection modes. The application accepts an FSM description as input in the form of a text file in the KISS2 format, allowing users to select from different state and code selection modes tailored to specific optimization goals and hardware architectures. The state encoding process within the application involves several selection modes, which determine the order in which states are encoded:  
* In max_P mode, the state with the highest number of outgoing transitions is selected;
* In max_C mode, the state with the highest number of incoming transitions is selected;
* In P mode, the state from which the maximum number of transitions leading to already encoded states is chosen;
* In C mode, the state with the maximum number of transitions starting from already encoded states is selected;
* In P_C mode, the state with the maximum number of links to already encoded states is chosen;
* In max_X mode, the state affected by the highest number of input variables in its transitions is selected. Additionally, the code selection modes were designed to optimize the FSM for different hardware architectures (FPGA, CPLD, or ASIC) where the FSM is implemented. This is reflected in the computation of the area of the FSM transition functions:  
* In FPGA mode, the area is computed using Equation (9);
* In CPLD mode, the area is determined using Equation (7);
* In ASIC mode, the area is calculated using Equation (8). Furthermore, the max_w code selection mode aims to minimize the maximum weight of the transition functions, whereas the diff_w mode seeks to minimize the disparity between the maximum and minimum weights of these functions. Consequently, while the max_w mode focuses on enhancing the performance of the FSM, the diff_w mode strives to optimize both the performance and the area of the FSM. For each FSM benchmark, the application sequentially selected states and assigned appropriate codes based on the chosen modes, generating various encoding configurations. The application produces a KISS2 file containing state encoding, which is then processed using a ZUBR package converter. This converter translates the state-encoded KISS2 file into an FSM description in a selected Hardware Description Language (HDL). The ZUBR package converters facilitate the conversion of KISS2 files into Verilog, SystemVerilog, or VHDL, and allow for the selection of different FSM description styles [21]. In Appendix A, we include a sample Verilog description of the FSM for the shiftreg test example, generated using the P_C_max_w state encoding mode.