# Design Trends and Comparative Analysis of Lightweight Block Ciphers for IoTs
## 4 Related Work
### Addition-Rotation-XOR (Arx)  
The BRIGHT [53] cipher is an LWBC family designed specifically for 32-bit processors, optimized for IoTs and resource-constrained environments. It employs an ARX (addition-rotation-XOR) structure, providing high diffusion and fast execution speed, making it ideal for applications with strict memory and computational limitations. The BRIGHT family includes six variants with different block and key sizes as presented in Figure 38, supporting 64-bit and 128-bit blocks. Its design incorporates key whitening, ARX operations, and round permutation, offering resistance against weak key attacks and efficient parallel implementation. Performance evaluations show that BRIGHT variants meet the Strict Avalanche Criteria (SAC), exhibit strong key sensitivity, and achieve superior performance in terms of speed, memory usage, and execution time compared to existing lightweight ciphers such as SPECK and RoadRunner. The cipher's efficiency and compact size make it highly suitable for IoTs devices, where low-power consumption and memory constraints are critical. BRIGHT is optimized for 32-bit software-based applications, making it less suitable for hardware implementations. Its computational complexity and memory usage vary across variants, and while secure against known attacks, its resistance to emerging cryptanalysis techniques remains unverified. Additionally, key whitening plays a crucial role in security, and performance on lower-bit architectures needs further evaluation. The paper introduces LiARX [54], an LWBC designed using the ARX architecture and the Long Trail Strategy (LTS), suitable for resource-constrained devices such as RFID tags and sensors. It discusses the fundamental characteristics of lightweight cryptography, emphasizing small block sizes and simple round functions to optimize performance and reduce resource usage. The ARX-based LiARX cipher aims to provide both efficiency and security against cryptographic attacks. The cipher design incorporates MARX-2 as the ARX box, a linear mixing layer as indicated in Figure 39, and a key schedule inspired by the generalized Feistel structure. Empirical results demonstrate LiARX's competitive performance, surpassing existing ciphers such as LED in efficiency and closely matching SPECK in terms of resource consumption, making it a promising candidate for low-power IoTs applications. One limitation of the LiARX cipher lies in its reliance on the ARX architecture, which, while efficient and resistant to certain side-channel attacks, still faces challenges against differential and linear cryptanalysis, particularly in the absence of traditional S-boxes. The use of ARX-based design strategies, while minimizing look-up tables and reducing memory requirements, limits its ability to provide robust non-linearity, making it potentially  
Figure 38: Layers in the BRIGHT family of ciphers. vulnerable to sophisticated attacks that exploit weak points in the ARX transformations. Furthermore, the cipher's security relies heavily on the effective design of the ARX boxes and the linear layers, which can be difficult to optimize without increasing complexity or compromising performance. DABC [55] (Dynamic ARX-based Lightweight Block Cipher) is designed to address several weaknesses in traditional ARX-based ciphers, particularly their poor diffusion and static structures. By combining ARX operations with a dynamic permutation layer based on the generalized two-dimensional cat map, DABC enhances the diffusion effect and improves resistance to attacks. The cipher alternates between NAND and AND gates in its round functions, as evidenced by Figure 40, to further increase security without excessive hardware resource consumption. It features a round-based architecture that supports both 96-bit and 128-bit keys, and its implementation on FPGA and ASIC platforms demonstrates high throughput and low resource usage. DABC's performance is competitive, particularly in terms of hardware efficiency and security, making it suitable for resource-constrained IoTs devices.