## 3 System Design
### Acquisition in High-Sensitivity Mode
#### 3.4.3 Implementation
Figure 8 shows a detailed block diagram of the CAF computation module shown in Figure 6, as it is implemented in the FPGA. The CAF computation module performs Doppler wipeoff and computes the circular correlation between the received signals and the local replica of the pilot tiered code in the frequency domain. It has four memory interfaces implemented using the AMBA AXI4-Lite protocol specification [34]: AXI4-Lite  
Figure 7: Acquisition timing diagram. interface 1 fetches the FFT of the local replica of the pilot-tiered code from the PL memory component. AXI4-Lite interface 2 fetches the captured samples from the analog front-end, which are also stored in the PL DDR4 memory component. AXI4-Lite interface 3 stores the computed CAF in the PL DDR4 memory. These three memory interfaces perform read and write transactions to and from the PL DDR4 simultaneously, thus decreasing the acquisition latency. AXI4-Lite interface 4 exposes a bank of memory-mapped registers to the embedded processor. The embedded processor uses these registers to configure and control the acquisition process. Furthermore, the CAF computation module also incorporates the following units, as depicted in Figure 8: a Doppler wipeoff unit, a unit for computing large FFTs and IFFTs (the large FFT/IFFT block), a unit for multiplying the FFT output with the local replica of the pilot tiered code (the Enable/Disable Local Code Mult block), and a unit for reporting a scaling factor to the embedded processor. This scaling factor is automatically applied to the FFT/IFFT output to prevent saturation, and it is referred to as the block exponent in Figure 8. Finally, a state machine controls the execution of the CAF computation, which occurs in two steps:  
1. In the first step, the CAF computation module computes the frequency domain representation of the circular correlation: the module fetches 100 ms of samples from the PL memory component, performs Doppler wipeoff, computes the FFT of the Doppler-corrected signal, and multiplies the results by the FFT of the local replica of the pilot tiered code. Finally, the result of this multiplication is stored back into the PL memory component. Storing intermediate results in the PL memory component reduces FPGA memory usage. During this first step, the Enable/Disable Doppler wipeoff block and the Enable/Disable FFT Multiplication block shown in Figure 8 are enabled. The local carrier used for Doppler wipeoff is efficiently implemented using the Coordinate Rotation Digital Computer (CORDIC) algorithm [38]. 2. In the second step, the CAF computation module calculates the time-domain representation of the circular cross-correlation. It retrieves the results of the multiplication of the FFT by the local replica obtained in step 1, performs the IFFT, and then stores the results back in the PL memory component. The large FFT/IFFT module depicted in Figure 8 computes the FFT and the IFFT, applying a scaling factor to the input signals to prevent overflow in the calculations. The scaling factor applied is made available to the embedded processor through the Report Block Exponent block. The embedded processor normalizes the application of the scaling factor to ensure uniform scaling across all Doppler frequencies and GPDIT iterations. Figure 8: CAF computation module. Figure 9 shows a block diagram of the large FFT/IFFT module depicted in Figure 8. This module computes large FFTs and IFFTs by combining multiple small FFTs and IFFTs with complex exponentials, extending the transform size. This approach is explained in Section 3.4.2 and illustrated in Equation (6), where an \(N\)-point DFT is computed as a weighted combination of \(P\) DFTs, each of length \(N/P\). The same principle applies for the computation of the IFFT. The 64k-FFT/IFFT module, shown in Figure 9, is implemented using AMD's FFT LogiCORE IP v9.1 [39]. This FFT core imposes a maximum transform size limit, restricting it to \(2^{16}=64k\) samples.