# Integrated DVB-X2 Receiver Architecture with Common Acceleration Engine
## 5 Implementation Results and Lab Test  
The proposed DVB-X2 receiver is implemented with a tuner block, a H/W-based receiver engine, a frame processor, and an A/V decoder as shown in Figure 14. The tuner block is composed of DVB-T2, DVB-C2, and DVB-S2 tuner modules. The DVB-T2 and DVB-C2 tuner modules are implemented in the same way using a half-network interface module (NIM) type tuner for DVB-T/C and a 14-bit analog-to-digital converter (ADC), and the DVB-S2 tuner module is implemented using a half-NIM type tuner for DVB-S/S2 and a 10-bit ADC. The DVB-X2 receiver engine for demodulation and channel decoding functions is implemented using two FPGA devices. The implementation results are given in Table 3. The frame processor is implemented with 256 MB memory and a DSP operating at up to 1.0 GHz, and the A/V decoder is implemented with a commercial chip for IP set-top boxes. Figure 12: Block diagram of the channel estimator and equalizer. Figure 13: Block diagram of residual STO and CFO synchronization. Table 4 shows a comparison of FPGA resource utilization for DVB-T2, DVB-C2, DVB-S2, and DVB-X2 demodulators. As shown in Table 4, the proposed DVB-X2 demodulator requires the same amount of memory while slice registers, slice LUTs, and DSP48 Es require 43.3%, 10.5%, 16.7% more resources compared to the DVB-T2 demodulator, respectively. To verify the functionality and reliability of the proposed DVB-X2 receiver, tests were conducted in the laboratory as shown in Figure 15. Commercial PC-based modulators are used to generate DVB-T2, DVB-C2, and DVB-S2-modulated signals. The laboratory test was conducted for more than 24 continuous hours and results show that the proposed DVB-X2 receiver operates without any service interruption. To verify the functionality and performance of the frame processor, the time to process the T2 frame generated as a test parameter of Table 5 was measured. DVB-T2, DVB-C2, and DVB-S2 all share similar BB frame structures, but signal processing of baseband in DVB-T2 is the most complicated, so the T2 frame was used for the test. The T2 frame, made up of the P1 symbol, the P2 symbol and data symbols, was received for every 9268 us. Table 6 shows the results of the time measurement for processing the T2 frame. For the measurement of processing time, the DSP \begin{table}
\begin{tabular}{l c c c c} \hline  & **DVB-T2** & **DVB-C2** & **DVB-S2** & **DVB-X2** \\  & **Used 1 (Scale 2)** & **Used (Scale)** & **Used (Scale)** & **Used (Scale)** \\ \hline Slice Registers & 7117 (100\%) & 5388 (75.7\%) & 5158 (72.5\%) & 10,200 (143.3\%) \\ Slice LUTs & 81,160 (100\%) & 43,781 (53.9\%) & 10,868 (13.4\%) & 89,715 (110.5\%) \\ Memory (KB) & 8064 (100\%) & 2340 (29.0\%) & 2106 (26.1\%) & 8064 (100.0\%) \\ DSP48 Es & 144 (100\%) & 81 (56.3\%) & 34 (23.6\%) & 168 (116.7\%) \\ \hline \end{tabular}
\end{table} 
Table 4: Comparison of resource utilization in DVB-T2, DVB-C2, DVB-S2, and DVB-X2 demodulators. Figure 14: Implementation of the proposed DVB-X2 receiver. \begin{table}
\begin{tabular}{l c c} \hline  & **FPGA Device 1** & **FPGA Device 2** \\  & **(Demodulator 1)** & **(LDPC Decoder)** \\  & **Used/Available** & **Used/Available** \\  & **(Utilization)** & **(Utilization)** \\ \hline Slice Registers & 10,200/207,360 (4\%) & 9868/207,360 (4\%) \\ Slice LUTs 2 & 89,715/207,360 (43\%) & 34,988/207,360 (16\%) \\ Memory (KB) & 8064/10,368 (77\%) & 3978/10,368 (38\%) \\ DSP48 Es 3 & 168/192 (87\%) & 0/192 (0\%) \\ \hline \end{tabular}
\end{table} 
Table 3: Implementation results for the DVB-X2 receiver engine. internal timer with clock cycle 6 ns was used. As the result of the measurement indicates, the frame processor needs 3717 us to process the T2 frame, which satisfies the required time of 9268 us. The frame de-mapping function, the frame decoding function, and de-interleaving functions such as frequency, cell, and time, do not require much processing time.