# Design of Static Random-Access Memory Cell for Fault Tolerant Digital System
## 3 Radiation-Hardened SRAM Cell Design
### Radiation-Hardened-by-Design 10 T and 14 T SRAM Cell (RHBD-10 T and RHBD-14 T)  
In Quatro-10 T, PS-10 T, or NS-10 T, only 1 to 0 or 0 to 1 is tolerable. However, the radiation-hardened-by-design 10 T SRAM cell (RHBD-10 T) [15], whose structure is shown in Figure 5a, is robust for both 1 to 0 and 0 to 1 SEU. Compared to Quatro-10 T, the two nFETs for driving the C and D nodes--N2 and N4 in Figure 2--are replaced by pFETs of P5 and P6. This change means that RHBD-10 T is tolerant for both 0 to 1 and 1 to 0 SEU. Figure 4: Schematic of (**a**) PS-10 T, (**b**) NS-10 T, and (**c**) RHD-12 T SRAM cell. Figure 5: Schematic of (**a**) RHBD-10 T, (**b**) RHBD-14 T, and (**c**) RHPD-12 T SRAM cell. For example, when the datum \"1\" is stored for RHBD-10 T, Q = S1 = VDD, and QN = S0 = 0 V. In this situation, 0 to 1 upset can occur for the QN of RHBD-10 T. This turns on N2, which lowers Q temporarily. However, P4 is kept on, which pulls Q back up to VDD, leading to QN being lowered back to 0 V. This means that 0 to 1 upset to Q or QN can be recovered. The 1 to 0 upset can also occur at the Q or QN node. For example, when the datum \"1\" is stored, Q, which is initially VDD, can be lowered due to 1 to 0 SEU. Then, P6 is unintentionally turned on to lower S1. However, the lowering of S1 is limited for two reasons: P1, which is sized larger than P6, is turned on to keep S1 high, and P6, which is pFET, can only deliver a weak \"0\" to S1. Hence, S1 will remain high and P2 stays off. Thus, the voltage of S0 is unchanged as 0 V to keep P4 turned on. Finally, the turned-on P4 flips Q back to its initial voltage, VDD, which means that 1 to 0 SEU can be recovered. For the S0 and S1 nodes, 1 to 0 SEU cannot occur because there are no nFET diffusions (i.e., drains or sources) connected to the S0 and S1 nodes, but there are only pFET diffusions. Thus, the S0 or S1 nodes only suffer from 0 to 1, which does not turn on any transistors. Consequently, although S0 or S1 is unintentionally raised from 0 to 1 by SEU, it is lowered back by turning on P6 or P5, respectively. Even with this good tolerance for all types of single node upset, the critical problem of RHBD-10 T is the weak write ability. For example, when datum \"0\" is supposed to be written for the datum \"1\" stored cell, Q should be lowered to 0 V by N4, which transfers BL = 0 V. To guarantee the lowering of Q, P4 should be turned off by raising S0, while the raising of S0 should be performed by turning on P2. However, turning on P2 requires the lowering of S1, which is highly challenging for RHBD-10 T. This is because S1 should be pulled down by pFET P6, not by nFET. Thus, the write failure probability of RHBD-10 T is greatly increased in low-voltage or high-frequency applications. To mitigate the write failure problem of RHBD-10 T, RHBD-14 T is proposed in [16], which is shown in Figure 5b. The most pronounced change is that N3 and N4 are added to enhance the write ability. This approach is similar to the way in which WE-Quatro-12 T resolves the write ability problem of Quatro-10 T. When the node A should be pulled down, P5 and P7 are more easily turned off by the raised D because the node C is directly pulled down by N3. In addition, RHBD-14 T also employs the stacked configuration of pFETs to drive the nodes A or B--P5--P7 or P6--P8, respectively--to enhance the error resilience through the charge-sharing effect [16]. However, unlike RHBD-10 T, which has complete tolerance for SEU, the nodes C and D of RHBD-14 T are not tolerant for 1 to 0 SEU. For example, when the datum \"1\" is stored, A = C = VDD, and B = D = 0 V, and the node C can be lowered by SEU, leading to the raising of D by the turned-on P3. The node B is also raised by the turned-on P6 and P8, so the node A is lowered by N4. Hence, P1 is turned on, driving the node C to be low.