## 5 Evaluation and Analysis
### Experimental Setup  
As shown in Figures 10a and 11, the hardware platform consists of a daughter board and a core board. The core board is built based on Xilinx Zynq on-chip programmable SoC architecture [21], which is equipped with dual hardware ARM Cortex A9 processors running at 800 MHz, 1 GB DDR3 RAM. The daughter board supports up to eight NAND flash packages with the sockets. In this evaluation, we used 64 Gb Micron 29F64 GCBAAA NAND flash memory chips. The configuration of this MLC NAND flash is shown in Table 2.  
All of the firmware were implemented in the Zynq SoC. As shown in Figure 9, the Zynq SoC resource is comprised of two parts: the processing system and the programmable logic. The processing system has dual ARM cores and other peripheral controllers, such as USB 2.0 interface controller and a DDR3 controller. The NAND flash controller was implemented in the programmable logic, which is a standard Xilinx 7 series FPGA. The programmable logic connects to the AMBA interconnect through 32-bit high-speed GP AXI port with a bandwidth of up to 1 GB/s. We wrapped the NAND flash controller with one AXI streaming interface which can achieve the maximum bandwidth of the AXI interface. One AXI like slave interface was used to operate the registers of the NAND flash controller, making it possible to take full advantage of the bandwidth of the high-speed High Performance (HP) AXI port of Zynq. \begin{table}
\begin{tabular}{c c c} \hline \multicolumn{2}{c}{**Configuration**} \\ \hline \multirow{4}{*}{Organization} & Page Size & \(8192+448\) bytes \\  & Block Size & 256 pages \\  & Plane Size & 2 planes \\  & Device Size & 4096 blocks \\ \hline \multirow{4}{*}{Performance} & Read Page & 75 us (MAX) \\  & Program Page & 1300 us (TYP) \\ \cline{1-1}  & Erase Block & 3.8 ms (TYP) \\ \hline \multirow{2}{*}{Reliability} & Data Retention & JESD47G compliant \\  & Endurance & 3000 P/E cycles \\ \hline \end{tabular}
\end{table} 
Table 2: Configuration of the Micron 29F64 GCBAAA NAND flash memoryDue to the limited bandwidth of the USB 2.0 interface, we also designed a hardware NAND flash timer to precisely monitor the response time of NAND flash memory. This hardware NAND flash timer can reach a resolution of 10 ns, which is accurate enough for our time-related experiments. Asymmetric Programming was implemented in the processing system of Xilinx Zynq. To evaluate Asymmetric Programming, we adopted the NTFS file system on the host computer and connected our hardware platform with the USB interface. To evaluate the efficiency of Asymmetric Programming, we focused on enhancing the reliability of the metadata in the NTFS file system. The size of the NTFS allocation unit size is configured as 8192 bytes and the original metadata were allocated to the first 1024 logical pages (_i.e._, #LPN 0 to #LPN 1023). Pure page-level FTL was implemented as a thread in the FreeRTOS which is widely used free real time operating system and ran at the processing system of the hardware platform, which is equipped with dual ARM cores. We maintained the mapping table of the logical page number (LPN) and physical page number (PPN), and the other important data structures (e.g., bad block information and a shared pages mapping table) in the RAM (DDR3). The capacity of DDR3 of our hardware platform is 1 GB, which is big enough to keep these data structures. We modified the widely used greedy policy [38] in the garbage collection process and made the metric of the P/E cycles and the metric of the number of valid pages in the block both have 50% weight to find the victim block. Thus, the wear leveling was also very effective in our design. An additional system monitor module was also added into the FTL, which can record all of the flash operations (e.g., the number of read, program and erase operations, the overall request number and the number of the valid page copies in the garbage collection process).