# High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA
## 1 Introduction  
Typically, a digital device is designed and represented by an operational unit (datapath) and a control unit (controller). As a rule, these blocks are designed separately. The datapath is based on a set of standard functional units (registers, buses, multiplexers, etc.). The controller is implemented as a finite state machine (FSM). The ASMD-FSMD method for creating digital devices involves describing the operation of the device as a diagram of an algorithmic state machine with datapath (ASMD) and coding the project in Verilog HDL as a finite state machine with datapath (FSMD). Due to their clearness, algorithmic state machines (ASMs) are widely used to represent FSM behavior. The ASMs were first proposed in [1] as an alternative to automata graphs. In [2], it was proposed to use the ASM to describe the behavior of a control unit and operations performed in the datapath. Such ASM was called an ASMD. Recently, ASMD charts have been increasingly used in projects implemented in field programmable logic devices (FPGA): for the implementation of industrial control systems [3], to implement the asin function using the CORDIC (coordinate rotation digital computer) algorithm [4]; in the hardware implementation of the cryptographic algorithm AES (Advanced Encryption Standard) [5]; when designing a universal asynchronous receiver-transmitter (UART) [6]; in the hardware implementation of high-speed speech classifiers [7]; when designing a memory controller with high performance and low power consumption [8], etc. In [9], it is proposed to combine the datapath and controller and represent them as a finite state machine with a datapath (FSMD). The FSMDs for synchronous and asynchronous projects are given in [10]. FSMDs are widely used in high-level synthesis: in theequivalence test method based on value propagation [11], for checking the correctness of translation of C/C++ descriptions into a register transfers level (RTL) [12], to solve the problem of global elimination of common subexpressions [13], etc. The ASMD-FSMD technique for designing digital devices was first presented in [14]. In the ASMD-FSMD technique, it is proposed to describe the project code in Verilog HDL (hardware description language) directly according to the ASMD chart in the form of FSMD. A comparison of the ASMD-FSMD technique with the traditional approach in the case of using the Mealy FSM and the Moore FSM as a control unit is given in [15]. In [16], the ASMD-FSMD technique for designing digital signal processing devices is considered. The paper [17] presents the application of ASMD-FSMD methodology to the design of embedded processors on FPGA. The main advantage of the ASMD-FSMD technique is a significant reduction of design time (5-7 times). In addition, the use of the ASMD-FSMD technique, as compared to the traditional approach, allows, in most cases, the reduction of the implementation cost and increase in the speed of the devices. Increasing the performance of digital devices and systems is always a topical problem. High performance is important in the design of the following devices and systems: adders [18; 19], multipliers [20; 21], frequency synthesizers [22], digital FIR filters [23; 24], pipelines [25], accelerators [26], a datapath [27], memory access controllers [28; 29], encoders/decoders for communication systems [30], programmable logic controllers [31], encryption systems [32], convolutional neural networks [33], finite state machines [34; 35] as well as in high-level synthesis of digital systems [36; 37]. It is also noticed in [38] that even slight variations in the description of devices using hardware description language (HDL) can result in notably distinct hardware implementations, affecting the final area usage, speed, and power consumption. The proposed paper addresses the problem of increasing the performance of digital devices by applying the ASMD-FSMD technique. The main idea lies in the possibility of performing several operations on the same variable in one Verilog HDL procedural block.