## 5 Experimental Results and Discussion
### Analysis of the Estimated Area and Time Complexities  
Table 1 provides the analytical formulas for both the hardware resource area and execution time complexities for the proposed structure, as well as the compared ones [45; 50; 60; 61]. The hardware resource area was evaluated in terms of the counts of the logic gates/components (tristate buffers, 2-input AND gate, 2-input XOR gate, 1 bit 2-input multiplexers, and flip-flops). In contrast, the execution time complexity was evaluated in terms of the latency and Critical Path Delay (CPD). We notice from Table 1 that the formulas of the counted gates/components of the multiplier structures of Pan [45] and Xie [50] are almost of order \(\mathcal{O}(nk)\), while being of order \(\mathcal{O}(k^{2})\), except for some gates/components of the proposed multiplier, in the case of the other multiplier structures. Therefore, the multiplier structures of Pan [45] and Xie [50] should have a higher area complexity over the other compared designs, including the proposed one. By further investigation of the gate count formulas of the proposed design and the designs of [PERSON] [60] and [PERSON] [61], we notice that the proposed design has a higher number of tristate buffers, AND gates, XOR gates, and MUXes. On the other hand, it has a lower number of flip-flops compared to them. The flip-flops formula of the proposed design is of order \(\mathcal{O}(k\lceil n/k\rceil)\), while it is of order \(\mathcal{O}(k^{2})\) in the case of the designs of [PERSON] [60] and [PERSON] [61]. Therefore, for large values of \(k\), the number of flip-flops of the proposed design will significantly decrease compared to the other designs. Based on the standard CMOS libraries' data, the area of the flip-flops, for most of the layout styles, is significantly higher than the area of the other basic gates. Thus, the significant reduction in the number of flip-flops in the design structure will lead to a considerable decrease in the design's overall area. The value of \(k\) at which the proposed design area outperforms the other design areas mainly depends on the amount of the field size \(n\). For the recommend field size of \(n=409\), the word size of \(k=32\) leads to a significant decrease in the number of flip-flops of the proposed design and hence compensates for the increase in the area of the other gate counts. Further, it exceeds that by reducing the total area of the proposed design over the compared designs as proven by the real results in Table 2. Compared to the other designs, the proposed design performs both multiplication and squaring operations concurrently, while the other designs perform both operations in sequence; hence, reducing the area of the proposed design, for large word sizes, over that of the different designs is a notable achievement. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Design** & **Tristate** & **AND** & **XOR** & **MUXes** & **Flip-Flops** & **Latency** & **CPD** \\ \hline Xie [50] & 0 & \(2 nk\) & \(2 nk+6n-6\frac{k}{2}+6\) & 0 & \(4 nk+4n+2k\) & \(2\lceil n/k\rceil+2\lceil\log_{2}k\rceil\) & \(2T_{X}\) \\ \hline [PERSON] [45] & 0 & \(n\sqrt{n}\) & \(\sqrt{nk}(2+n)+k\) & 0 & \(7n+n(\lceil\log n\rceil)+k+3\) & \(2\lceil\sqrt{n/k}\rceil\) & \(T_{A}+(\lceil\log_{2}k\rceil+1)T_{X}\) \\ \hline [PERSON] [60] & 0 & \(k^{2}\) & \(k^{2}+4-5k+1\)\({}^{(1)}\) & 0 & \(2k^{2}+2k(\lceil n/k\rceil)+4k+1\) & \(6k\lceil n/k\rceil^{2}\) & \(T_{A}+2T_{X}\) \\ \hline [PERSON] [61] & 0 & \(k^{2}+k\) & \(k^{2}+2k\) & \(2k^{(2)}\) & \(2k^{2}+3k(\lceil n/k\rceil)+2k\) & \(k+\lceil n/k\rceil^{2}+\lceil n/k\rceil\) & \(T_{A}+T_{X}\) \\ \hline Proposed & \(6k+2\) & \(6k^{2}+4k+2\) & \(6k^{2}+4k\) & \(3k+2\) & \((7k+2)(\lceil n/k\rceil)-4(k+1)\) & \((\lceil d/k\rceil+1)\lceil n/k\rceil\) & \(\lceil\log_{2}(\frac{k}{2})\rceil(T_{A}+2T_{X})\) \\ \hline \hline \end{tabular} (1) Area of the 3-input XOR gate as a \(1.5\times\)2-input XOR gate; (2) the multiplier of [61] uses switches that have the same transistor count as the 2-input MUX.  
\end{table}