## 3 Results  
The proposed TDC was synthesized, implemented, and generated bitstream using Xilinx Vivado 2018.3, implemented on the ZYNQ-7020 FPGA (xc/z020 clg400-2) as Figure 7 shows. The controllable time intervals between channel 1 and channel 2 were generated by utilizing the IDELAYCTRL and IDELAY2 primitive. Owing to the two signals generated inside the ZYNQ-7020, measurement errors were minimized. The performances of the DNL, the INL, and the precision of the TDC and sample rate are evaluated in this section. Subsequently, the code density test was performed with 1,024,000 hit signals, which was clear from the histogram that the delay elements were not uniform (Figure 8a). The bin width of some elements was almost zero, whereas others were very large (even close to 90 ps), but most were below 40 ps. However, the bin width is more uniform after bin-by-bin calibration, with the max value of bin width of 46 ps, and with many around 17 ps as shown in Figure 8b. Only 165 elements were valid; therefore, 165 elements correspond to a clock cycle. Therefore, the least significant bit (LSB) = 2.857 ns/165 = 17.4 ps. Figure 8: Measured TDC bin widths: (**a**) before bin-by-bin calibration; (**b**) after bin-by-bin calibration. Figure 7: Experimental setup of the proposed FPGA-TDC measure system. The DNL reached \([-0.97,4.12]\) LSB before calibration, and reached \([-0.90,1.67]\) LSB after bin-by-bin calibration (see Figure 9a). The INL reached \([-2.45,9.54]\) LSB before calibration, and reached \([-1.90,3.31]\) LSB after bin-by-bin calibration (see Figure 9b). To further evaluate the performance of the TDC precision, the FPGA is used for testing standard deviation of the repeated 102,400 measurements. Figure 10a shows that the precision is 58 ps before bin-by-bin calibration when choosing the time interval of 0 ns. The precision is 18 ps after calibration when choosing the time interval of 0 ns, as shown in Figure 10b. Given the different time intervals ranging from 0 to 4.8 ns, the precision is below 19 ps, as shown in Figure 11.  
Figure 10: Measurement value of time interval (**a**) before calibration; (**b**) after calibration. Figure 9: (**a**) Comparison of the DNL before and after calibration; (**b**) comparison of the INL before and after calibration. Figure 12 shows the change of frequency count with temperature. It can be seen that the frequency count value decreases linearly with the increase of temperature, about 4 \({}^{\circ}\)C. In order to estimate the change of RMS precision with temperature, the TDC online temperature compensation circuit is tested from 30 \({}^{\circ}\)C to 70 \({}^{\circ}\)C, as shown in Figure 13. Figure 13 shows that the TDC RMS precision without calibration increases linearly with the increase of temperature (about 0.6 ps/\({}^{\circ}\)C), whereas the TDC with calibration circuit remains below 19 ps. Figure 11: RMS precision of difference time intervals. Figure 12: Dependence of ring oscillator frequencies on temperature. Figure 13: The TDC RMS precision under different temperatures with and without temperature calibration. Dead time is also an important parameter influencing the sample rate. Different frequency signals entered into the TDC for testing the dead time. The precision is greatly reduced once the frequency is greater than 170 MHz as shown in Figure 14. The safest time interval is 5.882 ns, meaning the dead time is less than 3 clock cycles. More than one clock cycle is utilized to propagate the signal along the delay line, and then another clock cycle is used to sample the fine count by the D flip-flops. Table 3 shows the timing of the TDC system. These data are obtained from the implementation timing report. The worst negative slack of setup is 0.348 ns and the worst negative slack of hold is 0.068 ns. The slack of both the hold and setup is positive, which means that the TDC meets the timing requirements. Table 4 shows the resource utilization of the TDC system. These data are obtained from the implementation utilization report.