# A 4.1 GHz-9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer
## 3 Measurement Results  
The division ratio of the MMD is selected from 101 to 164. The duty cycle of the output signal of MMD is also specially designed by adjusting counter P and counter S. Counter P can count from 23 to 38 while counter S can count from 9 to 15, which are controlled by a six-bit encoder, and it is integrated in the chip. A \(\Sigma-\Delta\) modulator is used in the chip for providing a division ratio of MMD, and it can also be used for fraction division in the PLL, it is controlled by a serial peripheral interface (SPI), which provides a division ratio of eight-bit integer and 24-bit decimal. Fabricated in TSMC 90 nm CMOS technology, the chip photo of MMD and test structure is shown in Figures 9 and 10. It occupies an area of 0.1063 mm\({}^{2}\), and the core MMD part area is 0.0091 mm\({}^{2}\). The power source of MMD and SPI is separated in order to avoid the noise from the digital modules. The power is provided by the external LDO chip. The MMD designed in the paper has been used in a Ka band fractional-N PLL and the PLL has been fabricated and measured. Agilent E8257D signal generator provides input signal of the MMD. Keysight N9030B signal analyzer is used to measure phase noise of PLL. The measured sensitivity curve of different division ratio is shown in Figure 11a. Working range has a little difference with different division ratio. It can be seen from the figure that it can work with a common operating frequency ranges from 4.1 GHz to 9.2 GHz as the input power is 0 dBm. The measured power consumption with a 9.5 GHz input signal at a division ratio of 164 is 13.8 mW, which contains the power consumption of \(\Sigma-\Delta\) modulator. \(\Sigma-\Delta\) modulator consumes most of power in the whole system. Simulation result of power consumption of MMD core is shown in Figure 11b. The simulated power efficiency of the MMD is nearly a constant. The simulated power consumption and power efficiency of MMD with 9.5 GHz input and a division ratio of 164 is 2.88 mW and 3.1 GHz/mW. In the meanwhile, the simulated power consumption of the whole system is 13.22 mW. The simulated result has a similar result compared with the measured result. The simulated result of the power consumption of the MMD core is convincible. The chip photo of the PLL of the architecture shown in Figure 1 with the designed MMD is presented in Figure 12. The amount of prescaler N is two. The prescalers provide a constant division ratio of 4. Figure 13 and Table 2 shows the phase noise of different output frequency and different  
Figure 11: (**a**) Measured input sensitivity curve of MMD in different division ratio; (**b**) Simulated power and power efficiency of the proposed MMD. Figure 10: Test structure. Figure 9: (**a**) Die micrograph of MMD, including \(\Sigma-\Delta\) modulator and MMD core; (**b**) Die micrograph of MMD core. division ratios of the whole PLL system. The reference frequency of the PLL is 45 MHz. When PLL works at the frequency of 24.93 GHz, with a MMD division ratio of 138.5, phase noise at 1 MHz offset is \(-\)91.55 dBc/Hz. When the division ratio of MMD is an integer 139, the output frequency of PLL is 25.02 GHz, phase noise at 1 MHz offset is \(-\)97.14 dBc/Hz. It can be indicated that MMD can work well in the PLL systems. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Frequency Offset** & **Division Ratio = 138.5** & **Division Ratio = 139** \\ \hline
10 kHz & \(-\)77.82 dBc/Hz & \(-\)71.41 dBc/Hz \\
100 kHz & \(-\)78.87 dBc/Hz & \(-\)71.94 dBc/Hz \\
1 MHz & \(-\)91.05 dBc/Hz & \(-\)97.40 dBc/Hz \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Phase noise of PLL different division ratios. Figure 12: The die photograph of the PLL. Figure 13: (a) Phase noise of PLL as the division ratio = 138.5; (b) Phase noise of PLL as the division ratio = 139.