# A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier
## 2 Proposed Topology  
Due to its capability to allow almost rail-to-rail input and output swing, the Arbel cell (or differential inverter) is often used as a building block for low-voltage analog CMOS circuits. To further reduce the minimum supply voltage of the Arbel cell, the bias current generators can be removed and the common mode current can be set by controlling the body terminals of MOS transistors following the approach proposed in [20]. However, for supply voltages lower than 0.5 V, the limited swing of the control voltage at the body terminals reduces the effectiveness of the current setting loop. To overcome this limitation, we propose a body-driven fully differential inverter (Figure 1a) as input stage of the amplifier. We then exploit the gate terminals of the four MOS devices to set both the common mode current by means of a replica bias control loop, and the output common mode voltage through a common mode feed-forward (CMFF) approach. By using the gates as control terminals we are able to enhance the loop gain, thus requiring a smaller swing of the control voltages to guarantee proper operation of the bias control loop even at a very low supply voltage. A simple push-pull second stage (Figure 1b) is exploited to convert the differential output of the first stage to a single-ended one, providing further gain to compensate for the reduced gain of the first stage due to the use of the body transconductance. One output of the first stage is directly applied to the gate of the PMOS common-source device, whereas the other one is applied to a NMOS common-source followed by a current mirror, to provide the required dc reversal needed both for the dual path compensation strategy and to improve the CMRR. The bias current of the output stage is given by:  
\[I_{oQ}=M\big{(}I_{6}-I_{5}\big{)}, \tag{1}\]  
where \(\,\mathrm{M}\) is the ratio between the form factor \((W_{8}/L_{8})\) of transistor \(M_{8}\) and the form factor \((W_{7}/L_{7})\) of transistor \(M_{7}\). \(I_{oQ}\) is therefore determined by the current source \(M_{6}\), by the sizing of \(M_{5}\), and by the current mirror ratio \(\,\mathrm{M}\). This is also the maximum current that can be sinked by the stage, that thus presents a class-A behavior, whereas the maximum sourced current is limited only by the available excursion of the gate voltage of \(M_{9}\). The replica bias loop to set the common mode current of the first stage is shown in Figure 2. The reference current, set by transistor \(M_{b1}\), is applied to devices \(M_{b2}\)-\(M_{b3}\), that are a replica of the N-part of the input stage and are diode connected: The loop acts varying the gate voltage \(V_{B}\) to contrast variations of the input common mode and of device parameters. This bias voltage is applied to the gates of the NMOS transistors of the input stage, thus setting its bias current to a scaled replica of the reference current (scaling factor is given by the ratio of the form factors of the devices). The gate control voltage \(V_{A}\) is exploited to set the output common voltage of the first stage using a common mode feed-forward (CMFF) technique: In the left part of Figure 2, the reference current is mirrored through devices \(M_{b4}\)-\(M_{b5}\) and applied to \(M_{b6}\)-\(M_{b7}\) that are a replica of the P-part of the input stage and are diode connected. The gate voltage \(V_{A}\) is applied to the PMOS transistor of the input stage, thus forming a current mirror, and it can be shown (detailed analysis in the Appendix A) that the output common mode voltage of the first stage is set to \(V_{A}\). The proposed CMFF does not exploit any reference to set the value of the output common mode voltage of the input stage that is determined by the sizing of the devices. In fact, by looking at Figure 2, it is evident that \(V_{A}\) is equal to \((V_{DD}\)-\(|V_{GSb6}|)\), and therefore, the output common mode is set close to the analog ground for an appropriate sizing of \(|V_{GSb6}|\).