## 3 Results
### Comparison with State of the Art  
To demonstrate the performance advantages of our FPGA-based VGG16 and VGG19 implementations, we compare them with recent state-of-the-art FPGA-based DL models. Table 3 provides a detailed comparison of key metrics for FPGA implementations across \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Resource** & **Utilization** & **Available** & **Utilization \%** \\ \hline LUT & 38,418 & 70,560 & 54.5\% \\ FF & 58,831 & 141,120 & 41.7\% \\ BRAM & 126 & 216 & 58.3\% \\ DSP & 326 & 360 & 90.6\% \\ RAM (MB) & 162 & 2 GB & 8.1\% \\ \hline \hline \end{tabular}
\end{table} 
Table 2: FPGA resource utilization in the proposed design. various models including Vitis-AI and HDL. The works included in Table 3 were selected to provide a broad comparison of FPGA-based DL implementations across varying hardware configurations, models, and datasets to provide a broad overview of FPGA-based implementations, showcasing the versatility of FPGA acceleration across diverse experimental setups along with their pros and cons. Despite these differences, the results demonstrate the robustness of our FPGA implementation in balancing accuracy, latency, and resource utilization. Future efforts will focus on replicating experiments with newer models and datasets to further validate the generalizability and efficiency of our approach. In terms of inference latency, our VGG16 model achieves a processing time of 0.652 ms/frame, while VGG19 completes inference in 0.846 ms/frame. These results significantly outperform prior implementations, such as AlexNet (6.54 ms/frame) and VGG-S (11.18 ms/frame) reported in [22], as well as the 84-layer ResNet (5.2 ms/frame) in [21]. While lightweight architectures like LeNet in [22] achieve a lower latency of 0.386 ms/frame, this comes at the cost of significantly reduced accuracy, rendering them less suitable for precision-critical applications. Inference latency is directly proportional to image resolution, as higher resolutions require more computational resources for processing. Additionally, it is important to note that the models in [8] process images with a resolution of 224 \(\times\) 224, which is 49 times higher than the resolution used in other works in Table 3 (32 \(\times\) 32). This accounts for their remarkably higher inference latency compared to other works. Despite  
\({}^{1}\) Recognition precision. \end{table}
Table 3: Performance summary of the proposed design and comparison with the state of the art. this difference, the architectural efficiency of our FPGA implementation suggests that, if evaluated on similar high-resolution datasets, our models would still demonstrate superior performance in terms of latency and resource efficiency. This superiority is supported by the scalable design of our approach, which leverages parallel processing and optimized resource utilization on FPGA, making it adaptable to higher-resolution inputs. According to Table 3, both VGG16 and VGG19 models in our work surpass the accuracy of all models in [8; 22], underscoring the robustness and reliability of our implementations. While the custom 84-layer ResNet in [21] achieves a slightly higher recognition precision of 92.5%, this improvement comes at the cost of increased architectural complexity and resource demands, highlighting a clear trade-off between precision and scalability. Furthermore, the inference latency of the 84-layer ResNet is 7.97 times higher than our VGG16 implementation and 6.14 times higher than VGG19, demonstrating the significant latency advantage of our models. By delivering high accuracy with an efficient and straightforward implementation, our approach is particularly well-suited for scenarios where hardware resources are constrained, and low latency is critical. Resource utilization further underscores the efficiency of our approach.