# An S/C/X-Band 4-Bit Digital Step Attenuator MMIC with 0.25 \(\upmu\)m GaN HEMT Technology
## 2 Design of the GaN HEMT SPDT Switch  
The proposed 4-bit digital step attenuator topology is shown in Figure 2. The attenuator consists of SPDT switches at the input and the output ports, three double-pole double-throw (DPDT) interstage switches, and T-type resistive attenuation networks. The digital step attenuator is implemented with only passive devices. Therefore, the digital step attenuator can operate in both the transmitter and the receiver with nearly zero DC power consumption.  
Because the switch transistors are generally large in GaN technology, the large parasitic capacitances reduce the operating frequency bandwidth. Even though large switch transistors are used, the parasitic elements of the switch transistors can be nearly identical in each attenuation state due to the switched path topology. This results small phase variations being provided even at high attenuation states. Wideband operating bandwidth can be achieved in this topology. For the 4-bit digital step attenuator, the RF signal passes only five series transistors, and so the insertion loss and the chip size can be reduced considerably. There are two resistive attenuation networks of the T-type and \(\pi\)-type, as shown in Figure 3. In this design, a T-type resistive attenuator is used to reduce the ground  
Figure 1: Various attenuator topologies: (**a**) switch embedded T/\(\pi\)-type, and (**b**) switched path type.  
Figure 2: Schematic of the S/C/X-band GaN 4-bit digital step attenuator.  
effect, in which the single shunt resistor can be directly connected to the substrate ground though the substrate via a hole with minimal inductance. The resistance values of the T-type attenuators can be calculated with Equations (1)-(3). The series resistance (R\({}_{\text{SR}}\)) and parallel resistance (R\({}_{\text{SH}}\)) values of the T-type resistive networks for each attenuation state are summarized in Table 1.  
\[R_{\text{SR}}=Z_{0}\,\left(\frac{\text{K}-1}{\text{K}+1}\right) \tag{1}\]  
\[R_{\text{SH}}=Z_{0}\,\left(\frac{2\text{K}}{\text{K}^{2}-1}\right) \tag{2}\]  
\[\text{K}=\frac{\text{V}_{\text{I}}}{\text{V}_{\text{O}}}=10^{\text{dB}/20} \tag{3}\]  
As shown in Figure 4a, the series transistors (T1, T2) are used in the SPDT switch for switching the attenuation states, and the shunt transistors (T3, T4) are used to improve switch isolation. Only four cross-connected series transistors (T1-T4) are used in the DPDT switch in Figure 4b. The shunt transistors for the isolation are not included in the DPDT switch in order to reduce parasitic shunt capacitances, since small-size switch transistors are not available in commercial GaN HEMT technology and a moderate isolation characteristic can be achieved with only series switches at less than 12 GHz. The series inductors of L\({}_{1}\) and L\({}_{2}\) are implemented to enhance the input- and output-matching performance. A simulated insertion loss of less than 1.3 dB is achieved and the isolation is greater than 15 dB at 12 GHz.  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Attenuation (dB)** & **R\({}_{\text{SR}}\) (\(\Omega\))** & **R\({}_{\text{SH}}\) (\(\Omega\))** \\ \hline
2 & 5 & 215 \\
4 & 11 & 104 \\
8 & 21 & 47 \\
16 & 36 & 16 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Component values of T-type resistive attenuators.  
Figure 3: Schematic of (**a**) the T-type attenuator and (**b**) the \(\pi\)-type attenuator.  
Since only two interconnecting metal layers are available in the GaN HEMT process, the top, thick metal layer is used in the inductors and the microstrip transmission lines for a high Q-factor, and the bottom, thin metal layer is used for the digital control lines. A 2.5D electromagnetic simulation was performed carefully to design the matching inductors and interconnection microstrip transmission lines.