# An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System
## 1 Introduction
Enhancing the real-time imaging processing capability of massive data on satellite has become a technical requirement for spaceborne SAR due to the constrained resource environment on satellite. In the current SAR imaging system research, efficient data exchange and on-chip system architecture design are two of the key technologies. Various traditional SAR imaging algorithms regularly call for several exchange operations. Additionally, due to the limited storage bandwidth caused by the low exchange efficiency of massive data in traditional methods, computation and storage are not matched, which wastes computing power and influences the performance of real-time processing. In recent years, researchers have proposed a variety of methods to solve the problem of the limited storage access bandwidth of two-dimensional matrices, and implemented them on FPGA. A matrix block linear mapping was applied by [PERSON] et al. [33] to improve data access bandwidth; however, the method has a low utilization of eight buffer RAMs and an imbalanced range and azimuth access efficiency. [PERSON] et al. [34] balanced the range and azimuth accesses efficiency using a matrix block cross-mapping method. [PERSON] et al. [35] used a dual-channel pipeline design to implement balanced two-dimensional access efficiency, higher buffer RAM utilization, and improved data exchange efficiency. This paper presents a potent method for the storage and exchange of synthetic aperture radar (SAR) imaging system data predicated on a superscalar pipeline. This approach addresses the inefficiencies in massive data exchange and limitations in storage access bandwidth that exist between the FPGA computing engine and DDR3 SDRAM. An examination of the Chirp scaling (CS) algorithm elucidated that the row activation and pre-charging of the DDR3 SDRAM memory chip posed the most significant challenges to storage access efficiency due to the two-dimensional matrix transposition operations. Consequently, we propose a three-dimensional cross-mapping approach grounded on the equal division of a sub-matrix with dual-channel DDR3. Further, an analysis of system pipeline processing led to the proposal of an efficient on-chip data exchange solution tailored for SAR imaging processors equipped with a superscalar pipeline buffer. Additionally, we suggest a hardware architecture for an on-chip data exchange engine to enhance hardware efficiency for real-time processing. The primary contributions of this study are as follows:* Through modeling and calculating the time parameters impacting DDR3 access efficiency, such as DDR3 row activation and pre-charging, a three-dimensional cross-mapping method is proposed premised on the equal division of sub-matrix with dual-channel DDR3. While maintaining the three-dimensional cross-mapping method, this approach maximizes the parallelism of two off-chip DDR3 to amplify the range and azimuth data storage access bandwidth, thereby achieving balance in range and azimuth data access. * By analyzing and studying traditional pipeline resources, a superscalar pipeline buffer is proposed as a method for efficient on-chip data exchange for SAR imaging processors. This method subdivides pipeline resources further, diminishes the idle ratio, optimizes spatial parallelism, and leverages the advantages of dual-channel DDR3 storage, thereby markedly augmenting the efficiency of data exchange. * Based on the aforementioned solution, we propose a hardware architecture for an on-chip efficient data exchange engine. This architecture employs a modular register addressing control mode and synthesizes a superscalar pipeline buffer module with a dual-channel DDR3 access control module, thereby forming a data exchange engine with configurable granularity and state monitoring capabilities. * We verified the proposed hardware architecture in a \"CPU + FPGA\" heterogeneous SAR imaging system, and evaluated the data bandwidth.