# Warpage Behavior on Silicon Semiconductor Device:
## 1 Introduction  
Formation of copper thick film on silicon substrate is desirable in the semiconductor industry because of its excellent electrical and thermal conductivity [1, 2]. Compared to other materials, such as aluminum, these properties allow us, respectively, to reduce the Joule effect and help the efficient dissipation of heat generated during operation. Furthermore, Cu metallization is better than aluminum in terms of resistance to electromigration and stress voiding phenomena [3, 4]. The main technique to produce thick copper film on silicon substrate is electrochemical deposition (ECD), which is a highly efficient wet process for depositing a uniform layer of metal (like copper) on a semiconductor wafer [5, 6]. Furthermore, Cu front metal is very attractive for integrated circuit (IC) manufacturing because it enables high-reliable Cu-Cu wire bonding solution [7, 8, 9, 10]. The integration of Cu into ICs is still a technical challenge due to the induced stress in back end of line structures [11, 12] and due to the severe wafer warpage induced by Cu annealing, which affects the accuracy of the subsequent manufacturing processes, such as the wafer handle and the adsorption of vacuum suction cup, having also a negative impact on device reliability. Wafer warpage caused by thick Cu layer is mostly due to plastic deformation during the annealing [13], which is a thermal process aimed to make softer Cu material, increasing and then stabilizing the Cu grains dimension. Stabilizing metal grain size, annealing permits to avoid electromigration issues in interconnect reliability, e.g., during reliability application related test [14, 15, 16, 17] or passive thermal cycles [18, 19]. It seems to miss in literature a detailed experimental warpage analysis for thick Cu layer: available data refer about maximum 5 \(\upmu\)m thick Cu metal [3, 20]. As later discussed, some analytical models are developed to calculate stress and warpage due to thermal budget. However, current approaches cannotaccount material no-linearity and they assume only simple geometries, such as wafer or rectangular beam. A dedicated numeric model should be useful to overcome the above mentioned limitations.  
The scope of this work is to characterize experimentally the warpage, which is intended as the maximum deflection, induced by 20 \(\upmu\)m thick Cu film on a rectangular wafer slice, considering two different annealing profiles. The considered sample and tests are described in Section 2 and the working principle of warpage measurements are reported in Section 3.1. Results in terms of warpage are presented in Section 3.2 and dedicated physical analysis is employed and presented in Section 3.3 to clarify the phenomenology behind the observed warpage. Two numerical approaches [21,22] to calculate warpage due to a thermal input are resumed in Section 4.1. A Finite Element Model (FEM) is developed to predict the stress-curvature relation inside the elastic regime. Numerical outcomes are compared with the results of Stoney and Timoshenko equations as reported in Section 4.2. The final target of this paper is to correlate the warpage behavior of silicon devices with thick (20 \(\upmu\)m) ECD copper film with physical modification induced by thermal treatment, such as annealing, and to find out a reliable numerical model to predict warpage. An analysis on micro-structure evolution due temperature evolution in the range between 150 and 250 \(\lx@math@degree\)C permits to understand if it is possible optimize manufacturing process to reduce the residual warpage.