## 3 Results and Discussion
### Model Validation Using TCAD Data  
We performed 3D self-consistent electrothermal simulations using the commercial TCAD simulator from Synopsys to analyze the degradation characteristics of the 14 nm  
Figure 11: Model predictions versus experimental data (not fitted). (**a**) \(V_{t}\_shift\) versus \(V_{g}-V_{t}\) in different energy regions; (**b**) \(V_{t}\_shift\) versus stress time under different temperatures. Figure 10: (**a**) Fitted curves of \(\Delta G_{m}\)-stress time under different substrate voltages; (**b**) fitted curves of \(\Delta I_{d}\)-stress time under different widths. \begin{table}
\begin{tabular}{c c c} \hline
**Parameters** & **SVE Region** & **MVE Region** \\ \hline n & 0.38324 & 0.3422 \\ c (s\({}^{-1}\)) & 0.02505 & 0.1344 \\ \(n_{1}\) & 2.99 & 11.907 \\ \(n_{2}\) & 1.889 & 2.082 \\ \(H_{1}\) (V) & 7.545 & 2.38693 \\ \(H_{2}\) (V) & 0.6403 & 3.76661 \\ \(E_{d}\) (eV) & 0.076 & 0.076 \\ \(\alpha_{i}\) & \(1.68\pm\delta\) & \(1.68\pm\delta\) \\ \(a_{n}\) & \(3.65\pm\delta\) & \(3.65\pm\delta\) \\ \(A\) (m\({}^{a_{n}}\)V\({}^{-n_{1}}\)s\({}^{-n}\)) & \(2.37\times 10^{-24}\pm\delta\) & \(2.88\times 10^{-27}\pm\delta\) \\ \(B\) (V\({}^{-n_{2}}\)m\({}^{a_{n}}\)) & \(1.9\times 10^{-27}\pm\delta\) & \(1.28\times 10^{-26}\pm\delta\) \\ \hline \end{tabular}
\end{table} 
Table 3: Model parameters fitted using data from [16; 17]. node bulk device under HC stress and compared them with the simulation results using the compact model mentioned before. The nFinFET TCAD model was carefully calibrated to reproduce the I-V characteristics extracted from the reported Intel 14 nm FinFET measurement data [26]. Figure 12a shows the 3D structure of the device, while Figure 12b gives the \(I_{DS}-V_{GS}\) curves after calibration. The device parameters are the same as those given in Table 1, except that the source/drain length has been shortened. The device structure was created using the TCAD Silvaco Device Editor (SDE) tool (Silvaco, Santa Clara, CA, USA). A Fermi model was used to describe the carrier distribution in the heavily doped region of the device during the electrical calibration simulations. The high-field-saturation model was calibrated to describe the mobility degradation, while the QuantumPotential model took into account the quantum confinement effects due to the small device size. The simulations also included a hydrodynamic model as well as a thermodynamic model, which were used in the thermal simulation to study the SHE in bulk FinFETs. And trap model containing a lucky electron model as a gate current model was used for HCI stress simulation. We simulated HCI degradation with and without self-heating under a stress voltage of 2 V using TCAD. The threshold voltage of the device and the carrier effective mobility were extracted. The threshold voltage was extracted using the constant current method, and the carrier's effective mobility was obtained by integrally averaging the carrier mobility distribution inside the channel. Figure 13 shows the results with and without self-heating; the scatter points represent the TCAD simulation results, while the lines represent the predictions of the compact model, which is not fitted. The root-mean-square error between the model's prediction of threshold voltage degradation and the simulation results is 5.82% with self-heating and 16.7% without self-heating. Similarly, the root-mean-square error for the prediction of mobility is 4.44% with self-heating and 4.92% without self-heating. Meanwhile, the simulation results indicate that the threshold voltage degradation due to HCI rises by 46.3% in the case of coupled self-heating, while the mobility drops by 12.42%. As a consequence, it is very necessary to consider the self-heating effect in HCI degradation. Figure 12: **(a)** The 3-D FinFET device structure; **(b)**\(I_{DS}-V_{GS}\) calibration between the TCAD modeling and measurement data from the Intel 14 nm FinFET.