## 4 Experimental Results and Hardware Implementation  
We proposed three equations for eADP-efficient antilogarithmic converters based on fractional-bit compensation schemes under different specifications and requirements for DSP applications. In general, the larger the approximation and maximum percentage error, the less the hardware area cost and delay time. Herein, we first sort the similar maximum percentage errors of antilogarithmic converters reported in the literature as one group and then compare their eADP efficiencies. Next, we compare the performances of the three equations as three groups with those of the methods in the literature. The percentage conversion errors of case 1, case 2, and case 3 are obtained using MATLAB and compared with those of the previous schemes. The maximum percentage conversion errors of case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Figure 6 compares case 1 with [PERSON] et al. 's two-region bit correction [13]. Figure 7 compares case 2 with [PERSON] and [PERSON]'s two-region shift-and-add method [5] and [PERSON] and [PERSON]'s 11-region constant compensation scheme [16]. Figure 8 compares case 3 with [PERSON] and [PERSON]'s  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{\(f_{-1}\)-\(f_{-5}\)} & \multicolumn{3}{c}{**Compensation Bit**} & \multirow{2}{*}{\(f_{-1}\)-\(f_{-5}\)} & \multicolumn{3}{c}{**Compensation Bit**} \\ \cline{2-2} \cline{6-9}  & \(\mathbf{2^{-4}}\) & \(\mathbf{2^{-5}}\) & \(\mathbf{2^{-6}}\) & \(\mathbf{2^{-7}}\) & & \(\mathbf{2^{-4}}\) & \(\mathbf{2^{-5}}\) & \(\mathbf{2^{-6}}\) & \(\mathbf{2^{  
six-region shift-and-add method [5], [PERSON] and [PERSON]'s two-region shift-and-add method [11], and [PERSON]'s 14-region constant compensation scheme [16]. Figures 6-8 clearly show that the three cases yield considerably lower percentage conversion errors than the previous methods. Figure 9 shows the approximated curve of case 3 compared to the accurate antilogarithmic curve; it is noted that the two-region equation of case 3 is extremely close to the accurate antilogarithmic curve. Comparisons of the results for VLSI hardware realization and maximum percentage conversion errors for cases 1, 2, and 3 are presented in Tables 9-11, respectively. The same hardware and software operation environments are used for all cases and reported methods. For hardware implementation, we used Verilog HDL and had the digital circuits created via VLSI by the Taiwan Semiconductor Manufacturing Company with 0.18 \(\upmu\)m CMOS technology. The percentage conversion error is simulated using MATLAB software. In Tables 9-11, ADP is defined as the product of hardware area and delay time, while eADP  
Figure 8: Comparison of the antilogarithmic percentage conversion errors of case 3 and [PERSON] and [PERSON]’s [5] 6-region shift-and-add, [PERSON] and [PERSON]’s [11] 2-region shift-and-add, and [PERSON] and [PERSON]’s [16] 14-region bit constant compensation schemes. Figure 9: Approximate curve of proposed case 3 compared to the accurate antilogarithmic curve. is defined as the product of the approximation's maximum percentage conversion error, hardware area, and delay time. The approximation's maximum percentage conversion error is defined as the sum of the absolute value of the positive maximum percentage error and the absolute value of the negative minimum percentage error. Tables 9-11 indicate that case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with the other methods. The antilogarithmic percentage conversion error, delay time, hardware area, and eADP savings of the proposed cases are superior to those of the other reported methods. It should be noted that [PERSON]'s law of logic circuits can be used to reduce the gate-count number for hardware realization in Equations (10)-(12).