## 4 A Survey on Cognitive Radio Implementation Research
### WARP platform from Rice Univ  
The WARP (Wireless Open-Access Research Platform) developed by CMC lab at Rice University is a scalable and configurable platform to develop, implement and test advanced wireless algorithms  
Figure 14: Orbit radio node.  
Figure 15: Software architecture of ORBIT testbed.  
for educational and research oriented applications at both physical layer and MAC layer. The platform architecture, depicted in Figure 16, consists of four key components: custom hardware, platform support packages, open-access repository and research applications; all together providing a reconfigurable wireless testbed [105, 106, 107].  
The hardware components include a FPGA motherboard and up to four peripheral daughterboards hosted by the FPGA board in its four daughterboard slots as Figure 17 shows. The Xilinx Virtex-II Pro FPGAs is the heart of the hardware and serves as the primary communication processor, the embedded PowerPC core in the Xilinx FPGA was programmed to implement a flexible medium access development framework, which enables researchers to develop network layer designs while abstracting away the physical layer. The four daughterboard slots on the WARP board can be used to build 4 multiple-input multiple-output (MIMO) system [105, 106, 107]. With the radio boards, the testbed may be used for wideband wireless communications in the 2.4 GHz/5 GHz ISM/UNII bands.  
Between multiple FPGA boards, the multi-gigabit transceivers (MGTs) built into the Xilinx FPGAs are utilized to provide high speed board-to-board connections which make the WARP platform scalable, each MGT provides a full duplex 3+ Gb/s connection between two FPGAs. The daughterboards can provide analog video capture, playback capabilities, six channels of fast analog I/O (2 A/D and 4 D/A). They can therefore enable the implementation of wireless algorithms in real-time at baseband frequencies, which decouples the processes of algorithmic and RF interface debugging [106].  
Figure 16: Architecture of the WARP platform.  
Figure 17: WARP custom hardware, including the Virtex-II Pro FPGA board and radio boards.  
For software development, the platform supports different levels of design flows from low level VHDL/Verilog RTL coding to system level MATLAB modeling. Xilinx ISE design tools are used to synthesize hand-coded HDL and map the designs to hardware. Xilinx System Generator, integrated in MATLAB Simulink, provides abstractions for building and debugging high performance DSP systems in MATLAB/Simulink using the Xilinx blockset. Moreover, Simulink hardware co-simulation that expedites the simulation and debugging steps is also supported for MAC and network layer design, the WARP platform supports C language based applications on the PowerPC while interfacing the physical layer implementations in the FPGA fabric [105, 106, 107]. Figure 18 shows how researchers design the various layers of a custom wireless network while using the platform interface tools to integrate different layer implementations.  
Rice university also held workshops to further expand the use of the WARP platform at Rice University as well as other universities and research centers. The online open-access repository [108] is the central archive for all source codes, models, platform support packages, application building blocks, research applications, design documents and hardware design files associated with WARP. The researchers can discuss problems and exchange ideas about different algorithmic and hardware implementations.