## 2 Materials and Methods
### Unipolar Pulser Generator Analysis
#### 2.6.2 Power Integrity Design  
Using the signal integrity (SI) analysis method resulted in signal lines on the PCB to ensure signal integrity. However, energy integrity was a major issue that needed to be considered, especially for high-speed PCB types. Power integrity (PI) analysis indicated that interference from the power supplies greatly influenced signals in the high-speed systems. The noise voltage caused by the transient current made the supplying power continuous and even affected the normal work of the high-speed system. At present, PI issues have two solutions: optimizing the layer stack structure of the PCB and placing decoupling capacitors on the PCB.  
In addition, we applied proper bypass capacitors and separation techniques to improve the overall power supply SI. A series of capacitors should be used to eliminate the effects of source voltage interference with the two main chips (FPGA and dsPIC33 EP64 GS508) in this design. Small decoupling capacitors with low current inductances could provide fast current to high-frequency converters. The average bypass capacitor could filter out noise, preventing them from entering the IC. Bulk capacitors continued to provide current after the high-frequency capacitors exhausted their energy storage. The application of these capacitors to the design is described in Figure 9.  
A good layer stack structure may be the best solution for most SI and electromagnetic compatibility (EMC) issues. Ground planes are an effective EMC shield, good image planes can be good return paths, and small loop areas reduce electromagnetic interference radiation. The closer the power plane is to the ground plane, the bigger the capacitance, and the lower the impedance, the better the reduction of switching noises.  
In this design, we used the eight-layer PCB with the stackup, as described in Figure 10. With this stackup, the impedance of the signal classes was calculated and matched with an impedance of 50 \(\Omega\). In this stackup, the third layer (high voltage) and the fifth layer (low voltage) separated. The layout of the source for the STHV800 chip had been optimized by us. The second layer (GND1, mainly ground for the dsPIC33 EP64 GS508, FPGA,... ), fourth layer (GND2, mainly ground for the low voltage of the STHV800) and seventh layer (GND3, mainly ground for the high voltage of the STHV) were the plane layers. We separated these layers to limit interference from the source.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Items** & **XC6 XLX9 PIN** & **STHV800 PIN** & **Length (Mil)** & **Width (Mil)** \\ \hline
1 & 8 & 28 & 1520 & 8 \\
2 & 10 & 27 & 1520 & 8 \\
3 & 12 & 26 & 1460 & 8 \\
4 & 15 & 25 & 1460 & 8 \\
5 & 17 & 24 & 1400 & 8 \\
6 & 22 & 23 & 1400 & 8 \\
7 & 24 & 22 & 1340 & 8 \\
8 & 27 & 21 & 1340 & 8 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Length and width of the pulse signal between the field programmable gate array (FPGA) and the pulse component.  
Figure 9: _Cont._The layout design of the decoupling capacitors for the two main chips (FPGA and STHV800) are presented in Figure 10b, and the impedance of the microstrips and striplines are shown in Figure 10c,d.  
Figure 10: (**a**) PCB stackup for the STHV800 layout; (**b**) PCB layout with the decoupling capacitor and signal integrity (SI) technique; (**c**) impedance with the microstrips; and (**d**) impedance with striplines.  
Figure 9: Design of the decoupling capacitor for the (**a**) dsPIC33 EP, (**b**) XC6 SLX9 and (**c**) STHV800.