## 2 Fabrication Process and Waveguide Performances  
### Fabrication Processes  
Over the last few years, our silicon photonics platform has become increasingly mature. High-performance optical components have been developed and repeatedly tested to build a complete device library [2] with reproducible performance. This Si platform is the starting point for the integration of the SiN layer. The process starts with 200 mm Silicon-on-Insulator (SOI) substrates with 300-nm-thick Si and buried oxide (BOX) thickness of 2 \(\upmu\)m. The Si process flow is designed to support various sets of devices using a multilevel etch defining silicon thicknesses of 50, 150 and 300 nm. A Deep Ultra Violet 193 nm lithography is used to pattern all three silicon etching levels providing an overlay control below 50 nm and definition of various shapes (isolated and arrayed lines and trenches) with critical dimensions as low as 120 nm (see Figure 1a). A Si\({}_{3}\)N\({}_{4}\) hard mask is used for the first Si level, ensuring low waveguide roughness leading to low optical propagation losses in silicon waveguides. To integrate an additional layer on top of the patterned Si, one needs to start with a flat oxide surface. Oxide encapsulation of patterned Si structures is therefore followed by Chemical Mechanical Polishing (CMP) to planarize the top oxide down to the Si\({}_{3}\)N\({}_{4}\) hard mask. The presence of dummy structures allows a high enough Si density for clear end point detection. This process is followed by another SiO\({}_{2}\) deposition. With a median value of 207 nm of SiO\({}_{2}\) on top of Si and a standard deviation of 4 nm over the 200 mm wafers, this process provides a flat surface with a very good uniformity of the interlayer thickness, which is important for hybrid devices such as Si-SiN grating couplers or Si-SiN transitions. Integrating a new material while staying compatible with a CMOS process imposes several challenges. In particular, a low thermal budget is necessary to prevent degradation of other components, in particular, active devices with doped regions. In addition, the new material should not induce further mechanical deflection of the wafer to maintain a low bow, compatible with the 200 mm facilities. Depending on the targeted applications, we developed two different silicon nitride integration processes, taking into account the aforementioned constraints: a low stress, low deposition temperature non-stoichiometric SiN in the O-band and a nearly stoichiometric Si\({}_{3}\)N\({}_{4}\) material with a low quantity of residual N-H bonds for lower absorption in the C-band. The former is used when preservation of the doping profile of active devices (p-n Si modulator and Ge photodiode) is the prime concern and is preferred for applications such as optical transceivers for datacom in the O-band where the material absorption is very low. The latter is used for applications in the C-band, where N-H bonds must be eliminated to minimize optical absorption. * SiNx for optical transceiver for Datacom in the O-band  
Figure 1: (**a**) Cross-section of the full Si-SiN platform based on SOI 300 nm (gray waveguides) and SiN (green waveguide), together with metallic heaters, PN modulator, Ge photodiode and metallic interconnection. The BOX is 2 \(\upmu\)m. (**b**) SEM cross-section view obtained by FIB cut of Si and SiN waveguides. Si is 300 nm thick, SiN is 600 nm thick. The interlayer SiO\({}_{2}\) thickness is 200 nm. To preserve the doping of implanted active devices, we developed a plasma-enhanced chemical vapor deposition (PECVD), non-stoichiometric, low-stress SiNx deposition process at 300 \({}^{\circ}\)C. The SiN film thickness is 600 nm (see Figure 1b), and its refractive index, measured by ellipsometry, is n\({}_{\text{SiNx}}\) = 1.88 at 1.31 \(\upmu\)m. This rather low value indicates the deposited film is not stoichiometric with a rather high fraction of nitrogen.