## 3 Measurement Results and Discussion
### On-Wafer Characterization  
First, small signal performance of the chip was evaluated by on-wafer measurements using a 2-port vector network analyzer (VNA). All measurements were performed with a supply voltage of 3.3 V, with the circuit drawing around 69 mA for a total DC power consumption of around 228 mW. The output power from the VNA was set to \(-40\) dBm to ensure linear operation at maximum gain. Figure 7a shows the measured forward S-parameters for each of the differential TIA outputs (\(S_{21}\) and \(S_{31}\)). In each case, the unused TIA output is DC blocked and terminated in a 50 \(\Omega\) load. The differential transimpedance response was obtained from the measured S-parameters, and is plotted in the figure together with the simulated response. For the simulated transimpedance, RC parasitic extraction of the amplifier core was combined with electromagnetic simulation of input and output structures and peaking inductors. Excellent agreement between measurement and simulation is observed. Lower and higher 3 dB cut-off frequencies (measured relative to the maximum transimpedance value of 68 dB\(\Omega\)) of 5 and 50 GHz, respectively, are obtained using a moving average (1 GHz wide) on the measured data. This was done in order to better illustrate the amplifier response towards the higher frequency end, where setup limitations lead to excess noise in the measurements. Figure 7b shows the behavior of the gain control functionality in the S-parameter response for one of the TIA outputs, where the possibility for gain reduction down to around 0 dB is demonstrated. Figure 6: Schematic representation for: (**a**) Gilbert-cell-based VGA with emitter degeneration and shunt inductive peaking; (**b**) CGA formed by a cascode gain stage with emitter degeneration and shunt inductive peaking. Figure 8a shows the simulated and measured group delay response. A moving average (2 GHz wide) was applied to the measurements to better illustrate the trend. The measured group delay variation closely follows the trend of the simulated response up to 35 GHz. Above this value, larger deviations are observed from the simulations. Figure 8b shows the amplitude and phase imbalance between the two TIA outputs. Good agreement is obtained for the phase imbalance up to 35 GHz. Above this frequency, the measured response also deviates from the simulation. This deviation from the simulated response in the phase measurements was mainly attributed to the limited accuracy of the setup, where excessive noise due the low input power used in the measurements can compromise the highly sensitive phase response. The amplitude imbalance remains within \(\pm 1\) dB up to 45 GHz. A 0.5 dB difference between the two outputs is observed already at low frequencies, which falls within the repeatability of the measurements, since the two outputs must be measured independently using a 2-port VNA. To evaluate the large signal performance, the 1 dB compression of the circuit was measured at 15 and 20 GHz. The probed circuit was fed from a signal generator, while the output power was monitored in a spectrum analyzer. Losses from cables and probes in the setup were calibrated out by probing of a thru standard from a calibration substrate. Figure 9 shows the resulting curves, where linear fits are provided for reference, together with markers identifying the 1 dB compression points. For both frequencies, the 1 dB compression is found at an input power of \(-30\) dBm, with a corresponding output power around \(-3\) dBm. In the figure, the simulated response is also provided. Slightly higher gain values are obtained in this case, since the circuit model for large signal simulation includes  
Figure 8: Small signal TIA measurements: (**a**) simulated and measured group delay response for each of the differential TIA outputs (ports 2 and 3); (**b**) amplitude and phase imbalance (deviation from out-of-phase condition) between the two TIA outputs.