# A 245 GHz Real-Time Wideband Wireless Communication Link with 30 Gbps Data Rate
## 3 Base-Band Module with 30 Gbps Data Rate  
The base-band module is the key component of the high-speed backhaul communication system. The structure of the base-band module in this work is shown in the dashed box of Figure 2. The digital base-band module is composed of two FPGAs, each capable of processing a 15 Gbps data rate. On the transmitter side, typical digital signal processing (DSP) modules include a low-density parity check (LDPC) encoder, modulation, and transmitter filter. With a 1.875 Gsps symbol rate and 2.5 Gsps sampling rate, sample rate conversion (SRC) with an up-sampling ratio of 4/3 is performed by the transmitter filter with root-raised-cosine (RRC) pulse shaping. Three symbols form a symbol group, each generating an RRC pulse and outputting four samples every three symbol intervals. On the receiver side, there is synchronization, channel estimation, the receiver filter, demodulation, and the LDPC decoder [21]. The receiver filter performs SRC, channel equalization, and I/Q mismatch compensation at the same time. After channel and I/Q mismatch estimation using the training sequence embedded in the transmission preamble, two equalizer impulse responses are constructed, with each being applied to the real part and imaginary part of the received signal samples, respectively, for I/Q mismatch compensation while SRC  
Figure 1: Configuration of the THZ wireless communication system. Figure 2: Structure of the proposed base-band module. with a down-sampling ratio of \({}^{3}/_{4}\) is implemented by outputting three equalized and I/Q mismatch compensated symbols every four sampling periods. Therefore, the overall implementation complexity is significantly reduced compared to conventional designs [22]. There is no feedback between the processing modules and each module does not require huge data storage. All modules are run by the parallel pipelined processing. Adopting this kind of simple structure, all modules can be implemented in real-time using affordable hardware. The base-band DSP platforms adopt Xilinx Virtex 7-690t FPGA devices [23]. The resource usage for all DSP modules is shown in Table 1, which shows that the usage rate of some typical cells is reasonable compared with the total resources and it is not difficult to meet the timing requirements for the high-frequency system clock (312 MHz). To prevent spectral overlap between two adjacent channels at the IF stage, a raised-cosine pulse shaping with a roll-off factor of 0.133 is implemented at each digital base-band. Therefore, the bandwidth of each IF channel is 2.125 GHz to ensure the adjacent IF channels are separated with sufficient inter-channel suppression. The digital-to-analog converters (DACs) of AD9739 [24] and digital-to-analog converters (ADCs) of EV10 AQ190A [25] are adopted for the base-band platforms. The sampling rate for each channel of DAC or ADC is 2.5 Giga-samples per second (Gsps) and the data symbol rate is 1.875 Gsps for each base-band signal. The four bits are mapped into one data symbol using 16 QAM. Therefore, the total data rate of four base-band signals is 1.875 \(\times\) 4 \(\times\) 4 = 30 Gbps. At the transmitter side, traffic streams generated by the Spinrent TestCenter [26] are the pseudo-random bit sequence with a 128 bytes packet size. At the receiver side, the received Ethernet traffic streams are fed back to the Spinrent TestCenter, and the BER result can be recorded from the user window of the Spinrent TestCenter. Figure 3 shows the measured 16 QAM constellations of the base-band platform loopback via direct DACs and ADCs connection, with an error vector magnitude (EVM) result of 4%. From this result, we can ensure that the signal processing produces a superb performance before connecting with the IF module and THz front-end.