# FPGA-Based Linear Detection Algorithm of an Underground Inspection Robot
## 3 System Implementation
### Region Growth Algorithm Module Design
The three growth modes are determined by the alignment of the central element and the seed. As shown in Figure 13, when the gradient of the central element point \(\text{Gra}=1\), growth is triggered. However, if \(\text{Gra}=0\), the growth is waiting to be triggered at \(\text{Gra}=1\). The judgment of termination of growth is very important to the accurate detection of line segments. In the image, due to the intersection of line segments or noise, the  
Figure 11: Processing flow of regional growth module. Figure 12: Heterogeneous convolution window. termination of growth cannot be judged only by the alignment of D[I,J], D[I+1,J], and D[I+1,J+1]. In this design, the growth possibility of the three directions is analyzed to judge continued growth, and then NOR operations on the three judgments are performed. Finally, the judgment condition for the termination of the growth is constructed. The right side of Figure 13 shows the method for judging the termination of growth in the area update. There are three possible directions for the continued growth of the central element D[I,J]:  
1. When the gradient value of D[I+1,J] is 1, the judgment of continuing lateral growth is performed;
2. When the gradient value of D[I,J+1] is 1, the judgment of continuing vertical growth is performed;
3. When the gradient value of D[I+1,J+1] is 1, the judgment of continuing diagonal growth is performed. At the same time, for the correctness of the region growth algorithm, the design of RAM control logic is also important. As shown in Figure 14, port A is the write port, which is responsible for the initialization of RAM and the update of line segment information. The B port is the read port. Since the updated region information of the seed point will participate in the next growth during the calculation process, the read data will participate in the construction of the heterogeneous convolution window. Figure 13: Area update method. In order to ensure the correctness of subsequent calculations, the RAM is initialized before the area growth; that is, the initialization data is written through Port A. The timing of the key signals is shown in Figure 15.  
The construction of the heterogeneous convolution window requires that the data read from RAM and the data read from FIFO are at the same time. The timing logic of key signals is shown in Figure 16. Both RAM and FIFO have a one-beat read delay. The read-enabled signal of FIFO drives the count of RAM read addresses. Figure 14: Construction of the RAM port signal. Figure 15: Timing diagram of RAM initialization key signals. The data update of area growth is determined by the growth mode and the judgment of the termination of growth. The timing diagram of key signals is shown in Figure 17. When the growth mode is vertical growth or initialization, the write enable of the A port is pulled high by one beat and the write data is determined by the growth termination signal. As the growth mode is horizontal, when the termination of growth is true, initialize J\(-\)1. When the termination of growth is false, it is necessary to initialize the address J\(-\)1 while updating the address J.