# Electronic Fourier-Galois Spectrum Analyzer for the Field \(Gf(31)\)
## 4 Spectrum Analyzer in the Galois Field _Gr_(31)
### Scheme of Adders and Multipliers by 5 Modulo Number 31  
Figure 5 shows the general scheme of the adder modulo Mersenne's prime number. This adder can be called a trigger adder because there are such values of the summed values at which it can be in two different steady states. The trigger adder modulo works as follows (Figure 3 shows its scheme for the particular case of the Mersenne number 31, which is used in this paper). Figure 4: Functional scheme of the spectrum analyzer in the Galois field GF(31). The scheme is based on the use of a typical binary adder, each element of which (a single-bit adder) performs the operation of addition modulo 2, as well as the operation of transferring a digit. A distinctive feature of the scheme in Figure 5[37] is the use of feedback between the output of the carry digit of the single-bit adder, which corresponds to the high digit, and the input of the carry digit of the single-bit adder, which corresponds to the low digit. According to the circuit of Figure 5, the feedback circuit includes the logical element OR. One of its inputs is supplied with the carry signal of the upper digit, and the other--the signal from the generator--forms short rectangular pulses. When adding (in the sense of ordinary arithmetic) two numbers \(A_{1,2}\) satisfying the following inequality:  
\[A_{1,2}\leq 2^{8}-1 \tag{52}\]  
The following three situations are possible:  
\[A_{1}+A_{2}>2^{8}-1A_{1}+A_{2}<2^{8}-1A_{1}+A_{2}=2^{8}-1\]  
In the first of these cases, the result of summation (in the sense of ordinary arithmetic) is represented by the following number in binary notation:  
\[A_{1}+A_{2}=a_{5}a_{4}a_{3}a_{2}a_{1}a_{0} \tag{53}\]  
i.e., one more binary digit appears, which is bolded in Formula (53). In order to bring this number to a number modulo 31, it is necessary to subtract 32 from it and add 1. Namely, this operation in this case is performed by the scheme in Figure 3. The value of the high digit \(a_{5}\) is added to the lower \(a_{0}\). The OR element (4) and the generator (5) have no effect on the result because at its input, which corresponds to the transfer of the highest digit, regardless of the state of the output of the generator (5), a logical one is formed. In the second case, the result of summation in the sense of ordinary arithmetic coincides with the result of calculation modulo 31. Here, the generator (5) and OR element (4) also do not affect the result of the calculation. After termination of the pulse forming at the output of the generator (5), the circuit returns to the initial state corresponding to the summation of numbers \(A_{1,2}\) in the sense of usual arithmetic. The third case from the above list is the most interesting. In this case, in general, the considered circuit can be in two different stable states, i.e., it becomes an analog of an RS-trigger. Figure 5: Functional diagram of the adder modulo 31. The value of the sum \(A_{1}+A_{2}=2^{8}-1\) corresponds to the case when the outputs of all single-bit adders in the scheme of Figure 5 are logical ones. This is one of two stable states. The second stable state corresponds to the situation when logical zeros are formed at all the above outputs due to the fact that the signal corresponding to a logical one is removed from the output of the OR element (4). Its addition to the number 11111 (binary coding) leads to the number 100000, which corresponds to the second steady state. Since there is no element in the circuit corresponding to the high digit of the number 100000, this state corresponds to the reduction of the number 11111 to the number 00000 modulo 31, which solves the problem. The transition from one steady state to another is provided by the generator (5), which provides the addition of one to the number 11111. In all other cases, as was shown above, it does not affect the operation of the circuit.