## 6 Validation Using Circuital Simulations  
The validation of the proposed PV system is performed using realistic and detailed simulations in the commercial power electronics simulator PSIM [20], which is used by several industries due to the capability to simulate the non-linear behavior of the MOSFET and diode, parasitic effects, and even emulate microprocessors using a C-code interface. The detailed circuital simulation is carried out using the circuital description of the PV system given in Figure 2. The controller block of such a figure is formed by the complete structure depicted in Figure 11, which uses the switching circuit of Figure 9 to generate the control signal \(u\) of the NEC boost converter. Finally, the circuital simulation is configured  
Figure 13: Design process for both the NEC boost converter and SMC. \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Value** \\ \hline \(v_{b}\) & 48 V \\ \(L_{1}\) & 150 \(\mu\)H \\ \(L_{2}\) & 150 \(\mu\)H \\ \(C_{cb}\) & 1.2 \(\mu\)F \\ \(C_{pv}\) & 110 \(\mu\)F \\ \hline \(t_{s}\) & 400 \(\mu\)s \\ \(H\) & 0.667 A \\ \(k_{p}\) & 2.96 A/V \\ \(k_{i}\) & 19.98 kA/V \\ \(\max(\left|\frac{d\gamma_{v}}{dt}\right|)\) & 0.061 V/\(\mu\)s \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Designed parameters for the NEC boost converter and SMC. using the parameters for both the NEC boost converter and SMC reported in Table 3, while the switching circuit is supplied with a \(V_{s}=5\) V power source and implemented using a Zener diode with \(V_{z}=2.5\) V, resulting in \(R_{x}=R_{y}=20\) k\(\Omega\) and \(R_{h}=27.5\) k\(\Omega\). Figure 14 shows the PSIM implementation of the PV system based on the NEC boost converter, including the SMC: in this circuit, the implementation of both the voltage controller and the calculation of the switching function \(\Psi\) are performed in an emulated microprocessor, which acquires the required signals using Analog-to-Digital converters (ADC) and delivers the output \(\Psi\) using a Digital-to-Analog converter (DAC). Appendix A reports the C code developed for the microprocessor, which can be used to implement those processes in any real device programmable in C language. The main advantage of the NEC boost converter concerns the reduced harmonic content introduced to the output DC bus in comparison with the classical boost topology. Such a condition is tested by comparing the performance of the proposed NEC solution with an equivalent PV system based on a boost converter: to provide a fair comparison, the boost converter is designed to provide the same current and voltage ripple to the PV panel; therefore, the capacitor and inductor of the boost topology are \(C_{boost}=110\) uF and \(L_{boost}=75\) uH, respectively. The design of such a boost inductor is also fair in terms of stored energy, as discussed in Section 2.2: the boost inductor stores almost the same energy as the two inductors of the NEC option. In fact, for a duty cycle of 50%, both \(L_{1}\) and \(L_{2}\) support half of the PV current, resulting in a combined stored energy of \(\frac{1}{2}\cdot L_{1}\cdot\left(i_{pv}\cdot 0.5\right)^{2}+\frac{1}{2}\cdot L _{2}\cdot\left(i_{pv}\cdot 0.5\right)^{2}=37.5\times 10^{-6}\cdot i_{pv}^{2}\), where \(L_{1}=L_{2}=150\) uF; the energy stored in the inductor of the boost current is \(\frac{1}{2}\cdot L_{boost}\cdot i_{pv}^{2}=37.5\times 10^{-6}\cdot i_{pv}^{2}\), which is the same. In the extreme case of the MPP at the highest irradiance (1000 W/m\({}^{2}\)), the duty cycle is \(d=61.77\%\), which results in a combined energy of the NEC converter inductors equal to \(39.57\times 10^{-6}\cdot i_{pv}^{2}\), which is only 5.5% higher than the energy stored in the inductor of the boost converter. Figure 15 reports the circuital simulations of the PV systems based on both the NEC and classical boost converters performed in PSIM. The detailed simulations confirm the desired condition for the PV voltage ripple, previously reported in Table 2: the peak voltage ripple is 8.9 mV\(<9\) mV.