# Analysis and Optimization of Output Low-Pass Filter
## 3 Frequency and Filter Component Normalization
### Limits of Filter Components  
The maximum allowable values for \(C_{n}\) and \(L_{n}\) can be established to meet power factor requirements. For a leading power factor, the maximum \(C_{n}\) is determined under circumstances where the inverter functions at 20% of its rated volt-amperes, which poses the most significant challenge in meeting power factor requirements. At this level, the inverter's output current is 0.2 pu, and \(Q\) is \(-0.12\) per unit. Given that \(Q\) equals \(Q_{L}-Q_{C}\), the maximum value of \(C_{n}\) is expressed as a function of \(L_{n}\). Specifically, when the inductance is zero, to comply with the power factor requirement, the normalized capacitance must be less than 0.12 per unit. Although this maximum capacitance is expected to increase slightly with higher \(L_{n}\), the increase is minimal since \(Q_{L}\) is equivalent to \(0.04L_{n}\) per unit at 20% rated capacity. For instance, the leading power factor standard is met when \(L_{n}\) is 0.5 pu, provided \(C_{n}\leq 0.124\) pu.  
This procedure is also used in the case of a lagging power factor, where the inverter output current is set to 1 pu and the power factor is set to 0.95 (lag). To confirm compliance with the power factor requirement, the normalized capacitance is once more computed as a function of \(L_{n}\). The maximum permissible inductance is 0.31 per unit without a capacitor. Introducing capacitance provides reactive power to the inductor, thereby leading to an increase in \(L_{n}\). Compared to the effect of \(L_{n}\) on \(C_{n}\) in the light-load, leading power factor case, the impact of \(C_{n}\) on \(L_{n}\) under full-load conditions is more pronounced, since the voltage across the capacitor, \(V_{C}\), exceeds 1 pu.  
Figure 13 illustrates the limiting values of inductance and capacitance that ensure the filter meets the grid's lagging and leading power factor requirements, depicted with dashed lines. Additionally, the figure includes \(\omega_{cn}\) contours at 10, 26, and 65 units per unit. The contours and dashed lines are integrated to represent two design areas, which are darkened to improve visibility. Area A, characterized by a thinner shading, corresponds to a switching frequency (\(f_{\text{sur}}\)) of 4 kHz. The wider shaded area, associated with a switching frequency of 10 kHz, includes areas A and B. Depending on the switching frequency selected, choosing  
filter components within these specified regions should result in a sinusoidal output current with a fundamental frequency within the appropriate power factor range. A minimum value of \(\omega_{cn}\) equal to 10 pu was selected to guarantee that the filter phase delay remains negligible. Maximum \(\omega_{cn}\) values of 26 and 65 per unit were established because they corresponded to cutoff frequencies, \(f_{cn}\), of approximately 0.33 pu, ensuring the output current waveform maintained less than 5% THD for switching frequencies of 4 kHz and 10 kHz, respectively.  
Inverter PF requirements can be met by the selection of \(C_{n}\) and \(L_{n}\) values within the designated design region. The characteristic impedance of the filter needs to be taken into account as well. The characteristic impedance, \(Z_{0n}\), is determined by the parameters \(C_{n}\) and \(L_{n}\), as illustrated in Equation (8). This impedance affects the selection of \(R_{D}\), which in turn affects the quality factor of the filter.  
As previously stated, a power factor ranging from 0.8 leading to 0.95 lagging is required for all output levels between 20% and 100% of the rated output power. The upper limit permissible for \(C_{n}\) at 20% output power is estimated to be 0.124 pu, derived from the requirement of a 0.8 leading power factor [10; 11]. Therefore, an initial \(C_{n}\) value of 0.1 pu was employed for the filter shown in Figure 2 to analyze the grid-connected CSI discussed in Section 4.