## 2 Buck Converter Modeling
As expected, fewer resources are needed in this case: around one fourth of LUTs (836 versus 3498) and less than half of flip-flops (521 versus 1177) are used. The usage of DSPs is similar in both cases (55 versus 60). A clock period of 25 ns can be achieved in this case. As seven cycles are necessary, the minimum achievable time step for Algorithm 2 is 175 ns. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Resource** & **Utilization** & **Available** & **Utilization \%** \\ \hline LUT & 3498 & 20,800 & 16.82\% \\ Flip-Flops & 1177 & 41,600 & 2.83\% \\ DSP & 60 & 90 & 66.67\% \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Resource utilization for the proposed Algorithm 4 and pipelined architecture using K-calculator blocks (XC7A35 TCSG324-2). The relation between integration time and error of Figures 4 and 6 can be updated by adding the timing limitations (Figure 9). The simulation error of both Algorithms 2 and 4 against dt is represented, only for the case of \(R=30\)\(\Omega\). The shaded area represents the zone not reachable with the proposed device. The area limit is defined by the intersection of Algorithm 2 error curve with a vertical line at 175 ns and the intersection of Algorithm 4 error curve with a vertical line at 1 \(\mu\)s.

The figure shows that lower integration times are reached with Algorithm 2 but at the cost much larger error than with Algorithm 4. Usually, lower integration times are sought in order to reach lower numerical errors, but in this case, a reduction in integration time step of less than one order of magnitude (from 1 \(\mu\)s to 175 ns) implies an error five orders of magnitude larger in both state variables, \(v_{C}\) and \(i_{L}\). Therefore, the proposed method, despite having more complexity and needing more clock cycles, delivers better results. ## 6 Conclusions

Fourth-order Runge-Kutta methods allow for accurate modeling of switched circuits. This high accuracy means that events such as the inductor current \(i_{L}\) crossing zero during a deadtime must be detected; otherwise the error of this source of error can ruin the noticeable accuracy of the solver method. In the proposed example, this source of error makes the error of the model six orders of magnitude higher when a dt of 1 \(\mu\)s is used. The proposed approximation by dividing the time step into two substeps serves to recover the expected accuracy. The initial simulations were performed with MATLAB and VHDL code using 64-bit floating point. The calculations were then translated to fixed point. The method used for this translation maintains an accuracy similar to that of 64-bit floating point. A pipelined architecture was designed to allow for an efficient implementation. The proposed generic K-calculator block serves as a building block for the successive calculation of the fourth-order Runge-Kutta \(KnL\) and \(KnC\) parameters. Results show that a highly accurate hardware-in-the-loop implementation of a buck converter with deadtimes is feasible with the selected Artix-7 device, having an integration time of 1 \(\mu\)s and calculation errors on the order of \(5.89\times 10^{-11}\) V for \(v_{C}\) and \(6.85\times 10^{-12}\) A for \(i_{L}\). Although this extremely low error is not usually needed as other sources of error \begin{table}
\begin{tabular}{c c c c} \hline
**Resource** & **Utilization** & **Available** & **Utilization \%** \\ \hline LUT & 836 & 20,800 & 4.02\% \\ Flip-Flops & 521 & 41,600 & 1.25\% \\ DSP & 55 & 90 & 61.11\% \\ \hline \end{tabular}
\end{table} 
Table 7: Resource utilization for the proposed Algorithm 2 and pipelined architecture using K-calculator blocks (XC7A35 TCSG324-2). Figure 9: Error in calculation of \(v_{C}\) and \(i_{L}\) as a function of the time step using Algorithms 2 and 4 for the case of \(R=30\)\(\Omega\), with the shaded area marking the zone not feasible with the proposed device. are present, this method allows the use of highly accurate numerical methods such as the fourth-order Runge-Kutta even when deadtime events are present.