## 3 Simulation Results
### Simulation Results for the IEEE 14-Bus Test System  
Figure 3 represents the modified IEEE 14-bus test system, including both LCC and VSC HVDC systems. The base of the complex power is 100 MW. Synchronous condensers are eliminated from the original test system, and only a single generator at Bus #1 is considered for simplification. Because Bus #1 is the reference bus, and the voltage-controlling generator is installed at the bus, the voltage magnitude and angle are 1 p.u. and 0 rad, respectively. The active power of the generator is fixed at 50 MW (0.5 p.u.) because it is not considered as a variable in the optimization problem. A 500 kV/200 MW LCC HVDC and a 400 kV/200 MW VSC HVDC are included at Bus #2 and #3, respectively. The parameters of the LCC HVDC are modified from the well-known CIGRE BENCHMARK model [40]. In the test system, the variables to be determined are \(P_{LCC}\), \(P_{VSC}\), and \(Q_{VSC}\). Note that the harmonic filters and shunt capacitors of the LCC HVDC system are considered at the admittance matrix. We compared the steady-state results of two conventional methods and the proposed method. In the first method, VSC HVDC operates in unity power factor (UPF) mode, so that the reactive power output is zero. In the second method (VC mode), the VSC HVDC controls AC voltage to be as high as possible. In both methods, the active power references of LCC and VSC HVDCs are identical. The forecasted load profile in the test system is illustrated in Figure 4, which is applied to both case studies. Figure 5 shows voltage profiles with the conventional and proposed method. Voltage profiles are investigated in the case studies, in that security constraints of AC voltage should be satisfied by utilizing the optimization problem. In UPF mode, the AC voltage profiles of most buses are lower than the lower bound (\(V_{lb}\)), as shown by the blue areas of Figure 5. On the other hand, in VC mode, AC  
Figure 4: Forecasted load profile for the IEEE 14-bus test system. Figure 3: Configuration of Institute of Electrical and Electronics Engineers (IEEE) 14-bus test system. voltage is maintained within the operational boundaries, because VSC HVDC compensates reactive power into the network as much as possible. The voltage is also maintained within its boundaries using the proposed method, because constraints on AC voltage are reflected in the optimization problem. However, the amount of reactive power with the proposed method is smaller than that of the VC mode, as shown in Figure 5.  
Table 1 shows the comparisons of active power outputs of LCC and VSC HVDCs, and the resulting power loss in three cases. As the outputs of LCC and VSC HVDCs are intended to be identical in the conventional methods, both HVDCs provide the same active power into the power network. On the other hand, VSC HVDC provides more active power than LCC HVDC in the case of the proposed method to minimize system loss. As a result, the active power loss of the test system with the proposed method is reduced 13.89% and 11.79% from that of the UPF mode and VC mode, respectively. Even the voltage level is higher when VSC HVDC operates on VC mode than the proposed case; power loss is smaller when using the proposed method, because the current flow increases for reactive power compensation in VC mode. As shown in Figure 5 and Table 1, the simulation results suggest that the proposed method is effective with steady-state characteristics for the IEEE 14-bus test system. To verify the droop coefficient determination method, we generate 10,000 load profiles reflecting forecasting error. We assume that the active and reactive load profile follows the normal distribution function, in which the average is the forecasted value and the standard deviation is 3% of the forecasted value. According to a previous study [21], we define \(R_{eq}\) and \(D\) as 0.1 and 2, respectively. Figure 6 illustrates the graphical analysis of the frequency-power droop coefficient design methodology.