# Effect of P+ Source Pattern in 4H-SiC Trench-Gate MOSFETs on Low Specific On-Resistance
## 2 Device Modeling and Simulation Methodology  
Figure 1a-c show the 3-D structures of 1.7-kV conventional SiC TMOSFETs with a P+ source with square and stripe patterns and the proposed TMOSFETs with a P+ source with a grid pattern, respectively. The top view of TMOSFETs with a square-pattern P+ source is shown in Figure 1d. The square-type P+ source is placed intermittently around the N+ source. The square pattern size was set to 2 \(\upmu\)m \(\times\) 2 \(\upmu\)m to consider alignment tolerance; thus, the half-cell pitch width was set to 2.3 \(\upmu\)m. Figure 1e shows the top view of TMOSFETs with a stripe pattern P+ source and a half-cell pitch width of 2.0 \(\upmu\)m. The stripe pattern is easily formed for two-direction patterning, allowing a smaller cell pitch than with a square pattern. The half-cell pitch width of TMOSFETs with a grid-pattern P+ source was set to 1.5 \(\upmu\)m, with a trench width (\(W_{\text{TRN}}\)) of 1.0 \(\upmu\)m, N+ source width (\(W_{\text{NP}}\)) of 1.0 \(\upmu\)m, and P+ source width (\(W_{\text{PP}}\)) of 1.0 \(\upmu\)m, as shown in Figure 1f. A P+ source with a grid pattern was placed next to the trench gate. Although the channel width was reduced, this pattern enabled a reduced cell-pitch. To analyze the effect of the grid pattern on electrical characteristics, a P+ source length (LPP) was divided into five cases from 0.5 \(\upmu\)m to 2.5 \(\upmu\)m in the half-cell pitch in the y-direction. For TMOSFETs with a 1.7-kV voltage rating, an N-type doping concentration of 6 \(\times\) 10\({}^{15}\) cm\({}^{-3}\) with a drift thickness of 15 \(\upmu\)m was designed using Sentaurus TCAD process tools. The detailed structural parameters presented in Table 1. TMOSFETs structural parameters were considered by experimental reference data [20; 21]. Grid-pattern TMOSFETs of the P-well, N+ source, P+ source, and trench gate were designed using the fabrication sequence shown in Figure 2. The fabrication processes of the proposed TMOSFETs with P+ source grid pattern is the same as those of the conventional TMOSFETs with P+ source square and stripe patterns except photo-patterning of P+ source. The electrical characteristics of TMOSFETs with P+ source patterns were compared using the Sentaurus device. All simulations of electrical characteristics used the Lombardi model for carrier-carrier scattering by acoustic surface phonons and surface roughness. Shockley-Read-Hall (SRH) and an Auger were used in the generation-recombination process [22]. For the breakdown simula  
Figure 1: (**a**) Conventional trench-gate MOSFETs with P+ source with square pattern, (**b**) stripe pattern, and (**c**) grid pattern. Top view of TMOSFETs with P+ source with (**d**) square pattern, (**e**) stripe pattern, and (**f**) grid pattern. tion, the van Overstraeten model was used for the avalanche generation model [22; 23]. The breakdown voltage was determined when the current reached 1 \(\upmu\)A. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameter** & **Value** & **Unit** \\ \hline Thickness of drift layer & 15 & \(\upmu\)m \\ Doping concentration of drift layer & 6 \(\times\) 10\({}^{15}\) & cm\({}^{-3}\) \\ Trench depth and width & 2, 1 & \(\upmu\)m \\ Doping concentration of P base & 2 \(\times\) 10\({}^{17}\) & cm\({}^{-3}\) \\ Channel length & 0.7 & \(\upmu\)m \\ Gate oxide thickness & 50 & nm \\ Width of inter layer dielectric (ILD) & 0.5 & \(\upmu\)m \\ Half-width of cell pitch (y-axis) & 5 & \(\upmu\)m \\ Half P+ source size (square pattern) & 1 \(\times\) 2 & \(\upmu\)m \\ Half P+ source size (stripe pattern) & 0.5 \(\times\) 5 & \(\upmu\)m \\ Half-width of cell pitch (square pattern) & 2.3 & \(\upmu\)m \\ Half-width of cell pitch (stripe pattern) & 2.0 & \(\upmu\)m \\ Half-width of cell pitch (grid pattern) & 1.5 & \(\upmu\)m \\ Half-width of P+ source (grid pattern) & 1.5 & \(\upmu\)m \\ Half-length of P+ source (grid pattern) & 0.5–2.5 (+0.5) & \(\upmu\)m \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Device structural parameters.