# An Adaptive Data Rate Algorithm for Power-Constrained End Devices in Long Range Networks
## 5 Adaptive Data Rate Algorithm Design
### Adaptive Data Rate Control Algorithm Based on Network Performance Optimization
#### 5.2.2 Adaptive Data Rate Algorithm for Network Performance Optimization
When the maximum number of iterations is reached or the optimal configuration is found, the algorithm returns \(list(node_{num},TP,SF,BW)\). Through this process, the algorithm gradually finds the optimal ED configuration combination in the complex search space, thereby improving overall network performance. ## 6 Testing and Result Analysis

To test the proposed ADR algorithm, this section designs an experimental scenario to verify the effectiveness of the algorithm from two perspectives: link state and network performance, assessing its performance in real-world applications. The experiment aims to determine whether the algorithm can effectively improve both link state and network performance. To ensure the accuracy of the results, the experiment was conducted in a real-world environment, testing multiple network performance metrics, including PRR, network throughput, average power consumption of the EDs, and average latency of the EDs. The experiment also compared the performance of this algorithm with the I-SFA scheme mentioned in [13], the LoRaWAN ADR algorithm, and the ADR+ algorithm. ### Construction of LoRa Network

#### 6.1.1 GW Hardware Design

The LoRa GW plays a key role in the LoRa network by serving as a protocol converter, responsible for converting IP packets from the network server into LoRa signals to be sent to the EDs and encapsulating the LoRa packets from the EDs into IP packets for upload to the network server. It mainly handles the forwarding of uplink and downlink messages, connecting LoRa EDs and the network server. Due to varying deployment environments, the GW needs to possess multiple networking capabilities, such as using Ethernet or Wi-Fi in urban areas, while relying on 3G/4G network connections in rural or outdoor settings. Additionally, the GW must support remote debugging and OTA (over-the-air) upgrades, and provide a certain level of computing power to support edge computing, thereby alleviating the burden on the network server. In terms of hardware, the GW uses the MediaTek MT7620A (manufactured by MediaTek Inc., Hsinchu, Taiwan) as the main control chip, which not only has strong computing capabilities but also supports the OpenWRT system for easier development. The RF section employs a four-channel MCU + SX1262 unit instead of Semtech's SX1301 chip, reducing costs while supporting bandwidth adjustment. To meet network demands, the system is designed to operate with two GWs working in coordination, with each GW equipped with four antennas, collectively achieving a configuration of eight antennas. Each RF unit is controlled by the main control chip through USB-extended serial ports and driven by the MCU to operate the SX1262. The GW also includes a 4G module for wireless access, LAN and WAN ports for Ethernet connections, and a Wi-Fi module for client access. Figure 10 shows the schematic diagram of the GW hardware architecture; Figure 11 displays the physical image of the GW. #### 6.1.2 ED Hardware Design

In the LoRa network, the EDs are critical components responsible for collecting sensor data and transmitting them to the gateway. The hardware design needs to support multiple sensor interfaces to accommodate different types of sensors while considering low power consumption requirements. To meet these demands, the STM32F103 RCT6 was selected as the microcontroller (MCU), paired with Semtech's SX1262 chip as the LoRa communication module. The SX1262 chip features higher transmission power, smaller packaging, and lower power consumption, making it highly suitable for low-power EDs. For the power supply design, an AC-DC conversion chip was employed, supporting both 5 V or 3.3 V DC input and AC power supply options. Additionally, the ED is equipped with an SMA RF interface, connecting to the antenna via an SMA to IPEX RF cable for the transmission of LoRa signals. This design ensures reliable communication for EDs across various application scenarios. Figure 12 shows the structural diagram of the ED hardware module, while Figure 13 displays the physical image of the ED.