# Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
## 4 Gate-Level Masking
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline
**Logic Style** & **Data** & **Based on** & **Area** & **Frequency** & **Power** & **Security** & **Special** \\
**CMOS** & NA 1 & STD 2 & 1 & 1 & 1 & 1 & NO \\ \hline
3 DDL [36] & FC 3 & 2.64 & 1.13 & 3.14 & 47.5-85.25 & YES \\ \hline
3 sDL [35] & FC 3 & 3-4 & 0.67-0.71 & 2.95-3.11 & 7.69-50.78 & YES \\ \hline
**AWDDL [31]** & STD & 4.36 & \(<\)WDDL & \(>\)\(\times\)CMOS & \(>\)DPL-noEE & YES \\ \hline
**BCDL [30]** & STD & 1.71 & 0.70 & NA & \(>\)20 & YES \\ \hline CRSABL [14; 59] & FC & 2.12 & 0.55 & 4.56 & 0.38-0.45 \(\times\) SABL & YES \\ \hline
**D\({}^{\prime}\)L [57; 58]** & STD & \(>\)\(\times\)CMOS & \(<\)\(\times\)CMOS & \(>\)\(\times\)CMOS & NO \\ \hline
**DDCVSL [44]** & FC & \(\sim\)0.8 \(\times\) DyCML & \(\sim\)1.68 \(\times\) DyCML & \(\sim\)2.70 \(\times\) DyCML & \(\sim\)1.16 \(\times\) DyCML & YES \\ \hline
**DDPL [39]** & FC & \(\sim\)0.75 \(\times\) SABL & NA & \(\sim\)1.86 \(\times\) SABL & \(\sim\)7.97 \(\times\) SABL & NO \\ \hline
**DDSLL [60]** & [47; 60; 61] & FC & 1.13-1.45 & 0.37 & 1.37 & \(>\)\(\times\)ICCML & YES \\ \hline
**Double-WDDL [20]** & [19; 20] & STD & 11.69 & 0.19 & 12 & \(>\)WDDL & YES \\ \hline
**DPL-noEE [26]** & STD & \(>\)WDDL & NA & \(>\)WDDL & \(>\)WDDL & YES \\ \hline
**DSDRL [24]** & [24; 25] & STD & 2.08-2.27 & \(\sim\)WDDL & \(\sim\)2.11-2.27 & \(>\)CMOS & NO \\ \hline
**DWDDL [8]** & [8] & STD & \(\sim\)WDDL & \(\sim\)WDDL & \(\sim\)WDDL & \(\sim\)WDDL & YES \\ \hline
**DyCML [15]** & [9; 15; 36; 59] & FC & 0.81-2.66 & 0.58-3.7 & 0.47-4.99 & 9.6-27.29 & YES \\ \hline
**GilFred [51]** & [51] & STD & 1.36 & 5.06 & 1.5 & \(>\)CMOS & NO \\ \hline
**GilFred-P [51]** & [51] & FC & 4.29 & 5.42 & 1.7 & \(>\)\(\times\)CMOS & NO \\ \hline
**HDRL [23]** & [23] & STD & 2 & 1 & 2 & \(>\)WDDL & NO \\ \hline
**iDDPL [40]** & [40; 41] & FC & 3.50 & 1.76 \(\times\) SABL & 4.40 & \(>\)SABL & NO \\ \hline
**IFLSML [47]** & [47] & FC & \(\sim\)1.10 \(\times\) DyCML & \(\sim\)D\(\times\)CML & \(\sim\)0.77 \(\times\) DyCML & \(\sim\)DyCML & YES \\ \hline
**WDDL [22]** & [22] & STD & 2 \(\times\) WDDL & 0.5 \(\times\) WDDL & \(\sim\)2 \(\times\) WDD & \(>\)Double-WDDL & YES \\ \hline
**LBDL [55]** & STD & 0.98 \(\times\) WDDL & 1.16 \(\times\) WDDL & 1.44 \(\times\) WDDL & \(>\)WDDL & YES \\ \hline
**LSCML [46]** & FC & \(\sim\)1.10 \(\times\) DyCML & \(\sim\)0.64 \(\times\) DyCML & \(\sim\)1.09 \(\times\) DyCML & \(>\)DyCML & YES \\ \hline
**MCML [33]** & [33; 34] & FC & 2.53 & 0.90 & 2360 & \(>\)CMOS & YES \\ \hline
**PG-MCML [34]** & [34] & FC & 2.57 & 0.88 & 0.20 & \(>\)CMOS & YES \\ \hline
**RCDDL [32]** & [32] & STD & 3.94 & 0.17 & 3.70 & \(>\)WDDL & NO \\ \hline
**RMTL [50]** & [50] & STD & 1.50 & 0.25 & 3.50 & \(>\)CMOS & NO \\ \hline
**SABL [7]** & [7; 9; 36; 40; 62] & FC & 1.8-3.27 & 0.51 \(\times\) DyCML & 1.91-7.98 & 14-166 & YES \\ \hline
**SC-DDPL [56]** & [56] & STD & 7.18 & NA & 4.2 & \(>\)2.42 \(\times\) WDDL & NO \\ \hline
**SDDL [8]** & [8; 20] & STD & 2 \(\times\) WDDL & 0.35 & 2 \(\times\) WDDL & \(>\)CMOS & YES \\ \hline
**SDML-p [54]** & [54] & STD & 1.41 & 0.67 & 1.07 & \(>\)WDDL & YES \\ \hline
**Sed.ib [28]** & [28; 30; 63; 64; 65] & STD & 15.09-28.00 & 0.25-0.5 & 4.05 & \(\sim\)10 \(\times\) WDDL & NO \\ \hline
**STTL [49]** & [49] & FC/STD & 5.68 & 0.22 & NA & \(>\)CMOS & NO \\ \hline
**TDPL [37]** & [37; 38] & FC & \(>\)SABL & 0.71-0.96 & 1.47-2.83 & \(>\)SABL & NO \\ \hline
**TSPL [38]** & [38] & FC & 1.3 & 1.20 & 1.14 & \(>\)WDDL & NO \\ \hline
**WDDL [8]** & [8; 19; 23; 30; 32; 38; 54; 56; 63; 44; 66; 67] & STD & 2.47-11.82 & 0.20-0.94 & 1.70-13.50 & 6.02-119.73 & YES \\ \hline \hline \end{tabular}  
* NA = not available. 2 STD: standard cells. 3 FC: full-custom.  
\end{table} 
Table 1: Gate-level hiding performance and security-normalized values with respect to CMOS logic style. In this section, a detailed description of the structure and functionality of each masking logic style proposed in the literature is provided.