# The Quanta Image Sensor: Every Photon Counts
## 6 Low-Power and High-Speed Readout Circuits
### Readout Circuits for Single-Bit QIS  
To implement the single-bit QIS ADC, the inherent random offset in a comparator and latch circuit must be overcome to permit practical use of a 500 \(\upmu\)V comparator threshold voltage. This traditionally requires additional gain and concomitant power dissipation. For low power, a charge-transfer amplifier (CTA) approach was taken [10]. Minimizing the power dissipation was achieved by using a 4-stage charge-transfer amplifier (CTA) as a gain stage in the analog readout signal chain. Use of CTA technique  
Figure 15: Illustration of polarization angle extraction from various sized cubicles of jets under each polarization-angle filter, from one Monte-Carlo simulation iteration (\(H=1\)) for each reference angle. Inset shows \(4\times 4\) jets under both polarization-angle filters and color filters, to create a \(3\times 3\) super-kernel to extract polarization and color information from a single-bit QIS. From [24]. implemented in pathfinder test chips have resulted in a significant improvement in an energy-per-bit figure of merit (FOM) compared to previous work, although detailed comparison is complicated. In the first test chip, low-power readout circuits based on the CTA were implemented in a 1000 fps megapixel binary imager [15; 19]. The architecture of the 1 Mpixel pathfinder image sensor is shown in Figure 16a. The 1376 (H) \(\times\) 768 (V) pixel image sensor uses a partially-pinned photodiode, 3.6 \(\upmu\)m 3T pixel, and readout architecture implemented in the X-FAB 0.18 \(\upmu\)m process. The sensor is operated in a single-row rolling-shutter mode so true correlated double sampling (CDS) can be utilized. This means that when a particular row is accessed, it is first reset, allowed to briefly integrate a signal, and then read out before moving to the next row. However, to achieve 1000 fps, this leads to extremely short integration times (i.e., <1 \(\upmu\)s), useful only in the lab. To characterize the pixels, lower frame rates were used. Figure 16: (**a**) Architecture of the 1 Mpixel pathfinder image sensor; (**b**) (I) 1-b ADC based on a cascade of sense amplifiers and a single D-latch comparator; (II) Schematic of each sense amplifier that is implemented as a differential charge transfer amplifier. A column-parallel single-bit ADC using a CTA-based design detects a minimum 0.5 mV output swing from the pixel (Figure 16b). The ADC is capable of sampling at speeds of 768 kSa/s. The sensor operates at 1000 fps, which corresponds to a row time of 1.3 us, a signal integration time, T\({}_{\text{int}}\), of 0.9 us, and an output data rate of 1 Gb/s. The final specifications of the image sensor are shown in Table 2. The power consumption of the entire chip (including I/O pads) is 20 mW. Total power consumption of the ADCs is 2.6 mW which corresponds to 1.9 \(\upmu\)W per column. The row addressing circuits including the buffers consume 0.73 uW per row, whereas the column shift registers dissipate 2.3 uW per column. The ADCs working in tandem with digital circuits consume an average power of 6.4 mW. It is also noted that in the QIS, input offset at 3\(\sigma\) must be less than 1/2 VLSB (=0.5 mV for this chip) which requires additional power dissipation. The FOM of the pathfinder chip is 2.5 pJ/b. The second test sensor explores the low-power readout circuits needed for a 1040 fps gigapixel binary image sensor [23; 25]. Due to limited available area on the die, only 32 of the columns (12,000 pixels in each column) and 16 1b-ADCs were implemented in this test chip. Since the column parallel architecture is used, the power consumption of a column can be multiplied by 2 \(\times\) 42,000 to estimate the expected total power consumption of a gigajot QIS. This imager was implemented in a 65 nm BSI CIS process. Pixel pitch is 1.4 um pitch, and 4-way-shared PPD pixels are used in the imager. The same structures of the sense-amplifier and 1b-ADC (size of the transistors and capacitors are scaled down) are implemented in this test chip.