# Analysis of Circuit Simulation Considering Total Ionizing Dose Effects on FinFET and Nanowire FET
## 1 Introduction  
Radiation hardening on semiconductor devices is a critical issue in various fields including radiation therapy, space, and nuclear reactor processes. The characteristics of devices change when they are exposed to a radiation environment. Designs, processes and shielding to reduce radiation effects are actively being studied in [1; 2; 3; 4]. However, the research on the radiation effect in a single device is still insufficient. Single event effects (SEE), total ionizing dose (TID) effects, soft error rate (SER), displacement damage (DD), and multiple bit upsets (MBU) lead to the obstruction of the reliable operation of semiconductor devices due to radiation [5; 6; 7; 8; 9]. The TID effect causes the issue of changing the electrical properties of semiconductor devices due to the hole trap. When the particles pass the dielectric area, electron-hole pairs (EHP) are generated. Electrons with relatively fast mobility exit the dielectric region, but holes with low mobility have some holes trapped at the existing trap site, which increases the leakage current and causes a threshold voltage (\(V_{T}\)) shift [10]. Therefore, the device reliability is degraded. Nanoscale devices can be further affected by other static and dynamic parameters by the TID effect [11]. However, it is challenging to analyze the exact radiation effect due to the trap recovery of the irradiated device from the measurement [12; 13]. Therefore, the TID phenomenon should be analyzed only by a simulation.  
\(V_{T}\)s has been used in the industry to continue the complementary metal-oxide-semiconductor (CMOS) scaling. However, critical issues such as the short-channel effect (SCE), \(V_{T}\) roll-off, and parasitic resistance emerge upon the FinFET scaling [14]. To alleviate these issues, Nanowire FET (NW-FET) has strong gate controllability and has been proposed to replace the FinFETs [15; 16]. The better gate controllability provided by the gate-all-around (GAA) structure can overcome the SCE problem and enable a moreaggressive gate length scaling than that for the FinFETs [17; 18; 19; 20]. Therefore, it is a promising solution for device miniaturization [21]. Thus, studies to mitigate the radiation effect of devices with this structure are required. In this study, TID simulations of a FinFET and NW-FET were carried out to analyze the element with a larger TID effect, according to the device structural part. This study was carried out by comparing the structural elements of the oxide area and gate controllability. Accurate TID simulation results were compared by calibrating the current and device sizes of the NW-FET and FinFET.  
As the oxide area increases, more EHP occurs and the number of trapped holes increases. However, despite the larger oxide area of the NW-FET than the FinFET, the \(V_{T}\) did not change significantly, and the device appeared to be more resistant to radiation. It is shown by introducing the GAA structure, that the higher the gate controllability, the more the TID effect can be suppressed in the oxide region. In addition, the FinFET and NW-FET affected by the TID were extracted using a Berkeley short-channel insulated-gate FET (BSIM) common multi-gate (CMG) and applied to an inverter circuit to perform the simulation.