# RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool
## 5 Conclusions and Future Works  
In this work, we implemented RTL-DEVS by leveraging the functionality of DEVS formalism-based modeling for hardware design. Through the designed RTL-DEVS model and simulation testbench, Verilog's timing control, netlist presentation, and abstract level simulation test were performed, and the simulation model could be expanded through the implementation of the simulation model and the waveform output of the testbench.  
Hardware design using RTL-DEVS, which can be continuously extended through the advancement of model specifications, suggests that simulations using extended libraries are possible in the limited environment of Verilog. DEVS formalism-based modeling is easily adaptable and translatable to other DEVS-based simulation environments, such as via XML, so it can be applied to multiple designs. In addition, it enables simulator development and plug-and-play model exchange through the addition of various languages, scalable classes, and test benches.  
As the complexity and size of modern developed SOCs (System on Chips) increases, verification becomes more important than design. Verification technologies are also evolving, and high scalability or automated methodologies such as UVM (Universal Verification Methodology) are becoming more important points for semiconductor chip development. Combining high-level language tools leveraging expertise in sequential programming for the validation of designed modules provides a design experience using an easily scalable and reusable DEVS format for the specification of hardware behavior and enables the use of sequential languages such as C for operations.  
The design and specification of the model based on DEVS formalism shows that it can be used as a simulation tool when it goes through the elaboration process. but for exhaustive simulations such as sequential equivalence checking, it faces the daunting task that commercial-level simulators must analyze in detail the functions supported by the commercial-level simulator and express them in DEVS formalism.  
Future research directions are to improve the RTL-DEVS model so that more expressions are possible, and to enable equivalence verification through the grafting of the Verilog to DEVS formalism tool under development.  
Figure 16: Delay time based model simulation components, they should be listed as: (**a**) Description of delay test module; (**b**) EPWave transform of original Verilog delay_t module (**c**) RTL-DEVS simulation result step graph.  
**Author Contributions:** Conceptualization, Y.-S.H.; methodology, B.-S.K.; software, B.-S.K.; validation, B.-S.K.; formal analysis, B.-S.K.; investigation, Y.-D.N.; writing original draft preparation, Y.-D.N.; writing, S.-W.J.; review and editing, S.-W.J.; supervision, J.-S.L.; project administration, J.-S.L.; funding acquisition, Y.-S.H. All authors have read and agreed to the published version of the manuscript.  
**Funding:** This research was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government funded by the Ministry of Science, ICT and Future Planning (NRF-2021R1A2C1003122).  
**Data Availability Statement:** Not applicable.  
**Conflicts of Interest:** The authors declare that they have no conflicts of interest.