# A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS
## 3 Transmitter System Architecture
### Driver Circuit Design  
The driver has two basic constructs, current mode logic (CML) and source-series terminated (SST). When the output swing is the same, the current required by the voltage mode driver is only 1/4 of the current mode driver [25]. The SST driver circuit has better linearity than the CML driver circuit for high-speed transmission, and the SST driver circuit can increase the height and width of the eye, so this paper used the SST driver circuit to drive the whole transmitter [5]. The transmitter in this design adopts a 7-bit SST driver circuit. If it is evenly divided, the SST driver circuit is divided into 127 parts, and the output impedance of each part is 6350 \(\Omega\). In this design, different weight ratios were used to reduce the impedance of each slice, thereby reducing the area occupied by the driver circuit, as shown in Figure 12.  
The 50 \(\Omega\) impedance matching of the 7-bit SST driver circuit is composed of MOS switch resistors and linear resistors in series and parallel. In general, the linear resistance occupies the main part of the device, because the linear resistance is much less sensitive to PVT changes than the MOS transistor as a switch tube. However, when the resistance of the MOS transistor is too small, the charging and discharging speed will be affected, thus limiting the output bandwidth. The relation between resistance and capacitance of the MOS transistor is shown in Figure 13. When the MOS transistor resistance increases from  
Figure 11: The 4:1 MUX differential output eye diagram. Figure 12: 7-bit SST DAC architecture. 12 to 25 \(\Omega\), the parasitic capacitance decreases by about half. However, when the resistance of the MOS transistor continues to increase, the reduction of capacitance is not obvious. Therefore, it is very important to choose a suitable MOS transistor resistance and linear resistance \(R_{E}\). The impedance of the traditional SST driver circuit matches the output impedance of 50 \(\Omega\), that is, \(R_{MOS}+R_{E}=Z_{0}\). The small resistance of the MOS transistor leads to a large parasitic capacitance. Therefore, the driver circuit was designed to add a linear parallel resistance \(R_{T}\) and linear series resistance \(R_{E}\) at the output end to increase the resistance of the MOS transistor and reduce the parasitic capacitance. Furthermore, the higher driver resistance can reduce the static current consumed by the driver. However, increasing the parallel resistance \(R_{T}\) will reduce the output swing, so it is necessary to make a compromise between power consumption and output swing. The relationship between the parallel resistance \(R_{T}\) and output swing is shown in Figure 14. According to references [26; 27; 28], it is infeasible that the output swing is far less than 0.67 Vppd under a multilevel modulation. Therefore, selecting \(R_{MOS}+R_{E}=75\)\(\Omega\) and \(R_{T}=150\)\(\Omega\) can not only ensure the output swing of the driver, but also reduce the dynamic power consumption of the driver. It can be seen from the previous analysis that when the resistance of the MOS transistor exceeds 25 \(\Omega\), the reduction of parasitic capacitance is not obvious. Finally, \(R_{MOS}=50\)\(\Omega\), \(R_{E}=25\)\(\Omega\), \(R_{T}=150\)\(\Omega\) were selected. Its output resistance is  
\[R_{out}=\frac{\prod\limits_{u=0}^{6}\left(R_{MOS}+R_{E}\right)_{u}}{\sum \limits_{i=0}^{6}\left(R_{MOS}+R_{E}\right)_{i}}\left\|R_{T}\right. \tag{5}\]  
Figure 14: Relation between shunt resistance and voltage swing. Figure 13: Relation between MOS resistance and capacitance. where \(R_{out}\) is the output resistance, \(R_{MOS}\) is the MOS transistor resistance, \(R_{E}\) is the series resistance, and \(R_{T}\) is the parallel resistance.