# Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial
## 1 Introduction  
The reliability feature for communication systems that must work in harsh environments such as space or radioactively contaminated areas, is a major concern nowadays [1, 2]. For these scenarios, not only area, delay and power consumption play an important role in the design process, but also fault tolerance is mandatory in order to deal with soft errors such as single event upsets (SEUs), multiple bit upsets (MBUs) or single event functional interrupt (SEFIs) produced by radiation [3]. These upsets are caused by ionizing radiation strikes that alter the charge in storage elements such as configuration memory cells, user memory or registers, causing non-permanent errors in the systems. In order to avoid these errors, there are two main approaches. The first option called radiation-hardening by process (RHBP), includes physical techniques that must change the manufacturing process by means of shielding or applying silicon on insulator (SOI) [4, 5]. Nowadays, rad-tolerant components are expensive and some generations older than the no rad-hard technology, which has led to the emergence of alternatives such as the radiation-hardening by design approach (RHBD) [6]. In RHBD approaches, the manufacturing processes are not modified to meet a specified radiation constraint. The techniques employed to meet these requirements are implemented in the VLSI architecture instead. This methodology applies some well-known hardening techniques based on spatial redundancy--e.g., triple modular redundancy (TMR) [7],information redundancy, error correction codes (ECC), or the \"system knowledge\" [8; 9; 10]-- to increase the reliability of the design. When the reliability parameter is introduced in the design workflow, it is important not only to design the protection schemes without penalizing hardware performance (area, timing and power), but also to be able to prove that the protected designs achieve the desired percentage of success under critical scenarios. To test the fault tolerance of protected designs, specific mechanisms and platforms are usually required. Fault injection is a feasible practice to achieve this purpose [11] by means of a platform capable of generating bit flips into the memory elements to emulate SEUs or MBUs. Fault injection platforms can be classified as [12]:  
* Based on hardware fault injection. * Based on software fault injection. * Based on simulation fault injection. * Based on emulation fault injection. This work is focused on explaining in-depth the whole workflow of an emulation-based fault injection platform for SRAM-based field-programmable gate arrays (FPGAs) based on the Xilinx soft error mitigation (SEM) intellectual property (IP) core. As an example to illustrate the step-by-step explanation of the fault injection platform, the reliability of a widely used finite impulse response (FIR) filter will be studied. The examples provided in this work are available as an online resource in a repository to facilitate the understanding and replication of the results. Also, in order to improve this workflow, the use and integration of the automatic configuration memory error-injection tool (ACME) [13] is introduced. This tool and the whole framework described here, despite others such as the Fault Injection Intel(r) FPGA IP Core [14], are totally open and free to be used by designers, providing the same amount of information and accuracy without requiring to purchase of a separate license. This paper is organized as follows: Section 2 presents an example of a common communication system that is exposed to radiation effects in satellites and, hence, it is interesting to be tested through fault injection. This module is the superheterodyne receiver that includes, for example, FIR filters and coordinate rotation digital computer (CORDIC) modules. This section also shows the effects of SEUs in the frequency domain.