# An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder
## 2 Related Definitions and Preliminaries  
### Definitions  
For simplicity, the list of notations used throughout the paper is given in Table 1.  
The information bits are a vector of K bits. It is encoded to produce the codeword \(\mathbf{c}=(c_{1},c_{2},\cdots,c_{N})\), which is a vector of \(N\) (\(N>K\)) bits, by adding \(M=N-K\) parity check bits to the message. These bits are used to detect and even correct transmission errors. In this work, a codeword \(\mathbf{c}\) of the LDPC code is modulated by Binary Phase Shift Keying (BPSK) modulation (\(\mathbf{x}=x_{1},x_{2},\cdots,x_{N}\)) and transmitted over the AWGN (Additive White Gaussian Noise) channel. The information at the receiver can be described by \(\mathbf{y}=\mathbf{x}+\mathbf{z}\), where \(\mathbf{z}\) is an independent Gaussian random variable with zero mean and noise variance \(\sigma^{2}\). The LDPC codes can be presented by a sparse Parity-Check Matrix (PCM) \(\mathbf{H}\) with \(M\) rows and \(N\) columns, where each row corresponds to a Check Node (CN) and each column corresponds to a Variable Node (VN). Moreover, the LDPC codes can be represented using a bipartite graph. This graph is also called a Tanner graph [24]. In the Tanner graph, each VN and each CN represent a code symbol and a parity check equation, respectively. An edge connects a VN \(i\) and a CN \(j\) if the entry \(H(j,i)\) of the PCM \(\mathbf{H}\) equals 1.  
\begin{table}
\begin{tabular}{l l} \hline \hline
**Notation** & **Meaning** \\ \hline
**B** & Base matrix \\
**H** & Parity-Check Matrix (PCM) \\ \(Z\) & The expansion factor \\ \(N\) & The length of the codeword \\ \(K\) & Information bits \\ \(R\) & The code rate \\
**c** & A codeword \(\mathbf{c}=(c_{1},c_{2},\ldots,c_{N})\) \\
**x** & The transmitted codeword \(\mathbf{x}=(x_{1},x_{2},\ldots,x_{N})\) \\
**y** & The received information \(\mathbf{y}=(y_{1},y_{2},\ldots,y_{N})\) \\ \(\sigma^{2}\) & Noise variance \\ \(n\) & The coded bit \(1\leq n\leq N\) \\ \(m\) & The parity check bit \(1\leq m\leq M\) \\ \(H(n)\) & The set of Check Nodes (CNs) connected to the \\ \(H(n)\backslash m\) & The set of \(H(n)\) with check node \(m\) excluded. \\ \(H(m)\) & The set of Variable Nodes (VNs) connected to \\ \(H(m)\backslash n\) & The set of \(H(m)\) with check node \(n\) excluded. \\ \(d_{v}\) & The number of neighbors of a VN is called its \\ \(d_{c}\) & The number of neighbors of a CN is called its \\ \(\widetilde{\gamma}_{n}\) & A Posteriori (AP) information update \\ \(\gamma_{n}\) & A priori information for each variable node \(n\) \\ \(\beta_{m,n}\) & Check-to-Variable (CTV) messages sent from \\  & CN \(m\) to VN \(n\) \\ \(\alpha_{m,n}\) & Variable-to-Check (VTC) messages sent from \\  & VN \(n\) to CN \(m\) \\ \(\widetilde{q}\) & The number of bits that represent \(\gamma_{n}\), \(\alpha_{m,n}\), \(\widetilde{\gamma}_{n}\) \\ \(q\) & The number of bits that represent \(\beta_{m,n}\) \\  & messages (in this paper, \(q=4\) bits) \\ \(\varphi(x)\) & The \(\widetilde{q}\)-bit quantization map of \(x\), that rounds \\  & each element of \(x\) to the nearest integer \\  & less than or equal to \(x\). \\ \hline \hline \end{tabular}
\end{table}
Table 1: The list of mathematical notations and their meaning.