# Low Power QC-LDPC Decoder Based on Token Ring Architecture
## 4 Experimental Results
It can be seen that despite the increase in \(P_{d}\) with increasing \(P\), the \(E_{d}\) significantly decreases with \(P\). This means that a semi-parallel decoder with a high degree of parallelization of computations will be characterized by a greater energy-efficiency in comparison to a decoder with a lower degree of parallelization. In view of the above, it can be seen that the correct selection of \(P\) for the design requirements is an important system design choice in terms of hardware requirements and dynamic energy losses. The presented architecture should finally be compared with the results from the literature. This is very complicated due to the enormous number of possible parity check matrices \(\mathbf{H}\) as well as the decoder design configurations. Even standards (like IEEE802.11 ad, WiGig) are characterized by a large number of utilized matrices \(\mathbf{H}\) upon which the QC-LDPC decoder can be designed. The most popular architectures in the literature are parallel architectures, which also pose a significant difficulty when trying to make a comparison, although in engineering practice the highest decoding speed is not always required. Nevertheless, an attempt was made to compare the proposed Token Ring-based architecture for the WiGig standard code. This is presented in Table 6, where NMS means Normalized Min-Sum decoder algorithm, which is a slightly modified decoding computation method in control nodes of the presented Min-Sum algorithm [37]. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Work** & **This Work** & [43] & [44] & [45] & [46] \\ \hline Voltage (V) & 1.1 & 0.9 & 1.1 & 1 & 1.1 \\ Core area mm\({}^{2}\) & – & 1.99 & 0.575 & 1.56 & 0.8 \\ Total memory (bits) & 24,424 & 160.727 & 7875 & – & – \\ Clock frequency (MHz) & 400 & 202 & 400 & 197 & 220 \\ Block length (bits) & 672 & 672 & 672 & 672 & 672 \\ Code rate & 1/2 & 1/2 & 1/2 & 1/2, 5/8, 3/4, 7/8 & 1/2, 5/8, 3/4, 13/16 \\ Throughput (Gb/s) & 0.611 & 6.78 & 9.25 & 5.79 & 6.16 \\ Measured power (mW) & 119.92 & 289 & 272.9 & 361 & 203 \\ Decoding algorithm & MS & MS & MS & NMS & MS \\ Message quantization (bits) & 4 & 5 & 4 & 6 & 5 \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Comparison of IEEE802.11 ad standard decoders. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline  & \multicolumn{4}{c}{**Without “Token Ring”**} & \multicolumn{4}{c}{**With “Token Ring”**} \\ \hline \(P\) & \(L_{c}\) & **ALM** & \(P_{d}\) **[mW]** & \(E_{d}\) **[n]** & **ALM** & \(P_{d}\) **[mW]** & \(E_{d}\) **[n]** \\ \hline
4 & 7920 & 598 & 40.99 & 811.602 & 712 & 28.41 & 562.518 \\
8 & 3960 & 979 & 44.84 & 443.916 & 1119 & 27.64 & 273.636 \\
18 & 1760 & 2183 & 91.05 & 400.62 & 2359 & 44.37 & 195.228 \\
24 & 1320 & 2837 & 101.43 & 334.719 & 3054 & 55.59 & 183.447 \\
32 & 990 & 3641 & 116.7 & 288.8325 & 3987 & 75 & 185.625 \\
48 & 660 & 5580 & 178.97 & 295.3005 & 6085 & 99.71 & 164.5215 \\
64 & 495 & 7883 & 230.15 & 284.8106 & 8210 & 124.91 & 154.5761 \\
96 & 330 & 11,822 & 343.69 & 283.5443 & 12,165 & 181.45 & 149.6963 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Analysis of the impact of \(P\) on energy consumption and hardware demand (\(f=400\) MHz). The design proposed in this article will be recommended in the systems when the maximum possible throughput is not critical, while maintaining a reduced \(P_{d}\) value, which has a direct impact on the temperature generated in the integrated circuit. Figure 6: Influence of the \(P\) value on the \(L_{c}\) value for a QC-LDPC decoder with an architecture based on Token Ring. Figure 7: Influence of the \(P\) value on the ALM value for a QC-LDPC decoder with an architecture based on Token Ring.