# SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
## 3 Modeling of GIDL Erase with SiGe Surrounded Structures  
In this section, we provide a detailed explanation of the methodology and modeling results of the erase operation of the SiGe integrated structure. First, we derived the capacitance of each layer between the BL PAD and the GIDL transistor over the A-A\({}^{\prime}\) region in Figure 1 using the cylindrical capacitance calculation method to calculate the voltage across all layers during the erase operation. Figure 8 compares the voltage across the SiGe layer of cylindrical capacitor modeling results and the TCAD simulation results for different t\({}_{\text{SiGe}}\) values. When t\({}_{\text{SiGe}}\) is below 15 nm, the difference between the modeling results and the TCAD simulation results is at most 5%, demonstrating a high accuracy of the model. However, when t\({}_{\text{SiGe}}\) is thicker than 16 nm, as mentioned in Section 2, the reduction in the BL PAD area causes its resistance to increase, preventing the BL PAD potential from reaching the intended level in time. As a result, a voltage discrepancy arises between the TCAD simulation and the modeling results. Therefore, we excluded the electrical characteristics modeling for the cases of t\({}_{\text{SiGe}}\) over 16 nm in this work. Figure 8: TCAD simulation and modeling results for the voltage across SiGe layer over t\({}_{\text{SiGe}}\) at V\({}_{\text{ERS}}\) = 14 V.  
Figure 7: BL Current for (**a**) different Ge composition ratios; (**b**) SiGe thickness over WL voltage. Figure 9 shows the distribution of the induced electric field and the resulting net generation-recombination rate via BTBT (\(R_{\text{net}}^{\text{bb}}\)) in the SiGe layer when tsiGe is 13 nm, Ge composition ratio is 0.5, and 14 V applied to BL. Here, \(r_{\text{in}}\) denotes the radius of the BL PAD, and \(r_{\text{out}}\) denotes the outer radius including the SiGe layer. The average electric field (\(E_{\text{avg\_SiGe}}\)) in the sidewall and bottom region of the SiGe layer was modeled as a function of tsiGe as Equation (1). \(C_{\text{total}}\) is the equivalent series capacitance of bandgap-engineered ONO layer, channel poly-Si layer, and SiGe layer. Since the electric field in the surface region near the BL is significantly larger than elsewhere and \(R_{\text{net}}^{\text{bb}}\) in this area dominates the total hole generation, this part was mainly considered in the modeling. The calculated \(E_{\text{avg\_SiGe}}\) was used to determine the surface electric field (\(E_{\text{sur}}\)) as defined in Equation (2). The parameter \(\alpha\) in Equation (2) is a fitting parameter that adjusts the surface electric field according to the \(V_{ERS}\)-\(V_{GIDL\_TR}\) value. Additionally, the electric field in the corner region (\(E_{\text{cor}}\)) was also separately modeled, as described in Equation (3). \[E_{\text{avg\_SiGe}}=\frac{V_{SiGe}}{t_{SiGe}}=(V_{ERS}-V_{GIDL\_TR})\frac{C_{ total}}{C_{SiGe}t_{SiGe}} \tag{1}\]  
\[E_{\text{sur}}(r)[\text{V}/\text{cm}]=(E_{\text{avg\_SiGe}}-\left(\frac{r_{ \text{in}}+r_{\text{out}}}{2}-r\right)\frac{dE_{\text{sur}}(r)}{dr})\alpha \tag{2}\]  
\[E_{\text{cor}}(r,\theta)[\text{V}/\text{cm}]=E_{\text{sur}}(r)\cos\theta \tag{3}\]  
Based on the individually calculated \(E_{\text{sur}}\) and \(E_{\text{cor}}\), we calculated the \(R_{\text{net}}^{\text{bb}}\) occurring in each region during the erase operation using Equations (4) and (5) from the Hurkx model [16,18]. Equation (5) defines the correction factor \(D\) used in the Hurkx model when computing the \(R_{\text{net}}^{\text{bb}}\). Here, \(n\) and \(p\) are the electron and hole concentrations, respectively, and \(n_{\text{i}}\) is the intrinsic carrier concentration. The parameter \(\beta\) in Equation (4) is a correction factor varying with the Ge composition ratio and \(V_{ERS}\)-\(V_{GIDL\_TR}\), and \(E_{\text{sur}}\) or \(E_{\text{cor}}\) is assigned to \(E\) in Equation (4) depending on the location of \(R_{\text{net}}^{\text{bb}}\).