# High-Speed, High-Performance DQPSK Optical Links with Reduced Complexity VDEE Equalizers
## 3 Proposed Partially-Joint Single-Ended DQPSK Equalization  
Boosting the performance while keeping the cost low is a challenging task in the design of reliable optical links. Low-complexity balanced DQPSK equalization demonstrates poor performance compared to the joint single-ended alternatives [2]. Motivated by former studies concerning the performance of the balanced receivers in DPSK and in DQPSK signaling [19; 23; 24], we proposed the use of a low complexity, partially-joint single-ended equalization scheme, using a subset of the signals available at the receiver, described by one of the possible combinations (\(I_{c}\), \(Q_{c}\), \(Q_{d}\)), (\(I_{d}\), \(Q_{c}\), \(Q_{d}\)), (\(I_{c}\), \(I_{d}\), \(Q_{c}\)), and (\(I_{c}\), \(I_{d}\), \(Q_{d}\)). Due to fractionally-spaced sampling, each triplet corresponds to six signals that are digitally processed by the pertinent equalizer. The proposed three-port partially-joint single-ended VDFE equalizers, hereafter denoted by the ignored port, e.g., VDFE[\(M_{f}\), \(M_{b}\)]-\(I_{x}\) or VDFE[\(M_{f}\), \(M_{b}\)]-\(Q_{x}\), offer approximately a 25% reduction in the required circuitry, compared to the full joint processing counterpart. As it will be demonstrated in Section 4, the proposed approach offers a low complexity alternative for electronic equalization, without sacrificing much of the performance if any at all, compared to the fully deployed counterpart. In order to complete the investigation of partially joint equalizer counterparts, also two port partially joint single ended VDFE equalizers are compared to the balanced receiver VDFE equalizers. All of the aforementioned equalization/receiver-related configurations are depicted in Figure 3.  
Let us consider that the signals processed are given by the triplet (\(I_{c}\), \(Q_{c}\), \(Q_{d}\)), i.e., the destructive port of \(I\) channel has been ignored, hence, the six signals (depicted on Figure 4a) fed to the feed-forward part of the equalizer are:  
\[ \begin{array}{l}y_{1,1}(n)\triangleq I_{c}(nT_{s}),y_{2,1}(n)\triangleq I_{ c}(nT_{s}+T/2)\\ y_{1,2}(n)\triangleq Q_{c}(nT_{s}),y_{2,2}(n)\triangleq Q_{c}(nT_{s}+T/2)\\ y_{1,3}(n)\triangleq Q_{d}(nT_{s}),y_{2,3}(n)\triangleq Q_{d}(nT_{s}+T/2)\\ \end{array}  \tag{4}\]  
Now the three-port partially-joint single ended VDFE equalizers VDFE[\(M_{f}\),\(M_{b}\)]-\(I_{d}\) (presented in Figure 4b) is described as: (\(l=1,2\)). \[\begin{array}{l}u_{l}(n)=\sum\limits_{i=1}^{2}\sum\limits_{k=1}^{3}\sum \limits_{m=0}^{M_{f}-1}f_{i,m}^{k,l}y_{i,k}(n-m)+\sum\limits_{i=1}^{2}\sum \limits_{k=1}^{3}\sum\limits_{m_{1}=1}^{M_{f}-1}\sum\limits_{m_{2}=m_{1}}^{M_{ f}-1}f_{i,m_{1},m_The three remaining cases are treated in a similar way. A metric of complexity of the implementation of the recursive scheme, is \(C=2M\), given by:  
\[C_{VDFE(M_{f},M_{b})}=12M_{f}+6M_{f}\Big{(}M_{f}+1\Big{)}+2M_{b}(M_{b}+1) \tag{6}\]  
Despite its high efficiency in combating the introduced distortion, VDFE in DQPSK exhibits quadratic computational complexity with respect to the ISI size. The increased hardware requirements raise a barrier in the deployment of such device in low-cost, high-speed optical links. To alleviate the complexity issues inherently introduced in the VDFE, reduced complexity counterparts has recently been introduced [11], resorting to pruning techniques for the reduction of the size of the pertinent Volterra kernels, suppressing that part of the Volterra kernel that has a marginal contribution in the overall performance. The resulting pruned VDFE (PVDFE) equalizers, compared to the full-term design, is more tractable from an implementation point of view, leading to significant computational complexity savings, without sacrificing much of the performance compared to the fully-deployed counterpart.