# Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs
## 3 Related Works  
A great deal of research has recently been conducted in the area of multicore systems on chips, particularly the relevant design and interconnection evaluating architecture, in a bid to construct optimally effective communication platforms. A major area of growing interest has been the design of novel alternatives to Network-on-chip (NoC) fit for implementation with massive computing architectures entailing reliable data exchange between cores and memories. NoCs are capable of bearing an increasing number of computing cores on a single chip, thereby achieving high levels of parallelism and speeding up execution time. Contrarily, however, conventional shared buses consume greater amounts of energy due to the complexity of wire interconnections on the chip, thus, bringing about only lower throughput levels. Additionally, the temporary registers implanted in shared buses usually consume a greater area and higher energy levels, resulting in poor scalability. This is likely to stand as a major hindrance to the maintenance of effective communication via \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Links** & **Stage 0** & **Stage \((d+1)\)** & **Stage \(k\in[1\dots d]\)** \\ \hline Baseline & I & I & \(\delta_{(d-i)}^{k}\) \\ Omega & I & \(\sigma^{k}\) & \(\sigma^{k}\) \\ Butterfly & I & \(\sigma^{k}\) & \(\beta_{(d-i)}^{k}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Swapping Delta MINs Functions. Figure 3: A Delta MIN model with eight nodes. future Multi-Processor Systems on Chip (MPSoC) designs [24; 25; 26; 27; 28]. To cater to these needs, Multistage Interconnection Networks (MINs) have emerged as a potential solution for the increasing demand for scalability and reliability in static Network-on-chip (NoC) architectures, to meet the exponential growth in massive parallel computing. The evaluation of MINs can be performed based on various metrics, including energy, area, throughput, fault-tolerance, network complexity, and cost-effectiveness. Most often, the functional formalization of MIN-based networks has been developed by identifying intrinsic properties of all MIN topologies. It has also been validated via the ACL2 theorem, to prove that the environment does actually comply with the network formal specification perquisite of integrating architectural parameters, with a significant impact on design costs [29; 30]. Comparative studies have also been established to assess MIN systems in relation to static topologies, mainly in terms of reliability, performance. A comprehensive review of MIN systems in matters of reliability, fault-tolerance, and cost perspective evaluative aspects is available in the relevant literature [31; 32]. As to the MPSoCs with heterogeneous cores, however, they have been designed to implement irregular topologies with hybrid wired/wireless interconnection [33]. Other research studies have been focused on comparing MINs architectures with other topologies [34; 35; 36]. In ref. [36], [PERSON] et al. introduced extra features to the Noxim simulator [37] to evaluate particular applications in an NoC system. They proposed a specialized design for relevant basic routing algorithms to explore their impact on performance metrics. Their major aim was to substitute longer channels with single-hop Radio Frequency transmissions among routers. With the significant increase in computational requirements necessary for operating and boosting the various related applications, researchers are now experimenting with the implementation of artificial intelligence techniques in System on Chip designs to further enhance their performance. A major suggested approach consists in integrating Deep Neural Network (DNN) accelerators in NOC-Based MPSOC to manage computation and communication within the chip, thereby, enhancing computational flexibility and scalability [38].