## 6 Conclusions  
In this paper, an FPGA-based algorithm for displaying star charts of a dynamic star simulator is designed that can output star charts under the condition that the star chart field of view is \(\Phi 20^{\circ}\) and the simulated magnitude is 2.0 \(\sim\) 6.0 Mv.  
(1) The article analyzes the calculation of the optical axis pointing calculation part, the optical axis pointing coordinate transformation calculation part, the star area search range calculation part, the star point coordinate transformation calculation part, the star point  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Name**} & **Slice LUTs** & **Slice Registers** & **Block RAM Tile** & **DSPs** \\  & **(20,800)** & **(41,600)** & **(50)** & **(90)** \\ \hline project & 52.20\% & 33.14\% & 8.00\% & 48.89\% \\ U\_sao\_top & 20.80\% & 19.26\% & 0.00\% & 48.89\% \\ U\_sao\_zone & 6.36\% & 2.73\% & 0.00\% & 32.22\% \\ U\_sao\_disp & 5.37\% & 4.05\% & 0.00\% & 0.00\% \\ U1\_div & 8.05\% & 11.52\% & 0.00\% & 0.00\% \\ Uart\_to\_img & 0.40\% & 0.55\% & 0.00\% & 0.00\% \\ PLL & 0.00\% & 0.00\% & 0.00\% & 0.00\% \\ Dvi\_pll & 0.00\% & 0.00\% & 0.00\% & 0.00\% \\ Dvi\_encoder1 & 0.89\% & 0.38\% & 0.00\% & 0.00\% \\ Disp\_driver & 0.25\% & 0.11\% & 0.00\% & 0.00\% \\ DDR3\_ctrl\_2 port & 30.16\% & 12.85\% & 8.00\% & 0.00\% \\ \hline \hline \end{tabular}
\end{table}
Table 4: FPGA hardware resource usage.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**References** & **Calculation Method** & **Number of Stars** & **Computation Time** \\ \hline
[5] & serial & 9006 & 56 ms \\
[6] & serial & 15,914 & 9.43 ms \\
[7] & serial & 5103 & 7.98 ms \\ article & parallel & 5067 & 72 us \\ \hline \hline \end{tabular}
\end{table}
Table 5: Comparison of the performance of different methods.  
Figure 22: FPGA hardware resource usage schematic.  
validity judgment part, and the calculation of the star point coordinate transformation part. The article uses the characteristics of FPGA parallel computing with pipelining to improve the calculation speed of data and accelerate the display speed of dynamic star charts.  
(2) This design utilizes FPGA to reduce the size and power consumption of the dynamic star simulator, get rid of the dependence of the existing algorithm on the computer, and significantly reduce the star point display time.  
Overall, the FPGA-based dynamic star chart algorithm design improves the display speed of star charts. However, there is still room for further optimization of hardware resources, especially the usage of LUTs. At the same time, there are more suitable algorithms for FPGA implementation, which is the direction of the future development of dynamic star map displays.  
Conceptualization, B.C., L.W. and G.L.; methodology, B.C. and L.W.; software, B.C.; validation, B.C., L.W. and X.R.; formal analysis, B.C.; investigation, B.C. and L.W.; resources, B.C.; data curation, B.C.; writing--original draft preparation, B.C.; writing--review and editing, B.C., L.W., G.L. and X.R.; visualization, B.C. and X.R.; supervision, L.W. and G.L.; project administration, B.C. and L.W.; funding acquisition, L.W. All authors have read and agreed to the published version of the manuscript.  
This research was funded by the Science and Technology Development Plan of Jilin Province, China, under Grant 20220201089 GX.  
Not applicable.  
Not new data were created or analyzed in this study. Data sharing is not applicable to this article.  
The authors declare no conflicts of interest.