## 3 Application and Results
### Particle Waveform Data FPGA Forward Inference Module
In convolution layer 2, the convolution kernel operates serially, requiring three clock cycles (\(x2=3\)), with four input channels (\(y2=4\)). The sliding window computation requires two passes (\(z2=2\)), and the output channel computation requires four passes (\(a2=4\)). For pooling layer 2, the pooling operation requires one clock cycle (\(clkpool=1\)), with input channels operating serially over eight cycles (\(clkchannel=8\)). In convolution layer 3, the convolution kernel operates serially, requiring three clock cycles (\(x3=3\)), with eight input channels (\(y3=8\)). The sliding window computation requires two passes (\(z3=2\)), and the output channel computation requires four passes (\(a3=4\)). In the fully connected layer, all parameters flatten to 256 elements. Each cycle performs eight multiplications; thus, the total number of multiplication clock cycles is \(clkmulti=256/8=32\). The eight multiplications are completed in one clock cycle, so \(clkoutputnode=1\). The comparison shows that the deviation value between the theoretical calculation and the actual time required is more than 100 clk, which is used for data synchronization, assignment, and other operations. Through layout and routing, the final results of FPGA resource utilization can be obtained, as shown in Table 7. The reason for the high LUT resource usage is that both the model weights and intermediate variables are stored using registers to maximize inference speed. The utilization rate of DSP modules can be further improved by implementing parallel computation within the convolution kernels or increasing the number of multiplication operations per clock cycle in the fully connected layers. The actual operating platform is the AX7z035 ZYNQ development board, which uses a 422 expansion board and a USB-to-422 converter to input waveform data and output and save the forward inference results. Additionally, the program for the development board is loaded in real-time by an FPGA programmer, and the board is powered by a 220 V to 12 V transformer. The overall hardware architecture is shown in Figure 13.  
Based on the results of the FPGA inference, two side-by-side comparisons need to be made: one is the match between the FPGA inference results and the test dataset to judge the actual accuracy, and the other is the comparison between the FPGA inference results and the floating-point computation results output from Pytorch to judge the difference between the fixed-point number and the floating-point number so as to assess the usability of the fixed-point computation results. The results of the analysis with the full waveform test dataset are shown in Table 8. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Resource** & **Utilization** & **Available** & **Utilization (\%)** \\ \hline LUT & 143,859 & 171,900 & 83.69 \\ LUTRAM & 97 & 70,400 & 0.14 \\ FF & 70,898 & 343,800 & 20.62 \\ BRAM & 0.50 & 500 & 0.10 \\ DSP & 240 & 900 & 26.67 \\ IO & 36 & 250 & 14.40 \\ BUFG & 3 & 32 & 9.38 \\ MMCM & 1 & 8 & 12.50 \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Final results of FPGA resource utilization. From the above table, it can be observed that the results calculated using fixed-point forward extrapolation are only 0.1% lower than the floating-point numbers, and the match between floating- and fixed-point numbers is 99.9%.