# Reduced Complexity Sequential Digital Predistortion Technique for 5G Applications
###### Abstract  
Wireless communication infrastructure is a key enabling technology for smart cities. This paper investigates a novel technique to enhance the performance of 5G base stations by addressing the compensation of nonlinear distortions caused by radiofrequency power amplifiers. For this purpose, a sequential digital predistortion approach that uses twin nonlinear two-box structure along with reduced sampling rates in the feedback path is proposed to implement a linearization system. Such a system is shown to have a correction bandwidth that exceeds the bandwidth of the feedback path. This is achieved by synthesizing the predistortion function in two successive characterization iterations. Both characterizations use the same hardware, which has a reduced sampling rate in the feedback path. Hence, the proposed predistorter scheme does not require any additional hardware compared to standard schemes. Moreover, coarse delay alignment is performed while identifying the memory polynomial function in order to further reduce the computational complexity of the proposed system. Experimental results using an inverse Class-F power amplifier demonstrate the ability of the proposed predistorter to achieve a correction bandwidth of 100 MHz with a feedback sampling rate as low as 25 MSA/s. 5G communications; digital predistortion; nonlinear distortions; power amplifiers +
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between linearity and efficiency. Such trade-off is commonly addressed by designing high-efficiency nonlinear power amplifiers and compensating for their nonlinearity by means of linearization techniques [9]. Predistortion, and more specifically baseband digital predistortion, is widely adopted for the linearization of base station power amplifiers. This consists of implementing, in the baseband digital domain, a nonlinear function that is complementary to that of the amplifier being linearized such that the cascade made of the predistorter and the amplifier operates as a linear amplification system. Even though digital predistortion is often perceived as a mature linearization technology, several improvements are continuously needed to address the specificities of emerging wireless standards and the evolving requirements that these impose. Recently, several researchers have addressed the challenges in digital predistortion systems. These include the linearization of millimeter-wave power amplifiers [10], the reduction of the computational complexity associated with delay estimation algorithm [11], and the computational stability of low sampling rate systems [12]. Furthermore, neural networks are gaining popularity, and have recently been reported for bandwidth, power and carrier configuration resilient predistorters [13], multi-input multi-output (MIMO) beamforming applications [14], 5G radio over fiber applications [15] and 6G dynamic spectrum aggregation [16]. Through all recent work, a common issue can be clearly identified. The design of digital predistorters for modern applications has to address two major concerns: the accurate characterization of the amplifier's nonlinear behavior, and the perfect match between the predistortion function and the amplifier's nonlinearity [9]. The observation bandwidth of the feedback path used to acquire the amplifier's output signal is becoming a design bottleneck due to the use of wideband signals in modern applications with up to 100 MHz in 5G sub-6 GHz frequency band and up to 400 MHz in the 5G millimeter wave frequency range (above 24 GHz). The main concern is that, due to spectrum regrowth, the signal at the output of the PA typically has up to five times the bandwidth of the signal being transmitted. This spectral regrowth is directly caused by the nonlinearity of the power amplifier. Therefore, the sampling rate of the analog to digital converter (ADC) in the feedback path of predistortion systems needs to accommodate such wide bandwidths.