# Adaptive Noise Cancellation Based on Time Delay Estimation for Low Frequency Communication
## 3 FPGA Implementation  
As shown in Figure 3, the proposed algorithm includes three modules: time delay estimation module, delay and channel control module, and noise cancellation module. As shown in Equation (17), there are (2P + 1) multiply-accumulate operations and one exponential operation for each sample to get the time delay estimation value. In order to obtain high time delay estimation accuracy, all the operations should be executed in one sampling period and the sampling period should be reduced [31]. Therefore, acceleration of computing is needed. FPGA is more suitable for multiple-instruction, single-data (MISD) applications when power and space considerations outweigh price [32]. In order to execute the proposed algorithm in real time, the proposed algorithm is implemented on FPGA. In this paper, the sampling frequency is 1 MHz and the ADC is 14 bit. Next, this system is described in detail.  
Figure 4 shows the time delay estimation block diagram. For each channel, the noise signal \(x\left(k\right)\) is stored in register stack and \(P\) is set to be 32. Through the multiply-accumulate (MAC) operation, the noise signal \(x\left(k\right)\) is multiplied by sinc and \(f(v)\) functions. To reduce the computational complexity, the sinc and \(f(v)\) functions are stored in two lookup tables. The values of sinc and \(f(v)\) functions are obtained from the lookup tables, based on the time delay estimation value \(D\left(k\right)\) from previous iteration. Then the time delay estimation value is updated based on Equation (17).  
Figure 4: Time delay estimation block diagram.  
After getting the time delay values of all channels, the values are processed by the delay control module, which is shown in Figure 5. In order to reduce the computational complexity, we use mean absolute error (MAE) of \(D\left(k\right)\) rather than the variance to evaluate the correlation between the primary input and the reference inputs. Then the reference input with least MAE will be selected as the reference noise. We will also obtain the time delay value \(D_{\text{c}}\left(k\right)\) inserted in the primary input:  
\[D_{c}\left(k\right)=E\left[D\left(k\right)\right]+\frac{L_{W}}{2} \tag{18}\]  
where, \(L_{W}\) is the length of coefficient vector \(\mathbf{W}\).  
Figure 6 shows the adaptive noise cancellation block diagram. The desired signal with the delay \(D_{C}\left(k\right)\) is subtracted by the filter output, which is obtained through MAC operation. As we have known the time delay between the primary input and the reference input, we can shorten the filter length. In this paper, the length of filter coefficient is 4 and the filter coefficient vector is updated based on Equation (11).  
The proposed algorithm is implemented with the Altera Stratix III EP3 SE260F1152C2N FPGA. Table 1 lists the hardware resource consumption. For this design, the resources of the Stratix III EP3 SE260F1152C2N are quite sufficient. The highest resource utilization module is the MCC-ETDE module, which requires 9 times more resource than the ANC module. In this paper, the length of filter coefficient is 4. Therefore, the resource utilization of ANC module is equal to that of the MCC-ETDE module when the length of filter coefficient is 40. In the actual situation, the proposed algorithm can reduce the hardware resource consumption when the time delay is more than 40 samples.  
Figure 5: Delay control block diagram.  
Figure 6: Adaptive noise cancellation block diagram.