# Vertical GaN MOSFET Power Devices
## 5 GaN Vertical Transistor Summary and Benchmarking  
Figure 11 presents a schematic comparison of GaN vertical MOSFETs designed for \(V_{BD}\) exceeding 1 kV. To achieve a high \(V_{BD}\), these devices employ both FP termination and mesa termination to eliminate potential crowding issues at the p-n junction edge. To reduce \(R_{ON}\), modifications are made to the thickness and doping concentration of the channel and drift layers. Reducing the doping concentration and thickness of the p-GaN layer decreases channel resistance, while adjusting the thickness and increasing the doping concentration of the n-GaN drift layer reduces drift resistance, thus increasing the \(V_{BD}\). Additionally, further \(R_{ON}\) reduction can be achieved by increasing the gate width per unit,  
Figure 10: Mesa edge termination of GaN MOSFET. Reprinted with permission from Ref. [96]. 2019, [PERSON].  
which in turn increases current density. This design improvement resulted in a reduction in \(R_{ON\text{-}SP}\) from 12.1 m\(\Omega\)-cm\({}^{2}\)[41] to 18 m\(\Omega\)-cm\({}^{2}\)[66]. To increase the \(V_{BD}\) from 1.2 kV [66] to 1.6 kV [67], the doping concentration of the n-GaN drift layer is reduced. However, there is a tradeoff between \(V_{BD}\) and device switching speed. As \(V_{BD}\) increases, \(R_{ON}\) also increases, which can slow down device performance. In addition, reducing leakage current can enhance the \(V_{BD}\)[59]. Sequential N implantation after Mg implantation significantly reduces leakage current by suppressing hole traps, resulting in improved \(V_{BD}\)[59; 114]. In addition, enhancing the MOS interface quality and stability can also improve breakdown characteristics. A two-step process introduced in [69] involves thorough surface cleaning followed by (NH4)\({}_{2}\)S passivation to improve the MOS interface. Furthermore, the lower electron mobility of p-GaN increases channel resistance, requiring a higher gate bias to lower resistance [115]. Therefore, a GaN interlayer is grown between the in situ oxide layer and the trench to increase channel mobility.  
Table 1 presents a comparison of different vertical GaN transistors featuring \(V_{BD}\) exceeding 1 kV. Generally, larger devices exhibit higher \(V_{BD}\), but this comes at the cost of increased \(R_{ON\text{-}SP}\). In the context of power devices, it is crucial to evaluate the PFOM, where higher values signify superior voltage-blocking capabilities. Although elevated \(V_{BD}\) enhances PFOM, higher \(R_{ON\text{-}SP}\) can offset them. Illustrated in Figure 12 is Baliga's figure of merit benchmark plot, which assesses various vertical GaN and SiC devices designed for \(V_{BD}\) of approximately 900 V and above [36; 41; 59; 66; 67; 69; 71; 72; 73; 74; 75; 76; 77; 78; 79; 80; 81; 82; 83; 84; 85; 86; 87; 88; 89; 90; 91; 92; 93; 94; 95; 96; 97; 98; 99; 100; 101; 102; 103; 104; 105; 106; 107; 108; 109; 110; 111; 112; 113; 114; 115; 116; 117; 118; 119; 120; 121; 122; 123; 124; 125; 126; 127; 128; 129; 130; 131; 132]. The plot suggests that, at present, GaN vertical devices lie mainly near the SiC limit, indicating the potential for further enhancements in GaN vertical technology to yield more efficient power devices.  
Figure 11: The schematic comparison of GaN vertical MOSFET with a breakdown voltage greater than 1 kV. Reprinted with permission from Refs. [41; 59; 66; 67; 69; 115].