## 2 SPDT Switch Design
Figure 4: Equivalent circuit of the proposed SPDT switch in (**a**) the TX and (**b**) the RX mode. Figure 3: Cross-sectional illustration diagram of the 90 nm CMOS process. The reason why a series DTMOS-R transistor is used in the RX path but not adopted in the TX path is for achieving a lower IL, higher linearity, and a better isolation in the TX mode. This can be explained in more detail as follows. To avoid high power loss in the high-output-power TX path, low IL and high linearity are essential for the TX path of an SPDT switch. Compared with a series active DTMOS-R transistor in the on-state, a series passive TL shows a lower IL and higher linearity (due to its metal-based structure). Moreover, compared with an equivalent \(\lambda\)/4-TL with a short-circuited load, a series DTMOS-R transistor in the off-state normally shows a better open circuit (needed for the high isolation operation of the RX path in the TX mode) due to the switching property of the transistor. Therefore, a series DTMOS-R transistor is used in the RX path. Instead of using a series DTMOS-R transistor (in the RX path), a \(\lambda\)/8-TL-based \(\lambda\)/4-TL is used in the TX path for a low IL, high linearity, and high isolation. The SPDT SW2 is designed via a 1P6M 0.18 \(\mu\)m CMOS process. The interconnection lines and the inductors are placed on the 2.34 \(\mu\)m thick MT\({}_{6}\) to minimize the resistive loss. The lowermost MT\({}_{1}\) with a pattern density of 90% is used as the ground plane of the TLs. The D between MT\({}_{6}\) and MT\({}_{1}\) is 5.14 \(\mu\)m. To avoid performance degradation, the space between the TLs is at least 5 times that of D (i.e., 25.7 \(\mu\)m) to control the mutual coupling and parasitics. The design and simulation of the spiral inductor L\({}_{1}\) and the \(\lambda\)/8-TL are conducted using ADS Momentum, a 2.5D EM piece of simulation software (suitable for the planar inductor and TL simulation) provided by Agilent Technologies, Santa Clara, United States. Then, EM-circuit co-simulation is performed using ADS to ensure the post-layout simulation results are close to the measured ones. For the CMOS SPDT switches in the literature, a gate voltage (or control voltage) V\({}_{\rm G}\) of 1.8 V is normally adopted to turn on the switch transistors, and a V\({}_{\rm G}\) of \(-\)1.8 V is normally used to turn off the switch transistors. For a fair comparison, V\({}_{\rm G}\) values of 1.8 V and \(-\)1.8 V, respectively, are adopted to turn on and turn off the switch transistors in this work. To obtain a better IL, isolation, and linearity performance, a V\({}_{\rm G}\) slightly higher than 1.8 V can be adopted to turn on the switch transistors to achieve a better on-state (i.e., lower on-state channel resistance), and a V\({}_{\rm G}\) slightly lower than \(-\)1.8 V can be adopted to turn off the switch transistors to achieve a better off-state (i.e., higher off-state channel resistance). Figure 4a shows the equivalent circuit of the SPDT switch in the TX mode. The control voltage V\({}_{\rm sw1}\) (=V\({}_{\rm G1}\) = V\({}_{\rm G2}\)) is equal to \(-\)1.8 V, and V\({}_{\rm sw2}\) (=V\({}_{\rm G3}\)) is equal to 1.8 V. That is, transistors M\({}_{1}\) and M\({}_{2}\) (controlled by V\({}_{\rm sw1}\)) are in the off-state and M\({}_{3}\) (controlled by V\({}_{\rm sw2}\)) is in the on-state. Ideally, R\({}_{\rm off1}\) and R\({}_{\rm off2}\) are high-resistance and R\({}_{\rm on3}\) is low-resistance (close to 0). According to the TL theory, the series \(\lambda\)/8-TL is equivalent to a series inductance L\({}_{\rm L1}\) and two parallel end-capacitance C\({}_{\rm L1}\). The \(\pi\)-network consisting of a parallel end-capacitance C\({}_{\rm L1}\)+ C\({}_{\rm G1,off}\) + C\({}_{\rm G1,off}\) (i.e., C\({}_{\rm L1}\) + C\({}_{\rm P}\)), a series inductance L\({}_{\rm L1}\), and a parallel end-capacitance C\({}_{\rm L1}\) + C\({}_{\rm Ant}\) + C\({}_{\rm gd2,off}\) (i.e., C\({}_{\rm L1}\) + C\({}_{\rm P}\)) in the TX path is equivalent to a \(\lambda\)/4-TL with a Z\({}_{\rm C}\) of 50 \(\Omega\).