## 6 Results and Comparison
### Results Comparison
#### 6.4.2 Demapper Module  
Table 6 summarizes the comparison of the proposed demapper architecture with relevant state-of-the-art implementations in terms of utilized resources and performance. The presented demapper architectures in [27] and [28] are dedicated to certain wireless communication standards. In [27], where the conventional RTL design approach has been used, DVB-T2 is the target standard; hence, the architecture design supports the QPSK, 16-QAM, 64-QAM and 256-QAM modulation schemes for non-GrayDVB constellation with rotation. Similarly, the architecture described in [28] has been designed to fulfill the requirements of the DVB-S2 standard. Four modulation schemes are supported (QPSK, 8-PSK, 16-PSK and 32-PSK) with Gray mapping constellation, as specified in [29]. Both architectures do not support iterative demodulation. In [26], an application-specific instruction set processor (ASIP) dedicated to the Max-Log-MAP demapping algorithm has been presented. The ASIP architecture, so-called _DemASIP_, provides full flexibility and can be utilized in multiple wireless communication standards (WiFi, WiMax, LTE and DVB) with the support of iterative demodulation. Compared to our proposed architecture, _DemASIP_ has the same computational units and supports the same flexibility parameters as our design. To compare fairly, our proposed architecture design has been synthesized with the same target technology used in the implementation being compared. When comparing to our proposed architecture, the demapper architecture in [27] almost requires 3.33-times more dedicated multipliers, 3.1-times more LUTs, but 2.2-times less registers to be implemented. Whatever the modulation type is, the demapping of one symbol lasts for 10 clock cycles with a maximum reached frequency of 62 MHz. In contrast, the number of required clock cycles to demap one symbol varies according to the modulation scheme in our proposed architecture. For the selected device, our proposed demapper can operate 3.1-times faster, and it outperforms the described design in [27] when adopting QPSK, 16-QAM and 64-QAM modulation modes. In case of 256-QAM, the latter design provides better throughput. In fact, the demapper architecture in [27] exploits demapping metric level parallelism. It can calculate nine Euclidean distances in parallel by using nine computational units; hence, high throughput is achieved in the case of high-order modulation schemes. Whereas in the case of lower modulation schemes, the computational units are not fully exploited to perform the computations related to one received symbol. In [28], the timing information about the hardware implementation is not available. Only device utilization is presented. Although the architecture is optimized targeting the M-PSK modulation schemes for Gray mapping constellation, the presented logic utilization summary reveals the need of 1.8-times more logic devices and 2.67-times more multipliers compared to our proposed demapper design. Regarding _DemASIP_[26], although it has a tailored instruction set, the architecture design has to integrate an instruction decoder. The comparison is conducted targeting the same device (Xilinx Virtex-5 LX330 FPGA) and using the same synthesis options and tools. From the implementation view, _DemASIP_ almost requires 1.44-times more slice registers and 2.1-times more slice LUTs compared to our proposed demapper architecture. In addition, the critical path of _DemASIP_ includes 24 levels of combinational logic, and it is related to the fetch program counter register. _DemASIP_ can achieve a maximum operating frequency of 186 MHz; whereas the proposed architecture can achieve a maximum operating frequency of 240 MHz and, thus, it is 1.29-times faster than _DemASIP_. On the other hand, fetching and decoding the instructions impose additional pipeline stages. As shown in Table 6, the proposed demapper architecture achieves better throughput than _DemASIP_ in all system configurations and all combinations of mapping styles, modulation types and SSD.