# Automatic Configurable Hardware Code Generation for Software-Defined Radios+
## 6 Hardware Model Using Finite State Machines
### FSM Optimizations
#### 6.2.2 Second Optimization  
The first optimization technique in Section 6.2.1 works effectively in systems where access patterns are short by exploiting the gaps and periodicity of the SDF-AP schedule. However, most real-world applications are often characterized by very long access patterns, this implies multiple sub-states of state type \(s_{k}\) which lead to a _state explosion problem_. The second optimization (_opt2_) alleviates this problem by grouping all the chained sub-states of \(s_{k}\) into one state. The corresponding hardware implementation involves the LUT of the consumption pattern (\(CP(c)\)) which is indexed with a digital counter where each element of the LUT is assigned to the read-enable output signal \(r\) in the same state type but at different clock cycles. As depicted in Figure 9, the optimized FSM \(M_{opt2}\) has a state type \(s_{k}\) that now uses multiplicity of \([1..*]\) and that has loop transition to enable the traversing of \(ET(v)\) elements of a \(CP(c)\). Two counters are used to control data access on the FIFO. The first counter \(ic\) counts the number of states in a single firing period of \(ET(v)\) after which the transition from \(s_{k}\) state type to \(s_{fg}\) state type takes place. The second counter \(jc\) counts the total number of sub-states passed by the \(s_{k}\) state type in one schedule iteration. When its threshold (i.e., \(jc=ET(v)\times RV(v)\)) is reached, an \(M_{opt2}\) moves from \(s_{k}\) state type to \(s_{ig}\) state type. Converting an optimized FSM \(M_{opt2}\) (shown in Figure 9) into hardware design results in VHDL process code that is shown in Listing 5. In comparison to the \(M_{opt1}\) VHDL process in Section 6.2.1, the number of states for the \(M_{opt2}\) are reduced from seven to three. This reduction is facilitated by the \(xInst\_yInst\_ch1\_cp\)\(CP(y)\) that maps a reversed \(CP(y)\) (i.e., \"10101\") in LUT using a big-endian style. At the transition from a periodic phase (i.e., comprises a single sub-state \"00\") to the periodic phase (i.e., comprises two states \"01\" and \"10\"), the least significant bit (LSB) of \(xInst\_yInst\_ch1\_cp\) is assigned to read-enable signal \(xInst\_yInst\_ch1\_re\) together with the activation of the \(ic,jc\) counters. The second state (i.e., \"01\") creates the \(s_{k}\) state type of the FSM with the aid of the two count registers namely \(xInst\_yInst\_ch1\_ic\) and \(xInst\_yInst\_ch1\_ic\). The indexing of individual bits of LUT is made possible by using the register \(xInst\_yInst\_ch1\_ic\) which counts from 0 to \(ET(y)-1=5-1=4\) where the actor firing terminates. Another count register \(xInst\_yInst\_ch1\_jc\) detects the end of iteration when the threshold of \((ET(y)\times RV(y))-1=(5\times 2)-1=10-1=9\) is reached. The second state transitions to the iteration gap state (i.e., \"10\") which introduces a time delay of (\(I  
Figure 9: The generic optimized composite FSM \(M_{opt2}\) as constructed using FSMs \(M_{X}\), \(M_{FF}\) and \(M_{Y}\) by using the computed 1-periodic schedule in Figure 2. Each node is the state type which may consists of sub-states which are defined by a sequence of one or two-dimensional vectors in lower half of the state type. hardware system. Computing the throughput using both the dataflow and hardware model is performed with respect to the sink actor. For the SDF-AP model, the transition model is used to compute throughput by counting the number of _gets_ per number of ticks in a periodic phase. For example, using Figure 4, the number of _gets_ is 6 while the _tick_ count is 12 resulting in throughput \(\frac{6}{12}\). For the FSM, the throughput is determined by counting the number of states with asserted _valid_ output signal value (i.e., \(v=1\)) per total number of transitions in a periodic phase. For example, in Figure 7, the number states with \(v=1\) are 6 and the number of transitions is 12, as a result the throughput becomes \(\frac{6}{12}\).