## 3 Design of Approximate QAM Demodulation Circuits
### Exploration Results
\begin{table}
\begin{tabular}{l c c c c c c c c c c c c c c c} \hline \hline  & \multicolumn{6}{c}{**Approximate LLR (ALLR)**} & \multicolumn{6}{c}{**Piecewise LLR (PLLR)**} & \multicolumn{6}{c}{**Approximate ML (AML)**} \\  & **FLP** & **FLP-W4** & **FXP** & **FXP-T8** & **FXP-T11** & **FXP-K6** & **FLP** & **FLP-W4** & **FXP** & **FXP-T8** & **FXP-T11** & **FLP** & **FLP-W4** & **FXP** & **FXP-T8** & **FXP-T11** \\ \hline
**LUT** & 106,097 & 104,881 & 56,278 & 19,957 & 10,210 & 37,653 & 2060 & 2020 & 160 & 76 & 59 & 3848 & 3504 & 139 & 91 & 44 \\
**DFF** & 42,432 & 42,432 & 21,596 & 10,684 & 9316 & 51,572 & 886 & 886 & 215 & 126 & 96 & 1204 & 1204 & 44 & 28 & 18 \\ \hline
**MHz**\({}^{1}\) & 286 & 294 & 312 & 323 & 416 & 321 & 333 & 435 & 571 & 645 & 740 & 385 & 416 & 588 & 645 & 769 \\
**W**\({}^{2}\) & 5.0 & 4.9 & 5.5 & 3.0 & 2.5 & 3.6 & 0.8 & 0.8 & 1.1 & 1.0 & 0.9 & 0.6 & 0.7 & 1.0 & 0.7 & 0.6 \\
**MHz/W**\({}^{3}\) & 114.4 & 117.6 & 56.7 & 107.7 & 166.4 & 89.2 & 416.3 & 543.8 & 519.1 & 645.0 & 822.2 & 641.7 & 594.3 & 588.0 & 921.4 & 1281.7 \\ \hline
**avg. MRE** & \(-\) & 86.00 & 2.22 & 20.59 & 193.14 & 1.74 & \(-\) & 177.05 & 1.28 & 23.35 & 165.55 & \(-\) & 8.36 & 0.02 & 4.65 & 22.98 \\ \hline \hline \end{tabular}  
* It is the maximum clock frequency. The throughput of all the circuits is 1 sample per CC, namely, _MHz_ Msamples/s. \({}^{2}\) It is the power consumption measured at the maximum clock frequency of the circuits. \({}^{3}\) It is the throughput-per-power ratio, i.e., Msamples/s per W.  
\end{table} 
Table 1: Resources of our 64-QAM circuits on Xilinx Zynq Ultrascale + ZCU106 (230 K LUTs, 461 K DFFs) w/o DSP. Figure 6: BER scaling in our 64-QAM circuits. FLP = accurate floating-point, FLP-W4 = floating-point with approximate addition [19], FXP = accurate fixed-point, FXP-TX = fixed-point with bit truncation, FXP-K6 = fixed-point with approximate multiplication [14]. (**a**) Approximate LLR (ALLR). (**b**) Piecewise LLR (PLLR). (**c**) Approximate ML (AML). * _ALLR circuits_ : The FLP-W4 implementation provides a negligible reduction of only 1% in LUTs and only 3% increase in frequency compared to FLP. On the other hand, the fixed-point ALLR circuits deliver increased gains. The accurate FXP circuit gains 50% in resources and has 9% higher frequency, while FXP-T8 and FXP-T11 have 81% and 90% reduction in LUTs, 75% and 78% reduction in DFFs, and 13% and 45% increase in frequency, respectively. FXP-K6 reduces its utilization by 64% in LUTs, 21% in DFFs and operates 12% faster. If we seek BER performance in-line with FLP, circuits with moderate truncation (FXP-T8) or approximate multipliers (FXP-K6) can be used. Additionally, considering the MRE metric, FXP-T8 is worse than FXP-K6 (20.59 vs 1.74). * _PLLR circuits_: FLP-W4 offers only 2% reduction in LUTs, but gains 30% in frequency compared to the FLP circuit. Regarding fixed-point circuits, we observe 92%, 96%, 97% reduction in LUTs, 75%, 85%, 89% reduction in DFFs and 71%, 93%, 122% higher operating frequencies for the accurate FXP, approximate FXP-T8 and FXP-T11 circuits, respectively. As SNR increases (Figure 6b), the BER performance of FLP-W4 and FXP-T11 deviates significantly from FLP; thus, a fixed-point architecture with moderate truncation can be adopted. * _AML circuits_: FLP-W4 achieves 9% LUT reduction and 8% frequency increase compared with the accurate FLP circuit. For the fixed-point circuits, we observe 96% LUT reduction, 98% DFF reduction either we have accurate circuits (FXP) or approximate ones (FXP-T8, FXP-T11). Regarding frequency, an increase by 53% for the accurate FXP, 68% for the FXP-T8 and almost 100% for the FXP-T11 is seen. However, we note that AML provides the worst BER performance among all algorithms and arithmetic, and thus, its deployment on a real-world system may be limited. Incorporating the BER results (Figure 6c), a fixed-point with moderate truncation (T8) circuit is preferable, as it follows the BER curve of FLP.