# A Programmable SRv6 Processor for SFC
## 2 Related Work
### Programmable Data Plane
Additionally, programming protocol-independent packet processors (P4) provide users with this capability, breaking the limitations of hardware devices on the data forwarding plane and allowing the data packet parsing and forwarding process to be programmatically controlled as well, making the network and devices truly open to users from the top to bottom. Disaggregated RMT (dRMT) separates computational resources (e.g., match/action processors) from memory, which are interconnected via a crossbar [18]. Each match-action (MA) processor holds a P4 program and processes packets in an RTC manner. The FlexCore architecture introduces another innovation in the dRMT partial decomposition design by holding an indirect data structure called a program description table (PDT) in the local memory of the MA processor [19]. This table contains metadata about the control flow of the program and can be used to reconfigure the processing flow of this processor. At present, the programmable NIC has become a general concept, which refers to any NIC module that has the programmable capability to support the uninstallation of various virtual network functions or application services. According to the different implementation mechanisms of the programmable NIC, the programmable NIC can be divided into three types according to the technical route, as follows: the programmable NIC based on ASIC, the programmable NIC based on a multi-core, and the programmable NIC based on FPGA. The programmable NIC based on ASIC has a fixed logic and can only be programmed by instruction (such as a CPU). Therefore, it needs to work with other external programmable modules to realize the main functions of the programmable NIC. However, its working frequency is high, and a high performance-power consumption ratio can be achieved by means of a special pipeline and other mechanisms. At the same time, the processing process has a good delay certainty. For example, the Intel IPU uses ASIC to realize the basic logic of NIC programmable switching layer, and implements accelerated logic of other data plane based on multi-core [20]. A multicore-based programmable NIC generally has one or more embedded core arrays, which are interconnected with the data/control pathways of the NIC through an on-chip bus to provide programmability to the NIC in a manner similar to an embedded server. Examples include Mellanox's BlueField [21] programmable NIC and Fungible's DPU [22]. Compared with ASIC, multi-core architecture has lower programming complexity and higher flexibility, but because it also uses [PERSON]'s computing architecture, its energy consumption is higher than that of general ASIC or FPGA logic. The characteristics of a FPGA-based programmable NIC are between the aforementioned two. Firstly, FPGA has the field programmable ability, which allows users to use HDL (Verilog, VHDL) to reconstruct the functional logic of a network card offline at the logic gate level, so it has better programmability. However, the disadvantage is that the programming complexity is relatively high compared to the CPU. In addition, due to the partial timing margin occupied by the routing between the configurable logic blocks and the logic, the ASIC generally operates less frequently than the ASIC of the same process level. The key idea of in-network computing is to take advantage of the unique advantages of switches to do part of the computation directly in the network, so as to reduce latency and improve performance. Although programmable switches have been an important enabler of this new paradigm, PISA is often not suitable for emerging in-network applications, thus, limiting further development and preventing widespread adoption of in-network computing applications. Thus, Juniper came up with a programmable architecture for in-network computing called the Trio [23]. The Trio is built on a custom processor core with an instruction set optimized for network applications.