# Late-Stage Optimization of Modern ILP Processor Cores via FPGA Simulation
## 4 FPGA Implementation
### FPGA System  
Figure 4 shows a conceptual block diagram of the FPGA system. The system comprises two parts: FPGA hardware and management software. The FPGA hardware hosts the target processor core and other components that facilitate performance analysis. The processor core has a conventional PMU that can perform general performance analysis. For information that cannot be obtained from the PMU, a specially designed PMU (SD-PMU) outside the processor core can be utilized. The SD-PMU is capable of supporting any processor hardware analysis because it can connect to any hardware signal in the processor if required. Another FPGA hardware component, the config/reset unit (CRU), is used to control the configuration of a design under test (DUT), such as frequency regulation and system reset.  
Figure 5 shows the logic view of FPGA implementation of PNX processor. This is also a minimal computing system that facilitate the performance evaluation and optimization. We have omitted some ASIC components that do not necessarily required in the FPGA simulation, such as USB controller. It contains a single PNX processor core with other peripherals connected through on-chip bus. The pipeline structure of PNX processor is shown in Figure 6.  
Management software contains the test manager and result analyzer, which run the host computer for FPGA environment management. The test manager is used to manage the generated FPGA bit files, control the FPGA configurations for several design options, and provide the reset signals for the FPGA system. The result analyzer collects and reports performance data from SD-PMU and PMU. Synplify Pro is used for high-level synthesis, and the Xilinx Vivado design suite is used for placement and routing onto the FPGA device. The system software, which runs on the target processor, consists of the BIOS program, operating system, and related test benchmarks.  
Figure 4: The conceptual block diagram of the FPGA system.  
\begin{table}
\begin{tabular}{c c c} \hline
**Block** & **Unit** & **Configuration** \\ \hline Execution block & Execution units & FPLatency (adder: 3, multiplier: 4), Load/StoreQueue (32) \\  & & SIMDUnitPresence (yes) \\ \hline \multirow{4}{*}{Cache} & L1 ICache & TLBSize (L1: 64, L1D: 64, L2: 1K), pageSize (4K), Size (L1: 32 KB, L1D: 32 KB, L2: 512 KB), \\  & L2 Cache & prefetch\_on\_access (L1I: next-line L1D/L2: stride-based) \\ \hline \end{tabular}
\end{table}
Table 3: _Cont._The FPGA hardware is generally flexible, and most development boards with adequate ASIC gate capacity can be used in FPGA simulation. The hardware comprises one main FPGA board and related peripherals. The main board contains a large FPGA chip, namely, an XCVU440. The main board should also have DDR SO-DIMM on-board sockets, which support large memory. A host computer interacts with the main FPGA boards using a standard ethernet or USB interface. All control functions, such as downloading an FPGA configuration, programming clock generation, self-testing, and running the DUT, are exposed to the users. The peripherals can be designed as daughter boards to the main FPGA boards, which are designed to be reusable to reduce cost. The current configuration has four external boards: a low-speed storage board, which contains a flash and an SD card; a physical (PHY) unit board, which provides ethernet connection with the host machine; an SRAM module board, which expands memory for FPGA implementation; and a GPIO extension board, which contains pin headers, LEDs, push buttons, and a JTAG interface.