## 3 Proposed Algorithm for Fractional-Bit Compensation

Table 2: Maximum conversion errors and percentage errors for the uncompensated first region and last region. Figure 4: Percentage conversion error of [PERSON]’s [3] straight-line \(out=1+f\) and the accurate antilogarithmic curve \(out=2^{\prime}\). The process of optimizing eADP is shown in the flowchart in Figure 5. In the algorithm shown in Figure 3, we first consider the upper bound of each partition region for different fractional bits \(n\). After determining the desired maximum percentage error, the compensation precision for \(2^{-k}\) (\(k=3\), \(4\), \(5\ldots\), \(26\)) is selected and adjusted. In this work, we adopt the Q6.26 format, which contains 6 bits of the integer part and 26 fractional bits. It should be noted that the smaller the partition number and the larger the compensation precision, the smaller the hardware area and the shorter the delay time, respectively. To obtain the truth table for the compensation bits, MATLAB software R2017b is used to simulate the percentage conversion error. Finally, the Karnaugh map is used to simplify the circuit of the truth table. Subsequently, we obtain two regions of the coarse equation for eADP-efficient antilogarithmic converters using fractional-bit compensation schemes. The hardware area and delay time for circuit implementation via very-large-scale integration (VLSI) are obtained using the coarse equation. If the product of error, hardware area, and delay time is larger than the desired target, then the process is repeated until the desired value is achieved. After the fine-tuning process, the eADP-efficient antilogarithmic converter using fractional-bit compensation schemes is designed. According to the above algorithm, we propose three different specifications for eADP-efficient antilogarithmic converters using fractional-bit compensation schemes. We denote the three equations as case 1, case 2, and case 3. For \(n=3\) (\(m_{-1}\)-\(m_{-3}\)), the maximum  
Figure 5: Flowchart for optimization of eADP in the range \(0\leq\)\(f\)\(<1.0\). percentage error is larger (3.1427%), so it is not used in the proposed algorithms. First, we use \(n=4\) (\(m_{-1}\)-\(m_{-4}\)) to give sixteen regions and the compensation values of \(2^{-4}\), \(2^{-5}\), \(2^{-6}\), and \(2^{-7}\), considering the hardware cost and latency. Note that \(2^{-1}\), \(2^{-2}\), and \(2^{-3}\) are not used, owing to their larger step compensation values. Table 3 shows the truth table and compensation bits for case 1. The corresponding partition regions and compensation values are shown in Table 4. After simplification of the Karnaugh map from Table 3, the proposed equation of the eADP-efficient antilogarithmic converter is given by Equation (10). The maximum percentage error of case 1 is 1.9089%. \[out=2^{f}\approx\left\{ \begin{array}{ll}[1+f-(\frac{(f_{-2}\wedge f_{-3}) \vee(f_{-2}\wedge(f_{-3}\oplus f_{-4}))}{16}\\ +\frac{(f_{-2}\wedge f_{-3})\vee(f_{-2}\wedge f_{-3}\wedge f_{-4})}{32}+\frac{( f_{-2}\wedge f_{-4})\vee(f_{-2}\wedge f_{-3}\wedge f_{-4})}{64})],\ 0\leq f<0.5;\\ [1+f-(\frac{f_{-2}}{16}+\frac{f_{-2}\wedge f_{-3}}{32}+\frac{f_{-2}\wedge f_{ -3}\wedge f_{-4}}{64}+\frac{f_{-2}\wedge f_{-3}}{128})],\ 0.5\leq f<1;\\ \end{array} \right. \tag{10}\]  
Table 5 shows the truth table and compensation bits for case 2. The corresponding partition regions and compensation values are shown in Table 6. After simplification of the Karnaugh map from Table 5, the proposed equation of the eADP-efficient antilogarithmic converter is given by Equation (11). The maximum percentage error of case 2 is 1.7330%. \[out=2^{f}\approx\left\{