## Appendix A Effects of the VSC Switches on Maximum Switching Frequency  
MOSFETS are widely used in applications that require higher power density and efficiency due to their higher switching speeds and lower losses [38; 39]. Irrespectively, increasing the switching speed naturally induces oscillations, higher frequency harmonics, voltage and current overshoots and even more loses. This challenges the use of the MOSFET in power converters, VSCs and active harmonic filters under supraharmonic frequency applications. The power MOSFET can be modeled as in Figure 11a which shows the parasitic capacitors; gate-to-source capacitor, \(C_{gs}\), gate-to-drain capacitor, \(C_{gd}\), and drain-to-source capacitor, \(C_{ds}\) of a power MOSFET. The gate of the MOSFET is insulated from the substrate; hence, an initial gate current, \(I_{g}\), is needed to charge both \(C_{gs}\) and \(C_{gd}\) to turn on the MOSFET. To turn off the MOSFET, the gate drive must be bi-directional to conduct/sink current away from the gate [40; 41; 42; 43; 44]. From Figure 11 and considering the initial switching-on stage, the parasitic input capacitances, (\(C_{gs}+C_{gd}\)), are charged through the gate resistor, \(R_{g}\), for a period of T\({}_{1}\). The total time delay is dependent on the input capacitance and the logarithmic function of the gate voltage and its threshold. This can be expressed as shown in Equation (A1). \[T_{1}\approx R_{g}\Big{(}C_{gs}+C_{gd}\Big{)}\ln\left(\frac{V_{gs}}{V_{gs}-V_{gsT }}\right)\] (A1)  
The second stage requires raising \(V_{gs}\) above the miller plateau. At this stage, the transistor is unblocked and experiences feedback from \(C_{gd}\). The drain voltage drops to its minimum as the drain current increases to its maximum. The total charge, \(Q_{tot3}\), and the equivalent charge, \(C_{\alpha\prime}\), required through this stage are estimated as Equation (A2) and Equation (A3), respectively. The total delay can be estimated as \(T_{2}\) in Equation (A5) [45]. \[Q_{tot3}=V_{gs}C_{gs}+C_{gd}\big{(}V_{gs}+V_{dd}\big{)}\] (A2)  
\[C_{eq}=\frac{Q_{tot3}}{V_{gsmax}}=C_{gs}+C_{gd}\bigg{(}1+\frac{V_{dd}}{V_{gsmax }}\bigg{)}\] (A3)  
\[\frac{V_{dd}}{V_{gsmax}}=miller\,effect\] (A4)  
\[T_{2}\approx 0.8C_{gd}\frac{R_{g}\big{(}V_{dd}-V_{dsmin}\big{)}}{V_{gs}-V_{gsT} \big{(}V_{dd}+V_{dsmin}\big{)}/2R_{d}S}\] (A5)  
For \(S:\ \Delta I_{d}/\Delta V_{gs}\)  
In the third stage, the \(V_{ds}\) drops to its minimum, and the MOSFET is driven in full enhancement mode, and the total time duration is \(T_{3}\) in Equation (A6). \[T_{3}\approx 3R_{g}\Big{(}C_{gs}+C_{gd}\Big{)}\] (A6)\(T_{1}\)+ \(T_{2}\)+ \(T_{3}\) makes up the total turn on time of the MOSFET, \(T_{on}\). \[T_{on}=\frac{1.6C_{gg}R_{g}R_{g}V_{dd}S}{2V_{gs}R_{d}S-V_{gsT}V_{dd}}+R_{g}\Big{(} 3+\ln\Big{(}\frac{V_{gs}}{V_{gs}-V_{gsT}}\Big{)}\Big{)}\Big{(}C_{gs}+C_{gd}\Big{)} \tag{11}\]  
At  
\[V_{dsmin}\approx 0\]  
The total required gate current to turn on the MOSFET can be calculated as shown in Equation (10). \[i_{g}=\frac{C_{eq}V_{gsmax}}{T_{on}} \tag{12}\]  
The next stage is from \(t_{4}\)-\(t_{5}\), which is characterized by constant values of currents and voltages and equivalent to the saturation stage of a bipolar transistor. The gate current remains zero during \(t_{4}\)-\(t_{5}\) when the MOSFET is fully on. No charge is required to keep it on. The fifth stage begins the turn-off stage of the MOSFET. The gate pulse signal becomes zero, and the turn-off sequence is initiated. When the input pulse signal drops to zero, the capacitance \(C_{gs}+C_{gd}\) begins to be discharged. It is most important for the appropriate gate driver to be bi-directional. The total time required to discharge can be calculated as Equation (11). \[T_{4}=R_{g}\Big{(}C_{gs}+C_{gd}\Big{)}\ln\bigg{(}\frac{V_{gs}}{V_{diss}}\bigg{)} \tag{13}\]  
where the discharge voltage is given as Equation (12). \[Q_{tot3}=V_{gs}C_{gs}+C_{gd}\big{(}V_{gs}+V_{dd}\big{)}\]0  
The MOSFET is discharged from the ohmic region to the off state. The drain-to-source voltage is increased during this time.