## 4 Derivation of the Hybrid Compact Systolic Multiplier
### The Explored Multiplier Layout
Furthermore, control signal \(q\) is broadcast to all PEs and must remain active every \(r\) clock cycles to enable the \(h\) outputs to pass through the tri-state buffers to the XOR gates located at the outputs of each PE, as illustrated in Figure 3.  
Ultimately, the final output bits of \(h_{j}\), for each \(j\) ranging from 1 to \(r\), are delivered in parallel through latches \(D_{h}\) at the outputs of the systolic array after a duration of \(3r\) clock cycles, as depicted in Figure 3.  
The operation of the examined hybrid systolic multiplier structure can be outlined through a series of systematic steps, each of which contributes to the overall functionality of the design, as detailed below. 1. In the initial clock period, the latches \(D_{h}\) are reset to zero (\(D_{h}=0\)), ensuring that the input bits of \(h_{j}\), for \(j\) ranging from 1 to \(r\), are initialized appropriately at the inputs of the XOR gates located both within and outside each processing element. This initialization is critical for maintaining data integrity, as depicted in Figures 3-5. Figure 5: PE\({}_{j}\) logic diagram overview. Concurrently, the control signal \(c\) is activated (\(c=1\)), allowing the input signals \(e_{j-1}\) to pass through the input port \(e_{in}\) of the regular PEs (PE\({}_{j}\)), where \(j\) is within the range from 1 to \(r\). This enables the utilization of these signals within each processing element. Additionally, during this clock period, control signals \(c_{1}\) and \(c_{0}\) are deactivated (\(c_{1}=0\) and \(c_{0}=0\)), permitting the first bits of the \(e_{r-i+1}\) and \(f_{i}\) signals, for \(i\) ranging from 1 to \(r\), to traverse the input ports \(e_{a}\) and \(f_{a}\) of the first PE (PE\({}_{1}\)). 2. From the second clock period up to the \(r^{th}\) clock period, control signal \(c\) is deactivated (\(c=0\)), allowing the sequential passage of signals \(e_{r-i+1}\) through the input port \(e_{s}\) of the regular PEs (PE\({}_{j}\)). This step is essential for their effective use within each processing element. During this interval, control signals \(c_{1}\) and \(c_{0}\) remain deactivated (\(c_{1}=0\) and \(c_{0}=0\)), facilitating the passage of all remaining sequential bits of the \(e_{r-i+1}\) and \(f_{i}\) signals through the input ports \(e_{a}\) and \(f_{a}\) of the first PE (PE\({}_{1}\)), thereby ensuring their availability for processing. 3. Upon completing the first \(r\) clock cycles, control signal \(q\) is activated (\(q=1\)), enabling the transfer of the intermediate bits of \(h\) to the accumulator, which comprises XOR gates and \(D_{h}\) latches positioned at the output of each PE, as illustrated in Figure 3. These accumulated bits are stored in the \(D_{h}\) latches and are intended to be combined with the output bits generated after the next set of \(r\) clock cycles, marking the beginning of the second operational phase of the systolic array. 4. Following the completion of the first \(r\) clock cycles, the systolic array transitions into a second computation phase. At the first clock cycle of this phase, the latches \(D_{h}\) within each PE are reset to initialize the input bits of \(h_{j}\), for \(j\) ranging from 1 to \(r\), to zero at the inputs of the XOR gates, as shown in Figures 4 and 5. Simultaneously, control signal \(c\) is activated (\(c=1\)) to facilitate the utilization of zero input signals assigned to input port \(e_{in}\) within each regular PE (PE\({}_{j}\)). During this clock period, control signals \(c_{1}\) and \(c_{0}\) are set to 1 and 0, respectively (\(c_{1}=1\) and \(c_{0}=0\)), allowing the first bits of the \(e_{i-1}\) and \(f_{i}\) signals, for \(i\) ranging from 1 to \(r\), to pass through the input ports \(e_{b}\) and \(f_{b}\) of the first PE (PE\({}_{1}\)). 5. From the second clock period until the \(r^{th}\) clock period of the second computation phase, control signal \(c\) is deactivated (\(c=0\)), enabling the sequential passage of signals \(e_{i-1}\) through the input port \(e_{s}\) of the regular PEs (PE\({}_{j}\)).