# A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA
## 5 Implementation Results and Comparison
### Comparison with the State of the Art  
We compare the implementation of our unified accelerator architecture with state-of-the-art accelerators in Table 4. Column one provides the reference of the implemented design (Ref). The implemented curve and the corresponding PM algorithm are presented in columns two to three. Column four shows the type (either dedicated or flexible/unified) of the implemented design. The field size \(m\) is shown in column five. The implementation device for logic synthesis and place-and-route steps is illustrated in column six. The area information is provided in columns seven to eight. We show the timing results, frequency of the circuit, and information about the latency in the last three columns (nine to eleven) of Table 4.  
Comparison with dedicated designs of Weierstrass curve [9; 10]The comparison to dedicated designs of [9; 10] shows that our unified accelerator utilizes more FPGA resources in slices and LUTs. The reason is the flexibility in our design to support three different ECC curves, i.e., Weierstrass, Edward, and Huff. In contrast, the dedicated designs of [9; 10] are specific to Weierstrass curve implementation on Virtex-7 FPGA. As shown in column eight of Table 3, comparing clock cycle utilization is impossible as the related data are unavailable in the reference designs. On the same Virtex-7 FPGA device, our unified accelerator can  
\begin{table}
\begin{tabular}{l l l l l l l l l l l} \hline \hline \multirow{2}{*}{**Ref**} & **Implemented** & \multirow{2}{*}{**PM Algorithm**} & \multirow{2}{*}{**Design**} & \multirow{2}{*}{**m**} & \multirow{2}{*}{**Device**} & \multirow{2}{*}{**Slices**} & \multirow{2}{*}{**LUTs**} & \multirow{2}{*}{**Cycles**} & **Freq** & **Lat** & **Thrtp** \\  & & & & & & & & & & & **kops** \\ \hline
[9] & Weierstrass & Montgomery & Dedicated & 233 & Virtex-7 & 2647 & 7895 & – & 370 & 16.01 & 62.46 \\
[10] & Weierstrass & Montgomery & Dedicated & 233 & Virtex-7 & 2048 & 6407 & – & 379 & 14.25 & 70.15 \\
[19] & Weierstrass & Montgomery & Flexible & 233 & Virtex-6 & – & 116,241 & 2609 & 135 & 19.33 & 51.73 \\
[14] & Edward & Double and & Dedicated & 256 & Virtex-6 & 6600 & – & – & 93 & 2130 & 0.47 \\
[14] & Edward & Double and & Dedicated & 256 & Virtex-7 & 6500 & – & – & 104 & 1900 & 0.53 \\
[12] & Edward & Montgomery & Dedicated & 256 & Virtex-6 & 9246 & 33,238 & 262,650 & 161 & 1630 & 0.61 \\
[12] & Edward & Montgomery & Dedicated & 256 & Virtex-7 & 8873 & 32,781 & 262,650 & 178 & 1480 & 0.67 \\
[15] & Edward & Montgomery & Dedicated & 233 & Virtex-6 & 1245 & 3878 & 718,805 & 107 & 6720 & 0.15 \\
[16] & Edward & Montgomery & Dedicated & 233 & Virtex-7 & 2662 & 24,727 & 3244 & 179 & 18.10 & 55.24 \\
[17] & Huff & Double and & Dedicated & 233 & Virtex-7 & 7017 & – & 13,057 & 434 & 30.08 & 33.24 \\
[13] & Huff & Module & Dedicated & 233 & Virtex-7 & 7123 & – & 15,495 & 188 & 82.4 & 12.13 \\
[18] & Weierstrass & Montgomery & Duolite and & Unified & 233 & Virtex-7 & 8866 & 23,017 & 5635 & 271 & 20.78 & 48.12 \\  & Huff & Add & & & & & & & 12,554 & & 46.32 & 21.58 \\ \hline \multirow{4}{*}{TW} & Weierstrass & Montgomery & & & & & & & 3607 & & 14.60 & 68.49 \\  & Edward & Montgomery & Duolite and & Unified & 233 & Virtex-6 & 6109 & 19,869 & 3472 & 247 & 14.05 & 71.17 \\  & Huff & Add & & & & & & 8913 & & 36.08 & 27.71 \\ \cline{1-1} \  
operate at a maximum of 294 MHz, while the designs of [9; 10] can operate at maximum frequencies of 370 and 379 MHz, respectively. This is due to the flexibility considered in our accelerator. Apart from the area and frequency comparison, our unified accelerator requires 1.30 (ratio of 16.01 with 12.26) and 1.16 (ratio of 14.25 with 12.26) times lower computation time as compared to the dedicated architectures of [9; 10], respectively.