## 4 Simulations and Measurements
The comparison results show that the mixer has excellent \(IP_{1 dB}\) and \(OP_{1 dB}\) performance, which is benefited from the use of the \"uplift reverse\" phenomenon. _FOM_ and \(FOM_{IF}\) are introduced to measure the overall performance, which are expressed as follows. \[FOM=10 log_{10}\left(\frac{10^{\frac{CC|dB|}{20}}\times 10^{\frac{IP_{1 dB}| dBm|}{10}}}{P_{DC}[W]\times 10^{\frac{IP_{1 dB}| dBm|}{10}}}\right) \tag{15}\]  
\[FOM_{IF}=10 log_{10}\left(\frac{10^{\frac{CC|dB|}{20}}\times 10^{\frac{IP_{1 dB}| dBm|}{10}}\times IFBW[GHz]}{P_{DC}[W]\times 10^{\frac{IP_{1 dB }| dBm|}{10}}}\right) \tag{16}\]  
It should be noted that the \(IP_{1 dB}\) in [6] and [19], and the \(OP_{1 dB}\) in [4; 16], and [20; 21; 22; 23], are calculated by Equation (17). The \(IP_{1 dB}\) in [4] is calculated by Equation (18). The \(CG\) in [18] refers to voltage conversion gain. Additionally, all data in the third column of Table 5 satisfy Equation (19). \[OP_{1 dB}[dBm]=IP_{1 dB}[dBm]+CG[dB]-1 \tag{17}\]  
\[IP_{1 dB}[dBm]=IIP_{3}[dBm]-9.6 \tag{18}\]  
\[S_{11}<-10\;dB \tag{19}\]  
For 5G communication systems, the improvement in the \(IP_{1 dB}\) enhances the capability of anti-blocking. A high \(IP_{1 dB}\) can effectively prevent the system from entering a saturated state when facing a large interference signal. At the same time, in the receivers, the realization of the high linearity mixer can reduce the design difficulty of other circuits, which is beneficial to the improvement of the overall performance. The mixer achieves higher \(IP_{1 dB}\) and \(OP_{1 dB}\) than any other work in this frequency band, including many passive mixers, showing an excellent linearity performance. At the same time, it achieves an IF bandwidth of 8 GHz under a silicon-based process with a relative bandwidth of 114%. The overall layout is compact, and the power consumption is moderate. The \(FOM\) reaches 24.73, the \(FOM_{IF}\) reaches 33.76; both show that the mixer has excellent overall performance. \begin{table}
\begin{tabular}{c c c c c c c c c c c c c c} \hline \hline
**Ref. ** & **Process** & \begin{tabular}{c} **RF Freq.** \\ **(GHz)** \\ \end{tabular}  & \begin{tabular}{c} **IF Bandwidth** \\ **(GHz)** \\ \end{tabular}  & \begin{tabular}{c} **LC Power** \\ **(dBm)** \\ \end{tabular}  & \begin{tabular}{c} **CC** \\ **(dBm)** \\ \end{tabular}  & \begin{tabular}{c} **IP\({}_{1\mu}\)** \\ **(dBm)** \\ \end{tabular}  & \begin{tabular}{c} **OP\({}_{1\mu}\)** \\ **(dBm)** \\ \end{tabular}  & \begin{tabular}{c} **SSB NF** \\ **(dBm)** \\ \end{tabular}  & \begin{tabular}{c} **LO-RF** \\ **(dBm)** \\ \end{tabular}  & \begin{tabular}{c} **Pic** \\ **(dBm)** \\ \end{tabular}  & \ \begin{tabular}{c} **Chip Area** \\ **(mm\({}^{3}\))** \\ \end{tabular}  & **FOM** & \begin{tabular}{c} **FOM\({}_{\text{MB}}\)** \\ \end{tabular}  \\ \hline
[4] & \begin{tabular}{c} 45 mm \\ CMOS SOI \\ \end{tabular}  & 23–33 & 4 & 2 & \(-\)3.5 & \(-\)0.2 & \(-\)4.7 & 15.3 & 31 & 24 & 0.78 & 12.25 & 18.27 \\
[6] & \begin{tabular}{c} 180 mm \\ CMOS \\ \end{tabular}  & 23–25 & N/A & 5 & \(-\)4.5 \(\pm\) 0.6 & \(-\)4.9 & \(-\)11 & N/A & N/A & 16 & 0.72 & 6.11 & N/A \\
[14] & \begin{tabular}{c} 90 mm \\ CMOS \\ \end{tabular}  & 35–83 & N/A & 1 & \(-\)1 \(\pm\) 1.5 & 0 & \(-\)2 & N/A & \(-\)30 & 6.5 & 0.54 & 21.32 & N/A \\
[18] & \ \begin{tabular}{c} 65 mm \\ CMOS \\ \end{tabular}  & 25-28.5 & 1.5 & 3 & \(172\pm 0.2\) & N/A & N/A & \( \begin{tabular}{c} 112.29.4 \\ (DSB) \\ \end{tabular}  & \(-\)48 & 7.1 & 0.88 & N/A & N/A \\
[19] & \begin{tabular}{c} 180 mm \\ SciGe BCMOS \\ \end{tabular}  & 2–67 & 0.59 & 0 & \begin{tabular}{c} 25.5 \(\pm\) 1.4 \\ (20-67 GHz) \\ \end{tabular}  & \begin{tabular}{c} -74 \\ (\#0 GHz) \\ \end{tabular}  & \ \begin{tabular}{c} -5.4 \\ (\#0 GHz) \\ \end{tabular}  &
\begin{tabular}{c} -5.