# Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications
## 2 Materials and Methods  
Each convolution layer input in the CNN is the features maps set \(\mathcal{F}\in\mathbb{R}^{M_{m}^{(l)}\times N_{m}^{(l)}\times CH^{(l)}}\) that is processed through the filters \(\mathcal{K}\in\mathbb{R}^{w^{(l)}\times w^{(l)}\times CH^{(l)}\times K^{(l)}}\) for generating a new feature maps set \(\mathcal{G}\in\mathbb{R}^{M_{out}^{(l)}\times N_{out}^{(l)}\times K^{(l)}}\) (Figure 1). The convolutional layer is represented by the index \(l\). \(\mathcal{K}(x,y,ch,k)\) represents the filter set that processes the features maps set \(\mathcal{F}(x,y,ch)\), and each convolution layer must be computed by \(K\) filters. The CNN elements' dimensions for each layer are depicted in Figure 1, where \(w\times w\times CH\) represent the \(k\) filters dimension, and \(w\) is typically odd. The Algorithm 1, with an optional interchange in the two external loops (\(CH\) and \(K\)), represents a convolution computing starting point, which has been considered in many state-of-the-art works [10; 44; 45]. The loop interchange, unrolling, or modification has effects on the hardware implementation technique. This standard algorithm is not modified in this work and is taken as a reference for the proposed convolver validation. Thus, a higher priority to the operations acceleration in the inner loops is given, and less priority to the outermost loop parallelism. The _Stride_ (\(S\)) and _Padding_ (\(P\)) parameters in the convolution layer are essential for data processing [46]. The former is helpful to avoid the whole input image being processed by the filter kernels, resulting in a dimension reduction of the resulting features maps set. The latter parameter helps to maintain the same image size regarding the obtained output feature maps, whose size is given by:  
\[N_{out}^{(l)}=M_{out}^{(l)}=\frac{N_{m}^{(l)}+(2\times P)-w^{(l)}}{S}+1. \tag{1}\]  
In general, a convolution layer is followed by a subsampling operation, where the size of the resulting convolution layer image is reduced through the computation of the maximum or average value of a specific image region. The most commonly used pooling methods are: _Maxpooling_ and _Meanpooling_ defined respectively by:  
Figure 1: Elements’ dimensions for the convolution process. \[\mathcal{G}(x,y,ch)=\sum_{s=0}^{p-1}\sum_{t=0}^{p-1}\frac{1}{p^{2}}\mathcal{F}((x^ {\prime}S)+s,(y^{\prime}S)+t,ch), \tag{2}\]  
\[\mathcal{G}(x,y,ch)=max(\mathbf{f}(ch)), \tag{3}\]  
where \(\mathbf{f}\in\mathbb{R}^{w(l)\times w(l)\times CH^{(l)}}\) is a convolution mask of \(\mathcal{F}\) whose position in \(\mathcal{F}\) is \((x^{\prime},y^{\prime})\), having as origin the upper left pixel, and subsampling window dimension \(p\). \(x\) and \(y\) are in the range \([0,M_{out}]\) whereas \(x^{\prime}\) and \(y^{\prime}\) have a range \([0,M_{in}]\). In most cases, a Fully Connected Network (FCN) is the CNN last data processing stage, where a class (represented as \(C\)) is assigned to the resulting feature maps set (\(\mathbf{x}\)) corresponding to the previous layer. The set \(\mathbf{x}\) represents the classification stage input. An FCN has \(n_{l}\) layers, where \(L_{1}\) and \(L_{nl}\) are the input and output layers, respectively. The \(l_{th}\) layer has \(Sl\) neurons, whereas the layer \(L_{nl}\) has \(C\) neurons equal to the number of FCN classes. The \(i_{th}\) neuron activation on \(l_{th}\) layer is denoted as \(a_{i}^{(l)}\). This activation is given by the function \(f(z_{i})\), where \(z_{i}\) is the weighted sum of the input data values: \(x_{1},x_{2},\ldots,x_{n}=\mathbf{x}\) plus the bias term \(x_{0}=1\); therefore, \(z_{i}=x_{0}w_{i0}+x_{1}w_{i1}+\ldots+x_{n}w_{in}\). The addition of the term \(x_{0}w_{i0}\) defines the \(f(z_{i})\) as a nonlinear function. The following layer activation \(a_{i}^{l+1}\) is defined as:  
\[a_{i}^{l+1}=f(z_{i}^{l+1})=f(\sum_{j=1}^{n}w_{ij}^{(1)}x_{j}+b_{i}^{l}). \tag{4}\]  
A matrix of PEs is the core of a Systolic array (SA), each composed of a multiplier and accumulator module with internal registers.