## 4 Results  
In this section, simulation results from the FPGA design are discussed. A stimulus is necessary to test the hardware inferred in VHDL code. Using MATLAB, a contiguous random sequence of bits was stored in an input text file. Then, a testbench was coded in VHDL to read the input generated by MATLAB, apply the stimulus to the logical design, and save the output in another TXT file named \"TX_out.txt\". It is important to mention that the VHDL testbench feeds the input to the transmitter using a slave AXI-stream interface and fetches the output with the help of a master AXI-stream [10]. To verify whether results are correct, one needs to have an available software-output reference stored within another TXT file named \"SW_out.txt\". This is obtained by modeling the system in MATLAB. Therefore, the two TXT output files containing the software and hardware outputs are compared in Figure 20. Here, each 14-bit pattern encodes a complex symbol from the physical layer frame in fixed-point format. Since both outputs are identical, this justifies that the system is working as expected. To further illustrate the system behavior, a snapshot of 8 used from a timing diagram is presented in Figure 21. A timing diagram shows the transitions of all digital signals in the hardware at any time; nevertheless, in Figure 21, we only include the input/output signals of interest to the whole design. These signals are explained below. * tb_aclk (IN) 2 MHz input clock;
* tb_areston (IN) synchronous active-low reset;
* s_axis.tdata (IN) contains input data to feed into the device. * s_axis.tvalid (IN) if '1' then the s_axis.tdata signal is considered valid;
* s_axis.ready (OUT) is set to '1' when the device is ready to process the data. * s_axis.enable (IN) = s_axis.tvalid and s_axis.tready, signals a valid transfer of data to the device;
* t_rline timer to count the number of lines read from the input file;
* reading_done set to '1' when the input file has been read;
* m_axis.tdata (OUT) contains output data generated by the device;
* m_axis.tvalid (OUT) is set to '1' when the input data m_axis.tdata signal is considered valid;
* m_axis.tready (IN) if '1', then the next device paired to the master interface is waiting to receive data;
* m_axis.enable (OUT) = m_axis.tvalid and m_axis.tready, indicates correct data transfer through the master interface;  
Figure 19: PART III—physical layer frame RTL block diagram. t_wline timer to count the number of lines written in output file;
* writing_done set to '1' when all output data have been captured in output TXT file. One might notice how input data in _s_axis._data_ are always valid since the transmitter is ready on every clock cycle. The signal _m_axis._ready_ is randomly generated within the testbench with the unique purpose of making the behavioral simulation more random to identify any possible bug. As stated in the AXI4-stream protocol, whenever there is a valid output datum in the master interface, i.e., _m_axis._tvalid_ ='1', the control logic must not change the signal _m_axis._tvalid_ until the downstream component samples _m_axis._data_. This behavior is crucial for data transfer to properly work, otherwise data could be overwritten and lost forever. This is the reason why the signal _m_axis._data_ in Figure 21 stretches over many clock cycles just until _m_axis._enable_ transitions back to '1'. In a similar way,  
Figure 20: MATLAB output for the first 41 symbols of a PL frame. the counter \(t\_rline\) increases whenever \(s\_axis.enable=^{\prime}1^{\prime}\) and \(t\_wline\) increases when \(m\_axis.enable=^{\prime}1^{\prime}\). Finally, a resource utilization chart obtained by synthesis simulation is presented in Figure 22. An FPGA uses a series of building blocks to create any digital electronic circuit within itself by using configuration logic blocks. These logic blocks are the elemental building blocks of any digital system within an FQPA.