## 4 Analysis of the Basic Unit of GSMLI
### Operating States  
The proposed topology can be utilized in asymmetric and symmetric configurations. Table 2 illustrates the switching states of \(T_{1}\) to \(T_{6}\) and \(S_{1}\)_to_\(S_{4}\), the charging and discharging states of capacitors \(C_{1}\) and \(C_{2}\) in a fastidious switching state. \"C\" and \"D\" indicate that the capacitor is charged and discharged, respectively. \"-\" indicates that there is no change in the states of the capacitors. \"1\" denotes the on state of switches, while \"0\" denotes the off state of switches.  
When both DC voltage sources have the same magnitude (\(V_{1}=V_{2}\)), then it is operated in symmetric configuration and produces 9 levels in \(0V,\pm V_{1},\pm(V_{1}+V_{C1}),\pm(2V_{1}+V_{C1})\), and \(\pm(2V_{1}+V_{C1}+V_{C2})\) output voltage waveform, which can be seen from Table 2. From Table 2, it can be observed that more levels are generated when both voltage sources have different magnitudes of voltage, i.e., asymmetric configuration.  
To generate the maximum available voltage levels, it must be operated in asymmetric configuration and the magnitude of DC voltage sources \(V_{1}\) and \(V_{2}\) must be selected in a 1:3 ratio. When it is operated in asymmetric configuration (\(3V_{1}=V_{2}\)), it produces 17 levels (\(0V,\pm V_{1},\pm(V_{1}+V_{C1})\), \(\pm 3V_{1}\), \(\pm 4V_{1}\), \(\pm(4V_{1}+V_{C1})\), \(\pm(3V_{1}+V_{C2})\), \(\pm(4V_{1}+V_{C2})\), and \(\pm(4V_{1}+V_{C1}+V_{C2})\)) in output voltage waveform, as shown in Table 2.  
Figure 3: Conducting path for positive half-cycle modes.  
Total standing voltage (\(TSV\)) is one of the most important parameters while designing different inverter topologies. \(TSV\) is defined as the sum of the maximum blocked voltage (stress) across the semiconductor switches and diodes when the output voltage of all possible levels is generated at the output.  
The maximum value of blocked voltage across each switch in symmetric configuration (\(V_{1}=V_{2}=V\)) is given as  
\[V_{T1}=V_{T2}=2V_{1}=2V,V_{T3}=V_{T4}=2V_{2}=2V\]  
\[V_{T5}=V_{T6}=2(V_{1}+V_{2})=4V,V_{S1}=V_{S2}=V_{1}=V\]  
\[V_{S3}=V_{S4}=V_{2}=V,V_{D1}=V_{1}=V,V_{D2}=V_{2}=V\]  
where \(V_{T1}\), \(V_{T2}\), \(V_{T3}\), \(V_{T4}\), \(V_{T5}\), \(V_{T6}\), \(V_{S1}\), \(V_{S2}\), \(V_{S3}\), \(V_{S4}\), \(V_{D1}\), and\(V_{D2}\) are the blocked voltages across switches \(T_{1}\), \(T_{2}\), \(T_{3}\), \(T_{4}\), \(T_{5}\), \(T_{6}\), \(S_{1}\), \(S_{2}\), \(S_{3}\), and \(S_{4}\) respectively.  
\[TSV=V_{T1}+V_{T2}+V_{T3}+V_{T4}+V_{T5}+V_{T6}+V_{S1}+V_{S2}+V_{D1}+V_{S3}+V_{D2 }+V_{S4}=22V\]  
\[TSV\) in per unit is defined as  
\[TSV_{p.u.}\ =\ \frac{TSV}{V_{o,max}}\]  
where \(V_{o,max}\) is the maximum value of output voltage  
\(TSV_{p.u}\) in symmetric configuration is given as  
\[TSV_{p.u.}\ =\ \frac{22V}{4V}\ =\ 5.5\]  
The maximum value of the blocked voltage across each switch in asymmetric configuration (\(V_{1}=V\) and \(V_{2}=3V\)) is given as  
\[V_{T1}=V_{T2}=2V_{1}=2V,V_{T3}=V_{T4}=2V_{2}=6V\]  
\[V_{T5}=V_{T6}=2(V_{1}+V_{2})=8V,V_{S1}=V_{S2}=V_{1}=V\]  
\[V_{S3}=V_{S4}=V_{2}=3V,V_{D1}=V_{1}=V,V_{D2}=V_{2}=3V\]  
\[TSV=44V\]  
\begin{table}
\begin{tabular}{c c c c c c c c c c c} \hline \hline
**States** & **Output** & \(\frac{S_{1}\,\mathbf{or}}{S_{2}}\) & \(\frac{S_{3}\,\mathbf{or}}{S_{4}}\) & \(\frac{T_{1}\,\mathbf{or}}{T_{2}}\) & \(\frac{T_{3}\,\mathbf{or}}{T_{4}}\) & \(\frac{T_{5}\,\mathbf{or}}{T_{6}}\) & \(\frac{T_{7}\,\mathbf{or}}{T_{8}}\) & \(\mathbf{C_{1}}\) & \(\mathbf{C_{2}}\) & \\(TSV_{p,u}\) in asymmetric configuration is given as  
\[TSV_{p,u}\ =\ \frac{44V}{8V}\ =\ 5.5\]