## 5 Implementation
### Sdr2
\begin{table}
\begin{tabular}{c c c c c c c} \hline
**Slice LUTs** & **Slice Regs** & **F7/F8 Muxes** & **Slice** & **LUT as Logic/Memory/FFs** & **BRAMs** & **DSPs** & **Bonded IOB/IOPADs** \\
**(218,600)** & **(437,200)** & **(109,300/54,650)** & **(54,650)** & **(218,600/70,400/218,600)** & **(545)** & **(900)** & **(362/130)** \\ \hline
29,296 & 37,628 & 591/24 & 13,174 & 25,961/3335/13,390 & \(18\) & \(71\) & \(223/130\) \\ \hline \end{tabular}
\end{table} 
Table 1: Implementation results of the SDR1 FPGA design where the maximum values of the FPGA resources per category are quoted in parentheses. ReproRun and a single embedded microprocessor running RTOS. However, such redesign falls beyond the scope of this paper. The access to the DDR3 memory of the SDR1 had to be shared among the RFNoC and ReproRun without generating any read or write conflicts. This was made feasible by using an AXI Interconnect IP core of Xilinx and adjusting the memory-mapped address ranges for each of the two SDRAM accesses. Hence, the existing MIG [43] configuration of the RFNoC Verilog firmware was reutilized and suitably modified. As already mentioned before, the PRC IP provides management functions for the PR designs. Upon a trigger event initiated in the PL or PS, the PRC fetches partial bitstreams from an external memory and delivers them to the ICAP. The PRC also assists with logical decoupling and startup events, customizable per reconfigurable partition. By default, the PRC operates with RM known a priori to the controller. An AXI4-Lite register interface allows the core to be reconfigured at run-time, which means that the PRC can also be used in systems where the RMs could change at run-time. The core can be customized for a number of RMs per Virtual Socket and interface. The PRC in SDR2 was configured in the same way we did so in the case of SDR1. The Vivado block design of the SDR2 with the key building blocks of ReproRun is shown in Figure 7 (e.g., MicroBlaze, PRC, and AXI 1G/2.5G Ethernet Subsystem IP cores). The shared access to the SDR2 SDRAM takes place in two nested Vivado block designs. Other parts of ReproRun include blocks developed in Verilog code and a series of modifications applied to the native RFNoC Verilog source code. The static FPGA design (static bitstream) is the combination of the modified RFNoC Verilog firmware and the HDL code of ReproRun. Two counters were developed to show the uninterrupted operation of the static bitstream (i.e., counting up and down) and their operation was mapped to a Xilinx virtual input-output (VIO) IP core to monitor them in real-time. In order to demonstrate the partial reconfiguration, we have selected the rfnoc_siggen.grc GNU radio companion (GRC) example for RFNoC (Figure 8). This GRC RFNoC example uses a coordinate rotation digital computer (CORDIC) function to produce a sinusoid in the FPGA device of SDR2 and then passes the I and Q samples to the host PC, where the samples are processed and visualized in the GRC project (e.g., time and frequency domain analysis); some user set parameters, such as the digital gain of the signal, can be manually modified from the host PC. The definition of the RR for the partial reconfiguration cannot be applied at the boundaries of the RFNoC blocks. By trying to do so, we noticed that when invoking RFNoC from the host it was not responsive. Hence, the RR had to be defined in one of the DSP functions of an RFNoC computation engine (CE), denoted as User IP in Figure 8. This in turn resulted in several limitations for the PR, when for instance we want to use one RR to run different partial bitstreams (e.g., size of RR, I/O compatibility of the different partial reconfigurable functions targeting the RR). The partial bitstream was produced following the standard PR design guidelines of Xilinx and the instructions for building  
Figure 7: The top-level Vivado Block Design of SDR2. a user-defined RFNoC CE [44]. For the case of the rfnoc_siggen.grc GRC example, we have applied the PR in the CORDIC function residing in this CE.