# Quantum Circuit-Width Reduction through Parameterisation and Specialisation
## 10 Conclusions and Future Work  
Quantum circuit transformation and parameterisation techniques were introduced that specifically target facilitating static analysis of quantum circuits for the purpose of circuit width reduction (reduced qubit count). Using these techniques, quantum circuits which would otherwise require excessive amounts of memory can be analysed on full state vector simulators. The introduced transformation approach can be applied to a wide range of quantum algorithms where quantum arithmetic operations form part of the computational work performed by the algorithm. The transformations are demonstrated for an exemplar quantum integer divider and its constituent parts, the comparators and subtractors. The first step in transformation involves a user-directed replacement of an quantum-circuit block performing arithmetic by a parameterised circuit performing this operation. In the next step, the presented static analysis tool can then automatically eliminate any qubits which are used only as controls for user-specified given inputs. As demonstrated for the integer divider example, using this approach, reductions in quantum circuit width can be achieved that match reductions obtained by manual reduction-by-specialisation.  
While the introduced transformation approach is specific to quantum circuit operations performing arithmetic in the computational basis, it is clear that the specialised circuits can be used as building blocks in larger circuits which go beyond the computational basis. Furthermore, it is important to note that the transformation approach is not limited to the particular tool chain employed here, i.e., it is expected that other tool chains designed to  
\begin{table}
\begin{tabular}{c c c c} \hline  & **Divider** & **Comparator** & **Subtractor** \\ \hline Baseline Circuit Qubit Count & 17 & 9 & 8 \\ Reduced Circuit Qubit Count & 12 & 5 & 4 \\ \hline Baseline Circuit Gate Count & 674 & 49 & 24 \\ Reduced Gate Count (for divisor \(|1001\rangle\) (9)) & 252 & 3 & 14 \\ Reduced Gate Count (for divisor \(|1011\rangle\) (11)) & 296 & 5 & 19 \\ \hline \end{tabular}
\end{table}
Table 3: Summary of circuit specialisation results. The results for the reduced circuit gate count are for specific examples of the divisor being specialised to 9 and 11.  
perform transformations on circuits specified in other DSLs can be extended to include the transformation approach discussed here.  
In future work, the introduced techniques will be extended to a wider range of quantum algorithms with embedded quantum arithmetic operations. Additionally, quantum algorithms for scientific computations using floating-point arithmetic will be targeted.  
**Author Contributions:** Circuit Transformation and Reduction Concepts, R.S.; derivation of Parameterised Comparator, Subtractor, and Divider circuits, R.S.; Project administration and supervision, R.S. and W.V.; Functional Quantum Toolchain, Y.M.; Implementation and validation of circuits, Y.M.; Writing--review and editing, W.V. All authors have read and agreed to the published version of the manuscript.  
**Funding:** This research received no external funding.  
**Institutional Review Board Statement:** Not applicable.  
**Informed Consent Statement:** Not applicable.  
**Data Availability Statement:** The data being made available for this work is in the form of the FQT code which generates and processes the discussed circuits. The code is available on Zenodo: [[https://zenodo.org/record/7645972#.Y-3-6S-11B0](https://zenodo.org/record/7645972#.Y-3-6S-11B0)]([https://zenodo.org/record/7645972#.Y-3-6S-11B0](https://zenodo.org/record/7645972#.Y-3-6S-11B0)) (accessed on 3 February 2023).  
**Acknowledgments:** The authors acknowledge financial support received from the University of Glasgow in the form of a Ph.D. scholarship for Y.M.  
**Conflicts of Interest:** The authors declare no conflict of interest.