## 6 Conclusions  
This paper presents a new layered QC-LDPC decoder architecture that focuses on quickly decoding the longest information length that 5G-NR standards allow. The architecture leverages a low-latency, flexible model with reduced hardware complexity. This complexity reduction is achieved through optimized designs for the internal blocks. Furthermore, we rigorously evaluate the effectiveness of the modified SOLL method for 5G-NR communication. These evaluations demonstrate the efficiency and a positive impact of the modified SOLL method on the decoder's performance. Potentially, this translates to improvements in SNR analysis and a reduction in the number of decoding iterations compared to previous works. The design exhibits broad adaptability by supporting a wide range of expansion factors and BG1 versions. The Virtex-7 XC7 VX980T FPGA platform implements the decoder. The implemented decoder achieves a footprint of 380,737 LUTs and 32,898 registers, which are coupled with a high operating frequency of 304.5 MHz.  
Figure 11: Timing consumed by each block of the decoder (a) and resources utilized by each block of the decoder (b).  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & **This Work** & **[2]** & **[3]** & **[4]** & **[5]** \\ \hline FPGA & Kintex-7 xc7 vx980t & Kintex Ultrasacle+ & Virtex7 xc7 vx690t & Zynq ultrascale+ & xc7 vx690t \\ \hline Max. Freq (MHz) & 304.5 & 153.5 & 261 & 128.36 & 255 \\ \hline Tnorm (Gbps) & 49.5 & - & 31.7 & 13.3 & 31.4 \\ \hline Hardware Usage & 382,786 & 314,968 & 100,929 & 1,200,394 & 103,674 \\ \hline Max. Iter. & 6 & 10 & 11 & 10 & 10 \\ \hline Code Rate & 2/3 & 1/2 & 8/9 & 8/9 & 8/9 \\ \hline Cword Length & 13,440 & 8832 & 10,368 & 10,368 & 10,368 \\ \hline Memory size (kb) & 231.35 & 173.25 & 4368 & 765.8 & 3456 \\ \hline Memory Type & Registers & BRAMS & BRAMs & Registers & BRAMs \\ \hline \hline \end{tabular}
\end{table}
Table 3: Implementation results of the 5G-NR LDPC decoder with a rate of \(2/3\).  
This creates to a favorable balance between decoding latency and hardware complexity, making the architecture suitable for real-time communication applications. The proposed decoder architecture can be used in real life in future IMT-2020 communication standards, as shown by the successful hardware implementation and the potential for better decoding performance.  
I.A. methodology, formal analysis, validation, and supervision; A.A. methodology, formal analysis, validation, supervision, and data curation; B.M. software, conceptualization, formal analysis, data curation, and writing--original draft preparation. All authors have read and agreed to the published version of the manuscript.  
This research received no external funding.  
**Institutional Review Board Statement:** Not applicable.  
**Informed Consent Statement:** Not applicable.  
**Data Availability Statement:** The data that support the findings of this study were obtained at the Engineer Sciences Laboratory from the Polydisciplinary Faculty of Taza, University Sidi Mohamed Ben Abdellah (USMBA), Fez. They are available upon reasonable request. Data sharing is subject to ethical and privacy considerations. Do not hesitate to contact [PERSON] at [EMAIL_ADDRESS] for inquiries regarding data access and availability.  
**Acknowledgments:** The author would like to express his deepest gratitude to his research supervisors [PERSON] and [PERSON] for their invaluable guidance, insightful critiques, and unwavering support throughout this research. A special appreciation is owed to the Laboratory of Engineer Sciences for providing the necessary facilities and resources.  
**Conflicts of Interest:** The authors declare no conflict of interest.