## 4 Simulation Verification
### Verification of Power Coordinated Control  
To verify the capability of the proposed PET to run stably and coordinate the control of the power distribution of all ports when the power demand of the output stage changes, the following settings are introduced:  
1. At \(t<2\) s, the reactive power \(Q\) at the input stage is set to 0, and the active power of AC port (\(P_{1}\)) and DC port (\(P_{2}\)) at the output stage are 3 MW and 1 MW, respectively; \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Value** \\ \hline Grid-side filter inductance \(L_{\mathrm{S}}/\mathrm{mH}\) & 20 \\ Grid-side filter resistance \(R_{\mathrm{S}}/\mathrm{\Omega}\) & 0.1 \\ Arm inductance \(L_{0}/\mathrm{mH}\) & 8 \\ SM capacitance \(C_{\mathrm{SM}}/\mathrm{\mu F}\) & 750 \\ DC side voltage \(U_{\mathrm{dc}}/\mathrm{kV}\) & 60 \\ Virtual inertia of VSM \(J/(\mathrm{kg}\cdot\mathrm{m^{2}})\) & 0.3 \\ Virtual damping of VSM \(D/(\mathrm{N}\cdot\mathrm{m}\cdot\mathrm{s}/\mathrm{rad})\) & 10 \\ Voltage control coefficient \(k_{\mathrm{v}}\) & 0.2 \\ Reactive power control coefficient \(k_{\mathrm{q}}\) & 0.08 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Input stage parameters. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameter** & **Value** \\ \hline HV-side DC link capacitance \(C_{\mathrm{H}}/\mathrm{\mu F}\) & 750 & 750 \\ LV-side DC link capacitance \(C_{\mathrm{L}}/\mathrm{\mu F}\) & 450 & 450 \\ Transformer operating frequency/kHz & 3 & 3 \\ LV-side capacitance voltage/kV & 1.25 & 0.7 \\ \(P_{f}\) droop coefficient \(k_{i}\) & \(\backslash\) & 20 \\ Number of DAB & 12 & 4 \\ Transformation ratio & 3:1 & 75:14 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Isolation stage parameters. \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Value** \\ \hline Filter resistance of AC port \(R_{1}/\mathrm{\Omega}\) & 0.1 \\ Filter inductance of AC port \(L_{1}/\mathrm{mH}\) & 5 \\ Arm inductance of AC port \(L_{0}/\mathrm{mH}\) & 6 \\ SM capacitance of AC port \(C_{\mathrm{SM}}/\mathrm{\mu F}\) & 450 \\ Filter capacitance of DC port \(C_{2}/\mathrm{mF}\) & 2 \\ Filter inductance of DC port \(L_{2}/\mathrm{mH}\) & 10 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Output stage parameters. At \(t\) = 2 s, \(P_{2}\) increases to 1.5 MW;
3. At \(t\) = 3 s, \(P_{1}\) increases to 3.5 MW;
4. At \(t\) = 4 s, \(P_{1}\) and \(P_{2}\) decrease to 3 MW and 1 MW, respectively;
5. At \(t\) = 5 s, \(Q\) decreases to \(-\)1 Mvar. The system dynamic response waveforms are shown in Figure 10. While PET runs stably to \(t\) = 2 s, the active power \(P_{1}\) and \(P_{2}\) are kept at their setpoints with negligible errors. \(P_{1}\): \(P_{2}\) and \(U_{\text{dc1}}\):\(U_{\text{dc2}}\) are both 3:1, which proves the accuracy of the average model proposed in Section 3.4. At \(t\) = 2 s, \(P_{2}\) increases to 1.5 MW, which is achieved by adjusting \(U_{1}\) and \(U_{2}\) to 20 kV and 40 kV, respectively, as shown in Figure 10a. It can be seen that the DC side voltage \(U_{\text{dc}}\) of the input stage fluctuates slightly when \(P_{2}\) changes, which is due to the energy buffering capacity of the DC side capacitors. Additionally, Figure 10b shows that \(P_{2}\) and \(U_{2}\) change simultaneously and quickly reach the setpoint after a short overshoot. At \(t\) = 3 s and 4 s, the system response is similar to that at \(t\) = 2 s. Figure 10c presents the simulation results of the output side voltages of ISOS and ISOP. It indicates the DAB modules in both ISOS and ISOP can maintain voltage stability, and achieve stable and efficient power transmission, which verifies the effectiveness of corresponding control strategy. Figure 10: System dynamic response when the power demand changes: (**a**) DC voltages at high-voltage side; (**b**) Active power of AC output port and DC output port; (**c**) DC voltage at output side of ISOS and ISOP. Figure 11a,b present the output characteristics of the input stage MMC. Figure 11a displays the active and reactive power that transmit between PET and the upper grid.