## 4 Experimental Validation  
As shown in Figure 11, a laboratory prototype of the EPC was fabricated to verify the ZVS and ZCS in the two-stage DC/DC converter, along with other characteristics. In the converter, there are four power switches: two switches are used in the buck regulator and another two switches are used in the push-pull circuit. The driver transformer is used to isolate the drive signals because the source electrodes of power switches in the buck circuit connect to the non-zero level. The inductances include one buck inductance and two filter inductances in input voltage. CPLD is used to generate control signals and control the sequence relationships. Dual interleaved drivers are used in the buck circuit, and the driving frequency of the buck regulator is consistent with that of the push-pull circuit. The single-channel drive frequency is 45.2 kHz, and the equivalent switching frequency of the dual interleaved drivers is 90.4 kHz. The drive signals are applied to the power switches of the buck circuit through the drive chip and the isolated drive transformer. Table 1 outlines the parameters. \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Value** \\ \hline Input voltage, \(V_{in}\) & 30 V DC \\ Output voltage, & 7000 V DC \\ Rated power, \(P_{O}\) & 130 W \\ Buck voltage, \(V_{b}\) & 22 V \\ Buck inductance, \(L_{b}\) & 75 uH \\ Buck capacitance, \(C_{b}\) & 4.4 uF \\ Output capacitance, \(C_{O}\) & 47 uF \\ Voltage-doubling rectifier capacitances, \(C_{o1}\) and \(C_{o2}\) & 2.2 uF \\ Power MOSFETs, \(Q_{1}\) to \(Q_{4}\) & IRFB4127 \\ Power diode, \(D_{1}\) & DSA30C150 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Parameters of the converter. Figure 12 shows that ZVS and ZCS can be realized in both the on and off states. The waveforms of both \(V_{DS(Q1)}\) and \(V_{DS(Q2)}\) are approximately trapezoidal, and \(I_{Q1}\) and \(I_{Q2}\) are sinusoidal. There is no voltage spike or overshooting current. The peak voltage of the switches:  
\[V_{p-p}=2V_{b}=46\ \mathrm{V} \tag{25}\]  
The voltage stress is independent of the load. The peak current of the switches:  
Figure 11: Experimental EPC in the laboratory. Figure 12: Steady-state waveforms of the converter. \[I_{p-p}=\frac{P_{o}}{V_{b}}\left(1+\frac{1}{cos\bigg{\{}\tan^{-1}\bigg{[}2\pi f^{2} \bigg{(}\frac{T_{eff}-T_{on}}{2}\bigg{)}^{2}\bigg{]}\bigg{\}}}\right)=12.64\ \mathrm{A} \tag{26}\]  
where \(f\) is the operating frequency of dual interleaved drivers, which is 90.4 kHz, \(T_{off}\) is the off time of the switches, which is 14.9 us, while \(T_{on}\) is the on time of the switches, which is 7.38 us. In the same load condition (130 W), the parasitic capacitance and leakage inductance are used to form the resonant tank. Moreover, another two-stage converter, boost and push-pull, can realize ZVS but cannot realize ZCS. The drain-source voltage also increases and reaches 70 V, as shown in Figure 13.  
According to Figure 14, the buck voltage is about 22 V in the two-stage converter. Figure 14: The waveform of buck voltage, \(V_{b}\). Figure 13: The waveform of another two-stage converter, boost and push–pull. The load is 130 W.  
The bus voltage in satellites always varies, but the target of high efficiency never changes. Figure 15 illustrates the variation in efficiency in different input voltages, where Figure 15a illustrates the efficiency when the output power is 130 W, while Figure 15b shows the efficiency when the output power is 75 W. The lower input voltage or the heavier load leads to a higher duty cycle for the buck converter. As a result, the efficiency of the DC/DC converter increases as well. The highest efficiency can be up to 95%. Figure 16 shows the test result of the conducted emission of this two-stage converter in different switching conditions, where Figure 16a presents the test result when the converter worked in hard switching, while Figure 16b shows the result when the converter worked in soft switching.