## 4 Methodology
### Implementation Details  
For the LET-TDMA solution implementation, we used the CYT2B75 Traveo II Entry Family Starter Kit platform, which features a 32-bit Arm Cortex-M0+ processor and an additional Arm Cortex-M4 core to handle complex tasks. The platform boasts a substantial memory architecture, including 4 MB of Flash, 128 KB of Work Flash, and 512 KB of SRAM. It supports advanced cryptographic operations with its Cortex-M0+ core and provides security features through a Memory Protection Unit (MPU) and a Shared Memory Protection Unit (SMPU). The software implementation was designed with a three-layer architecture to decouple hardware-specific software for shared memory static allocation and access from model-specific software. This architecture comprises three layers: hardware-specific software, LET operations, and TDMA management. Figure 8 illustrates the architecture developed, highlighting the interconnected layers designed to optimize both the flow and the consistency of the information. The first of these layers is the Data Intermediation Layer, which manages the shared memory used by various software components to access common information. This layer provides APIs to manage direct access to shared buffers, which are declared through a configuration header. Platform-specific labels must be provided in the configuration files to provide the linker with the memory address range for allocating the shared buffers and controlling data in the global RAM. Figure 7: Implementation of LET and TDMA methods in multicore real-time systems. The figure illustrates how write and read operations are synchronized across multiple cores using TDMA slots and LET intervals. Each core has its shared memory, with tasks executing within their LET intervals. Guard bands are included between TDMA slots to prevent conflicts and ensure data consistency. This combined approach enhances the predictability and composability of inter-core data exchange. The Access Times Manager Layer establishes the times for read and write operations for cross-core LET and performs the write operation between local and shared buffers. As input configuration, this layer requires the periods from tasks allocated to different cores belonging to the same event chain. It also requires the local buffer sizes to handle data copy operations at the LET periods. Its main functions include the following:  
* Enqueue: Organizes writing tasks from local memory to shared memory, acquiring local memory addresses from the local buffers for the writing process, and executes them throughout the task execution. * Trigger: Checks and transfers pending data to the designated areas of the shared memory, ensuring its availability for other processes. * Read: Facilitates access to the shared memory using specific identifiers to locate the necessary sections. Finally, the TDMA Controller coordinates the activation and access to the assigned time slots for using shared memory among the system cores, leveraging the APIs provided by the LET layer. The TDMA Controller provides the base time for the TDMA time slots and is executed at a periodic rate driven either by an ISR or an OS scheduler-handled task with a high priority to minimize jitter or delayed access to the time slots. The timing of the base period defines the TDMA timing granularity, which for efficiency, can be calculated using the greatest common divisor of the periods of the communicating tasks. The TDMA Controller also provides the means to coordinate the activation of consumer tasks based on the availability of producer data and its configured activation period through implementation or platform-specific callbacks. The implementation of these callbacks is out of the scope of this study. Algorithm 1 illustrates the main functions of this process. Figure 8: Implementation of LET and TDMA architecture. This figure illustrates the three-layer architecture developed for real-time implementation, highlighting the Data Intermediation Layer, Latency Exchange Time Manager, and TDMA Controller.