###### Abstract  
This paper proposes a compact, physics-based current model for fully depleted silicon-on-insulator (FDSOI) MOSFETs and applies it to delay variability analysis. An analytical method is applied to avoid the numerical iterations required in the evaluation of surface potential, which directly improves the computational efficiency. The accuracy of the explicit surface potential approximation is 190.3 nV, which allows for fast convergence. Surface potential and current calculations achieve 1.8\(\times\) and 1.4\(\times\) acceleration compared with BSIM-IMG, respectively. To establish the relationship between delay and underlying process parameters, we introduce the effective current and propose a process variation-aware delay prediction model. Higher-order derivatives are calculated to compensate the nonlinearity of delay variations with respect to process parameters. Experiments show a significant improvement in the prediction accuracy with higher-order derivatives, which are proved to be able to handle nonlinearity under process variations. The front gate work function contributes the most to the nonlinearity of the delay variation and the accuracy of the third-order prediction is 4.07%. Under the variation in the channel length and width, front and back gate oxide thickness and body thickness, delay variations have similar characteristics and the second-order prediction is found to be sufficient to model the nonlinearity with a maximum relative error of 1.22%. The delay prediction model only requires a single-point HSPICE DC or transient simulation and is universal for different voltages and different cells. Compared with the Monte Carlo (MC) simulation, the accuracy of the first-order prediction in the above-threshold region (0.8 V) is 0.94%. In the sub-threshold region (0.3 V), a prediction accuracy of 2.01% can be obtained while achieving a 21\(\times\) reduction in computational time. FDSOI MOSFETs; computational efficiency; delay model; process variation +
Footnote †: journal: Applied Sciences  
reduces the simulation speed. Therefore, improving the computational efficiency of device models is a key factor in effective circuit performance evaluation flows. (2) The relationship between the circuit delay and process parameters is too complex for direct connection to be established between them, and the required circuit matrix must be iteratively resolved. Methods based on machine learning can model complex relationships and achieve high accuracy [5] but model training requires a large amount of data support. Therefore, another major challenge of effective circuit performance analysis is how to relate the process variation to the circuit performance variation in the trade-off between computational efficiency and accuracy. (3) The nonlinearity of delay to process variation. The existing sensitivity-based process variation analysis works under the assumption of linearity [6] and is not suitable for sub-threshold circuits. The sub-threshold circuit delay exhibits a non-Gaussian distribution, and it is necessary to consider how to accurately model the nonlinearity of the circuit delay to process variation. Some works have been used to model the statistical variability of FDSOI MOSFETs [7], which mainly focus on threshold voltage variability. Reference [8] analyzes the process variability at the device level based on the analytical current model. Reference [9] proposes a nonlinear delay variation model based on Monte Carlo sampling to obtain the cumulative probability density function of the delay distribution and uses the 65 nm FDSOI process for verification. These works mainly focus on the analysis of threshold voltage variation, and have limitations regarding the selection of process parameters. Reference [10] uses a finite combination of input parameters to extract the statistical delay distribution.