# A 200-MS/s 10-Bit SAR ADC Applied in WLAN Systems
## 3 Circuit Implementation
### Comparator  
The dynamic comparator with kickback noise cancellation mechanism proposed in this paper uses a conventional two-stage structure consisting of a preamplifier and a latch stage, as shown in Figures 9 and 10.  
Figure 8: The proposed bootstrap.  
Figure 9: The preamplifier stage of the comparator.  
During the reset phase of the preamplifier, the clock signal CLK is maintained at a high level, resulting in the preamplifier output voltages VOP_0 and VON_0 being initialized to a ground voltage. Following this, during the subsequent comparison phase, the CLK signal transitions to a low level, enabling the charging process of the capacitor CL. The voltages VOP_0 and VON_0 exhibit varying charging rates, influenced by the input voltages VIP and VIN. This generates a differential voltage VO between VOP_0 and VON_0. When the differential voltage VO exceeds the threshold voltage of the second stage input transistor, the latch stage enters operating mode and finally produces a digital output at the points VOP and VON.  
As described earlier, kickback noise is a common issue faced by all dynamic comparators, and its impact on the comparator is mainly manifested in the comparison phase. The kickback noise cancellation circuit proposed in this design is shown in Figure 9, where device M1d is a dummy transistor of M1, with its source/drain node discharged to ground during the reset phase of the preamplifier. When the comparator starts working, the comparator clock generates a falling edge, which causes the source terminal Vs of the input pair to start charging, producing an upward pulse that injects a charge amount \(\Delta\)Q into the CDAC top plate, as shown in Figure 11. At the same time, the source-drain end of M1d produces a corresponding downward discharge pulse, which extracts a charge amount of \(\Delta\)Q at the top plate of CDAC. In other words, all the charge injected by the input pair is taken away by the dummy transistor, effectively avoiding the impact of kickback noise. In addition, the purpose of the M4 and M2 transistor is to discharge Vs to ground and charge Vdp/Vdn to Vdd during the reset phase, so as to better ensure the consistency of charge and discharge at the CDAC top plate during the comparison phase.  
Furthermore, due to the influence of the phase difference between CLK and CLKN, there may be a time deviation between the charge extraction of the dummy transistor and the charge injection of the comparator input pair, resulting in some residual charge. Therefore, in this design, the P/NMOS impedances of the transistors M3 and M3d, as well as M5 and M5d, need to be matched as much as possible.  
Figure 11: Kickback cancellation during the comparison phase.  
Figure 10: The latch stage of the comparator.  
The transient simulation of the comparator is conducted to demonstrate the effectiveness of the kickback cancellation circuit. Assume that the capacitor from the comparator input to ground is 410 fF and that the operating frequency of the comparator is 2 GHz. The transient simulation result of the comparator input voltage with and without the kickback cancellation circuit is shown in Figure 12, and it can be seen that the kickback cancellation mechanism plays a good suppression role for kickback noise in the comparison phase. In fact, the source-drain end of M1d needs to undergo charging and discharging operations in each comparison cycle, which increases the power consumption of the comparator. When the comparator operates normally at a frequency of 3 GHz, the approximate increase in dynamic current can be calculated using the CVF formula as 300 uA. Therefore, this structure trades off power consumption for the low kickback input characteristics of the comparator.