## 3 Sliding-Mode Controller
### Practical Implementation  
The theoretical conceptualization of the SMC considers the switching function \(\Psi\) sliding around the surface \(\Psi=0\). This behavior is imposed by the reachability conditions (45) and (46), both ensured in (47) and (48): when \(\Psi\) is below 0, the SMC forces a positive derivative in \(\Psi\), driving \(\Psi\) to 0; however, \(\Psi\) continues increasing and becomes positive. At that moment, the SMC forces a negative derivative in \(\Psi\), driving \(\Psi\) to 0. That derivative change occurs at the instant in which \(\Psi\) crosses 0, producing an unlimited switching frequency that introduces high-frequency harmonics to the system, which could damage the MOSFETs.  
The previous problem is solved by limiting the switching frequency in agreement with the MOSFET specifications. This limitation is performed by introducing a hysteresis band around \(\Psi=0\), where the bandwidth defines the maximum switching frequency. Figure 8 illustrates the effect of the hysteresis band, where a larger hysteresis width \(H\) produces a longer switching period \(T_{sw}\), thus reducing the switching frequency \(F_{sw}=1/T_{sw}\). Moreover, since the switching function derivative is a finite number (42), Figure 8 shows that the hysteresis band imposes a limited switching frequency.  
The introduction of the hysteresis band imposes the practical control law that must be implemented, which is also observed in Figure 8, as follows:  
\[u=\left\{\begin{array}{ll}\text{change to ON (1)}&\text{when}&\Psi\leq-H\\ \text{change to OFF (0)}&\text{when}&\Psi\geq+H\end{array}\right. \tag{51}\]  
The switching circuit designed to implement the hysteresis band, which also imposes the control law given in (51), must be supplied with single-ended voltage to avoid the need for dual-polarity voltage sources. Therefore, the switching function must be raised on a positive offset to avoid negative values. On the other hand, the implementation of the hysteresis band is performed using a hysteresis comparator based on an operational amplifier. Figure 9 shows the proposed switching circuit implementation, which includes three main parts: first, a zener network is used to generate the positive offset, which raises \(\Psi\) on a \(V_{z}\) offset voltage (\(V_{z}\) is the zener voltage); second, a positive adder to sum both \(\Psi\) and \(V_{z}\); third, the hysteresis comparator reported in [26].  
Defining the hysteresis width as \(H\), the hysteresis limits must be \([V_{z}-H,V_{z}+H]\). Then, the equations for designing the hysteresis comparator, given in [26], are applied to calculate the \(R_{h}\) and \(R_{y}\) resistances in terms of \(R_{x}\) resistance as given in (52), where \(V_{s}\) is the single-ended voltage supply.  
\[R_{h}=\frac{V_{z}-H}{2\cdot H}\cdot R_{x}\quad\wedge\quad R_{y}=\frac{V_{z}-H}{ V_{s}-V_{z}-H}\cdot R_{x} \tag{52}\]  
The resistances of both the offset generator and adder are considered equal to \(R_{x}\) for simplicity. Such \(R_{x}\) resistance is selected depending on the characteristics of the operational amplifiers used in the implementation, typically between 10 k\(\Omega\) and 500 k\(\Omega\). The zener voltage \(V_{z}\) is selected as \(V_{s}/2\) to provide the same positive and negative dynamic range to \(\Psi\). Finally, the calculation of the hysteresis band \(H\) depends on the maximum switching frequency supported by the MOSFETs, which is analyzed in the following subsection.