# EXPRESS: Exploiting Energy-Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage
## 3 Proposed Technique--Express  
The EXPRESS technique reduces the energy consumed during the flash program operations, at the cost of a negligible loss of accuracy. It relies on a partial page program operation to counter the disproportionate energy-accuracy tradeoff inherent in the ISPP scheme. Figure 4a illustrates the proposed EXPRESS technique. The solid black line represents the status of the RB pin during a regular page program operation. This pin goes low, indicating that the NAND array is busy for the duration of the program operation, \(t_{prog}\). The \(t_{prog}\) value lies in the range of 300-600 \(\upmu\)s for an SLC memory page of the chip used  
Figure 3: Timing diagram for a sequence of steps carried out by the host during the page program operation in an asynchronous interface. in this study [27]. The program operation, however, can be terminated prematurely using a RESET command, such as the program suspend operation [28]. In this case, the state of the RB pin is illustrated with the red dashed line. The premature termination of the program operation results in a partial program operation. Although this operation may slightly increase the bit error rate (BER), it can significantly reduce the time and energy of the page program operations. The critical parameter that enables an exploration of the tradeoffs between the energy and the accuracy is the partial program time, \(t_{pp}\). The following equation can be used to estimate the \(t_{pp}\):  
\[t_{pp}=t_{init}+\left(n-n_{skip}-1\right)\times t_{py}+\left(t_{p}^{su}+t_{p} \right)=t_{prog}-\left(n_{skip}+1\right)t_{py}+\left(t_{p}^{su}+t_{p}\right) \tag{2}\]  
Here, \(n_{skip}\) is the number of program cycles that can be skipped to achieve higher energy efficiency. Note that we have not included the verification phase of the last program cycle in Equation (2), as no additional bits are programmed during the verification phase. In general, Equation (2) can be used as a guideline for finding an optimal \(t_{pp}\), which needs to be precharacterized on the basis of the properties of the particular family of flash memory chips. Figure 4b sheds more light on the rationale behind EXPRESS by illustrating three different reference voltages, which correspond to three different memory operations. The erase operation ensures that the threshold voltages of all the erased cells in the block are below the reference voltage, \(V_{ref}^{EYY}\). Similarly, \(V_{ref}^{PVY}\) is the reference voltage used during the program verification phase of the page program operation. The ISPP scheme ensures that the threshold voltages of all the programmed cells are above the reference voltage, \(V_{ref}^{PVY}\). Finally, a read reference voltage, \(V_{ref}^{Read}\), is used to distinguish between the erase and program states of the cell during a page read operation. All NAND manufacturers keep a sufficient voltage margin between the read and program verification voltages in order to minimize read errors. However, this margin can be exploited to increase the energy efficiency in all applications where the BER is sufficiently low and it can be corrected using error-correction techniques. In addition, EXPRESS can be used even when a somewhat higher BER can be tolerated, e.g., in applications where approximate short-lived data are common. For example, if we terminate the program operation prematurely, the resulting threshold voltage distribution will be mostly above the read reference voltage, as is shown with the dashed lines in Figure 4b. The resulting distribution may have some area below the read reference voltage and that will create errors, which we are trading off for the saved energy. Since 3D NAND flash memory cells in the erased state exhibit long tails of the threshold voltage distribution, programming these cells may require several extra program pulses.