# A Temperature-Robust Envelope Detector Receiving OOK-Modulated Signals for Low-Power Applications
## 4 Implementation Criteria  
### Parameter Optimization  
Detailed study of this ED architecture has shown there are two different sources for loss of signal within the ED with respect to the theoretical value for \(V_{ED}\) (3). The first one is MOSFET junction leakage within the diodes, whereas the second one is non-perfect coupling of the input signal \(V_{RF}\) to the internal gate and drain nodes. These phenomena directly translate into a reduction in the gain of the ED, which was modeled as a multiplication of the theoretical gain by a factor \(k<1\) independent of \(N\), yielding  
\[V_{ED}=\frac{kNV_{M0}^{2}}{4 nV_{T}} \tag{20}\]  
and ultimately, at room temperature,  
\[P_{SEN}=\sqrt{\frac{SNR_{roq}NF(4 nV_{T})^{2}k_{B}TR_{inf}f_{N}}{A_{v}^{4}k^{2}R _{S}^{2}}}. \tag{21}\]  
The MOSFET type featuring the lower \(n\) available within the chosen technology has been selected in order to maximize ED output amplitude, as in (20). Also, a high resistivity resistor with low temperature coefficient is needed for \(R_{PTAT}\). The same holds for \(R_{bias}\) if implemented as an actual resistor. As for capacitors, the choice of type and polarity for \(C_{gate}\) and \(C_{drain}\) may have a critical impact on sensitivity. Unless parasitics towards ground are negligible with respect to the nominal capacitance value or are evenly distributed between the two terminals of the capacitors, it is necessary to determine on which side it is best to leave most of the parasitics themselves--towards the RF input or the internal diode nodes. If non-negligible coupling capacitor parasitics are placed towards the RF input, a significant increase in the overall input capacitance of the ED, \(C_{in}\), may occur, ultimately reducing the matching  
Figure 5: Sample simulated waveforms in a differential passive ED for \(V_{M}=5\) mV, \(15\) mV and \(30\) mV. From top to bottom: ED single-ended outputs \(V_{ED}^{+}\) and \(V_{ED}^{-}\), ED differential output \(V_{ED}^{+}-V_{ED}^{-}\). The picture shows ED output distortion due to increased input power. network gain (5). On the other hand, if non-negligible coupling capacitor parasitics are placed towards the internal diode nodes, capacitive dividers may result in a loss of signal at the diode terminals themselves. It is possible to determine which of the two situations is best by simulation. In both our versions, an assessment of this aspect has led us to place most of \(C_{gate}\) and \(C_{drain}\) parasitics, which amount to roughly one third of their nominal capacitance value, towards the RF input. Capacitor losses, in particular on \(C_{gnd}\), also need to be assessed. First, a preliminary design was carried out based on the formulas reported in Section 3.1, with an \(NF\) value close enough to unity in the whole operating temperature range and the following remarks, with reference to Figure 2:  
* High L in \(M1\) and \(M2\) for good mirroring. * High W in \(M1\) and \(M2\) for low \(V_{GS}\) to make room for \(M3\) and \(M4\). * \(\frac{(W/L)_{3}}{(W/L)_{4}}=2\) and highest possible \(R_{PTAT}\) allowed by the technology considering area occupation to minimize the static current of the PTAT block. * Lowest possible \(C_{gnd}\) for effectively cutting the chosen carrier RF frequency. * Lowest possible \(C_{gate}\) and \(C_{drain}\) for effectively coupling the input signal to the internal diode nodes at the chosen carrier RF frequency. However, mismatch between the diodes and MOSFET \(M4\) may negatively affect temperature compensation precision. Let us assume that a difference \(\Delta V_{TH}\) exists between the average threshold voltage of the diodes \(V_{TH}\) and that of MOSFET \(M4\), \(V_{TH,M4}\), due to mismatch. Since mismatch is random, \(\Delta V_{TH}\) can have both signs.