## 1 Introduction  
Elliptic curve cryptography (ECC) and Rivest-Shamir-Adleman (RSA) are two well-known public-key cryptography (PKC) schemes. ECC, described by [PERSON] [1], offers comparable security to RSA but with shorter key lengths [2]. For instance, a 233 bit ECC key provides similar protection to a 2048 bit RSA key. The advantage of ECC lies in its ability to achieve security with shorter key sizes, resulting in lower power consumption, reduced channel bandwidth requirements, and more efficient use of hardware resources; on the other hand, the longer key lengths are advantageous for maximizing security. However, challenges arise when implementing longer ECC key lengths while minimizing area utilization, especially in designs optimized for securing area-constrained applications.  
For security purposes, various applications demand area-optimized implementations of cryptographic algorithms, such as wireless sensor nodes [3, 4], radio-frequency-identification (RFID) networks [5], and secure robotics communication [6, 7]. Using shorter ECC key lengths than RSA helps protect these applications with minimum area utilization and is the main focus of this work.  
The National Institute of Standards and Technology (NIST) has standardized ECC for prime and binary fields (i.e., \(GF(P)\) and \(GF(2^{m})\)) to maintain security standards for efficient communications [8]. More precisely, NIST has recommended specific field lengths for \(GF(P)\) and \(GF(2^{m})\), such as 192, 224, 256, 384, and 521 for \(GF(P)\), and 163, 233, 283, 409, and 571 for \(GF(2^{m})\)[8; 9]. ECC employs a four-layer model to implement NIST's suggested prime and binary field lengths. Therefore, the foremost layer ensures encryption/decryption, signature generation/verification, secret-key authentication, and other similar functions. The essential operation in ECC is point multiplication (PM), which involves point addition (PA) and point double (PD) operations for computations--these operations are the second layer of the ECC model. Modular arithmetic operators (such as adder, square, multiplier, and inversion) show the layer one ECC operations. ECC's PM operation efficiency depends on implementing these modular arithmetic operators efficiently.  
Two alternatives to implement ECC are software-based implementations on microcontrollers and hardware accelerators on field-programmable gate arrays (FPGA) and application-specific integrated circuits (ASIC). Although software-based implementations offer greater flexibility, they provide limited throughput [2; 10; 11]. Conversely, hardware accelerators offer higher throughput but with lower flexibility [2; 10]. Therefore, the implementation choice relies on the platform used. The \(GF(2^{m})\) fields are beneficial for hardware acceleration due to their carry-free additions, whereas \(GF(P)\) fields are more advantageous for software platforms [10; 12]. In addition, ECC offers a polynomial and normal basis for point representation [9]. The polynomial basis is more practical for efficient modular multiplications, and the normal basis is helpful for frequent modular square computations [12]. Two coordinates, i.e., affine, and projective, used in ECC also affect performance. The affine coordinate is more computationally expensive, requiring an inversion operation during each PA and PD computation. In contrast, the projective coordinate is more suitable to maximize the performance of the ECC accelerators [9; 12; 13]. Based on this compliance, binary fields, projective coordinates, and polynomial basis representations are chosen in this study due to the focus on accelerating ECC on a hardware platform.