# Doherty Power Amplifier Design via Differential Combining
## 3 DPA Design  
After understanding the capabilities of the proposed combiner, it can be applied to design a DPA using a straightforward structure. This structure is depicted in Figure 2. In this design, the main and peak amplifiers are formed by two devices combined by using the proposed combiner. If the optimal load for each transistor is \(R_{opt}\), then the characteristic impedance of the impedance inverter is defined as \(R_{opt}/2\), and the common load of the DPA is \(R_{opt}/4\)[11]. The selected device is a \(4\times 50\,\mathrm{\SIUnitSymbolMicro m}\) from GaN-on-SiC MMIC Wolfspeed G28v5 process with \(0.15\,\mathrm{\SIUnitSymbolMicro m}\) gate length. For this device, \(I_{max}=0.25\,\mathrm{A}\), \(V_{k}=3\,\mathrm{V}\), \(V_{DD}=28\,\mathrm{V}\), and \(C_{OUT}=76\,\mathrm{fF}\). The chosen frequency for this design is \(f=32\,\mathrm{GHz}\). Thus, the characteristic impedance for both transmission lines in the combiner is  
\[Z_{0}=\frac{1}{\omega C_{OUT}}=65.3\,\mathrm{\SIUnitSymbolMicro m} \tag{6}\]  
where the capacitance between both lines is \(2C_{OUT}=152\,\mathrm{fF}\). Additionally, with \(R_{opt}=200\,\mathrm{\SIUnitSymbolMicro m}\), the impedance inverter's characteristic impedance is \(R_{opt}/2=100\,\mathrm{\SIUnitSymbolMicro m}\) and the common load is \(R_{opt}/4=50\,\mathrm{\SIUnitSymbolMicro m}\). To evaluate the concept, a DPA using ideal components (transmission lines, capacitors, etc.) and drivers is simulated. Figure 3 shows the simulated drain efficiency versus output power and the load modulation effect for the main and peak devices (i.e., \(Z_{1}\) and \(Z_{2}\)). The simulation indicates a potential bandwidth of \(4\,\mathrm{GHz}\) for the DPA. Note that the most optimal load modulation is achieved at \(32\,\mathrm{GHz}\), the chosen frequency. Figure 2: DPA structure. The input matching networks are designed to maintain circuit stability and enable broadband performance with optimized gain. The Wilkinson divider at the input is configured with an uneven division ratio to enhance load modulation effects, while the other two Wilkinson dividers are designed for an equal power split. In the DPA version incorporating real transmission lines, a 100 \(\Omega\) impedance inverter was synthesized using a four-section structure. This approach was necessary because a 100-ohm impedance results in a very narrow width in the employed technology. Consequently, an adjustment was required in the delay at the input of the main amplifier cell to ensure proper phase alignment. Additionally, bias tees were designed utilizing high impedance transmission lines, characterized by narrow lines. Circuit stability was maintained with the inclusion of a series resistor at the gate of each device, complemented by an additional resistor within the bias tee structure. The driver amplifier was designed with an input matching network similar to that of the main and peak amplifiers, and an output matching network (OMN) was implemented to match the 50-ohm impedance of the dividers at the input of the main and peak cells. The preamplifier (driver) at the peak branch has been biased at class C, while the peak cell was kept in Class AB. Figure 4 shows the schematic of the obtained DPA. The nominal value of the capacitor between lines in the combiner structure changes due to the non-ideal characteristics of real capacitors, which introduce parasitic effects that alter the effective capacitance. This variation must be accounted for in the design to ensure proper combiner performance. The DPA layout is shown in Figure 5 with a chip size of 4.6\(\times\)3.6 mm, where the applied voltages to any stage of the circuit are indicated. Simulation results for the 30 to 34 GHz bandwidth reveal that the amplifier achieves a Power Added Efficiency (PAE) at 6 dB Output Power Back Off (OBO) ranging between 14% and 28%, indicating a robust performance across the frequency range. At saturation, the PAE improves significantly, reaching between 24% and 37%, demonstrating the amplifier's efficiency under peak conditions.