# SARDIM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging
## 2 Background
### Near-Memory Processing  
The von Neumann architecture, the foundation of modern computer architecture, comprises a CPU, memory, and program structure. In this architecture, the CPU reads programs and data from the same memory space, executes the programs, and stores the results back into memory. This process is based on the sequential fetching and execution of instructions from memory. However, this sequential execution method creates a problem known as the von Neumann bottleneck, which is caused by the limited data transfer rate between the CPU and memory and unnecessary data movement. This bottleneck is particularly prominent in data-intensive algorithms that process large volumes of data with low reuse rates, such as deep learning recommendation models (DLRMs) [28; 33] and graph neural networks (GNNs) [29; 34]. Additionally, modern memory systems consist of multiple ranks connected to a memory controller that share a single data path. Because the data path can transmit only one rank and data at a time, there is a bandwidth limit even when multiple DIMMs are used to increase the number of ranks. Consequently, this limitation on memory bandwidth constrains the overall system peak performance, despite improvements in CPU performance.  
Processing in memory (PIM) and NMP have the potential to overcome the limitations of modern computers and memory systems. Figure 3 illustrates conventional memory semiconductors and memory semiconductors integrated with PIM and NMP technologies. A PIM semiconductor combines computational logic and memory cells on a single chip, whereas an NMP semiconductor features separate chips for computational logic and  
Figure 2: Operation flow of the RDA.  
memory cells. Instead of transferring data to the CPU for processing during memory read and write operations, the PIM and NMP technologies enable data processing directly inside or near the memory. This minimizes unnecessary data movement and enhances the efficiency of data processing. Furthermore, employing PIM or NMP modules per bank allows for parallel data handling by the bank, employing modules per rank enables parallel data handling by rank, thereby expanding the bandwidth. Owing to these capabilities, the PIM [25; 35; 36; 37; 38] and NMP [27; 28; 29; 30; 31] technologies have garnered significant attention in recent years and are promising for effectively alleviating memory bottlenecks.  
Previous studies have indicated that existing memory cells require modification to implement PIM-related technologies in real systems [25; 35; 36; 37; 38]. However, integrating PIM technology into existing commercial memory systems poses challenges, because the current general protocol defined by the Joint Electron Device Engineering Council (JEDEC) [39] does not support modified memory cells. Even if the JEDEC were to define a protocol for PIM in the future, it is anticipated that applying existing research and development to that protocol would be complex. In contrast, the NMP technology is relatively compatible with existing systems because it adds a separate processor near the memory without altering the memory cells. Therefore, SARDIMM is designed to manage NMP operations as standard memory write requests and to adhere to a standard DRAM interface, thereby facilitating its integration into commercial memory systems.