# Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
## 3 Bit-Cell External Driver Design  
### WL Driver Structure and Performance  
To manage the read and write operations within the bit-cell and to accurately apply the desired weight during computation, we have designed a specialized word line (WL) driver circuit. This driver is responsible for adjusting the signals on both the word line left (WL) and word line right (WLR) to ensure proper activation of the bit-cell. The ability to dynamically control these word lines is critical, as it allows for precise read/write operations and facilitates the integration of computational tasks, such as applying weights during in-memory processing. By adjusting the word line signals based on the operational state (read, write, or hold), the WL driver plays a pivotal role in coordinating the functionality of the bit-cell for various computational and memory storage tasks. The WL driver is composed of several key components, including transmission gates and a 2-to-1 multiplexer, which work together to regulate the word line voltages. The operation of the driver is largely governed by the clock (CLK) signal, which dictates whether the system is in a computation state or a hold state. When theCLK signal is at a low logic level (0), the WL voltage is set based on the value of the applied weight, and this voltage is output to the word lines to enable access to the bit cell for read or write operations. On the other hand, when theCLK signal transitions to a high logic level (1), both the WLL and WLR signals are pulled down to 0 V, effectively deactivating the access transistors inside the bit-cell. This process isolates the bit-cell from further interactions with the word lines, allowing the data currently stored in the cell to be held securely without interference or modification. In addition to theCLK signal, the Y signal serves as an important control input to the driver, determining whether the driver is actively engaged for a specific memory row. If the Y signal is at a low logic level (0), the driver is disabled for the corresponding row, and a low voltage is applied to the WL to ensure that no access is granted to that row. Conversely, when the Y signal is high (1), the voltage determined by the driver's internal operation is applied to the WL, enabling access to the corresponding memory row for read or write operations as required. This selective control of memory rows allows for efficient data management within the memory array, as only the desired rows are activated at any given time. The final stage of the WL driver includes a multiplexer that is controlled by the W_R signal, which determines whether a read or write operation is to be performed. If the W_R signal is set to 0, the output from the previous multiplexer is passed through unchanged, maintaining the current state of the word lines. However, when the W_R signal is set to 1, indicating a read or write operation, both WLL and WLR are set to a high voltage (1 V), enabling access to the bit-cell and facilitating the execution of the specified operation. This dynamic control of the word lines allows for efficient transitions between read, write, and hold states, ensuring that the system operates with minimal latency and power consumption while maintaining data integrity. Figure 7 illustrates the behavior of the WL driver under the condition where the Y signal is held at a high level (1 V), ensuring that the driver remains continuously active. In this example, we assume that the input weight value is set to 0, and we examine how the WL driver's operation varies based on the values of the W_R and CLK signals. The figure demonstrates that when the W_R signal is set to 1 and the CLK signal is 0, the word lines are activated, and the voltage corresponding to the input weight is applied to the bit-cell. However, when the CLK signal transitions to 1, both word lines are set to 0 V, deactivating the access transistors and isolating the bit-cell, allowing the data to be stored without any further changes.