# 25-34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver
## 2 Design of the Single-Pole, Double-Throw (SPDT) Switch
\(C_{GS}\) and \(C_{GD}\) are the parasitic capacitances between the gate and source, and the gate and drain, respectively. \(C_{SB}\) and \(C_{DB}\) are the junction capacitances between the source and body, and drain and body, respectively. The mm-wave-band signal can leak through parasitic capacitors which are caused by junction diodes. All signal paths through these junction diodes to ground (GND) or DC control voltage sources should be alternative current (AC)-floated to block unwanted signal leakages. Hence, 17.7 k\(\Omega\) AC-floating resistors, \(\mathrm{R_{F}}\), of are used to the gate, drain, source, body, and DNW, as shown in Figure 3.  
The insertion loss and isolation of the switch core in Figure 5a can be defined, according to the switch state, as \(\left|S_{21}\right|\). The power delivered to the output port is determined by the impedances of the input and output ports, and the impedance of the source-drain channel (\(Z_{sw}\)). The magnitude of \(S_{21}\) can be written as:  
\[\left|S_{21}\right|(\mathrm{dB})=10\log\biggl{(}\frac{2R_{0}}{2R_{0}+\left|Z_ {sw}\right|}\biggr{)}^{2} \tag{1}\]  
where \(R_{0}\) is the input and output port impedance of 50 \(\Omega\)[17]. The IE inductor, \(L_{\mathrm{DS}}\), is introduced to remove the reactance component of the \(Z_{sw}\), which is defined as:  
\[Z_{sw}=R_{ch}||j\omega L_{DS}||\frac{1}{j\omega C_{sq}}. \tag{2}\]  
In Figure 5b, \(R_{ch}\) is the channel resistance of the transistor, which is greater than the impedance of the blocking capacitance, \(C_{B}\), at operating frequency. \(C_{sq}\) is the effective capacitance of the source and drain, which is expressed as,  
\[C_{eq}=\frac{C_{GS}C_{DS}}{C_{GS}+C_{DS}}+\frac{C_{SB}C_{DB}}{C_{SB}+C_{DB}} \tag{3}\]  
The IE inductance is designed such that the inductor resonates at the operating frequency, to cancel the effective parasitic capacitance of the transistor. Figure 6 show the simulated insertion loss and isolation results of the CB switch core when all the inductors (\(L_{DS}\), \(L_{TRX}\), \(L_{ANT}\)) are assumed to be ideal, with infinite Q-factor, and the total gate width of the switching transistor is 128 \(\upmu\)m. Since the channel capacitance is canceled out at resonance, the isolation improves from \(-11\) dB to \(-38\) dB. The insertion loss also improves from \(-1.1\) dB to \(-0.78\) dB, due to the reduction of the channel capacitance. The switches are designed such that maximum isolation occurs at a target frequency of 28 GHz. Reducing the Q-factor of the IE inductor widens the switch bandwidth. However, the loss and isolation performance will decrease. Figure 4: Cross-sectional view of the triple-well complementary metal oxide semiconductor (CMOS) transistor. SUB: substrate; DNW: deep-N-well. The CB selector in Figure 7a consists of a two-bit decoder and inverters. The DSB selector in Figure 7b requires a negative voltage, \(-V_{NN}\), which is generated by an NVG. The NVG comprises a ring oscillator (OSC), a negative charge pump (CP), and two level shifters (LVS). The oscillator charges the capacitors, \(C_{CP}\), which have a capacitance of 2.3 pF. Negative charges from the capacitors are transferred to the output node of the CP, generating \(-V_{NN}\). The oscillation frequency of the OSC is set to 350 MHz. The estimated settling time is 380 ns, with \(-V_{NN}=-836\) mV, as shown in Figure 8. The level shifter changes the control voltages from \(V_{DD}\) and 0, to V\({}_{\rm DD}\) and \(-V_{NN}\). The total static current consumption of the NVG is 150 \(\upmu\)A.  
Figure 4.0 (**a**) Schematic and (**b**) alternative current (AC)-model of the cross-biasing (CB) switch core with isolation enhancement (IE) inductor. Figure 4.1 Simulated insertion losses and isolations using the IE inductor, \(L_{DS}\). Figure 4.2 _Cont._  
Table 1 shows the switch control voltages according to the control mode and selector.