# An Automatic Detection Method for Cutting Path of Chips in Wafer
###### Abstract
[PERSON] and [PERSON] (2021) used a convolutional neural network to roughly align the wafer, with an error of \(\pm 5^{\circ}\). Regression analysis was used when the fine alignment was performed. Before fine alignment, brightness calibration was required for the image, and then the slight difference in feature points between the two images was compared to derive the rotation angle of the wafer. [PERSON] et al. (2021) proposed an improved U-Net convolution neural network method to directly determine the cutting path. To speed up the process, the image is down-sampled to one-quarter of the original image, and the location of the chip location is determined using the advantageous genetic Adaptive Genetic Algorithm (AGA) for the downsampled image [14]. In contrast, the quadratic exponential function is used to smooth the histogram of the image and obtain the binary image, distinguish the street and chip region, and calculate the cutting path according to the binary result [15]. Current algorithms focus on finding the edges of chip regions and determining the chip region and Mark point locations using template matching algorithms, which only exploit the geometric features and grayscale variations of the image and have high requirements for image quality. The neural network algorithm has high accuracy in street recognition through training, but it requires a large number of images to train different specifications of wafers, which is time consuming. In summary, the existing methods used to determine the cutting path based on the wafer image have the following problems: (1) The wafer images processed are all taken under a high magnification optical system and there is a great deal of pollution in the street and chip region. Although template matching and contour edge detection can determine the location of the chip region, it is very difficult to accurately determine its chip region with high accuracy. (2) When the neural network is used to find the street directly, it requires a lot of training and takes a long time. Moreover, the interference factors of the street region in each image are different, and the recognition accuracy is disturbed. (3) Only the contour features of the chip region in the image are used, and no other useful information about the chip region is used. In order to solve the above problems, this paper proposes a cutting path planning algorithm for the chip region in the wafer image. First, the tilted wafer is aligned, and then the brightness calibration of the image is performed on a global scale. The chip region and the center of gravity position are determined by calculating the frequency domain correlation between the template and the target image, and the interlayer position is found in the determined chip region. The interlayer is used as an auxiliary to positioning to determine the cutting path. The accuracy of real-time performance and adaptability between different state images using the chip interlayer as the auxiliary location to determine the cutting path is verified by experiments. The innovation of our method is mainly reflected in three aspects: (1) The proposed image brightness calibration algorithm can improve image quality. Compared with the traditional image enhancement and grayscale transformation algorithms, when the illumination changes significantly, it can better improve the overall grayscale distribution of the image. (2) A template matching algorithm based on frequency domain correlation is used to find the chip region, which enhances the dependence on the frequency domain characteristics of the chip region and reduces the chip region pollution and other factors' interference. (3) On the premise of determining the chip region, the interlayer is used as an auxiliary to positioning, and the cutting path is not affected by the geometric shape change of the chip region. The determined cutting path is distanced from the chip region to improve the yield of wafer cutting.