# A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA
## 2 Mathematical Background over \(GF(2^{m})\)
### Control Unit and Clock Cycle Calculation  
In the following text, we first describe the FSM-based dedicated controller, and then we show the overall cycle counts required to implement Algorithms 1-3. FSM control unitThe FSM of our accelerator architecture comprises a total of 104 states. Descriptions of these states are as follows:  
* _Idle state (State 1)._ State one is an idle state. The processor remains in this state until a one-bit start signal becomes 1. * _Affine to projective conversions (State 2 to State 6)._ As the processor receives the start signal, it switches from state one to state two to implement the affine to projective conversions of Algorithms 1-3. * _Mode checker (State 7)._ This is a conditional state. It checks a two-bit mode signal to implement the PM on the respective curve (Weierstrass, Edward, and Huff). The encoding of a two-bit mode signal is as follows: (i) 00 means not to do anything, (ii) 01 determines the execution of PM computation for the Weierstrass curve using Algorithm 1, (iii) 10 means the computation of the PM operation for the selected Edward curve using Algorithm 2, and (iv) 11 shows the implementation of the PM operation for the Huff curve using Algorithm 3. * _PM computation in projective coordinates (States 8 to 73)._ The PM states of the Weierstrass curve are from states 8 to 21, which are liable to execute the formulations of column two of Table 2. Similarly, the PM states of the Edward curve are from states 22 to 35 and are responsible for the execution of the formulations of column three of Table 2. Finally, the Huff curve's PM states are from 36 to 72, and these are responsible for operating the execution of the formulations of column four of Table 2. State 73 acts as a conditional state which checks the inspected key bit value (\(k_{i}\) in Algorithms 1-3). Moreover, the processor switches from state 73 to either 8, 22, or 36 based on a two-bit mode signal and a value of \(m-2\). Whenever the value of \(m-2\) becomes 0, the processor switches to state 74. It is essential to state that we set the initial value of \(m\) to 233. * _Projective to affine conversions (States 74 to 103)_. As shown in Algorithms 1 and 3, the projective to affine conversion needs an inversion operation and some additional arithmetic operations to generate the resultant point on the respective curve (Weierstrass, Edward, and Huff). Therefore, states 74 to 92 execute the modular inversion using the quad-block variant of an Itoh-Tsujii algorithm of [27]. Nine additional states from 93 to 101 generate the control signals to implement the remaining projective to affine conversion instructions of Algorithm 1. Similarly, two states from 102 to 103 generate the control signals to implement the remaining projective to affine conversion instructions of Algorithm 3. * _Finish (State 104)_. This state is responsible for generating the finished signal after completing the PM operation either on the Weierstrass, Edward, or Huff curve, depending on a two-bit mode signal. In the case of the Weierstrass curve, the finish state comes after state 101. Similarly, for Edward curve implementation, the finish state comes after state 73. Finally, for Huff curve implementation, the finish state comes after state 103. **Clock cycle calculations. ** One clock cycle is needed for the idle state. Moreover, five cycles are required to implement the affine to projective conversions during states 2 to 6. Furthermore, one cycle is needed for the mode checker state of the FSM. As we can see, \(for\) loops of Algorithms 1-3 require modular operations to be executed. Moreover, columns two to four of Table 2 reveal that the Weierstrass, Edward, and Huff curves require 14, 14, and 37 instructions to implement the PM operation. Consequently, the complexity of the \(for\) loop of Algorithm 1 in terms of required computations is \(15\times(m-2)\) cycles. Here, \(m\) specifies the targeted key length (233). Similarly, the cycle count of the \(for\) loop of Algorithm 1 is 3465.