## 5 The Hardware Implementation of the Dual-Axis-Based Solar Tracking System
### Proposed ASPCB Design with Self-Testing Facilities  
In addition to the original operational circuit, the modified Arduino Mega development board includes a cost-effective and energy-efficient self-test architecture. Thus, the schematic representation created in Altium Designer v22, illustrated in Figure 12, can be separated into multiple portions based on the function of the ICs used. The power and control area, as seen in Figure 11(a), contains the Atmega2560 microcontroller (U1), which controls the entire system, as well as voltage stabilizers that power all of the ICs on the board. According to the scheme, the board receives voltage from an external source via a RASM722 PTR13X power connector J1, which is protected by a Schottky diode marked D1 (MBRA140T3G). Biased capacitors PC1 and PC2 (47 uF), as well as C1 (100 nF), C2 (10 uF), and C3 (22 uF), are used to filter the input voltages in the circuit. Circuit U2 (NCP1117 ST50T3G) stabilizes the 12 V voltage from the input to 5 V (output), whereas unit U3 (LM1117T-3.3) generates a stable voltage of 3.3 V from a nominal 12 V. The quartz oscillator X1 (ATS16 ASM-1) generates a clock signal at 16 MHz for the Atmega2560 microprocessor. Non-polarized capacitors C4 and C5 (100 nF) play the role of carrying out phase inversion. The resistors R1 (1 M  
Figure 12: Proposed ASPCB layout with self-testing features for the solar tracking system. crystal's stability and facilitate its oscillations. The normally open contact SW1 enables the activation of the Reset input, which is active on the logical 0 level and restores the system to its initial state. The P1 unit is an array of integrated circuit serial programming (ICSP) pins that connect an external AVR microcontroller to modify or update the firmware on the Atmega2560 microprocessor. The input vector generating component, as shown in Figure 12b, is composed of two LFSRs that comprise D-type FF ICs (SN74 LVC2G74 DCTR) with a D data channel, Q, and Q negated outputs, as well as the clock, reset, and preset signals, respectively. The first group of FFs, labeled U4A-U8A, consists of a series of XOR ICs (SN54 HC86) labeled U14A, U15B, U16C, and U17D, which process the data transferred from one data cell to another, resulting in the desired binary sequence. Similarly, the second group of FFs labeled U9A-U13A has an identical hardware configuration, with XOR gates (U18A-U21A) positioned between segments of 1-bit registers. The 10-bit binary strings from both LFSR structures will be routed to the Atmega2560 microchip's analog inputs via an intermediate segment filter. The selection and conversion segment, as depicted in Figure 12c, comprises the switching ICs (SN74 CBTD16210 DGGR) marked SEL1A to SEL4A. These demultiplexers have the role of transmitting the 10-bit data packets in a predetermined order. The selection of the pairs of vectors is performed with the help of an inverter circuit (SN74 LVC1 GU04 DBVT), which turns on the switches SEL1A and SEL2A or, respectively SEL3A and SEL4A, depending on the value of the control signal. Since the Atmega2560 microchip only recognizes purely analog values on inputs A0-A3, it was necessary to insert TLC5615 CP ICs, marked U23 to U26, which enable the digital-to-analog conversion of the 10-bit data packets. The command-and-control section of the BIST testing, presented in Figure 12d, uses four L7805 CV ICs to enable the test paths obtained by combining switches with digital-to-analog converters. Thus, the voltage stabilizer U27 turns on or off the power to the light sensors LDR0-LDR3, allowing for the next three stabilizers, U28-U30, to associate the appropriate switch-converter pairs. The four voltage stabilizers are controlled numerically by means of FOD817A3 SD optocoupler circuits marked from U31 to U34. Thus, when the optocoupler transistor is activated, it allows for the stabilizer to be connected to the ground, which in turn provide a voltage of 5 V at its output.