# An Energy-Efficient Strategy for Microcontrollers
## 3 Analytical Models
### How Will Overhead Affect Energy Consumption? DVFS and power-saving modes are commonly used low power technologies. The STM32F407 used as the target device supports the runtime processor frequency transitions. By modifying Phase-Locked Loop (PLL) parameters and setting PLL as the clock source, the clock frequency of the STM32F407 processor can be up to 168 MHz. During the transition, the high-speed internal crystal oscillator (HSI) or high-speed external crystal oscillator (HSE) is used as the clock source, and now PLL parameters can be modified. After setting the PLL parameters, the PLL output is enabled, and when it is ready, the clock source is switched to PLL output. If peripherals are required, SysTick, the peripheral clock, and all the peripherals need to get reinitialized as well. It can be seen that adjusting the processor clock frequency may take a lot of time, so the impact of the overhead of processor clock frequency transitions on the energy consumption should be calculated. In addition, the STM32F407 processor also comes with three power-saving modes: sleep mode, stop mode, and standby mode. It is evident that entering and waking up from power-saving modes will introduce energy consumption overhead, and the overhead should be calculated as well. Utilizing DVFS technology and applying power-saving modes have many similarities: they change the power consumption of the microcontroller, and both of them introduce a certain amount of overhead. The impact of their overhead on energy consumption can be studied in a similar way. Whether applying low power technologies such as DVFS and power-saving modes will contribute to energy saving can be expressed as Equation (10), where E\({}_{\text{lp}}\) represents the energy consumption after low power technologies applied, E\({}_{\text{oh}}\) represents the overhead energy consumption of applying low power technologies, and E\({}_{\text{ori}}\) represents the energy consumption under the original condition. In Equation (11), the energy consumption is expressed by the product of power and time. Thus, we derive Equation (12), and the key to this question is whether the energy saved by applying low power technologies can cover the overhead that is introduced. Figure 2 shows schematic diagrams of the energy consumption of applying DVFS and power-saving modes. \[\mathrm{E_{lp}+E_{oh}<E_{ori}} \tag{10}\]  
\[\mathrm{P_{lp}\times t_{lp}+P_{oh}\times t_{oh}<P_{ori}\times t_{ori}} \tag{11}\]  
\[\mathrm{P_{oh}\times t_{oh}<P_{ori}\times t_{ori}-P_{lp}\times t_{lp}} \tag{12}\]  
The total energy consumption of an embedded system after low power technologies being applied is made up of two parts: \(\mathrm{E_{oh}}\), the overhead (the red area), and \(\mathrm{E_{lp}}\), the energy consumption of the system (the orange area). Energy can be saved when the sum of the red and orange area is smaller than the blue area, \(\mathrm{E_{ori}}\), the energy consumption under the original condition. The overhead of DVFS in (a) includes two processor clock frequency transitions. The first transition is to adjust the frequency to the target frequency, and the second is to reset the frequency to the previous frequency. However, the overhead of applying a power-saving mode in (b) is slightly different from that of DVFS: the energy consumed to enter the power-saving mode and the energy consumed to wake up. There will be at most one system clock reconfiguration when waking up. If the overhead introduced by applying low power technologies is significant enough, we must consider whether the energy saved by using these technologies is sufficient to cover their overheads. In this case, a minimum time for which the system is required to stay in power-saving modes is  
\[\mathrm{t_{min}=\frac{E_{oh}}{P_{ori}-P_{oh}}} \tag{13}\]  
For two different power-saving modes A and B, if Mode A has a better power-saving effect and less overhead, Mode A should always be the best choice.