## 2 Related Work  
The binary extension field GF(\(2^{n}\)) is exceptionally efficient in hardware implementation due to the removal of the carry arithmetic. One more advantage of GF(\(2^{n}\)) over the other fields is the availability of various representations of the field elements such as the normal, polynomial, and dual basis. There are three main categories of polynomial basis multipliers in GF(\(2^{n}\)): bit-serial, word-serial, and bit-parallel. Most of the bit-serial and bit-parallel multiplier structures have a large hardware resource area and large time complexities, making them unsuitable for implementation in resource-constrained embedded devices such as RFID devices [38; 39; 40; 41]. Thus, there is a need to possess multiplier architectures with limited hardware resources and a reasonable execution time suitable for these embedded devices. Word-serial multipliers are the potential candidate for solving this problem because they have a trade-off between the hardware resource area and the time complexities. Therefore, they provide more adaptability to manage the design space and speed. The word-serial multiplier structures can be divided into four categories: Serial-In/Serial-Output (SISO), Serial-In/Parallel-Output (SIFO), Parallel-In/Serial-Output (PISO), and scalable structures. There are several polynomial-basis word-serial SISO systolic multiplier structures, published in [42; 43; 44; 45; 46]. Other polynomial-basis word-serial SIPO systolic multipliers were exhibited in [47; 48; 49; 50]. [PERSON] et al. in [51] developed a type-T Gaussian normal-basis word-serial PISO multiplier structure. Different scalable systolic multiplier structures were published in [52; 53; 54; 55; 56; 57; 58].  
Several authors in the literature [40; 41; 59] tried to increase the performance and hardware utilization of multiplier structures by merging both multiplication and squaring operations in a combined construction. Even though the presented structures perform both operations concurrently and perform well in high-speed applications, they are mainly not suitable for embedded devices due to the considerable amount of consumed hardware resources and meaningful wasted power. This is mainly attributed to their parallel systolic/semisystolic structures, which require a large amount of hardware resources, which are limited in resource-constrained embedded devices. Increasing the hardware resources necessary to implement these parallel structures leads to increasing their extracted parasitic capacitances and hence raising the circuit switching activities, resulting in a considerable amount of consumed power that cannot be afforded by the embedded devices.  
In this research article, we present a competent word-based SISO semisystolic processor to perform the bipartite multiplication and squaring algorithm suggested by [PERSON] in [37]. We developed the bit-level version of the suggested algorithm to be able to extract the hardware structure of the semisystolic multiplier and squarer processor. As mentioned in Section 1.2, the processor architecture simultaneously computes both operations and shares the hardware resources, leading to a reduction of the total processing time, hardware resources, and consumed energy. Moreover, the semisystolic array core of the proposed processor has a regular architecture and local interconnections between the processing elements constituting it, making it highly practical for VLSI implementation. The obtained implementation results for the recommended field size \(n=409\) indicate that the proposed multiplier-squarer structure realizes a reduction in the area-time product and consumed energy over the compared competing multiplier structures at specific embedded word sizes, as discussed in the Results Section. The results also confirm that the recommended multiplier-squarer structure is suitable to realize cryptographic primitives in RFID tags, especially semipassive and active tags, that have modest limitations in area and delay and significant restrictions in wasted energy.