## 1 Introduction  
The continuous growth of hyperscale data centers (DCs) designed to handle cloud applications, social media and big data analytics is driving the datacom industry-servers, switches and optical interconnects. Hyperscale DCs are organized in several hierarchy layers and include hundreds of thousands of servers. Thus, they require an efficient interconnection network that is both low-cost and energy-efficient [1; 2]. The DC interconnection network is based on high capacity, high throughput Ethernet switches that handle packet parsing, buffering and queuing. These switch ASICs are characterized by their digital processing power (number of packets processed per second) and the bandwidth of the analog interfaces to the chip (number of I/O ports). With every generation of switch silicon, the I/O bandwidth doubles, thus, enabling faster logic processing capabilities. The current generation of Ethernet switch systems use a 12.8 Tb/s [3] switch bandwidth. The architecture of modern DCs is based on non-blocking Clos topology [4], in which all compute and storage nodes are connected to each other in a full mesh configuration. A prerequisite for such a network is that the switches connecting all the nodes have a large enough chip radix to avoid traffic congestion. However, the number of I/O ports is limited due to packaging constraints, thus forcing an increase in both the optical and electrical line rate with each switch generation. Increasing the electrical lane speed from 50 Gb/s (25 GBd PAM4) to 100 Gb/s (50 GBd PAM4) requires advanced equalization for the serializer-deserializer (SerDes) at each I/O port. A DSP is thus realized at each port to enable the electrical link from the switch across the linecard to the optical transceiver on the front panel of the switch (Figure 1a). Using the advanced 7-nm CMOS node, the power consumption of a single port is in the 700 mW range. Given that a 51 Tb/s switch has 512 ports, the chip I/O consumes about 350 W out of a total chip power of \(\sim\)900 W. This means that less power is available for packet processing, leading to inefficient use of the overall bandwidth. Adding to this figure is the power of the 64 optical transceivers, each at 800 Gb/s (\(\sim\)20 W)-so the switch chip I/O consumes more than 1500 W.  
A second limitation on such high bandwidth devices is related to signal integrity. Routing the high-speed traffic through the switch ASIC package introduces losses due to reflection and impedance mismatch of the signal crossing the package core. These problems are so serious that switch vendors are now considering alternative technologies to enable the next generation of devices [5]. Reducing the SerDes power consumption and improving signal integrity can be carried out only if the long metal traces on the board (Figure 1a) are  
Figure 1: The progress of integrating the optical interconnect with the switch ASIC. eliminated. In that case, the SerDes is required to handle a trace loss of 1-2 dB, compared with the >20 dB trace loss of the standard design. This can be carried out if the optical interconnect is co-packaged with the switch ASIC (Figure 1c). Hybrid integration (Figure 1d) with the III-V optoelectronics assembled directly onto the ASIC was demonstrated to be a very promising approach, notably enabling o triple the number of chip I/O ports [6]. However, several challenges need to be overcome before it can be fully implemented, mainly related to its high complexity and thus relatively high cost. This approach requires a customized fab as each time we change the laser, we must adapt the PIC and vice versa. Therefore, co-packaging is very suitable as an intermediate step before full integration (Figure 1e) may be achieved. More details regarding the extensive work that has recently been carried out on researching the co-integrated optical I/O may be found in the literature [2; 7; 8; 9; 10].