# Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL
## 3 Transistor Level Design of the PLL
### Charge Pump and Phase/Frequency Detector
#### 3.1.1 Charge Pump
switching period, and therefore, although the Drain Switching is the fastest architecture and all of them can be enhanced, increasing the complexity, it has been chosen as the target topology for the whole PLL design. However, it is important to notice that this architecture is intrinsically more complex because there is the need to separate the bias circuits for the UP (M8, M9, M10) and DOWN (M3, M4, M5) branches. Figure 8: Transient behavior of the three CPs of Figure 7. The source current is represented in red, while the sink current is represented in black for two different values of ON time of the input signals (UP and DOWN): 3.2 ns on the left, which corresponds to a duty cycle of 50%, and 500 ps on the right, which corresponds to a duty cycle of 7.8125%. The Drain Switching CP results are represented in (**a**); the Source Switching CP results are represented in (**b**); the Gate Switching CP results are represented in (**c**). Once the CP topology has been chosen, the target architecture has been modified to obtain better performances, as shown in Figure 9 versus Figure 7c. Firstly, the output simple current mirrors have been replaced with high swing current mirrors to enhance the output impedance without degrading the output range too much. This change also allowed the reduction of the sizes of the output transistors, leading to a faster CP. Moreover, both the UP and DOWN branches have their bias circuitry in order to reduce the effect of the UP signal on the sink current and of the DOWN signal on the source current. This has led to an output impedance of 250 k\(\Omega\), with an output range of 0.3-0.9 V. Instead, in terms of DC current mismatch, the worst case of process-temperature corners is 1.454 uA. Regarding the transient characteristics shown in Figure 10, the designed architecture is peak-free, and it is able to start sinking or sourcing the current in less than 500 ps. A differential input Gate Switching CP has also been developed. Indeed, a differential PFD/CP guarantees a better current matching during the switching period, thanks to the symmetric input load of the CP and to the lack of necessity of adding an inverter between one of the PFD outputs and the corresponding CP's input. Hence, the switch transistors have been replaced with differential pairs  
Figure 10: Transient behavior of the CP of Figure 9. The source current is in red, and the sink current is in black for two different values of ON time of the input signals (UP and DW_N): (**a**) 3.2 ns, (**b**) 500 ps. Figure 9: Enhanced CP’s Gate Switching architecture with CMOS standard inputs. (M6-M7 and M8-M9), and the mirror M22-M23 has been added to enhance the switching speed of the source current during the ON-to-OFF switch [21], as shown in Figure 11. The DC characteristics are similar to the previous architecture: an output range of about 0.3-0.9 V, an output impedance of about 250 k\(\Omega\), and a DC current mismatch in the worst case of all the temperature-process variations of 1.66 \(\upmu\)A. Instead, regarding the transient behavior, it is peak-free and shows a better transient current matching, as can be seen from Figure 12.