## 2 FM-ACSK Communication System
### Chaos Generator and Chaotic Synchronization  
For the core element of the proposed communication system, the chaos generator, a fourth-order modified [PERSON]'s circuit model is used. It is a relatively simple chaos generator, but it is rarely used. As we have investigated its properties in past studies [23], we chose to use it for this prototype as a well-known foundation that suits the present task. The chaotic system is defined by the following ODE system:  
\[\left\{ \begin{array}{l}\frac{dp_{1}}{dt}=-g(p_{1},p_{3})-p_{2}\\ \frac{dp_{2}}{dt}=p_{1}+\gamma p_{2}\\ \frac{dp_{3}}{dt}=\theta(g(p_{1},p_{3})-p_{4})\\ \frac{dp_{4}}{dt}=\sigma p_{3}\end{array} \right., \tag{1}\]  
Figure 1: General diagram of FM-ACSK transmitter and receiver. Figure 2: From the top—synchronization error at slave chaos generator with direct input, error at generator with inverse input, and difference of averaged synchronization errors (\(\Delta\)sync) when “10101010” data bits are being transmitted. where \(\gamma\) = 0.5, \(\sigma\) = 1.5, and \(\theta\) = 10 are system parameters; \(p_{1}\)... \(p_{4}\) are the system state variables; and \(g(p_{1},p_{3})\) is a piecewise linear function, which is defined as follows:  
\[g(p_{1},p_{3})= \begin{cases}c(p_{1}-p_{3}-d)&(p_{1}-p_{3})>d\\ 0&(p_{1}-p_{3})\leq d^{{}^{\prime}}\end{cases}  \tag{2}\]  
where \(c\) = 3 and \(d\) = 1. With such parameters, the present system exhibits chaotic behavior, which can be illustrated by the projections of the chaotic attractor (see Figure 3). For digital implementation of this chaos generator in the FPGA, the forward Euler discrete integration method was used, which provides a simple, stable, converging solution of acceptable precision and low FPGA hardware resource usage. The chaos generator is implemented on a 14-bit singed fixed point numeric basis with 8 bits used for the fractional number part. This way, digital nets can represent numeric values from \(-2^{5}\) = \(-32\) to \(2^{5}\)\(-2^{-8}\) = 31.99609375, with a precision of \(2^{-8}\) = 0.00390625. For the chosen chaos generator, these limits are more than enough to represent all chaotic signal values within the generator. The precision is limited due to the limited number of DAC and ADC bits (14) by which the signal is transmitted and received. After applying the forward Euler discrete integration method, the chaos generator equation system (1) can be rewritten as follows:  
\[ \begin{cases}p_{1_{4+1}}=p_{1_{x}}+h(-g(p_{1_{x}},p_{3_{x}})-p_{2_{x}})\\ p_{2_{x+1}}=p_{2_{x}}+h\Big{(}p_{1_{x}}+\gamma p_{2_{x}}\Big{)}\\ p_{3_{x+1}}=p_{3_{x}}+h\theta(g(p_{1_{x}},p_{3_{x}})-p_{4_{x}})\\ p_{4_{x+1}}=p_{4_{x}}+h\sigma p_{3_{x}}\end{cases} , \tag{3}\]  
where \(h\) = (20 \(\times\) 50 \(\times\) 10\({}^{6}\))/1024 is the discrete integration step size, which provides acceptable precision, and is suitable for simple FPGA implementation. The chaotic output from the generator (see Figure 4) is composed of a weighted sum of all system state variables and the following piecewise linear function:  
\[R_{out}=\mathrm{k_{1}P_{1}}+\mathrm{k_{2}P_{2}}+\mathrm{k_{3}P_{3}}+\mathrm{ k_{4}P_{4}}+g(p_{1},p_{3}), \tag{4}\]  
where \(\mathrm{k_{1}}=-2.6302\), \(\mathrm{k_{2}}=-0.6054\), \(\mathrm{k_{3}}=0.5870\), and \(\mathrm{k_{4}}=0.7763\). Figure 3: Modified Chua chaos generator’s attractor projections in different phase planes. The chaotic synchronization between the two modified Chua chaos generators is achieved using an error linear feedback method combined with a substitution of the piecewise linear function in the slave system. As shown in Figure 5, the master chaos generator outputs the weighted sum of all four state variables and the piecewise linear function, while the slave chaos generator uses only the sum of its four state variables, which is subtracted from the input. This way, the piecewise linear function information is reconstructed at the slave system and used to synchronize the state variables.