# Application-Specific Integrated Circuit of an Inter-IC Sound Digital Filter for Audio Systems
## 3 Implementation Results and Discussion  
### FPGA Implementation  
The design was implemented in the Verilog hardware description language with Intel FPGA technology. The register transfer level (RTL) architecture in Verilog of every module, the functional verification, the timing diagrams, and additional material are described in [10]. Figure 7 corresponds to the Intel-Quartus fitter report, which shows the summary of the required logic elements, registers, multipliers, and pins that form the project, with a specific FPGA.  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Process** & **Description** \\ \hline \multirow{2}{*}{Deserialize} & I2S data come from the serialized DAC; this process converts it to a \\  & & parallel bus of 16 bits. \\ \hline \multirow{2}{*}{Push} & Once there is parallel data available, they are entered into the shift \\  & register, shifting all previously entered data to the right and \\  & overflowing the oldest data. \\ \hline \multirow{2}{*}{Multiply} & Perform the 16 words’ calculation given by: \(y(n)=\sum_{n=0}^{15}w(n)x(n)\). \\ \hline \multirow{2}{*}{Serialize} & Serializes the output parallel data to be written to the DAC. \\ \hline \multirow{4}{*}{Save bus} & As seen in Figures 5 and 6, it takes two full cycles of _I2S_LR_ for the \\  & input to be deserialized and pushed into the shift register; therefore, the \\  & shift register needs to be saved before the next data are pushed in, and \\  & the subsequent calculations match with the actual processed data. \\ \hline \multirow{2}{*}{Power} & Calculates the actual quadratic power of the shift register: \\  & \(||x(n)^{2}||=\sum_{n=0}^{15}x(n)x(n)\), to be used in the adaptive filter (only used \\  & in the adaptive filtering mode). \\ \hline \multirow{2}{*}{Write new coefficient} & Calculates and updates the next coefficient given by (2) (only used in \\  & the adaptive filtering mode). \\ \hline \multirow{4}{*}{Repeat the left channel} & When using deterministic filtering, the right and left channels are \\  & filtered by using the same coefficients, but when using adaptive \\  & filtering mode, the left channel (data and noise) will be filtered based \\  & on the right channel (noise); this creates a mono output signal; this \\  & module delays the left channel output 16 clocks to the right channel, \\  & replicating the data and converting them once more to a stereo signal \\  & (only used in the adaptive filtering mode). \\ \hline \hline \end{tabular}
\end{table}
Table 13: Description of the stages involved in the filtering process.  
Figure 6: Adaptive filtering process timing.  
The Cyclone IV FPGA used to emulate the hardware had enough resources for this specific design using only 3% of the total logic elements, 2% of the total embedded multipliers, and no memory bits; instead, the entire design can be achieved by using only registers. Although the entire project can be developed with only 10 multipliers, these are the most-area-consuming cells in the entire project, and this is a critical parameter for the physical implementation. The information shown in Figure 8 was used in the VLSI implementation as the timing requirements; the maximum input frequency, considering 44.1 kHz as the sample rate with a 16-bit stereo input, was 1.4112 MHz; this timing analysis ensured that every critical path can be synthesized.  
The functional validation of the digital audio system prototyped in FPGA technology was carried out with a development platform based on a Cyclone IV FPGA (Terasic DE1) with a Signal Tap embedded logic analyzer. The audio digital signal coming from the I2S was tested with each one of the filter operation modes defined by the FOPT, as was described previously in Table 6. For a more-detailed description and validation of each individual module, refer to [10].