# Design of PAM-8 VLC Transceiver System Employing Neural Network-Based FFE and Post-Equalization
## 4 Architecture of VLC Transceiver Circuits
### Transmitter in VLC System  
The digital baseband in the proposed VLC transmitter consisted of a pseudo-random binary sequence (PRBS) waveform generator, a PAM-8 signal modulator, and an NN-based pre-equalizer using a FFE algorithm, and a DAC generated the analog PAM-8 signal with the FFE. A PRBS-9 signal was generated and encoded, and then it was sent to the PAM-8 modulator. An NN-based equalizer following the modulator added an FFE algorithm to compensate for the limited bandwidth. After this equalizer, the PAM-8 FFE signal was upsampled and transmitted to the AFE in the form of.dat-formatted data.  
\begin{table}
\begin{tabular}{c c c c} \hline
**Type of NN** & **Activation Function** & **Approximation Approach** & **Neuron Layers** \\ \hline RBF-NN & Gaussian Kennel Function & Local Approximation & 3 \\ \hline DNN & Sigmoid Function & Universal Approximation & \textgreater{}3 \\ \hline \end{tabular}
\end{table}
Table 2: Comparison of RBF-NN and DNN.  
Figure 10: Architecture of proposed VLC system with NN-based equalizations.  
The core circuit of the AFE on the transmitter side presented in Figure 10 was the integrated LED driver, and its structure is presented in Figure 11. It consisted of four transistors: M1 and M2 were the differential pair, while M3 was the tail current source and cooperated with M4 to form a current mirror [33]. The differential pair worked in the saturation region for driving the LED with the required output swing. The differential input voltage signals generated from the digital baseband in the transmitter were sent to the gate nodes of M1 and M2, and then the differential outputs were elicited out from the drain nodes. The gain in \(\mathrm{V_{out}}\) to \(\mathrm{V_{in}}\) is equal to \(\mathrm{g_{m}}(\mathrm{R_{L}}/\mathrm{r_{o}})\), where \(\mathrm{g_{m}}\) is the transconductance of the transistor, and \(\mathrm{r_{o}}\) is the output resistance of M1 or M2. The current mirror composed of M3 and M4 was utilized to provide a tail current to the differential pair. Since referred current \(\mathrm{I_{ref}}\) from outside flowing through M4 was smaller than the required tail current, a current mirror that could provide a current with the ratio of the transistor size was necessary. The value of the tail current through M3 was \(\mathrm{I_{ref}}(\mathrm{W_{3}L_{3}}/\mathrm{W_{4}L_{4}})\), where \(\mathrm{W_{3}L_{3}}/\mathrm{W_{4}L_{4}}\) is the transistor size ratio of M3 and M4. The whole CML circuit owned several advantages that made it suitable for a high-speed communication circuit. It owned a simple structure, and the differential pair guaranteed low common mode noise. In addition, the low switching noise decreased the rising and falling times, which improved the switching speeds of M1 and M2. The large output impedance contributed to the low power consumption.  
The passive equalizers shown in Figure 6 were placed after the CML LED driver to extend the modulation bandwidth by serving as a high-pass filter. The model of LED used in this system owned a limited bandwidth of 50 MHz, and it was based on the compact equivalent model of the \(\upmu\)-LED introduced in Section 2. This \(\upmu\)-LED model was also implemented in Cadence with fixed RLC components and a Verilog-A-code-based current-dependent model. For the free-space and underwater channels, their models are illustrated in Section 2, and the channel loss at the alignment occasion of the LED and PD was adopted in this VLC system as the total loss.