# Real-Time Optimization of RISC-V Processors Based on Branch Prediction and Division Data Dependency
## 4 Experiment and Result Analysis
### Stage Experiments and Result Analysis
#### 4.2.1 Branch Prediction Test Results and Analysis  
We implemented two types of branch predictors using Verilog code: the simplified branch history predictor (SLBHP) and the static branch predictor. Both branch predictors were integrated into the Rev-riscv processor. We used Vivado to analyze the resource consumption in both scenarios, as shown in Table 5.  
The simplified branch history predictor (SLBHP) increases the overall resource consumption (LUTs) of the processor by 24% (2723 units) compared to the static branch predictor.  
In the hardware design code, to better monitor the number of jump instructions executed and the number of correct predictions, we have added a jump count register (Skp_counter) to display the number of executed jump instructions. Additionally, we have incorporated a correct jump prediction count register (Skp_right_counter) to show the number of times predictions were accurate. We use the Logic Analyzer (ILA) provided by Vivado to observe the values of these two counters for data collection. A screenshot of the data capture at a particular instance is shown in Figure 11.  
The data were calculated and analyzed, with the prediction accuracy of the static branch predictor shown in Table 6. The prediction accuracy of the simplified local history branch predictor is shown in Table 7.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Serial** & \begin{tabular}{c} **Number of** \\ **Branch** \\ **Instructions** \\ \end{tabular} & \begin{tabular}{c} **Number of** \\ **Correct** \\ **Branches** \\ \end{tabular} & \
\begin{tabular}{c} **Prediction** \\ **Accuracy** \\ \end{tabular} &
\begin{tabular}{c} **Average** \\ **Accuracy** \\ \end{tabular} \\ \hline
1 & 140,890 & 88,338 & 62.7\% & \\
2 & 140,293 & 87,683 & 62.5\% & \\
3 & 140,594 & 89,277 & 63.5\% & \\
4 & 141,122 & 87,072 & 61.7\% & \\
5 & 140,951 & 90,631 & 64.3\% & \\
6 & 140,584 & 89,833 & 63.9\% & 61.3\% \\
7 & 140,964 & 87,116 & 61.8\% & \\
8 & 140,458 & 89,612 & 63.8\% & \\
9 & 140,367 & 89,414 & 63.7\% & \\
10 & 140,485 & 88,646 & 63.1\% & \\ \hline \hline \end{tabular}
\end{table}
Table 6: Accuracy of the static branch predictor.  
Figure 11: A screenshot of the analysis from the embedded Logic Analyzer (ILA).  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Resource Name** & \
\begin{tabular}{c} **Processor with Static Branch** \\ **Predictor** \\ \end{tabular} &
\begin{tabular}{c} **Processor with Simplified** \\ **Local Branch History** \\ **Predictor** \\ \end{tabular} \\ \hline LUT & 11,203 & 13,926 \\ LUTRAM & 4200 & 4216 \\ FF & 6211 & 6410 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Comparison of the main resource consumption of two branch predictors.  
The simplified branch history predictor (SLBHP) can improve the prediction accuracy of the Rev-riscv processor by approximately 10% compared to the static branch predictor.  
In summary, the simplified branch history predictor can increase the branch prediction accuracy of the processor by about 12% compared to the static branch predictor at the cost of consuming approximately 24% (2723 units) more LUT resources. The total LUT resources of the FPGA development board with model XC7A100T are 53,200. A resource consumption of 2723 units is within an acceptable range.