# Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions
## 4 Results  
A complex evaluation of the proposed floorplanning solution was performed. Compatibility with Xilinx Vivado tools and general propriety of the operation was tested in static overlay design implementation. Manual floorplans used in the partition relocation tests described in the previous study by the main author of this manuscript [29] were replaced with the results generated by the automated floorplanner proposed in this article. The tool correctly identified identical regions in all tested Xilix 7-Series FPGAs. The automatically generated floorplans were successfully used in the Xilinx Vivado implementation flow. Figure 9: Directional consistency in PBlock selection process. In logical array PE(1,1) is located in direction \([-1,-1]\) from its predecessor PE(2,2). To preserve consistent geometry, it should be assigned to a region situated below and to the left of A. However, in the next iteration more elements—PE(0,0), PE(0,1), PE(1,0)—need to be located farther in that direction. Although the position of C in relation to A is consistent with PE(1,1) to PE(2,2) direction, selecting C would result in later placement of elements PE(0,0) and PE(0,1) to the right of PE(1,1)—as no regions are available in their preferred directions. Moreover, if D is used for PE(2,1) or worse PE(3,1), too many elements will opt for PBlocks E and F, resulting in some of them being placed far from their optimal location. Despite immediate directional inconsistency, PE(1,1) should prefer D over C.  
The quality of results and execution time of the proposed partition to PBlock assignment procedure based on initial modified breadth-first search and fine 2-opt improvements has been evaluated and compared to the simulated annealing approach, which is used in most state-of-the-art solutions. The common objective function was used in both cases. As the results of any stochastic method depend greatly on the randomly selected start point, average values calculated from repeated simulated annealing searches were used to mitigate the influence of this deviation. Additionally, the floorplan found in the modified breadth-first search of the custom solution is used as a starting point for simulated annealing instead of 2-opt in a so-called hybrid approach. For a better quantitative measure of the quality of the generated floorplans, reference objective-function values, calculated as an average for 10 random floorplans for each case, are presented as well. Tables 1 and 2 present objective-function and elapsed time for the partition to PBlock assignment of various overlays in Artix7 xc7a200t and Virtex7 xc7v2000t, respectively. Results for simulated annealing with constant (30 for A, 100 for B) and PE array size dependent (5 xy for C) number of iterations between temperature decrements are presented. Oversizing this parameter results in long execution time, despite procedure termination when a limit of cycles without changes is reached. On the other hand, if too few steps are used in a large search space, the obtained results have worse objective-function values. Further analyses use simulated annealing and scale the parameter with array size, as this approach seems to offer better results. Improvement of the starting point solution used in the hybrid approach has little impact on the execution time and objective function compared to random start point if the same set of parameters is used. The proposed custom search is several orders of magnitude faster than simulated annealing and offers solutions of comparable quality. Large deviations in 2-opt stage execution time are possible, as the procedure is terminated as soon as an iteration with no swaps occurs. The proposed solution seems to offer a significant advantage when floorplanning large arrays.