## 1 Introduction
There are several works related to the single-architecture design related to LED block ciphers [19; 20; 21; 22; 23; 24; 25] and the PHOTON hash function [19; 26; 27; 28; 29; 30]. These designs were synthesized on different hardware platforms and targeting different optimization goals. Several authenticated encryption architectures based on different composition methods were presented, including the latest designs in [10; 21; 31; 32; 33; 34; 35]. However, some of them were synthesized and simulated on different platforms and others consume large amounts of logic resources when composing the encryption with the authentication. The work in [10] integrated the PRESENT block cipher [36] and the SPONGENT hash function [37] to construct an authenticated encryption. Both PRESENT and SPONGENT were designed by the same group with similar permutation functions. Therefore, the authors of [10] achieved a good reduction rate of logic resources by sharing the common functions within both primitives. However, they implemented their design in ASIC and reported their results in Gate Equivalent. Additionally, their design resulted in a very low operating frequency and throughput. The authors of [21; 31] presented an authenticated encryption composed of an LED block cipher [38] and a PHOTON hash function [39], with the objective of reusing the common datapath functions and reducing the footprints. They achieved a considerable operating frequency and throughput; however, they could share only small parts of the datapath and achieved a low reduction rate of the footprints. Additionally, they implemented their design on Xilinx FPGA and reported their results in Slices. The work reported in [33] utilized the AES block cipher with an Offset Tow Round (OTR) to create an authenticated encryption. They implemented their design on Altera Startix FPGA from the Virtex family. They achieved high speeds and reduced the logic resource utilization to almost half of the original architecture design. However, their reduced architecture design is still considered high when compared to other proposals. The authors of [34; 35] introduced an authentication framework for smart homes and industrial environments. They utilized Ascon authenticated encryption with a hash function to construct their architecture, as referenced in [34], and an AEAD encryption algorithm with a hash function, as referenced in [35]. However, their design was implemented on software and their results were reported based on the computational, communication, and storage costs. The work reported in [40] introduced a new proposal of authenticated encryption submitted to the NIST. The work was implemented on Xilinx FPGA Sparta 6. They achieved higher speeds but at the cost of larger footprints, even compared to their competitors' proposals. In this study, an authenticated encryption (AE) architecture is proposed that aims to reduce its footprint compared to other existing AE architectures. This is accomplished by employing the most minimal versions of the LED block cipher (LED-64) and the PHOTON hash function (PHOTON-80/20/16) and sharing similar resources between the two. The round-dependent constants generated by the linear feedback shift register (LFSR) serve a dual purpose: they control the permutation rounds and the multiplexer selectors. Furthermore, employing look-up tables (LUTs) in place of Galois multiplications decreases the computational intensity of the _MixColumns_ matrices, leading to the reduced utilization of logical resources. These shared resources, combined with the use of LFSR and LUTs, make a substantial impact in terms of minimizing the logic resources needed for the architecture of the AE (authenticated encryption).