# 185-215 GHz CMOS Frequency Doubler with a Single Row Staggered Distribution Layout Design
###### Abstract  
This paper presents a 220 GHz \(\times\) 2 amplifier-doubler chain composed of a rat-race balun, a 6-stage driver amplifier, and a frequency doubler. The presented amplifier-doubler chain was fabricated in commercial 40 nm bulk CMOS technology. The maximum cutoff frequency \(\mathrm{f}_{\mathrm{max}}\) for the NMOS transistor produced by this manufacturing process was 290 GHz. The saturation output power of the six-stage driver amplifier at 110 GHz was 11.5 dBm. The transistor of the frequency doubler consisted of a single-row interleaved Poly-Diffusion Contact balancing structure. Theoretically, the single-row interleaved Poly-Diffusion Contact balancing structure was able to effectively avoid parasitic components. The simulated results demonstrate that the presented structure achieves a higher output than the conventional designs. Based on these measured results, the presented amplifier-doubler chain provides a peak output power of 7.9 dBm at 200 GHz and a 3-dB bandwidth of 30 GHz. Based on the comparison with other reported results, the presented amplifier-doubler chain provides the highest output power among reported frequency doublers fabricated in CMOS technology.  
doubler; frequency multiplier; terahertz (T  
are used as the substrates' transistor can achieve low insertion loss [22; 23], and the passive devices fabricated under the III-V group process have a good quality factor [24]. In recent years, with the increasing cut-off frequency of silicon-based processes, more and more reports have been reported of implementing a 220 GHz frequency multiplier using silicon [25; 26]. Among silicon-based processes, the CMOS process is the most commercially valuable [27; 28]. It has the advantages of low noise, high reliability, fast response, low power consumption, functionality, and economy. These advantages have led to an increasing number of studies focusing on the design of the frequency multiplier in the CMOS processes. In 2016, [PERSON] et al. demonstrated a 160-310 GHz frequency doubler for rotational spectroscopy with a driver amplifier in a 65 nm bulk CMOS process [29]. At 0-dBm input power, the measured output power (Pout) varied from 3 to \(-8\) dBm. In 2021, [PERSON] et al. implemented a \(\times 9\) frequency multiplier chain with a 3-dB bandwidth of 213-233 GHz in a 40 nm bulk CMOS. The chain realized a 4.1 dBm peak output power without using power combining [30].  
In this paper, an amplifier-doubler chain including an integrated 110 GHz rat race balancer, a driving amplifier (DA), and an active doubler with an output frequency covering 185-215 GHz was designed. The 110 GHz Rat race balancer converted the single-ended signal to a differential signal with low insertion losses. The drive amplifier (DA) used a sixth-order pseudo-differential structure to ensure sufficient power input to the frequency doubler. The structure of the frequency doubler used a single-row interleaved Poly-Diffusion Contact balancing structure to replace the traditional two-separated transistors' topology, which reduced the parasitic components of the frequency doubler. According to the results of the measurement, the output power of the frequency doubler reached 7.9 dBm.