## 2 Buck Converter Modeling
```
1:\((iL_{n+1},vC_{n+1})\leftarrow\textsc{calculateRK4}(iL_{n},vC_{n},dt,R,L,C,S1,S2,v_{s})\)
2:if\(sign(iL_{n+1})\
eq sign(iL_{n})\) AND \(S1=open\) AND \(S2=open\)then\(\triangleright\) iL crosses zero
3:\(dt1\gets dt\times abs(iL_{n})/(abs(iL_{n})+abs(iL_{n+1}))\)
4:\(dt2\gets dt-dt1\)
5:\((iL_{intermediate},vC_{intermediate})\leftarrow\textsc{calculateRK4}(iL_{n},vC_{n}, \textbf{dt1},R,L,C,S1,S2,v_{s})\)\(\triangleright\) first time step
6:\((iL_{n+1},vC_{n+1})\leftarrow\textsc{calculateRK4}(iL_{intermediate},vC_{ intermediate},\textbf{dt2},R,L,C,S1,S2,v_{s})\)\(\triangleright\) 2 nd step
7:endif
```

**Algorithm 5** Simulation and Implementation Results

Table 3 compares the error obtained in the simulation using the proposed Algorithm 4 implemented in 64-bit floating point. The errors were measured at \(dt=1\) us, and the reference was the calculation with the same algorithm and \(dt=10\) ns. The error values obtained with the initial algorithm, shown in Table 2, are repeated for comparison. Both for the inductor current \(iL\) and the capacitor voltage \(vC\), the error remains in the same order of magnitude as with no zero-crossing events. Note that the values for \(R=7.5\)\(\Omega\) are identical, as expected, since the if-then block of the algorithm was never executed and therefore identical operations were performed in both cases. The error for both \(v_{C}\) and \(i_{L}\) in cases with many zero-crossing events are comparable to those of cases with no zero-crossing events. This shows that the proposed method for time step subdivision modeled with Algorithm 4 returns the accuracy in the calculations, which was lost when the zero-crossing events were introduced in the simulation. The right half of Figure 6 shows the error in the calculation of inductor current as a function of the \(dt\) chosen. The curves show in all cases a slope of 4 before reaching machine epsilon, which proves that the loss of accuracy was caused by the mis-detection of the inductor current crossing zero. The left half of Figure 6 shows the error in the calculation of capacitor voltage. The curves are similar to those of the inductor current, which shows that using the proposed substep approximation, the propagation of the error due to the interdependence of \(i_{L}\) and \(v_{C}\) variables no longer takes place. ### Fixed-Point Implementation

The error calculations above were performed with the 64-bit floating-point representation of the state variables. This ensures that the optimal assignment of integer and fractional bits is made in all steps of the calculation. The small error values on the order of \(10^{-12}\) are an indication of this. However, the designer of a hardware-in-the-loop system also needs to perform trade-offs between low error and complexity in order to achieve real-time calculation speed. For this, the VHDL code for both Algorithms 2 and 4 was translated from 64-bit floating point into fixed point representation for all steps of the calculation. The translation of all state variables and constants into fixed point was performed with the method proposed in [23]. Maximum values for state variables are estimated to determine how many integer bits are assigned. The number of fractional bits is derived from the minimum estimated incremental value. Then, additional fractional bits are added to store small-value increments with an accuracy of more than one bit. Bit assignment to constants follows a similar process. Integer bits are assigned based on real values. Extra bits are added based on the desired accuracy of the represented values. Constant expressions containing a division, such as \(1/(R\times C)\), \(1/C\) and \(1/L\) were pre-calculated in 64-bit floating point and the results were assigned a number of fractional bits.