# A Radiation-Hardened Low-Power SRAM with Enhanced Write Capability for Space Applications
## 1 Introduction  
With the advancement of the space industry, satellite-based communication technology has become a core technology in various fields, including military intelligence gathering, disaster monitoring, climate observation, and the construction of global network infrastructure [1]. Given the increasing demand for high integration density in modern satellite systems, ensuring stable operation under harsh radiation environments has become a critical design challenge. To ensure the stable operation of such systems in extreme space environments, it is crucial to employ memory devices that can maintain data integrity even under radiation exposure. Among various memory technologies, static random-access memory (SRAM) has been widely utilized in space applications due to its fast access speed, high integration density, and low power consumption [2]. However, unlike terrestrial environments, outer space continuously exposes semiconductor circuits such as SRAM to high-energy particle radiation, making them highly susceptible to soft errors. When a high-energy particle strikes a reverse-biased junction in a semiconductor, electron-hole pairs are generated. If these carriers accumulate at a sensitivenode, they induce a short voltage pulse known as a single-event transient (SET) [3]. When the amplitude of this pulse exceeds the threshold voltage of the node, it can flip the stored data, resulting in a SEU [4]. The threshold voltage refers to the minimum gate voltage required to turn on a transistor. Moreover, as CMOS process technology continues to scale down and the spacing between transistors becomes narrower, charge-sharing effects are exacerbated. Consequently, a single particle strike can affect multiple nodes simultaneously, leading to SEMNUs [5]. To mitigate these radiation-induced faults, several circuit-level techniques, such as error correction codes (ECC) and radiation-hardened by design (RHBD), have been employed. ECC detects and corrects errors through encoded data structures, but the inclusion of encoding and decoding logic increases circuit complexity and computational delay [6]. In contrast, RHBD enhances circuit resilience by structurally optimizing the topology to provide internal recovery paths in the event of SEUs or SEMNUs [7]. This approach is considered a more practical solution, as it ensures the high reliability required in space while minimizing area and power overhead. In this paper, we adopt an RHBD-based approach to mitigate the impact of SEUs and propose the EWS-16T cell, which offers high write performance and low power characteristics. The proposed cell comprises 16 transistors and includes two storage nodes (Q and QB) and two internal nodes (S0 and S1). By separating the write path from the storage path and minimizing the number of sensitive nodes, the EWS-16T achieves high operational reliability. In particular, Q and S0 are designated as sensitive nodes, and the design allows for self-recovery from SEUs occurring at a single node. Although recovery is limited when both sensitive nodes are simultaneously struck, the cell layout ensures sufficient spacing between transistors to reduce the likelihood of charge-sharing-induced SEMNUs. Furthermore, the proposed cell demonstrates the best write performance, the shortest write access time, and the lowest hold power consumption among all compared cells [8; 9; 10; 11; 12]. EWS-16T distinguishes itself from previous designs, such as SAW16T and RHSCC16T, by optimizing radiation tolerance and improving write performance while minimizing power consumption. Unlike SAW16T, which struggles with SEMNU recovery and high power consumption, and RHSCC16T, which faces significant area and power overheads, EWS-16T offers superior efficiency by separating the write path from the storage path, reducing sensitive nodes, and enhancing reliability without the drawbacks of increased complexity or power usage. This makes EWS-16T a more efficient and practical solution in radiation-prone environments. The rest of this paper is organized as follows.