## 2 Background
### Fault Injection Methods for SEU Analysis  
Depending on the method used to analyze the single-event upset (SEU) in electronic equipment, it can be classified into the following four types: (1) hardware-based fault injection, (2) software-based fault injection, (3) simulation-based fault injection, and (4) emulation-based fault injection.  
(1) Hardware-based fault injection involves creating a physical fault in an integrated circuit and is mainly divided into two methods. The first method is contact-related fault injection, which employs tools such as pin-level fault injection to perturb the circuit [16; 17; 18]. The second method is contactless fault injection, where an external source utilizes physical phenomena like heavy ion radiation to induce faults in the circuit [5; 6; 7]. This approach offers the advantage of accurate system error rate (SER) evaluation but comes with challenges, including high cost, the inability to reproduce test results, and difficulties in detailed analysis, such as fault propagation analysis.  
(2) Software-based fault injection is a technique used to investigate software errors by intentionally introducing errors into a running software system. This can be carried out in the following two primary ways: injecting errors directly into the code and triggering errors through a specific mechanism [8; 9]. The trigger mechanisms include timeouts (activating fault injection when a timer expires), software traps (transferring control to a fault injection module), and code injection (modifying the program instructions to induce a fault) [19; 20; 21]. These methods are valuable for testing and analysis because they allow for the intentional introduction of faults and provide clear traceability of results. In particular, they are effective in identifying vulnerabilities and analyzing errors. However, it should be noted that the efficiency decreases as the size and complexity of the code being analyzed increases. As the codebase grows larger and more complex, the time required for analysis increases exponentially.  
Figure 2: Example of an SEU occurrence in CLB of SRAM-based FPGA.  
(3) Simulation-based fault injection is a mechanism that analyzes faults by injecting faults during the simulation of the hardware design code [22; 23; 24; 25]. The representative methods include the saboteur method of synthesizing a fault module within the design code, a method of introducing a fault provided within a simulation, such as \"force\", and a method of authorizing a fault by accessing the kernel during testing. Research has also been carried out to rapidly and precisely estimate the system error rate (SER) from limited test data through the use of Monte Carlo simulations [26; 27; 28; 29]. These methods are cost-effective and can provide more accurate sensitivity analysis because they can calculate both the fault injection rate and injection location. However, as the complexity of the analysis circuit increases, there is a problem of rapidly increasing analysis time and complexity.  
(4) Emulation-based fault injection is a method of artificially inducing a phenomenon similar to SEU on the actual target board in order to address the challenges of hardware/software fault injection methods [10; 11; 12; 13; 14]. The emulation method applies bit flip-flops from radiation testing to the actual boards to analyze the effects of failures, thereby reducing testing costs and time. It also offers the advantage of being able to reproduce test results. However, there are challenges in establishing an emulation test environment, such as a deep understanding of the target board and implementation difficulties.  
Table 1 summarizes the characteristics of four fault injection techniques. As a result, if accessibility to test environment construction is guaranteed, the fault injection technique of the emulation technique can be found to be very attractive.