# A Low-Power Read-Decoupled Radiation-Hardened 16T SRAM for Space Applications
## 2 The Proposed LDRH16T Cell and Its Operation
### Soft-Error Recovery Analysis  
Transient recovery waveforms and operating behavior of the LDRH16T cell are illustrated in Figure 4. When a high-energy particle strikes the drain region of a reverse-biased OFF-state transistor, excess carriers are generated within the device, producing a transient current pulse at the drain [5]. A node located near the reverse-biased drain diffusion region is considered a sensitive node [17]. Generally, when a radiation particle impacts a PMOS transistor, only a positive transient--such as a '1' \(\rightarrow\) '1' or '0' \(\rightarrow\) '1' transition--can occur, depending on the node's initial logic level. In contrast, for NMOS transistors, only negative transients such as '1' \(\rightarrow\) '0' or '0' \(\rightarrow\) '0' are possible. Therefore, when the LDRH16T stores logic '1', the storage node QB holds '0' and is surrounded solely by NMOS transistors, making the only possible upset a non-inverting '0' \(\rightarrow\) '0' transition. Similarly, the internal node S1 holds '1' and is connected only to PMOS drains, so it can only undergo a non-inverting '1' \(\rightarrow\) '1' transition during an SEU event. As a result, both QB and S1 can be regarded as insensitive nodes [21]. In hold mode, the proposed memory cell has only two sensitive nodes: Q and S0.  
(1) SEU at node Q: When an SEU inverts the stored logic value at node Q from '1' to '0', transistor P5 turns ON, while transistors N2 and N4 turn OFF. Although P5 becomes active, transistors N3 and N1 remain OFF due to the logic level at node QB, thereby maintaining the logic state of node S1. Moreover, since transistor P2 is designed to be stronger than P5, S1 is held even more firmly at its original logic level. As a result, transistors P1, P4, and N6 remain OFF, allowing S0 and QB to retain their respective values. Consequently, transistors  
Figure 4: SEU resilience verification waveform of the proposed LDRH16T cell.  
P2, P3, and N5 remain ON, while N1 stays OFF, enabling node Q to recover its original logic '1' state.  
(2) SEU at node S0: When an SEU causes the internal node S0 to flip from its initial value '0' to '1', transistor N6 turns ON, while transistors P2 and P3 turn OFF. Since P2, P3, and N1 (the latter being OFF due to the hold mode) are all inactive, nodes S1 and Q enter a high-impedance state. In this state, both pull-up and pull-down paths are disconnected, preventing any change in their logic levels. Meanwhile, node QB remains at logic '0' because transistor N2 stays ON, controlled by the logic level at node Q, thereby pulling QB down to GND. Since nodes Q, QB, and S1 are unaffected by the SEU and remain in their original states, node S0 is eventually pulled down to GND through transistors N2, N4, and P6, restoring its initial logic '0' state.  
(3) SEMNU at node Q and S0: When a SEMNU occurs, the initial logic values at nodes Q and S0--'1' and '0', respectively--are flipped to '0' and '1'. As both nodes transition simultaneously, each loses its recovery mechanism, resulting in a permanent logic inversion. However, this type of charge-sharing-induced SEMNU can only occur when the distance between two PMOS transistors is less than 1.62 \(\upmu\)m or when the distance between a PMOS and an NMOS transistor is less than 0.6 \(\upmu\)m [4]. Therefore, ensuring sufficient spacing between transistors further enhances immunity to SEMNU. As shown in Figure 2, the layout of the proposed LDRH16T cell ensures a physical separation of 6.378 \(\upmu\)m between nodes Q and S0, thereby preventing SEMNU from occurring between this sensitive node pair [19].