# Effect of Thermal via Design on Heat Dissipation of High-Lead QFN Packages Mounted on PCB
## 3 Simulation Results
### Integration of Thermal Via with I/O Pads on PCB  
While introducing thermal via around the thermal pads can enhance the heat dissipation performance of the QFN package, the efficiency of heat transfer from the die to these thermal via is relatively lower, resulting in suboptimal heat dissipation. To further optimize the heat dissipation efficiency, we consider the placement of thermal via around the I/O pads and integrate these thermal via with the I/O pads (Figure 10). To ensure simulation accuracy, the distance between the thermal vias and the I/O pads is set at 0.3 mm. Figure 11 shows the temperature distribution of three different types of QFN packages under these conditions. The maximum temperatures of the conventional QFN, the dual-row QFN, and the high-lead QFN packages are 52.4 \({}^{\circ}\)C, 52.6 \({}^{\circ}\)C, and 52.0 \({}^{\circ}\)C, respectively. It is evident that among these three QFN packages, the high-lead QFN package demonstrates the best heat dissipation performance when thermal vias are combined with the I/O pads, resulting in a reduction of 6.4 \({}^{\circ}\)C in the maximum temperature. Therefore, this approach significantly enhances the heat dissipation efficiency of the QFN package. Furthermore, this method also substantially lowers the temperature of the solder joints, thereby reducing solder joint thermal stress and improving the solder joint's operational lifespan. To further validate the excellent thermal performance of high-lead QFN, the variation of the maximum temperature of the three QFN packages with different thermal via diameters and copper plating thicknesses was discussed. Firstly, with the copper plating thickness of 0.02 mm, the effects of thermal via diameters ranging from 0.2 mm to 0.5 mm on chip heat dissipation were investigated. Subsequently, keeping the thermal via diameter at 0.3 mm, the copper plating thickness was gradually increased from an initial value of 0.01 mm to a maximum of 0.15 mm, ensuring that the vias were fully filled with copper. Figure 12 illustrates the variation of the maximum temperature under different thermal via diameters. It is observed that with an increase in thermal via diameter, the maximum temperature decreases gradually for all three QFN packages, concurrently reducing thermal stress. The maximum temperature of the conventional QFN package has decreased from 53.5 \({}^{\circ}\)C to 50.6 \({}^{\circ}\)C. For the dual-row QFN package, the maximum temperature has decreased from 53.883 \({}^{\circ}\)C to 50.614 \({}^{\circ}\)C. The high-lead QFN package has seen a reduction in its maximum temperature from 53.1 \({}^{\circ}\)C to 50.2 \({}^{\circ}\)C. This is attributed to the larger thermal via diameter, which increases the contact area between heat and air, thus enhancing heat convection. Notably, the high-lead QFN package consistently maintains the lowest maximum temperature. Figure 10: Integration of thermal vias with I/O pads: (**a**) conventional QFN, (**b**) dual-row QFN, and (**c**) high-lead QFN. Figure 11: Temperature distribution with integration of thermal vias and I/O pads under reference conditions: (**a**) conventional QFN, (**b**) dual-row QFN, and (**c**) high-lead QFN. Figure 12: Maximum temperatures for different thermal via diameters. Figure 13 presents the variation of the maximum temperature under different copper plating thickness conditions. The results indicate a general increase in the maximum temperature for all three QFN packages as the copper plating thickness increases. The maximum temperature of the conventional QFN package increased from 52.4 \({}^{\circ}\)C to 54.9 \({}^{\circ}\)C. The maximum temperature of the dual-row QFN package increased from 52.6 \({}^{\circ}\)C to 55.5 \({}^{\circ}\)C. The maximum temperature of the high-lead QFN package increased from 52.0 \({}^{\circ}\)C to 54.5 \({}^{\circ}\)C. This rise is attributed to the increased copper thickness elongating the heat transfer path, subsequently elevating thermal resistance and affecting the heat dissipation effectiveness of the thermal vias.