## 3 Hardware Speedup: Advanced Sensors and Ultra-Fast Computing Platforms
### SPAD Arrays as High-Resolution Time-Resolved Sensors  
A relevant part of the speedup that we are seeking is determined by replacing commercial high-resolution sensors, like scientific CMOS and EMCCD cameras, with sensors based on cutting-edge technology such as single-photon avalanche diode (SPAD) arrays. A SPAD is basically a photodiode which is reversely biased above its breakdown voltage, so that a single photon which impinges onto its photosensitive area can create an electron-hole pair, triggering in turn an avalanche of secondary carriers and developing a large current on a very short timescale (picoseconds) [17; 18]. This operation regime is known as Geiger mode. The SPAD output voltage is sensed by an electronic circuit and directly converted into a digital signal, further processed to store the binary information that a photon arrived, and/or the photon time of arrival. In essence, a SPAD can be seen as a photon-to-digital conversion device with exquisite temporal precision. SPADs can also be gated, in order to be sensitive only within temporal windows as short as a few nanoseconds, as shown in Figure 3. Individual SPADs can nowadays be used as the building blocks of large arrays, with each pixel circuit containing both the SPAD and the immediate photon processing logic and interconnect. Several CMOS processes are readily available and allow for tailoring both the key SPAD performance metrics and the overall sensor or imager architecture [43; 44]. Sensitivity and fill-factor have for some time lagged behind those of their scientific CMOS or EMCCD counterparts but have been substantially catching up in recent years. Based on the requirements of QPI, we have chosen to employ the SwissSPAD2 array developed by the AQUA laboratory group of EPFL, characterized by a 512 \(\times\) 512 pixel resolution (see Figure 4), which is one of the widest and most advanced SPAD arrays to date [20; 22]. The sensor is internally organized as two halves of 256 \(\times\) 512 pixels to reduce load and skew on signal lines and enable faster operation. It is a purely binary gated imager, i.e., each pixel records either a 0 (no photon) or a 1 (one or more photons) for each frame, with basically zero readout noise. The sensor is controlled by an FPGA generating the control signals for the gating circuitry and readout sequence and collecting the pixel detection results. In the FPGA, the resulting one-bit images can be further processed, e.g., accumulated into multi-bit images, before being sent to a computer/GPU for analysis and storage. The maximum frame rate is 97.7 kfps, and the native fill factor of 10.5% can be improved by 4-5 times, for collimated light, by means of a microlens array [21] (higher values are expected from simulation after optimization); the photon detection probability is 50% (25%) at 520 nm (700 nm) and 6.5 V excess bias. The device is also characterized by low noise (typically less than 100 cps average Dark Count Rate per pixel at room temperature, with a median value about 10 times lower) and advanced circuitry for nanosecond gating. A detailed comparison of SwissSPAD2 with other large-format CMOS SPAD imaging cameras is presented in Ref. [22]. Currently, we are using the available version of SwissSPAD2, with a 512 \(\times\) 256 pixel resolution, to generate sequences of frames and store them in an on-board 2 GB memory, before transferring them to a computer by a standard USB3 connection, which can be done using existing hardware. We are integrating this sensor in the prototype of chaotic-light base quantum plenoptic camera in a way that two disjoint halves of the sensor (of 256 \(\times\) 256 pixels each) are used for retrieving the images of the two reference planes.