# Updates on Impact Ionisation Triggering of Thyristors
## 2 Materials and Methods
### Gate-Boosting of SiC MOSFETs  
Gate-boosting is a method aimed at speeding the switching transitions of SiC MOSFETs. It is based on the application of an overvoltage on the gate terminal during the commutation time of the device; thus fighting the internal lead inductance and semiconductor structure parasitic capacitances while avoiding permanent damage on said structure. Its effectiveness has been proven in [24], and we succeeded in testing the gate-boosting on a single transistor in previous works ([19; 20; 21; 22]). After this test phase, we proceed to the next phase, where we seek to trigger several SiC MOSFET transistors in parallel in order to increase the output current of the pulse generator to more than 220 A, as the requirements explained in Section 2. We decided to trigger all parallel SiC MOSFETs by a common driver to simplify the system, thus avoiding synchronization issues that could arise from using individual drivers for each transistor. We address the potential problematic coupling of the six parallel transistors between themselves by adding a microstrip to each branch. A microstrip is a transmission line configuration consisting of a conductive trace mounted on a dielectric substrate, with a ground plane on the reverse side [25]. This setup facilitates controlled impedance and effective signal propagation. This physically decouples the SiC MOSFET's respective drains and adds a certain time delay; this said delay is compensated by the geometrical property of the connection. Figure 2 shows the schematic including the six gate-boosted SiC MOSFETs and the corresponding microstrips acting as transmission lines, and Figure 3 shows a 3D rendering of the PCB layout. To ensure gate boosting of these devices, the values of capacitors C2_1 through C2_6 are adjusted. These capacitors are used to counteract the impact of both input and reverse transfer (Miller) capacitance inherent in the SiC MOSFET being triggered. In our strategy, we prioritize controlling the total injected MOS gate charge (\(Q_{tot}\)) rather than attempting to measure or restrict the gate-source voltage at the wafer level. To maintain adherence to this criterion, we use a capacitor (C2_1 to _6) in series between the driver output and the MOS gate. The choice of their value follows Equation (1):  
\[(U_{drmax}-U_{gmax})\cdot\text{C2\_i}=Q_{tot}(\text{@}U_{gmax}) \tag{1}\]  
where  
Figure 2: Schematic of the six SiC MOSFETs (_SiC_1 to _6), with the corresponding microstrips, in parallel. * \(U_{dr_{max}}\) represents the maximum output voltage of the gate driver circuit. * \(U_{gmx}\) is the absolute maximum allowable gate-source voltage. * \(C2\_i\) is the value of the series capacitor between the driver output and corresponding MOS gate. * \(Q_{tot}(@U_{gmx})\) denotes the total gate charge extrapolated from the datasheet curve at the maximum gate voltage. This equation is rooted in three assumptions:  
1. \(Q_{tot}\) follows a linear progression with the gate applied voltage and can as such be extrapolated, as per [26]. 2. All relevant voltages are initially zero before triggering. 3. After the SiC reaches complete turn-on, the driver output voltage becomes \(U_{dr_{max}}\), the MOS transistor gate-source voltage reaches \(U_{gmx}\), and the series capacitor accumulates a charge of \((U_{dr_{max}}-U_{gmx})\cdot C2\_i\). As \(C2\_i\) is in series with the MOS gate, an equivalent charge is delivered to the MOS gate. While acknowledging a transient period and a brief duration of overvoltage on the gate, these considerations are intentionally deemed acceptable. Regarding the gate resistors \(R2\_1,3,5,7,9,11\) and \(R2\_2,4,6,8,10,12\), they form a voltage divider with the goal to fix the DC gate voltage to \(<\)20 V, at \(Udr_{Vmax}\) as per [26]. It is important to note that any momentary spikes in the gate voltage exceeding this threshold during the commutation time have limited effects given the sub-nanosecond timescales involved.