# Quantum Circuit-Width Reduction through Parameterisation and Specialisation
## 5 Derivation of Parameterised Comparator Circuits  
In Section 1, the concept of the comparator step in quantum circuit implementations of a long-division based quantum integer divider was introduced. An example quantum circuit that performs the comparator step for two 4-qubit registers was shown in the top half of Figure 4, where the quantum circuit design followed the work of [PERSON] et al. [33]. In this section, an alternative type of quantum comparator circuits will be derived that facilitates automated quantum circuit reduction steps. Specifically, the aim is to create comparator circuits where, in contrast to the quantum comparator shown in Figure 4, the qubits defining the divisor in the long division will remain unchanged in the circuit and where these qubits can only acts as control qubits in quantum gate operations. For an \(n\)-qubit comparator, the derivation works as follows.  
* An \((n+1)\)-qubit ripple-carry modulo adder of the type introduced by [PERSON] acts as starting point where subtraction of two positive numbers can be achieved by having one of the \((n+1)\)-qubit inputs represent an \(n\)-qubit number in 2's complement, while the second input will have its leading qubit in state \(|0\rangle\);
* For a specific choice of the \(n+1\) qubits defining the divisor in 2's complements representation, qubit specialisation steps of the type previously illustrated in Figure 5 for a 3-qubit modulo adder are applied;
* The reduced circuits that result from this process represent a subtraction operation by the integer value represented in negative form by the 2's complement representation;
* Next, the gate operations in the reduced circuits are sorted in \(n+1\) groups, where each group represents gate operations affecting the state of each of the \(n+1\) qubits from the second (remaining) input string;
* To create the comparator circuit, the group acting on the most-significant qubit of the input qubit register is selected, while the rest of the gate operations can be ignored;
* The subtractor circuits discussed in Section 6 are similarly created by using the gate operations from each of the \(n+1\)groups identified.  
Since the interest is only in positive divisors defined by a qubit string with the most-significant qubit in state \(|1\rangle\), \(2^{n-1}\) specialised, reduced circuits can be defined. For \(n=3\) and \(n=4\), the top half of Figures 8 and 9, respectively, shows these circuits for specific values of the divisor. As a final step in creating a parameterised comparator, the gate operations from these \(2^{n-1}\) specialised circuits are parameterised using the qubits defining the divisor. Two options are available here. First, the use of the \(n\) qubits defining the divisor in its original form. Alternatively, the \(n+1\) qubits defining the divisor in \(2\)'s complement representation can be used. Design choices made in the quantum circuit implementation of the integer divider determine which approach is the most suitable. In this work, for qubit registers where prime superscripts are used in qubit indices, the integer representation is in \(2\)'s complement representation. The next subsections show the quantum comparators for \(n=3\), \(n=4\), and \(n=5\) to illustrate the results of the specialisation for divisors represented by an increasing number of qubits.  
Figure 8: Comparator circuits for use in quantum dividers with 3-qubit divisor. Parameterisation with divisor qubits and with 2’s complement representation of divisor shown in lower half.  
Figure 9: Comparator circuits for use in quantum dividers with 4-qubit divisor. Parameterisation with 2’s complement of the divisor is shown in the lower half.