## 4 Space-Qualified RF Generator Techniques
### DDS Inside an FPGA  
The use of a Direct Digital Synthesis (DDS) RF generator is already established due to multiple space missions [28; 29; 30]. The principle consists of a of DDS core implemented inside a space-qualified Field Programmable Gate Array (FPGA). The core is written in a hardware description language like Verilog or VHDL. The output frequency \(RF_{OUT}\) depends on the tuning word \(M\) and on the N-bits wide phase accumulator (Figure 6). By adapting the value of \(M\), the \(RF\) output frequency can be changed [31; 32]:  
\[RF_{OUT}=\frac{M\cdot f_{CLK}}{2^{N}} \tag{5}\]  
in which \(f_{CLK}\) is the system clock frequency. The output of the phase accumulator is applied to the Lock-Up Table (LUT), in which the phase information is converted into a digital sine wave. The output of the LUT is applied to a Digital-to-Analog Convertor (DAC), which generates a differential output signal. Based on the Nyquist theorem, a minimum of two digital sinewave period samples need to be sent to the DAC for appropriate analog sinewave reconstruction. Practically, the RF output frequency is limited to 30-40% of \(f_{CLK}\)[31; 32]. The generated output spectrum of the DDS technique is a sampled stepping waveform, having an output amplitude (\(Ampl_{OUT}\)) with a \(sin(\text{x})/\text{x}\) dependency. The latter is calculated as [31; 32]:  
\[Ampl_{OUT}=\frac{sin\left(\frac{\pi\cdot RF_{OUT}}{f_{CLK}}\right)}{\frac{ \pi\cdot RF_{OUT}}{f_{CLK}}} \tag{6}\]  
The spectrum consists of many different harmonics and spurs, which need to be removed in order to generate a pure sinewave. The combination of a balun and a low-pass filter at the output fulfills this task. Components applicable to be used in space applications, based on the abovementioned technique, are the rad-tolerant DAC5675A-SP of Texas Instruments (Dallas, Texas, USA) [33], combined with a space-qualified Virtex 4 or Virtex 5 FPGA of Xilinx [34]. Taking into account size and power consumption, the Virtex 4 is the preferred choice. This device, having a clock frequency of 400 MHz, is capable of covering the VIS and NIR optical ranges. For the UV range, a frequency doubler is needed. This will impose additional harmonics and spurs that need to be filtered in an adequate manner. As an alternative, the RTAX of the Microchip can be used [35]. A huge disadvantage is the low clock frequency at which this device runs (127 MHz). This will limit the output frequency of the DDS to 50 MHz. This can be circumvented by using a pipelined DDS setup. However, this could possibly cover the  
Figure 6: DDS principle. frequency range up to the VIS range but certainly not for the UV. A third possible candidate is the RTG4 of the Microchip [36]. This device is able to generate a clock frequency of 400 MHz (comparable with the Virtex 4) but consumes more power, PCB area, and mass. A fourth option is the NG Medium FPGA developed by NanoXplore (Sevres; France) [37]. This device is also able to cover the frequency up to the VIS range. Based on the availability, mass, power consumption, and used PCB area, the Virtex 4 FPGA, combined with the Texas Instruments 14-bit DAC5675A-SP, was used in a test setup (Figure 7). Due to the limited clock frequency of 400 MHz, the VIS optical range (and partially the UV range) can be covered by using a steerable double switch at the output of the setup. This switch is necessary to cover a frequency range of more than one octave (45 up to 180 MHz). Two seventh-order passive Cauer filters (a low-pass filter with a cut off at 90 MHz, and a bandpass filter 90-180 MHz) were used, in combination with an AD8001S RF amplifier of Analog Devices [38]. The latter is used to increase to output power level up to an acceptable level (>0 dBm). In order to communicate with the Virtex 4 FPGA, a Universal Serial Bus to Universal Asynchronous Receiver-Transmitter (USB-to-UART) transformer is used. All necessary supply voltages are generated based on a +5 V input.