## 3 SOC Balancing
### SOC Balancing Control Strategy
This intrinsic correlation enables automatic SOC balancing through conventional capacitor voltage regulation when all ESMs within an arm share a common controller, eliminating the need for additional SOC balancing control. Submodule capacitor voltage balancing is typically achieved by a real-time sorting algorithm [36]. This strategy determines the operational states of ESMs based on both capacitor voltage and arm currents' direction. During the discharging state, ESMs with higher submodule capacitor voltages are preferentially for insertion, while those with lower voltages are bypassed. Conversely, in the charging state, the opposite action is taken. However, the balancing algorithm is applied unconditionally to every control cycle of the arm, and the gate signals are updated at the sampling control frequency. This process results in redundant switching operations, even when the total number of inserting ESMs in one arm remains constant. High switching frequencies create significant power losses as heat, lowering system efficiency and requiring longer balancing times. More critically, these continuous losses increase operating temperatures, accelerating aging in both power devices and supercapacitor energy storage systems [37; 38]. The rapid switching also generates damaging electrical stresses on IGBTs. Cumulative stress leads to gradual performance degradation or failure, impairing both the SOC balancing accuracy and system responsiveness [39; 40]. Ultimately, these combined effects exacerbate SOC imbalances and significantly shorten the system's operational lifespan. To address this issue, a reduced switching-frequency (RSF) voltage balancing algorithm is proposed [41]. Figure 5 illustrates both the conventional submodule capacitor voltage balancing algorithm and the RSF algorithm. In contrast to the conventional algorithm, the RSF voltage balancing algorithm introduces the concept of the submodule capacitor voltage unbalance degree \(\sigma\), defined as the ratio of the maximum voltage deviation among submodules to the rated capacitor voltage. When the submodule capacitor voltage unbalance degree exceeds the threshold value \(\sigma_{\text{m}}\), all submodule capacitor voltages are sorted. Otherwise, only the incremental ESMs are sorted according to their capacitor voltages. Figure 5: Flowchart of submodule capacitor voltage balancing strategy. The capacitor voltage balancing control strategy capitalizes on the operational flexibility of the submodule insertion number to regulate charging and discharging durations. This dynamic voltage regulation inherently enables SOC balancing among all ESMs within each arm by exploiting the voltage-SOC correlation. In contrast to the traditional strategy requiring \(N\) independent controllers per arm, the proposed strategy achieves equivalent balancing performance with only six centralized controllers. This represents an \(N\) times reduction in controller hardware while maintaining equivalent voltage and SOC regulation performance. In summary, the final power command for the ESMs in each arm is shown in Equation (18):  
\[P^{*}_{\text{sc},rj}=\frac{P^{\text{pref}}_{\text{sc}}}{6}+\frac{1}{2}\Delta P _{\text{sc},j}+\Delta P_{\text{sc},rj}, \tag{18}\]  
where \(P^{\text{pref}}_{\text{sc}}\) is the power command before SOC balancing is applied.