# A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis
## 3 TSV Reliability  
### Copper Contamination  
After completing the silicon via etch in high aspect ratio TSVs, it is necessary to deposit an insulating dielectric liner to increase the breakdown voltage and reduce current leakage. The electromigration (EM) wear mechanism observed in contemporary CMOS damascene copper interconnects primarily involves void formation and expansion. Notably, the maximum divergence of current flow takes place in proximity to the via at the cathode of the line, resulting in void nucleation at the interface between copper and the dielectric layer (Cu/SiN or Cu/SiCN). This interface is particularly vulnerable due to its poor adhesion properties, leading to a high diffusion rate and making it the weakest point. Consequently, the presence of an inadequate barrier can lead to the occurrence of leakage currents. Therefore, ensuring the deposition of suitable liner, barrier, and seed technologies is essential for achieving reliable process integration [42]. In order to ensure the reliability of the liner, a negative voltage is applied to the TSV to attract copper ions towards the voltage source, preventing them from being injected into the pad during the test. This method allows for the study of the inherent characteristics of the liner. The barrier performance, on the other hand, is analyzed by comparing measurement results obtained in the copper closed mode with those obtained when a positive voltage is applied to the TSV. In case of barrier defects, copper ions are pushed into the liner during the latter stress mode. A significant difference in TDDB data between the two modes may indicate poor barrier characteristics. Therefore, it is essential to conduct these tests to ensure that the TSVs  
Figure 8: Cu-confined and Cu-driven schematic (adapted from [41]). (**a**) TDDB data of Cu-confined model (**b**) TDDB data of Cu-driven model. meet the desired reliability standards, and to improve the liner and barrier deposition technologies to achieve optimal performance [21, 35, 43]. In addition, the electrical characteristics of through-silicon vias (TSVs) are influenced by several factors, including the geometry, material properties, and temperature of the tsv. As a result, numerical calculations in simulation software become more complicated and time-consuming. To accurately model the behavior of tsv, simulation software must consider a wide range of parameters, such as the length, width, aspect ratio, and shape of the tsv. Additionally, the electrical properties of the surrounding dielectric and conductive materials, as well as the temperature-dependent behavior of the tsv, must also be considered. Despite the complexity of simulating tsv, various software tools, such as the high-frequency structure simulator (HFSS) and computer simulation technology (cst), are available to calculate the transmission characteristics of tsv. These tools employ numerical methods, such as finite element analysis (FEA) and finite difference time domain (FDTD), to model the behavior of tsv and predict their electrical performance. By simulating tsv using these software tools, designers can optimize the tsv geometry and material properties to achieve desired electrical characteristics, including high bandwidth, low insertion loss, and low crosstalk. The electrical characteristics of tsv are determined by several factors, making numerical simulations complex and time-consuming. However, software tools, such as HFSS and CST, can be used to model the behavior of tsv and predict their electrical performance. By optimizing the tsv geometry and material properties using these tools, designers can achieve the desired electrical characteristics of tsv for high-performance electronic applications. Atomic migration (AM) is a significant concern for the reliability of backend of line (BEOL) interconnects, which refers to the mass transport of metal atoms caused by the electron wind and intensified by temperature. Therefore, atomic migration consists of electromigration (EM), stress migration (SM), and thermal migration (TM).