## 3 PUF
### Improving Inter-HD
#### 3.3.2 Improving Row Performance  
By improving column performance, inter-die HD of stuck columns improves by 1.7X-4X (individually). However, total inter-HD remains poor (\(\approx\)28%) due to poor performance of some rows that exhibit 0% inter-HD. Further, we observe that the rows with poor inter-HD are mainly stuck to either all 0s or all 1s. The rows stuck to 0s (perhaps due to higher thermal stability) are fixed by re-writing them with higher write time to trigger statistical flipping. The row stuck to all 1s (perhaps due to low thermal stability) are fixed by re-writing them with lower write time.  
After improving row/column performances, we obtain inter-HD of 46.25% which is close to the ideal value. The proposed improvement technique incurs one-time energy (\(\approx\)2.7X) and computational overhead during the enrollment phase. Furthermore, it should be noted that, alternative improvement technique of masking the rows/blocks of rows incurs significant area overhead. For the case of Figure 11, 75% bits are lost if masking is implemented. The energy, bandwidth and area of the wPUF are 0.14 pJ/bit, 0.34 Gbit/s, 0.385 \(\upmu\)m\({}^{2}\)/bit (including all peripheral circuits). Table 2 benchmarks proposed wPUF with existing MRAM/STTRAM PUFs. We can observe that the proposed PUF is comparable to prior works. It should be noted that (i) the proposed PUF is based on a commercial chip which gives practical process variation; and, (ii) the data bus is 8 bit long, therefore the bandwidth is comparatively low.  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**PUFs**} & \multirow{2}{*}{\begin{tabular}{c} **Inter-Die HD** \\ **(\%)** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Inter-Die HD** \\ **(\%)** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Inter-Die HD** \\ **(\(\upmu\)m\({}^{2}\))** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Entropy** \\ **(\(\upmu\)m\({}^{2}\))** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Area (MT)** \\ **(Gbit/s)** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Bandwidth** \\ **(pJ)** \\ \end{tabular} } & \multirow{2}{*}{\
\begin{tabular}{c} **Energy/bit** \\ **(pJ)** \\ \end{tabular} } & \multirow{2}{*}{
\begin{tabular}{c} **Experimental** \\ \end{tabular} } \\ \hline
[15] & - & 50.1 & 0.985 & 0.046 & 6.4 & - & No \\ \hline
[17] & 0.02 & 47 & 0.99 &
\begin{tabular}{c} 6.74 \\ (64 bit) \\ \end{tabular} & 12.8 & - & Yes \\ \hline
[27] & 7.76 & 60.6 & - & 0.065 & 6.4 & 2.42 & No \\ \hline
[28] & - & 49.89 & 0.95 & 0.005 & 6.4 & 0.001 & No \\ \hline wPUF & \multirow{2}{*}{0} & \multirow{2}{*}{
\begin{tabular}{c} 22.5 (before) \\ 46.26 (after) \\ \end{tabular} } & \multirow{2}{*}{0.95} & \multirow{2}{*}{0.385 1} & \multirow{2}{*}{0.34} & \multirow{2}{*}{0.14 1} & \multirow{2}{*}{Yes} \\ \hline \hline \end{tabular}  
* \({}^{1}\) includes decoder, sense amp, and other peripheral circuitry and considers 100 mil \(\times\) 100 mil of die size for TSOP-II IC package.  
\end{table}
Table 2: Performance comparison of different MRAM/STTRAM PUFs with the proposed wPUF.  
Figure 11: Average inter-HD of 10 chips for first 80 rows (8 rows/block).