# COTS Battery Charge Equalizer for Small Satellite Applications
## 3 Implementation of the Selected Balancing Methods
### Delta-Structured Switched Capacitor Equalizer  
This section describes the implementation of a passive balancing method based on a switched capacitor architecture. The principle of operation is based on the periodic connection of adjacent cells through capacitors, allowing the redistribution of the cells' charge without the need for magnetic components. The Figure 1A shows the electric schematic diagram of the topology.  
The main reason for choosing this topology is the ease of converting it into a fault-tolerant circuit. The multiple energy transfer paths allow continuous operation if any transistor or capacitor fails. It is worth noting that it is necessary to place a fuse in series with each switch, so in case of a short-circuit, the affected branch is disconnected, ensuring that the remaining components maintain balance without any problems.  
Figure 1: Schematic diagrams of the chosen topologies. (**A**) DSSCE topology; (**B**) SFCBE topology.  
As stated in [19], there are two asymptotic limits that have great importance in the selection of the switching frequency in this balancing method: the slow-switching limit (SSL) and the fast-switching limit (FSL).  
On the one hand, in the SSL the capacitors have enough time to fully charge and discharge during each switching period. Its associated resistance R\({}_{\text{SSL}}\) is dominated by the capacitive elements, and energy losses are mainly due to the finite amount of charge transferred through the balancing capacitors. According to [31], for this specific configuration, this parameter can be calculated with Equation (1).  
\[R_{SSL}=\frac{2.88}{\text{C}\cdot f_{sw}} \tag{1}\]  
where 2.88 is the sum of the multiplier coefficient of the capacitors, \(C\) is the capacity of the balancing capacitors, and \(f_{sw}\) is the switching frequency.  
On the other hand, in the FSL the capacitors do not reach full voltage equilibrium during each phase. Its associated impedance R\({}_{\text{FSL}}\) is governed by the conduction losses across the switches and can be calculated with Equation (2), which was developed in [19].  
\[R_{FSL}=5\cdot R_{eq} \tag{2}\]  
where 5 is the double of the sum of the multiplier coefficients of the switches, and \(R_{eq}\) is the sum of the ON drain-source resistances of the switches and the measured PCB traces' resistance.  
According to [31], if an efficient design is intended, both impedances must be equal, obtaining Equation (3).  
\[C=\frac{2.88}{5\cdot R_{eq}f_{sw}} \tag{3}\]  
Through this expression, it is possible to choose an optimal theoretical operating point where neither conduction losses nor switching losses dominate the system. Figure 2 illustrates the R\({}_{\text{FSL}}\) impedance, as well as several R\({}_{\text{SSL}}\) impedances as functions of the switching frequency for different \(C\) values with R\({}_{\text{eq}}\) = 190 m\(\Omega\). As can be seen at lower frequencies, the energy losses due to energy transfer are higher. Furthermore, it is important to note that at higher frequencies, the switching losses of the system are higher, and the influence of the stray inductances in the real implementation is also greater. Consequently, it is necessary to consider all type of losses in the selection of the optimal operating point. In this particular case, it was determined that a capacity of 60 uF for the balancing capacitor and a frequency of 50 kHz were the optimal values for this implementation.  
Figure 2: Intersection of different SSL and FSL impedance curves as a function of switching frequency for this design.  
Table 2 presents the manufacturer and product number of the main components of the equalizer. It is important to note that the total capacity of the balancing capacitors was achieved by using six 10 \(\upmu\)F capacitors in parallel in the indicated model. Consequently, this approach resulted in a substantial decrease in the total ESR of the capacitors.