# Design of K-Band Power Amplifier with 180-Degree Phase-Shift Function Using Low-Power CMOS Process
## 3 Simulation and Measurement Results  
In this study, we designed a power amplifier for 5G communications using the 40-nm CMOS LP process that provides eight metal layers to verify the feasibility of the proposed structure. The design parameters of the used device are shown in Figures 2 and 4. Figure 7 shows a photograph of the designed power amplifier with 180\({}^{\circ}\) phase-shift function in the first driver stage. In the chip photograph, the first, second, and third driver stages were sequentially placed from left to right. The power stage is situated on the right-most side in the chip photograph. The chip size was 1.19 \(\times\) 0.61 mm\({}^{2}\), including all test pads. The core size was 0.97 \(\times\) 0.23 mm\({}^{2}\), excluding all test pads and decoupling capacitors. To secure AC ground, the decoupling capacitors were placed near the test pads. However, since the power amplifier in this study was designed in a differential structure, the decoupling capacitor played an auxiliary role and the virtual ground of the differential structure was actively utilized for the AC ground. As can be seen in Figure 7, there is no additionally required chip area for implementing the 180\({}^{\circ}\) phase-shift function. The used supply voltage, V\({}_{\rm DD}\), of the designed power amplifier was 1.1 V. In the case of the first stage with the cascode structure for phase-shift function, the gain could be increased by using a higher supply voltage; however, the first stage also used a supply voltage of 1.1 V to minimize the additionally required low-dropout (LDO) regulators. As shown in Figure 8, in the frequency range of 22.0 GHz to 26.0 GHz, the simulated gain was higher than 28.4 dB and the gain flatness was 1.4 dB or less. Originally, the power amplifier was designed through simulation with a typical corner model. However, in the worst case, the size of the transistor was determined in preparation for being implemented as a slow corner. After measuring the DC current of the power amplifier manufactured in a foundry, it was confirmed that the power amplifier was manufactured as a slow corner. Since the designed power amplifier was made as a slow corner, the simulation results were performed under slow corner conditions. As a result of the simulation of the k-factor, we confirmed that the designed power amplifier was unconditionally stable. In the first stage, with 180\({}^{\circ}\) phase-shift function, a difference in measured \(S\)-parameters between 0\({}^{\circ}\) and 180\({}^{\circ}\) modes occurred due to parasitic components occurring at the cross-over region circled in Figure 4.  
As illustrated in Figure 9, the power amplifier has a saturation power (\(P_{sat}\)) of 16 dBm or more in the frequency range of 22.0 GHz to 26.0 GHz. However, for the same reason of the parasitic components occurring at the cross-over region of the metal lines, as shown in Figure 10, the power and PAE were measured to be degraded in the 180\({}^{\circ}\)-mode compared to the 0\({}^{\circ}\)-mode. The measured P\({}_{\rm 1 dB}\) for the 0\({}^{\circ}\)- and 180\({}^{\circ}\)-modes were 15.25 dBm and 14.30 dBm, respectively, in the operating frequency of 25.0 GHz. Figure 7: Photograph of the designed CMOS power amplifier. Figure 8: Simulation and measurement results: S-parameters. Figure 10: Measurement results: gain and PAE according to the output power: (a) 0\({}^{\circ}\)- and (b) 180\({}^{\circ}\)-modes. Figure 9: Simulation results: gain and PAE according to the output power: (a) 0\({}^{\circ}\)- and (b) 180\({}^{\circ}\)-modes. As shown in Figure 11, the measured phase difference between 0\({}^{\circ}\)- and 180\({}^{\circ}\)- modes was 217\({}^{\circ}\) at the frequency of 25.0 GHz.