## 1 Introduction
The dynamic response is as desirable as possible, while the E-P characteristic is still of the drop type, and due to the inverse relationship between reactive power and frequency, the \(\omega\)-Q characteristic must be of the incremental type [17]. Using a predetermined virtual inductor and estimating the feeder impedance, the slope of the voltage droop characteristic is corrected to compensate the voltage fluctuations across the feeder impedance variation [18]. Nevertheless, to estimate the feeder impedance, it is necessary that the  
Figure 1: A typical microgrid (MG) considering distributed generations (DGs). MG be operated in grid connected mode before operating in the islanding mode. In [19], the point of common coupling (PCC) voltage harmonics is measured and sent via a telecommunication link to the local controller (LC) of each DG to estimate the feeder impedance. This estimation is based on the assumption of a small difference in the phase angles difference between the source voltage and the PCC voltage. Through measuring the feeder current, the authors in [20] presented an approach to estimate the feeder impedance. It is worth noting that there are many methods in grid control considering the parallel inverters, but they use complicated calculations to determine the control loop coefficients such as fuzzy [21], artificial neural network (ANN) [22], sliding mode control (SMC) or combined with space vector modulation [23; 24], multi agent [25], hierarchical process [26], and master slave techniques [27]. Phase locked loops (PLLs) have many applications in the field of power engineering to detect the operation frequency. In cases where the synchronous operation of a converter is required, the most common method is to use PLL. However, network disturbances due to noise, unbalancing, and harmonics can impair the performance of a PLL and the system connected to it [28; 29; 30]. PLLs are found in modulators, de-modulators, state-of-the-art frequency suppliers, and a variety of signal processes. The PLL mechanism is described as follows: if the input signal is not equal to the internal oscillator signal, the amplified phase error signal causes the voltage controlled oscillator (VCO) frequency to deviate from the input signal direction. Under proper conditions, the VCO signal completely locks in the input signal. Note that the output signal of phase detector is DC and the control input of VCO has some frequency harmonics with it. The output of VCO should be a signal with a generated frequency equal to the input. Therefore, it is somewhat difficult to detect and clean the input from noise. Because any slight variation in the potential difference of the circuit will cause a frequency shift, and the VCO output can compare and lock a triangular, sine wave, or whatever noise which is generated by the operation method. Consequently, the noise will appear in the PLL outputs [31; 32]. In order to avoid observing these malfunctions, an appropriate scheme is proposed in this paper based on classic stationary frame and Clarke transformation. The novelties of presented paper are mentioned in bullet below:  
* A modified proportional-resonant (PR) controller is proposed to overcome reactive power sharing errors considering feeder impedance effect. This leads to a more simple implementation than other complicated approaches. * Some modifications are applied to the conventional PLLs to develop the performance. This can help us to detect phase shift and harmonic compensation. * The simplicity of proposed method has raised the accuracy and system response in each case study. This causes low overshoot and minimized settling time. This paper is organized as follows: in Section 2, the existing PLLs are described and the modified PLL is proposed. Section 3 describes the proposed PLL validation using some control indices such as settling time and overshoot considering some case studies. The system under study with PR controller and problem formulation are presented in Section 4.