## 3 Advanced Techniques in Fault Injection and Error Rate Estimation
### Automatic Configuration Memory Fault Injection Tool
#### 3.2.3 Statistical Fault Injection Testing Process Using ACMFI  
This section explains the process of statistical fault injection testing using ACMFI. Figure 8 illustrates the system flowchart of the host PC and the target board in accordance with the statistical fault injection testing process. The statistical fault injection testing procedure using the ACMFI tool mainly involves three steps, and each sub-process is outlined in Figure 9. In this section, the statistical fault injection testing procedure using the ACMFI tool is explained in detail, based on each sub-process. Figure 8: System Flow Chart ((**a**) Host PC and (**b**) Zybo Z7-20 Board). Figure 9: Automatic Configuration Memory Fault Injection operation flowcharts and captures. Step 1-1: Set Up Fault Space  
This is the stage where the user selects spatial information for fault injection. The user should click on the \"Test Scenario Setting\" tab, input the X and Y coordinates of the identified CLB accurately, and then click the \"Fault Space\" button. When this task is completed, the FPGA Fault Injection Tool identifies the clock region from the input information and presents the user with the fault injection range (memory range), as shown Figure 10.  
Step 1-2: Decide Number of Tests  
The step for setting the number of fault injection tests is a procedure for configuring the test quantity in statistical fault injection testing. Once the user specifies the desired confidence interval, the number of tests that fulfill that criterion is computed. When the user clicks the preferred confidence interval button within the \"Confidence Interval (CI)\" group box, the number of tests at the bottom is generated automatically. For example, we can observe that the number of tests satisfying the 95% confidence interval for one SLICE (X_L: 47 Y_L: 100 / X_H: 66 Y_H: 124) is set to 8378. Step 1-3: Create Test List  
Generating a fault injection command list is a step in which a fault injection location is randomly selected within a specified fault injection range for the chosen number of tests, and a corresponding fault injection command is generated. The fault injection command can be represented as 10 hexadecimal ASCII words combined with the \"N\" instruction. The structure of the word is illustrated in the diagram below, and the user is responsible for creating a command accordingly and inputting it into the SEM IP. Clicking the \"Test Scenario\" button in the upper right corner generates SLICE information and fault injection commands for the predetermined number of tests, then displays them to the user. Step 2-1: Connect Target Board  
Connecting the target board is a step used to verify if normal operation has been established after connecting the host PC and the target board (Zybo Z7-20) through micro-USB. They establish a connection via UART serial communication, and the target board sends a SEM IP initialization report to the host PC. The transmitted report information can be viewed in the reception window of the FPGA Fault Injection Tool. The user should go to the \"Automatic Testing\" tab and configure the port number for the target board then click the \"Connect\" button. When the port connection is successfully established, the port is opened, and the message changes. Following this, when we initiate the target board, the  
Figure 10: Set up fault injection space. SEM IP report window appears in the receiving window. The Figure 9 illustrates the result screen for a successful connection to the target board. Step 2-2: Start Fault Injection Test  
The fault injection test is an automated step in which the commands from the fault injection command list created in step three are sequentially transmitted to the SEM IP of the target board, and the test results are received. The test results are categorized as either \"normal\" or \"failure\", and any deviation from the golden module result is considered a \"failure\". The test concludes when the selected number of tests is completed or when the target board fails to self-recover.