# All-Digital Computing-in-Memory Macro Supporting FP64-Based Fused Multiply-Add Operation
## 4 Simulation and Discussion
\begin{table}
\begin{tabular}{c c c c} \hline  & **Input** & **Output** \\ \hline a & **b** & **c** & **d** \\ \hline
0x40485194a3294653 & 0x4043b7c6 tf9 edf3e & 0x408c3336e66 dccdc & 0x40a608 ee290e4081 \\ (48.64) & (39.44) & (902.40) & (2820.47) \\ \hline
0x4056764 ede9 dbd4 & 0x40340 aa015402a80 & 0x407726f04 de09 bc1 & 0x40a0f6 acacac57 ff \\ (89.86) & (20.04) & (370.43) & (2171.34) \\ \hline
0x40345982b305660b & 0x4052a5794b297e5 & 0x4084a6c84d909b21 & 0x40a64445c82b8f97 \\ (29.35) & (74.59) & (660.85) & (2850.14) \\ \hline
0x4053b5a96b52d6a6 & 0x403633c46788 cf12 & 0x408507b58 ff6b1 ed6 & 0x40a2 eeb45c197595 \\ (78.84) & (22.20) & (672.96) & (2423.35) \\ \hline
0x40580 ec81d903b20 & 0x40585a4 fb596 bd3 & 0x4077c61f8c3f187e & 0x40c30 da89 eda44c6 \\ (96.23) & (97.42) & (380.38) & (9755.32) \\ \hline
0x40224 af495e92 bd2 & 0x4056940f281e503d & 0x408d1d98 bb317663 & 0x409b76f7d900 be1 \\ (9.15) & (90.31) & (931.70) & (1757.74) \\ \hline
0x40182 bb05760 aec1 & 0x4051e68 fd19a3f & 0x405128b6516 ca2d9 & 0x40754e634717e2c \\ (6.04) & (71.60) & (68.64) & (501.31) \\ \hline
0x4035 cbdb97b72f6e & 0x402e5 dacb5976b3 & 0x4085b413e827d050 & 0x409005c4f3053501 \\ (21.80) & (15.18) & (694.51) & (1025.44) \\ \hline
0x4019d4b3a96752 cf & 0x4042658 cbd197a3 & 0x407 edc24b8497093 & 0x4086 db06849 fa665 \\ (6.46) & (36.80) & (493.76) & (731.38) \\ \hline
0x4050f2 ffe5 ffcc00 & 0x40574e329c6538 ca & 0x40882 edcddb9 bb73 & 0x40 bbb601b2e4538b \\ (67.80) & (93.22) & (773.86) & (7094.01) \\ \hline
0x40558770 fe1 dcfc & 0x4058a97952f2a5e5 & 0x407146c8 df91 bf2 & 0x40c121 dc66 cd7400 \\ (86.12) & (98.65) & (276.44) & (8771.72) \\ \hline
0x40454d4a9a95352a & 0x40425f44 be897d13 & 0x408073 cc6798 cf32 & 0x40a057d8496a0647 \\ (42.60) & (36.74) & (526.47) & (2091.92) \\ \hline
0x402b9 cf739 ee73 dd & 0x4045124e249c4939 & 0x4081a05840b08161 & 0x409i7931 bfd1a3 \\ (13.81) & (42.14) & (564.04) & (1145.89) \\ \hline
0x404 ed729 ae535 ca7 & 0x402c429885310a62 & 0x40842 ee7 ddcfbb9f & 0x4097b5 ad8d59 deb1 \\ (61.68) & (14.13) & (645.86) & (1517.42) \\ \hline
0x3 ffdeebbdd77 baef & 0x4042f095e12 bc258 & 0x408d9f3d527a7 cf5 & 0x408 fd627 ca73d130 \\ (1.87) & (37.88) & (947.90) & (1018.77) \\ \hline \end{tabular}
\end{table} 
Table 2: Sample 2 results of **DCIM-FF**. The **DCIM-FF** was synthesized with CMOS-55 nm technology with normal case parameters using related software. As shown in Figure 6, it dissipates 0.12-2.16 mW at 50-150 MHz operating frequency with 0.9-1.32 V supply voltage. The power efficiency of **DCIM-FF** can reach up to 26.9 TOPS/W. Compared to previous FMA designs, the proposed **DCIM-FF** macro achieves FMA functionality with significant power efficiency improvement and less area overhead, based on CIM technology. The comparison of **DCIM-FF** with some other FMA works that support FP64 arithmetic is shown in Table 3[30; 31; 32; 33; 34]. DCIM-FF completes a FMA operation for a total of nine computation cycles, which causes a delay of 60 ns at 150 MHz operating frequency. There are four computation cycles of DCIM-FF consumed in the pipeline architecture of adder trees and five computation cycles consumed in the normalization operation of the FP64_adder module. The throughput of DCIM-FF can be obtained by calculating the reciprocal of the delay, which is approximately 16.7 MOPS and represents the number of operations that can be completed by the macro per second. As can be seen from Table 3, the comprehensive performance of the proposed design in [33] is optimal among all references. Ref. [33] presented a three-stage, eight-level, pipelined, dual-precision FMA design that can perform operations either at one double-precision or at two single-precisions in parallel. In terms of area and power consumption, DCIM-FF takes over 65% less area and improves power efficiency by more than 50% compared to the previous FMA design in [33].