## 4 Proposed Method
### Implementation of APUIF  
Originally, FPGAs were primarily used for proof-of-concept (PoC) and prototype development. However, they continue to be valuable in applications that demand high performance, low latency, and real-time adaptability. As a result, FPGAs are especially well-suited for tasks that require rapid prototyping, hardware acceleration, customization, and long-term reliability. Cyclone IV devices are composed of logic elements (LEs), which include four-input lookup tables (LUTs), memory blocks, and multipliers, as listed in Table 2. The M9K memory block provides 9 Kbits of embedded SRAM and can be configured as single-port, simple dual-port, or true dual-port RAM, as well as FIFO buffers or ROM. In delay-based PUFs, such as arbiter PUFs implemented on FPGAs, the propagation delays of input and output signals through LUTs determine their responses. Additionally, the placement of LUTs on the FPGA fabric and the routing between them impact propagation delays, ultimately affecting the behavior of the arbiter PUF.  
The internal architecture of LEs in Altera Cyclone IV FPGAs is depicted in Figure 11. Each LE comprises a flip-flop, a lookup table (LUT) configurable as either a four-input,  
Figure 10: Proposed framework.  
one-output, or a three-input, one-output LUT, and fast carry logic. A total of 16 LEs are stacked into a Logic Array Block (LAB), and depending on the FPGA family version, the device may include up to 8000 LABs. Each LE contains a configurable register that can be set to operate as a D, T, JK, or SR flip-flop. The clock and clear input signals to these registers can be sourced from the global clock network, general-purpose I/O pins, or internal logic. LEs can be configured to operate in two distinct modes. The normal mode is used to implement general-purpose logic and combinational functions, supporting up to four data inputs from the local interconnect of the LAB. The second operating mode is the arithmetic mode, which is optimized for arithmetic functions such as adders, counters, accumulators, and comparators. In arithmetic mode, the LE functions as a 2-bit full adder with a carry chain, and the output is available in both registered and unregistered versions from the LUT. This versatile structure of the LEs enables designers to optimally implement a wide range of digital logic and arithmetic operations.  
Intel Quartus Prime 18.1 software configures the operating mode of each LE based on the design logic, optimization constraints, and synthesis settings. FPGA design implementation begins with the logic synthesis stage, followed by a planning stage that manages periphery placement, clock allocation, and early global retiming. During the subsequent placement stage, LEs are assigned and grouped into Adaptive Logic Modules (ALMs) and LABs on the FPGA. This stage also ensures the correct positioning of block RAM and DSP elements within the FPGA fabric, which is in accordance with the user's design. Finally, in  
Figure 11: Altera Cyclone IV logic elements.  
\begin{table}
\begin{tabular}{l c} \hline \hline
**Resources** & \# \\ \hline Logic elements (LEs) & 10,320 \\ \hline Embedded memory (Kbits) & 414 \\ \hline Embedded 18 \(\times\) 18 multipliers & 23 \\ \hline General-purpose PLLs & 2 \\ \hline Global clock networks & 10 \\ \hline User I/O banks & 8 \\ \hline Maximum user I/O & 179 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Cyclone IV E (EP4 CE10) device resources.  
the routing stage, all connections in the design are established using the programmable routing fabric of the FPGA, ensuring proper signal flow across the chip [127].