## 2 Literature Review  
Several publications explore the application of CI and PDI techniques to increase the sensitivity of GNSS receivers. Ref. [11] investigates and assesses the performance of several PDI techniques, including Non-coherent Post-Detection Integration (NPDI), Differential Post-Detection Integration (DPDI), Generalized Post-Detection Integration Truncated (GPDIT), Squaring Detector (SD), and GPDITSD, which employs the GPDIT strategy and the SD. The evaluation of these techniques involves the use of three types of clocks: a TCXO, a Chip Scale Atomic Clock (CSAC), and an OCXO. In [22], an analysis is performed to identify the most effective PDI technique in the presence of various impairments like data bit transitions and frequency offset. Additionally, [12] conducts a comprehensive investigation into current PDI techniques, specifically addressing the impact of phase noise originating from two different clocks: a TCXO and an OCXO. Ultimately, the PhD thesis [7] consolidates comprehensive insights and benchmarks the most relevant PDI techniques for acquiring GNSS signals under the challenging conditions mentioned above (phase noise, frequency offset, and the presence of data bits). According to the simulation results presented in [7], a receiver equipped with a TCXO can reliably acquire GNSS signals at a \(C/N_{0}\) as low as 20 dB-Hz. This achievement is possible by employing the GPDIT strategy, using a CI time of 100 ms, and allowing for a maximum of seven non-coherent combinations. These conditions result in a total integration time of 700 ms. The GPDIT strategy is not robust against data bit transitions, necessitating that the receiver either eliminates the modulated data or utilizes pilot signals. This approach is implementable in the FPGA and facilitates the acquisition of GNSS signals in soft indoor scenarios. For this reason, the HS-GNSS receiver prototype introduced in this paper adopts the GPDIT strategy and acquires the pilot signals. The proposed receiver employs the Parallel Code Phase Search (PCPS) algorithm to achieve CI by performing circular cross-correlation in the frequency domain between the received signal and a locally generated replica of the satellite's PRN code [23]. The PhD thesis [24] explores methods to optimize the implementation of the PCPS algorithm for HS-GNSS receivers, aiming for reduced complexity without incurring implementation losses. The detection of weak signals demands extended CI times. Consequently, the computation of the circular cross-correlations accounts for the presence of both primary and secondary codes in the pilot signals and requires the use of large FFTs and inverse FFTs (IFFTs). This thesis investigates the algorithm's implementation in FPGAs, where FPGA vendors provide FFT and IFFT hardware accelerators as Intellectual Property (IP) cores. These accelerators typically have limitations on transform lengths, requiring them to be powers of two. As a result, the optimization of the PCPS algorithm is driven by the need to efficiently compute large FFTs using small power-of-two length FFTs and the need to minimize resource usage and algorithm latency. Ref. [24] shows ways to compute an \(N\)-point FFT using a combination of two FFTs, each of \(\frac{N}{2}\) points. One way to do it is by separating the input samples by parity and the output samples by section. This method can be generalized to compute an \(N\)-point FFT using \(P\) FFTs, each of \(\frac{N}{P}\) points. The same method is applicable to the computation of IFFTs. The receiver presented in this paper adopts this approach. This method enables the efficient implementation of the CI in the FPGA using a multi-channel FFT, with an optimized pipeline scheme that minimizes latency, albeit with a smallincrease in mathematical operations compared to the computation of a single large FFT. This algorithm does not require complex branch decisions, as it relies on a streamlined and efficient process, resulting in faster execution. Ref.