# A Fully Integrated Low-Power Multi-Mode RF Receiver for BDS-3/GPS
## 4 Receiver Design
### AGC and DCOC  
Although the out-of-band interference is attenuated, the spectrum after CBPF is still determined by the in-band thermal noise. Therefore, the main purpose of AGC is to minimize the error between the IF output power and ADC full-scale power [20]. DCOC is necessary to avoid reception failure due to signal saturation [7]. The receiver only supports a single frequency of 1575.42 MHz for BD3 and GPS, and only the in-phase path output of CBPF is amplified and processed, so the area and power are reduced a lot. The simplified AGC and DCOC circuit diagram is shown in Figure 6, where PGA is the key to a sufficiently wide gain range [5]. SIGN and MAG are, respectively, the symbol and amplitude of the four-bit ADC output. The PGA circuit composed of a two-stage differential amplifier with a common-mode feedback circuit is shown in Figure 7, whose gain can be changed by \(R_{10}\), \(R_{11}\), and \(R_{14}\). PGA1 differs from PGA2 in that the resistors in the red box in Figure 7 are only owned by PGA2. GC[50] is the gain control code, encoded as G[26:0]. The most significant bit (MSB) G[26] controls \(R_{10}\), \(R_{11}\), and \(R_{14}\) in PGA1 for coarse tuning, G[25] controls \(R_{11}\) and \(R_{14}\) in PGA2 for coarse tuning, and G[24:0] controls \(R_{10}\) in PGA2 for fine-tuning. C[11:0] is the offset control code. The 6 MSBs C[11:6] are connected to the output of PGA1 through DAC2 for coarse tuning and the 6 least significant bits (LSBs) C[5:0] are connected to the internal nodes of the PGA1 (i.e., \(DAC_{p}\) and \(DAC_{p}\) in Figure 7) through DAC1 for fine-tuning. By adjusting these four terminals, the DC offset voltages of \(V_{outp}\) and \(V_{outn}\) can be changed to achieve DCOC. The two control codes are generated by detecting MAG and SIGN signals, respectively. In Figure 7, \(R_{18}\)\(\sim\)\(R_{22}\) have the same value, and so do \(R_{3}\)\(\sim\)\(R_{5}\). \(M_{3}\)\(\sim\)\(M_{5}\) have the same W/L and so do \(M_{10}\)\(\sim\)\(M_{12}\). On this basis, the bias current of \(M_{8}\) and \(M_{9}\) is determined by the bias current of \(M_{5}\). \(M_{10}\) is connected to \(M_{1}\), forming a negative feedback loop to stabilize the first stage output. Compared with the traditional folded cascode amplifier, this structure saves two bias circuits (the bias currents of the input transistors and the bias currents of \(M_{1}\) and \(M_{2}\)), thus conserving space and power. Figure 5: Comparison of the frequency response before and after the RC calibration for the bandwidth of (**a**) 2 MHz and (**b**) 4 MHz. Since the signal received by the navigation system is a fixed thermal noise power, the gain can be fixed once AGC is completed. Therefore, there is no need for a table to store gains, saving chip memory. In cycle 512 CLK, ADC outputs MAG at the falling edge of the clock, while the AGC algorithm samples it at the rising edge and counts the results to obtain the actual threshold value \(M_{AGC}\). Two power thresholds are configured by the serial peripheral interface (SPI), which are, respectively, the high threshold \(\mathit{powth\_high}\) and the low threshold \(\mathit{powth\_low}\) in the power range. When navigation signals are received, if \(M_{AGC}\) exceeds the power range, AGC will be enabled. \(M_{ACC}\) is then compared with the average value of the two powers \(\mathit{powth\_mid}\) (\((\mathit{powth\_high}+\mathit{powth\_low})/2\)). If \(M_{AGC}\) is larger than \(\mathit{powth\_mid}\), the PAG gain decreases and then \(M_{AGC}\) is recalculated and recompared with \(\mathit{powth\_mid}\). Until \(M_{AGC}\) is smaller than \(\mathit{powth\_mid}\), the gain is stable, and vice versa. After that, as long as \(M_{AGC}\) is within the power range [\(\mathit{powth\_low}\), \(\mathit{powth\_high}\)], the gain will remain unchanged. This is mainly to reduce the influence of the detection accuracy and signal randomness on the \(M_{AGC}\) calculation.