## 4 Algorithm Flow
### Basic Flow
It indicates that the static power consumption cost of using LVT cells is too large. Therefore, when fixing timing violations, the design should prioritize converting the cell from HVT to SVT before considering converting the cell from SVT to LVT. The TPSPOM method implements a design philosophy that prioritizes HVT, followed by SVT, and finally LVT, which is more consistent with the current circuit design goals. Therefore, even if the percentage of SVT cells of TPSPOM is significantly larger than that of CAPCOM, it can achieve a lower static power consumption value because of the lower percentage of LVT cells. ### Method Runtime

The experiments are run on a computer with 41.60 GFLOPS. With the lower LVT percentage of CAPCOM compared to CBLPRP, there will be fewer operations for CAPCOM to replace cells that do not meet the timing from HVT back to LVT, which makes CAPCOM run faster than CBLPRP. In the triple-threshold case, under the timing constraints of 1 ns, the CAPCOM runs for 139.6 h and the TPSPOM for 4.4 h. It shows that another advantage of the TPSPOM is that the time is acceptable when applied to a VLSI design. In addition, with the initial path collection, the running time of Algorithm 1 is 15.6 h, while Algorithm 3 is 6 min. ## 6 Conclusions

This paper describes a triple-threshold path-based static power-optimization methodology (TPSPOM) using the MTCMOS technique. This method addresses the shortcomings of existing threshold voltage assignment algorithms that do not specifically consider the connection between cells and paths and frequently update the timing in STA tools. It improves both static power consumption results and algorithm running time:

1. The algorithm proposed in this paper locates the cells to be replaced based on path weights and cell weights to optimize static power consumption. The path weight is obtained from the path constraint, and the cell weight is obtained from the path weight through the cell and its delay-to-power consumption ratio. 2. The proposed algorithm uses a simplified collection of paths for running-time optimization to characterize the overall timing and avoids frequent timing updates in STA tools. The experiments on a CPU IP containing 385,781 cells on a 28 nm process show that the TPSPOM method reduces static power consumption by 15.16% more than CAPCOM with a cycle time of 1 ns while reducing the running time by 96.85%. It proves that the algorithm flow provided in this paper can be effectively applied in the designs of VLSI and supports the distribution of triple-threshold voltage with a significant effect of optimizing static power consumption and low running time. For future work, since the running speed of the algorithm is directly related to the scale of the circuit, we will further improve the running speed of the algorithm to be suitable for larger-scale circuits. **Author Contributions:** Conceptualization and supervision, D.Z. and K.H. ; methodology, P.L. and S.Z. ; validation, P.L., S.Z., W.X. and C.X. ; data curation, W.X. and C.X. ; writing--original draft preparation, S.Z. ; writing--review and editing, S.Z. ; funding acquisition, D.Z. and K.H. All authors have read and agreed to the published version of the manuscript. **Funding:** This work is supported by the National Key R&D Program of China (2020 YFB0906000, 2020 YFB0906001). **Institutional Review Board Statement:** Not applicable. **Informed Consent Statement:** Not applicable. **Data Availability Statement:** Not applicable. **Conflicts of Interest:** The authors declare no conflict of interest. ## References

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