# NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method
## 3 Methodology
### ILP Formulation for NBTI Mitigation and Leakage Reduction Only
#### 3.1.1 ILP Formulation for NBTI Mitigation  
For each path, the NBTI-induced delay degradation is calculated by summing all the delay increases of the gate along that path. Therefore, the ILP formulation for NBTI mitigation is to minimize the total delay increase by considering all the postaging delay in the critical and vulnerable critical path; that is, minimizing the maximum postaging delay in all paths so that the circuit's performance will be maintained to the greatest extent. Suppose \(\mathbf{X}=\{x_{i},\ i=1\ \ldots\ N|\}\) is a vector of variables which represents the state (0/1) of each node in standby mode, where \(N\) is the number of nodes. Then, the duty cycle, the \(V_{th}\) increase, and the delay degradation corresponding to node \(i\) and its connected gate can be expressed by a linear function of \(x_{i}\) and an ILP formulation which is compatible with Equation (10) can be generated using a pseudo-Boolean function. For instance, to an NAND gate, its input vector combination and corresponding delay increase is shown in Figure 2.  
In Figure 2, \(a\) and \(b\) are the input nodes of an NAND gate, \(D_{ab}\) is the delay increase when the input signal value is \(ab\), and \(D_{ab}\) is extracted by HSPICE simulation. Then, the NBTI-induced delay increase for the NAND gate can be expressed as:  
Figure 2: The input vector combination and corresponding delay increase for an NAND gate. \[ \begin{array}{lcl}\text{Objective function}&=&\Delta D\\ &=&\overline{ab}D_{00}+\overline{ab}D_{01}+a\overline{b}D_{10}+abD_{11}\\ &=&(1-a)(1-b)D_{00}+(1-a)bD_{01}\\ &\quad+a(1-b)D_{10}+abD_{11}\end{array} . \tag{11}\]  
By applying the Boole-Shannon expansion, we can modify Equation (11) into:  
\[ \begin{array}{lcl}\Delta D=&D_{00}+(D_{10}-D_{00})a+(D_{01}-D_{00})b\\ &+&(D_{00}+D_{11}-D_{01}-D_{10})ab\end{array} . \tag{12}\]  
In order to express the object function in an ILP-compatible format, it has to be linearized. Since in a NAND gate, \(c=1-(ab)\), the above equation can be rewritten as:  
\[ \begin{array}{lcl}\Delta D=&(2D_{00}+D_{11}-D_{01}-D_{10})+(D_{10}-D_{00})a \\ &+&(D_{01}-D_{00})b-(D_{00}+D_{11}-D_{01}-D_{10})c\end{array} . \tag{13}\]  
With the same approach, the objective function for an INV and an NOR gate can also be obtained, which is shown in Table 1.  
Next, the logic circuit functionality should be transformed into a set of linear constraints, so that a reasonable ILP minimization result can be obtained. Table 2 illustrates the set of constraints for basic gates. It should be noted that, in this paper, three kind of logic gates (INV, NAND, and NOR gates) are exploited to synthesize the target circuit. Additionally, when some other kinds of gates (AND, OR, etc. gate) are required in the synthesis process, the Virtual Gate (VG) insertion technique can be used in the ILP formulation, which adds the virtual cells into the circuit to acquire ILP-compatible models [32]. Because of the possible critical path reordering effect induced by NBTI, both the critical and vulnerable critical paths are chosen in the Potential Critical Path (**PCP**) set in analyzing the postaging circuit delay. Supposing that there are \(L\) paths in a circuit, the original timing information of each path can be obtained using the static timing analysis (STA) tool. A sorting procedure is carried out for these \(L\) paths according to their original delay. If \(T_{i}\) is the largest delay for all the paths, then the **PCP** set is defined as follows:  
\[\textbf{PCP}=\ \{p_{i}|D(p_{i})\geq 0.9\times T_{i},i=1,2,\ \ldots,M\} \tag{14}\] \begin{table}
\begin{tabular}{c c c} \hline \hline
**Gate** & **Logic Function** & **Objective Function** \\ \hline INV & \(b=1-a\) & \(\Delta D=D_{0}b+D_{1}a\) \\ NAND & \(c=1-(ab)\) & \(\Delta D=(2D_{00}+D_{11}-D_{01}-D_{10})+(D_{10}-D_{01})a+(D_{01}-D_{00})b-(D_{00 }+D_{11}-D_{01}-D_{10})c\) \\ NOR & \(c=1-(\overline{ab})\) & \(\Delta D=(D_{01}+D_{10}-D_{11})+(D_{11}-D_{01})a+(D_{11}-D_{10})b-(D_{01}+D_{1 0}-D_{00}-D_{11})c\) \\ \hline \hline \end{tabular}
\end{table}