## 3 Results
### Hardware Simulation of Digital Filters  
Hardware simulation was performed on FPGA Artix xc7a200 tfg1156-3 in Xilinx Vivado 18.3 using the very-high-speed integrated circuit (VHSIC) hardware description language (VHDL).  
The goal of the simulation was to compare the technical characteristics of FIR DFs containing TMAC units with FIR DFs using traditional MAC units [28].  
Results of the hardware simulation of FIR DFs are shown in Figures 7 and 8, which demonstrate that using TMAC units in the implementation of FIR DFs allowed for an increase in the devices' maximum clock frequency by 4.41-10.89%, but at the same time, the hardware costs increased: the number of used look up tables (LUTs) by 0.63-18.63% and power consumption by 1.80-27.17%. The difference between theoretical and practical results is explained by the FPGA features and the weaknesses of the \"unit-gate\" model, which include ignoring the effects of the load outputs capacity of individual logic units and the circuit, generally.  
Our approach allows for improvements in systems where performance is critical. The approach proposed in this paper may be applied in real-time systems or other systems where performance is the main characteristic, for example in medical image processing systems. Increasing the max clock frequency of a medical tomogram processing system would allow for an increase in its performance (i.e., the number of processed frames per second).  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Bit Width, \(k\)**} & \multicolumn{3}{c}{\(U_{delay}\)} & \multicolumn{3}{c}{\(U_{area}\)} \\ \cline{2-7}  & **[22]** & **Proposed** & **Difference,\%** & **[22]** & **Proposed** & **Difference,\%** \\ \hline
8 & 502 & 352 & 29.86 & 8848 & 8289 & 6.32 \\
16 & 643 & 463 & 27.99 & 34,832 & 33,009 & 5.23 \\
32 & 784 & 574 & 26.79 & 136,720 & 131,649 & 3.71 \\
64 & 925 & 685 & 25.95 & 538,640 & 525,633 & 2.41 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Comparison of 15 th-order FIR DFs with different bit width based on known architecture [28] and based on the proposed architecture.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Filter Order, \(K\)**} & \multicolumn{3}{c}{\(U_{delay}\)} & \multicolumn{3}{c}{\(U_{area}\)} \\ \cline{2-7}  & **[22]** & **Proposed** & **Difference,\%** & **[22]** & **Proposed** & **Difference,\%** \\ \hline
3 & 161 & 125 & 22.39 & 8708 & 8433 & 3.16 \\
7 & 322 & 238 & 26.12 & 17,416 & 16,625 & 4.54 \\
15 & 643 & 463 & 27.99 & 34,832 & 33,009 & 5.23 \\
31 & 1286 & 914 & 28.92 & 69,664 & 65,777 & 5.58 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Comparison of FIR DFs with different orders based on known architecture [28] and based on the proposed architecture.  
Figure 8: Hardware simulation results of FIR DFs with different orders based on known architecture [28] and based on the proposed architecture: (**a**) frequency; (**b**) number of LUTs; (**c**) power consumption.  
Figure 7: Hardware simulation results of 15 th-order FIR DFs with different bit width based on known architecture [28] and based on the proposed architecture: (**a**) frequency; (**b**) number of look up tables (LUTs); (**c**) power consumption.