## 5 Experimental Results  
A prototype was built, based on parameters listed in Table 3, as shown in Figure 13. The capacitive coupling interface was made of copper boards and the metal faces are covered by the polypropylene tape (relative permittivity is about 2.5) as a dielectric material. The dimensions of the pickup plates were chosen to suit the back side of an Apple 10-inch iPad, 10 cm \(\times\) 14 cm each. Four Schottky diodes were used to compose the rectifier for its high-frequency abilities, and Litz-wire was used for inductors to reduce skin effect. Duty cycles 20%, 30% and 100% (system without buck converter) of DC-DC buck converter were examined. The input voltage value was determined according to the duty cycle used in the DC-DC buck converter for delivering 10 W of power to the load. The frequency was swiped from 0.35 MHz to 2.5 MHz to show the frequency responses of the output power and the voltage stress across the interface.  
For kilowatt (kW) level high power applications, silicon-carbide (SiC) field effect transistors (FETs) can be used instead of conventional power metal oxide semiconductor field effect transistor (MOSFETs) used in this experiment; while at low power high frequency operations at several tens of MHz, gallium-nitride (GaN) FETs provides a good option [29].  
Figure 12: Simulated electric field at measurement points C, D, and E above the center of Tx1 and Rx1.  
Figure 14 shows the frequency response of the DC output power at different duty cycles. \(Q\) reduction is confirmed by reducing the duty cycle of the buck converter as predicted from the analysis. The main reason for the shift in the response is the change in the value of the total impedance of the load and the parasitic capacitance of the diodes that constructs the rectifier by changing the duty cycle. As proved in the analysis section, by reducing \(Q\), the system's tolerance to misalignment improves, as shown in Figure 15. Figure 16 shows the amplitude of voltage stress measured across the single pair of the capacitive interface (\(C_{c1}\)). A differential probe was used to eliminate the common ground effect. The voltage stress is proportionally decreasing with the duty cycle which follows Equation (14) from the mathematical analysis. The maximum voltage stress across the capacitive interface (\(C_{c1}\)) is reduced to about 65 V at \(D\) = 30% and 44 V at \(D\) = 20%, corresponding to an output power of 10 W, while 211 V is measured for the no buck converter used case. The values of the experimental results of \(V_{c}\) is higher than the calculated ones due to the non-ideal components in the system and the switching losses which decrease the efficiency, so a higher input voltage is needed to deliver 10 W resulting in higher voltage stress across the interface. By using 64 V DC input voltage (\(V_{D}\)), the system could deliver 10 W of power at the duty cycle of 30% and operating frequency 1 MHz, while the end-to-end system efficiency reached 80%. Figure 17 shows the measured \(V_{in}\), \(V_{c}\), and \(V_{out}\).  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameter** & **Unit** & **Value** \\ \hline \(P_{load}\) & Watt & 10 \\ _freq._ & MHz & 1 \\ \(C_{c1}\) & nF & \(\sim\)2.1 \\ \(C_{c2}\) & nF & \(\sim\)1.9 \\ Duty Cycle & \% & 20, 30, 100 \\ \(L\) & \(\mu\)H & 25 \\ \(R_{load}\) & \(\Omega\) & 10 \\ \hline \hline \end{tabular}
\end{table}
Table 3: Circuit parameters and system specifications.  
Figure 13: The system prototype. PWM: pulse-width modulation.  
Figure 14: Frequency response of the DC output power.  
Figure 15: The tolerance of the output power with the change in the capacitive interface equivalent series value.