# Research on Clock Synchronization of Data Acquisition Based on NoC
## 4 The Implementation of Clock Synchronization
### The Implementation of Ddmtd  
(1) Phase discrimination of master and slave clocks  
After coarse synchronization of the master and slave clocks, the phase difference of the master and slave clocks is kept within one clock cycle. Some slave clocks are ahead of the master clock, while others lag behind the master clock. Therefore, it is necessary to determine the phases of the master and slave clocks after rough synchronization, so as to implement fine synchronization of the master and slave clocks. In this paper, DDMTD technology is used to determine the phase difference of the master and slave clocks. After obtaining the phase difference, the Xilinx 7 series FPGA [30; 31] is used for functional verification, and the clock PLL of the FPGA is used to shift the synchronized slave clock phase, so as to achieve high-precision synchronization of the sampling clock of the TI-ADC [32; 33]. In this paper, the asynchronous router's clock at 250 MHz is used for the sampling clock. The external PLL is a high-precision clock (248.88 MHz) close to the router's clock frequency, and the difference between its clock cycle and the router's clock cycle is the resolution of clock synchronization. The resolution of clock synchronization cannot be enhanced infinitely, since a higher resolution needs a larger amplification factor A for the phase difference, which may cause the metastable state of the D flip-flop [34]. According to the clock IP core MMCM of the Xilinx 7 series FPGA, the highest dynamic phase-shift precision is 1/56 of the internal VCO period. For example, when the clock crystal oscillator is 50 MHz, the internal VCO frequency is 1000 MHz and the highest phase-shift resolution is 18 ps. According to Equation (9), the frequency of the external PLL can be calculated as 248.88 MHz, and then, the external DAC and VCO are adopted to generate this frequency. In addition, when the resolution is known, the corresponding amplification factor A is 221.22 according to Equation (10), which can avoid the metastable state of the D flip-flop. \[\Delta T = T_{pll}-T_{clk} \tag{9}\] \[A = \frac{T_{clk}}{\Delta T}-1 \tag{10}\]A counter is used to count the falling edge of the output signals from the two D flip-flops, and the phase relationship between the master and slave clocks has three possible scenarios, shown in Figure 11.  
They are also the cases of the signals from the two D flip-flops. If the D flip-flop with the master clock as its input turns to the high level first, it means that the phase of the master clock is in front while the phase of the slave clock is behind, so the phase_flag_ms signal will be pulled high, and its count value is the amplified phase difference value between the master and slave clocks. On the contrary, if the D flip-flop with the slave clock as input turns to the high level first, it indicates that the phase of the slave clock is in front and the phase of the master clock is behind, so the phase_flag_sm signal will be pulled high, and its count value is the amplified phase difference. If the two D flip-flops turn high at the same time, that means the master and slave clocks have the same phase, and the phase difference is 0. After obtaining the amplified phase difference between the master and slave clocks, according to the total sampling rate of 1.5 GSPS in the data acquisition system, the sampling interval of TI-ADC is 0.667 ns, and the phases of the six sampling clocks (with respect to the original phase of the reference master clock) are 0.000 ns, 0.667 ns, 1.332 ns, 1.998 ns, 2.664 ns, and 3.333 ns, respectively. In this paper, samples are taken in the sequence of routing nodes 1, 3, 4, 6, 7, and 9. According to Equations (1)-(11), the amplified phase difference between each slave clock and the master clock can be calculated, while i denotes the sampling sequence (\(i=1,\,2,\,\ldots,\,6\)).