# Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
## 3 Bit-Cell External Driver Design
### Write Driver Structure and Performance  
To facilitate the application of input values to the bit-cell during write operations, we designed a dedicated write driver circuit that precisely controls the voltages at the storage nodes Q and QB. This is accomplished by adjusting the voltages of the signal lines bit line (BL) and bit line bar (BLB), as illustrated in Figure 8. The circuit incorporates key components, including an inverter and a transmission gate, which work in tandem to ensure that the input value is correctly transferred to the bit-cell. The input signal write serves as the control signal that dictates whether a write operation is active. When the input signal write is set to logic '1', a write operation is initiated, and the BL and BLB lines are driven to complementary voltage levels based on the value of the input data. Specifically, if the input value is logic '1', BL is set to a high voltage (VDD) and BLB is set to a low voltage (VSS), and conversely, if the input value is logic '0', BL is set to a low voltage (VSS) and BLB is set to a high voltage (VDD). These complementary voltage levels allow the correct data to be written into the storage nodes Q and QB, effectively replacing any previously stored values with the new input data. In contrast, when the input signal write is set to logic '0', indicating that no write operation is currently taking place, the BL and BLB lines are pre-charged to a predefined voltage level. This pre-charging step ensures that both signal lines are brought to an equal voltage, typically VDD, in preparation for future operations. The pre-charging process is crucial for maintaining the integrity of the bit-cell and preventing spurious data from being written during inactive periods. By bringing the bit lines to a neutral state when no write operation is required, the write driver minimizes power consumption and enhances the overall stability of the memory system.  
Figure 9 presents the simulation results of the write operation, assuming an initial condition where the input value is logic '0' and a logic '1' is stored in the storage node Q. The figure demonstrates how the voltages of BL and BLB are dynamically adjusted according to the value of the write signal. When the write signal transitions from logic '0' to logic '1', the voltages on BL and BLB change in accordance with the input value, thereby updating the storage node Q. The simulation results clearly illustrate the effectiveness of the write driver in correctly setting the bit lines to complementary voltages and successfully overwriting the data stored in the bit-cell. This ensures that the new input value is properly  
Figure 7: Word line driver simulation result.  
applied to the memory cell, maintaining data accuracy and consistency. Furthermore, the careful design of the write driver minimizes noise and signal contention during the write process. By using the transmission gate in conjunction with the inverter, we ensure that the voltage levels applied to BL and BLB are robust and stable, reducing the likelihood of data corruption or erroneous writes. This is particularly important in high-speed memory operations, where even small disturbances in signal levels can lead to operational failures. The results shown in Figure 9 confirm that the write driver performs as expected, providing reliable control over the storage nodes and ensuring that the input value is successfully written into the bit-cell. In Figure 7, read, write, and hold operations are closely related to the pre-charge process shown in Figure 9. During these operations, the pre-charge phase stabilizes the bit lines, ensuring consistent voltage levels before accessing or updating the bit-cell values. This alignment between Figures 7 and 9 highlights the coordinated control mechanism that optimizes power and stability across different operational states.