## 3 Experiment Results and Discussion
### Results and Discussion  
The proposed DDL-TDC output 7-bit \(\sim\) 5-btidigital code over a conversion range of 6 ns, such that the least significant bit (LSB) of the DDL-TDC was 46.875 ps (= 6 ns/128) \(\sim\) 187.5 ps (= 6 ns/32). Figures 7-9 compare DNL and INL values from a traditional TDL-TDC (without any calibration) and from the proposed DDL-TDC (with real-time calibration) for the LSBs of 46.875 ps, 93.75 ps,  
\begin{table}
\begin{tabular}{l c c c c c} \hline \hline \multirow{2}{*}{**Resources**} & \multirow{2}{*}{**Available**} & \multicolumn{2}{c}{**TDL-TDC**} & \multicolumn{2}{c}{**DDL-TDC**} \\  & & \multicolumn{2}{c}{**(No _Calibration_)**} & \multicolumn{2}{c}{**(Real-Time _Calibration_)**} \\  & & **Used** & **Utilization** & **Used** & **Utilization** \\ \hline Slice Registers & 69,120 & 1023 & 1\% & 2147 & 3\% \\ Slice LUTs & 69,120 & 1567 & 2\% & 4107 & 5\% \\ Occupied Slices & 17,280 & 473 & 2\% & 1342 & 7\% \\ PLL\_ADVis & 6 & 0 & 0\% & 2 & 33\% \\ Block RAM/FIFO & 148 & 0 & 0\% & 2 & 1\% \\ \hline Total Power & & 1.507 W (100\%) & & 1.606 W (107\%) \\ \hline \hline \end{tabular}
\end{table}
Table 2: FPGA resource utilization and power consumption of the DDL-TDC.  
Figure 6: Experimental setup of the proposed DDL-TDC measured system.  
and 187.5 ps, respectively. The ranges of DNL and INL values were \([-0.64,0.92]\) and \([-7.12,4.18]\) for 46.875 ps, \([-0.50,0.44]\) and \([-3.35,2.06]\) for 93.75 ps, and \([-0.47,0.35]\) and \([-1.34,1.03]\) for 187.5 ps. Table 3 shows the linearity improvement of the DDL-TDC compared with the TDC-TDC, which is presented as percentages without any calibration. The DDL-TDC clearly outperformed TDL-TDC in terms of INL and DNL. These results clearly demonstrate the efficacy of DDL-TDC in terms of time linearity.  
To verify the time resolution of the proposed DDL-TDC, a constant time interval was fed as _Trigger 2_, which was constantly delayed by the _Trigger 1_ signal. Figure 10 presents the histogram of the measured data after performing \(10\times 2^{17}\) measurements of the constant delay time. The measured mean time was 252.8 ps, and the RMS value was 32.41 ps. Thus, the single-shot precision of DDL-TDC was 22.9 ps = \(32.41/\sqrt{2}\) ps. For various temperatures, Figure 11 also illustrates the RMS values for real-time calibration TDC (DDL-TDC) and for the TDL-TDC with a constant mapping calibration table in software. The proposed DDL-TDC exhibited considerable robustness against fluctuations in temperature, as indicated by the RMS values in Figure 11. Consequently, the proposed DDL-TDC not only improved DNL and INL performance but also achieved high-resolution measurements in an FPGA-based TDC design.  
\begin{table}
\begin{tabular}{l c c} \hline \hline
**LSB** & **DNL Improvements** & **INL Improvements** \\ \hline
46.875 ps & 31\% & 30\% \\
93.75 ps & 46\% & 30\% \\
187.5 ps & 26\% & 41\% \\ \hline \hline \end{tabular}
\end{table}
Table 3: Linearity improvements for the proposed DDL-TDC and TDL-TDC.  
Figure 7: INL/DNL values obtained using the proposed DDL-TDC with 7-bit digital output.  
Figure 8: INL/DNL values obtained using the proposed DDL-TDC with 6-bit digital output.  
Figure 10: Measurements of constant delay for the proposed DDL-TDC.  
Figure 9: INL/DNL values obtained using the proposed DDL-TDC with 5-bit digital output.  
In addition, the proposed DDL-TDC achieved high-resolution and high-linearity measurements. Thus, the time conversion range was only 6 ns, but a 32-ps resolution time was achieved for high-resolution measurements. The DDL-TDC could be augmented with an additional coarse counter to increase the conversion range for some applications that might require larger conversion range measurements. However, the fine time measurements would still use the DDL-TDC to maintain the high-resolution measurements.