## 1 Introduction  
The continuous progress of semiconductor technologies has made possible the fabrication of increasingly faster power transistors to be used in switched power applications, e.g., motor inverters and DC-DC converters. Indeed, power designers can benefit from lower on-resistance, higher switching frequency, and smaller heat-sinks, all resulting in converter designs with higher power density. Although the pros of using more performing power switches are valuable, they are counteracted by the higher level of electromagnetic interference (EMI) they deliver, which can be attenuated quite hardly. Such an aspect can not be neglected by practitioners, since, in order for any electronic equipment to be placed on the market, it must comply with electromagnetic compatibility (EMC) standards in accordance with national or international legislation. Amongst the required EMC tests, the measurement of conducted emission aims to assess the noise current, which is delivered by the equipment under test (EUT) and it is conducted back onto the power supply system, to be within given limits. A general description of the test setup used for measuring the conducted emissions is shown in Figure 1, where in between each power line and the EUT power supply terminal, a line impedance stabilization network (LISN) is inserted to have the impedance shown by the power supply network univocally defined over the frequency range of interest. As far as switched power circuits are concerned, the half-bridge is identified as a root element from the EMC viewpoint, since the switched operation of the active devices it is made of, i.e., transistors and diodes, is the primary cause of the conducted disturbance current [1, 2]. The EUT shown in Figure 1 is modeled as a single leg and an input capacitance, which provides the switching current \(t_{\text{sw}}\) during the commutations of the \(S_{\text{HS}}\) and \(S_{\text{LS}}\)power switches. The power supply network shown in Figure 1 is a three-conductor system, thus the current flowing in the positive and in the negative lines can be expressed in terms of a differential-mode (DM) component (\(i_{\text{DM}}\)) and a common-mode (CM) component (\(i_{\text{CM}}\)). The former is due to the parasitics of the input capacitor \(C_{\text{in}}\) that cause high-frequency components \(i_{\text{sw}}\) not to flow in \(C_{\text{in}}\) entirely, resulting in a DM current provided by the power line. The latter (\(i_{\text{CM}}\)) is the current that flows in the ground conductor and it is related to the \(dV/dt\) affecting the sw node, which causes a current to flow in the parasitic capacitance \(C_{\text{p}}\). As far as the half-bridge shown in Figure 1 is concerned, it is possible to identify the primary sources of EM noise as the switching current (\(i_{\text{sw}}\)) for the DM EMI, and the switching voltage (\(v_{\text{sw}}\)) for the CM EMI. The magnitude of the CM current usually increases with frequency as the impedance shown by the parasitic capacitance \(C_{\text{p}}\) decreases, and usually, it dominates over the DM emission in the mid-frequency range [3], i.e., from 1 MHz to 30 MHz, where the regulatory limits are stricter. As a result, the mitigation of conducted EMI (CE) is definitely a key issue, as higher \(dV/dt\), caused by faster power switch, results in higher emission levels. Since the switching voltage (\(v_{\text{sw}}\)) is the major source of conducted EMI, its frequency spectrum allows one to predict the CE, provided that the propagation path is known. As far as hard-switched power circuits are concerned, such a voltage can be approximated by a trapezoidal waveform, whose pulse-width (\(\tau\)) corresponds to the on-time of \(S_{\text{HS}}\) and its high value equals to the DC voltage across \(C_{\text{in}}\). Even though more accurate models can be considered, as in [4], where multiple slopes are accounted for during commutations, the trapezoidal approximation results in an upper boundary of the frequency spectrum magnitude [5].