## 2 Materials and Methods
### Global Digital Controller
#### 2.2.4 Pulse Protocols for 256-Pixel Stimulator  
The digital controller receives the signals for data and clock after processing them via a wireless data telemetry system and recovering them via a demodulator. The global digital controller uses the data and clock obtained from the transmitter to construct precise pulse patterns that will produce a biphasic pulse. In order to evaluate the entire wireless telemetry system, three platforms for the global digital controller were deployed. For the simulations, Xilinx Vivado (Version 2020.1) was employed. The outcomes were validated by hypothetical  
Figure 3: A packet format protocol is used in this system for wireless data transmission. simulations on ModelSim (Version 21.1). The system was initially implemented on the FPGA to validate the global digital controller output. Data were sent and collected using FPGAs, and the findings were shown on an oscilloscope. A wireless telemetry system sent the data it had received from the transmitter to the FPGA receiver. The data transmission rate of the receiver was 10 kbps, while the transmission rate of the clock was 2 MHz. The received clock was internally separated into 10 kHz clocks for data synchronization. The inside of the receiver comprises a sequential controller, pulse modulator, and output pulse controller, as shown in Figure 4. The sequential controller determines the order of pixel channels that are activated sequentially. The pulse modulator generates a diverse pulse according to the light intensity. Finally, the output pulse controller passes the pulse information and produces suitable pulse profiles. Pulse profiles contain five distinct signals (RST, CHR, CATH, ANO, and BAL). The RST signal serves to reset the photosensor of the single-pixel stimulator depicted in Figure 1. The CHR is generated separately for each of the 16 channel sets based on the input light-dependent data from the transmitter side. The \(\overline{\text{CHR}}\) signal is created at the same time that CHR is determined, and it is the inverted signal of CHR. CHR and \(\overline{\text{CHR}}\) control the time to charge the capacitor, and the duration of charging regulates the current range between 0 and 150 uA. The CHR time is adjusted from 1 to 10 ms depending on the light intensity. As the number of electrode pixels increases, generating flicker-free presents a challenge. Flicker-free vision in terms of a subretinal implant is defined as the time at which each electrode pixel is turned on for the next phase. The refresh rate of each electrode pixel should be within the flicker-free vision range between 20 and 50 Hz [26]. This study proposes a design that contributes to controlling the flicker-free frequency, requiring 12 ms for each phase. Consequently, the sequential turning on of 16 channel sets could take a total time of 192 ms. In other words, the frequency is 5.20 Hz, based on Equation (1). \[\text{T}=1/\text{f};\text{f}=1/\text{T} \tag{1}\]  
\[\text{f}=5.20\text{ Hz} \tag{2}\]  
This rate is significantly lower than the flicker-free vision range. To prevent this, we applied an overlapping technique in which each phase starts 1 ms after the previous phase, with overlapping CHR pulses. Figure 5 shows an example of overlapping current pulses for sequential channel sets. Since each CATH for the next phase starts with the ANO of the previous phase, this overlap effectively reduces the current leakage during the phase shift, and a flicker-free frequency can be achieved using the following equation:  
Time for a single phase = 12 ms  
Time for 16 phases starting 1 ms after the previous phase = 27 ms  
Figure 4: Diagram of complete receiver architecture. Figure 6 presents a detailed representation of the various pulse shapes and amplitudes derived from the data. CHR pulses can be modulated between 1 ms and 10 ms. CATH and ANO, which combine to form cathodic and anodic shapes of biphasic pulses, are generated in 128 different shapes and amplitudes.