# A Novel Reconfigurable Vector-Processed Interleaving Algorithm for a DVB-RCS2 Turbo Encoder
## 2 The Turbo Encoder  
Figure 1 depicts the TE implemented by the DVB-RCS2 standard. It has a coding rate of 1:3, meaning that for every input bit, there are three output bits. The input is a 2-bit stream denoted as A and B. The output codeword is composed of three couplelets: (1) The original A and B couplet remains unchanged. (2) A and B are encoded by the 'Encoder Core', a convolutional calculation block. (3) N couplelets are delayed and rearranged in the 'Permutation' block, then encoded via the 'Encoder Core' block.  
The permutation stage of the TE is determined by five parameters, \(P,Q_{0},Q_{1},Q_{2}\) and \(Q_{3}\), with ranges defined by the DVB-RCS2 standard, and vector size N, the number of couplelets in bits. The specific parameters used in the implementation are in compliance with the DVB-RCS2 standard and are detailed in Table 1[13].  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**N [bits]** & **P** & \(Q_{0}\) & \(Q_{1}\) & \(Q_{2}\) & \(Q_{3}\) \\ \hline
56 & 9 & 2 & 2 & 8 & 0 \\
152 & 17 & 9 & 5 & 14 & 1 \\
236 & 23 & 10 & 2 & 11 & 1 \\
384 & 25 & 1 & 2 & 0 & 1 \\
432 & 29 & 1 & 4 & 1 & 1 \\
492 & 31 & 0 & 3 & 1 & 0 \\
520 & 31 & 0 & 1 & 2 & 0 \\
776 & 39 & 7 & 0 & 0 & 0 \\
1056 & 43 & 0 & 0 & 6 & 2 \\
1192 & 49 & 0 & 3 & 5 & 0 \\
2396 & 81 & 1 & 2 & 5 & 2 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Example of used Turbo Encoder parameter sets.  
Figure 1: Turbo Encoder scheme.  
The original A and B couple are unchanged.
2. A and B are encoded by the 'Encoder Core', a convolutional calculation block.
3. \(N\) couplets are delayed and rearranged in the 'Permutation' block, then encoded via the 'Encoder Core' block.  
The permutation stage of the TE is determined by five parameters, \(P,Q_{0},Q_{1},Q_{2}\) and \(Q_{3}\), with ranges defined by the DVB-RCS2 standard, and vector size \(N\) (the number of couplets in bits). The specific parameters used in the implementation are in compliance with the DVB-RCS2 standard and are detailed in Table 1[13].  
Initial simulations running a simple existing serial implementation of this TE result in the permutation stage taking up to 78% of the application (cycle-wise) and show potential parallelism features such as repetitiveness modulo calculations which could be reconfigured to enhance performance. Figure 2 depicts an example of the permuted indexes by original indexes (for \(N=776\) and matching parameters from Table 1) and shows the constant \(4P\) incrimination leading to the new parallel approach described in Section 4. The turbo encoder permutation stage is carried out in two levels.  
(1)  
Describes a swap of the bit couplets for every odd-indexed component  
\[\text{if}\{j\;(\text{mod}\;2)=1\}\Rightarrow(A_{j},B_{j})\rightarrow(B_{j},A_{ j}), \tag{1}\]  
(2)  
Describes a calculated rearrangement of the indexes based on the chosen parameters. Further elaboration of the latter can be found in Section 4.  
\[i\equiv\Pi(j)=(P\cdot j+Q+3)\;(\text{mod}\;N) \tag{2}\]  
where  
\[Q=\begin{cases}0,&j\;(\text{mod}\;4)=0\\ 4Q_{1},&j\;(\text{mod}\;4)=1\\ 4Q_{0}\cdot P+4Q_{2},&j\;(\text{mod}\;4)=2\\ 4Q_{0}\cdot P+4Q_{3},&j\;(\text{mod}\;4)=3\end{cases} \tag{3}\]  
Figure 2: Permuted indexes for example vector length of 776. \(\Delta=4\cdot P\) is the offset between two consecutive indexes after permutation.