# JFET Integration Using a Foundry SOI Photonics Platform
## 2 JFET Design and Characteristics
The simulated JFET drain current is demonstrated in Figure 2; all current curves are saturated when V\({}_{\rm DS}\) exceeds \(10\) V. As the gate bias V\({}_{\rm GS}\) increases, the channel conductance decreases until it becomes zero at the pinch-off voltage, around \(-7\) V.  
The fabricated JFET drain characteristics are shown in Figure 3. Textbook JFET behavior is observed, with I\({}_{\rm D}\) nearly constant in the saturation region. However, the pinch-off voltage is much larger than the design value, at V\({}_{\rm GS}\) = \(-20\) V. This could be due to the variation of the doping concentration in the fabrication process or inaccurate doping profiles estimated by SUPREM simulations. We plot the transfer characteristics of JFET at V\({}_{\rm D}\) = \(10\) V in Figure 4. The intersection points on the x-axis and y-axis indicate that the pinch-off voltage is \(-20\) V and the saturation drain current I\({}_{\rm DSS}\) is \(0.14\) mA at V\({}_{\rm GS}\) = \(0\) V, respectively. The actual channel doping level is estimated to be \(N_{D}\) = \(1.6\times 10^{17}\) cm\({}^{-3}\), based on the measured \(Vp\) using Equation (1), which is a little higher than our proposed doping level of \(7\times 10^{16}\) cm\({}^{-3}\). This dosage variation can be used to explain the difference of predicted and measured pinch-off voltage. Revised _SPICE_ model parameters (see Table 1) were extracted from Figures 3 and 4 in order to support circuit design and simulation. There is a notable difference in the final measurements and target design performance. We believe that this is due to variations in the doping and photolithography steps during the fabrication process. The cut-off frequency is calculated to be \(1\) GHz according to Equation (2), with the transconductance g\({}_{\rm m}\) being \(1.2\times 10^{-5}\) A/V. The frequency response limitation is dependent on the dimensions and physical constants of the transistors [3]. To obtain a higher frequency response, we can either decrease the channel length \(L\) to reduce the capacitance and increase \(g_{m}\), or enhance the channel doping level. In this work, we do not have an option to vary the implant dosage parameters, since these are pre-defined by the fabrication technology. We also have the design limitation of the layout rules with a fixed minimum feature size. However, with possible reductions in feature size by using a more advanced lithography technology,  
Figure 2: Simulated junction field effect transistor (JFET) drain characteristics. We custom designed the transimpedance amplifiers by using LBJTs and JFETs. Figure 5 shows a block diagram of the integration, using the standard processing parameters supported by A*STAR IME's silicon photonic multi-project wafer service. A waveguide is used to carry and transmit light on the integrated platform. A \(500\) nm \(\times\) 220 nm strip waveguide was used to connect each optical component. The TE 1550-nm surface grating coupler and Ge PIN photodiode were selected in the support library for input/output light coupling and detection. A transimpedance amplifier (TIA) is connected at the back end of the Ge photodetector. As we mentioned previously, the IME silicon photonics general-purpose fabrication process does not support the fabrication of MOS devices due to a lack of polysilicon deposition availability. A MOSFET would also need a high-quality gate oxide. Therefore, we chose to demonstrate the integrated electronic components using an \(n\)-channel JFET. Figure 6 shows a microscopic image of the entire integrated circuit. For the optical device, we selected design models from the PDK layout library that have been verified by other research groups. The transimpedance amplifier on the image was constructed by using LBJTs, which was followed by a differential JFET amplifier. The schematic diagram is shown in Figure 7. A photodiode is illustrated by D1; a common-emitter input (Q1) and an emitter follower (Q2) are used to create a low-impedance output and the feedback source in the first stage.