# Harvesting the Aggregate Computing Power of Commodity Computers for Supercomputing Applications
## 4 Experimental Evaluation and Results
### DeepStack Cluster  
The benchmark experiments on the HPC cluster have passed through the test and debugging level programs to test the availability of the cluster server compute nodes and then data with intermediate complexity including Markov chains, Monte-Carlo simulation, distributed PageRank algorithm, HITS algorithm, Distributed Gradient descent. After successful tests of these stages benchmarking programs are used. Benchmark programs include the problems based on highly optimized libraries for core scientific research with competitive baseline figures in the form of linear algebra, genetics, and simulation studies using LPACK, LINPACK, BLAS, etc. Based on the theoretical basis, the experiment is tested for speedups. Three types of speedups were used in the experiment, and comparable latency and throughput can be achieved using our cluster architecture:  
1. linear speedup(fully parallel case experimented),
2. sublinear speedup(sequential parallel mixed case),
3. superliner speedup(cached case--future work)  
Items (1) and (2) can be explained by [PERSON]'s diminishing returns, whereas (3) is explained by the principle of locality of data (i.e., distributed caching architecture is used). To perform the experiments and compare the results based on the theoretical basis, the sample workload taken for experimentation is seen in Table 4. The latency (\(L\)) of architecture is the time taken per unit of workload and is given by the following formula:  
\[L=\frac{W}{T} \tag{1}\]  
where, \(T\) is the total time taken by the workload on this architecture, and \(W\) denotes the total workload in the number of instructions/jobs. From the relative performance of two systems processing the same problem as speedup, we measured the speedup/performance improvements from speedup latency and speedup throughput perspectives. Hence, the throughput is the execution rate of a task as follows: density \(\rho\), the number of processors. In addition, \(Q\) is inversely proportional to the latency of the architecture:  
\[Q=\frac{\rho\cdot AW}{T}=\frac{\rho\cdot A}{L} \tag{2}\]  
where \(A\)--is the number of processors, \(\rho\)--execution density( the number of stages in an instruction pipeline, \(W\)--denotes the total workload executed, and \(T\) represents the total time taken. Regarding the speedup in latency, by making the architecture parallel, we intend to speed up the system latency. The following formula is used to compute the speed up in latency between architectures 1 and 2:  
\[S_{latency}=\frac{L_{1}}{L_{2}}=\frac{T_{1}W_{2}}{T_{2}W_{1}} \tag{3}\]  
where \(S\) denotes the speedup in latency from architecture 1 to 2. In addition, \(L_{1}\) is the latency on architecture 1, and \(L_{2}\) is the latency on architecture 2. The following formula defines the speedup in throughput:  
\[S_{throughput}=\frac{Q_{2}}{Q_{1}}=\frac{\rho 2A_{2}T_{1}W_{2}}{\rho 1A_{1}T_{2}W_{1}} =\frac{\rho 2A_{2}}{\rho 1A_{1}}S_{latency} \tag{4}\]  
where \(S_{throughput}\) represents the speedup in throughput of Architecture 2 with respect to Architecture 1. Moreover, \(Q_{1}\) denotes the throughput of architecture 1, and \(Q_{2}\) is the throughput of architecture 2. Regarding [PERSON]'s law, if some part of the program cannot be parallelized because of dependencies, then the actual speedup cannot be linearly scaled in proportion to the number of newly added processors. In addition, the speedup is inversely proportional to the amount of sequentially in the program with the following formula:  
\[S_{latency}(S)=\frac{1}{(1-p)+(p/s)} \tag{5}\]  
where \(S_{latency}\) is the theoretical speedup of the execution of the whole task, \(s\) is the speedup of part of the task that benefits from improved system resources, \(p\) is the proportion of execution time that the part benefiting from improved resources originally occupied. The performance of the DeepStack cluster increased as the compute nodes were added.