## 2 Models for Voltage Distributions and Measurement Data
### Threshold Voltage Distributions  
NAND flash technologies are differentiated by the number of bits stored per cell. While SLC flash stores only one bit per cell, TLC flash stores three bits per cell. Hence, a TLC flash requires eight different charge levels (\(L_{0},\ldots,L_{7}\)) and seven reference voltages (\(r_{1},\ldots,r_{7}\)) to read all three bits. The three bits of each cell are typically mapped to three different pages called MSB-, CSB-, and LSB-page, where MSB, CSB, and LSB stand for most significant bit, center significant bit, and least significant bit, respectively. Figure 1 illustrates the conditional distributions \(f(V_{th}|L)\) of the threshold voltages \(V_{th}\) of the flash cells given the charge levels. The figure also provides a possible bit-labeling for the charge levels, where the colors indicate the corresponding page, i.e., MSB in red, CSB in blue, and LSB in green. Most flash memories support page-wise read operations. For instance, to read the MSB-page with the bit-labeling in Figure 1, we need to read at the reference voltages \(r_{3}\) and \(r_{7}\).  
Figure 1: Model of voltage distribution of a TLC flash memory with labeled reference threshold voltages (dashed lines) and bit labeling.  
The distributions \(f(V_{th}|L)\) are not static but change over the lifetime of the flash. Two of the most important factors for these changes are the number of program/erase (P/E) cycles and the data retention time. The P/E cycles lead to a wear-out of the floating gate, while the data retention time leads to a charge loss. The distributions also depend on effects such as the program and read temperature and the charges of adjacent cells. Moreover, they can vary over pages and blocks.  
The threshold distributions can be measured by successively applying all possible threshold voltages and counting the number of cells that are activated for the given voltage and charge level. For those measurements the data retention time is simulated by baking the chip for a specific time [38; 39]. Figure 2 shows measured histograms for three different life-cycle states. The measurements were performed using fresh cells, cells with 1500 P/E-cycles and 13 h of baking, which simulates about two months of data retention, and cells with 3000 P/E-cycles and 80 h of baking, which corresponds to the end of life (EOL) defined by the manufacturer. Note that only the charged states \(L_{1}\) to \(L_{7}\) are shown. The voltages are represented by the index numbers of the possible voltage steps.  
This figure shows the charge loss due to data retention time as well as the widening of the distributions due to wear-out. Due to the logarithmic scale of the y-axis, it is apparent that the distributions are not symmetric and the voltages are not normally distributed. While the threshold voltage distributions are often modeled as Gaussian distributions, the measured distributions show an exponential tail toward the lower voltages. To cope with this exponential tail, the exponentially-modified Gaussian distribution was proposed [23] which is the sum of two independent normal and exponential random variables. In [40], a Normal-Laplace mixture model was proposed. Similarly, the model in [41] copes with program errors in MLC-Flash memory. In our measurements, all three bit-pages are programmed simultaneously; hence, no write errors happen. Moreover, neither the exponentially-modified Gaussian distribution nor the Normal-Laplace mixture model is able to fit our measurements because these models do not allow for an inflection point, as observed in the measurement data.