###### Abstract
However, maximum absolute error (MAE) is a better metric for fixed-point in implementation when considering the hardware efficiency. The error-flattened method is proposed for the first time in [23], minimizing MAE to approximate the logarithmic function by dividing the output range into equal regions. Additionally, the method in [23] optimizes the hardware implementation of logarithmic function and achieves the theoretically best segmentation performance. The trouble of the method in [23] is that it is not universal but only for logarithmic function. In [24], another logarithmic converter with a novel error-aware segmentation procedure is proposed, which approximates logarithmic function by unity slope straight lines and maximizes the length of each segment under the MAE requirement. The PWL methods mentioned above are all for specific functions. A universal PWL method for all transcendental functions is proposed in [25] for the first time, which uses the software to select the minimum number of segments under the constraint of controllable and predefined MAE. However, the method in [25] cannot achieve the best segmentation performance reached in [23], because of segment endpoints overlapping and the inconsistencies between hardware and software. In the meantime, the hardware architecture in [25] still has redundant logic, resulting in unnecessary hardware overheads. A PWL approximation computation (PLAC) method is proposed in [26], which is an optimization of [25], improving the problems mentioned above. Moreover, a bisection method is proposed in PLAC to reduce the segmentation time as well. In [27], PLAC is used to perform the Nth root computations on floating-point numbers and is much better than the methods based on CORDIC. However, the optimal intercept value should change after quantization, but PLAC does not solve this problem. Based on PLAC, the method in [28] solves the remaining problem and inserts the quantification operations into the segmentor (SQ) for the logarithmic computation of floating-point numbers. Getting the errors after slope quantification, SQ method optimizes the value of y-intercept to acquire the minimum MAE. SQ is extended to other nonlinear functions and replaces multipliers with shift-and-add (SAA) parts in [29], which is called multiplierless SQ (ML-SQ). In ML-SQ, the substitution process is simulated by the software, in consideration of the fractional bit widths of the intermediate data and slope. The whole process is called multiplierless PLAC (ML-PLAC). When the slope fraction is small, the ML-PLAC method can significantly reduce the delay and area as for hardware implementation. The comparison of the different PWL methods is shown in Table 1 and it can be concluded that among the piecewise approximate methods of nonlinear functions, the piecewise method of error flattening has better universality and better performance on hardware circuits. In this paper, we make some improvements based on the ML-PLAC method, which we call optimized ML-PLAC (OML-PLAC). Like the ML-PLAC method, OML-PLAC also adopts SQ segmentation method and multiplierless hardware structure. The biggest difference is the definition of kw. In ML-PLAC, kw represents the fractional bit widths of the slope while represents the number of ones in the slope value in this paper. To put it another way, kw represents the maximum number of multiplexers in fractional bits and the maximum number of multiplexers overall in ML-PLAC and OML-PLAC, respectively, while the efficiency of the multiplexers is different. As the fractional bit widths of the slope, since the kw of different segments may be different, it is often the case that some inputs of the multiplexers are 0, which causes the waste of the multiplexer resources. However, as the number of ones in the slope value, the multiplexers are at full load (There are some special cases, which will be mentioned later).