# A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier
## 3 Small Signal Analysis
### Frequency Response and Compensation  
The use of a dual signal path in the second stage allows some flexibility in optimizing the frequency response: in particular, the zero provided by the dual path can be exploited to cancel one pole of the overall transfer function thus improving the phase margin. An approximate analysis of the amplifier can be carried out by exploiting the Miller approximation and referring to the small signal equivalent circuit reported in Figure 4, where \(G_{1}\) and \(G_{o1}\) are defined in (2), \(G_{o}\) is given by (7), \(C_{L}\) is the load capacitance and the other capacitances can be expressed as  
\[C_{1}=C_{gd_{1}}+C_{gd_{3}}+C_{db_{1}}+C_{db_{3}}+C_{gs_{9}}+C_{gd_{9}}\big{(}1 +g_{m_{\eta}}/G_{o}\big{)} \tag{11}\]  
\[C_{2}=C_{gd_{1}}+C_{gd_{3}}+C_{db_{1}}+C_{db_{3}}+C_{gs_{5}}+C_{gd_{5}}\big{(}1 +g_{m_{5}}/g_{m_{\gamma}}\big{)} \tag{12}\]  
\[C_{x}=C_{gd_{y}}\Big{(}1+\frac{g_{m_{\gamma}}}{g_{ms}}\Big{)}+C_{gd_{6}}+C_{gg ^{\gamma}}+C_{gg*}+C_{gd_{8}}\Big{(}1+\frac{g_{m_{S}}}{G_{o}}\Big{)} \tag{13}\]  
Figure 3: Common mode equivalent circuit of the input stage with replica bias (**a**) and corresponding small signal model (**b**). Since \(C_{1}\) results much larger than \(C_{2}\), the transfer function \(V_{o}/V_{id}\) has to be calculated by separately considering the paths from \(V_{ip}\)=\(V_{id}/2\) and \(V_{im}\)= \(-V_{id}/2\) to \(V_{o}\):  
\[A_{d}(s)=\frac{V_{o}}{V_{ip}}|_{V_{im}=0}+\frac{V_{o}}{V_{im}}|_{V_{ip}=0} \tag{14}\]  
The analysis of the circuit in Figure 4 yields a transfer function in the form:  
\[A_{d}(s)=\frac{A_{0}N(s)}{\big{(}1+s\tau_{1}\big{)}\big{(}1+s\tau_{2}\big{)} \big{(}1+s\tau_{3}\big{)}\big{(}1+s\tau_{4}\big{)}} \tag{15}\]  
where  
\[A_{0}=\frac{G_{1}}{2G_{o1}}\bigg{(}g_{m9}+g_{m8}\frac{g_{m5}}{g_{m7}}\bigg{)} \frac{1}{G_{o}} \tag{16}\]  
is the dc gain, the time constants of the poles are  
\[\tau_{1}=C_{L}/G_{0} \tag{17}\]  
\[\tau_{2}=C_{1}/G_{o1} \tag{18}\]  
\[\tau_{3}=C_{2}/G_{o1} \tag{19}\]  
\[C_{2}=C_{gd_{1}}+C_{gd_{3}}+C_{db_{1}}+C_{db_{3}}+C_{gs_{5}}+C_{gd_{5}}\big{(}1 +g_{m_{5}}/g_{m_{\gamma}}\big{)} \tag{12}\]0  
and  
\[C_{2}=C_{gd_{1}}+C_{gd_{3}}+C_{db_{1}}+C_{db_{3}}+C_{gs_{5}}+C_{gd_{5}}\big{(}1 +g_{m_{5}}/g_{m_{\gamma}}\big{)} \tag{12}\]1  
which can be solved by means of well known approximations to obtain the expression of the two zeros as follows:  
\[C_{2}=C_{gd_{1}}+C_{gd_{3}}+C_{db_{1}}+C_{db_{3}}+C_{gs_{5}}+C_{gd_{5}}\big{(}1 +g_{m_{5}}/g_{m_{\gamma}}\big{)} \tag{12}\]2  
\[C_{2}=C_{gd_{1}}+C_{gd_{3}}+C_{db_{1}}+C_{db_{3}}+C_{gs_{5}}+C_{gd_{5}}\big{(}1 +g_{m_{5}}/g_{m_{\gamma}}\big{)} \tag{12}\]3  
For large load capacitances \(C_{L}\), \(1/\tau_{1}\) is the dominant pole, and the circuit can be sized to cancel the second pole with one of the zeros, thus improving the phase margin and providing stability without sacrificing bandwidth. To add a further degree of freedom and achieve an adequate phase margin even for smaller load capacitances, a compensation capacitor \(C_{c}\) can be added between \(V_{o1n}\) and \(V_{o}\) (i.e., between gate and drain of \(M_{9}\) in Figure 1b): Its pole-splitting effect leads to some reduction of the bandwidth that is however negligible if \(C_{c}<<C_{L}\) and moves the pole \(1/\tau_{2}\), placing it nearer to the zero \(1/\tau_{z1}\).