## 2 Current CORNERSTONE Platforms
### CONERSTONE Partner Highlights
#### 2.4.1 CONERSTONE Partner: Tyndall National Institute, Ireland--High Efficiency Optical Packaging
CORNERSTONE Partner: University of Bristol, UK--Microelectromechanical Systems (MEMS) Switches  
The need for efficient, low-loss and scalable phase shifters has long been recognized in Si photonics. Traditional thermal phase shifters common in Si photonics typically dissipate 10 s of mW of electrical power to achieve \(\pi\) phase shifts. A wide variety of applications in areas ranging from integrated quantum photonics, programmable photonic integrated circuits and photonic implementations of artificial neural networks require 10\({}^{3}\)-10\({}^{5}\) phase shifters on a chip, which makes the power dissipation prohibitive for scalability. Especially for quantum integrated photonics, the need for low loss, low dissipation phase shifters is critical, because these devices need to work at cryogenic temperatures, where the available cooling power is limited to begin with. Microelectromechanical systems (MEMS) based phase shifters are a potential solution to this problem. MEMS-based switches and phase shifters have long been the standard in the RF domain on account of their low static dissipation. The same advantage applies to their photonic implementations: for example, while a Si thermo-optic phase shifter may consume 10 mW/\(\pi\) (Figure 4), and the power must be continuously applied to maintain the desired phase shift, a MEMS phase shifter has achieved 3\(\pi\) of phase shift with negligible continuous power consumption [79]. Although optical MEMS has a long and distinguished history, until recently [80] there has been very little effort at systematically implementing MEMS based devices in Si photonics foundries. This is because MEMS devices require a substrate release step, which is not compatible with current Si photonics manufacturing process flows. While it is possible to build proof of principle devices in academic cleanrooms, the only way to achieve the scale necessary to build 1000 s of these devices (and ensure adequate performance at this scale) is to perform postprocessing on an existing foundry process. At the University of Bristol, we have explored for the past couple of years MEMS based devices that are built around the standard CORNERSTONE passive photonics process. The photonic layers in the device are fabricated using the standard MPW design rules. After the chips arrive at Bristol, we removed the top cladding oxide, overlay metallic electrodes for actuation (using e-beam lithography) and undercut the oxide layer to suspend the MEMS devices. While the standard Si photonics process is ideal for achieving scalability, it provides a few challenges from a MEMS device perspective. The first challenge is to accurately overlay metallic electrodes, which are not included in the MPW process. Since the Si device layer used for photonics is undoped, to achieve significant beam actuation at reasonable voltages requires accurate electrode overlays. To illustrate this, it is instructive to look at a MEMS based phase shifter implemented in the CORNERSTONE process (Figure 13a). The doubly clamped suspended hammerhead cantilever is pulled toward the signal electrode by applying a DC bias across the signal and ground pads (as the cantilever is deflected away from the microdisk resonator, it changes the effective index of the circulating whispering gallery mode, leading to a shift in the resonant wavelength). Overlaying the pads with metal ensures the field drops predominantly in the actuator gap between the cantilever beam and the signal electrode (Figure 13b). While it is reasonably straightforward to do these overlays with electron beam lithography, a self-aligned electrode process compatible with Si photonics is the more realistic long-term solution. The second challenge is designing MEMS actuators with relatively large actuation gaps. The minimum feature size in current Si photonics processes is 200 nm, while typical MEMS capacitive gaps, defined by sidewall lithography, can be as small as 50 nm [81].