# Interference Mitigation for GNSS Receivers Using FFT Excision Filtering Implemented on an FPGA
## 4 Hardware Implementation  
The greatest challenge in previous studies was the hardware implementation due to the significant required number of hardware resources. FPGA was used in the implementation due to its parallelism as the hardware and software technologies are used in parallel with general reconfigurable solutions. Additionally, it has the ability to manipulate the system through software changes. FPGAs are well-structured processors that perform fast Fourier transforms (FFTs), which are often used during a GNSS receiver's initial signal search and acquisition operations. FPGAs are generally used for prototyping GNSS receiver designs before the fabrication of a dedicated ASIC. In some cases, such as space GNSS receivers, FPGAs are used for the final product (SGR-AXIO, NAVILEO receivers).  
The FPGA KCU105 kit has the Xilinx Kintex UltraScale family, which provides a hardware environment for developing and evaluating designs targeting the UltraScale XCKU040-2 FFVA1156E device [41]. The Kintex UltraScale family performs ASIC-class systems with a high-level performance, clock management, and power management. This kit is suitable for prototyping for medium-to-high applications such as data centres, wireless communication, and DSP applications. This kit has a variety of features that make it suitable and sufficient for our design, such as block RAM with 21.1 MB,1920 DSP slices, and 520 I/O pins [41]. Moreover, this kit is compatible with the NAVLEO GNSS receiver. This receiver provides high-sensitivity acquisition and tracking loops. Furthermore, it supports both passive and active antennas. Additionally, it has a highly customizable and  
Figure 10: Amount of spectrum (passband) removed by the filter with a single jammer (55 kHz from the centre frequency, PRN Doppler = 700 Hz) with different windowing functions.  
Figure 9: Effect of a single jammer on receiver estimated _C/No_ (55 kHz from the centre frequency, PRN Doppler = 700 Hz) with different windowing functions.  
compact design, which makes it suitable for some GNSS space applications. The hardware prototype demonstration is shown in Figure 11.  
The system design was implemented with two data formats, which are fixed-point and float-point, in order to obtain the best performance design with the minimum hardware resources used. The fixed-point version was implemented by testing different precision sizes such as 8, 12, 16, 22, and 32 bits. The float-point was implemented with single-precision (32 bits). The algorithm in Figure 8 was implemented using Xilinx Vivado VHDL and each stage was validated. Table 2 shows the hardware implementation techniques that were used based on the precision types for the hardware development stage. Figure 12 shows the block diagram of the hardware implementation for the fixed-point design. The following sections explain the processes of developing the proposed algorithm.  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Hardware Techniques** & **Precision** \\ \hline
2 FFT & \\
2 IFFT & \\ ROM (1 K \(\times\) 8) & 8, 12, 16, 22, 32 bits (Fixed-Point) \\
4 FIFO & \\
3 Multiplexers (2 to 1) & \\ \hline
2 FFT & \\ Converter (fixed to float) & \\
2 IFFT & \\ ROM (1 K \(\times\) 8) & \\
4 FIFO & \\
3 Multiplexers (2 to 1) & \\ \hline \hline \end{tabular}
\end{table}
Table 2: Hardware techniques and precision types.  
Figure 11: Hardware prototype demonstration.