## 3 Building Blocks Designs
### Third-Order LC Ladder Filter and LO Buffer  
In mixer design, the trade-off between conversion gain and bandwidth is significant because the mixer operates in a broad bandwidth. To alleviate the gain drop at high frequency, an additional inductor is put between the mixer load and output buffer. With the introduced peaking inductor (L\({}_{P}\)), we can model the interface between the mixer load and the output buffer as a C-L-C ladder filter with single termination at the source. Figure 8 shows the single-ended representation of the interface network. R\({}_{L}\) is the output resistance of the mixer, C\({}_{INT}\) denotes the interconnection lines' parasitic capacitance parallel with the parasitic capacitance of the mixer switching stage, and C\({}_{BUF}\) denotes the input capacitance of the output buffer. The transfer functions of conversion gain without and with inductor, L\({}_{P}\), are presented as follows  
\[A_{v}(s)=\frac{2/\pi(g_{mp}+g_{mn})R_{L}}{1+sR_{L}(C_{INT}+C_{BUF})}\, \tag{2}\]  
\[A_{v,3 rd}(s)=\frac{2/\pi(g_{mp}+g_{mn})R_{L}}{1+sR_{L}(C_{INT}+C_{BUF})+s^{2} L_{P}C_{BUF}+S^{3}L_{P}C_{BUF}C_{INT}R_{L}}. \tag{3}\]  
By adding L\({}_{P}\), the conversion gain has a third-order response, and we synthesized the pole location following the Chebyshev filter realization to maximize the bandwidth [17]. The condition for a third-order Chebyshev filter dictates the following design parameter. The third-order Chebyshev filter with a 2 dB ripple was chosen with normalized pole locations at S\({}_{1,2}^{N}\) = -(0.185 \(\pm\) j0.923) and S\({}_{3}^{N}\) = -0.369. With R\({}_{L}\) = 86 \(\Omega\), C\({}_{INT}\) = 136 fF and C\({}_{BUF}\) = 234 fF for the given bias in the LC ladder network, L\({}_{P}\) was chosen to the value of 1 nH, which gives the desired filter transfer function.  
Figure 7: Schema of single-balanced mixer.  
The effect of the bandwidth extension with third-order LC ladder filter is clearly seen in Figure 9. At the band-edge (10 GHz IF frequency), the conversion gain is improved by 5.26 dB by employing the inductor peaking load as part of the ladder filter. The required LO signal of 30 GHz in the proposed receiver front-end is injected from the off-chip source. To ensure maximum signal reception at such a high frequency, we employed the reactive matching network to match 50 \(\Omega\) reference impedance. The matching network is implemented with a parallel capacitor and series inductor.  
Figure 10 shows the value of the matching components as well as the trajectory from the gate of the LO buffer to the 50 \(\Omega\). The series inductor is realized with serpentine line inductance from the pad to the active circuit. This line inductance is clearly noticeable from the chip photograph shown in Figure 11. The LO buffer is realized with two-stage inverter-type amplifiers, where the first stage is AC coupled to the off-chip source, and the second stage is DC coupled to maximize the f\({}_{t}\).  
Figure 8: Modeling of the mixer load with additional inductor for bandwidth extension.  
Figure 9: Simulated conversion gain of the down-conversion mixer with and without series peaking inductor L\({}_{P}\).  
Figure 11: Chip photograph of the proposed receiver front-end.  
Figure 10: Schema of the two-stage LO buffer with reactive matching and a Smith chart with the trajectory from \(Z_{BUF}\) to the 50 \(\Omega\).