## 3 Proposed DC-GCDRAM Architecture
### Convolution Mode  
The convolutional neural networks (CNNs) and deep learning are currently widely used for modern AI tasks such as traffic prediction, speech recognition, or image classification. But they consume extensive computing and memory resources. To reduce their arithmetic complexity and memory access, in recent algorithms called binarized neural networks [62], network weights and input activations are restricted to single bits (+1 or \(-1\)), such that the MAC operation, the most dominant operation in DNNs, is replaced by a simple bit-wise XNOR followed by population count (XNOR-and-accumulate) operation. The binarized neural networks (BNNs) are one of good candidates for deep learning implementation on DNN hardware, owing to their extreme energy efficiency. In Figure 15, we show how the configurable DC-GCDRAM perform the XAC operation for BNNs. The memory array composed of 3T cells stores network weights (W\({}_{i}\)) in a binary format. Activation switches [34] in Figure 15a, controlled by the input activations (marked with A\({}_{i}\) and /A\({}_{i}\) in a complementary style), connect a pair of bitlines to a bit-wise XNOR-SA. Thus, an XNOR result between W\({}_{i}\) and A\({}_{i}\) can be calculated during a read access. Figure 15b represents a simplified configuration to illustrate how the DC-GCDRAM executes the XAC operation. For each operating cycle, two rows (one from each 16-kbit array) are activated by enabling their RWLs. After the BL-SAs (SABL) are fired, the XNOR-SAs compute the bit-wise XNORs between activations and weights, and then the results are forwarded to the bit counters to carry out the population count operation. Each counter takes 128 bit inputs and generates an 8-bit count as output. Although this digital architecture has a  
Figure 14: Retention time constraint: (**a**) leakage currents during data hold; (**b**) storage voltage variations after data write (1.0 V, 85 \({}^{\circ}\)C, 5000 samples); and (**c**) RDL voltages for three possible cases—AB = 00 (V\({}_{\text{RDL0}}\)), AB = 01/10 (V\({}_{\text{RDL1}}\)), and AB = 11 (V\({}_{\text{RDL2}}\)). limited throughput compared to the analog XAC implementations which activate all their rows at once [18; 19], this approach does not need analog-to-digital converters incurring huge area/power overhead and provides extremely accurate computation results even with process-voltage-temperature (PVT) variation. Figure 16 shows the digital bit counter implemented in this design, which adds all of the bit-wise XNOR results to generate a population count. The counter circuit uses a Wallace-tree structure to compress the 128-bit digital input (XNOR\(<\)0:127\(>\)) to an 8-bit digital output (PC\({}_{\text{OUT}}\)\(<\)0:7\(>\)), which ranges from 0 to 128. The 12-layer tree structure  
Figure 15: XAC operation for BNNs: (**a**) bit-wise XNOR sensing scheme; (**b**) simplified configuration. achieves maximum possible reduction using 120 FAs and 15 half-adders (HAs), in which the schematics of adders are shown in Figure 17. Here, two kinds of FAs (22T FA with driving inverter and 16T FA without driving inverter) are interleaved to trade off the circuit delay against the circuit area. At 1.0 V and 25 \({}^{\circ}\)C, the total power dissipation and critical-path delay of the bit counter in performing a 128-bit population count have been observed to be 0.84 mW and 0.58 ns, respectively. Figure 16: Wallace tree population counter. The internal wire connections in tree structure are not shown. To verify the operation of convolution mode within the DC-GCDRAM array, circuit-level simulations have been performed for all XAC combinations. The simulated waveforms shown in Figure 18 plot the results for the case when both 128 network weights and 128 input activations are all logic-high. The convolution operation, similar to the read operation of memory mode, begins by pulling RWL up to a high level after the BL and XNOR-SA prechargers are disabled.