# The Challenges of Advanced CMOS Process from 2D to 3D
## 8 Conclusions  
This article has highlighted and compared the process of planar (2D) and 3D FETs. An overall view over the process flow of 2D and 3D FETs shows many similarities steps except the formation of fins cause new challenges in the fabrication. These challenges are addressed to the issues e.g., gate and spacer patterning, forming uniform fins and the growth of SiGe stressor material on source/drain regions. At first, a state-of-art lithography to form the nano-scale patterns is required. Nowadays, 193 nm ArF immersion with self-aligned double patterning and self-aligned quadruple patterning techniques are used for lithography of 22 nm node and beyond. Extreme ultraviolet lithography is a promising technique as well, but the high cost of this technique requires a second thought for implementing it for mass production. In planar transistors, SiO\({}_{2}\) layer as gate oxide was abandoned already in 45 nm technology node and HfO\({}_{2}\) was introduced instead due to its high dielectric constant and a relatively large bandgap. However, one of the main challenges of HfO\({}_{2}\) integration in nano transistors is the thermal instability of HfO\({}_{2}\)/Si contact. There is usually a SiO\({}_{x}\) interlayer between HfO\({}_{2}\) and Si substrate. The thickness of SiO\({}_{x}\) interlayer as well as the high-\(k\) dielectric have been constantly decreased leading to a decrease of the equivalent oxide thickness of gate dielectric. The traditional Si polycrystalline as gate material was also replaced with a metal gate e.g., TiAlN and TiN in a gate-last approach to avoid crystallizaitons of the high-\(k\) dielectric during the thermal treatment for dopants activation. To have a full control to form a Si fin with defined dimensions is a difficult task. It is especially critical to define the fin's height by etching the shallow trench isolation oxide. The variation in fin height influences electrical properties of transistors, e.g., the threshold voltage. This indicates (dry or wet) etching step needs more attention to be paid for 3D transistors compared to the planar ones. Dopant implantation of the fins requires a profile with conformal distribution otherwise the drive current of the transistors is degraded. To implant the fins in an array is a difficult task due to the shadowing caused by the neighboring fins. An alternative technique is using plasma doping with optimized process parameters. SiGe layers are grown selectively in source/drain areas to create strain in the channel region. The selective epitaxy in the planar transistor is performed in the recessed areas while for 3D FETs is intended to elevate in the source/drain. The epi-layers on 3D FETs may involve in several problems e.g., strain relaxation on the fins' faceted shape leading to higher defect density and pattern dependency effect due to different transistor architecture and their density in the chip. In final, most of the presented process challenges in this article are undergoing developments or have partially solved. However, the most critical issue of future downscaling of transistors is the dramatic increase of manufacturing cost due to the use of innovative techniques e.g., EUVL. One way to reach a solution is the increase of wafer diameter from present 300 mm to 450 mm. However, there is a big skepticism to use such big wafers due to their heavy weight totally new mechanical robot systems have to be developed. Furthermore, the process time will remarkably increase in terms of low rate of warming and cooling of such big wafers. There is a better solution to overcome these difficulties by using 3D structures instead of continuously downscaling the transistors. This effort would extend our research for many years in future to integrate many layers or devices vertically in the chip. This work was supported by the National Key Research and Development Program of China under Grant No. 2016 YFA0301701, and the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No. 2016112.