# Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing
## 3 Results and Discussion
### Full Adder Implementation with n-SIMPLY  
Exploiting n-SIMPLY, we propose a novel implementation of a LIM 1-bit full adder (FA). The schematic of the array and the sequence of operations are shown in Figure 8a,d. We simulated the FA at 0.5 GHz (see the example in Figure 8c) using the 4 RRAM technologies and compared the total energy consumption (including the comparator and the effects of variability and RTN) in Figure 8b. Not surprisingly, technology 3 [29], which is the technology with the lowest current compliance (I\({}_{\text{C}}\) = 100 \(\mu\)A, see Figure 1c), results in the lowest energy consumption. We considered the worst-case result (i.e., Energy FA max column in Figure 8b) obtained with technology 3 and benchmarked it in detail against existing LIM solutions in the literature and its CMOS counterpart in Tables 4 and 5, respectively. Considering the worst-case energy contribution for each 1-bit FA operation results in an energy consumption overestimation, that, as a first-order approximation, provides enough room to account for additional energy dissipated by components in the peripheral circuitry that were not included in the circuit simulations (i.e., the analog tri-state buffers). The proposed FA outperforms all existing IMPLY-based LIM solutions (both simulation \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Parameters** & **Tech. 1** & **Tech. 2** & **Tech. 3** & **Tech. 4** \\ \hline R\({}_{\text{G}}\) & 2 k\(\Omega\) & 6 k\(\Omega\) & 10 k\(\Omega\) & 1.5 k\(\Omega\) \\ V\({}_{\text{SET}}\) & 1.9 V & 1.7 V & 3 V & 1 V \\ V\({}_{\text{READ}}\) & 0.2 V & 0.2 V & 0.2 V & 0.2 V \\ V\({}_{\text{FAIL5}}\) & \(-\)1.55 V & \(-\)2 V & \(-\)2.8 V & \(-\)1.54 V \\ Energy 2-SIMPLY & 29 f\(-\)2.1 pJ & 13 fJ\(-\)370 fJ & 12 fJ\(-\)571 fJ & 35.4\(-\)462 fJ \\ (min-max) * & 30 fJ\(-\)2.2 pJ & 18 fJ\(-\)371 fJ & 13 fJ\(-\)568 fJ & 32.6\(-\)462 fJ \\ Energy 4-SIMPLY & 29 fJ\(-\)2.2 pJ & 12 fJ\(-\)380 fJ & 12 fJ\(-\)567 fJ & 38.7\(-\)465 fJ \\ (min-max) * & & & & \\ \hline \hline \end{tabular}  
* The comparator overhead, variability, and RTN are included in the simulations by repeating the simulation 50 times for each input configuration.  
\end{table} 
Table 3: Circuit parameters and energy consumption of n-SIMPLY operation (n = 2, 3, 4) with t\({}_{\text{pulse}}\) = 1 ns. Figure 7: Distribution of the V\({}_{\text{N}}\) voltage (**a**) experimentally evaluated with technology 4, and (**b**) simulated with the compact model calibrated on technology 3, for increasing number of input bits (i.e., n = 2, 3, 4), including variability (50 trials) when P = Q = 0 (blue bands) and P\(\
eq\)Q (green bands) for the \(n\)-SIMPLY operation (\(n\) = 2, 3, 4) at V\({}_{\text{READ}}\) = 0.2 V. The read margins (RM—black arrows) and associated threshold voltages (V\({}_{\text{TH}}\)—grey circle) for the comparator are evidenced. Black whiskers indicate the extreme points of the distributions. Red crosses indicate outliers due to RTN. V\({}_{\text{N}}\) when P = Q = 1 is always much higher than in all other cases (thus is not reported in these box plots). and experimental works [12; 20; 36; 37; 38]), in terms of the number of steps (delay) and energy consumption, using few devices and lowering the energy-delay product (EDP) by a factor \(>\)10\({}^{3}\), bringing it much closer to the CMOS one. We compare the performance of the proposed solution vs. CMOS (with and without considering the VNB energy and time overhead) in Table 5 considering the parallel execution of 512 32-bit FA operations (simple ripple carry architecture), which entails 4 kB data, which is the common memory page size [39]. The proposed solution strongly outperforms different CMOS FA solutions [40; 41; 42] (\(>\)10\({}^{6}\) improvement in EDP) when VNB data exchange overhead [39] is included.