## 5 Experimental Results and Analysis  
### Experimental Setup  
The robustness of APUFs against malicious attacks is evaluated by deploying the proposed architecture on the ALINX AX4010 FPGA development board. The distinct responses of APUFs to challenge inputs serve as a means of device authentication, preventing unauthorized access to IoT networks. The design is implemented using Quartus(r) Prime Standard Edition version 18.1, as depicted in Figure 12. A 64-bit APUF is implemented on an Altera, Cyclone IV EP4 CE10F17C8 FPGA from Intel, Santa Clara, CA, USA (60 nm technology, 1.2 V, 256-pin FBGA). In our experiments, an FPGA is designated as an IoT node incorporating an embedded PUF for authentication. Since the objective of this study is to leverage default routing, we allow the FPGA tool to place APUF components autonomously without applying placement constraints, manual routing, or hard macros. The proposed APUF-based authentication scheme utilizes an LFSR-based random generator, implemented on the FPGA, which inputs a 64-bit challenge to the APUF circuit, and the corresponding responses are collected. FPGA resource utilization for APUF implementation includes 81 (out of 10,320) LEs, 129 registers, 68 (out of 92) available I/Os, and a maximum frequency (\(f_{\text{max}}\)) of 98.97 MHz. A database of approximately 100,000 unique challenge-response pairs (CRPs) is collected using a logic analyzer and stored in a.csv file. During the authentication stage, a challenge from the CRP database is presented to the PUF, and the generated response is compared with the stored response associated with that challenge for verification. The outline of the complete flow for generating the PUF response is shown in Algorithm 1. The APUF and pseudo-random generator are modeled using the VHDL programming language. The design is then synthesized into a circuit comprising the LEs available on the FPGA chip. Logical synthesis optimizes the design and maps it onto FPGA resources such as LEs, ALMs, or dedicated logic blocks. All design files, including third-party netlists, are integrated into a single project database. The functional correctness of the synthesized design is verified through RTL simulation without considering timing closure. During the fitting stage, the Quartus Fitter tool automatically places the LEs, which may result in varying path delays in the APUF, regardless of the challenge inputs. However, the chip's floorplan can be manually adjusted using the Chip Planner. Timing analysis is performed to estimate the propagation delays across all routing paths in the fitted circuit, followed by timing simulations. Finally, the designed circuit is implemented on the target  
Figure 12: Intel Quartus Prime Design Suite targeted to a Cyclone IV FPGA development board. FPGA chip by programming the configuration switches to configure the LEs and establish the required wiring connections. ```
Input:\(N\): number of challenge bits per PUF instance \(challenge[N]\): vector of size \(N\) bits \(clk\): system clock signal Output: response bit /* Initialization */ \(path\_A[1]\gets 0\) \(path\_B[1]\gets 1\) for\(i\gets 1\)to\(N-1\)do /*Generate delay paths using multiplexers */
if\(challenge[i]=1\)then \(path\_A[i+1]\gets path\_B[i]\) \(path\_B[i+1]\gets path\_A[i]\) else \(path\_A[i+1]\gets path\_A[i]\) \(path\_B[i+1]\gets path\_B[i]\)  end if  end for /* Determine the response bit */
#If\(path\_A\) wins, response is 0; else 1 */
#response \(\leftarrow path\_A[N]\)  end for return\(challenge,response\)
```  
**Algorithm 1**Arbiter PUF  
The reproducibility of a PUF evaluates how consistently it generates the same response on a given device, like FPGAs. It is quantified by the intra-device Hamming distance (intra-HD), and a perfectly reproducible PUF achieves an average intra-HD of 0% [73]. Figure 13 represents the intra-HD metrics of the proposed APUF against CRP size, and it is benchmarked with the works of other researchers in Table 3, along with other performance metrics.