# Reliability Prediction of Mixed-Signal Module Based on Multi-Stress Field Failure Mechanisms
## 5 Electro-Thermo-Mechanical Multi-Physics Coupling Analysis
### Power Consumption Analysis and Thermal Simulation of the Communication Module  
This article conducts a power consumption analysis for the FPGA and SRAM based on the communication module's operating conditions. Subsequently, a thermal simulation model is created using Icepak to perform transient thermal simulations, obtaining the temperature field distribution at different time points during the temperature cycling process. This serves as a foundation for the subsequent mechanical simulation analysis and reliability evaluation of the communication module. The FPGA and SRAM are the main sources of heat in the communication module, and their power consumption directly affects the temperature distribution and structural stress. The power consumption of CMOS circuits, such as FPGA and SRAM, can be divided into static power consumption and dynamic power consumption. The power consumption of CMOS circuits is expressed as follows:  
\[P_{\text{total}}=P_{\text{s}}+P_{\text{d}}=V_{\text{dd}}\cdot I_{\text{leakage }}+\alpha\cdot C\cdot V_{\text{dd}}^{2}\cdot f \tag{1}\]  
where \(P_{\text{total}}\) is the total power consumption, \(P_{\text{s}}\) is static power consumption, \(P_{\text{d}}\) is dynamic power consumption, \(V_{\text{dd}}\) is the supply voltage, \(I_{\text{leakage}}\) is the leakage current, \(\alpha\) is a factor representing the switching activity of the circuit, \(C\) is the equivalent node capacitance, and \(f\) is the operating frequency. From this equation, it is clear that power consumption is closely related to the leakage current and operating frequency in the communication module. For CMOS circuits, the standby current is 10 mA, and the operating current at a frequency of 20 MHz is 185 mA. The standby current is considered the leakage current, and the difference between the operating current and the standby current represents the dynamic power consumption. When analyzing SRAM at high power consumption with a communication baud rate of 921,600, the circuit simulation model shows that the SRAM operating frequency is approximately 10,000 Hz at this baud rate. Using the equation below, the power consumption of the SRAM is estimated to be about 50.09 mW, with static power consumption as the dominant factor. \[P_{\text{SRAM}}=P_{\text{s}}+P_{\text{d}}=5\cdot 10+(185-10)\cdot\frac{10000}{20000 0000}\approx 50.09\text{mW} \tag{2}\]  
In the FPGA power consumption analysis, direct monitoring is difficult due to the numerous signals. Therefore, two rounds of data transmission and reception tests are conducted using Quartus II 13.1 and Modelsim 10.4 for co-simulation. The Modelsim gate-level simulation generates VCD waveform files, which are then analyzed using PowerPlay, as shown in Table 2. The total power consumption of the FPGA is found to be 108.38 mW, with static power consumption exceeding dynamic power consumption. The I/O power consumption is caused by the charging and discharging of drivers and external capacitors, combining both static and dynamic power consumption. The thermal simulation model for the communication module is established by importing the 3D model and setting boundary conditions, environmental temperature, and material properties. Based on the power consumption analysis results for FPGA and SRAM, thermal loads are applied to the model, and meshing is performed to complete the thermal simulation model. The environmental temperature of the spacecraft is a temperature cycle, with a temperature range from 0 \({}^{\circ}\)C to 50 \({}^{\circ}\)C, a heating and cooling rate of 10 \({}^{\circ}\)C/min, a high and low temperature holding time of 25 min, and a cycle frequency of 1 cycle/h, with an initial temperature of 20 \({}^{\circ}\)C.  
Material properties for the model are determined, with the PCB's thermal conductivity treated as anisotropic, and the rest of the materials are assumed to be homogeneous. Internal thermal loads are applied, focusing solely on the power consumption of the FPGA and SRAM chips.