## 5 FPGA Implementation  
Implementing algorithms on hardware devices is crucial as it optimizes the use of hardware resources. For instance, we can determine the number of coefficients in a series to achieve an appropriate approximation of and the number of bits used to represent a real number (precision). We can also ascertain if the implementation can be duplicated for multichannel problems.  
Analyzing the arithmetic operations in Equation (17), we conclude that a feedback implementation is appropriate, as it minimizes hardware resources. The operations in Equation (17) will be repeated as follows:  
1. Perform the products \(A_{1}V_{1}^{1}cos(\theta)\) and \(A_{1}V_{1}^{2}sin(\theta)\). The two's complement format is chosen for number representation, as the algorithm involves signed arithmetic operations.
2. Sum the results from the previous step.
3. Temporarily store the result.
4. Perform the products \(A_{2}V_{2}^{1}cos(2\theta)\) and \(A_{1}V_{2}^{2}sin(2\theta)\) and add them to the temporary result.
5. Repeat the process until term \(N=16\).  
The advantage of this implementation is that the arithmetic modules can be reused. The hardware implementation components include:  
1. A double-memory ROM block to store the coefficients \(A_{k}V_{k}^{1}\) and \(A_{k}V_{k}^{2}\).
2. A Xilinx direct digital synthesizer (DDS) module (see [23]) to generate the values of \(sin(k\theta)\) and \(cos(k\theta)\) for \(k=1,\dots,16\).
3. Multiplexers to maintain synchrony in the control section.  
Considering this, Figures 12 and 13 show the required hardware resources for architecture Modes 1 and 2, respectively.  
The implementation results presented were obtained using the VHDL (Very High Speed Integrated Circuit Hardware Description Language) code synthesized on the Vivado IDE c2018.2.2 (64 bit) and tested on the Xilinx(r) 7 FPGA series. This series comprises four FPGA families that address a complete range of system requirements ranging from low-cost, small form factor, cost-sensitive, high-volume applications to ultra-high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications: Spartan-7 xc7s100 fgga484, Virtex-7 xc7v585 ffg1157, Kintex-7 xc7k70 tfbg484, and Artik-7 xc7a35 tcpg236. Tests were carried out using a 100 MHz base clock.  
Figure 11: Exact source is shown in red, and the recovered source with regularization is in blue. The Tikhonov regularization method was used to handle numerical instability and to obtain a good approximation of the exact source. The regularized solution acted as a smoothing filter.  
The instrumentation developed for the implementation of the algorithm consists of 48 coefficients involved in expression (13) with \(N=16\). Each coefficient is 16 bits long. Therefore, there are 16 coefficients for \(A_{k}\), \(V_{k}^{1}\), and \(V_{k}^{2}\). The DDS component was configured with a partition of 8 bits for the phase and amplitude of the sinusoidal functions.  
Figure 12: Feedback architecture, Mode 1: In this mode, the control unit (Section B), as well as the phase generation and the processing unit, are independent in each channel. This allows for operation at different speeds.  
Figure 13: Feedback architecture, Mode 2: In this mode, the control section is shared with the algorithm operations section, resulting in coupled synchronization of the trigonometric base operations.  
The product requires 40 bits since we have 32-bit and 8-bit numbers. Finally, both the accumulated sum and the resulting output require 40 bits.