## 2 CCSDS 131.2-B Protocol for High-Rate Telemetry
### Receiver Side  
Transmitter functions of the standard have to be implemented on satellites, for transmitting data towards Earth. On the other side, ground stations need to implement a standard-compliant receiver to receive and decode the signal. The general architecture of a receiver compliant with the CCSDS 131.2-B standard is detailed in Figure 2.  
The receiver side is composed of a sequence of blocks that aims to extract and decode the information sent by the transmitting side. First, an ADC block should sample the incoming IF signal that is then down-converted to the base-band. This can be carried out for example by using a local digital quadrature oscillator. The signal is then filtered and decimated up to an integer number of samples required by the timing synchronization algorithm. The latter is used to recover the transmission clock; thus, it samples the data stream in the correct instant, to recover the amplitude and phase-modulated symbols. After that, the frame marker detector block allows the recovery of the PL frame structure by applying a correlation between the reference FM and the received bits. This is crucial to enhance the data-aided algorithms used for frequency correction and phase correction, whereas the previous blocks (i.e., timing recovery) must be capable of performing their functions without knowing the structure of the frame and in the presence of a frequency error. After compensating for the frequency impairment, the symbols are unscrambled according to the standard. This allows us to mitigate the effect of transmitter pseudo-randomization, re-establishing pilot values. At the same time, the descriptor decoder, analyses the FD of the frame, identifying the presence/absence of pilots and the ModCod used. The last part of the architecture is preceded by the estimation of the signal-to-noise ratio (SNR) and the correction of the amplitude of the symbols to match the reference constellation. This step is needed to compute the log-likelihood ratio (LLR) of the received bits by the constellation demapper module. Finally, the SCCC decoder uses this soft-bit information (i.e., the LLRs) to recover errors in the satellite transmission and produce the information bits. Figure 2: Receiver Architecture. The structure of the described receiver is quite complex, both for impairment recovery and for the internal architecture of the SCCC decoder. For decoding information at a high data rate, it is necessary to compute many operations on a large quantity of data in a small amount of time. For this reason, the state-of-the-art receivers for CCSDS 131.2-B communication are based on complex and expensive HW solutions, such as the aforementioned Cortex HDR [14]. The limiting factor of this receiver, and other HW receivers as well, is not only represented by the complexity of the design, but also by its very high cost, which restricts the testing and adoption of the standard. This is currently one of the main factors limiting the use of the CCSDS 131.2-B standard, considering also that it could be involved also for science missions where the performance requirements can be relaxed; hence, there is no need to reach the highest performance provided by a HW receiver (i.e., 500 Mbaud). For these reasons, this paper describes the implementation of a SW receiver to provide a low-cost alternative to HW receivers for promoting the use of the CCSDS 131.2-B standard by implementing easier and lower-cost ESEs to test the transmission and satisfy the requirements of science missions. At the state of the art, as far as the author knows, the only SW solution for CCSDS 131.2-B is represented by the so-called SW EGSE [19]. It is a software simulator based on Matlab SW [20], capable of emulating the downlink communication compliant with the standard. This has been implemented for testing the communication and above all for testing the standard itself, as well as for assessing its capabilities.