# Design of Nanosecond Pulse Laser Diode Array Driver Circuit for LiDAR
## 2 Circuit Principle
### Pulse Narrowing Circuit  
The laser pulse width we require is several nanoseconds, indicating that the pulse width output by the control circuit should also be in the nanosecond range. However, the clock frequencies of common microcontrollers (MCU) typically range from tens of MHz to hundreds of MHz, resulting in an output pulse width of approximately tens of nanoseconds. The core operating frequency of FPGAs usually does not exceed 200 MHz, yielding an output pulse width of around tens of nanoseconds. Therefore, it is necessary to utilize a pulse narrowing circuit to narrow the wide pulse signal from the MCU or FPGA. Currently, the primary methods for narrowing pulse signals include avalanche transistors, RC charging and discharging, and gate circuit delay [35; 36]. An avalanche transistor utilizes the avalanche effect of the collector junction to generate and amplify narrow pulses [35], typically achieving nanosecond and sub-nanosecond narrow pulses. Since the gate driver we employ can only support nanosecond-level pulse inputs, we utilize RC charging and discharging and gate circuit delay methods to obtain narrow pulses.  
Figure 4 shows the schematic diagram and signal timing diagram of the RC pulse narrowing circuit, which consists of capacitors, resistors, and an AND-gate. When the signal \(V_{A}\) generates a pulse, the capacitor \(C\) starts charging; due to the charging of the capacitor, the voltage of signal \(V_{B}\) decreases, eventually dropping to a low level. When the signal \(V_{B}\) drops from a high level to the threshold level of the AND-gate, the signal \(V_{C}\) drops from a high level to a low level, and the pulse width can be calculated using Equation (6).  
\[V_{T}=V_{T}\Big{[}1-\exp\Big{(}-\frac{\tau}{RC}\Big{)}\Big{]}\Rightarrow\tau= \ln\!\left(\frac{V_{H}}{V_{H}-V_{L}}\right)\cdot RC \tag{6}\]  
Figure 3: Simulation waveform of LD pulse response. (**a**) \(L>4R^{2}C\). (**b**) \(L=4R^{2}C\). (**c**) \(L<4R^{2}C\).  
Here, \(V_{H}\) represents the high-level voltage, \(V_{L}\) denotes the low-level voltage, \(V_{T}\) signifies the threshold voltage, and \(\tau\) indicates the output pulse width. When \(V_{T}\) is set to half of \(V_{H}-V_{L}\), the output pulse width \(\tau\) is approximately 0.7\(RC\). To achieve a narrow pulse, we need to reduce the value of \(RC\). Through experiments, we discovered that when the pulse width is 10 ns, further reducing the value of \(RC\) renders the signal unable to drive the gate circuit due to the excessively small capacitance, leading to insufficient current. Ultimately, we opted to utilize gate circuit delay to achieve a narrow pulse output.  
Figure 5 shows a pulse narrowing circuit implemented using NOT-gate delays. It can be achieved by combining an odd number of NOT-gates with an AND-gate, or by combining an even number of NOT-gates with an XOR-gate. The NOT-gate we used is the SN74 LVC1G04 produced by Texas Instruments (TI) (Dallas, TX, USA), with a propagation delay of 2.5 ns at 5 V voltage. In practice, we take the full width at half maximum (FWHM) of the output pulse as the pulse width. Theoretically, the fewer the number of NOT-gates used, the smaller the pulse width obtained. However, an excessively narrow pulse cannot drive the gate driver or the MOSFET of the subsequent circuit. To match the subsequent circuit, we ultimately used 3 NOT-gates to achieve a delay time of approximately 7.5 ns. The FWHM of the output pulse is approximately 3.7 ns, which is less than 5 ns.