## 7 Conclusions  
The proposed solution of direct hardware control program implementation allows for obtaining high-performance control systems, directly from the control programs given, according to the IEC61131-3 requirements [1,11]. A complete methodology is shown, covering the initial program translation to an intermediate graph form, which is target independent. The fast LD theorem and utilization of data flow graph in the hardware structure synthesis process is essential for obtaining an efficient program implementation. The intermediate data flow graph form enables abstract processing representation and the extended optimization of an input program. The optimization process allows for the detection of unused variables and operations. Enhancing the data flow graph with the synthesis process using BDD further extends the optimization process by optimizing logic expression. Finally, using BDD representation for logic operations enables performing technology to map the logic operations to modern LUT-based FPGA devices. It should be noted that, at the same time, intermediate representation enables managing arithmetic computations that are optimized and implemented, using the respective components available inside FPGA devices. Finally, the program is translated into a partially-mapped structure, ready for implementation, using FPGA vendor tools [42]. The obtained hardware structure of the dedicated controller offers very high performance and a short response time. The response time of the controller is constant and does not depend on logic conditions or the internal program state during execution. This allows using the controller structure in time-critical applications, when a response must be delivered in a given time. As it was shown, the total processing time requires several clock cycles (the benchmarks in Table 2 required two to seven clock cycles). This allows for obtaining the response time, in the range from 10 ns to 35 ns. The performance comparison, to the number of IL instructions executed, reaches up to 43.4 GIPS (billion instructions per second). This significantly outperforms the programmatic execution of control algorithms and shows the power of a dedicated hardware implementation methodology (Table 3). It is essential to point out that the user implementation process of a control program is fully automatic.  
PLC program compilation, intermediate representation, hardware scheduling, mapping, and main author, A.M.; BDD decomposition and decomposition section author, M.K.; algorithms verification, result discussion, text review, D.K. All authors have read and agreed to the published version of the manuscript.  
This work was supported by funding from the Ministry of Science and Higher Education for Statutory Activities of Digital Systems Division of the Silesian University of Technology of Gliwice (BK226/RAu-12/2021).  
Not applicable.  
The authors declare no conflict of interest.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Program** & **Rungs** & **I\({}_{\text{CNT}}\)** & **S7-319** & **RG** & **RGO** **\({}^{**}\)** & **DFG** \\  & & **[ns]** & **[ns]**/[T\({}_{\text{CK}}\)] & **[ns]/[T\({}_{\text{CK}}\)]** & **[ns]/[T\({}_{\text{CK}}\)]** \\ \hline AGV & 23 \({}^{*}\) & 86 & 344 & 120/24 & 25/5 & 10/2 \\ GRAVEL & 33 \({}^{*}\) & 162 & 696 & 165/33 & 55/11 & 35/7 \\ MIX\_BRIX & 35 \({}^{*}\) & 141 & 852 & 180/36 & 35/7 & 25/5 \\ LIFT\_4 & 28 & 151 & 620 & 145/29 & 35/7 & 20/4 \\ LIFT\_8 & 40 & 396 & 1584 & 205/41 & 35/7 & 20/4 \\ LIFT\_12 & 62 & 716 & 2912 & 315/63 & 35/7 & 20/4 \\ \hline \hline \end{tabular}  
* Equivalent rungs count translating SFC program to LD. ** Estimated execution time, due to lack of timers, counter, and arithmetic block handling by the method.  
\end{table}
Table 3: Performance comparison with other methods and Simatic S7 PLC CPU [43].