# Design of Nanosecond Pulse Laser Diode Array Driver Circuit for LiDAR
## 3 Testing and Experimentation  
Figure 12 depicts the experimental system we established for circuit testing. The system comprises a pulsed laser emission circuit, an FPGA test circuit, a battery, a screen, and a charge coupled device (CCD) camera. The pulsed laser emission circuit incorporates eight semiconductor LDs, GaN MOSFETs, gate drivers, analog multiplexers, and a boost power supply. As described earlier, the external laser diode address configuration signal and pulse input signal are generated by the FPGA and sent to the analog multiplexer and pulse narrowing circuit, respectively, enabling the eight semiconductor laser diodes to emit laser pulses individually. The scanning period of the FPGA is 8 \(\upmu\)s, and the emission frequency of a single pulse emission circuit is 125 kHz. The CCD camera captures laser spots on the screen. Due to the extremely fast scanning speed, the camera cannot recognize changes in the spots. Therefore, what is visible in the images captured by the camera are eight distinct laser spots, as shown in Figure 12.  
Next, we measured the pulse width and jitter of the eight channels of pulses output by the multiplexer. As shown in Figure 13, the pulse widths of channels 1, 2, 3, and 4 displayed on the oscilloscope were 3.386 ns, 3.313 ns, 3.266 ns, and 3.381 ns, respectively. Table 1 displays the pulse widths of all eight channels, all of which are less than 5 ns. Figure 13 also shows the histogram distribution of the pulse widths of these four channels, with each channel measured 5000 times. The standard deviations of the pulse width jitter for the four channels are 48 ps, 46 ps, 53 ps, and 102 ps, respectively. Table 1 displays the standard deviations of the pulse width jitter for all eight channels, which generally do not exceed 102 ps. The pulse jitter standard deviation is less than 3% of the pulse width, indicating that both the pulse width and stability meet the design requirements. Figure 14 illustrates the pulse timing sequence for channels 1, 2, 3, and 4. The phase difference between channels 1 and 2 is 998.1 ns, that between channels 2 and 3 is 1.001 \(\upmu\)s, and that between channels 3 and 4 is 999.1 ns. This indicates a channel switching time of 1 \(\upmu\)s. The pulse emission frequency is 1 MHz, and the emission frequency of the same LD is 125 kHz. Figure 14b shows that the gate driver output pulse width of channel 1 is 3.402 ns, with the peak value of the first positive pulse being 6.527 V, the peak value of the first negative pulse being \(-1.408\) V, the peak value of the second positive pulse being 1.243 V, and a pulse oscillation decay time of 71.575 ns. Due to the influence of the external circuit on the pulse waveform of the LD, it is impossible to directly measure the current of the LD. Therefore, we indirectly measure the voltage across the LD by measuring the change in the drain voltage of the GaN MOSFET. As shown in Figure 7, the voltage across the LD is obtained by subtracting the drain voltage of the Ga  
Figure 12: Physical image of the testing system. supply voltage \(V_{LD}\) of the LD. According to the chip manual of the LD, when the voltage is 18 V, the peak power of the output pulse light is 75 W. Therefore, when the drain voltage of the GaN MOSFET is less than 0 V during conduction, the output power of the LD can reach 75 W. Figure 14c shows the drain voltage pulse of the GaN MOSFET in channel 1. This pulse is a negative pulse with a pulse width of 4.153 ns. Since it operates in the mode shown in Figure 3c, the pulse will oscillate. The peak voltage of the negative pulse is \(-\)2.516 V, which can ensure that the pulse power of the LD exceeds 75 W. The peak value of the second negative pulse is 7.873 V, the peak value of the first positive pulse is 33.830 V, the pulse width is 2.828 ns, the peak value of the second positive pulse is 23.085 V, and the pulse oscillation decay time is 107.326 ns. The above measurement results are fully consistent with the description in Figure 3c. Figure 14: Pulse signal waveform testing.