# A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs
## 2 Proposed Self-Calibration Technique  
A switched-capacitor amplifier (SCA) with a gain of two is a key building block of the MDAC in a 1.5-bit pipeline stage. The conventional SCA and proposed self-calibrating SCA for gain-of-two amplification are shown in Figure 1. Compared with the conventional SCA, only two additional switches, which are placed in the dashed box, are added to self-calibrate the capacitor mismatch error. Even though the calibration circuit is employed for the gain-of-two SCA for this work, it can be used for the SCA with various gains using a flip-around amplification scheme. Figure 1: Simplified circuit diagram of an SCA for gain-of-two amplification: (**a**) Conventional SCA. (**b**) Proposed self-calibrating SCA. The SCA operates in two modes: calibration and normal. In calibration mode, the error voltage caused by the capacitor mismatch is converted into a digital signal, saved in memory, and subtracted from the ADC output. In normal operation, the two additional switches remain OFF and the SCA functions as a conventional MDAC for a 1.5-bit pipeline stage. The operation of the SCA during capacitor mismatch calibration is shown in Figure 2. The SCA operates with a two-phase non-overlapping clock, sampling, and amplification phases, similar to the conventional SCA. In the sampling phase, the reference voltage V\({}_{\text{REF}}\) is applied to the feedback capacitor (C\({}_{\text{F}}\)) and a common-mode voltage or 0 is applied to the sampling capacitor (C\({}_{\text{S}}\)), as shown in Figure 2a. The total charge sampled on the capacitors is expressed as follows:  
\[\text{Q}_{\text{total}}=\text{V}_{\text{REF}}\cdot\text{C}_{\text{F}}+(\text{ V}_{\text{CM}}-\text{V}_{\text{CM}})\cdot\text{C}_{\text{S}} \tag{1}\]  
In the amplification phase, the bottom plate of C\({}_{\text{F}}\) is flipped around and connected to the op-amp output, whereas the bottom plate of C\({}_{\text{S}}\) is connected to V\({}_{\text{REF}}\), as shown in Figure 2b. From the principle of charge conservation, the total charge Q at the end of the amplification phase is as follows:  
\[\text{Q}_{\text{J}}^{\text{total}}=\text{V}_{\text{OUT}}\cdot\text{C}_{\text{ F}}+\text{V}_{\text{REF}}\cdot\text{C}_{\text{S}} \tag{2}\]  
Figure 2: Operation of the self-calibrating SCA at each clock phase: (**a**) Sampling Phase 1. (**b**) Amplification Phase 1. (**c**) Sampling Phase 2. (**d**) Amplification Phase 2. Suppose \(\mathrm{C_{F}}=\mathrm{C}\) and \(\mathrm{C_{S}}=(1+\epsilon)\mathrm{C}\). In that case, the op-amp output voltage becomes \(\mathrm{V_{REF}}\) multiplied by the mismatch factor, which is called the error voltage (\(\mathrm{V_{E}}\)), expressed as follows:  
\[ \begin{array}{ll}\mathrm{V_{OUT}}&=\mathrm{V_{REF}}\ -\ \mathrm{V_{REF}}\ \cdot \mathrm{C_{S}}/\mathrm{C_{F}}\\ &=-\ \epsilon\cdot\mathrm{V_{REF}}\end{array}  \tag{3}\]  
In sampling phase 2, as shown in Figure 2c, \(\mathrm{V_{OUT}}\) is sampled on \(\mathrm{C_{S}}\) by turning \(\mathrm{S_{4}}\) and \(\mathrm{S6}\) ON. The charge on \(\mathrm{C_{S}}\) is then transferred to \(\mathrm{C_{F}}\) in amplification phase 2 and \(\mathrm{V_{OUT}}\) becomes:  
\[\mathrm{V_{OUT}}=-2\epsilon\cdot\mathrm{V_{REF}}\ -\ \varepsilon^{2}\cdot \mathrm{V_{REF}}\cong-2\epsilon\cdot\mathrm{V_{REF}} \tag{4}\]  
Since \(\mathrm{V_{REF}}\) is known, the mismatch factor \(\epsilon\) can be derived from the digitized value of \(\mathrm{V_{E}}\), converted by the remaining pipeline stages. The proposed SCA is particularly advantageous in that \(\mathrm{V_{E}}\) can be accurately amplified by a power of two with no additional circuits by repeating the processes of sampling phase 2 and amplification phase 2. Furthermore, amplification by a gain of two can be considered as a 1.5-bit pipeline stage operation when the amplitude input is relatively small.