# A Temperature-Robust Envelope Detector Receiving OOK-Modulated Signals for Low-Power Applications
## 3 ED and PTAT Block Description  
### ED Model and Receiving Chain Sensitivity Optimization  
For the sake of clarity, this subsection summarizes the features of the employed ED architecture just as in [12]. Its topology (Figure 1a) is a variation of the Dickson charge pump. The following is based on the standard subthreshold current model for the MOSFET-based diodes:  
\[I_{DS}=I_{S}\frac{W}{L}e^{\frac{V_{GS}}{nT_{T}}}\left(1-e^{-\frac{V_{DS}}{T}} \right), \tag{1}\]  
where  
\[I_{S}=I_{S0}e^{-\frac{V_{TH}}{nT}}, \tag{2}\]  
\(W/L\) is the aspect ratio of the MOSFET and \(I_{S0}\) is a technological parameter. Assuming an input OOK-modulated signal \(V_{RF,ant}(t)=V_{M}(t)\cos(\omega t)\), where \(V_{M}(t)\) is the envelope signal and is equal to \(V_{M0}\) when a '1' is transmitted and equal to 0 when a '0' is transmitted, the output amplitude is [12]  
\[V_{ED}=\frac{NV_{M0}^{2}}{4 nV_{T}}, \tag{3}\]  
where \(N\) is the number of diode stages, \(n\) is the non-ideality factor of the diodes and \(V_{T}\) is the thermal voltage. Figure 3 shows the typical receiving chain of an ultra-low-power system, such as that of a WuRX, excluding the final digitizing element. It is composed of a matching network, ED and baseband amplifier. As mentioned, at RF, the ED can be seen as a load composed of a resistance and a capacitance in parallel, \(R_{in}\) and \(C_{in}\), for the preceding matching network. This implies that the matching network is designed based on \(R_{in}\) and \(C_{in}\) values. The values for \(C_{gate}\), \(C_{drain}\) and \(C_{gnd}\) of Figure 2 are mainly determined by the RF frequency they need to correctly transfer to the internal diode nodes and filter out, respectively. Assuming \(C_{gate}\), \(C_{drain}\) and \(C_{gnd}\) to be big enough with respect to the \(C_{gs}\) of the diodes and to have negligible parasitics, \(R_{in}=r_{DS}/N\), where \(r_{DS}\) is the channel resistance of diodes, and \(C_{in}=C_{in}^{\prime}+C_{pad}=NC_{gs}+C_{pad}\), where \(C_{pad}\) is the parasitic capacitance of the RF input pad. The delay introduced by the ED and, thus, its maximum operating bitrate, can be found by applying the open circuit time constant method to the equivalent circuit in Figure 1b, assuming all capacitances to have the same value. This yields [20]  
\[\tau\sim Cr_{DS}\frac{N(N+1)}{2}=CR_{in}\frac{N^{2}(N+1)}{2}. \tag{4}\]  
Therefore, \(\tau\) is almost proportional to the cube of \(N\), which results in any increase in \(N\) having a strong impact on the delay introduced by the circuit. As mentioned, Figure 3 shows the typical receiving chain of an ultra-low-power system excluding the final digitizing element. This is useful to estimate the overall chain sensitivity [12]. The following analysis is carried out assuming the matching condition to be met. First, the input power is \(P_{RF,ant}=V_{RF,ant}^{2}/2R_{S}\), where \(R_{S}=50\)\(\Omega\) is the resistance of the source. This implies the voltage amplitude virtually needed within the generator before \(R_{S}\) is \(V_{AV}=2V_{RF,ant}\). The peak-to-peak signal at the output of the matching network is then \(V_{RF}=A_{v}\)\(V_{RF,ant}\), with \(A_{v}\) being the matching network gain. Since it is the most practical  
Figure 3: The typical WuRX chain excluding the final digitizing element, as in [12]. implementation for the matching network, a commercial component simple LC network such as the one shown in Figure 2 shall be considered in the following, yielding [12]  
\[A_{v}=\sqrt{\frac{R_{in}}{R_{S}}}/\sqrt{\left(1+\frac{\omega R_{in}C_{in}}{Q_{ind }}\right)}, \tag{5}\]  
where \(Q_{ind}\) is the Q factor of the matching network inductance. Necessary conditions for high \(A_{v}\) are low \(C_{in}\) and high \(Q_{ind}\) at the target RF carrier frequency. The peak-to-peak signal at the output of the ED is \(V_{ED}=\left(NA_{v}^{2}p_{RF,ant}2R_{S}\right)/\left(4 nV_{T}\right)\) from (3).