## 3 Case Study and Simulation
### Clock Adjustment  
Once the clock error has been extracted, the next step is clock adjustment. In this simulation, the sub frame has an overlay of 0.2 s and the clock adjustment time period is 1 s, which implies that each control signal is predicted by 5 sets of previous data. The PLL parameters of the clock adjustment loop are described in Table 4. The bandwidth Bl of the control loop is 0.5 Hz.  
For both two scenarios, the slave clock has the same on-board VC-OCXO. The free running characteristic of this particular clock is shown in Figure 10, it is obtained with \(a_{0}=1\times 10^{-8}\) s, \(a_{1}=1\times 10^{-12}\) s/s and \(a_{2}=1\times 10^{-17}\) s/s\({}^{2}\) and the free run clock 3 shown in Table 3 is employed.  
Figure 10: _Cont._  
Figure 9: Decoupling clock error of Beidou A2 before (up) and after (down) motion compensation.  
Figure 10a shows the Allan deviations of the simulated slave clock in three different situations: free running and steered by the master clock in the GRACE and Beidou G1 & A2 scenarios. Compared with the free running clock, the Allan deviation reduces by orders of magnitude when the clock is steered. In addition, the Allan deviations of GRACE 1 and Beidou A2 are nearly the same, which proves that the dynamic error can be practically eliminated in both cases. To better express the performance of the proposed system, the simulated clock error of both scenarios are shown in Figure 10b, from which it can be seen that the synchronization loop stabilizes in less than 25 s, even in the event that the on-board clock is drifting. In order to evaluate the stability of the synchronization loop, statistics relating to the synchronization error data \(\epsilon_{n}\) from the first hour to the 24 th h have been determined for an arbitrary number of initial conditions. These statistics include the bias \(\Delta\hat{\mathbf{x}}\!=\!E\!\left[\epsilon_{n}\right]\), the variance \(\sigma_{\epsilon}^{2}\!=\!E\!\left[\left(\epsilon_{n}-\Delta\hat{\mathbf{x}} \right)^{2}\right]\) root-mean-square deviation (RMSD), \(\sigma_{\epsilon}\!=\!\sqrt{\sigma_{\epsilon}^{2}}\), and root-mean-square error (RMSE) \(\epsilon_{n_{\text{RMS}}}\!=\!\sqrt{E\!\left[\epsilon_{n}^{2}\right]}\!=\!\sqrt{ \Delta\hat{\mathbf{x}}^{2}\!+\!\sigma_{\epsilon}^{2}}\). The results from these simulations are shown in Table 5.  
We can therefore infer that the dynamic error and the clock error are effectively eliminated and that the system could meet the requirement of various scenarios with different relative velocities and orbit planes.  
Figure 10: **(a)** Allan deviations of the simulated free running on-board VC-OCXO, and its Allan deviation in the provided scenarios when the synchronization loop stabilizes; **(b)** Time synchronization performance of GRACE 1 and Beidou A2.  
\begin{table}
\begin{tabular}{c c c} \hline \hline \multirow{2}{*}{**Synchronization Error (Picosecond)**} & \multicolumn{2}{c}{**Scenarios**} \\ \cline{2-3}  & **GRACE** & **Beidou A2 \& G1** \\ \hline Bias & 0.280 & 0.280 \\ RMSD & 40.816 & 40.818 \\ RMSE & 40.817 & 40.819 \\ Max error & 20.86 & 20.87 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Synchronization errors of the GRACE mission and Beidou A2 & G1.