## 1 Introduction  
Nowadays, the alteration of power from DC to AC is an important process and performs a vital task in modern power system network and industrial processes powered by electric drives [1]. DC to AC conversion is carried out by power electronics converters. Due to high harmonic losses in two-level inverters, multilevel inverters are used in order to have highly efficient power electronics and drive systems [2]. The main property of the Multilevel Inverter (MLI) is to generate an output voltage waveform resembling a staircase using several voltage sources at the input, which results in the low value of total harmonics distortion (THD) and minimal values of electromagnetic interference (EMI) and voltage stress across switches [3]. The three classical topologies of MLI are Cascaded H-bridge inverter (CHB), Flying Capacitor Clamped inverter (FC), and Neutral Point Clamped inverter (NPC) [4]. Due to easy control and unique characteristics, they are practically implemented as alteration technology in various applications ranging from small- to large-scale industries. In order to achieve higher voltage levels, a large number of devices are required, which enhances the size and cost of MLIs [5]. At higher voltage levels, NPC and FC show capacitor voltage unbalancing problems besides the requirement for a significant number of clamping diodes and capacitors, respectively [6]. Cascaded H-bridge is the most feasible and flexible among the conventional topologies, utilizing less components, but the requirement of high DC power supply is a shortcoming, which makes MLI bulky and costly. Further, the classical topologies also do not have the ability to boost the output voltage [7]. Many symmetric topologies with less switches have been presented by the authors of [8; 9; 10; 11; 12] to overcome the problem of large switch requirements. However, as voltage levels increase considerably, DC power supplies, power semiconductor devices, gate driver circuits, and capacitors required in the topology increases. To overcome this drawback, reduced device count asymmetric topologies are used, which have DC power supplies of different magnitudes. In [13; 14; 15; 16; 17; 18; 19; 20], various reduced device count asymmetric topologies have been presented. Both reduced device count symmetric as well as asymmetric topologies presented in [8; 9; 20] suffer from a self-voltage boosting inability and the capacitor voltage unbalancing problem due to which these topologies are not suitable for low-input DC voltage source applications. Some auxiliary circuits such as impedance network or forehead-type boost converter are used along with MLI to achieve a self-voltage boosting capability [21]. To overcome the problem of capacitor voltage unbalancing, a complex control algorithm was proposed in [22; 23]. However, the cost, size, and complexity in the control mechanism are enhanced. To overcome MLI's shortcomings, a Switched-capacitor Multilevel Inverter (SCMLI) has recently been proposed by various researchers. SCMLIs require fewer switches and driver circuits compared to other existing topologies, and they need less DC power supplies because capacitors act as alternate DC sources. The idea of SCMLIs was first proposed by [PERSON] and [PERSON] in 1998 [24]. In [25], an integrated switched-capacitor MLI topology with a voltage string was presented, which needed a low number of switches, but it suffered from high voltage stress across the backend switch H-Bridge. To overcome this problem, the author of [26] presented an improved integrated switched-capacitor MLI topology. The author of [27] proposed an SCMLI topology using a series-parallel conversion, and it can be extended to generate a high number of voltage levels. However, it requires a significant number of components at high voltage levels. A novel stepup SCMLI topology developed by the author of [28] includes a switched capacitor DC/DC converter (SCC) and a full-bridge. SCC and full-bridge are used as a level generator and polarity generator, respectively.