# 185-215 GHz CMOS Frequency Doubler with a Single Row Staggered Distribution Layout Design
## 2 Circuit Design
### 220 GHz Frequency Doubler  
As shown in Figure 1, the frequency doubler is a balanced structure that was constructed using NMOS transistors. Due to the nonlinearity of the NMOS transistors, the signal input from the DA into the NMOS transistor excited the high-order harmonics. The output matching network was used to extract the second harmonics among the high-order harmonics, achieving the frequency doubling function. In the design of the frequency doubler layout, the transistor consists of a single-row of staggered distribution. As shown in Figure 6, the single row interleaving distribution meant that the policies of two transistors were interleaved, and the diffusion contact used as the ground or output port was placed between two policies. These diffusion contacts were reused by both transistors. As can be seen from Figure 6, this design had two advantages over the regular two-line design. First, the length of the metal connection line between the ground and output ports was effectively reduced, which effectively reduced the parasitic components. Second, the area of the layout became more compact because the number of diffusion contacts was  
Figure 4: (**a**) Schematic and (**b**) Diagram of the final stage of the DA. Figure 5: Simulated output power of the DA when input power was \(-10\) dBm. halved. The above discussion shows that the single-row interleaving distribution design can achieve more efficient parasitic parameters and a greater compact layout. The output power of a frequency doubler with a single-row interleaved Poly-Diffusion Contact balancing structure and a conventional structure at 220 GHz was simulated with different input power levels and different bias voltages. In the simulations, considering the absence of the transistor model in the cadence virtuoso with the structure, as shown in Figure 6b, the parallel connections of multiple single-gate ideal transistors were used equivalent to the single-row interleaving distribution structures. The simulated results of the power contours for different bias voltages are compared in Figure 7. According to Figure 7, the output power of a frequency doubler with the single-row interleaved Poly-Diffusion Contact balancing structure was able to reach a maximum of 7.8 dBm with a drive power of 11.5 dBm and a gate bias voltage V\({}_{\text{gs}}\) of 0 V, while the output power of a frequency doubler with a conventional structure could only reach a maximum of 6.8 dBm with a drive power of 11 dBm and a gate bias voltage V\({}_{\text{gs}}\) of 0 V.  
Figure 8 illustrates the simulated output power versus the input power at 220 GHz with a bias voltage of 0 V for two frequency doublers with different structures. As can be seen from Figure 8, the frequency doubler with a single-row interleaved Poly-Diffusion Contact balancing structure can obtain a higher output power than the doubler with a conventional two-line structure when the power of the input doubler exceeds 7 dBm. In addition, the peak output power of the frequency doubler with a single-row interleaved Poly-Diffusion Contact balancing structure was 1 dB higher than that of the frequency doubler with a conventional two-line structure. In short, when the DA provided sufficient power, the frequency doubler with a single-row interleaved Poly-Diffusion Contact balancing structure could obtain higher output power than the frequency doubler with a conventional two-line structure. The difference in the peak output power between the two kinds of frequency doublers exceeded 1 dB. This comparison demonstrates that the presented structure can effectively reduce the parasitic components and achieve higher output power. Figure 6: Schematic diagram of frequency doubler transistor design. (**a**) Regular two-line design; (**b**) Single-row interleaving distribution design.