## 3 Time Domain Analysis of the CM Voltage Source  
From what presented so far, the source of CM emission in a half-bridge is the voltage across the low-side power switch (\(v_{\mathrm{SW}}\)), as it causes a CM current to flow in the parasitic capacitance \(C_{\mathrm{p,sw}}\) and a CM voltage \(v_{\mathrm{CM}}\) on the EMI receiver, eventually. Before introducing the source inductance and its effect on \(v_{\mathrm{sw}}\), it is convenient to introduce a detail description of the phenomena taking place during the high-side transistor turn-on. Such analysis allows one to identify the resonant circuit excited during the turn-on transient, more precisely, the circuit shown in Figure 4a is considered. The high-side transistor is driven by a conventional gate driver (CGD) comprising of an ideal square wave voltage generator (\(v_{\mathrm{DRV}}\)) and the gate resistance (\(R_{\mathrm{g}}\)), and it is complemented by the low-side transistor (\(T_{\mathrm{LS}}\)). The power inductor (\(L_{\mathrm{pow}}\)) is modeled by the current sink \(I_{\mathrm{LOAD}}\), since the current flowing in \(L_{\mathrm{pow}}\) is subjected to much slower variations with respect to the \(dI/dt\) taking place during the transition [19]. In addition, the active devices, the parasitic inductance \(L_{\mathrm{d}}\), which includes both the package interconnections and the PCB traces, is considered, as well as the parasitic capacitance \(C_{\mathrm{s}}\) between sw and LG, which is due to the PCB layout. Referring to the corresponding switching waveforms shown in Figure 4b, the \(v_{\mathrm{DRV}}\) positive edge triggers the \(T_{\mathrm{HS}}\) turn-on, and after the gate source voltage (\(v_{\mathrm{GS}}\)) overcomes its threshold voltage, a positive current (\(i_{\mathrm{sw}}\)) flows in \(T_{\mathrm{HS}}\), resulting in a linear decrease in the drain-source voltage (\(v_{\mathrm{DS}}\)). To avoid a cross-conduction current to flow in \(T_{\mathrm{HS}}\) and \(T_{\mathrm{LS}}\), the low-side transistor is assumed to be already turned-off when the positive edge of \(v_{\mathrm{DRV}}\) occurs, meaning that only its body diode should be considered in what follows. Figure 4: (a) Simplified model of a single leg for the analysis of the turn-on when the high-side transistor is driven by a convention gate driver and (b) the corresponding switching waveforms. Figure 3: Equivalent circuit for the analysis of the CM electro-magnetic interference (EMI) in a half-bridge. The source voltage corresponds to the switching voltage \(v_{\mathrm{sw}}\), the coupling is due to the parasitic capacitance \(C_{\mathrm{p,sw}}\) and the receiver is modeled by the LISNs equivalent impedance. When the current \(i_{\text{aw}}\) reaches the value \(I_{\text{LOAD}}\), the low-side body diode turns-off and the voltage \(v_{\text{sw}}\) increases, eventually. In this phase, the \(T_{\text{LS}}\) diode can be modeled through its junction capacitance \(C_{\text{j}}\), which is in parallel to the parasitic capacitance of the PCB layout (\(C_{\text{s}}\)) since it is reverse biased, resulting in a series LC resonator with the inductance \(L_{\text{d}}\). More precisely, the voltage across the \(C_{\text{s}},C_{\text{j}}\) capacitances, i.e., \(v_{\text{sw}}\), must be charged to \(V_{\text{PS}}\). Such a voltage step may excite the resonator, and result in oscillations affecting both the switching voltage (\(v_{\text{sw}}\)) and the switching current (\(i_{\text{sw}}\)) at the \(f_{\text{r,on}}\) frequency, which is equal to  
\[f_{\text{r,on}}=\frac{1}{2\pi\sqrt{L_{\text{d}}(C_{\text{j}}+C_{\text{s}})}}. \tag{3}\]  
The damping factor characterizing the resonator \(C_{\text{j}}+C_{\text{s}},L_{\text{d}}\) depends on the resistive components, more precisely on the parasitic resistance of the interconnections, which is typically negligible, and the on-resistance of \(T_{\text{HS}}\), provided that it is in triode when the oscillation takes place.