# Low-Cost Three-Quadrant Single Solar Cell _I-V_ Tracer
## 2 Methods and Materials
### Device Implementation  
**Time of the process and capacitance calculation. **  
The time spent in the charge transfer between \(C_{1}\) and \(C_{2}\) depends on the current flowing from the first to the second, as well as their capacitances. Of course, the higher the capacitances of both capacitors, the higher the time. The current depends on the technology fabrication of the PV cell and its efficiency, especially, on its surface area. For silicon technology (mono or polycrystalline) cells of common sizes today (around 160 by 160 mm), \(I_{\text{SC}}\) goes from 7 to 12 A, more or less (however, larger sizes are coming in future years). Current (\(I\)) is related to charge (\(Q\)) and time (\(t\)) by its definition, and the voltage across the capacitors (\(V\)) is obtained by dividing the charge stored (\(Q\)) over the capacitance (\(C\)), assuming a constant current process, as shown (2):  
\[I=\frac{Q}{t},\ V=\frac{Q}{C},\ t=\frac{C\cdot V}{I} \tag{2}\]  
In fact, the current in a general case is not strictly constant, especially if the avalanche zone is also traced, but this calculation can provide us with the order of magnitude of the  
Figure 5: Step 6 of the process of the measurements. (**a**) Equivalent circuit. (**b**) Path on the \(I\)-\(V\) curve. processing time for some chosen capacitances and voltages at the source. For a more precise estimation of the real-time, we simulate the circuit in LTSpice with the one-diode model for the DUT (see Figure 6), for the first voltage sweep. As an example, for the circuit simulated in Figure 6, with an initial \(V(C_{1})\) = 15 V, \(V(C_{2})\) = 0 V, \(I(\text{DUT})_{\text{SC}}\) = 10 A and \(C_{1}\) = \(C_{2}\) = 10,000 \(\mu\)F (with reasonable values for the diode characteristics, the parallel resistance, and the series resistance), the current flow and voltages at capacitors are shown in Figure 7. This simulation corresponds to the first voltage sweep described in Section 2.2. The second quadrant curve is traced from the starting point to the time where \(C_{1}\) and \(C_{2}\) voltage traces overlaps; that is, \(V(\text{DUT})\) = 0 V, and then the usual \(I\)-\(V\) curve of the PV device (first quadrant) is traced until the end of the sweep. We can appreciate better in Figure 8 how effectively the final voltages of both capacitors are not equal, but the difference is the \(V_{\text{OC}}\) of the measured cell. The total sweep time in this example is around 9.4 ms, and the capacitor voltage trace overlap occurs at 7.4 ms, so the usual \(I\)-\(V\) curve in the first quadrant is travelled in about 2 ms.  
For our prototype, we chose capacitors with capacitances of 22,000 \(\mu\)F rated up to 40 V. This added to the use of PV cells with \(I_{\text{SC}}\) = 7.5 A and gave us more than double the amount of time to perform the measurements. Figure 6: Circuit simulated in LTSpice for estimating the necessary capacitance for \(C_{1}\) and \(C_{2}\). Figure 7: Time simulation for the discharge of \(C_{1}\) and the charge of \(C_{2}\) across the DUT. Current flow (red line), voltage of \(C_{1}\) (blue line), and voltage of \(C_{2}\) (green line) over time. If we simulate in LTSpice the second voltage sweep (step 6 of the process, see Figure 9), we also obtain a time of around 2 ms (see Figure 10), but as shown in the figure, this implies currents of hundreds of amperes that will destroy the current sensor, so, to limit the reverse current for this measurement, an external resistor must be placed in series with the circuit. A shunt diode conducted in the forward current direction of the current avoids this series resistance for first sweep measurements. The effect of adding a resistor of 0.3 \(\Omega\) is shown in Figure 11, where more moderate currents occur and the time spans 20 ms.  
**Prototype design. **  
For switch implementations, we selected metal oxide semiconductor field-effect transistor (MOSFET) devices controlled by a microcontroller (MCU) programmed adequately.