## 5 Implementation Results
The theoretical critical path delays associated with the function module (FM) are expressed by (45) and (46) with respect to RTZ and RTO handshaking. The theoretical cycle times of the QDI TMR circuits incorporating Singh_MV, DIMS_MV, Toms_MV and SL_MV are expressed by Equations (47) to (50) with respect to RTZ handshaking, and Equations (51) to (54) with respect to RTO handshaking. In the equations, the typical propagation delays of a two-input C-element, a four-input OR gate, a \begin{table}
\begin{tabular}{c c c c c} \hline
**QDI TMR** & **Forward Latency** & **Cycle Time (ns)** & **Area (\(\mu\)m\({}^{2}\))** & **Power (\(\mu\)W)** \\
**Implementation and** & **(ns)** & **Cycle Time (ns)** & **Area (\(\mu\)m\({}^{2}\))** & **Power (\(\mu\)W)** \\ \hline \multicolumn{5}{c}{RTZ Handshaking} \\ \hline QDI TMR with & 1.16 & 2.32 & 267.61 & 232.8 \\ [PERSON]\_MV & & & & \\ QDI TMR with & 0.89 & 1.78 & 259.99 & 219.6 \\ [PERSON]\_MV & & & & \\ QDI TMR with SL\_MV & 0.94 & 1.88 & 252.87 & 219.3 \\ QDI TMR with SL\_MV & 0.97 & 1.94 & 240.67 & 236.3 \\ \hline \multicolumn{5}{c}{RTO Handshaking} \\ \hline QDI TMR with & 1.13 & 2.26 & 267.61 & 233.3 \\ [PERSON]\_MV & & & & \\ QDI TMR with & 0.86 & 1.72 & 255.92 & 217.7 \\ QDI TMR with & & & & \\ [PERSON]\_MV & 0.94 & 1.88 & 252.87 & 220.1 \\ QDI TMR with SL\_MV & 0.96 & 1.92 & 240.67 & 237.0 \\ \hline \end{tabular}
\end{table} 
Table 2: Design metrics of quasi delay insensitive triple modular redundant circuits corresponding to RTZ and RTO handshaking, estimated using a 32/28 nm CMOS technology. Figure 13: Screenshot of a portion of the simulation waveforms of a QDI TMR circuit comprising SL_MV, corresponding to RTO handshaking. four-input AND gate, a two-input OR gate, a two-input AND gate, an AO22 complex gate, and an OA22 complex gate are denoted by TCE2, TOR4, TAND4, TOR2, TAND2, TAO22 and TOA22 respectively. Treg denotes the typical propagation delay of an input register, which is the same as TCE2. Equations (45) to (54) are rather approximate since the propagation delays of gates are alone accounted for and the interconnect delays have been neglected for simplicity. \[\mathrm{T}_{\mathrm{FM}}^{\mathrm{RTZ}}=(\mathrm{T}_{\mathrm{AO22}}+\mathrm{ T}_{\mathrm{CE2}}+\mathrm{T}_{\mathrm{OR2}}) \tag{45}\]  
\[\mathrm{T}_{\mathrm{FM}}^{\mathrm{RTO}}=(\mathrm{T}_{\mathrm{OA22}}+\mathrm{ T}_{\mathrm{CE2}}+\mathrm{T}_{\mathrm{AND2}}) \tag{46}\]  
\[\mathrm{T}_{\mathrm{Singh\_MV}}^{\mathrm{TMR\_RTZ}}=2\Big{(}\mathrm{T}_{ \mathrm{reg}}+\mathrm{T}_{\mathrm{FM}}^{\mathrm{RTZ}}+3\mathrm{T}_{\mathrm{CE2 }}+2\mathrm{T}_{\mathrm{OR3}}+\mathrm{T}_{\mathrm{OR2}}\Big{)} \tag{47}\]  
\[\mathrm{T}_{\mathrm{DMS\_MV}}^{\mathrm{TMR\_RTZ}}=2\Big{(}\mathrm{T}_{ \mathrm{reg}}+\mathrm{T}_{\mathrm{FM}}^{\mathrm{RTZ}}+2\mathrm{T}_{\mathrm{CE2 }}+\mathrm{T}_{\mathrm{OR4}}\Big{)} \tag{48}\]  
\[\mathrm{T}_{\mathrm{T}_{\mathrm{DMS\_MV}}^{\mathrm{TMR\_RTZ}}}^{\mathrm{TMR\_ RTZ}}=2\Big{(}\mathrm{T}_{\mathrm{reg}}+\mathrm{T}_{\mathrm{FM}}^{\mathrm{RTZ}}+2 \mathrm{T}_{\mathrm{CE2}}+3\mathrm{T}_{\mathrm{OR2}}\Big{)} \tag{49}\]  
\[\mathrm{T}_{\mathrm{SL\_MV}}^{\mathrm{TMR\_RTZ}}=2\Big{(}\mathrm{T}_{ \mathrm{reg}}+\mathrm{T}_{\mathrm{FM}}^{\mathrm{RTZ}}+\mathrm{T}_{\mathrm{OR2 }}+3\mathrm{T}_{\mathrm{CE2}}\Big{)} \tag{50}\]  
\[\mathrm{T}_{\mathrm{Singh\_MV}}^{\mathrm{TMR\_RTO}}=2\Big{(}\mathrm{T}_{ \mathrm{reg}}+\mathrm{T}_{\mathrm{FM}}^{\mathrm{RTO}}+3\mathrm{T}_{\mathrm{CE2 }}+2\mathrm{T}_{\mathrm{AND3}}+\mathrm{T}_{\mathrm{AND2}}\Big{)} \tag{51}\]  
\[\mathrm{T}_{\mathrm{DMS\_MV}}^{\mathrm{TMR\_RTO}}=2\Big{(}\mathrm{T}_{ \mathrm{reg}}+\mathrm{T}_{\mathrm{FM}}^{\mathrm{RTO}}+2\mathrm{T}_{\mathrm{CE2 }}+\mathrm{T}_{\mathrm{AND4}}\Big{)} \tag{52}\]  
Figure 13:0  
Figure 13:1  
From the above equations, it may be observed that the critical path traversed in the TMR circuit incorporating Singh_MV encounters an input register, a function module, three two-input C-elements, two three-input OR/AND gates and one two-input OR/AND gate.