# Design Considerations of Multi-Phase Buck DC-DC Converter
## 3 Design Considerations of Multi-Phase Buck DC-DC Converters
Figure 3: Multi-phase synchronous buck converter efficiency \(\eta\) vs. output current \(I_{0}\): (**a**) Duty cycle D = 0.133, \(f_{SW}\) = 200 kHz; (**b**) duty cycle D = 0.133, \(f_{SW}\) = 300 kHz. (**c**) duty cycle D = 0.275, \(f_{SW}\) = 200 kHz; (**d**) duty cycle D = 0.275, \(f_{SW}\) = 300 kHz; (**e**) duty cycle D = 0.417, \(f_{SW}\) = 200 kHz; (**f**) duty cycle D = 0.417, \(f_{SW}\) = 300 kHz. These results indicate that when selecting the optimal number of phases, a comprehensive approach should be taken to assess the advantages that will be achieved by increasing the number of stages in a multi-phase buck configuration. Furthermore, the optimal phase number should be evaluated over the entire duty cycle range. Moreover, Figure 4 shows the 3D plots of (23) as a function of duty cycle D and switching frequency \(f_{SW}\) - \(\eta\) (\(D,f_{SW}\)), %. Figure 4a shows the performance \(\eta\) at the following input data: \(I_{0}\) = 200 A, \(N\) = 8,\(f_{SW}\) = 75 kHz \(\div\) 300 kHz, dead time td = 100 ns, and Figure 4b at \(N\) = 12. Here, the output voltage _Uout_ is assumed to be fixed at 1.6 V, and the input voltage is varied, resulting in a duty cycle D changing from 0.1 to 0.9. At N = 12, the efficiency of the circuit, over the whole range of the changes in duty cycle D, was higher by approximately 0.92 \(\div\) 1.37% compared to that at \(N\) = 8. \begin{table}
\begin{tabular}{c c c c c|c c c} \hline  & \multicolumn{3}{c|}{\(\eta\), \%, \(f_{SW}\) = 200 kHz} & \multicolumn{3}{c}{\(\eta\), \%, \(f_{SW}\) = 300 kHz} \\ \hline  & \(N\) = 4 & \(N\) = 6 & \(N\) = 8 & \(N\) = 12 & \(N\) = 4 & \(N\) = 6 & \(N\) = 8 & \(N\) = 12 \\ \hline \(I_{0}\) = 45 A & 90.44 & 90.77 & 90.77 & 90.4 & 87.14 & 87.25 & 87.03 & 86.29 \\ \(I_{0}\) = 100 A & 88.41 & 89.73 & 90.31 & 90.74 & 85.48 & 86.61 & 87.07 & 87.27 \\ \(I_{0}\) = 150 A & 86.43 & 88.45 & 89.43 & 90.31 & 83.68 & 85.51 & 86.37 & 87.07 \\ \(I_{0}\) = 200 A & 84.48 & 87.13 & 88.47 & 89.74 & 81.88 & 84.32 & 85.53 & 86.62 \\ \hline \end{tabular}
\end{table} 
Table 4: Multi-phase buck converter efficiency \(\eta\) - \(\mathit{Uin}\) = 12 V, \(\mathit{Uout}\) = 1.6 V.  
Figure 4: Multi-phase synchronous buck converter efficiency \(\eta\) (\(D,f_{SW}\)). (a) _Uout_ = 1.6 V, \(I_{0}\) = 200 A; \(N\) = 8; \(f_{SW}\) = 75 kHz \(\div\) 300 kHz; D = 0.1 \(\div\) 0.9; (b) _Uout_ = 1.6 V, \(I_{0}\) = 200 A; \(N\) = 12; \(f_{SW}\) = 75 kHz \(\div\) 300 kHz; D = 0.1 \(\div\) 0.9. \begin{table}
\begin{tabular}{c c c c c|c c c} \hline  & \multicolumn{3}{c|}{\(\eta\), \%, \(f_{SW}\) = 200 kHz} & \multicolumn{3}{c}{\(\eta\), \%, \(f_{SW}\) = 300 kHz} \\ \hline  & \(N\) = 4 & \(N\) = 6 & \(N\) = 8 & \(N\) = 12 & \(N\) = 4 & \(N\) = 6 & \(N\) = 8 & \(N\) = 12 \\ \hline \(I_{0}\) = 45 A & 95.23 & 95.43 & 95.46 & 95.34 & 93.44 & 93.52 & 93.49 & 93.1 \\ \(I_{0}\) = 100 A & 94.14 & 94.83 & 95.15 & 95.40 & 92.5 & 93.13 & 93.38 & 93.52 \\ \(I_{0}\) = 150 A & 93.06 & 94.13 & 94.66 & 95.15 & 91.49 & 92.49 & 92.98 & 93.38 \\ \(I_{0}\) = 200 A & 91.99 & 93.41 & 94.14 & 94.83 & 90.47 & 91.82 & 92.50 & 93.12 \\ \hline \end{tabular}
\end{table} 
Table 5: Multi-phase buck converter efficiency \(\eta\) - \(\mathit{Uin}\) = 12 V, \(\mathit{Uout}\) = 3.3 V.  
Based on the results presented in Figures 3 and 4, it is recommended to select the buck stages as outlined in Table 6, with a focus on optimizing circuit efficiency and minimizing ripple currents. Additionally, the cost-effectiveness of the schematic should be taken into account when choosing larger \(N\)-stage circuits.