# Multiple-Parallel Morphological Anti-Aliasing Algorithm Implemented in FPGA
## 1 Introduction
The first step is to upscale the low-resolution texture to the target resolution by adaptive upsampling, and the second step is to perform adaptive sharpening to further strengthen the edge information. Although this technique can be used for all pipelines, and the consumption of the hardware is very low when implemented, this technique has many flaws in the presentation of the final image--for example, some pixel-level details will be lost. In addition, the Subpixel Reconstruction Anti-Aliasing (SRAA) technique and the Temporal Anti-Aliasing (TAA) technique are also suitable for deferred 3D rendering pipelines, but unlike FXAA and MLAA, these techniques are placed before the post-processing of the image. SRAA is a technique that uses subpixel normals and the location information of sampling points to refine the shading results and present images with a better quality [35]. Similar to MSAA, SRAA only requires the fragment shader to progress once on each pixel of a 3D primitive; however, this technique requires more information--such as the depth and normals about the sampling points of each pixel--than MSAA to refine the pixel color. TAA is a technique that allocates the amount of calculation to different frames to realize temporal anti-aliasing [36, 37, 38, 39]. It performs a weighted calculation of the color of the current frame and the historical frame through reprojection and rectification of the history frame, which improves the continuity of colors between frames and eliminates ghosting and other phenomena that may appear between frames. However, this technique requires a large number of storage resources to store the colors of the historical frame when it is implemented, and when the historical frame is rectified, it will involve a large amount of time and power. Deep Learning Super Sampling (DLSS) has also been proposed [40, 41]. DLSS is a technique that combines deep learning and anti-aliasing; it contains two steps: one is the training phase and the other is the processing phase, both of which use the same model. In the training phase, the model needs to be trained and optimized with a large number of original images and corresponding supercomputer antialised images. After the training, the model is sent to the user, and on the user's side, the processing phase begins. In the processing phase, low-resolution images are first generated and then handed over to the model to process high-resolution images. No matter how the parameters of this model are changed, it only needs to support 60 frames per second to obtain an anti-aliasing performance close to the supercomputer. This technique can achieve a similar anti-aliasing performance to SSAA without the occupation of the image processing resources, but the training and optimization of the model will increase the complexity of the implementation of this technique. Among the techniques above, although techniques such as MSAA and EQAA can achieve very good anti-aliasing performance, they require a high hardware complexity and power consumption during implementation, so they can only be used in the GPU of the PC. For the GPU in mobile embedded devices, we need to use low-power anti-aliasing techniques suitable for deferred 3D rendering pipelines, such as FXAA and MLAA [20]. However, the anti-aliasing performance improved by these techniques is very poor. Other techniques, such as DLSS, require very complex training and optimization of the image processing model before implementation, which increases the difficulty of technical implementation. To further improve the anti-aliasing performance achieved by the GPU of mobile embedded devices, we propose a multiple-parallel morphological anti-aliasing algorithm and implemented it in FPGA. The algorithm achieves better anti-aliasing performance and reduces the consumption of storage resources by scaling the area texture, which stores the color blending coefficients between pixels. In addition, the algorithm also reduces the time cost of the algorithm by setting more hardware parallelism. This paper is organized as follows.