# A Tile-Based Multi-Core Hardware Architecture for Lossless Image Compression and Decompression
## 5 Conclusions  
In conclusion, this study presents a novel high-throughput, lossless image compression and decompression system designed to meet the growing demands of modern data-intensive applications. By integrating a hybrid compression strategy that incorporates run-length coding, predictive coding, and a non-coding mechanism, the proposed system optimally compresses various image components. Implementing the algorithm on an FPGA-based platform allows for parallel processing and efficient resource utilization, significantly improving throughput. The system's tile-based approach, coupled with a multi-core architecture, further enhances its parallel processing capabilities. Additionally, the use of a five-stage pipeline in the compression process and three dynamic state machines in the decompression process ensures high clock frequencies and overall performance efficiency. This solution demonstrates clear advantages over existing methods, making it a robust and scalable option for real-time image processing tasks where high throughput and lossless quality are essential.  
The system is implemented on Xilinx Zynq platform. As it is not purely a PL-side design, participation from the PS side is required. On other platforms, the PL-side code can be migrated by updating the IP cores. However, migrating the PS-side code is more challenging. This is due to differences in the connection methods and communication protocols between PS and PL components across platforms. These variations increase the complexity of cross-platform migration. Migration is feasible within the Zynq family, for example, the design can be ported to the ZCU104 UltraScale+ platform. In ASIC implementations, the PS must be replaced with a soft-core processor, which also adds to the migration difficulty.  
In the future, further acceleration of the decompression process will be pursued. Pipelining techniques will be applied to the decompression algorithm, and the pipeline structure of the compression algorithm will also be optimized. A deeper pipeline with additional stages will be adopted to increase both operating frequency and throughput. The method will also be considered for deployment in radiation-prone environments, such as satellite systems and medical applications, where tile-based compression can enhance radiation resistance.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Name** & **System** & **Compression Module** & **Decompression Module** \\ \hline Slice LUTs & 88754 & 21147 & 20268 \\ Block RAM & 310.5 & 226.5 & 50.5 \\ Bonded IOPADS & 130 & 0 & 0 \\ BUFGCTRL & 4 & 0 & 0 \\ MMCME2\_ADV & 2 & 0 & 0 \\ Slice Registers & 85156 & 5035 & 3974 \\ F7 Muxes & 1718 & 314 & 264 \\ F8 Muxes & 225 & 72 & 95 \\ Slice & 29850 & 8437 & 7422 \\ LUT as Logic & 84069 & 20995 & 19848 \\ LUT as Memory & 4685 & 152 & 420 \\ \hline \hline \end{tabular}
\end{table}
Table 4: Resource utilization.  
**Author Contributions:** Methodology, X.L.; software, X.L.; validation, X.L. and L.Z.; formal analysis, X.L.; investigation, X.L. and L.Z.; resources, X.L. and Y.Z.; data curation, X.L.; writing--original draft preparation, X.L.; writing--review and editing, L.Z.; supervision, Y.Z.; project administration, X.L. All authors have read and agreed to the published version of the manuscript.  
**Funding:** This research was funded by the Key Program of the Chinese Academy of Sciences, grant number E16505B31S. The APC was funded by the same source.  
**Institutional Review Board Statement:** Not applicable.  
**Informed Consent Statement:** Not applicable.  
**Data Availability Statement:** The raw data supporting the conclusions of this article will be made available by the authors on request.  
**Conflicts of Interest:** The authors declare no conflicts of interest.