# A Scalable Bidimensional Randomization Scheme for TLC 3D NAND Flash Memories
## 2 Background
### Randomizers Based on LFSRs  
The principal solutions adopted for data randomization utilize a \(k\)-bit ALFSR (Autonomous Linear Feedback Shift Register), as shown in Figure 2. Feedback functions exist for any \(k\) value [18], guaranteeing that, once initialized in any state but \"all zeros\", the register evolves through all the \(2^{k}-1\) states before returning to the initial state. The initial state is generally denoted as the register _Seed_. If the sequence generated by the ALFSR--for instance, that collected at exit \(Y_{k-1}\)--is sufficiently long, pseudorandom characteristics are guaranteed: the probability of having bits equal to 0 is 0.5, that of having any 2-bit sequence (00, 01, 10, 11) is 0.25, that of having any 3-bit sequence (000, 001, \(\cdots\), 111) is 0.125 and so on. Besides these important statistical properties, for the problem at hand it must be observed that the maximum number of consecutive zeros is equal to \(k-1\), whereas the maximum number of ones is equal to \(k\). The former statement derives from the fact that \(k\) consecutive zeros correspond to the \"all zeros\" register state, which does not belong to the state diagram (otherwise the register would remain in that state because of the absence of any input). The latter derives from the fact that, when \(k\) consecutive bits equal to one are encountered, the ALFSR is in the \"all one\" state and, consequently, the next state must be 0111 \(\cdots\) 111 (otherwise the ALFSR would remain in the same state, contradicting its  
Figure 1: (**a**) The TLC 3D NAND Flash architecture. Reprinted with permission from [9] under Creative Commons License 4.0 (CC-BY). (**b**) Sequence of operations during program operation considering on-chip randomization. (**c**) Sequence of operations during read operation considering on-chip randomization. (**d**) Sequence of operations during program operation considering off-chip randomization. (**e**) Sequence of operations during read operation considering off-chip randomization. cycling properties). The sequences of \(k-1\) zeros and those of \(k\) ones occur just once in an entire \(2^{k}-1\) bit sequence. Two possible schemes adopted to randomize the data to be stored in a memory page are shown in Figure 3. In the former, at any clock cycle \(c\), input data \(d(c)\) is XORed with the content of the last register bit \(Y_{k-1}(c)\); in the latter, the ALFSR is cycled for \(k\) clock cycles, then all the register content \(Y_{0}(c+k)\), \(\cdots\), \(Y_{k-1}(c+k)\) is XORed with \(k\) input data (\(d(c)\), \(\cdots\), \(d(c+k)\)) and this procedure is repeated until all page data are randomized. If the same Seed in considered, the two schemes are fully equivalent in terms of randomization since, for the same data input sequence, they produce the same data sequence to be stored in the memory page. A 3D NAND Flash memory block is constituted by \(N_{p}\) pages featuring \(N_{B}\) cells each. \(N_{B}\) is in the range of 4 kB \(\div\) 16 kB (corresponding to \(2^{15}\div 2^{17}\) cells) whereas \(N_{P}\) is in the range of 256 \(\div\) 1024 (i.e., \(2^{8}\div 2^{10}\)). The typical ALFSR length adopted in the randomizing schemes is \(k=32\), so that a sequence of \(N_{L}=2^{32}-1\) can be generated by the register before returning to its initial state. Since \(N_{B}\ll N_{L}\), it is clear that the statistical properties of the ALFSR are not fully exploited. A 32-bit ALFSR is generally considered a good player in data randomization. Figure 3: Possible schemes used to randomize data in a memory page. (**a**) at any clock cycle \(c\), the input data \(d(c)\) is XORed with the last register bit \(Y_{k-1}(c)\); (**b**) \(k\) clock pulses are applied to the register, then the register content is XORed with \(k\) input data and the procedure is repeated until all page data are randomized. Figure 2: Schematic representation of an ALFSR. It is realized by \(k\) D-flip-flop (FF\({}_{0}\div\) FF\({}_{k-1}\)) and a feedback path where some XOR \(C_{i}\) may be present.