## 3 System Design
### High Sensitivity GNSS Receiver Architecture
The chosen OCXO was an ECOC-2522 by ECS [33], operating at 40 MHz, with a frequency stability of \(\pm\)10 ppb. Figure 3 illustrates the architecture of the FPGA. The FPGA incorporates the above mentioned sample conditioning and buffering, as well as the high-sensitivity acquisition and tracking multicorrelator hardware accelerators. Additionally, it features an interface to the processing system (PS/PL interface). The sample conditioning and buffering incorporates dynamic bit selection in each frequency band. This process dynamically selects the most significant bits from the incoming signal samples, mapping their dynamic range to the sample quantization in the hardware accelerators. The hardware accelerators are implemented in the form of reusable Intellectual Property (IP) cores, which can be targeted at many variants of FPGAs. The PS/PL interface uses the Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI4) protocol specification [34]. Figure 2: High-sensitivity GNSS receiver block diagram. The incoming GNSS signal is captured by the A/D converters and then transferred to the FPGA buffers. These buffers feed the various hardware accelerators for real-time processing. The receiver comprises one high-sensitivity acquisition FPGA IP core and 48 tracking multicorrelator FPGA IP cores, distributed as follows: 12 tracking IP cores for GPS L1 C/A, 12 for Galileo E1b/c, 12 for GPS L5, and 12 for Galileo E5a. This configuration enables the receiver to process GPS L1 C/A, Galileo E1b/c, GPS L5, and Galileo E5a signals in any combination of GNSS signals and up to 12 channels per signal--allowing for a maximum of 48 channels in a dual-frequency E1/L1 and L5/E5a setup. The input of the acquisition hardware accelerator is preceded by a downsampling filter in the L1/E1 band. In this way, the receiver adjusts its sampling frequency downward for capturing GNSS signals in the E1/L1 frequency band, and, subsequently, it switches to a higher sampling frequency for tracking these signals. This configuration is in accordance with the fact that the signal detection is not significantly benefited from operating within a  
Figure 3: Detailed FPGA design. bandwidth exceeding that necessary to capture the main lobe of the received signals, which is approximately 2 MHz for GPS L1 C/A signals and 4 MHz for Galileo E1b/c signals, due to the increased noise in the captured signal [35]. A Direct Memory Access (DMA) in the FPGA can be employed for processing recorded signals. Alternatively, the DMA can be used to capture snapshots of the received signals and transmit them to an external device via the PS and the LAN. To integrate the high-sensitivity capabilities, significant modifications were made to the SoC-FPGA receiver architecture presented in [21]. These modifications included the implementation of a new acquisition hardware accelerator in the FPGA and modifications to the GNSS-SDR software receiver. The new acquisition hardware accelerator is designed to perform extended CI, enabling the detection of weak signals in real-time. It is named the 'high-sensitivity acquisition hardware accelerator' because it enables the receiver to acquire signals in both standard and high-sensitivity modes, unlike the standard acquisition hardware accelerator presented in [21], which can only operate in normal sensitivity mode. The high-sensitivity acquisition hardware accelerator necessitates temporary storage of received signal samples to compute the CI. To facilitate this, the acquisition is directly connected to a Double Data Rate 4 (DDR4) memory controller implemented in the FPGA. The memory controller, in turn, is connected to an DDR4 memory component on the ZCU102 board, which is located outside the SoC FPGA, but directly accessible by the FPGA itself. This memory component is called 'PL memory' because it is directly connected to the Programmable Logic (the FPGA).