## 3 Technology Modules
### High-Density Spacer Gate Patterning  
To fabricate the gate structure for quantum dot tuning and qubit manipulation, electron beam lithography in combination with metal lift-off gates have been widely used [13; 60; 61]. To achieve small gate pitches and high-density gate structures, multiple layers have to be aligned and electrically insulated [17; 18]. Depending on the used material combination, strong variations in gate size and uncontrolled oxidation of the metal gates can lead to additional variations in the final gate structure [62]. Furthermore, multiple gate layers lead to differences in the controllability of the chemical potential depending on the applied voltages due to the different gate dielectric thicknesses above the silicon surface. In this work, we aim at a high-density gate array in a single layer using a self-aligned spacer process in combination with a damascene process. The fabrication scheme for the used spacer process is shown in Figure 5a. The layer-stack includes an Al\({}_{2}\)O\({}_{3}\) etch stop layer (green), a sacrificial amorphous silicon (\(\alpha\)Si) layer (dark grey), and a SiO\({}_{2}\) hard mask (blue). Electron beam lithography (EBL) is initially used to pattern the gate structure (60-nm lines with 120-nm pitch) in the resist (red) with a 30-kV RAITH eLine system. The structured resist is transferred into the sacrificial layer using a highly-anisotropic SF\({}_{6}\)/O\({}_{2}\) reactive ion etching process at a temperature of \(-130\,^{\circ}\)C in an Oxford Instrument PlasmaPro 100 Cobra etching system. Then, SiO\({}_{2}\) is conformally deposited by a high-pressure SiH\({}_{4}\)/O\({}_{2}\) CVD process at a temperature of 350\(\,^{\circ}\)C in an Oxford Instruments Plasmalab System 100. Finally, we etch the gate structure by a second SF\({}_{6}\)/O\({}_{2}\) dry-etching process developed for a high SiO\({}_{2}\)/\(\alpha\)Si etch rate selectivity. The deposited SiO\({}_{2}\) on the sidewall of the transferred structure withstand the back-etch, while the sacrificial layer is fully removed. The remaining SiO\({}_{2}\) sidewalls (from now on referred to as spacers) provide the electric insulation of the metallic gate array. Similar to the fabrication of the side-gates as discussed above, subsequently over-depositing these spacers with TiN by atomic layer deposition (ALD) followed by a TiN/SiO\({}_{2}\) selective damascene process using chemical mechanical polishing yields insulated gates within one single layer. This step has to be done in the future. Fabricated SiO\({}_{2}\) spacers of 15 nm in width with a (75 \(\pm\) 5) nm pitch are shown as cross-section and top-view images taken with scanning electron microscopy (SEM) in Figure 5b. The spacer height is measured with 45 nm limited by the second anisotropic dry-etching process. Smaller feature sizes have been achieved by downscaling the initial gate structure and decreasing the conformally-deposited SiO\({}_{2}\) layer thickness. A top-view image of fabricated SiO\({}_{2}\) spacers of 10 nm in width with a 50-nm pitch taken with SEM is shown in Figure 5c. Due to the reduced feature size, SEM leads to significant charging effects and deformations of the fabricated SiO\({}_{2}\), prohibiting cross-section images. Therefore, we cannot provide a cross-section image of these smaller SiO\({}_{2}\) spacers. Electrical contacts are schematically added for clarity including ohmic contacts to the silicon nano-ridge indicated by crossed squares. The final gate structure is used for top-ridge localization, as discussed above. The final size and pitch of these SiO\({}_{2}\) spacer depend predominantly on the initial resolution of the electron beam lithography. By downscaling the gate structure, a target gate width of 30 nm with a pitch of 45 nm can be achieved. Especially, the high density gate structure within a single layer results in a sensitive control of the electrostatic potential within the silicon ridge. This allows the possibility to compensate disorder sources as discussed above.