## 4 Results and Discussion of SPDT SW2
Figure 12a shows the measured and simulated power gain \(\rm S_{12}\) against the \(\rm P_{in}\) characteristics of SPDT SW2 at 28 GHz in the TX mode. That is, DTMOS-R \(\rm M_{1}\) and \(\rm M_{2}\) are in the off-state and \(\rm M_{3}\) is in the on-state. SPDT SW2 achieves a measured \(\rm S_{12}\) of \(-\)1.05 dB at a low \(\rm P_{in}\) of 0 dBm and an \(\rm S_{12}\) of \(-\)2.05 dB at a high \(\rm P_{in}\) of 24.6 dBm. The corresponding \(\rm P_{1 dB}\) is 24.6 dBm. This result is consistent with the simulated one, i.e., an \(\rm S_{12}\) of \(-\)0.81 dB at a low \(\rm P_{in}\) of 0 dBm and an \(\rm S_{12}\) of \(-\)1.81 dB at a high \(\rm P_{in}\) of 24.3 dBm, corresponding to a simulated \(\rm P_{1 dB}\) of 24.3 dBm. The decent \(\rm P_{1 dB}\) performance of SPDT SW2 in the TX mode is mainly attributed to the novel SPDT switch topology and the adoption of DTMOS-R switch transistors. This can be explained in more detail as follows. In contrast to the traditional CS switch transistors using a \(\rm V_{sw1}\)/\(\rm V_{sw2}\) of \(\rm 0/V_{DD}\) and a body voltage of 0 V, DTMOS-R \(\rm M_{1}\) and \(\rm M_{2}\) achieve a better off-state due to higher off-state channel/substrate resistance (\(\rm R_{off,ch}\)/\(\rm R_{off,sub}\)) because of a higher \(\rm V_{th}\), a lower overdrive voltage \(\rm V_{ov}\), and the suppression of \(\rm I_{B}\). Moreover, DTMOS-R \(\rm M_{3}\) achieves a better on-state due to lower on-state channel/substrate resistance (\(\rm R_{on,ch}\)/\(\rm R_{on,sub}\)) because of a lower \(\rm V_{th}\) and a higher over-drive voltage \(\rm V_{ov}\). In other words, a higher \(\rm P_{in}\) is required to conduct the off-state shunt/series \(\rm M_{1}\)/\(\rm M_{2}\). This leads to a high \(\rm P_{1 dB}\) in the TX mode. Moreover, the high \(\rm P_{1 dB}\) of 24.6 dBm is partly due to the prominent (TX-to-RX) isolation of 59.2 dB (see Figure 11a). Figure 12b shows the measured power gain \(\rm S_{31}\) against the \(\rm P_{in}\) characteristics of SPDT SW2 at 28 GHz in the RX mode. That is, DTMOS-R \(\rm M_{1}\) and \(\rm M_{2}\) (controlled by \(\rm V_{sw1}\)) are in the on-state, and \(\rm M_{3}\) (controlled by \(\rm V_{sw2}\)) is in the off-state. The measured result is consistent with the simulated one. SPDT SW2 achieves a measured \(\rm S_{31}\) of \(-\)2.48 dB at a low \(\rm P_{in}\) of 0 dBm, and \(-\)3.48 dB at a high \(\rm P_{in}\) of 20.2 dBm. The corresponding \(\rm P_{1 dB}\) is 20.2 dBm. This decent \(\rm P_{1 dB}\) performance of the SPDT switch in the RX mode is also attributed to the novel SPDT switch topology and the adoption of DTMOS-R switch transistors. A figure-of-merit (FOM) suitable for the evaluation of a wideband, low-IL, high-linearity, and decent-isolation SPDT switch can be defined as follows. \[FOM[GHz\cdot mW]=\frac{BW[GHz]\cdot Isolation[1]\cdot P_{1 dB}[mW]}{IL[1]} \tag{12}\]  
in which IL [1] is the insertion loss in magnitude, BW[GHz] is the bandwidth in GHz, Isolation [1] is the isolation in magnitude, and \(\rm P_{1 dB}\) is the input 1 dB compression point in mW. Table 1 is a summary of SPDT SW1 and SW2, and recently reported state-of-the-art SPDT switches with similar operation frequency using similar CMOS technologies. The operation bandwidth (BW) is a function of the specification of the maximum allowed IL (IL\({}_{\rm max}\)). As shown, SPDT SW1 achieves BW values of 13.3 and 21.1 GHz for IL\({}_{\rm max}\) of 2.1 and 2.5 dB, respectively. SPDT SW2 achieves a BW of 22.3 GHz for IL\({}_{\rm max}\) 2.5 dB. For the same IL\({}_{\rm max}\) of 2.5 dB, for a fair comparison, SPDT SW1 achieves a BW of 21.1 GHz, close to  
Figure 12: Measured and simulated \(\rm P_{1 dB}\) of SPDT SW2 in (**a**) the TX mode and (**b**) the RX mode. that (22.3 GHz) of SPDT SW2. Overall, SPDT SW1 occupies a medium area, and achieves decent reflection coefficients, IL, isolation, bandwidth, and P1 dB, and excellent FOM in the RX mode and the best FOM in the TX mode.