## 2 Sensor Structure and Measurement Principle
### Absolute Measurement Principle  
The double-row capacitive structure of the VATG sensor is illustrated in Figure 2a, where stationary excitation electrodes serve as the stator, and moveable induction electrodes serve as the mover. Here, the stator consists of two-row stationary excitation electrodes, and each row occupies an equivalent overall length of L. In the same way, the mover consists of two-row corresponding inductive electrodes, and each row occupies an equivalent length of L/12. Meanwhile, a multilayer thin-film sensing structure is employed, where the electrodes and the lead wires are separated by a thin-film insulating layer, and the electrodes and lead wires are connected by a connecting column. Figure 1: Schematic diagrams of a single-row capacitive displacement sensing structure and its measurement principle. Top view (**a**) and side view (**b**) schematic diagrams of the single-row sensing structure. (**c**) Schematic diagram presents a geometric representation of the effective area variation of the selected region in (**a**). (**d**) Equivalent capacitor circuit based on (**b**). As shown in Figure 2b, the VATG sensor includes two single-row capacitive sensing structures denoted as row 1 and row 2 with different periodicities of \(W_{row1}\) and \(W_{row2}\), respectively. Because the value of \(I\) is equivalent for both rows, the widths of the excitation electrodes in row 1 and row 2 are \((W_{row1}/4-I)\) and \((W_{row2}/4-I)\), respectively. In addition, \(L/W_{row1}\) and \(L/W_{row2}\) are both integers, and \(L/W_{row1}-L/W_{row2}=1\). According to (5), the corresponding output voltage signals \(U_{row1}\) and \(U_{row2}\) of row 1 and row 2 can be given as  
\[U_{row1}=\ A_{row1}\sin(\frac{2\pi}{T}t-\frac{2\pi x}{W_{row1}}),\ U_{row2}=\ A_{row2}\sin(\frac{2\pi}{T}t-\frac{2\pi x }{W_{row2}}), \tag{6}\]  
where \(A_{row1}\) and \(A_{row2}\) are coupling coefficients of row 1 and row 2, respectively. We then define a reference signal \(U_{ref}\) with an equivalent frequency as \(U_{row1}\) and \(U_{row2}\). Accordingly, we can define the time difference \(\Delta t_{row1}\) along the time axis as representing the phase difference between \(U_{row1}\) and \(U_{ref}\) and the time difference \(\Delta t\) as representing the phase difference between \(U_{row1}\) and \(U_{row2}\)[25]. As shown in Figure 2b, \(U_{row1}\), \(U_{row2}\), and \(U_{ref}\) are routed to a shaping circuit to convert them into square wave signals. The respective rising edges of the square wave signals, which are collectively denoted as \(P_{s}\) for convenience, are then routed to a phase-comparing circuit constructed using a field-programmable gate array (FPGA). High-frequency clock pulses \(P_{t}\) with a period \(T_{p}\) are also input into the phase-comparing circuit as the time standard to interpolate \(\Delta t_{row1}\) and \(\Delta t\). The interpolation process is illustrated in Figure 2c, where the rising edge of the converted \(U_{ref}\) initiates the counting of pulses \(P_{f}\) until the rising edge of the converted \(U_{row1}\) is encountered. Then, pulses \(P_{c}\) are counted until the next rising edge  
Figure 2: (**a**) Schematic diagram of a double-row Vernier-type capacitive structure for conducting absolute position measurements with time-grating. (**b**) Schematic diagram illustrating the absolute position measurement principle of double-row capacitive structure. (**c**) High-frequency clock pulse interpolation. of the converted \(U_{r\!\!f}\) is encountered after a total period \(T\). Accordingly, if \(n\) pulses \(P_{f}\) are counted, \(\Delta t_{row1}=nT_{p}\) to realize the fine measurement of row 1, and, if \(m\) pulses \(P_{c}\) are counted, \(\Delta t=mT_{p}\) to realize the coarse measurement of row 2.