## 1 Introduction  
For industrial applications, reliability and power density are two important considerations in the design process of power converters. Modern power converters with increased power density require efficient and intelligent thermal design and management [1; 2] to ensure the reliability of the systems. Accordingly, there is an ongoing need to build thermal models to help thermal analysis and power converter optimization. The forth-order Foster [3; 4] and Cauer networks [5; 6] are being widely used to describe the thermal response of junction-to-case for power components. Based on the Cauer network, the one-dimensional thermal network can be extended to one or two orders of case-to-heatsink as shown in Figure 1[7] for thermal analysis. The network is fast to calculate the junction temperatures (\(T_{j}\)) of power components. While this kind of model just focuses on the self-resistances, it cannot calculate the thermal coupling. In a compact IGBT (insulated-gate bipolar transistor) module, multiple IGBT chips and diodes are packaged as shown in Figure 2a. \(T_{j}\) of the Si-chips can be affected thermally by the neighboring chips placed on the same substrate. Based on the multi-chip structure of an IGBT module, the networks built in [8; 9] consider the conduction thermal coupling resistance (\(R_{cdcp}\)) generated by neighboring Si-chips. The model in Figure 2b can be used to calculate the \(T_{j}\) of power devices and the method is more accurate than the ones that do not consider the effect of thermal coupling among the surrounding chips. While this kind of thermal model just focuses on a single module, it ignores the coupling between modules in a system. FEM simulations [10] can be used to describe the thermal distribution of components or converter systems and the junction and case temperatures can be extracted by adding virtual thermal probes to active and passive power components. The thermal coupling matrix in [11] is extracted by FEM simulation with a given power to heat up the chip. In this study \(R_{cdcp}\) is dependent on the geometric positions of the chips in a LED module. This thermal matrix is used for \(T_{j}\) estimation. Heat flow in Figure 3 shows the \(R_{cdcp}\) that is generated among several structure layers and the model in [12] compares the temperatures at the same position in the vertical direction of each layer and computes the thermal resistances among them. However, to build more accurate FEM models, familiarity with complex geometric structures, appropriate meshing methods, and boundary conditions are essential [13]. This model focuses on the coupling between different layers in a single module and it does not consider the coupling between neighboring modules. Figure 1: One-dimensional thermal network. Figure 3: The \(R_{cdcp}\) among layers in an IGBT module. Figure 2: Multiple Si-chips power module: (**a**) an opened commercial module; and (**b**) \(R_{cdcp}\) via the same baseplate. [PERSON] et al. built a thermal model which considers the \(R_{cdcp}\) between the components in a power converter based on the surface or case temperatures (\(T_{c}\)) mapping in [14]. The \(R_{cdcp}\) in the red color in Figure 4 are generated by connected copper traces in the PCB and these resistances are dependent on the location of the components. Their locations can be optimized based on the temperature's mapping network and a power converter is optimized in [15]. The advantage of this model is that it considers the components in the overall system. While this model just focuses on the conduction coupling, it ignores the convection coupling effect. Higher power and smaller size are required for high-power density converters [16; 17], which make the process of thermal dissipation more difficult. Moreover, power devices are exposed in power converters and part of the heat that is released in the narrow space by the way of convection and thermal convection is environmentally dependent.