# Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA
## 5 EEG IP Core  
The objective of creating the EEG IP core is to perform the classification of EEG signals in hardware, without intervention from the CPU. The KNN classifier comprises three main tasks. The first one is the Canberra distance computation, the second one is sorting the computed distances, and the third one is the translation of the shortest distances into a predicted emotion. The candidate tasks to be integrated into a hardware specification are the calculation of distances between test and training instances and the retrieval of the K shortest values. The assessment of the emotion class does not execute significant processing tasks, and thus it may be assured by software-only instructions. This section addresses \begin{table}
\begin{tabular}{c l} \hline \hline
**Design Iteration** & **Description** \\ \hline
0 & software-only \\
1 & dot-product \\
2 & array dot-product \\
3 & data access optimization \\
4 & internal cache \\
5 & linear regression, mean square and Pearson correlation functions \\
6 & DC subtraction routine \\
7 & DC mean computation task \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Main improvement added on each design iteration. the implementation of the module that receives instances of feature sets to output the K nearest ones. The approach to tackle the problem is to design two independent IP cores implementing each task. This design concept implies that an output channel of the first core is connected to an input channel of the second core. The block diagram of the core, EEG_CALCDIST, is depicted in Figure 6. The module that computes distances is simplified by a green box named _Canberra_. The diagram allows to visualize the data flowing from the incoming stream channel down to the output port. In the hardware perspective, 8 _Canberra_ blocks are instantiated so that partial distances can be computed in parallel and added to an accumulator. In more detail, the _Canberra_ boxes implement the logic written in Figure 7. It consists of the computation of a partial distance between two features. In other words, given two arrays, \(x\) and \(y\), a partial result is the distance between \(x_{i}\) and \(y_{i}\), regarding a specific arrays' dimension \(i\). To obtain a Canberra distance, this box must iterate over two complete test and training arrays. Then, the final result is the sum of all terms. Figure 6: Block diagram of calculate distances core. input: featureTest, featureTraining output: partialDistance begin num $$gets$ $$$featureTest - featureTraining $$$den$$featureTest + featureTraining ifden$-Figure 6.0Figure 6.1 0 else partialDistanceFigure 6.2gets$num/den end return partialDistance end ```  
**Figure 7**. Pseudo-code of _Canberra_ block. The second module of the EEG IP core is the EEG_SORTDIST, designed to sort the outcome of EEG_CALCDIST. A possible method to sort distances is to pass the input values through all memory elements, comparing the distances to the stored values. The idea is to, at each memory address (cell), update or hold the stored value, depending on its comparison to the received value. If the received distance is less than the distance stored at a given cell, the cell is updated. Before being overwritten, the stored value is passed to the next cell. Otherwise, the stored value is held, and the input value is propagated to the next cell, where the logic repeats. This iterative procedure can be seen as a chain, or an array, transferring values between adjacent cells, or elements. This logic guarantees that, for each received distance, a precise number of instructions is executed to complete an iteration of the insertion sort. The design diagram of sort distances core is depicted in Figure 6.3  
This provides a graphical view of the datapath that implements the insertion sort of _distances_ and _indexes_.