# The Challenges of Advanced CMOS Process from 2D to 3D
## 5 The Etching Challenges and Solution of 3D
### Gate Process  
The replacement metal gate (RMG) was introduced by using poly-Si as dummy gate and SiO\({}_{2}\) as dummy gate oxide [131] where eventually these layers are removed with wet process by means of none metal alkaine solutions, as shown in Figure 19[132; 133; 134]. One of benefits of RMG is to avoid crystallization of the high-\(k\) dielectric during the rapid thermal annealing (RTA) process for dopants activation [135]. The other important benefit is the chemical reaction between the metal gate and  
Figure 17: A schematic of STI process of Si fins with (**a**) Si fins formation; (**b**) STI oxide filled in; (**c**) STI oxide recess and (**d**) channel stop and well implants. Reproduced with permission from [129]. Copyright Springer, 2008.  
Figure 18: STI footing by wet etching with (**a**) an oxide foot at the bottom edge and (**b**) footing is reduced and recess control is improved due to digital nature of the etching. Reproduced with permission from [130]. Copyright Solid-State Electronics, 2012.  
the high-_k_ in RTA processes is also avoided otherwise the boron diffusion into high-_k_ is inevitable. As an example, the boron diffusion for HfO\({}_{2}\) is significant higher than SiO\({}_{2}\)[135; 136].  
Compared to the 2D devices, the RMG for 3D structures are even more complicated as shown for vertically stacked nanowire process in Figure 20. Firstly, poly-Si dummy gate has to be completely removed without any residues in narrow and steep trenches [132; 133; 134], otherwise, due to chemical nature of the HF-based wet etchant for the dummy gate oxide etching could not remove the poly-Si without any oxidizer [137; 138; 139]. Therefore, the residues occupy the space where the high-_k_ and metal gates should be filled in, which might cause device failure. Besides this problem, a careful selective etching process is required to create dangling structures, for example in the vertically stacked nanowires [130]. In general, the wet processes use aqueous solutions which are using water as the solvent, and the final rinses are using deionized water (DIW) or ultra-pure water (UPW) to clean away the chemicals from wafer surfaces. However, it is well known that some defects can be generated due to the surface tension of water. Normally, during the drying process, the high capillary force of water could pull nearby structures to form permanent defects so called pattern collapse [140] or stiction [141] in terms of micro electro-mechanical systems (MEMS) field. To avoid such defects, gas phase etching (GPE) was carefully studied in the latest decades. In gas phase, the intermolecular force is not too strong compared to the liquid phase, then there is no worry about any pattern collapse. Besides that, the diffusivities in gases are \(10^{4}\) time greater than in a liquid. The commonly used GPE is a HF vapor process. Recently, GAA transistors have been manufactured by using HCl vapor process as well [130; 131; 132; 133; 134; 135; 136; 137; 138; 139; 140; 141; 142].  
As mentioned before, the devices from 2D to 3D also introduced \"new materials\". In many advanced vertical transistor structures, multilayer of SiGe/Si is implemented. Since it is needed to selectively etch either Si or SiGe layers, a lot of efforts were made to use HF:H\({}_{2}\)O\({}_{2}\):CH\({}_{3}\)COOH mixtures to etch SiGe selectively to Si [143; 144; 145] or to use tetramethylammonium hydroxide (TMAH) based to remove Si from SiGe [146] and a formulated semi-aqueous reagent to selectively etch SiGe to Ge [147].  
Among new materials for nano-scaled transistors have 2D crystals e.g., graphene, black phosphorous, molybdenum disulfide etc. have also delivered exciting results. The main problem for integration of 2D crystal is lack of a reliable synthesis technique for mass production.  
Figure 19: Planar transistors with high-_k_ metal gate processes, including replacement metal gate (RMG) modules. (Reprinted with permission from [3]. Copyright Japan Society of Applied Physics, 2011).