# Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
## 2 Proposed SRAM Structure and Operation Principles
### MAC Operation
The body voltage effect in MOSFET transistors refers to the influence that the voltage differential between the transistor's source and body terminals has on the transistor's threshold voltage (_Vth_). This adjustment to the threshold voltage improves the robustness of the bit-cell operation during computation. The dependency of the threshold voltage (_Vth_) on the source-body voltage (_Vsb_) can be quantitatively described by the following equation:  
\[V_{th}=V_{th0}+r\Big{(}\sqrt{V_{sb}+2\phi_{F}}-\sqrt{2\phi_{F}}\Big{)} \tag{1}\]  
where \(V_{th0}\) represents the threshold voltage when \(V_{sb}=0,r\) is the body effect coefficient and \(\phi_{F}\) is the Fermi potential of the semiconductor. This relationship illustrates how an increase in \(V_{sb}\) raises \(V_{th}\), effectively enhancing stability during MAC operations by controlling transistor switching behavior. This phenomenon is particularly useful for optimizing the performance of low-power circuits, such as those used in memory arrays performing computational tasks. As shown in Figure 5a, when a lower voltage is applied to the body terminal of the NMOS transistor than to its source terminal, the threshold voltage increases. This effect directly impacts the switching characteristics of the transistor, thereby influencing the overall performance of the bit-cell during MAC operations. Figure 5b further confirms this body effect through experimental results, which demonstrate that the threshold voltage increases as the body voltage is reduced relative to the source voltage, as indicated by the red curve. In Figure 6a, we observe the voltage differences across R2 in a column of bit-cells when the body voltage of transistor P3 is set to VDD (1 V) and the body voltage of transistor N5 is set to VSS (0 V). This configuration reveals a relatively narrow voltage distribution range, as well as a non-uniform voltage distribution across the bit-cells. These non-uniformities are undesirable, as they lead to inaccuracies in the accumulation phase of the MAC operation and hinder the overall computational stability of the memory array. To address these limitations, we applied an alternative body biasing scheme to enhance the stability and  
Figure 4: Bit-cell internal multiplication output process. accuracy of the MAC operations. Specifically, we applied VSS (0 V) as the body voltage for the PMOS transistor P3 and VDD (1 V) as the body voltage for the NMOS transistor N5. This body biasing configuration has the effect of lowering the threshold voltages of both transistors, thereby improving their switching speeds and reducing the overall power consumption of the bit-cell during MAC operations. To further manage the power efficiency, the body voltages of P3 and N5 are controlled by a static body control circuit, which dynamically adjusts the voltages in response to the operational state of the bit-cell. As demonstrated in Figure 6b, this adjustment led to an expansion of the dynamic range of the voltage differences across R2, increasing the range from 400 mV to 600 mV. Additionally, the voltage differences became more distinguishable, which significantly improved the accuracy of the calculations performed within the bit-cell. This enhanced performance, particularly in terms of voltage stability and expanded dynamic range, is highly beneficial in applications that require precise computations, such as neural network operations and other complex mathematical tasks. This expanded differential also reduces the need for high-performance ADCs by allowing effective binary multiplication and accumulation directly within the SRAM array, thus enhancing computational efficiency and lowering power requirements. By leveraging the body voltage effect and optimizing the transistor threshold voltages, the proposed architecture achieves a balance between low  
Figure 5: (a) Body voltage effect and (b) threshold voltage variation. Figure 6: (a) Voltage difference before body voltage effect and (b) after body voltage effect.