## 5 Results and Discussion  
### Comparison of Multiplier Structures  
In this section, we conduct a comprehensive comparison between the recommended SISO systolic multiplier layout and previously published rival constructions, which include bit-serial systolic and non-systolic multiplier designs [8; 9; 10; 13; 24; 26; 38]. The evaluation encompasses several crucial factors, such as total gate counts, latency, and critical path delay (CPD), providing valuable insights into the performance and efficiency of each architecture. The results of this comparison, presented in Table 1, offer a clear understanding of the strengths and weaknesses associated with different approaches. Within the table, the symbols \(\Pi_{tri}\), \(\Pi_{A}\), \(\Pi_{X}\), and \(\Pi_{M}\) represent the latencies of specific logic components, including tri-state buffers, two-input AND gates, two-input XOR gates, and two-to-one MUXs, respectively. By thoroughly examining these metrics, designers and researchers can make well-informed decisions regarding the selection of the most suitable multiplier architecture. Before delving into the analysis of the area and delay complexity data presented in Table 1, it is worth noting an interesting observation. Among the compared multiplier layouts, the majority adhere to a systolic or semi-systolic design, whereas the multiplier constructions discussed in [9; 38] stand out as non-systolic architectures. It is worth noting that the architectures proposed in [9; 38] are built upon two different types of irreducible polynomials: trinomials and \(\phi\)-nomials, which are irreducible polynomials characterized by having \(\phi\) non-zero terms. Among these two types, trinomial-based solutions exhibit superior performance compared to \(\phi\)-nomial solutions. Therefore, for the purpose of comparison, we choose to focus on the trinomial-based multiplier construction and evaluate it against the recommended SISO systolic multiplier layout. The generated multiplier layout showcases several advantageous characteristics compared to existing multiplier structures. In terms of tri-state buffers, the presented multiplier construction requires only \(k\) tri-state buffers, whereas the Ibrahim multiplier structure [13] necessitates \(2k\) tri-state buffers, and all other multiplier layouts do not require any tri-state buffers at all. Also, it is worth highlighting that the recommended multiplier layout significantly reduces the number of latches compared to all other multiplier structures. In terms of gate counts, when compared to the Song multiplier [8], the proposed multiplier layout has similar numbers of AND and XOR gates but eliminates the need for the \(3k\) MUXes present in the Song multiplier. Similarly, when compared to the Fenn multiplier structure [24], the proposed layout has a lower count of AND gates but a higher count of XOR gates while having the lowest number of MUXes between the two designs. Compared to the multiplier structure proposed by [PERSON] [26], the proposed design exhibits nearly the same number of AND and XOR gates but significantly reduces the number of required MUXes. Although both the multiplier structures of Masoleh [9; 38] and the proposed layout have zero MUXes, the Masoleh structures feature a substantial number of AND and XOR gates, in contrast to the proposed design. Lastly, when compared to the Ibrahim multiplier structures [10; 13], the proposed layout demonstrates a similar count of AND and XOR gates while completely eliminating the need for the \(k\) MUXes required by [PERSON]'s designs. These comparisons highlight the favourable characteristics of the proposed multiplier layout, such as a lower latch count and competitive gate counts in relation to existing multiplier structures.