# Efficient QC-LDPC Encoder for 5G New Radio
## 5 Performance Analysis and Comparison
The computation of \(p_{a}\) requires \((g+2)\) clock cycles, in which \(g\) clock cycles are used to compute all the \(\lambda\) values and \(p_{a_{1}}\), and two extra clock cycles are required for estimation of the remaining parity bits in the \(p_{a}\) portion. The computation of \(p_{c}\) requires \((m_{b}-g)\) clock cycles. Hence, this method requires \((m_{b}+2)\) clock cycles in total. The information throughput reported in Table 7 is given by the formula  
\[Throughput=\frac{m_{b}\times Z\times f_{max}}{CPC}, \tag{35}\]  
where \(f_{max}\) is the maximum operating frequency (post synthesis). For different submatrix sizes, the throughput varied from 22.1-202.4 Gbps. In Table 7, the occupied areas are also reported. It should be noted that there is a significant increase in the core area when processing higher submatrix sizes. Since encoder architecture of a higher submatrix size \(Z\) requires a higher \(\bar{q}\) size, additional memory and hardware components are required. It is shown that the encoding complexity of the proposed design is linearly proportional to the submatrix size \(Z\) of the code. To keep the throughput comparison on equal basis, the throughput-to-area ratio metric was further defined as \begin{table}
\begin{tabular}{c c c c c} \hline \hline  & & **Gaussian** & **RU** & **Proposed** \\ \hline \multirow{4}{*}{Area} & Flip-flops & 352 & 416 & 416 \\ \cline{2-5}  & XOR gates & 258,336 & 764 & 464 \\ \cline{2-5}  & AND gates & 259,072 & – & – \\ \cline{2-5}  & Barrel shifter (\(Z\) bits) & – & – & 27 \\ \cline{2-5}  & Memory (bits) & ROM = 259,072 & ROM = 42,488 &
\begin{tabular}{c} ROM = 4720 \\ \(\lambda\)\(\_\)mem = 64 \\ \end{tabular} \\ \hline \multicolumn{2}{c}{Speed (clock cycles)} & 23 & 471 & 70 \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Comparison between Gaussian method, RU method, and proposed method for submatrix size \(Z=16\). \begin{table}
\begin{tabular}{c c c c c} \hline \hline  & & **Gaussian** & **RU** & **Proposed** \\ \hline \multirow{4}{*}{Area} & Flip-flops & \(k_{b}Z\) & \((k_{b}+g)Z\) & \((k_{b}+g)Z\) \\ \cline{2-5}  & XOR gates & \((k_{b}Z-1)m_{b}Z\) & \(2m_{b}+(m_{b}-g)Z\) & \((k_{b}+2g-1)Z\) \\ \cline{2-5}  & AND gates & \(k_{b}m_{b}Z^{2}\) & – & – \\ \cline{2-5}  & Barrel shifter (\(Z\) bits) & – & – & \(k_{b}+g+1\) \\ \cline{2-5}  & Memory (bits) & ROM = \(k_{b}m_{b}Z^{2}\) & ROM = \((245\pi+29y+274)Z\) & ROM = \(\bar{q}[m_{b}(k_{b}+g)-g^{2}]\) \\ \cline{2-5}  & & & & \(\lambda\)\(\_\)mem = \(gZ\) \\ \hline \multicolumn{2}{c}{Speed (clock cycles)} & \(k_{b}+1\) & \(28Z+k_{b}+1\) & \(n_{b}+2\) \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Comparison between Gaussian method, RU method, and proposed method. \(TAR=Throughput/Area\) (Gbps/mm\({}^{2}\)). For all the considered submatrix sizes in Table 7, the \(TAR\) ranged from 520-597 Gbps/mm\({}^{2}\). Based on the implementation results presented above, it is clear that the design methodology is applicable to different submatrix sizes and offers a significantly high area efficiency and high information throughput, which is more than enough to satisfy the throughput requirement for the 5G NR standard.