## 4 Evaluation Results and Discussion  
The proposed DC-GCDRAM shown in Figure 3 has been evaluated under different operating modes by extensive simulations using 45 nm CMOS technology. Basically, the designed computational DRAM consists of two 16-kbit memory arrays and the peripheral  
Figure 17: CMOS adder circuits: (**a**) 22T full adder (FA_22T); (**b**) 16T full adder (FA_16T); (**c**) 15T half-adder (HA_15T). Figure 18: Simulated waveforms for XAC operation; VDD = 1.0 V and T = 25 \({}^{\circ}\)C.  
circitiries like address buffers, predecoders, block signal generators, control buffers, control logic, refresh controller, oscillator, refresh address counter, and I/O buffers. The CIM macro contains two WWL boosters, 256 row decoders, 32 column decoders, 8 computing logics, 8 write drivers, and 2 population counters. In the memory mode, the data-in or data-out is 8 bits wide. In the logic-arithmetic mode, the macro outputs 8-bit wide logic computation results or produces 8-bit wide addition results with a single-bit carry-out. In the convolution mode, the CIM macro takes two 128-bit activations and generates two 8-bit counts as output. The operation cycle of each functional mode is self-timed from the positive clock (CLK) edge. In Figure 19, we have shown the maximum frequency and energy dissipation of the memory operation from 1.1 down to 0.8 V. The energy consumption here represents a whole energy wasted in bitlines, datalines, main datalines, wordlines, decoders, BL-SAs, BSAs, write drivers, WWL booster, predecoders, control logic, I/O buffers, and other peripheral circuits. The simulations are consistent with the predictions; reducing the supply voltage brings about longer delays and lower energy consumption. For the supply voltage of 1.0 V, the DC-GCDRAM functions at 241 MHz with write and read energy figures of 8.12 and 7.72 pJ/cycle, respectively. The write energy is 5.2% higher than the read energy because of the WWL boost. The operation of the logic-arithmetic mode is alike to the read operation in the memory mode, but the difference is that two RWLs are activated at the same time and two binary logic SAs are used in the logic-arithmetic mode. In Figure 20, we show the simulated frequency and energy consumption across the supply voltage for the logic (NOR/OR, NAND/AND, XNOR/XOR) and arithmetic (SUM, carry-out) operations between two words in two rows at room temperature. As V\({}_{\text{DD}}\) decreases, the energy dissipation and the frequency of both operations are reduced. The logic operation, in general, consumes higher energy than that dissipated by the memory read operation due to activations of two rows and two SAs. The latency of logic operation is about 5% longer than that of the memory read operation. Compared with the logic operation, the arithmetic operation has a slightly longer delay and slightly worse energy consumption because of a few additional logic gates. At V\({}_{\text{DD}}\) = 1.0 V, the maximum frequencies for the logic and arithmetic operation are 229 and 224 MHz, and the energy consumptions measure 8.09 and 8.19 pJ/cycle, respectively. Using the simulation results in this study, we compared CIM with conventional digital computing, which reads two words for two memory cycles and calculates them within ALUs, in Figure 21. For the arithmetic (FA) operation at 1.0 V supply, it is estimated that the proposed CIM architecture saves energy and latency by at least 47% and 46% compared with the conventional digital hardware. Figure 19: Maximum frequency and energy dissipation in the memory mode (T = 25 \({}^{\circ}\)C). We also evaluated the energy wasted by the binary XAC operation under a range of conditions. In the convolution mode, the total power or energy consumption of the DC-GCDRAM much depends on the bit-wise XNOR results. This is because the outputs of the XNOR-SAs are initially all tied to the ground. The CIM macro computes two independent 128-input XACs in one cycle.