# FPGA-Based Linear Detection Algorithm of an Underground Inspection Robot
## 4 Experimental Verification  
In order to prove the effectiveness of the construction algorithm, a noise-free hand-drawn image, as shown in Figure 18a, is used. The circle in the image is divided by line segments with an interval of \(\pi/8\). Figure 18b is the image edge detected by the Canny software operator, and Figure 18c is the processing result of the hardware algorithm constructed in the previous section [22]. The algorithm detects the edge while suppressing the edge pixels located in the LLA interval. Figure 18d,e are the line segments detected by the original LSD algorithm. Figure 18f,g are the processing results of the algorithm IP core constructed in this chapter. The pixel threshold of the algorithm in Figure 18d,f is set to 30; that is, the detected line segment contains at least 30 pixels. The pixel threshold of the algorithm in Figure 18e,g is set to 50; that is, the detected line segment contains at least 50 pixels. By comparison, it can be found that the original LSD algorithm has a higher  
Figure 16: Timing diagram of the heterogeneous convolution window. Figure 17: Timing diagram of key signals for area growth. detection rate for the line segment area in the circle, and the two have similar detection results for the line segment area inside the circle. In order to verify the stability of the construction algorithm, the top plan view of the belt conveyor operation collected by the IMX22 camera was used for testing. Figure 19a is the collected test image, Figure 19b is the converted gray image, and Figure 19c,d are the edge detection results before and after angle suppression, which is implemented by the hardware of the edge detection algorithm. Respectively, Figure 19e,\(f\) are the line segment information detected by the original LSD algorithm and the line segment information detected by the hardware algorithm IP core. Comparing both of them, the hardware algorithm constructed in this article has a good application effect in real images with noise. It can accurately detect line segment information with an edge direction angle from 45\({}^{\circ}\) to 135\({}^{\circ}\). However, due to the fixed-point number calculation method and pipelined processing architecture, relative to the original LSD algorithm, the detected line segment information has certain errors. Figure 19: Comparison of actual image processing results. (**a**) Test image; (**b**) Gray image; (**c**) Edge detection image before angle suppression; (**d**) Edge detection image after angle suppres-sion; (**e**) Line segment information by original LSD; (**f**) Line segment information by IP core. Figure 18: Comparison of processing effects of multi-angle line segments. (**a**) Noise-free hand-drawn image; (**b**) Divided image of \(\pi\)/8; (**c**) Processing picture of the hardware algorithm; (**d,e**) Pictures of line segments detected by the original LSD algorithm; (**f,g**) Processing pic-tures of the algorithm IP core. The line detection algorithm constructed in this paper is based on the XC7Z020-2 CLG484l FPGA platform [23], and it is analyzed, synthesized, placed, and routed through the Vivado synthesis tool. Table 1 shows the resource consumption of the constructed algorithm on the FPGA platform. A 100 MHz clock was used during the test, and the algorithm clock delay was analyzed after the synthesis was completed, as shown in Figure 20[24]. According to the analysis of this table, the calculation method of time latency (TL) and the frame rate N of the line segment detection IP core can be obtained, as shown in Equations (2) and (3). \[TL=7\text{W}+40 \tag{2}\]  
\[\text{N}=\frac{\text{C}-\text{TL}}{\text{H}\times\text{W}} \tag{3}\]  
In these two formulas, W and H, respectively, represent the width and height of the image, and C is the clock frequency of the module application.