# Design of Indoor Visible Light Communication PAM4 System
## 3 Key Component Design
### FPGA Overall Design  
The encoded PAM4 frame data needs to be converted into an analog signal by a digital-to-analog conversion (DAC) circuit, and then the PAM4 signal carrying the original data is processed by the LED driver circuit and sent out in the form of an optical signal through the LED lamp. After the optical signal sent by the LED is transmitted to the receiving end through the channel, the photoelectric receiving circuit first receives the optical signal and converts it into a voltage signal. At the same time, the signal is amplified and filtered. The processed signal is adjusted to the appropriate range by the automatic gain control (AGC) circuit to facilitate subsequent decoding. Then, the analog signal is  
Figure 5: The principle of the lead-lag synchronization method.  
Figure 6: The principle of detecting frame header by correlation method.  
converted into a digital signal by the analog-to-digital conversion (ADC) circuit, and then the FPGA development board performs synchronization and decoding operations to restore the source data. The design block diagram is shown in Figure 7, in which the data interface includes an asynchronous serial interface, a universal serial bus (USB) interface, and an audio interface. The FPGA development board integrates functions such as coding and modulation, demodulation and decoding, synchronization, DAC, and ADC.  
The software structure diagram of the sending end is shown in Figure 8. The local crystal oscillator generates the clock signal, sending the data through the data-sending module. After that, the serial data stream is converted to parallel data. The FIFO buffers the data first-in, first-out, and then encodes and modulates the data. At the same time, a control signal is the output to control the buffer for the next operation, and then a frame synchronization header is added to the encoded data, and finally, the data is sent out.  
The software structure diagram of the receiving end is shown in Figure 9. The received PAM4 signal needs to be restored by the synchronization module for bit synchronization clock signal and frame synchronization determination, and then the data is decoded. At the same time, it is converted into serial data through parallel serial conversion and received by the receiving module.  
The whole software design mainly includes four modules: the data sending and receiving module, encoding module, decoding module, and synchronization module. Each module is composed of a series of algorithm functions. The encoding module completes gray coding, 8b/10b coding, and PAM4 coding. The decoding module completes the corresponding decoding operation. The synchronization module includes a bit synchronization module and a frame synchronization module. The bit synchronization module extracts the clock synchronization signal from the received PAM4 signal through a phase-locked loop.  
Figure 8: The software structure diagram of the sending end.  
Figure 7: The design block diagram.  
Figure 9: The software structure diagram of the receiving end.  
The frame synchronization module uses a Barker code correlator to determine the starting position of the frame header of the PAM4 data frame.