## 1 Introduction  
With the development of complex semiconductors and communication technologies, the research and development of very large-scale integration (VLSI) designs have gradually emerged since the 1970s. With further process development, VLSI is mainly limited by area, speed, and power consumption [1]. Researchers have moved their focus from high-speed to low-power designs to improve portable system endurance, decrease heat dissipation issues, improve reliability, and decrease packaging complexity [2, 3, 4, 5]. The purpose of low-power design is to reduce power consumption while maintaining performance [6].  
The circuit power consumption is composed of static power consumption and dynamic power consumption. It is observed that in deep submicron technology, the leakage current contributes 50% of total power consumption [7]. Meanwhile, at the sub-threshold level, the leakage current influences static stability [8]. Therefore, reducing static power consumption is an essential part of low-power design. The sub-threshold leakage current is given by [9]  
\[\begin{cases}I_{takage}=I_{o}10^{(V_{gs}-V_{th})/S}\\ S=ln(10)V_{T}(1+\frac{C_{d}}{C_{ex}})\end{cases} \tag{1}\]  
where \(V_{gs}\) is the gate-to-source voltage, \(V_{th}\) is the threshold voltage, \(I_{o}\) is the drain current with \(V_{th}=V_{gs}\), \(C_{d}\) is the depletion layer capacitance, \(C_{ex}\) is the gate-oxide capacitance, \(V_{T}\) is the thermal voltage, and \(S\) is the subthreshold slope.  
Techniques such as multi-threshold CMOS (MTCMOS), transistor stacking [10], sleepy stack approach [11], sleepy keeper approach [12], and body bias technique [13] are used to minimize static power consumption. In these techniques, multi-threshold CMOS is very influential in reducing leakage currents [14; 15]. Low-threshold voltage (LVT) devices have low latency but high static power consumption, while high-threshold voltage (HVT) devices do the opposite. According to Equation (1), the static power consumption will increase exponentially when the threshold voltage decreases linearly. Thus, when a cell is swapped from LVT to HVT, the proportion of change in static power consumption is much more significant than the proportion of change in delay [16]. Therefore, multi-threshold CMOS technology aims to reduce the proportion of LVT cells as much as possible. It means only using LVT cells on critical paths to meet the timing constraints and HVT cells on non-critical paths to reduce static power consumption. However, the complex circuit network makes it difficult to distribute the threshold voltage. In many circuit designs, the standard-threshold voltage (SVT) between LVT and HVT is also used, further increasing the threshold voltage distribution's complexity.  
The threshold voltage distribution algorithms in [17; 18; 19] effectively reduce static power consumption. However, these methods require updating the timing in the static timing analysis (STA) tools after each cell replacement, which means that the number of timing updates depends directly on the circuit scale. When applied to a VLSI design, the algorithms are less time feasible. On the other hand, when considering the circuit timing, these algorithms use the number of critical paths passing through the cell to distinguish whether the cell is critical, which cannot accurately reflect the connection between the cell and the path timing.  
This paper describes a triple-threshold path-based static power optimization methodology (TPSPOM). This method can effectively assign the three threshold voltages of the cell to reduce static power consumption. Its primary significance is as follows.  
1. We proposed a new way of distinguishing critical cells. We distinguish the criticality of a cell based on its delay-to-power ratio and the criticality of the paths through it. The most critical cell in the most critical path is then selected in the replacement process.
2. Our algorithm flow avoids many operations of updating the timing and is suitable for VLSI designs.