# Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing
## 3 Results and Discussion
### Binarized Neural Networks Applications
\begin{tabular}{c c c} \multicolumn{3}{c}{\(O=\overline{A\oplus W}\)} \\ \hline \# & **Operation** & **Equivalent** \\
**Step** & **Operation** & **Operation** \\ \hline
1-2 & sFALSE (O, M\({}_{\rm J}\)) & \(O=M_{1}\)= 0 \\
3 & 2-SIMPLY (A, M\({}_{\rm J}\)) & \(M_{1}=\overline{A}\) \\
4 & 3-SIMPLY (W, A, O) & \(O=\overline{W+A}=\overline{AW}\) \\
5 & 3-SIMPLY (\(\widetilde{W},\)M\({}_{\rm V}\)) & \(O=\overline{A\overline{W}}+WA\) \\ \hline \end{tabular}   
**(a)**  
**(b)**  
**Figure 9. (a) Sequence of IMPLY and FALSE operations required for implementing the XNOR operation using n-SIMPLY. While 9 steps and 2 support devices are needed when using only 2-SIMPLY [30], the increased parallelism provided by n-SIMPLY reduces to 5 the number of computing steps, and only 1 support device is needed. (b) Circuit implementation of the XNOR operation on the SIMPLY architecture. ** \begin{tabular}{c c c} \multicolumn{3}{c}{\(\#\)**Step**} & **Operation** & **Equivalent Operation** \\ \hline
1-6 & sFALSE (C, M\({}_{\rm V}\) M\({}_{\rm J}\) M\({}_{\rm J}\) M\({}_{\rm J}\) M\({}_{\rm J}\) M\({}_{\rm J}\)) & C = M\({}_{1}\) = M\({}_{2}\) = M\({}_{3}\) = M\({}_{4}\) = M\({}_{5}\) = 0 \\
7 & 2-SIMPLY (I, M\({}_{\rm J}\)) & \(M_{1}=\Gamma\) \\
8 & 2-SIMPLY (S\({}_{\rm\sigma}\) M\({}_{\rm J}\)) & M\({}_{2}=\widetilde{S_{0}}\) \\
9 & 2-SIMPLY (S\({}_{\rm J}\) M\({}_{\rm J}\)) & M\({}_{3}=\widetilde{S_{1}}\) \\
10 & 4-SIMPLY (M\({}_{\rm J}\) M\({}_{\rm J}\) M\({}_{\rm J}\) C) & \(C=\mathbf{S_{0}S_{1}I}\) \\
11 & 2-SIMPLY (M\({}_{\rm J^{\prime}}\) M\({}_{\rm J}\)) & \(M_{4}=S_{0}\) \\
12 & 2-SIMPLY (M\({}_{\rm J^{\prime}}\) M\({}_{\rm J}\)) & \(M_{5}=S_{1}\) \\
13,14 & sFALSE (S\({}_{\rm\sigma}\) S\({}_{\rm\sigma}\)) & \(S_{0}=S_{1}=0\) \\
15 & 3-SIMPLY (I, M\({}_{\rm\sigma}\) S\({}_{\rm\sigma}\)) & S\({}_{0}=S_{0}\bar{\Gamma}\) \\
16 & 3-SIMPLY (M\({}_{\rm J^{\prime}}\) M\({}_{\rm\sigma}\) S\({}_{\rm\sigma}\)) & \(\mathbf{S_{0}=i\overline{S_{0}}+S_{0}\bar{I}}\) \\
17 & 3-SIMPLY (I, M\({}_{\rm J^{\prime}}\) S\({}_{\rm J}\)) & S\({}_{1}=S_{1}\bar{I}\) \\
18 & 3-SIMPLY (M\({}_{\rm\sigma}\) M\({}_{\rm J^{\prime}}\) S\({}_{\rm J}\)) & \(S_{1}=S_{1}\bar{I}+S_{1}\overline{S_{0}}\) \\
19 & 4-SIMPLY (M\({}_{\rm J^{\prime}}\) M\({}_{\rm J^{\prime}}\) M\({}_{\rm\sigma}\) S\({}_{\rm J}\)) & \(\mathbf{S_{1}=S_{1}\bar{I}+S_{1}\overline{S_{0}}+IS_{0}\overline{S_{1}}}\) \\ \hline \end{tabular}   
**(b)**  
**(c)**  
**Figure 10. n-SIMPLY-based accumulator for implementing the popcounting operation used in BNNs. (a) Two serially connected half-adders (HAs) used to implement the popcount operation. (b) Truth table of the sequence of two serially connected half-adders (HAs). The carry-out (C) of the complete operation is computed in a single step by using a 4-SIMPLY. (c) Sequence of IMPLY and FALSE operations implementing the operation described by the truth table in (b). The use of 4-SIMPLY reduces the number of computing steps from 26 (when using only the 2-SIMPLY [30]) to 19. (d) Percentage of saved computing steps for increasing number of output bits and increasing parallelism with respect to the baseline 2-SIMPLY implementation from [30]. Most computing steps are saved by using the 3-SIMPLY and up to the 4-SIMPLY operations, while further increasing the parallelism of the SIMPLY operation results in a limited improvement. For the activation (i.e., comparison with a trained threshold), we improved the 2-SIMPLY implementation from [30], by removing unnecessary computing steps. The resulting sequence of computing steps can be built using the flowchart reported in Supplementary Figure S5, which consists in the computation of a bitwise XNOR between the input and the trained threshold, and additional AND/OR operations. By following this method, the number of computing steps scales exponentially with the number of compared input bits (i.e., 2-SIMPLYbaseline in Figure 11).