## 1 Introduction  
CMOS is the semiconductor technology used in most of today's integrated circuits. The performance of CMOS has been improved by increasing the density of circuits; however, the speed of development of CMOS circuits is slowing due to physical limitations. Therefore, next-generation circuit technology to replace CMOS is being developed to solve this problem [1; 2; 3; 4; 5; 6]. Quantum-dot cellular automata (QCA) is a next-generation digital nanocircuit design technology that does not use transistors [7; 8]. Circuits designed with QCA have lower power, faster speed, and higher signal transmission stability than circuits designed with the CMOS technology [9; 10; 11; 12; 13]. Therefore, QCA is attracting attention from many research communities as an excellent next-generation circuit technology to replace CMOS [14; 15]. In QCA, various circuits can be designed based on digital logic, including memory essential for computers. Representatively, RAM, ROM, CAM, and registers have been proposed, and currently, research is focused on designing registers and RAM [16; 17; 18; 19; 20; 21; 22; 23; 24; 25]. The conventionally proposed QCA-based RAM cells have a disadvantage in that values stored in most circuits are initialized according to a selection input. This is because the value stored in the RAM cell and the actual output value are treated identically, greatly affecting scalability. When RAM has multiple selection input lines, all the lines, except the line whose signal value is 1, transmit a signal of 0, hence, apart from the RAM cell that receives the signal of 1, the rest of the cells do not store values and are initialized. Therefore, when designing the RAM, only one selection input line has to be used. In the end, the corresponding circuits were designed with only 1 \(\times\) N RAM, and N \(\times\) N RAM cannot be designed using multiple select input lines due to scalability problems [16; 17; 18; 19; 20]. As a solution for designing an N \(\times\) N type RAM, some studies have recently been carried out to design the stored values and output values differently [21; 22; 23; 24]. These RAM cells can be designed to be extended to N \(\times\) N type RAM like CMOS-based RAM cells. However, these RAM cells have a problem in that signal transfer is unstable due to the use of many planar structure intersections. In particular, the recently proposed circuit [22] uses a large number of planar intersections, thus the signal is unstable and the circuit does not operate properly. The proposed 2-to-1 multiplexer is designed with a single clock and can satisfy the real clocking system with simple wiring clock control. We show a typical clocking design by fitting MXLR to 3 \(\times\) 3 square bins so that the proposed circuits can potentially satisfy current real clocking systems. The contributions of this study can be summarized as follows:  
* We design a planar 2-to-1 multiplexer circuit using cell interactions. * We propose a RAM cell logic diagram that separates stored values and output values. * Based on the proposed multiplexer and logic diagram, we propose a secure QCA-based RAM cell with excellent scalability. * We show that the proposed structures can work well in a real clocking system by simply adjusting the clocking of the wire. * The performance of the proposed circuit and existing circuits is verified and compared using QCADesigner. * In addition, circuits are measured and compared with energy dissipation using QCAPro. * The proposed multiplexer is mathematically verified through physical proof. This paper is organized as follows. Section 2 explains the basic knowledge on QCA, the previously proposed multiplexer circuits, and the logic diagrams and circuits of RAM cells. Section 3 proposes the 2-to-1 multiplexers and the RAM cells designed based on them and provides the real clocking design by fitting our scheme in 3 \(\times\) 3 square bins. In Section 4, the performances of the proposed circuit and existing circuits are compared.