## 5 Findings and Analysis
### Complexity Examination
By employing a design that scales linearly, the proposed architecture can fit into more compact spaces while still delivering the necessary computational power. Moreover, the analysis demonstrates that all systems evaluated share a comparable time complexity, which is linear. This finding suggests that the operational efficiency of the hybrid systolic multiplier is similar to that of current architectures in terms of processing speed. However, it achieves this efficiency while requiring significantly fewer resources. The ability to maintain linear complexity in both space and time reinforces the advantages \begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline
**Multiplier** & & & & & & & & & \\
**Layout** & & & & & & & & & \\ \[PERSON] [19] & 0 & \(r^{2}\) & \(3r^{2}+2r\) & 0 & \(3r^{2}+4r\) & \(r+1\) & \(\lambda_{A}+3\lambda_{X}\) & \(\mathcal{O}(r^{2})\) & \(\mathcal{O}(r)\) \\ \[PERSON] [20] & 0 & \(r^{2}\) & \(r^{2}+r\) & 0 & \(3r^{2}\) & \(r+2\) & \(\lambda_{A}+\lambda_{X}\) & \(\mathcal{O}(r^{2})\) & \(\mathcal{O}(r)\) \\ \[PERSON] [43] & 0 & \(r^{2}+r\) & \(r^{2}+2r\) & 0 & \(1.6r^{2}+4r\) & \((r+7)/2\) & \(\lambda_{A}+\lambda_{X}\) & \(\mathcal{O}(r^{2})\) & \(\mathcal{O}(r)\) \\ \[PERSON] [44] & 0 & \(r^{2}+r\) & \(r^{2}+(7r+1)/2\) & 0 & \(2.1r^{2}+6.5r\) & \((r+7)/2\) & \(\lambda_{A}+\lambda_{X}\) & \(\mathcal{O}(r^{2})\) & \(\mathcal{O}(r)\) \\ \hline [PERSON] [50] & 0 & \(r^{2}\) & \(r^{2}+r\) & \(r\) & \(2r^{2}+3r\) & \(r+1\) & \(\lambda_{A}+\lambda_{X}+\lambda_{M}\) & \(\mathcal{O}(r^{2})\) & \(\mathcal{O}(r)\) \\ \hline Proposed & \(2r+6\) & \(r\) & \(2r\) & 0 & \(3r\) & \(3r\) & \(2\lambda_{tri}+\lambda_{A}+\lambda_{X}\) & \(\mathcal{O}(r)\) & \(\mathcal{O}(r)\) \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Assessment of Resource Utilization and Execution Time in Proposed and Rival Multipliers. of this architecture, making it particularly well-suited for applications where efficient use of resources is critical. This combination of low area utilization and power consumption, alongside comparable performance, positions the hybrid systolic multiplier as an optimal choice for modern IoT applications. This balance between performance and resource optimization makes the proposed configuration an appealing choice for practical applications. It is especially relevant in contexts where effective resource management is crucial, especially in the development of assistive technologies for individuals with disabilities. By addressing both performance standards and resource limitations, the hybrid systolic multiplier represents a promising solution for modern computational challenges. The hybrid systolic multiplier setup offers several advantages that greatly enhance its suitability for IoT solutions designed to assist individuals with disabilities. One of the key benefits of this design is its compact nature, which minimizes space demands while maximizing the use of available hardware resources. This efficient arrangement not only leads to a more compact physical form but also positively influences essential performance indicators. By reducing the overall footprint, the hybrid systolic multiplier allows for easier integration into various devices, making it an ideal choice for assistive technologies. Additionally, the optimized use of resources contributes to improved efficiency and effectiveness in operation, further supporting the needs of individuals with disabilities. Overall, this design represents a significant step forward in creating accessible and efficient solutions in the IoT landscape. The enhancements in space efficiency result in improved values for both the area-delay product (ADP) and the power-delay product (PDP) of the multiplier. These improvements enhance overall functionality and promote better energy conservation, making the proposed configuration an attractive option for scenarios that demand efficient resource management and low power usage.