# Design of K-Band Power Amplifier with 180-Degree Phase-Shift Function Using Low-Power CMOS Process
## 2 Design of the CMOS Power Amplifier with LP Process  
In this study, a power amplifier was designed using a 40-nm LP CMOS process. Figure 1 shows the I-V curve of NMOS with the same gate width using the 65-nm GP and the 40-nm LP processes. As shown in Figure 1, the transistor using the 40-nm LP process has a relatively high threshold voltage, a low current level, and a low \(g_{m}\) value compared to the transistor using the 65-nm GP process.  
With the same gate width, comparing the \(g_{m}\) values of the transistors using 65-nm GP and 40-nm LP processes in Figure 1, the 40-nm LP transistor has a \(g_{m}\) value of approximately 66% compared to that of the 65-nm GP transistor. Therefore, when the 40-nm LP process is used to obtain the same gain as the two-stage power amplifier using the 65-nm GP process, a three-stage structure is required. In a simple calculation, to obtain the same gain from the power amplifier, in the case of the 40-nm LP process, the required IC area is increased by approximately 33% compared to the 65-nm GP process. Furthermore, a low current level of the 40-nm LP process compared to the 65-nm GP process causes a low output power of the power amplifier. In order to obtain the required output power, sufficient drain current is required, and, to this end, an LP process-based power amplifier should use an increased transistor size. However, the increased transistor size also increases parasitic capacitances, which requires high driving power, resulting in a decrease in gains and an increase in dc power consumption. Furthermore, the low \(g_{m}\) of the LP process-based transistor directly degrades the gain of the power amplifier. Such characteristics of the LP process act as  
Figure 1: Comparison of current levels of NMOS of low- and general-power CMOS processes.  
unfavorable factors in terms of power gain, output power, and efficiency of the power amplifier.  
Among them, in particular, due to the low gain characteristics of the LP process, it is essential to apply a multi-stage structure in the power amplifier using the LP process. In this study, four stages were used, as shown in Figure 2, to secure sufficient gain of the power amplifier. As shown in Figure 2, the power amplifier is designed using a differential structure to obtain virtual AC ground [10; 11; 12; 13]. Accordingly, transformers as a function of input and output baluns were essentially used in the input and output matching networks [14]. In addition, the transformer was used for the component of the inter-stage matching networks. The matching networks were completed with the transformers and additional metal-insulator--metal (MIM) capacitors. Second, third-driver and power stages were designed as common-source (CS) structures. The structure of the first driver stage is described in the following section. Additionally, the capacitive neutralization technique was used to secure stability and power gain [15; 16; 17]. The supply voltage of each amplification stage was entered through the center-tap of the primary winding of the transformer. To obtain accuracy of the simulation, the electromagnetic (EM) simulation was conducted in the design of the passive devices, including transformers and inter-connection lines.  
In the power stage of the power amplifier, the power-matching technique was used to improve maximum output power using output transformer and shunt MIM capacitors, as shown in Figure 2. The used values of the MIM capacitors and transistors of the power amplifier are also shown in Figure 2.