# Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications
## 4 All-Digital Frequency Synthesiser for Multiband Transceivers
After that, all counters are reset and the TDC waits for another pair of the input signals for a new measurement. As shown in reference [28], a TDC employing such a structure can be synthesised in various technology nodes. It was implemented in 65 nm and 0.13 \(\upmu\)m CMOS technologies and resolutions close to 1 ps can be achieved in both technologies, which exceeds our requirements by 12 times. However, to achieve resolutions close to 1 ps, more stages of the gated ring oscillator should be turned on, which increases power consumption. Therefore, high resolution should be used only when it is needed. Similar mismatches to those in the DCO's tuning banks occur in the synthesised ring oscillators which are used in TDC. All delay cells (tri-state inverters), which are used to compose ring oscillators, are the same. However, due to their irregular location and wiring after automatic place and route, these cells have different effective driving strengths, which results in different stage delays. However, despite the mismatch in stage delay, ring oscillator periods, which are utilized in calculations of the TDC's output, are consistent during measurement. Also, the resolution of such TDC depends on the difference between stage-delay of higher and lower frequency oscillators and not on absolute value of stage delay (delay mismatch usually is much lower than stage-delay). Therefore, this structure is less susceptible to delay mismatch compared to TDC based on delay lines. Although these mismatches in TDC stage delay are generally undesirable, they can be used to fine tune resolution of TDC based on ring oscillators. A TDC calibration technique which takes advantage of the place and route irregularity is presented in reference [29]. This mechanism sorts used delay elements by driving strength and uses this information to achieve a different oscillation frequency (and corresponding stage delay) with same number of enabled sections of ring oscillators, i.e., same number of the parallel-connected sections will result in a different stage delay, depending on the position in chip layout of the sections. As mentioned earlier, the filter of frequency synthesiser has the important role of controlling the synthesiser's dynamic characteristics and noise filtering. However, it gets little attention in publications related to frequency synthesisers [30; 31; 32]. Often it is only stated that there is a filter in the structure, without further elaboration. Filters, suitable for IoT and IoV applications in multiband frequency synthesisers can be based on structure from references [33; 34]. Its main proportional-integral part is shown in Figure 10. Additional cascaded IIR filter stages can be used to form a higher order filter. Proportional and integral paths can be reconfigured by changing their gain coefficients, respectively \(\alpha\) and \(\rho\). Gain stages are implemented as right-shift registers. The type of synthesiser (from type-I to type-II and vice versa) that is controlled by signal _TII_--integral paths activates only  
Figure 10: Structure of filter for type-II frequency synthesiser. when it is set to a high logic level. If four additional IIR filter stages are used, such a filter enables changing the synthesiser order from first to sixth. The most power-hungry blocks in a proposed structure of frequency synthesiser are DCO and TDC. Power consumption of the presented DCO core is 18 mW, while the power consumption of TDC is 3,6 mW. All other circuitry is low-power and operates at a relatively low reference frequency. Therefore, we will estimate 50% of sum of DCO and TDC power consumption i.e., 10.8 mW. Total power consumption is 32.4 mW. Calculated achievable phase noise and its components of all digital frequency synthesiser, when presented time to digital converter and digitally controlled oscillator are used is shown in Figure 11. The maximal frequency of designed DCO, which is equal to 5.44 GHz, was used for calculations.