# The Challenges of Advanced CMOS Process from 2D to 3D
## 6 Challenges in Processing III-V 3D Transistor on Si  
The historical down-scaling path for Si-based transistors may drive to integrate new materials in the channel region with high carrier mobility property. In the latest years, III-V compound semiconductors have emerged as a credible alternative. To achieve this technological point, fundamental technical problems have to be solved where many challenges need to be addressed before the first non-Si CMOS technology becomes a reality. Among these difficulties, contact resistance, off-state characteristics, reliability and integration with Si remain serious problems [148]. Figure 21 shows the schematic view of p-and n-FET and their process flow of planar III-V and SiGe-based transistors. There are a series differences in the process, which make III-V compounds problematic with industrial application in future. The main problem with integration of III-V on Si is the difficulty of direct growth of these materials with high epitaxial quality on Si. There are many methods to achieve this goal e.g., lateral growth, wafer bonding and using advanced GeSnSi buffer layers prior to III-V growth. The best way to manufacture 3D transistors is to grow III/V material in a trench when the Si of a Si-fin is etched and refilled by the III-V material for 3D transistor structures. The full process flow for an InGaAs FinFET is demonstrated in Figure 22. The lowest defect density of \(8\times 10^{8}\) cm\({}^{-2}\) was obtained on \"V\" shaped bottom trenches, where GaAs nucleation occurs only on [111] Si planes, minimizing the interfacial energy and preventing the formation of anti-phase boundaries. InAs and GaSb are thought to be promising candidates to replace Si in sub-7 nm CMOS devices due to their respective high electron and hole mobility [149]. The deposition of III-V material was done by metal organic chemical vapor deposition (MOCVD) on large CMOS compatible on-axis Si (001) substrates, using a thin buffer layer stack to manage thermal mismatch. The growth rate on the different planes is manipulated by the chosen metal organic vapor phase epitaxy (MOVPE) growth conditions. Parameters such as the growth temperature, reactor pressure, partial pressure of the precursors, V/III ratio, pattern mask ratio as well as the effective SAG rate have a strong impact on the surface reconstruction and on all kinetic processes (ad- and desorption of precursors, decomposition, diffusion, incorporation etc.). The interplay of above parameters defines the final growth rate hierarchy and hence the ridge formation [150]. Figure 20: Vertically stacked nanowire process flow including RMG modules. (**a**) Ground plane _I/I_ + anneal; (**b**) SiGe/Si/SiGe/Si epitaxy; (**c**) Low-temperature STI filling; (**d**) Embedded Si S/D epitaxy; (**e**) Si nanowire formation by SiGe etch; (**f**) Fill metal (W) deposition/CMP. Reprinted with permission from [4]. Copyright IEEE, 2016. The replacement of Si fins has proven to be a very versatile technique, allowing for the fabrication of FinFET, GAA and dual nanowire devices from the same basic flow. This process has enabled the first demonstration of fully integrated III-V devices on 300 mm Si substrates in a very large scale integration (VLSI) compatible flow. For the FinFET architecture, the unintentional background doping from the  
Figure 21: (**a**) Schematic of devices cross section and (**b**) process flow of 2D hybrid InGaAs/SiGe CMOS technology with representative best-known process for n- and p-MOSFET. Non-compatible process steps are highlighted in red in the process flow description. Figure 22: Summary of process flow of formation fin when (**a**) post InP deposited; (**b**) InP chemical mechanical polish (CMP); (**c**) InP recess; (**d**) InGaAs growth; (**e**) InGaAs CMP; (**f**) STI oxide recess. Reprinted with permission from [151]. Copyright Solid State Electron, 2016.  
carbon inherent in the metal organic precursors requires development of a p-type doping solution to suppress S/D leakage through the InP buffer layer.