# Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
## 4 Performance Comparison of Proposed Structures
### Comparison of the Power Consumption of a Single Bit-Cell  
As demonstrated in Figure 12, a detailed comparison of maximum power consumption was conducted for each of the three SRAM structures during read operations within a single bit-cell. The conventional 8T SRAM structure, depicted in Figure 11a, exhibits a maximum power consumption of 61.078 uW during a read operation. This power level reflects the baseline consumption typical of traditional 8T designs, which, while reliable, often encounter limitations in terms of power efficiency, especially in applications that require frequent read access or are constrained by energy availability. In contrast, the modified low power 8T structure introduced by [PERSON], shown in Figure 11b, demonstrates a reduction in power consumption, with a measured maximum of 48.751 uW. This reduction highlights the effectiveness of [PERSON]'s design modifications, which focus on minimizing dynamic power consumption through optimized transistor configurations, though the design remains inherently limited by certain structural constraints. Notably, the proposed 8T bit-cell structure in this study achieves a substantial reduction in power consumption  
Figure 11: (**a**) Conventional 8T SRAM and (**b**) ultra-low power (ULP) 8T SRAM.  
during read operations, with a maximum consumption of only 20.569 uW. This represents a significant decrease of approximately 66% compared to the conventional structure in Figure 11a and a 58% reduction compared to [PERSON]'s low power 8T design, underscoring the enhanced power efficiency achieved by the proposed structure.  
Further comparative analysis was conducted to evaluate the maximum power consumption of each structure during write operations. The conventional 8T SRAM design (Figure 11a) registers a maximum power consumption of 151.65 uW during the write cycle. This relatively high consumption reflects the power demands of the traditional design, which can be a limiting factor in energy-constrained applications. Similarly, [PERSON]'s low power 8T SRAM design, shown in Figure 11b, records a maximum write power consumption of 152.664 uW, indicating that while the structure is optimized for read operations, it does not significantly reduce the power consumption during write operations compared to the traditional design. In contrast, the proposed 8T SRAM structure demonstrates a more substantial improvement, with a maximum power consumption of 130.847 uW during write operations. This represents a reduction of approximately 13.7% compared to the conventional 8T SRAM and an improvement over [PERSON]'s design as well, highlighting the proposed structure's efficacy in reducing power demands across both read and write operations.  
These results demonstrate that the proposed 8T SRAM structure is the most power-efficient of the three designs evaluated, achieving the lowest power consumption during both read and write cycles. This improved efficiency is particularly beneficial in applications requiring extensive memory access, such as AI edge devices and other energy-sensitive computing environments, where power conservation is critical. By reducing the power demands during both read and write operations, the proposed structure not only addresses limitations found in conventional and low-power designs but also advances the performance capabilities of SRAM technology for compute-in-memory (CIM) applications. The observed reductions in power consumption further emphasize the importance of innovative design approaches in the development of energy-efficient memory solutions.