## Sensor Bus Standards
### Inter-IC Bus  
The Inter-IC (I\({}^{2}\)C) bus [2] was introduced by Philips Semiconductor as a standard for connecting networked integrated circuits which may or may not include sensors. I\({}^{2}\)C is intended for application in systems which connect microcontrollers and other microcontroller-based peripheral devices. It is a two wire serial bus to minimize the cost of connecting the various devices in the system, as shown in Figure 1. Two wires, serial data and serial clock, carry information between the devices connected to the bus. The serial data wire is bi-directional but data may flow in only one direction at a given time. Each device is identified by a unique address. Devices on the bus are defined as masters or slaves. A master initiates a data transfer on the bus and generates the clock; it also generates the control signals which are placed on the data wire. The slave device is a device which is controlled by the master. A slave can either receive or send data depending on the master.  
Master devices are usually microcontrollers. The I\({}^{2}\)C bus is a multi-master bus. Therefore, more than one microcontroller can be connected to the bus. An arbitration procedure is implemented to avoid the chaos that might ensue from simultaneous data transfer by multiple micro-controllers.  
The bus can operate in three modes with different data rates. Data on the bus can be transferred at rates of up to 100 kbit/s in the standard-mode, up to 400 kbit/ in the fast-mode, or up to 3.4 Mbit/s in the high-speed mode. The number of interfaces connected to the bus is dependent on the bus capacitance limit of 400 pf.  
I\({}^{2}\)C bus supports two addressing schemes: 7-bit address and 10-bit address. Up to 1024 devices are allowed to be connected to the bus. The 7-bit address scheme has shorter message length and requires less complex hardware. Devices with 7 and 10 bit addresses can be mixed in the same system.  
I\({}^{2}\)C bus allows a system design to rapidly progress directly from a functional block diagram to a prototype. The integrated addressing and data-transfer protocol allow systems to be completely software-defined. The topology is simple and the number of connection wire is minimized. However, although the hardware specification allows for simple interfacing, the communication protocol is rigid. The control signals from the master (such as start condition, stop condition, acknowledge) are encoded on the data wire which increase the required complexity of the interface hardware.  
I\({}^{2}\)C bus does not support plug-n-play or interrupt functions which are important for many sensor networks. To save energy, some sensor nodes should be in sleep mode most of the time and woken up by a timer or sensing event. For each information transport, the microcontroller should initiate the request and provide the clock to the sensors. To get the updated information from the sensor, the microcontroller has to poll each sensor node connected on the bus very often to make sure it will not miss new information or unexpected events. These features make I\({}^{2}\)C unsuitable for the applications which have strict requirement for the power efficiency and emergency processing. Although the sensor node could be clipped to or from the system easily, the microcontroller can not detect an event or configure the system during operation. This limits the application of I\({}^{2}\)C in sensor networks which are usually dynamically reconfigurable and/or demand high energy-efficiency.