# Late-Stage Optimization of Modern ILP Processor Cores via FPGA Simulation
## 3 FPGA-Enhanced Design Flow
### RTL Design Categories  
The key to utilizing late-stage optimization is that the design effort for RTL change should be affordable. The late-stage aware RTL design can help minimize RTL change effort. Table 2 shows that the late-stage aware RTL design options are divided into four categories: (1) PAR, whose RTL change can be conducted by a parameter identifier. Once the parameterized design is determined before RTL implementation, PAR is the easiest case for RTL change and most suitable for late-stage optimization. (2) MIN, whose implementation difficulty is determined by the design of its minimal value. This option typically denotes the latency of an operation, such as the _issueLat_ and _opLat_ parameters in FUs. We can introduce a configurable delay unit to implement other lengthy latencies on the basis of a minimalist design. The difficulty of minimizing latency in late-stage optimization can be reduced in two ways: increasing the cycle time if the performance reduction is bearable and not implementing several minimal values. For options whose latency affects several modules, configuration becomes increasingly difficult. Hence, exploring such a design option at the early stage is recommended. For example, the _various latencies_ parameter of the pipeline belongs to this type. (3) MAX, whose difficulty in implementation is determined by the \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Module** & **Parameter** & **Op-Type** & **RTL** & **Effort** \\ \hline \multirow{6}{*}{FUs} & Count & PT & MAX & H \\  & opLat & VT & MIN & M \\  & issueLat & VT & MIN & M \\  & opclass & CT & IMP & M \\ \hline \multirow{6}{*}{BPU} & preType & PT & IMP & M \\  & TableSize & VT & PAR & E \\  & BTBEntries & VT & PAR & E \\  & BTBTagSize & VT & PAR & E \\  & RASSize & VT & PAR & E \\ \hline \multirow{6}{*}{LSU} & LQEntries & VT & PAR & E \\  & SQEntries & VT & PAR & E \\  & LFSTSize & VT & PAR & E \\  & SSITSize & VT & PAR & E \\ \hline \multirow{6}{*}{Pipeline} & fetchWidth & PT & MAX & M \\  & fetchBufferSize & VT & PAR & E \\  & decodeWidth & PT & MAX & M \\  & dispatchWidth & PT & MAX & M \\  & issueWidth & PT & MAX & M \\  & commitWidth & PT & MAX & M \\  & squashWidth & PT & MAX & M \\  & trapLatency & VT & MIN & E \\  & backComSize & VT & PAR & E \\  & forwardComSize & VT & PAR & E \\  & numPhysIntRegs & VT & PAR & E \\  & numPhysFloatRegs & VT & PAR & E \\  & numIQEntries & VT & PAR & E \\  & numROBEntries & VT & PAR & E \\  & various latencies & VT & MIN & H \\ \hline \multirow{6}{*}{Cache (L11/D L2/L3)} & hit\_latency & VT & MIN & M \\  & mshrs & VT & PAR & E \\  & tgts\_per\_mshr & VT & PAR & E \\  & size & VT & PAR & E \\  & assoc & PT & IMP & M \\  & write\_buffers & VT & PAR & E \\  & prefetch\_on\_access & CT & IMP & M \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Categorization consideration of design options from GEM5 (VT: value type; PT: policy type; CT: choice type. PAR: parameter; MIN: minimal; MAX: maximum; IMP: implementation. E: easy; M: medium; H: hard). design of its maximum value. This option typically refers to the buffer size or operation width. Similar to the MIN option, MAX allows an increase in cycle time or omission of other options to handle such a difficulty. For small sizes or widths, parameter primitives or mask signals can be introduced on the basis of the design with the maximum value. (4) IMP, which requires a nearly new RTL design for late-stage optimization. This option may add to the design effort burden of RTL implementation. Therefore, our principle is that an option can be implemented only if it can be used in one type of processor core. Otherwise, only early-stage optimization should be considered. Nevertheless, certain cases call for the design of various processor cores, thereby rendering these IMP options with different values useful. Using the late-stage aware RTL design method, we can see that most of the design parameters can be optimized at the late stage with minimal design effort. Only a few design parameters cannot be optimized at this stage.