# A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver
## 5 Simulation Results  
To verify the effectiveness of our proposed DBB-CDR circuit, we implemented a complete 32 Gb/s ADC-based receiver using 28 nm CMOS technology. The ADC-based receiver circuit included a T-coil inductor, injection lock/divider, DCD/QED, DCC/QEC, phase interpolator, CTLE, T/H, delay cell, 32-way time-interleaved SAR ADC, and an additional sub-ADC and time interpolator, implemented using analog circuits. The data demux, DSP, DBB-CDR and skew calibration logic were implemented in the digital domain. The whole 32 Gb/s ADC-based receiver, with the exception of the DSP and DBB-CDR circuit, occupied an area of 0.34 mm \(\times\) 0.8 mm. According to the simulation results, we determined that the power consumption of the whole 32 Gb/s ADC-based receiver was 233 mW. We set different frequency offsets to examine the frequency offset tracking ability of the DBB-CDR circuit using AMS digital-analog hybrid simulations. Figure 12a,b show plots of the tracking ability of the DBB-CDR circuit under a 0 ppm and \(-\)448 ppm frequency offset, respectively. As can be seen from Figure 12a, when there was no frequency offset, the DBB-CDR circuit converged to the most suitable phase after about 500 ns. When the phase converged, the phase tracking speed was stable around 0, and the error number of the data symbols transmitted throughout the entire system no longer increased. As can be seen from Figure 12b, when there was a \(-\)448 ppm frequency offset, the phase tracking speed of DBB-CDR gradually accelerated, and the phase of the DBB-CDR circuit also accelerated between 0 and 127, until the speed of the phase movement caught up with the signal frequency offset. Once the tracking speed of the DBB-CDR circuit gradually stabilized to about \(-\)56, the speed of the phase movement could maintain a relatively constant positional relationship between the clock and the signal. At this time, the error number of the data symbols in the whole system also remained unchanged, which reflected the effective frequency offset tracking performance of the DBB-CDR circuit. According to our linearization analysis of DBBPD and the linearized DBB-CDR model in Section 4, we performed jitter transfer function and jitter tolerance simulations on the DBB-CDR circuit using Equations (8) and (9), and the parameter values were selected from those in Table 3. In order to compare the performance of our DBB-CDR circuit to that of an original MM-CDR circuit, we set the same gains for the MMPD as for the DBBPD. In addition, the other parameters of a MM-CDR circuit were also selected to be consistent with those of the DBB-CDR circuit and only the gain of a decimation module needed to be added. Figure 13a shows the plots of the jitter transfer function performance of the DBB-CDR and MM-CDR circuits under a 0.04 UI, 0.03 UI and 0.02 UI variance of Gaussian jitter. Different Gaussian jitter deviations were reflected by different PD gains. It can be seen in the figure that the greater the PD gain, the wider the bandwidth of the jitter transfer function and the smaller the jitter peaks. It can also be observed that the bandwidths of the DBB-CDR circuit were 11.39, 14.48 and 20.62 MHz, and the corresponding bandwidths of the MM-CDR circuit were 2.86, 4.06 and 7.08 MHz. Thus, the DBB-CDR circuit could obtain a higher bandwidth under the same phase detection gain compared with the MM-CDR circuit. As can be seen from Figure 13b, the DBB-CDR and MM-CDR circuits readily met the JESD204C jitter tolerance limit. Whether \(\sigma\) was equal to 0.04 UI, 0.03 UI or 0.02 UI, the higher the PD gain, the greater the JTOL margin. Although the JTOL margins of the DBB-CDR and MM-CDR circuits were similar at high frequencies under the same phase  
detection gain, the JTOL performance of the DBB-CDR circuit was much better than that of the MM-CDR circuit at low frequencies. Figure 12: (a) The tracking ability of the DBB-CDR circuit under a 0 ppm frequency offset; (b) the tracking ability of the DBB-CDR circuit under a \(-\)448 ppm frequency offset.