## 1 Introduction and Related Work
The selection of the irreducible polynomial is of utmost importance and offers various options, including trinomials, All-One Polynomials (AOPs), pentanomials, and Equally Spaced Polynomials (ESPs). This choice significantly impacts the efficiency and security of the multiplication operation. Each type of irreducible polynomial possesses unique properties and considerations, influencing factors such as computational performance, implementation complexity, and resistance to cryptographic attacks. The careful evaluation and selection of the appropriate irreducible polynomial are critical in achieving optimal performance and security within GF(2\({}^{k}\)) multiplication. While trinomials and pentanomials have been extensively studied, the exploration of AOPs for finite-field multiplication has received comparatively little attention. However, investigating the utilization of AOPs in GF(2\({}^{k}\)) computations holds the potential for unlocking new insights and optimizing hardware implementations, offering fresh perspectives for enhancing the performance of Galois field operations. The literature extensively explores various hardware architectures for implementing polynomial basis (PB) multiplication in GF(2\({}^{k}\)), including bit-parallel, bit-serial, and digit-serial multipliers. Among these architectures, bit-parallel multipliers stand out for accomplishing field multiplication in a fixed number of iterations, regardless of the field size \(m\), despite their significant space complexity [15]. On the other hand, systolic bit-parallel multiplier topologies, based on systolic arrays, offer an alternative approach that greatly enhances multiplier throughput at the expense of increased hardware complexity and latency [11; 12; 13]. These systolic architectures leverage parallelism and data flow to maximize the efficiency of GF(2\({}^{k}\)) multiplication operations, making them particularly attractive for high-throughput applications where performance is of paramount importance [16; 17; 18; 19]. However, when selecting the most appropriate multiplier architecture for a specific GF(2\({}^{k}\)) implementation, it is vital to carefully consider the trade-off between hardware complexity, latency, and throughput requirements [20; 21; 22; 23]. In cryptography applications where resources are limited, bit-parallel architectures are not the most suitable option due to their high hardware requirements. Instead, bit-serial multiplier layouts provide a better trade-off between speed and space, making them well suited for cryptographic applications with constrained space and power limitations [8; 24; 25]. These architectures offer efficient multiplication while accommodating tighter resource constraints [9; 10; 26]. However, it is worth noting that bit-serial architectures lack performance scalability and require a minimum of \(m\) time steps to produce the multiplication result [27; 28]. On the other hand, digit-serial multiplier architectures offer a slight improvement in hardware resources and performance scalability compared to bit-serial layouts [29; 30; 31; 32; 33]. This makes them a better fit for cryptography algorithms with fixed word sizes of data, striking a balance between resource utilization and performance requirements. This study introduces a novel approach to implementing the Montgomery multiplication algorithm in GF(\(2^{k}\)) using a newly devised bit-serial systolic array configuration. The construction process involves a thorough examination of the dependency graph (DG) derived from the multiplication method, followed by the careful selection of scheduling and projection vectors. By assigning appropriate timing and mapping the DG nodes to appropriate processing elements (PEs), a bit-serial systolic array construction is formed. Notably, the proposed bit-serial multiplier exhibits a remarkable reduction in both area and area-time complexity compared to existing constructions documented in the previous literature.