## 4 Simulation and Experimental Results  
In order to further verify the feasibility and correctness of the proposed modulation strategy, a linear-load typical system with unity input power factor is built on the Matlab/Simulink platform. The simulation results based on traditional and improved modulation strategy, respectively, are compared to prove the validity of the improved strategy. Simulation parameters are shown in Table 2.  
Figure 7 shows the waveforms of input/output voltage, current, and DC-link voltage under traditional control when \(\varphi\) is equal to 0.4. The percentage of DC-link voltage variation is limited into 2.71% (1.24 V/45.81 V = 2.71%), and total harmonic distortion (THD) of the output voltage \(v_{c}\) is 1.39%. Figure 8 shows the waveforms of input/output voltage, current, and DC-link voltage under improved control when \(\varphi^{\prime}\) is equal to 0.8. The percentage of DC-link voltage variation is limited to 0.56% (0.225 V/45.28 V = 0.56%), and  
Through (17) and (24) in the previous section, \(I_{c}=I_{c}{{}^{\prime}}\) can be attained when phase angle difference is equal to zero. At this point, it should be observed that the DC-link voltage fluctuations are equal under the line frequency cycle, regardless of which modulation strategy is adopted, as shown in Figure 9.  
Seen from the above figure, the voltage fluctuations of the DC side under the line frequency cycle are equal. Comparing the ripples under the switching cycle, clearly, the ripple under the traditional modulation strategy is larger than the ripple under the improved modulation strategy (the yellow envelope is thicker than the green one in the figure above), which demonstrates again the effectiveness of improved modulation strategy under switching period scale. When only the DC-link capacitance \(C_{d}\) is changed, the DC-link ripple coefficient, amplitude and THD of output voltage under traditional modulation strategy and improved modulation strategy are shown in Tables 3 and 4. Figure 10 intuitively depicts the trends of ripple coefficient changing with \(C_{d}\) under two modulation strategies, respectively. As \(C_{d}\) increases, the DC-link voltage fluctuation should reduce. However, when the capacitor is small, DC-link voltage waveform under the line frequency cycle is mainly caused by the oscillation under the switching cycle. In fact, the magnitude of voltage fluctuation under the switching cycle still shows a decline trend. \begin{table}
\begin{tabular}{c c c c c} \hline \hline  & \(C_{d}\) (uF) & Ripple Coefficient (\%) & \(V_{c}\) (V) & THD \\ \hline
1 & 20 & 4.26 & 34.01 & 0.13\% \\
2 & 100 & 0.91 & 34.01 & 0.14\% \\
3 & 200 & 0.51 & 34.03 & 0.20\% \\
4 & 300 & 0.50 & 34.05 & 0.22\% \\
5 & 400 & 0.44 & 34.07 & 0.22\% \\
6 & 500 & 0.45 & 34.09 & 0.23\% \\
7 & 600 & 0.53 & 34.09 & 0.39\% \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Parameters under improved modulation strategy. Figure 9: Capacitor voltage waveforms under traditional modulation strategy and improved modulation strategy when \(\varphi=\varphi^{\prime}=0^{\circ}\). In order to further prove the theoretical analysis of the proposed converter, an experimental prototype is made in laboratory. Specifications of the prototype are the same as Table 2. The prototype block diagram, experimental setup, and the top-view of the proposed converter are shown in Figure 11a-c, respectively. Notice that the converter is operated in an open loop and the driving signal is generated by RCP and FPGA EP4 CE10F17C8. The switching control signals of the upper, middle, and lower switches on the same bridge arm generated by RCP and FPGA are shown in Figure 12.  
Figure 11: (a) Block diagram of the experimental system; (b) Experimental set up; (c) Top-view of prototype. Figure 10: DC voltage ripple coefficient under traditional and improved modulation strategies. Figure 12 shows that the switch sequence is consistent with the theoretical analysis and simulation results.