# Power Consumption Modeling of Discontinuous Reception for Cellular Machine Type Communications
## 6 Simulation Setup and Results Analysis
### Analytical Model Results Validation  
In this subsection, the results obtained from the proposed analytical model for analyzing a DRX mechanism are validated through simulation results. For this reason, the performance metrics of the DRX mechanism, such as the power-saving factor and wake-up latency, were also determined via simulations by modeling all the DRX parameters. Figure 4 shows how the power-saving factor \(P_{S}\) and wake-up latency \(d\) vary according to the different values of packet inter-arrival time \(1/\lambda\). Therefore, Figure 4a shows the impact of packet inter-arrival time on \(P_{S}\). Results showed that \(P_{S}\) increases as the packet inter-arrival time increases. When the packet inter-arrival time is increased from 10s to 3600s, the \(P_{S}\) factor is approximately increased by 79%. This means that the device remains in sleep mode more often for longer packet inter-arrival times. Similarly, the wake-up latency \(d\) also increases for the increasing packet inter-arrival time, as depicted in Figure 4b. The wake-up Latency is approximately increased by 83% when the packet inter-arrival time is raised from 10 s to 3600 s. This shows that the packets are buffered in the device for longer periods of time for greater values of packet inter-arrival time. \begin{table}
\begin{tabular}{c c} \hline \hline
**Simulation Parameters** & **Values** \\ \hline Packet inter-arrival time (\(\frac{1}{\lambda}\)) & 60 s \\ Inactivity timer (\(T_{I}\)) & 20 ms \\ On Duration Time (\(T_{\text{ON}}\)) & 40 ms \\ Short Cycle timer (\(T_{SC}\)) & 640 ms \\ Short Cycle Number (\(N_{\text{SC}}\)) & 16 \\ Long Cycle Timer (\(T_{LC}\)) & 1.28 s \\ RRC Connection Time (\(T_{RC}\)) & 260 ms \\ Tail Time (\(T_{tail}\)) & 11.576 s \\ Sample size & 10 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: List of DRX simulation parameters [29; 30]. Similarly, Figure 5 shows the impact of the DRX inactivity time \(T_{I}\) on the power-saving factor \(P_{S}\) and wake-up latency \(d\). Results showed that the power-saving factor decreases gradually as the value of the DRX inactivity timer increases, see Figure 4(a). When the value of the DRX inactivity timer increases from 20 ms to 2560 ms, the power-saving factor is approximately decreased by 5%. Consequently, this increases the device power consumption as it spends more time in active mode due to the longer DRX inactivity timer. Nevertheless, Figure 4(b) further shows that the wake-up latency is decreased by 4% for the increasing values of the DRX inactivity timer due to the given value of tail time \(T_{tail}=11.576\) s, which increases the probability of a packet arrival during the tail state. Figure 6 presents the impact of the different values of the on duration Timer \(T_{ON}\) on the power-saving factor \(P_{S}\) and wake-up latency \(d\). Figure 5(a) shows the impact of the on duration Timer on \(P_{S}\). Results showed that \(P_{S}\) decreases approximately 9% when the value of \(T_{ON}\) is raised from 5 ms to 100 ms. This is due to the fact that the device consumes more power during on duration. Moreover, the wake-up latency \(d\) decreases by approximately 11% for the increasing values of \(T_{ON}\), as shown in Figure 5(b). Since the packet inter-arrival time is set to 60 s, \(T_{ON}\) has a relatively small impact on the DRX mechanism. Figure 4: Performance analysis of the DRX mechanism for different values of packet inter-arrival time. Other parameter settings are \(T_{I}=20\) ms, \(T_{ON}=40\) ms, \(T_{SC}=0.64\) s, \(T_{LC}=1.28\) s, \(T_{RC}=260\) ms, and \(T_{tail}=11.576\) s.  
In Figure 7, the influence of various long cycle timers is investigated. The power-saving factor \(P_{S}\) increases for the larger values of the long cycle timer due to the fact that the device spends more time in sleep mode, as depicted in Figure 6(a). For instance, the \(P_{S}\) factor increases approximately 20% when the long cycle timer value is increased from 160 ms to 2560 ms. As a result, the overall power consumption of the device decreases.