## 2 System Overview
### The Data Link  
The downlink data package is shown in Figure 2b. It contains the DAC controller configuration information. The 13 bits are organized as shown in Figure 2c. The start bits \"010\" signifies the start of a data package, which also helps improve the bit error rate (BER). The current amplitude control bits A\({}_{50}\) corresponds to 5 \(\upmu\)A to 320 \(\upmu\)A with 6-bit quantization; the frequency control bits F\({}_{30}\) corresponds to 10 Hz to 160 Hz with 4-bit quantization; and the duty ratio control bits D\({}_{20}\) corresponds to 2.5% to 20% with 3-bit quantization. The final bit P is the even-parity check bit. ASK modulation is used for the downlink. In the idle state, the idle bit is \"1\", and power but not data is transferred. If the data \"1\" is transmitted, power transfer is not affected. However, if the data \"0\" is transmitted, power transfer is reduced abruptly to generate a negative pulse, and the implant unit may not obtain enough power. Due to the limited bandwidth of both the primary and secondary \(LC\) tanks, high data rate may not be easily achieved. The situation gets worse as the downlink data package has 17 bits in total, and the data package time-slot is quite long. In the worst case of transmitting a long chain of \"0\" s, the rectifier output would drop as the on-chip filtering capacitor is not too large. The solution is to use the coding scheme as shown in Figure 2b: \"0\" is coded as \"1011\"; and \"1\" is coded as \"1111\". Therefore, even a long chain of data \"0\" s are transmitted the implant unit could get 75% of full power, which is designed to be adequate. An additional benefit is the relaxed requirement of the internal decoder. The data are decoded as \"0\" s and \"1\" s with and without negative pulses, respectively. Both pulse width and pulse phase are not required to be accurate. With this coding scheme, the length of the downlink data package is 170 \(\upmu\)s.  
The 9-bit uplink data package that is sent to the external control unit is shown in Figure 2e. The first 3 bits are the \"010\" start bits. The 4 th bit A\({}_{\text{C}}\) is the active-low acknowledgement bit. The 5 th bit P\({}_{\text{R}}\) is the power requirement bit for power boosting, which will be explained later. The next 3 bits V\({}_{2,0}\) indicate the quantized rectifier output voltage for power regulation; and the last bit P is the even-parity check bit. The uplink is based on backscattering that also uses ASK modulation. The uplink data transmission affects the power received, but as the data package has only 9 bits, the duration is much shorter. To balance the package duration and its effect on the received power, no special coding is used. The length of the uplink data package is 45 \(\upmu\)s.  
Both the downlink and the uplink are ASK modulated that share the same coupling channel, and they cannot work simultaneously. Time multiplexing is used as shown in Figure 2f. The uplink data package is sent to the external control unit every 500 \(\upmu\)s. The downlink data transmission interleaves with the uplink, but it only transmits data when there is a new configuration input data. When the new data is transmitted, the acknowledgement bit \(\mathrm{A_{C}}\) will be checked in the next uplink data package. If there is no acknowledgement, this new data will be retransmitted until the external control unit receives \(\mathrm{A_{C}}\) from the internal implant unit.