# Low Power QC-LDPC Decoder Based on Token Ring Architecture  
Mateusz Kuc  
1 Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland; wojciech.sulek@polsl.pl (W.S. ); dariusz.kania@polsl.pl (D.K. )1 Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland; wojciech.sulek@polsl.pl (W.S. ); dariusz.kania@polsl. mention the resulting environmental benefits. By limiting electricity consumption of designed devices, we reduce the negative impact on the environment, as well as reduce the cost of operating the device itself. There exists a relationship between the seemingly independent issues of reliable data transmission and the electricity consumption in data transmission systems. It results from the relationship between the power of the transmitted signal and the expected level of reliability (error rate), as well as from the fact that there are possibilities to limit the energy consumption of hardware systems implementing the advanced correction mechanisms. A properly designed system should ensure error-free data transfer, with the lowest possible consumption of electricity. Most of the published research works in the field of ECC focus on finding fast coding-decoding solutions. However, few works take into account the need to search also for energy-saving solutions. With the development of communication technology, many methods of ECC have been developed, with different levels of computational complexity on the one hand and error correction effectiveness (performance) on the other hand. One of the basic parameters characterizing the ECC coding system is the Bit Error Rate (BER), which quantifies the number of erroneous bits observed in the receiver to the total number of transmitted bits. Similarly, a Frame Error Rate (FER) indicates the relative number of observed erroneous data frames (blocks) in a coding scheme, for schemes that partition data into blocks (which is the case in a broad range of block coding methods). Low-Density Parity-Check (LDPC) codes are one of the best block ECC methods known today. They were first presented by R. G. Gallager Gallager (1999), but the computing technology available at that time did not allow for their practical use. In 1999, LDPC codes were recalled by D. J. C. MacKay MacKay (1999). The scientific community began to look for methods to simplify the algorithm for implementation in integrated circuits. The proposed simplifications enabled the use of LDPC codes in the telecommunication industry, for example, (DVB-S2) (Cheng et al., 2002; Wang et al., 2003), Ethernet 10 GBase-T (Cheng et al., 2003; Wang et al., 2004), 802.16e (WiMax) (Kang et al., 2004; Wang et al., 2005), 802.11 ad (WiGig) (Kang et al., 2004; Wang et al., 2005), 802.11n/ac/ax (WiFi) (Kang et al., 2004; Wang et al., 2005), GSFC-STD-9100 (NASA) (Kang et al., 2005) and recently 5G mobile (Wang et al., 2005; Wang et al., 2006). Along with the growing popularity of LDPC codes, the development of optimized LDPC codes and their decoding methods with improved performance is observed. Due to the high computational complexity of such effective solutions, the power consumption seems to be an important, but often neglected issue. Designing energy-efficient LDPC decoders calls for providing a system solution with power saving potential at several design stages. It seems that at each project level, specific techniques to reduce energy consumption can be used (Kang et al., 2004). Probably great benefits can be obtained by minimizing expected energy consumption at the system level. For example, we have found that it is possible to design the architecture with the possibility of involving elements responsible for power gating (Kang et al., 2004; Wang et al., 2005; Wang et al., 2006) of individual elements, or the clock gating (Kang et al., 2005; Wang et al., 2006; Wang et al., 2007).