## 2 Buck Converter Modeling
Figure 5: If \(i_{L}\) (blue line) crosses zero in a deadtime (dotted line), the time step dt is divided into two substeps and \(i_{L}\) is forced to zero at the end of the first substep (continuous line) until the end of the deadtime. Then, \(vC\) (red line) is also calculated at both substeps. ```
1:\((iL_{n+1},vC_{n+1})\leftarrow\textsc{calculateRK4}(iL_{n},vC_{n},dt,R,L,C,S1,S2,v_{s})\)
2:if\(sign(iL_{n+1})\
eq sign(iL_{n})\) AND \(S1=open\) AND \(S2=open\)then\(\triangleright\) iL crosses zero
3:\(dt1\gets dt\times abs(iL_{n})/(abs(iL_{n})+abs(iL_{n+1}))\)
4:\(dt2\gets dt-dt1\)
5:\((iL_{intermediate},vC_{intermediate})\leftarrow\textsc{calculateRK4}(iL_{n},vC_{n}, \textbf{dt1},R,L,C,S1,S2,v_{s})\)\(\triangleright\) first time step
6:\((iL_{n+1},vC_{n+1})\leftarrow\textsc{calculateRK4}(iL_{intermediate},vC_{intermediate},\textbf{dt2},R,L,C,S1,S2,v_{s})\)\(\triangleright\) 2 nd step
7:endif
```

**Algorithm 3** State variable calculation

An additional improvement can be identified upon considering the fact that after the first substep, \(iL_{intermediate}\) has a value of zero, because \(dt1\) has been calculated as the time it takes for \(iL\) to reach zero. The rounding errors coming from the calculation of the ratio \(dt1/dt\) and the calculations in the first call to calculateRK4 might deliver a value of \(iL\) at line 5 in Algorithm 3, which is very small but not zero. As the behavior of the model explained in Section 3 shows that \(iL\) must be zero if it reaches zero during a deadtime, an additional statement can be introduced to the algorithm, to set \(iL_{intermediate}\) to exactly zero at the end of the first substep, independently of the calculated value. The revised Algorithm 4 contains this statement. ```
1:\((iL_{n+1},vC_{n+1})\leftarrow\textsc{calculateRK4}(iL_{n},vC_{n},dt,R,L,C,S1,S2,v_{s})\)
2:if\(sign(iL_{n+1})\
eq sign(iL_{n})\) AND \(S1=open\) AND \(S2=open\)then
3:\(dt1\gets dt\times abs(iL_{n})/(abs(iL_{n})+abs(iL_{n+1}))\)
4:\(dt2\gets dt-dt1\)
5:\((iL_{intermediate},vC_{intermediate})\leftarrow\textsc{calculateRK4}(iL_{n},vC_{n}, \textbf{dt1},R,L,C,S1,S2,v_{s})\)
6:\(iL_{intermediate}\gets 0\)
7:\((iL_{n+1},vC_{n+1})\leftarrow\textsc{calculateRK4}(iL_{intermediate},vC_{ intermediate},\textbf{dt2},R,L,C,S1,S2,v_{s})\)
8:endif
```

**Algorithm 4** Improved substep calculation

## 5 Simulation and Implementation Results

### Floating-Point Simulations

The proposed method was simulated in MATLAB (Mathworks, Natick, MA, USA) using 64-bit floating-point arithmetic and in VHDL using both 64-bit floating-point arithmetic and fixed point. The fixed-point implementation uses IEEE sfixed package available in VHDL-2008. Division in VHDL was implemented with IP cores from the Vivado tool (Xilinx Inc, San Jose, CA, USA), which provides both floating-point and fixed-point dividers. The initial VHDL implementation of the numerical calculations follows the architecture of the proposed pseudo-code. The VHDL component contains a procedure and two processes. The procedure mirrors the calculations of Algorithm 1. One process follows the logic proposed in Algorithm 4, calling the procedure for evaluation of the intermediate values of \(iL\) and \(vC\) and if necessary calculating the division and making two additional calls to the procedure. A second process performs the assignment of the calculated values to the synchronous signals.