# A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Sredes Receiver
## 4 Simulation Results  
Figure 12 shows all setups for the whole DSP verification. The verification of the design is through Simulink and Modelsim co-simulation, import the RTL code required by the design in Modelsim and compile, and then on Simulink through the oscilloscope display to observe the data. The input data of this design is generated by Maltab program, and the pseudo-random binary sequence (PRBS) generated by Matlab program is applied to the channel characterized by S21, and then the output data of Matlab is written into the txt document. Then the data of the document is sampled by simulating the sampling method of ADC in testbench file, and finally it is used as the input of the design. Figure 13 displays the adopted channel spectrums that are extracted from practical PCB traces. After the channel, the data are sampled and digitalized by an ideal ADC. These digitalized data are finally applied to the developed DSP. Figure 14 shows the equalized eye diagram before slices when operating at 100 Gb/s using a 33-dB loss channel at the Nyquist frequency (see Figure 13). It can be seen that the eye height achieves around 15. Figure 15a,b separately give the convergence process of the FFE and DFE at 100 Gb/s with a 33-dB channel loss at the Nyquist frequency. As depicted, the FFE tap coefficients become stable within 5 us, while the DFE coefficients need 15 us to get convergence. This convergence-speed setup can effectively prevent mutual pulling between these two loops. Figure 11: Trend of vertical eye closure and vertical eye-opening ratio with attenuation. (**a**) VEC. (**b**) VEOR. Figure 12: The verification structure. Figure 13: The S21 for channels. Table 4 summarizes the performance of the DSP in this design and compares it to other DSPs running PAM4 receivers over 56 Gb/s. Clearly, the DSP field has an area advantage compared to [10], which also uses a 28-nm process. In addition, the DSP power consumption of this design is 7.2 pJ/bit, which is higher than the DSP power consumption of [1; 13], but the 7 nm FinFET process is used in the design of [1; 13], compared with 28 nm is more advanced. In the design of [10], only 2-tap FFE is used, which greatly reduces the number of taps compared to this design. Therefore, the power consumption of [10] has a large advantage in the 28 nm process. In addition, the 33 dB equalization capability of this design is also competitive with other designs. \begin{table}
\begin{tabular}{l l l l l} \hline \hline
**References** & **This Work** & [10] & [13] & [1] \\ \hline Technology & 28 nm CMOS & 28 nm CMOS & 7 nm FinFET & 7 nm FinFET \\ Data rate & 100 Gb/s & 100 Gb/s & 112 Gb/s & 134 Gb/s \\ Data formate & PAM4 & PAM4 & PAM4 & PAM4 \\ Equalization & 16-tap FFE,1-tap DFE & 2-tap FFE,2-tap DFE & 32-tap FFE,1-tap DFE & CTLE,16-tap FFE,1-tap DFE \\ Channel & 33 dB & - & 35 dB & 33 dB \\ Area & 1.2 mm\({}^{2}\) & 5.5 mm\({}^{2}\) & - & 0.383 mm\({}^{2}\) \\ Supply & 0.9 V & - & 0.75 V/0.9 V/1.2 V & 0.88 V/1.2 V/1.5 V \\ DSP power efficiency & 7.22 pJ/bit & 3.9 pJ/bit & 3.0 pJ/bit & 5.1 pJ/bit \\ BER & \(1\times 10^{-8}\) & - & \(1\times 10^{-9}\) & \(1\times 10^{-6}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 4: PAM4 receiver performance comparisons. Figure 14: The eye diagram in 100 Gb/s \(-\)33 dB. Figure 15: LMS FFE/DFE coefficients in 100 Gb/s \(-\)33 dB. (a) FFE coefficients. (b) DFE coefficient. Finally, we successfully realized the DSP chip applied to the Serdes receiver on the 28 nm process node. Figure 16 gives the layout of the whole system, and Figure 17 is the micrograph of the chip, where the DSP is located at the right bottom. From the simulation results and comparison with other designs, it can be concluded that the design has certain advantages on the 28 nm process node. However, it is worth noting that by optimizing the algorithm in DSP, the power consumption of the whole system can be reduced, but the balancing time will be increased.