# Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate
## 3 Result and Discussion
### SPICE Compatible Compact Modeling  
To analyze the reliability of the inverter operation, compact modeling of the load/driver transistors during the DC and AC bias should be studied. From the inverter schematic in Figure 2a, it is known that the CS condition dominates for the load transistor in which V\({}_{\text{GS}}\) and V\({}_{\text{DS}}\) are simultaneously applied, while the PBS condition dominates for the driver transistor. To implement experimentally the CS/PBS stress and recovery conditions, the change of the transfer curve was observed for up to 1800 s in each case. The width (W) and length (L) of the load transistor were designed as W/L = 5/50 \(\upmu\)m and of the driver transistor were designed as W/L = 50/5 \(\upmu\)m. Additionally, different V\({}_{\text{GS}}\) and V\({}_{\text{DS}}\) bias conditions ranging from 4 V to 8 V were applied to see the change of device characteristics in accordance with the applied voltage. The transfer curve change over time when 4 V and 7 V of V\({}_{\text{GS}}\) and V\({}_{\text{DS}}\) were applied (i.e., CS condition) to the load transistor in a flat state is shown in Figure 3a,b, respectively. The threshold voltage shift (\(\Delta V_{T}\)) depending on the stress and recovery time is summarized in Figure 3c. Meanwhile, the transfer curve changes and the summarized \(\Delta V_{T}\) when the load transistor was in a bending condition are shown in Figure 3d-f.  
From the measurement results, it can be seen that a positive \(\Delta V_{T}\) and a negative \(\Delta V_{T}\) were mixed under stress and recovery conditions, and the trend changed for various voltages. In general, when electron trapping occurs in the gate insulator, a positive \(\Delta V_{T}\) occurs because more gate bias is required for the same channel charge, and the opposite phenomenon occurs when de-trapping takes place. As mentioned above and in other studies [18; 19; 20; 21; 22; 23], the hydrogen migration takes place opposite to the electron trapping by H  
Figure 3: Threshold voltage shift (\(\Delta V_{T}\)) of load transistors in flat and bending conditions. (**a**) Transfer curve change in flat conditions when V\({}_{\text{GS}}\) = V\({}_{\text{DS}}\) = 4 V and (**b**) when V\({}_{\text{GS}}\) = V\({}_{\text{DS}}\) = 7 V. (**c**) Summarized \(\Delta V_{T}\) of flat load transistors depending on the stress and recovery time. (**d**) Transfer curve change in bending radius of 10 mm when V\({}_{\text{GS}}\) = V\({}_{\text{DS}}\) = 4 V, and (**e**) when V\({}_{\text{GS}}\) = V\({}_{\text{DS}}\) = 7 V. (**f**) Summarized \(\Delta V_{T}\) of bending load transistors depending on the stress and recovery time. cations, which results in a negative \(\Delta V_{T}\) for the hydrogen migration and a positive \(\Delta V_{T}\) for the recovery of hydrogen migration. For the flat load transistors, as shown in Figure 3c, the largest positive \(\Delta V_{T}\) was observed in low-voltage stress, which is attributed to the dominant electron trapping. In the recovery condition, the total amount of charge contributed by the recovery of hydrogen migration is dominant, which results in a positive \(\Delta V_{T}\). The measurement results in the bending condition were similar, as shown in Figure 3d-f. The larger \(\Delta V_{T}\) range is attributed to the increased oxygen vacancy during the tensile stress along the channel direction, which can increase the hydrogen migration [28; 29]. The \(\Delta V_{T}\) over time for the driver transistors in the PBS stress/recovery conditions is shown in Figure 4. The biggest difference from the result of the load transistor in Figure 3 is that, because there is no drain bias, electrons and hydrogens move only with gate bias. This could enhance the effect of V\({}_{\text{CS}}\) bias throughout the entire channel region. The driver transistors in the flat state are shown in Figure 4a-c, while those for the bending condition are shown in Figure 4d-f.