## 4 Experimental Results and Hardware Implementation
Taking \(f_{-2}\wedge\overline{f_{-3}}\wedge\overline{f_{-4}}\wedge\overline{f_{-5}}\) in Equation (12) as an example, \(f_{-2}/(\overline{f_{-3}}\wedge\overline{f_{-4}}\vee\overline{f_{-5}})\) can be used to save two gate-counts. Hence, the hardware cost of the proposed eADP-efficient antilogarithmic converters can be significantly reduced by the proposed algorithm of the fractional-bit compensation, Karnaugh map and [PERSON]'s law of logic circuits. \begin{table}
\begin{tabular}{l c c c} \hline \hline \multirow{2}{*}{**Compared Items**} & **[PERSON] \& [PERSON]** & **[PERSON] \& [PERSON]** & **Proposed** \\  & [5,16] & [16] & **Case 2** \\ \hline \multirow{2}{*}{**Compensation scheme**} & Shift-and-Add & Constant & **Fractional bits** \\  & 2 & 11 & **2** \\
**Significant fractional bit** & 7 & none & **none** \\
**Max. positive percentage error** & \(1.3310\%\) & \(1.7327\%\) & **1.7330\%** \\
**Min. negative percentage error** & \(-0.5631\%\) & \(-0.0992\%\) & **0** \\
**Total percentage conversion** & \(1.8941\%\) & \(1.8319\%\) & **1.7330\%** \\
**error** & \(1.8941\%\) & \(1.8319\%\) & **1.7330\%** \\
**Area (\(\upmu\)m\({}^{2}\))** & \(3562.57\) & \(2807.48\) & **1869.44** \\
**Delay (ns)** & 2 & 1.4 & **0.8** \\
**ADP** & \(7125.14\) & \(3930.47\) & **1495.55** \\
**ADP saving** & 0 & \(44.84\%\) & **79.01\%** \\
**eADP** & \(134.9573\) & \(71.2594\) & **25.9179** \\
**eADP saving** & 0 & \(47.20\%\) & **80.80\%** \\ \hline \hline \end{tabular}
\end{table} 
Table 10: Comparison of percentage conversion errors and results for proposed case 2 and [PERSON] and [PERSON]’s [5] two-region and [PERSON] and [PERSON]’s [16] 11-region schemes. \begin{table}
\begin{tabular}{l c c} \hline \hline \multirow{2}{*}{**Compensed Items**} & **[PERSON] et al. [13]** & **Proposed** \\  & **Case 1** \\ \hline \multirow{2}{*}{**Compensation scheme**} & Bit & **Fractional bits** \\  & 2 & **2** \\
**Significant fractional bit** & none & **none** \\
**Max. positive percentage error** & \(1.72\%\) & **1.9089\%** \\
**Min. negative percentage error** & \(-0.6\%\) & **0** \\
**Total percentage conversion error** & \(2.32\%\) & **1.9089\%** \\
**Area (\(\upmu\)m\({}^{2}\))** & \(1729.62\) & **1772.97** \\
**Delay (ns)** & \(0.7\) & **0.7** \\
**ADP** & \(1210.734\) & **1241.079** \\
**ADP saving** & 0 & \(-2.51\%\) \\
**eADP** & \(28.0890\) & **23.6910** \\
**eADP saving** & 0 & \(15.66\%\) \\ \hline \hline \end{tabular}
\end{table} 
Table 9: Comparison of percentage conversion errors and results for proposed case 1 and [PERSON] et al.’s [13] two-region bit correction schemes. The circuit block diagram for hardware implementation for the three cases is shown in Figure 10, where HS is a half subtractor, FS is a full subtractor, \(f_{-n}\) (where \(n=1\) to \(26\)) is the uncompensated fractional bit, and \(f_{-n}\)* (where \(n=1\) to \(26\)) is the compensated bit. Two regions (\(0\leq f<0.5\) and \(0.5\leq f<1\)) of the equations are selected by \(f_{-1}\). The block of logic gates for the compensation circuit (e.g., OR, AND, XOR, and NOT gates) incorporates the combinational logic in the numerators of the equations. In Figure 10, \(f_{1/16}\), \(f_{1/32}\), \(f_{1/64}\), and \(f_{1/128}\) are the compensated output values of \(1/16\), \(1/32\), \(1/64\), and \(1/128\) in Equations (10)-(12), respectively. For the DSP applications of cases 1, 2, and 3, the more fractional bits there are, the lower the maximum percentage error and approximation error will be. However, more fractional bits will lead to larger hardware area and longer delay time. Therefore, the maximum percentage conversion errors (1.9089%, 1.7330%, and 1.2063%) of cases 1, 2, and 3 can be individually adopted for the error tolerances of specific DSP, digital image processing, or AI applications. We should note that, in this study, the circuit block of Figure 10 is implemented using Verilog HDL code and the digital circuits are integrated by the Taiwan Semiconductor Manufacturing Company with 0.18 um CMOS technology.