## 3 Proposed Distributed Secondary Control Technique
### Case Four: Proposed Control DER Plug-and-Play Capability  
In this case study, we assess the functionality of the proposed control technique in terms of its DER plug-and-play capability. The simulation was divided into three stages and spanned a time frame of [0, 10] s. During \(t\in[0,3)\), representing the first stage, both the primary droop and secondary controls in each DER are in operation at \(t=0\) s, with load, \(R_{L1}\), \(R_{L2}\), and \(R_{L3}\), connected. DER 4 is disconnected at \(t=3\) s during the second \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Performance Metrics** & **At Stage 2** & **At Stage 3** & **Stage 4** \\  & **(\(t=2\) s)** & **(\(t=9\) s)** & **(\(t=16\) s)** \\ \hline \hline Settling Time & \(\leq\)0.1 s & \(\leq\)0.9 s & \(\leq\)0.9 s \\ \hline \hline Overshoot & 1.02\% & none & 6.66\% \\ \hline \hline Undershoot & none & 6.25\% & none \\ \hline \hline \end{tabular}
\end{table} 
Table 7: FDSC transient response at the DC bus voltage under case three. Figure 17: Currents output of DERs under CPL. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & & \begin{tabular}{c} **Stage 1** \\ \((t\in[0,2))\) \\ \end{tabular} & \begin{tabular}{c} **Stage 2** \\ \((t\in(2,9))\) \\ \end{tabular} & \begin{tabular}{c} **Stage 3** \\ \((t\in(9,16))\) \\ \end{tabular} & \begin{tabular}{c} **Stage 4** \\ \((t\in(16,26])\) \\ \end{tabular} \\ \hline \hline DER 1 & \begin{tabular}{c} Output Current \\ \end{tabular} & 4.7 A & 4.8 A & 5.8 A & 4.8 A \\ \cline{2-6}  & \begin{tabular}{c} Output Voltage \\ \end{tabular} & 43.2 V & 49.0 V & 49.0 V & 49.0 V \\ \hline \hline DER 2 & \begin{tabular}{c} Output Current \\ \end{tabular} & 4.0A & 4.8 A & 5.8 A & 4.8A \\ \cline{2-6}  & \begin{tabular}{c} Output Voltage \\ \end{tabular} & 43.9 V & 50.0 V & 50.2 V & 49.9 V \\ \hline \hline DER 3 & \begin{tabular}{c} Output Current \\ \end{tabular} & 3.8 A & 4.8 A & 5.8 A & 4.8A \\ \cline{2-6}  & \begin{tabular}{c} Output Voltage \\ \end{tabular} & 44.2 V & 50.5 V & 50.8 V & 50.4 V \\ \hline \hline DER 4 & \begin{tabular}{c} Output Current \\ \end{tabular} & 4.4 A & 4.8 A & 5.8 A & 4.8 A \\ \cline{2-6}  & \
\begin{tabular}{c} Output Voltage \\ \end{tabular} & 43.6 V & 49.5 V & 49.6 V & 49.4 V \\ \hline \hline DC Bus &
\begin{tabular}{c} Output Voltage \\ \end{tabular} & 42.3 V & 48 V & 48 V & 48 V \\ \hline \hline \end{tabular}
\end{table} 
Table 8: Voltage and current outputs of DERs under case three. Figure 18: Signal output of the proposed FDSC under CPL. stage, \(t\in(3,6)\), and connected back at \(t=6\) during the third stage, \(t\in(6,9]\). The results obtained are shown in Figures 19-21 and interpreted into Tables 9 and 10. It is observed that the current output is balanced among the DERs, and the voltage is maintained at the nominal value during the first stage. During the second stage, as presented in Figure 19, the disconnection of DER 4 resulted in its current output to the MG becoming zero. At the same time, the current output of the other DERs is abruptly increased from 9.7 A to 12.5 A and the consensus is maintained without any current overshoot. The proposed FDSC, as seen in Figure 21, is able to act swiftly to maintain equal current sharing among the other active DERs operating within the MG, as needed. However, as shown in Figure 20a, the bus voltage recovers to its steady-state value after a short transient caused by the disconnection. As interpreted in Table 10, the transient with a voltage undershoot of 5.2% damped out swiftly within 0.9 s. Figures 20b and 21 further reveal that DER 4 went into standby mode, having an output voltage of 47.5 V and a zero correction signal when disconnected from the MG.  
Figure 19: Currents output of DERs under plug-and-play. Figure 20: (**a**) Common bus voltage; (**b**) Voltage output of DERs under plug-and-play.