## 1 Introduction  
Phased arrays are widely adopted in modern radio-frequency (RF)-integrated systems such as radar remote sensing and low-orbit broadband satellite communication applications due to their high-precision beam pointing, fast beam synthesis and scanning capabilities [1, 2]. These superior characteristics result from the transmit/receive (T/R) components in each antenna unit. As one of the critical modules in phased-array T/R design, the amplitude control circuits play an indispensable role in tuning the link gain variation and suppressing the sidelobes [3, 4, 5, 6]. Typically, its realizations can be classified as active-type [7] and passive-type categories [8], which should be determined on the basis of system specifications and performance requirements, including insertion loss (IL), resolution, tuning range, operating bandwidth, amplitude/phase error, and compactness. Compared to the method using a variable gain amplifier (VGA), the main-stream solutions prefer digital-step attenuator (DSA) since it offers high linearity, high switching speed, bidirectional wideband operation and fine amplitude control without any power consumption [9, 10]. Currently, there is still a wide demand for single DSA designs for the following applications: (1) novel topologies specifically studied for DSAs to improve their RF performance [6, 8, 11], which do not need to be integrated with other functional chips; (2) Off-chipintegration is required for wideband multimode multichannel receiver systems where several narrowband signals are multiplexed through a common attenuator; (3) Attenuator-first software-defined radios (SDRs) for communication infrastructure require a single MMIC DSA solution [12]; and (4) Customized DSA chip designs based on customer requirements for different bands. Several common passive DSA topologies have been reported in the literature [11; 12; 13; 14; 15; 16; 17], including distributed [11; 13], switched-path [14], and switched T-/\(\pi\)-/bridge T-type [15; 16; 17], as illustrated in Figure 1. These networks form a two-state architecture with selectable insertion paths through controlled RF switches, where the difference between the ILs of the respective states is the desired attenuation value [18]. Compared to the distributed structure exhibited in Figure 1d, other topologies with the advantages of a larger attenuation range and smaller chip area are preferred. However, with regards to a high-frequency broadband attenuator design, these structures critically suffer, gradually increasing amplitude/phase variations, which restrict the operating bandwidth of traditional DSAs [19]. Moreover, especially when cascading multi-stage units, the inter-stage impedance mismatch leads to further worsening of the property. In order to address this issue, the literature [20; 21; 22; 23] elucidates the compensation methods and effects of \(\pi\)-type, T-type, bridge T-type and distributed structures, and verifies the principle under different technologies. Nevertheless, this solution still suffers from a high attenuator IL due to the presence of the transistor lossy resistance \(R_{on}\) in the reference state, which is the reason why switching path designs should be adopted with caution [5]. To put it simply, this high-precision compensation approach comes at the cost of a high IL. Therefore, the realization of the amplitude tuning capability with accurate phase compensation while simultaneously maintaining compactness and low IL is an issue that needs to be addressed. Furthermore, the characteristic of RF switches also constitutes majorly to the attenuator performance. These switches are achieved by utilizing CMOS [24; 25], BJT/HBT [26; 27], and HEMT [28; 29] transistors. Among the numerous processes available, the GaAs pseudomorphic high-electron mobility transistor (p-HEMT) process is generally preferred due to its low switching loss and high isolation.