# Logic Synthesis Strategy Oriented to Low Power Optimization
## 3 A Synthesis Method Aimed at Minimizing Power Consumption  
Power in digital systems can be divided into static power _Pstat_ and dynamic power _Pdyn_ (2):  
\[\textit{Pdev}=\textit{Pstat}+\textit{Pdyn} \tag{2}\]  
The static power _Pstat_ depends on the technology of making the digital circuit. This power depends on many factors such as: gate leakage, drain junction leakage, sub-threshold current, i.e., a number of technological parameters. In the case of FPGAs, the designer has minimal possibilities to limit static power consumption in the process of designing the implemented circuit. It can only look for an FPGA chip that will ensure minimal static power consumption. In the case of dynamic power _Pdyn_, the designer has a much greater impact on reducing power dissipation. The dynamic power is expressed with the relationship (3):  
\[P_{dyn}=\frac{1}{2}V_{dd}^{2}f\sum_{i=1}^{n}C_{i}SW_{i} \tag{3}\]  
It is clearly visible that dynamic power depends on a number of factors. The main factor that allows the dynamic power to be limited is to reduce the supply voltage _Vdd_. Unfortunately, it is practically impossible to limit the supply voltage in FPGAs. Another factor influencing the dynamic power is the frequency of the clock signal \(f\). Naturally, it is possible to imagine a local decrease in the clock frequency, although it should be remembered that, as a rule, the aim is to design structures as fast as possible, which means that this method usually cannot be used. The implemented logic structure resulting from decomposition is usually a logic network composed in the general case of n nodes. In the case of FPGAs, the nodes of this network correspond to the LUTs. The internal capacity _Ci_ can be associated with the lines corresponding to the connections between the nodes of the network. This capacity must be reloaded each time in the process of switching logic states, which, of course, has an impact on dynamic power consumption. The value of the capacitance _Ci_ can be treated individually due to the same technology of making the entire FPGA matrix. Therefore, it becomes crucial to determine how often this capacity is reloaded, i.e., the state changes to the opposite one in the _i_-th node. It is determined by introducing an additional _SWi_ parameter into Formula (3), i.e., switching activity for each node. Thus, it can be concluded that limiting the switching activity for as many nodes of the logic network as possible should lead to the limitation of dynamic power dissipation. Thus, the idea of limiting switching activity appears at the stage of designing the implemented structure. However, a problem arises as to how to take into account the  
Figure 3: Technology mapping of the xor function in three inputs LUTs: BDD in the next steps of decomposition (**a**–**d**), the result of technology mapping (**e**). The ideas presented may be, depending on the strategy, aimed at minimizing the number of blocks or minimizing the number of logical levels. The main drawback of these approaches is the complete disregard of power consumption.  
limitations of \(SW\) in low-level stages of synthesis, such as decomposition or technological mapping. In order to solve this problem, it becomes necessary to develop an appropriate form of description of a logic function, taking into account the parameter expressions in the description.