# A Novel Top-Down Fabrication Process for Vertically-Stacked Silicon-Nanowire Array
## 2 Fabrication Process  
The major challenge during the monolithic fabrication of a vertically-stacked silicon-nanowire array is the isolation between the layers of laterally-aligned silicon nanowires. To address this challenge, the fabrication process proposed in this paper is based on the Bosch process [23], which is used to fabricate anisotropic structures with high aspect ratios. In the Bosch process, by controlling the etching time for the isotropic-silicon etching step, it is possible to define the fabrication region of the silicon nanowire as well as the region where the isolation layer is fabricated. By using the wet-oxidation process, which consumes silicon in order to produce silicon-dioxide (SiO\({}_{2}\)) and results in the insulation layer, vertical isolation between the upper and lower layers is achieved. Based on this concept, the top-down fabrication proposed in this paper is depicted in Figure 2. As previously mentioned, it uses a combination of photolithography, DRIE, and a wet-oxidation process. Moreover, a p-type (111)-oriented single-crystalline silicon wafer is used, which has a diameter of 100 mm, a thickness of 525 \(\upmu\)m, and a resistivity of 1-10 \(\Omega\)-cm. The reason for using (111)-silicon instead of the commonly used (100)-silicon is to allow the current to flow through the silicon nanowires rather than the bulk silicon part. In fact, (100)-silicon can also be used to fabricate laterally-aligned silicon-nanowire arrays, as our group has also reported in previous publication [5]. However, in the case of (100)-silicon, only a single layer can be manufactured due to the orientation of the [111] plane and the wet etching characteristics of the silicon. In this paper, we need to implement a multiple layer-stacked array of silicon nanowires and isolate them from the silicon bulk. The (111) silicon is suitable for isolating the nanowire from the substrate because the silicon is rapidly etched sideways during wet etching [6]. This facilitates the isolation of multilayered-nanowire array structures from the silicon bulk. First, as shown in Figure 2a, an oxide-mask layer (3000 A thick) is deposited by a plasma-enhanced chemical vapor deposition (PECVD) process, with a radio frequency (RF) power of 350 W, an O\({}_{2}\) flow rate of 150 sccm, and a tetraethyl-orthosilicate (TEOS) flow rate of 150 sccm. The TEOS layer is used as a passivation hard mask for bulk silicon etching. A GRX-601 (AZ Electronic Materials, Luxembourg) photoresist (PR) film is spin-coated on the TEOS layer with a rotation speed of 4000 rpm and exposed to a UV light source with a wavelength of 365 nm for 3.1 s. Following the exposure, the PR is developed in an AZ 300 MIF developer for 18 s and then rinsed in deionized (DI) water, as shown in Figure 2b. The photolithography step defines the in-plane dimension of the silicon-nanowire arrays, such as the pattern width and length. Figure 1: Previously reported silicon-nanowire array fabricated by top-down processes. (**a**) (100) silicon-nanowire array [5] (Reproduced with permission from [PERSON] et al., Sensors and Materials; published by MY K.K., 2012); (**b**) (111) silicon-nanowire array [6] (Reproduced with permission from [PERSON] et al., Journal of Micromechanics and Microengineering; published by IOP Publishing 2014). After PR patterning, the TEOS hard-mask layer is etched by an inductive-coupled plasma (ICP) etcher with a CHF3 flow rate of 25 sccm, a CF4 flow rate of 5 sccm, and a pressure of 130 mTorr with an RF power of 600 W, as depicted in Figure 2c. The target etching thickness of the TEOS layer is calculated to be approximately 110% of the deposited thickness, which guarantees the exposure of the silicon surface. As shown in Figure 2d, after the PR strip step, a piranha solution (a mixture of sulfuric acid and hydrogen peroxide) cleaning process and an O2 plasma ashing process are conducted to remove the residuals. In Figure 2e, the bulk silicon is etched using a cyclic DRIE process, which consists of a single deposition step and two etching steps.