# Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications
## 4 All-Digital Frequency Synthesiser for Multiband Transceivers
cyclically shift within switched-capacitor bank) unit-weighted mismatched components, so that averaged in time equivalent values of these components would be equal. From the discussion in chapters 2 and 3 it is seen that quantisation noise of the TDC depends on delay of the inverter. Actually, delay of the inverter is equal to the resolution of the commonly used TDC, which is based on the inverter delay line. This delay can be reduced by increasing its driving strength, together with increasing its power consumption. Table 1 shows modelling results of inverter's delay (\(\tau_{\text{inv}}\)) in 65 nm CMOS technology at different load capacitance (\(C_{\text{L}}\)) and ratio of width and length (\(W_{\text{n}}/L\)) of used transistors. Length of all transistors was set to the minimum value in  
Figure 8: Structure of 5 GHz LC digitally controlled oscillator. current technology (60 nm) and width of NMOS transistors (\(W_{\text{n}}\)) was set to 4, 8 and 16 \(\upmu\)m. Width of PMOS transistor is always set to double of NMOS, i.e., \(W_{\text{p}}=2W_{\text{n}}\). It is seen from Table 1 that even when greatly increasing the driving strength of an inverter, it remains challenging to achieve lower than 12 ps delay of an inverter. It is obvious that other negative results of such an approach are a rapidly increasing used area of silicon. Therefore, the more advanced structure of TDC should be used. High resolution of TDC is achieved by using 2D Vernier TDC based on gated ring oscillators, which was presented in our previous works [27; 28] and shown in Figure 9a. Such TDC allows us to measure the time interval, which is lower than delay of the inverter. Main blocks of this TDCs are two gated ring oscillators, which are used as infinite delay lines, lap and edge counters of both oscillators, matrix of arbiters, control block and output decoder. The resolution of such TDC is defined as difference of delay of stages from which two oscillators are made. To have the ability to control the resolution of TDC, stage delay of oscillator (and its corresponding oscillation frequency) should also be controllable. For this reason, each oscillator is made of parallel-connected oscillator sections, as shown in Figure 9b. Stage delay is decreasing when additional sections of the oscillator are enabled. At the beginning of the measurement, TDC is waiting for the rising edge of the reference signal. When it is received, the lower frequency gated ring oscillator and its lap counter are started. After that \begin{table}
\begin{tabular}{c c c c} \hline \hline \multirow{2}{*}{\(\mathbf{C_{L}}\) **f**} & \multicolumn{3}{c}{\(\mathbf{\tau_{inv}}\)**, ps**} \\ \cline{2-4}  & \(W_{\text{n}}\)/**\(L\) = 66.67** & \(W_{\text{n}}\)/**\(L\) = 133.33** & \(W_{\text{n}}\)/**\(L\) = 266.67** \\ \hline
10 & 10.49 & 8.97 & 8.28 \\
20 & 12.94 & 10.26 & 8.90 \\
30 & 15.33 & 11.49 & 9.59 \\
40 & 17.69 & 12.72 & 10.22 \\
50 & 20.04 & 13.91 & 10.82 \\
60 & 22.37 & 15.13 & 11.46 \\
70 & 24.63 & 16.33 & 12.10 \\
80 & 26.79 & 17.50 & 12.71 \\
90 & 28.84 & 18.68 & 13.30 \\
100 & 30.76 & 19.85 & 13.88 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Modeling results of dependency of inverter’s delay time on load capacitance and ratio of width and length of transistors in 65 nm CMOS technology. Figure 9: (a) Structure of proposed 2D Vernier time to digital converter based on gated ring oscillators. GROL—lower frequency oscillator, GROH—higher frequency oscillator; (b) Structure of gated ring oscillators used in TDC. TDC is waiting for the rising edge of the DCO signal. When it is received, the state of lower frequency oscillator is saved, and the higher frequency oscillator and its edge counter are started. When both oscillators are started, the output signals of arbiters are monitored. When the output of any arbiter changes to a high level, it means that the higher frequency oscillator has caught up with the lower frequency oscillator. The position of that arbiter is located and depending on that position, the output signal of TDC is decoded.