# Architecture and Process Integration Overview of 3D NAND Flash Technologies
## 2 Three-Dimensional NAND Flash Architectures
All the WLs are exposed on the same plane simultaneously during the chemical-mechanical planarization (CMP) process. The WLs do not need to be etched consecutively for each layer, unlike in a stair-like method, which implies that the PIPE structure increases the efficiency of the WL interconnection without an additional lithography step after stacking. The VSAT is aimed at solving the difficulties in the fabrication of the VRAT structure, as shown in Figure 5b. Instead of the gate-last process, in which an undercut region is formed and filled, the VSAT structure is fabricated using the gate-first method with doped poly-Si. Because the undercut process is not required for the VSAT structure, it is easy to realize vertical strings along with the stacked WLs, which are similar to the currently commercialized 3D NAND flash string. In addition, the dual-gate structure of the VSAT architecture effectively elongates the channel length without cell density loss, leading to a reduction in the off-current [5; 33; 34; 35]. A schematic and unit cell diagram of the VG NAND structure are illustrated in Figure 6[6]. Here, the channels are horizontally stacked, unlike in the BiCS and TCAT structures, and it has an almost identical structure to that of a planar flash array, except for the SSL, which means that the effective cell size per layer is maintained as 4F\({}^{2}\). The source and the active body (\(V_{\text{bb}}\)) are connected to the CSL, enabling the body erase operation, and the required number of SSLs depends on the number of active layers. Common BLs and WLs are used between the stacked active channel layers, and a string needs to be selected to program a specific target cell by SSL biasing. Figure 4: (**a**) Cross-section view and (**b**) equivalent circuit diagram of TCAT flash array structure. Unlike the above-mentioned approaches, a floating gate is used as the charge storage layer in the DC-SF structure, as shown in Figure 7a [8]. In this structure, an FG is surrounded by two CGs and covered by an inter-poly dielectric (IPD) and a tunneling oxide. It consists of two CGs and presents a vertical direction. Owing to the thick IPD layer, no tunneling occurs in the CG direction. In addition, a charge spreading phenomenon rarely occurs thanks to the isolated charge in the FG, unlike in the BiCS, as shown in Figure 7b. In the case of the BiCS, charge spreading occurs because the CTL is connected successively to the adjacent cells, while it does not occur in the DC-SF, because the FG is separated and isolated from each cell. Moreover, cell-to-cell interference is negligible, owing to the shielding effect of the two CGs. It also has a wide program/erase window, low operating voltage, and high coupling ratio. The DC-SF can have good retention characteristics by using the FG; however, it is not advantageous for 3D stacking due to a thicker memory film than CTL, which limits the scaling of channel hole dimension. Figure 5: Schematics of (**a**) VRAT and (**b**) VSAT with PIPE structure. Figure 6: Schematic of VG NAND flash array [6], Copyright IEEE, 2009. Another 3D NAND structure with an FG is the HC-FG structure, as shown in Figure 8a [3]. Unlike in the DC-SF structure, horizontal channels are stacked in the HC-FG architecture; however, the unit cell is not surrounded by CGs. Consequently, the FG cells can be stacked by the channel-first process, similar to that in a conventional 2D planar flash array, and a 3D structure can be implemented at a low cost. In addition, the HC-FG structure is combined with a layer select transistor (LST), as shown in Figure 8b, to enable additional bit cost scaling. The HC-FG and LST structures are connected via an SSL and share the gate electrodes. The LST structure requires a simple and low-cost process, because impurity regions can be incorporated simultaneously using a self-aligned method, owing to a stair-like structure. The VG NAND architecture has both WL and SSL in the same active layer; therefore, the cell density becomes worse as the stack layer increases.