# An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder
## 3 The Proposed Decoder Architecture
### Check Node Unit  
The main task of the CNU is to calculate the CTV messages (\(\beta_{m,n}\)). On the hardware aspect, conventional algorithms need to determine the two minimum values of the VTC input signals and the index of the first minimum. In this work, the HOMS method simply requires the first minimum of incoming VTC messages and its index. It is the competitive advantage of the proposed architecture, which may reduce the hardware resources. In addition, to reduce CN-MB storage space, CTV messages are compressed as shown in Figure 3. For a current check node, the CTV messages, named compressed \(\beta-\)messages, are represented in the format of \(q-1+\lceil\log_{2}(d_{\text{cmax}})\rceil+d_{\text{cmax}}=27\) bits. It is important to note that each conventional \(\beta\)-message includes \(2\cdot(q-1)+\lceil\log_{2}(d_{\text{cmax}})\rceil+d_{\text{cmax}}=30\) bits.  
Each CNU has \(d_{\text{cmax}}\) inputs, and each one has \(Z\times q=768\) bits. As a result, each CNU block really contains \(Z\) computing units that are utilized to compute the \(Z\) check nodes within a single row of the BG1 matrix in parallel. Each layer of these \(d_{\text{cmax}}\) CNNs produces \(Z\times(q-1+\lceil\log_{2}{(d_{\text{cmax}})}\rceil+d_{\text{cmax}})=5184\)-bit extrinsic CTV messages and delivers to CN-MB.  
As illustrated in Figure 4, the proposed CNU architecture consists of \(d_{\text{cmax}}\) multiplexer units, a Min & Index Finder, a sign unit, and some control signals. In this design, we suppose that all check nodes have the same degree, which is represented by \(d_{\text{cmax}}\). To support irregular 5G LDPC codes, some additional control logic (i.e., a set signal) is used. More precisely, in the case of check node degree \(d_{c}<d_{\text{cmax}}\), \"inactivate\" (set = '0') refers to setting the last \((d_{\text{cmax}}-d_{c})\) to the maximum value (\(2^{q-1}-1=+7\) including the sign bit). Multiplexers are set up at the inputs to choose the input message based on either the \"real\" VTC message (\(\alpha_{m,n}\)) or the maximum value. To find the first minimum (\(min1\)) and its index (\(index\_min1\)), the CNU is constructed by applying the effective Tree-Structure (TS) technique suggested in [27]. The structure of the CNU is described in more detail in Figure 4. The Most Significant Bits (MSBs) of the \(d_{\text{cmax}}\) VTC messages are XORed to generate a sign bit, and the remaining (\(q-1\))-bits of these are processed by the Min & Index finder to find \(min1\) and its index. The \(d_{\text{cmax}}\) inputs of Min & Index finder can be split down into the sum of 16 and 3 inputs. As a result, the \(d_{\text{cmax}}\)-mVU (minimum Value Unit) is achieved by combining the corresponding blocks similar to the TS approach used in [27]. The 2-mVU includes one multiplex and one comparator, as illustrated in Figure 5a. The architecture of the 3-mVU consists of two 2-mVU for finding the minimum value and its index, as depicted in Figure 5b. The 16-mVU (or 24-mVU) can be constructed from the 2-mVU. The Index Generator (IG) block is used to compute the \(index\_min1\). This IG block uses the same methodology as in [27].  
Figure 3: Presentation of the check-to-variable node message in compressed and uncompressed formats.