## 5 Simulation and Validation  
To validate the proposed mixed-mode filter, it was designed and simulated in Cadence Virtuoso design software. The VD-EXCCII was designed in 0.18 \(\upmu\)m Silterra Malaysia technology at a supply voltage of \(\pm 1.25\) V. The width and length of the transistors used are given in Table 5. The layout of the VD-EXCCII as presented in Figure 6 was drawn using the nhp and php high-performance MOS transistors from the Silterra library, and the layout verification was done using the Calibre tool. The layout occupied a total area of 54.28 \(\times\) 22.80 \(\upmu\)m\({}^{2}\). The bias current of the OTA was fixed at 120 \(\upmu\)A resulting in transconductance of 1.0321 mS. The important design parameters were extracted from post-layout simulations and are summarized in Table 6.  
The proposed filter was tested by designing for a center frequency of 8.0844 MHz and quality factor of 1.015 by selecting the passive component as \(R_{1}=R_{2}=R_{3}=1\) k\(\Omega\), \(C_{1}~{}=~{}C_{2}=20\) pF and \(g_{m1}~{}=1.0321\) mS. The power dissipation of the filter was found to be 5.76 mW. The five filter responses in VM, CM, TAM and TIM modes are presented in Figures 7-10. Figure 6: Layout of the VD-EXCCII. Figure 7: VM MISO configuration: (**a**) frequency responses of the LP, BP, HP and BR filter and (**b**) gain and phase responses of the AP filter. Figure 8: TAM MISO configuration: (**a**) frequency responses of the LP, BP, HP and BR filter and (**b**) gain and phase responses of the AP filter. Figure 10: TIM MISO configuration: (**a**) frequency responses of the LP, BP, HP and BR filter and (**b**) gain and phase responses of the AP filter. Figure 9: CM MISO configuration: (**a**) frequency responses of the LP, BP, HP, and BR filter and (**b**) gain and phase responses of the AP filter. To examine the signal processing capability of the proposed universal filter, the transient analysis was carried out in VM mode for HP, LP and BP responses. A VM sinusoidal signal of 100 mV\({}_{\text{P-P}}\) and a frequency of 8.0844 MHz was applied at the input, and the output was analyzed as presented in Figure 11. It can be inferred from the figure that the phase relation between the input and LP, BP and HP outputs of the filter are correct. In the presented filter, the quality factor can be set independent of the pole frequency of the filter, as is clear from Equations (17) and (18). The quality factor tunability was verified by analyzing the BP response in CM for different values of \(R_{2}\), as shown in Figure 12. It can be deduced from Figure 12b that the quality factor of the filter can be tuned linearly. The fitting equation using a linear regression with coefficient of determination \(R^{2}\) = 0.9832, which indicates the fraction of the fitting values that are closest to the line of reference data, is given in Figure 12. The pole frequency of the proposed filter can be tuned by varying the bias current of the OTA, as can be inferred from Equation (17). The tuning property is validated by plotting the VM-AP response for the different values of the OTA bias current, as shown in Table 6.0 The fitting equation using a power regression with \(R^{2}\) = 0.9962 is given in Figure 13b. Table 6.1 VM MISO configuration: transient analysis results for LP, BP and HP filter configurations. Table 6.2 CM MISO configuration: (**a**) frequency responses and (**b**) quality factor tuning for different resistor values in BP filter. To study the effect of process spread and the non-idealities of the capacitors employed on the performance of the designed filter, a Monte Carlo analysis is carried out for 200 runs. The Monte Carlo analysis results for the VM BP response are given in Table 6.3 The results for CM AP configuration are given Table 6.4 Corresponding histograms demonstrate the variations of the pole frequency at \(-180^{\circ}\). The results indicate that the frequency deviation of the filter is within acceptable limits. This further validates the robustness of the design.