# Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits
## 3 Fabrication and Integration with CMOS
Both the temporary handle and the transparent substrate are bonded using oxide-oxide bonding with no adhesive. The transfer process provides APD arrays that can then be quickly bumped to any CMOS readout chip that matches the format and pixel pitch. It is, however, a relatively complex process because of the two-step transfer involved. Lincoln Laboratory pioneered a 3D-integration process using its in-house fully depleted silicon-on-insulator (SOI) CMOS process. One of the first imager demonstrations was a 64 \(\times\) 64-pixel GMAPD array for lidar [13]. The APD was integrated with two tiers of SOI CMOS readout circuitry. Figure 4 illustrates the process. After APD and SOI CMOS fabrication is complete, the APD wafer (tier 1) and the first CMOS wafer (tier 2) are precision aligned and oxide bonded face to face. Then the SOI handle wafer is removed, using the SOI buried oxide as an etch stop. Concentric vias are then etched through the oxide layers and filled with tungsten to interconnect the last metal of the SOI wafer with the top metal of the APD wafer. These tungsten plugs are micron-scale in diameter and only a few microns in height, much smaller than bump bonds or through-silicon vias used in some wafer  
Figure 3: Transfer and bump bonding. stacking processes. The process can be repeated, adding the tier-3 CMOS wafer to the stack. Because the SOI handle wafer is removed, the process is amenable to multiple-tier structures. Figure 5 shows a cross-sectional micrograph of a pixel of the 64 \(\times\) 64-pixel GMAPD lidar imager. 3D integration is an important technology direction for advanced image sensors. In the device structure shown in Figure 5, tier 1 contains the photodetectors, tier 2 has first-level signal conditioning circuits, and tier 3 has high-speed logic for photon time stamping. The ability to divide the pixel circuitry among multiple tiers enables a sophisticated pixel circuit to fit into a smaller area than would be possible for a conventional 2D-integrated circuit. A tier could be dedicated to image processing functions to extract information at the pixel level and reduce readout bandwidth. Having multiple tiers also enables the designer to combine multiple circuit or device technologies into a single integrated device, as in Figure 5.  
Figure 4: Steps in the Lincoln 3D-integration process to integrate the APD wafer (tier 1) with the first SOI CMOS wafer (tier 2). Figure 5: Cross-sectional SEM through a pixel of the 64\(\times\)64 GMAPD array. The Lincoln 3D process is an example of a _via-last_ process. The connection via from each tier of SOI CMOS down to the previous tier is made after wafer bonding and SOI handle removal. This approach is amenable to multi-tier structures, but requires dedicated full-wafer SOI CMOS for each tier, with the exception of tier 1. One can also use a _via-first_ approach [14], illustrated in Figure 6. Metal posts (which perform the same function as bump bonds, but are much smaller) are patterned on each wafer and planarized along with the bonding oxide. When the wafers are bonded and then heated to strengthen the oxide-oxide bond, the posts expand and fuse. In a single step, therefore, mechanical bonding and electrical connection are achieved simultaneously. The CMOS wafer also functions as a permanent mechanical support for APD substrate removal, backside processing, and subsequent imager operation. The _via-first_ approach allows for the use of any CMOS process, although it is not easily extendable to multi-tier structures.