## 7 Discussion and Future Perspective
### Photonic Device  
Moving the optical interconnect from the switch front panel to the vicinity of the switch ASIC requires the fabrication of an I/O-specific chiplet. There are several designs used in different chiplet applications ranging from discrete, 4-lane SiP arrays to large 64-lanes devices, as described here. In terms of fabrication complexity, it is evident that the former approach shows better yield and process simplicity. However, the stringent space/power limitations expected in an actual 51 Tb/s switch favor the grouping of the optical devices in one large array that will enable both power and space-saving resulting from the combined device overhead.  
All L3 Matrix components have been designed having two important restrictions in mind: in terms of compatibility with high-volume manufacturing and with the CMOS technology. To this end, we have strictly utilized only CMOS-compatible materials and fabrication processes, and we have worked in close collaboration with AMS AG to only use processes that are compatible with their high-volume fabrication protocols.  
The L3 Matrix co-packaging technology demonstrated here is very versatile, and it can be potentially combined with other technologies, for example, with a 100 Gb/s modulation to intersect the 51 Tb/s switch generation in the future.  
It is worth mentioning that, moving one step further, we have exploited the optical devices designed in L3 MATRIX to develop a novel high-radix optical packet switch (OPS) architecture, named 'Hipo\(\lambda\)aos' [51]. This architecture provides low latency, high bandwidth and high radio connectivity towards meeting the requirements of End-of-Row (EoR) network architectures, and its feasibility is well documented in the literature [51; 52; 53; 54; 55; 56; 57; 58]. As a result, the proposed architecture can, by leveraging the L3 MATRIX large-scale SiP matrix with its low-power and low-cost credentials, lead to considerable power savings in conjunction with a significant decrease in the number of DC switching layers.  
Regarding the light source, there are two accepted approaches-integrated and external. Both have their pros and cons, specifically regarding thermal stability in the vicinity of the hot switch ASIC and assembly. We have decided to investigate the integrated approach  
Figure 21: The optical design of the 2-lens relay over a 10\({}^{\circ}\) grating coupler through the silicon substrate. The optical ray trace is shown in the upper figure and the fiber coupling efficiency from beam propagation on the right side. The lower image shows the bottom silicon lens array. Additional lenses are added to the 2 \(\times\) 8 array for mechanical support and process integrity.  
as it allows for efficient packaging that can be scaled even further to larger SiP matrices. Compared to the external laser source approach, integrated lasers have a \(\sim\)6 dB advantage in power efficiency as the coupling of light to and from the fiber is not required. The downside of this design is the reduced lifetime of the laser and its thermal instability. Reliability issues can be solved by the addition of redundant lasers to each cell or the same wavelength cell rows (see Figures 4 and 5). The lasers can be connected to each other using an MMI with the redundant laser enabled upon monitoring the degradation of the active one. The thermal instability issue is more difficult to handle. We have added 'dummy' laser structures on each CWDM row (4 cells) to compensate for thermal drifts. These problems are obviously not present with external laser banks, and more experimentation is required to address this problem.