## 3 Constant Power Load (CPL) Model  
Nowadays, CPLs have been recently used in MGs [14; 15; 16; 17; 18; 19; 20; 21; 22; 23; 24]. CPLs have two important characteristics: negative incremental resistance and control loop dynamic with a similar frequency range of the inverter [14]. The negative resistance property and the interaction between the DGs and CPLs reduce the system damping and lead to instability or unacceptable oscillatory responses [15]. Furthermore, the highly penetrated CPLs in an MG make the MG stability problem more sophisticated. The dynamic behavior of an MG challenges both stability and control effectiveness in the presence of CPLs. Several methods have been proposed to cope with the mentioned CPL instability [14; 15; 16; 17; 18; 19; 20; 21; 22; 23; 24]. The CPL circuit shown in Figure 4 is modeled in MATLAB. The model contains the rectifier bridge, DC load, LC filter, AC current, and DC voltage controllers, and PLL. The rectifier bridge is used to convert the AC into DC and feed the DC load. The AC current and DC voltage controllers are shown in Figure 5. The DC voltage controller is employed to control the DC voltage of the CPL and to generate the reference current of the current controller, while the current controller is utilized to control the AC inductor current and to generate the required rectifier pulses. The PLL depicted in Figure 6 is used to synchronize the CPLs with the MG, extract the phase angle, and deliver the reference voltage for the MG. To extract the grid frequency, one of the \(dq\) voltage components is devised to be constant. The \(q\)-component of the voltage of the point of common connection (PCC) and reference voltage are compared. The error signal is fed to the PI controller to generate the frequency. This frequency is compared with the reference frequency to extract the synchronized MG frequency. The synchronized frequency is integrated to obtain the inverter phase reference \(\theta\) needed to convert from \(abc\) to \(dq\) and vice versa, as given in (13).  
\[\omega=k_{p}^{PLL}(v_{\alpha q}-v_{\alpha q}^{*})+k_{l}^{PLL}\int{(v_{\alpha q }-v_{\alpha q}^{*})dt} \tag{12}\]  
\[\theta=\int{(\omega-\omega_{ref})dt}+\theta(0) \tag{13}\]  
where \(k_{p}^{PLL}\) and \(k_{l}^{PLL}\) are the PLL controller parameters.  
The common reference (\(DQ\)) frame of the whole MG, reference (\(dq_{i}\)) frame of each DGi, and reference (\(dq_{ALj}\)) frame of the jth CPL are shown in Figure 7. These frames are rotated at frequencies \(\omega_{com}\), \(\omega_{i}\), and \(\omega_{ALj}\), respectively. The angles \(\delta_{i}\) and \(\delta_{ALj}\) represent the angles between the DGi reference frame, CPL reference frame, and DQ frame, respectively. Each DG and CPL must be modeled on its rotating reference frame. DGs and CPLs share the MG DQ frame. The CPL current controller has the same state equations of the DG inverter. However, the CPL current has an opposite sign to the DG current because the CPL receives the current from the MG. The \(dq\) components of the inductor current are decoupled using the feed-forward as displayed in Figure 5. The CPLs state-space equations are given in (14)-(20).  
Figure 4: Constant power loads (CPL) circuit.