# Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
## 2 Proposed SRAM Structure and Operation Principles  
### Proposed SRAM Structure  
In this study, we introduce a novel 8 transistor (T) SRAM bit-cell architecture, as illustrated in Figure 1, which is designed to perform multiple operations including read, write, data storage, and binary multiplication. Traditional 6 transistor (6T) SRAM cells generally support basic read and write functions but are not inherently optimized for multiply-and-accumulate (MAC) operations, a function crucial in applications like in-memory computing (IMC). To overcome these limitations, the proposed bit-cell incorporates two additional transistors, a PMOS (P3) and an NMOS (N5), within the conventional 6T structure, expanding its functionality. These additional transistors enable the bit-cell to execute a bitwise AND operation (denoted as R2 in Figure 1) between an external input and a stored weight within the cell. This design modification supports computational functions at the memory level, improving efficiency for MAC operations directly within the memory array without relying on external processing units. The 8T SRAM bit-cell structure is compact, maintaining a balance between area efficiency and operational stability. The incorporation of additional transistors is carefully engineered to ensure that the physical area of the bit-cell remains manageable, thus maintaining high memory density. Stability during read and MAC operations is a critical aspect of this design; hence, we leverage body biasing techniques to manage power consumption and stability dynamically. Specifically, for power efficiency, the body voltage of the P3 transistor is set to VSS (0 V), effectively reducing leakage currents during idle states and optimizing power utilization. For N5, dynamic body biasing is applied, where 0.6 V is applied during standard read and write operations, and a higher bias of 1 V is applied during MAC operations, ensuring stable performance under varying operational demands. The gating mechanism of the PMOS and NMOS transistors within each bit-cell is designed to enhance the voltage stability by setting the gate voltages to match the logic level stored at node Q. This configuration ensures that only one transistor (either PMOS or NMOS) is active at any given time, thus preventing contention within the bit-cell and promoting stable voltage distribution across the cell. This structural arrangement is crucial to achieving low-noise and consistent performance during high-speed operations, particularly in IMC applications where continuous switching occurs. Figure 2 further expands on this structure by illustrating an SRAM-CIM (computing-in-memory) array with a 128-byte (128 B) capacity, composed of 128 columns and 8 rows. This array structure leverages the capabilities of the 8T SRAM bit-cells to execute parallel MAC operations across multiple cells, facilitating high-speed binary multiplication at a low power cost. Each bit-cell is connected to a word line (WL), managed by a word line driver, which controls access to each row of memory cells. Additionally, the bit line (BL) and its complementary bit line bar (BLB) are controlled by dedicated BL/BLB drivers, which manage the read and write voltage levels and ensure reliable data transfer. This fine-tuned control mechanism aids in maintaining stability and reducing power consumption, thus optimizing the SRAM array for energy-efficient and high-performance CIM operations. This architecture provides an advantage in performing internal operations directly within each bit-cell and enables further calculations through voltage differentials across cells, enhancing both computational efficiency and power savings. To further enhance power efficiency, this design incorporates dynamic body biasing to adjust threshold voltages based on the bit-cell's operational state, which minimizes leakage current during idle periods. Additionally, fine control over supply voltage across cells helps reduce unnecessary power draw, optimizing the SRAM array for high-efficiency, compute-in-memory applications.