# Harnessing FPGA Technology for Energy-Efficient Wearable Medical Devices
## 5 Power Optimization Strategies
### Designing an Energy-Conscious Algorithm
#### 5.1.4 Parameter Quantization  
Arithmetic operations with real numbers on an FPGA consume substantial power due to floating-point (FP) computations. Moreover, these FP operations utilize significant on-chip resources, memory bandwidth, and inference times [7]. Parameter quantization is used to reduce the model's size, memory footprint, and resource consumption by compromising the precision of model parameters. It involves converting high-precision floating-point numbers (e.g., 32 bit) into lower-precision formats (e.g., 8 bit integers). To optimize the model for resource-constrained hardware, the model's parameters are quantified from float to fixed for compression and efficient inference [83]. Such optimization also results in the reduction of resource consumption and improves power consumption. For instance, the authors of [84] implemented a real-time apnea detection module, taking input from a pulse oximeter and single-channel ECG sensors and using a BiNN on an Artix-7 Nexys FPGA. The input data were quantized into eight-bit binary values. The hyperparameters of the trained model were also binarized, enabling the substitution of MAC operations with SAC operations, including the use of a SAC-based activation function. Such implementation of the SABiNN model, as opposed to a feedforward neural network (FNN), resulted in a reduction in power consumption of nine times and a reduction in resource usage of four times, with only a minimal but acceptable loss in accuracy. The authors of [68] also exploited parameter quantization in their SNN-based ECG classifier. The parameters were mapped to the (\(-\)1, 1) range during the training phase and then quantized to a six-bit fixed point for hardware implementation. This approach significantly reduced complexity and power consumption at the cost of little accuracy loss from 98.39% to 98.22%. An arrhythmia classification at the edge was designed based on the DCNN model in [83], where a large-scale DCNN was optimized to accelerate itsinference on the FPGA-based embedded platform by quantizing the parameters of the pruned model. The weights and feature maps of the pruned model were quantified to unsigned 8 bit integers, while the bias vectors were quantified to signed 32 bit integers. Such integer operation resulted in a reduction in communication, along with memory and power consumption. In another approach, the authors of [77] converted the FP parameters to corresponding integer values in their FNN-based sleep apnea detector for power consumption. Similarly, in [66], the authors used fixed-point arithmetic in their QRS extractor based on the Pan and Tompkins algorithm. The IIR filters in the digital signal processing (DSP) section of this algorithm are power-hungry components due to the large number of arithmetic computations involved. They reduced the number of bits at input from 16 to 4, thereby reducing the bit size of all of the processing elements involved in the computation. The authors of [72] used fixed 16 bit precision and also binarized the weights, simplifying computations and thereby reducing resource usage and dynamic power consumption. However, this came at the cost of a slight reduction in accuracy due to the simplified arithmetic operations. Likewise, ECG signal classification using dynamically biased LSTM was proposed in [85], where weights were quantized to fixed points for hardware implementation. The author quantized the widths from FP32 to INT4 to improve power consumption, with an acceptable loss of accuracy of 2.4%. Likewise, the authors of [78] used fixed points (16 bit) to represent LDWT factors, computed in a parallel fashion to reduce the clock cycles from \(n\) to 1. The authors were able to achieve a 20% reduction in power consumption operating at 35 MHz with 98.29% accuracy while using only 4.36% of the total resources. The authors of [86] also quantized the parameters of each trainable layer to 8 bit integers in their 1D CNN-based ECG classifier.