## 2 Related Work  
Various algorithms have been proposed for minimizing static power consumption using the dual-threshold technique at the transistor level [20; 21; 22]. However, the transistor-level analysis and assignment methodology is complex and unsuitable for current VLSI designs. Compared to the transistor stage, the gate-level circuit uses standard cells as the basic unit of the circuit, significantly reducing the complexity of the VLSI designs. As a result, the design approach for threshold voltage distribution has also evolved from the transistor level to the gate level [17; 18; 19; 23; 24]. The methods in [23; 24] significantly reduce the number of operations by batch replacement, while the methods in [17; 18; 19] choose a node-by-node replacement for accuracy. The gate-level dual-threshold static power-optimization methodology (GDSPOM) [17] provides a way to distribute threshold voltages at the gate level. The circuit's initial state in this method is all-HVT. This method analyzes the timing by STA [25] and then swaps the cell with the highest cost to LVT, where the cost of the cell refers to the number of critical paths through it. This method then repeats the above operation of analyzing the timing and replacing the cell until the timing meets the constraints. For example, as shown in Figure 1, there are six paths in the design, three of which are critical. Cells \(A\) and \(D\) will be swapped to LVT first since their costs are the highest. The cell-based leakage power reduction priority (CBLPRP) [18] optimization methodology views the static power consumption difference \(\Delta p\) as a more effective indicator than the number of critical paths through the cell. The circuit's initial state in this method is all-LVT. This method calculates each cell's static power consumption difference \(\Delta p\) between LVT and HVT states, then swaps the cell with the highest \(\Delta p\) to HVT. If the timing does not meet the constraints after replacement, this method will swap the cell back to LVT. The above swapping operation continues until all cells are accessed. In Figure 2, for example, the cells are accessible in the order of \(ACBD\) based on the value of \(\Delta p\). Critical-path aware power-consumption optimization methodology (CAPCOM) [19] considers that cells' delay, static power consumption, and the number of critical paths through the cells need to be considered. This method divides cells into critical cells and non-critical cells. For non-critical cells, this method calculates the delay difference \(\Delta d\) and the static power difference \(\Delta p\) for each cell between LVT and HVT states. For critical cells, this method calculates the number of critical paths \(N\) through each cell additionally. The initial state of the circuit is all-LVT, and the non-critical cells are first accessed in descending order of the power-to-delay ratio \(\Delta p/\Delta d\). Then, access each critical cell in descending order of \(\Delta p/(\Delta d*N)\) values. As with CBLPRP, if the swapped cell does not meet the timing constraint, swap it back and loop until all cells are accessed. This method can be applied to triple-threshold voltage distribution: prioritize whether the cell can be swapped from LVT to HVT; after accessing all cells, consider whether the remaining LVT cells can be swapped to SVT. However, these methods have the following drawbacks:  
* These methods need to update the timing every time they swap a cell, which can lead to significant runtime in VLSI designs. The operation to update the timing is performed in STA tools, which calls the composite current source (CCS) timing library to recalculate the cell's delay and update the path timing. Calculating delay using the CCS library is time-consuming [26], and updating the paths requires traversing  
Figure 1: A gate-level dual-threshold static power-optimization methodology (GDSPOM) cell-swapping example. Figure 2: A cell-based leakage power reduction priority (CBLPRP) cell-swapping example. many paths.