# A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS
## 3 Results  
The proposed dual-loop dual-output frequency synthesizer is implemented using 0.13 \(\upmu\)m SiGe BiCMOS technology. The top metal and second metal with thickness of 4 and 1.42 \(\upmu\)m are used in the design of RF signal interconnections/passive parts, as well as the power routing, while the third metal with thickness of 0.6 \(\upmu\)m is used as the RF/DC ground. The implemented synthesizer chip is wire-bonded to the printed circuit board (PCB), on which the PLL's loop filters are implemented for low cost and flexibility. The output spectrum and the phase noise of the chip are measured with Keysight PXA N9030A, and R&S phase noise analyzer FSWP, which also provides the supply voltage to the low noise LDOs on PCB board, distributing the required voltages to each core circuit. The total DC power consumption is 610 mW for the dual-loop synthesizer chip. Figure 8 shows the measurement setup environment and the photograph of the wire-bonded dual-loop dual-output synthesizer. The chip size including all pads is 2.7 mm \(\times\) 2.4 mm. Figure 9a shows the measured output frequency of the Colpitts VCO1 in Loop1, which is from 12.28 to 13.25 GHz. Figure 9b shows the measured phase noise for VCO1 at 1 MHz offset, from \(-\)112 to \(-\)116 dBc/Hz. Thanks to the high-Q varactor provided by the process, the VCO1 shows good phase noise performance with the average VCO gain, Kvco, of 485 MHz/V for the varactor tuning voltage, Vt, from 0.2-1.6 V, where the charge pump has well-matched up/down currents to optimize the phase noise and spur performance for the frequency synthesizer. Figure 8: _Cont._  
Figure 7: Simulated phase noise contributions at (**a**) the Output1 from Loop1; (**b**) the Output2 from Loop2 with doubler. Figure 9c shows the measured output frequency of the Colpitts VCO2 with three-bit cap bank in Loop2, which is from 14.81 GHz to 17.78 GHz. The VCO2, together with the frequency doubler, can cover 29.835-35.1 GHz, which is designed to support all 540/1080 MHz channels in IEEE802.11 aj (45 GHz) standard. Figure 9d shows the measured phase noise for VCO2 at 1 MHz offset, from \(-110\) dBc/Hz to \(-115\) dBc/Hz. With the three-bit cap bank, the average Kvco is kept below 450 MHz/V for the eight sub-bands, optimizing for the phase noise performance and loop dynamics of the frequency synthesizer. Figure 8: (**a**) Measurement setup environment for the output spectrum and phase noise of the dual-loop dual-output synthesizer chip; (**b**) photograph of the wire-bonded dual-loop dual-output frequency synthesizer chip; (**c**) function module blocks in the chip. Figure 9: Measured results for (**a**) the output frequency for the Colpitts VCO1 in Loop1; (**b**) the phase noise of the VCO1 at 1 MHz offset; (**c**) the output frequency for the Colpitts VCO2 with three-bit cap bank in Loop2; (**d**) the phase noise of the VCO2 at 1 MHz offset. Figure 10a,b shows the measured phase noise of the dual-loop dual-output frequency synthesizer, which are \(-79.3\) dBc/Hz@10 kHz, \(-88.9\) dBc/Hz@100 kHz, and \(-129.1\) dBc/Hz@100 MHz at 12.96 GHz for Output1 and \(-76.6\) dBc/Hz@10 kHz, \(-80.2\) dBc/Hz@100 kHz, and \(-117.2\) dBc/Hz@10 MHz at 32.535 GHz for Output2. The two outputs of the frequency synthesizer can support the channel centered at 45.495 GHz for IEEE 802.11 aj (45 GHz) in a super-heterodyne transceiver, as shown in Figure 2b. By configuring a series of division ratios (N = 29, 31, 33, \(\ldots\), 57, 64, 66, 68) for MMD in Loop2, all the 540/1080 MHz channels of IEEE802.11 aj (45 GHz) can be supported. The loop bandwidth of the two loops is designed as \(\sim\)50 kHz and \(\sim\)450 kHz, respectively, to optimize the in-band/out-of-band phase noise and spur attenuation.