# An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks
## 3 Architecture of the E-ML-SpFi Core  
### Overall Architecture  
In this section, we fully illustrate the architecture of the E-ML-SpFi core. Figure 2 shows a block diagram of the E-ML-SpFi core. The architecture does not specify the number of VCs and number of lanes, which can be easily expanded. The proposed core integrates an MIB, a Data-Link layer, a Multi-Lane layer, \(L\) Lane layers, and \(L\) Physical layers. Each layer is made up of several interconnected subsystems.  
The broadcast subsystem is constituted by an output broadcast (BC) buffer, a BC flow control block, a BC-framing block and an input BC buffer in the Data-Link layer.  
Figure 2: Overall architecture of the E-ML-SpFi core.  
The QoS subsystem comprises VC buffers, a media access controller (MAC), a data-framing block and a VC De-Multiplexer on the receiver side of the Data-Link layer. The Data-Link layer has \(N(N\in[1,32])\) pairs of input VC buffers and output VC buffers, which are employed to provide separate packet streams. The arbitration between VCs is realized by the MAC providing a high degree of QoS with priority, reserved bandwidth, and deterministic delivery. Data segments, which are read out the chosen output VC buffer, are collected into a data frame by the data-framing block.  
The flow control subsystem is made up of an FCT-framing block, output flow control blocks, and input flow control blocks. An input VC flow control block sends a request for FCT control words to the FCT-framing block if a certain number of words are read out an input VC buffer. Each output flow control block at the local node monitors the space available in the corresponding input flow control block at the destination node by receiving FCT words.  
Data frames are backed up in the error recovery subsystem, and so are broadcast frames and FCT control words. The error recovery subsystem is also employed to achieve the retransmission mechanism. Subsequently, control words and data words are interleaved with the precedence described in Section 2. The interleaved traffic is adjusted by the word re-ordering block for adaptive bandwidth. After that, the traffic goes through scramblers and CRC blocks. The word re-ordering block and the word concentration block on the receiver side constitute the switching subsystem.  
On the receiver side of the Data-Link layer, data from the Multi-Lane layer is transmitted to the error detection subsystem after CRC and descrambling processes. The subsystem requests an ACK control word if an increment frame mentioned in Section 2 is correctly received. Similarly, an NACK control word is requested in case of an error.  
The multi-lane monitor FSM monitors the real-time status of all lanes and promotes hot redundant lanes to data-sending lanes in the event of a lane failure. On the transmitter side of the Multi-Lane layer, words from the Data-Link layer are distributed to each data-sending lane. The multi-lane control words are inserted into the traffic for alignment, as depicted in Section 2. On the receiver side, the alignment subsystem is employed to provide aligned data-receiving rows.  
The hardware implementations of the Lane layer and the Physical layer leave no space for interpretation [26]. However, the Data-Link layer and the Multi-Lane layer have significantly different hardware implementations due to the high-level description in the SpaceFibre protocol. The following section will concentrate on the key technologies in the Data-Link layer and the Multi-Lane layer, alongside the design choice made and the impacts of the choice.