## 3 Proposed Distributed Secondary Control Technique
### Case Two: Proposed Control Capability during Resistive Load Variations  
This case study involves evaluating the response of the proposed FDSC approach during demand or load variation. Utilizing the sparse communication protocol (Topology \(X\)) described in _case one_, the simulation was divided into four stages and carried out for a duration of 26 s. During \(t\in[0,2)\), representing the first stage, only the droop control in each DER is enabled at \(t=0\) s, with resistive load, \(R_{L1}\) and \(R_{L2}\), connected. The proposed FDSC for all DERs is enabled at \(t=2\) s during the second stage, \(t\in(2,9)\). Another resistive load \(R_{L3}\) is connected to the microgrid at \(t=9\) s during the third stage, \(t\in(9,16)\) and disconnected from the common bus at \(t=16\) s during the last stage, \(t\in(16,26]\). Figures 13 and 14 show the results obtained from this case study. The results for the first  
\begin{table}
\begin{tabular}{c c c c c} \hline
**Control Objectives** & **Q1** & **Q2** & **Q3** & **Proposed Control** \\ \hline Voltage regulation & 2 s & 1.72 s & 3 s & \(\leq\)0.1 s \\ \hline Current Sharing & 2.8 s & 2s & 3.4 s & \(\leq\)1.5 s \\ \hline \end{tabular}
\end{table}
Table 4: Proposed control technique compared to other techniques.  
and second stages exhibit similarities to those examined in _case one_. Figure 13 displays the output voltages of each DER and the common bus voltage. At the connection of the new load, \(R_{13}\), during the third stage, a short voltage transient, with an undershoot of 8.48% is observed at the common bus, as shown in Table 5. However, this transient is swiftly resolved within 0.8 s, restoring the voltage at the common bus to 48 V. Disconnecting the load from the microgrid during the fourth stage, a short transient with a voltage overshoot of 11.08%, which dampens out quickly, i.e., within 0.8, s is observed while restoring the bus voltage to its nominal value to stabilize the system. Therefore, the voltage at the DC bus is still well sustained regardless of the load variations. As mentioned earlier, the line resistances that exist between the common bus and the DERs are responsible for the observed higher output voltages of the DERs above the nominal voltage value, as seen in Table 6.  
The current output response is shown in Figure 14. The results show that including an additional load on the microgrid increases the current generated by the DERs, with DER 1 having the highest overshoot of 9.3% while still achieving the consensus with the other DERs within 0.9 s. Disconnecting the load results in a current drop, DER 1 having the least undershoot of 13.8% and attaining consensus within 0.7 s. Hence, it can be inferred that the proposed control approach presented in this study is robust and reliable, guaranteeing effective current sharing and voltage restoration regardless of any variations in the load. Furthermore, Figure 15 illustrates the output correction signal, \(\mathcal{H}_{i}\), generated by the proposed FDSC for each DER. As described in (13), this correction signal effectively removes any deviation due to the droop operations. The output voltage and current of each \(DER\) during each stage are further provided in Table 6. Similar results were also discovered in [7; 32; 36], where the case of a resistive load change was considered.  
Figure 13: (**a**) Common bus voltage; (**b**) Voltage output of DERs under resistive load.