# Automatic Configurable Hardware Code Generation for Software-Defined Radios+
## 5 Hardware Implementation
### Hardware Design  
The SDF-AP model may be closest to the hardware in contrast to other SDF-based models but its implementation on hardware is not as trivial as it may seem. Like most dataflow models, SDF-AP model is asynchronous and abstracts most of the hardware behaviour, therefore, making it suitable for high-level application description. It performs analysis of timing (i.e., token consumptions and productions) and performance (i.e., such throughput, latency and buffer sizes) properties which are often difficult to analyse at the low-level of hardware description. However, it has no prior knowledge of the low-level models of hardware implementation such as the finite state machines, datapath components, multiplexers, LUTs, pipeline registers etc. In this work, we put more emphasis on the synchronous finite-state machine (FSM) as it is the most dominant model in the generated hardware design. It is evident that there is a huge semantic gap between a dataflow model and hardware and this complicates the correct implementation of the hardware. Our first step towards hardware design is by an illustration of the expected hardware design in Figure 5 which is implemented from the SDF-AP example in Figure 1. Each HW block in Figure 5 has the input and output ports which connect to other blocks using signals or wires. The signals in Figure 5 are of output type which makes the system compliant with a [PERSON] machine. The ports which are not shown in HW blocks \(X\) and \(Y\) interface with the external systems. These ports are either system input ports or system output ports which form a top-level entity of the VHDL design as shown in Listing 1. The input signals _en_ and _din_ of the HW block \(X\) allow input data to be received by the system while signals _vld_ and _dout_ of block \(Y\) send the data out of the system. All the blocks connect to the fundamental system signals _rst_ and _clk_. The top-level entity description is followed by the behavioural description which composes of two the HW blocks (i.e., \(X\) and \(Y\)) using a FIFO buffer of size 2. In this example, the HW blocks have been described in VHDL \"by hand\". In real-world applications, some blocks may be acquired from a library of IP cores which are provided by mainstream commercial VLSI vendors such Xilinx, Altera etc or the open-source development communities such OpenCores [19], GRLIB [20; 21], etc. The VHDL code in Listing 2 is an extract from the system architecture description in Figure 5.  
Figure 5: The hardware design of SDF-AP (based on Figure 1). ```
1 libraryIEEE;
2 useieee.std_logic_1164.all;
3 useieee.std_logic_unsigned.all;
4 entitysdfapv0 is
5 port(
6 clk:instd_logic;
7 rst:instd_logic;
8 en:instd_logic;
9 din:instd_logic_vector(7 downto0);
10 vld:outstd_logic;
11 dout:outstd_logic_vector(7 downto0)
12);
13 end;
```  
Listing 1: A top-level entity of the hardware design in Figure 5.  
```
1 architecturertlofsdfapv0 is
2...-hiddenregisterandcomponentdeclaration
3 begin
4 xInst_en_i<=en;
5 xInst_din_i<=din;
6 xInst:xportmap(...);
7 yInst:yportmap(...);
8 xInst_yInst_ch1:fifo
9 genericmap(DATA_WIDTH=>8,FIFO_DEPTH=>2)
10 portmap(...);
11 xInst_yInst_ch1_we<=xInst_vld_o;
12 xInst_yInst_ch1_din<=xInst_dout_o;
13 yInst_en_i<=xInst_yInst_ch1_vld;
14 yInst_din_i<=xInst_yInst_ch1_dout;
15...-processdefinitionhidden
16 vld<=yInst_vld_o;
17 dout<=yInst_dout_o;
18 end;
```  
Listing 2: The architecture description of the hardware design in Figure 5.  
First, the input registers of the source block \(X\) are connected to top-level entity ports and then followed by the instantiation of the HW blocks and FIFO channel. The interfacing of the HW blocks with the FIFO is a combinational assignment of output signals (lines 11-14). The _process_ implements the FSM that controls the flow of data to or from the FIFO and the details of how it is built are presented in Section 6. The last two lines route data samples to the external environment of the system.