## 3 Design of Approximate QAM Demodulation Circuits
### Arithmetic Approximation Techniques
#### 3.5.2 Fixed-Point Approximations  
In this work, we target multiplication architectures based on radix encodings, due to their efficiency compared to other algorithms [30]. To decrease the circuit complexity of the fixed-point (FXP) multiplication, we perform inexact partial product (PP) generation based on the hybrid high-radix encoding [14]. This technique tunes the approximation levels with the configuration parameter \(K=2\cdot l\geq 4\). In particular, the \(L-K\) MSBs of one of the \(L\)-bit input operands (e.g., \(A\)) are accurately encoded with radix-4, while its \(K\) LSBs are approximately encoded with radix-2\({}^{K}\). The approximation is inserted by mapping the high-radix encoded values to the nearest of the four largest powers of 2 or 0 [14]:  
\[A=\left\langle a_{L-1}\dots a_{1}a_{0}\right\rangle\ \ \rightarrow\ \ \ A=A_{MSB}+A_{LSB}=\sum_{ \begin{subarray}{c}j=K/2\\ K\geq 4\end{subarray}}^{L/2-1}\!\!\!\!\!\!\!  
various arithmetic and approximation configurations, and we discuss the most interesting results from our design space exploration. For the evaluation, we assume a transmitter producing random bits and a convolutional encoder of 1/2 code rate with generator polynomial \((133,171)\) and constraint length of 7. The QAM modulator considers a normalized constellation diagram, and the modulated signal is transmitted through an AWGN channel of variance \(\sigma^{2}=10^{-(\text{SNR}_{\text{2g}}/10)}\). Finally, the outputs of our LLR-based demodulation architectures are processed by a Viterbi decoder in unquantized mode.  
To evaluate the hardware efficiency of the proposed approximate designs, we implement our QAM architectures on the Xilinx Zynq Ultrascale+ ZCU106 (XCZU7 EV) FPGA, using parametric VHDL and design space exploration. Considering that the proposed architectures can be deployed on various technologies, e.g., ASICs, flash FPGAs, we assess the circuits' complexity and throughput without employing elaborate FPGA primitives, such as the DSPs. Hence, in a prototyping fashion, we force the Xilinx Vivado 2019.2 tool to utilize only LUTs and DFFs. Moreover, for the designs without approximate arithmetic units, i.e., the accurate FLP and FXP designs as well as the FXP designs with bit truncation, we force the tool to employ the built-in libraries to map the arithmetic operations on the LUTs. The data bit-width of the FLP designs is 32 bits, while the bit-width of the accurate FXP design is 16 bits (with 14 fractional bits). Moreover, we present the power consumption, as reported by Vivado Design Suite, for the maximum achievable frequency. To assess the accuracy of our approximate demodulation designs, we use two metrics: (i) BER, which is equal to the number of bit errors divided by the total number of transmitted bits, and (ii) mean relative error (MRE), i.e., the mean error of LLRs and symbol distances for the LLR and ML techniques, respectively (versus the \"accurate\" floating-point model).  
We note that we do not present results for the ELLR, as it provides similar accuracy to ALLR, at the expense of increased resource utilization. For example, for 64-QAM, the BER scaling of ELLR almost matches the scaling of ALLR (for small SNR, it is the same). In terms of hardware, when considering the accurate FXP arithmetic, the CORDIC-based implementation utilizes 2.2\(\times\) LUTs and 3.8\(\times\) DFFs, while the polynomial-based implementation utilizes 2.6\(\times\) LUTs and 8\(\times\) DFFs. The resource utilization is increased for higher-order QAMs, e.g., for 256-QAM, the ELLR does not fit in such a big FPGA device, even when using approximation techniques.