# Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput
## 1 Introduction  
NASA Goddard Space Flight Center is currently working on several space based thermal radiometer concepts (e.g., [1, 2]). One of these concepts is the Ice-Giants Net-flux Radiometer (IG-NFR) being developed for a future Uranus or Neptune probe mission [3]. IG-NFR is capable of measuring energy fluxes in seven spectral bands from 0.2 \(\upmu\)m to 300 \(\upmu\)m, each with a \(10^{\circ}\) field-of-view (FOV) projected into the sky. As the probe descends through the planetary atmosphere, a motor drives the IG-NFR field-of-view sequentially and repetitively in clockwise and anti-clockwise directions to five distinct viewing angles. Figure 1 shows a mechanical drawing and a system block diagram of the IG-NFR instrument. The scientific integrity of IG-NFR relies on all seven spectral channels being data logged simultaneously (in parallel). Along with scientific data, there are also auxiliary data and thermal data to aid with understanding of the scientific data [2]. Here, we will use the IG-NFR as an example space-based instrument to demonstrate error check high data throughput using parallel computation of the CRC-code. Table 1 shows details of both science data and auxiliary data generated by the instrument. As the probe descends rapidly into the atmosphere, remote sensing measurements and error checking computations must be executed in a real-time manner before the spacecraft loses communication connection with the probe, e.g., for a Uranus probe, instruments are being designed for a 10-20 bar atmospheric pressure survival. The processor card proposed in this work is a hybrid platform that contains both an FPGA and an embedded processor. It is the heart of the instrument which controls the IG-NFR, acquires data, packages data, and then forwards it to the probe communication protocol to the spacecraft. The system block diagram is shown in Figure 2. In this paper, we will focus on how to implement the CRC error check protocol on an FPGA to meet the real-time requirements dictated by the constraints of the physical system.  
Figure 1: (**a**) Mechanical drawing of the IG-NFR instrument concept; (**b**) IG-NFR accommodated inside the probe.  
Figure 2: System block diagram. The CRC error check will run on the processor card shown in the main electronics box.  
\begin{table}
\begin{tabular}{c c c c c} \hline
**Name** & **Number of Bits** & **Number of Channels** & **Total** & **Comment** \\ \hline Thermopile Data + Time Stamp & 32 & 8 & 256 & Science Data \\ Thermistor data on thermopile & 16 & 8 & 128 & Science Data \\ Hot Target Temperature & 12 & 1 & 12 & Thermal data \\ Fan-out board Temperature & 12 & 1 & 12 & Thermal data \\ Vessel Temperature & 12 & 1 & 12 & Thermal data \\ Windows Temperature & 12 & 1 & 12 & Thermal data \\ Cold Target Temperature & 12 & 1 & 12 & Thermal data \\ LED status & 1 & 1 & 1 & Auxiliary data, 1 bit for ON/OFF \\ Motor Position & 3 & 1 & 3 & Auxiliary data, 3 bits for 7 positions \\ Survival Heater Status & 1 & 1 & 1 & Auxiliary data, 1 bit for ON/OFF \\ Thermopile Data + Time Stamp & 32 & 8 & 256 & Science Data \\ \hline \end{tabular}
\end{table}
Table 1: IG-NFR data.