## 5 Experimental Results
### Performance Analyses of Hardware and Software Co-Design  
In comparison to the hardware generator of key stream blocks discussed in the previous section, we have also implemented the \"KS-Generator\" controller shown within the green box in Figure 8 on the FPGA system bus, using a hardware and software co-design approach (\(\upmu\)P + HW Accelerator). This allows the micro-processor (i.e., \(\upmu\)P in Figure 8) to read the results of the operation results from the \"KS-Generator\" controller. Figure 13b shows that generating ten thousand key stream blocks in the \"\(\upmu\)P + HW Accelerator\" manner takes an average time of 4402 \(\upmu\)s, which is only 14.39% (4402 \(\upmu\)s/30,597 \(\upmu\)s) of the average time required by \"Pure \(\upmu\)P\" (30,597 \(\upmu\)s) as indicated in Figure 14a. In other words, this approach can save over 85% of the micro-processor's processing time. Furthermore, to accelerate the processing speed of NR-PRNG for real-time stream processing, the performance of implemented REG-CAM controller introduced in Section 4.3.1 was evaluated. As shown in the experimental results in Figure 14b, when the micro-processor employs the REG-CAM controller (\(\upmu\)P + HW Accelerator) to operate ten thousand key stream blocks for duplication checking, it takes 27,601 \(\upmu\)s. This is only 0.29% (27,601 \(\upmu\)s/9,371,161 \(\upmu\)s) of the time (9,371,161 \(\upmu\)s) required by pure software (Pure \(\upmu\)P). The significant performance enhancement is attributed to the fact that as the number of generated key blocks accumulates, new key blocks must be compared to all previously used blocks. This leads to an increasing time to obtain a valid Non-Repeating Key Block (NR-KB). In this scenario, as the quantity of generated blocks accumulates, the use of  
Figure 14: Performance comparisons of pure software (Pure \(\upmu\)P) processing and hardware and software co-design approach (\(\upmu\)P + HW Accelerator) for (**a**) generation and (**b**) non-repeating checking for ten thousand NR-KBs. Figure 13: Performance comparisons of pure software (Pure \(\upmu\)P) processing between (**a**) hardware generator (HW Generator) and (**b**) hardware and software co-design approach (\(\upmu\)P + HW Accelerator) for generation of ten thousand key stream blocks. REG-CAM for a hardware-accelerated comparison becomes even more effective compared to the time-consuming software-only approach. Next, to evaluate and demonstrate the performance of applying the implemented SG-DMA, we selected setting a different Data Block Size (DBS) for each operation of memory access. The DBS is a unit of burst memory access length used by the designed SG-DMA. That is, a memory read is continual for the assigned DBS, and then a memory write is also continual for the same DBS. Accordingly, the SG-DMA controller will support a First-In First-Out (FIFO) buffer to temporarily store the access data from a source memory address and then transfer them to another destination memory address. In experiments, we selected DBSs of 64, 128, 256, 512, and 1024 bytes. For a fair comparison, to transfer the same amount of data of 8192 bytes, the number of burst transfers for DBSs of 64, 128, 256, 512, and 1024 bytes are 128, 64, 32, 16, and 8 times, respectively. As Figure 15a shows, they are denoted as DBS:64, DBS:128, DBS:256, DB:512, and DBS:1024, respectively. In Figure 15a, the throughput of DBS:64 is 6.66 MB/s, which is the lowest throughput performance in this experiment. Next, the throughput of DBS:128 is 9.64 MB/s, which is higher than that of DBS of 64 bytes (i.e., DBS:64). It is notable that the throughput of DBS:1024 is 15.83 MB/s, which is the best performance in this experiment. Overall, we observed that the memory accesses with a larger data block size came out with a better throughput performance.