# Parallel Eclipse-Aware Routing on FPGA for SpaceWire-Based OBC in LEO Satellite Networks
###### Abstract
When a satellite is exposed to sunlight, its solar panels generate power to support on-board operations such as communications and data processing, and the excess energy is stored in on-board batteries. However, when the satellite enters Earth's shadow (eclipse), it can no longer generate power and must rely solely on the stored battery energy. During this eclipse period, the charge-discharge cycles of the battery are constrained, and the depth of discharge (DoD) measures the fraction of stored energy that has been consumed. As DoD increases, battery degradation accelerates and overall battery lifetime is reduced. Therefore, to extend battery life during eclipse periods, it is essential to minimize excessive energy consumption and keep DoD as low as possible [9; 10; 11]. The conventional OBC has faced significant challenges in real-time routing and data processing due to its limited hardware resources and computational performance. To address these issues, this study proposes the use of an FPGA--offering superior computation capabilities and abundant logic resources--as the next-generation OBC [12]. We implemented on the FPGA both the Eclipse-Aware Routing (EAR) algorithm, which accounts for satellite energy consumption rate, eclipse duration, and expected transmission load, and the K-Shortest Paths (KSP) algorithm, which concurrently identifies K optimal paths to flexibly accommodate the frequent link disruptions inherent in LEO constellations. While prior work has demonstrated EAR and KSP acceleration via GPU-based parallelization, our approach adopts a space-qualified FPGA platform with a PS-PL heterogeneous architecture [13]. Recent comparative studies report that FPGAs deliver 1.2-22.3 \(\times\) lower energy-per-frame than state-of-the-art GPUs in embedded-vision pipelines and therefore recommend FPGAs for power-constrained platforms [14; 15]. Although several GPUaccelerated or dynamically routed schemes have been proposed for LEO networks, their high-power envelopes and limited radiation tolerance render them impractical for on-board deployment. Consequently, we adopt an FPGA accelerator to achieve efficiency while meeting space-grade reliability requirements. Specifically, the programmable logic (PL) region employs parallel processing and pipelining techniques to dramatically reduce latency, thereby meeting the stringent real-time requirements of LEO satellite networks. Finally, we conducted experiments by integrating the routing algorithms with the SpaceWire Brick MK4--an IEEE 1355-standard SpaceWire device for space communication networks [16]. These experiments included updating the Brick's routing table based on the FPGA-executed KSP algorithm results, thereby demonstrating the networking feasibility in a realistic satellite environment. The main contributions of this paper are as follows:  
1. We verified the feasibility of implementing a K-Shortest Paths (KSP) algorithm, tailored for LEO satellites, on an FPGA and secured real-time performance by reducing computation time through acceleration and parallelization; additionally, we incorporated the Eclipse-Aware Routing (EAR) algorithm, which considers eclipse conditions and energy consumption rates. 2. We demonstrated the practical applicability of our approach by integrating the FPGA with SpaceWire-based systems and implementing dynamic routing-table updates on actual SpaceWire network hardware, SpaceWire Brick MK4. The remainder of this paper is organized as follows. Section 2 describes the topology characteristics of LEO satellite networks, their energy-efficiency challenges, and the real-time routing limitations of conventional OBCs. Section 3 presents the Eclipse-Aware Routing (EAR) algorithm, the K-Shortest Paths (KSP) algorithm, and the methods used for parallelization and acceleration on FPGA. Section 4 details the experimental setup and discusses the results. Finally, Section 5 summarizes the findings and outlines future work.