## 3 Monolithic Photonic Integration for Optical Memories  
To this end, photonic integration processes have matured to the point where a wealth of optical FF and RAM memory configurations have been successfully demonstrated [33; 34; 35; 36; 37; 38; 39; 40; 41], with most of these demonstrations relying on the mature SOA switching technology, owing to its high-gain, high-speed, and high-yield performance characteristics [2]. In this paper, our analysis draws from the architecture of an FF memory with two cross-coupled asymmetric SOA-MZI switches, as illustrated in Figure 2a, which was initially developed in [37] and more recently theoretically investigated in the time and frequency domain in [43]. Each SOA-MZI switch features one SOA (SOA1 and SOA2) at the lower branch and a phase shifting element (\(\Phi\)1 and \(\Phi\)2) at the upper branch for controlling the biasing conditions of the interferometer. The two SOA-MZIs (SOA-MZI1 and SOA-MZI2) are each powered by a weak Continuous Wavelength (CW) input signal at wavelengths \(\lambda\)1 and \(\lambda\)2, respectively, while their Unswitched output ports (U-ports) are interconnected through a common coupling waveguide path. This symmetric configuration of the two SOA-MZI switches allows for a master-slave operation with the U-output of the master switch controlling the operating condition of the opposite slave switch and blocking its transmission at the U-port. Owing to the symmetric configuration, the roles of the master and slave switch are interchangeable, allowing the FF state to be defined by the wavelength of the emitted signal outputs at either one of the Switched ports (S-ports). The FF state can be monitored through the respective FFOut1 and FFOut2 output ports in terms of high power levels of \(\lambda\)1 and \(\lambda\)2 optical signals, respectively. The state of the FF can be optically controlled by external _Set_/_Reset_ (SR) pulses fed through the S-ports of the SOA-MZIs. When a high _Set_ or _Reset_ pulse is injected at the master SOA-MZI, it will block its light-transmission and set it in the slave condition regardless of the previous state of the FF, allowing for the opposite SOA-MZI to recover and become the master. In this arrangement, the two logical values of the data-bit stored in the FF-memory, logical _\"1\"_ and _\"0\"_, can be associated with the high optical power of the wavelength-signal emerging at the two outputs. The present FF memory configuration was initially demonstrated as a hybridly integrated module in [37] with the use of silica-on-silicon integration technology, exhibiting a total footprint of 45 \(\times\) 12 mm\({}^{2}\) and coupling length between the two SOAs of 2.5 cm, which was theoretically shown to be the main speed determining factor of the memory architecture [42; 43]. Following the conclusions drawn by the underlying theory on the critical performance parameters [42; 43], an integrated version of the SR FF was presented using library-based components of a generic monolithic InP platform [33], to benefit from an integration technique that offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity. The two SOA-MZI switches were fitted in a die footprint-area of 6 \(\times\) 2 mm\({}^{2}\) and cross-coupled together  
Figure 2: (**a**) All-optical Flip-Flop architecture and operation; (**b**) Mask-layout of the fabricated monolithic InP Flip-Flop; (**c**) Image of the packaged Flip-Flop device with electrical/optical connections and TEC element; and (**d**) Microscope image of the fabricated Flip-Flop device. through a 5 mm-long coupling waveguide. In this configuration, the intra FF coupling waveguide was 5 mm-long, reducing the total footprint by two orders of magnitude, compared to the previous hybridly-integrated FF implementation [37]. The mask file of the Photonic Integrated Chip (PIC) is illustrated in Figure 2b.