## 2 Basic Elements
### Implementation of Algorithms in FPGAs  
A variety of algorithms have been implemented in FPGAs [13; 14; 15; 16; 17; 18]. The study [16] addresses the challenge of implementing histogram projection using FPGAs. Histogram projection is an effective enhancement technique for images captured by uncooled infrared imagers. Thermal imagers that utilize uncooled focal plane array detectors offer several significant advantages over their cooled counterparts. These advantages include lower cost, silent operation, absence of delicate mechanical parts for cooling, reduced lifecycle cost, and decreased weight and power consumption. Despite suffering from limitations in thermal and geometrical resolutions, these imagers are highly performant and are widely accepted for commercial applications. This acceptance is largely due to their reasonable price point, especially when compared to cooled imagers, which, while offering superior image quality, are prohibitively expensive for commercial use. In the study [17], digital watermarking is examined. This technique, which embeds watermark information into a digital signal in a way that makes it difficult to remove, is of significant importance. The authors developed an adaptive digital watermarking algorithm to improve performance in a multi-parametric solution space for hiding copyright information. This was achieved through the use of phase congruence and singular-value decomposition, which was supported by an information-hiding technique. The Tikhonov regularization method is analyzed as a filter that reduces the effect of the small-singular-value decomposition using the regularization parameter. The truncation of the series is considered as another regularization parameter: thereby eliminating the effects of the small-singular-value decomposition. The performance of the algorithm is evaluated through a simulation in MATLAB using metrics such as the peak signal-noise ratio, structural similarity index metrics, and the normalized cross-correlation index. In [13], the authors present an efficient FPGA implementation of a reconfigurable finite impulse response (RFIR) filter. This implementation utilizes anti-symmetric product coding and odd multiple storage modules. The finite impulse response filter is widely used in various digital signal processing applications, such as echo removal, speech signal processing, speaker standardization, versatile noise removal, and communication. The RFIR filter has the advantage of allowing real-time changes to the coefficient while performing operations. In this particular case, filters were not used to clean the signal. Instead, a random error was emulated by adding it using the _rand_ function of MATLAB. In the study [18], the authors developed an FPGA-based solution for classifying generalized and focal epileptic seizure types using a feed-forward multi-layer neural network architecture. The FPGA implementation in the last two works was validated by comparing its results with those of the MATLAB implementation: a method also employed in our study to validate our FPGA implementation. In [14], the authors implemented the minimum residual algorithm: an effective method for solving problems provided the matrix exhibits certain characteristics. The paper examines an IEEE 754 single-precision floating-point implementation of the algorithm on an FPGA. It demonstrates that through parallelization and heavy pipelining of all floating-point components, it is possible to achieve sustained performance of up to 53 GFLOPS on the Virtex5-330T. This performance compares favorably to other hardware implementations of floating-point matrix inversion algorithms and represents an improvement of nearly an order of magnitude compared to a software implementation. In [15], the authors present an efficient implementation of a multiplier of irreducible polynomials modulo for cryptographic encryption and decryption using FPGAs. For this purpose, the Nexys 4 board based on the Artix-7 FPGA from Xilinx was chosen.