## 3 Theoretical Analysis and Simulation of the Frequency Synthesis Chain  
### Analysis of the Model for the PLLs  
From control theory, the PLL phase-transfer function H(s) can be defined, which establishes a relationship between the input reference source and the output of the PLL. Figure 3 depicts a simplified configuration based on the architecture of the frequency  
Figure 2: (**a**): The set-up of the frequency synthesis chain, (**b**): a photograph of the microwave frequency synthesizer. In (**a**), Part (1): 10 MHz OCXO. Part (2): the first PLL, including 20\(\times\) frequency multiplier. Part (3): 200 MHz to 9.2 GHz. Part (4): the second PLL, including the DRO. OCXO, over-controlled crystal oscillators; DRO, dielectric resonant oscillator; AMP, amplifier; ATT, attenuator; PD, phase detector; PID, proportional–integral–derivative controller; LPF, low-pass filter; BPF, band-pass filter. synthesis chain shown in Figure 2a. In an analog PLL circuit, the mixer primarily functions as a phase detector. In PLL1, as illustrated in Figure 3, the 10 MHz reference source undergoes direct multiplication by a factor of \(M_{1}\) to obtain a 200 MHz clock through the use of two cascaded frequency multipliers. The resulting clock is then compared with the 200 MHz clock generated from the 200 MHz OCXO in PD1. Thus, the phase argument of the 200 MHz clock \(\Theta_{m1}(s)\) is given by  
\[\Theta_{m1}(s)=M_{1}\Theta_{i}(s), \tag{1}\]  
where \(\Theta_{i}(s)\) represents the phase argument of the 10 MHz reference source. \(U_{e1}(s)\) is defined as the phase error signal generated by PD1. In the complex frequency domain, \(U_{e1}(s)\) can be expressed as  
\[U_{e1}(s)=k_{d1}\Theta_{e1}(s)=k_{d1}(\Theta_{o1}(s)-\Theta_{m1}(s)), \tag{2}\]  
where \(k_{d1}\) denotes the detector gain of PLL1. \(\Theta_{e1}\) represents the phase argument of the error signal generated by PD1, while \(\Theta_{o1}(s)\) is the phase argument of the 200 MHz OCXO output. Equation (2) presents a linearized model of PD1. The output from the 200 MHz OCXO is divided into two paths by a coupler. The main path is utilized directly, while the other path is amplified, low-pass filtered, and further divided into two additional paths. One of these paths serves as the sampling rate of the DDS, while the other is fed back to PD1. In Figure 3, the transfer function of the first loop filter is defined as \(F_{1}(s)\). Hence, the error signal of the filter can be expressed as  
\[U_{f1}(s)=F_{1}(s)U_{e1}(s), \tag{3}\]  
where \(U_{f1}(s)\) represents the error signal from the first low-pass filter (LPF1) in PLL1, which is employed to tune the 200 MHz OCXO. In the complex frequency domain, the output signal from the 200 MHz OCXO is proportional to the control signal and can be given as  
\[\Theta_{o1}(s)=\frac{k_{o1}}{s}U_{f1}(s), \tag{4}\]  
where \(k_{o1}\) represents the gain of the 200 MHz OCXO. When the phase error signal generated by PD1 is sufficiently small, the output signal from the mixer can be approximated by its argument. The transfer function \(G_{1}(s)\) is defined as the first loop gain in Figure 3. Based on Equations (2)-(4), \(G_{1}(s)\) can be expressed as  
\[G_{1}(s)=\frac{\Theta_{o1}(s)}{\Theta_{e1}(s)}=\frac{k_{d1}k_{o1}F_{1}(s)}{s}, \tag{5}\]  
Figure 3: Mathematical model of the frequency synthesis chain. Furthermore, \(H_{1}(s)\) in Figure 3 relates the input 10 MHz reference source to the 200 MHz OCXO output. \(H_{1}(s)\) can be expressed as  
\[H_{1}(s)=\frac{\Theta_{o1}(s)}{\Theta_{l1}(s)}=\frac{\Theta_{o1}(s)}{\Theta_{e1} (s)/M_{1}}=\frac{k_{d1}k_{o1}M_{1}F_{1}(s)}{s+k_{d1}k_{o1}F_{1}(s)}, \tag{6}\]  
Equations (5) and (6) represent the mathematical model of PLL1. Assuming that PLL1 is phase-locked in the time domain, the 200 MHz output signal \(u_{o1}\) can be expressed as  
\[u_{o1}(t)=a_{1}cos(\omega_{1}t+\theta_{o1}), \tag{7}\]  
where \(a_{1}\) represents the amplitude argument of the signal, and \(\omega_{1}\) and \(\theta_{o1}\) are the radian frequency and initial phase of the 200 MHz OCXO output, respectively.