## 1 Introduction  
NAND flash memory technology has been flourishing since the first flash memory being invented by Dr [PERSON] [1] in 1984. The development of NAND technology has brought tremendous changes to the memory market and the electronics industry. However, the cost of flash memory still needs to be reduced to gain wider acceptance in mass storage by increasing the storage density. The innovation of etching technology has made NAND flash develop from 2D structure [2] to 3D structure [3], and the application of incremental step pulse program (ISPP) scheme [4, 5] has realized the precise program voltage control, which makes it possible to increase the storage density of NAND flash. The density of storage has been rising from 2D-256 Kb single-level cell (SLC) [6], 2D multi-level cell (MLC) [7], and 3D MLC [8], to the current 3D-768 Gb triple-level cell (TLC) [3], 3D quad-level cell (QLC) [9, 10], and the under-developed penta-level cell (PLC). NAND cells can be designed as \(n\) bits/cell by precisely controlling the levels of the program threshold voltage \(V_{th}\), where SLC to PLC stores 1-5 bits/cell corresponding to \(2^{1}\)-\(2^{5}\) voltage levels respectively. The high-storage-density NAND flash memories like QLC and PLC start to receive much attention due to the high demands on storage capacity and the low cost. However, the increase in storage density makes the data stored in these NAND flash memories vulnerable to noise interference [11, 12, 13, 14]. Some error control strategies such as decoding statuses selection [15], ANN-coupled decoding [16], retention optimized reading [13] are of high potential to be applied in the NAND flash memory of high storage density (HSD) to improve its error performance and extend its lifetime, considering that it has more errors and shorter lifetime as the storage density gets higher. The idea is to adopt different strategies for low raw bit error rate (RBER) and high RBER respectively, including using different decoding algorithms for low and high RBER, inputting more accurate soft information to the decoder based on RBER change learned with artificial neural networks (ANN), shifting read reference voltages \(V_{t}\)s or configuring multi-level \(V_{t}\)s in read operation when RBER goes high due to \(V_{th}\) shift. Therefore, having RBER estimated would be a great help to these strategies for memory management and wearing level monitoring. As RBER grows fast in HSD NAND flash, it is very necessary to frequently monitor the RBER in a long term so that the error control methods can be executed at the right time to maintain the performance of the flash. Ref. [17] proposed a method of using parity violation to estimate RBER, and it needs to multiply a pre-set quantized scalar with the number of parity violations, which is a function of the number of parity violations and determines the accuracy of the estimated BER. However, considering that parity violation can only reflect the odd number of errors in a codeword, it needs a large sample size \(N\) to ensure accurate estimation. For example, it needs to collect \(N=2880\) for a 16 KB-page-size flash, which is a very time-consuming collection. The pre-set parameter may not be able to cope with the complex and changing noise condition in HSD flash in time. Hence, it is of hysteresis for HSD NAND flash, where the noise, including Program/Erase (P/E) cycle effects [12], retention error [13], and read disturb error [14], will cause RBER increasing quickly with reading times or P/E cycles and the quickly changed error condition that happens during a read operation is necessary to be measured and reflected in time. Ref. [18] proposed a fast estimation method by comparing the test data with the data read from the flash memory, but it may not be so suitable for HSD flash memory because frames from different pages have unbalanced error distribution due to data modulation, which can cause inaccuracy in estimation.