# A Tile-Based Multi-Core Hardware Architecture for Lossless Image Compression and Decompression
## 4 Validation and Analysis
### Performance of Proposed System  
The lossless compression ratio was assessed using tile sizes of 4 \(\times\) 4, 8 \(\times\) 8, 16 \(\times\) 16, and full images. The system can also compress ARGB and RGB images. Comparisons were made with eight codecs, as detailed in Table 1. In this table, the last four rows of data refer to the proposed system, with the values in parentheses indicating the size of the tile. \"Full\" indicates that the image was not divided into tiles and was instead compressed using the entire image. The proposed system demonstrated optimal compression performance across various datasets, particularly excelling with full-image and 16 \(\times\) 16 tile sizes. Notably, the compression efficiency declined with a tile size of 4 \(\times\) 4, indicating that larger tiles yield better results for diverse image modalities. Table 2 presents a comparative analysis of the proposed system against several previously reported implementations of lossless image compression algorithms. The comparison includes metrics such as operating frequency, throughput, resource utilization, and the hardware platform used. From the table, it can be observed that earlier designs, such as the 2009 Spartan-3 implementation [17], operated at relatively low frequencies and achieved limited throughput, reflecting the constraints of older FPGA technology and simpler pipeline structures. More recent works, including those from 2021 [14], 2022 [13], and 2024 [12], have shown substantial improvements in throughput due to enhanced pipeline depth and optimized algorithm-hardware integration. The proposed system, implemented on a Zynq-7000 XC7Z045 platform, achieved the highest throughput among all the compared designs: 480 Mpixels/s at a clock frequency of 300 MHz. This was accomplished while maintaining a moderate resource utilization, suggesting a balanced trade-off between speed and logic complexity. This also demonstrates the effectiveness of the proposed pipelined architecture and tile-based parallel processing strategy. Table 3 presents a comparative evaluation of the decompression performance between the proposed system and several existing JPEG-LS-based implementations. The comparison includes operating frequency, throughput, logic resource usage, and the FPGA technology employed. The earliest implementation, reported in 2002 [31], achieved a modest throughput of 7.14 Mpixels/s with 20k equivalent gates, reflecting the technological limitations of the time. Improvements were observed in 2015 [32] with the use of a Virtex-6 platform, where the throughput was increased to 21.07 Mpixels/s at 66.66 MHz using only 1.4k LUTs. A more recent design from 2024 [12], implemented on a Zynq-7000 XC7Z020, \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Method** & **ImageNet64** & **DIV2K** & **CLIC.p** & **CLIC.m** & **Kodak** \\ \hline PNG [10] & 1.22 & 1.30 & 1.34 & 1.34 & 1.29 \\ JPEG-LS [11] & 1.28 & 1.50 & 1.54 & 1.65 & 1.46 \\ CALIC [9] & 1.26 & 1.48 & 1.53 & 1.62 & 1.45 \\ JPEG2000 [29] & 1.26 & 1.47 & 1.51 & 1.58 & 1.45 \\ WebP [2] & 1.29 & 1.47 & 1.52 & 1.57 & 1.45 \\ BPG [8] & 1.29 & 1.43 & 1.48 & 1.54 & 1.42 \\ Proposed (4 \(\times\) 4) & 1.09 & 1.27 & 1.38 & 1.41 & 1.27 \\ Proposed (8 \(\times\) 8) & 1.27 & 1.47 & 1.50 & 1.62 & 1.44 \\ Proposed (16 \(\times\) 16) & 1.28 & 1.50 & 1.52 & 1.64 & 1.45 \\ Proposed (full) & 1.28 & 1.50 & 1.53 & 1.64 & 1.45 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Comparison with other methods using compression ratio metric.