# High-Performance QC-LDPC Code Co-Processing Approach and VLSI Architecture for Wi-Fi 6
## 1 Introduction  
Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes have been widely used in wireless communication protocols, with their excellent error correction performance and relative ease of implementation. Like the Wireless Local Area Network (WLAN) series protocol IEEE 802.11n/ac/ax, the QC-LDPC encoding scheme of the Data Field (DF) is optional in IEEE 802.11n/ac [1]. Furthermore, in IEEE 802.11 ax, it is stipulated that only QC-LDPC encoding can be used when the modulation method is 1024 Quadrature Amplitude Modulation (QAM) or the resource units are more significant than 484 [2]. To ensure that the encoded data can be sent in a string of integer symbols and the rate matches, different protocols adopt their processing characteristics. If the amount of data to be sent in IEEE 802.16e is less than the allocated amount, redundant ones are added at the end of the data [3]. For 5G NR, the bit sequence after encoding is written into a circular buffer and combines with the Hybrid Automatic Repeat Request (HARQ) to complete the rate matching [4]. For the WLAN, exact symbol matching is carried out by pre-processing before encoding and post-processing after encoding. Pre- and post-processing can be collectively referred to as co-processing. Decoding is the inverse process of encoding. The decoder's pre-processing and post-processing correspond to the encoder's post-processing and pre-processing. The difference is that the acquisition of the decoding parameters depends on the parsing of the received frame. Taking the decoder as an example, after the receiver completes the demodulation to obtain the soft information of the DF, the pre-processing module adds the shortened bits and punctured bits or removes the repeated bits according to the given parameters, and spells out a series of complete codewords to the decoder core. The post-processing module extracts pure Physical Layer Service Data Unit (PSDU) data from the information bits in the codewords when the decoding is completed. In the actual processing process, due to the uncertainty of user data size and the selectivity ofmodulation mode and spatial stream number, Wi-Fi 6 co-processing needs to deal with more than \(10^{6}\) situations. At the same time, the time slot budget needs to be allocated to compute-intensive tasks such as demodulation and decoding, and the overall latency of the co-processor is less than 1 us, which brings challenges to the circuit design of co-processing.  
Although wireless communication protocols widely use co-processing, and its theoretical research is endless, there has been no research on co-processing implementation [5; 6; 7]. [PERSON] mentioned coprocessing in his encoder architecture, but did not give a specific implementation [8]. This paper first proposes a QC-LDPC code co-processing method and VLSI architecture for Wi-Fi 6, which can be compatible with all possible protocol scenarios through reasonable hierarchical division and field analysis. Through the ping-pong operation of the block splicing module, the problem of practical input across blocks is solved. This paper is organized as follows: Section 2 introduces the decoder's parameter calculation and decoding process. Section 3 presents the methods and architectures for pre-processing and post-processing of decoders. Section 4 gives the implementation results, and Section 5 provides a summary.