# Reducing LUT Count for FPGA-Based Mealy FSMs
## 6 Experimental Results
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Benchmark** & **Auto** & **One-Hot** & **JEDI** & **DEMAIN** & **Our Approach** & **Category** \\ \hline ex1 & 70 & 74 & 53 & 57 & 40 & 2 \\ kirkman & 42 & 58 & 39 & 41 & 33 & 2 \\ planet & 131 & 131 & 88 & 94 & 78 & 2 \\ planet1 & 131 & 131 & 88 & 94 & 78 & 2 \\ pma & 94 & 94 & 86 & 91 & 72 & 2 \\ s1 & 65 & 99 & 61 & 64 & 54 & 2 \\ s1488 & 124 & 131 & 108 & 112 & 89 & 2  
such an FSM in the known literature. We have got its structural diagram by transformation the FSM \(U_{2}\) (Figure 2). We replaced the multiplexer by the block \(LUTerP\); the memory block is replaced by \(LUTerTY\). The \(LUTerP\) implements the system (5), the LUTerTY the systems (6) and (7). The FSM \(U_{6}\) is based on the encoding of collections of outputs (Figure 12b). There is no such an FSM in the known literature. We have got its structural diagram by transformation the FSM \(U_{3}\) (Figure 3). We replaced the block \(EMBer\) by the block \(LUTerTZ\) generating functions (2) and (11). As it is for FSM \(U_{3}\), the \(LUTerY\) implements the system (10). The FSM \(U_{7}\) is based on the transformation of state codes into outputs (Figure 12c) [35]. In this FSM, additional variables from the set \(V\) replace inputs for output functions. The FSM \(U_{8}\) is based on the transformation of collections of outputs into state codes (Figure 12d) [35]. In this FSM, additional variables from the set V replace inputs for input memory functions. Both methods belong to the group of object transformation methods [35]. We do not discuss these approaches in this article. We just use them as examples of FSMs having two levels of logic. Figure 11: Experimental results for categories 2–4 (the number of LUTs—total percentage). Figure 10: Experimental results for category \(1\) (the number of LUTs—total percentage). We compared the FSMs (Figure 12) with our approach for the most complex benchmarks (categories 2-4). The results of experiments are shown in Table 10 and Figure 13. As follows from Table 10, our method produces better results for FSMs than it is for FSMs \(U_{5}\)-\(U_{8}\). There is the following economy: (1) 17.11% regarding \(U_{5}\); (2) 11.95% \(U_{6}\) (3) 20.18% regarding \(U_{7}\) and 4) 9.1% regarding \(U_{8}\). So, our approach produces FSM circuits with better amount than two-level Mealy FSMs having \(L+R\geq 12\). However, the gain is noticeably less than for \(U_{1}\)-based FSMs from these categories. Figure 12: Structural diagrams of LUT-based Mealy FSMs with two-levels of logic: (**a**) replacement of inputs; (**b**) encoding of collections of outputs; (**c**) transformation of state codes into outputs; (**d**) transformation of collections of outputs into state codes. Figure 13: Comparison diagrams of our approach with two-level FSMs. So, the results of our experiments show that the proposed approach can reduce the LUT counts respectively to single- and two-level Mealy FSMs having \(L+R\geq 12\). Of course, this conclusion is true only for benchmarks [27] and the device XC7 VX690 ffg1761-2 by Virtex-7, where LUTs have 6 inputs. It is almost impossible to make a similar conclusion for the general case. However, we hope that our approach rather good potential and can be used in CAD systems targeting FPGA-based Mealy FSMs.