# A Reconfigurable Framework for Hybrid Quantum-Classical Computing
###### Abstract  
Hybrid quantum-classical (HQC) computing refers to the approach of executing algorithms coherently on both quantum and classical resources. This approach makes the best use of current or near-term quantum computers by sharing the workload with classical high-performance computing. However, HQC algorithms often require a back-and-forth exchange of data between quantum and classical processors, causing system bottlenecks and leading to high latency in applications. The objective of this study is to investigate novel frameworks that unify quantum and reconfigurable resources for HQC and mitigate system bottleneck and latency issues. In this paper, we propose a reconfigurable framework for hybrid quantum-classical computing. The proposed framework integrates field-programmable gate arrays (FPGAs) with quantum processing units (QPUs) for deploying HQC algorithms. The classical subroutines of the algorithms are accelerated on FPGA fabric using a high-throughput processing pipeline, while quantum subroutines are executed on the QPUs. High-level software is used to seamlessly facilitate data exchange between classical and quantum workloads through high-performance channels. To evaluate the proposed framework, an HQC algorithm, namely variational quantum classification, and the MNIST dataset are used as a test case. We present a quantitative comparison of the proposed framework with a state-of-the-art quantum software framework running on a server-grade CPU. The results demonstrate that the FPGA pipeline achieves up to 8\(\times\) improvement in runtime compared to the CPU baseline. hybrid quantum-classical computing; reconfigurable computing; field-programmable gate arrays [1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29  
HPC system but connected by a network, either on or off premises, and (2) tight integration, where the QPU is located directly on an HPC node. The loose integration model is more practical today and in the near future; however, there are several crucial research challenges involved in developing such quantum-classical integrated systems. Firstly, computational bottlenecks arise in a system with both quantum and classical resources, with QCs having different latencies and I/O time than conventional processors, which have a sequential nature of execution. Secondly, there is a lack of cost-effective heterogeneous platforms facilitating rapid testing, prototyping, and benchmarking of integrated quantum-classical workflows. QC-HPC platforms that are undergoing development are not yet available to researchers, who require a cost-effective platform for developing and benchmarking hybrid quantum-classical applications before deploying them on actual large-scale systems. Thirdly, there is also a lack of unified software environments for deploying algorithms on quantum-classical architectures. In integrated environments, software schedulers are critical for efficient workload distribution and sharing among quantum and classical resources. These challenges have thus far hindered the progress of quantum-classical computing toward demonstrating computational advantage [6]. Reconfigurable computing is a computing paradigm that combines some of the flexibility of software with the high-performance of hardware by processing with cost-effective reconfigurable technology such as field-programmable gate arrays (FPGAs). The principal difference compared to conventional processors is the ability to add custom computational blocks using FPGAs. FPGAs have played critical roles in quantum computing: they are used as control processors to control and measure superconducting quantum processors [7; 8]; they are used to develop low-latency scalable architectures for quantum error correction [9]; and they are also used for quantum circuit emulation/simulation [10; 11].