## 4 System Implementation and Simulation Results
### Physical Implementation  
For the physical implementation of the circuit, the power transistors are first laid out. Initially, 70% of the available chip area is designated for the power transistors, with the remaining 30% designated for the gate drivers. Through an iterative process, the combination of device channel width, length, and number of parallel elements are adjusted to fully utilize the available chip area of 25 mm\({}^{2}\) (5 mm by 5 mm). These components are selected from the IISB's 2 \(\upmu\)m 4H-SiC CMOS PDK, with the selection criteria based on the current capacity of the devices. The resulting sizes of the transistors for one channel, along with their multiplicities and important characteristics such as the on-resistance and gate capacitances, are shown in Table 4. The \(R_{on}\) value has been estimated with the approximation \(V_{ds}/I_{d}\) at \(V_{gs}=20\) V. Note that, the already reported value for \(R_{on}\) for the 4H-SiC CMOS PDK is 53 m\(\Omega\) cm\({}^{2}\)[40], i.e., for the case of the NMOS \(M_{2}\) the total transistor area is 0.0082 cm\({}^{2}\) and the equivalent on-resistor is \(R_{on}=6.46\)\(\Omega\). This value is high for power SiC MOSFETs, but this technology is for CMOS ICs, so high values are expected. Note that, the obtained \(R_{on}\) value is higher for PMOS \(M_{1}\) than for NMOS \(M_{2}\). This is the main reason why in the power electronics field the NMOS designs are preferred. For the proper operation of the gate drivers, the dimensions of each transistor have been carefully selected, as detailed in Table 5. Transistors \(M_{D3}\) and \(M_{D4}\) are dimensioned identically to \(M_{D1}\) and \(M_{D2}\), respectively. Additionally, the designs of the output stage transistors \(M_{D5}\), \(M_{D6}\), \(M_{D7}\), and \(M_{D8}\) specifically address the current drive requirements for activating the gates of the power transistors. The designed gate drivers operate with a rectangular input signal \(V_{S1,2}\) varying between 0 V and 12 V, ensuring reliable transistor activation as it surpasses the threshold voltage [33], which is crucial for proper operation. Additionally, 12 V is a commonly used value in industrial systems, making it a practical choice. The system is operated at a nominal frequency of 75 kHz, which is a reasonable value that allows off-chip control and dead time generation using a conventional FPGA. It requires power supplies of \(V_{DD}=12\) V and \(V_{H}=20\) V. The expected output signal is \(V_{G1,2}\), with a high voltage level of 20 V. The layout of the implemented system can be seen in Figure 4. This figure illustrates the arrangement of the power transistors and gate drivers within the allocated chip area. The layout strategy incorporates a rectangular device structure with multiple transistors in parallel using a finger layout. This design ensures a more uniform distribution of current than other techniques [46], enhancing the overall reliability and efficiency of the converter. The iterative process to finalize the transistor sizes ensures that the chip area is used efficiently, balancing the needs of the power transistors and gate drivers for the target performance. The passive components used for the system nominal design include three non-coupled inductors with a value of \(L_{01,2,3}=450\) uH, and a capacitor and load resistor with values of \(C_{o}=8.7\) nF and \(R_{o}=40\)\(\Omega\) and \(R_{o}^{\square}=3R_{o}\), respectively. These components \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Description** & **Symbol** & \(M_{1}\) & \(M_{2}\) \\ \hline Width & W [\(\mu\)m] & 100 & 20 \\ Length & L [\(\mu\)m] & 6 & 2 \\ Multiplier 1  & Mult & 1406 & 896 \\ On resistance & \(R_{on}[\Omega]\) & 17.39 & 5.05 \\ Gate-source capacitance & \(C_{gg}\) [pF] & 465.1 & 38.3 \\ Total transistor area & A [mm\({}^{2}\)] & 3.74 & 0.82 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Transistor sizing for \(M_{1}\) (power PMOS) and \(M_{2}\) (power NMOS) of one channel.