# The Fast Detection and Identification Algorithm of Optical Fiber Intrusion Signals
## 3 The Implementation of Recognition Algorithm and the Experimental Analysis  
### The Implementation of Fast Identification Algorithm  
As shown in Figure 7, the optical fiber early warning system is equipped with an optical pulse transmitting board, an optical pulse receiving board, a signal processing board, a data switching board, a motherboard, and a display. Optical pulse-emitting plates are used to modulate, amplify, and emit light pulses. The optical pulse-receiving plate is for receiving backscattered light in the optical fiber and converting the optical signal into an electrical signal. The signal processing board is used to collect and process data, complete the detection and identification of the intrusion signal, and send the alarm result to the upper computer. The software architecture designed in this paper is implemented in the signal processing board. The motherboard runs the host computer software, together with the display to complete the display of the alarm results and the setting of the system parameters. As shown in Figure 8, the fiber-optic warning system signal processing board is equipped with two TS201 processors, one FPGA processor and one PowerPC processor, as well as multiple memory and interface circuits. The signal processing board inputs the in-phase analog signal Sig_I and the quadrature analog signal Sig_Q, and the ADC module with the sampling frequency of 100 MHz is converted into a digital signal; the FIFO queue in the FPGA module is used to read the data in the ADC and cache, and the FPGA takes 1 ms as the the cycle simultaneously initiates an interrupt request to DSP1 and DSP2; DSP1 and DSP2 respond to the interrupt request and read the cache data from the FIFO queue of the FPGA. In addition, the peripheral interface of DSP1 and DSP2 is implemented in the FPGA to ensure data between the two DSPs and the PowerPC. Transparent transmission; PowerPC is responsible for communication with the host computer, and managing DSP software upgrades. Figure 7: Optical fiber Pre-warning monitoring system. As shown in Figure 9, the entire system is consisted of DSP and host computer. The DSP module is used for optical fiber intrusion signals acquisition at the test site and subsequent signal processing. A mechanical drill is used to shovel the soil near the underground optical fiber, and the mechanical drilling signals are collected. Near the underground optical fiber, electric pick is used to excavate the soil and generate mechanical picking signals. We generate the walking signals by walking around the optical fiber. According to the characteristics and requirements of algorithm implementation on embedded hardware, the computational complexity and operation time of each algorithm module are analyzed. The algorithm flow is decomposed into different processors on the board. The processing flow after filtering is distributed in two parallel-processing DSPs. The two DSPs work in parallel and the intermediate results are input to the Synchronous Dynamic Random Access Memory (SDRAM) through the data bus. The external raw data is input to the DSP through the AD interface and LINK port. Finally, the identification results are sent to the host through the PCI interface. The processing flows in the two DSPs are shown in Figure 10. First, the raw data is received from the TTL interface. Then it is sent to DSP1 through the link port, and stored in the Ping-Pang SDRAM memory. At the same time, DSP1 obtains the data of 1024 ms from the Ping-Pang memory for the subsequent high-pass filtering, and the results are stored in the on-chip RAM. After the detection and identification processing of the first 512 ms filtered data is completed, the results are uploaded through the PCI bus. Then DSP1 waits for the next 1024 ms of data. At the same time, DSP2 obtains the filtered data of the second 512 ms from the Ping-Pang structure for subsequent processing. DSP1 and DSP2 work in parallel mode, and finally determine the output signal type. In this way, parallel flow  
Figure 8: Signal processing board module diagram.