# Bounding Volume Hierarchy-Assisted Fast SAR Image Simulation Based on Spatial Segmentation
## 3 Fast SAR Image Simulation Based on Spatial Segmentation
### CUDA Thread Organization Based on Spatial Segmentation  
Combining the design characteristics of the CUDA kernel function and the characteristics of the SAR phase reference system, we encode the correspondence between each echo matrix cell and the thread index of the CUDA 3D Grid and design a thread organization architecture that is compatible with the CUDA kernel function, as shown in Figure 6. The azimuthal and range direction of the echo matrix are divided into grids corresponding to the thread index \((X,Y)\) of the planar dimension of the 3D Grid, respectively; the position of the spatial segmentation processed latticed blocks corresponds to the thread index \((Z)\) of the longitudinal dimension of the 3D Grid, and the number of the latticed blocks determines the size of the longitudinal dimension (\(Z\)-axis) of the 3D Grid. We give specific constraints among the size of the lattice radiation area, the number of latticed blocks, the size of the 3D thread grid, the size of the 3D thread block, and the actual configuration parameters of the computer, controlling the parameters of the CUDA software into a reasonable range to ensure the effective operation of the CUDA program. The constraints can be expressed in Equation (11). \[\left\{ \begin{array}{l}\text{sum\_segs}=\lceil(\text{P}_{z}+\text{sub\_seg }-1)\,/\text{sub\_seg}\rceil\\ \text{gridDim.z}=\lceil(\text{sum\_segs}+\text{blockDim.z}-1)/\text{blockDim.z}\rceil\\ \text{gridDim.x}=\lceil(\text{echo.cols}+\text{blockDim.x}-1)/\text{blockDim.x}\rceil\\ \text{gridDim.y}=\lceil(\text{echo.rows}+\text{blockDim.y}-1)/\text{blockDim.y}\rceil\\ \text{blockDim.x}*\text{blockDim.y}*\text{blockDim.z}\leq\text{maxThreadsPerBlock} \\ \text{gridDim.x}*\text{gridDim.y}*\text{gridDim.z}\leq\text{maxBlocksPerGrid} \end{array} \right. \tag{11}\]  
where sub_seg is e size of the latticed block; sum_segs is e number of latticed blocks; P\({}_{z}\) denotes the number of lattice radiation areas; blockDim and gridDim denote the size of the 3D thread grid and 3D thread block, respectively; and maxThreadsPerBlock and maxBlocksPerGrid denote the capacity size of the thread block and the thread net, respectively. echo.cols and echo.rows are the number of sampling points along the azimuth and range directions of the target echo matrix, respectively. The index value of the planar dimension of the thread grid corresponds to each cell of the target echo matrix, and the  
Figure 6: CUDA thread organization based on spatial segmentation. number of rows and columns of the echo matrix is determined by the parameters of the SAR system and the area of the simulation scene, which can be referred to in Equation (12). \[\left\{ \begin{array}{l}L_{s}=0.886\lambda/D_{a}\cdot R_{0}\\ N_{a}=(x_{\max}-x_{\min}+L_{s})/V_{r}\cdot PRF\\ N_{r}=(2R_{\min}/c-2R_{\max}/c+T_{r})F_{r}\end{array} \right. \tag{12}\]  
where \(L_{s}\) is the synthetic aperture length; \(N_{a}\) and \(N_{r}\) are the number of azimuthal and range sampling points, matching with the number of rows and columns of the echo matrix; \(\lambda\) is the wavelength; \(D_{a}\) is the azimuthal length of real aperture; \(R_{0}\) is the shortest slant range in the scene; \(x_{\max}\) and \(x_{\min}\) are the azimuthal maxima and minima of the simulation scene, respectively; \(V_{r}\) is the effective radar velocity; \(PRF\) is the pulse frequency; \(R_{\max}\) and \(R_{\min}\) are the near and far slant range, respectively; \(c\) is the light speed; \(T_{r}\) is the pulse width; and \(F_{r}\) is the range sampling frequency. In order to further reduce the workload of each thread, each echo matrix cell matching with the two-dimensional envelope window is utilized to select the coherent lattices in each latticed block, and only a small number of coherent lattices falling into the two-dimensional envelope window are launched with EM waves and tracked for their multiple scattering paths. This step substantially reduces the amount of computation in each thread and accomplishes the local optimization of the CUDA kernel function.