esa-sceva/satcom-chunk-collection huggingface dataset:
# Enhancing Privacy in Large Language Model with Homomorphic Encryption and Sparse Attention
## 3 Materials and Methods
### Experiment Configuration  
#### 3.4.1 Experimental Evaluation Metrics  
When evaluating the privacy-preserving transformer framework based on FHE and attention mechanisms, key performance indicators include accuracy, response time, and computational efficiency. These metrics are crucial for understanding the practicality, efficiency, and security of the model. Below, each evaluation metric's mathematical definition and its importance are described in detail. Accuracy is typically measured by three metrics: precision, recall, and accuracy.  
**Precision:** Precision refers to the proportion of true positives among the samples predicted as positive by the model. It is calculated as:  
\[\text{Precision}=\frac{TP}{TP+FP} \tag{22}\]  
where \(TP\) represents true positives, the number of samples correctly predicted as positive by the model; \(FP\) represents false positives, the number of samples incorrectly predicted as positive.  
**Recall:** Recall indicates the proportion of actual positive samples that are correctly predicted as positive by the model. It is calculated as:  
\[\text{Recall}=\frac{TP}{TP+FN} \tag{23}\]  
where \(FN\) represents false negatives, the number of samples incorrectly predicted as negative by the model.  
**Accuracy:** Accuracy refers to the proportion of samples correctly predicted by the model (regardless of positive or negative) out of the total number of samples. It is calculated as:  
\[\text{Accuracy}=\frac{TP+TN}{TP+TN+FP+FN} \tag{24}\]  
where \(TN\) represents true negatives, the number of samples correctly predicted as negative by the model.  
**Latency:** Latency measures the time taken for the model to respond to a request, which is vital for user experience. In a homomorphic encryption environment, maintaining reasonable latency is challenging due to increased computational complexity. Latency is typically expressed as the average processing time for individual requests:  
\[\text{Latency}=\frac{1}{N}\sum_{i=1}^{N}t_{i} \tag{25}\]  
where \(N\) is the total number of requests, and \(t_{i}\) is the time taken to process the \(i\)-th request.  
In experiments, these evaluation metrics will be used to compare the performance of our privacy-preserving model framework with other baseline models. Through the comparison of these quantitative metrics, the advantages and potential areas for improvement of the proposed model in this paper can be objectively demonstrated. Furthermore, they assist in understanding the model's performance in real-world applications and how the model can be further optimized to meet practical needs.
## 5 Simulation-to-Reality Transfer  
Deep reinforcement learning is a relatively novel technology with a promising future in the industry field. However, its major challenge is the implementation in real-world tasks, which demands an increase in the stability, sample efficiency and generalisation of DRL algorithms [198]. To improve these aspects and avoid the drawbacks of training with real environments, the current trend is to first train the algorithm in simulated environments and then test it in real environments [199]. Nonetheless, the knowledge transfer from simulation to reality is not straightforward. To this end, there is an area in reinforcement learning called sim-to-real transfer that encompasses a whole ream of techniques to achieve an effective learning transfer [200]. This section presents the most used ones in industrial DRL applications. The selection of the simulator is crucial for attaining a successful transfer from simulation to reality [200]. The more realistic a simulation is, the better performance of the algorithm may be expected in real-world tasks. Additionally, in industrial use cases, many factors must be considered due to their complexity, such as physic simulations, virtual representations of objects, recreations of sensor data and artificial lightning [201]. Gazebo [202], Unity3D [203], PyBullet [204] and MuJoCo [205] are the most popular simulators in the literature thanks to their accurate physics engine and customisable environments. These platforms allow for creating customised environments, loading pre-existing models of robots and systems and simulating the interaction between them and other elements. In addition, benchmark suites can be loaded into those platforms, such as Arena-bench [206], which allows training, testing and evaluating navigation algorithms for dynamic obstacle avoidance. Regarding the performance of the aforementioned simulators, Gazebo and Unity3D offer highly realistic simulations of complex scenarios, while PyBullet and MuJoCo slightly reduce these features in exchange for faster simulations. Table 1 gathers some examples of DRL applications trained to learn industrial tasks in those simulators. Lastly, although they are not simulators as such, special mention should be made of digital twin models for training, as they improve the performance of the algorithm in real-world tasks by improving the simulation environment [159]. In most cases, training with a realistic simulated environment and an appropriate hyperparameter setting of the algorithm does not guarantee the successful performance of the algorithm in the real task. For this purpose, there are numerous sim-to-real techniques that help to bridge the gap between simulation and reality. Based on the literature search, three
# Review on Optimization Techniques of PV/Inverter Ratio for Grid-Tie PV Systems
## 2 Literature Review
### Derating Factor of PV Technology  
The derating factor in PV technology is not difficult to understand from the standpoint of system design concerns. Numerous researchers have remarked that they are more concerned with the number of electrical characteristics produced by PV modules, such as voltage, current, and power outputs. Three researchers stated that the LID phenomenon has a detrimental effect on the usage of PV in terms of sizing consideration. Their study [37] only conducted one investigation, which accounted for a sizing ratio value of approximately 0.98. When designing and sizing, the recommended value should be adjusted between 0.90 and 0.99. However, as DC/AC increases, the inverter is more likely to derate.  
The preliminary power stability of PV technologies was confirmed below 1%, while only a few cases showed more than 4%, according to other authors [38]. Over several days of exposure, stability was observed for all of them. One recent study, summarized in [39], revealed that with c-Si technology, the preliminary LID often takes place over the variety of 2% to 4%, with LID predominating in terms of power decrease. According to a study by [40], the potential of the LID phenomena may typically be created by 30% to 10% in the initial few months of outside coverage.
## 4 Discussion
### Compatibility Analysis with the Cascading PCPE-BPS Algorithm  
In this subsection, the compatibility of the proposed scheme with the cascading PCPE-BPS algorithm is simulated and analyzed. The PCPE-BPS algorithm is a two-stage phase recovery algorithm proposed in [17] to further improve the MI performance of the PCPE algorithm in the high SNR range. The main idea is to use the PCPE algorithm for coarse phase recovery in the first stage, and then perform a BPS algorithm for second stage recovery with test phases of [17]:  
\[\varnothing_{b}=\eta\pi\bigg{(}\frac{2b-1}{4B_{2}}-\frac{1}{4}\bigg{)},\ b\in\{1,2, \ldots,B_{2}\}, \tag{10}\]  
where \(B_{2}\) represents the total number of test phases and \(\eta\) represents the phase aperture in which the fine phase recovery will be carried out.  
In order to explore the compatibility of the PCPE-BPS algorithm with the proposed GS scheme, the simulation system in Section 3.1 is used again, and the performance is studied and compared under the same parameter settings. The obtained simulation results shown in Figure 15 indicate that, for both 32 QAM and 128 QAM modulation formats, the MI performance of the PCPE-BPS algorithm can be significantly improved by using the GS scheme proposed in this paper. Taking the 20% SD-FEC threshold as a reference, SNR gains of 0.82 dB and 1.82 dB can be achieved, respectively.
# The Impact of Pressure on the Fingerprint Impression: Presentation Attack Detection Scheme
## 6 Experimental Results
### Experiment IV: Comparison with SoA Mechanisms  
Literature studies had aimed to evidence the assumption that under certain presentation instruction, genuine fingerprints produce unique variation or distortion patterns that assist the process of detecting attacks. The aforementioned assumption counts on the natural structure of the human finger and its phenomena, such as elasticity, internal bone position, etc. Moreover, previous studies had attempted to define some characteristics of different PAI species. For instance, [PERSON] et al. [34] had studied five PAI species and concluded that artificial artefacts are more rigid than genuine fingerprints. Thus, the produced distortion while rotating and pressuring the finger during a presentation is higher for genuine users.  
In this experiment, we compare our results with previous studies on static and dynamic PAD (Table 10). We find that the obtained results are significantly improved compared to the SoA methods based on fingerprint distortion features. In addition, a wider set of attack species were used in this investigation.  
We find that the obtained results are significantly improved compared to the SoA results, even though a wider set of attack species were used in our experiments.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Category** & **Method** & **TER (\%)** & **APCER (\%)** & **BPCER (\%)** \\ \hline \multirow{4}{*}{**Distortion-based**} & [PERSON] et al. [34] & 11.24 & - & - \\ \cline{2-5}  & [PERSON] et al. [35] & 4.5 & - & - \\ \cline{2-5}  & [PERSON] et al. [36] & 4.78 & - & - \\ \cline{2-5}  & **Proposed** & 1.67–2.38 & 5 & 0–1.66 \\ \hline \multirow{2}{*}{**Hardware/based**} & [PERSON] et al. [15] & - & 7 & 0.1 \\ \cline{2-5}  & [PERSON] et al. [17] & \multicolumn{3}{c}{Classification accuracy = 98.8\%} \\ \hline \multirow{4}{*}{**Handcrafted features**} & [PERSON] et al. [18] & - & 13 & 14 \\ \cline{2-5}  & [PERSON] et al. [19] & - & 5 & 4.3 \\ \cline{2-5}  & [PERSON] et al. [20] & \multicolumn{3}{c}{Classification accuracy = 96.17\%} \\ \cline{2-5}  & [PERSON] et al. [22] & - & 5 & 18.1–19.5 \\ \cline{2-5}  & [PERSON] et al. [23] & - & 5 & 1.11–3.89 \\ \hline \multirow{4}{*}{**Deep features**} & [PERSON] et al. [24] & \multicolumn{3}{c}{Classification accuracy = 97.1\%} \\ \cline{2-5}  & [PERSON] et al. [25] & \multicolumn{3}{c}{Classification accuracy = 99.03\%} \\ \cline{2-5}  & [PERSON] et al. [28] & \multicolumn{3}{c}{Average Classification Error = 3.6\%} \\ \hline \hline \end{tabular}
\end{table}
Table 10: Comparison with fingerprint-deformation-based PAD mechanisms.  
Figure 13: PAD mechanisms capability of eliminating PAI species.
# EXPRESS: Exploiting Energy-Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage
## 4 Experimental Evaluation
### Experimental Setup  
Figure 5 shows our experimental setup, which consists of a TSOP-48 socket that holds a flash memory chip, an FT2232H mini module from Future Technology Devices International (FTDI), and a workstation. The FT2232H module acts as a bridge between the workstation and the device, implementing an asynchronous 8-bit parallel interface to the device, as described in Figure 3. A software package running on the workstation executes the ONFI commands for sending data to the flash memory chip, erasing a block, writing a page, reading a page, or retrieving the data from the device. This hardware setup allows us to access raw memory bits without any error correction. We used a logic analyzer and a Digilent Analog Discovery II multifunction instrument to measure the time and capture the voltage samples from a shunt resistor connected to the power line of the TSOP socket. We performed the experimental evaluation on several 3D NAND MLC chips, with the following properties: the chip capacity is 256 Gbits; the number of blocks is 2192; each block contains 1024 pages; and each page contains 18,592 bytes of data (16,384 bytes of user data, with 2208 spare bytes reserved for storing out-of-band information, such as error correction codes). The chip was manufactured using 32-layer 3D technology.
## 3 Results and Discussion
This applied to apartments A1, A4, A5, and A7. The number of overheating hours above category I was in a range between 62 and 163. If the highest temperature was between 28.5 \({}^{\circ}\)C and 30.0 \({}^{\circ}\)C, the extreme thermal conditions were estimated as +2, meaning warm. These votes were given by the residents of apartments A3 (both female and male), A6 (both female and male), A8, and A10. The number of overheating hours above category I was between 0 and 52 in those cases. The highest noted temperature below 28.0 \({}^{\circ}\)C meant a +1 (slightly warm) perception of the worst experienced conditions. In those two cases (A2 and A9), the highest number of overheating hours was negligible, namely 0 or 3. Another observation from the survey was a probable tendency to overestimate the overheating time by the polled occupants. According to the adaptive comfort assessment, the percentage of overheating hours compared with the presented time of observation did not exceed 10.5%. However, the inhabitants of the least comfortable dwellings graded the \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**No.**} & \multirow{2}{*}{
\begin{tabular}{c} **Extreme** \\ **Conditions** \\ \end{tabular} } & \multicolumn{4}{c}{**Share of Time Within the Conditions**} & \multicolumn{2}{c}{**Highest Noted**} & \multicolumn{2}{c}{**Highest Number of**} \\ \cline{3-8}  & & **+3** & **+2** & **+1** & **0** & **Temperature** [\({}^{\circ}\)C] & **Overheating Hours** \\ \hline A1 & +3 (hot) & 30\% & 20\% & 20\% & 30\% & 30.1 & 163 (10.5\%) \\ \hline A2 & +1 (slightly warm) & 0\% & 0\% & 50\% & 50\% & 26.4 & 0 (0.0\%) \\ \hline A3 & +2 (warm) & 0\% & 70\% & 15\% & 15\% & 28.9 & 5 (0.3\%) \\ \hline A4 & +3 (hot) & 60\% & 40\% & 0\% & 0\% & 30.0 & 62 (4.0\%) \\ \hline A5 & +3 (hot) & 60\% & 40\% & 0\% & 0\% & 30.3 & 163 (10.5\%) \\ \hline A6 & +2 (warm) & n.a. & n.a. & n.a. & & & \\ \hline A7 & +3 (hot) & 25\% & 45\% & 30\% & 0\% & 30.1 & 92 (5.9\%) \\ \hline A8 & +2 (warm) & 0\% & 35\% & 50\% & 15\% & 28.9 & 9 (0.8\%) \\ \hline A9 & +1 (slightly warm) & 0\% & 0\% & 50\% & 50\% & 28.0 & 3 (0.2\%) \\ \hline A10 & +2 (warm) & 0\% & 30\% & 40\% & 30\% & 29.7 & 52 (3.3) \\ \hline \hline \end{tabular}  
* n.a.: no answer, in case some of the people did not want to take part in the survey.  
\end{table} 
Table 6: Occupants’ perception of internal conditions. discomfort time as being from 25% to 60% of this period. It was difficult to compare the two scales, but this range of discrepancy may be confusing.
# Moving Deep Learning to the Edge
## 3 Deep Learning
### Deep Neural Network Models
The complete structure of ResNeXt is identical to the structure of ResNet with the residual module substituted by the new ResNeXt module. The new architecture improves the accuracy of ResNet from one to almost two percentage points. DenseNet [49] proposes a modified residual block where layers receive and concatenate data from all preceding layers within the block. Between dense blocks, there is a transition layer with a \(1\times 1\) convolutional layer and an average pooling layer. Different configurations were proposed for DenseNet with a different number of layers. For example, DenseNet-201 has an initial convolutional layer with a window of size of \(7\times 7\) followed by a \(3\times 3\) max pooling, then a sequence of 6, 12, 48, and 32 dense blocks and three transition layers in between. There is a final global \(7\times 7\) average pool and softmax function with 1000 classes. The Squeeze and Excitation network, SENet [50], introduced the squeeze and excitation block that can be added to inception or residual blocks. SENet includes a content-aware mechanism to remove or emphasize input channels dynamically. To implement the idea, the input maps are first squeezed to a single value using pooling followed by two fully connected layers. This results in a numeric value for each input channel. These weights are then used together with the original feature maps to scale the importance of each channel. This has a high impact on the size of the network. For example, ResNet-50 with the ResNet modules replaced by the squeeze and excitation blocks achieves the same accuracy as ResNet-101 with half the number of operations. The models described above are summarized in Table 2.  
The major goal of the networks described above is to improve accuracy as much as possible. The trend is to increase the depth as a way to enhance accuracy. To balance the inevitable increase in the number of weights, layers are grouped into blocks and large convolutions are replaced by a series of smaller convolutions. Dense layers require many weights, and therefore, recent networks have at \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & **Depth** & **Parameters (M)** & **Operations (G)** & **Top 5 Error (\%)** & **Top- 1 Error (\%)** \\ \hline
**AlexNet** & 8 & 61 & 1.45 & 15.4 & 36.7 \\
**ZfNet** & 8 & 60 & 1.47 & — & 36.0 \\
**VGG16** & 16 & 138 & 31.0 & 8.1 & 25.6 \\
**Inception-v1** & 22 & 5 & 2.86 & 10.1 & 30.2 \\
**Inception-v2** & 42 & 11 & 4.0 & 7.8 & 25.2 \\
**Inception-v3** & 48 & 24 & 11.4 & 5.6 & 21.2 \\
**Inception-v4** & 76 & 35 & 24.5 & 4.9 & 19.9 \\
**ResNet-152** & 152 & 60 & 22.6 & 4.5 & 19.4 \\
**ResNeXt** & 50 & 68 & 8.4 & 4.4 & 19.1 \\
**DenseNet-201** & 201 & 20 & 8.4 & 6.4 & 23.6 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Summary of popular accuracy-oriented DNN models. most one fully connected layer. Therefore, in CNN, most of the parameters and operations are now associated with the convolutional layers.
## 2 Interconnect Technologies in Power Electronics and SSL
### Sintering  
Particle sintering has emerged as a reliable alternative to soldering in recent years for high-temperature applications [18]. Sintering is a mass transport phenomenon driven by the reduction in surface energy [16] and can be classified into three main stages: an initial stage defined by the formation of necks between the particles in contact, an intermediate stage defined by the formation of interconnected pores and the onset of grain growth, and a final stage defined by the development of isolated pores, thereby removing any hindrance to grain growth. Therefore, sintering as an advanced packaging solution helps in realizing an interconnect at relatively low temperature (\(<\)300 \({}^{\circ}\)C) but with a near-bulk-like microstructure characterized by finely dispersed micro and nanopores. A silver/copper sintered interconnect, hence, provides thermal, electrical, and mechanical properties far superior to any of the standard solder materials and offers a high operating temperature range (\(>\)200 \({}^{\circ}\)C).  
Silver sintering under pressure has been industrialized for many applications in the power electronics sector [19], and copper sintering is being actively researched as a reliable low-cost alternative to silver sintering [20]. Stencil/screen printing, dispensing, and direct transfer film are some of the standard techniques used in the industry for die-attach applications using sinter pastes. Apart from the direct transfer film technique, a standard die-attach bonding sintering process involves the application of the sintering paste, a predrying step to remove excess volatile binder from the formation, and finally placement of the die and isothermal sintering under pressure. Pressureless sintering has also been suggested as an alternative process; however, reliability issues are a challenge to large-scale industrialization [21].  
One of the most frequently observed defects with sintering is delaminations. These could occur due to contamination of the bonding surfaces, an insufficient/ineffective predrying process in the case of sintering under pressure, and/or improper application of bonding force during sintering among other factors, affecting the thermal path and, thus, the performance of the interconnect. Furthermore, the sintered interconnect reveals a porous microstructure characterized by finely dispersed micro and nanopores, where less porous structures lead to better thermal performance.
# QoS-Aware Flexible Handover Management in Software-Defined Mobile Networks
###### Abstract  
Handover support is one of the important issues in mobile networks to guarantee the quality of service (QoS) requirements for mobile users. Alongside the development of network technologies, handover management to provide service continuity has been researched and applied for the Internet or cellular networks such as 3G/4G/5G. However, each network paradigm provides its own individual handover management system, even though there are different kinds of QoS requirements for various mobile services. This causes inefficient network resource utilization from the network operators' perspectives. Therefore, this paper proposes a QoS-aware flexible mobility management scheme for software-defined networking (SDN)-based mobile networks. The proposed scheme classifies flows into four classes based on the QoS requirements of services in terms of delay and loss tolerance. According to the classified service characteristics, it provides a differential handover method for each flow class to support efficient network operation without any service degradation by interacting between the forwarding plane nodes and SDN controller. The performance analysis shows that the proposed scheme enables flexible network resource utilization, satisfying the QoS requirements for each class well compared to the conventional schemes that only consider their own individual handover procedure.  
software-defined networking (SDN); mobility management; resource utilization; quality of service (QoS); handover +
Footnote †: journal: Applied Sciences