## 4 Direct Duty Ratio CSI PWM  
This modulator produces PWM signals for a three-phase system utilizing two triangular carriers and three reference signals. This method decreases losses caused by an effective switching frequency of two-thirds of the carrier frequency at each active switch by allowing for the direct creation of CSI gating signals from VSI signals and using overmodulation (see Figure 15). The CSI topology can be represented as a Single-Pole Triple-Throw Switch (SPTT). Figure 16a shows a simple circuit diagram of a three-phase CSI to illustrate the synthesis of the output phase currents. It determines the three phases (max, medium, min) according to the magnitude of the output currents (\(i_{a}^{*},i_{b}^{*},i_{c}^{*}\)). This simplifies the analysis by focusing on the maximum (max), medium (mid), and minimum (min) current phases at any given time. Figure 16b shows the waveforms of the maximum (\(i_{max}\)) and minimum (\(i_{min}\)) currents when balanced three-phase sinusoidal command currents (\(i_{a}^{*},i_{b}^{*},i_{c}^{*}\)) are applied. The maximum phase current \(i_{max}\) is always positive, and the minimum phase current \(i_{min}\) is always negative. Thus, the sum of the currents of the three phases will be equal to zero. These waveforms indicate the lowest and highest phase current values needed to create output current using the DDPWM method. Figure 14: Output current waveforms of the CSI using direct space vector modulation: (**a**) Unfiltered phase currents (red: phase 1, green: phase 2, blue: phase 3) and filtered sinusoidal output currents below Sector ID; (**b**) Sum of phase currents validating zero-sequence balance. Figure 15: Overmodulation capability of DDPWM [15]. Where \(S_{MXp}\) and \(S_{MXn}\) represent the maximum and minimum values of the three-phase currents. The relevant relations for the DDPWM operation are given below [15]:  
\[s_{MXp}=\overline{s}_{MDp}\,\ s_{MNp}=0 \tag{13}\]  
\[s_{MNn}=\overline{s}_{MDn}\,\ s_{MXn}=0 \tag{14}\]  
\[s_{MXp}=\left\{ \begin{array}{l}1\ \ \mathrm{if}\ \ i_{T1}<I_{MAX}\\ 0\ \ \mathrm{if}\ \ i_{T1}<I_{MIN}\end{array} \right. \tag{15}\]  
\[s_{MNn}=\left\{ \begin{array}{l}1\ \ \mathrm{if}\ \ i_{T2}<I_{MAX}\\ 0\ \ \mathrm{if}\ \ i_{T2}<I_{MIN}\end{array} \right. \tag{16}\]  
Figure 17 graphically shows Equations (15) and (16), therefore showing the generation of the minimum (\(S_{MNn}\)) and maximum (\(S_{MXp}\)) phase currents in the DDPWM system. The waveforms show the timing signals \(T_{MDp1}\), \(T_{MDp2}\), \(T_{MDn1}\), and \(T_{MDn2}\) together with the relationship between the input DC current (\(I_{DC}\)), the maximum (\(I_{MAX}\)), and minimum (\(I_{MIN}\)) thresholds. The timing signals control the duration of the related currents during each switching cycle. A proper output current waveform depends on the accurate decision for \(S_{MXp}\) and \(S_{MNn}\). Figure 18a shows a block diagram of the DDPWM, highlighting its key components. The Max-Min Identifier block determines the maximum and minimum phase currents. The values are then fed into the Upper and Lower SPTT Selectors, which produce the required gating signals according to the switching strategy. This direct approach simplifies the modulation process relative to alternative CSI modulation techniques. Figure 18b shows the subblocks of the simulation circuit that implement the DDPWM technique. The main CSI circuit is identical to that shown in Figure 3.  
Figures 19 and A4 in Appendix A illustrate subcircuits in Figure 18b that generate DDPWM. The three-phase reference signals (a, b, and c) and the DDPWM technique are implemented in the simulation model as shown in Figure 19. This figure describes the DDPWM technique and how the simulation produces the three-phase reference signals (a, b, and c). Figure 16: (a) CSI model using SPTT switches, (b) the max phase current \(i_{max}\) and the min phase current \(i_{min}\). Figure 17: Synthesis of max phase current on the left and min phase current on the right.