## 4 Experimental Verification
### Experimental Result 1: Verification of Output Characteristic  
Figure 8 shows the prototype IPT system manufactured for actual experimental verification. Figure 9a-c show the experimental waveforms of modes 1, 2, and 3 mentioned in Section 3, respectively. In short-circuit experiments, a short resistance with a value of 0.46 \(\Omega\) was used. Figure 9b shows that mode 2 can demonstrate, based on the electric load, that the resistance is 2000 \(\Omega\) with output voltage limitation. The maximum current and voltage were almost equal to the theoretical calculations, as illustrated in Figure 9a. Figure 9a,b show that the SS topology with the proposed design method can be verified to demonstrate self-limitation without any other control system or components. The measured short-current in Figure 9a is 24.1 A, which was equal to the value calculated using (18). The measured output voltage in Figure 9b was 35.1 V, which was equal to the value calculated using (17). Figure 8: (**a**) Prototype IPT system for experimental verification in the case of the proposed design method; (**b**) a prototype coil. As shown in Figure 9, the SS topology with the proposed design method achieved ZVS in all the ranges, thus reducing switching loss. Table 4 shows the results of the prototype experiments (voltage and current in the case of a short-circuit; \(P_{o}\) = 100, 200, 300, and 400 W; and an open-circuit). The short-circuit currents were measured by connecting a short resistance. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Symbols** & **Parameters** & **Values** \\ \hline \(U_{s}\) & DC link voltage & 96 V \\ \(I_{L}\) & Output load current & 21.5 A \\ \(C_{r}\) & Leakage resonance capacitor & 60.4 nF \\ \(R_{L}\) & Load resistance & 0.4–0.8 \(\Omega\) \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Result of prototype (Charging and fault) experiments. Figure 9: Experimental waveforms of the proposed topology: (**a**) Mode 1: short–circuit load; (**b**) Mode 2: open–circuit load; (**c**) Mode 3: charging region. Figure 10a-c show waveforms from major charging to short-circuit, from major charging to open-circuit, and from short-circuit to open-circuit, respectively. Experimental results were almost consistent with the output equation theories specified in Section 3. Figure 10 shows that the SS topology with the proposed design method prevented overcurrent and overvoltage in dynamic short-circuit and open-circuit, respectively. Experimental Result 2: Comparison of Output Characteristics and Efficiency with the Conventional Design Method  
Figure 11a,b show the experimental waveform of the SS topology with conventional design. As illustrated in Figure 11, the output current is independent of the load resistance value, and the input current waveform of the conventional SS topology design has a zero-phase angle. Figure 10: Input/output current and voltage waveforms for the proposed topology are: (**a**) from charging to short–circuit load; (**b**) from charging to open–circuit load; and (**c**) from short–circuit load to open–circuit load. Figure 12 shows the efficiency of the SS topology with the conventional design method and the proposed design method, which were measured using the power analyzer PW6001 from HIOKI. Because of the CC characteristics (minimum output resistance is 0.4 \(\Omega\)), the SS topology with the conventional design method was measured from 200 W to 400 W. The maximum efficiency of the SS topology with the proposed design method was 89.6% at 350 W. The maximum efficiency of the SS topology with the conventional design method was 87.1%. Owing to the current on the secondary side, the copper loss of the SS topology with the conventional design method was higher than with the proposed design method. Figure 13 shows a graph of the loss ratio at full load for the two topologies compared experimentally.