# A Novel Active Polyphase Filter Employing Frequency-Dependent Image Rejection Enhancement Technique
## 4 Simulation and Measurement Results
Figure 11: Simulated results of the single-stage APPF with input signals of different phases: (**a**) the quadrature input signal phase is 85\({}^{\circ}\); (**b**) the quadrature input signal phase is 90\({}^{\circ}\); and (**c**) the quadrature input signal phase is 95\({}^{\circ}\). Figure 14: OIP3 simulation result of the proposed single-stage APPF. Figure 12: Simulated results of the single-stage APPF at different PVT combinations: (**a**) TT-Typical voltage-Typical temperature; (**b**) four PVT combinations under the FF process corner: FF-Low voltage-Low temperature; FF-High voltage-Low temperature; FF-Low voltage-High temperature; and FF-High voltage-High temperature; and (**c**) four PVT combinations under the SS process corner: SS-Low voltage-Low temperature; SS-High voltage-Low temperature; SS-Low voltage-High temperature; and SS-High voltage-High temperature. Figure 13: Simulation of the IRR of the single-stage APPF based on 500 Monte Carlo results. The 180 nm CMOS process was also used to fabricate the proposed novel single-stage APPF to verify the effectiveness of the frequency-dependent image rejection enhancement technique. The photograph of the fabricated APPF die and the measurement setup is shown in Figure 17. The RF input signal generated by the signal generator is fed into the chip and amplified by a low-noise amplifier (LNA). The phase-locked loop (PLL) generates quadrature LO signals. In the mixer, the amplified RF signal is down-converted into quadrature IF signals by the quadrature LO signals. Then, IF signals flow into the APPF to complete image interference rejection. To drive the measurement instruments, a low-noise on-chip buffer with high linearity is placed after the APPF. The bias circuit provides the appropriate bias voltages for each of the other modules on the chip. Finally, the output signal of the chip is fed into the spectrum analyzer to complete the performance test. Figure 16: Simulated result of the two-stage APPF employing the proposed enhancement technique. Figure 15: Gain simulation result of the proposed single-stage APPF. The core area of the single-stage APPF is 150 \(\times\) 340 \(\upmu\)m\({}^{2}\). With a supply voltage of 1.8 V, the power consumption is 1.5 mW. Figure 18 shows that the measured IRR of \(-\)31 dB can be achieved in the frequency range of 95 to 105 MHz. On the one hand, choosing 10 MHz as the operating bandwidth to measure the IRR is the bandwidth requirement for certain wireless system applications, such as satellite navigation, the Internet of Things (IoT), and mobile communications. On the other hand, an IRR of greater than 30 dB can be obtained from the references [6; 17; 18] to basically meet the image rejection capability requirements of many wireless communication standards. And, it has an optimum IRR of better than \(-\)56 dB. The OIP3 at the output of the APPF is greater than 0.9 dBm, as shown in Figure 9:0 The gain and the IRN are extrapolated to 3.53 dB and 37.4 \(\upmu\)V, respectively. Figure 9:1 Photograph of the proposed single-stage APPF and the measurement setup. Figure 9:2 Measured IRR of the proposed single-stage APPF.