## 1 Introduction  
Wireless local area network (WLAN) technology has become increasingly popular in recent years, and has been integrated into various mobile devices such as computers, mobile phones, and tablets. Research on CMOS SOC that can be used in wireless local area network (WLAN) technology has been the focus of attention in recent years [1; 2; 3; 4; 5]. However, integrating power amplifiers (PAs) into WLAN systems has been a major bottleneck due to the low breakdown voltage and the lossy substrate in the CMOS process. Due to the lossy substrate in the CMOS process, the low-Q on-chip inductors and transformers seriously affect the linearity and efficiency of the PA. Off-chip matching can be used to solve these problems [6], but it increases the complexity and cost of the system. Moreover, directly connecting the drain of the transistor to the output PAD can cause severe breakdown problems that need to be carefully solved using ESD protection circuits without affecting linearity. Preferably, fully integrated PAs offer a better solution to help WLAN SOC achieve better gain control and system calibration, such as digital pre-distortion (DPD) loopback and adjustable gain control (AGC). Other roadblocks to the integration of high-performance power amplifiers (PAs) are low breakdown voltage and low current driving capabilities. To address these challenges, various techniques have been employed in CMOS PAs, such as series-combing transformers/parallel-combing transformers (SCTs/PCTs) [7; 8] and multistage cascode topology, aiming to enhance output power and gain. However, the SCTs and PCTs require extensive layout design to mitigate additional phase shifts and coupling between transformers, which can adversely impact the linearity and efficiency of the PA due to their large areas. Similarly, the multistage cascode topology has its own limitations attributable to the common gate (CG) transistor, as the presence of extra non-linearities from the CG transistor can degrade the overall linearity performance of the PA, including the bias circuit impedance of the CG transistor. Reference [6] indicates that the gate bias circuit of the CG transistor can introduce additional IMD3 asymmetry, which constitutes a critical factor in determining the linearity of the PA. Eliminating this non-linear effect adds complexity to the design. Nonetheless, despite these challenges, CMOS PAs remain a focal point of research due to their low cost and high integration capabilities. In particular, multi-band, multi-standard transceivers can be integrated into one single chip [9; 10; 11], which greatly reduces off-chip components, thereby reducing both costs and the PCB area. Therefore, CMOS SOC are widely used in portable devices such as mobile phones, watches, and tablets. The modern Wireless Local Area Network (WLAN) 802.11 ax/ac standard supports high data throughputs with strict linearity requirements, including support for modulation schemes such as 1024 and 256 quadrature amplitude modulation (QAM) and bandwidths up to 160 MHz. The linearity requirements are primarily characterized by two main factors: the error vector magnitude (EVM) and the spectral emission mask. In the case of transmitters, the linearity of the power amplifier (PA) plays a crucial role in determining the overall linearity of the entire transmitter. However, when compared to the PA design of III-V compound technology [12; 13; 14], CMOS PAs exhibit relatively poorer linearity. Consequently, various linearization techniques have been employed to enhance the linearity of CMOS PAs and meet the EVM requirements of WLAN modulation signals. These techniques include the employment of MGTR (Multigated Transistors) [15; 16], analog and digital pre-distortion technology [17; 18; 19], feedback and feedforward technology [20; 21], and adaptive bias circuits [22]. The adoption of these techniques aims to mitigate linearity limitations and improve the overall performance of CMOS PAs so they can meet the stringent requirements of WLAN modulation signals.