# Design and Performance Analysis of Hardware Realization of 3 GPP Physical Layer for 5G Cell Search
## 5 Performance and Complexity Analysis
### PSS Search  
The main task of the PSS Search is to identify the PCI_2 and GSCN. Since the identification of PCI_2 also confirms the correct identification of the GSCN, we limit the discussion  
Figure 10: Boundary Search Architecture.  
Figure 9: DMRS Search Architecture.  
on the probability of detection of PCI_2 for different SNRs and \(D_{PSS}=\{1,6,10,12,14\}\). It is referred to as \(P_{D}^{PSS}\). In Figure 11, \(P_{D}^{PSS}\) obtained from the experimental results on single-precision floating-point (SPFL) architecture for SNR ranging from \(-16\) dB to \(8\) dB and \(D_{PSS}=\{1,6,10,12,14\}\) are shown. It can be observed that \(P_{D}^{PSS}\) increases with the increase in SNR and \(D_{PSS}\). The degradation in the \(P_{D}^{PSS}\) is not significant for \(D_{PSS}\leq 10\) even at low SNR when compared to PSS Search without any downsampling, i.e., \(D_{PSS}=1\). At SNR higher than \(5\) dB, it is possible to perform PSS Search with \(D_{PSS}\) of \(14\) as well. Experimental results show that PSS Search fails for \(D_{PSS}\geq 14\) due to the insufficient number of samples available for correlation with reference PSS.  
Next, we analyze the effect of WL of the PSS search architecture on the \(P_{D}^{PSS}\). We consider two fixed-point architectures with a total WL of \(32\) and \(24\) bits. The WL of \(32\) bits is selected to keep the number of bits the same as that of SPFL architecture. Experimental results showed that the PSS detection fails for any WL lower than \(24\) bits and hence, second architecture with a WL of \(24\) bits is selected. In each fixed-point architecture, the number of bits allocated to integer and fractional parts is carefully selected to maximize the probability of detection. In Figure 12, we compare the difference in \(P_{D}^{PSS}\) for SPFL and fixed-point \(24\)-bit architecture for SNR ranging from -\(16\) dB to \(8\) dB and \(D_{PSS}=\{1,10,14\}\). It can be observed that the error is small and negligible for \(D_{PSS}\leq 10\) even at low SNR.  
The architecture with lower WL and higher \(D_{PSS}\) offers significant savings in resource utilization and execution time. In Table 1, we first compare the execution time in milliseconds (ms). It can be observed that the execution time decreases with the increase in the \(D_{PSS}\). Also, fixed-point architectures offer a \(2\)-\(3\) factor reduction in the execution time over SPFL architecture. Similarly, higher \(D_{PSS}\) leads to lower utilization of on-chip memory, i.e., FPGA block RAM, due to a few samples of the received and reference PSS. The use of lower WL also offers a further reduction in on-chip memory. Interestingly, the effect of \(D_{PSS}\) on the number of embedded multipliers and FPGA LUTs is not significant since the correlation block is realized in a sequential manner due to the limited number of memory ports. However, lower WL offers further savings in multipliers and LUTs since the size of multipliers and accumulators is smaller for lower WL. Overall, the proposed approach offers a \(60\%\) reduction in on-chip memory and \(50\%\) lower latency, i.e., PSS search time. To summarize, the appropriate selection of \(D_{PSS}\) and WL is important to meet the desired execution time, functional accuracy, and resource utilization constraints. For such analysis, the proposed work of mapping complete transmit and receiver PHY on the SoC is critical.  
Figure 11: Effect of SNR and \(D_{PSS}\) on the probability of detection, \(P_{D}^{PSS}\), for PSS search architecture.