## 3 Proposed QCA Circuits
### Proposed QCA RAM Cell  
Table 1 is a truth table of RAM cells used in digital circuits. It has three input values--SEL, R/W, and IN--and an output value, OUT. \(Q_{t-1}\) is the value of \(Q_{t}\) stored in the RAM cell at the previous time step, and \(Q_{t}\) is the value stored in the current RAM cell. If SEL = 0, OUT outputs 0, and \(Q_{t}\) does not change its value. When SEL = 1, read/write functions are performed based on the value of R/W, and when R/W = 0, read functions are performed. At this time, \(Q_{t}\) maintains the value as it is and OUT outputs the value of the stored value \(Q_{t-1}\). Conversely, if R/W = 1, the write function is performed, while at this time, \(Q_{t}\) and OUT output the value of IN. Based on the truth table in Table 1, the expression of the output value is summarized as (1) and (2). \[OUT=SEL\times R/W\times IN+SEL\times\overline{R/W}\times Q_{t-1} \tag{1}\]  
\[Q_{t}=SEL\times R/W\times IN+\overline{SEL\times R/W}\times Q_{t-1} \tag{2}\]  
As shown in Equation (1), the most important input value in the selected RAM cell is R/W. Since the resulting value changes based on R/W, Equation (1) can be modified to  
\begin{table}
\begin{tabular}{c c c c c c} \hline
**SEL** & **R/W** & **IN** & \(\mathbf{Q}_{t-1}\) & \(\mathbf{Q}_{t}\) & **OUT** \\ \hline
0 &  
Equation (3). In addition, since the circuit operates when SEL = 1 and the output value when SEL = 0, OUT = 0, Equation (3) can be replaced with Equation (4). Equation (2) can be transformed into Equation (5) using the same principle. \[OUT=SEL\times MUX(R/W,IN,Q_{t-1}) \tag{3}\]  
\[OUT=SEL\times MUX(SEL\times R/W,IN,Q_{t-1}) \tag{4}\]  
\[Q_{t}=MUX(SEL\times R/W,IN,Q_{t-1}) \tag{5}\]  
Figure 8 is a proposed RAM cell logic diagram based on Equations (4) and (5), designed using a multiplexer and two AND gates. The corresponding logic diagram is designed to minimize the number of gates, and is very simplified compared with the existing logic diagram. Figure 9 shows the QCA RAM cell proposed in this paper. It consists of a 2-to-1 multiplexer, a 3-input majority gate, and a rotated 3-input majority gate, shown in Figures 2 and 7. First, an input value IN or a stored value is output through cell Q using a multiplexer. The output value Q is connected to the input of the multiplexer or connected to the input cell SEL and the AND gate. At this time, if SEL = 1, Q is output to cell OUT, and if SEL = 0, the binary value 0 is output. Figure 9,b show designs based on MXC and MXL. MXL is designed to be suitable for making loop structures, and MXCR has low spatial density. Meanwhile, the proposed 2-to-1 multiplexer is designed with a single clock and can satisfy the real clocking system with a simple wiring clock control. Figure 10 shows a typical clocking design by fitting MXLR to 3 \(\times\) 3 square bins so that the proposed circuits can potentially satisfy current real clocking systems [43; 44]. Figure 8: Proposed logic diagram of QCA RAM cell. Figure 9: Proposed QCA RAM cell: (**a**) MXC-based RAM cell (MXCR); (**b**) MXL-based RAM cell (MXLR). Figure 12 shows the simulation results of the proposed RAM cells. If the selected input cell SEL = 0, 0 is output from the output cell OUT. When SEL = 1 and input cell \(R/W=0\), that is, when performing the read function, the stored value, 1, is output. Conversely, when SEL = 1 and \(R/W=1\), that is, when performing the write function, 0 and 1, the values of the input cell IN, are sequentially output. Both MXLR and MXCR add one cell before the output cell (OUT) for signal stability and reliability. Table 4 shows comparisons between the QCA 2-to-1 multiplexer and previously proposed 2-to-1 multiplexers. The comparison standards are the number of cells, the number of fixed inputs, the circuit area, and latency. The \(AT^{2}\) is calculated by multiplying the area of the circuit by the square of the latency [43].