# Quantum Circuit Implementation of Multi-Dimensional Non-Linear Lattice Models
## Appendix A Quantum Floating-Point Representation  
An important characteristic of the quantum-circuit development described in this work is the use of a floating-point representation along with computational basis encoding. This quantum floating-point format was introduced by the author in a previous work [6; 12] and has the following main features:  
* Its design follows the IEEE-754 standard [15] in employing sub-normal numbers and consistent rounding (rounding down to the nearest is used here), as well as the representation of overflow conditions. The maximum value for the exponent possible (considering the number of exponent qubits used) defines overflow, while an exponent value of 0 means that the number represented is sub-normal;
* The number of mantissa and exponent qubits is smaller than the equivalent number of bits in the IEEE-754 single-precision format. The example circuits shown here typically employ four mantissa qubits in the interest of limiting the size and improving the clarity of the circuits;
* Using the 'hidden-qubit' approach, only \(N_{M}-1\) qubits are stored in a representation with \(N_{M}\) mantissa qubits. \(N_{E}\) qubits represent the exponent;
* The qubit layout for a floating-point number is as follows: the leading qubit represents the sign (\(|0\rangle\) for positive numbers), followed by \(N_{E}\) exponent qubits, and finally, \(N_{M}-1\) mantissa qubits;
* In contrast to the IEEE-754 standard, an asymmetric bias is used here for the exponent. The motivation for this choice was to reduce the number of exponent qubits required to provide a sufficient range for the floating-point numbers for the specific application considered. In the quantum circuits developed here, \(N_{E}=3\) was selected as a good comprise between range and quantum-circuit width;
* For \(N_{E}=3\), the maximum exponent value is seven, so the state \(|111\rangle\) for exponent qubits indicates overflow. For \(N_{E}=3\), an exponent bias equal to three is a'symmetric' bias when following the approach used in the IEEE-754 definition. In the current applications, the floating-point numbers are biased toward smaller numbers by using an exponent bias greater than three. In Table 1, the sub-normal numbers (and zero) for \(N_{M}=4\) and \(N_{E}=3\) are shown for a symmetric bias (3 for \(N_{E}=3\)) and for an exponent bias of eight, selected here for applications of the modified D1Q3 model. As expected, the sub-normal numbers for the asymmetric bias are a factor \(2^{(8-3)}=32\) smaller. Although the floating-point format includes a sign qubit, the arithmetic performed in the quantum circuits typically accounts for a negative sign by temporarily converting the mantissa to 2's complement. The last column in Table 1 shows 2's complement representation of the mantissa for the sub-normal numbers. Starting from the mantissa (including 'hidden qubit'), \(N_{M}+1=5\) qubits are needed to represent 2's complement. As in the IEEE-754 standard, sub-normal numbers are the smallest numbers that can be represented. The best accuracy in using floating-point arithmetic is obtained when normalized floating-point numbers are used. For the D1Q3 lattice example, velocity components (scaled by lattice speeds) are among the variables that need to be represented. Small numbers will result (typically \(<0.1\) due to scaling used), so an asymmetric bias is used to make the floating-point representation use normalized numbers for these velocities and for the similarly small distribution function components represented in floating-point format (at least for most of the considered computational domain). Further,for velocity components represented as normalized numbers, computing the square will lead to reduced rounding and truncation compared with velocity components defined as sub-normal numbers for the same \(N_{M}\). To illustrate normalized numbers as used in the present work, Table 14 shows the floating-point numbers for an exponent value of six.