## 4 Implementation Results and Comparisons
### Comparison to State of the Art
#### 4.3.1 Comparison to Bit-Parallel Systolic Multiplier Architectures  
Comparison of our designs of Figures 2 and 7 over Virtex-7 with [17; 18; 19; 20]A scalable polynomial multiplication architecture of [17] is 27.65 (ratio of 32,685 with 1182) times more area-consuming in terms of FPGA slices as compared to our dedicated architecture of Figure 2. The scalability in [17] is achieved with the division of processing nodes into \(k\) cells to perform bit-wise AND and exclusive(OR) operations. The splitting of processing nodes into several cells results in higher hardware resources. When we consider the slices of our Figure 7 for comparison, the proposed flexible design utilizes 8.70 (ratio of 32,685 with 3753) times lower hardware area. As far as the power consumption is concerned, the proposed multipliers of Figures 2 and 7 are 1.64 (ratio of 5.277 with 3.201) and 1.35 (ratio of 5.277 with 3.905) times more power-efficient as compared to the bit-parallel systolic multiplier of [17]. Therefore, the division of processing nodes into \(k\) cells results in higher hardware resources and consumed power as compared to our dedicated and flexible designs, where we employ a digit-parallel-based schoolbook multiplication approach with a digit length of 32 bits. Another bit-parallel systolic multiplier over \(GF(2^{m})\) is illustrated in [18], where the used FPGA slices are 130.82 (ratio of 154,635 with 1182) times higher than our dedicated architecture of Figure 2. This is due to the use of interleaved conventional multiplication and folded techniques. When we consider the slices of our Figure 7 for comparison, the proposed flexible design utilizes 41.20 (ratio of 154,635 with 3753) times lower hardware area. The employed interleaved conventional multiplication and folded techniques in [18] consume 1.12 (ratio of 3.600 with 3.201) times more power as compared to the proposed multiplier of Figure 2. On the other hand, our flexible multiplier design is 1.08 (ratio of 3.905 with 3.600) times more power-consuming. This is due to the longer critical path as compared to the critical path of the parallel-systolic multiplier of [18]. The Montgomery-based versatile bit-parallel systolic multiplication architecture of [19] is 89.49 (ratio of 105,787 with 1182) times more area-consuming as compared to our digital-parallel schoolbook-based dedicated architecture of Figure 2. Likewise, the slices of [19] are 28.18 (ratio of 105,787 with 3753) times higher than our flexible digit-parallel-based schoolbook multiplier design of Figure 7. Due to the versatile nature in [19], the power consumption is 1.93 (ratio of 6.187 with 3.201) and 1.58 (ratio of 6.187 with 3.905) times higher as compared to our dedicated and flexible designs. With the aim of obtaining low-power and low-hardware resource utilizations, the bit-parallel polynomial basis systolic multiplier architecture of [20] utilizes 56.20 (ratio of 66,434 with 1182) and 17.70 (ratio of 66,434 with 3753) times more FPGA slices as compared with our dedicated and flexible architectures of Figures 2 and 7, respectively. The cause of the higher hardware resource utilizations in [20] is the use of a modular interleaved multiplication method. As shown in the last column of Table 2, the architecture of [20] is more power-efficient as compared to our multipliers of Figures 2 and 7. There is always a tradeoff between several design parameters such as area and power (in this case). It is essential to note that the additional design parameters, i.e., clock cycles, clock frequency and latency, cannot be compared as the relevant information is not provided (see the corresponding columns in Table 2). _Comparison of our architectures of Figures 3 and 7 over Virtex-7 with [21; 22; 23]._ Concerning the FPGA slices of [21; 22] and [23] for comparison, our dedicated architecture of Figure 3 utilizes 15.75 (ratio of 22,864 with 1451), 65.12 (ratio of 94,498 with 1451) and 38.74 (ratio of 56,223 with 1451) times lower hardware resources.