# Constrained Optimization of FPGA Design for Spaceborne InSAR Processing
## 3 Design of System and Structure
### Hardware Structure of Graduated Registration  
Before the interferogram generation, the images must be aligned in the range and azimuth directions. To improve the processing capacity, this paper proposed a specialized structure based on FPGA called \"graduated registration.\" It fits the FPGA pipeline, thus improving the processing capacity and reducing the algorithm's complexity. The analysis is as follows.  
Figure 2: The architecture of the system. In “FIFOA-M” and “FIFOA-S”, “FIFO” means “First In First Out”, “N” is the number of FIFO, “M” and “S” denotes Master and Slave respectively. “DDR” represents “Double Data Rate”.  
The offset coordinates (\(x\)-axis, \(y\)-axis) are obtained when the registration process is completed. Before entering the interferogram generation process, the two images must be registered by the offset coordinates. The coordinate offset reflects the relative position of the main and auxiliary images. The offset coordinates (\(x\)-axis, \(y\)-axis) can be positive or negative; the auxiliary image can be moved either positively or negatively along the X or \(y\)-axis. \(x\)-axis > 0 means that Image A moves in the positive X direction relative to Image B; similarly, \(y\)-axis > 0 means Image A moves in the positive Y direction relative to Image B. Therefore, there are four cases of offset in the four quadrants, as shown in Figure 3.  
If the offset of X and Y works in the DDR3 SDRAM, like 2D_Address, shown in Figure 4, the algorithm's complexity is O(\(n^{2}\)) because the offset coordinate works in two loops. More importantly, when filtering data in two-dimensional space, the corresponding DDR3 SDRAM addresses are discontinuous, which affects storage efficiency terribly. To improve efficiency and fully take advantage of the pipeline processing capacity of FPGA, we designed a structure called graduated registration, as shown in Figure 4. The \(x\)-axis was moved from the DDR3 SDRAM into the FIFO, and only the \(y\)-axis worked in the DDR3 SDRAM. In this way, the algorithm's complexity was reduced to O(\(n\)) without the loss of efficiency caused by discontinuous addresses, like 1D_Address.  
The data flow works as follows. First, the initial address of azimuth data is obtained according to \(y\)-axis. Then, a particular row of the original data is read from the DDR3 SDRAM. Finally, two lines of data from two DDR3 SDRAM chips are buffered in S1_PRE and S2_PRE to filter range data, thus realizing the registration process of two-dimensional data. As the offset, \(y\)-axis and \(x\)-axis work in DDR3 SDRAM and FIFO, respectively, to perform two-dimensional registration. We called the proposed structure \"graduated registration\".  
According to the \(x\)-axis, both the S1_PRE and S2_PRE modules have two cases, as shown in Figure 4. It can be seen that data in the modules could be divided into three segments: the \(C\) segment was for the coherence coefficient and phase, the \(A\) segment was discarded, and the \(B\) segment was zeroed. In this structure, the unavailable data was zeroed or discarded, so the depth of FIFO stayed unchanged (i.e., 4096).  
The graduated registration structure proposed in this paper has two advantages. On the one hand, it ensures a high data bandwidth reading from DDR3 SDRAM with lower algorithm complexity and efficiency loss. On the other hand, the length of data buffered in this structure is constant by filling zeros, which can easily be controlled and debugged.  
Figure 3: The relative position of the images.