# Secure ECDSA SRAM-PUF Based on Universal Single/Double Scalar Multiplication Architecture
## 5 Implementation Results
### FPGA Results  
The proposed architecture was instantiated on the Xilinx Virtex-7 FPGAs using Vivado 2022, a choice made to ensure a fair and contemporary comparison with existing designs. To gauge our design's performance in a manner that is both comprehensive and reasonable, we executed the architecture across NIST-recommended \(GF(2^{16S})\) and encompassed variations in scale to provide a thorough evaluation of its capabilities and efficiency. Considering the ECDSA in our work is a custom design, we compare the performance of ECDSM with existing works to ensure fairness in comparison. For existing designs that only implement ECSM, we consider twice their total latency as an approximate latency for ECDSM. In reality, this rough evaluation method often yields more optimistic estimates for existing designs, as it neglects the PA after two ECSMs. In our design, the total latency includes DAC generation, iteration, and inversion. Although in the precomputation stage, our design needs to compute both flag signals for DAC construction and \(P\pm Q\), these two parts are executed in separate circuit components, allowing them to be performed in parallel. Moreover, the latency of computing flag signals is significantly greater than computing \(P\pm Q\). Therefore, in the total latency consideration, we no longer account for the latency introduced by \(P\pm Q\). For \(GF(2^{m})\), constructing the DAC chain requires \(m\) clock cycles. The total latency can be calculated by Equation (4). \[T=(C_{DAC}+C_{ITR}+C_{INV})\times T_{CLK} \tag{4}\]  
In our design, there is one multiplier and one square unit. When utilizing [PERSON]'s [30] proposed modular inversion algorithm, the modular inverse can be calculated within \(m+1\) cycles. The iteration consumes \(10\times m+1\) clock cycles over GF(\(2^{m}\)) and one additional clock cycle to wait for the final multiplication result. \[C_{ITR}=m+10\times m+(m+1)+1 \tag{5}\]  
Most existing research utilizes ATP as a performance benchmark to assess the trade-offs between hardware resources and latency. While some research evaluates the area using the number of LUTs #_LUT_, most employ the number of slices #_Slice_. In our design, we evaluate ATP using the number of slices to ensure fair comparisons, as our design introduces additional storage resources. We estimate the number of slices for the literature lacking slice data based on reported LUT data. For Xilinx Virtex-7 FPGAs, each slice typically contains four LUT6. However, not all utilized slices are fully occupied with all  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Research Work** & **Device or Process** & **Reliability** & **Uniqueness** & **Temperature** & **Voltage Supply** \\  & & **Intra-Chip Variation** & **Inter-Device Variation** & & \\ \hline \multirow{2}{*}{Latch-PUF [26]} & \multirow{2}{*}{Spartan-3E} & M = 2.4\% & M = 46\% & 0 \({}^{\circ}\)C–85 \({}^{\circ}\)C & — \({}^{*}\) \\  & & SD = 0.75\% & SD = 3.8\% & & \\ \multirow{2}{*}{Latch-PUF [26]} & \multirow{2}{*}{Spartan-6} & M = 0.86\% & M = 49\% & — & 1.14 V–1.26 V \\  & & SD = 0.54\% & SD = 3.9\% & & \\ SRAM-PUF [27] & 45 nm & M = 0.72\% & M = 49.97\% & 10 \({}^{\circ}\)C–85 \({}^{\circ}\)C & — \\  & & SD = 10\% & SD = 15\% & & \\ Butterfly-PUF [28] & 65 nm & M\({}_{max}\) = 6\% & M = 50\({}_{around}\)\% & \(-\)20 \({}^{\circ}\)C–80 \({}^{\circ}\)C & — \\  & & — & — & & \\ TERO-PUF [29] & \multirow{2}{*}{Cyclone II} & M = 1.7\% & M = 48\% & 28 \({}^{\circ}\)C & 1.5 V \\  & & — & — & & \\ Delay-Hardened- & \multirow{2}{*}{14 nm} & M = 3.4\% & M = 48.6\% & 25 \({}^{\circ}\)C–110 \({}^{\circ}\)C & 0.55 V–0.75 V \\ PUF [23] & & — & — & & \\ Amplifier-PUF [25] & 180 nm & M = 0.07\% & M = 49.89\% & \(-\)40 \({}^{\circ}\)C–120 \({}^{\circ}\)C & 0.8 V–1.8 V \\  & & SD = 0.32\% & SD = 6.24\% & & \\ This work & 40 nm & M = 3.17\% & M = 49.44\% & 0 \({}^{\circ}\)C–85 \({}^{\circ}\)C & 0.8 V–1.2 V \\  & & SD = 1.63\% & SD = 2.44\% & & \\ \hline \hline \end{four LUT6.