## 4 Direct Output Current Control Based on Virtual Voltage Compensation under No Backflow Power
### The Estimation of \(d\)  
The waveforms of voltages and currents of the LCL-DAB converter are symmetrical in each half period, so the operating state only needs to be analyzed in half period. Taking the  
Figure 5: Showing 3D plots of \(Y_{\text{P}}\) varying with \(d_{1}\) and \(d\).  
Figure 6: Showing 3D plots of \(Y_{\text{Q}}\) varying with \(d_{1}\) and \(d\).  
Figure 7: Output voltage gain comparison for the two types of converters.  
waveforms under no backflow power operation in Figure 3 as an example, the backflow power can be regarded as the negative part of the instantaneous power. Therefore, the consistent directions of \(u_{\rm P}\) and \(i_{\rm P}\) can be regarded as the criterion of no backflow power operation for H\({}_{1}\), as expressed in (33) and (34). Similarly, the consistent directions of \(u_{\rm S}\) and \(i_{\rm S}\) can be regarded as the criterion of no backflow power operation for H\({}_{2}\), as expressed in (35) and (36).  
\[i_{\rm P}(t_{4})\leq 0 \tag{33}\]  
\[i_{\rm P}(t_{7})\geq 0 \tag{34}\]  
\[i_{\rm S}(t_{1})\geq 0 \tag{35}\]  
\[i_{\rm P}(t_{3})\leq 0 \tag{36}\]  
Substituting (9) into (33)-(36), the solutions of \(d_{1}\) and \(d\) of these constraints can be solved. Figure 8 shows the design boundaries of no backflow power for LCL-DAB converters with DPS modulation scheme, in which the regions surrounded by the curves are the design regions with different \(k\). It also shows that the design regions for H\({}_{1}\) expand with the increase in \(k\), and the trend becomes unapparent with large values of \(k\). On the contrary, the design regions for H\({}_{2}\) shrink with the increase in \(k\), and the trend becomes unapparent with small values of \(k\). Notably, the design regions for H\({}_{1}\) and H\({}_{2}\) overlap when \(k\) = 1 (voltage matching), which means the same operating state of two bridges in the converter. Therefore, a reasonable \(k\) can be determined to avoid too narrow regions for H\({}_{1}\) or H\({}_{2}\) during the system design process.  
The above analysis reveals that, for most values of \(k\), the wide design ranges of \(d_{1}\) can be obtained when \(d\) is around 0.2, i.e., an appropriate value of \(d_{1}\) can ensure no backflow power operation in a wide range. Given that the output voltage gain is symmetric at \(d\) = 0.25, the preset modulation range of \(d\) should be determined for the first time according to the design acquirement. Moreover, other control objectives should be considered in the actual application, such as transmission power, output voltage, etc. Taking voltage gain as an example, for a fixed \(d\), the uppercase form of it \(D\) denotes its steady state, so the maximal voltage gain can be expressed as (37), representing the voltage conversion ability. According to (37), the power conversion ability increases and then decreases with the increase in \(d\) and reaches the maximal value when \(D\) = 0.25. However, if only voltage gain is considered, the design region of no backflow operation could be nonexistent under a too tiny \(k\) for H\({}_{1}\), or under a too large \(k\) for H\({}_{2}\). Generally, the value of \(d\) should be weighed and determined according to the actual requirement.  
\[G_{\rm DCmax}=\frac{8 NR\sin(2\pi D)}{\pi^{2}Z_{0}} \tag{37}\]  
Figure 8: Design regions of no backflow power operation with DPS modulation scheme: (a) for H\({}_{1}\); (b) for H\({}_{2}\).