# Architecture and Process Integration Overview of 3D NAND Flash Technologies
## 2 Three-Dimensional NAND Flash Architectures
This is improved in a hybrid 3D NAND flash, in which the density is increased by placing the WL and the SSL in the same string, as shown in Figure 9a [9]. In this hybrid structure, the GAA string selector and the metal-alumina-nitride-oxide-silicon (MANOS) cells form string lines, and each channel layer is connected to the BL through the SSL. This structure allows both a vertical channel of the GAA string selectors and horizontal channels of the MANOS cells. The cell string exhibits high channel controllability, owing to GAA structure, and the double-gate memory cell provides a sufficient threshold voltage (\(V_{\text{T}}\)) window for multibit operation. Figure 9b shows the SMArT structure [10], which minimizes the stack height using the ONO layer and employs the low-resistance of the metal gate by employing the gate-last  
Figure 8: (**a**) Cell structure and (**b**) schematic of HC-FG NAND flash structure [3], Copyright IEEE, 2013. Figure 7: (**a**) Aerial view of DC-SF structure [8], Copyright IEEE, 2010. (**b**) Charge spreading in BiCS and DC-SF structures. process method. The SMArT structure shows superior \(V_{\text{T}}\) distribution and endurance compared to planar FG cells; however, the retention characteristics need to be improved. In general, the channel-stacked method can have the same pitch size as a 2D NAND architecture; however, it has an issue that the SSL for the target cell access (decoding) increases as the stack layer increases. To address this issue, Macronix proposed several structures for decoding the SSL [12; 13; 14; 15; 36]. Figure 10 shows the architecture of an island-gate decoded VG structure with channel-stacked BE-SONOS (bandgap engineered SONOS) [37], containing an island gate for the SSL selection [12]. Unlike the VG NAND structure, the presence of an \(n\)-type doped poly-Si buried channel allows a junction-free structure, and no additional junction implantation is required. In the island-gate decoded VG structure, the intercepts of the WL, BL, and SSL planes are used for cell decoding, and the WLs and BL are grouped into planes. Another type of gate-stacked 3D NAND structure of Macronix is a single-gate vertical channel (SGVC) [38]. In the SGVC structure, the cell transistor is not based on a nanowire channel of a GAA structure but instead on a flat channel in the WL trench. Figure 11a presents a comparison of GAA and the SGVC cell structure. The SGVC structure is a flat channel-based charge trapping device and has an initial \(V_{\text{T}}\) distribution and short channel effect similar to that of GAA structure, owing to the ultra-thin body. Compared to the curvature-shaped GAA structure, the SGVC cell structure advantages are in the formation of the critical dimension and channel hole etching. Figure 11b shows the layouts  
Figure 10: Schematic of island-gate decoded VG structure [12], Copyright IEEE, 2010. Figure 1:0 (a) Aerial view of a hybrid 3D NAND flash cell with equivalent circuits [9], Copyright IEEE, 2011. (b) Cross-section view of a SMArT structure [10], Copyright IEEE, 2012.  
of the GAA VC and SGVC structures. Compared to the GAA VC structure, the SGVC has approximately 2.4 times the memory density in the same stack layer [38; 39; 40; 41]. Figure 12a,b show the U-turn and bottom-source SGVC architectures, respectively [39; 40]. In the former, an ONO CTL and poly channels are deposited on the WL trench. The thin poly channel layers are separated by the BL cut process, and the CTL and channel are controlled by independent WLs. Owing to the use of a flat channel cell transistor, the scalability of the U-turn SGVC structure is comparable to that of 2D NAND flash, and its etching controllability is better than that of a GAA structure. The bottom-source structure has almost the same characteristics as the U-turn structure, except thin poly channels are connected to the bottom n\({}^{+}\) substrate. The gate-first process for the bottom-source SGVC fabrication, similar to the BiCS, causes ONO layer damage, and a two-step poly channel process is required to protect the ONO layer.