# 8-W 2-Stage GaN Doherty Power Amplifier Module on 7 \(\times\) 7 QFN for the 5G N78 Band
## 2 Design of 2-Stage DPAM
### Load Network Design  
Figure 4 shows the schematic of the load network of the proposed 2-stage DPAM, which includes output matching circuits for both the carrier and peaking amplifiers, along with a post matching network. The output matching circuit for the carrier amplifier employs a TL with an electrical length of \(90^{\circ}\) utilizing the output capacitance of the transistor, bond wires, a shunt inductor for DC supply, an L-section matching circuit, and a DC blocking capacitor. For the peaking amplifier, the output matching circuit consists of a TL with an electrical length of \(0^{\circ}\), also including the output capacitance of the transistor, the inductance of the bond wires, a shunt inductor for DC, and an L-section matching network. This structure is further enhanced by a high-pass TL composed of lumped components, offering an equivalent electrical length of \(-90^{\circ}\). The power combining node and the current source plane's impedances for both low and peak power levels can be determined using the peak power ratio (\(\alpha\)) between the carrier and peaking amplifiers. The post matching network  
Figure 3: Impedance transformation with a 1 dB output power contour for the driver amplifier.  
Figure 2: Schematic of the interstage matching network using an IPD.  
consists of a simple L-section low-pass structure that serves to match the output impedance of the combining node to the standard 50 \(\Omega\) load. In the entire load network, high-Q multi-layer chip capacitors are included, and TLs with high characteristic impedance replace inductors in the matching network.  
The proposed DPAM exhibits an output PBO of 8.3 dB, and the peak power ratio \(\alpha\) between the carrier and peaking amplifiers is set to 1.6 for asymmetric structures. The optimum load impedance of the carrier amplifier at peak power, marked as \(R_{L}\), is established at 50 \(\Omega\). Using these parameter values, other design parameters are derived as illustrated in Figure 4. In addition, to reduce circuit complexity, multiple shunt components located at the same node can be combined into a single equivalent element.  
Figure 5 illustrates the distribution of load impedances over frequency at the current source plane for both low and peak power levels. At the low power level, as the peaking amplifier operates in class-C, the output impedance, \(Z_{op}\), can be approximated as infinity. The class-AB carrier amplifier is matched from \(Z^{\prime}{}_{c,low}\) of \(R_{L}/2\) to \(Z_{c,low}\) of \((1+\alpha)\cdot R_{L}\). For the frequency range of 3.4-3.8 GHz, the load impedances of the carrier amplifier remain within a 1 dB power contour centered at 130 \(\Omega\). At peak power level, matching for the carrier amplifier is executed from \(Z^{\prime}{}_{c,peak}\) of \((1+\alpha)\cdot(R_{L}/2)\) to \(Z_{c,peak}\) of \(R_{L}\), whereas the peaking amplifier matches from \(Z^{\prime}{}_{p,peak}\) of \((1+1/\alpha)\cdot(R_{L}/2)\) to \(Z_{p,peak}\) of \((1/\alpha)\cdot R_{L}\). In the 3.4-3.8 GHz range, the load impedances of the carrier amplifier stay within a 1 dB power contour centered at 50 \(\Omega\), and that of the peaking amplifier also stay within a 1 dB power contour centered at 31 \(\Omega\), as demonstrated in Figure 5.  
Figure 4: Schematic of the load network.  
Figure 6 shows the simulated insertion loss of the load network across the frequency range. Achieving high output power and maintaining high efficiency require that insertion loss within the load network be minimized across the operating bandwidth. For this purpose, the load network was designed using high-Q multi-layer chip capacitors and transmission lines (TLs) implemented on a PCB. As a result, the designed load network exhibits an insertion loss ranging from 0.68 to 0.98 dB over the 3.4-3.8 GHz band.