# A 4K-Capable FPGA Implementation of Single Image Haze Removal Using Hazy Particle Maps
## 4 Hardware Implementation
Considering additional horizontal and vertical blank periods in hardware implementation, the maximum processing speed (MPS) in fps can be calculated easily using the following equation:  
\[\text{MPS}=\frac{f_{max}}{(W+HB)(H+VB)}, \tag{11}\]  
where \(f_{max}\) is the maximum operating frequency, \(W\) denotes the width of the input image, \(HB\) represents the horizontal blank, \(H\) refers to the height of the input image, and \(VB\) indicates the vertical blank. In this study, the proposed design required a clock cycle and a horizontal line for each horizontal and vertical blank period. Figure 7: Verification using a SoC evaluation board. Table 5 shows the processing speeds for various video standards. The number of clock cycles required to process the DCI 4K video standard of a 4096 \(\times\) 2160 image was 8,853,617 (= 4097 \(\times\) 2161), suggesting that the proposed haze removal system can handle up to 26.7 fps (= 236.29 \(\times\) 10\({}^{6}\)/8,853,617) and meets the real-time processing criteria of handling at least 25 fps. This result demonstrates that the proposed method can be applied to real-time applications using up to 4K video standards. The comparison with other hardware designs is also shown in Table 6. Since [PERSON] et al. and [PERSON] et al. did not present the implementation results thoroughly as [PERSON] et al. did, their data of Registers, LUTs, DSPs (Digital Signal Processing blocks), and Memory are listed as NA (Not Available). In Reference [1], [PERSON] et al. claimed that their design can achieve 200 MHz using TSMC 0.13-\(\upmu\)m technology. However, when they implemented it on Altera Stratix EP1510F780C6 FPGA platform, the maximum frequency is only 58.43 MHz, leading to the fact that it is solely fast enough to process a video resolution of FHD at 28.1 fps in real time. [PERSON] et al. proposed a hardware architecture for haze removal at fixed frame sizes of \(320\times 240\), \(640\times 480\), and \(800\times 600\). Accordingly, even though their design achieved the maximum frequency of 88.70 MHz, it can only process the maximum video resolution of Super VGA (SVGA). Adding to that, it requires 32,000 ALMs (Adaptive Logic Modules), which comprises two adaptive lookup tables and then can be inferred to 64,000 LUTs. Except the number of registers, more LUTs, DSPs, and memory are needed to implement a design that cannot be compared to our proposed design in terms of processing speed and resource utilization. Finally, the design of [PERSON] et al. can be considered as an improvement upon [PERSON] et al. 's under the processing speed metric. Their design is capable of processing a Quad HD video resolution at 31.4 fps in real time. All the calculations of processing speed for designs of [PERSON] et al. and [PERSON] et al. are based on the assumption that they also require a clock cycle and a horizontal line for each horizontal and vertical blank period. In fact, their requirement for horizontal and vertical blank period may be different, and the processing speed may decrease. Therefore, it is evident from Table 6 that our proposed hardware architecture is superior to other benchmarking designs in term of processing speeds in References [1; 2; 22] and requires less resources than the design in Reference [2]. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Slice Logic Utilization** & **Available** & **Used** & **Utilization** \\ \hline Registers (\#) & 437,200 & 70,864 & 16.21\% \\ LUTs (\#) & 218,600 & 56,664 & 25.92\% \\ RAMB36E1 & 545 & 85 & 15.60\% \\ Minimum Period (ns) & & 4.23 & \\ Maximum Frequency (MHz) & & 236.29 & \\ \hline \hline \end{tabular}
\end{table} 
Table 4: FPGA implementation of the proposed method.