# SARDIM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging
## 3 SARDIMM: The Proposed NMP Architecture for RDA
### Execution Flow  
The execution flow of RDA with a SARDIMM consists of five main steps:  
Figure 6: Hardware architecture of the FPBF module. Figure 7: Representation of the FPBF module operation for stage 1 of the 16-point DIF FFT: (**a**) data buffer storing stage 1 input data; (**b**) simplified block diagram of the FPBF module; (**c**) data buffer storing part of stage 1 output data. Range FFT, range reference signal multiplication, and range IFFT in the NMP module;
2 Transpose the range compression result in the host processor;
3 Azimuth FFT in the NMP module;
4 RCMC in the host processor;
5 Azimuth reference signal multiplication and azimuth IFFT in the NMP module. The NMP instructions for RDA include FFT and IFFT instructions, each containing Opcode, \(N\)-point, and RM. The Opcode distinguishes between FFT and IFFT instructions, whereas the \(N\)-point indicates the FFT length and number of stages. The NMP controller generates addresses to read the data required for each FFT stage accordingly. The RM determines whether reference multiplication is enabled or disabled. SARDIMM performs RDA using appropriate NMP instructions. First, the FFT and IFFT instructions are sent to the NMP module for range compression. When SARDIMM completes the range compression, the host processor receives the NMP end signal and reads the compression result. The host processor then transposes the results for azimuth compression. To handle transposition within the NMP module, data sharing between ranks would be necessary. However, the SARDIMM architecture does not support data sharing between ranks. Therefore, the host processor is responsible for performing the transposition. Second, an FFT instruction is sent for the azimuth FFT. After completion, the host processor reads the FFT results for RCMC. Finally, an IFFT instruction is sent to finalize azimuth compression. The detailed execution flow for each phase of the NMP operation is as follows:  
1. The host processor initializes the buffer data in the NMP module;
2. The host processor sends NMP instructions to the NMP module;
3. The host processor sets the status register in the NMP module;
4. The NMP module operates and loads the result. Figure 8 shows the flow of NMP operation in the SARDIMM system. Initially, the host processor stores the data necessary for operation, including the RDA input image, reference signal, and twiddle factor, in the NMP module buffer. SARDIMM employs a memory-mapped I/O method to distinguish the buffer addresses from memory addresses. After initialization, it transmits the corresponding NMP instruction for the operation. At this stage, SARDIMM must send instructions to each NMP module simultaneously, as the NMP modules operate in rank-level parallelism. In a traditional memory system, all the ranks on the same channel as the memory controller are connected by sharing the DQ and C/A paths. Therefore, when data are sent to one rank, the same data are also sent to the other ranks, but the other ranks ignore the data. This feature of the memory system allows SARDIMM to simultaneously send the same NMP instruction to all NMP modules on the same channel. When the host processor issues a command to write the NMP instruction to the instruction buffer, the NMP module responds to it regardless of the rank [29]. After transmitting an NMP instruction, the status register is set. This is also performed simultaneously by all the NMP modules. Upon checking the NMP start signal in the status register, the NMP controller begins the NMP operation. The controller starts reading the data from the instruction buffer and decodes the first instruction to obtain information regarding the Opcode, \(N\)-point, and RM. Next, it performs FFT or IFFT, with or without reference signal multiplication, until the end of the last stage and stores the result of the operation in the data buffer. When the last stage is completed, the next instruction is decoded to perform the next operation. If there is no next instruction, the status register is set to the NMP end state.