# PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA
## 3 Proposed P4-Programmable Parser
### Software Overview
#### 3.1.2 P4 Compiled JSON File
It allows continuous data processing without waiting for the previous block's results, significantly increasing throughput. By dividing the processing task into stages, each packet part can be processed concurrently at different stages, enhancing overall efficiency. This design is especially beneficial in high-speed network environments where minimizing latency and maximizing data processing rates are crucial. Unrolling both the bitmap and control multiplexers simplifies the parser block by dedicating one information set to each pipeline stage. This method is particularly effective for larger bus sizes, such as 512 and 1024 bits, as it improves block frequency and throughput. It allows the longest graph path headers to be parsed in one or two clock cycles, eliminating the need for packet storage and avoiding system back pressure. One significant advantage of this approach is that it does not require changes to the software to generate parsing information. This method enhances performance while maintaining simplicity and reliability. Additionally, the configuration and control data generated via software remain unchanged, ensuring compatibility and ease of implementation. Overall, this approach provides a throughput comparable to other high-performance designs, making it a robust solution for handling larger bus sizes efficiently. ## 4 Experimental Results

This section discusses the experimental results obtained by evaluating the proposed P4-programmable packet parser framework. The experiments were conducted on an Alveo U280 FPGA board. The hardware architecture was reprogrammed via software-generated configurations to process different input graphs. Configurations were generated for three different graphs: an enterprise network graph, a firewall graph, and an Access Gateway Function (AGF) graph (Figure 8). The enterprise network graph was the most complex, \begin{table}
\begin{tabular}{l l c c c c c c} \hline \hline  & & \multicolumn{4}{c}{**Performance**} & \multicolumn{4}{c}{**Resources**} \\ \cline{3-8}
**Work** & **FPGA** & **Bus Size** & **Frequency** & **TP** & **Latency** & **LUTs** & **FFs** & **Total Logic** \\  & & **[bits]** & **[MHz]** & **[Gb/s]** & **[ns]** & **LUTs** & **FFs** & **Logic** \\ \hline
[19]—Golden & Virtex-7 & 512 & 195.30 & 100.00 & 27.00 & N/A & N/A & 8000 \\
[19] & Virtex-7 & 512 & 195.30 & 100.00 & 46.10 & 10,103 & 5537 & 15,640 \\
[24] & Virtex-7 & 320 & 312.50 & 100.00 & 25.60 & 7831 & 13,67 & 21,502 \\
[20] & Ultrascale+ & 512 & 250.00 & 128.00 & 36.00 & 2587 & 2395 & 4990 \\ Proposed—Pipeline & Alveo U280 & 512 & 282.32 & 144.55 & 31.87 & 8435 & 3880 & 12,315 \\
[16] & Virtex-7 & 1136 & 279.30 & 317.00 & 25.06 & 16,888 & 12,033 & 28,921 \\
[17] & Ultrascale+ & 1280 & 800.00 & 1024.00 & 15.00 & 15,634 & 11,476 & 27,110 \\ Proposed—Pipeline & Alveo U280 & 1024 & 282.32 & 289.10 & 31.87 & 8435 & 3880 & 12,315 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Results comparison for pipeline block. comprising ten nodes and seven transitioning nodes that require parsing states. The maximum number of connections between a node and its subordinate nodes in the hierarchy was four. Therefore, there are seven protocol investigators and four match detectors, and the protocol bitmap vector comprises 10 bits, one per protocol. The other two graphs fit within the boundaries considered for the enterprise network graph, and the same methodology can be applied to even more complex graphs if needed. Each of the seven protocols is allocated a 16-bit mask, resulting in a total of \(7\times 16=112\) bits. Given that this graph has a maximum of four connections, there are four keys for each protocol, each being 16 bits in size, totaling \(7\times(4\times 16)=448\) bits. Additionally, each key has an associated next protocol ID, representing each ID as a 4-bit array, leading to a total of \(7\times(4\times 4)=112\) bits. This means that the total number of bits required for Protocol Investigators is 672.