## 4 Results  
We implemented our proposed design on the FPGA platform, which boasts high throughput, low latency, and efficient area. The layered MS algorithm for QC-LDPC codes forms the foundation of our design. In particular, we opted for a \(2/3\) rate from the BG1. Our decoder architecture offers significant area efficiency advantages, enabling a more compact and cost-effective communication system design. We synthesized and implemented the decoder on the FPGA platform Virtex-7 to validate our approach, utilizing the XC7 VX980T part. The Virtex-7 family's balance of performance, rich connectivity, and cost-effectiveness made it ideal for our demanding implementation. Our comprehensive synthesis analysis revealed a range of LUTs (Look-Up Tables) from 380,737 to 384,956, depending on the chosen synthesis strategy. The results of each strategy are visually depicted in Figure 7.  
Figure 6: SNR performance of the proposed decoder and its comparison with the state-of-the-art based on the rate of \(2/3\)[14; 15] (a) and the rate of \(1/3\)[13] (b) of BG1. In the previous figure, we present a comparative analysis of four key parameters: maximum frequency, LUTs, worst negative slack (WNS), and total power consumption. Each parameter is represented by a bar graph, illustrating the performance metrics among the three distinct strategies: \"AreaOptimized_high\", \"PerOptimized_high\" and \"AlternateRoutability\". Each strategy prioritizes different aspects of the decoder's performance. For instance, PerOptimized_high prioritizes achieving the highest frequency, AreaOptimized_high concentrates on reducing the amount of logic resources, and AlternateRoutability strikes a balance between performance and resource utilization, with a particular focus on improving the design interconnection. Figure 8 presents a detailed breakdown of the proposed decoder's resource utilization within the FPGA board (XC7 VX980T). The color scheme, dominated by shades of blue, strongly suggests the allocation of LUTs. This aligns with the hardware implementation of the decoder architecture in VHDL, as LUTs are a fundamental building block for implementing logic functions on FPGAs. Figure 8: Graphical visualization with cyan color of resource utilization (Flow_AreaOptimized_high) by the proposed decoder. Figure 7: The impact of three different synthesis strategies on frequency, WNS, LUTs, and power consumption evaluated through hardware implementation on the XC7 VX980T board. The allocation of key programmable logic components such as slice LUTs, slice registers, and multiplexers is captured in Figure 9. The 'top' row, which aggregates total usage, denotes the main module. Sub-modules, such as 'tp0(top_rd)', 'tp2(CNPU)', 'tp8(top_wt)', etc., list each other row with its corresponding resource counts. This breakdown is particularly insightful for optimizing the performance and efficiency of our designs. By analyzing the data, we can make informed decisions to refine the system architecture, ensuring that each component is not only functionally robust but also resource-efficient. The development of high-performance 5G communication systems relies heavily on meticulous resource management, leveraging every bit of computational power and memory to achieve the desired throughput and latency specifications. An examination of resource utilization reveals that the \"top_rd\" block consumes the most significant portion of resources within the FPGA, accounting for, for example, 341,104 LUTs out of 380,737. This dominance aligns with its function of managing the serial data reading process according to each layer of the base graph, which inherently necessitates a complex logic implementation. Conversely, the CNPU demonstrates exceptional efficiency in the context of 5G-NR standards by utilizing only 17,647 LUTs to process the maximum message word. This observation underscores the effectiveness of the SOLL method we employed for the first time in 5G-NR. The memory block occupies 5934 LUTs, contributing a relatively smaller portion to the overall resource usage.