# Development of Additive Fibonacci Generators with Improved Characteristics for Cybersecurity Needs
## 2 Related Works  
A large number of works are devoted to the construction of AGF. In particular, analyses of the implementation of Fibonacci hardware generators on FPGA are given in [17]. There are also similar studies of Fibonacci generator implementations on FPGA in [18], and in [19], true random number generators, based on Fibonacci-Galois ring oscillators for FPGA, are considered, and the possibility of using these generators in cryptographic applications is shown. The results of research that used a combination of a hybrid of two existing generators--a linear congruential method and a delayed Fibonacci technique--are presented in [20]. The analysis of the efficiency of using a Fibonacci generator for cryptographic problems is also considered in [21; 22]. Moreover, in [23], Fibonacci generators are used for the key generation algorithm with the necessary randomness and low algorithmic complexity. The work in [24] is devoted to the question of the correct choice of Fibonacci generator parameters. AFGs operate according to the following generalized recurrent equation:  
\[x_{i}=(x_{i-a}+x_{i-b}+\ldots+x_{i-q})\bmod(m), \tag{1}\]  
where \(a>b>\ldots>q>0\). Usually, AFGs are used in which the module \(m=2^{n}\), where \(n\) is the number of generator structural elements binary bits, that simplifies their hardware implementation. Under certain conditions, the repetition period of such AFGs is not less  
In [10; 11; 12; 13; 14; 15] we proposed modified MAFGs, in which the module is determined by the equation \(m=2^{n}\), but they include an additional logic circuit (LC), the function of which is logical addition of the module 2 of the bits values of one of the generator registers, and then the result is added to the main operation of the arithmetic addition. This allows a significant increase in the repetition periods of the output sequences and an improvement of their statistical characteristics. However, for today, there are no reasonable developments in which the structures of AFGs and MAFGs are proposed with an arbitrary value of the module of the recurrent equation. Structure Scheme and Work Principle of AFG and MAFG with Arbitrary Value of the Module of the Recurrent Equation  
Figure 1 shows the structure scheme of AFG and MAFG, which can operate with any value of the recurrent equation module. The AFG consists of registers RG1-RG6, adders AD1 and AD2, multiplexer MUX, and logical element OR. The logic circuit LC is additionally introduced to the MAFG structure. The schemes are given for generators operating according to the following equations:  
\[x_{i}=(x_{i-5}+x_{i-4})\bmod p,\text{(for AFG)} \tag{3}\]  
\[x_{i}=(x_{i-5}+x_{i-4}+a)\bmod p,\text{(for MAFG)} \tag{4}\]  
where: \(x_{i}\), \(x_{i-4}\), \(x_{i-5}\)--numbers at the outputs of registers RG1, RG5, and RG6, respectively. In Equation (4):  
\[a=b_{0}\oplus b_{1}\oplus\ldots\oplus b_{s}, \tag{5}\]  
where: \(b_{i}\) (\(i=0,\,1,\,\ldots,\,s;s\leq n\))--values of the number \(x_{i}\) binary bits; \(n\)--the total number of binary bits. With each clock pulse, new values of numbers are formed in the registers RG1-RG6, in particular in the register RG1--the number determined by the output signal of the multiplexer MUX. Figure 1: Structure scheme of AFG and MAFG. At the output of the logic circuit LC, the signal \(a\) is formed in accordance with logic Equation (5). Adding the LC output signal \(a\), in the process of arithmetic addition, implemented by the adder AD1, can significantly improve the statistical characteristics of the output pseudorandom signals of the generator. In the absence of carry signals at the outputs of the adders AD1 and AD2, to the information inputs of the memory register RG1, through the multiplexer MUX, arrives a number from the information outputs of the adder AD1; moreover, if at least one of them is present, the number of information outputs are those of the adder AD2.