## 4 Implementation and Comparison
### Performance Comparison for the Hyperbolic Function  
We adopt four sets of experiments with TSMC 90-nm, 65-nm and 40-nm. The first and second sets of experiments set the variables to the same values and the results are listed in Table 7. We set iw = 8, qw = 8, kw = 1 and MAE\({}_{\text{def}}\) = 3.5 \(\times\) 10\({}^{-3}\). After the re-segmentation and error adaptation of the proposed method, the same number of segments and MAE are obtained, which means that software improvements do not contribute to the improvement in circuit performance in both sets of experiments. In addition, the effect of software on performance depends on the value of the variable and the slope of the function. Therefore, in this part, the hardware performance improvement is due to the hardware structure improvement of the tree-cascaded structure. The hardware structure of the tanh(x) function includes 23 8-bit comparators, 1 24:1 8-bit multiplexer, 1 2:1 8-bit multiplexer and 1 8-bit adder in the first and second set of experiments. In addition, the critical path consists of 1 8-bit comparators, 1 8-bit multiplexer and 1 8-bit adder. The proposed design saves 4.80% of the area, 13.33% of the delay, and 20.06% of the power when implemented by TSMC 90-nm, while the three percentages are 12.97%, 2%, and 5.34%, respectively, implemented by TSMC 40-nm. The third and fourth groups are supplementary comparative experiments, comparing the universal method proposed in this paper with the more specific methods in [9; 16]. Compared with the first and second sets of experiments, our method has more obvious performance advantages in these two groups of experiments. In the circuit implementation process, we optimize the hardware according to the parity of the function, and only consider the case when the independent variable x is positive. When x is negative, the corresponding positive number is used as input to get the intermediate result, and the final result can be obtained by inverting the intermediate result value and adding 1 (Complement code). ### Performance Comparison for the Hyperbolic Function  
In the performance comparison of sigmoid function implementation, we still take four sets of experiments to analyze, with the use of TSMC 90-nm, TSMC 65-nm and TSMC 40-nm processes, as shown in Table 8.  
In the first set of experiments, the data of ML-PLAC are obtained from [29]. After software processing of the proposed method, the same number of segments, MAE, segment boundary and quantized slope value of each segment are obtained. In addition, the performance of the circuit is basically similar after the hardware implementation. In this set of experiments, too few segments lead to less input of the multiplexers, so the advantages of the tree-cascaded structure are not reflected. There are only 3 8-bit comparators, 1 4:1 8-bit multiplexer, 1 2:1 8-bit multiplexer and 1 8-bit adder in the hardware circuit, and the critical path includes 1 8-bit comparators, 1 4:1 8-bit multiplexer and 1 8-bit adder. In order to prove the advantages of the method in this paper, we conduct the second set of experiments, in which the data of ML-PLAC are not derived from [29] but are acquired by the implemented results according to the method in [29]. We set the range of independent variables, iw, qw and MAE\({}_{\text{def}}\) as (\(-\)1,1), 13, 13 and 3.79 \(\times\) 10\({}^{-4}\), respectively. In ML-PLAC, kw is set to 5 and then we get 29 segments. The critical path includes 1 14-bit comparator, 1 3:1 15-bit multiplexer and 3 15-bit adders. Using the method in this paper, kw is set to 3, we get 22 segments and the critical path is the same as that in ML-PLAC. The hardware architecture implemented by the ML-PLAC method includes 28 14-bit comparator, 4 multiplexers (1 29:1, 2 3:1, and 1 6:1) and 3 15-bit adders, and the relevant components are 21 14-bit comparators, 4 multiplexers (1 21:1, 2 3:1, and 1 5:1) and 3 15-bit adders with the method of this paper.