# Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol
## 4 Results and Comparisons
### Comparisons with State-of-the-Art
On Virtex-7 FPGA, a two-stage pipeline design of [12] utilizes 1.09 (ratio of 5120 over 5102) times higher slices as compared to our two-stage pipelined architecture. Similar to hardware resources, the architecture of [12] requires higher computational time as compared to this work (given in the last column of Table 3). On the other hand, the ECPM architecture of [12] is 1.12 (ratio of 357 over 318) times faster in terms of clock frequency as compared to our design. The \begin{table}
\begin{tabular}{c c c c c c} \hline
**Ref \#.** & \(GF(2^{m})\)**/Algorithm** & **Device** & **FPGA Slices** & **Freq. (in MHz)** & **Latency (in \(\upmu\)s)** \\ \hline \multicolumn{6}{c}{Designs for specific to Elliptic-curve Point Multiplication computation} \\ \hline
[17] & \(GF(2^{163})\)/Montgomery & Virtex-7 & 11657 & 159 & 2.83 \\
[19] & \(GF(2^{163})\)/Montgomery & Virtex-7 & 3657 & 135 & 25.30 \\
[31] & \(GF(2^{163})\)/Double and Add & Kintex-7 & 2253 (7963 LUTs) & 306 & 1060 \\
[12] & \(GF(2^{233})\)/Montgomery & Virtex-7 & 5120 & 357 & 15.78 \\ This work & \(GF(2^{233})\)/Montgomery & Virtex-7 & 5102 & 318 & 15.54 \\ This work & \(GF(2^{233})\)/Montgomery & Kintex-7 & 6102 & 304 & 16.25 \\ \hline \multicolumn{6}{c}{Designs for shared key generation} \\ \hline
[35] & \(GF(2^{233})\)/Montgomery & Virtex-7 & 1809 & 62 & 4130.00 \\
[33] & ECDH + SIKEX434/ - & Artix-7 & 1663 & 195 & 6200 \\
[32] & Ed25519 + X25519/ - & Artix-7 & 3204 & 82 & – \\ This work & \(GF(2^{233})\)/Montgomery & Virtex-7 & 5102 & 318 & 31.08 \\ This work & \(GF(2^{233})\)/Montgomery & Artix-7 & 5957 & 316 & 15.63 \\ \hline \end{tabular}
\end{table} 
Table 3: Comparison to state-of-the-art architectures over 7-series FPGA devices. reason is the support for all the ECC layers in our design while the protocol layer is not considered for implementation in [12]. _Comparison with ECDH design of [35] over \(GF(2^{233})\) on Virtex-7 FPGA._ Although, our design utilizes 2.82 (ratio of 4763 over 1809) times higher slices on Virtex-7 FPGA when compared to the most recent ECDH architecture of [35], however, it is 5.08 (ratio of 318 over 62.5) times faster in terms of clock frequency. The latency requirement of the presented architecture is 132.88 (ratio of 4130 over 31.08) times lower as compared to the most recent design. Moreover, we have compared our FoM results with only the design of [35] as this architecture is specifically described for the ECDH implementation. Therefore, the calculated FoM values are illustrated in Figure 5. It shows that the proposed ECDH accelerator architecture results in higher throughput. Moreover, the proposed dedicated crypto processor architecture is 2.76 (ratio of 6.31 over 2.28) times faster in the context of \(\frac{throughput}{area}\). _Comparison with architecture of [33] over ECDH + SIKEX434 algorithms on Artix-7 FPGA._ Our ECDH architecture utilizes 3.58 (ratio of 5957 over 1663) times lower FPGA slices. The reasons for the use of higher hardware resources in our work are (i) pipelining and (ii) a bit-parallel Karatsuba multiplier for multiplying polynomial coefficients. On the other hand, our ECDH design achieves 1.62 (ratio of 316 over 195) times higher clock frequency as we employed two-stage pipelining to reduce the critical path of the proposed architecture. Moreover, our design is 396.6 (ratio of 6200 over 15.63) times faster in terms of computational time (i.e., latency). There is always a tradeoff between hardware area and performance (in terms of clock frequency or latency). _Comparison with design of [32] over Ed25519 + X25519 curves on Artix-7 FPGA._ The proposed ECDH design is 1.85 (ratio of 5957 over 3204) times more area efficient in terms of FPGA slices. Moreover, due to 2-stage pipelining, our ECDH architecture is 3.85 (ratio of 316 over 82) times faster in terms of operational frequency. The comparison to latency is not possible to provide as the relevant information is not described in [32].