# Thermomechanical Stresses in Silicon Chips for
## 5 Conclusions  
A crucial point in the realization of devices with high performance, reliability, and durability is the evaluation of the mechanical properties of the materials that make up the device itself and are necessary for its assembly. Internal stresses can deform the microstructure of the device and occasionally destroy it. The aim of this work was to investigate the stresses induced in silicon devices during the assembling process as a function of the different assembly parameters, i.e., the physical-chemical characteristics of the involved materials, temperature, and pressure. Silicon chips soldered with AuSn alloy on copper substrates demonstrated differences in stress values and distributions, depending on the experimental parameters of the assembly process. The stress distribution observed on the assembly on the copper substrate, obtained without additional pressure, depends on the temperature: at 180 \({}^{\circ}\)C, no stress is observable, while at 22 \({}^{\circ}\)C a compressive stress is developed in the center of the assembly with a maximum value of \(-\)700 MPa, which reaches \(-\)1 GPa at \(-\)50 \({}^{\circ}\)C. Indeed, from corner to center, a maximum variation in the Raman band of 1.8 cm\({}^{-1}\) is recorded, corresponding to a maximum stress of 900 MPa. These samples present a stress distribution with a symmetric profile with respect to the central area of the chip. In contrast, the samples assembled under pressure conditions of 5 N showed very weak stress values due to inefficient interconnections. The silicon chip assembled on a ceramic substrate without pressure turned out to be extremely interesting. Even in the absence of pressure, the sample did not show a large shift in the Raman position indicating a low stress: it reaches in the central region a compressive stress of 329 MPa, a value that is lower if compared with the corresponding sample assembled on the copper substrate. AuSn solder, with a eutectic temperature of 280 \({}^{\circ}\)C, is a very promising material for the microelectronic industry, because it shows excellent shear strength and good resistance to oxidation and corrosion. Because intensive studies are ongoing to optimize lead-free soldering, the properties of AuSn solder make it useful in high-performance optoelectronics, power electronics, MEMS sensors, and other various applications. However, Raman measurements show high stress on samples assembled with this material, and this problem \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Temperature** & **Maximum** & **Minimum** & **Average** & **Maximum** & **Unit for Shift** \\
[\({}^{\circ}\)**C]** & **Value** & **Value** & **Value** & **Variation** & **and Stress** \\ \hline  & 519.87 \(\pm\) 0.04 & 519.18 \(\pm\) 0.05 & 519.56 \(\pm\) 0.02 & 0.69 \(\pm\) 0.09 & [cm\({}^{-1}\)] \\
20 & \(-\)170 \(\pm\) 20 & \(-\)499 \(\pm\) 20 & \(-\)345 \(\pm\) 6 & 329 \(\pm\) 30 & [MPa] \\ \hline \hline \end{tabular}
\end{table} 
Table 8: Raman shift [cm\({}^{-1}\)] and stress values [MPa] obtained for the B_AuSn sample. must be considered to improve the mechanical reliability of the bonded joints. Studies on sintering are ongoing as an alternative to soldering. The following supporting information can be downloaded at [[https://www.mdpi.com/article/10.3390/app13042737/s1](https://www.mdpi.com/article/10.3390/app13042737/s1)]([https://www.mdpi.com/article/10.3390/app13042737/s1](https://www.mdpi.com/article/10.3390/app13042737/s1)), Table S1: Comparison between results acquired at position [6,6] of the A_AuSn sample at an increasing temperature (from \(-50\) to \(180\)\({}^{\circ}\)C) and at a decreasing temperature (from \(180\) to \(-50\)\({}^{\circ}\)C) temperature. FWHM: full width at half maximum. Conceptualization, R.S., D.P. and F.C. ; methodology, R.S. and D.P. ; software, C.M. ; validation, C.M. ; formal analysis, C.M. ; investigation, C.M. ; resources, R.S. and D.P. ; data curation, C.M. ; writing--original draft preparation, R.S., C.M. and D.P. ; writing--review and editing, R.S., D.P., C.M. and F.C.