# A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis
## 3 TSV Reliability
### Noise Coupling  
One of the major challenges of TSVs is their signal integrity (SI) characteristics, particularly coupling. TSVs have a relatively large diameter and are suspended in a low-resistance silicon substrate with only a thin layer of oxide (known as a TSV liner) separating them from the substrate. This thin oxide liner and the large TSV surface area result in significant capacitance between the TSV and the substrate. As a result, signal coupling occurs from the TSV into the substrate and then to other TSVs. The diameter of the TSV and the thickness of the liner are determined by the manufacturing process and cannot be easily altered. Thus, designers must consider design techniques to handle the low-impedance coupling path between TSVs. Failure to address noise coupling may cause a circuit to malfunction or degrade its performance in several ways. It is important to consider TSV fabrication techniques for power-noise coupling during service. Typical TSV parameters with noise trends using different fabrication techniques are presented in Table 2. The power supply noise in TSV-based 3-D ICs increases with the scaling of CMOS technology. This trend occurs because the current density within each layer and the operating frequency of 3-D ICs tend to increase as CMOS technology scales. With the same TSV technology and distribution conditions, larger currents pass through each P/G TSV, resulting in higher levels of on-chip power supply noise in 3D ICs. The noise signal ratio due to on-chip inductance is increasing due to increased switching speeds, reduced spacing between interconnects, and reduced device noise tolerance. The effects of this noise, such as oscillation, overshoot, and downshoot, make chip performance a concern in design. The effects of crosstalk-induced overshoot and undershoot generated at noisy sites can propagate false switches and generate logic errors. False switching occurs when the overshoot or downshoot amplitude exceeds the threshold. The peak overshoot and undershoot generated by the noise field can wear away the thin gate oxide layer and lead to permanent chip failure. As the line resistance increases, the noise peak decreases. As the width of the PMOS driver increases, the victim line is more susceptible to crosstalk noise. The crosstalk level increases substantially with increasing driver width, as shown in Table 2.  
For instance, coupling between signal transmission lines may result in changes in the logic value at the transistor gate input, leading to incorrect logic or short-circuit currents. Similarly, coupling between the signal TSV and the power supply TSV can lead to changes in the VDD or GND supply rails, which can increase leakage currents. Furthermore, TSV - TSV coupling may result in the conversion signal changing value too slowly, leading to timing \begin{table}
\begin{tabular}{l c c c} \hline \hline
**Parameter** & **Via-First** & **Via-Middle** & **Via-Last** \\ \hline Diameter (\(\mu\)m) & 4 & 4 & 10 \\ Pitch (\(\mu\)m) & 8 & 8 & 20 \\ Length (\(\mu\)m) & 10 & 60 & 60 \\ TSV resistance (\(\Omega\)) & 5.7 & 0.9 & 0.02 \\ TSV inductance (pH) & 4.2 & 49.8 & 34.9 \\ TSV coupling capacitance (tf) & 1.2 & 6.7 & 6 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Typical parameters for different TSV fabrication technologies [58; 59]. violations. Therefore, to mitigate the adverse effects of coupling, 3D IC designers can implement various design techniques, such as optimizing the power distribution network, utilizing shielded TSVs, and reducing the signal's rise time. These techniques can help reduce the impact of noise coupling and improve the overall signal integrity of TSVs in 3D ICs [3; 60]. According to the shrinking of CMOS technology CMOS RF/mixed signals is the leading response for moderate cost, moderate power, and extreme functionality and provides higher performance. However, circuit sizes are becoming tremendous and enlarging the noise of digital circuits.