## 5 Comparative Assessment with the Existing Topologies  
This section includes a comparison study to emphasize the importance of PT. The PT is compared to various recently proposed inverter architectures in terms of the semiconductor switches, diodes, capacitors, gain, total voltage stress, and cost function, among other things. Table 2 compares the PTto existing inverter topologies in terms of the single-phase leg. However, the components necessary to build a three-phase architecture are three times those required for a single-phase leg. The component count per level \((F_{\text{C/L}})\) can be mathematically written as  
\[F_{\text{C/L}}=\frac{N_{\text{C}}+N_{\text{S}w}+N_{D}+N_{S}+N_{dri}}{N_{L}} \tag{18}\]  
where \(N_{L}\), \(N_{\text{C}}\), \(N_{D}\), \(N_{\text{S}w}\), and \(N_{S}\) are the number of levels, capacitors, diodes, switches, and the number of isolated DC sources per phase, respectively. Additionally, the cost function will decide the overall cost of the PT. The weight factor (\(\alpha\)) for the PT is set to one because the switching components and TSV are both valued equally.  
The cost factor is defined by Equation (18) as  
\[CF=\frac{[N_{SW}+N_{\text{C}}+N_{D}+N_{dri}+\alpha TSV]\times N_{S}}{N_{L}} \tag{19}\]  
The PT has a smaller \(CF\) and \(F_{\text{C/L}}\) than prior topologies. The proposed topology is compared with other existing topologies for TSV and in references [16; 18] are better as compared to proposed topology and the proposed topology is better while comparing all other topologies in Table 2 for specific levels, i.e., five levels. Although topologies [7; 8; 22] share the same gain factor, they have a higher component count per level factor and cost function. As a result, PT employs the least number of components, resulting in a more compact inverter. As a result, the weight and energy consumption of the PTare decreased. Additionally, it lowers equipment costs by lowering the TSV and provides the lowest possible voltage and current THD performance. As a result, the proposed inverter beats its competitors in every way.In comparison to other existing topologies, the PT's overall efficiency is superior. Table 3 presents a cost comparison, which was evaluated to help further clarify the unique benefits of the proposed topology. All topologies were given the same voltage parameters for the sake of cost analysis. In addition, the cost analysis gave equal weight to all factors. The costs for alternative topologies are listed in Table 3, and the proposed topology is shown to have the lowest overall component costs.  
\begin{table}
\begin{tabular}{c c c c c c c c c c c c c} \hline
**Topology** & \(A\) & \(B\) & \(C\) & \(D\) & \(E\) & \(F\) & \(H\) & \(F_{CIL}\) & \(G\) & \(CF\) & **Losses (W)** & **Efficiency** \\ \hline
[5] & 7 & 10 & - & 4 & 1 & 10 & 8 & 3.14 & 1.5 & 4.57 & 25.44 & 92.4\% \\ \hline
[7] & 7 & 6 & 2 & 1 & 1 & 8 & 6 & 2.28 & 3 & 3.28 & 23.48 & 95.45\% \\ \hline
[8] & 5 & 6 & 2 & 2 & 1 & 8 & & 2.2 & 2 & 3.6 & 23.67 & 95.23\% \\ \hline
[12] & 7 & 10 & - & 3 & 1 & 9 & 10 & 3.28 & 1.5 & 4.57 & 24.68 & 94.45\% \\ \hline
[13] & 7 & 9 & - & 3 & 1 & 6.5 & 8 & 2.87 & 1.5 & 3.78 & 25.89 & 94.76\% \\ \hline
[14] & 7 & 9 & - & 3 & 1 & 8 & 8 & 2.85 & 1.5 & 4 & 22.24 & 95.48\% \\ \hline
[15] & 5 & 9 & - & 1 & 1 & 9 & 9 & 3.8 & 2 & 5.6 & 22.45 & 95.34\% \\ \hline
[16] & 5 & 6 & 2 & 3 & 1 & 6 & 6 & 3.4 & 1 & 4.6 & 18.69 & 96.23\% \\ \hline
[18] & 5 & 10 & - & - & 2 & 14 & 9 & 3.8 & 1 & 13.2 & 25.25 & 92.14\% \\ \hline
[P] & 5 & 4 & 1 & 1 & 1 & 6 & 4 & 2 & 2 & 3.2 & 14.21 & 96.7\% \\ \hline \end{tabular}  
A : \(N_{L}\), B : \(N_{SW}\), C : \(N_{D}\), D : \(N_{\text{C}}\), E : \(N_{S}\), F : TSV, G : Gain, H : \(N_{dri}\)  
\end{table}
Table 2: Comparative assessment for per phase leg with recent SCMLI topologies.