# A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit
## 1 Introduction  
With the advantages of high stability [1; 2; 3] and strong portability [4; 5; 6; 7], the all digital delay-locked loop (ADDLL) is widely used as multiphase clock generator [8; 9; 10; 11] in double data rate (DDR) synchronous interfaces. The Open NAND Flash Interface Specification (ONFI) [12], which is the industry standard, strictly stipulates the timing requirements of non-volatile double data rate (NV-DDR) high-speed interfaces. To ensure the accuracy of data sampling, the ONFI specifies that in the write operation, the edge of the data strobe signal (DQS) is aligned to the center of the valid window of data signal (DQ); in the read operation, the edge of the DQS is aligned to the edge of the DQ. Therefore, a four-phase DLL is needed in NAND Flash interfaces to provide different delay for the read and write channels. According to ONFI 5.0, the four-phase DLL must be able to achieve high precision in a wide frequency range of (33 MHz, 1.2 GHz).  
In the synchronous interface circuit, the system clock (SCLK) needs to go through a complex clock network [13; 14; 15] before entering the four-phase DLL. Then, the input clock passes through the internal buffers and logic units to reach the 0\({}^{\circ}\) output clock (CLK0) of the four-phase DLL [16]. The propagation delay caused by these units is easily affected by process, voltage and temperature (PVT) [17; 18; 19], leading to unpredictable clock skew between SCLK and CLK0. The clock skew causes the four-phase clock outputs to be offset from SCLK, increasing the bit error rate (BER) at high-speed data transmission. Moreover, this impact becomes more serious as frequency increases, which will greatly limit the system operating frequency; thus, the clock skew should be eliminated.  
A classic four-phase digitally controlled delay line (4P-DCDL) is used in four-phase DLLs [20; 21] to generate four-phase outputs, which consist of four sub-lines with the same structure and control code. To improve frequency range and phase accuracy, the 4P-DCDL of the four-phase DLL in [16] adopted a configurable structure with an adaptive time-to-digital (TDC)-based controller, which could meet the requirements of ONFI 4.2. However, this circuit does not consider the four-phase offset brought by clock skew in synchronous systems. In [22], the authors proposed a half-delay-line skew-compensation circuit (HDSC)with a phase adjuster (PA), which could shorten the delay line length by half without affecting the locking frequency range. With the advantages of small area and low power consumption, the HDSC architecture is suitable for wide-range applications. However, the PA requires a clock with a 50% duty cycle, which is difficult for the clock system.  
A four-phase all-digital DLL with a de-skew circuit is proposed in this paper, which has the advantages of wide frequency range and high precision. The four-phase DLL adopts the configurable delay line and the adaptive TDC-based controller to generate four-phase outputs over a wide frequency range. The embedded de-skew circuit is based on the HDSC architecture with a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to precisely align the system input clock and the 0\({}^{\circ}\) output clock. Moreover, a parallel-cascade configuration is proposed, which can solve the variable phase alignment problem due to the switching of de-skew mode and four-phase output generation mode.  
This paper is organized as follows. Section 2 describes the architecture of the proposed four-phase all-digital DLL with a de-skew circuit. Section 3 details the implementation of the de-skew circuit and gives the design formulas of the frequency range and phase accuracy. Section 4 presents the proposed parallel-cascade configuration. Section 5 shows the chip micrograph and chip testing results. Finally, Section 6 summarizes this paper.