## 1 Introduction
### Literature Review
Recent developments in multiplier designs have primarily concentrated on enhancing both efficiency and speed, particularly in the context of cryptographic systems that necessitate fast and accurate computations. For instance, [PERSON] et al. [19] engineered a semi-systolic array multiplier that significantly diminishes time complexity, enabling it to handle rapid multiplication tasks with impressive performance metrics. This innovation is especially valuable in environments where quick calculations are vital, such as digital signatures and encryption algorithms. Expanding upon this foundational work, [PERSON] [43; 44] proposed semi-systolic Montgomery modular multipliers that utilize a two-tiered approach to systolic computation. This design not only enhances area utilization by effectively managing hardware resources but also substantially reduces latency, making it a critical advancement for high-performance VLSI implementations. The two-tiered methodology facilitates a robust capacity for parallel processing and pipelining, allowing multiple operations to be executed simultaneously. As a result, this approach leads to a marked increase in the efficiency of modular multiplication operations, which are essential for a range of contemporary cryptographic applications. Additionally, [PERSON] and [PERSON] [45] introduced an innovative and versatile multiplier architecture that adeptly manages both parallel and serial input formats. This flexibility allows for optimal performance across a diverse range of operand types, en hancing adaptability in various computational scenarios. Building on this foundation, [PERSON] [46] designed one-dimensional bit-serial and bit-parallel systolic array structures specifically aimed at computations in the Galois Field GF(2\({}^{m}\)). These structures improve resource utilization, ensuring that hardware resources are deployed effectively and achieving greater processing efficiency. This design is particularly beneficial for applications such as error correction codes and cryptographic systems, where the demand for speed and efficiency is critical in today's digital landscape. [PERSON] and [PERSON] [23] have made notable contributions to the field through the introduction of a polynomial basis systolic multiplier specifically engineered for designated field sizes. This advancement signifies a shift towards specialized architectures that are adept at addressing the distinct requirements of various computational tasks. In a related context, [PERSON]'s implementation of a Toeplitz matrix-vector representation has effectively reduced the complexities associated with Montgomery-based bit-parallel multipliers. This methodological refinement has resulted in designs that demonstrate enhanced efficiency and practicality, as documented in [38]. Moreover, [PERSON]'s development of a two-dimensional parallel systolic multiplier [39], grounded in the Montgomery algorithm, achieves impressive performance while maintaining minimal spatial requirements. This architecture facilitates the simultaneous execution of multiple operations, thereby significantly increasing throughput and establishing itself as an essential asset in high-demand computational environments. [PERSON] [40] has significantly advanced the field by integrating interleaving multiplication techniques into a two-dimensional parallel systolic multiplier architecture. This innovative approach facilitates effective resource utilization while simultaneously ensuring high performance levels. The implementation of interleaving techniques allows for the concurrent processing of multiple operations, thereby substantially enhancing throughput. These developments collectively signify a concerted effort to establish flexible multiplier architectures that can adapt to the evolving requirements of modern cryptographic applications. Furthermore, they contribute to improved performance and resource efficiency in hardware implementations.