# Constrained Optimization of FPGA Design for Spaceborne InSAR Processing
## 4 System Analysis under Double Constraints
### Analysis of Threads in Interferogram Generation  
This part analyzes the relationship between resources and processing time in interferogram generation. According to the algorithm introduced in Section 3, 16,384 \(\times\) 4096 image points were to be calculated in the process of interferogram generation, and 512 \(\times\) 512 points were to be calculated in the coarse registration process; thus, the former required much more time than the latter process. Therefore, the time interferogram generation took up was critical to the total system runtime.  
If 64-bit float complex data is regarded as a thread, the number of threads could represent the degree of parallelism. Faced with the constraint of the 512-bit data width for one DDR3 SDRAM chip, the thread can be set as 1, 2, or 4. Here, we designed an IP in 4 threads to find the critical resource. The synthesis results of the IP are shown in Table 1. Due to nonlinear operations in the calculation process, LUT took up the most significant proportion among other resources, so LUT was the critical resource.  
To increase the proportion of the coarse registration on the system processing time, the thread of coarse registration was set as 1. When the system clock worked at 100 MHz,  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Logic** & **LUT** & **FF** & **BRAM\_36K** & **DSP** \\
**(Amount)** & **(433,200)** & **(866,400)** & **(1470)** & **(3600)** \\ \hline Results (percentage) & 41,723 (9.63\%) & 25,506 (2.94\%) & 7 (0.48\%) & 112 (3.11\%) \\ \hline \hline \end{tabular}
\end{table}
Table 1: Vivado synthesis results of the IP.  
\(512\times 512\) points were calculated in 262,144 clocks, 2.62 ms in theory. Therefore, the ideal coarse registration time \(T_{c}\) was 7.86 ms. Similarly, to calculate 16,384 \(\times\) 4096 points, the ideal interferogram generation time \(T_{g}\) was 671.09 ms. When the thread of interferogram generation changed from 1 to 4, the results are shown in Table 2. \(T_{i}\) was the entire calculation time \(T_{i}=T_{c}+T_{g}\).  
The variation \(\Delta R_{\text{LUT}}\) was obtained by subtraction between the schemes \(R_{i}\), as shown in Table 3. When threads changed from 1 to 4 \(\
abla G\) was less than 0.1, which indicated that relatively few resources were saved while the processing capacity was lowered sharply. As \(\
abla G\) was too low to meet the requirement \(\
abla G\geq\
abla G_{gate}=3\), there was no balanced scheme. As for \(\Delta h\) (i.e., from scheme \(b\) to plan \(a\)), the resources were saved by 2.41%, but the time increased by 97.7%.  
When the thread was 4, 256-bit data width, two images were read from the two DDRs, respectively. The calculation results, 128-bit phase and 256-bit coherence coefficients were written into two DDR3 SDRAM chips. Since the data width of either DDR3 SDRAM channel was no more than 512 bits, there was no efficiency loss when data passed through the arbitrating structure. However, when the thread was 8, either channel reading or writing worked in 512 bits, which led to efficiency loss. Therefore, due to the hardware constraints, it was hard to analyze the performance of the 8-thread scheme.  
By analyzing schemes with different threads, low \(\
abla G\) (i.e., lower than 0.5) indicated that the greater processing capacity could be improved with fewer resources. As the thread of FPGA increased, the processing capacity increased accordingly.