## 5 Conclusions  
In this paper, we propose the design of an STFT processor architecture that supports a variable overlap ratio of 0/25/50/75% to minimize the data loss depending on the type of window used as well as variable window lengths of 16/64/256/1024 to provide various time-frequency resolutions. In the proposed WM architecture for our R4 MDC-based STFT processor, the single-channel data stream is converted into four overlapped data streams by 75%, greatly reducing the number of delay elements needed, which occupy the largest portion of the device's area. To assess the complexity of the proposed STFT processor, we implemented the conventional R2 SDF-based and R4 MDC-based STFT processors as well as the proposed STFT processor. Our comparison results indicate that the proposed processor architecture can reduce the logic gates by 63% compared with the R2 SDF-based STFT processor. It can also be implemented with 54% fewer gates compared with the conventional R4 MDC-based STFT processor. We have thereby demonstrated that the proposed architecture is efficient for the implementation of STFT processors, which are widely used in many fields to measure the changes in a signal's frequency over time.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Block Name**} & \multirow{2}{*}{**R2 SDF Based**} & \multirow{2}{*}{**R4 MDC Based**} & \multirow{2}{*}{**Proposed**} & \multicolumn{2}{c}{**Reduction (\%)**} \\ \cline{5-6}  & & & & & **R2 SDF** & **R4 MDC** \\ \hline Butterfly Unit & 30,072 & 15,036 & 15,036 & 50 & 0 \\ Multiplier & 141,138 & 47,046 & 47,046 & 67 & 0 \\ Delay Elements & 369,360 & 369,360 & 135,888 & 63 & 63 \\ Total & 540,670 & 431,442 & 197,970 & 63 & 54 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Comparison of the logic synthesis results between the proposed and conventional STFT processors.  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**Circuit**} & \multirow{2}{*}{\begin{tabular}{c} _Tech_ \\ **(nm)** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **FFT** \\ **Architecture** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Window** \\ **Length (N)** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Overlap** \\ **Ratio (\(\alpha\))** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Frequency** \\ **(MHz)** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Operating** \\ **Time (ns)** \\ \end{tabular} } & \multirow{2}{*}{\
\begin{tabular}{c} **Area** \\ **(mm2)** \\ \end{tabular} } & \multirow{2}{*}{
\begin{tabular}{c} _Anorm_ \\ \end{tabular} } \\ \hline
[18] & 180 & R2 SDF & 32 & max. 94 & 180 & N.A. & 7.74 & 2.15 \\ Proposed & 65 & R4 MDC & 16/64/ & 0/25/ & 200 & 175/665/ & 0.27 & 0.93 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Comparison of the proposed STFT processor with previous research results.  
and led the research, analyzed the implementation results, and wrote the paper. All authors have read and agreed to the published version of the manuscript.  
This research received no external funding.  
This work was supported by Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No. 2020-0-00201) and CAD tools were supported by IDEC.  
The authors declare no conflict of interest.