# A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits
## 6 Test Pattern Generations for Delay Faults
### Pattern Grading and Evaluation  
Various pattern selection, grading, and reordering techniques are available in the literature for SDD and HDD detection. The timing-unaware N-detect ATPG [29] is found to be better than TA ATPG in terms of run time and ability to sensitize multiple long paths. But it suffers from the significant disadvantage of pattern count. The N-detect pattern set is considered as a base pattern repository, and the pattern count is reduced through pattern grading, and evaluation [21; 31; 32]. In [31], output deviation is the factor used to guide the pattern selection for detecting SDDs. The delay defect and signal transition probabilities are used to calculate the pattern's output deviations. The delay defect probability is calculated using the pdf of the delay  
Figure 6: Comparison of normalized values of SDDs detected, pattern count, CPU runtime of various N-detect and TA pattern (Usb_function benchmark) [21]. distribution of each gate. The output deviation at the observation point is compared with a threshold value, and the corresponding pattern is stored in a list if it satisfies the threshold condition. When the pattern occurs many times in the list, it is considered to be an effective pattern. This metric has a high correlation with the path length. Hence, it acts as a promising metric to guarantee that the pattern propagates the fault effect through the long paths. The layout information is also added in the calculation of output deviation in [33] to improve the accuracy. Compared to the commercial TA ATPG tool, the output deviation-based method has produced the best and reduced pattern set that sensitizes more long paths. But the problem here is that the value of the output deviation metric will remain the same for different paths for large circuits, for example, when there are more than twenty gates in the paths. As the value saturates, especially for larger designs, this metric cannot be used to differentiate between long and intermediate paths, leading to a loss of accuracy. To make the fault coverage and pattern count comparable to TA ATPG, several other hybrid techniques that use the N-detect pattern repository for pattern grading and selection are proposed in the literature [34; 35; 36]. A weight assignment to the patterns is performed based on its ability to detect the SDDs. The ability of the patterns to sensitize the fault effect through the longer path is used as a criterion for assigning weights to the pattern in [21; 36]. Higher weights are assigned to such patterns. In [21], the process variation (PV) and crosstalk information are included in the path delay calculation, which increases the accuracy of pattern selection for SDD detection. Here the path length is regarded as a random variable as it considers the effect of PV and crosstalk, and the pdf of the path is used for path delay evaluation and weight assignment to patterns, as shown in Figure 7. Here, weights are assigned to different paths sensitized by the same pattern as per the threshold Lth value. The overall weight calculation of the pattern is given by Equation (1), where \(W_{path_{i}}\) is the weight of the path \(j\) sensitized by the \(pattern_{i}\), as shown in Figure 7. \(W_{pattern_{i}}\) is the weight of the \(pattern_{i}\). \(N_{i}\) is the total number of paths sensitized by the \(pattern_{i}\). There is no saturation problem like the delay defect probability matrix (DDPM) of the output deviation method. Even though these methods reduce the pattern count for SDD detection through pattern selection, the selected pattern alone cannot achieve the maximum TDF coverage. The top-off patterns are also required to achieve the maximum TDF coverage. But the selected and the top-off pattern together exceeds the 1-detect TDF pattern count. This disadvantage does not allow us to extract the complete essence of the proposed pattern selection methods. This is because the 1-detect TDF-based pattern generation produces the maximum fault coverage for the circuit under test.