# A Reconfigurable Framework for Hybrid Quantum-Classical Computing
## 3 Proposed Framework
### Quantum Machine Learning Task
#### 3.1.4 Training: Gradient Computation and Loss Function
For a mini-batch of size \(B\), the loss function is averaged over the batch:  
\[\mathcal{L}_{\text{batch}}=-\frac{1}{B}\sum_{i=1}^{B}\Bigl{[}y^{(i)}\log \Bigl{(}\hat{y}^{(i)}+\epsilon\Bigr{)}+(1-y^{(i)})\log\Bigl{(}1-\hat{y}^{(i)} +\epsilon\Bigr{)}\Bigr{]} \tag{5}\]  
This batched approach effectively reduces computational overhead by averaging gradients across multiple samples before updating circuit parameters, while maintaining training stability through consistent gradient estimates. The implementation achieves this by accumulating gradients over each batch. We implement a processing pipeline on the FPGA, see Figure 4, which consists of multiple kernels performing optimized parameter optimization specifically designed for quantum circuit training. The kernel architectures are structured around efficient gradient computation and weight updates, utilizing high-level synthesis compilers to synthesize C++ descriptions of the kernels to hardware description language. The pipeline employs multiple AXI interfaces for data communication: AXI Master interfaces for high-bandwidthdata transfer and AXI-Lite Slave interfaces for managing control and status signals. The kernels perform three critical computations:  
* Loss calculation: Implements parallel cross-entropy loss computation using optimized log-likelihood functions. * Gradient computation: Accelerates stochastic gradient descent calculations through block processing. * Weight updates: Performs parallel parameter updates using computed gradients and configurable learning rates. As illustrated in Figure 4, the _Input Data_ block initiates the process by transferring predicted outputs _y_pred_ (predicted probabilities generated by the quantum circuit for the input data), perturbed outputs _y_pred_plus_batch_ (model outputs from perturbed forward passes used for gradient estimation), ground-truth labels _y_true_, and the current circuit parameters _current_weights_ from the host memory to the on-board (local) memory. This transfer is optimized using separate LOAD_WEIGHTS and LOAD_BLOCK pipelines for burst transfers and localized access, minimizing latency and improving throughput. The kernels define the generalized input and output interfaces using HLS pragmas, as shown in Figure 5. Scalar inputs such as the learning rate \(learning\_rate\) (used for parameter updates), the stability parameter \(\epsilon\) (used to prevent numerical instability in division and logarithms), the number of qubits \(n_{qubits}\), and the number of circuit layers \(n_{layers}\) are configured via the AXI-Lite control registers generated by #pragma HLS INTERFACE s_axilite. This interface allows the host processor to dynamically adjust these parameters at runtime, enhancing the flexibility and reusability of the kernel. To avoid an inflexible design, the kernel does not hardcode \(n_{qubits}\) and \(n_{layers}\), thus supporting various quantum circuit topologies without requiring recompilation. High-bandwidth memory transfers for array inputs, specifically _y_pred_ (probabilities from the quantum circuit based on current model weights), _y_pred_plus_batch_ (probabilities from the quantum circuit based on perturbed weight configurations), _y_true_ (ground-truth labels), and _current_weights_ (current values of model parameters), as well as array outputs including _grads_ (computed gradients for each parameter), _updated_weights_ (parameter values after the optimization step), and _loss_out_ (computed loss value for the current mini-batch), are achieved using AXI-Master ports specified via #pragma HLS INTERFACE m_axi. This directive allows the host to supply the base addresses of memory buffers, enabling the FPGA to perform direct memory access (DMA) for efficient data movement. This significantly enhances the throughput of data between host and FPGA on-board memory, especially for large batch sizes or complex quantum circuits. Figure 4: FPGA pipeline architecture with multiple kernels.