# A Manycore Vision Processor for Real-Time Smart Cameras +
## 5 Results and Analysis
### Performance Evaluation
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Reference** & **Architecture** & **Cycles/Pixel** & **Application Agnostic?** \\ \hline
[35] 2014 ** & FPGA & 1.00 & no \\
[34] 2014 & FPGA & 1.00 & no \\
[31] 2013 & FPGA & 1.36 & yes \\
[33] 2017 ** & FPGA & 2.11 & no \\ Ours (sim.) & MPSoC-FPGA & 3.02 & yes \\
[32] 2013 ** & FPGA & 3.03 & no \\
[30] 2010 & SIMD ASIC & 3.42 & yes \\
[12] 2015 & MPSoC-ASIC & 7.07 & yes \\
[29] 2018 * & Embedded GPU & 7.19 & yes \\ Ours (impl.) & MPSoC-FPGA & 11.61 & yes \\ \hline \hline \end{tabular}  
* Includes the initial image transfer time. ** includes acquisition and visualization scheme.  
\end{table} 
Table 5: Comparison of implementations of the HCD. (CUs), where each CU has eight processing elements. The FGPU's programming model is based on single-instruction multiple-threads (SIMT) and provides full-thread divergence, which means that each PE operates individually over the same program. Our manycore has the same characteristic, where each PE is independent and runs the same program. The authors in [6] benchmarked the FGPU with a varied number of CUs, as well as with a diversity of application domains. The authors connected the FGPU to an ARM processor using the AXI bus in a similar fashion to our work. The ARM was then responsible for sending data to be processed and receiving back the results. To perform this comparison, we used the ARM processor to operate in the place of our camera, resulting in a very similar testbench. Figure 12 shows the results for our testbench in different configurations, running some applications [4]. In [6], there is the benchmarking of a _Sharpen_ filter, a convolution operation in a \(5\times 5\) neighborhood. For the sake of comparison, we selected their results with an eight-CUs configuration (64 PEs), the one with the highest number of PEs. Table 6 shows the comparison in its first two rows. We can see there that the manycore architecture is more efficient in parallelism exploration for the same number of PEs, reaching a higher throughput (pixels/s) with a smaller operating frequency. The second comparison is against a commercial embedded GPU [36]. The third and fourth rows of Table 6 show the comparison. In [36], a NVidia Jetson TX2 with 256 cores runs the HCD algorithm. We compared it with our manycore with 64 PEs (4 times fewer PEs than the Jetson TX2). We can see in Table 6 that our architecture is more efficient in the parallelism exploration, with \(5\times\) fewer cycles needed per pixel. \begin{table}
\begin{tabular}{l c c c c c c c} \hline \hline
**Architecture** & **Algorithm** & **Image Resolution** & **Time Per Frame** & **fps** & **freq. (MHz)** & **Pixels/s** & **Cycles Per Pixel** \\ \hline MCVP-64 (64 PEs) & Convolution \(5\times 5\) & 256 \(\times\) 256 & 3.55 & 282 & 100 & 18,481,152 & 5.411 \\ \hline FGPU-8 (64 PEs) [6] & Sharpen \(5\times 5\) & 512 \(\times\) 512 & 6.1 & 16.4 & 250 & 4,299,162 & 58.150 \\ \hline MCVP-81 (81 PEs) & HCD & 256 \(\times\) 256 & 9.17 & 109 & 100 & 7,143,424 & 14 \\ \hline NVidia Jetson TX2 [36] (256 cores) & HCD & 640 \(\times\) 480 & 26 & 38 & 854 & 11,673,600 & 73.156 \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Efficiency comparison among. Figure 12: Performance in frames per second per architecture, all running in a testbench without a camera.