# Analysis of Pre-Driver and Last-Stage Power--Ground-Induced Jitter at Different PVT Corners
###### Abstract  
This paper presents the study of power/ground (P/G) supply-induced jitter (PGSI) on a cascaded inverter output buffer. The PGSI) analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct P/G DC supply voltages at the pre-driver (i.e., \(V_{DD}/V_{SS}\)) and last stage (i.e., \(V_{DDQ}/V_{SSQ}\)). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input-output buffer information specification (IBIS)-like model. Accordingly, the measured PGSI) depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver's technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSI) induced by both the driver's IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions. PVT corner analysis; eye diagram jitter; power supply-induced jitter; power delivery network; IBIS algorithm; power and ground noise; signal and power integrity; aerospace +
Footnote †: journal: Sensors  
020222265310  
Timing and amplitude distortions of the signals (i.e., currents and voltages) are not only due to channel design, such as inter-symbol interference, reflection, and crosstalk between lines, but can also be induced by the power and ground supply voltage (PGSV) variations at the die level. In fact, the fast and power state-dependent switching current profile of different power and ground supply domains lead to a considerable power and ground supply noise, e.g., (\(L.di/dt\)) that affects the nonlinear dynamic electrical behavior of the transistor-based IO device. Consequently, it is crucial to study the IO device's SiPI issues under different PVT corners and supply voltage variations, input signal noise, and crosstalk, etc., in order to ensure a robust and reliable device performance [1,2]. In fact, jitter is defined by the timing deviation (e.g., TD \(=t_{2}-t_{1}\)) of the distorted output signal (e.g., assuming PGSV variations) under a sequence of transition edges from their ideal positions (e.g., with constant DC PGSV), as shown in Figure 1. These timing differences depend on the PGSV variations and can be different for the rising and falling transitions [4], under a determined bit error rate and data speed. Therefore, designers need to estimate the jitter induced by SiPI simulation of high-speed IO links [5,6]. Furthermore, PGSV variations affect the transistor current-voltage (I-V) and capacitance-voltage (C-V) operation regions (e.g., cut-off, linear and saturation) forming the output buffer/driver [5]. Moreover, distinct PDNs are commonly deployed for powering the pre-driver and last stage, \(V_{DD}/V_{SS}\) and \(V_{DDQ}/V_{SSQ}\), respectively, as shown in the IO buffer circuit diagram of Figure 2. The device's switching currents in the last stage (e.g., \(i_{H}(t)\) and \(i_{L}(t)\)) and pre-driver stage (e.g., \(i_{Hp}(t)\) and \(i_{Lp}(t)\)), flowing via the PDN, produce the PGSV variations, generating the timing distortions at the output voltage, which is defined by the P/G supply-induced jitter (PGSIJ) [7].