# Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions
## 3 Materials and Methods
### Module Relocation  
In the proposed approach, homogenous array of processing elements uses numerous instances of logically equivalent partitions. Physical implementation of any module associated with a partition needs to be contained within explicitly defined sector of FPGA fabric--PBlocks. If partitions are assigned to compatible PBlocks with the same arrangement of hardware components, they can use identical relative placement and routing (P&R). Instead of performing independent implementation runs for each instance, common results can be applied to all partitions.  
Module relocation--i.e., moving a fully placed and routed module to another partition at a different position--can be performed by forcing fixed P&R constraints or by readressing entire partial bitstreams. In the first scenario, location-specific implementation runs are drastically accelerated since modules are already pre-placed and pre-routed. In the other, the location-specific run is not required at all, provided that timing closure can be guaranteed by different means (e.g., by using register buffers or constraining net delays on both sides of partition-to-static connection) [29].  
Although Xilinx Vivado toolchain offers no support for module relocation per se, it can be obtained using a combination of inbuilt Partial Reconfiguration Flow (PRF) and Isolation Design Flow (IDF) with additional constraining and TCL scripted processing of intermediate results. The techniques used to provide module relocatability are described in detail in previous work by the main author of this article [29; 39]. General concept and details with crucial influence on floorplanning are outlined below.  
Partition relocation is performed between partitions that have vertical span of a single clock region and identical set of reconfigurable resource columns with the same interconnected alignment. For each different PBlock construction, reconfigurable modules are implemented only once in a so-called reference partition. Placement and routing results are then extracted and re-applied as constraints with new location offsets. Alternatively, a partial bitstream can be generated and relocated by changing frame address register value. Static design with black-box partition is implemented independently. Partitions are isolated from the static to prevent global routing feed through. A so-called isolation fence--single primitive wide space that cannot be used for logic placement--is required. Partitions can be assigned to the same columns in adjacent clock regions. However, as global routing cannot cross partitions, at least a clock-region high sector of all columns needs to be included in the static. Partition-to-static connection cannot cross clock-region borders, as the adjacent regions may be unavailable at different locations. Consequently, partition ports must be placed only alongside either left, right, or both vertical borders. All partition-to-static nets use additional buffers on both ends to preserve identical connection and help with timing closure management. Buffers in the static serve as anchoring points. They can be  
Figure 5: Other patterns used in Virtual CGRAs: linear dataflow (**a**) and configurable each-to-any (e.g., crossbar) connection (**b**).  
implemented alongside different entities in CLBL or CLBM columns. The column type does not need to match, but the placement in relation to partitions must be the same. This is obtained by implementing the partition-to-static interface in the reference design and then relocate the results in form of P&R constraints. The entire process is fully automated and does not require any manual engagement.