# Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA
## 2 ECC Background over \(GF(2^{m})\)
Line one of Algorithm 1 specifies the initializations or conversions from affine to projective coordinates. As our implemented modular operators (adder, square and multiplier) require one clock cycle for one modular operation computation, 5 clock cycles are required for affine to projective conversions. * _Point multiplication computation (PMC)_. A for loop in Algorithm 1 defines the PM computation in Lopez Dahab projective coordinate system. The instructions mentioned in the if and else statements are for PA and PD operations. More precisely, from \(Inst_{1}\) to \(Inst_{7}\) are for PA and \(Inst_{8}\) to \(Inst_{14}\) are for PD. The switching between if and else statements relies on the value of the inspected one-bit scalar multiplier \(k\). A total of fourteen instructions are concerned with PA and PD computations. Therefore, to implement the fourteen instructions, our design takes \(14\times(m-2)\) clock cycles, where \(m\) is the size of a secret key (i.e., 571). * _Generating output (GOP)_. Algorithm 1 produces \(x\) and \(y\) coordinates of a resultant point \(Q\) as an output. Therefore, the statements in the last two lines in Algorithm 1 are for generating the \(x_{q}\) and \(y_{q}\) coordinates of a final point \(Q\). This stage is (also) known as reconversions from Lopez Dahab projective to affine coordinates. As observed in the last two lines of Algorithm 1, two modular inverse operations and some addition and multiplication operations are required to compute. As described earlier in this paper, our design requires 583 cycles for one inverse computation. So, we need 1166 clock cycles for two inverse operations. Moreover, our architecture takes 28 clock cycles for other addition and multiplication operations to compute. Hence, \(1166+28\) clock cycles are required for projective to affine conversions. Consequently, the total clock cycles for one PM computation using Algorithm 1 over \(GF(2^{571})\) is 9165 (and can be calculated using cycles for \(INT\) + cycles for \(PMC\) + cycles for \(GOP\)). ## 4 Results and Comparison

The implementation results and our comparison to the state-of-the-art are given in Sections 4.1 and 4.2, respectively. ### Results

Our large-field size design over \(GF(2^{571})\) is implemented in Verilog HDL using a Vivado IDE tool. We have selected the coordinates of the initial point \(P\) and a curve constant value \(b\) as inputs from NIST standardized document [9]. For Xilinx Virtex-6 and Virtex-7 FPGA devices, we have provided implementation results in Table 2 after place-and-route level. Columns one to three of Table 2 provide the hardware cost in slices, look-up-tables (LUTs) and flip-flops (FFs). The computation cost (of our proposed design) in terms of clock cycles, frequency (Freq in MHz), and latency (in \(\upmu\)s) are given in columns four to six. We have demonstrated the throughput values in column seven. We have computed a ratio of throughput over slices to show the performance of our proposed design and the calculated values are provided in the last column of Table 2. We have collected slices, LUTs, FFs and frequency values from the synthesis tool (i.e., Vivado IDE). We have already described the clock cycles calculation in Section 3.4. Moreover, we have calculated latency and throughput values from Equation (4) and Equation (5), respectively. Finally, we have calculated the throughput over area results using Equation (6). It is essential to mention that we have used slices as an area in Equation (6). \[Latency\;(\mu s)=\frac{Clock\;cycles}{Clock\;frequency\;(MHz)} \tag{4}\]

\[Throughput=\frac{1}{Latency\;(\mu s)}=\frac{10^{6}}{Latency} \tag{5}\]

\[Performance\;metric\;(PM)=\frac{Throughput}{Area} \tag{6}\]

Our proposed architecture on Xilinx Virtex-7 FPGA utilizes 1.07x (ratio of 6107 over 5683), 1.05x (ratio of 15,216 over 14,356) and 1.02x (ratio of 6103 over 5961) lower slices, LUTs and FFs as compared to Virtex-6 FPGA implementation.