## 4 Simulations and Discussions
As shown in Figure 5b, when the state of \(\mathrm{M_{data}}\) is P, the output value Q during the recovery process is \"0\", which is consistent with the expected result. The simulation results in Figure 5 demonstrate that the VC-DFF can successfully operate in the modes, achieving data recovery and normal reading and writing processes. Figure 6 presents the transient simulation waveforms of the VC-SRFF. In the normal mode, the VC-SRFF functions similarly to the VC-DFF. When S and R are set to different logic levels, and the output terminals Q and QB have two complementary stable states. As shown in Figure 6, when S = \"0\" and R = \"1\", a SOT write current flows from \(\mathrm{M_{ref}}\) to \(\mathrm{M_{data}}\). The write operation is achieved by switching the magnetization of \(\mathrm{M_{ref}}\) and \(\mathrm{M_{data}}\) to AP and P, respectively. When S = \"1\" and R = \"0\", a SOT write current flows from \(\mathrm{M_{ref}}\) to \(\mathrm{M_{data}}\). The magnetizations of \(\mathrm{M_{ref}}\) and \(\mathrm{M_{data}}\) are switched to P and AP states, respectively. During the read processes, the output result Q is not affected by changes in S and R. The value of Q is the data stored in \(\mathrm{M_{data}}\) after the last write operation. The operation in the data recovery phase is the same as the operation process in VC-DFF, which essentially involves reading the data stored in MTJs. The simulation results in Figure 6 show that VC-SRFF works successfully in all modes. Table 2 compares the performance of our work with the state-of-the-art NVFFs [8; 12; 19; 24]. As can be seen, ref. [8] has a certain area advantage, but it has a large read-write power consumption. However, the total number of devices in this paper represents the number of all devices involved in the work, while the number of devices in the STT-based NVFF [12; 24] and the SOT-based NVFF [8; 19] does not include the number of devices in the peripheral state detection circuit. Compared to the STT-based NVFF [12; 24], our work can achieve up to a 20\(\times\) (1.4\(\times\)) reduction in write latency. Moreover, in terms of write power consumption, our work shows up to a 718\(\times\) (7.2\(\times\)) and 18.7\(\times\) (31\(\times\)) improvement compared to the STT-based NVFF [12; 24] and the SOT-based NVFF [8; 19], respectively. Additionally, the recovery power consumption of the STT-based NVFF [8; 12] is 1.54 (3.47) times that of our work, while the SOT-based NVFF is about twice that of our work. The main reason for the significant reduction in write and recovery power consumption is the complexity of the circuit architecture. Specifically, the STT-based NVFF not only requires  
Figure 6: Transient simulation waveforms of our VC-SRFF: (a) simulation results when the initial state of Mdata is AP; (b) simulation results when the initial state of Mdata is P.  
an additional system power state detection circuit for backup and restore operations but also additional write circuits and complex control logic gates for data-writing operations. In comparison, the SOT-based NVFF only requires a system power state detection circuit, resulting in a simpler circuit design. The VC-FFs we propose do not require additional peripheral circuits. Therefore, among these three designs, our work exhibits the simplest structure and best performance. Although VC-FFs provide very low read and write power consumption for nonvolatile devices in normal operating mode, additional read and write operations inevitably result in unnecessary power consumption. In order to reduce the power consumption, we will optimize the read and write operation mode of the FF in future work.