# An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields
## 2 Lopez-Dahab Projective Form of ECC over \(GF(2^{m})\)
* Loading the values of constant and a scalar multiplier: we use \(ctrl_{ext}\) = 100 and \(ctrl_{ext}\) = 101 to load the curve constant parameter and a scalar multiplier on a 571-_bit dbuff_ using one-bit \(din\)-\(ext\) signal. * Collecting bits of final point : we use \(ctrl_{ext}\) = 110 and \(ctrl_{ext}\) = 111 to collect the bits of \(x\) and \(y\) components of the final point \(Q\), respectively. After loading each input parameter and the corresponding address, the IOLC unit passes data and address using \(data\) and \(addr\) signals to the control unit of the PM-core. Subsequently, the data is written on the used memory block. Similarly, the next input parameter is written on the memory block. Once writing all input parameters on the memory block is finished, the IOLC unit generates the \(start\) signal for the control unit of the PM-core to start computations. After computing the PM operation, the control unit of

Figure 1: Block diagram of the proposed hardware accelerator architecture. the PM-core corresponds to the IOLC block by setting a _done_ signal, as shown in Figure 1. Based on this _done_ signal, the IOLC unit communicates to the control unit of the PM-core for reading final data from the memory block. Once reading the resultant data from the memory unit is finished, the IOLC unit generates a one-bit _done-f_ signal. It ensures that the final results have been read. It is important to note that we must load the \(x\), \(y\) components of the starting point \(P\), the constant \(b\), and a secret key in a memory unit. All these input parameters need to load in a sequential style, one after another. This serial data loading is the initialization and needs \((4\times m)+4\) clock cycles. Out of \((4\times m)+4\) cycles, \(4\times m\) cycles are needed to load four input parameters (\(x_{p}\), \(y_{p}\), \(b\) and secret key \(k\)) serially. Moreover, an additional four cycles are needed to reset the 571-_bit_\(dbuff\) after loading each corresponding 571-bit value into the buffer. Similarly, we also need to load the corresponding read/write address, which takes five clock cycles; four for the address and an additional cycle to reset the 4-_bit_\(abuff\). This (serial data loading to the memory unit) enables the flexibility feature of our proposed accelerator design. Therefore, different ECC parameters can be loaded into our design for PM computation. The next subsection elaborates on the PM-core of the proposed accelerator architecture. ### PM-Core

As shown in Figure 1, the PM-core has three main components. The first component is the memory unit that stores the initial, intermediate, and end results during the computation of the PM operation in ECC. The second unit is the arithmetic unit (AU) that executes the arithmetic operations required for PM computation, including addition, squaring, multiplication, reduction, and inversion. Finally, the last unit is the control unit (CU) which plays a crucial role in the accelerator's operation by generating the control signals necessary for efficient control functionalities. Moreover, it communicates to the IOLC unit for read/write data on the memory block and (also for) other essential controls. In addition, the CU block of our PM-core ensures proper synchronization and coordination between the memory unit, an arithmetic unit, and other components, enabling the accelerator to execute the PM operation effectively. An in-depth discussion of the three components of the PM-core is given in the following subsections. #### 3.2.1 Memory Unit (MU)

The data memory in our proposed design is implemented as an array of registers as shown in Figure 1. It has a size of \(11\times m\). Here, the number 11 depicts the number of addresses. The variable \(m\) denotes the number of bits stored in each address. The number of locations in the memory unit varies depending on the specific value of \(m\). This value can be 163, 233, 283, 409, or 571. For example, if the accelerator is designed for \(GF(2^{163})\), the memory size would be \(11\times 163\).