# A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis
## 1 Introduction  
The advancement of 3D IC technology presents a promising solution for the continuation of \"more Moore's law\" in the future. However, a major challenge in the development of 3D IC technology is the establishment of reliable and high-performance 3D circuits and systems. The implementation of 3D technology helps alleviate problems associated with interconnection delays by reducing gate delays and increasing interconnections through the use of shorter wires. These shorter wires help reduce the average load capacitance and resistance, resulting in a decrease in the number of repeaters required to regenerate the signal on long wires [1, 2]. Vertical stacking of ICs has become a viable option in the semiconductor industry for reducing wirelength and integration. For example, stackingDRAM on top of processor cores helps to increase CPU-DRAM bandwidth, while stacking processor cores vertically can increase inter-core communication bandwidth. To enable vertical stacking, vertical interconnects are required, with the most common type being the silicon through-hole [3; 4; 5]. Three-dimensional integration refers to a configuration and technique used to vertically integrate multiple chips by means of wafer bonding and electrical interconnections using through-silicon vias (TSVs, Figure 1). The idea of utilizing hollow vias for signal transmission through a wafer was first proposed by [PERSON] in 1958. Subsequently, in 1964, IBM explicitly introduced the concept of etching and metal deposition for TSV fabrication. In 1969, IBM further proposed a 3D integration method employing double-sided KOH etching and metal deposition to create TSVs, with metal solder employed for chip bonding. However, it was not until 1984 that the stacking of CMOS chips in a three-dimensional configuration was achieved. The introduction of Bosch deep reactive ion etching (DRIE) technology in the mid-1990s made it possible to etch vertical and deep through-holes in silicon wafers, enabling the fabrication of TSVs with high aspect ratios filled with tungsten (W) or polysilicon conductors by the end of the last century. Since the year 2000, copper (Cu) plating in deep via holes has emerged as the primary technology for filling high aspect ratio TSVs [6; 7; 8]. The goal of electroplating is low stress, free of holes and voids during TSV fabrication [9]. TSV technology enables high-density interconnection in the \(z\)-axis direction, which significantly reduces the three-dimensional size of the microsystem. The shortened interconnect length also results in lower chip power consumption, improves data propagation speed, reduces signal delay, and improves the electrical interconnection reliability of the system. As a result, TSV technology is crucial to the success of 3D IC technology, and it has the potential to revolutionize the semiconductor industry. As technology advances and systems are designed to improve their performance, the physical size of the channels continues to decrease. In the case of through-silicon via (TSV) technology, the diameter of the via has reduced to less than 10 \(\upmu\)m, while the  
Figure 1: (**a**) Progression of packaging technology; (**b**) roadmap for TSV diameter and aspect ratio; (**c**) 3D chips; (**d**) TSV package samples (adapted from [6; 10; 11; 12]). pitches have reduced to tens of microns. This miniaturization of TSVs has resulted in the increase in I/Os to tens of thousands of orders of magnitude for wide bandwidth data transmission. However, such small structures are highly susceptible to defects, which can negatively impact the performance of the integrated circuit. To achieve a highly accurate manufacturing process for these small structures, it is essential to understand the root causes of defects in TSVs. A common type of TSV defect is a void, which can occur during the deposition of the copper layer or the chemical mechanical planarization (CMP) process. The formation of a void in the TSV can result in increased electrical resistance, decreased mechanical strength, and even device failure.