## 3 Proposed Hardware Architecture
### Arithmetic Logic Unit
#### 3.3.2 Radix-4 Multiplier  
Radix-4 serial multiplier architecture employs [PERSON]'s recording technique as shown in Figure 2. The primary objective is to multiply two numbers efficiently by a systematic process of addition and shifting. The multiplier operand is denoted as \"y\". The operand is sequentially transferred into a shift register, bit by bit, with each clock cycle. This sequential shifting allows for the processing of each bit of the multiplier. The Booth recoding circuit comes into play during this process. It checks not only the current bit but also the subsequent two bits of the multiplier operand (\"y\"). Based on this evaluation, it determines which of the five possible values to output from the multiplexer (MUX_X). These values include 0, x, 2x, -x, or -2x. \"x\" represents the second multiplier operand.  
Following the Booth recoding step, the output of mux is sign extended. The objective is to match the width of the multiplicand operand. The sign extension ensures the handling of both positive and negative numbers. The sign-extended output from the Booth recoding circuit is then added to the accumulator. The initial value of the accumulator is zero. Subsequently, the result of addition is subject to a right shift by two bits. This particular right shift is instrumental because the Booth recoding technique effectively reduces the  
\begin{table}
\begin{tabular}{l l l l} \hline \hline
**Clock Cycles** & \(Instr_{i}\) & **Addition Law (15 \(\times\)\(m\) Storage Elements)** &
\begin{tabular}{l} **Proposed Simplified Formulations (11 \(\times\)\(m\)** \\ Storage Elements)** \\ \end{tabular} \\ \hline
1 & \(Instr_{1}\) & \(A=W_{1}\times Z_{1}\) & \(A=W_{1}\times Z_{1}\) \\
2 & \(Instr_{2}\) & \(B=W_{1}\times W_{2}\) & \(B=W_{1}\times W_{2}\) \\
3 & \(Instr_{3}\) & \(C=Z_{1}\times Z_{2}\) & \(C=Z_{1}\times Z_{2}\) \\
4 & \(Instr_{4}\) & \(W_{d}=A\times A\) & \(D=A\times A\) \\
5 & \(Instr_{5}\) & \(T_{1}=e_{1}\times W_{1}\) & \(E=e_{1}\times W_{1}\) \\
6 & \(Instr_{6}\) & \(T_{2}=T_{1}+Z_{1}\) & \(F=E+Z_{1}\) \\
7 & \(Instr_{7}\) & \(T_{3}=T_{2}\times T2\) & merged with \(instr_{8}\) \\
8 & \(Instr_{8}\) & \(Z_{d}=T_{3}\times T_{3}\) & \(A=(F\times F)^{2}\) \\
9 & \(Instr_{9}\) & \(T_{1}=e_{2}\times B\) & \(E=e_{2}\times B\) \\
10 & \(Instr_{10}\) & \(T_{2}=T_{1}+C\) & - \\
11 & \(Instr_{11}\) & \(Z_{d}=T_{2}\times T_{2}\) & \(F=(E+C)  
number of partial products by half. Consequently, the result of the multiplication becomes effectively twice as wide as the original multiplicand multiplier operands.  
The aforementioned cycle of operations, encompassing Booth recoding, sign extension, addition, and right shift, persists until every bit of the multiplier operand is systematically shifted into the shift register. Upon the completion of this comprehensive process, the accumulator securely contains the final product of the multiplication. Radix-4 serial multiplier architecture, complemented by the Booth recoding technique, stands as an efficient methodology for multiplication, particularly in scenarios where both computational speed and optimized power consumption are paramount considerations.