# A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA
## 5 Implementation Results and Comparison
### Implementation Results  
Table 3 shows the implementation results of our proposed unified architecture. The first column shows the implemented ECC curves (Weierstrass, Edward, and Huff). The second column represents the implementation platform (the name of a particular device used in the experiments). The consumed area information is generally provided in three  
different notations. These notations are slices (column three), look-up tables (represented as LUTs and shown in column four), and flip-flops (represented as FFs and shown in column five). The circuit frequency (Freq), total cycle counts, information about latency, and the achieved throughput (represented as Thrpt) results are available in columns six to nine of Table 3. To evaluate the performance of our unified architecture, we built a figure of merit (FoM); related values are available in the last column. Note that the slices, LUTs, and FFs values were taken directly from the Vivado synthesis tool. We already described the total cycle counts for different ECC curves (Weierstrass, Edward, and Huff) in Section 4.5. Latency specifies the time needed to execute one PM operation, and it can be calculated using Equation (5). The throughput values can be calculated using Equation (6). Finally, dividing the achieved throughput by the total number of slices provides the value of FoM (Equation (7)). \[Latency\;(\mu s)=\frac{Clock\;cycles}{Clock\;frequency\;(MHz)} \tag{5}\]  
\[Throughput\;(Thrpt)=\frac{1}{Latency\;(\mu s)}=\frac{10^{6}}{Latency} \tag{6}\]  
\[FoM=\frac{Throughput\;(Thrpt)}{Area\;(Slices)} \tag{7}\]  
As can be seen in Table 3, the area utilization of our proposed unified accelerator architecture increases when driving from Virtex-6 to Virtex-7 FPGA devices. The reason is the technology advancement, as Virtex-6 is produced on 40 nm process technology, while Virtex-7 is built on 28 nm technology. Moreover, column six of Table 3 reveals that the circuit frequency also increases when we change the implementation device from Virtex-6 to modern Virtex-7 FPGA. As for the clock cycles used for comparison, the Edward curve requires the lower cycle count of 3472, compared with the Weierstrass (3607) and Huff (8913) curves. This is normally due to the number of PA and PD computation instructions. As shown in columns two to four of Table 2, the instructions for PA and PD computations for Weierstrass, Edward, and Huff curves are fourteen, fourteen, and thirty-seven. Similarly, the execution cost (latency) of Weierstrass, Edward, and Huff curves is obtained using Equation (5). Subsequently, the calculated latency values for Weierstrass, Edward, and Huff curves on the Virtex-6 device are 14.60, 14.05, and 36.08 us. The maximum circuit frequency achievement for Virtex-7 FPGA ensures a shorter computation time. Hence, on Virtex-7 FPGA, the calculated latency values for Weierstrass, Edward, and Huff curves are 12.26, 11.80, and 30.31 us. Our Virtex-7 implementation of the unified design (for implementing Weierstrass, Edward, and Huff curves) is 1.19x faster than the Virtex-6 implementation. Similarly, our Virtex-7 implementation of the unified accelerator architecture for implementing Weierstrass, Edward, and Huff curves results in a 0.83x improvement compared with the Virtex-6 implementation. \begin{table}
\begin{tabular}{l l l l l l l l l l} \hline \hline
**ECC Curve** & **Technology** & **Slices** & **LUTs** & **FFs** & **Freq (MHz)** & **Cycles** & **Lat (\#s)** & **Thrpt** & **FoM** \\ \hline [PERSON] & & & & & & 3607 & 14.60 & 68.49 kbps & 11.21 \\ [PERSON] & Virtex-6 (40 nm) & 6109 & 19,869 & 3421 & 246.738 \(\approx\) 247 & 3472 & 14.05 & 71.17 kbps & 11.65 \\ Huff & & & & & & 8913 & 36.08 & 27.71 kbps & 4.53 \\ \hline [PERSON] & & & & & & 3607 & 12.26 & 81.56 kbps & 10.98 \\ [PERSON] & Virtex-7 (28 nm) & 7423 & 21,917 & 3824 & 293.671 \(\approx\) 294 & 3472 & 11.80 & 84.74 kbps & 11.41 \\ Huff & & & & & & 8913 & 30.31 & 32.99 kbps & 4.44 \\ \hline \hline \end{tabular}
\end{table}