# A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers
###### Abstract  
A high-speed serial interface is the core IP of a high-performance computer, data center and interconnection network; its bandwidth and bit error performance restrict the development of the system. With the evolution of high-speed serial interface line rates from 56 G to 112 G in high-end information systems, their bit errors increase sharply, limiting system performance. In order to solve the high-bit-error problem of the 112 Gb/s high-speed serial interface, this paper proposes a low-error Duo-binary PAM4 (DB-PAM) receive equalization technology. This technology utilizes the Duo-binary (DB) signal in which the channel and the transceiving equalizer work together to realize the low-error reception of the 112 Gb/s signal in the high-attenuation channel. To solve the problem of difficulty in generating high-speed DB-PAM4 signals and the complex adjustment of equalization parameters, this paper proposes a two-step progressive equalization technique. In the first step, the technology transmits not-return-to-zero (NRZ) signals at the transmitter (TX) and generates a Duo-binary (DB) signal path at the receiver using the least mean square error (LMS) algorithm. In the second step, the technology sends a precode-PAM4 (pre-PAM4) signal at TX; at the receiving end, the adaptive equalization algorithm is used to adjust the DSP equalization parameters to generate the optimal equalization parameters of the DB-PAM4 signal. This paper uses Cadence's AMS simulation platform to verify the receive equalizer of DB-PAM4. Simulation results show: when a 112 Gb/s pre-PAM4 signal passes through the 35 dB@28 GHz channel, the receiver (RX) utilizes the adaptive equalizer to generate a 112 Gb/s DB-PAM4 signal, and the receiver bit error rate (BER) is less than 3e-9. digital signal process (DSP); least mean square (LMS) algorithm; DB-PAM4; BER Article  
[PERSON], [PERSON], [PERSON], [PERSON] Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers  
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and differences in channel materials and lengths, the equalizer usually uses self-adaptive algorithms to compensate for the attenuation of the different frequency components of the signal. In the literature [3], periodic calibration is performed by means of a preset protocol to update the DFE coefficients. In this way, although the tap coefficient of the equalizer can be converged to the optimum, the transmission efficiency of the signal is reduced due to the periodic transmission of redundant signals. In the literature [4], in order to reduce the equalization intensity, a 5-tap feedforward equalizer of the transmitter is used in combination with the channel to generate a duobinary signal. However, a data-driven feed-forward equalizer (FFE) at the TX does not help to reduce jitter amplification. Moreover, performing adaptive equalization at the transmitting end requires additional algorithms to solve the synchronization problem at the transmitting and receiving ends. In order to meet the requirements of fast and accurate equalization of high-loss channels, the Serdes equalizer designed in this paper adopts the method of combining digital and analog equalization. Analog equalization is carried out by a two-stage continuous-time linear equalizer (CTLE), which provides equalization and gain just below the Nyquist frequency. This equalization combined with partial channel loss can be used for DB signal generation while reducing the performance requirements of the subsequent analog-to-digital converter (ADC). The data sampled by the 64-channel ADC is sent to the 16-tap FFE and the 1-tap pre-decision decision feedback equalizer (DFE) for adaptive equalization processing, which further improves the signal quality of the receiver. Compared with digital DFE, the realization of digital FFE equalization is simple and compact, and the requirements for timing are more flexible.