# _Ku_-Band CMOS Power Amplifier with Three-Stack Power Stage to Enhance Output Power and Efficiency
## 5 Measurement Results  
A transformer was used for the matching network between the driver and power stages, and a supply voltage of the driver stage was applied through a center tab of the transformer. The designed driver stage used a gate voltage of 0.4 V for the Class-AB operation, and the gate voltages of V\({}_{\rm G,PW,1}\), V\({}_{\rm G,PW,2}\), and V\({}_{\rm G,PW,3}\) were 0.3 V, 1.7 V, and 2.6 V, respectively. The supply voltages of the driver and power stages were 1.0 V and 2.6 V, respectively. Measurements were carried out at room temperature.  
Figure 10 is a chip photograph of the designed power amplifier. The total size, including the test pad, is 0.725 \(\times\) 0.500 mm\({}^{2}\). DC bias was applied through boning wires, and a GSG probe was used for the RF signals. Figure 11 shows the measured \(S\)-parameters of the designed power amplifier. Because the power stage was designed with the power matching technique, the measured value of S\({}_{22}\) was higher than that of S\({}_{11}\). Due to parasitic effects that were not predicted by electromagnetic (EM) simulation, compared with the simulation results, the measured optimum frequency was downshifted.  
Figure 8: Simulation results: current consumptions of driver and power stages.  
Figure 9: Simulation results: P\({}_{\rm sat}\), P1 dB, PAE, and gain depending on frequency.  
Figure 12 shows the power gain and power-added efficiency (PAE) according to the output power at the center frequency of 15 GHz. The measured Psat is 22.1 dBm, and the maximum PAE is 17.2%. Figure 13 shows the measured current at the driver and power stages. As the supply voltage for the driver stage was 1.0 V, the dc power consumption in the driver stage was minimized. In the process of optimizing the dc bias to obtain a high P1 dB during measurement, the amount of dc current in the power stage increased compared with the simulation. Figure 14 shows measured Psat, gain, P1 dB, and PAE according to frequency. The measured output power and PAE were degraded when compared with the simulation results shown in Figure 9. It is predicted that this is due to the lack of accuracy of the EM simulation and the dummy patterns to satisfy the design rule. In particular, as the bias values in the measurement were optimized to ensure P1 dB, the degradation of the measured PAE increased compared with the simulation. At the 15 GHz operating frequency, the measured P1 dB compared with the simulation degraded by approximately 0.7 dB, but in the case of PAE, it degraded by approximately 7.3%.  
Table 1 shows a comparison of the performance of the designed power amplifier with that of state-of-the-art CMOS power amplifiers. As shown in Table 1, the PAE itself of the proposed power amplifier seems to be somewhat low. However, it should be considered that P1 dB, Psat, and PAE are trade-offs with each other. In particular, in the case of a power amplifier composed of only a power stage, the efficiency decreases when considering the design of an essential driver stage. An additional output power improvement can be expected if an additional power combining technique, such as reference [13], is applied to the power stage.  
Figure 11: Measurement results: S-parameters.  
Figure 10: Photograph of the designed CMOS power amplifier (0.725 \(\times\) 0.55 mm\({}^{2}\)).  
Figure 14: Measurement results: P\({}_{\rm sat}\), PIdB, PAE, and gain depending on frequency.  
Figure 12: Measurement results: gain and PAE according to output power.  
Figure 13: Measurement results: current consumptions of driver and power stages.