## 2 Voltage Differencing Extra X Current Conveyor (VD-EXCCII)  
The proposed Voltage Differencing Extra X current conveyor (VD-EXCCII) is derived by connecting extra X second generation current conveyor (EXCCII) [42] and operational transconductance amplifier (OTA). The first stage comprises of OTA followed by the CCII with two current input terminals. The developed active element has characteristics of CCII and tunable OTA in one structure. The voltage-current (V-I) characteristics of the developed VD-EXCCII are presented in Equations (1)-(4) and the block diagram is presented in Figure 1.  
\[I_{\text{W}}=I_{\text{WC+}}=-I_{\text{WC-}}=g_{m1}(V_{P}-V_{N}) \tag{1}\]  
\[V_{XP}=V_{\text{XN}}=V_{W} \tag{2}\]  
\[I_{XP}=I_{ZP+}=-I_{ZP-} \tag{3}\]  
\[I_{\text{XN}}=I_{ZN+}=-I_{ZN-} \tag{4}\]  
The CMOS implementation of VD-EXCCII is given in Figure 2. The first stage consists of OTA MOS transistors (M1-M14). The output current of the transconductor depends on the voltage difference \((V_{P}-V_{N})\). Assuming that all transistors are operating in saturation region and the transistors (M1-M2) have equal width to length ratio, the output current is given by:  
\[I_{\text{W}}=I_{\text{WC+}}=-I_{\text{WC-}}=g_{m1}(V_{P}-V_{N})=\left(\sqrt{2I _{\text{Bias}}K_{i}}\right)(V_{P}-V_{N}) \tag{5}\]  
where the transconductance parameter \(K_{i}=\mu C_{ox}\dfrac{W}{2L}\), (\(i=1,2\)), \(W\) is the effective channel width, \(L\) is the effective length of the channel, \(C_{ox}\) is the gate oxide capacitance per unit area and \(\mu\) is the carrier mobility. The second stage is made up of hybrid voltage and current followers (M15-M44). The voltage developed at node W is transferred to nodes \(X_{P}\) and \(X_{N}\). In the same way the input current from \(X_{P}\) node is transferred to \(Z_{P+}\) and \(Z_{P-}\). Furthermore, the input current from \(X_{N}\) node is transferred to \(Z_{N+}\) and \(Z_{N-}\). The current flowing in the \(Z_{N}\) and \(Z_{P}\) terminals are independent of each other. The class AB output stage is utilized in the output stage, as it is suitable for low voltage operation and better dynamic range [2]. The current and voltage reference circuits available in the literature [43] can be employed to generate the \(I_{Bias}\) and \(V_{Bias}\) for the circuit. Figure 1: Block diagram of VD-EXCCII. Figure 2: CMOS implementation of VD-EXCCI. The small signal analysis yields the expression relating \(V_{W},~{}V_{XP}\) and \(V_{XN}\). The analysis is carried out for the differential stage formed by transistors (M\({}_{15}\)-M\({}_{24}\), M\({}_{39}\)-M\({}_{42}\)). The voltage transfer ratio between the \(W\) and \(X_{p}\) node can be derived as given in Equation (6). \[\alpha_{P}=\frac{V_{XP}}{V_{W}}=\frac{\frac{r_{039}r_{040}}{r_{039}+r_{040}}(g_ {m39}+g_{m40})\frac{r_{0p}}{2}g_{m18}}{\frac{r_{039}r_{040}}{r_{039}+r_{040}}(g_ {m39}+g_{m40})\frac{r_{0p}}{2}g_{m17}+1}\cong\frac{g_{m18}}{g_{m17}} \tag{6}\]  
where \(r_{0p}=r_{017}//r_{021}\), \(r_{0}\) is the output resistance of the MOS transistor and \(g_{mi}\) is the transconductance of the MOS transistor \(M_{i}\). Similarly, the voltage transfer gain \(\alpha_{N}\) is computed as:  
\[I_{\text{W}}=I_{\text{WC+}}=-I_{\text{WC-}}=g_{m1}(V_{P}-V_{N}) \tag{1}\]0  
The current transfer ratios are derived as given in Equations (8) and (9):  
\[I_{\text{W}}=I_{\text{WC+}}=-I_{\text{WC-}}=g_{m1}(V_{P}-V_{N}) \tag{1}\]1  
\[I_{\text{W}}=I_{\text{WC+}}=-I_{\text{WC-}}=g_{m1}(V_{P}-V_{N}) \tag{1}\]2  
\[I_{\text{W}}=I_{\text{WC+}}=-I_{\text{WC-}}=g_{m1}(V_{P}-V_{N}) \tag{1}\]3  
The terminal resistance of \(X_{N}\) and \(X_{p}\) terminals is calculated as given in Equations (10) and (11). The \(Z_{P+}\), \(Z_{N+}\) and \(W_{C+}\) resistance are presented in Equations (12)-(14). \[I_{\text{W}}=I_{\text{WC+}}=-I_{\text{WC-}}=g_{m1}(V_{P}-V_{N}) \tag{1}\]4  
\[I_{\text{W}}=I_{\text{WC+}}=-I_{\text{WC-}}=g_{m1}(V_{P}-V_{N}) \tag{1}\]5  
where \(r_{0p}=r_{017}//r_{021}\) and \(r_{0n}=r_{016}/r_{020}\).