# A Real Time and Lossless Encoding Scheme for Patch Electrocardiogram Monitors
## 5 Conclusions  
Wearable ECG monitors do not provide sufficient computing power to detect critical P, QRS, and T events to allow a reliable cardiovascular assessment [37; 38; 39; 40; 41; 42]. The proposed encoding uses a basic  
Figure 12: Xilinx ML505 field-programmable gate array (FPGA) evaluation board. Figure 13: FPGA implementation. \begin{table}
\begin{tabular}{c c c c} \hline \hline  & [35] & [36] & **Proposed** \\ \hline
**Compress Rate** & 1.9 & 2.43 & 2.11 \\ \hline
**Operation Frequency** & 100M Hz & 100M Hz & 360 Hz \\ \hline
**Gate counts (K)** & 13.4 & 3.57 & 1.16 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Compression operation clock. logic component, arithmetic and logic unit subtraction, rotation, comparator, and counter, and stores original real-time and lossless data for processing in clinical contexts. It is used to minimize the physical size and power consumption of a unit, and the encoding scheme offers superior efficiency to comparable software solutions. Since this scheme rotates only one bit, a simple circuit switch can be used to replace the rotating arithmetic logic unit (ALU). In addition, because each module is triggered by the previous one, the pipeline architecture achieves real-time ECG data encoding, and the scheme can be integrated into a wearable ECG monitor or PEM system. Replacing wireless modules with local storage in wearable ECG monitors (e.g., Holter device or PEM) reduces the overall footprint, power consumption, and battery weight. Existing PEM ASICs are suitable for implementing this design to minimize equipment size and power consumption while enhancing user convenience. The designed scheme detects significant QRS complexes in a normal ECG signal. MIT records 100 and 103 have the best CR of approximately 2.1, whereas MIT 107 has the worst (i.e., 1.5), because it contains abnormal signals such as premature ventricular contractions and pauses. However, when high-bit resolution was split into five bits for MIT recording 107, both the CR and heartbeat detection correction increased. Despite its poor performance with abnormal ECG signals, the proposed approach can be used for Holter or PEM-based health care devices for occasional CVD assessment without data loss. FPGA was used to compress real ECG data from an ECG generator with a high sampling rate, and has reached a high CR (2.7 when a five-KHz sampling rate is used), as shown in Figure 14. This result confirms that an ADC-ready signal can be used as an operation clock when this scheme is implemented on a chip. However, the actual performance did not meet expectations in dynamic-block mode. With an eight-bit high-bit resolution and a sampling rate of 360 Hz, the longest plate period of one heartbeat has 320 values for non-QRS segmentation, and it has the same storage requirements for the end tag (zero, zero) and zero encoding (zero and number). Dynamic-block mode could provide excellent performance with a higher data sampling rate or more high-bit resolution with a long continual zero values. MIT/BIH arrhythmia provides Physikalisch-Technische Bundesanstalt (PTB) databases with a one-kHz sampling rate and 16 bits of raw data resolution. However, this encoding scheme doesn't archive expected performance; the CR is only 1.98 because of eight high-bit resolutions and 8 eight high-bit resolutions. Figure 15 shows the MIT s0010_re probability of occurrence of each distinct symbol between the ECG (original) volume and delta volume variance. However, this record has high resolution, but the plate period needs eight bits in order to be present. Then, the maximal CR of  
Figure 14: FPGA compresses real ECG data. s0010_re is restricted to the ratio of high bits and low bits. In fact, although MIT s0010_re has a 16-bit resolution, it still only uses nine bits to record data. The rough heartbeat rate detection feature of dynamic-block mode, which has a lower CR than that of fixed-block mode, could be used in medic alert applications.