# Design and Signal-Decoding Test Verification of Dual-Channel Round Inductsyn Decoding Circuit
## 3 Decoding-Circuit Hardware Design  
### Hardware Architecture of Decoding Circuit  
The overall hardware architecture diagram of the decoding circuit is shown in Figure 3. The paper selects ADI's RDC decoding chip AD2S1210 as the core decoding chip of the decoding circuit. Similar to the widely used AD2S80 chip, it is based on the Type-II tracking loop principle and is commonly used in resolver systems to convert the rotor's angular  
Figure 1: Diagram of the dual-channel round inductsyn.  
Figure 2: Electrical schematic diagram of the dual-channel round inductsyn.  
position into digital data. This digital data are then sent to the system microprocessor to decode the angle position information. Compared to the AD2S80, the AD2S1210 has a smaller size and a more simplified peripheral circuit configuration. It is powered by a single +5 V power supply instead of dual power supplies. Additionally, when configuring different resolution modes, only adjusting the chip's register configuration is sufficient; no need to modify the circuit hardware. This greatly simplifies the circuit design and debugging work.  
The JGX120/360 dual-channel round inductsyn developed by Changzhou Weinengda Precision Machinery Co., Ltd., which is used in this paper, is a dual-channel round inductsyn with one excitation input and two channel-induced signal outputs. To achieve synchronized decoding for the dual-channel round inductsyn, as each AD2S1210 chip can only take one set of sine and cosine differential signals, the paper adopts a parallel connection method where two AD2S1210 chips share a common clock signal. One chip is selected for outputting the excitation signal, while the output pin of the other chip remains floating. Each of the two AD2S1210 chips decodes the position information of the coarse and fine channels of the inductsyn and converts it into digital signals. According to the AD2S1210 chip's datasheet, when powered by +5 V, the chip can provide a typical differential excitation signal of 7.2 Vp-p for the round inductsyn. However, the drive capability of this signal may not meet the excitation signal input requirements of the round inductsyn, necessitating power amplification processing. According to the operation manual of the dual-channel round inductsyn, it is known that the range of the sine excitation signal should be between 6 Vp-p and 9 Vp-p, with a frequency around 10 KHz, to be in the optimal working state. Taking the example of an input sine excitation signal of 7.2 Vp-p and 10 KHz, the coarse-channel-induced signal of the round inductsyn was measured at 10 mVp-p and 10 KHz, while the fine-channel-induced signal was measured at 20 mVp-p and 10 KHz.  
Figure 3: Overall hardware connection diagram of the decoding circuit.  
According to the AD2S1210's datasheet, the input range for the sine and cosine differential signals is 2.3 Vp-p to 4.0 Vp-p. Therefore, it is necessary to amplify and filter the original induced signals. After the induced signal passes through the amplifier and filter, it will introduce a certain phase shift. However, as the phase difference between the input signal and excitation signal of the AD2S1210 chip needs to be less than 44\({}^{\circ}\), a phase adjustment should be added to the decoding circuit to correct the signal phase. Based on the above information, the design specifications for the decoding circuit can be summarized as shown in Table 1.