# True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA
## 4 Implementation Results
### Synthesis and Implementation Results
The throughput remains limited to 1.15 Mbps and 1.07 Mbps respectively on Xilinx Spartan-6 FPGA and Intel Cyclone V FPGAs, with a Shannon entropy of 0.997; according to the authors, this entropy cannot be achieved for higher frequency without dedicated post-processing circuits. The works in [32; 33] employed RO as entropy sources. In particular, the authors in [33] incorporated Programmable Delay Lines (PDLs) to generate a large variety of the oscillations and to introduce jitter, achieving high entropy. Even if the achieved entropy is remarkable, the resource utilization is not negligible and moreover the result is highly influenced by the operating frequency, which is a limitation not present in our proposed TRNG. In [35], authors presents another STRs-based implementation. The Bit Rate to resource ratio is much greater than the one presented in [34]; however, it is difficult to further compare them due to the lack of measured entropy. Finally, in [36], authors propose a very competing solution in terms of entropy, complexity and resource usage. The disadvantage here comes from the fact that the sole employment of GaRO makes the oscillator more susceptible to faults respect to the FiGaRO approach [24]. Our work showed a very high throughput with a resource consumption in line with other works, and a high level of entropy per bit. Additionally, our implementation can therefore be adapted to the user needs easily, paying a resource utilization fee linearly with the required level of robustness and the required bandwidth. For what concerns entropy, we recommend to use the 1 FiRO-1 GaRO configuration only for a resource optimized scenario, otherwise since the required hardware is still limited, it is possible to achieve higher entropy with the other two configurations. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline  & **TRNG Type** & **Platform** & **LUTs** & **Registers** & **Bit Rate (Mbps)** & **Entropy** \\ \hline This work & \multirow{2}{*}{FiGaRO} & Intel & \multirow{2}{*}{288} & \multirow{2}{*}{190} & \multirow{2}{*}{400} & \multirow{2}{*}{0.995} \\ (4 Stages, 2 FiRO-2 GaRO) & & & & & & \\ \cline{1-1} \cline{5-7}  & & & & & \\ \hline
[31] & ES & \
\begin{tabular}{c} Xilinx \\ Spartan 6 \\ \end{tabular} & 10 & 5 & 1.15 &
\begin{tabular}{c} 0.997 \\ (Shannon Entropy) \\ \end{tabular} \\ \hline
[32] & RO &
\begin{tabular}{c} Xilinx \\ Virtex 2 \\ \end{tabular} & – & – & 2.5 & 0.97 \\ \hline
[33] & RO—PDLs &
\begin{tabular}{c} Xilinx \\ Spartan-3A \\ \end{tabular} & 528 & 177 & 6 & 0.9993 \\ \hline
[34] & STRs &
\begin{tabular}{c} Xilinx \\ Virtex 6 \\ \end{tabular} & 32 & 48 & 4 & – \\ \hline
[27] & TERO & \
\begin{tabular}{c} Xilinx \\ Artix 7 \\ \end{tabular} & 40 & 29 & 1.91 &
\begin{tabular}{c} 0.9993 \\ (Shannon Entropy) \\ \end{tabular} \\ \hline
[35] & STRs &
\begin{tabular}{c} Xilinx \\ Virtex 6 \\ \end{tabular} & 56 & 19 & 100 & – \\ \hline
[36] & GaRO & \
\begin{tabular}{c} Xilinx \\ Artix 7 \\ \end{tabular} & 50 & 79 & 280 &
\begin{tabular}{c} 0.998 \\ (Shannon Entropy) \\ \end{tabular} \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Comparison among the proposed TRNG with other TRNG implementations on FPGA.