## 2 DC-DC Synchronous Buck Converter
### General Operation  
In the description of the DC-DC synchronous buck converter employing a three-channel topology, detailed operational states are explained. Figure 2 represents only one of the channels, which includes a high-side p-channel metal-oxide-semiconductor (PMOS) transistor \(M_{1}\), a low-side N-channel metal-oxide-semiconductor (NMOS) transistor \(M_{2}\) replacing the conventional diode, the output filter composed of an inductor \(L_{o1}\) and a capacitor \(C_{o}\), and the output load \(R_{o}\). The capacitor and load are common among all three channels, while each channel has individual inductors and transistors. The synchronous buck converter can operate with both positive and negative inductor currents. However, to simplify the analysis and design, only positive inductor currents were considered in the explanation and design. The operation of the converter is explained based on the single-channel representation and it can be described in a sequence of distinct states, each associated with specific transistor activities and voltage conditions. Figure 2 visually represents the topology in each operational state, while Table 3 provides a structured summary of the transistor states and key dynamic parameters across different switching states. * Operational State S1: In the first operational state, the PMOS transistor \(M_{1}\) is turned on, allowing the current to flow from the input through the inductor \(L_{o1}\) to the output, charging the output capacitor \(C_{o}\) and supplying the load \(R_{o}\). During this phase, the NMOS transistor \(M_{2}\) is off, preventing any backflow of current. * Operational State S2: With the PMOS transistor \(M_{1}\) off, the NMOS transistor \(M_{2}\) fully takes over, allowing current to continue flowing through the inductor \(L_{o1}\) to the \begin{table}
\begin{tabular}{c c c} \hline \hline
**Description** & **Symbol** & **Value** \\ \hline Input Voltage & \(V_{dc}\) [V] & 20 \\ Output Voltage & \(V_{o}\) [V] & 12/9/5/3.3 \\ Output Current (per channel) & \(l_{L}\) [mA] & 100 \\ Maximum Power (per channel) & - [W] & 1.3 \\ Peak Efficiency & - & \textgreater{}80\% \\ Switching Frequency & \(f_{s\omega}\) [kHz] & 75 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: DC-DC synchronous buck converter design specifications. output, but now through the NMOS transistor \(M_{2}\). This stage is critical for improving efficiency by reducing power losses that would otherwise occur if a diode were used instead of a synchronous NMOS. * Operational State S3: In this state, both transistors \(M_{1}\) and \(M_{2}\) are turned off if the output voltage reaches the desired level. The energy stored in the inductor and capacitor is used to maintain the output voltage and the current flows through the body diode of transistor \(M_{2}\). This stage serves as a dead time and is always placed between the other two stages to prevent source short circuits. By employing a multi-channel approach, it can significantly enhance the performance of the converter. Each channel operates independently, and by introducing a specific phase shift between their control signals, it can achieve several advantages [35]. In the design, the currents from all three channels are summed at the output, resulting in the desired output current across the load \(R_{o}\). As a result of this summation, the average output current is greater than the average current per channel, and the effective frequency is higher. This configuration helps to evenly distribute the current load and minimize ripple, as the ripple in each individual channel is higher than the overall ripple observed at the output. The aforementioned behavior is assisted by the corresponding gate drive signals, ensuring that the transistors are properly synchronized with a specific phase shift introduced for each channel.