# Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL
## 6 Conclusions and Future Work  
The design of a PLL for the new ESA Spacefibre standard has been presented in this paper. The work was carried out in ADS for the modeling activity and Cadence Virtuoso for the design activity. In particular, the design of a TMR PFD, a CP, and a passive Loop Filter has been presented, starting from an already designed 6.25 GHz rad-hard VCO in 65 nm technology. The modeling activity has shown that the PLL can be completely integrated on-chip, with a Loop Filter area consumption of only 6000 \(\upmu\)m\({}^{2}\). The PLL is able to generate three output signals at 6.25, 3.125, and 1.5625 GHz with a gain margin of 86 dB and phase margins of 50\({}^{\circ}\). The Phase Noise of the PLL, considering the  
Figure 23: Draft floor plan of the test chip.  
Figure 22: Block schematic of the test chip.  
higher frequency output, is below \(-85\) dBc/Hz @ 1 MHz, and hence, it is in line with that of the VCO. The PLL power consumption in the locked state is about 10.24 mW. The PFD/CP is dead-zone free and shows a current matching below 2 uA (5% of the nominal CP's current value) in the worst case of process-temperature corners. Moreover, the PLL is highly immune to SEE on the PFD, while it is able to relock in less than 600 ns for an SEE on the CP. Finally, an area estimation has been done considering also the VCO, resulting in a total area of 0.09 mm\({}^{2}\).  
In Table 2, a comparison with the state-of-the-art rad-hard PLLs is performed. In [15], a CP-PLL in 65 nm technology for high-energy physics is presented. It generates a tunable output frequency in the range of 4.8-6 GHz, which is slightly lower the SpaceFibre standard. As reported in [15], the CP-PLL was not designed to be SEE tolerant; indeed, a simple PFD was used in the PLL loop. Instead, in this work, a TMR PFD was implemented to increase the hardness against SEE. In [13], all the digital logic of the CP-PLL is implemented using a TMR approach, but its low-frequency range is not suitable for SpaceFibre application. In [25], the design of a rad-hard CP-PLL that is able to generate an output frequency in the range 1.17-3.16 GHz is reported. It bases its radiation hardness on the use of a Silicon On Sapphire. Indeed, the SOS having a resistive sapphire in the substrate reduces the creation of electron-hole pairs and their migration in the device bulk in the case of energetic ion strikes. An example of radiation hardness improvement achieved using a different technology is presented also in [26], where a high-frequency CP-PLL is designed in 250 nm SiGe technology. Instead, this work presents the design of a PLL that is suitable for space applications in standard silicon CMOS technology, whose radiation hardness is achieved by TMR and layout techniques.  
The next step is test chip fabrication to prototype the proposed PLL solution. The design has been submitted to tape out through MPW (Multi Project Wafer), and hence, the experimental verification of the fabricated prototype is part of the future roadmap.  
M.M.: conceptualization, investigation, methodology, software, writing--original draft, writing--review & editing; B.N.: conceptualization, methodology, supervision, writing-review & editing; G.C.: conceptualization, investigation, methodology, software, writing-review & editing; S.S.: conceptualization, investigation, methodology, supervision, writing-review & editing. All authors have read and agreed to the published version of the manuscript.  
Work supported by ISHTAR and Dipartimento di Eccellenza projects by Pisa University and MIUR.  
Discussions with [PERSON], Pisa University, and [PERSON], INFN, are acknowledged.  
The authors declare no conflict of interest.