## 4 Analysis of Reliability of SSDs  
In this section, we explain analytic formulas used to analyze the ECC that protects data using only the existing ECC and RAID-like protection model that provides differentiated data protection strength (we also refer to this as Differentiated Protection in this work) in terms of error rates.  
The raw bit error rate (\(RBER\)) of flash memory increases exponentially with the P/E cycle period as follows. In this equation, \(x\) represents the P/E cycle of the block, and \(A\) and \(B\) are constant values depending on the type and process of the flash memory [14].  
\[RBER(x)=A\times e^{Bx} \tag{1}\]  
Figure 7: Example of data placement structure. (**a**) Upper Layer; (**b**) Middle Layer; (**c**) Lower Layer.  
ECC codes can correct errors up to \(k\) bits per \(n\)-specific code words. If ECC can correct \(k\) bits errors. The correctable page error rate (\(CPER\)) that ECC can correct from 0 bit error to \(k\) bits error rate, can be calculated with a binary distribution as follows [12; 14].  
\[CPER(n,k,x)=\sum_{i=0}^{k}\biggl{(}\begin{array}{c}n\\ i\end{array}\biggr{)}RBER(x)^{i}(1-RBER(x))^{n-i} \tag{2}\]  
Furthermore, there is a \(k+1\) or more bits error rate that ECC cannot correct, the uncorrectable page error rate (\(UPER\)) is as follow [12; 14].  
\[UPER(n,k,x)=1-CPER(n,k,x) \tag{3}\]  
ECC has a limitation that ECC cannot correct errors when the number of error bits exceeds \(k\), and errors that cannot be corrected by ECC are corrected through RAID parity. In addition, to correct the error through RAID parity, the error must first be detected through ECC.  
ECC can correct errors up to \(k\) bits and detect errors up to 2 \(k\) bits. This is generally valid because coding theory supports this claim [12]. Additionally, assume that SSDs using RAID architecture can correct errors with parity only when a page has bit errors less than or equal to 2 \(k\). Therefore, although it cannot be corrected, the detectable page error rate that can be detected by ECC is defined as follows [14].  
\[DPER(n,k,x)=\sum_{i=k+1}^{2k}\biggl{(}\begin{array}{c}n\\ i\end{array}\biggr{)}RBER(x)^{i}*~{}(1-RBER(x))^{n-i} \tag{4}\]  
There are two cases in which bit errors in the stripe can be corrected. The first case is when all pages containing a stripe have less than or equal to \(k\) bits errors. A case in which an error of \(k\) bits or less occurs in all pages containing a stripe can be corrected by ECC, and the probability of occurrence, in this case, is defined as follows [21].  
\[\biggl{(}\begin{array}{c}N\\ 0\end{array}\biggr{)}CPER(n,k,x)^{N-1}*~{}DPER(n,k,x)\]  
If there is no parity per stripe (only ECC is provided), the error bit will be corrected only by the ECC of the stripe page, so the \(UPER\) in the ECC model is as follows.  
\[UPER_{ECC}(n,k,x)=\frac{1}{N}\biggl{(}1-\biggl{(}\begin{array}{c}N\\ 0\end{array}\biggr{)}CPER(n,k,x)^{N}\biggr{)} \tag{5}\]  
\(N\) stands for stripe size, if there is one parity per stripe: (1) When only bit errors that can be corrected by ECC occur in the striped page, and (2) ECC detectable errors occur on one page of the stripe and ECC correctable errors occur on the remaining pages. Since errors can be corrected in these two cases, the \(UPER\) is as follows [14].  
\[UPER_{P1}(n,k,x) =\frac{1}{N}(1-\biggl{(}\begin{array}{c}N\\ 0\end{array}\biggr{)}CPER(n,k,x)^{N}-\biggl{(}\begin{array}{c}N\\ 1\end{array}\biggr{)}CPER(n,k,x)^{N-1} \tag{6}\] \[*DPER(n,k,x))\]In the case where two parities per stripe are maintained, if two-page errors that can be detected by ECC occur at the same time, both pages can be modified at the same time, so the _UPER_ is as follows [14].  
\[\begin{array}{ll}UPER_{P2}(n,k,x)&=\frac{1}{N}\bigg{(}1-\left(\begin{array}[] {c}N\\ 0\end{array}\right)CPER(n,k,x)^{N}-\left(\begin{array}{c}N\\ 1\end{array}\right)CPER(n,k,x)^{N-1}\\ &*DPER(n,k,x)-\left(\begin{array}{c}N\\ 2\end{array}\right)CPER(n,k,x)^{N-2}*DPER(n,k,x)^{2}\bigg{)}\end{array} \tag{7}\]