# Thermomechanical Stresses in Silicon Chips for
## 4 Discussion
Therefore, the initial considerations of the phenomena of weak stress must be reconsidered. Investigations in this direction are underway to understand the effect of applied pressure on the assembly process. Raman shift profiles at the same sample position recorded at different temperatures show a linear trend with slightly different slope values for the three samples. Therefore, it shows that the effect of temperature has different repercussions on the samples depending on their stress values. In particular, a difference in the variations in the stress values, along the diagonal, from \(-50\) to 180 \({}^{\circ}\)C is found, particularly for the A_AuSn sample. At high temperatures, the stress is significantly lower than at the other temperatures. This fact can be explained by considering the assembly process and the materials involved in the process. The residual stresses in the mounted samples are mainly due to thermal mismatch due to the different thermal expansion coefficients, reported in Table 7, of the materials involved. The working conditions of the soldering process reach a temperature of approximately 320 \({}^{\circ}\)C. At this temperature, the AuSn interconnection layer is melted and is in contact with a dilated substrate and a dilated chip. During the cooling process, the materials shrink differently according to their thermal expansion coefficients, and the further we recede from the highest process temperature, the more the effect of the different thermal expansion coefficients increases, accentuating the stress on the device. In particular, since the copper substrate has a higher thermal expansion coefficient than silicon, it contracts more than the chip, causing the chip to be more susceptible to tensile stresses. The measurement temperature of 180 \({}^{\circ}\)C represents a value closer to that of the soldering, which means that the materials are characterized by geometric distortions between molecules and intramolecular forces similar to what they have during the assembly process. Furthermore, at 180 \({}^{\circ}\)C the Si atoms in the lattice are much more mobile and can \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Material** & \multicolumn{2}{c}{**CTE**} & \multirow{2}{*}{**Young’s Modulus (GPa)**} & \multirow{2}{*}{**Poisson’s Ratio**} \\  & [ppm/\({}^{\circ}\)C] & & \\ \hline Si & 2.8 at 25 \({}^{\circ}\)C & 191 & 0.278 \\ AuSn & 16 & 68 & 0.4 \\ Cu & 16.4 at 25 \({}^{\circ}\)C & 131 & 0.35 \\ Al\({}_{2}\)O\({}_{3}\) & 8.1 & 330 & 0.238 \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Materials properties of investigated assemblies’ components [29; 30; 31]. easily adapt to the new conditions to which the system is subjected. It results in low variations in the stress on the materials. The pressure applied during the assembly plays a crucial role in the results: the difference in stress is clearly evident by comparing samples mounted with and without pressure and needs to be further investigated. The pressure may influence the dynamics of the interconnection layer by affecting the voids in the AuSn alloy and the compactness of the conductive layer, influencing the stress of the active layer. In any case, from these measurements it clearly emerges that Raman spectroscopy can be used as a valuable tool to understand the efficiency and quality of the interconnection process. The results of the analysis on sample B_AuSn, consisting of a silicon chip soldered on a ceramic substrate, are reported in Table 8. They suggest a lower Raman signal shift along the sample surface than for the same sample assembled on a copper substrate. This result can be easily explained by considering the thermal effect: comparing the mismatch of the linear thermal expansion coefficients of silicon and alumina with the mismatch between silicon and copper, it is observed that for the alumina substrate it is about half as much as for copper. This means that the thermal mismatch generates only weaker stresses.