# High-Performance QC-LDPC Code Co-Processing Approach and VLSI Architecture for Wi-Fi 6
## 3 The Co-Processing Schemes and Architectures
### The Strategy and Architecture of Pre-Processing
Next, the residual widths are written to the DBs, and the remaining lengths of the DBs are continuously taken out of the IB, as shown in case 2 in Figure 5.  
SBs: If the SBs for current codewords are not null, they should be padded with zero of the corresponding length at the end of DBs. If the quantization bit width is 7, the related soft information is +63 (determined to be zero), the sign bit is filled with zero, and the other bits are filled with one. When implemented, a control signal can be given so that the block splicing module will fill the remaining bits of the current block with zero. Suppose the SBs of the codeword are more significant than the block size. In that case, the block splicing module continues to output all zero blocks until the number of output blocks reaches the number of standard information blocks corresponding to the current code rate. PBs: The processing of the PBs is similar to the DBs. First, according to the total number of PUBs \(N_{punc}\), the \(N_{CW}\), the current codeword order, and the length of the standard PBs, the actual PBs are determined. Similarly, if there is a residual width in the final output of IB for the DBs, the remaining bits are written before the number of remaining PBs is taken from the IB. PUBs: If the PUBs are not null, it is filled with indeterminate data of the corresponding length, corresponding to zero value for the soft information. The detailed implementation is similar to the SBs. RBs: If the RBs are exited, the length of the RBs of the current codeword is determined based on the total number of RBs \(N_{rep}\), the \(N_{CW}\), and the ordinal number of the current codeword. If residual widths exist in the last IB output data widths for the PBs, the residual data are discarded before the remaining RBs lengths are read out of the IB. In the case of higher modulation, such as 1024 QAM, it may be possible for an output of IB to contain both the PBs, the RBs, and the DBs for the next codeword. To this end, this paper designs the state flow diagram shown in Figure 6, which is divided into the following six states:  
IDLE\({}_{1}\): idle  
INFOR: IF processing  
SHORT: SBs processing  
PARITY: PBs processing  
PUNC: PUBs processing  
REPT: RBs processing  
Where:  
Figure 5: Input buffer output residual bits. statrt1: the start of field processing. Four conditions determine it: there are remaining codewords in this frame, the ready signal that the decoding core has prepared, the IB is not empty, and there are no residual bits to be processed. len_if_cnt: length of the remaining pending IF. w_ib: the output width of the IB. b_if_cnt: the number of blocks of the IF to be processed. len_p: length of PUBs. len_r: the size of RPs. len_r_cnt: length of the remaining pending RPs. b_cnt: the number of blocks to be processed. Block stitching is the next layer of field stitching, and block stitching is carried out based on the output of the IB and the corresponding valid bit length. Figure 7 shows the state diagram, with a total of seven states:  
IDLE2: idle  
WR_B: general block stitching  
REPT: RPs processing  
SH_PD: SBs padding  
SH_B: SBs full block padding  
PU_PD: PUBs padding  
PU_B: PUBs full block padding  
Thereinto:  
start2: the start of block splicing, and valid when start1 is valid, or there is a residual bit, that is start2 = start1 || res_bits. state 1: the state of field splicing  
P_pd: the first block padding of PUBs is complete  
s_pd: the first block padding of SBs is complete  
It is worth noting that len_p and len_r cannot be greater than zero at the same time. Because when we conduct rate matching, we can only delete a part of the bits (punctured) or add a part (repeated) to adapt to the communication system integer symbol transmitting and receiving. Figure 6: State diagram of field splicing. The valid bit length may be cross-block, as shown in Figure 8. This paper adopts a ping-pong structure, two sets of shift registers, and alternately outputs the spliced blocks.