## 4 Implementation Results and Comparisons
### Comparison of Our Dedicated Multipliers with Scalable Architecture  
_Slices and LUTs comparison._ As shown in columns two and three of Table 1, the utilized slices and LUTs for only the dedicated multiplier implementations are lower than the slices and LUTs achieved for our flexible design. The reason is the support for all NIST-defined binary fields in our flexible architecture. For better comparison, if we calculate the sum of slices and LUTs of all the binary fields together, it becomes 9766 and 25,987, which are comparatively 2.60 (ratio of 9766 with 3753) and 3.48 (ratio of 25,987 with 7461) times higher as compared with the slices and LUTs of our flexible architecture. _Comparison over computational time in terms of clock cycles, frequency and latency._ Due to its flexibility, our scalable design requires more clock cycles (i.e., four) as it offers all the NIST-defined binary fields for implementation. The dedicated architectures require only one clock cycle for computation, including the reduction over polynomials. As expected, the flexible architecture is operating at a lower operational frequency of 305 MHz as compared to our dedicated multiplier designs, as shown in Figures 2-6. Similar to the clock frequency, column seven in Table 1 provides the latency values, which indicate that the dedicated design over \(GF(2^{571})\) is 5.82 (ratio of 0.01311 over 0.00225) times faster (in terms of computational time) as compared to the flexible design of Figure 7. It is important to clarify that the flexible design has a critical path similar to the dedicated design of Figure 6. Even if the critical path is almost similar, the latency value for the flexible design is 5.82 times lower. The reasons are the requirement for four-times higher clock cycles as compared to the dedicated design of Figure 6 and the use of an additional \(5\times 1\) multiplexer in the data path of Figure 7. Another cause is the lower operational frequency in our scalable design in Figure 7. Consequently, the latency is the ratio of clock cycles over operational frequency, as given in Equation (3). Thus, this ratio (i.e., 4 over 305) results in more computational time in terms of latency as compared to the latency (i.e., ratio of 1 over 443) calculated for our design in Figure 6.  
_Comparison over consumed power._ For the dedicated architecture of a higher 571-bit binary field length, the consumed power is 3.726 W, which is comparatively 1.04 (ratio of 3.905 with 3.726) times lower than the flexible design. The reason is the longer routing delays in our flexible multiplier architecture as compared to our dedicated multiplication designs. As we finalize the comparisons, it is evident that the flexible architecture results in lower hardware resource utilization (slices and LUTs). Moreover, the dedicated multiplication architectures result in a lower computational time (latency) and consumed power. Therefore, there is always a tradeoff between several design parameters. \begin{table}
\begin{tabular}{l c c c c c c c c} \hline \hline \(m\) & **Slices** & **LUTs** & **CCs** & **PP (in ns)** & **Freq. (MHz)** & **Latency (in μs)** & **Pwr. (in W)** & **Slices \(\times\) Latency** \\ \hline \multicolumn{10}{l}{**Dedicated architectures**} \\ \hline
163 (Figure 2) & 1182 & 3925 & 1 & 2.000 & 500 & 0.00200 & 3.201 & 2.364 \\
233 (Figure 3) & 1451 & 4464 & 1 & 2.100 & 476 & 0.00210 & 3.326 & 3.047 \\
283 (Figure 4) & 1589 & 4927 & 1 & 2.150 & 465 & 0.00215 & 3.409 & 3.416 \\
409 (Figure 5) & 2093 & 5728 & 1 & 2.215 & 451 & 0.00221 & 3.561 & 4.625 \\
571 (Figure 6) & 3451 & 6943 & 1 & 2.255 & 443 & 0.00225 & 3.726 & 7.764 \\ \hline \multicolumn{10}{l}{**Scalable/flexible architecture**} \\ \hline
163 (Figure 7) & & & & & & & \\
233 (Figure 7) & & & & & & \\
283 (Figure 7) & 3753 & 7461 & 4 & 3.275 & 305 & 0.01311 & 3.905 & 49.201 \\
409 (Figure 7) & & & & & & & \\
571 (Figure 7) & & & & & & & \\ \hline \hline \end{tabular}  
Pwr is the total (sum of static and dynamic) power. CCs is the clock cycles. PP is the provided clock period.  
\end{table}