# An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks
## 1 Introduction  
Spacecraft data-handling networks [1] are required to sustain multi-gigabit capabilities, due to the increasingly high data volume produced by high-rate payloads, such as hyperspectral imagers [2] and synthetic aperture radars [3]. The demand for high bandwidth leads to some limitations of single-lane standards [4; 5; 6; 7; 8; 9], and some multi-lane standards [10] support only an even number of lane configurations. To enhance the data processing ability in a space environment, the European Space Agency developed the SpaceFibre [11] standard for interconnection networks designed for satellite payloads. SpaceFibre supports an arbitrary number of lanes between 1 and 16, and each lane has a maximum data rate of 6.25 Gbps. To handle a lane failure when a cable is damaged during the launch of a spacecraft, SpaceFibre provides hot redundant lanes [12] and graceful degradation. The standard adopts built-in integrated quality of service (QoS) [13], allowing data from different virtual channels (VCs) to multiplex over a link. In SpaceFibre, a detection isolation and recovery (FDIR) mechanism [14] is responsible for resending corrupted data, which are generally caused by space radiation. The standard introduces a token-based flow control mechanism to avoid overrunning the recipient resources. Several implementations of single-lane SpaceFibre cores are proposed in the literature [15; 16; 17; 18; 19]. Nevertheless, a limited reference is provided by the implementations because the inclusion of a multi-lane attribute brings major adjustments in the architecture of a SpaceFibre core. For these reasons, implementations of a multi-lane SpaceFibre core, compliant with all features, face complex challenges. Implementations of multi-lane SpaceFibre cores can be found in the publications [20; 21; 22; 23]. A multi-lane hardware prototype was proposed in Reference [20] for the development of the SpaceFibre protocol. Regardless, the prototype still needs to be improved in terms of its resource consumption. Reference [21] reported a silicon implementation of a multi-lane SpaceFibre core, with two lanes for low-cost satellite electrical ground segment equipment. However, the data signaling rate of the core is limited by the maximum number of lanes. In Reference [22], a multi-lane core with good performance was presented. As a proprietary core, the work does not report any details of the core. Reference [23] detailed the architecture of a multi-lane core and introduced a test campaign to measure recovery time after a lane failure, whereas the resource overhead and recovery time consumed by the core need to be improved. To solve the above problems, we propose the complete hardware architecture of an efficient multi-lane SpaceFibre (E-ML-SpFi) core, featuring easy expansion, low resource consumption, and high performance. The three main contributions of this work are given as follows. The first is the powerful hierarchical control method, which is responsible for simplifying the complex control logic [24] of the retry mechanism. The hierarchical control is divided into three levels, namely the response control level, the storage control level, and the retry control level. As a result, the hardware resources are saved and the Data-Link layer recovery (DLRec) time is shortened. The second contribution is the modified word re-ordering block. The modified block introduces an extended set of words compared with the original block [25]. Each type of word in the set corresponds to rules belonging to a ruleset specific to SpaceFibre. Based on the ruleset and the initial order of words, the block automatically splits the words on a variable number of data-sending lanes. Consequently, the core can accommodate the entire ruleset for SpaceFibre and can accomplish adaptive control. The third one is the design of a fast alignment subsystem, which is adopted to speed up alignment operations. The subsystem combines three main techniques: advance extractions, characteristic bits, and parallel examinations.