# Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate
## 1 Introduction  
Recently, amorphous indium gallium zinc oxide (a-IGZO) has drawn much attention as an active channel material for thin-film transistors (TFTs) because of its relatively high mobility, low off-current, high I\({}_{\text{on}}\)/I\({}_{\text{off}}\) ratio, and low-temperature process [1; 2; 3; 4; 5]. In particular, IGZO TFTs can be fabricated on a flexible substrate, such as polyethylene terephthalate (PET) and polyimide (PI), through a low-temperature process, and they have been applied to rollable and foldable electronics [6; 7; 8]. However, the inherent performance degradation caused by bending conditions and bias stress is problematic in flexible IGZO systems. Therefore, a systemic study about the effect of mechanical and electrical stress on long-term reliability should be performed at both device and circuit levels. It is necessary to predict the circuit operation in alternating current (AC) driving conditions through simulations that reflect analysis results. Until now, there has been much research on direct current (DC) stress [9; 10; 11; 12; 13; 14; 15; 16; 17], even though most circuits are driven in AC conditions. Hence, it is very important to analyze the instability characteristics of IGZO devices and circuits in various AC conditions so that compact modeling can be drawn for the reliability-aware SPICE (Simulation Program with Integrated Circuit Emphasis) simulation.  
Generally, a positive gate bias stress (+V\({}_{\text{G}}\)) on IGZO TFTs results in a positive shift of threshold voltage (\(V_{T}\)). This is due to electron-trapping inside the gate insulator and on the interface trap. However, when the gate insulator is aluminum oxide (Al\({}_{2}\)O\({}_{3}\)) depositedby atomic layer deposition (ALD) at low temperatures, in addition to electron-trapping that generates positive \(\Delta V_{T}\), there is also a hydrogen migration mechanism that generates negative \(\Delta V_{T}\)[18; 19; 20; 21; 22; 23]. [PERSON] et al. investigated the static and dynamic bias stress-induced charge trapping and de-trapping in IGZO TFTs [18]. [PERSON] et al. examined the impact of channel length on the performance of IGZO TFTs with self-aligned structures [19]. Although these studies investigated the mechanism of \(V_{T}\) shift in various conditions, the studies were performed at the transistor level, which has a limitation in circuit-level AC simulation.  
In this paper, we analyzed the performance of IGZO TFTs and inverters based on the aforementioned degradation mechanisms, while mechanical stress (bending) and electrical stress (AC stress) were applied simultaneously. The NMOS-only inverters were fabricated on a flexible PET substrate consisting of a low-temperature processed a-IGZO and an ALD Al\({}_{2}\)O\({}_{3}\) gate insulator. The electrical stress and recovery on the driver and load transistor of the inverters were analyzed under AC bias conditions. Multiple bending tests were also performed for the mechanical stress test. Parameters such as \(\tau(V)\), \(\beta\), and \(\Delta V_{T0}(V)\) were obtained by applying the stretched exponential function (SEF) to the instability characteristics that appeared in each stress condition [24; 25]. These parameters were loaded into HSPICE so that the simulation could reflect the \(\Delta V_{T}\) in real-time, while AC bias was applied. This work can be a useful approach for a reliability-aware simulation of flexible IGZO circuits, enabling a circuit operation prediction based on compact modeling.