# Radiation-Hardened 16T SRAM Cell with Improved Read and Write Stability for Space Applications
###### Abstract  
The critical charge of sensitive nodes decreases as transistors scale down with the advancement of CMOS technology, making SRAM cells more susceptible to soft errors in the space industry. When a radiation particle strikes a sensitive node of a conventional 6T SRAM cell, a single event upset (SEU) can occur, flipping in the stored data in the cell. Additionally, charge sharing between transistors can cause single-event multi-node upsets (SEMNUs), where data in multiple nodes are flipped simultaneously due to a single particle strike. Therefore, this paper proposes a radiation-hardened high stability 16T (RHIS16T) cell for space applications. The characteristics of RHHS16T are evaluated and compared with previously proposed radiation-hardened SRAM cells such as QUCCE12T, WEQUATRO, RHBD10T, RHD12T, RSP14T, RHPD14T, and RHBD14T. Simulation results for RHHS16T indicated that the proposed cell demonstrates improved performance in read stability, write access time, and write stability compared to all comparison cells. These improvements in the proposed cell are achieved with higher power consumption and a minor area penalty. Notably, isolating the storage node from the bit line during read operations and the feedback loop between nodes during write operations enables the proposed RHHS16T to achieve enhanced read stability and write stability, respectively. The proposed integrated circuit was implemented using a 90 nm CMOS process and operates at a supply voltage of 1V. Furthermore, RHHS16T provides high immunity against SEUs and SEMNUs. Through its enhanced read and write stability, it ensures reliable data retention for space applications. c 2024 14 11940. [[https://doi.org/10.3390/app142411940](https://doi.org/10.3390/app142411940)]([https://doi.org/10.3390/app142411940](https://doi.org/10.3390/app142411940))  
c 2024 16T 2024 16  
upsets (SEMNUs) [6; 7]. Therefore, to enhance the reliability of data stored in SRAM, it is necessary to design SRAM cells to be robust against SEU and SEMNUs. To address the malfunction of SRAM caused by an SEU, researchers have proposed various methods such as triple modular redundancy (TMR), error correction code (ECC), and SRAM cell design that can recover from the influence of SEUs. Firstly, the TMR method requires two additional redundant cells for each existing SRAM bit cell [8]. This method selects the correct value through majority voting among the three cells [9]. However, this method results in a significant increase in area and power consumption. Therefore, it is not suitable for SRAM cells in the space industry. Secondly, the ECC method mitigates SEUs by utilizing additional encoding and decoding circuits [10]. This method is based on error correction and detection codes, requiring additional circuits, which makes it unsuitable for memory cells in satellite communication technology when considering time, power, and area [11]. Compared to these two methods, using radiation-hardened SRAM cells is relatively superior in terms of time, power, and area. Therefore, it is desirable to design radiation-hardened SRAM cells that can recover from both SEUs and SEMNUs [12]. Due to the advantages of radiation-hardened SRAM cells, researchers have proposed various SRAM cells with recovery capabilities from soft errors over the years. [PERSON] et al. proposed the QUATRO10T [13]. However, QUATRO10T has a limited recovery capability only for a '1'-\(\rightarrow\)0' SEU occurring at the '1'-storing node and is vulnerable to write operations due to long write delays and high write failure rates. To improve the write stability of QUATRO10T, [PERSON] et al. proposed the 12T structure WE-QUATRO [14]. However, this structure also has limited recovery capability for SEUs and shows degraded read stability. [PERSON] et al. proposed two hardened SRAM cells, NS10T and PS10T, with recovery capabilities from SEUs [15]. However, NS10T and PS10T provide only partial immunity to SEUs.