# Reduction of Bias and Light Instability of Mixed Oxide Thin-Film Transistors
## 1 Introduction  
The interest in mixed oxide semiconductor-based thin-film transistors (TFTs) for applications in active-matrix displays (AMDs) has generated a large body of experimental and theoretical studies devoted to mixed oxide semiconductors, particularly amorphous indium-gallium zinc-oxide (a-IGZO) [1; 2]. For applications in AMDs, reliability and stability of the TFTs used as pixel-switching elements are of primary concern [3]. Stability against negative-gate bias stress combined with visible light illumination (NBIS) is of particular importance, given that TFTs in a display pixel operate in an illuminated environment. Although many investigations have focused on the effects of NBIS, which include persistent negative threshold-voltage (\(V_{\text{TH}}\)) shift [4; 5; 6; 7], they have not yet found ways to suppress them completely. Since the TFTs' \(V_{\text{TH}}\) stability has a strong bearing on display uniformity, lifetime, and pixel architecture [3], some groups have proposed subjecting mixed oxide TFTs to post-deposition annealing at high temperatures under wet [8], oxygenated [9], ozonated [10], or nitrogenated environments as a way of minimizing the effects of NBIS. Other groups have proposed the use of light shields, nitrogen cap layers [11], high-quality dielectrics (both as gate insulators [12], and passivation [13] layers), but such methods suppress the NBIS-induced instability only to limited extents.  
Recently, bulk accumulation, which is achieved by the use of a dual-gate structure in which the top gate and bottom gate are electrically shorted together, has been shown to reduce the NBIS instability ofmixed oxide TFTs with thin semiconductor layers (\(<\)25 nm) [14, 15]. However, similar to other stability improvement methods, bulk accumulation also suppresses the NBIS instability only to a limited extent. In addition, several reports have indicated the importance of the semiconductor thickness in the stability of the mixed oxide TFTs but different groups reached different conclusions [8, 16, 17, 18]. For instance, for some groups, the bias stability of the TFTs became better as semiconductor thickness increased [16, 17], whereas, for other groups, it worsened [18]. [PERSON] et al. also showed opposite trends for wet-annealed and non-annealed TFTs [8]. For wet-annealed TFTs, the \(V_{\text{TH}}\) shift (\(\Delta V_{\text{TH}}\)) decreased with increasing semiconductor thickness, and for non-annealed TFTs, \(\Delta V_{\text{TH}}\) increased with increasing semiconductor thickness. [PERSON] et al., therefore, concluded that the density of trap states increased with increasing semiconductor thickness in the non-annealed TFTs, whereas in the wet-annealed TFTs, there was almost no bulk effect.  
In this study, we investigate the effect of semiconductor thickness on the stability of mixed oxide semiconductor TFTs against NBIS. In contrast to previous reports [8, 16, 17, 18, 19, 20], we fabricate the TFTs using an optimized fabrication process, which involves the in situ passivation of the mixed oxide semiconductor, and we investigate very thin (3-10 nm) and thick (20-100 nm) semiconductor layers. For the mixed oxide, we use the a-IGZO semiconductor, given that a-IGZO TFTs can be built with the simple and cost-effective inverted staggered structure, and exhibit high field-effect mobility (\(\mu_{\text{FE}}\)) and low \(V_{\text{TH}}\)[1, 2].