## 4 Measurements, Simulations and Discussion  
Several measurements have been performed using the experimental setup described in Sections 2 and 3. In particular, different sinusoidal signals have been generated by the power amplifier and applied to the transformer. In more detail, input voltages at constant amplitude and with three different frequencies (i.e., 20, 50 and 80 Hz) have been exploited. Moreover, the controllable parameters D and T\({}_{\text{D}}\) have been varied and the output voltage measured. The experimental signals have been compared with LTspice circuit solver simulations. The circuit of Figure 3 has been implemented, and the experimental V\({}_{\text{in}}\) and PWMs signals have been used as input voltages of the circuit. Figure 8 shows an example of a comparison in steady-state between the measured and simulated output voltages at T\({}_{\text{D}}\) = 1% and D = 80%, which are the optimal parameters at f\({}_{\text{in}}\) = 50 Hz, as shown in the following. The output voltages and currents are in very good agreement. It is noticeable that the PWM1 (red) signal rises linearly when the input voltage positively crosses zero and falls after about 15 ms, i.e., 0.8 T, while the PWM2 (blue) signal follows the PWM1's behavior after T/2, as expected. Finally, the current profiles show that the inductor discharges on the capacitor-resistor parallel after each intersection between the two \"ON\" states of the PWM signals (i.e., both MOSFETs are closed). Figure 7: Picture of the setup sketched in Figure 6 and used for the experimental measurements. It is worth noting that, in order to exploit the circuit as a boost, the following working conditions should be addressed:  
* Duty Cycle > 50%, which means that the inductor should be short-circuited on the AC input and then charged in a certain time interval;
* (T\({}_{\rm D}\) + D) < 100%, i.e., Time Delay and \"ON\" timing of the two PWM signals should belong to a time period T of the AC input (100% of the time period T). Moreover, because of the intrinsic rising and falling time of the PWM signals and the MOSFET's switching time, T\({}_{\rm D}\) cannot be null; rather, it needs to start from a minimum value of 1% of the period T. Then, the RMS output voltages are represented as triangular matrices with respect to T\({}_{\rm D}\) and D.  
Figure 9 shows the RMS voltage surfaces with respect to different values of Time Delay, Duty Cycle and input voltage frequency. The surfaces have similar shapes and show a maximum in the region where the circuit acts as boost, while it decreases near the above-mentioned boundary working condition. The RMS voltage maximums increase with the input frequency because of the related switching frequency that is dependent on f\({}_{\rm in}\). Indeed, the peak RMS voltage increases from 1.6 V at f\({}_{\rm in}\) = 20 Hz up to 2.94 V at f\({}_{\rm in}\) = 80 Hz, with a gain of about 10.3 and 19, respectively. Furthermore, the T\({}_{\rm D}\) - D parameters that maximize the voltage are placed on a almost straight line. Finally, maximum RMS voltages are achieved at D = 75% and T\({}_{\rm D}\) = 1% for f\({}_{\rm in}\)= 20 Hz (see Figure 9a) and at D = 80% and T\({}_{\rm D}\) = 1% for f\({}_{\rm in}\) equal to 50 and 80 Hz, respectively (see Figure 9b,c). The corresponding peaks of the RMS powers are about 1.2, 3 and 4 mW, respectively. Figure 8: Steady\(-\)state signals over time at T\({}_{\rm D}\) = 1% and D = 80%. Input voltage frequency f\({}_{\rm in}\) = 50 Hz. From the top pane to the bottom one: measured input voltage, measured PWMs signals, measured and simulated inductor current, measured and simulated output voltage. Figure 10 reports the RMS output voltage relative errors between measured and simulated data, with respect to Time Delay and Duty Cycle, at three different input voltage frequencies.