# A Current-Mode Optoelectronic Receiver IC for Short-Range LiDAR Sensors in 180 nm CMOS
## 4 Proposed Current-Mode Optoelectronic Receiver (C-OER)
According to small signal analysis, the input resistance of the CCIBs varies with respect to the number of the switched-on blocks. When only CCIB#3 is turned on, the input resistance (\(R_{in,3}\)) is given by,  
\[R_{in,3}=\frac{1}{g_{m2}}||\frac{1}{g_{m5}}\cong\frac{1}{2g_{m}}, \tag{2}\]  
where \(g_{m2}\) and \(g_{m5}\) represent the transconductance of M\({}_{2}\) and M\({}_{5}\), respectively. Provided that \(g_{m2}=g_{m5}=g_{m}\), the input resistance becomes equal to \(1/2g_{m}\). When other two CCIB blocks (#2 and #4) are added to CCIB#3 with the switch turned on, the new input resistance (\(R_{in,2}\)) is given by,  
\[R_{in,2}=R_{in,3}||R_{in,parallel}\cong\frac{1}{2g_{m}}||\left(\frac{1}{2g_{ m}}||\frac{1}{2g_{m}}\right)=\frac{1}{6g_{m}} \tag{3}\]  
All the CCIB blocks are turned on simultaneously, the input resistance (\(R_{in}\)) is given by,  
\[R_{in}=R_{in,2}||R_{in,parallel}\cong\frac{1}{6g_{m}}||\left(\frac{1}{2g_{m}} ||\frac{1}{2g_{m}}\right)=\frac{1}{10g_{m}} \tag{4}\]  
Therefore, it is clearly seen that the CCIB stage provides a very low input resistance of \(1/10g_{m}\), hence helping to isolate the photodiode capacitance from the bandwidth determination more effectively than the V-OER. Additionally, it yields a large output resistance of \(\
eg(1/2)g_{mm}{}^{2}\), thereby preventing the loss of the input current signals more efficiently. Figure 13b shows the schematic diagram of the cascode inverter stage (CIS) with a feedback resistor array (FRA) that comprises five resistors (\(R_{F1}\)\(\sim\)\(R_{F3}\)) and four switches (M\({}_{17}\)\(\sim\)M\({}_{20}\)). The FRA conducts the function of automatic gain control (AGC). Among the five resistors in the FRA, R\({}_{\rm F1}\) should always be connected, while the other four resistors (\(R_{F2}\) and \(R_{F3}\)) are turned on via thick-gate NMOS switches (M\({}_{17}\)\(\sim\)M\({}_{20}\)). These thick-gate NMOS switches are designed to operate in pairs and are controlled by a feedforward voltage generator (FVG) that consists of two-stage cascaded amplifiers and an on-chip MIM capacitor (C\({}_{\rm MIM}\)) for low-pass filtering, as shown in Figure 13c. Thereby, the transimpedance gain can be tuned automatically within the duration of a narrow single pulse at the different input voltages of VB1 and VB2, respectively. Based on the output voltage (IB_OUT) of the CCIB stage, the FVG generates 3.3 V DC voltages (FVG_OUT) to turn the NMOS switches on in the FRA. When the FVG turns all the NMOS switches on, the CIS produces the lowest transimpedance gain. When the FVG is turned off, only the feedback resistor \(R_{F1}\) is activated and thus the CIS amplifies the input currents with the highest transimpedance gain. Figure 12: Block diagram of the proposed C-OER. Small signal analysis indicates that the transimpedance gain of the CIS is given by,  
\[Z_{T,inv}\approx\left(\frac{A_{inv}}{1+A_{inv}}\right)R_{F,EQ}\cong R_{F,EQ}, \tag{5}\]  
where \(A_{inv}\) is the voltage gain of the CIS, and \(R_{F,EQ}\) represents the equivalent feedback resistance of the FRA [10]. The input resistance of the CIS is given by,  
\[R_{in,ITS}=\frac{R_{F}}{A_{inv}+1}\cong\frac{R_{F,tot}}{g_{m}^{2}r_{0}{}^{2}}, \tag{6}\]  
where the non-dominant pole occurs at the input node of the CIS. The output pole also becomes non-dominant because of its small capacitance [10]. Therefore, the bandwidth (\(f_{\text{-3 dB}}\)) is nearly determined at the input node of the CCIB stage, i.e.,  
\[f_{\text{-3 dB}}\cong\frac{1}{10\pi R_{in}(C_{pd}+2C_{gs,n}+2C_{gs,p})}, \tag{7}\]  
where \(R_{in}\) is the input resistance of the CCIB stage as defined in (3), \(C_{pd}\) is the photodiode capacitance, \(C_{gs,n}\) is the gate-source capacitance of NMOS transistors (M\({}_{2}\) and M\({}_{4}\)), and \(C_{gs,p}\) is the gate-source capacitance of PMOS transistors (M\({}_{5}\) and M\({}_{7}\)), respectively [10]. Figure 13: Schematic diagrams and the specific parameters of (**a**) CCIB, (**b**) CIS, and (**c**) FVG blocks.