# Independent Double-Boost Interleaved Converter with Three-Level Output
## 3 Simulation and Practical Implementation  
Figures 11 and 12 introduce the PLECS simulation and practical measurements for the discontinuous conduction mode (DCM) and continuous conduction mode (CCM) of the proposed IDBIC converter in the symmetrical operation of the two integrated boost converters. The gate-source command voltages of the transistors (T\({}_{1}\), T\({}_{2}\), T\({}_{3}\), T\({}_{4}\)) are represented by V\({}_{\text{GS-T1}}\), V\({}_{\text{GS-T2}}\), V\({}_{\text{GS-T3}}\), and V\({}_{\text{GS-T4}}\). The drain-source voltages on all transistors are shown as V\({}_{\text{DS-T1}}\), V\({}_{\text{DS-T2}}\), V\({}_{\text{DS-T3}}\), and V\({}_{\text{DS-T4}}\). The inductors' currents, I\({}_{\text{L1}}\) and I\({}_{\text{L2}}\), are illustrated as well. The command signals V\({}_{\text{GS-T1}}\) and V\({}_{\text{GS-T2}}\) are pulse width modulation signals (PWM), normally used in the regular interleaved boost converter with a 180\({}^{\circ}\) phase shift between the two signals. The logic 1 (high value) of the gate signal V\({}_{\text{GS-T3}}\) was obtained between the falling edges of the V\({}_{\text{GS-T1}}\) and V\({}_{\text{GS-T2}}\) signals. The gate signal V\({}_{\text{GS-T4}}\) was obtained by inverting the signal V\({}_{\text{GS-T3}}\). A compulsory deadtime is introduced for the T\({}_{3}\) and T\({}_{4}\) transistor gate signals. As one can notice, no significant difference can be observed between the simulated and practical measurements. The main differences are obtained during the DCM modes when the inductors' currents are zero. Because of the parasitic components associated with the switching devices and PCB layout, resonant and transient behavior can be observed during the practical measurements. Despite this phenomenon, it is important to note that no relevant negative effect was present in the working behavior of the converter. Figure 10: CCM–DCM boundary limit plot for D < 0.5 (orange line) and for D > 0.5 (blue line). Figure 11: PLECS Simulation results in DCM and CCM operation modes. Figure 12: Practical measurements of the proposed converter in DCM and CCM. To operate the integrated boost converters in an independent manner, a three-voltage level system with two loads is needed at the output, as one can notice in Figure 13, where the generic voltage control loops and the PWM signal generator are highlighted. This schematic is suitable for an asymmetric control of the converter in which the reference voltages \(\mathrm{V_{ref\,1}}\) and \(\mathrm{V_{ref\,2}}\) can have different values; thus, each integrated boost converter needs to operate independently. The most common usage of the asymmetrical control is related to the energy balancing/interconnections in bipolar DC grids/applications. Thus, in this case, the voltage references \(\mathrm{V_{ref\,1}}\) and \(\mathrm{V_{ref\,2}}\) are equal. Considering different values for the R\({}_{1}\) and R\({}_{2}\) loads in the asymmetric mode, indicating different inductor currents, the independent operation of the two integrated boost converters is demonstrated. For an application in which the overall output voltage \(\mathrm{V_{out}}\) must be regulated, a symmetrical control loop approach is sufficient, meaning that only one PI controller and one voltage reference \(\mathrm{V_{ref}}\) are needed. Figure 14 presents the practical measurements for the symmetric and asymmetric control of the converter considering the control schematics presented in Figure 13. For this situation, the output voltage \(\mathrm{V_{out}}\) is set at 400 V, and the voltages \(\mathrm{V_{R1}}\) and \(\mathrm{V_{R2}}\) are equal to 200 V. During CCM operation, the command signals are almost identical, while the inductor currents are equal for the symmetric control and have different values for the asymmetrical control.