# Design of Static Random-Access Memory Cell for Fault Tolerant Digital System
## 3 Radiation-Hardened SRAM Cell Design
### Quadruple Cross-Coupled Latch-Based 10 T and 12 T SRAM Cell (QUCCE-10 T and QUCCE-12 T)  
Figure 7a,b show the schematics of the quadruple cross-coupled latch-based 10 T and 12 T SRAM cell (QUCCE-10 T and QUCCE-12 T), respectively [19]. Similar to the other previous SRAM cell structures, the four nodes A, B, Q, and QN are used to store the data, while each node is driven by pFET and nFET, whose gate nodes are connected to the different nodes. Specifically, the four cross-couple FETs form a full positive feedback network to store data. However, the full positive feedback of QUCCE-10 T considerably lowers the SEU tolerance compared to the other radiation-hardened SRAM cell designs. An SEU-induced voltage change at any storage node can trigger the positive feedback, which in turn makes the initial voltage change severe. For example, for the data \"1\" stored cell--A = 0 V, B = VDD, Q = VDD, and QN = 0 V--0 to 1 SEU can occur on the QN node, leading to the pull-down of the Q node. This turns on P1 to raise the node A, so N4 is turned on, leading to the pull-down of B. As a result, P3 is turned on, making the voltage rise of QN more severe. Figure 6: Schematic of RHBD-12 T SRAM cell. In addition, QUCCE-10 T suffers from a large write delay or reduced write stability in low-voltage regions. For example, when \"0\" is written to the \"1\" stored cell, Q = VDD is supposed to be pulled down by the turned-on N5. For a successful write, WL should be kept high until Q is lowered, A is raised, and then B is lowered so that QN becomes VDD to ensure that N2 is fully turned on. This necessitates a large pulse width for WL assertion, which results in an excessive write delay. To resolve this problem, QUCCE-12 T, shown in Figure 7b is also proposed, but the limited SEU tolerance issue still exists in QUCCE-12 T.  
Radiation-Hardened-by-Design 11 T and 13 T SRAM Cell (RHBD-11 T and RHBD-13 T) and Radiation-Hardened Dynamic 11 T and 13 T SRAM Cell (RHD-11 T and RHBD-13 T)  
Figure 8a,b show the schematics of RHBD-11 T [12] and the 13 T SRAM cell [20], respectively. The key structural feature of these designs is that the nodes a1 and a2 are isolated and the refresh signals--rf and rfb--are employed. The roles of these refresh signals are to be explained later. There are four nodes to store the data; the nodes d, db, a1, and a2. For the write operation, the single-ended bit-line BL is driven first, and then WL and WLB become high and low, respectively, to connect the node d with BL. The refresh signals are only inserted for the refresh operation; thus, the nodes rf and rfb are low and high, respectively. For example, when the datum \"0\" is written, BL is low, so d is driven to be  
Figure 8: Schematic of (**a**) RHBD-11 T and (**b**) RHBD-13 T SRAM cell. Figure 7: Schematic of (**a**) QUCCE-10 T and (**b**) QUCCE-12 T SRAM cell. low as well. This makes db high and so the nodes a1 and a2 also become high due to the turned-on M6 and M7. For the data hold, WL and WLB are disabled, so M6 and M7 are turned off. As a result, the nodes a1 and a2 are isolated and floated. To prevent the instability of the nodes a1 and a2 caused by being floated, rf and rfb are periodically enabled by being high and low, respectively, to refresh the nodes a1 and a2. In RHBD-11 T, all types of SEU can be recovered. This is attributed to the isolation of the nodes a1 and a2, which are implemented through only pFET and nFET, respectively. In this manner, the node a1 (a2) is exposed to only 0 to 1 (0 to 1) SEU, which causes it to turn off M10 (M11) while not turning on any transistor. In this manner, even if the node a1 or a2 is upset, the d and db node voltages are not affected, so the upset node a1 or a2 can be properly recovered through the refresh operation, which drives the nodes a1 and a2 with the intact db node. If the d node is upset, it is recovered by M10 or M11 because the nodes a1 and a2 are isolated and not affected. Likewise, if the db node is upset, it can be easily recovered through the M3-M4 inverter as the node d is intact.