## 4 Discussion
### Comparison of the Proposed AES-128 Implementation with Other Works Reported in the Literature  
For the Zynq SoC, just like other FPGA, the PL section is constituted by CLBs arranged according to matrix structure; each CLB contains two slices, each including four LUTs and eight FFs and a configurable switch matrix [37]. Therefore, from the results shown in Tables 1 and 2, the number of CLBs and slices employed by the developed AES-128 encryption and decryption blocks are 1631/3262 and 3464/6928, respectively. Table 4 reports the comparison between the proposed implementation of AES-128 encryption algorithm with other pipelined implementations previously reported in the scientific literature, similar for operative frequency and supported throughput; also, the platform employed to develop the reported implementations are indicated, since the FPGA technology affects the performance of encryption and decryption. However, the figure of merit chosen for comparing the different implementations is the efficiency, defined as:  
\[Efficiency=\frac{Throughput\ [Mbps]}{\#\ of\ used\ slices}. \tag{6}\] \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Design.** & **Platform** & **Frequency** & **Throughput** & **Slices** & **Efficiency** \\  & & **[MHz]** & **[Cbit/s]** & **[Mbps/slice]** & **[Mbps/slice]** \\ \hline [PERSON] et al. [38] (Enc) & XC2V4000 & 184.1 & 23.57 & 16,938 & 1.39 \\ [PERSON] et al. [25] (Enc) & XC4 VLX200 & 250.0 & 32.00 & 86,806 & 0.36 \\ [PERSON] et al. [39] (Enc) & Virtex-4 & 250.0 & 2.90 & 1220 & 2.30 \\ [PERSON] et al. [40] (Enc) & XCV3200E8 & 145.0 & 18.56 & 10,750 & 1.66 \\ [PERSON] et al. [41] (Enc) & XC2 VP20-7 & 168.3 & 21.54 & 5177 & 4.16 \\ [PERSON] et al. [24] (Enc) & XC2 VP70-7 & 232.6 & 29.77 & 5408 & 5.50 \\ [PERSON] et al. [43] (Enc) & XC7Z200 & 192.0 & 1.29 & 431 & 2.99 \\ [PERSON] et al. [33] (Enc/Dec) & XC3S2000-5 & 196.1 & 23.65 & 16,693 & 1.42 \\ Our solution (Enc) & XCZU9 EG & 220.0 & 28.16 & 3262 & 8.63 \\ Our solution (Enc/Dec) & XCZU9 EG & 220.0 & 28.16 & 10,278 & 2.74 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Comparison of the proposed AES-128 solution with other FPGA implementations. Figure 25: Temporal trends with shown the plaintext data packets provided to the system on each rising edge of the clock; the packets are obtained from the decryption block after 20 clock periods, 10 of which needed for encryption operation and the remaining 10 for the decryption one. The error_sig signal, highlighted in yellow, is low along the whole observation interval, as expected. The packets leaving the decryption block (blue-dashed box) are equal to those entering the encryption block (red-dashed box). In particular, this quantity is representative of how efficiently the FPGA hardware resources are used to support a given output throughput. As evident from the results reported in the following table, the proposed solution can reach high data throughput values (up to 28.16 Gbit/s) but with commensurably lower utilization of the hardware resources compared to other works, thus allowing higher efficiency. Considering the most performing implementation, reported in Reference [42], our solution obtains a maximum data throughput slightly lower (\(-5.3\%\)) but also employs a lot less FPGA hardware resources (i.e., \(-39.7\%\)), thus resulting into a higher efficiency value (\(+56.9\%\)). Also, comparing our solution implementing encryption and decryption operation with those reported in Reference [33], a clear superiority of the former is evident, indicated with a higher efficiency value (\(+92.9\%\)). As aforementioned, it must be considered that the comparison shown in the previous table is made between solutions implemented with different platforms for technology, architecture and maximum clock frequency; therefore, the enhanced performances of our solution are also attributable to the advanced features and complex architecture of the used platform but mainly to the implemented solutions aimed to speed up the encryption/decryption process.