# High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA
## 2 Traditional Approach to the Design of Sequential Multipliers  
The following classical multiplication methods are known by which sequential multipliers are built:  
* Algorithm _a_: the least significant bit of the multiplier is examined, the multiplier is shifted to the right, and the multiplicand to the left;
* Algorithm _b_: the most significant bit of the multiplier is examined, the multiplier is shifted to the left and the multiplicand to the right;
* Algorithm _c_: the most significant bit of the multiplier is examined, and the multiplier, along with the partial product, are shifted to the left;
* Algorithm _d_: the least significant bit of the multiplier is examined, and the multiplier, along with the partial product, is shifted to the right. The datapath of the sequential multiplier \(c\), as presented in Figure 1, consists of the following:  
* A and B: the multiplicand and multiplier, respectively;
* Registers ra and rb for storing the multiplicand and multiplier, respectively;
* Register rp for storing the result;
* Counter cnt generates the done signal to indicate the end of the multiplication process and the internal signal roll that is used by the FSM. Figure 1: The datapath of the sequential multiplier \(c\). Input signals for every block are defined as follows:  
* load: to load the values of multiplied words A and B into registers ra and rb;
* load_p: to load the result of addition into the register rp;
* clr: to reset the register rp and the counter cnt;
* ena: to allow the shift of the content of the register rb and the increase the counter cnt;
* ena_p: to allow the shift of the register rp;
* clk: clock signal;
* reset: reset signal;  
The datapath of the sequential multiplier d presented in Figure 2 consists of:  
* A and B: the multiplicand and multiplier, respectively;
* Registers ra and rb for storing the multiplicand and multiplier, respectively;
* Register rp for storing the result;
* Counter cnt, which generates the signal done to indicate the end of the multiplication process, and the internal signal roll, used by the FSM. Input signals for every block are used for:  
* load: to load the values of multiplied words A and B into registers ra and rb;
* load_p: to load the result of addition into the register rp;
* clr: to reset the register rp and the counter cnt;
* ena: to allow the shift of the content of the register rb and the increase the counter cnt;
* ena_p: to allow the shift of the register rp;
* clk: clock signal;
* reset: reset signal. Using the ASMD-FSMD technique is the most efficient (in terms of speed) in designing multipliers c and d. So, consider the traditional approach in the design of multipliers c and  
Figure 2: The datapath of the sequential multiplier d.  
d. The datapath in the case of the traditional approach for both algorithms is shown in Figures 1 and 2, respectively. The counter cnt generates the signal done, which indicates the end of the multiplication process and the internal signal roll that is used by the FSM. The process of multiplying the numbers A and B starts with the signal run. The control functions identically for both algorithms (c and d). The FSM (Figure 3), based on the values of the signals run and roll, generates the necessary values for the control signals. These include load, which loads the values of multiplied words A and B into registers ra and rb; load_p, which loads the result of addition into the register rp; clr, which resets the register rp and the counter cnt; ena, which allows the shift of the content of the register rb and the increase the counter cnt; ena_p, which allows the shift of the register rp. Additionally, the multiplier is controlled by the clock signal clk and the reset signal reset. In the state S\({}_{0}\), the FSM waits for the signal run, which starts the multiplication process by switching to the state S\({}_{1}\) and generating the signals load and clr.