## 4 SDR Receiver Performance Evaluation  
The performance of the implemented system has been evaluated from two points of view, considering data-rate and error correction performance. To evaluate the system, a compliant SW transmitter has been developed to produce input data for the receiver. To decouple transmitter and receiver speed, the encoded bits were computed offline and then provided to the receiver as sets of thousands of PL frames. Also, for evaluating the error correction performance of the system, the channel was emulated by adding Additive White Gaussian Noise (AWGN) to the input. This has been used to compute the Bit Error Rate (BER) of the system, compared with the ideal BER given by the standard [36]. In this case, the input of the system was computed as a well-known Pseudo-random Noise sequence (PN23) [37]. To describe the performance of the system, the implementation choice for the development of the SCCC decoder will be taken into account. For the other modules, indeed, the parallel GPU implementation has been demonstrated to be enough to optimize the execution of the receiver. The achieved results will be analyzed step-by-step while investigating the added optimization of the code (e.g., Jacobian logarithm approximation, windowing). Regarding the speed performance of the system, it has been compared with the aforementioned SW EGSE [19], but also with two other systems which have been implemented for reference, referred to as _Matlab Script_ and _Serial Process_. The Matlab Script is a system implemented on Matlab, modeled on the SW EGSE, but excluding the debug options, to optimize the computation. The serial process was implemented in C++, without exploiting parallel computation. It is the same version of the receiver where each module is executed on a CPU instead of a GPU. As explained before, this implementation has been possible without additional effort, thanks to the use of the Factory Method Design Pattern. Both the Matlab and the C++ solution were executed on the same CPU used for the SDR receiver (i.e., Intel Core i9-12900K). For the implemented GPU receiver, three different versions have been developed, optimizing the system at each step. In particular, the first system, referred to as _GPU1_, is the first developed system, where the code is optimized only for parallel execution on a GPU. The second system (_GPU2_) has been optimized by an efficient use of the GPU memory and by introducing the approximation of the Jacobian logarithm, while the third system (_GPU3_) has been further optimized by implementing windowing, with a variable number of windows, based on the applied ACM. The three distinct GPU receiver implementations have been compared, demonstrating not only the performance increase over the state-of-the-art receiver, but also the performance improvement across the various implementations. To comprehensively evaluate the speed performance of the system, the NVIDIA CUDA profiling tools have been used [38]. This has allowed for not only the evaluation of the speed of each single developed module, but also for the evaluation of the GPU memory occupancy and read/write operation, to optimize the code. To evaluate the error correction performance of the system, the BER was computed, applying AWGN impairment to the input and modifying the applied signal-to-noise ratio (Eb_N0) to produce the so-called BER curves. The BER curves show the decrease in the error rate when increasing the Eb_N0, hence the number of symbols with respect to the noise. BER curves have been computed for all the ACM, considering at minimum a number of 1000 PL frames as input, and for all the GPU implementation, to show the implementation loss introduced by optimizing the code.