# An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System
## 3 The Data Storage and Exchange Method Based on Superscalar Pipeline
### Superscalar Pipeline Ping-Pong Buffer
#### 3.2.2 Data Exchange in Azimuth Direction Based on Superscalar Pipeline  
When performing azimuth access, as shown in Figure 10, one column of data in the figure belongs to one azimuth line; therefore, two data points of the same color in a row belong to two different azimuth lines. The data points of four azimuth lines are designed to be processed at the same time. Therefore, the eight data points in green will be accessed from DDR3A, belonging to four consecutive azimuth lines, and stored in the buffer RAM0-RAM3 corresponding to DD3A. The eight data points in yellow will be accessed from DDR3B, which also belongs to four consecutive azimuth directions, and is stored in the buffer RAM0-RAM3 corresponding to DD3B. After the 16 data points in the four azimuth directions in total are accessed, the other data in the four azimuth directions will be accessed because of the operation in the azimuth direction. After the data in the four azimuth directions in the sub-matrix are all accessed, the adjacent azimuth direction sub-matrix is accessed by azimuth direction. Repeat the operation until all the data points in these four azimuth directions are accessed.  
The following four azimuth direction data points will be accessed when DDR3A and DDR3B continue work simultaneously after the first fourtypes azimuth direction data are accessed and stored in the Ping RAM buffers corresponding to DDR3A and DDR3B. As shown in Figure 10, the eight data points in blue will be accessed from DDR3A, which belongs to four consecutive azimuth directions, while the eight data points in orange will be accessed from DDR3B, which also belongs to four consecutive azimuth directions. The four types of azimuth data will be stored in the Pong RAMs corresponding to DDR3A and DDR3B, and form a pipeline design mode with the Ping RAMs corresponding to DDR3A and DDR3B. At this time, while the Pong RAM corresponding to DDR3A and DDR3B is buffering the four types of azimuth data, the Ping RAM corresponding to DDR3A and DDR3B transfers the four types of azimuth data that have been buffered to the compute core for processing.  
In the traditional three-dimensional cross-mapping method, the eight data points transmitted in a single burst of DDR3 belong to four azimuth data and two range data, which will cause half of the computing engine to be idle during processing in the range direction. However, the eight data points transmitted in a single burst by the method proposed in this paper belong to four azimuth data and four range data, which will make the data access in the range direction and azimuth direction completely balanced. The computing resource utilization in the range direction can reach 100%.  
Figure 9: Schematic diagram of data exchange in range direction based on superscalar pipeline.  
The superscalar architecture pipeline design is shown Figure 11; each DDR3 corresponds to a group of ping-pong RAM buffers, which can form a pipeline independently. Dual-channel DDR3 read and write operations can be executed concurrently through the design of the superscalar pipeline, meaning that read or write operations are performed on both DDR3A and DDR3B simultaneously, increasing the parallelism of data access. This method can result in greatly reduced idle latency in conventional pipelined or non-pipelined designs.