# Soft Error-Tolerant and Highly Stable Low-Power SRAM for Satellite Applications
## 3 Simulation Results and Analysis
### Read and Write Access Time Comparison  
Read access time (RAT) can evaluated with the time interval from when the voltage of the WL reaches 50% of the supply voltage VDD to when the voltage difference between the two bit lines, BL and BLB, reaches 50 mV [17]. It is shown in Figure 4a. Generally, read access time heavily depends on the read current through the access and pull-down transistors and the bit-line capacitance [18]. The excessive use of access transistors results in higher bit-line capacitance than a single access transistor, leading to longer read access times. Furthermore, a higher cell ratio (CR), representing the ratio of the pull-down transistor to the access transistor, tends to result in shorter read access times [19]. Table 1 shows that the proposed RHSP16T structure has the longest read access time among all the cells. During the read operation in the RHSP16T, only the access transistor connected to the internal node was activated, resulting in higher bit-line capacitance than in the cells using a single access transistor. Additionally, the access transistor activated during the read operation was a PMOS transistor with a lower charge mobility than NMOS transistors. This contributed to the longer read access time for the RHSP16T cell during the read operations.  
Write access time (WAT) can evaluated with the time interval from when the WL voltage reaches 50% of the supply voltage VDD to when the storage nodes Q and QB intersect [18]. It is shown in Figure 4b. According to Table 1, the WAT of the proposed RHSP16T is 86.71%, 95.56%, 61.64%, 62.65%, and 63.29% of those of QUCCE12T, WEQUATRO, RHBD10T, RHD12T, and RSP14T, respectively, making it the shortest among all the compared cells. Several factors contribute to this. Firstly, in the proposed RHSP16T, both access transistors connected to each bit line were activated during the write operation, allowing simultaneous flipping of the storage node and internal node values. This process accelerated the write operation compared to cells using a single access transistor [18]. Moreover, the RHSP16T has the lowest pull-up ratios of 0.34 and 0.5 for the two pairs of access transistors. A lower pull-up ratio ensures that the pull-down force exerted by the access transistors discharging to a pre-discharged bit line at '0' was stronger than the pull-up force of the pull-up transistors pulling the node to '1', resulting in a shorter WAT. Furthermore, the RHSP16T uses an NMOS pull-up transistor, which has a weak '1' characteristic, for the storage nodes, making it easier for the access transistors to discharge the weak '1'. Consequently, the proposed RHSP16T achieved the shortest WAT, allowing for faster writing of new signals.  
\begin{table}
\begin{tabular}{c c c c c c c c} \hline
**Structure** & **Qc** & **RAT** & **WAT** & **RSNM** & **WWTV** & **Hold Power** & **Relative** \\
**Name** & **[fC]** & **[ps]** & **[ps]** & **[mV]** & **[mV]** & **[nW]** & **Area** \\ \hline WE\_QUATRO [10] & 16.46 & 32.25 & 35.27 & 106.10 & 412.28 & 50.91 & 0.62 \\ \hline QUCCE12T [11] & 16.76 & 31.38 & 35.54 & 129.41 & 408.41 & 53.47 & 0.67 \\ \hline RHBD10T [12] & 13.34 & 24.55 & 50 & 171.99 & 340.24 & 66.51 & 0.57 \\ \hline RHD12T [13] & 23.52 & 30.59 & 49.19 & 156.09 & 401.29 & 70.22 & 0.74 \\ \hline RSP14T [14] & 24.61 & 29.49 & 48.69 & 151.59 & 401.14 & 70.22 & 0.78 \\ \hline This Work & \textgreater{}100 & 50.06 & 30.82 & 272.69 & 499.07 & 51.91 & 1.00 \\ \hline \end{tabular}
\end{table}
Table 1: Performance comparison at VDD = 1 V.  
Figure 4: Measuring methods: (**a**) RAT, (**b**) WAT, and WWTV.