## 3 Prototype Design
### Hardware Components  
The essential hardware components of the on-board sensor are:  
1. the GNSS antennas,
2. the commercial off-the-shelf (COTS) RF front-ends (FEs) and
3. the digital signal processing (DSP) stage. Figure 2 shows the functional block diagram of the sensor, with the major hardware components highlighted and their connections. While a conventional low-cost hemispherical GNSS L1 RHCP patch antenna, properly mounted to point to the zenith and normally available on-board, is enough to receive the direct GNSS signals, the reflected ones require an _ad hoc_ antenna oriented toward the nadir. Since one of our purposes was the reception of the reflected signals with both polarizations (LHCP + RHCP), we preferred a single dual-polarization antenna instead of two separate single-polarization ones, in order to limit weight and volume. However, very stringent requirements were set against the level of cross-polarization isolation, which represents a measure of the cross-talk between the two nominal polarizations. The work in [18] suggests a value lower than \(-24\) dB, in particular for the measurement of the very weak RHCP component of the reflected signals against the stronger LHCP component. Unfortunately, commercial products typically do not meet both requirements of weight and cross-polarization isolation. Nonetheless, we decided to adopt the dual-polarization L1/L2 GNSS Antcom antenna 1G1215 RL-PP-XS-X RevA [24], whose cross-polarization isolation declared by the manufacturer is \(-17\) dB; despite its suboptimal performance in polarization separation to perform precise GNSS-R polarimetric measurements [18], it is light, small and has a quite flat profile. Another custom Antcom device based on the G8 ANT-52A4 SC1-RL model, whose cross-polarization rejection specification was set at \(-24\) dB, showed RF compatibility problems with the front-end and cross-polarization issues, making its use more difficult and even having lesser performance. The second stage of the hardware platform is the RF front-end. It includes the stages of signal conditioning, RF down conversion, filtering and analog-to-digital conversion (ADC). The number of RF chains in the FE must be equal to the number of separate signals and polarizations: one RF chain is employed for the direct signal and connected to the zenith-pointing antenna, while two RF chains are devoted to the two LHC- and RHC-polarized reflected signals and connected to the two ports of the nadir-pointing antenna. The same clock reference must be distributed on the three chains. To implement this setup, two FEs of the \"Stereo\" family commercialized by Nottingham Scientific Ltd (NSL) were selected [25], configured in a master/slave architecture. Each FE embeds two full and synchronized receiving chains, implemented in two separate chipsets: the MAX2769B, covering the GNSS upper L-band and indicated as L1, and the MAX2112, covering both the upper and lower L-bands and indicated as LB. In Figure 2, we identified the two chains as \"Channel IF\" and \"Channel BB\" respectively, to indicate the different down conversion schemes applied in the two chains. The FE contains one shared clock (TXC 26 MHz TCXO) with interfaces for alternative oscillators and external frequency input. Slaving two FEs to the same clock guarantees four synchronized channels. To do this operation, a logic level translator, from low voltage positive emitter coupled logic (LVPECL) to  
to low voltage complementary metal oxide semiconductor (LVCMOS) levels was specifically designed and manufactured as a printed circuit board (PCB). In Figure 2, the exact connection between antennas and FE chains is indicated: the direct signal is split and sent to Channel BB of both the FEs as a reference, while the reflected LHCP and RHCP are connected to the Channel IF of the master and slave boards, respectively. Finally, a DSP stage is necessary to process the digital data after the ADC.