## 2 Design and Implementation  
### SoC Design  
Figure 2 shows the overall block diagram of the iTDS-2 with the TDS-UI and target applications. The iTDS-2 consists of four 3-axis magnetometers (HMC1043, Honeywell, Golden Valley, MN, USA) measuring the magnetic field generated by the magnetic tracer on the tongue, a FPGA generating digital control signals, and a system-on-a-chip (SoC) that amplifies, filters, digitizes, and wirelessly transmits the sensor data. The TDS-UI receives the raw magnetic sensor data from the iTDS-2, processes the data, and classifies it into user-defined commands that are delivered into target devices, such as a computer or a powered wheelchair. Figure 3 shows the detailed block diagram of the iTDS-2 SoC that is architecturally similar to the iTDS-1 SoC in analog front-end (AFE), dual-band Tx, and power management (PM) blocks. The iTDS-2 also employs several new circuit blocks over the iTDS-1, such as a 13-bit SAR ADC and a SR-Rx. The AFE in the iTDS-2 employs four gain steps (25, 50, 100, and 200). A current-feedback instrumentation amplifier (CFIA) is followed by a pseudo-RC low-pass filter and a differential amplifier, similar to [32]. The CFIA is equipped with offset cancellation, an auto-zeroing scheme, and a correction current that is applied accordingly to balance the CFIA until the next readout [32]. The 27 MHz carrier  
Figure 3: Detailed block diagram of the iTDS-2 system-on-a-chip (SoC). Figure 2: Overall system block diagram of the iTDS-2 including the TDS-UI and target devices. is generated by an internal oscillator circuit that has a 27 MHz off-chip ceramic crystal, and the 432 MHz carrier is generated by nine voltage-controlled delay cells in a dual-loop DLL that has a 48 MHz off-chip ceramic crystal. The class-C power amplifier generates on-off-keying (OOK) or frequency-shift-keying (FSK) outputs at 27 MHz, while the edge combiner operates as a nonlinear amplifier to generate OOK or FSK outputs at 432 MHz [12]. The PM block consists of voltage regulators, data telemetry, and battery charging circuits. The data telemetry block has bidirectional capability. Forward data telemetry consists of data and clock recovery circuits, while back telemetry consists of a load-shift-keying (LSK) mechanism built into an active rectifier [33]. Details of the AFE, Tx, and PM blocks can be found in [12]. While the iTDS-1 used the ADC built in the MCU, the iTDS-2 has an on-chip 13-bit SAR ADC to reduce power consumption and loading effect on the AFE output stage. The SAR ADC operates at 1024 Hz and employs noise shaping and foreground digital calibration schemes, to decrease the digitization noise by pushing it out into a higher frequency band and to minimize the effects of capacitor mismatch, respectively [34,35]. For noise shaping, the residual charge at the end of each conversion process is delivered to the next conversion stage, using the switched capacitor connected in parallel to the capacitor bank [34]. For calibration, the residual voltages are digitized by the ADC itself and the capacitor mismatches are calculated accordingly. The calibration results are stored in the microprocessor of the TDS-UI to correct the capacitor mismatch in advance [36]. The SR-Rx was added to the iTDS-2 to overcome the limitation of the one directional communication in the iTDS-1, and to improve the system robustness. The SR-Rx is designed to detect the 27 MHz carrier and recover the OOK-modulated data up to 5 kbps. Figure 4a shows the SR-Rx implemented with an isolation amplifier, a 27 MHz quench-controlled oscillator, a Schmitt trigger, and part of the FPGA. Because of the power constraint in the iTDS-2, the SR-Rx incorporates a digitally-assisted self-quenching architecture, which reduces the power consumption by turning off the oscillation following each bit [37]. The FPGA counts the number of oscillations and turns off an oscillator faster than the conventional analog self-quenching architecture using a peak detector [38].