# Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices
## 3 NAND Flash Memory Reliability
### Endurance  
This parameter specifies the maximum number of program/erase (P/E) cycles \(N_{C}\) that the memory chip can tolerate. The onset of this limitation can be observed by repeating simple, single-pulse P/E operations on a cell and monitoring the resulting \(V_{T}\). An example of such a dependence in a NAND device is shown in Figure 3[63]: the \(V_{T}\) levels experience an increase for high values of \(N_{C}\), eventually leading to a read failure. Higher increase is usually observed on the erased level. Like most reliability concerns for Flash memories, this phenomenon is one consequence of the electron flow through the oxide during FN tunneling, which has been observed to generate oxide traps and fixed charge in MOS (Metal-Oxide-Semiconductor) devices since the 1980s [64; 65; 66; 67; 68; 69]. At first glance, such charges should result in a constant shift of both \(V_{T}\) levels, while the actual behavior features a milder dependence on \(N_{C}\) by the programmed \(V_{T}\) with respect to the erased one, pointing toward an interplay among different mechanisms. This picture is confirmed by early results on different non-volatile memory technologies, where different P/E schemes (i.e., different electron injection conditions into the oxide) resulted in different \(V_{T}\) dependences on \(N_{C}\)[70]. A thorough analysis of the phenomenon was first conducted in [71], using charge-pumping and \(V_{T}\) measurements to assess the roles of interface and oxide charges, and was later corroborated by subsequent studies [72]. The authors' conclusion was that trapped oxide charge should not influence the programmed \(V_{T}\) value because tunnel injection from the channel during the program pulse is controlled by the oxide field at the cathode interface, meaning that the final condition reached by the cell will be of equal field, irrespective of the starting \(V_{T}\) and trapped charge (if not too close to the cathode interface). In turn, the same oxide field at the channel interface means the same final \(V_{T}\), explaining the experimental behavior of a nearly constant programmed \(V_{T}\) level. Simply put, as trapped negative oxide charge builds up, it reduces injection, giving a negative \(V_{T}\) shift that is balanced by the positive \(V_{T}\) shift given by the charge itself. This \"converging\" behavior of the FN tunneling operation has been in fact exploited to tighten the \(V_{T}\) distribution after erase [73]. The same reasoning holds for the erase operation, but now the final condition is the one with the same field at the oxide-floating gate interface (the cathode during erase), which does not translate into the same \(V_{T}\), now dictated by the oxide trapped charge: a larger increase in \(V_{T}\) vs. \(N_{C}\) is then expected. This model was then refined [63] to include the effect of charged stress-generated interface states, that provide an additional positive \(V_{T}\) shift for both levels (while not influencing injection) for high cycling conditions, explaining the slight increase in the programmed \(V_{T}\). Finally, the effect of non-uniform tunneling current flow and oxide charge distribution over the area of scaled NAND devices have been investigated in [74; 75], pointing out their effect on the endurance curve and on the assessment of the endurance degradation with scaling. A recent technique for separating the endurance degradation components, including subthreshold slope and transconductance, which also influence the \(V_{T}\) values, has been reported in [76]. From the product viewpoint, the \(V_{T}\) window degradation is managed by the program and verify ISPP algorithm, meaning that any variation in the P/E characteristics of the cell will result in a change in the number of ISPP pulses. Eventually, when--say--the number of erase pulses will become higher than the maximum allowed by the erase time specifications, an erase failure will be signaled.