## 4 Experimental Verification
### Testing Results and Analysis  
First, the items of parallel applications without saturation were analyzed, and the related results are shown in Figure 16,c. To validate the strategy without saturation in parallel applications, \(n\) was set to 8 to guarantee that the peak current was no higher than \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Communication** & **Transmission** & **Reception** & **Involved Variables** \\ \hline \multirow{4}{*}{CAN} & DSP\#1 & DSP\#2 & \(i_{\text{sum}}\), \(SoC_{i}^{n}\), \(SoC_{i}^{n}\), \(i_{\text{dcr}}\) \\  & DSP\#2 & DSP\#1 & \(SoC_{i}^{2}\), \(SoC_{i}\), \(i_{2}\) \\  & DSP\#1 & DSP\#3 & \(i_{\text{sum}}\), \(SoC_{i}^{n}\), \(SoC_{i}^{n}\) \\  & DSP\#3 & DSP\#1 & \(SoC_{i}^{n}\), \(SoC_{3}\), \(i_{3}\) \\ \hline \multirow{2}{*}{RS232} & Labview & DSP\#1 & \(u_{\text{ref}}\) \\  & DSP\#1 & Labview & \(u_{\text{dc}}\), \(i_{1}\), \(i_{2}\), \(i_{3}\) \\ \end{tabular}
\begin{tabular}{c c c} \hline \hline
**\(SoC_{1}\)**, \(SoC_{2}\)**, \(SoC_{3}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Communication variables. Figure 14: Schematic diagram of experimental platform. Figure 15: Photo of experimental platform. \(i_{\rm satu}\). To ensure that \(u_{\rm dc}\) was constant, the phase currents were set to gradually increase as a result of a declining SoC and increasing inner resistances. The equilibrium point was reached at 3800 s. Subsequently, \(i_{\rm satu}\) was adopted to accelerate the convergence of the balancing process, and \(n\) was increased to 50. The required time was about 1450 s according to Figure 17a,c. This corresponds to time savings of around 62% when current saturation is applied. After that, the experiment conducted under variable load (\(n=50\)) was carried out. As Figure 17b displays, the load current was suddenly reduced by half at \(t=200\) s, while it returned to 20 A after a duration of 800 s. According to the testing data, equal SoC levels and currents were still realized, although the balanced point is delayed somewhat. Figure 16: Experimental curves without saturation: (**a**) currents in parallel applications, (**b**) currents in series applications, (**c**) SoC in parallel applications, and (**d**) SoC in series applications. Figure 17: Experimental curves using saturation in parallel applications: (**a**) currents during normal operation, (**b**) currents under load change, (**c**) SoC during normal operation, and (**d**) SoC under load change. After that, the series application experiments were performed, and the corresponding outcomes are described in Figure 16b,d. To ensure that phase currents are between \(i_{\text{satur}}\) and \(i_{\text{satur}}\), the proper value of \(n\) should be 5. Based on Figure 16b,d, it takes as long as 5630 s to accomplish SoC equalization and current balance without saturation because only a small \(n\) is utilized. To reduce the balancing time, current saturations were put into use. Figure 18 gives the testing results for when \(i_{\text{satur}}\) is 24 A and 33 A, respectively. In terms of the requisite seconds, there is no obvious difference. However, voltage fluctuation exists when \(i_{\text{satur}}\) is 33 A because excessive \(i_{\text{satur}}\) leads to a step change in the current reference. In contrast, a steady voltage can be maintained when \(i_{\text{satur}}\) is 24 A. To check the performance regarding variable \(i_{\text{satur}}\), tests of load change were executed, and the results are shown in Figure 19. Fixed saturation of the step current reference may be not escapable even if it is elaborately designed. The original condition for preventing step change may no longer be satisfied, as the trajectories of the currents have altered (more or less). If the upper limit varies in proportion to the sum current, the abovementioned condition is always realizable, and Figure 19b gives proof for this.