# Analysis of Pre-Driver and Last-Stage Power--Ground-Induced Jitter at Different PVT Corners
## 2 Methodology: PSIJ under PVT Comers and Jitter Sensitivity  
In order to accurately predict the PSIJ by the IO circuit, it is crucial to provide the accurate model representation of the PDN, the current switching due to data pattern activity and the jitter sensitivity. The combinations of these three inputs are illustrated in Figure 3, which presents the generic frequency modelling approach of the PSIJ in the frequency domain. In fact, the resulting supply noise spectrum (i.e., \(V(f)=Z_{PDN}\left(f\right)\times I(f)\) from Equations (1) and (2)), is multiplied by the jitter sensitivity, \(S(f)\), \(\left[\text{ps mV}^{-1}\right]\), to yield to the jitter spectrum \(J(f)\). \[J(f)=V(f)\times S(f) \tag{4}\]  
The examples of the PDN impedance profile modeling methodologies and extraction are shown in [17; 18]. Current switching profiles can be simulated based on transient simulation or estimated at the early design stage [18]. The noise-to-jitter transfer function sensitivity is determined by characterizing the IO buffer under PGSV noise and measuring the output eye jitter. It is worth noting that the jitter sensitivity profile only depends on the intrinsic transistor-based circuit implementation of the IO buffer. Once the jitter spectrum is obtained, the time domain jitter is formed by applying an inverse of Fourier transform to determine the jitter in time domain. This methodology can be applied both in the pre-layout and/or post-layout phase of the circuit and PDN design because it helps the system on chip (SoC) design team to figure out the necessary on-die and package decoupling capacitor requirements, along with PCB/package inductance, leading to an acceptable supply noise profile and jitter that can be tolerated by their system. Since a distorted sinusoidal waveform is typically induced at the PGSV, the jitter sensitivity function to supply noise frequency, \(S(f)\), can be determined via transient simulation by sweeping the frequency of the voltage noise over the frequency range of interest at which the device is more sensitive to the jitter. Nevertheless, the derivation of the simulation data and setup is time consuming and requires high computational resources. Another theoretical approach that has led to an analytical approximate solution for open-loop circuit paths is proposed to model the frequency-dependent sensitivity of jitter  
Figure 3: Block diagram illustrating the variables contributing to PSIJ generation. by characterizing the IO buffer delay difference at two different bias voltages. \(S(f)\) can be identified straightforwardly by the following analytical method [19; 20]. \[\left\{ \begin{aligned} S(f)&=\frac{j}{2\pi f\tau_{d}}S_{0} \Big{[}1-e^{-j\pi f\tau_{d}}\Big{]}\\ S_{0}&=\frac{TD\
u_{1}-TD\
u_{2}}{V_{2}-V_{1}}\end{aligned} \right. \tag{5}\]  
\(S_{0}\) is the DC delay sensitivity, which is determined by the static delay difference of the \(TD_{V1}\) and \(TD_{V2}\) at their respective dc voltages, \(V_{1}\) and \(V_{2}\), respectively, as illustrated in Figure 1. \(\tau_{d}\) is the sub-circuit path delay. Therefore, the jitter sensitivity magnitude can be expressed as follow:  
\[|S(f)|=S_{0}\Big{|}\frac{\sin(\pi f\tau_{d})}{\pi f\tau_{d}}\Big{|}=S_{0}| since(\pi f\tau_{d})| \tag{6}\]  
The jitter prediction methodology in the frequency domain of Figure 3, which is either based on simulation data or the analytical theoretical approximation of the PSIJ sensitivity, assumes that the supply ripple noise is regarded as perturbation and thus it is behaving as a small signal with respect to the operation point of the driver's circuit IO stages (i.e., pre-driver and last stage). Therefore, the jitter sensitivity is assumed to be independent of the supply noise amplitude. However, the PSIJ flow and jitter sensitivity cannot be considered as a linear-time-invariant system because the validity range of the linear approximation depends on supply voltage and IO buffer PVT corners [20].