## 2 FM-ACSK Communication System
### Timing Recovery  
Since the communication between the transmitter and receiver in real-world scenarios will have an undefined delay (depending on distance and other factors), the receiver cannot immediately know where a single transmitted symbol begins and ends (in the current system, there is one data bit per symbol). This problem is usually solved using a timing error detector (TED). TEDs detect and correct timing mismatches by evaluating the incoming signal and adjusting the receiver's timing to align with the transmitted signal. Most common TEDs [24] include such decision-directed methods as Zero-Crossing and Mueller-Muller, and such non-data-aided feedback methods as Gardner and early-late gate. While decision-directed TEDs rely on estimated symbols and prior knowledge about data content, non-data-aided TEDs do not require any knowledge of the transmitted data; hence, they are more versatile for initial or blind synchronization. These TED methods are mainly designed for conventional digital communication schemes. In the present chaotic digital communication system, the receiver can use information on the fixed symbol length (8192 samples at 50 MHz clock) and the nature of the Async (see Figure 2) signal at the output of the ACSK demodulator, which correlates with the values of transmitted data bits. This information is sufficient to implement blind synchronization of the bit timing phase using the simple early-late gate method. The early-late gate TED method application principle in the context of the Async signal example is shown in Figure 8. Two gates are accumulators, which integrate the first and second halves of the Async signal relative to the half-periods of the assumed clock. The assumed clock's period, without any phase adjustments, is equal to the symbol length of 8192 samples. If the assumed clock timing matches the symbol bit timing in the Async signal, the difference between both accumulators will be close to zero; therefore, symbol timing phase synchronization is established. However, if the phase of the assumed clock does not match the symbol timing, there will be a notable difference between the values accumulated in both gates. The sign of this difference shows the direction of the timing shift, and the absolute value of this difference can be correlated to the magnitude of the correction shift that should be applied to the assumed clock timing phase. The obtained timing error is used in a controlled feedback loop to modify the assumed clock phase and, with each cycle iteration, bring it closer to the actual symbol timing. After achieving the symbol phase synchronization, the early-late gate synchronizer will continue to track and slightly adjust the timing phase during the entire duration of the data transmission. The example is shown for the specific case, when bit \"1\" is between bits \"0\". As the absolute values of gate's accumulated signal are compared, in the case of opposite bit values, this TED will work the same way. The early-late gate TED will also work in cases when data transition from \"0\" to \"1\", or the opposite, occurs only on one side of the gates' period, but with less efficiency. And finally, when there is no data bit transition (where a sequential \"1\" or \"0\" is transmitted), the early-late gate synchronizer will not be able to obtain information about the timing error and the assumed clock will not be significantly shifted. For this reason, communication in such a system should start with alternating bits, which speeds up symbol phase synchronization and, therefore, reduces the bit error rate probability. A conventional early-late gate symbol timing synchronizer design [25] was adapted, considering the requirements of the FM-ACSK communication system and the FPGA implementation. The symbol phase synchronizer was initially built in the Simulink environment, using a fixed-point approach, and implemented into the VHDL code with the assistance of the HDL Coder toolbox. The developed design is explained further.