# Low-Power Two-Phase Clocking Adiabatic PUF Circuit
## 2 Fundamental Adiabatic PUF  
### Principle of Adiabatic Switching  
Adiabatic switching is commonly used to minimize the energy loss during charging/discharging process [25]. During adiabatic switching, all nodes are charged or discharged at a constant current to minimize the power dissipation. This is accomplished using AC power supplies that initially charge the circuit during specific adiabatic phases and then discharge the circuit to recover the supplied charge. The principle of adiabatic switching can best be explained by comparing the internal equivalent RC model for charging and discharging the output load capacitance, as shown in Figure 1a,b, for conventional CMOS and adiabatic switching, respectively. The difference between the adiabatic switching and conventional CMOS RC model is that the latter uses the step voltage of Vdd, whereas the former uses a power clock signal as the source voltage in which the ramped step voltage gradually increases (indicated by \(\tau\)), as shown in Figure 1b.  
Applying the Kirchhoff voltage law (KVL) to the circuit in Figure 1a,b, the charging network of the conventional CMOS is expressed as follows:  
\[Ri(t)+\frac{1}{C}\int_{0}^{\tau}i(t)dt+\mathbf{v}(0_{-})=\mathrm{V_{dd}} \tag{1}\]  
and the charging network for adiabatic switching is expressed as  
\[Ri(t)+\frac{1}{C}\int_{0}^{\tau}i(t)dt+\mathbf{v}(0_{-})=\frac{\mathrm{V_{dd}}}{ \tau}t \tag{2}\]  
where \(\tau\) is the rising time of the ramp voltage Vdd. The Laplace transform and inverse Laplace transform are employed to obtain the charging current for CMOS logic and adiabatic logic, as expressed in Equations (3) and (4), respectively.  
\[i(t)=\frac{\mathrm{V_{dd}}}{R}e^{-\frac{1}{RC}t} \tag{3}\]  
\[i(t)=\frac{\mathrm{V_{dd}C}}{\tau}(1-e^{-\frac{1}{RC}t}) \tag{4}\]  
The peak current difference shown in Equations (3) and (4) indicate a large area and sudden flow of current in the conventional CMOS. In addition, a gradual increase in the supply current peak of the adiabatic switching can be observed in Figure 1c.  
From the energy consumption perspective, the dissipated energy over the period \(t=0\) to \(t=\tau\) is expressed as follows:  
\[E_{diss}=\int_{0}^{\tau}Ri^{2}(t)dt+E(0_{-}) \tag{5}\]  
Figure 1: Comparison of the supply current transitions for the equivalent RC models of the (**a**) CMOS logic step voltage and (**b**) adiabatic logic ramped step voltage. (**c**) The peak supply current of the adiabatic logic is significantly lower than that of the conventional CMOS logic under the same parameters and conditions.  
Substituting the current \(i(t)\) from Equations (3) and (4) into Equation (5), we obtain the energy stored in the capacitor for the conventional CMOS and adiabatic switching, as expressed in Equations (6) and (7), respectively.  
\[E_{CMOS}=\frac{1}{2}\text{CV}_{\text{dd}}^{2} \tag{6}\]  
\[E_{Adiabatic}=\frac{RC}{\tau}\text{CV}_{\text{dd}}^{2} \tag{7}\]  
Equations (6) and (7) clearly show that the dissipated energy of the conventional CMOS (Equation (6)) depends on the values of C and Vdd, while that of the adiabatic logic depends on the switching time \(\tau\). Hence, by increasing the switching time (where \(\tau>RC\)), the energy dissipation of adiabatic logic is significantly lower than that of the conventional CMOS logic.