# A Tile-Based Multi-Core Hardware Architecture for Lossless Image Compression and Decompression
## 1 Introduction  
Efficient image compression and decompression algorithms are considered essential for managing the increasing volume of image data across various domains, including multimedia [1, 2], medical imaging [3, 4], and surveillance systems [5, 6, 7]. These applications require high-throughput and low-latency solutions to support real-time performance and data transmission. To meet these demands, hardware-accelerated lossless compression and decompression algorithms have become increasingly critical. Conventional techniques such as BPG [8], CALIC [9], and PNG [10], though effective in software environments, are often constrained in hardware due to their strong dependence on algorithmic parameters. This dependence makes the effective use of pipelining difficult, thereby limiting their scalability on hardware platforms. Lightweight hybrid compression algorithms, such as JPEG-LS [11], have emerged as promising alternatives. Recognized for their compression efficiency and relatively low computational complexity, these methods have been widely adopted in FPGA implementations [12; 13; 14; 15; 16; 17; 18]. Earlier foundational research by [PERSON] et al. [16] introduced modifications to the run-length coding mode in JPEG-LS, successfully reducing algorithmic complexity, though only modest gains in processing speed were realized. [PERSON] and [PERSON] [17] explored pipelining for JPEG-LS, but their design was limited to clock frequencies of approximately 21 MHz for the encoder and 16 MHz for the decoder. Subsequent efforts focused on boosting throughput. [PERSON] and [PERSON] [18] demonstrated a fully pipelined JPEG-LS encoder capable of achieving 120 Mpixels/s, marking a substantial advance in real-time image compression capabilities. To further improve the trade-off between performance and resource usage, [PERSON] et al. [14] proposed a hardware/software co-design utilizing pixel-level parallelism and a pseudo-lossless compression approach. However, this method increased cache requirements and slightly reduced compression efficiency. Similarly, in the works of [PERSON] et al. [15], pipeline implementations addressed data and structural hazards primarily through stalling, a limitation caused by the algorithm's inherent dependence on sequential parameter updates. More recently, [PERSON] et al. [12] introduced an adaptive pipelined architecture that improves parameter update management, enhances context modeling, and supports block-level parallel processing. This design achieved an operating frequency of 108.6 MHz and a throughput of 43.03 Mpixels/s, offering a more balanced and efficient implementation suitable for FPGA-based platforms. As a result, the throughput achieved by these systems is still insufficient to meet the demands of modern high-speed applications. To overcome these limitations, hybrid compression strategies more suitable for FPGA acceleration have been explored [19]. By leveraging the parallel processing capabilities of hardware, higher processing speeds can be achieved. In this study, a hybrid image compression and decompression algorithm is reviewed and optimized for hardware implementation. The algorithm integrates run-length coding [20], predictive coding [21], and a non-coding mechanism. These techniques are selectively applied based on the characteristics of the image data, enabling effective compression across various image types while maintaining lossless fidelity. A tile-based strategy is adopted in the algorithm, where input images are divided into smaller regions for independent compression and decompression. This approach enables hardware support for multi-core operation, allowing multiple processing cores to handle image tiles in parallel. A multi-core system architecture is proposed, where up to eight tiles can be processed concurrently. The algorithm is designed with low dependency on specific parameters, making it well suited for pipelined acceleration. As a result, a four-stage pipeline is applied in the compression process.