# Three-Level Hybrid Envelope Tracking Supply Modulator with High-Bandwidth Wide-Output-Swing
## 3 Circuit Design
### Control Loop  
The logic control circuit connects the linear stage and the switching stage. Through the adjustment of the control circuit, the output current of the LA and SWR is reasonably arranged to maximize the efficiency. The control loop in this paper consists of high-speed hysteresis comparators and logic gate circuits, as shown in Figure 10. The output voltage \(V_{O\_LA}\) of LA determines which path is used (0 \(<V_{O\_LA}<V_{DD}/2\) selects the logic path Ctrl-A, \(V_{DD}/2<V_{O\_LA}<V_{DD}\) selects the path Ctrl-B). The current detection resistor R\({}_{\text{SEN}}\) connects the LA and the output terminal, and the voltage of R\({}_{\text{SEN}}\) is V\({}_{\text{sense}}\). The simplified representation is shown in Table 2 (the Result column corresponds to Table 1), and the control logic analysis is as follows:  
1. Ctrl-A: When I\({}_{\text{SW}}\) > I\({}_{\text{L}}\), I\({}_{\text{LA}}\) absorbs excess current, the sinking LA current increases, the output of the A1 comparator is high, and the output of P1N1 and P2N2 is high, resulting in the decrease in I\({}_{\text{SW}}\) and I\({}_{\text{LA}}\). Due to the decrease in I\({}_{\text{SW}}\), the sourcing current of I\({}_{\text{LA}}\) increases, and the output of A1 is low. At this time, when V\({}_{\text{CF}}\) is lower than \(V_{DD}/2\), the output of A2 comparator is high, resulting in P1N1 being low and P2N2 being high, increasing I\({}_{\text{SW}}\). When V\({}_{\text{CF}}\) is higher than \(V_{DD}/2\), the A2 comparator output is low, resulting in P1N1 high and P2N2 low, which also increases I\({}_{\text{SW}}\).
2. Ctrl-B: the sourcing current of I\({}_{\text{LA}}\) increases, the output of the A1 comparator is low, and the output of P1N1 and P2N2 is low, increasing the I\({}_{\text{SW}}\). If I\({}_{\text{SW}}\) is higher than the load current I\({}_{\text{L}}\), I\({}_{\text{LA}}\) will absorb the excess current. Like ctrl-A, it repeats the above operation.  
Summarizing the above analysis, if the sinking LA current increases, the output of the A1 is high, P1N1 and P2N2 are not in low state at the same time, the corresponding V\({}_{\text{SW}}\) will not be \(V_{DD}\). Similarly, if the sourcing LA current increases, the output of the A1 is low, P1N1 and P2N2 are not high at the same time, the V\({}_{\text{SW}}\) will not be GND. Figure 11 is the simulation result of the control circuit, which verifies the above analysis.  
Figure 11: The logic results of control loop: (**a**) A1 output is high; (**b**) A1 output is low.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Input** & **Comparator State** & **Result** \\ \hline \(0<V_{O,LA}<V_{DD}/2\) & A1: high & & Case: 1 \\ \cline{2-3} (Ctrl-A) & A3: high & A1: low & A2: high & Case: 2 \\ \cline{2-3} \(V_{DD}/2<V_{O,LA}<V_{DD}\) & A1: low & & Case: 4 \\ \cline{2-3} \(V_{DD}/2\) (Ctrl-B) & A1: high & A2: high & Case: 2 \\ \cline{2-3} A3: low & A1: high & A2: low & Case: 3 \\ \hline \end{tabular}
\end{table}
Table 2: Operation of the control loop.  
Figure 10: Circuit structure of the hysteretic control loop.  
The control loop employs high-speed hysteretic comparators (Figure 10). This comparator is different from ordinary comparators in that it adopts a positive feedback loop as shown in Figure 12, which is composed of transistors M1-4. M3 and M4 have the same W/L, and M1 and M2 are the same. The hysteresis width H is related to \(\beta=(\text{W/L})_{3,4}/(\text{W/L})_{1,2}\), and H is changed by adjusting \(\beta\). In this design, the hysteresis width of comparators A1, A2, and A3 are 10 mV, 20 mV, and 50 mV, respectively.