# Method for Improving the Reliability of SRAM-Based PUF Using Convolution Operation
## 4 Implementation Results
### The Results of One-Layer Convolution Scheme  
The one-layer convolution scheme uses a 256 \(\times\) 256 standard matrix. The convolution calculates the sum of the elements in the standard matrix through a 16 \(\times\) 16 convolution kernel. The step size of the convolution is 16. The verification matrix generated is a 16 \(\times\) 16 matrix. Our test data show that about 10% of the SRAM in the CCM area of this chip was unstable. So, the redundancy coefficient was first set to 0.05 according to Formula 3, meaning that the redundancy was 0.05 times the convolution kernel size.  
Using the proposed scheme, the 256 \(\times\) 256 matrix data was convoluted to obtain 16 \(\times\) 16 response information. The absolute address was 0X10000000. The results showed that the 5, 7, 24, 26, 45, 53, 55, 63, 67, 70, 76, 83, 97 groups had errors in their own data. The group with the most errors was the 83 rd group, which had four error positions, as shown in Figure 4. The error numbers of the other groups were all one or two. The total number of errors was 26. It should be emphasized that the outputs of the 100 groups had a total of 16 \(\times\) 16 \(\times\) 100 bits. The reliability of this scheme was 99.8984% when the redundancy coefficient was 0.05.  
The data for the absolute address 0X10005700 had 29 total errors, with a reliability rate of 99.8867%. The absolute address 0X10007000 had 77 total errors, with a reliability rate of 99.6999%. The absolute address 0X1000 ABC0 had 16 total errors, with a reliability rate of 99.9375%. The absolute address 0X1000B000 had 5 total errors, with a reliability rate of 99.9805%. The absolute addresses, total number of errors and reliabilities are shown in Table 2.  
Figure 4: Location and number of errors in one verification.  
Figure 3: The STM32F407 used in the experiment.  
A small adjustment to the redundancy coefficient can improve the reliability of the scheme. The redundancy coefficient was changed to 0.06 and the verification process was performed for the above data again. The results were as follows: For the absolute address 0x10005700, the total error was 2, and the reliability was 99.992%. For the absolute address 0x10007000, the total error was 6, and the reliability was 99.9765%. The reliabilities for all other areas were 100%. When the redundancy coefficient was increased to 0.08, all reliabilities were able to reach 100%. Before initializing the SRAM PUF, it is necessary to adjust the redundancy coefficient for high reliability according to the different types of SRAM.  
The standard result for 0X10000000 was compared with the standard result for 0X10005700 bit-by-bit. A total of 45.7% of the elements in the same position had different values. Ten groups of areas were selected with absolute addresses 0X1000000, 0X1000100, 0X10002000, 0X10003500, 0X10005700, 0X10007000, 0X10009000, 0X1000 ABC0, 0X1000B000, 0X10004A00. The inter-chip HD is shown in Figure 5. The average inter-chip HD for all data was 50.8073%. The standard outputs generated were around 50%, which means that the scheme exhibited good uniqueness.