## 5 Results and Discussion
### Result Comparisons  
Table 4 lists the area utilization for creating RO and metric comparison of RO-PUFs. The previous works improved the PUF quality by using different techniques [12; 28; 30; 49], such as applying gray code to the counter value [12]. This study compares LUT utilization for implementing ROs, where this work requires 150 LUTs, which is the least compared to other works with higher LUT utilization. As a comparison for \(r_{b}=28\), and by assuming RO or counter fits onto one LAB, the proposed structure would require 8 LABs for ROs + 8 LABs for counters + 28 of 2-to-1 MUXs. Meanwhile, in the conventional design [29], in contrast, it would require 56 LABs for ROs + 2 LABs for counters + 2 of 28-to-1 MUXs. Then, by assuming the resource for MUXs is equal, the conventional structure requires 58 LABs, while the proposed method is about 16 LABs. Furthermore, the CRP of the proposed structure is independent, which means it could be realized outside the FPGA chip to enhance response bits. From this work, additional gates are required for realizing other circuits. Upon implementation of RO-PUF onto Cyclone V, this work requires 702 ALMs plus 794 registers. However, most of the utilized gates are due to control circuits. Upon realization of a fixed runtime, area utilization may be reduced. An additional area is required for CRP generation; however, the total area occupied is less than 5% (DE1-SoC) and 7% (DE0-Nano). The design would draw approximately 420 mW of static power, as estimated using the Power Analyzer Tool (available in Quartus). Comparing RO-PUFs, this study did not classify or identify the impact of aging, which may shift the frequency [53; 54; 55]. For instance, a high-temperature setup and its duration for extracting data from chips may degrade the frequency--this work extracts a frequency at a temperature no higher than 50 \({}^{\circ}\)C. In general, the result of this work is better compared to the previously proposed methods using a similar platform (Altera), and the performance \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & **ROs (LUTs)** & **Uniqueness (\%)** & **Reliability (\%)** & **Uniformity (\%)** & **Platform** \\ \hline [PERSON] et al. [20], 2007 & 1024 (6144) & 46.15 & 99.52 & - & Xilinx \\ [PERSON] et al. [21], 2009 & 256 (1280) & 35.91–45.90 & - & - & Xilinx \\ [PERSON] et al. [49], 2010 & 129 (-) & 43.40–48.51 & 99.20,98.28 & - & Xilinx \\ [PERSON] et al. [40], 2011 & 64 (3008) & 32, 41 & 99.29 & - & Xilinx \\ [PERSON] et al. [30], 2011 & 16 (256) & 49.99 –50.07 & \(\pm\)92 \(\pm\) 70 * & 50.02, 49.4 & Xilinx \\ [PERSON] et al. [28], 2013 & 64 (1024) & 6.68 –37.03 & 99.41–82.5 & 50.00, 62.07 & Altera \\ [PERSON] et al. [50], 2013 & 75 (1200) & 47.57 & 90.70 ** & 47 & Altera \\ [PERSON] et al. [12], 2016 & 900 (6300) & 48.42 –48.74 & 98.22, 97.55 & - & Xilinx \\ [PERSON] et al. [31], 2016 & 512 (775) & 49.81 & 96.07 & - & Xilinx \\ [PERSON] et al. [51], 2019 & 11,264 (-) & 49.9 & 97.85–99.80 & - & Xilinx \\ [PERSON] et al. [52], 2020 & 128 (2048) & 49.95 & 91.4–99.13 * & 49.61 & Xilinx \\ This work & 30 (150) & 50.18 * & 99.51 ** & 47.55 & Intel (Altera) \\ \hline \hline \end{tabular}  
* Approximation, *
* Reliability measured in room temperature,
* Pattern-1 (WR2).  
\end{table} 
Table 4: Area utilization for creating RO and metrics comparison of RO-PUFs. Figure 7: Uniformity and its shifts over scenarios. is as good as the latest works implemented onto Xilinx [51; 52]. Upon a similar FPGA platform (Altera/Intel), this work is the first to realized RO-PUF onto Cyclone V (28 nm). In 2012, [PERSON] et al. implemented the ROs using Cyclone II (90 nm) and Cyclone III (65 nm) [26], but there is no performance metric reported. Later, [PERSON] et al. utilized their design onto Cyclone III (65 nm) [50], where the reported uniqueness is slightly closer to the ideal (47.57%) but has poor reliability (90.70%). Later, [PERSON] et al. implemented RO-PUF onto Cyclone IV (60 nm) [28].