# A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier
## 1 Introduction  
The scaling of CMOS technology, and the diffusion of applications requiring very low power consumption, such as IoT (Internet of Things) nodes [1, 2] or biomedical and wearable devices [3, 4], have paved the way to the development of compact and ultralow voltage (ULV) circuits. The operation of MOS devices in the deep subthreshold region is mandatory [5, 6], to achieve ultralow-power (ULP) consumption and to allow the usage of very low supply voltages.  
However, to allow such ultralow supply voltages, specific design approaches are required: floating-gate [7] techniques have been proposed in the past, but the most common solutions are the body-driven (BD) technique and the inverter-based design approach.  
Several amplifier designs operating at supply voltages in the order of 0.6 V or lower and exploiting multi-stage, folded cascode or symmetrical OTA topologies have been presented in the last years. The use of a very low supply voltage often requires to eliminate the bias current generator of the differential pair: the resulting pseudo-differential amplifier shows class-AB behavior, but no common mode rejection if the common mode output is exploited. Moreover, there is no control on the bias current, resulting in large variations of small signal performances under process, supply voltage and temperature (PVT) variations.  
In BD amplifiers [8, 9, 10, 11, 12, 13], the body is used as input terminal instead of the gate, thus allowing the input dc level not to be constrained by the threshold voltage of the devices, at the cost of reduced transconductance gain, higher noise, and an input impedance that is not purely capacitive. In this context, [PERSON] et al. proposed a Miller amplifier designed in 350 nm CMOS process and operating at a supply voltage of 0.6 V in 2007 [8]. [PERSON] etal. published an amplifier with a supply voltage of 0.5 V and 75 nW power consumption in 2014 [10]. In the same year, [PERSON] et al. designed an amplifier with a supply voltage as low as 0.25 V [9]. [PERSON] et al. presented an ULV self-biased amplifier, insensitive to CMOS process variations in 2016 [14]. In 2018 [PERSON] et al. presented bulk-driven 0.5 V amplifiers, exploiting different gain-boosting techniques in 0.18 \(\upmu\)m CMOS process [12]. In 2020 the same authors presented an ULV-ULP class AB amplifier, biased in deep sub-threshold region, that exploits the body-driven non-tailed differential pair [13], attaining state of the art performance in terms of the most important figures of merit.  
Inverter-based solutions [15; 16; 17; 18] exploit the CMOS inverter, or inverter-like structures, such as the Arbel cell [19], as building blocks that allow rail-to-rail signal swing with reduced supply voltages. Moreover, in these structures, the elimination of the bias current generator of the differential pair worsens the common mode rejection (CMRR) and results in large variations of small signal parameters under PVT variations.  
In this paper, we propose an inverter-based, differential, body-driven input stage, with a replica bias loop that accurately sets the common mode current of the input stage by controlling the gate terminals of the MOS devices. The novel input stage is used to build an ULV, ULP, two-stage amplifier, in which a dual path compensation strategy is exploited to improve the frequency response of the amplifier.  
The paper is structured as follows: Section 2 presents the proposed amplifier topology and describes the replica bias loop that sets the common mode current of the inverter based input stage as well as the CMFF technique adopted to improve the CMRR. Section 3 focuses on small signal analysis of dc-gain, CMRR, and frequency response explaining the adopted compensation strategy. Section 4 discusses the design of the amplifier and presents the simulation results and comparisons with ULV, ULP state of the art amplifiers. Finally some conclusions are reported in Section 5.