# SARDIM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging
## 3 SARDIMM: The Proposed NMP Architecture for RDA
### Overview of the Proposed SARDIMM Architecture  
Figure 5 illustrates the system architecture of the proposed SARDIMM. SARDIMM is a rank-level parallel structure, in which one NMP module is inserted per rank. Therefore, the proposed architecture incorporates two NMP modules operating in parallel per DIMM, and the level of parallelism scales with the number of DIMMs. For instance, in the RDA processing of an \(N\times N\) image, an \(N\)-point FFT must be executed \(N\) times. If the system comprises \(M\) SARDIMMs, \(2M\) parallel \(N\)-point FFTs are conducted \(N/2M\) times.  
To operate the NMP module, the host processor must generate and transmit the NMP instructions to the NMP module. The host and memory exchange data via the C/A and the DQ paths. The C/A path transmits commands and addresses, and the DQ path transmits data for reading or writing. The NMP module is located between the host and the memory, and it exchanges data through these two paths. Hence, the NMP instruction must be transmitted through one of these two paths. The instructions must contain sufficient information for the operation, but the C/A path has a relatively small bandwidth; therefore, the amount of information that can be contained is limited. On the other hand, the DQ path has a larger bandwidth than the C/A path and can include a large amount of information. For this reason, previous NMP studies have utilized the DQ path to transmit instructions, ensuring that it includes the necessary operational details [27; 28; 30]. Similarly, SARDIMM employs a standard memory write request to transmit an NMP instruction to the DQ path, where the NMP module that receives the instruction decodes it. Subsequently, the data are read/written in the buffer, and RDA calculations are executed through computational logic in the NMP module.  
Figure 5 shows the architecture of the NMP module responsible for executing RDA operations. The instruction buffer, which is 0.016 KB SRAM, can accommodate up to two NMP instructions. As SARDIMM supports up to 65,536-point FFTs, both the reference signal buffer and the data buffer, each with a capacity of 262 KB SRAM, can store up to 65,536 complex data. The twiddle factor buffer, with a capacity of 131 KB SRAM, can hold up to 32,768 twiddle factors for single butterfly operations. The status register stores the status of the NMP module, which is used to determine the start and end of NMP operations. When the NMP controller receives the NMP start signal in the status register, it initiates the NMP operation. The NMP controller orchestrates various tasks, including generating buffer addresses; selecting the appropriate multiplexer (MUX) for FFT, IFFT, and reference signal multiplication; and issuing an NMP end signal to mark the completion of the NMP operation. The decoder extracts essential information for the NMP operation, such as Opcode and \(N\)-point, from the NMP instructions read from the instruction buffer. The floating-point butterfly (FPBF) module selectively executes the FFT, IFFT, and reference  
signal multiplication based on the data extracted from the buffers and the MUX selection signal provided by the NMP controller. The results of each FFT stage calculated by the FPBF module are stored in the data buffer.