## 5 Use Cases of Attack Detection with Matana
### Use Case: Prime + Probe Cache Attack Detection
#### 5.2.1 Technical Background  
Memory cache is the hardware component that is designed to speed up the processor's access to the main memory. It is built on the temporal and spatial locality principle of memory access, i.e., the same location and the nearby location of a recently accessed location is likely to be used again in the near future. If data access is required by the processor, and the data are not in the cache, the corresponding data and nearby data are read from the memory and loaded into the cache for likely future access (so-called a cache miss). If the data is in the cache, the access is quicker (so-called a cache hit). The correspondence between the main memory and the cache is usually based on physical addresses, as shown in Figure 6. For the L2 cache of our prototype, the lower bits of the address correspond to the offset in a cache line (the basic unit of the cache, usually 64 bytes), the medium bits of the address correspond to the cache set index (64 sets), and the higher bits of the address constitute the tag used to determine if a given cache line contains data from this specific memory address location. One set can have multiple cache lines; for example, our L2 cache is 8-way associative, which means that each cache set contains 8 cache lines. One address that is mapped to a given cache set can then be placed on one of the 8 cache lines based on a replacement policy, for example, Least Recently Used (LRU). Prime + Probe is a powerful CSCA that benefits from this access acceleration property of the cache. It only requires that the attacker's process and the victim's process share the same physical cache at the same time. For example, processes running on different CPUs of the same system that share the Last Level cache can satisfy this requirement [33]. The global attack works in three phases: the preparation phase, the attack phase itself, and the analysis phase. In the preparation phase, the attacker needs to locate one or multiple cache sets of interest to monitor and, for each set, find 8 addresses (for a 8-way associative cache) that are located in the given set but with different tags. The attack phase's assembly code is shown in Listing 1. The first step is called Prime, in which the attacker accesses in turn the 8 addresses previously identified. Due to the replacement policy of the cache, all 8 cache lines of this selected set are occupied by the attacker's data. Then, in a second step, so-called Wait, the attacker's process waits for the victim process to execute. During this step, if the victim uses the set, some victim's data are loaded in the set and evict the attacker's data. The third step is so-called Probe, in which the attacker accesses the 8 previously identified addresses and measures the total access time. The access is arranged in the form of a linked list (i.e., the value of the next address is stored in the contents of the previous address) and in inverse order of Prime phase to prevent the prediction of accesses and the self-replacement due to LRU. If the victim process did not use the set monitored by the attacker in the Wait step, then all the 8 attacker's data are still in the cache, and access to these data generates 8 cache hits, which corresponds to a fast access. If the victim process used this set, then some attacker's data were evicted and the access to these data generates a cache miss, which corresponds to a slow access. By repeating Prime, Wait, and Probe (Probe can be served as a Prime for the next round of Prime + Probe), the attacker learns a sequence of accesses of the victim process on monitored sets, which allows them to deduce some of the victim's secret information in the Analysis phase. Figure 6: Cache indexing for 64-set cache and 64-byte cache line. CSCAs can also be used as part of other attacks.