## 4 Experimental Results and Comparison  
The proposed structure of the multi-modulus HMG and multi-modulus multipliers based on radix-8 Booth encoding, which is covered in Section 3, is discussed in this section, along with the experimental results and comparison. The proposed multi-modulus HMG structure integrates and improves the HMG used by the modulo (\(2^{n}-1\)) multiplier [22], modulo (\(2^{n}\)) multiplier [23], and modulo (\(2^{n}+1\)) multiplier [24] proposed in the reported studies. The area-saving multifunction based on these three moduli is proposed, and it shares the same hardware architecture. The proposed modified multi-modulus HMG can save 34.48-55.23% of hardware area compared with the reported work [20], as shown in Table 2.  
Figure 15: Example of the operational process of the proposed multi-modulus multiplier for 8 bits (\(n=8\)). The proposed multi-modulus modulo (\(2^{n}-1\)), modulo (\(2^{n}\)), and modulo (\(2^{n}+1\)) multiplexers can support the aforementioned modular multiplication functions in the same circuit hardware. By integrating the individual functions of the modulo (\(2^{n}-1\)), modulo (\(2^{n}\)), and modulo (\(2^{n}+1\)) multiplexers into a single multi-modulus multiplier, the proposed approach can save 22.78-35.46% of hardware area compared with previous work [20], as tabulated in Table 3. In addition, the proposed approach can reduce delay time by 4.12-11.15% compared with previous work [20], as tabulated in Table 4. The dynamic power consumption can be reduced by 12.59-24.73% of dissipation power compared with previous work [20], as tabulated in Table 5. Moreover, it can save 27.88-38.88% of ADP compared with previous work [20], as shown in Table 6. Finally, it can save 20.49-27.85% of PDP compared with previous work [20], as tabulated in Table 7. \begin{table}
\begin{tabular}{c c c c} \hline \hline  & \multicolumn{2}{c}{**[PERSON]**} & \multicolumn{2}{c}{**This Work**} \\  & **and [PERSON] [20]** & **Delay (ns)** & **Delay Saving** \\ \hline
8 & 19.488 & 17.37 & 10.87\% \\ \hline
16 & 25.047 & 22.254 & 11.15\% \\ \hline
24 & 31.024 & 29.74 & 4.14\% \\ \hline
32 & 33.583 & 32.166 & 4.22\% \\ \hline
40 & 39.271 & 37.614 & 4.22\% \\ \hline
48 & 39.723 & 38.086 & 4.12\% \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Comparison of delay of the proposed multiplier with [PERSON] and [PERSON] [20]. \begin{table}
\begin{tabular}{c c c c} \hline \hline  & \multicolumn{2}{c}{**[PERSON] and**} & \multicolumn{2}{c}{**Proposed Modified HMG**} \\  & **[PERSON] [20]** & **Area (LUT)** & **Area (LUT)** & **Area Saving** \\ \hline
8 & 29 & 19 & 34.48\% \\ \hline
16 & 101 & 46 & 54.46\% \\ \hline
24 & 174 & 96 & 44.83\% \\ \hline
32 & 267 & 136 & 49.06\% \\ \hline
40 & 373 & 167 & 55.23\% \\ \hline
48 & 484 & 230 & 52.48\% \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Comparison of area of the proposed modified HMG with [PERSON] and [PERSON] [20]. \begin{table}
\begin{tabular}{c c c c} \hline \hline  & \multicolumn{2}{c}{**[PERSON] and**} & \multicolumn{2}{c}{**This Work**} \\  & **and [PERSON] [20]** & **Delay (ns)** & **Delay Saving** \\ \hline
8 & 197 & 133 & 32.5\% \\ \hline
16 & 597 & 461 & 22.78\% \\ \hline
24 & 1461 & 943 & 35.46\% \\ \hline
32 & 2190 & 1491 & 31.92\% \\ \hline
40 & 3481 & 2621 & 24.71\% \\ \hline
48 & 4970 & 3560 & 28.37\% \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Comparison of area of the proposed multiplier with [PERSON] and [PERSON] [20]. In Table 2 to Table 7, it is clear that the proposed multi-modulus multiplier based on radix-8 Booth encoding achieves better performance with a lower power, faster operation, greater area-efficiency, and lower ADP and PDP compared with a similar method reported in the literature [20]. The system structure of the proposed approach is compared with that of [PERSON] and [PERSON] [20] in Table 8, showing the weighted system structures adopted for all the modulo multipliers. There are several methods of implementing a multiplier in FPFAs.