# On the Safe Deployment of Matrix Multiplication in Massively Parallel Safety-Related Systems
## 4 Evaluation
### Trade-Off between Performance Impact and DC
\begin{table}
\begin{tabular}{l c c c c c c c c c c c c c c c c c c} \hline \hline \multicolumn{1}{c}{} & \multicolumn{1}{c}{**Square**} & \multicolumn{1}{c}{**Unbalanced**} & & & & & & & & & & & & & & & & & & & & & & \\ \hline \multirow{3}{*}{**Checksum**} & \multicolumn{3}{c}{**20**} & \multicolumn{3}{c}{**40**} & \multicolumn{3}{c}{**80**} & \multicolumn{3}{c}{**L1**} & & & & & & & & & & & & & & & & & & & & \\
**Implemented** & **Seq** & **AVX** & **GPU** & **Seq** & **AVX** & **GPU** & **Seq** & **AVX** & **GPU** & **Seq** & **AVX** & **GPU** & **Seq** & **AVX** & **GPU** & **Seq** & **AVX** & **GPU** \\ \hline XOR (E) & 2.5 & 2.5 & 10.0 & 1.3 & 1.3 & 10.0 & 0.6 & 0.6 & 12.5 & 0.4 & 0.4 & 6.6 & 0.1 & 0.1 & 12.4 & 0.1 & 0.1 & 12.1 \\ XOR (M) & 50.0 & 50.0 & 50.0 & 50.0 & 50.0 & 50.0 & 50.0 & 50.0 & 50.0 & 50.0 & 52.5 & 52.5 & 0.9 & 0.9 & 0.9 & 0.6 & 100.0 & 6.3 \\ One’s (E) & 2.5 & 2.5 & 10.0 & 1.3 & 1.3 & 10.0 & 0.6 & 0.6 & 12.5 & 0.4 & 0.4 & 6.6 & 0.1 & 0.1 & 12.4 & 0.1 & 0.2 & 12.1 \\ One’s (M) & 52.5 & 79.2 & 62.5 & 51.2 & 59.2 & 62.5 & 50.6 & 54.4 & 62.5 & 54.1 & 72.9 & 63.0 & 1.0 & 2.2 & 57.7 & 7.1 & 9.9 & 30.0 \\ One’s (M) & 98.5 & 99.2 & 100.0 & 97.7 & 99.2 & 100.0 & 96.9 & 93.8 & 100.0 & 98.4 & 98.9 & 100.0 & 97.7 & 99.2 & 100.0 & 96.9 & 99.9 & 100.0 \\ Two’s (E) & 2.5 & 2.5 & 10.0 & 1.3 & 1.3 & 10.0 & 0.6 & 0.6 & 12.5 & 0.4 & 0.4 & 6.6 & 0.1 & 0.1 & 12.4 & 1.0 & 0.2 & 12.1 \\ Two’s (M) & 52.3 & 68.8 & 61.7 & 51.1 & 59.1 & 61.7 & 50.6 & 54.2 & 61.7 & 54.1 & 63.3 & 63.2 & 1.0 & 1.7 & 24.1 & 7.1 & 9.6 & 28.5 \\ Two’s (M) & 96.9 & 96.9 & 95.7 & 95.3 & 95.3 & 95.7 & 93.8 & 99.2 & 95.7 & 98.4 & 92.6 & 95.9 & 90.7 & 90.7 & 91.5 & 96.9 & 100.0 & 92.0 \\ Fletcher (E) & 2.6 & 3.5 & 10.0 & 1.3 & 1.5 & 10.0 & 0.6 & 0.7 & 12.5 & 0.4 & 0.5 & 6.6 & 0.1 & 0.2 & 12.4 & 0.1 & 0.2 & 12.1 \\ Fletcher (M) & 52.2 & 68.8 & 62.5 & 51.1 & 60.0 & 62.5 & 50.6 & 55.0 & 62.5 & 54.1 & 73.8 & 63.9 & 1.0 & 2.2 & 25.7 & 7.1 & 10.0 & 30.0 \\ Fletcher (I) & 100.0 & 96.9 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 \\ CRC (E) & 2.6 & 3.5 & 10.0 & 1.3 & 1.5 & 10.0 & 0.6 & 0.7 & 12.5 & 0.4 & 0.5 & 6.6 & 0.1 & 0.2 & 12.4 & 0.1 & 0.2 & 12.1 \\ CRC (M) & 52.5 & 80.0 & 62.5 & 51.3 & 60.0 & 62.5 & 50.6 & 55.0 & 62.5 & 54.1 & 73.8 & 63.9 & 1.0 & 2.2 & 25.7 & 7.1 & 10.0 & 30.0 \\ CRC (I) & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 & 100.0 \\ XOR\_Fletcher & 99.8 & 100.0 & 90.6 & 99.8 & 100.0 & 90.6 & 99.8 & 100.0 & 90.6 & 99.8 & 100.0 & 91.0 & 99.8 & 100.0 & 81.4 & 99.8 & 100.0 & 82.5 \\ One’s\_Fletcher & 100.0 & 100.0 & 96.3 & 100.0 & 100.0 & 95.6 & 100.0 & 100.0 & 95.6 & 100.0 & 100.0 & 95.5 & 100.0 & 100.0 & 90.7 & 100.0 & 100.0 & 91.3 \\ Two’s\_Fletcher & 97.9 & 100.0 & 96.3 & 97.8 & 100.0 & 95.6 & 97.7 & 100.0 & 95.6 & 99.6 & 100.0 & 95.5 & 99.8 & 99.9 & 90.7 & 99.6 & 100.0 & 91.3 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: DC in sequential [14], AVX-based [14], and GPU-based implementations. for detecting single-bit errors for this matrix-matrix multiplication dimension (1.09 in non-optimization compilation and 3.70 the highest compiler optimization). For medium DC, the most suitable option for -O0 compilation remains the same but with -O3 optimization the best trade-off can be reached with two's complement (I) (3.33 performance impact). Finally, the best performance for low DC is achieved in both optimizations with two's complement (M) (1.01 and 1.44 performance impact). After analyzing the most suitable checksums according to the DC range, performance impact, and compiler optimization for 80 \(\times\) 80 square matrix dimensions, we examine the DC required to achieve the SIL and HFT established in the functional safety standards. For that, we recur to IEC 61508-2 in Table 2, where those relationships are defined.