# EXPRESS: Exploiting Energy-Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage
## 2 Background
### ISPP Programming Scheme  
A page program operation in the NAND array utilizes an incremental step pulse program (ISPP) scheme with multiple program cycles, as illustrated in Figure 2a. Each program cycle consists of a program pulse, followed by a verification phase. During a program pulse phase, a high voltage (~15-18 V) is applied to the corresponding WL to cause the injection of electrons into the FG/CTs of the memory cells that need to be programmed. The verification phase identifies the cells that have reached the required threshold voltage, \(V_{t}\), by performing a page read operation, with a program verification voltage (\(V_{ref}^{PVY}\)) applied on the corresponding WL. Thus, the \(V_{ref}^{PVY}\) represents the minimum voltage of the program state distribution. The cells whose \(V_{t}\) exceed \(V_{ref}^{PVY}\) are identified as \"programmed\", and they are subsequently locked out from further programming using a program inhibit scheme. The following program cycle starts with an incrementally higher voltage on the WL, which increases the chances that the cells that did not switch their state in the previous cycle become programmed [24]. This sequence of the program and the verification steps continue until most of the cells that are supposed to be programmed are, indeed, programmed. Figure 2a illustrates the different steps associated with the one-page program operation as a function of time. The steps include the high-voltage program pulse phase of the duration \(t_{p}\), a relatively lower voltage verification phase of the duration \(t_{tyy}\), and two setup time intervals--one for the program pulse of the duration, \(t_{p}^{\text{s}u}\), and the other for the verification phase, \(t_{tyy}^{su}\). Assuming that all of these times remain constant across all of the program cycles, the total page program time can be expressed as follows:  
\[t_{prog}=t_{init}+n\times\left(t_{p}^{su}+t_{p}+t_{tyy}^{su}+t_{tyy}\right)=t_ {init}+n\times t_{py} \tag{1}\]  
Here, \(t_{py}=\left(t_{p}^{su}+t_{p}+t_{tyy}^{su}+t_{tyy}\right)\) represents the time required for one full program cycle, \(n\) stands for the total number of program cycles required for the page program operation, and \(t_{init}\) is the initial time required by the NAND array to verify the page status before applying a series of program cycles. Please note that Equation (1) captures the common features of the NAND page program operations. However, it may need to be adjusted depending on the specific implementation of the on-chip control logic in a particular flash memory chip. The primary purpose of the ISPP scheme is to tighten the program state \(V_{t}\) distribution, relative to the initial erase state \(V_{t}\) distribution, which is typically wider because of the intrinsic cell-to-cell process variation. The evolution of the cell \(V_{t}\) distribution with the ISPP scheme is further illustrated in Figure 2b. For simplicity, we consider an SLC memory, although the same principle holds for MLC and TLC flash memories. We choose a program operation with four program cycles to illustrate the ISPP scheme. In practice, the number of program cycles could be higher. The distribution depicted with the dashed line represents the right-shifted erase state \(V_{t}\) distribution after each program cycle, if all the cells are programmed. In practice, a certain number of cells that attain a \(V_{t}\) exceeding the program verification voltage are locked out of (or inhibited from) further programming cycles. Thus, the ISPP scheme tightens the cell \(V_{t}\) distribution by selectively providing fewer program pulses to the fast program cells, and more program pulses to the slow program cells. As a result, the final program state distribution becomes much tighter than in the erase state, as illustrated with the yellow distribution in Figure 2b. Since a tighter \(V_{t}\) distribution is essential for ensuring data integrity, the ISPP scheme is invariably used in all NAND flash memories.