## 2 Materials and Methods  
### Device Structure and Fabrication  
Fabricated OFETs have a bottom gate-bottom contact structure, shown in Figure 1. Two different substrates were employed: 175-um-thick polyethylene terephthalate (PET, Goodfellow) and 700-nm-thick Parylene C substrates. The latest were fabricated by depositing Parylene C with a PDS 2010 Labcoater 2 (Specialty Coating System, Indianapolis, IN) over 175-um-thick PET substrates, previously coated with 1:50 water solution of an industrial soap (Micro-90 Concentrated Cleaning Solution, International Corporation, Burlington, NJ). Before printing, both kinds of substrate were cleaned with acetone and ethanol (Sigma Aldrich) and dried with nitrogen. Gate electrodes were inkjet-printed using a Dimatix Materials Printer DMP2831 (Fujifilm Dimatix, Lebanon, NH). A 16-nozzle cartridge with single drop volume of 1 pL (DMC11601, Fujifilm Dimatix) was filled with PJET HC (Heraeus, Hanau, Germany), a commercially available, Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS)-based ink. Three nozzles, biased with a firing voltage of 25 V, were employed for patterning gate lines of \(10\times 2\) mm\({}^{2}\), defined by the overlap of two subsequently printed layers. A drop spacing of 20 um was set, and the printer platen was maintained at a fixed temperature of 60 \({}^{\circ}\)C.  
The gate insulator is a 250 nm-thick Parylene C film, deposited by CVD using the previously cited PDS 2010 Parylene coating equipment. In this case, an adhesion promoter (A-174 Silane, Specialty Coating Systems, Indianapolis, IN) was inserted in the deposition chamber to improve the quality of the deposited film. It is worth noting that this technique is perfectly compatible, in terms of throughput and area, with inkjet printing [34; 35], and can be possibly extended to roll-to-roll fabrication processes [36]. The final insulating capacitance is of 10 nFcm\({}^{-2}\).  
After a thorough cleaning of Parylene C surface with acetone and ethanol, the source and drain electrodes were inkjet-printed using PJET HC, in the same conditions described for gate patterning (with the exception of the employment of a single nozzle). Interdigitated structures comprising 10 channels were fabricated by printing 2-mm-long, 200-\(\upmu\)m-wide and 175-\(\upmu\)m-spaced electrodes. A final channel width W = 20 mm and channel length L = 100 \(\upmu\)m were obtained. Source and drain electrodes were post-processed with a curing step over a hot plate (90 \({}^{\circ}\)C for 15 min) and a subsequent deposition of ethylene glycol (EG, Sigma Aldrich) by inkjet printing, using a cartridge with a single drop volume of 10 pL (DMC11610, Fujifilm Dimatix), two nozzles with a firing voltage of 40 V and a drop spacing of 80 \(\upmu\)m. EG was left to dry for 30 min over the printer platen at a temperature of 60 \({}^{\circ}\)C. 6,13-Bis(triisopropylsilylethylynyl)pentacene (TIPS pentacene, Sigma Aldrich) was printed from a 1.5 wt % solution in anisole (Sigma-Aldrich), using a cartridge with a single drop volume of 10 pL, employing three nozzles biased at 40 V, with a drop spacing of 30 \(\upmu\)m, and leaving the platen at room temperature. This semiconductor was chosen for its significant air stability [37] and its moderately high charge carrier mobility [38]. Figure S1 in Supplementary Information shows the obtained device structure, and some details obtained using the fiducial camera of the printer.