# An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System
## 1 Introduction
OPDP enables the high-speed processing of SAR imaging data at 1K \(\times\) 1K granularity on the RTAX2000S FPGA through a combination of the general-purpose AT697 LEON2 fault-tolerant processor ASIC and the flexible FFT-oriented DSP coprocessor fast fourier transform coprocessor (FFTC), coupled with configured SDRAM memory and data interaction Switch Fabric modules [18; 19]. In 2018, Ruhr University in Germany implemented an SAR imaging system based on the back projection (BP) algorithm on a Xilinx Zynq-7000 chip. In 2019, NASA launched the latest SpaceCube v3.0 space-embedded heterogeneous processing board with different kinds of FPGAs, MPSoC chips, which can perform a variety of on-orbit data real-time processing tasks, providing solutions to meet the needs of next-generation science and defense missions [20; 21]. Xilinx released the world's first 20 nm space-grade Kintex Ultra-Scale field-programmable gate array (FPGA) chip in 2020. This new chip offers enhanced radiation tolerance, extremely high data throughput, and bandwidth performance, making it an excellent choice for space and satellite applications. Moreover, this chip supports artificial intelligence applications, making it possible for satellites to process imagery or radar data locally, without ground review. This innovation provides several benefits, such as improved mission responsiveness and real-time processing capabilities, thereby enabling a new system architecture [22]. The development of technology for the real-time processing of spaceborne SAR demonstrates that a high-performance satellite-based real-time processing platform requires processors with high processing power, low power consumption, and high scalability, as well as memory with a large capacity and high bandwidth. In the direction of real-time process ing, central processing unit (CPU), digital signal processor (DSP), field-programmable gate array (FPGA), graphics processing unit (GPU) and application-specific integrated circuit (ASIC) have some degree of superiority [23]. Processors such as embedded multi-core CPUs, which can meet a larger number of applications, have a high processing accuracy and can run operating systems, thus realizing complex embedded control processes, and have flexible designs; however, they have a relatively weak computing power when processing massive amounts of data. Flexibility in programming, high processing precision, multi-chip scalability, ease of development, and low power consumption are all advantages of DSP processors; however, the parallelism is subpar. Despite its high power consumption and lack of suitability for satellite-processing scenarios, GPU is now mostly used in ground stations as a data-processing processor. ASIC is a self-designed processor with a lengthy development time and limited adaptability for fixed algorithm applications. Compared with CPU, DSP and ASIC, FPGA has the advantages of high programmable flexibility, a short development cycle, high parallelism, better performance and higher energy efficiency. Therefore, in recent years, FPGAs have become more and more widely used in the field of on-board real-time processing [24; 25; 26]. At present, it is the trend for the real-time processing of SAR imaging to compensate for the shortcomings of a single processor in some specific application scenarios through multi-processor heterogeneous integration [27]. The central processing unit (CPU) in a heterogeneous processor such as the \"CPU + FPGA\" takes care of scheduling and task management while the FPGA acts as a co-processor to speed up computations [28]. Because the above processors' on-chip storage capacity is extremely constrained and it is unable to accommodate the demands of massive data storage, SAR data must be stored in a high-speed, large-capacity, off-chip memory. Currently, DDR3 SDRAM can be used as an off-chip memory option for space-borne real-time processing. This has been widely used in the real-time processing platform for satellites [29; 30; 31; 32].