## 1 Introduction  
Numerical computations based on structured grids play an important role in scientific research and industrial applications. The commonly used finite element method, finite difference method, and finite volume method are all computed on grids. Sparse matrix-vector multiplication (SpMV) and Gauss-Seidel iterations are very important kernel functions [1] that have a significant impact on performance in practical applications. Both functions are memory-intensive and require indirect memory access by an index. All Krylov subspace methods require calls to SpMV functions, and Gauss-Seidel iterations are commonly used as smoothing operators and as the bottom solver in multigrid solvers. The original Gaussian-Seidel iteration has very limited parallelism because of its strict dependencies. It is possible to break its dependencies and develop fine-grained parallelism by multicolor reordering [2]. Gauss-Seidel fine-grained parallel algorithms are usually closely related to the processor architecture. A two-level blocked Gauss-Seidel algorithm was used on the SW26010-Pro processor [2]. A Gauss-Seidel algorithm with 8-color block reordering was applied to the SW26010 [3]. The red-black reordering Gauss-Seidel algorithm was designed for the CPU-MIC architecture on the Tianhe-2 supercomputer [4]. The K supercomputer is a homogeneous architecture, and the performance of the Gauss-Seidel algorithm for 8-color point reordering and 4-color row reordering was compared [5]. Currently, the computing performance of high-performance supercomputers has reached the E-level. The power consumption and heat dissipation are important factors affecting supercomputers. The general purpose digital signal processor (GPDSP) is a very important embedded processor. It has the advantage of ultra-low power consumption due to its very long instruction words and on-chip temporary memory [6]. GPDSPs that have been introduced for high-performance computing include TI's C66X series [7; 8] and Phytium's Matrix series [9; 10; 11; 12; 13]. The Matrix-DSP is a GPDSP developed by Phytium, which can be used either as an accelerator with a CPU or as a processor alone. It has a complex architecture containing multilevel memory structures and multilevel parallel components, which can implement instruction-level parallelism, vectorized parallelism, and multicore parallelism. It is difficult to fully exploit the performance of the Matrix-DSP by simply transplanting existing algorithms designed for single-core processors [12]. [PERSON] et al. mapped the Winograd algorithm for accelerating convolutional neural networks onto the Matrix-DSP [14]. [PERSON] et al. designed a multicore vectorization GEMM for the Matrix-DSP [12]. [PERSON] et al. evaluated the efficiency of a DCNN on the Matrix-DSP [15]. Due to the novelty of the Matrix-DSP processor, memory-intensive programs are still underdeveloped, and there are no public papers on sparse matrix computation for the Matrix-DSP yet available. In this paper, we designed multi-core vector algorithms based on structured grid SpMV and Gauss-Seidel iterations for the Matrix-DSP and evaluated our algorithms on the Matrix-DSP platform. The main contributions are as follows:  
(1) We improved the data locality and indirect memory access speed by blocking, using a multicolor reordering method to develop the fine-grained parallelism of the Gauss-Seidel algorithm, and dividing the data finely according to the memory structure of the Matrix-DSP. (2) In terms of the data transfer, we used a double-buffered DMA scheme, which overlaps the computation and transfer time. We also implemented general mixed-precision algorithms, which reduced the memory access. (3) We tested various grid cases on the Matrix-DSP, and the experimental results show that our improved algorithms could fully exploit the bandwidth efficiency of the Matrix-DSP, wherein they reached 72% and 81% of the theoretical bandwidth, respectively.