## Appendix A Effects of the VSC Switches on Maximum Switching Frequency
The total time duration can be given by Equation (13). \[Q_{tot3}=V_{gs}C_{gs}+C_{gd}\big{(}V_{gs}+V_{dd}\big{)}\]1  
In the final stage, \(C_{gs}\) is discharged to a full turn-off state, \(V_{ds}\) is raised to its initial value and \(I_{d}\) is minimized to zero. The total time delay can be estimated based on \(R_{g}\) and the input capacitances as in Equation (14). \[Q_{tot3}=V_{gs}C_{gs}+C_{gd}\big{(}V_{gs}+V_{dd}\big{)}\]2  
The total off time can be estimated based on the combination of T\({}_{4}\) + T\({}_{5}\) + T\({}_{6}\) as in Equation (15) at a minimum V\({}_{dsmin}\) of 0. \[Q_{tot3}=V_{gs}C_{gs}+C_{gd}\big{(}V_{gs}+V_{dd}\big{)}\]3  
The total switching time of the MOSFET can be calculated as \(T_{on}\) + \(T_{off}\). The maximum allowable switching frequency based on the above deduction can then be obtained with the inverse of the total switching period. Considering the IRFP450 enhancement mode MOSFET parameters specified in Table 11, the total on and off time delays from Equations (11) and (17), the maximum switching frequency can be mathematically estimated as Equation (18). \[Q_{tot3}=V_{gs}C_{gs}+C_{gd}\big{(}V_{gs}+V_{dd}\big{)}\]4  
\[Q_{tot3}=V_{gs}C_{gs}+C_{gd}\big{(}V_{gs}+V_{dd}\big{)}\]5  
For  
S: 1 mA/V  
R\({}_{g}\): 3 \(\Omega\)R\({}_{d}\): 3.57 \(\Omega\)  
\[Q_{tot3}=V_{gs}C_{gs}+C_{gd}\big{(}V_{gs}+V_{dd}\big{)}\]6  
\(F_{sw}=\frac{1}{T_{on}+T_{off}}=20.8 MHz\)  
The obtained maximum frequency, \(F_{sw}\), from Equation (A14) is calculated based on manufacturers data provided on the datasheet of the IRFP450, and operational values will differ. The maximum obtainable frequency was analyzed for various values of \(R_{g}\) and \(R_{d}\) at S = 1 mA/V. Tables 15 and 16 show the results of these variations of the frequency. From Table 16, it can be observed that increasing the gate resistance alleviates the switching frequency, which will eventually reduce oscillations and electromagnetic interferences (EMIs) [44; 45; 46; 47]. However, the reduction in switching speed increases switching losses and the on/off time delays. * _[PERSON] and [PERSON] (2018)_ [PERSON]; [PERSON] Impact of Network Conditions on the Harmonic Performance of PV Inverters. In Proceedings of the 2018 Power Systems Computation Conference (PSCC), Dublin, Ireland, 11-15 June 2018; pp. 1-7. [CrossRef]
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