# Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices
## 3 NAND Flash Memory Reliability
### Disturbs
#### 3.6.2 Program and Pass Disturbs  
When programming a page, we must ensure that only the desired BLs are actually programmed, while other cells on the same page that must remain in their original state are not affected by such operation. Since electrons are injected into the floating gate via FN tunneling, which is a process strongly dependent on the oxide field, we can inhibit programming by reducing such a field, i.e., the gate-to-channel voltage drop. The simpler solution is to disconnect (i.e., ground) the SSL (see Figure 1) and raise the inhibited BLs to a high voltage [263; 264], while biasing the unselected WLs too, to avoid unintentional erase. However, this solution was soon abandoned because of power and time issues related to the charging of highly-capacitive BLs and because of high-voltage limitations in scaled technologies. In replacement, a _self boosting_ technique was proposed [265], illustrated in Figure 31: BLs to be programmed are grounded, which turns on their DSL and maintains the string channel to ground (green line). Note that a pass voltage (different from the one used during read) is applied to the unselected WLs. Inhibted BLs, instead, are biased at \(V_{cc}\), which precharges their channel. When the high passing voltage is applied to the WLs, however, the channel potential (red line) is lifted by capacitive coupling, turning off the DSL and reaching a value high enough to suppress electron injection into the floating gate. This solution generates two kinds of disturbs, highlighted in Figure 32: a program disturb on the cells on the programmed WL (encircled in green), related to the potential difference between program and boosted bias, and a pass disturb on the cells located on the same (grounded) BL as the programmed ones (red circles), related to the pass voltage. The nature of such disturbs is just the same as the RD, namely a soft-programming at low voltage, with the difference that now the applied field is higher with respect to RD, while the number of cycles is significantly lower. Note also that an increase in the pass voltage will lead to an increase in the channel potential, reducing the program disturb but raising the pass one. This typical behavior is shown in Figure 33 (left). While a logarithmic dependence of \(V_{T}\) on the number of cycles has been reported [266], the dependence of BER is more complex, as shown on the right of Figure 33 [257]. To limit the pass disturb, improved boosting schemes have been developed, including local boosting [36; 267], ramped WL voltage [268], dynamic pass voltage biasing [269] or negative WL pre-biasing [270]. Interestingly, a self-boosting scheme during read was also proposed, to alleviate read-disturb issues [271]. Figure 30: (**Left**) \(V_{T}\) distribution for increasing RD time; (**Right**) mean \(V_{T}\) shift of the different levels as a function of the number of reads [255], © 2015 IEEE. Figure 31: NAND array bias condition during program, highlighting the self-boosting effect. Figure 32: NAND array bias condition during program. Cells subjected to program (green) and pass (red) disturbs are circled. The boosting operation in scaled NAND devices is also responsible for additional reliability concerns. First, the string select transistors must withstand the boosted potential with minimum leakage current, as such current will discharge the channel and increase program disturb (for this reason, such devices are hard to scale). However, under program inhibit conditions, the SSL transistor is subjected to gate-induced drain leakage (GIDL) due to band-to-band tunneling, injecting hot electrons toward the first WL (see Figure 32) and into its floating gate, when erased [266]. This effect leads to an enhanced program disturb at the first WL and is usually curbed by increasing the SSL-to-WL spacing [266] or employing one [272] or two [273] dummy edge WLs.