## 2 Proposed Method  
Before discussing 2D-VLEDC, we first introduce a two-dimensional parity (2D-parity) check. Figure 3 describes a ROM whose physical size is 20 \(\times\) 32 (address 0-19, each address has 32 bits) bits as an example. The addresses from 0 to 16 contain the program codes that Central Processing Unit (CPU) runs with. It is called as data area. The C1 column is \(Y\)-axis 1-bit parity check of data word at relative address. For example, green square (address 0) in the Figure 3 specifies an even parity coding scheme. In the address 0, only bit (0, 30) from bit 0 to 31 equals to 1, so bit (0, C1) equals to 1. In the same way, address 17 is \(X\)-axis 1-bit even parity bit for column bits of the program codes. As shown as blue square in the Figure 3, there are totally 15 ones in the column 1 from address 0 to address 16, so the (17, 1) equals to 1 according to even parity rule. To apply the 2D-parity in a typical memory, the \(Y\)-axis parity bits (address 18) are stored in the address behind the program codes (address 0 to 16), and \(X\)-axis parity (address 17). As shown in Figure 3, the \(Y\)-axis (column C1) bits are stored at the address 18 as presented in the red square. The remaining bits in the address 18 are filled with 0. The storage of \(X\)-axis and \(Y\)-axis is called as signature area. In addition, as shown in address 19, the same 2D-parity can be applied to the signature area again to implement self-checking-like scheme to improve the fault tolerant quality. The 2D-parity could detect and correct single bit error in both data area and signature area. Any 2-bit error could be detected. However, the locating of two error bits is not always successful. For example, if there are two error bits in one data word, the \(X\)-axis shows no change of parity bit even two of bit changes in \(Y\)-axis parity are found--that is to say, this 2-bit error can be identified but the location of error bit cannot be found, resulting in failure to recover them. As a result, the error handling capability is named as single error correction and double error detection (SECDED). Figure 3: 2D-parity check applied to non-volatile memory (NVM). To compare the undetected error rate of 2D-parity with ECC, a fault injection simulation was applied, as shown in Table 1. In this simulation, 1 to 4 errors were injected and all possible error location combinations in an 8 \(\times\) 32 size of ROM were evaluated. In other words, for 4-errors fault injection simulation, there are C (8 \(\times\) 32, 4) operations including injecting fault, decoding, and comparison in the simulation, where C means \"combination\". Table 1 shows the results of fault injection simulation with 2D-parity and ECC. Undetected error rate equals to (undetected error counts)/C (8 \(\times\) 32, 4) \(\times\) 100%. Table 1 show that 2D-parity and ECC can detect all errors from 1 to 3 errors' fault injection. In the 4 errors' fault injection simulation, ECC has effectiveness better (twice) than 2D-parity. The cost overhead of 2D-parity equals to ((8 + 32)/(8 \(\times\) 32)) \(\times\) 100% = 15.625%. The cost of ECC equals to ((7 \(\times\) 8)/(8 \(\times\) 32)) \(\times\) 100% = 21.875%. 2D-parity overhead/ECC overhead = 71.43%. One possible way to improve the error detection rate of 2D parity is to include ECC on data word to replace the \(X\)-axis parity. However, it induces significant increase in redundancy. Here an idea of variable length error detection code is proposed. The probability of read error between 1-to-0 and 0-to-1 is different after NVM in the radiation. It was taken into account to select appropriate \(X\)-axis redundancy. Figure 4 shows the concept of our VLEDC, the content of data word decides the method of encoding with respective redundant bits. As a result, the length of redundant bits is variable for each data word in NVM. Figure 5 shows the architecture of the proposed 2D-VLEDC, including: Filter, encoder, boot checker and NVM modules.