# A 200-MS/s 10-Bit SAR ADC Applied in WLAN Systems
## 2 ADC Architecture and Considerations
### In Terms of Linearity  
The ADC's linearity is constrained by several factors. The first issue faced is the CDAC mismatch. According to capacitor mismatch theory, due to capacitor mismatch deterioration caused by size reduction, larger unit capacitors are needed to meet the linearity requirement [9,10]. However, the use of a large CDAC not only wastes power in the input and reference buffers but also imposes more stringent timing constraints. To reduce the total capacitance, the current mainstream solution is to reduce the size of the unit capacitor and then combine it with a digital calibration scheme [11]. However, whether based on self-calibration [12], LMS-based digital calibration [13, 14, 15], or capacitor mismatch shaping technology [16], these calibration schemes demand a significant amount of digital resources and lead to an increase in gain error. Therefore, these calibration solutions are more cost-effective for designs with 12 bits or more, but less so for the 10-bit design in this paper. The introduction of the dual-reference voltage technique [17] provides a new solution to reduce the total capacitance of the CDAC. Unlike the previous approach of reducing the size of the unit capacitor, the dual-reference voltage technique can directly reduce the total number of required capacitors in CDAC. The core theory of the multi-reference voltage scheme is charge conservation. In this paper, a 4-reference voltage technique is proposed based on this theory. Figure 4 shows the voltage jumping in the top plate of the CDAC during the switching process of the proposed 4-reference voltage technique. According to the law of charge conservation, it can be seen that the voltage change ratio \(\Delta\)V1: \(\Delta\)V4 satisfies 1:8 during the switching process of S1 and S4. However, to achieve a voltage jump ratio of 1:8 in a standard binary CDAC, the capacitance value of the corresponding bit position must satisfy an 8-fold relationship.  
Following the switching scheme of the 4-reference voltage, the requirement for the number of capacitors in CDAC that meet the 10-bit requirement is reduced from 512 to 66. The unit capacitor is ultimately designed to be 6 fF. The capacitance value of a unit capacitor can better meet the requirements of linearity for mismatch consideration, and the total capacitance value of CDAC is about 410 fF, which can better balance the KT/C noise and the design pressure of the driving stage.  
The second issue encountered by high-linearity ADCs is kickback noise. At sampling rates of hundreds of MHz [18,19], the comparator's speed is usually as high as several GHz. During the entire SA phase, comparator kickback noise will be injected into the CDAC through the \(C_{gs}\) and \(C_{gd}\) of the input differential pair. Due to the samping transistor being in the OFF state, the kickback noise on the top plate of the CDAC will affect the front-end driving structure through the \(C_{ds}\) of the switch transistor and will also be coupled to the output end of the RVB through the CDAC, as shown in Figure 5. Both situations will present a limiting factor for ADC resolution. This paper proposes a dynamic comparator  
Figure 3: Architecture of the proposed SAR ADC.  
kickback noise cancellation technique that can effectively solve the degradation caused by the kickback noise on the CDAC top plate.