# Hardware-Based Architecture for DNN Wireless Communication Models
## 6 Experimental Results and Discussions
### Hardware Results  
This section shows BER verification results on hardware architectures designed to demonstrate that our hardware architectures work as designed. In addition, we also provide comparisons of the number of calculations performed for the conventional MIMO OFDM system and the proposed DL model systems. Then, the trade-off between performance and resource consumption is evaluated.  
Through the software simulation results, BER performances of model type I and model type II of the 4 \(\times\) 4 OFDM MIMO systems are better than those of the conventional systems. Therefore, the hardware designs of model type I and model type II are implemented for the 4 \(\times\) 4 OFDM MIMO systems. Meanwhile, BER performances of model type III of the 2 \(\times\) 2 OFDM MIMO systems are better than those of the conventional systems. Therefore, the hardware designs of model type III are implemented for the 2 \(\times\) 2 OFDM MIMO systems.  
Figures 20-25 show the hardware simulation results. We can see that the hardware results provide the same BER performances as their corresponding software results, i.e., the hardware architectures are designed successfully without any functional defects.  
Figure 20: BER versus SNR for the receiver hardware architectures with M = 2, ZF is used and the clipping level of the nonlinear PAs is 5 dB.  
Figure 21: BER versus SNR for the receiver hardware architectures with M = 2, ZF is used and the clipping level of the nonlinear PAs is 7 dB.  
Figure 22: BER versus SNR for the receiver hardware architectures with M = 4, ZF is used and the clipping level of the nonlinear PAs is 5 dB.  
Figure 23: BER versus SNR for the receiver hardware architectures with M = 4, ZF is used and the clipping level of the nonlinear PAs is 7 dB.  
Figure 24: BER versus SNR for the receiver hardware architectures with M = 4, MLD is used and the clipping level of the nonlinear PAs is 5 dB.  
Hardware design comparisons are presented in Table 3. In the proposed hardware design, the 32-bit fixed-point number is used to convert between quantization domains that are presented in the Section 5.2. The proposed designs using quantization numbers cost lower bit width than those designs using floating-point numbers, but the accuracy of our proposed designs remains unchanged.  
Table 3 shows that the proposed models can be entirely hardware implemented on the Virtex 7 vc709 FPGA board. To compare the complexity among the three models, the hardware resources of the lookup table (LUT), lookup table random access memory (LUT RAM), flip flop (FF), block random access memory (BRAM), digital signal processing unit (DSP), input/output pin (IO), global clock buffer (BUFG) are shown. From the implementation results, the 4 \(\times\) 4 model type II costs the highest resources since this model includes the DSP signal detection module, DNN noise prediction module, noise canceling module, and demapping module. Meanwhile, the 4 \(\times\) 4 model type I costs the smallest hardware resources since the noise canceling and the demapping modules are not used. The hardware resources of the 2 \(\times\) 2 model type III are quite high since the DNN module is large to replace for whole DSP signal detection and demapping modules. The complexity of hardware design also affects power consumption and processing latency. The higher complexity design costs larger power consumption and takes longer processing latency.  
Figure 25: BER versus SNR for the receiver hardware architectures with M = 4, MLD is used and the clipping level of the nonlinear PAs is 7 dB.