###### Abstract  
Electrostatically-defined quantum dots (QDs) in silicon are an attractive platform for quantum computation. Localized single electron spins define qubits and provide excellent manipulation and read-out fidelities. We propose a scalable silicon-based qubit device that can be fabricated by industry-compatible processes. The device consists of a dense array of QDs localized along an etched silicon nano-ridge. Due to its lateral confinement, a simple dense array of metallic top-gates forms an array of QDs with controllable tunnel-couplings. To avoid potential fluctuations because of roughness and charged defects at the nano-ridge sidewall, the cross-section of the nano-ridge is trapezoidal and bounded by atomically-flat [111] facets. In addition to side-gates on top of the low-defect oxidized [111] facets, we implement a global back-gate facilitated by the use of silicon-on-insulator. The most relevant process modules are demonstrated experimentally including anisotropic wet-etching and local oxidation of the silicon nano-ridge, side-gate formation with chemical-mechanical polishing, and top-gate fabrication employing the spacer process. According to electrostatic simulations, our device concept allows forming capacitively-coupled QD double-arrays or adjacent charge detectors for spin-readout. Defining a logical qubit or realizing a single electron conveyor for mid-range qubit-coupling will be future applications. electron spin qubit; silicon nano-ridge; TMAH-etching; MOS structure; interface defects; self-aligned spacer process; device simulation +
Footnote †: journal: Applied Physics Letters  
_Applied Physics Letters_  
rendered this progress possible, as qubit dephasing by randomly-fluctuating nuclear spins is largely suppressed [6; 13]. Since quantum error correction comes at the cost of requiring on the order of 1000 physical qubits to represent one logical qubit, reliable and reproducible manufacturing of individual qubits becomes mandatory to enable an up-scaling of the number of physical qubits in a multi-qubit device [3; 14]. Furthermore, the potential landscape setting the charge state and the tunnel barriers has to be homogeneous and well controllable by the voltages applied to metallic gates across the entire multi-qubit device [15]. Limiting factors include fabrication inaccuracy and most significantly potential disorder due to charged defects near the confined electron spin. Several approaches for forming QDs in silicon are being pursued by various research groups that exhibit different strengths and weaknesses [16]. The first types of devices are planar and confine electrons either in a strained undoped Si/SiGe quantum well [6; 10; 17] or at the Si/SiO\({}_{2}\) interface [13] along the out-of-plane direction. However, the lateral two-dimensional QD confinement requires elaborated multi-layer metallic gate stacks [17; 18], the fabrication of which is involved. The valley splitting of the strained Si/SiGe heterostructure is typically low and limits qubit coherence and operation temperature [18; 19; 20]. Progress in the growth of the Si/SiGe stack will lead to enhanced valley splittings [21]. The second type, planar metal-oxide-semiconductor (MOS) devices, exhibits conveniently large valley splittings of up to 1 meV [22], but potential disorder and strain due to the close vicinity of the oxide interface and the metal layers, respectively, are very challenging [23]. An alternative to these planar devices is modified fin field-effect transistor (FinFET) structures [12; 24; 25]. For the latter, a one-dimensional silicon channel etched from a silicon-on-insulator substrate sets the confinement in two dimensions. Hence, the complexity of the metal top-gates is reduced. These modified FinFET structures are compatible with industrial foundries and have been fabricated on 300-mm wafers. Hole spins and electron spins have been confined, and Pauli spin blockade was observed in double-quantum wells [26].