# A Survey of of Side-Channel Attacks and Mitigation for Processor Interconnects
###### Abstract  
With advancements in chip technology, the number of cores in modern commercial processors continues to rise, leading to increased complexity in interconnects and on-chip networks. This complexity, however, exposes significant security vulnerabilities, primarily in the form of side-channel and covert-channel exploits. Unlike other microarchitectural side-channel attacks, those leveraging on-chip interconnects utilize unique characteristics, allowing attackers to develop novel methods that can bypass existing effective defenses. In this paper, we present a comprehensive survey of current side-channel and covert-channel attacks based on processor-on-chip interconnects. We categorize these attacks into three types: contention-based, distance-based, and layout-based, according to the specific interconnect characteristics they exploit, and discuss corresponding countermeasures for each. Finally, we provide an outlook on future development trends in processor interconnect side channels. This survey is the first to specifically focus on interconnect-based side channels in processors. processor microarchitecture; interconnect; network-on-chip; side channel; covert channel +
Footnote †: journal: Applied  
0000-0002-431X/00/0000-0000-0000-0000-0000-0000-0000-0000-0000-0000-00000-0000-0000-00000-00000-0000-00000-00000-00000-00000-00000-00000-00000-00000-00000-00000-00000-00000-000000-00000-00000-00000-00000-00000-00000-000000-00000-000000-00000-000000-000000-000000-000000-000000-000000-However, on the one hand, these defensive measures inevitably incur additional performance overhead, while on the other hand, there are numerous undocumented components within the microarchitecture that may provide opportunities for side-channel attacks, but not all aspects have been sufficiently discussed [3]. In recent years, on-chip interconnect side-channel attacks have begun to attract attention. These interconnects are used to connect various resources on the chip, including physical cores, LLC, DRAM controllers, and I/O ports. On-chip interconnects are highly accessible; specifically, most accesses to the last-level cache and all accesses to DRAM must go through the on-chip interconnect. Therefore, restricting access to on-chip interconnects, similar to caches, is very challenging, implying a high correlation between on-chip interconnects and microarchitectural security. However, for a long time, especially since the emergence of side-channel attacks based on ring buses and mesh interconnects [20; 21; 22], there has been little discussion about defensive measures against on-chip interconnects. Since the advent of large-scale integrated circuit technology, people have been exploring ways to integrate more and smaller electronic components into one. Chips, as one of the most important technological products and application forms, have also seen their manufacturing processes shrink. The most advanced chip manufacturing process has reached 3 nm [23]. However, this is believed to be close to the physical limit, with factors such as quantum effects, tunneling effects, and electron migration posing significant challenges. While a further reduction in manufacturing process sizes may be limited in the near future, the pursuit of higher-performance processors has not ceased. Instead of further shrinking the manufacturing process, improvements are being made by integrating more cores, increasing chip areas, and developing more complex on-chip interconnects in multi-core processors. The 2022 International Roadmap for Devices and Systems (IRDS) projects that lithography technology will soon reach its limits, necessitating the introduction of new 3D structures in chip design and manufacturing [24]. This shift implies larger spatial scales and more cores, along with complex interconnect structures and their corresponding optimizations.