## 2 Related Works
### Typical RAM Cell  
Figure 4 shows logic diagrams of recently proposed RAM cells. Figure 4a is a logic diagram based on a majority vote gate, and this type of RAM cell has been most frequently proposed [17]. A 5-input majority vote gate is used to store values and is characterized by resetting to 0 (RESET) or setting to 1 (SET) depending on whether the values of SET and RESET are equal. Figure 4b is a multiplexer-based RAM cell logic diagram that selects either SET/RESET or IN as the input value based on the SEL function and then selects and outputs the input value or stored value based on the R/W value [20]. Figure 5 shows the logic diagrams of a RAM cell that can be expanded to an N \(\times\) N RAM among previously proposed circuits. Figure 5a was proposed by [PERSON] et al. [21] and used four AND gates, one OR gate, and one multiplexer. Figure 5b is the logic diagram proposed by [PERSON] et al. [22], designed using four AND gates, one OR gate, and one majority vote gate.  
Figure 3: Typical QCA 2-to-1 Multiplexers: (**a**) circuit developed by [PERSON] et al. [37]; (**b**) circuit developed by [PERSON] et al. [38]; (**c**) circuit developed by [PERSON] et al. [39]; (**d**) circuit developed by [PERSON] et al. [40]; (**e**) circuit developed by [PERSON] et al. [41]; (**f**) circuit developed by [PERSON] et al. [42].  
Figure 6 shows the previously proposed QCA RAM cells. Figure 6a is a RAM cell designed by [PERSON] et al. using a 5-input majority vote gate as a D-latch [17]. The circuit connects SEL (Select) and R/W (Read/Write) with an AND gate to transmit a selection signal to a 5-input majority vote gate. If both SET and RESET values are 1 or 0, the corresponding circuit stores and outputs 1 or 0, regardless of other input values. When the values of SET and RESET are different and SEL = R/W = 1, that is, when the corresponding RAM cell is activated and the Write function is executed, the value of IN is output and saved. Conversely, if at least one of the SEL and R/W values is 0, the previously stored value is output.  
Figure 6b is a QCA RAM cell designed by [PERSON] et al. using a rotated 3-input majority gate [20]. This circuit was designed based on a multiplexer implemented using a rotated 3-input majority gate, and one of the two multiplexers was modified to be a D latch. This circuit selects the value to be updated by IN or SET/RESET based on the value of SEL and transmits it to the D latch and outputs and stores the value to be updated based on the value of R/W, or outputs the previously stored value.  
The above two circuits cannot be used to design N x N type RAM because the value to be stored and the value to be output are the same. Figure 6c is a QCA RAM cell proposed by [PERSON] et al. [21]. Figure 6c shows the modification and design of the multiplexer into a D latch, but the values to be stored and the values to be output are set differently. This means that when SEL = 0, the stored value is not initialized and is continuously stored, and N \(\times\) N RAM can be designed using this function.  
Figure 4: Typical logic diagrams of non-expandable RAM cells: (**a**) 5-input majority vote gate-based RAM cell [17]; (**b**) multiplexer-based RAM cell [20].  
Figure 5: Typical logic diagrams of expandable RAM cells: (**a**) logic diagram proposed by [PERSON] et al. [21]; (**b**) logic diagram proposed by [PERSON] et al. [22].