## 3 Results and Discussion  
In order to further explore the programming capabilities and charge retention of the recently developed memory device, a series of thorough examinations were conducted. These examinations focused on analyzing the transfer characteristic responses under different programming conditions. The device's ability to undergo significant changes in threshold voltage (\(\Delta\mathrm{V_{th}}\)) when exposed to positive and negative gate biases was examined, demonstrating its responsiveness to various electrical stimuli from the external environment. Measurements taken following short 5 ms programming pulses at various gate voltages provided a comprehensive understanding of the electrical characteristics of the device. The noticeable changes in the drain current versus gate voltage curves (\(\mathrm{I_{d}}-\mathrm{V_{g}}\)) after applying positive gate pulses highlight the sensitivity and effectiveness of the device in efficiently adjusting the threshold voltage. The increase in programming voltage leads to a concurrent escalation in \(\Delta\mathrm{Vth}\), which is particularly noticeable as it rises from 11 V to 13 V. This highlights the significant level of control that can be achieved over the programming state of the device. The level of control demonstrated suggests the presence of a robust and reliable memory storage system in the device, which enables precise encoding of data by modifying the threshold voltage [15]. Conversely, the adaptability of the device in programming is further confirmed by its performance under negative gate pulses. The \(\mathrm{I_{d}}-\mathrm{V_{g}}\) curves exhibit a shift toward the negative direction, which becomes more pro  
Figure 1: Detailed schematic representation of the layered architecture within the memory device. nounced as the negative gate bias increases. This confirms the effectiveness of the device in retaining charge, even in reverse electrical situations. The increase in \(\Delta\text{V}_{\text{th}}\) from \(-12\) V to \(-14\) V, as shown in Figure 2b, indicates a broad operational range, allowing for flexible methods in memory programming and data archiving strategies [15]. When compared to a conventional a-IGZO TFT that does not have a specialized layer for charge storage and only has a 55 nm single-layer HfZrO as the gate dielectric, there is a significant difference in functional performance. Despite subjecting this standard device to considerably high gate biases of \(+30\) V\(/-30\) V over a prolonged ten-minute interval, negligible shifts in \(\Delta\text{V}_{\text{th}}\) were observed. This pronounced absence of CTM behavior in the pure TFT configuration vividly underscores the pivotal significance of the HfZrO layer within the enhanced memory device. In the absence of this layer dedicated to charge storage, the device is incapable of sequestering and preserving a sufficient quantity of electrons necessary for satisfying memory operation prerequisites. This juxtaposition clearly accentuates the fabricated memory device's superior capabilities in charge storage and programming efficiency, ascribed to its intricately architected structure that integrates HfZrO as a layer for charge storage. Such a design not only supports the capture of electrons at high density but also guarantees consistency and reproducibility in the programming actions of the device, positioning it as a formidable contender for cutting-edge memory technology applications. An investigation was conducted to analyze the fluctuations in threshold voltage (\(\Delta\text{V}_{\text{th}}\)) associated with various programming durations, as depicted in Figure 3a. The investigation employed a range of positive voltages, specifically from 11 V to 13 V, represented by a continuous line on the chart. This revealed significant differences in \(\Delta\text{V}\)th across this voltage range. These discrepancies distinctly illustrate the capacity for attaining multilevel attributes within a brief timeframe, extending from 5 ms to 30 ms.