# A Biologically Inspired Sound Localisation System Using a Silicon Cochlea Pair
## 2 Materials and Methods
### Binaural CAR-FAC Pre-Processing
The \(n\) instantaneous correlograms are averaged to form the onset correlogram. (**F**) The regression convolutional neural network (CNN); the onset correlogram is used to train the CNN to learn the azimuthal angle of the sound source. The details of the CNN will be described later in the Experiments and Evaluation section. In this system, the binaural CAR FAC and the onset correlogram have been implemented on Field Programmable Gate Array (FPGA), and the onset detection and the CNN were implemented on a PC, but can also be ported to FPGA. The mammalian cochlea exhibits an exponentially increasing delay along with the BM [43]. The CAR-FAC model also exhibits this effect where the channel delay is proportional to the inverse of the CFs for each cochlear channel and, therefore, scales exponentially. Figure 4 shows the channel delay of a 70-channel CAR-FAC in response to a speech signal. Figure 4A (blue line) highlights an exponentially increasing delay along the CAR-FAC channels. The maximum delay of the 70-channel CAR-FAC delay line to speech is around 6.5 ms. The exponentially increased delay of each section is also shown in Figure 4A (orange line). The largest section delay is in the last section, and it is around 0.5 ms.  
Figure 2: The binaural CAR-FAC system architecture. The system consists of an audio codec, a controller, a synchronisation circuit, an external Double Data Rate Synchronous Dynamic Random Access Memory (DDR) and two ’ears’. Each ear includes a CAR FAC module. The system provides two ways for sound input. One way is through the SSM2603 audio codec on the FPGA board, and a second provides recorded audio file input from the PC host through a USB 3.0 interface. There are two clock domains in the system: a system clock domain (250 MHz) and a synchronisation clock domain (100 MHz). The system clock domain includes the controller, the two CAR-FACs, and the Correlogram module. The synchronisation clock domain is unique to the synchronisation unit. The external memory is a 1 GB DDR3 SDRAM on the FPGA board: it stores the CAR-FAC output or the correlogram via a selector. The USB interface communicates between the FPGA board and the PC, and transmits the system’s initial parameters, and, if required, the input audio file from the PC to the FPGA board. The controller state machine determines the cochlear channel to be processed at any particular time and controls the CAR-FAC coefficients and data for that channel. The BM_start signal controls the start of the system through the controller, and it is triggered by the “Audio_in ready” signal. The ohc_sel is a selector switch for the CAR/CAR-FAC function. The agc_sel is a switch for the AGC loop function. The CAR state machine calculates the CAR transfer function and controls the DOHC and DIIHC_AGC start in the system. The DOHC state machine calculates OHC function and feeds back an updated \(r\) to the CAR. The DIIHC-AGC calculates the IHC function, as well as the AGC_loop function. The AGC output \(b\) feeds back to the DOHC module. The details of the module are presented in References [38,39]. The DIIHC-LI outputs of the two ’ears’ are used to generate correlograms in the correlogram module, which is presented in Reference [36]. The FPGA board is hosted by a PC through the USB interface. Figure 4B shows the DIHC-LI output over the DIHC. The LI is inspired by Reference [44] and for sharping the DIHC response temporally. The LI is implemented using a simple discrete difference operation between adjacent channels of the DIHC output:  
\[z(i,t)=DIHC(i,t)-DIHC(i+1,t) \tag{1}\]  
where \(i\) is the cochlear channel number, \(t\) is the discrete time, and \(z(i,t)\) is the LI output.