## 5 Simulation Verification  
In this section, simulations were conducted in PSCAD. The main simulation parameters are shown in Table 1 below. The data were sourced from the Electrical Engineering Laboratory at North China University of Water Resources and Electric Power. Figure 10: Control Block Diagram of the Improved Control Strategy for VSG. (1) Simulation Comparison of Improved DSOGI-PLL  
The simulation configuration is as follows: Between 1 s and 2 s, an asymmetric voltage sag containing harmonics occurs in the three-phase grid voltage. Specifically, the BC-phase voltage decreases to 70% of the nominal voltage, whereas the A-phase voltage drops to 50% of the BC-phase voltage. Furthermore, each of the three-phase voltages includes a 20% component of the 5 th harmonic, a 10% component of the 7 th harmonic, and a 5% component of the 11 th harmonic. Figure 11 contrasts the frequency response of the conventional DSOGI-PLL with the enhanced AHE-DSOGI-PLL, which incorporates harmonic pre-elimination. Both PLLs achieve 0 dB gain at 50 Hz and maintain a phase margin. However, in the high-frequency range, the improved DSOGI-PLL outperforms the traditional version in suppressing harmonics. As a result, the conventional DSOGI-PLL struggles to accurately leading to issues with the VSG's low-voltage ride-through control system. Figure 12a shows the d-axis voltage waveform using the traditional DSOGI-PLL, and Figure 12b shows the positive-sequence d-axis voltage waveform using the improved DSOGI-PLL. It can be observed that the positive-sequence d-axis voltage under the traditional DSOGI-PLL experiences fluctuations within 15 V due to harmonic interference. In contrast, the improved DSOGI-PLL, which incorporates a harmonic elimination module in advance, exhibits a stable positive-sequence d-axis voltage during the fault, stabilizing at 184.5 V with negligible fluctuation amplitude. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameters** & **Value** & **Parameters** & **Value** \\ \hline Input voltage (Vdc/V) & 800 & Grid inductor (L\({}_{\text{g}}\)/mH) & 0.2 \\ Grid voltage (Vg/V) & 311 & Grid resistance (R\({}_{\text{g}}\)/\(\Omega\)) & 0.1 \\ Filter inductor (L\({}_{\text{f}}\)/mH) & 3.2 & J/kg/m\({}^{3}\) & 90 \\ Filter capacitor (C\({}_{\text{f}}\)/uF) & 10 & Damping/D & 0.7 \\ Damping resistance (R\({}_{\text{f}}\)/\(\Omega\)) & 0.1 & Switching frequency (fs) & 20 kHz \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Simulation-related Parameters. Figure 11: Frequency response with Different Phase–Locked Loops. Figure 13 compares the frequencies obtained by two different PLLs. It can be observed that the grid voltage frequency obtained by the traditional DSOGI-PLL, under asymmetric fault conditions with harmonic distortion in the grid voltage, experiences fluctuations of 0.6 Hz, which fails to meet the frequency detection standards. In contrast, the improved DSOGI-PLL can quickly and accurately obtain the grid voltage frequency, with a deviation of only 0.005 Hz from the power frequency of 50 Hz. Figure 12: Grid Voltage with Different Phase\(-\)Locked Loops. Figure 13: Frequency Comparison of Different Phase-Locked Loops. In conclusion, the enhanced DSOGI-PLL effectively extracts the positive and negative sequence components as well as the frequency of the grid voltage during asymmetric faults with abundant harmonics. Its precise frequency detection also allows for accurate phase determination. Conversely, the conventional DSOGI-PLL fails to perform similarly under intricate grid fault conditions. (2) Simulation of VSG Low-Voltage Ride-Through Under Complex Grid Faults  
The simulation settings for the VSG LVRT control strategies are identical to those used for PLL simulations. Figure 14 depicts the grid-connected current when using the traditional VSG LVRT control strategy paired with an enhanced PLL, while retaining the standard grid voltage feedforward control. Figure 14b showcases the grid-connected current when employing the traditional dsogi-pll alongside the grid voltage feedforward control method.