## 5 Evaluation and Analysis
### Experimental Results and Analysis with IOMeter Tool
#### 5.3.1 Uncorrectable Page Errors  
As the program and erase cycles (P/E cycles) increase, the bit error rate (BER) increases correspondingly. Table 5 presents the number of uncorrectable page errors under two levels of wear, which are 1000 and 3000 P/E cycles. The objective is to quantify the error correction capability beyond the built-in ECC when the NAND flash is in a normal condition and a nearly worn out condition. The maximum number of P/E cycles of the NAND flash chip used in the experiment was 3000. In Table 5, \"ECC strength\" indicates the number of bits of errors that can be corrected by the BCH code for one physical page. The workload generated by the IOMeter was configured with 50% random requests and 50% read accesses and lasted for 10 minutes.  
\begin{table}
\begin{tabular}{l c c c c c c c c c c} \hline \hline \multirow{2}{*}{**ECC**} & \multicolumn{4}{c}{**1000 P/E Cycles**} & \multicolumn{4}{c}{**3000 P/E Cycles**} \\ \cline{2-10}  & \# of Uncorrectable Page Errors & \multicolumn{2}{c}{**Reduction (\%)**} & \multicolumn{2}{c}{**\# of Uncorrectable Page Errors**} & \multicolumn{2}{c}{**Reduction (\%)**} \\ \cline{2-10}  & **BL** & **MC** & **AP** & **AP vs. BL** & **AP vs. MC** & **BL** & **MC** & **AP** & **AP vs. BL** & **AP vs. MC** \\ \hline
0-bit & 9647 & 6572 & 5716 & 40.75 & 13.04 & 12,947 & 12,937 & 8133 & 37.18 & 37.13 \\
1-bit & 6270 & 3589 & 1384 & 77.93 & 61.43 & 8238 & 7197 & 3208 & 61.06 & 55.43 \\
2-bit & 2559 & 1002 & 295 & 88.47 & 70.56 & 4667 & 4177 & 1243 & 73.34 & 70.24 \\
3-bit & 1328 & 361 & 57 & 95.71 & 84.21 & 2331 & 1230 & 532 & 77.18 & 56.75 \\
4-bit & 658 & 135 & 11 & 98.33 & 91.85 & 1106 & 570 & 170 & 84.63 & 70.18 \\
5-bit & 316 & 53 & 3 & 99.05 & 94.34 & 539 & 141 & 53 & 90.17 & 62.41 \\
6-bit & 165 & 27 & 2 & 98.79 & 92.59 & 250 & 80 & 15 & 94.00 & 76.67 \\
7-bit & 66 & 7 & 2 & 96.97 & 71.43 & 120 & 30 & 7 & 94.17 & 76.67 \\
8-bit & 66 & 7 & 2 & 96.97 & 71.43 & 32 & 4 & 4 & 87.50 & 0.00 \\ Average & & & & 88.11 & 72.32 & & & & & 77.69 & 56.67 \\ \hline \hline \end{tabular}
\end{table}
Table 5: The number of uncorrectable page errors for Baseline, Meta-Cure, and Asymmetric Programming with different ECC strengths with a P/E cycle of 1000 and a P/E cycle of 3000 (BL: Base Line; MC: Meta-Cure; AP: Asymmetric Programming).  
Figure 11: The system architecture and illustration of the data flow with IOMeter  
From the experimental results, it can be seen that the number of uncorrectable pages decreases dramatically as ECC strength increases. Although Meta-Cure can reduce the number of error pages significantly, our proposed Asymmetric Programming can further improve the performance and cause the error rate to be maintained at a very low level. When the P/E cycles are 1000 times, compared with the baseline scheme, Asymmetric Programming can avoid up to 40.75% of page errors even without any ECC (0-bit ECC).  
If Asymmetric Programming is combined with the BCH code, reduction in page errors of at least 77.93% can be achieved. Compared with Meta-Cure, our proposed Asymmetric Programming can reduce page errors by 72.32% on average, which means that Asymmetric Programming can improve the reliability of system critical page by 72.32% compared to Meta-Cure. When the P/E cycles are 3000, the NAND flash is on the verge of wearing out. The number of uncorrectable pages increases sharply as shown in Table 5. However, Asymmetric Programming can still reduce error pages by up to 94.17%. Compared to the baseline scheme and Meta-Cure, Asymmetric Programming can also reduce the number of uncorrectable page errors by an average of 77.69% and 56.67%, respectively. These results show that Asymmetric Programming can work effectively even if the NAND flash is approaching its maximum lifetime. Through the behavior of Asymmetric Programming under the two levels of wears, we can conclude that Asymmetric Programming effectively enhances the reliability of critical pages during the whole lifetime of NAND flash memory.