## 4 Simulation and Performance Analysis  
In this section, QCADesigner 2.0.3 and its extended version, QCADesigner-E 2.2, are used to measure QCA performance and energy dissipation [43; 44]. They each use  
Figure 8: QCA implementation of the proposed RFAS: (**a**) top view; (**b**) first layer; (**c**) second layer; (**d**) third layer. Figure 9: Simulation results of the proposed RFAS circuit. \"Bistable Approximation\" and \"Coherence Vector with Energy\" as simulation engines, and the related parameters are summarized in Table 3.  
Recently, with the rapid development of hardware, the importance of delay is evaluated more highly than area. Therefore, Equation (7) is the most commonly used cost calculation formula including area and delay [45,46]. Here, area and delay refer to the rectangular area and clock phase required for circuit design, respectively. In particular, the area of a multi-layer structure is the flat area multiplied by the number of layers. Equation (6) is applied to the area of a multilayer structure. \[Area_{multi-layer}=Area_{single-layer}\times m \tag{6}\]  
where \(m\) is the number of layers on a multi-layer structure to reflect the higher area cost of a multi-layer design over a coplanar structure [24,45]. As shown in Table 4, the proposed circuit performs both reversible full adder and full subtractor, and has the best performance and cost in terms of number of cells, area, delay, and \(Cost_{AD}\). Compared to the best existing structure in [37], it showed significant improvements of 67% and 180% in delay and \(Cost_{AD}\). Due to the rapid development of hardware, delay is becoming more important than area, so \(Cost_{AD}\) is proportional to the square of delay. \[Cost_{AD}=A\times D^{2} \tag{7}\]  
where \(A\) and \(D\) refers to the area and the delay of a circuit, respectively. Equation (8) is a standard design cost measurement method including energy dissipation and delay [44,45]. The importance of energy dissipation is viewed as being equal to delay, and \(Cost_{ED}\) is proportional to the square of energy dissipation and the square of delay. \[Cost_{ED}=E^{2}\times D^{2} \tag{8}\]  
where \(E\) and \(D\) refers to the energy dissipation and the delay of a circuit, respectively [47]. Avg_Ebath and Sum_Ebath in Table 5 indicate the average energy dissipation per cycle and the total energy dissipation for all coordinates, respectively [48, 49, 50, 51]. Both Avg_Ebath and \begin{table}
\begin{tabular}{c c c} \hline \hline  & **QCADesigner 2.0.3** & **QCADesigner-E 2.2** \\ \hline
**Parameters** & **Bistable Approximation** & **Coherence Vector with Energy** \\ \hline Cell size (nm) & 18 & 18 \\ Dot diameter (nm) & 5 & 5 \\ Cell separation (nm) & 2 & 2 \\ Layer separation (nm) & 11.5 & 11.5 \\ Clock high (J) & \(9.8\times 10^{-22}\) & \(9.8\times 10^{-22}\) \\ Clock low (J) & \(3.8\times 10^{-23}\) & \(3.8\times 10^{-23}\) \\ Clock shift & 0 & 0 \\ Clock amplitude factor & 2.0 & 2.0 \\ Relative permittivity & 12.9 & 12.9 \\ Radius of effect (nm) & 65 & 80 \\ Number of samples & 12,800 & - \\ Convergence tolerance & \(1.0\times 10^{-3}\) & - \\ Maximum iterations per sample & 100 & - \\ Temperature (K) & - & 1 \\ Relaxation time (s) & - & \(1.0\times 10^{-15}\) \\ Clock slope (s) & - & \(1.0\times 10^{-12}\) \\ Time step (s) & - & \(1.0\times 10^{-16}\) \\ Clock/input period (s) & - & \(4.0\times 10^{-12}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Simulation engines and parameters. Sum_Ebath showed an improvement of 54% compared to the existing circuit in [37], which had the lowest energy dissipation, and \(\mathit{Cost}_{ED}\) achieved a remarkable reduction of 562%. \[\mathrm{AOP}=\sum_{\mathrm{d}}^{n}\frac{\mathrm{Max\ Polarization}-\mathrm{Min\ Polarization}}{2n} \tag{9}\]  
The average output polarization (AOP) is an important indicator of the output strength of a circuit [48].