# Research Progress on Flexible Oxide-Based Thin Film Transistors
## 3 Approaches to Flexible Oxide-Based TFTs
### Flexible TFTs on Different Kinds of Substrates
#### 3.1.3 Polyimide (PI) Flexible Substrate  
According to Figure 2, PI substrates are high-temperature polymers, exhibiting a superior performance with a CTE of 12 \(\times\) 10\({}^{-6}\) K, a small humidity expansion coefficient (HEC) (9 \(\times\) 10\({}^{-6}\)% RH), a high T\({}_{g}\) of 360 \({}^{\circ}\)C, and a surface roughness in the nanometer range. Although the standard PI exhibits a yellowish to brownish color, PI is the most frequently used kind of substrates. Recently, colorless and transparent polyimide (CPI) films and their analogues occupy the leading edge positions in advanced polymer optical films in terms of their comprehensive properties and potential market volume, including polyamideimide (PAI) and polyethermimide (PEI) [149]. Figure 6: (**a**) Schematic of TFT with the dielectric of anodized aluminum oxide. (**b**) AMOLED on a PEN substrate [156]. As shown in Figure 7a, a high-\(\kappa\) HfLaO gate dielectric was fabricated in an a-IGZO TFT on a PI substrate [76]. Due to the high-k gate dielectric, this device exhibits a low threshold voltage of 0.1 V, a small subthreshold swing of 0.18 Vdec\({}^{-1}\), a high mobility of 22.1 cm\({}^{2}\) V\({}^{-1}\) s\({}^{-1}\) and an acceptable on/off ratio of 2 \(\times\) 10\({}^{5}\), making it possible for portable applications. [PERSON] et al. reported a type of oxide semiconductor TFT formed by a solution process [157]. In this device, the active layer film was enhanced by co-doping Li and Zr. Depending on the annealing temperature, these devices exhibited variable performance. Dual gate a-IGZO TFTs on PI substrates were presented by [PERSON] [158; 159]. The structure of TFTs on PI substrate is shown in Figure 7b, 35 nm Ti was evaporated as a bottom gate, while 50 nm Cr was used as a top gate. With the dual gate structure, the gate capacitance was increased by 78% and the threshold voltage was higher (700 mV), while the transconductance was nearly double. Hence, the performance of the device was improved as well, such as the subthreshold swing of 69 mV dec\({}^{-1}\) and the on/off ratio of 2 \(\times\) 10\({}^{9}\). While the self-alignment could also be used in fabricating the device. The S/D to gate overlaps as small as 1 \(\upmu\)m led to parasitic overlap capacitances of 5.5 Hfum\({}^{-1}\). As a consequence, the frequency of the TFT reached 5.6 MHz. [PERSON] and his co-workers presented a type of a-IGZO memory TFTs as shown in Figure 7c. In this device, 100 nm-thick P(VDF-TrFE) was used as a floating gate and formed using spin-coating a solution of 1 wt% VDF (70 mol%) and TrFE (30 mol%) in methyl-ethyl-ketone. The deposited film was crystallized at 140 \({}^{\circ}\)C for 15 min in ambient air. The thickness and the recipe of the P(VDF-TrFE) layer were optimized to obtain Fe-TFTs capable of low-voltage operation (<10V). The results shown that the mobility was 8 cm\({}^{2}\) V\({}^{-1}\) s\({}^{-1}\), the on/off ratio was 1.7 \(\times\) 10\({}^{7}\), the subthreshold swing was 152 mVdec\({}^{-1}\) and the gate leakage current I\({}_{\text{G}}\) was confirmed to be smaller than 10\({}^{-10}\) A [50]. Nevertheless, the stability on mechanical stress should be further improved. Figure 8 illustrates a type of IGZO-TFT with high reliability under bending tests. This device employed a thermally stable SA7 organic material as the multi-functional barrier and dielectric layers [160]. The fabricated TFTs exhibited a good performance with a mobility of 15.67 cm\({}^{2}\) V\({}^{-1}\) s\({}^{-1}\), a threshold voltage of 6.4 V and an on/off ratio of 4.5 \(\times\) 10\({}^{5}\). Furthermore, bending tests were carried out. After 1000 bending cycles under a bending strain of 3.33% and a bending radius of 1.5 mm, no significant device degradation could be observed. Figure 7: Schematic of TFTs on PI: (**a**) with a high-\(\kappa\) HfLaO as a gate dielectric, (**b**) dual gate structure with the conventional process at room temperature, (**c**) with a ferroelectric poly as a buried gate. Recently, [PERSON] and [PERSON] et al.