## 1 Introduction
Here, we focus on publications from the past few decades. In [4], the cuckoo search optimization method is compared with the binary particle swarm optimization algorithm, the genetic algorithm, and the deterministic algorithms NOVA [5] and JEDI [6]. In [7], traditional Boolean algebra and Reed-Muller logic are proposed for minimizing the FSM area. In [8], the evolutionary algorithm called GP-ES is discussed, demonstrating good results in the design of small- and medium-sized FSMs. In [9], probabilities for each pair of code substitutions are proposed. In [10], the multi-population evolution strategy, denoted as MPES, is introduced, utilizing inner-ES and outer-ES evolution to address the problem. In [11], a method is proposed to minimize the area of Moore FSMs by representing state codes as concatenations of codes from pseudo-equivalent state classes and collections of output functions. A similar approach for state encoding in Mealy FSMs is suggested in [12]. In [13], state encoding utilizes the values of output variables, while in [14], the input variables of FSMs are used for this purpose. In [15], multiplexers are added to the FSM circuit to use the values of output variables as state codes. In [16], anti-race state encoding is proposed for designing robust FSMs. Several works focus on FSM state encoding for protection against unwanted attacks. In [17], a secure state encoding method for FSMs is presented to protect against power analysis attacks. In [18], a state encoding method to defend against Laser Fault Injection (LFI) attacks is introduced. In [19], a CAD tool for state encoding of FSMs robust to multiple LFI models is presented. In [20], differential power analysis (DPA) and fault injection attacks (FIAs) on FSMs are considered. Numerous studies are dedicated to FSM state encoding for power consumption reduction. A comprehensive review of these methods is provided in [21]. In [22], a sequential algorithm, and in [23], an iterative algorithm for FSM state encoding are proposed to minimize dynamic power consumption. In [24], varying the length of state codes is suggested for the same purpose. Additionally, the authors of [25] present a state encoding method aimed at minimizing power consumption using binary particle swarm optimization and flip-flop selection. Several studies focus on designing fault-tolerant FSMs. In [26], a heuristic algorithm for state encoding is proposed to mitigate the effects of transient faults. In [27], a method for FSM state encoding using stochastic numbers is introduced. However, despite the extensive research on FSM state encoding, there is a lack of studies focused on methods tailored for modern electronic devices such as CPLDs, FPGAs, and ASICs. This paper introduces a heuristic approach for FSM state encoding that sequentially selects states and assigns the most appropriate codes based on a combination of state selection and code selection modes. Our method aims to optimize both the area and performance of FSM implementations by leveraging the internal relationships between states and the specific architectural characteristics of the target hardware. We propose several state selection modes (P, C, P_C, max_C, and max_X) to account for the intricate interconnections between FSM states. Additionally, we introduce code selection modes (FPGA, CPLD, diff_w, and max_w) that align with the architectural features and optimization goals of various hardware platforms. By combining these modes, we construct a diverse set of sequential state encoding methods tailored to different optimization objectives. The proposed approach is intended for practical use in FSM implementations not only in FPGAs but also in CPLDs and ASICs.