## 4 Implementation Results and Comparisons
### Comparison to State of the Art
#### 4.3.1 Comparison to Bit-Parallel Systolic Multiplier Architectures
Likewise, our scalable design of Figure 7 utilizes 6.09 (ratio of 22,864 with 3753), 25.17 (ratio of 94,498 with 3753) and 14.98 (ratio of 56,223 with 3753) times lower hardware resources. The reason for the use of higher \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline
**Ref \#/Year** & **Multiplier** & **m** & **Device** & **Slices** & **CCs** & **Freq. (MHz)** & **Latency** & **Pwr. (in W)** \\ \hline
[17]/2022 & bit-parallel systolic & 163 & Virtex-7 & 32,685 & – & – & – & 5.277 \\
[18]/2008 & bit-parallel systolic & 163 & Virtex-7 & 154,635 & – & – & – & 3.600 \\
[19]/2008 & bit-parallel systolic & 163 & Virtex-7 & 105,787 & – & – & – & 6.187 \\
[20]/2017 & bit-parallel systolic & 163 & Virtex-7 & 66,434 & – & – & – & 2.848 \\
[21]/2021 & bit-parallel systolic & 233 & Virtex-7 & 22,864 & – & – & – & 0.717 \\
[22]/2015 & bit-parallel systolic & 233 & Virtex-7 & 94,498 & – & – & – & 2.148 \\
[23]/2018 & bit-parallel systolic & 233 & Virtex-7 & 56,223 & 233 & 44 & 5.295 \(\upmu\)s & 1.192 \\
[24]/2021 & overlap-free Karatsuba & 409 & Artix-7 & 49,211 * & – & – & – & – \\
[26]/2018 & Montgomery & 521 & Virtex-7 & 20,695 * & 7 & 99.68 & 0.070 \(\upmu\)s & – \\
[27]/2022 & similar to Karatsuba & 409 & Spartan-7 & 40,056 * & – & – & – & – \\ \hline Figure 2 & digit-parallel & 163 & Virtex-7 & 1182 & 1 & 500 & 0.002 \(\upmu\)s & 3.201 \\ Figure 3 & digit-parallel & 233 & Virtex-7 & 1451 & 1 & 476 & 0.00210 \(\upmu\)s & 3.326 \\ Figure 5 & digit-parallel & 409 & Artix-7 & 6128 * & 1 & 468 & 0.00213 \(\upmu\)s & 3.632 \\ Figure 5 & digit-parallel & 409 & Spartan-7 & 6784 * & 1 & 457 & 0.00218 \(\upmu\)s & 3.541 \\ Figure 6 & digit-parallel & 571 & Virtex-7 & 6943 * & 1 & 443 & 0.00225 \(\upmu\)s & 3.726 \\ Figure 7 & scalable digit-parallel & BFL & Virtex-7 & 3753 & 4 & 305 & 0.01311 \(\upmu\)s & 3.905 \\ Figure 7 & scalable digit-parallel & BFL & Artix-7 & 8019 * & 4 & 331 & 0.01208 \(\upmu\)s & 4.251 \\ Figure 7 & scalable digit-parallel & BFL & Spartan-7 & 8653 * & 4 & 316 & 0.01265 \(\upmu\)s & 4.016 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Comparison of our proposed dedicated and scalable least-significant digit-parallel multiplier(s) over \(GF(2^{m})\) with state-of-the-art multipliers. hardware resources in [21; 22; 23] is the systolic multiplication designs. In these architectures, several small arrays are employed in parallel to multiply and accumulate for obtaining the resultant polynomial after multiplication. In our dedicated and flexible architectures, we have performed several smaller polynomial multiplications in parallel to each other using a schoolbook multiplication method. The use of a schoolbook method results in lower hardware resources (in terms of FPGA slices). Apart from the hardware resources, the proposed dedicated and flexible architectures consume more power as compared to multiplier designs published in [21; 22; 23]. One factor behind the consumption of more power is the higher clock frequency in our dedicated and flexible architectures, while the state-of-the-art designs are operating on a lower clock frequency (given in column seven of Table 2). For example, the multiplier design of [23] can operate at a maximum frequency of 44 MHz, while our dedicated and flexible architectures can operate at 476 and 305 MHz. Due to the higher operational frequencies, our dedicated and flexible designs are comparatively 2521 (ratio of 5.295 \(\upmu\)s with 0.00210 \(\upmu\)s) and 403.89 (ratio of 5.295 \(\upmu\)s with 0.01311 \(\upmu\)s) times faster in terms of latency as compared to [23].