## 5 Simulations Results  
Simulations are carried out considering the parameters in Table 1. Since 8 sub-modules per stack are used, the topology comprises a total of 48 H-bridges. The input and output voltage values have been defined for a typical MVdc distribution system. Since the focus of this paper is on the control strategy for the double-T topology, the design aspects of the converter are not addressed in detail. However, general design procedures reported in [32; 34; 35] were followed. Regarding the nomenclature used to show the results, the capacitor of the first H-bridge of the _series\({}_{1,2}\)_, _derivation\({}_{1,2}\)_, and _output\({}_{1,2}\)_ stacks will be called \(v_{c_{1s+2}}\), \(v_{c_{1d+1,2}}\) and \(v_{c_{1d+2}}\), respectively. In the first test, simulations for load changes applied at t = 0.4 s, t = 0.8 s, and t = 1.2, are performed. Figure 8a shows one dc-link voltage per stack. As can be seen, the energy balance controller responds satisfactorily and very small variations in the dc-link voltages are obtained when the load changes. The voltage reference for all the dc-links has been set to 3 kV. Figure 8b shows the output power. From 0.8 to 1.2 s the output power is nominal. Figure 9 shows the 24 voltage waveforms of the dc-links of the \(T_{1}\) structure whereas Figure 10 shows the dc-link voltages associated with the \(T_{2}\) struct \begin{table}
\begin{tabular}{c c} \hline \hline
**Description** & **Value** \\ \hline Input voltage, \(HVDC_{1}=V_{in}\) & 23000 \(\mathrm{[V]}\) \\ Output voltage, \(HVDC_{2}=V_{o}\) & 13000 \(\mathrm{[V]}\) \\ Rated output power, \(p_{out}\) & 1.25 \(\mathrm{[MW]}\) \\ Dc-links capacitors, \(C_{sc_{1,2}}=C_{dc_{1,2}}=C_{0,2}\) & 1 \(\mathrm{[mF]}\) \\ Arm inductances, \(L\) & 2.5 \(\mathrm{[mH]}\) \\ Series equivalent resistance of inductors, \(R\) & 50 \(\mathrm{[mG]}\) \\ Dc-links reference voltage & 3000 \(\mathrm{[V]}\) \\ Frequency of ac circulating currents & 500 \(\mathrm{[Hz]}\) \\ Number of H-bridges per stack & 8 \\ Number of arms & 6 \\ Switching frequency, \(f_{sw}\) & 2 \(\mathrm{[kHz]}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Simulation parameters. Figure 8: (**a**) One dc-link voltage per stack. (**b**) Converter output power. of the control scheme can be appreciated, with a minimum variation on the dc-link voltages when the load varies. The converter output voltage and input current are shown in Figure 11, both presenting very low ripple. The spectra associated to these waveforms are shown in Figure 12. In both waveforms, the THD is lower than 1% with respect to the fundamental frequency, which in this case is 0 Hz. The average voltage value is \(V_{0_{0 Hz}}=13\) kV and the average current is \(I_{In_{0 Hz}}=53\) A. As the number of sub-modules per stack are 8 and the switching frequency is 2 kHz, the harmonic components appear around 32 kHz (since the H-bridge doubles the equivalent switching frequency). Figure 10: \(T_{2}\) dc-link voltages. (**a**) _series_\({}_{2}\) stack. (**b**) _derivation_\({}_{2}\) stack. (**c**) _output_\({}_{2}\) stack. Figure 9: \(T_{1}\) dc-link voltages. (**a**) _series_\({}_{1}\) stack. (**b**) _derivation_\({}_{1}\) stack. (**c**) _output_\({}_{1}\) stack. Figure 13 shows the currents of each converter arm. The currents in the _series_ and _derivation_ stacks are shown in Figure 13a,b, respectively. It can be noted that these currents have both ac and dc components. On the other hand, the current in the _output_ stacks in Figure 13c is mainly dc with a small ac component. It is important to note that the currents \(i_{\text{sc1}}\) and \(i_{\text{sc2}}\) must be phase-shifted 180\({}^{\circ}\) so that the converter input current \(I_{in}\) has negligible ac component (see Figure 11b). Figure 14 shows results for power variation and changes in the dc-link voltage reference. One dc-link voltage per stack is shown in Figure 14a and the output power is presented in Figure 14b. At t = 0.5 s a change in the reference of the dc-link voltages from 3 kV to 3.6 kV is applied.