# Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM
## 3 Design of an Adaptive Fault Tolerance Mechanism
### Case Example: Intermittent Fault Detection  
As a case example, we have designed an adaptive memory controller able to detect intermittent faults. For the sake of simplicity, we have assumed that only single faults can occur, at least before the system wearout. Given the fault hypothesis, the system will use two ECCs generated by using the FUEC methodology [14]: a typical Hsiao-based (39, 32) SEC-DED code [57] and an EPB3932 [58]. The EPB3932 code is also a (39, 32) code, but with some special features: it has asymmetric error control (it is an Unequal Error Control, UEC, code) so that it can tolerate intermittent faults in one bit, marked as an error-prone bit (EPB). It was generated to be able to correct single errors, double (both adjacent and random) errors that contain the EPB, and triple-adjacent errors containing the EPB; it also can detect double-adjacent errors (not containing the EPB). SEC-DED is a common ECC used in memory systems. EPB3932 is a code with the same redundancy (7 bits) as SEC-DED, but it has unbalanced correction capabilities, as it overprotects the corresponding EPB. It is important to remark that, as the EPB3932 applies special error control to the EPB, unlike the SEC-DED, this code is not uniform for all 39 bits in the codeword. Instead, there is a different EPB3932 code for each bit, and each of them has its associated \"ECC Encoder\" and \"ECC Decoder\" modules. In this case example, the only monitoring mission of the _error monitor_ module is to detect the occurrence of an intermittent error in a memory bit. For this reason, we have named this module an \"Intermittent Error Detector\" in Figure 2.  
Figure 4 shows the block diagram of the \"Intermittent Error Detector\" module. There, notice the 39 error counters, one per codeword bit. Regarding Equation (1), in the counters, \(J\) (generated by the \"Syndrome Decoder\") represents now that an error has been corrected in the corresponding bit, and \(dec=1\). If \(dec=0\), the counter would be simpler, but it may detect false positives. By setting \(dec=1\), only errors corrected consecutively in the same bit will be considered as originated by intermittent faults. From our fault hypothesis, we assume that the occurrence of consecutive errors (as many as the \(\alpha_{\text{TH}}\) threshold) in the same bit is very unlikely unless they are due to an intermittent error. Hence, we have considered that consecutive errors corrected in the same bit must belong to the same memory word. For this reason, the number of error counters in the \"Intermittent Error Detector\" coincides with the codeword length (i.e., 39). The operation of the \"Adaptive Memory Controller\" module is as follows: When the system starts, the SEC-DED code is selected as encoding mode. When a read error is corrected in bit \(i\), the \"Intermittent Error Detector\" module increases the \"BITi counter\" (and decrements the other counters). If the count surpasses the predetermined threshold (\(\alpha_{\text{TH}}\)), then an alleged intermittent fault is detected, and the bit \(i\) is marked as EPB. In that case, the \"Intermittent Error Detector\" module activates the \"INTERMITENT ERROR DETECTED\" signal and sets \"ERROR PRONE BIT\" and \"ENCODING MODE\" values to force the reconfiguration of the adaptive memory controller. Then, the system should switch the \"ECC Encoder\", the \"ECC Decoder\", and the \"Syndrome Decoder\" circuits to those of the EPB3932 code for the bit \(i\). Figure 4: Block diagram of the “Intermittent Error Detector” module in Plasma_ADAPTIVE core. To implement the Plasma_ADAPTIVE model, we have modified the VHDL description of the Plasma model [24], implementing all the modules described. We have tried two different synthesis strategies. First, we have synthesized the system in a non-reconfigurable device (see description in Section 4.5). We will refer to this version as \"static\". Figure 5 shows a detail of the \"Adaptive Memory Controller\" for this synthesis approach.