# A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs
## 3 ADC Implementation  
A 12-bit pipeline ADC was designed as the readout circuit in a CMOS image sensor. Since the pixel output behaves like a DC signal and sample-to-sample conversion of the pixel signal is performed by the ADC, a static performance, especially differential nonlinearity, is more important than a dynamic performance and capacitor mismatch calibration is needed for this purpose. A block diagram of the ADC is shown in Figure 6. The ADC was composed of eight 1.5-bit stages followed by a 4-bit flash ADC as the final stage, a reference generation circuit, and distributed clock drivers. A simplified circuit for the first stage is shown in Figure 7. Because the ADC did not have a dedicated front-end sample or hold amplifier, the sub-ADC of the first stage had its own input sampling network that held the input signal while the comparator made its decision. The second stage was similar to the first and was a scaled-down version of the first stage, except that the sub-ADC did not have a sampling network. Capacitor mismatch calibration was performed only for the first and second stages. Therefore, from the 3 rd stage, the circuit configurations were similar to that of the conventional 1.5-bit pipeline stage. An op-amp of the MDAC was shared between two adjacent stages to reduce power consumption [22]. During calibration, the mismatch error between each C\({}_{\text{S}}\) and C\({}_{\text{F}}\) was amplified and converted into a digital signal, as explained in the previous section. During normal operation, the ADC output code was corrected by adding or subtracting the converted error voltage whenever the digital output value of the calibrated stage was either \"00\" or \"10\". A simplified circuit of the op-amp with a gain-boosting amplifier is shown in Figure 8. A folded-cascode architecture with PMOS input transistors was employed to set the input common-mode (CM) voltage lower than the output CM voltage, and the output cascade transistors were gain-boosted to increase the DC gain of the op-amp without reducing the output signal swing. The switched-capacitor CM feedback circuit proposed in [23] was utilized to determine the output CM voltage of the op-amp. As shown in Figure 8, a simple differential pair was utilized as the gain-boosting amplifier. A PMOS transistor (M3) was added between the input transistors for CM control of the amplifier. The simulated DC gain of the op-amp was higher than 90 dB for all the corners. Figure 6: Block diagram of the ADC. Bandwidth of the op-amp was derived from the first order approximation of the amplifier transfer function. During the amplification phase, the op-amp is placed in feedback with a feedback factor (\(\updelta\)) of 1/2, and the op-amp output voltage in the first MDAC needs to settle within a half LSB voltage for 11-bit resolution. This requires a settling time of 7.6 times time constant (\(\uptau\)), which should be smaller than a half clock cycle, i.e., 16.7 ns. The resulting \(\uptau\) is about 2.2 ns and the unity-gain bandwidth of the op-amp, which is calculated as 1/(2\(\uptau\).8-\(\uptau\)), is about 145 MHz. However, considering the static  
Figure 8: Circuit diagram of the main op-amp and gain-boosting amplifier. Figure 7: Simplified circuit of the 1 st stage of the ADC. error caused by the finite op-amp gain and slewing of the op-amp, the actual unity-gain bandwidth was set to be about 250 MHz through transient simulations. The op-amp for the first and second stages consumed approximately 4 mA from the 2.8 V supply. The second, third, and fourth op-amps consumed approximately 1 mA, 0.5 mA, and 0.5 mA, respectively. A MOS transmission gate is used as a switch in the MDAC except for the switches that are connected to the common-mode voltages. They are implemented with only NMOS transistors. The switch size is determined based on the RC delay requirement. With a sampling frequency of 30 MHz, the required settling time for 12-bit resolution is about 8.3\(\upmu\)t and this should be smaller than 16.7 nsec. The resulting \(\uptau\) is about 2 nsec.