# Effects of Fractional Time Delay as a Low-Power True Time Delay Digital Beamforming Architecture
## 2 Theory of Operation  
This section aims to describe the system constraints and relevant key performance parameters that influenced the design of the VFD filter. These key metrics will tie into the use cases of a VFD beamforming solution in order to develop a relevant true time delay (TTD) beamforming architecture. As such, a lowpass FIR filter was utilized due to a deterministic group delay and future ease of integration with standard silicon processes [14; 15]. This choice was made due to significant research in literature to develop silicon-based FIR filter architectures that are size and power efficient [20; 21; 22]. Additionally, FPGA vendors including Xilinx incorporate purpose-built DSP slices as a standard feature of their integrated circuits for optimized FIR filter implementations [23]. A traditional FIR filter structure produces excellent least-squared approximation error; however, it is also computationally expensive when calculating new filter coefficients to adjust filter parameters [14; 15]. Although Farrow filter architectures enable easy adjustment for arbitrary fractional delays, this work aims to provide a method that overcomes some disadvantages of the Farrow architecture by focusing on minimum size and power. As a result, this work will focus on a look-up-table (LUT) approach to filter coefficients. In this method, a modest number of fractional delay steps achieves a fractional delay resolution which enables filter coefficient assignment through an LUT. The LUT-based approach removes the polynomial approximation calculations of the Farrow filter, drastically improving filter implementation size and cost. Additionally, an LUT VFD design can enable multi-gigahertz bandwidths without the need for up- or down-conversion. In order to verify this method, a simulation of an ideal Uniform Linear Array (ULA) was performed using MATLAB and used to analyze quantization error, sidelobe level, fractional delay, and system accuracy. As with most digitally reconstructed signals, DBF designs create quantization error which results in spatial noise that manifests as quantization sidelobes. As such, this work utilizes the Digital Video Broadcast (DVB) S2 specifications in order to determine acceptable sidelobe levels [24]. Table 20 DVB states that Direct-To-Home physical layer simulations must have a cross-polarity sidelobe limit of \(-24\) dB [24]. To ensure this DVB specification is met, a \(10\) dB margin is added, producing a target sidelobe floor of \(-34\) dB max. In order to determine a performance baseline of time delay quantization resolution, an array was simulated that steered to the minimum beam angle resolution, \(\theta_{RES}\), which is defined using Equation (1) for a linear array of N elements with the spacing of \(\frac{\lambda}{2}\)[25]  
\[\theta_{RES}\propto\sin^{-1}\frac{\phi_{LSB}}{N\pi}, \tag{1}\]  
where \(\phi_{LSB}\) is the minimum phase resolution available in the delay unit. The equivalent phase shift of a time delay is a function of the signal frequency, and is defined in Equation (2) [26]  
\[\Delta\phi=2\pi f\Delta t, \tag{2}\]  
where \(\Delta t\) is the desired time delay, \(f\) is the frequency of the signal, and \(\Delta\phi\) is the resulting phase shift. To demonstrate the need for improved time delay quantization resolution with respect to quantization sidelobes, a \(30\)-element system was simulated in two cases: (1) using only integer delays, where half of the elements have \(1\) sample delay and the other half have no delay, Figure 1a blue curve, and (2) an ideal beam pattern with double precision floating point fractional resolution, Figure 1a orange curve. Note the \(25\) dB change in the sidelobe floor, \(-5\) dB quantization sidelobe, and steering angle error with only integer delays. This initial simulated array demonstrates that to achieve the desired \(4\)GHz bandwidth and \(-34\) dB sidelobe floor, fractional sample delays must be employed.