## 1 Introduction
### Our Contributions  
The main objective of this work is to perform the polynomial multiplications using the same features in the dedicated and scalable architectures. This allows us to make a realistic comparison between the dedicated and scalable designs having the same digit lengths and reduction algorithms. Therefore, to achieve this, our contributions are as follows:  
1. **Five dedicated architectures.** We have presented a dedicated digit-parallel architecture for each variant of the NIST-standardized binary elliptic curves, i.e., 163, 233, 283, 409 and 571. The experimental results are evaluated to estimate the area and timing characteristics of the implemented multiplier circuits.
2. **A scalable polynomial multiplication architecture.** Similar to our dedicated designs, a scalable digit-parallel architecture supporting all variants of NIST-specified binary elliptic curves, i.e., 163, 233, 283, 409 and 571, is described. Our scalable architecture results in a decrease in the hardware resources when compared to the sum of resources of our dedicated architectures.
3. **Dedicated and flexible architecture(s) for NIST reduction algorithms.** For each dedicated multiplication architecture, a dedicated architecture for NIST-defined reduction routines is provided. Moreover, a unified architecture for NIST-specified reduction algorithms is presented for our scalable design.
4. **A dedicated controller.** In our scalable architecture, a finite state machine (FSM) controller is used to perform control functionalities over multiplication and reduction operations.  
All our dedicated and scalable finite field polynomial multiplication architectures are implemented in Verilog HDL using a Vivado IDE tool on the Xilinx Virtex-7 FPGA device. The outcomes of our polynomial multiplication mean that the dedicated multipliers utilize FPGA slices of 1182, 1451, 1589, 2093 and 3451 for \(m=163,233,283,409\) and 571. Moreover, the dedicated architectures can operate at a maximum frequency of 500, 476, 465, 451 and 443 MHz. Furthermore, due to the higher operational frequency, the power consumption of our dedicated architectures is rather high (3.201 W for 163 and 3.726 W for 571). For all NIST-supported binary fields, our scalable architecture (i) uses 3753 slices, (ii) acquires 305 MHz frequency, (iii) bears 0.013 \(\upmu\)s for one finite field multiplication and (iv) consumes 3.905 W power. Our scalable digit-parallel architecture is comparatively 8, 6 and 14 times more area-efficient than most recent state-of-the-art multipliers of [17; 21; 23]. Moreover, our scalable design is 403.89 times faster in terms of computational time than [23]. The implementation results and comparison to the state of the art reveal that our multiplication architectures are good alternatives in competitive cryptographic applications.  
The structure of this paper is formulated as follows. Section 2 describes the schoolbook multiplication method for polynomial multiplications. Dedicated and scalable multiplier architectures are presented in Section 3. We provide the implementation results and a comparison to the state of the art in Section 4. Finally, we present the critical findings of this work in Section 5.