## 3 Results and Discussion
In contrast to the F8T2 FETs on 200-nm-thick gate insulators treated with CPTS SAMs (Figure 4b), the short-channel F8T2 FETs on 50-nm-thick gate insulators treated with PETS SAMs still exhibit a nonlinear increase in the drain current in the low-\(V_{D}\) region. The strength of the built-in electric field produced by the dipole SAMs has been reported to be on the order of 1-10 MV cm\({}^{-1}\)[14; 15; 16; 17; 32; 33], which is comparable to the gate electric field induced by applying gate voltages of 20-200 V for the 200-nm-thick SiO\({}_{2}\) gate insulator and 5-50 V for the 50-nm-thick SiO\({}_{2}\) gate insulators. Therefore, a similar degree of improvement in charge injection is expected in devices with thinner gate insulators. These results clearly show that using gate insulators modified with dipole SAMs is effective not only for increasing the threshold voltage, but also for reducing the charge injection barriers at the source electrode/organic semiconductor contacts of short-channel OFETs. Figure 6 shows the channel-length dependence of the field-effect mobilities of FST2 FETs fabricated on PETS- and CPTS-treated SiO\({}_{2}\) gate insulators with different thicknesses (\(d_{ox}\)). In all devices, the field-effect mobility decreases with the channel length. Similar dependences have typically been observed in OFETs and explained by the increased influence of the contact resistance on the channel resistance [34]. This apparently reduces the field-effect mobility calculated with Equation (1). Therefore, the improved charge injection of FST2 FETs by the CPTS treatment of gate insulators is expected to increase the field-effect mobility of short-channel FST2 FETs. In fact, the devices with \(L\) = 5 \(\upmu\)m formed on CPTS-treated gate insulators exhibited higher mobility (3.9 \(\pm\) 0.77 \(\times\) 10\({}^{-3}\) cm\({}^{2}\) V\({}^{-1}\) s\({}^{-1}\)) than those formed on PETS-treated gate insulators (1.5 \(\pm\) 0.30 \(\times\) 10\({}^{-3}\) cm\({}^{2}\) V\({}^{-1}\) s\({}^{-1}\)), as observed in Figure 6. The influence of the CPTS treatment on the mobility of FST2 FETs is different from that of P3 HT FETs shown in Figure 2, which can result from the larger influence of contact resistances on the field-effect mobility of FST2 FETs [29]. However, the field-effect mobility of the devices with CPTS-treated gate  
Figure 4: Output characteristics of FST2 FETs with \(L\) of 5 \(\upmu\)m, 500 nm, and 30 nm on 200-nm-thick SiO\({}_{2}\) insulators treated with (**a**) PETS and (**b**) CPTS; and (**c**) their transfer characteristics. insulators shows a larger decrease as the channel length is reduced to the nanometer scale, as compared to those with PETS-treated gate insulators. Such behavior can be related to the smaller modulation of the drain current by the gate voltage observed in the F8T2 FETs with \(L=30\) nm by the CPTS treatment (Figure 4b). The results strongly suggest that the increased net source-drain electric field caused by the decreased voltage drop at the Au/F8T2 contact by the CPTS treatment reduces the effectiveness of the gate electric field in the channel, and it also leads to the apparent decrease in the field-effect mobility of OFETs with nanometer channels. Optimizing the dipole moments of SAM materials and using high-k gate dielectrics can further improve the field-effect mobility of nanochannel OFETs.