# A Model-Based Engineering Approach for Evaluating Software-Defined Radio Architecture
## 4 Architecture Definition
### Application of the Architecture Definition Process for the Development of Alternative Archeteure 1
Architecture 2 converts a real digital IF signal to complex digital baseband data in a comparable manner to Architecture 1, which is accomplished by a single FPGA. Additionally, the RF Tuner is used to _down-convert analog RF signals to analog IF frequencies,_ and the ADC is used to _digitize the IF signal and convert the analog IF signal to real digital IF samples._ However, the method of managing heat is different. Since the functional decomposition is similar to Architecture 1, only differing aspects are highlighted in Figure 11. The activity diagram in Figure 12 displays functional allocations, flows, and interfaces between SDR-MM components. Heat is first conducted to a thermal solution through the Enclosure and then dissipated to the environment via a heat sink. The Enclosure manages the first stage, while the heat sink manages the second. Additionally, the structural model (Figure 13) was generated automatically using the capability of the MBSE tool [31]. Figure 11: Functional breakdown of Architecture 2 using SysML activity decomposition map. Figure 10: Sensitivity analysis using the thermal management model: (**a**) with variation in thermal conductivity, and (**b**) with variation in enclosure thickness. The thermal analysis was performed in two steps. First, the required thermal resistance of a heat sink was calculated using Equation (8) under extreme operating conditions, 30 W power dissipation from the FPGA and a maximum SDR-MM operating temperature of 130 \({}^{\circ}\)C, and was found to be 1.5 \({}^{\circ}\)C/W. Then, the AEST was calculated at different numbers of NB outputs. As Figure 4b shows, this architecture can support up to three NB outputs due to the use of a thermal solution (a heat sink in this case) with the maximum temperature reaching 127 \({}^{\circ}\)C.  
A similar approach used for Architecture 1 cost and mass estimation was used for this architecture. This also has a single FPGA, so the electronic COTS hardware, assembly, and SW programming were estimated to cost USD 10,000, with a similar cost for the Enclosure. Additionally, an estimated USD 125 was added to the total for material and labor costs  
Figure 12: SDR-MM system behavior of Architecture 2 captured with activity diagram. Figure 13: Internal block diagram (IBD) of Architecture 2 depicting SDR-MM elements and structure. for the thermal solution and attachment to the Enclosure. The mass of this architecture is estimated to be 2.12 kg. As stated, it uses a similar enclosure but differs in extra weight due to a thermal solution. Application of the Architecture Definition Process for the Development of Alternative Archetecture 3  
Architecture 3 manages heat similarly to Architecture 2 but differs in the conversion of a real digital IF signal to complex digital baseband data. An RF tuner is utilized similar to Architectures 1 and 2 to _down-convert analog RF signals to analog IF frequencies_ and an ADC is used to _digitize the IF signal and convert the analog IF signal_; however, the conversion function is divided into two stages, each handling one WB output, as shown in Figure 9.0 The activity diagram of this architecture is similar to that of Architecture 2, and thus is not presented. However, it has different elements and structure as depicted in Figure 9.1 Based on the assumption that each WB output generates 12 W of heat, two FPGAs are required, as depicted in Figure 16 (for clarity, not all input and output flows are displayed in the figure). Figure 9.2 Functional breakdown of Architecture 3 using SysML activity decomposition map. Figure 9.3 Internal block diagram (IBD) of Architecture 3 depicting SDR-MM elements and structure. The thermal dissipation model is slightly different from architectures 1 and 2, where a maximum of 60 W can be dissipated as heat from both FPGAs. The thermal analysis was also performed in two steps.