# Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
## 6 Conclusions  
In this paper, a deep review of the state of the art of gate-level countermeasures against power analysis attacks has been carried out. The importance of developing new secure logic styles and techniques to be used in secure IoT applications where the security is a crucial issue has generated dozens of proposals claiming high protection against power analysis attacks with reduced area-delay costs. This work splits the existing gate-level solution into two large groups: those following a hiding approach (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The presented analysis considers the most relevant solutions in the literature, 35 hiding proposals, and 6 based on masking, not only by using the data provided by proposing authors, but also those included in the other references for comparison. Advantages and drawbacks of the proposals are analyzed, showing quantified data for cost, performance (delay and power), and estimated security level, when available. This work also visually depicts the performance, cost, and security level relation of the several solutions to better assist cryptodesigners in the selection of the best solution, style according to their constraints. Overall, these results suggest that RSL and DRSL solutions are the best approaches when considering masking, while BCDL, SDMLp, TSPL, HDRL, and SABL are those with best security-performance figures. It can also be concluded that hiding proposals reach higher security levels, but with more difficult design constraints, which, if not met, can result in security weaknesses. Finally, this review also suggests that the combination of masking and hiding, as in masked_SABL, can provide the most secure solution, but at the cost of more complexity.  
Figure 18: Top five countermeasures in security levels (**a**) and top five countermeasures with best trade-off between performance and security levels (**b**).  
**Author Contributions:** Conceptualization, E.T.-S., F.E.P.-O., A.J.A., C.J.J.-F. and R.C.; methodology, E.T.-S., F.E.P.-O. and R.C.; formal analysis, E.T.-S., F.E.P.-O., A.J.A., C.J.J.-F. and R.C.; investigation, E.T.-S., F.E.P.-O. and A.J.A.; resources, A.J.A., C.J.J.-F. and R.C.; data curation, E.T.-S., F.E.P.-O. and A.J.A.; writing--original draft preparation, E.T.-S., F.E.P.-O., A.J.A. and R.C.; writing--review and editing, E.T.-S., F.E.P.-O., A.J.A., C.J.-F. and R.C.; visualization, E.T.-S., F.E.P.-O., A.J.A. and R.C.; supervision, A.J.A., C.J.J.-F. and R.C.; project administration, A.J.A., C.J.J.-F. and R.C.; funding acquisition A.J.A. and C.J.J.-F. All authors have read and agreed to the published version of the manuscript.  
**Funding:** This work was funded by Grant PID2020-116664 RB-I00 funded by MCIN/AEI/10.13039/501100011033.  
**Acknowledgments:** Authors want to acknowledge to projects Programa Operativo FEDER 2014-2020 and Consejeria de Economia, Conocimiento, Empresas y Universidad de la Junta de Andalucia under Project US-1380823, to the SPIRS (Secure Platform for ICT Systems Rooted at the Silicon Manufacturing Process) Project with Grant Agreement No. 952622 under the European Union's Horizon 2020 research and innovation programme, to Erasmus+, to COST Action CRYPTACUS, to FCT (Fundacao para a Ciencia e a Tecnologia, Portugal), to the ERDF (European Regional Development Fund, EU) through the projects FCT: UIDB/50021/2020 and LISBOA-01-0145-FEDER-031901 (PTDC/CCI-COM/31901/2017, HiPrEBio) and to Disruptive Sdn seCuRE communicaITons for eurOpen defeNse, EDIDP-CSAMN-SDN-202-74-DISCRETION.  
**Conflicts of Interest:** The authors declare no conflicts of interest.