# Automatic Configurable Hardware Code Generation for Software-Defined Radios+
## 6 Hardware Model Using Finite State Machines
### FSM Composition
An observable behaviour of the closed \(M\) therefore becomes  
\[\omega_{M} =(\overline{w}\overline{v})\Big{(}(w\overline{v})(w\overline{v}) (w\overline{v})(\overline{w}\overline{v})(w\overline{v})(w\overline{v})(w \overline{v})(w\overline{v})(\overline{w}\overline{v})(\overline{w}\overline{ v})(w\overline{v})(w\overline{v})(w\overline{v}\overline{v})(\overline{w}\overline{v})( \overline{w}\overline{v})(\overline{w}\overline{v})(\overline{w}\overline{v}) \overline{w}\overline{v})\Big{)}^{\infty}\] \[=(000)\Big{(}(100)(110)(001)(010)(101)(110)(011)(001)(110)(101)(10 1)(010)(001)\Big{)}^{\infty}\]  
where \(()^{\infty}\) denotes the periodic phase of \(M\). Figure 7: The composite FSM \(M\) is constructed using FSMs \(M_{X}\), \(M_{FF}\) and \(M_{Y}\) by using the computed 1-periodic schedule in Figure 2. The vectors in lower half of each state represent the respective output signals \(w\), \(r\) and \(v\) in that state. The FSM \(M\) in Figure 7 implements the control logic that enables the sink HW block to read data from the FIFO. Since the buffer holds data for a finite period of time until the sink block is ready to read it, the controller determines the exact clock times when this should happen as specified in the consumption execution pattern (\(EP_{s,q}\)). Writing data to the FIFO block does not require the FSM control logic as the allocated buffer size of the FIFO buffer is sufficient to store the received data from source HW block. Therefore a direct asynchronous connection of \(X_{vld}\) to \(FF_{we}\) is sufficient to write the data samples into a FIFO buffer. Implementing a controller involves a sequential description of the FSM \(M\) inside the _process_ in VHDL as shown in Listing 3. ```
1 xInst_yInst_chlproc:process(rst,clk)
2 begin
3 ifrst='1'then
4...-resetprocessregisters
5 elsifclk'EVENTandclk='1'then
6...-hiddencode
7 casexInst_yInst_chl_stateis
8 whenp^0000\"=\">
9 xInst_yInst_chl_re<='0';
10 xInst_yInst_chl_state<='b^0000\";
11 ifxInst_vld_o='1'then
12 xInst_yInst_chl_re<='1';
13 xInst_yInst_chl_state<='b^0010\";
14 endif;
15 whenb^0001\"=\">
16 xInst_yInst_chl_re<='1';
17 xInst_yInst_chl_state<='b^0010\";
18 whenb^0010\"=\">
19 xInst_yInst_chl_re<='0';
20 xInst_yInst_chl_state<='b^0011\";
21 whenb^0011\"=\">
22 xInst_yInst_chl_re<='1';
23 xInst_yInst_chl_rate<='b^0100\";
24 whenb^0100\"=\">
25 xInst_yInst_chl_re<='0';
26 xInst_yInst_chl_re<='0';
27 xInst_yInst_chl_state<='b^0101\";
28 whenb^0101\"=\">
29 xInst_yInst_chl_re<='1';
30 xInst_yInst_chl_re<='0';
31 whenb^0101\"=\">
32 xInst_yInst_chl_re<='0';
33 xInst_yInst_chl_re<='0';
34 xInst_yInst_chl_rate<='0';
35 xInst_yInst_chl_rate<='0';
36 xInst_yInst_chl_rate<='0';
37 whenb^0101\"=\">
38 endprocess;
```  
**Listing 3**. The process implementation of the FSM \(M\) for hardware design in Figure 5.  
As mentioned above, a startup phase only consists of the first state (i.e., \(s_{0}\)) of \(M\) which corresponds to the state _\"0000\"_ in VHDL. A transition from the startup phase to the periodic phase takes place when the HW block \(X\) produces the first sample. This is detected by \(M\) when the value of the output signal \(X_{vld}\) is set high thereby moving the M to the second state where the periodic phase starts. The register _state_ (i.e., \(xInst\_yInst\_chl\_state\) in VHDL) keeps track of the next state of FSM \(M\).