## 4 Performance Evaluation  
This section evaluates the proposed circuits for the QCA implementation of the XOR gate and the FA circuits and compares them to those of previous works. For this evaluation, the number of cells, the area, and the delay obtained with the QCA Designer tool are considered. In Table 2, the simulation parameters used by the QCA Designer tool are listed. The simulation results of the proposed full adder (FA) circuits are shown in Table 3. As can be seen, the proposed full adder (FA) circuits in this research were compared with the best previous examples. As can be seen, the proposed collectors of this research have a better advantage than the previous designs due to the lack of any crossovers and inverter gate (NOT gate), as well as the reduced use of the majority gate number. As can be seen in Table 3, the consumption area of the proposed FA design-2 circuit is less than that of all the compared works. Regarding the consumption area of the proposed FA design-1 circuit, as shown in the table, the consumption area of this proposed design is equal to that of the design in [27]; however, the delay of our proposed design is better. Moreover, compared to the design in [23], the consumption area of our proposed design is higher, but in the design in [23], a 45-degree cell was used to implement the FA circuit. Comparing the parameter of the number of cells used, as can be seen, the number of cells in the proposed circuit design of FA design-2 is less than that of all previous works, and in the case of the number of cells in the circuit of FA design-1, it can be said that \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Value** \\ \hline Cell width & 18 nm \\ Cell height & 18 nm \\ Dot diameter & 5 nm \\ Number of samples & 12,800 \\ Convergence tolerance & 0.001 \\ Radius of effect & 65 nm \\ Relative permittivity & 12.9 \\ Clock high & \(9.8\times 10^{-22}\) J \\ Clock low & \(3.8\times 10^{-23}\) J \\ Clock amplitude factor & 2 \\ Layer separation & 11.5 nm \\ Maximum iteration per sample & 100 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Simulation parameters for the QCA Designer. \begin{table}
\begin{tabular}{l c c c c c} \hline \hline
**Design** & \begin{tabular}{c} **Area** \\ **(um2)** \\ \end{tabular} & **Cell Count** & \begin{tabular}{c} **Latency** \\ **(Clock)** \\ \end{tabular} & **Crossover Type** & \
\begin{tabular}{c} **45\({}^{\circ}\) Cells** \\ **Count** \\ \end{tabular} &
\begin{tabular}{c} **NOT Gate** \\ **Count** \\ \end{tabular} \\ \hline FA [21] & 0.043 & 59 & 1 & Coplanar (clocking based) & 0 & 2 \\ \hline FA [22] & 0.047 & 58 & 1 & Coplanar (clocking based) & 0 & 4 \\ \hline FA [23] & 0.038 & 52 & 0.75 & Not required & 1 & 6 \\ \hline FA [24] & 0.057 & 60 & 1 & Not required & 0 & 1 \\ \hline FA [25] & 0.047 & 56 & 1 & Coplanar (clocking based) & 0 & 2 \\ \hline FA [26] & 0.076 & 61 & 0.5 & Coplanar (rotated cells) & 8 & 4 \\ \hline FA [27] & 0.043 & 44 & 1.5 & Not required & 0 & 6 \\ \hline Proposed FA design-1 & 0.043 & 45 & 0.75 & Not required & 0 & 0 \\ \hline Proposed FA design-2 & 0.037 & 43 & 0.75 & Not required & 0 & 0 (or \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Relative evaluation of the proposed full adder (FA) circuits in comparison with the state of the art. compared to the design in [27], one more cell is used for implementation; however, our proposed FA design-1 circuit is designed using three clock phase (0.75 clock cycle). Regarding the comparison of the proposed designs' delay compared to the previous works, as can be seen, the delay of both of our proposed circuits is the same, and the delay of these two designs is less (superior) than that of all previous designs, except those in [23; 26]. The delay of our proposed circuit designs is equal to that of the design in [22], but, instead, the number of its cells is more than that of our proposed designs, and also, in this design [23], 45-degree cells have been used to implement the circuit.