# A 60 GHz CMOS I/Q Receiver for High-Speed Wireless Communication System
## 3 Measurement Results  
The chip microphotograph of the 60 GHz CMOS LNA is shown in Figure 8. The measured S-parameter results of the 3-stage LNA are shown in Figure 9. The gain of 13.5 dB is achieved in the frequency from 57 to 62 GHz. The input return loss is <10 dB, and the output return loss is <7 dB from 57 to 62 GHz. The 60 GHz LNA consumes a current of 25 mA with a supply of 0.9 V. The chip size of the LNA including the pads is 0.45 \(\times\) 0.49 mm\({}^{2}\). The proposed 60 GHz I/Q receiver uses a 40 nm CMOS technology. Figure 10 shows the microphotograph of the proposed 60 GHz I/Q receiver. The chip size is 2.02 \(\times\) 1.45 mm\({}^{2}\), including the pads. The measurements are performed on a high-frequency probe station with DC pads wire bonded to a PCB. The measurement setup for the 60 GHz CMOS I/Q receiver using a spectrum analyzer is shown in Figure 11. The millimeter-wave source module is used to increase the frequency of the signal generator up to V-band. The LO signal generated from the vector network analyzer has also a limit on the frequency and power, thus the frequency quadrupler is used to extend the frequency up to the V-band and increase the output power to ~16 dBm. The IF outputs \(\rm{I_{p}}\) is observed in the spectrum analyzer while other IF ports are terminated at 50 \(\rm{\Omega}\). The I2C interface is used to control the 60 GHz I/Q receiver chip. Figure 7: (a) Block diagram of 60 GHz baseband amplifier, (b) schematic of gain stage, (c) schematic of buffer stage of baseband amplifier. Figure 8: Chip microphotograph of 60 GHz CMOS LNA test pattern. Figure 9: Measured S-parameters of the 60 GHz LNA test pattern. Figure 12a plots the three different conversion gain states with the LO power varied from \(-\)10 to 10 dBm. The 8-bit gain control is implemented in the receiver, in which 2 bits from MSB are for LNA gain control, and the next 2 bits are for the S2D gain control, and the last 4 bits are for the baseband amplifier. The gain code of 1111_1111 is the highest gain state, and the gain code of 0000_0001 is the lowest gain state. As shown in Figure 12a, the conversion gain is saturated over the LO power of \(-\)2 dBm. The measured conversion gain is  
1111_1111), ~30 dB (Gain code: 1010_0100), and ~3 dB (Gain code: 0000_0001) at RF power of ~70 dBm. The conversion gain across frequency is measured by sweeping RF and LO together, keeping the IF fixed and superimposed as shown in Figure 13a. The conversion gain of  
Figure 12: Measured (**a**) conversion gain versus LO power, (**b**) conversion gain versus RF power of 60 GHz CMOS I/Q receiver. different IF ports versus RF Frequency is plotted. The RF frequency is varied from 57 to 61 GHz, maintaining the constant IF frequency of 10 MHz. The RF and the LO power of \(-\)61 dBm and 5 dBm respectively are applied. The peak gain is \(\sim\)56 dB at 59 GHz. Figure 13b shows the conversion gain of the I/Q Rx receiver against the IF frequency at the LO frequency of 60 GHz. The measured conversion gains are \(\sim\)50 dB (Gain code: 1111_1111), \(\sim\)32 dB (Gain code: 1010_0100), and \(\sim\)3 dB (Gain code: 0000_0001). The 3 dB baseband bandwidth is around 300 MHz at the highest gain state (Gain code: 1111_1111). The gain control range achieved is around 48 dB. Figure 13: Measured (**a**) conversion gain versus RF frequencies at different IF ports (Gain code: 1111_1111), (**b**) conversion gain versus IF frequency. The I/Q waveform measurement setup of the 60 GHz CMOS receiver is shown in Figure 14. The RF signal of 60 GHz is applied using the V-band source module to extend the frequency and power range. The LO signal of 60.01 GHz is applied from VNA using a frequency quadrupler to the LO port of the receiver. The DC voltage supply of 0.9 V is applied. The chip consumes a total current of 191 mA. The four IF outputs are connected to the four channels of the oscilloscope, and the output waveforms are observed.