# A Fast, Decentralized, Self-Aligned Carrier Method for Multicellular Converters +
## 5 Experimental Result
### Experiment with DSA-PSC Method  
Figure 30 shows the connection diagrams for DSA-PSC method, each cell is controlled by a DSP controller and communicates with other cells via the functional pins described in Table 8. Parameters of four-phase converter (Figure 10a) with algorithm DSA-PSC are shown in Table 9. \begin{table}
\begin{tabular}{c c} \hline \hline
**Component** & **Information** \\ \hline \multirow{3}{*}{Controller board} & C2000 Delfino MCUs F28379D LaunchPad \\  & Development Kit, Texas Instruments, Dallas, \\  & TX, USA \\ \hline Power circuit & IGBT GW40N120 KD \\ \hline \multirow{3}{*}{Driver circuit} & Hybrid integrated IGBT driver MORNSUN \\  & QP12W088-37, MORNSUn Guangzhou \\  & Science \& Technology Co., Ltd. \\ \hline \multirow{3}{*}{Current sensor} & Current Transducer LTS 15-NP IPN = 15 At, \\  & LEM \\ \cline{1-1}  & Tektronix A622 AC/DC current probe \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Information on experimental components. Figure 29: Experimental prototype for the test of the DSA-PSC and the DSA-LSC methods. Figure 31 depicts the arrangement of the carrier phases and the IGBT control signals when all cells are active. Figure 31a shows that four triangular carriers are arranged with an exact 90\({}^{\circ}\) phase-shift, resulting in four PWM control signals (to the four high-side cell switches) with same duty-cycle and same inter-carrier phase-shift, as shown in Figure 31b. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameter** & **Pin on DSP** & **Function** \\ \hline count\_in & GPIO 97, 94, 65 & Get information of cell index from the previous cell \\ \hline count\_out & GPIO 130, 63, 64 & Send information of cell index to the next cell \\ \hline number\_in & GPIO 52, 41, 40 & Get information of total number of cell in the system \\ \hline number\_out & GPIO 26, 27, 25 & Send information of total number of cell in the system \\ \hline EN & GPIO 66 & Enable to Activate/Deadivate the cell \\ \hline clk\_in & GPIO 14 & Receive synchronous clock pulse \\ \hline clk\_out & GPIO 04 & Send information of synchronous clock pulse to the next cell \\ \hline tea\_base & ADCA15 & Get information of carrier phase angle from the previous cell \\ \hline send\_teta & DACB & Send information of carrier phase angle to the next cell \\ \hline Vrf\_in & ADCA14 & Get information of modulation index of master cell \\ \hline Vrf\_out & DACA & Send information of modulation index to other cell \\ \hline B signal & GPIO 0 & IGBT control signal B (high-side switch) \\ \hline H signal & GPIO 1 & IGBT control signal H (low-side switch) \\ \hline \hline \end{tabular}
\end{table} 
Table 8: Function of control pins of digital signal processor (DSP) for algorithm DSA-PSC. Figure 30: System diagram for the experimentation of the DSA-PSC method. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameter** & **Symbol** & **Unit** & **Value** \\ \hline Output inductor & L\({}_{1}\)... L\({}_{4}\), & H & 0.06 \\  & R\({}_{1}\)... R\({}_{4}\), & \(\Omega\) & 2.5 \\ \hline Load resistor & R & \(\Omega\) & 20 \\ \hline Voltage source & E & V & 100 \\ \hline Switching frequency & f\({}_{\rm sw}\) & Hz & 10,000 \\ \hline Sampling time & T\({}_{\rm s}\) & s & \(5\times 10^{-5}\) \\ \hline Duty cycle & D & & 0.8 \\ \hline \hline \end{tabular}
\end{table} 
Table 9: Parameters of four-phase converter with algorithm DSA-PSC. When cell 3 is deactivated, the system has three remaining cells, and their carriers are rearranged at an exact 120\({}^{\circ}\) phase-shift, as shown in Figure 32a, and the triggering pulses are also rearranged to three pulses with 120\({}^{\circ}\) inter-carrier phase-shift, as shown in Figure 32b. When both cells 3 and 4 are deactivated, the system has two remaining cells, and their carriers are rearranged 180\({}^{\circ}\) apart, as shown in Figure 33a, and the triggering pulses are also changed accordingly to two pulses with 180\({}^{\circ}\) inter-carrier phase-shift (Figure 33b).