## 3 System Design
### Acquisition in High-Sensitivity Mode
#### 3.4.3 Implementation
Once the first 100 ms worth of samples has been captured, concurrently with the remaining part of the sample capture process, the CAF computation module initiates the calculation of the successive CAFs. By overlapping the CAF computation and the sample capture, the acquisition latency is reduced. The FPGA writes the computed CAFs to the PL memory. Concurrently, the embedded processor reads the computed CAFs from the PL memory component and executes the GPDIT iterations. The embedded processor executes the GPDIT iterations simultaneously to the FPGA calculating the CAFs, to further reduce the acquisition latency. In accordance with the architecture presented in [21], the high-sensitivity acquisition hardware accelerator exposes memory-mapped registers to the embedded processor for operation control. Additionally, it is equipped to issue interrupt requests to the embedded processor, facilitating the efficient synchronization of operations. Figure 7 presents a timing diagram for the acquisition process, illustrating the concurrent computation of successive CAFs (\(R_{k}(\tau,f_{d})\)) and GPDIT iterations (\(Z_{\text{GPDIT}_{k}}(\tau,f_{d})\)) within the FPGA and the embedded processor, respectively. In the figure, time progresses from left to right. The FPGA and the embedded processor synchronize their operations by means of interrupt requests (marked as \"Int.\" in Figure 7), going from the FPGA to the PS. This process is explained below in more detail. The embedded processor commences the acquisition process, as indicated by 'Initiate Acquisition Process' in Figure 7, which includes directing the FPGA to capture samples, a step referred to as 'Initiate Sample Capture' in the same figure. This involves the FPGA collecting 700 ms worth of samples in 100 ms increments. After capturing the first segment, the FPGA generates an interrupt request to the embedded processor. The processor, in response, instructs the FPGA to start the computation of the first CAF at the initial tested Doppler frequency (\(R_{k}(\tau,f_{min})\)). This instruction from the processor to the FPGA is denoted as 'Initiate CAF Computation' in Figure 7. Following this, the FPGA and embedded processor work in sequence to compute the CAFs and GPDIT iterations for each Doppler frequency. For each frequency, the FPGA performs circular cross-correlation between the received signal and the local replica. After completing this computation, it issues an interrupt request to the embedded processor. Upon receiving the interrupt, the processor initiates the corresponding GPDIT iteration for that Doppler frequency. Simultaneously, it commands the FPGA to calculate the CAF for the next frequency. This command is not shown in Figure 7 to maintain clarity. This procedure is systematically repeated across all Doppler frequencies, progressing from \(f_{d}=f_{min}\) to \(f_{d}=f_{max}\) in increments defined by \(f_{step}\). Through this orchestrated approach, the FPGA consistently stays ahead by computing the CAF for the next frequency while the embedded processor concurrently handles the GPDIT iteration for the current frequency. Specifically, the FPGA computes the CAF for  
Figure 6: High-sensitivity acquisition FPGA hardware accelerator block diagram. the (\(n+1\))-th Doppler frequency (\(R_{k}(\tau,f_{min}+n\cdot f_{step})\)), while the embedded processor executes the GPDIT iteration for the \(n\)-th frequency (\(Z_{\text{GPDITI}}(\tau,f_{min}+(n-1)\cdot f_{step})\)). With this approach, upon completion of the computation of the \(n_{nc}\)-th CAF, the FPGA initiates the computation of the subsequent (\(n_{nc}\)+1)-th CAF in parallel with the embedded processor finishing the execution of the \(n_{nc}\)-th GPDIT iteration. Importantly, this parallel computation is speculative, meaning the results of the (\(n_{nc}\)+1)-th CAF might not be utilized if the CFAR detector signals a positive detection at the conclusion of the \(n_{nc}\)-th GPDIT iteration. Adopting this strategy minimizes acquisition latency through the simultaneous computation of CAF and GPDIT iterations.