# A Tile-Based Multi-Core Hardware Architecture for Lossless Image Compression and Decompression
## 3 High-Efficiency Parallel Processing Architecture  
The system is based on a parallel processing architecture. It is designed to accelerate image compression and decompression. As shown in Figure 5, a dual-side architecture is used, consisting of a processing system (PS) side and a programmable logic (PL) side. Data in the PS and PL sides are transmitted directly through 128-bit, 256-bit, and 512-bit data channels. The burst lengths for each transmission are 4, 8, and 16, respectively. Each burst transfers 2048 bits of data, equivalent to 256 subpixels, which corresponds to one subpixel channel of a \(16\times 16\) tile. To achieve maximum system performance, each burst transmission must transfer at least one complete subpixel channel of a tile. Therefore, tile sizes of \(4\times 4\), \(8\times 8\), and \(16\times 16\) were selected for use in the system. Figure 5: Architecture diagram. In compression mode, the initial operations are executed on the PS side. Image data are read from memory. During reading, addresses provided by the ARM core are not continuous. Instead, the starting address of each tile row is given, and the burst length is set to match the length of the tile row. This approach allows tiles to be segmented during reading, making tile-based compression easier. The tile data are directly stored in DDR3 SDRAM. Afterward, the tiles are transferred through DMA to the compression module on the PL side. Each multi-core compression module on the PL side has eight compression cores. All cores work in parallel and can process up to eight tiles simultaneously. Since each tile is compressed independently, no parameter dependencies exist. This enables the eight cores to operate fully in sync. After compression, the length of the compressed data from each core is recorded in an AXI Stream FIFO. A signal is then sent to the PS. Based on the recorded length information, the PS transfers the compressed data back to DDR3 memory. When all the data have been compressed, the ARM core sends a command to store the data into external memory. Necessary information is added to form a complete compressed file. For decompression, a similar but reversed process is followed. The compressed file is first read by the PS. Based on the file's internal information, the PS identifies the position of each tile. The tile data are then transferred to DDR3 SDRAM. DMA is used to move the data into the multi-core decompression module. After finding the header of each tile, the compressed data are assigned to the eight decompression cores. After decompression, the data are transferred back to DDR memory. The PS software reconstructs and stores the final image. The completed image is saved in external memory. The multi-core compression module is composed of multiple compression cores, a tile scheduling module, and a compressed tile hub module. The tile scheduling component is utilized to efficiently assign tiles to individual compression cores based on the bit width determined by the transmission standard and the specific tile size. Once fetched from the FIFO queue, a tile is directed to the active cores, where the compression algorithm is executed. The cores operate collaboratively to compress the tiles, with length metadata attached before the data are passed to the merging module, which amalgamates the outputs from all cores, preparing the data for subsequent transmission or storage. The efficacy of this module is further enhanced by the implementation of four-stage pipeline technology within the compression cores. The multi-core decompression module consists of several decompression cores, each working in tandem with a compressed tile scheduling module, a tile hub module, and a set of data FIFOs. The data scheduling module plays a pivotal role within this architecture, orchestrating the flow of data through the decompression process. Data are retrieved from the FIFO, matched to the transmission bit width, and allocated to the active decompression cores.