## 5 Findings and Analysis
### Complexity Examination  
In analyzing the presented hybrid systolic design depicted in Figure 3, it becomes evident that the structure comprises multiple processing elements (PEs), amounting to \(r\) in number. The implemented systolic array is comprised of \(2r+6\) tri-state buffers, \(r\) AND gates, \(2r\) XOR gates, no MUXes, and \(3r\) latches. A thorough analysis of the computational logic within PEs allows for the calculation of the critical path delay (CPD) of the proposed multiplier. The CPD represents the cumulative propagation delays through two tri-state buffers (\(2\lambda_{tri}\)), a two-input AND gate (\(\lambda_{A}\)), and a two-input XOR gate (\(\lambda_{X}\)). These components are essential in shaping the overall performance and efficiency of the architecture, as they directly influence the speed at which data can be processed and the system's responsiveness in real-time applications. In the analysis of the multiplier setup, it is imperative to underscore that the proposed design achieves its ultimate outcome within \(3r\) clock intervals. This duration signifies that the entire calculation sequence--starting with the beginning of the multiplication process and finishing with the output being delivered--transpires within these 3\(r\) clock intervals. Understanding this timeframe is vital for assessing the multiplier's efficiency and speed, thus enabling a thorough appraisal of its effectiveness in real-world applications. Table 2 presents a detailed comparison of the newly introduced hybrid systolic multiplier with several established systolic and semi-systolic multiplier designs [19; 20; 43; 44; 50]. This comparison is structured around three key criteria. First, the analysis evaluates the utilization of essential components, such as gates, multiplexers, and latches. These components are critical for the functionality of each multiplier design. Second, the study examines the latency associated with each multiplier. Latency refers to the time taken for the multiplier to produce its output after the input is provided. This metric is vital for understanding the efficiency of the design in practical applications. Finally, the critical path delay (CPD) is assessed. CPD is a significant factor that influences the overall performance of the multiplier, as it determines the maximum time required for the signal to propagate through the circuit. By analyzing these aspects, the study aims to demonstrate the benefits of the hybrid approach and identify potential improvements in the efficiency and effectiveness of multipliers in real-world scenarios. The results of the analysis reveal a significant disparity in area utilization between the newly introduced multiplier architecture and the previously referenced architectures. Multiplier architectures discussed in existing research typically exhibit a quadratic space complexity. This means that as the field size \(r\) increases, the number of components required expands quadratically. Specifically, if the field size doubles, the number of components may increase by a factor of four, leading to substantial increases in resource demands. This rapid growth in resource requirements poses challenges for various applications, particularly in environments where space and power are at a premium. In contrast, the hybrid systolic multiplier offers a more favorable linear space complexity. This linear relationship means that the increase in resource consumption is directly proportional to the increase in the field size. For instance, if the field size doubles, the number of components required also approximately doubles. This characteristic enables a significant reduction in resource consumption for the proposed design compared to existing designs with quadratic complexity, making the hybrid systolic architecture a more efficient alternative. This improved spatial utilization is particularly valuable for Internet IoT solutions aimed at individuals with disabilities, who often face considerable constraints related to limited resource access and physical space.