# Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm CMOS FD-SOI and 40 nm GaN HEMT
## 2 Design Methodology  
Different design techniques and methodologies will be explored using these two technologies to achieve a very broad BW with good PAE performance. For example, a high-order input-matching network (3 rd-order) has been used for the GaN technology, which improves the BW by adding additional zeros and poles to the PA's transfer function. In the CMOS PA, RC feedback is utilized, which improves the BW with a small sacrifice to the maximum gain with feedback and by also adding an additional pole to the transfer function. Load-pull simulations are performed in both technologies to help design these broadband PAs. For broadband operation, it is desirable to have the device's optimum load for PAE near 50 \(\Omega\) so that minimal impedance transformation is needed, reducing the number of lossy components to realize the narrow-band impedance transformation. In addition, it would be great to have a very small reactance at the device's optimum load to minimize frequency dependence in the impedance to achieve good broadband performance. Using load-pull simulations on several GaN devices of different sizes with measurement-based models performed in the Cadence AWR (Applied Wave Research) design environment, a 4 \(\times\) 37.5 \(\upmu\)m device is chosen for a good trade-off of high PAE and gain. The fundamental load-pull simulations for maximum PAE circles for the 4 \(\times\) 37.5 \(\upmu\)m device are shown in Figure 2 for \(V_{DD}\) = 4/6/12 V at 24 GHz and 37 GHz, respectively. Not only is the PAE lower for a 12 V supply compared to a 4/6 V supply, but the optimum load also has higher reactance, and thus may make it more difficult to achieve broadband results with 12 V operation. First, a single-ended PA is designed with input and output matching networks, RF choke, and 1 pF bypass capacitors all on-chip. Using the load-pull simulations, the output matching is designed using only 3 matching components (including  
Figure 1: Simulated \(f_{T}\) and \(f_{MAX}\) of the 40 nm GaN HEMT (4 \(\times\) 37.5 \(\upmu\)m) and 22 nm CMOS FD-SOI (2 \(\times\) 20 \(\upmu\)m) PA power transistors with parasitic elements extracted to the top metal layer and plotted vs. (**a**) bias current (mA); and (**b**) current density (mA/\(\upmu\)m). the RF choke) to minimize the loss for high PAE. To achieve good broadband \(S_{11}\) and increase the usable gain bandwidth, a 3 rd-order input matching network is utilized (see Figure 4). The PA is biased at class A/B mode for a good trade-off of linearity and PAE. After this single-ended PA was designed and tested, a differential version was designed where neutralization capacitors are added to increase the gain, as will be discussed later. In the CMOS FD-SOI technology, PAE and \(P_{OUT}\) load-pull simulations are performed in Cadence Spectre. First, these simulations are performed on a single-ended cascode device pair with parasitic elements again extracted up to the top metal layer as shown in the schematic in Figure 3a. These simulations are performed at around \(OP_{1 dB}\) and indicate  
Figure 2: Load-pull simulations of the \(4\times 37.5\)\(\upmu\) GaN device at (**a**) 24 GHz and (**b**) 37 GHz for \(V_{DD}\) = 12 V; (**c**) 24 GHz; and (**d**) 37 GHz for \(V_{DD}\) = 6 V; (**e**) 24 GHz and (**f**) 37 GHz for \(V_{DD}\) = 4 V all at around \(OP_{1 dB}\). that at 24/37 GHz, the cascode device can achieve maximum PAE of 35.0%/33.0% and \(P_{OUT,MAX}\) of 11.9/11.8 dBm, respectively. Load-pulls simulations are then also performed on a differential cascode device pair with small neutralization capacitors (see Figure 3d), and they achieve maximum PAE and \(P_{OUT,MAX}\) values of 33.5%/32.5% and 14.8/14.5 dBm at 24/37 GHz, respectively (still at around \(OP_{1 dB}\)). The optimal load impedance of maximum PAE and \(P_{OUT,MAX}\) can occur close to each other on the Smith Chart as indicated by the load-pull simulations, and thus, these devices can almost be simultaneously optimized for both PAE and output power.