# A Power Processing Circuit for Indoor Wi-Fi Energy Harvesting for Ultra-Low Power Wireless Sensors
## 6 The Proposed Power Processing Circuit Performance  
The matching circuit performance of the proposed power processing circuit is demonstrated by measuring the return loss at the input terminal of the circuit. A vector network analyser measured the return loss, and the result is depicted in Figure 11. As reported in the figure, the lowest return loss is approximate at \(-17.5\) dB, which is at 2.4 GHz. At 2.45 GHz, the return loss is at \(-16.5\) db. The proposed power processing circuit is fabricated, and the component values of the proposed power processing circuit are listed in Table 3.  
Figure 11: The actual matching circuit return loss (\(S_{11}\)). Figure 10: The simulation result at the three most important testing points for the proposed power processing circuit when \(V_{AC}\) is (**a**) 2 mVp-p, (**b**) 6 mVp-p, (**c**) 20 mVp-p and (**d**) 35 mVp-p. The developed power processing circuit is tested with a varying input voltage and power which is injected by an RF signal generator. This step is taken to demonstrate that the proposed power processing circuit can rectify instantaneous input signal, accordingly. For this experiment, a load resistor and a capacitor are connected to the output terminal of the circuit, and the value is 10 k\(\Omega\) and 0.1 uF, respectively. The reading obtained from the experiment is reported in Figure 12, it is found that the circuit output voltage level reached 1.8 V and 35 mV, for an input of 620 mVp and \(-\)20 dBm, respectively. The capacitance of \(C_{STORE}\) is changed to 0.22 F to investigate the time required for the voltage across the capacitor to reach a constant level. The capacitance value is the lowest supercapacitor commercially available in the market. The supercapacitor is from Copper-Bussmann, and the equivalent series resistance (ESR) of the capacitor is less than 2 \(\Omega\). A signal generator supplies five different input powers at 2.45 GHz, and the voltage across \(C_{STORE}\) is recorded using the data logger. The measurement results are illustrated in Figure 13. From the measured value, it was noticed that the charging time could be divided into four separate phases as highlighted in Figure 13a. The period for each step is approximately \(\omega_{1}\) = 0 s \(<\) t \(<\) 3600 s, \(\omega_{2}\) = 3600 s \(<\) t \(<\) 5400 s, \(\omega_{3}\) = 5400 s \(<\) t \(<\) 7200 s and \(\omega_{4}\) = 7200 s \(<\) t \(<\) 10800 s. The voltage across \(C_{STORE}\) increased linearly during \(\omega_{1}\) and steadily increased for \(\omega_{2}\) and \(\omega_{3}\). For the period of \(\omega_{4}\) the voltage across the capacitor is constant. The current flow through the capacitor can be calculated by differentiating the measured voltage with respect to time (\(d_{\circ}/d_{1}\)), then multiplying by the capacitance of \(C_{STORE}\), and the result is shown in Figure 13b. The current flow through the capacitor is the highest during \(\omega_{1}\) for all levels of input power, and at the lowest towards \(\omega_{4}\) as the capacitor starts to behave in a saturation condition. By multiplying the voltage and current, \begin{table}
\begin{tabular}{l l l l l l} \hline
**Parameter** & **Value** & **Unit** & **Parameter** & **Value** & **Unit** \\ \hline \(L_{1}\) & 3.0 & nH & \(R_{1},R_{2}\) & 510 & k\(\Omega\) \\ \(L_{2}\) and \(L_{3}\) & 32.0 & nH & \(R_{3}\) & 1 & k\(\Omega\) \\ \(C_{1}\) & 1.0 & pF & R\({}_{\mathrm{L}}\) & 10 & k\(\Omega\) \\ \(C_{2}\) & 10 & uF & \(L_{4}\)-\(L_{6}\) & 420 & uH \\ \(C_{5}\)-\(C_{4}\) & 1.0 & uF & \(D_{1}\)-\(D_{4}\) & SMS7621 & - \\ \(C_{5}\)-\(C_{6}\) & 4.7 & nF & M\({}_{3}\)-\(D_{4}\) & ALD210800A & - \\ \(C_{7}\) & 0.47 & uF & PMU & EH5205 & - \\ \hline \end{tabular}
\end{table} 
Table 3: The proposed circuit components value. Figure 12: The measured output voltage versus peak input voltage (**a**), and input power (**b**) when \(R_{PMU}\) =10 k\(\Omega\) and \(C_{STORE}\) = 0.1 uF. the amount of power absorbed by \(C_{STORE}\) is depicted in Figure 13c.