## 1 Introduction  
Nowadays, the frequency band of fourth Generation wireless systems (4G) is almost saturated. As shown in Figure 1, the fifth Generation of wireless systems (5G) offers a high data-rate communication, and the operating frequency has been extended to the mm-Wave band, due to its large bandwidth. Therefore, the design of mm-Wave integrated circuits has become popular in the last decade. Phase-Locked Loops (PLL) and frequency multipliers are widely used for the generation of a high-frequency clock from a low-frequency clock, to ensure the synchronized operation of different  
Figure 1: Frequency spectrum of the 5G. blocks [1]. Alternatively, in a Radio Frequency (RF) and mm-Wave transceiver [2], PLL provides the local oscillator signals (LO) for the up- and down-conversion of the RF signals. Figure 2 shows the well-known top block diagram of an analog PLL. As an essential building block of an analog PLL inside the transceiver architecture, a wide tuning range and low phase noise Voltage Controlled Oscillator (VCO), operating at a higher frequency, is highly demanded. The phase noise of the VCO results in leakage of power into adjacent channels, as well as interference, and also enhances the bit error rate in digital communication. On the other hand, a low phase noise design cannot satisfy the error vector magnitude (EVM). Therefore, a wide tuning range with low phase noise is a trending demand of such applications. Recently, to achieve a wide range and low phase noise at the same time, several techniques, such as capacitive and inductive tunings, have been reported. By using a combination of the switched capacitor bank for coarse tuning and the Metal Oxide Semiconductor (MOS) varactor for fine-tuning, a wide tuning range can be obtained [3,4]. However, in the mm-Wave frequency band, due to the capacitor and varactor, the quality factor of the Inductor and Capacitor (LC) tank decreases. Another work [5] employs the inductive tuning technique and uses switches at different locations in the secondary coil to increase the number of sub-bands and the resulting wide tuning range. A large number of switches on the coil path introduces more parasitic capacitance, and the parasitic capacitance of switches highly affects the overall performance. The work proposed in [6] utilizes a topology based on triple-coupled inductors, which are used to couple three pairs of varactors and compensates for the tuning nonlinearities of the LC tank, while achieving a tuning range of 15.8%, with the center frequency of 20.85 GHz. Simulation and measurement results show the phase noise performance has not been improved sufficiently. In contrast, the design of a wide-range and low phase noise VCO would be difficult, considering the trade-offs between the tuning range, phase noise and power consumption. On the other hand, the design process at higher frequencies becomes more complicated when the layout parasitic effects come into play. In this brief, a wide tuning range and low phase noise VCO is proposed. Since in a CMOS VCO the phase noise is limited by the oscillation amplitude and device noise, the transconductance linearization technique is employed to provide sufficient signal swing and low device noise. Coarse and middle switched capacitor arrays are provided to cover the whole frequency range, of 14 GHz to 18 GHz, while the varactor offers continuous fine-tuning. The switch sizes inside the switch capacitor array are optimized to lower the introduced flicker and channel noise, while keeping the frequency range wide. A new layout technique is employed to shrink the VCO output routing and resistance, which prevents the reduction of the quality factor of the Inductor and Capacitor (LC) tank. Figure 2: Top block diagram of an analog Phase-Locked Loops (PLL). The rest of this paper is organized as follows: Section 2 describes VCO implementation, with the transconductance linearization technique and capacitive tuning method. Post-layout simulation results are presented in Section 3.