# Harnessing FPGA Technology for Energy-Efficient Wearable Medical Devices
###### Abstract
The need to accommodate rapidly changing medical requirements and procedures, evolving AI techniques, adaptability for individual patient needs, and competition to reach the market earlier make the choice of hard-wired ASICs for WMDs riskier [12]. Similarly, low-power MCUs, while offering lower energy consumption and the flexibility of reprogrammability to adapt to evolving changes, lack the ability to provide a high level of parallelism and computational power. Typically, MCUs have fixed architectures optimized for general-purpose tasks, with predefined peripherals and processing capabilities. This can limit their performance in WMD applications, which require increased parallelism and computational power due to the incorporation of AI and multimodal sensors and the need to perform all computations at the edge for privacy and security reasons. On the other hand, GPPs and GPUs provide extremely good computational power, but their energy consumption is not well suited for small battery-powered devices. While both MCUs and ASICs offer advantages in power efficiency and cost-effectiveness, making them suitable for most power-sensitive applications, there exist some applications which require higher computational power, parallelism, flexibility in reconfigurability, scalability, adaptability, and a faster time to market all at once. Therefore, researchers are also exploring other energy-efficient, reconfigurable solutions to adapt to the rapid evolution of requirements and speed up the time to market. FPGAs, despite being a costly choice for mass production, offer a feasible solution by providing the necessary computational power and parallelism, along with the flexibility of reconfigurability to adapt to changing requirements. They are more flexible than ASICs, more powerful than DSPs and MCUs, and more energy-efficient than GPUs and GPPs [13]. Some FPGAs even allow real-time reconfiguration to avoid downtime. However, FPGAs are generally not as power-efficient as low-power MCUs and ASICs. Therefore, power optimization strategies must be employed to make FPGA power consumption acceptable for those applications where MCUs and ASICs are not feasible due to the required computational power or reconfigurability and time to market. By optimizing power usage, FPGAs can become a viable option for these demanding applications, balancing the need for high performance and flexibility with acceptable power consumption. Numerous recent and ongoing research efforts have focused on addressing the power consumption of WMDs using FPGAs. This paper reviews the power optimization strategies employed by different researchers in FPGA-based WMDs. The outcomes of this work are listed below:  
* Identifying power optimization strategies used in FPGA-based WMDs for physiological monitoring;
* Categorizing these strategies to provide a holistic view of system design for energy efficiency, along with their benefits and constraints;
* Highlighting the shortcomings while proposing future research directions and guidelines. Section 2 introduces continuous health monitoring using WMDs along with the exploration of low-power FPGA families from different manufacturers. Section 3 outlines the motivation behind this review by exploring existing review papers and highlighting their strengths and shortcomings in comparison to our work. Section 4 lists the objectives of this review, along with the database search methodologies and the screening of articles against the inclusion and exclusion criteria. In Section 5, the power optimization strategies found in the selected literature are analyzed and categorized along with their benefits and limitations. Section 6 presents critical analyses of the practical implications of these strategies, shortcomings, future research, and guidelines for WMDs developers. Finally, we conclude our work by summarizing the key findings and suggestions for future research in Section 7.