# Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies
## 2 Integrated Inductive Components: Loss Phenomena and Main Design Guidelines
The interleaved configuration guarantees better winding \(Q\)-factors at the cost of a lower magnetic coupling factor, \(k\), compared to the stacked configuration. However, interleaved transformers easily implement high transformer ratios, \(N\), and achieve better _SRFs_. The interstacked configuration exploits mixed interleaved/stacked coils and guarantees higher \(k\) with respect to the stacked configuration, providing full winding symmetry [6,14,15]. Finally, when the operative frequency is excessively high with respect to the adopted BEOL, stacked folded configurations can be exploited [16]. Table 2 summarizes the pros and cons of the integrated transformer structures shown in Figure 2.  
A final comment must be made about the BEOL of integration technologies. Bipolar and BiCMOS technologies benefit from optimized BEOL for RF/mm-wave applications with at least two thick copper top metals (i.e., thicker than 2 \(\upmu\)m), along with thick intermetal oxide layers to reduce losses and capacitive parasitics. On the other hand, CMOS technologies usually adopt a standard BEOL with thin metals and intermetal oxides, leading to lower quality passive devices with limited SRF. Figure 3 shows a comparison between an optimized BiCMOS process [17] and a 28-nm CMOS technology with standard BEOL [2]. Although at mm-wave frequencies, an optimized BEOL technology produces small performance enhancements, due to increased fringing effects [18], it could have a significant \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Inductor** & \multicolumn{2}{c}{**Peak Q-Factor**} & \multicolumn{2}{c}{**Low-Frequency**} & \multicolumn{1}{c}{**Self-Resonance**} \\
**Parameters** & & \(\left(Q_{\text{MAX}}\right)\) & **Inductance** & **Frequency** \\  & & \(\left(L_{\text{DC}}\right)\) & **(SRF)** \\ \hline Number of turns, \(n\) & \(\blacktriangle\) & \(\blacktriangledown\) & \(\blacktriangle\) & \(\blacktriangledown\) \\ Metal width, \(w\) & \(\blacktriangle\) & \(\blacktriangle\) & \(\blacktriangledown\) & \(\blacktriangledown\) \\ Metal spacing, \(s\) & \(\blacktriangle\) & \(\blacktriangledown\) & \(\blacktriangledown\) & \(\blacktriangledown\) \\ Fill ratio, \(\rho\) & \(\blacktriangle\) & \(\blacktriangle\blacktriangledown\) & \(\blacktriangle\blacktriangledown\) & \(\blacktriangledown\) \\ Metal thickness, \(t\) & \(\blacktriangle\) & \(\blacktriangle\) & \(\blacktriangledown\) & \(\blacktriangle\) \\ Oxide thickness \(t_{\text{ox}}\) & \(\blacktriangle\) & \(\blacktriangle\) & \(\blacktriangle\) & \(\blacktriangle\) \\ Substrate resistivity, \(\rho_{\text{SI}}\) & \(\blacktriangle\) & \(\blacktriangle\) & \(\blacktriangle\) & \(\blacktriangle\) & \(\blacktriangle\) \\ \hline \hline \end{tabular}  
* increase; \(\blacktriangledown\) decrease; \(\blacktriangle\blacktriangledown\) optimum; — constant.  
\end{table} 
Table 1: Layout/process parameters vs. electrical performance of an integrated inductor. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Performance Parameters** & \multicolumn{4}{c}{**Transformer Structures**} \\ \cline{2-5}  & **Interleaved** & **Stacked** & **Interstacked** & **Stacked Folded** \\ \hline Magnetic coupling factor, \(k\) & + & ++ & ++ & ++ \\ Winding \(Q\)-factors & +++ & + & ++ & + \\ Self-resonance frequency (SRF) & +++ & + & + & ++ \\ Turn ratio, \(N\) & ++ & + & - & - \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Pros and cons of different integrated transformer configurations. impact on inductive components operated at lower frequencies, where higher inductances and, hence, larger coils are used. Therefore, inductor design in standard CMOS is still a challenging issue.