# True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA
## 4 Implementation Results
### Synthesis and Implementation Results  
In Table 4 we present the implementation results obtained on a Stratix IV FPGA. The synthesis operating frequency was fixed to 100 MHz, therefore each FiGaRO stage contributed with 100 Mbps to the throughput; thus, we achieved a throughput of 400 Mbps for a four stage oscillator and 800 Mbps for an eight stage oscillator. The results are shown varying the number of FiGaRO stages and the configuration. The obtained numbers showed, as expected, that the resources usage grew linearly with both these parameters. Considering also the results achieved in terms of entropy, we observed the following:  
* 1 FiRO-1 GaRO Configuration was the one with smaller area footprint but also the worst entropy;
* 2 FiRO-2 GaRO and 4 FiRO 4 GaRO were comparable in terms of entropy;
* System robustness to possible stuck in the oscillation grew linearly with the number of FiRO and GaRO composing a FiGaRO stage;
* Resources usage grew linearly with the number of FiRO and GaRO composing a FiGaRO stage;
* The throughput of the system grew linearly with the number of FiGaRO stages in parallel;
* Resources usage grew linearly with the number of FiGaRO stages in parallel;  
Table 5 shows a comparison between our work and other TRNGs implemented on FPGA platforms. Please note that we did not implement the reported design but we relied on the results presented in the cited works. For the same reason and for conciseness, we do not report the architectural details of the design here; they can be accessed by consulting the cited works. Unfortunately the available works relied on different FPGA technology nodes: this made unfair the comparison in terms of bit rate, as newer technologies obviously are able to reach higher clock speeds. However, the rest of the metrics were not directly affected by the technology node. Moreover, most of the proposed solutions (e.g., the Self-Timed Rings (STRs) based one) were not limited by the technology but rather than entropy harvesting method: the clock frequency was limited well under the maximum available values to preserve the randomness quality. The overall comparison gave however an indication on the achievable throughput of random numbers, together with the randomness quality (entropy). \begin{table}
\begin{tabular}{c c c c} \hline \hline
**FiGaRO** & **Configuration** & **Comb.** & **Logic** \\
**Stages** & & **ALUTs** & **Regs** \\ \hline
8 & 1 FiRO 1 GaRO & 291 & 186 \\
8 & 2 FiRO 2 GaRO & 571 & 354 \\
8 & 4 FiRO 4 GaRO & 1140 & 698 \\ \hline
4 & 1 FiRO 1 GaRO & 148 & 106 \\
4 & 2 FiRO 2 GaRO & 288 & 190 \\
4 & 4 FiRO 4 GaRO & 572 & 358 \\ \hline
2 & 1 FiRO 1 GaRO & 76 & 62 \\
2 & 2 FiRO 2 GaRO & 146 & 104 \\
2 & 4 FiRO 4 GaRO & 288 & 188 \\ \hline
1 & 1 FiRO 1 GaRO & 40 & 40 \\
1 & 2 FiRO 2 GaRO & 75 & 61 \\
1 & 4 FiRO 4 GaRO & 146 & 103 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: TRNG implementation results on Stratix IV Field Programmable Gate Array (FPGA). In [27] the authors demonstrate that the TERO is highly dependent on the origin of placement; therefore, they introduce a particular TERO (TC-TERO) which overcome this issue, at the price of employing FPGA dependent primitives, loosing therefore the technology independence. The authors in [34] proposed an implementation based on Coherent Sampling (CS) phenomenon using Self-Timed Rings (STRs) instead of the commonly employed Ring Oscillators (ROs). The authors demonstrated the portability of the design and they achieved an extremely compact design, but the bit-rate remained limited due to the low sampling frequency. In fact, the design has been synthesized at 1 MHz on a Xilinx Virtex 6 FPGA, and the authors declare that higher sampling frequencies might degrade the randomness quality. On the contrary, as shown in Figure 17, in our proposed solution entropy is stable with frequency variations. The design proposed in [31] is based on the Edge Sampling (ES) technique and achieves the lowest resource consumption.