## 4 Experimental Condition
### Logic Arrangements  
This work is the first to implement various logic arrangements in forming RO inside the FPGA chip. Different arrangements of logic may influence RO performance due to  
\begin{table}
\begin{tabular}{l l} \hline
**FPGA Technology** & **Intel Cyclone V (28 nm)** \\ \hline Chip No. & 5 CSEMA45F31C6 and SCSEMA4U23C6 \\ Software & Quartus Prime 17.1 \\ RO stage & Five-stage \\ Logic arrangement & Five patterns \\ RO runtimes & 100 ns–1 ms \\ Counter size & 20-bit \\ \hline \end{tabular}
\end{table}
Table 1: Experimental conditions of the proposed RO-PUF.  
routing density. Five different arrangements of logic (called patterns) are created. The LAB of Cyclone V consists of ten Adaptive Logic Modules (ALMs). There are two LUTs and several other components in an ALM. The gates forming RO will be placed on the LUTs. Figure 2 shows five variations in the position of the gate arrangement.  
Figure 2a shows an arrangement according to Pattern-1. The gates were placed on the ALM-1, ALM-2, and ALM-3 in sequence or top to bottom. Meanwhile, Pattern-2 (as shown in Figure 2b) was the reverse sequence of Pattern-1. Pattern-3 was arranged using gates located in the middle of the LAB (ALM-5, ALM-6, and ALM-7), as shown in Figure 2c. Meanwhile, Pattern-4 (as shown in Figure 2d) was the opposite sequence of Pattern-3. The position of the gate placement following Pattern-5 was at the bottom of the LAB. Gates were placed on node ALM-10, ALM-9, and ALM-8, as shown in Figure 2e.  
The study analyzed the configuration of all gates input forming RO in the LAB. Table 2 lists all input configurations of LUTs versus patterns assigned by Quartus. For instance, the input gates configuration of Pattern-2 is [DATAF DATAE-DATAF-DATAF-DATAF-DATAF-DATAC], or FE-F-F-F-C, as shown in Table 2, of gates NAND-buffer-buffer-buffer-buffer.  
All ROs arranged according to Pattern-2 are triggered via DATAF (F). More than one configuration is assigned to ROs of Pattern-1, Pattern-3, Pattern-4, and Pattern-5, as listed in Table 2. The assignments are due to the heavy routing around some ROs. Different input configurations of LUTs might impact the total delay of the RO. The delay is minimal when a buffer or NAND is configured via input DATAF or DATAE since the signal will only pass a multiplexer. Input DATAD resulted in a higher delay because the signal will pass two multiplexers or a four-input LUT (F0) and a multiplexer, while input DATAA, DATAB, or DATAC results in the highest delay.  
\begin{table}
\begin{tabular}{l l l} \hline \hline
**Arrangement** & **Input Configurations** & **RO Trigger** \\ \hline Pattern-1 & FB-D-C-F-F, DF-D-C-F-F, FB-A-C-F-F & F, D \\ \hline Pattern-2 & FE-F-F-F-F-C & F \\ \hline Pattern-3 & FC-F-F-F-F, FC-F-D-F-F, FC-F-C-F-F, DC-F-F-F-F, FD-F-F-F-F & F, D \\ \hline Pattern-4 & FD-F-D-F-F, FA-F-D-F-F, DA-F-A-F-F & F, D \\ \hline Pattern-5 & FD-F-D-F-F, FC-F-D-F-F, FD-B-A-F-F, FD-D-D-F-F & F \\ \hline \hline \end{tabular}
\end{table}
Table 2: Configuration of LUT gate inputs in the Cyclone V.  
Figure 2: RO arrangements in a LAB (**a**) Pattern-1 (**b**) Pattern-2 (**c**) Pattern-3 (**d**) Pattern-4 (**e**) Pattern-5.