# Long-Lifetime Event-Driven Wireless Monitoring System for Pole-Mounted Transformers
## 3 Proposed Event-Driven Monitoring System
Then, the SNR of the proposed monitoring system for the \(i\)th intermittent abnormal input, \(SNR_{\text{Propi}}\), can be approximated as  
\[SNR_{\text{Propi}}\approx\alpha[\text{Max}(RMS(v_{\text{S}}(t)))]^{2}, \tag{9}\]  
If the maximum RMS value is obtained at \(t=t_{\text{M}}\), it can be rewritten as  
\[SNR_{\text{Propi}}\approx\alpha[RMS(v_{\text{S}}(t_{\text{M}}))]^{2}. \tag{10}\]  
This indicates that \(SNR_{\text{Propi}}\) is always equal to or larger than \(SNR_{\text{ECI}}\). Although local peaks can exist, the proposed monitoring system stores only the global maximum value for each intermittent abnormal input to maximize the SNR. The proposed monitoring system takes advantage of event-driven sampling and data transmission, yielding just one sample per abnormal input to reduce sampling and thus energy consumption. The energy consumption of the proposed system for the \(i\)th intermittent abnormal input, \(E_{\text{Propi}}\), can be expressed as  
\[E_{\text{Propi}}=E_{\text{ECI}}+P(\text{PEAK})(t_{\text{Ui}}-t_{\text{Li}}), \tag{11}\]  
where \(P(\text{PEAK})\) is the power consumption of the peak detector. Figure 7a shows the circuit diagram of the proposed event-driven monitoring system in detail. A passive BPF that does not require power can be used to lower energy consump  
Figure 6: Proposed event-driven monitoring system. (**a**) Block and (**b**) timing diagrams. tion. The enable signals generated by the EC set each block--the RMS converter, peak detector, ADC, and TX--to fall into either normal or sleep mode. The EC is composed of three comparators, a D flip-flop, an AND gate, and two capacitors with reset switches. _CMP\({}_{1}\)_ operates at high speed to detect abnormalities over a wide frequency range, but _CMP\({}_{2}\)_ and _CMP\({}_{3}\)_ can be low-speed and low-power comparators that only reset the enable signals. For event-driven enable controls, the EC needs to be always on to monitor input abnormalities. The timing diagram of the proposed monitoring system is shown in Figure 7b. It has four phases. In phase I, an abnormality in the input is detected by _CMP\({}_{1}\)_ when \(v_{\text{IN}}>V_{\text{REF1}}\). Then, the generated clock pulse \(CK_{\text{IN}}\) triggers a D flip-flop and sets \(EN_{\text{RMS}}\) high to turn on both the RMS converter and the peak detector until _CMP\({}_{2}\)_ and _CMP\({}_{3}\)_ detect the conditions \(v_{\text{PEAK}}>v_{\text{RMS}}\) and \(v_{\text{RMS}}<V_{\text{REF2}}\). The increment in \(v_{\text{RMS}}\) is proportional to \(C_{1}\), which works as a low-pass filter; \(v_{\text{PEAK}}\) is stored in \(C_{2}\). In phase II, the ADC is enabled to sample \(v_{\text{PEAK}}\) after disabling both the RMS converter and the peak detector. Thereafter, the digital value \(D_{\text{O}}\) of \(v_{\text{PEAK}}\) is delivered to the TX. In phase III, after finishing sampling, the ADC generates an end-of-conversion (EOC) signal that enables the TX and resets \(C_{1}\) and \(C_{2}\). Finally, the output of the TX, \(D_{\text{OUT}}\), is generated by adding a wireless communication protocol to \(D_{\text{O}}\). In phase IV, after finishing transmission, all blocks except the EC fall into sleep mode; the EC continues to monitor abnormality in the input. Figure 7: Proposed monitoring system. (**a**) Detailed circuit and (**b**) timing diagram.