## 4 Extraction of the Word-Based SISO Semisystolic Processor  
The approach used to explore the intended word-based SISO semisystolic processor starts by extracting the DG of the adopted algorithm. As we notice, Algorithm 2 performs regular iterations with two indices \(i\) and \(j\). Therefore, it can be expressed in the two-dimensional (2D) domain, as shown in Figure 1. The DG consists of an array of node operations. Each node can be allocated using the corresponding row index \(i\) and the corresponding column index \(j\). The DG has two types of nodes: the upper light orange nodes and the lower light blue nodes. The light orange nodes, arranged in the upper \(d\) rows, perform the operations of Steps 4 to 8 of Algorithm 2, while the light blue nodes perform the operations of Steps 13 and 14 of the same algorithm. The nodes in the first row of the DG receive the initial bits \(e_{j}^{0}\), \(x_{j}^{0}\), \(y_{j}^{0}\), \(p_{j}^{0}\), \(s_{j}^{0}\), \(g_{j}\), and \(g_{j}^{\prime}\) of variables \(E\), \(X,Y,P,S,G\), and \(G^{\prime}\), respectively. In the upper \(d\) rows of DG, the updated partial bits \(e_{j}^{i}\), \(x_{j}^{i}\), \(y_{j}^{i}\), \(p_{j}^{i}\), and \(s_{j}^{i}\) besides the bits \(g_{j}\) and \(g_{j}^{\prime}\) are designated by the vertical lines. The updated partial bits of \(e_{j}^{i}\) are also passed diagonally as designated by the slanted red lines. The input bits of \(e_{2i-2}\), \(e_{2i-1}\), \(f_{2i-2}\), and \(f_{2i-1}\), as well as the updated partial bits of \(e_{n-2}\), \(e_{n-1}^{i-1}\), and \(e_{j-2}^{i-1}\) are broadcast horizontally to all nodes in the same row of the upper \(d\) rows in DG. The resulting bits \(x_{j}^{d}\), \(p_{j}^{d}\) from the \(d\)th row, as well as the broadcast bits \(g_{j}\) are passed vertically to the nodes in the last row of the DG. Furthermore, the resulting bits of \(y_{j}^{c}\) and \(s_{j}^{c}\) are passed diagonally to the same nodes as shown in Figure 1. These bits are used to compute the final bits of field multiplication \(q_{j}\) and field squaring \(r_{j}\), as indicated in Figure 1.  
The second step in the utilized approach, as discussed in [30], is to find a valid scheduling function to allocate a time value to each node of the DG. The last step of the procedure is to find a projection function to map the DG nodes to a corresponding Processing Element (PE) in the extracted systolic/semisystolic array. There are two types of scheduling and projection functions, as explained in [30]: affine (linear) scheduling and projection functions and nonlinear scheduling and projection functions. The affine scheduling and projection functions have the following limitations:  
1. The inputs and outputs can only be accessed as bit-serial (one bit at a time) or bit-parallel (all bits at the same time instance) based on our choice of the scheduling function. That means that the linear functions cannot satisfy any restrictions on the processor bus size;
2. The designer cannot manage the number of accessed input or output samples at a particular time step;
3. The number of active PEs cannot be managed at a specific time step;
4. The designer cannot manage the PE's workload. The nonlinear scheduling and projection functions avoid all of these limitations and provide the designer with more flexibility to control the number of accessed inputs and outputs and the number of utilized PEs, as well as the PE's workload. In our case, we require that the unified SISO multiplier-squarer feeds in variables \(E\), \(F\), \(G\), and \(G^{\prime}\) in a word-serial fashion at the start of the iteration and produces the output products \(Q\) and \(R\) in a word-serial fashion at the end of the iteration. Assuming the processor word size is \(k\), we need to feed in \(k\) bits of input variables at the first clock cycle and produce \(k\) bits of output products at the last clock cycle. The following subsections display the selected nonlinear scheduling  
Figure 1: DG of the bipartite multiplication-square algorithm for \(n=5\).