# Interference Mitigation for GNSS Receivers Using FFT Excision Filtering Implemented on an FPGA
## 3 Proposed Methodology  
This research methodology is based on quantitative research methods. The quantitative methods are presented using experimental research methodology and engineering-oriented research methodology.  
Figure 3 shows the full scheme of the proposed methodology and experimental work for this research. This research work consists of three stages as shown in Figure 3, which are GNSS data capture, MATLAB simulation, and FPGA implementation. The first stage is called GNSS data capture. The first block of this stage represents the GNSS simulator (Spirent GSS8000), which produces representative GNSS signals whose power levels can be controlled as desired. The output of the simulator represents the RF GNSS signal at the output of the receiver's antenna. It is then amplified using the low noise amplifier (LNA). LNA is a fundamental component because it amplifies the signal that comes from the antenna without adding a significant level of noise. This boosts the signal to protect it from the noise sources generated within the system (switching noise, harmonics, etc).  
The next block is the RF front-end datalogger. This block has two phases. Regarding the first phase, the RF signal is converted to an intermediate frequency (IF) that has a sufficient frequency to support the signal bandwidth. The second phase is the signal being converted to digital signals using an analogue digital converter (ADC) with automatic gain control (AGC). The output digital IF is passed to PC and stored as a data file. The second stage is the simulation and testing of the GNSS receiver performance using MATLAB. This stage contains three main blocks, which is the addition of interference, interference mitigation (the FFT excision), and the software GNSS receiver. The narrowband interferences that can be applied are single jammer, multiple jammers, and sweeping jammers, all with configurable power levels and frequencies. After this, the data is sent to the interference removal filter block, which represents the designed FFT excision filter, to mitigate the GNSS receiver interference. Finally, the signals are sent to the software GNSS receiver after the interference mitigation to test the influence of the jamming on the receiver operations.  
The fundamental stage of this research is the third stage, which is the implementation stage in FPGA. This stage is carried out for both the hardware implementation and to validate the simulation and testing stage. As shown in Figure 3, the output signal data with the added interference acts as an input for the very high-speed integrated circuit hardware description language (VHDL) test bench. Then, the output of the VHDL test bench is verified by sending it back to the software GNSS receiver to test the performance and compare it with the MATLAB simulation results. Using this comparison algorithm, the FFT excision-designed filter is verified as an optimal solution to mitigate the interference of the GNSS receiver in terms of software simulation and hardware implementation. The following sections illustrate the stages of developing the proposed scheme.