## 7 Conclusions and Future Directions  
In this study, we have introduced a communication model between cores that combines the predictability of Logical Execution Time with a synchronization mechanism in heterogeneous systems and the composability of time-controlled buffers. This is achieved using a Time-Division Multiple Access scheme for inter-core communication. Given the critical nature of deadlines in real-time tasks, this approach ensures constant latency between tasks on different cores using a shared memory channel, addressing hardware limitations and timing dependencies. This reduces the need to bind applications to specific cores and facilitates the creation of less dependent event chains. Furthermore, by establishing time intervals for data transfer between cores, deterministic data flows can be modeled. The portability of this approach allows it to be used across various platforms, as it is not tied to specific hardware implementations. Our analysis and results demonstrate the following: (a) Improved temporal predictability: The integration of LET with TDMA improves the temporal predictability of read and write operations in multicore systems, achieving a constant latency of 11 ms. (b) Reduced variable latency: Measurements of data transfer between cores using shared buffers of 8, 16, and 32 bits showed a latency of approximately 1 ms, enhancing system consistency, compared to the LET model, which showed variable latencies of 3.2846 ms, 8.9257 ms, 0.2338 ms for 8, 16 and 32 bits. (c) Enhanced system consistency: Implementing this method enabled predictable and synchronized access times to shared resources, with access times improving to 10 ms, thereby enhancing system consistency. Moreover, the TDMA implementation allows global buffers to be shared among multiple tasks across different cores due to the temporal isolation of this scheme, making them reusable within defined time intervals. Despite its performance benefits, this method faces certain limitations. The event chains were limited to two tasks and one label each, focusing on latency improvement on a dual-core embedded microcontroller. RAM was used for shared buffers, and LET management was independent of the Runtime Environment (RTE) and operating system software. The reference conditions in this study focused on evaluating the real impact of the cross-core LET-TDMA implementation and its improvements. However, in more complex configurations with event chains distributed across more than two cores, data loss could still occur, especially in systems handling multiple external events. Balancing external event handling is crucial to avoid TDMA scheduling disruptions. Future work could explore expanding this technique to support more cores by distributing event chains across multiple cores. Integrating LET-TDMA management as an RTE implementation addon could simplify inter-core event chaining through configuration and code generation. Additionally, optimizing shared buffer strategies using technologies like DMA or platform-specific inter-process communication implementations, abstracted through standardized interfaces, remains a relevant topic for future research. Conceptualization, C.-A.M.-A. and J.-A.-R.-G.; methodology, C.-A.M.-A. and J.-A.-R.-G.; software, C.-A.M.-A. ; validation, C.-A.M.-A., J.-A.R.-G., D.-M.C.-E., J.R.-R. and J.T. ; formal analysis, C.-A.M.-A., J.-A.R.-G., D.-M.C.-E., R.C.-S. and J.T. ; investigation, C.-A.M.-A., J.-A.R.-G., D.-M.C.-E., R.C.-S., J.T. and J.R.-R.; resources, J.R.-R.; data curation, C.-A.M.-A., J.-A.-R.-G.,D.-M.C.-E., R.C.-S., J.R.-R. and J.T. ; writing--original draft preparation, C.-A.M.-A. and J.-A.-R.-G., writing--review and editing, C.-A.M.-A., J.-A.R.-G., D.-M.C.-E., R.C.-S., J.T. and J.R.-R.; visualization, C.-A.M.-A., J.-A.R.-G., D.-M.C.-E., R.C.-S., J.T. and J.R.-R.; supervision, C.-A.M.-A., J.-A.R.-G., D.-M.C.-E., R.C.-S., J.T. and J.R.-R.; project administration, C.-A.M.-A., J.-A.R.-G., D.-M.C.-E., R.C.-S., J.T. and J.R.-R.; funding acquisition, C.-A.M.-A., J.-A.R.-G., D.-M.C.-E., R.C.-S., J.T.