# Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices
## 1 Introduction  
In recent years, the emerging Internet of Things (IoT) technology has simultaneously introduced challenges and opportunities for engineering-related fields. IoT devices include smartphones, smart cards, biomedical devices, radio frequency identification (RFID) tags, and many other cryptographic devices that require security characteristics, such as authenticity, integrity, and confidentiality in performing their tasks [1, 2]. Security is one of the main current challenges for IoT [3, 4, 5, 6] as it begins to materialize in our daily life and future industrial systems (Industry 4.0) [7]. IoT devices must face several tough challenges, such as low energy consumption, lack of computational resources [8, 9], as well as the need to secure devices against cyber-attacks [10]. Authentication, authorization, and privacy are three sides of the security triangle in IoT. Authentication is the first barrier in front of cyber-attacks. Physical unclonable functions (PUFs) have been proposed as a lightweight, cost-efficient, and ubiquitous solution. Importantly for IoT developers, PUFs promise to achieve perfectly secure authentication without any cryptographic assets on the device, which makes them especially interesting for resource-scarce IoT devices [11, 12]. The characteristics of a PUF include unpredictable response (R) as an output of the system owing to intrinsic variations, which are stimulated by the input challenge (C). The challenge-response system is modeled as a black box; hence, the PUF input-output relation is described as R = f(C), where f(.) is an unknown internal parameter influenced by theintrinsic variations of the device [13; 14]. Practically, no two chips generate identical responses for a particular challenge, as depicted in Figure 1. The combination of a challenge and its corresponding response is called a challenge response pair (CRP). The PUF security metrics (the stability, the reliability, and the uniqueness) and the low power requirement have triggered enormous studies at the PUF cell level, such as investigations on the arbiter PUF [16; 17; 18], ring-oscillator (RO) PUF [19; 20; 21; 22; 23; 24], be-stable ring PUF [25], glitch PUF [26], dynamic random access memory (DRAM) PUF [27; 28], and static random access memory (SRAM) PUF [29; 30]. In addition, many studies on low-power PUF circuits have been conducted, such as robust digital response and low-power current-based PUF [31], as well as the SRAM-based PUFs, over a wide range of supply voltages from the super-threshold voltage regime down to the near-threshold voltage (NTV) regime [32]. It has to be noted that the IoT devices are mostly battery-powered embedded devices and operate in low-frequency ranges. Meanwhile, all PUF cells presented in [16; 17; 18; 19; 20; 21; 22; 23; 24; 25; 26; 27; 28; 29; 30], undergo high-power consumption and voltage ramp-up time adaptation for a reliable PUF circuit [33]. To address for low-power and stable PUF security profiles, the low-power technique of the adiabatic switching principle [34] has been adopted in SRAM style PUF cell design [33; 35]. Continuous scaling-down of planar MOSFETs over the past four decades has delivered ever-increasing transistor density into integrated circuits (ICs). However, continuing this trend in the nanometer regime is very challenging due to the drastic increase in the subthreshold leakage current (Joff) [36; 37; 38]. Due to the very narrow channel lengths in deeply scaled MOSFETs, the drain potential begins to influence the electrostatics of the channel and, consequently, the gate loses adequate control over the channel. As a result, the gate is unable to shut off the channel completely in the off-mode of operation, which leads to an increased Joff between the drain and the source [39]. Very limited work on employing FinFET-based PUF has reported, such as FinFET-based hybrid ring arbiter PUF [40] and oscillator collapse and time collapse comparator PUFs [41]. In this work, a novel study on FinFET-based SRAM PUF is presented.