###### Abstract  
This paper addresses the increasing demand for computing power and the challenges associated with adding more core units to a computer processor. It explores the utilization of System-on-Chip (SoC) technology, which integrates Terahertz (THz) wave communication capabilities for intra- and inter-chip communication, using the concept of Wireless Network-on-Chips (WNoCs). Various types of network topologies are discussed, along with the disadvantages of wired networks. We explore the idea of applying wireless connections among cores and across the chip. Additionally, we describe the WNoC architecture, the flip-chip package, and the THz antenna. Electromagnetic fields are analyzed using a full-wave simulation software, Ansys High Frequency Structure Simulator (HFSS). The simulation is conducted with dipole and zigzag antennas communicating within the chip at resonant frequencies of 446 GHz and 462.5 GHz, with transmission coefficients of around \(-28\) dB and \(-33\) to \(-41\) dB, respectively. Transmission coefficient characterization, path loss analysis, a study of electric field distribution, and a basic link budget for transmission are provided. Furthermore, the feasibility of calculated transmission power is validated in cases of high insertion loss, ensuring that the achieved energy expenditure is less than 1 pJ/bit. Finally, employing a similar setup, we study intra-chip communication using the same antennas. Simulation results indicate that the zigzag antenna exhibits a higher electric field magnitude compared with the dipole antenna across the simulated chip structure. We conclude that transmission occurs through reflection from the ground plane of a printed circuit board (PCB), as evidenced by the electric field distribution. system-on-chip; on-chip antenna; intra- and inter-chip communication; wireless network networks. Sensors2024232202432202  
number of cores in a device increases for HPC workloads, communication between distant cores requires many hops, where data packets will transit via a router/switch. This causes extra delay and power consumption, as well as a high signal-to-noise ratio (SNR) requirement [3]. A Wireless Network-on-Chip (WNoC) is a new concept that replaces conventional interconnects with wireless ones. By embedding an antenna into the chip of a multi-core system, communication may occur throughout the entire chip via a single hop, which can be either point-to-point or point-to-many, as in a broadcast system such as sharing cache memory [4]. WNoCs are made up of transmitters and receivers. Artificial intelligence (AI), virtual reality (VR), and augmented reality (AR) applications necessitate high-speed data processing, putting substantial strain on the chip's processing units. Wireless networks linking these cores must support orders-of-magnitude-greater data speeds, in the hundreds of gigabits per second (Gbps) range. Terahertz (THz) technology appears as a viable alternative to satisfy the bandwidth and low-latency needs of these wireless links. THz antennas are particularly well suited for WNoC research because of their small size. A micron-sized wireless transceiver improves communications within the chip, enhancing the computational capability of multi-core processors [5]. In this study, we make a significant contribution to advancing communication within multi-core processor architectures by focusing on the implementation of wireless interconnects. Through rigorous modeling and simulation, we investigate the capabilities of THz antennas for ultra-short-distance communication both within and among chips. Specifically, we explore the potential of THz technology within the context of a realistic flip-chip package and analyze the results of electromagnetic wave propagation such as transmission parameter, path loss, and electric field distribution within the chips. Our contribution incentivizes CPU manufacturing companies to explore the feasibility of intra- and inter-chip communication via THz wireless links.