# Reduction of Bias and Light Instability of Mixed Oxide Thin-Film Transistors
## 2 Materials and Methods  
Figure 1 illustrates the fabrication process of the a-IGZO TFTs investigated in this study. The process begins with the deposition of a 60-nm thick Mo layer on glass by sputtering and its patterning by standard lithography to form the gate electrode (Figure 1a). This is followed by the consecutive deposition of a 250 nm-thick SiO\({}_{2}\) layer by plasma-enhanced chemical vapor deposition (PECVD) as the gate insulator at 380 \({}^{\circ}\)C, deposition of an a-IGZO layer by sputtering at 200 \({}^{\circ}\)C, and deposition of a 100 nm-thick SiO\({}_{2}\) back passivation layer by PECVD at 200 \({}^{\circ}\)C in a cluster deposition tool, without breaking vacuum (Figure 1b). This step ensures the in situ passivation of the a-IGZO, immediately after deposition, to realize an uncontaminated and very stable a-IGZO layer that is necessary for the detection of intrinsic characteristics, rather than fabrication process-related variations. Samples with a-IGZO thickness (\(t_{\text{IGZO}}\)) of \(\sim\)3, 5, 10, 20, 50, and 100 nm are fabricated. The sputtering of the a-IGZO is performed using a polycrystalline IGZO target (In\({}_{2}\)O\({}_{3}\):Ga\({}_{2}\)O\({}_{3}\):ZnO = 1:1:1 mol %) at 200 \({}^{\circ}\)C. The Ar:O\({}_{2}\) gas ratio is set at 4:8 for sputtering. The top SiO\({}_{2}\) layer, which is a protective layer, commonly referred to as the \"etch stopper\", is patterned to expose the source and drain regions for the metal contacts (Figure 1c). During the fabrication process, the etch stopper protects the a-IGZO from exposure to air and also shields it from being etched away or contaminated by the etchant used to define the source/drain electrodes. The patterning of the a-IGZO layer to form active islands (Figure 1d) follows the etch-stopper process. Deposition of another Mo layer and its patterning to form the source/drain electrode contacts and a 200 nm-thick SiO\({}_{2}\) layer as the final TFT passivation layer (Figure 1e) follows the a-GZO process. The final step is the annealing of the TFTs at 250 \({}^{\circ}\)C in vacuum to ensure a reproducible unstressed state. We confirmed TFT layer thicknesses by means of transmission electron microscopy (TEM) imaging as shown in Figure 2 and determined the crystallinity and chemical composition of the IGZO layers by X-ray diffraction (XRD) patterns and X-ray photon electron spectroscopy (XPS), respectively. In XRD (Figure 3a), the IGZO films do not exhibit sharp diffraction peaks assignable to a crystalline phase but have two halo peaks at 32\({}^{\circ}\) and 56\({}^{\circ}\), indicating that they are amorphous. The a-IGZO film is transparent in the visible range (Figure 3b), owing to its large band gap = -3.2 eV (Figure 3c). XPS results show that the a-IGZO chemical composition is In:Ga:Zn = 3:2:1 in an atomic ratio (Figure 3d). We measured the current-voltage (\(I\)-\(V\)) characteristics using the Agilent 4156C precision semiconductor parameter analyzer, and the capacitance-voltage (\(C\)-\(V\)) characteristics using the Agilent E4980A Precision LCR meter by superimposing the gate DC voltage (\(V_{\text{GS}}\)) on a small AC signal (0.1 V) of frequency (\(f\)) at 1 kHz, keeping the source and drain shorted. Note that the \(f\) of the AC signal should be low enough to guarantee quasi-static conditions, \(1/f\gg\) RC time constant of the system, so that the induced AC variation of surface potential \(\Psi_{\text{S}}\) can be considered constant along the channel [21]. Consistent with previous reports, we accomplished the NBIS by holding the TFT \(V_{\text{GS}}\) at \(-20\) V for 10,000 s, while biasing the source and drain electrodes at zero volts, under white-light illumination (9000 nit) and at room temperature [8; 16; 17; 18]. TFT parameters were derived from the conventional metal-oxide, semiconductor field-effect transistor (MOSFET) equation.