# Interface Growth and Void Formation in Sn/Cu and Sn0.7 Cu/Cu Systems
## 1 Introduction  
Intermetallic compounds (IMCs) and voids that form at the interface between solder and copper joints have been given great attention, because the existence of these interfacial IMCs and voids are crucial to several reliability concerns [1; 2]. Especially, the solder joints have been continuously scaled down due to the trends of microelectronic products from two-dimensional integration of circuits (2D IC) to three-dimensional integration of circuits (3D IC) [3]. IMCs' growth and voids formed at the interfacial could induce more brittle fracture and impact fatigue failures [4; 5].  
In a Sn-Cu system, when the molten Sn-based solder alloy wets the Cu substrates, two different types of IMCs, e.g., Cu\({}_{6}\)Sn\({}_{5}\) and Cu\({}_{3}\)Sn, form at the solder/Cu interface. Generally, the Cu\({}_{6}\)Sn\({}_{5}\) layer was reported to be firstly formed at the liquid reaction stage, and becomes thicker with the solid state aging process. Later, a thin Cu\({}_{3}\)Sn layer is usually formed during the solid state aging process [6; 7]. The Cu\({}_{3}\)Sn layer is usually formed during solid state aging process. Moreover, the formation of Cu\({}_{3}\)Sn would result in much bigger volume shrinkage relative to Cu\({}_{6}\)Sn\({}_{5}\)[8; 9]. As a result, Kirkendall voids (KVs) usually were observed at the Cu/Cu\({}_{3}\)Sn interface. It was reported that adding minor metallic (e.g., Ni, Ag, Cu, Zn, Al, Fe etc.) and ceramic (e.g., Al\({}_{2}\)O\({}_{3}\), ZrO\({}_{2}\), TiO\({}_{2}\), SiC etc.) elements into the Sn-based solder could suppress the formation of voids and retard the growth of IMCs [10; 11; 12; 13; 14; 15]. Cu is a basic element in the lead-free solder. Actually, recent research found that Cu also played an importantrole in reducing the thickness of the Cu\({}_{3}\)Sn IMC layer [16]. However, the mechanism of Cu addition retarding the growth of the Cu\({}_{3}\)Sn layer and void formation has not been clarified.  
As we know, the Cu substrate in solders/Cu joint is made by the electroplating process. It is clearly different from high-purity Cu (HP Cu). Researchers points out that the voids are more prone to be formed in the Sn-based solder/EP Cu joints, relative to the Sn-based solder/HP Cu joints. Extensive research has been done on the effect of impurities of EP Cu on the formation of KVs [17; 18; 19]. [PERSON] and [PERSON] [17; 18] clearly pointed out the detrimental effect of residual impurities in electroplated Cu UBM (under ball metal) on the void formation, and especially studied the effect of the S element. [PERSON] et al. [19], proceeding from the source of impurities, systematically studied the influence of electroplating parameters on void formation at the interface. However, there have been few studies that explore the microstructure of Cu substrate. [PERSON] et al. [20] mentioned that the formation of voids might be affected by the grain size of the Cu substrate.  
In the present study, the HP Cu substrate, EP Cu substrate, and Sn0.7 Cu solder were used to produce Sn/Cu joints. The effect of the microstructure of Cu substrates and Cu addition (0.7%) on the interface growth and void formation were analyzed. The interface evolution, especially the Kirkendall voiding level, was discussed.