## 5 Simulation and Hardware Realization of the Basic Unit of the Proposed GSMLI Topologies  
To assert the feasibility of the topologies, a MATLAB(r)/Simulink-based simulation was carried out. For the simulation of this topology in symmetric configuration, \(V_{1}\) and \(V_{2}\) were taken equal to 12 volts and the other parameters were taken according to Table 3. For simulation of the proposed topology in asymmetric configuration, \(V_{1}\) and \(V_{2}\) were taken equal to 12 and 36 volts, respectively, and the other parameters were taken according to Table 3.  
Figure 8 shows the output voltage waveform and load current for the symmetric configuration (9 levels) of the proposed topology under R load for M at unity. Figure 9a \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameters** & **Attributes** \\ \hline Switches (\(T_{1}\) to \(S_{d}\)) & IGBT/Diode \\ Switching frequency (\(f_{s}\)) & 50 Hz \\ Load (purely resistive) & 100 \(\Omega\), \\ Capacators \(C_{1}\),\(C_{2}\) & 2200 \(\mu\)F, 4300 \(\mu\)F \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Parameters used in the simulation of the symmetrical and asymmetrical configurations. Figure 6: Level generation method of the optimized nearest level control. Figure 7: Block diagram of an Optimized Nearest Level Control (ONLC). shows the output voltage and current for dynamic change in modulation index and Figure 9b shows the total harmonics distortion (THD) in output voltage for symmetric configuration. Figure 10 show the voltage across capacitor C1 (2.5% ripple) and capacitor C2 (2.5% ripple) under the symmetric configuration. Figure 11 shows the waveforms of load current and output voltage for the asymmetric configuration (17 levels) of this topology at M = 1.0 with a purely resistive load. From these figures, it is confirmed that the proposed topology has the capability to generate all positive and negative voltage levels. A gain factor of 40 was taken to multiply the load current in order to have its scale be the same as that of the output voltage. While Figure 12a shows the voltage and current during dynamic change in the load from resistive to resistive-inductive, Figure 12b shows the voltage and current for the asymmetric case for a varying modulation index. THD in output voltage is 9.06% and 4.63% under the symmetric (9 levels) and asymmetric (17 levels) configurations, respectively. Due to the resistive load, the current harmonic spectrum is the same as the load voltage. Figure 13 show the voltage across capacitor C1 (2.5% ripple) and capacitor C2 (2.5% ripple) under the asymmetric configuration. Figure 8: Output voltage and load current for symmetric configuration. Figure 9: (**a**) Output voltage and current for dynamic change in modulation index and (**b**) total harmonics distortion (THD) in output voltage for symmetric configuration. A laboratory prototype was developed in order to verify the simulation results and performance of the proposed SCMLI topology. Figure 14 shows the setup of the laboratory prototype for the proposed topology. In this experimental work, an Insulated Gate Bipolar Transistor (IGBT) (FGA25N120 AND) with rating 1200 V/25 A was utilized as the power electronic switch signals to the switches by interfacing with SIMULINK. Diode BEC0141 with a rating of 10A was used as the power diodes, an electrolyte capacitor with a rating of 4700 \(\upmu\)F/63V was utilized as the switched capacitors, and TMS320 F28335 (Texas Instruments) was used as a controller for the generation of the gating prototype and controller isolated by using the TLP 250 (TOSHIBA) optocoupler. A Digital Storage Oscilloscope (TPS2024B TEKTRONIX) was employed for the measurement of the waveforms of voltage and current. For the experimental results of the symmetric configuration, voltage sources V1 and V2 were taken equal to 12 volts each. This resulted in a 9-level staircase output voltage with a 48-volt peak value, as shown in Figure 15a. Figure 15a also shows the load current when a purely resistive load of 100 \(\Omega\) was connected at the output.