## 3 Performance Evaluation of the Proposed SAR Processor
### Hardware Resource Utilisation  
In term of hardware resource utilisations, the proposed SAR processor was evaluated by synthesis and implemented into the FPGA device, Altera Stratix IV GX series EP4 SGX230 KF40C2 is, which is located inside the embedded SAR processor, an DE4 development board. There are six metrics to be considered in the area of hardware resource utilisations, i.e., the combinational adaptive look-up table (ALUT), total dedicated logic registers, total pins, total block-memory bits, M9K block memory and DSP block 18-bit elements [14]. Performance evaluations were conducted by comparing the hardware resource utilisations in six metrics for both the Altera IP FFT /IFFT coprocessor and the proposed FFT /IFFT coprocessor with a transform length of 2048 points and 4096 points. The evaluations are tabulated in Table 3. From Table 3, it is noticeable that for all transform lengths of the FFT /IFFT coprocessors, the proposed FFT /IFFT coprocessors used less hardware resources in all six metrics as compared to the Altera IP FFT /IFFT coprocessor. The reduction in hardware usage significantly helps in the development of the integrated SAR processor, as more hardware resources quota can be allocated to other submodule designs in the SAR processor. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Modules**} & \multicolumn{3}{c}{**Range Compression**} & \multicolumn{3}{c}{**Azimuth Compression**} \\  & \multicolumn{3}{c}{**(2048 Azimuth Lines)**} & \multicolumn{3}{c}{**(4096 Range Lines)**} & \multicolumn{3}{c}{**Total Time (ms) to**} \\ \cline{2-7}  & **4096 FFT** & **Complex Multiplier** & **4096 IFFT** & **2048 FFT** & **Complex Multiplier** & **2048 IFFT** \\ \hline Operation & \multirow{2}{*}{345.27} & \multirow{2}{*}{24.66} & \multirow{2}{*}{345.27} & \multirow{2}{*}{320.6} & \multirow{2}{*}{24.66} & \multirow{2}{*}{320.6} & \multirow{2}{*}{1381.06} \\ Time (ms) & & & & & & & \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Timing performances of the proposed SAR processor. \begin{table}
\begin{tabular}{l l l} \hline \hline \multirow{2}{*}{**Area of Hardware Resources**} & \multicolumn{3}{c}{**Resources Reduction**} \\ \cline{3-4}  & **Altera IP 2048-FFT/IFFT vs.** & **Altera IP 4096-FFT/IFFT vs.** \\  & **Proposed 2048-FFT/IFFT** & **Proposed 4096-FFT/IFFT** \\ \hline \hline \multicolumn{1}{l}{Combinational ALUTs} & 68.16\% & 55.46\% \\ \multicolumn{1}{l}{Total dedicated logic registers} & 79.84\% & 80.08\% \\ \multicolumn{1}{l}{Total pins} & 20.00\% & 20.00\% \\ \multicolumn{1}{l}{Total block-memory bits} & 44.78\% & 43.44\% \\ \multicolumn{1}{l}{M9K block memory} & 38.46\% & 36.84\% \\ \multicolumn{1}{l}{DSP block 18-bit elements} & 33.33\% & 66.67\% \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Resource reduction of the proposed system (different points of FFT /IFFT, 2048-, and 4096-point) in reference to Altera IP. Total hardware resource utilisation for the proposed SAR processor is summarised and tabulated in Table 4. The hardware utilisations are partitioned into two main sections, which are the range-compression module and the azimuth-compression module. The range-compression module comprises a 4096-FFT coprocessor, a complex multiplier, a ROM precomputed for the range-reference function and, lastly, a 4096-IFFT coprocessor. As for the azimuth-compression module, it consists of a 2048-FFT coprocessor, a complex multiplier, a ROM precomputed for the azimuth reference function and, lastly, a 2048-IFFT coprocessor. Overall, the range-compression module utilises more hardware resources as compared to the azimuth-compression module. This is mainly due to the 2048-point FFT/IFFT modules used in the azimuth compression, while the range-compression module consist of 4096 points FFT/IFFT. The comparison of the performance between the proposed system and the previous SAR onboard processor is summarised in Table 5. The proposed system is to be used for low-altitude UAV-based SAR, with an image size of 4096 \(\times\) 2048 tested in this project.