## 2 Significance of the Study  
In the wired connection of a multi-core CPU, communication among the cores is achieved through metallic wires, forming the interconnected network topology. Common topologies include ring and mesh topologies [6], as depicted in Figure 1. Depending on the application and the need to improve communication performance among cores, various topologies are utilized, such as ring circulant [7], Spidergon STNoC [8], star, binary tree, butterfly, and torus [9]. The network faces challenges with high latencies as the network diameter increases. In any network with an N \(\times\) N mesh configuration, the network diameter is typically \(\text{2N}-1\). Therefore, to establish communication between cores situated at the edge in a  
Figure 1: Ring and mesh topology. 3 \(\times\) 3 configuration, wired connections would require four hops, resulting in relatively higher latency. Efforts have been made by [10] to address this, including proposing the flattened butterfly, which connects concentrated cores/nodes in all dimensions using dedicated links to reduce the network diameter where cores are separated by two hops [11]. However, connecting distant cores requires long wires, which suffer from signal attenuation in high-speed communication. Numerous methods have been proposed to enhance network efficiency, such as inserting long-range links in existing mesh networks (also known as diametrical 2D-mesh interconnection [12]), implementing long-range wired links following a small-world (SW) graph [13], virtualizing channels to connect distant cores directly to avoid intermediate nodes [14], and introducing global lines (G-lines) for control signals [15]. Intermediate repeaters/switches/routers are necessary to reach indirectly connected or distant cores. Additionally, the limited bandwidth of metal wires makes them unsuitable for contemporary high-speed computing applications. New solutions have been proposed to enhance core communication efficiency, such as through-silicon vias (TSVs) [16], which enable the 3D integration of multiple cores stacked atop one another in a single chip, connected through TSVs. However, this approach leads to higher heat densities in specific areas, resulting in cooling issues. These issues could be mitigated through the use of micro-cooling channels [17], but due to their taller and wider nature, they increase the processing power and data transfer delay when using TSVs [18]. Recently, new designs incorporating photonics and optical interconnections have emerged [19; 20], enabling communication at the speed of light with reduced interference, low loss, and increased bandwidth. Despite the larger bandwidth offered by optical communications, optical modulators, even in wired optical fiber links, still operate at relatively slow speeds [16]. Additionally, auxiliary circuits such as modulators, demodulators, and electrical-to-optical converters introduce fabrication costs and pose unique challenges in design and packaging. Furthermore, scattering and diffracting phenomena are unavoidable in optical systems, and implementing broadcasting features proves to be challenging. Alternatively, Field Programmable Gate Arrays (FPGAs) offer adaptability, allowing the configuration of hops for specific functions. This adaptability reduces the number of hops among cores, enhancing performance and decreasing latency [21]. In a wired connection, the signal travels at the speed of light through metallic wires. However, the rate can be influenced by several factors, such as the material, thickness, width, and spacing of the wires, which contribute to the RC delay [22]. Similarly, in wireless interconnections like Wireless Network-on-Chip (WNoC), the delay is affected by factors such as signal attenuation, path loss, interference, and a higher likelihood of errors. Despite these challenges, the larger bandwidth available in the THz band enables higher data rates and supports parallel transmissions without physical interference.