# An Energy-Efficient Strategy for Microcontrollers
## 4 Experiments and Results
### DVFS, Power Modes, and Their Overheads  
A series of test cases are designed to investigate how much time and energy the processor will consume during processor clock frequency transitions. A rich set of test cases for DVFS technology is designed. The results are shown in Figure 9. According to our test results, some conclusions can be drawn:  
1. The time overhead of processor clock frequency transitions is relatively fixed, regardless of the difference between the previous and the latter processor frequency. 2. The time overhead for STM32F407 to switch the processor frequency can be as high as approximately 70 ms.
3. Considering that the peripheral clock of STM32F407 is obtained by dividing the HCLK, adjusting the processor frequency not only brings time overhead but also makes the peripherals unable to work and communicate during this period. After the processor frequency is changed, APB1 and APB2 must be reinitialized to work with the peripherals again, making the situation even worse. The working current during the transition of the processor clock frequency is about 12.053 mA, among which about 4.075 mA is consumed by the processor, and the remaining 7.978 mA is consumed by peripheral components. Thus, the energy consumption of the processor clock frequency transition is about 4.218 mJ each time. STM32F407 offers three different power-saving modes: sleep mode, stop mode, and standby mode. There are different regulator options in sleep mode and stop mode. Different power-saving modes with varying regulator options have different power domains turned off, which results in varying energy-saving effects. Table 2 shows the working current and power consumption of STM32F407 in different power modes with different regulator options. Figure 9: Time overhead of the processor clock frequency transitions for STM32F407. The experiment results in the previous subsection show that the power consumption of the peripheral components will not vary with different processor clock frequencies. However, from the table above, it can be seen that the power consumption of the peripheral components shows a significant change with the processor power-saving modes. The results show that standby mode has the best energy-saving performance, while sleep mode has the lowest. However, with different power domains turned off, the data loss and time cost for returning to normal mode are also different. According to the STM32F407 datasheet and user manual, standby mode can be regarded as 'power off' to some degree, which means that all data in the random access memory (RAM) and registers will be lost and can only be woken up by registered external interruptions. Stop mode will keep data in RAM and registers but will turn off the main clock generator; thus, the clock (as well as the peripheral clock) needs to be reconfigured after being woken up. We also measured the time taken to return to normal mode from sleep, stop, and standby modes with the help of external hardware, and the results are listed in Table 3.  
If the DVFS technology is used to reduce power consumption when the system is idle by reducing processor clock frequency, it will require two frequency transitions as well as the overhead. The total overhead of time and energy will be about 140 ms and 8.4316 mJ. Moreover, DVFS technology will not affect the power consumption of peripheral components even though they are idle. Unlike the cost of DVFS, the cost of entering and waking up from energy-saving mode is much smaller, and it is even ignorable. Not only the power consumption of the processor but also that of peripheral components will be reduced in power-saving modes. However, at the same time, we also noticed that the processor clock would be turned off after entering stop or standby mode, and it will be reset to use HSE as the clock source after waking up. To satisfy the needs of the computing performance, the system clock requires reinitialization. Even in this case, the processor clock frequency transition is required only once, which is half of DVFS.