## 2 Platform Architecture
### Particle Waveform Data FPGA Forward Inference Module
The essence of the forward inference calculation of the convolutional neural network is to perform a large number of multiplication and addition operations, as well as the intercept, shift, splice, and other operations of register arrays; thus, it is necessary to use the DSP module inside the FPGA to perform parallel calculations. At the same time, considering the large flux factors of the actual application scenarios of particle identification, the inference time must be reduced as much as possible. Thus, if the resources allow, we directly use the on-chip registers in the FPGA to store all kinds of parameters. Therefore, the FPGA on-chip registers are directly used as the storage of various kinds of parameters when the resources allow in order to maximize the reduction in the data access operation times and reduce the delay of forward inferences; all the data are quantized by means of a 16-bit fixed-point number--which effectively reduces the complexity of multiplication-addition operations on the basis of not generating data overflow--and the strategy of parallel computation to meet the requirements of the inference time of the actual application environment. Considering that the model of the convolutional neural network may change with the modification of the actual model, and the strategy of parallel computation will also change with the modification of the model and the resource adjustment of the hardware platform,the modular design of the entire structure should be as flexible as possible to adapt to various changes. The kernel architecture of the convolutional layer is shown in Figure 5.  
The computation of the convolutional layer consists of four main levels, which are the computation of the elements inside the convolutional kernel, the computation of the convolutional kernel corresponding to the different input channels of a single filter, the computation of the sliding of a single filter on one-dimensional data, and the computation of multiple filters. Based on the current architectural design of convolutional layer computation, the elements within the convolutional kernel, the one-dimensional data sliding computation, and the computation of multiple output channels can be fully or partially parallelized, whereas the convolutional kernel computation of the input channels is designed to be serial due to the need to accumulate computation between multiple channels. Convolutional computation is a big user of chip resources and time resources, and the quantitative analysis of computing resources and an understanding of time delay are key steps in building a platform. Since the convolutional operation is mainly a multiplication-addition operation and the parallelism requirement is high, the special DSP module within the FPGA is used in the construction of the operation unit (PE unit), and the relationship between the actual construction process of the DSP module and the degree of parallelism is shown in Equation (5):  
\[\text{DSPNum}= k\times n\times m \tag{5}\]  
where DSPNum is the number of DSP modules of the FPGA that need to be consumed, \(k\) represents the degree of parallelism within the convolutional kernel, \(n\) represents the  
Figure 5: Block diagram of the data flow of the convolutional layer. degree of the sliding window's parallelism, and \(m\) represents the degree of the output channel's parallelism. The extrapolation time is related to how serially the architecture is running, i.e., how many operations are required for each layer to complete the construction of the output data.