# A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS
## 1 Introduction  
Recently, high-data-rate communication systems with increasing bandwidth requirements have drawn much attention. The millimeter-wave frequency band with rich spectrum resources is well-matched for massive data-driven communications, such as 5G, wireless high-definition video streaming, and future ultra-high-speed wireless communication. Millimeter-wave systems, in 28/39 GHz band for 5G new radio standard and in 60 GHz bands for IEEE802.11 ad/WiGig standard, have been developed for the increasing data-rate demands [1; 2; 3; 4; 5; 6].  
In Q-band, IEEE 802.11 aj (45 GHz) standard was approved in 2018 as a IEEE802.11 family member for high-data-rate wireless personal area networks and portable devices. These devices define 10 channels with a channel bandwidth of 540 MHz or 5 channels of 1080 MHz, as shown in Figure 1, with up to 15 Gb/s data rate [7; 8]. Although there are many reported synthesizer studies [9; 10; 11; 12; 13; 14; 15], very few synthesizer studies have been reported for the IEEE802.11 aj (45 GHz) standard [16]. For the millimeter-wave transceiver design, super-heterodyne system is preferred for high-dynamic range, alleviated LO leakage, and DC-offset issues, where two or more LO frequencies (denoted as LO1, LO2, etc.) are needed in the system. To simplify the synthesizer design, sliding-IF transceiver topology is often used [2; 5; 6], where the LO1 frequency is harmonic-related to the LO2, so one single-loop frequency synthesizer can support the transceiver application, as shown in Figure 2a. However, in sliding-IF topology, both LO1 and LO2 are variable for selecting different channels, which add complexity in wide-band IF transceiver and filter design. On the contrary, for super-heterodyne topology with dual-loop LO synthesizer, LO1 frequency can be fixedfor high-performance IF transceiver and band-pass filter design, while LO2 frequency is variable for channel selection, as shown in Figure 2b. Moreover, since LO1 and LO2 are generated by independent phase locked loops synchronized with a reference source, the overall phase noise performance can be improved, with the price of more chip area and DC power consumption.  
In this article, the design of the dual-loop dual-output frequency synthesizer for the IEEE802.11 aj (45 GHz) standard is presented. Thanks to the dual-loop topology, the frequency of Loop1 is fixed for easy design of high-performance IF transceiver and filter, and the frequency of Loop2 varies for the channel selection. In addition, the power hungry high-speed prescaler or multi-modulus-divider (MMD) is replaced with a mixer in Loop2, thus in-band phase noise degeneration can be avoided, which helps to improve the integrated phase noise for high-data-rate communications. The dual-loop dual-output synthesizer is fabricated in 0.13 \(\upmu\)m SiGe BiCMOS process. Measured results have shown the phase noise of \(-\)79.3 dBc/Hz@10 kHz and \(-\)129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and \(-\)76.6 dBc/Hz@10 kHz and \(-\)117.2 dBc/Hz@10 MHz at 32.535 GHz for  
Figure 1: Channel allocation for IEEE802.11 aj (45 GHz) standard.  
Figure 2: Schematic of the super-heterodyne receiver with (**a**) the sliding-IF LO synthesizer; (**b**) the proposed dual-loop LO synthesizer.  
Output2. Low-level reference spurs and spurious tones are also obtained at the outputs. In Section 2, the proposed dual-loop dual-output frequency synthesizer is designed and implemented. In Section 3, measured results of the dual-output synthesizer are provided in detail, and the conclusion is presented in Section 4.