## 2 Hybrid Real-Time Scheduler in the MIROS
### Performance Evaluation
#### 2.6.3 Execution Efficiency of the Different OS Schedulers  
The execution efficiency of the scheduling primitives can be evaluated by the clock cycles, and the evaluation results are shown in Tables 2 and 3.  
\begin{table}
\begin{tabular}{|c|c|c|c|c|c|c|} \hline
**WSN** & **Scheduling** & \multicolumn{2}{c|}{**Data Memory Consumption**} & \multicolumn{1}{c|}{\multirow{2}{*}{**Scenario**}} & \multicolumn{1}{c|}{\multirow{2}{*}{**Data Size (bytes)**}} \\ \cline{3-4}
**OSes** & **Mechanism** & & & & & **Event-Driven** & **Multi-Threading** \\ \hline \multirow{3}{*}{TinyOS} & Event-driven & 8 + 1*L\({}_{\text{SQ}}\) & N/A & & 23 & / \\ \cline{2-6}  & TOST Thread & N/A & \begin{tabular}{c} 22 + 16*N\({}_{\text{TCB}}\) + \\ Size(STK) \\ \end{tabular} & & & & \\ \cline{2-6}  & \multirow{2}{*}{\begin{tabular}{c} Event-driven \\ 8*N\({}_{\text{TCB}}\) \\ \end{tabular} } & 10 + 6*L\({}_{\text{SQ}}\) + & N/A & & & \\ \cline{2-6}  & & 8*N\({}_{\text{TCB}}\) + & N/A & & & \\ \cline{2-6}  & Multithreading & N/A & \begin{tabular}{c} 8 + 8*N\({}_{\text{TCB}}\) + \\ Size(STK) \\ \end{tabular} & & & & \\ \hline SOS & Event-driven & \begin{tabular}{c} 62 + 18*L\({}_{\text{SQ}}\) + \\ 24*N\({}_{\text{TCB}}\) \\ \end{tabular} & N/A & & & \\ \cline{2-6}  & N/A & \
\begin{tabular}{c} 40 + 22*N\({}_{\text{TCB}}\) + \\ Size(STK2) \\ \end{tabular} & & & & \\ \hline \multirow{3}{*}{MIROS} & Event-driven & 4 + 4*N\({}_{\text{TCB}}\) & N/A & & & \\ \cline{2-6}  & Multithreading & N/A &
\begin{tabular}{c} 4 + 8*N\({}_{\text{TCB}}\) + \\ Size(STK) \\ \end{tabular} & & & & \\ \cline{2-6}  & \multicolumn{1}{c|}{} & & & & \\ \cline{2-6}  & \multicolumn{1}{c|}{} & & & & \\ \end{tabular}
\end{table}
Table 1: Date memory cost of the event-driven and multithreaded schedulers in different OSes.  
\begin{table}
\begin{tabular}{|c|c|c|c|c|c|c|} \hline
**Event-Driven** & \multicolumn{4}{c|}{**Clock Cycles (AVR ATmega1281)**} & \multicolumn{1}{c|}{**Clock Cycles of**} \\ \cline{2-6}
**Scheduling** & **TinyOS** & **Contiki** & **SOS** & **MIROS** & **mantisOS** & **One-Byte** \\
**Primitives** & **ToySM Thread** & **Multithreading** & & & & \\ \hline Thread switch & 77 & 93 & & 102 & 99 \\ \hline Selection of next thread & 26 (RR scheduling) & 22 (RR scheduling) & N/A & \
\begin{tabular}{c} 5 + 9n (RMS scheduling) \\ scheduling in multi- \\ level queues) \\ \end{tabular} &
\begin{tabular}{c} 72 (RR scheduling in multi- \\ level queues) \\ \end{tabular} \\ \hline \end{tabular}
\end{table}
Table 2: Clock cycles of the event posting and task dispatching primitives in different schedulers.  
\begin{table}
\begin{tabular}{|c|c|c|c|c|c|c|} \hline
**Event-Driven** & \multicolumn{4}{c|}{**Clock Cycles (AVR ATmega1281)**} & \multicolumn{1}{c|}{**Clock Cycles of**} \\ \cline{2-6}
**Scheduling** & **TinyOS** & **Contiki** & **SOS** & **MIROS** & **mantisOS** & **One-Byte** \\  
In MIROS, the simple flag-polling mechanism is used for event scheduling, thus the clock cycles of the event posting and the task dispatching are small. As for the thread scheduling, the static priority-based RMS algorithm is implemented. The clock cycles to select the next thread is (5 + 9n), where n represents the searching steps in the thread queue. In the case that n is 3 (thread number is small in MIROS, Section 2.4), the clock cycle will be 32.