# A Review of DSP-Based Enabling Technologies for Cloud Access Networks
## 3 CAN Network Elements
### Reconfigurable Optical Transceivers
#### 3.1.2 DSP Architecture and Real-Time Experimental Demonstrations  
Figure 4 illustrates the DSP architectures of the demonstrated FPGA-based ROTs incorporating on-line reconfigurable digital orthogonal filters. For the demonstration, a two channel real-time transmitter and the single channel real-time receiver are employed. In the transmitter FPGA, two separate digital OFDM modulators incorporating adaptive bit and power loading generate two independent OFDM-modulated digital signals. The OFDM signal generation is described in detail in [17], and employs the OFDM parameters specified in Table 1, thus each individual OFDM symbol consists of 40 \(\times\) 8-bit parallel samples at a symbol rate of 25 M symbols/s. The OFDM modulator sub-systems thus utilise a 25 MHz clock domain within the FPGA, as shown in Figure 4.  
Figure 4: Two Channel reconfigurable optical transceiver digital signal processing (DSP) architecture. JTAG, Joint Test Action Group; FIR, finite impulse response; FPGA, field programmable gate array. To significantly reduce the logic resource usage of the digital filters, each OFDM symbol is converted to eight parallel samples at an increased clock speed of 125 MHz, as shown in Figure 4. A clock domain of 125 MHz is therefore used for the digital filters. To achieve the channel multiplexing, as described in Section 2.2, each OFDM channel is first up-sampled by a factor of 2, this doubles the samples per symbol to 80 and increases the sample rate to 2 GS/s. The up-sampled channel is then passed through a bank of parallel 32-tap FIR digital shaping filters, with signed 8-bit filter coefficients. As the FPGA can only operate at 100 s MHz, parallel FIR filters are necessary to achieve the required 2 GS/s throughput. Thus 16 parallel samples at 125 MHz achieves a sample throughput of 2 GS/s. For the two-channel system implemented here, in the up-sampling function, zero-valued samples are not physically inserted before input to the FIR filters, this is because the FIR filters operate on parallel samples so it is not necessary to include multipliers for tap coefficients corresponding to the zero-valued samples. Moreover, a feature which is unique to the two channel system, due to the filter characteristics, is that every second output sample will be zero-valued, thus due to the parallel filter architecture only eight parallel FIRs are physically required to produce the 16 parallel output samples as eight output samples are fixed at zero-value. Each digitally filtered channel output is quantised to eight bits and then the channels are directly summed. To comply with the DAC interface implementation the 16 parallel samples are converted to 40 parallel samples, at a clock rate of 50 MHz, as shown in Figure 4. The multiplexed channels are, subsequently, inputted into the DAC interface block, which interfaces to an 8-bit, 2 GS/s DAC. To recover a desired channel in the receiver FPGA, the 40 parallel samples clocked at 50 MHz, output from the ADC interface, are converted to 16 parallel samples clocked at 125 MHz before being input to the online reconfigurable digital matching filter. The 16 parallel samples output from the matching filter are subsequently down-sampled by a factor of 2 by removing every second sample. This produces eight parallel samples, which are converted to 40 parallel samples to match the interface of the OFDM decoder function. Thus, the receiver employs bus width conversions and clock domains similar to those used in the transmitter, with the signal now flowing in the opposite direction. To recover a specific channel, the coefficients of the matching filter are dynamically reconfigured to set its impulse response to correspond to the required matching filter. The complete real-time ROT experimental system setup is shown in Figure 5 and the key system parameters are listed in Table 1. In the transmitter, the digital samples are converted via a DAC to an analogue electrical signal with a bandwidth of 1 GHz.