## 3 Proposed Crypto Processor Design
### Arithmetic Unit  
To perform modular finite field operations, an arithmetic unit is required to perform essential functions such as addition, multiplication, square, reduction, and inversion. The blue color portion in Figure 1 shows the arithmetic unit, which comprises three multiplexers (M1, M2, and M3) for routing purposes, an adder, and a polynomial multiplier unit. The routing multiplexers select appropriate operands for the arithmetic operators (adder and multiplier) and data memory. The M1 and M2 multiplexers select operands for the adder and multiplier units. The M3 multiplexer is leveraged to choose the outputs of these modular operators to be written back on the data memory. The control unit generates the related control signals for operating M1, M2, and M3 multiplexers. Below, we describe the arithmetic operators required to implement ECC's PM operation. Implementing a modular adder over the \(GF(2^{m})\) field is straightforward, requiring only bitwise exclusive (OR) gates, as shown in Figure 2. For example, adding two 233 bit input operands \(a\) and \(b\), two-input 233 exclusives (OR) gates are needed [12; 13; 18]. Implementation of an adder is a combinational circuit; therefore, one polynomial addition over binary field results in one clock cycle. Let us discuss polynomial multiplication approaches. According to the study in [30], four commonly utilized methods are bit-serial, digit-serial, bit-parallel, and digit-parallel multiplication. Another resource, [31], presents an open-source tool that can generate Verilog HDL implementations of different modular multipliers, such as schoolbook, Booth, 2-way Karatsuba, 3-way Toom-Cook, and 4-way Toom-Cook. These multiplication methods have their unique benefits and weaknesses. For example, bit and digit-serial methods help implement area and power-optimized circuits [15; 32]. Conversely, bit-parallel and digit-parallel multipliers for high-performance implementations are more suitable [12; 13; 30]. It is important to note that the computational cost of these methods can vary. For instance, for two \(m\) bit sizes of polynomial operands as input, the bit-serial multipliers require \(m^{2}\) cycles; on the other hand, the digit-serial approach requires \(\frac{m}{n}\) cycles, where \(m\) is the operand length and \(n\) is the digit size. The computational cost of digit and bit-parallel approaches is one clock cycle with additional area and power  
Figure 1: Proposed crypto processor architecture for PM computation of binary ECC field over \(GF(2^{233})\): LD/LK shows load data and key, din presents data in, start is a start signal to ensure computations begin, addr/data determines addr/data signals to/from memory, dout shows processor data as an output, done means computation has been finished. overheads. There is always a tradeoff between design parameters (such as area, power, and performance). We recommend [30; 31] for a more comprehensive comparison of different multiplication architectures. Our design premise is an area-efficient realization of PM implementation of ECC; hence, we have implemented a bit-serial multiplication method, as presented in Figure 3. It comprises two multiplexers, a one bit shift towards the right (\(\ll\)), an exclusive (OR) gate (XOR), and a 233 bit accumulator register (ACC). The multiplexers help to generate the partial products depending on the value of \(a_{i}\) and \(b\), where \(a_{i}\) is the \(i\)th value of the operand \(a\) and \(b\) is the second operand. The symbol \(\ll\) in Figure 3 shows a one bit shift right. The exclusive (OR) or XOR performs the corresponding operation on shifted and accumulated results. The ACC accumulates the results to keep the final result. The multiplier takes \(m\) bit \(a\) and \(b\) as inputs, resulting in \(2\times(m-1)\) bits out as output. Similarly, we used the same multiplier design by providing identical inputs to perform the modular square instructions of Algorithm 1.