## 2 Principles of Inter-Satellite Laser Communication for Space-Based Gravitational Wave Detection
First, in the phase detector, the input beat note signal is compared in phase with the orthogonal signal output by the NCO, generating a phase error signal. The phase error signal is then passed through the PI controller to generate a control signal that adjusts the phase of the NCO. Next, the NCO generates the phase-adjusted orthogonal signal, which is once again phase-compared with the input beat note signal in the phase detector. This process repeats, and when the DPLL achieves loop locking, it enters a stable operating state. At this point, the signal output by the phase detector is the demodulated communication ranging code. (2) DLL  
For the DLL, it consists of an acquisition branch, a tracking branch, a PRN code phase regulator and a local PRN code generator. In the local PRN code generator, three PRN code signals are generated from the same PRN code sequence as the transmitter: the punctual code, the early code and the late code. The early code is shifted half a PRN chip period ahead of the punctual code, while the late code is shifted half a PRN chip period behind. The structural schematic of the DLL is shown in Figure 4.  
Upon receiving the demodulated communication ranging code signal from the DPLL, the DLL begins by performing acquisition. In the acquisition state, the input signal is first multiplied by the punctual code, followed by processing through the first-level integrator and dump filter (IAD1). In IAD1, integration is achieved by summing over multiple samples. Once the number of summations equals the number of data code samples, the integration resets. After IAD1 processing, the absolute value of the resulting signal is taken and passed to the second-level integrator and dump filter (IAD2) for further processing. Similar to IAD1, IAD2 performs integration by summing samples, but it resets after the number of summations reaches the total number of samples in one full code cycle. The output from IAD2 provides the correlation value between the punctual code and the input  
Figure 4: Structural schematic of the DLL. Figure 3: Structural schematic of the DPLL. signal for each full code cycle, which serves as the control signal for the acquisition branch. When the correlation value from the acquisition branch is below the predefined threshold, the PRN code phase regulator will regulate the phases of the three PRN codes with one-chip-period precision. If the correlation value remains above the threshold for a sustained period, the acquisition is considered complete. At this point, the phase difference between the punctual code and the input signal is confined to within one PRN chip period. The acquisition process of the DLL can be seen in the acquisition state section of Figure 5.  
Figure 5: Flowchart of the DLL operation. Upon acquisition completion, the DLL transitions to the tracking state. In tracking, the input signal is multiplied by both the early and late codes. IAD1 and IAD2 process these multiplications to obtain the correlation values for each full code cycle. The difference between these correlation values controls the tracking branch. When this difference deviates from zero, the PRN code phase regulator refines the phases of the three PRN codes by one sample period. Once the difference remains zero or oscillates within a specific range, tracking is considered complete and the punctual code aligns with the input signal phase. The tracking process of the DLL can be seen in the tracking state section of Figure 5.  
Once tracking is completed, the output signal from the acquisition branch's IAD1 is processed to retrieve the demodulated data code after accumulating a number of times equal to the sampling points in a data code. Thereby, the the demodulated data code is obtained.