# Barrel Shifter Physical Unclonable Function Based Encryption
## 6 Post-Layout Simulation Results
### Intra-Chip Reproducibility  
The robustness of a single PUF is predicated on the consistency of its response to a challenge. The response should be the same regardless of the environment. Tests are performed subjecting BS-PUF to: (1) temperature variation and (2) voltage supply variation. The frequency of response bit flips is quantified.  
Figure 10: The path delay capture unit tests for and stores the path delay. The edge detector detects an \(output\) transition; \(S\) equal to \(output\) will not be detected. Consequently, the transmission path receives \(S\) and \(\overline{S}\) successively; a transition at \(output\) is guaranteed.  
Bit flip rate is the frequency of bit changes from \(0\to 1\) or \(1\to 0\). It is computed relative to a baseline response. Gathering responses at common room temperature (25 \({}^{\circ}\)C) and supply voltage (5 V) establishes this baseline. The percentage of path delays where a bit flips is the bit flip rate. For example, the LSB flipping in 64/256 paths represents a 25% bit flip rate.  
Path delays for all 256 bit paths are gathered with Monte Carlo sampling under different temperatures and supply voltages. Temperature is varied from 0 \({}^{\circ}\)C to 50 \({}^{\circ}\)C and supply voltage from 4.64 V to 5 V. The corresponding test results are shown in Figures 11 and 12. Flip rates for the 2 nd LSB are smaller than 12% and 18% under temperature and voltage variation, respectively. On the contrary, the flip rate of the LSB is significantly higher. The 2 nd LSB provides better reproducibility. By taking 2 nd LSB, the stability performance of BS-PUF is similar to traditional RO-PUFs [24].  
Usually, an error caused by PUF reproducibility can be resolved by error correction code (ECC) [25], ECC implementations usually need 3k-10k raw PUF response bits (with bit error rate of 15%) to a 128-bit reproducible PUF response with a targeted key error rate less than \(10^{6}\)[26]. This implies that we need to provide 23-80 raw bits to generate one single reproducible bit. The instability of BS-PUF responses (18%) can also be compensated by generating a sufficient number of redundant bits. For instance, an error detection capability based on the parity bits, as deployed in communication protocols, could be incorporated into the encryption protocol. For a 128-bit message, nine additional parity bits--one for each byte--can be computed. The actual message block to be encrypted is the concatenation of the 128-bit message with nine parity bits, resulting in a 137-bit message block. After the proposed encryption protocol delivers a message to the receiver, it also computes the parity bits on the 128-bit message part. These computed parity bits are then compared against the received parity bits. If there is an error, the receiver can ask the sender to resend the message. The error correction overhead can be reduced by developing some stable keyed-PUF in the future.  
A higher order bit could be selected. It would have comparatively better flip rates, but reduced variability. Many feasible techniques exist to compensate for temperature and voltage variation [27; 28]. These techniques would be helpful at the flip rates expressed by the 2 nd LSB. Thus, the advantage of choosing a higher order bit is minimal. All of the following evaluations are performed on the 2 nd LSB only.  
Figure 11: Percentage of bit flips under temperature variation. Flip rates demonstrate signal-to-noise ratio (SNR) under different temperatures. Flip rates of LSB are shown in dark grey. Flip rates of 2 nd LSB are shown in grey. The flip rate of LSB is much higher than 2 nd LSB.  
Figure 12: Percentage of bit flips under voltage variation. Flip rates of LSB are shown in dark grey. Flip rates of 2 nd LSB are shown in grey.