## 4 Emerging Lightweight Security Approaches
### Symmetric Encryption--Lightweight AES Approaches
#### 4.1.2 Low-Power AES Data Encryption Architecture (LPADA)  
Used in LoRaWAN, the Low-Power AES Data Encryption Architecture (LPADA) [77] is also an AES encryption hardware solution combined with custom CPU techniques to reduce power consumption and ensure a ten-year battery life for LoRaWAN devices. LPADA reduces the power required to perform AES transformations at LoRaWAN motes, using the following three methods to conserve power:  
* Low-power S-Box: an ultra-low-power Content Addressable Memory (CAM) stores the S-Box as a look-up table in memory, the contents of which are generated before  
Figure 7: (**A**) Ten-round AES transformation schedule for 128-bit keys; (**B**) conventional AES masked implementation; (**C**) masked AES implementation based on the algorithm in [80]. a data substitution begins. To improve the speed and reduce power in the SubBytes transformation, two approaches are adopted together in LPADA. The first is that the CAM uses parallel searching techniques to reduce delays in the SubBytes operation. Second, a low-power CAM architecture is used to discharge entries in the look-up table that do not match the search data. Power management techniques also ensure that the S-Box portion of the memory remains powered at all times to avoid losing its contents. * Power-gating technique: to reduce power consumption, this technique means that the power supply to certain logic circuits in the FPGA, which are built using transistors, is turned off. This power-gating technique is done in LPADA using P-type metal oxide semiconductor transistors (PMOS), which can switch off power to all components of the AES circuit when in sleep mode. The exception for this is the S-Box, for which power is maintained. * Dynamic power management (DPM) method: consists of three operation modes that control supply voltages and clock frequencies based on the device's state. These modes include active, idle, and sleep modes. The active mode consists of all components receiving power and a clock when the device is performing an action request, such as an encryption operation. In idle mode, which is controlled by a five-minute timer, all components receive power while their clock rates are gated to reduce dynamic power consumption. This means that the clock rates are reduced to a lower value or set to zero. If an action request is not made within the five-minute timer interval, the device will enter sleep mode when power to all circuits is switched off, except for the S-Box. These three power reduction methods employed by the LPADA architecture work together to extend the battery life of LoRa motes, while executing the AES algorithm. These methods are mostly about the AES transformations and hardware improvements to conserve power and can be reproduced for not only LoRA devices but for other communication protocols that use AES. Another contribution of LPADA is to LoRa's key management scheme, as it tries to improve the way in which encryption keys are updated in LoRaWAN networks when a device rejoins the network. LoRa's key management protocol defines how LoRa motes obtain the AppSKey and NwkSKey, used in Equations (4) and (5). At manufacturing, three values are programmed in the mote: a 128-bit key called AppKey and two global device identifiers, or extended unique identifiers (EUI), called AppEUI and DevEUI [87]. When a new device joins the LoRaWAN network, the AppKey and DevEUI are used to create an application session key (AppSKey) and a network session key (NwkSKey). They exchange messages with a Join Server, which is an additional server in LoRa's networks to the Network Server and Application Server. The Join Server also knows the AppKey, DevEUI, and AppEUI. When the device sends a Join request to the Join Server, the DevEUI together with an application identifier (AppEUI) and a 128-bit AES application key (AppKey) are required to establish a secure connection via over-the-air activation (OTAA).