## 4 Fabrication Process  
The hybrid MEMS resonator microfabrication process is a complex endeavor that integrates both capacitive and piezoelectric transducers to implement a lateral-extensional mode resonator with potentials for superior RF performance characteristics. Figure 3 depicts the fabrication process of the capacitive and piezoelectric hybrid resonator. A silicon-on insulator (SOI) wafer with a 500 \(\upmu\)m Si substrate layer, a 2 \(\upmu\)m buried oxide layer, and a 10 \(\upmu\)m silicon device layer has been used as the starting substrate, as seen in Figure 3a. Each step in the process flow is crucial to ensure the optimal performance and reliability of fabricated hybrid resonators. The process begins with the fabrication of a capacitively transduced resonator, where a silicon substrate is coated with a five \(\upmu\)m-thick layer of AZ12 xt photoresist that has been selected due to its resistance to dry-etching processes [26,33]. This is followed by meticulous etching using a modified high-aspect ratio deep-reactive ion-etching (HAR DRIE) Bosch recipe to define the microstructural framework that is necessary for the capacitive elements of the resonator. After the etching, a critical 80-90 nm-thick gap spacing layer of Al\({}_{2}\)O\({}_{3}\) is deposited through atomic layer deposition (ALD), which serves to define the precise capacitive air gaps essential for the capacitive resonator's functionality, such as the electromechanical coupling coefficient. To enhance the structural integrity and performance, the capacitive electrodes are anchored directly to the SOI silicon substrate layer rather than just being positioned atop the gap spacing layer. This modification is achieved by selectively etching the ALD gap spacing layer from the sidewalls of the capacitive electrodes, using a combination of special masking  
Figure 1: Schematic illustration of electrode and anchor design configurations for a hybrid MEMS resonator. This hybrid resonator integrates capacitive and piezoelectric transducers, which are designed to enhance performance metrics such as quality factor, insertion loss, and motional impedance, and so on. Figure 2: COMSOL® finite element eigenfrequency simulation depicting the first four lateral extensional contour modes of a disk-shaped resonator: (**a**) 1 st lateral extensional mode, (**b**) 2 nd lateral extensional mode, (**c**) 3 rd lateral extensional mode, (**d**) 4 th lateral extensional mode. and a 6:1 buffer oxide etch (BOE). This step ensures the surrounding capacitive electrodes are attached to the SOI silicon substrate layer, preventing delamination during subsequent fabrication processes. Following the structural modifications, a seed layer made of a chrome adhesion layer and a copper layer is deposited by sputtering for the electroplating of capacitive electrodes. Nickel electroplating is then employed to form the thick capacitive electrodes that enclose the resonator body. This involves a detailed lithography step to define a mold for plating over selective areas within a thick layer of photoresist, ensuring precise deposition of nickel to form patterned surrounding capacitive electrodes. The activation of the seed layer prior to electroplating is critical and involves treating the wafer in a solution of ammonium hydroxide to remove any oxide that could impede the plating  
Figure 3: (**a**) Top-view (3D) and (**b**) cross-sectional view (3D) diagrams of proposed hybrid resonator; (**c**–**f**) step-by-step illustration of the simplified fabrication process flow of a hybrid lateral extensional mode resonator with capacitive and piezoelectric transducers. The process begins with the preparation of a silicon-on-insulator (SOI) wafer and proceeds through steps such as photolithography, deep-reactive ion-etching (DRIE), atomic layer deposition (ALD) for gap spacing, and the deposition of a ZnO piezoelectric layer, which concludes with the final releasing step to suspend the resonator structure. process.