## 3 Proposed Multi-Modulus Multiplier Based on Radix-8 Booth Encoding
### Proposed Radix-8 Multi-Modulus Multiplier
 \tag{27}\]  
From Equation (27), \(C_{2}^{\prime}\) can be rewritten as:  
\[C2\prime=\sum\limits_{i=1}^{\lfloor n/3\rfloor}2^{3i}\cdot 1+\sum\limits_{i=0}^{ \lfloor n/3\rfloor}2^{3i+1}\cdot\overline{s_{i}}+\sum\limits_{i=0}^{\lfloor n /3\rfloor-1}2^{3i+2}s_{i} \tag{28}\]  
For \(C_{1}^{\prime}\) in Equation (27), the \(2^{3i}+1\) terms can be summed as:  
\[\sum\limits_{i=0}^{\lfloor n/3\rfloor}[(\underbrace{\overline{m3_{i}+m4_{i}}}_{ K1_{i}})\cdot 2^{3i+1}+\underbrace{s_{i}(m2_{i}+m4_{i})}_{K2_{i}}\cdot 2^{3i+1}] \tag{29}\]  
where \(K1_{i}\) and \(K2_{i}\) are defined as \((\overline{m3_{i}+m4_{i}})\) and \(s_{i}(m2_{i}+m4_{i})\), respectively. \(K1_{i}+K2_{i}\) can be written as:  
\[K1_{i}+K2_{i}=(K1_{i}\oplus K2_{i})2^{0}+(K1_{i}\bullet K2_{i})2^{1} \tag{30}\]  
where \"\(\oplus\)\" represents the logic Exclusive OR gate, and \"\(\bullet\)\" represents the logic AND gate. The \((2^{3i+1})\)th term of \(K1_{i}+K2_{i}\) is 0 when \((K1_{i}\), \(K2_{i})\) = (0, 0) or carry out when \((K1_{i}\), \(K2_{i})\) = (1, 1). Therefore, the \((2^{3i+1})\)th term can be rewritten as:  
Figure 11: (**a**) The Booth selector of the radix-8 Booth-encoding-based architecture [20]. (**b**) The Booth selector for \(n=6k+4\). (**c**) The Booth selector for \(n=6k\). \[\sum\limits_{i=0}^{\lfloor n/3\rfloor}\frac{(\overline{m3_{i}+m4_{i}})}{k1_{i}} \cdot 2^{3i+1}\oplus\underbrace{s_{i}(m2_{i}+m4_{i})}_{k2_{i}}\cdot 2^{3i+1} \tag{31}\]  
And by merging the (\(2^{3i+2}\))th term in Equation (27), it can be rewritten as:  
\[\sum\limits_{i=0}^{\lfloor n/3\rfloor-1}2^{3i+2}[((m3_{i}+m4_{i})\cdot s_{i}) \oplus(K1_{i}\cdot K2_{i})] \tag{32}\]  
The exclusive OR logic symbol is used in Equation (32) because \((m3_{i}+m4_{i})\) and \(K1_{i}\) do not appear simultaneously. In Equation (32), when \(n=3k+2\) bits for \(k=1\), \(2\), \(3\ldots\), the sum of \(K1_{i}\) and \(K2_{i}\) at the highest bit position in \(2^{3i+1}\) carry out to \(2^{3i+2}\) when \((K1_{i},\,K2_{i})=(1,\,1)\). It cannot also be represented for \(n\) bits. Therefore, for \(i=\lfloor n/3\rfloor\), it should appear at the upper bound of \(i=\lfloor n/3\rfloor\). Taking \(n=8\) as an example, the upper bound of \(\lfloor n/3\rfloor\) is \(2\). For the (\(2^{7}\))th bit, the sum of \(K1_{i}\) and \(K2_{i}\) probably carries out to \(2^{8}\). Therefore, merging the (\(2^{3i+1}\))th term of \(C_{2^{\prime}}\) in Equation (28) for \(C_{1^{\prime}}\) at \(i=\lfloor n/3\rfloor\) yields:  
\[\sum\limits_{i=\lfloor n/3\rfloor}^{\lfloor n/3\rfloor}2^{3i+1}\big{(}\overline {m3_{i}+m4_{i}}\big{)}+((m2_{i}+m4_{i})\cdot s_{i})\big{]} \tag{33}\]  
and for \(C_{2^{\prime}}\) at \(i=\lfloor n/3\rfloor\), it yields:  
\[\sum\limits_{i=\lfloor n/3\rfloor}^{\lfloor n/3\rfloor}2^{3i+1}[\overline{s_{ i}}\oplus(K1_{i}\cdot K2_{i})] \tag{34}\]  
Here, the weighted representation is adopted to replace the original diminish-\(1\) representation. Therefore, the extra circuit for adding \(2\) should be processed in the compensation circuit for the modulo (\(2^{n}+1\)) multiplier. Merging the circuit for adding \(2\) and \(C_{2^{\prime}}\) in Equation (28), which makes \(i=0\), the modified value is obtained as follows:  
\[ \begin{array}{ll}\sum\limits_{i=0}^{0}(2^{3i+1}\cdot\overline{s_{i}})+2+ \sum\limits_{i=0}^{0}2^{3i+2}s_{i}&=\sum\limits_{i=0}^{0}2^{3i+1}(1+\overline {s_{i}})+\sum\limits_{i=0}^{0}2^{3i+2}s_{i}\\ &=\sum\limits_{i=0}^{0}2^{3i+1}\cdot(\overline{s_{i}}\oplus 1)+\sum\limits_{i=0}^{0}2 ^{3i+2}(s_{i}+1)\end{array}  \tag{35}\]  
For the modulo (\(2^{n}\)) multiplier, the compensation value is described as follows [20]:  
\[C_{1}=\sum\limits_{i=0}^{\lfloor n/3\rfloor}2^{3i}\cdot s_{i} \tag{36}\]  
According to the derivation in this subsection, for the modulo (\(2^{n}+1\)) multiplier, the final compensation of \(C_{1}\) (replacing \(C_{1}\)) can be obtained as follows:  
\[