# Improvement of Power Converters Performance by an Efficient Use of Dead Time Compensation Technique
## 3 Proposed Dead Time Compensation Technique
### Modeling of the Proposed Dead Time Compensation  
The block diagram for 3-phase idealized PWM inverter is illustrated in Figure 6. The DTC model is schematically presented in Figure 7. The model employs an ideal relay possessing two specifications: memory-less, and nonlinearity. The voltage distortion \(\varepsilon\) depends on \(T_{d}\) the delay time and carrier signal \(V_{c}(t)\) the slope of the triangular waveform. Take the required signal \(V_{i}(t)\) is gradually varying as compared to the high-frequency carrier signal \(C\). The ratio \(\varepsilon/T_{d}\) is equal to \(2V_{c}/\left(\frac{T_{c}}{2}\right)\) the down-slope, the triangular carrier signal \(V_{c}(t)\) and therefore we have \(\varepsilon=2V_{c}T_{d}/\left(\frac{T_{c}}{2}\right)=4f_{c}V_{c}T_{d}\). Where \(\varepsilon\) represents as voltage distortion, \(T_{d}\) is a time delay and \(f_{c}\) represents the frequency of the carrier signal. Figure 5: Illustration of voltage waveforms and gate signals [21]. The desired results can be obtained by setting the deviation '\(\varepsilon\)' to 0 or dead time '\(T_{d}\)' to 0. Since the inherent objective is to compensate for the dead time, the following derivation further explores the ideal PWM inverter [27]. \[T_{err}=T_{off}-T_{on}-T_{d}+2T_{com} \tag{1}\]  
where '\(T_{com}\)' indicates the compensation time when '\(i_{a}<0\)'. For phase A:  
\[T_{err,a}=Sign(i_{a})T_{ma} \tag{2}\]  
where  
\[T_{ma}=T_{off}-T_{on}-T_{d}+2T_{com} \tag{3}\]  
\[\text{Sign}(i_{a})=\left\{ \begin{array}{ll}1&(i_{a}>0)\\ 1&(i_{a}<0)\end{array} \right. \tag{4}\]  
When voltage \(U_{a}\) is positive for phase A, the switching cycle time duration is \(T_{a}\), and for \(S_{1}\), it is \(T_{d}^{*}\). For negative \(U_{a}\), the switching cycle time duration is \(T_{d}\) for phase A, and for \(S_{4}\) it is \(T_{d}^{*}\). Figure 6: Block diagram for 3-phase idealized pulse width modulation (PWM) inverter. Figure 7: Proposed model for the (DTC) method. Correspondingly the relation between effective time \((T_{a})\) and commanded time \((T_{a}^{*})\) comes out to be [21]:  
\[T_{a}=T_{a}^{*}+Sign(i_{a})T_{ma} \tag{5}\]  
Similarly, for Phase B and C the same quantities are given as:  
\[T_{b}=T_{b}^{*}+Sign(i_{b})T_{mb} \tag{6}\]  
\[T_{c}=T_{c}^{*}+Sign(i_{c})T_{mc} \tag{7}\]  
where IGBTs \(S_{3}\) and \(S_{1}\) remain turned on and off respectively for (1) to (7). However, at the neutral point when fundamental voltage is balanced:  
\[V_{dc1}=V_{dc2}=\frac{V_{dc2}}{2}\]  
when \(i_{a}>0\):  
\[V_{ao}=\frac{V_{dc}}{2}-2V_{\alpha c}\ (\textit{when}\ S_{a}=1) \tag{8}\]  
\[V_{ao}=-V_{d}-V_{\alpha c}\ (\textit{when}\ S_{a}=0) \tag{9}\]  
\[V_{ao}=-\frac{V_{dc}}{2}+2V_{\alpha c}\ (\textit{when}\ S_{a}=-1) \tag{10}\]  
when \(i_{a}<0\);  
\[V_{ao}=\frac{V_{dc}}{2}+2V_{d}\ (\textit{when}\ S_{a}=1) \tag{11}\]  
Figure 7:0  
Figure 7:1  
Supposing no change in the direction of current, (8)-(13) gives:  
Figure 7:2  
When voltage drop increases with respect to current:  
Figure 7:3  
Figure 7:4  
Combining (15) and (16) with (14) gives:  
Figure 7:5  
As per volt-second balance theorem:  
Figure 7:6  
Figure 7:7  
Now for phase \(b\) and \(c\):  
Figure 7:8Figure 7:9  
Balanced load for three-phase loads is indicated as:  
\[T_{a}=T_{a}^{*}+Sign(i_{a})T_{ma} \tag{5}\]0 \[T_{a}=T_{a}^{*}+Sign(i_{a})T_{ma} \tag{5}\]1 (23) \[\left\{ \begin{array}{l}V_{a}=V_{ao}+V_{o}\\ V_{b}=V_{bo}+V_{o}\\ V_{c}=V_{co}+V_{o}\end{array} \right. \tag{24}\]  
Hence, the schematic illustration of the PWM inverter shown in Figure 3 is thus transformed into the final DTC model schematically represented in Figure 8.  
Subsequently, the control block of the upper section (\(-\left(\frac{\varepsilon}{2}\right)sign(i_{a})\)) is canceled out with a feedback block \((g(i_{a})=\left(\frac{\varepsilon}{2}\right)sign(i_{a})a)\). The Feed-forward \(f(\varepsilon)\) method is employed for dealing with hysteresis. The hysteresis compensation block as given in Figure 7 is utilized.