# Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions
## 4 Results
Due to the multitude of potential combinations, simulated annealing based solutions either take significantly more time to finish (for 8 \(\times\) 8 array: 2263.7 s = 37.7 min compared  
\begin{table}
\begin{tabular}{c c c c c c c c c c c c c c} \hline \hline \multirow{2}{*}{**Array**} & \multicolumn{3}{c}{**Proposed Approach**} & \multicolumn{3}{c}{**Hybrid**} & \multicolumn{3}{c}{**Simulated Annealing**} & \multicolumn{3}{c}{**Reference**} \\ \cline{2-13}  & \multicolumn{3}{c}{**Initial**} & \multicolumn{3}{c}{**Optimized**} & \multicolumn{3}{c}{**A**} & \multicolumn{3}{c}{**B**} & \multicolumn{3}{c}{**C**} & \multicolumn{3}{c}{**Random**} \\  & \multicolumn{3}{c}{**Floorplan**} & \multicolumn{3}{c}{**Floorplan**} & \multicolumn{3}{c}{**Steps/dT = 30**} & \multicolumn{3}{c}{**Steps/dT = 100**} & \multicolumn{3}{c}{**Steps/dT = 5 xy**} & \\ \hline
**X** & **Y** & **F\({}_{\textbf{obj}}\)** & **t [ms]** & **F\({}_{\textbf{obj}}\)** & **t [ms]** & **F\({}_{\textbf{obj}}\)** & **t [ms]** & **F\({}_{\textbf{obj}}\)** & **t [ms]** & **F\({}_{\textbf{obj}}\)** & **t [ms]** & **F\({}_{\textbf{obj}}\)** & **t [ms]** & **F\({}_{\textbf{obj}}\)** \\ \hline
2 & 2 & 1860 &to 3.82 s) or introduce the risk of premature termination. In the latter case, minimization of the objective function value is notably less efficient. Although the improvement from the non-optimized reference is still significant (for 8 \(\times\) 8 array: 337,978 reduced to 123,696), the proposed approach offers much better results (F\({}_{\text{obj}}\) = 76,105). As the floorplanner attempts to place innermost elements of the array near the center of the fabric, it may not be capable of finding viable solutions located at peripheral positions. Thus, objective-function results for small arrays placed in large devices might be higher than for reference methods. Depending on the connection to I/O ports and various aspects of the design not considered in the objective function, a central location of the array may still be beneficial. Moreover, if placement far from the center is desirable, the central point can be shifted closer to any position by prohibiting regions located in the opposite direction. Considering the significant acceleration offered by the proposed approach, multiple solutions with variously shifted centers can be checked in a fraction of the time required for a single simulated annealing run. Execution time reduction for designs with small PE arrays might seem irrelevant as floorplanning time of several seconds is negligible in comparison to placement and routing time. However, in the case of larger array sizes, the floorplanning is accelerated by minutes, while offering similar quality results (Figure 10). Considering multiple reiteration during development, this can contribute to a significant time saving. Note that, in order to increase legibility the floorplanning time in Figure 10 is depicted in logarithmic scale. Moreover, as the total cost is geometry dependent (M(N \(-\) 1) + N(M \(-\) 1) connections for M \(\times\) N array), objective-function values are normalized with respect to total number of connections within PE array. The proposed floorplanning approach attempts to keep consistency between logical and physical structure. If the geometries of the PE array and partition distribution differ significantly, the method may be less effective. Indeed, differences in the quality of the results can be observed in the floorplanning results for various PE arrays of similar size presented in Table 3.  
The importance of the proposed direction inconsistency penalties is proved by comparing simple outward breadth-first search with the modified version (Table 4). It can be observed that using the proposed modifications allows one to obtain significantly lower objective-function values for both the initial floorplan and 2-opt optimized results.