# RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool
## 2 Hardware Representation Requirements
### DEVS Formalism for Verilog Semantics  
The DEVS (Discrete Event System Specification) formalism introduced by [PERSON] is a set-theoretic formalism which provides a means of modeling a discrete event system in a hierarchical, modular way. With DEVS formalism, we can perform system modeling more easily by breaking down huge hierarchical systems into small component model units that are interconnected and interactive. There are two types of models in DEVS formalism. The atomic model is the most basic model that can no longer be decomposed in DEVS-based design specifications. The atomic model describes the change in the behavior and state of a component over time. Formally, an atomic model M is specified by a septuple as follows:  
M = <X, S, Y, \(\delta\) int, \(\delta\) ext, \(\lambda\), ta>  
where X is the set of input values. S is a set of states. Y is the set of output values. \(\delta\) int: S \(\rightarrow\) S is the internal transition function. \(\delta\) ext: Q \(\times\) Xb \(\rightarrow\) S is the external transition function,  
where Q \(\in\) {(s,e) \(\mid\) s \(\in\) S, 0 \(\leq\) e \(\leq\) ta(s)} is the total state set,  
e is the time elapsed since last transition,  
Xb denotes the collection of bags over X. \(\lambda\): S \(\rightarrow\) Yb is the output function. ta: S \(\rightarrow\) R + 0, is the time advance function  
The septuple DEVS model is the most commonly used form. When matched with the Verilog module, X matches the input wire/register list and trigger that activates the always statement. S is common to all atomic models clk/wire input \(\rightarrow\) (S2, \(\mathrm{\SIUnitSymbolMicro}\)(0)) 0-time internal transition followed by logical operations and event queues, output wire update \(\rightarrow\) (S3, \(\mathrm{\SIUnitSymbolMicro}\)ext(t)) wire (Y) output. Then, time advance by timescale \(\rightarrow\) (S1, \(\mathrm{\SIUnitSymbolMicro}\)(infinity)) has  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Aspect** & & **Requirements** \\ \hline \multirow{2}{*}{Sequential/} & \multirow{2}{*}{Combinational} & \multirow{2}{*}{Output evaluation for the input with delay (feedback free, no state)} \\ \cline{3-3  
the entire system hierarchically. This model can construct a complex model by combining multiple atomic models into one to create a new model. The definition of the coupling model DN is as follows:  
DN = < X, Y, D, EIC, EOC, IC, SELECT >  
where  
X: input events set  
Y: output events set  
D: set of all component models in DEVS  
EIC \(\subseteq\) X \(\times\) \(\cup\)iXiXi: external input coupling relation  
EOC \(\subseteq\)\(\cup\)iYi \(\times\) Y: external output coupling relation  
IC \(\subseteq\)\(\cup\)iXiXi \(\times\)\(\cup\)iYi: internal coupling relation  
SELECT: 2M - - \(\varphi\) -> D is a function which chooses one model when more than two models are scheduled simultaneously. The coupled model is required when multiple atomic model groups, i.e., multiple modules, are used in a single simulation. The output signal from one module is transmitted to the appropriate DN model with reference to D, and to the atomic model inside the coupled model with reference to IC. Each model has both EIC and EOC that manage internal input/output. Such a coupled model can be basically used to simulate multiple modules within one testbench, but it is also necessary to ensure an installation that mixes submodules within the modules. Additionally, expressing and performing an HDL simulation with DEVS formalism must be accompanied by a confluent transition function on what state and how to respond when internal transition occurs and race conditions occur due to message input from the outside. In previous studies, the concept of Delta-time advance, as with HDL simulators,  
Figure 3: Hardware model to atomic DEVS model mapping-based behavioral module. has been introduced to generate minute time advancements that are expressed on the simulator but not shown in the actual simulation results.