# An LLC Converter with Capacitive Insulation
## 4 Experimental Results  
The traditional circuit shown in Figure 7a and the proposed circuit shown in Figure 7b adopt individual Y1 capacitors, named C\({}_{Y}\), to remove common-mode EMI without affecting circuit behavior. These two have the same input voltage, output voltage, primary-side LLC controller IC, secondary-side SR controller IC, and MOSFETs, except for resonant parameters and transformer parameters. Figure 8a-c present the measured waveforms of \(v_{c\text{r}1}\), \(v_{c\text{r}2}\), \(i_{\text{L}r}\), and \(v_{g\text{s}2}\) at 10%, 50%, and 100% load, respectively. It can be seen that when the load is lower than 40%, the converter enters burst mode operation, which is a common technology that improves the efficiency of the LLC at a light load for the commercial LLC IC in industry applications. As the load current increases, the amplitudes of \(v_{C\text{r}1}\), \(v_{C\text{r}2}\), and \(i_{\text{L}r}\) will increase. It can be observed that the operation of the burst mode allows the light-load frequency to be reduced to maintain a relatively high \(i_{\text{L}r}\), so that the resonant tank has enough energy for the output capacitance \(C_{\text{oss}}\) of the MOSFET to be charged and discharged, as well as to obtain near-ZVS. As the load increases, \(i_{\text{L}r}\) increases, and complete ZVS can be achieved. Figure 9a-c show the measured waveforms of \(v_{g\text{s}1}\), \(v_{g\text{s}2}\), \(v_{d\text{s}1}\), and \(v_{d\text{s}2}\) at 10%, 50, and 100% load, respectively. Both switches are near-ZVS or ZVS. Figure 7: Actual circuit structure: (**a**) traditional; (**b**) proposed. Figure 8: Measured waveforms: \(v_{c\tau 1}\), \(v_{c\tau 2}\), \(i_{Lr}\), and \(v_{g2}\) under (**a**) 10% load, (**b**) 50% load, and (**c**) 100% load. Figure 9: Measured waveforms: \(v_{gs1}\), \(v_{g2}\), \(v_{ds1}\), and \(v_{ds2}\) under (**a**) 10% load, (**b**) 50% load, and (**c**) 100% load. Figure 10a-c display the measured waveforms of \(v_{gs1}\), \(v_{gs2}\), \(v_{gs3}\), and \(v_{gs4}\) at 10%, 50%, and 100% load, respectively. All the switches operate as the traditional LLC converter. The reduction in the voltages on \(v_{gs3}\) and \(v_{gs4}\) is a patented driving mechanism [25]. This mechanism can keep \(v_{ds3}\) and \(v_{ds4}\) at around \(-40\) mV, even when the current through the MOSFET is low. This function puts the gate driving voltage at a low level when the synchronous MOSFET is turned off, which shortens the turn-off time. When \(v_{ds3}\) or \(v_{ds4}\) rises to trigger the turn-off threshold of \(+40\) mV, the gate driving voltage drops to zero rapidly. Figure 10: _Cont._  
All the measured efficiency results do not include the front-end bridge rectifier and power factor correction stage. From Figure 11, it can be observed that the efficiency throughout the load range is above 87.5% and can be up to 95%. Even though the prototype is designed with a specification of DC input voltage from 370 V to 390 V, the final prototype can still work with lower input voltage down to 340 V DC and perform similar conversion efficiency, which is helpful to extend the hold-up time further. The proposed prototype is compared with the 150 W LLC DC-DC module product from Asian Power Device Inc. (Taipei, Taiwan). Their LLC controller, primary-side switches, and SR switches are all the same. As shown as Figure 12, the former LLC DC-DC module is a 150 W product from Asian Power Device Inc. with a power density of 1.81 W/cm\({}^{3}\), and the latter is a 120 W product with a power density of 2.71 W/cm\({}^{3}\). The proposed prototype has a higher power density than the traditional circuit due to the reduction in the size of the transformer. Figure 11: Curves of efficiency versus load current. The efficiency comparison is shown in Figure 13. The proposed prototype has the same efficiency performance when the load current is above 4 A. The prototype has higher efficiency under light load conditions due to the burst mode setting point at 40% load.