## 5 Findings and Analysis
### Implementation Insights and Results  
The newly developed systolic multiplier design underwent a thorough evaluation compared to current systolic and semi-systolic multiplier implementations [19; 20; 43; 44; 50]. This assessment was carried out using a systematic methodology. The modelling and realization of the various multiplier architectures were conducted with the VHDL programming language, which is well-suited for detailed hardware representation. During the synthesis phase, the framework employed the Synopsys Design Compiler alongside the Nangate library (15 nm, 0.8 V), a reputable tool known for its accuracy in estimating area, delay, and power consumption. This comprehensive methodology ensures that the performance of the proposed design is effectively compared to established implementations in the field. To ensure that the designs met their performance criteria, a comprehensive assessment procedure was conducted utilizing ModelSim's simulation capabilities. This phase involved creating intricate testbenches specifically designed to evaluate a wide range of operational scenarios, thereby verifying the consistency and reliability of outputs across various conditions. The meticulous nature of this validation effort was crucial for identifying potential issues early on, ensuring that only designs meeting all performance requirements progressed to the synthesis phase. This structured approach not only streamlined the overall development process but also significantly enhanced the quality and integrity of the final designs. The synthesis phase represents a crucial step in the design workflow, as it converts VHDL code for each multiplier design into a gate-level netlist, a task efficiently handled by the synthesis tool. This significant process translates abstract design specifications into a format that is ready for physical implementation, ensuring that the designs can be successfully realized in hardware. The produced gate-level netlists provide a comprehensive depiction of the circuit architecture, which is instrumental for additional refinement and evaluation in the following stages of the design process.The synthesis phase stands as a pivotal moment in the design workflow, transforming the intricate VHDL code of each multiplier design into a tangible gate-level netlist. This essential process, deftly executed by the synthesis tool, breathes life into abstract design specifications, converting them into a format primed for physical implementation. As the netlists emerge, they unveil a comprehensive depiction of the circuit architecture, revealing the intricate connections and relationships that will ultimately be realized in hardware. This detailed representation serves not only as a blueprint but also as a foundation for further refinement and meticulous evaluation in the subsequent stages of the design process, ensuring that every aspect aligns with the intended performance and functionality. To facilitate this conversion, the compiler harnesses the power of the Nangate library, which is meticulously designed to account for critical environmental factors affecting circuit performance. This library provides essential parameters that are tailored to the specific technology, including gate sizes, signal propagation delays, and power characteristics. Importantly, it incorporates considerations for noise margins, thereby ensuring that circuits can withstand signal fluctuations without compromising their functionality. Moreover, the library models temperature variations, enabling designers to predict the impact of temperature changes on performance metrics such as propagation delays and power consumption. Additionally, it accommodates voltage fluctuations to guarantee reliable operation across a range of supply voltages. The library also emphasizes electromagnetic effects, which can disrupt circuit performance through issues like crosstalk and signal integrity degradation, particularly in densely packed designs.