# SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
## 2 SiGe-Surrounded BL PAD Structure and Erase Speed Enhancement  
Figure 1 shows the cross-sectional view of a 3D NAND with 96 WLs in the COP structure used for the TCAD simulation. The diagram includes detailed material information and layer thicknesses. In this work, we propose an approach in which an undoped SiGe layer surrounds a n+ doped BL PAD. For the device simulation, the SiGe composition was specified by setting the Ge composition ratio (\(\mathrm{SiGe_{X}}\)) to the desired value. Figure 1: Cross-section of the top part of the simulated 3D NAND string and the details of material and thickness of each layer. The carrier recombination model was based on Shockley-Read-Hall (SRH) processes with doping dependence, while BTBT was modeled using the Hurkx formulation [16]. Carrier transport employed the Philips unified mobility (PhuMob) model calibrated for arsenic doping, supplemented by an electric field normal to the interface (Enormal) high-field saturation correction to capture velocity saturation effects. Meanwhile, in the nitride layer, we introduced donor trap energy level of 2.5 eV below the conduction band and acceptor traps 1.0 eV below the conduction band, each at a density of \(1\times 10^{20}\) cm\({}^{-3}\) with electron and hole capture cross-sections of \(1\times 10^{-13}\) cm\({}^{2}\). Next, Table 1 shows the operating voltages for the program, erase, and read operations in 3D NAND Flash. Figure 2 presents the timing diagrams for the erase sequences. As shown in Figure 2, the erase voltage V\({}_{\text{ERS}}\) is applied simultaneously to the BL and common source line (CSL), while the GIDL transistor (GIDL TR), string-select line (SSL), and ground-select line (GSL) are held at a fixed 10 V. The erase operation is divided into a 0.1 ms ramp-up phase followed by a 1 ms erase execution phase. The V\({}_{\text{FGM}}\) is applied to the selected WL for 30 \(\upmu\)s, while the SSL, GSL, GIDL TR, and unselected WLs are held at 7 V and the BL and CSL are held at 0 V. The erase operation is performed across the entire string, while the program operation is carried out only on the selected WL. Figure 3 shows the portion of the energy band diagram along the A-A\({}^{\prime}\) cut in Figure 1 for a SiGe thickness of 5 nm. The band diagram was taken immediately after the 0.1 ms ramp-up of the 14 V erase voltage. It highlights how the bandgaps of the pure Si (SiGe\({}_{0}\)) and SiGe\({}_{0.5}\) materials differ. The horizontal axis shows the position along the A-A\({}^{\prime}\) direction, and the vertical axis shows energy level. Because SiGe\({}_{0.5}\) has a narrower bandgap than Si (SiGe\({}_{0}\)), electrons can tunnel more readily from the valence band into the conduction band, yielding a higher BTBT rate. This explains the differences in average channel potential rise and GIDL current observed in Figures 4 and 5 as functions of Ge composition ratio and t\({}_{\text{SiGe}}\). \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Contact** & **Erase** & **Program** & **Read** \\ \hline BL & V\({}_{\text{ERS}}\) & 0 V & 0.2 V \\ CSL & V\({}_{\text{ERS}}\) & 0 V & 0 V \\ SSL & 10 V & 7 V & 7 V \\ GSL & 10 V & 7 V & 7 V \\ GIDL transistor & 10 V & 7 V & 7 V \\ Selected WL & 0 V & V\({}_{\text{FGM}}\) & V\({}_{\text{Read}}\) \\ Unselected WLs & 0 V & 7 V & 5 V \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Bias Conditions for Program, Erase, and Read Operations in 3D NAND Flash. Figure 2: Timing diagram of erase operations. Figure 4 shows the average channel potential for various Ge composition ratios. The SiGe bandgap shrinks as x increases [17], directly boosting the BTBT rate in the SiGe layer, which in turn accelerates the average channel potential rise and boosts the GIDL current during the erase operation.