## 2 Design and Micro-Nano Fabrication
### Micro-Nano Fabrication  
Figure 7 shows a diagram of the 12-step micro-nano fabrication process of the IPD technology for proposed BPF. The device was manufactured and cut on a 6-inch GaAs substrate. The air-bridge structure, which is the most complicated part of this device, was considered as a representative in Figure 7 to intuitively explain the entire microfabrication process. First, an acetone bath, isopropanol (IPA), and deionized (DI) water were used to treat and eliminate ionic contaminants, organic impurities, and natural chemical oxides on the surface of the GaAs wafer, as shown in Step 1. Next, plasma-enhanced chemical vapor deposition (PECVD) was exploited to deposit a 200 nm thickness SiNx passivation layer (relative permittivity: 7.5, loss tangent: 0.002) in a chamber environment of the mixture of SiH\({}_{4}\) and NH\({}_{3}\) (ratio of 1:19), with temperature of 250 \({}^{\circ}\)C, pressure of 1200 mTorr, gas flow of 2000 sccm, and an RF power of 100 W, to obtain a flat wafer surface. Subsequently, a seed metal layer with 20 nm Ti and 80 nm Au was formed through the sputtering process to enhance the adhesion between the passivation layer and first metal layer, as shown in Step 2. Subsequently, the positive photoresist was coated onto the preliminarily processed wafer using a spin-coated, and the layout of the first metal layer was defined by the exposure and development process, as shown in Step 3. The first metal layer (bond layer) with 4.5 and 0.5 \(\upmu\)m thick Cu and Au, respectively, was electroplated on the wafer surface in an environment of 5.0 \(\times\) 10\({}^{-6}\) mTorr pressure, 0.5 A/s minimum deposition rate, and 10 kV electron energy (Step 4). Then, the photoresist was peeled off in a lift-off machine with an environment of acetone/IPA/DI water mixture for 90 s (Step 5). Subsequently, the positive photoresist was spin-coated on the wafer again, and the second exposure and development process were applied to define the layout of the middle metal layer, as shown in Step 6. The second metal layer (test layer) with 1.6 and 0.2 \(\upmu\)m thick Cu and Au, respectively, was electroplated on the wafer surface (Step 7) using the same deposition process as the bottom metal layer. Likewise, the remaining photoresist was eliminated using the lift-off machine to obtain the results shown in Step 8. Subsequently, a 6.8 \(\upmu\)m thick positive photoresist was spin-coated on the wafer surface until it was flushed with the second metal layer. Then, a 5 \(\upmu\)m thick negative photoresist was spin-coated on the positive photoresist and was allowed to expose and develop to define the layout of the top metal layer, as shown in  
Figure 6: Simulation results of the capacitance and resistance for optimization: (**a**) Simulated capacitance value; (**b**) Simulated resistance value. Step 9. It should be noted that because the line width of the top metal layer is wider than that of the middle layer metal, two types of photoresists must be used simultaneously to perfectly expose the shape of the top metal layer. Lastly, the third metal layer (lead layer) with 4.5 and 0.5 um thick Cu and Au, respectively, was electroplated on the wafer surface (Step 10) using the same deposition process as the previous metal layer. Similarly, the remaining photoresist was peeled off using the lift-off machine for 90 s, a sufficient time to ensure the complete stripping of the PR without residue, to obtain the results shown in Step 11. Subsequently, a 300 nm SiNx passivation layer was deposited on the entire surface (Step 12) to protect the device from moisture and oxidation. Ultimately, the fabricated resonator was mounted on the PCB via polishing, cutting, and wire bonding processes to measure the RF performance of the manufactured devices. Table 3 summarizes the details of the technologies and metals used in the manufacturing process.