## 4 System Architecture
### Phase Control Validation  
The Keysight E5071C vector network analyzer (VNA) was used to validate the phase shifts introduced by the system. This was determined by measuring the S\({}_{21}\) of each channel. Port 1 of the VNA was connected to each ADC through uncalibrated cables and baluns, and Port 2 was connected to the DAC. \begin{table}
\begin{tabular}{c c c c} \hline  & **LUT** & **FF** & **DSP48E2** \\ \hline Available & 425,280 & 850,560 & 4272 \\
1 Beam & 13,501 (3.17\%) & 12,680 (1.49\%) & 64 (1.5\%) \\
4 Beams & 21,724 (5.11\%) & 25,182 (5.11\%) & 512 (11.99\%) \\
8 Beams & 32,990 (7.76\%) & 41,008 (4.82\%) & 512 (11.99\%) \\
12 Beams & 43,046 (10.12\%) & 56,304 (6.62\%) & 768 (17.98\%) \\
20 Beams & 63,908 (15.03\%) & 87,569 (10.30\%) & 1280 (29.96\%) \\ \hline \end{tabular}
\end{table} 
Table 1: Hardware resource usage according to the number of beams used. \begin{table}
\begin{tabular}{c c c} \hline  & **Single Threaded** & **Multithreaded** \\ \hline
1 Beam & 0.42 ms (2407 Hz) & - \\
4 Beams & 1.34 ms (746 Hz) & 0.81 ms (1231 Hz) \\
8 Beams & 2.67 ms (374 Hz) & 1.21 ms (822 Hz) \\
12 Beams & 4.04 ms (247 Hz) & 1.49 ms (670 Hz) \\
20 Beams & 6.69 ms (149 Hz) & 2.44 ms (409 Hz) \\ \hline \end{tabular}
\end{table} 
Table 2: Average computation time and frequency according to the number of beams processed. Three situations were taken into consideration when validating the functionality of the system. Firstly, without introducing any phase shifts the phases of each channel were measured. This was performed to assess the phases introduced by each channel when left uncalibrated. Secondly, the previous results were used to calibrate the system by aligning all channel's phases with respect to ADC 0, and new measurements were taken to check if the calibration worked as expected. These results are demonstrated in Table 3. After that, the channel phases were introduced for a beam with \(\theta=45^{\circ}\) and \(\phi=90^{\circ}\) and the phases were measured again to assess the difference between the computed phases and the measured ones. All the results presented are for the central frequency of L1, 1.57542 GHz. Table 4 shows the results for the calibration step of the process. The RFSoC is capable of synchronizing every channel using Xilin's \"Multi-tile Synchronization\". This delays every sample by a fixed amount of time and is repeatable even during power cycles. However, due to the uncalibrated cables and baluns, the measured phases are not equal but can be easily compensated. This was achieved by using the measurements to approximate the phase of each channel to the one of the ADC 0, resulting in repeatable differences of less than a degree. \begin{table}
\begin{tabular}{c c c c} \hline \hline  & **Calculated** & **Measured** & **Difference** \\ \hline ADC 0 & \(-101.82^{\circ}\) & \(-101.73\) & \(-0.09^{\circ}\) \\ ADC 1 & \(-203.65^{\circ}\) & \(-203.57^{\circ}\) & \(-0.08^{\circ}\) \\ ADC 2 & \(-305.47^{\circ}\) & \(-305.40^{\circ}\) & \(-0.07^{\circ}\) \\ ADC 3 & \(-407.29^{\circ}\) & \(-407.51^{\circ}\) & \(+0.22^{\circ}\) \\ ADC 4 & \(-101.82^{\circ}\) & \(-102.06^{\circ}\) & \(+0.24^{\circ}\) \\ ADC 5 & \(-203.65^{\circ}\) & \(-203.58^{\circ}\) & \(-0.07^{\circ}\) \\ ADC 6 & \(-305.47^{\circ}\) & \(-305.55^{\circ}\) & \(+0.08^{\circ}\) \\ ADC 7 & \(-407.29^{\circ}\) & \(-407.41^{\circ}\) & \(+0.12^{\circ}\) \\ ADC 8 & \(-101.82^{\circ}\) & \(-101.65^{\circ}\) & \(-0.17^{\circ}\) \\ ADC 9 & \(-203.65^{\circ}\) & \(-203.73^{\circ}\) & \(+0.08^{\circ}\) \\ ADC 10 & \(-305.47^{\circ}\) & \(-305.54^{\circ}\) & \(+0.07^{\circ}\) \\ ADC 11 & \(-407.29^{\circ}\) & \(-407.23^{\circ}\) & \(-0.06^{\circ}\) \\ ADC 12 & \(-101.82^{\circ}\) & \(-101.46^{\circ}\) & \(-0.36^{\circ}\) \\ ADC 13 & \(-203.65^{\circ}\) & \(-203.57^{\circ}\) & \(-0.08^{\circ}\) \\ ADC 14 & \(-305.47^{\circ}\) & \(-305.50^{\circ}\) & \(+0.03^{\circ}\) \\ ADC 15 & \(-407.29^{\circ}\) & \(-407.25^{\circ}\) & \(-0.04^{\circ}\) \\ \hline \hline \end{tabular}
\end{table}