## 5 Results
These values were calculated by obtaining the difference in execution times between the write and read tasks (\(T_{W,R}^{i}-T_{W,R}^{i-1}\)), as illustrated in Figure 9. Furthermore, the parameter \(T_{\text{max}}\) establishes the maximum interval within which tasks must be coordinated, acting as a reference period for the task execution cycle. The values of \(\phi_{\text{max}}\) indicate the additional adjustment needed to synchronize producer and consumer operations. Figure 11: Measurements of data transfer between cores using a 16-bit shared buffer with the LET-TDMA method implementation. The figure shows the data values written by the producer task on Core 1 and read by the consumer task on Core 2 over time. The execution log performed on real hardware highlights the determinism and low latency variability achieved by using the proposed solution. Figure 12 shows the results of calculating the values of \(P_{W,R}\) and \(Q_{W,R}\), which are identical at all calculated data points. These ensure that both read and write execution tasks operate at synchronized moments, thus avoiding desynchronization between operations. Figure 12a-c represent the values of \(P_{W,R}\) and \(Q_{W,R}\) for buffer sizes of 8, 16, and 32 bits, respectively. Table 6 presents the analysis of communication methods in multicore systems, where the LET model stands out for its high predictability and consistency in response times, crucial attributes for applications that require temporal synchronization. LET's ability to provide consistent and predictable response times makes it ideal for real-time control environments and critical safety applications. However, its implementation is more complex and requires detailed planning of Logical Execution Times. On the other hand, the combination of TDMA-DMA and SPM demonstrates advantages for applications that can benefit from optimized memory management, thus improving overall system performance and reducing wait and processing times. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \(T_{W}\) & \(T_{R}\) & \(\phi_{W}\) & \(\phi_{R}\) & \(T_{\text{max}}\) & \(\phi_{\text{max}}\) & \(P_{W,R}\) & \(Q_{W,R}\) \\ \hline  
\hline \hline \end{tabular}
\end{table} 
Table 5: Time values for execution of reading and writing tasks for 32 bits. The table includes the write times (\(T_{W}\)) and the read times (\(T_{R}\)), along with the offsets (\(\phi_{W}\) and \(\phi_{R}\)) applied for synchronization. The table also presents the maximum interval (\(T_{\text{max}}\)) and additional synchronization adjustment (\(\phi_{\text{max}}\)), as well as the adjusted write and read times (\(P_{W,R}\) and \(Q_{W,R}\)) to ensure coordinated task execution. Additionally, explicit communication tends to show less variability in reactive latency times compared to implicit communication. This lower variability is required for applications that need consistent and reliable response times, as it reduces uncertainty and improves the predictability of system behavior. However, it can increase programming complexity and the overhead of synchronization management. Meanwhile, implicit communication simplifies implementation by automatically managing synchronization, but it presents greater variability in latency times and less predictability, which can lead to synchronization problems. Nevertheless, the combination of LET and TDMA has shown that the predictability and consistency of Logical Execution Time applied to task communication, along with the composability of time-controlled buffers, ensures consistent latency and temporal determinism for communication between cores in 8-bit, 16-bit, and 32-bit architectures. This reduces the need to link applications to specific cores, facilitating the creation of less dependent event chains. In this work, the LET implementation in a dual-core processor was first reproduced to measure its variability against our LET-TDMA method.