## 3 Proposed Low Voltage Delay Element  
The proposed low voltage delay element is presented in detail in this section. The abovementioned works [6; 8; 9; 21] focus on the fact that the leakage current can be declined by reducing the voltage difference between the source and the drain of transistors when they are off. However, \(i_{on}\)/\(i_{off}\) can also be enhanced by increasing \(i_{on}\). To enhance \(i_{on}\) when the transistors are on, the threshold voltage is dynamically adjusted with the change of input signal. As shown in Figure 4a, M3 and M4 are replaced by deep n-well (DNW) transistors and their bodies are connected together with the output of VLS. Meanwhile, the input of VLS is controlled by the input signal and VLS is powered by VDDH. Thus, with the help of VLS, the input signal is shifted into a high voltage domain and higher voltage swing is obtained to bias the body of the DNW transistors. Finally, the threshold voltage of the DNW transistors is reduced with the input signal and the enhanced \(i_{on}\) is obtained.  
However, the main issue is that the complementary phase in the low voltage domain is required for conventional VLSs. In most cases, the complementary phase is obtained through an inverter. As mentioned in Section 2.2, due to the fundamental limit on the power supply of a delay element, it is extremely difficult to obtain the complementary phase under a low VDD, such as below 30 mV. Thus, VLS without the need of a complementary phase is a preferred candidate for the proposed low voltage delay element. Accordingly, a VLS published in previous literature [25], as shown in Figure 4b, is inserted to assist the realization of the proposed low voltage delay element. The detailed description of this VLS is included in previous research [25]. When the input voltage is low, the bodies of M3 and M4 are also low and the threshold voltage of M3 is reduced, and thus \(i_{on}\) is enhanced. Similarly, when the input voltage is high, the bodies of M3 and M4 are high and the threshold voltage of M3 and M4 is increased and reduced, respectively. Finally, the leakage current through M3 becomes smaller and the discharging current through M4 becomes larger. The enhanced \(i_{on}\)/\(i_{off}\) indicates that the proposed low voltage delay element can ensure normal operation under a lower supply voltage and a wider voltage swing is obtained.  
As shown in Figure 4c,d, the VTC and DC gain curve are obtained by schematic-level simulation under a typical process corner at room temperature. DC gain during the flipping moment is about 1.5, which indicates that the binary switching ability still keeps under this condition. Figure 4e presents the simulated oscillation of the 21-stage ring oscillator with the proposed delay element. Due to the improved gain, it is observed that the 21-stage ring oscillator can start and sustain oscillation under an input voltage as low as 20 mV with a typical process corner at room temperature. However, when parasitic parameters of the physical layout are extracted for a more accurate evaluation of the proposed delay element, the minimal oscillation voltage of the 21-stage ring oscillator will be deteriorated, which will be illustrated in the next section.  
Figure 3: Circuit of already published delay elements: (**a**) Schmitt trigger inverter [21]; (**b**) selective Schmitt trigger inverter [6]; (**c**) stacked inverter [8]; (**d**) redundant inverter [9].