# A GPS Phase-Locked Loop Performance Metric Based on the Phase Discriminator Output
## 8 Tracking Error as a Design Metric  
In this section, we take a closer look at phase error and tracking error results by plotting \(\sigma_{\phi}\) vs. \(\sigma_{e}\). For the AWGN only case (as we have considered thus far) \(\sigma_{\phi}\) is equivalent to the jitter metric, as shown in Figure 9. Thus, we are essentially plotting the jitter metric versus our proposed metric, the standard deviation of tracking error.  
Figure 10 shows sigma phase error versus sigma tracking error for a 1 ms coherent averaging time. Both theory and simulation results are presented. Each curve represents a constant carrier-to-noise ratio, and varying PLL bandwidth. Note that reducing PLL bandwidth reduces the sigma phase error, \(\sigma_{\phi}\), but has little observable effect on the tracking error. This means that, in Figure 10, decreasing \(\sigma_{\phi}\) corresponds to decreasing bandwidth. Bandwidth for the theory ranges between 40 Hz and 0.1 Hz, while PLL simulation is conducted for 30 s at bandwidths of 15, 5, 1, 0.5, and 0.2 Hz. The 15 degrees threshold on \(\sigma_{\phi}\), corresponds to the standard jitter metric threshold [12]. Both theory and simulation results agree well until the standard deviation of tracking error, \(\sigma_{e}\), reaches about 40 degrees. For larger \(\sigma_{e}\), theory and simulation do not match in either \(\sigma_{\phi}\) or \(\sigma_{e}\).  
The solid black curve in Figure 10, corresponding to \(C/N_{0}=25.5\) dB-Hz, shows that the jitter metric only exceeds the 15 degrees threshold for large PLL bandwidths approaching 40 Hz. It can be deduced (by re-plotting Figure 9 for a 25.5 dB-Hz carrier-to-noise ratio) that this corresponds to bandwidths larger than 24 Hz. The phase jitter metric suggests that a PLL using any of the bandwidths in our simulation, would be able to track a carrier-to-noise ratio of 25.5 dB-Hz. However, the simulation results show extremely large \(\sigma_{\phi}\) that do not match theory, because the phase error is in fact non-stationary over the 30 s simulation, and the PLL has lost lock. In addition, the standard deviation of tracking error saturates at about 52 degrees, even though theory predicts it to be much larger. This phenomenon is explained in greater detail in Section 8.1.  
Figure 9: Sigma phase error vs. PLL bandwidth.  
Figure 11 shows \(\sigma_{\phi}\) versus \(\sigma_{e}\), but for a 20 ms coherent averaging time. In this case, the PLL is able to successfully track a 25.5 dB-Hz carrier-to-noise ratio. Theory and simulation agree well down to this noise level. According to [6], increasing the coherent average time should not make a difference to the \(C/N_{0}\) that can be tracked. However, Figures 10 and 11 show the opposite. Furthermore, the phase error standard deviation deviates from theory when the tracking error standard deviation approaches its saturation level of 52 degrees.  
The theoretical computation of the standard deviation of phase error breaks down as \(C/N_{0}\) decreases. However, the point at which this happens is dependent on factors such as the coherent averaging time. Figures 10 and 11 illustrate what has been observed in previous work [4; 5; 6; 7]. The phase jitter metric does not accurately predict cycle slipping and loss of lock in the presence of wideband interference. Our results suggest that the reason why is related to the tracking error standard deviation becoming saturated at 52 degrees. We believe this saturation is the result of the tracking error is exceeding the discriminator phase pull-in region (90 degrees for the arctangent discriminator) too frequently. This idea is investigated in greater depth next.  
Figure 11: Sigma phase error vs. sigma tracking error, for \(T_{co}=20\) ms.  
Figure 10: Sigma phase error vs. sigma tracking error.