# Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
## 3 Gate-Level Hiding Countermeasures
The same feature of using three-state logic was also used in [36], presenting the three-state differential dynamic logic (3 sDDL). The structure of 3 sDDL is depicted in Figure 7c. With \(CLK=0\), the gate is in the precharge phase with \(Q\) and \(\overline{Q}\) to \(V_{dd}/2\) value, in the evaluation phase with \(CLK=1\), the outputs \(Q\) and \(\overline{Q}\) go to values \(\{1,0\}\) or \(\{0,1\}\), respectively, depending on the logic function implemented in the DPDN. It has the same advantages as 3 sDL, but in this case it is not necessary to design the capacitance \(C_{DUMMY}\). As main drawbacks, it has the need for differential place and route as well as a good symmetry in the DPDN, and the fact that it requires a full custom design. In [37], the authors present the three-phase dual-rail precharge logic (TDPL), as an enhancement of the SABL logic style, to avoid the need of differential routing due to imbalances on output capacitances. The TDPL structure is depicted in Figure 8a, and it works in three different phases, namely precharge, evaluation, and discharge phases. In the precharge phase, the output nodes are precharged to \(V_{dd}\); in the evaluation phase, one of the differential branches of the DPDN is discharged by implementing the functionality of the gate and having in the output the values of \(Q\) and \(\overline{Q}\) as \(\{1,0\}\) or \(\{0,1\}\); and, finally, in the discharge phase, the output \(Q\) or \(\overline{Q}\) with value \(V_{dd}\) is also discharged. As the output wires are precharged to \(V_{dd}\) and discharged to \(GND\), the power consumption of the gate remains constant even in the presence of output capacitance mismatches, which is the main advantage of this logic style. The main drawbacks are the increment in the power consumption and the need of generating _charge_, _evaluation_, and _discharge_ signals following a specific timing diagram. In [38], the authors present the three-phase single-rail precharge logic (TSPL), based on TDPL but which eliminates the need for complementary outputs. TSPL is a dynamic logic family that operates with three different phases, namely, precharge (PRE, the output \(Q\) is charged to \(V_{DD}\)), evaluation (EVAL, the output \(Q\) is discharged depending on the inputs and the implemented gate functionality), and discharge (DCH, the output is always discharged). In Figure 8b, the schematic of the generic TSPL n-gate is depicted. The main advantages are the single rail implementation scheme and the resilience against process variations as it does not require special place and routing to balance output loads. The main disadvantages are the security level, being more vulnerable than TDPL or WDDL, and the overhead area. As in the case of TSPL, the delay-based dual-rail precharge logic (DDPL) is insensitive to unbalanced load conditions, so it allows for the use of a semi-custom design flow with automatic place and routing without any constraints in the routing of the complementary wires [39]. However, in contrast to TDPL, it operates in two phases, namely precharge (output lines precharged to \(V_{DD}\) value) and evaluation phases (both output lines discharged to \(V_{SS}\)), but maintaining the insensitivity to unbalanced load conditions. DDPL is based on time-enclosed logic (TEL) encoding [40], where the information is represented in the time domain, the logical value 1 being represented by a positive relative delay in the output lines \(Q\) and \(\overline{Q}\), and the logical value 0 by a negative relative delay in \(Q\) and \(\overline{Q}\). This means that to represent logical 1, as both differential branches are discharged to \(V_{SS}\) in the evaluation  
Figure 8: Gate-level hiding logic styles: (**a**) TDPL, (**b**) TSPL, and (**c**) DDPL. phase, the positive branch \(Q\) is discharged at a specific time before the negative branch \(\overline{Q}\). In the other case, to represent 0, the negative branch \(\overline{Q}\) is discharged before the positive branch \(Q\).