###### Abstract  
This paper proposes a step-up 3-\(\phi\) switched-capacitor multilevel inverter topology with minimal switch count and voltage stresses. The proposed topology is designed to provide five distinct output voltage levels from a single isolated dc source, making it suitable for medium and low-voltage applications. Each leg of the proposed topology contains four switches, one power diode, and a capacitor. The switching signals are also generated using a staircase universal modulation method. As a result, the proposed topology will operate at both low and high switching frequencies. To highlight the proposed topology's advantages, a comparison of three-phase topologies wasperformed in terms of the switching components, voltage stress, component count per level factor, and cost function withthe recent literature. The topology achieved an efficiency of about 96.7% with dynamic loading, and 75% of the switches experienced half of the peak output voltage (\(V_{\mathrm{DC}}\)), whereas the remaining switches experienced peak output voltage (\(2V_{\mathrm{DC}}\)) as voltage stress. The MATLAB/Simulink environment was used to simulate the proposed topology, and a laboratory prototype was also built to verify the inverter's theoretical justifications and real-time performance. cost function; multilevel inverter; pulse width modulation; switched capacitor; total standing voltage +
Footnote †: journal: Applied Science Research Center, Applied Science Private University, Amman 11931, Jordan  
(CHB),are some of the most common and classic topologies. These topologies have been used extensively in a wide variety of applications in energy storage and electrical conversion systems. NPC and FC inverters are responsible for the introduction of the balanced charging problem of DC link capacitors. In order to generate higherlevel output, the CHB design necessitates the utilization of a significant number of discrete DC voltage sources. In addition to this, each of these traditional topologies calls for an increasing quantity of semiconductor components in proportion to the number of output levels. Because of these factors, the reduction in semiconductor components as well as passive parts has become a key priority. This lessens the size and weight of the entire system, as well as the conduction and switching losses, and increases the efficiency of the system overall [3; 4]. In contrast to NPC, FC, CHB, and MMC, which have been commercialized in medium- and high-voltage applications, SC-based MLIs (SCMLIs) have primarily been developed for low/high voltage applications because they have the advantages of voltage-boosting capability as well as the voltages of self-balanced capacitors. As a result, the switched-capacitor (SC) architecture, which has gained increased attention from researchers in recent years to improve input voltage, eliminate switching components, and lower the requirements of DC sources, is the greatest invention. Therefore, researchers havestarted focusing on switched-capacitor multilevel inverter (SC-MLI) topologies. These SCMLIs are categorized as single-stage or two-stage topologies. A single-stage SCMLI generates a bipolar waveform, and as a result, it offers the opportunity to incorporate power switches that require fewer PIVs, despite the fact that the total number of power switches across all levels is relatively high.As an illustration, the SCMLI that was proposed in ref. [5] makes use of switches with PIV, which is restricted to the input voltage, but it provides a waveform with a low resolution and a low voltage gain. It synthesizes seven levels with many switching components. A self-balanced MLI topology is presented in this paper to achieve the lowest possible TSV and PIV for switches that have the capability of staircase multilevel bipolar voltage generation. This type of SCMLI is also quite popular. It is developed by inserting an SC-based circuit.