# High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA
## 5 Conclusions  
The following hypothesis was investigated in the paper: in the ASMD-FSMD technique, it is possible to perform several operations with the same variable in one clock cycle, which leads to an increase in the device performance compared to the traditional approach. This hypothesis was fully confirmed by the implementation of sequential multipliers in FPGA.  
The presented approach is not limited only to multipliers; it can be applied to the design process of various devices, where control device and datapath are used. The multiplier design process is only an example of how this methodology was used to improve the implementation results. Of course, it cannot completely replace a variety of multipliers types. There are a lot of different approaches, mostly not sequential, such as Wallace, Booth, Dadd's, CSAM (Carry-Save Array Multiplier), and others. The user can also apply embedded MAC (multiply and accumulate) blocks of FPGA. The aim of this work was not to develop the best multiplier but to show how the presented technique can improve the results of sequential circuit synthesis by only changing the way the system is described in the HDL language. Our recommendations for the practical use of the ASMD-FSMD technique to implement high-performance digital devices are as follows:  
* Use the ASMD chart for the Mealy FSMD;
* The cycles of the algorithm should be described by an ASMD chart with a minimum number of states (ASMD blocks), preferably using only one state;
* In one ASMD block, multiple operations can be applied to the same variable, and the results of those operations can be checked. Future studies on enhancing the performance of the ASMD-FSMD technique should focus on the following:
* Determining subsets of Verilog HDL operations that can be executed with the same variable in one procedural block;
* Determining subsets of Verilog HDL operations that cannot be executed with the same variable in one procedural block;
* Determining by how much (in a number of clock cycles) the performance of a digital device increases when certain operations are combined in one procedural block.  
Note that the ASMD-FSMD technique can also be used with other hardware description languages, such as VHDL and SystemVerilog, as well as in the design of digital devices not only on FPGA but also on ASICs (Application Specified Integrated Circuits).  
The results of this experiment showed that the different factors of different tools (Vivado, Quartus) are better optimized. Thus, future work should also verify the impact of external factors on the results should be verified, including the following:  
* Hardware description language used for implementation;
* Synthesis parameters are used in the Vivado and Quartus tools.  
**Author Contributions:** Conceptualization, V.S.; methodology, V.S.; software, V.S.; validation, A.K. and T.G.; formal analysis, A.K.; investigation, A.K.; resources, A.K. and T.G.; writing--original draft preparation, V.S. and A.K.; writing--review and editing, A.K. and T.G.; visualization, A.K.; supervision, V.S.; project administration, A.K. and T.G.; funding acquisition, A.K. and T.G. All authors have read and agreed to the published version of the manuscript.  
**Funding:** The work was supported by the WZ/WI-IIT/5/2023 and WZ/WI-IIT/3/2023 grants from the Bialystok University of Technology and funded with resources for research by the Ministry of Science and Higher Education in Poland.  
**Data Availability Statement:** The original contributions presented in the study are included in the article, further inquiries can be directed to the corresponding author.  
**Conflicts of Interest:** The authors declare no conflicts of interest.