## 3 Simulation Results  
To define the sensitivity requirements for the sensing front-end, the intrinsic circuit noise and external noise are analyzed. Although this study primarily presents simulation results rather than measurement data, the proposed simulation methodology can be utilized to define system specifications and provide practical design guidelines. Moreover, this approach is not limited to the proposed system but can be adapted to other sensing front-end structures, enhancing its applicability. Figure 8 shows the overall AFE architecture, incorporating both intrinsic and external noise power within the system. The output-referred noise voltages for the C\({}_{\text{S}}\)-compensator, reference generator, op-amp in C2V, and Gaussian-shaped S/H circuits are represented as \(\overline{V_{NO,CP}}^{2}\), \(\overline{V_{NO,REF}}^{2}\), \(\overline{V_{NO,pump}}^{2}\), and \(\overline{V_{NO,S/H}}^{2}\) while the input-referred noise voltage of the CCII is \(\overline{V_{NIN,CCII}}^{2}\) and the noise current of the feedback resistor in the C2V is \(\overline{I_{RINT}}^{2}\). Additionally, the external noise from the capacitive coupling is denoted as \(\overline{V_{ND}}^{2}\). Thus, the overall noise at the AFE output or S/H output is expressed as \(\overline{V_{NO}}^{2}\), as also depicted in Figure 8. However, its amount cannot be quantified due to its dependence on the environmental noise condition. Thus, we define two evaluation metrics: one to qualify the SNR over the intrinsic circuit noise, and the other to assess noise immunity against the external noise by measuring the system's responsiveness to noise frequencies ranging from DC to a predefined high frequency. First, the intrinsic SNR can be described [21] in Equation (2)  
\[\text{SNR (dB)}=20\text{log}_{10}\frac{\sqrt{\text{N}_{\text{Filter}}}\times \text{V}_{S/H,\text{OMax}}}{2\overline{V_{NO}}} \tag{2}\]  
where N\({}_{\text{Filter}}\) is the number of filter taps, which is twice the number of TSP driving, and V\({}_{\text{S/H,OMax}}\) and \(\overline{V_{NO}}\) are the maximum output voltage level and the total output-referred noise observed at the Gaussian-shaped S/H circuit, respectively. Since the signal power from capacitive changes is proportional to N\({}_{\text{Filter}}\), and the noise power is proportional to the square root of N\({}_{\text{Filter}}\), the SNR becomes proportional to the square root of N\({}_{\text{Filter}}\), indicating that a higher SNR can be achieved with increased scan time. Moreover, the factor of 2 in the denominator of Equation (2) reflects the reduction in the total signal amplitude due to Gaussian shaping in the S/H circuit, compared to maintaining a constant V\({}_{\text{S/H,OMax}}\) at the output. We target an intrinsic SNR exceeding 60 dB with a 1 pF capacitive variation from a finger (C\({}_{\text{F}}\)), N\({}_{\text{Filter}}\) = 64 Gaussian filter coefficients, and a 200 kHz TSP driving fre- patency. Figure 9 shows the simulated output (V\({}_{\text{S/H,OMax}}\)) of the Gaussian S/H circuit. The output root mean square (RMS) integrated noise of the S/H circuit over the system bandwidth was also evaluated using the noise simulation function in Virtuoso. The V\({}_{\text{S/H,OMax}}\) reaches up to 2.67 V at the center of the Gaussian-shaped output, achieving a signal voltage of 1.17 V for capacitive change (V\({}_{\text{S/H,OMax}}\)-V\({}_{\text{CM}}\)), while the simulated output RMS noise (\(\overline{V_{NO,RMS}}\)) is 2.31 mV, resulting in an intrinsic SNR of 54 dB in a single pulse. With N\({}_{\text{Filter}}\) of 64 and a 200 kHz TSP driving frequency, the SNR is further enhanced to 66 dB within a scan time of 160 us. As the TSP frame rate is typically synchronized with the display in TDDI, the reduced scan time enhances system efficiency by maximizing the time allocated to display driving.