## 4 Experimental Results  
In order to simulate the function of a feedforward network on hardware FPGA, this paper implements an extensible neural network based on the improved butterfly fat tree (IBFT) architecture. Stratix III EP3 SE260 FPGA can effectively implement the proposed neural network. In total, 64 NPs are implemented with the time division multiplexing technique for a single NP. Each NP is responsible for 1000 virtual neurons. The hardware resource cost is shown in Table 1. Traditionally, the use of lookup tables to compute multiplication solves this problem, but this method is expensive and backward in terms of memory resources and digital signal processing (DSP) resources. It can be clearly found from Table 2 that the hardware resource cost of only 18 bits of DSP block using the traditional method exceeds all available hardware resources. In contrast, the proposed implementation method  
Figure 3: Digital implementation of the single neuron. (**a**) Digital implementation of the Izhikevich model; (**b**) Digital implementation of the coordinate rotation digital computer (CORDIC) algorithm. can effectively reduce hardware resource costs in terms of the DSP and memory resources which are extravagant elements on FPGA hardware. The proposed digital neuromorphic system operates at a working frequency of 146.03 MHz. The design and programming of the proposed digital neural morphological network is realized by using the VHDL modeling language. On the premise of using ALTERA Quartus II to synthesize HDL code, a Stratix III FPGA development board with 60 nm can be successfully developed. The oscilloscope photograph of the membrane potential of the neurons in the hippocampal neural network is shown in Figure 4. This indicates that the proposed neuromorphic hippocampal neural network can accurately track the biodynamics in real time. The relationship of the computational precision, the iteration number and the CORDIC module number is shown in Figure 5a. The computational precision is defined by relative error between the CORDIC-based results and the desired results. It shows that the precision increases with increasing iteration number. The calculation accuracy will decrease as the number of CORDIC modules increases. Figure 5b reveals the relationship between the number of CORDIC modules and different kinds of the hardware resource cost. The CORDIC module can significantly reduce the hardware resource cost of the DSP block 18-bit elements and total storage bits. Considering both Figure 5a,b, it means that the CORDIC module in the proposed hardware implementation can save hardware resources while maintaining high level of computational precision. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Resources** & **Conventional** & **CORDIC-Based** \\ \hline \hline \begin{tabular}{c} Combinational ALUTs \\ Memory ALUTs \\ Dedicated logic registers \\ Total block memory bits \\ DSP block 18-bit elements \\ Total PLLs \\ \end{tabular} & \
\begin{tabular}{c} 19,652/203,520 (10\%) \\ 490/101,760 (\(<\)1\%) \\ 8924/203,520 (4\%) \\ 7,771,246/15,040,512 (52\%) \\ 2384/768 (310\%) \\ 1/8 (13\%) \\ \end{tabular} &
\begin{tabular}{c} 10,642/203,520 (5\%) \\ 712/101,760 (1\%) \\ 11,546/203,520 (6\%) \\ 2106/15,040,512 (<1\%) \\ 0/768 (0\%) \\ 1/8 (13\%) \\ \end{tabular} \\ \hline \hline \end{tabular}
\end{table} 
Table 2: The hardware resource consumption when conventional and CORDIC-based implementation methods are used respectively to implement the hippocampal neural network. Figure 4: Biological behaviors of the hippocampal neural network implemented on Stratix III field programmable gate array (FPGA), which are observed on the oscilloscope device. The voltage scale is 50 mV.