## 4 Optimal Utilization  
Up to this point, optimal utilization has been discussed primarily at the hardware level, focusing on reducing comparator count and memory consumption through the proposed AFP architecture. However, to fully realize system-wide efficiency in DCS, it is essential to extend this concept to the system level. In this context, a newly designed MFP module is proposed and applied within the DCS framework to manage computational tasks more effectively. To evaluate the impact of this architectural enhancement, a simulation of the conventional DCS configuration was first performed as a baseline [9,14]. Following this, the proposed MFP module was integrated into the DCS, and a second simulation was conducted. The results of this simulation illustrate the performance gains achieved under the proposed architecture in terms of processor utilization, execution latency, and real-time responsiveness. Figure 4a represents the conventional architecture, in which a single processing block (SEGCRM) handles all logic and computation tasks. This block outputs a processor utilization value of 83.84%, as shown on the display, indicating a high processing load. The centralized nature of this structure can lead to performance bottlenecks and increased risk of overload, particularly under complex or high-frequency operations. All computations are processed within one module, offering limited flexibility for scaling or optimization. In contrast, Figure 4b depicts the proposed architecture, which decomposes the computational logic into multiple parallel SEGCRM blocks. Each block processes part of the overall logic independently, significantly reducing individual processor load. The outputs from these distributed blocks are then combined using a _sum logic unit_, as shown on the right side of Figure 4b. This summation process aggregates the results from each module, resulting in an overall processor utilization output of 57.2%, which is markedly lower than in the conventional case. The modular design enhances load balancing, improves response time, and provides a scalable path for future system expansion. Together, Figure 4a,b demonstrate how architectural restructuring--particularly through distributed computation and summation logic--can yield significant improvements in processor efficiency and system reliability. Figure 3: (**a**) Comparison of comparator counts required by the conventional flash ADC and the proposed AFP cross different bit resolutions. (**b**) Efficiency improvement in the AFP relative to the conventional architecture, calculated based on comparator count reduction. As a result, the proposed architecture enhances both the reliability and efficiency of modern DCS, making it highly suitable for next-generation energy and automation systems where precision, responsiveness, and resource optimization are essential. Figure 5 presents the simulation results of the proposed DCS architecture incorporating the newly designed MFP module. Figure 5a displays a real-time interface capturing key system metrics such as CPU utilization and memory usage. In this simulation, the CPU utilization is shown to be 12.195612%, and memory utilization is 643 bytes, both of which are significantly reduced compared to the conventional architecture, demonstrating the effectiveness of the optimized logic distribution and lightweight design. Figure 5b provides a detailed time-series performance graph along with tabulated control block data, showing stable and balanced processing loads across multiple loops and PCUs. The colored trend lines represent individual signal blocks and indicate minimal fluctuation and high reliability in execution under continuous operation. These results further validate the impact of the proposed architecture in reducing computational overhead while maintaining precise, real-time process control in distributed environments.