# A Fully Integrated Low-Power Multi-Mode RF Receiver for BDS-3/GPS
## 4 Receiver Design
### AGC and DCOC
The duty cycles of the MSB MAG signals are 33% and 18.85% for two- and four-bit ADCs, respectively, to provide a negligible SNR loss that is less than 0.5 dB [5; 8], which is used to determine \(\mathit{powth\_high}\) and \(\mathit{powth\_low}\). DCOC is implemented based on DACs, as shown in Figure 6. There is no operational amplifier in DAC and the currents of the current source array directly flow through resistors to improve speed and reduce power, as shown in Figure 8. DAC steers currents from PGA or releases currents to PGA by evaluating the signal SIGN to eliminate the DC offset of its balanced branches [14]. Similar to the AGC detection principle, the sum of SIGN is calculated within 512 CLK, and recorded as \(M_{DCOC}\). Ideally, the DC offset is 0, and \(M_{DCOC}\)  
Figure 6: Simplified AGC and DCOC circuit diagram. Figure 7: PGA circuit where the resistors in the red box are owned only by PGA2. should be 256, with a duty cycle of 50%. When the receiver is powered on or the gain of the PGA is changed, DCOC is performed. The code C[11:0] starts from 100,000,000,000 and the dichotomy scan is used to make \(M_{DCOC}\) approach 256. The dichotomy process for DCOC is shown in Figure 9, where s represents the bit number of C[11:0]; that is, C[11:0] from the most to the least significant bit corresponds to s equals 0, 1, 2,..., 11. For example, D[11] corresponds to s equals 0, and D[10] corresponds to s equals 1. When \(M_{DCOC}\) equals 256 or s is beyond 10, the DCOC ends, as shown by the red line in Figure 9. In general, the probability of \(M_{DCOC}\) being exactly 256 is very low, so C[11:0] corresponding to s beyond 10 is the code that makes \(M_{DCOC}\) closest to 256. The Monte Carlo simulation is carried out at the PGA1 outputs to verify the performance of the DCOC circuit. The mean output DC offset of 6.9 mV and the 3\(\sigma\) variation of  
Figure 8: DAC circuit. Figure 9: Flow chart of the dichotomy search method for DCOC. \(-340\) to \(350\) mV are observed without DCOC. This means that PGA1 amplifies the offset voltage of the previous circuits to more than \(300\) mV, which makes DAC need a wide output range. PGA2 amplifies the residual after DCOC to ADC; this residual amplified to ADC needs to be smaller than the accuracy of ADC, so a high-accuracy DAC is needed. As a result, two six-bit DACs are adopted, one for coarse tuning and the other for fine-tuning, as mentioned above. Since the DAC is differential and the sum of the output currents of the DAC remains constant, the currents from DAC do not affect the common-mode voltage of the PGA outputs. When \(DCOC\_EN\) is 1, if the gain control code GC[5:0] is changed, the signal \(WORK\_DC\_RY\) is set to 0 and DCOC is executed. When the DCOC is complete, we set \(WORK\_DC\_RY\) to 1 and start the next AGC. If \(DCOC\_EN\) is 0, DCOC is not executed. So the signal \(WORK\_DC\_RY\) is first set to 0 and then set to 1 after 100 CLK. Then we start the next AGC. The mixed flow chart of AGC and DCOC is shown in Figure 10. When powering up, we initialize the DCOC first; that is, the signal \(INIT\_DCOC\_RY\) is set to 0, and when the DCOC initialization is complete, the signal \(INIT\_DCOC\_RY\) is set to 1. At the same time, because the DCOC is complete, the signal \(WORK\_DC\_RY\) is set to 1. The signal \(Gain\_3 dB\_EN\) determines whether the gain step is 1 dB or 3 dB. The timing diagram is shown in Figure 11.  
A four-bit flash ADC [7] with a resistor ladder is adopted. The PGA's differential outputs are shorted through resistors to obtain the common-mode voltage (i.e., \(V_{cm}\) in Figure 7). To reduce the ADC's quantization error, this common-mode voltage is used as the input of the resistor ladder. The simulation shows that the PGA can achieve a programmable gain range of 63.1 dB, and the output voltage range of DAC is \(\pm 398\) mV, covering the DC offset range observed at outputs of PGA1 without DCOC; moreover, the compensation voltage accuracy is less than 0.2 mV. Figure 6.0 Mixed flow chart of AGC and DCOC.