## 5 Discussion  
A fully differential LNA with transformer-based interstage matching networks for the K band in a 45 nm SOI process is presented. The methodology addresses the improvement of critical design trade-offs, allowing the design of a high-performance, low-power, and very compact LNA. This is accomplished thanks to the transformer-based matching network approach, which allows improved area use, as the transformers simultaneously act as RF chokes and as baluns at the input and output terminals to convert the SE signal into differential mode, and vice versa. In order to generate and equalize the desired transformer inductances a state-of-the-art tool was used following the proposal in [12]. In addition, a low-power LNA based on optimal current density selection is obtained, allowing the reduction of the nominal DC power supply from 0.9 V to 0.38 V, which results in a significant reduction in power consumption (which is more than halved). The circuit consumes a total power of 11.7 mW from a 0.38 V DC supply, and occupies an area of 0.15 mm\({}^{2}\) excluding pads. The LNA obtains a gain of 12.9 dB, a _NF_ of 2.2 dB with an IRL higher than 10 dB. Non-linearity simulations show the proposed circuit achieves a P\({}_{0.4B}\) of -7.3 dBm, and an OIP3 of 7 dBm. To validate the circuit, EM simulations, and Monte Carlo analysis results are presented as well. Compared to similar works available in the scientific literature, the results of the developed circuit achieve an excellent trade-off between gain, bandwidth, NF, power consumption, and area. In particular, the circuit presents a remarkably low power consumption and NF, obtaining the lowest values reported in a differential LNA compared to the state-of-the-art solutions. Although the reported results of our study demonstrate excellent performance there is room for further improvement. In this sense, future lines of work include the fabrication and measurement of the proposed circuit to validate the results, optimization of the second stage amplifier to improve gain and linearity, integration of the proposed LNA in a complete receiver or a real system, and improvement of the circuit PVT (Process-Voltage-Temperature) resilience.  
Methodology, J.M.C.-A., D.G.-S., S.L.K. and J.d.P.; Investigation, J.M.C.-A., D.G.-S., S.L.K. and J.d.P.; Supervision, S.L.K. and J.d.P.; Writing--original draft, J.M.C.-A. and D.G.-S.; Writing--review and editing, S.L.K. and J.d.P.; Visualization, J.M.C.-A., D.G.-S., S.L.K. and J.d.P.; Project administration, J.M.C.-A., D.G.-S., S.L.K. and J.d.P.; Funding acquisition, J.M.C.-A., D.G.-S., S.L.K. and J.d.P. All authors have read and agreed to the published version of the manuscript.  
This work has been partially supported by Grant PID2021-127712 OB-C21 funded by MCIN/AEI/10.13039/501100011033 and, by \"ERDF a way of making Europe\" and the Canary Agency for Research, Innovation, and Information Society (ACIISI) by the TESI2019010100 grant. Publication fees have been charged by the project ULPGC Excellence, funded by the Consejeria de Economia, Conocimiento y Empleo del Gobierno de Canarias.  
Not Applicable.  
The authors declare no conflict of interest.  
The following abbreviations are used in this manuscript:  
\begin{tabular}{l l} Balun & Balanced to Unbalanced \\ BW & Bandwidth \\ CAS & Cascade \\ CMOS & Complementary Metal Oxide Semiconductor \\ CMRR & Common Mode Rejection Ratio \\ CG & Common Gate \\ CS & Common Source \\ EM & Electromagnetic \\ FoM & Figure of Merit \\ \end{tabular}