###### Abstract  
Synthetic aperture radar (SAR) is a unique imaging radar system that is capable of obtaining high-resolution images by using signal-processing techniques while operating in all weather and in the absence of a light source. The potential of SAR in a wide range of applications has led to new challenges in digital SAR processor design. On-board storage of SAR raw data is often not practical for real-time applications. The design of digital SAR processors is always restricted by the available space of the carrier system, data transfer rate, payload capacity and on-board power supplies. As reported in the literature, although customized hardware solutions could offer the desired performance, they are not feasible for low-volume production. This research aims to design and develop an efficient digital SAR processor by using field-programmable gate array (FPGA) with the consideration of hardware resources, processing speed and precision. In this paper, a hardware implementation of an FPGA-based SAR processor is presented. The implementation and architecture of the proposed SAR processor are highlighted in this paper. A MATLAB-based SAR processing range-Doppler algorithm (RDA) was developed as the benchmark for the development of an SAR processor. The target device, Altera Stratix IV GX FPGA EP4 SGX230 KF40C2, was selected for the design and implementation of an FPGA-based SAR processor. Comprehensive evaluations of the performance of the proposed SAR processor in terms of precision, timing performance and hardware resource utilizations are also presented. The proposed FPGA-based digital SAR processor achieves optimum performance in processing SAR signals for image formation. Evaluation shows that the designed SAR processor is capable of processing SAR images with \(\pm 1\%\) difference error as compared to SAR images processed by MATLAB. The results also show a reduction in hardware usage via the implementation of an FPGA-based FFT/IFFT coprocessor. These promising results prove that the performance of the proposed processor is satisfactory and the achieved processing time, as well as the power consumption of the processor, outperformed existing implementations. s +
Footnote †: journal: Applied Sciences  
1 Faculty of Engineering & Technology, Multimedia University, Melaka 75450, Malaysia, [EMAIL_ADDRESS]  
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Interest in digital SAR processors began in the late 1970s. One of the earliest studies on data reduction using parallel processors was performed by Jet Propulsion Laboratory (JPL) in 1976 to produce SEASAT SAR imagery [6]. Another digital SAR processor was developed in 1978 by a company called MacDonald Dettwiler [7]. Although this processor was slower than its predecessors (it took hours to process a few seconds of data), it showed an improvement in image quality. Since then, digital systems have progressed in leaps and bounds. Advancements in processor technology promise not only faster but also more space- and energy-efficient digital processors. Another early work on the implementation of hardware architecture of digital SAR processors was introduced by [PERSON] and [PERSON] [8]. The authors proposed a multiprocessor single instruction multiple data (SIMD) architecture in order to meet the requirement of high computation throughput. The required processing parameters of the system is every 256 range lines of 2048 real samples must be processed in less than 3.2 s. In 1996, [PERSON], [PERSON] and [PERSON] designed a parallel SAR processor capable of processing high-resolution SAR data based on special-purpose digital-signal processors (DSP), general-purpose microprocessors and general-purpose DSP [9].