## 3 Results and Discussions
Figure 2: (**a**) Transfer characteristics at V\({}_{\rm{DS}}\) = 1.0 V (**b**) output characteristics at V\({}_{\rm{GS}}\) = 1.0 V with different \(\kappa\) values of spacers. Although the impacts of the spacer \(\kappa\) values on the electrical characteristics of the proposed tunnel FET is studied with the fixed spacer thickness of 10 nm, the effects of the spacer thickness variation should be evaluated when considering the process feasibility. Typical high-\(\kappa\) materials are formed by using atomic layer deposition (ALD), which is a thin-film deposition technique based on the sequential use of a gas phase chemical process. Since the ALD is a very time-consuming process, it has been generally considered for thin film less than 10 nm. If the thick spacer is required for high fringing field, it would be one of the most serious obstacles against mass production. Therefore, the sensitivities on the reduction of the spacer thickness are simulated for thickness optimization. Figure 4 shows the transfer characteristics with various spacer thicknesses. As the thickness increases, the drain current is improved from V\({}_{\text{GS}}\) = 0.35 V by the increased fringing field through the spacer and the improvement is saturated from thicker than 3 nm. It means that a too thick spacer is not necessary to get the high fringing field, and it is advantageous to use the ALD process. However, there are disadvantages when the high-\(\kappa\) spacer is applied. First, ambipolar current becomes increased due to the enhanced fringing field between gate and drain as well as between gate and source. Thus, with the larger \(\kappa\) values of the spacer, both on-current and ambipolar current are increased simultaneously (Figure 2a) although the drain-side underlap is used. Figure 5a shows the 2D contour on electron tunneling rate (off-state) with the spacer of \(\kappa\) = 3.9 and 25 at V\({}_{\text{DS}}\)/V\({}_{\text{GS}}\) = 1.0 V/\(-\)0.3 V. Compared to \(\kappa\) = 3.9, more electron tunneling is generated between the channel and the drain for \(\kappa\) = 25. The amount of the increased tunneling is around ten times in the case of the high-\(\kappa\) spacer (Figure 5b). Second, gate-to-drain Miller capacitance gets increasing due to the enhanced fringing field by using high-\(\kappa\) spacer. In tunnel FETs, the AC performance is limited by Miller capacitance effects, which induce voltage overshoot and undershoot in transient responses, unlike conventional MOSFETs [29]. It causes severe inverter delay. Therefore, the gate-to-drain capacitance is checked with respect to V\({}_{\text{GS}}\) for the different \(\kappa\) values of the drain-side spacer in Figure 6. To evaluate the impacts on the different \(\kappa\) values, the gate-to-drain capacitance is separated into each capacitance component. Except for inversion capacitance, the gate-to-drain capacitance consists of inner-fringing, outer-fringing, and direct overlap capacitance as parasitic capacitances. However, in this study, ideal junction is assumed so that direct overlap capacitance can be ignored. Hence, only the outer-fringing capacitance related to the \(\kappa\) values can be extracted when the channel is in accumulation (V\({}_{\text{GS}}=-1.0\) V). Figure 4: Transfer characteristics with various spacer thickness (1–5 nm) based on \(\kappa\) = 25. This is because the inner-fringing capacitance component can be removed by the accumulation charge layer. In the case of the spacer with \(\kappa\) = 25, the outer-fringing capacitance goes up by 78% compared to \(\kappa\) = 3.9, and the increase of this parasitic capacitance makes the switching characteristics worse. To improve the inverter delay caused by the large gate-to-drain capacitance, the tunnel FET with asymmetric spacers is proposed. The tunnel FET has the source-side high-\(\kappa\) spacer to boost the on-current, whereas the low-\(\kappa\) spacer is formed on the drain-side to decrease the ambipolar current and the outer-fringing capacitance.