## 4 Experimental Results and Analysis
### Performance Analysis  
The comparison of the total time taken, in case of an error, is compared for the hardware [20], GPU [8; 9], and hybrid architecture (proposed) in Figure 8 (the variable _be_ represents bit error). We can see that the hybrid approach was better than the GPU method because of the SRU implementation in hardware. However, the hardware implementation took less than 1 \(\upmu\)s because of the high performance (which is indistinguishable in Figure 8). We can observe a gain of more than 25% when the system has errors. We can find the probability of sector error from a given bit error rate using Equation (7). For a given \(P_{secError}\), the throughput was calculated for a second's worth of data transfer. \begin{table}
\begin{tabular}{c c c c c c c c c c c c} \hline \hline  & \multirow{2}{*}{**Setup**} & \multicolumn{8}{c}{**Area for \(t\) (\(\upmu\)m\({}^{2}\))**} \\ \cline{3-11}  & & **4** & **8** & **12** & **16** & **20** & **24** & **28** & **32** & **36** & **40** \\ \hline \multirow{2}{*}{**m = 12**} & [20] & 606 & 1287 & 2079 & 2871 & 3256 & 3661 & 3959 & 4252 & 4611 & 4917 \\  & Prop. & 853 & 1704 & 2550 & 3399 & 4209 & 5061 & 5903 & 6747 & 7592 & 8436 \\ \hline \multirow{2}{*}{**m = 13**} & [20] & 858 & 1863 & 2962 & 4043 & 4648 & 5246 & 5814 & 6387 & 6988 & 7573 \\  & Prop. & 924 & 1846 & 2767 & 3682 & 4607 & 5532 & 6390 & 7305 & 8308 & 9134 \\ \hline \multirow{2}{*}{**m = 14**} & [20] & 916 & 2002 & 3167 & 4330 & 5016 & 5723 & 6375 & 7048 & 7714 & 8390 \\  & Prop. & 994 & 1985 & 2976 & 3966 & 4966 & 5959 & 6948 & 7942 & 8935 & 9927 \\ \hline \multirow{2}{*}{**m = 15**} & [20] & 988 & 2172 & 3435 & 4707 & 5485 & 6292 & 7043 & 7818 & 8587 & 9367 \\  & Prop. & 1064 & 2125 & 3186 & 4249 & 5318 & 6383 & 7448 & 8504 & 9570 & 10,633 \\ \hline \multirow{2}{*}{**m = 12**,..., 15**} & [20] & 3368 & 7324 & 116,43 & 15,951 & 18,405 & 20,922 & 23,191 & 25,505 & 27,900 & **30,247** \\  & Prop. & 1064 & 2125 & 3186 & 4249 & 5318 & 6383 & 7448 & 8504 & 9570 & **10,633** \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Area comparison for different syndrome generators vs. the proposed SRU. \begin{table}
\begin{tabular}{c c c c c c c c c c c} \hline \hline  & \multirow{2}{*}{**Setup**} & \multicolumn{8}{c}{**Power for \(t\) (mW)**} \\ \cline{3-11}  & & **4** & **8** & **12** & **16** & **20** & **24** & **28** & **32** & **36** & **40** \\ \hline \multirow{2}{*}{**m = 12**} & [20] & 0.179 & 0.374 & 0.599 & 0.819 & 0.897 & 0.978 & 1.037 & 1.097 & 1.170 & 1.232 \\  & Proposed & 0.167 & 0.336 & 0.499 & 0.673 & 0.841 & 1.014 & 1.185 & 1.354 & 1.524 & 1.695 \\ \hline \multirow{2}{*}{**m = 13**} & [20] & 0.226 & 0.491 & 0.773 & 1.054 & 1.178 & 1.304 & 1.426 & 1.546 & 1.674 & 1.797 \\  & Proposed & 0.178 & 0.355 & 0.534 & 0.714 & 0.889 & 1.061 & 1.248 & 1.424 & 1.615 & 1.778 \\ \hline \multirow{2}{*}{**m = 14**} & [20] & 0.231 & 0.503 & 0.784 & 1.068 & 1.213 & 1.363 & 1.499 & 1.640 & 1.780 & 1.923 \\  & Proposed & 0.187 & 0.373 & 0.561 & 0.747 & 0.938 & 1.122 & 1.309 & 1.493 & 1.678 & 1.863 \\ \hline \multirow{2}{*}{**m = 15**} & [20] & 0.235 & 0.512 & 0.812 & 1.110 & 1.270 & 1.438 & 1.593 & 1.755 & 1.915 & 2.078 \\  & Proposed & 0.194 & 0.388 & 0.588 & 0.776 & 0.975 & 1.168 & 1.370 & 1.564 & 1.755 & 1.953 \\ \hline \multirow{2}{*}{**m = 12**,..., 15**} & [20] & 0.692 & 1.506 & 2.369 & 3.232 & 3.661 & 4.105 & 4.518 & 4.941 & 5.369 & **5.798** \\  & Proposed & 0.194 & 0.388 & 0.588 & 0.776 & 0.975 & 1.168 & 1.370 & 1.564 & 1.755 & **1.953** \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Power comparison for different syndrome generators vs. the proposed SRU. Figure 9 represents the plot for throughput vs. bit error rate for different finite fields (\(m=12,13,14,15\)) and different \(t=4,...,40\). We can see that for \(m=12,13\), the throughput was sustained till \(10^{-3}\), and for \(m=14,15\), the throughput was sustained till \(10^{-3.5}\).