## 3 Unit Cell and MS Reflector Concept and Design
This point is demonstrated in Figure 5c. For standard mushroom unit cell configuration, reducing the distance between the patch's edges compared to the varactor length dimension allows the varactor assembly directly on the patches' edges. But, it increased the \(C_{int}\), which impaired the ability and quality of the realization for the X-band frequencies and above. Thus, the varactor diodes were placed between the unit cells' patches on the customized pads according to the layout of the varactor, which required the proper design of vertical lines from the patches to the customized pads, as shown in Figure 5b. To overcome this limitation, the varactor diodes were placed between the unit cells' patches on the customized pads according to the varactor layout, which required the proper design of vertical lines from the patches to the pads, as shown in Figure 5b. The maximum and minimum values of the diode capacitance for three voltage states (0, 4, and 15 volts) are given in the datasheet without providing a typical value. As a result, there is a non-uniformity in the simulation-defined \(C_{max}\) and \(C_{min}\) capacitance values in published works that use this diode. For example, in [43], \(C_{max}=0.27\) pF and \(C_{min}=0.032\) pF; in [44], \(C_{max}=0.19\) pF and \(C_{min}=0.025\) pF; and in [45], \(C_{max}=0.25\) pF and \(C_{min}=0.033\) pF. These varactor capacitance values are critical for design considerations. Therefore, for reducing uncertainty in the varactor capacitance values, the average capacitances values of \(C_{max}\) and \(C_{min}\) are 0.21639 pF and 0.03258 pF, respectively, and were provided after contacting MACOM. A good agreement was obtained in our previous work between the measurements and the simulations based on the provided average capacitance values [18]. The varactor edges' capacitance values' tolerance was considered in the unit cell's design stage, which minimized its effect. In addition, the varactor has a constant gamma around one, which allows for linear tuning within the reverse bias voltage range of 2 to 12 V [42], as shown in Figure 6.  
Figure 6: Varactor capacitance values \(C_{d}\) as a function of the reverse bias voltage in log scale. A prototype based on this unit cell was manufactured. This prototype allowed one-dimensional reflection phase control, where each column was separately stimulated with a DC bias. A photo of the prototype is shown in Figure 7.  
Figure 7 shows the manufactured 40-row and 33-column MS, summing up to 1320 unit cells. The MS area sizes were 185 mm \(\times\) 140.6 mm (7.4\(\lambda_{0}\)\(\times\) 6.2\(\lambda_{0}\) in wavelength units at 12 GHz). The design of the MS prototype bottom layer, which functioned as the varactor DC biasing layer, is shown in Figure 8 with a reduced number of lines for convenience. The vias (shown in green) were shortened by vertical DC lines for each unit cells column on the prototype biasing layer. Thus, all odd columns were connected to a common DC ground, and each even column was connected to a separate independent DC voltage of \(V_{1}\) to \(V_{16}\). The stimulation voltages \(V_{1}\) to \(V_{16}\) to the varactors in each even column were supplied by an inexpensive programmable DAC model AD5766 from Analog Devices, shown in the left part of Figure 7. This DAC has 16 channels with a 12-bit resolution and a dynamic range of 0 to 16 V. The use of a varactor as a tuning method enabled very high capacitance resolution. However, there was a practical limitation on the reflection phase resolution due to the DAC resolution, which was \(\Delta DC\) = 3.9 mV. Figure 8: Scheme of a varactor DC biasing layer. Figure 7: The prototype front side with a zoom-in view on the varactor which is located between each two adjacent unit cells. On the left is the DAC for the DC voltage bias.