## 3 Doherty Power Amplifier Circuit Design
### Thermal Management  
(1) Chip layout-level thermal analysis:  
Due to the large layout size of PA power cell core, the parasitic parameters including resistance, capacitance, and inductance between sub-cells affect the performance of the whole chip die greatly. Also, because of the high saturated power, thermal coupling between transistors brings a big thermal design challenge. In order to push the performance to the limit of transistor, the geometry of layout should be optimized to decrease the parasitic effect and thermal coupling.  
Common state-of-art solutions to such thermal design challenges include increasing the size of thermal bars and improving the heat dissipation environment to avoid heat spot breakdown and adopting novel power devices [13]. In layout design, optimizing the cooling environment can be achieved by changing the spacing or length of fingers and constructing a strong ground thermal path to obtain a uniform temperature distribution of the power cells [14; 15; 16].  
In this work, two kinds of different layout geometries in power cell are presented, as show in Figure 9a. The conventional layout shows the merits of easy connection and signal isolation between transistors, but it leads to the risk of heat spot in the layout, thus burning the transistors under certain conditions. The main concept of layout configuration in this study is the geometrical thermal isolation of power sub-cells. As illustrated in Figure 9b, the power sub-cells are divided into smaller sizes with strong ground surrounding. Although the connection of this layout structure is complex and brings more parasitic capacitance, it can be solved by careful layout and accurate parasitic extraction. As shown in Figure 10, this layout geometry shows an overwhelming advantage of average thermal distribution with lower working temperature. The thermal performance is simulated by heatwave software provide by Agilent Corporation. By distributing the power sub-cells, the maximum operating temperature of the power transistors is decreased by 25 \({}^{\circ}\)C when the PA is in saturated operation with a continuous wave signal.  
Figure 9: Comparison of different power cell layout geometries. (a) Conventional structure and (b) distribution structure.  
(2) System-level thermal analysis:  
Thermal analysis in package systems presents increased complexity, requiring consideration of thermal dissipation variations across different technologies and architectures, alongside reliability, cost, and manufacturing consistency factors. As illustrated in Figures 11 and 12, two primary packaging technologies emerge: bond-wire and flip-chip configurations, with their thermal and characteristic comparisons detailed in Table 1. The flip-chip approach demonstrates distinct advantages, offering superior thermal dissipation performance and enhanced manufacturing consistency compared to traditional wire-bonding methods. Thermal performance is particularly important in high-power applications like 5G, where amplifiers can generate significant heat. Effective thermal management solutions, such as thermal vias and heat sinks, can be integrated within the packaging design to ensure reliable operation.  
Figure 11: Bond-wire technology in chips.  
Figure 12: Flip-chip technology in chips.  
Figure 10: Thermal simulation results of the power cells. (**a**) Conventional structure and (**b**) distribution structure.