###### Abstract
The authors showed that general-purpose-micoprocessor-based SAR processors offer greater flexibility, keeping the development cost low. Meanwhile general-purpose DSP-based SAR processors offer the highest performance. However, the tradeoff is less flexibility, requiring more design work to be done. In 2002, [PERSON], [PERSON], [PERSON] and [PERSON] introduced a DSP hardware implementation of an SAR raw data compressor [10]. The processor consists of two main modules, which are generic array logic (GAL) and in-system programmable large scale integrated circuit (ISPRSIC), in order to maintain system flexibility and ease of maintenance. The overall processor allows the main data to be processed in DSP. In 2004, a novel generation of compact airborne SAR on-board processor was introduced by [PERSON], [PERSON], [PERSON], [PERSON] and [PERSON] [11]. The processor uses a wavenumber domain algorithm to further reduce the output data rate in the SAR raw data processing cycle. The SAR processor is a system on chip (SoC) that maps and integrates the entire SAR processing chain into a single semiconductor chip. In recent years, commercial off-the-shelf (COTS) components have gained popularity in SAR applications. [PERSON] and [PERSON] demonstrated the use of a low-power multicore digital signal processor for the application of SAR [12]. However, the demanded parallelism processing of the SAR data can be achieved via multicore DSP instead of single-chip. Since SAR is a remote sensor used for global coverage and monitoring, it generates a large amount of SAR raw data via the receiver. For instance, ERS-1 SAR, launched by the European Space Agency (ESA) in 1991, generated few hundred MBs of SAR raw data for a duration of 10 s. The generation of two-dimensional images from SAR raw data by using SAR signal-processing techniques is a highly computationally intensive task. It demands heavy computational power and large memory for operations. Therefore, using a general computer is not an optimized implementation, as the required processing power cannot be achieved by a sequentially working single-processor system. With the development of wideband technology signal- and information-processing technology, radar coverage, detection accuracy and resolution have been greatly improved in SAR imaging technology. Meanwhile, for the application of radar detection and remote sensing with high resolution and wide swath, the amount of data has been greatly increased. Therefore, the radar is required to have low latency and real-time processing capability under the constraints of size, weight and power consumption [13]. Exploitation of parallelisation by splitting the algorithm into independent and isolated data blocks in order to achieve parallel processing is an essential implementation. Therefore, improvement of the hardware implementation of SAR processors is needed due to inflexibility of customised hardware solutions, as well as stringent space and power requirements in the SAR platform. An FPGA-based system is one of the best choices for hardware implementation of an efficient digital SAR processor due to its flexibility, reconfigurability and exploit pipelining [14]. An FPGA-based system is able to fulfil the demands of massively parallel processing, lower power consumption and smaller form factor. Bases on all of the mentioned advantages of an FPGA-based system, it is beneficial to select an FPGA-based system for the implementation of SAR processors in this research work. This research was developed based on an unmanned aerial vehicle (UAV) SAR operating in monostatic configuration with the transmitting antenna and receiving antenna collocated. Therefore, RDA is the most suitable algorithm [15]. The major contribution of this research work is the development and establishment of an efficient airborne digital SAR signal processor using FPGA. The proposed FPGA-based digital SAR processor achieves optimum performance in processing SAR signals for image formation.