# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 5 Saving Power by State Assignment
Also, it gives a switching activity equal to 1.357. After swapping codes for pairs of states \(\langle a_{5},a_{2}\rangle\) and \(\langle a_{3},a_{7}\rangle\), the sum is equal to 15 and the average switching activity is equal to 1.19. Obviously, the less switching activity there is, the less the power consumption. In [122], some results of experiments were shown. The system SIS [36] was used to calculate power consumption. The results were compared with results obtained using one-hot approach, JEDI, NOVA, and the one-level tree (OLT) algorithm [83]. The calculations were performed for the benchmarks from [82], with \(V_{dd}\) = 5 V and \(f_{op}\) = 20 MHz. The results of these experiments showed the following values of power consumption and area (Table 2). \[\omega_{m,s}=(1-\alpha)\omega_{m,s}^{area}+\alpha\omega_{m,s}^{power}. \tag{14}\]5 Undirected weighted graph for dk27 [122]. \[\omega_{m,s}=(1-\alpha)\omega_{m,s}^{area}+\alpha\omega_{m,s}^{power}. \tag{14}\]6 Binary tree for dk27 [122] (**a**) and Karnaugh map with state codes (**b**). These results show that the method in [122] provides the minimum power consumption for the benchmarks from [82]. At the same time, the minimum area is provided by JEDI. The worst area characteristics are provided by the one-hot approach, whereas the maximum power is consumed by NOVA. We can evaluate the overall efficiency of an algorithm by finding the product \"Area \(\times\) Power\". In the discussed case, the following values of this product were found: \(48.9\times 10^{6}\) for one-hot, \(25.4\times 10^{6}\) for JEDI, \(44.6\times 10^{6}\) for NOVA, \(31.02\times 10^{6}\) for OLT, and \(25.8\times 10^{6}\) for [122]. A comparison these products show that both JEDI and [122] produce practically the same results. All discussed state assignment methods are deterministic. To optimize power consumption in FPGA-based circuits, it is necessary to minimize the switching activity of flip-flops. This reduces the dynamic power consumption. To reduce the static power, it is necessary to reduce the chip area occupied by an FSM circuit. The chip area is determined by the number of LUTs and their interconnections. As noted in [92], the deterministic algorithms \"are far from being optimal\". To improve the power consumption, various nondeterministic evolutionary methods have been developed. A survey of them can be found, for example, in [94]. All these methods deal with NP-complex problem, where NP stands for nondeterministic-polynomial time [123]. In [124], a genetic algorithm is proposed. For a given FSM, the algorithm optimizes the chip area occupied by its circuit. To get the optimal result, this algorithm uses a fitness function to evaluate the resulting chip area. In another genetic algorithm [125], the authors use literal counts as a cost function. In [93], both literal count (for area) and switching probability (for power) are used as an approximate cost function. In [111], the genetic algorithm optimizes both static and dynamic power consumption. To do it, the algorithm uses a fitness function based on the number of product terms, the switching activity, and Hamming distance among pairs of state codes. In [87; 126], a genetic algorithm tries to optimize both static and dynamic power consumption. In [127], a multiobjective genetic algorithm optimizes both the area and power. To create a fitness function, it uses the number of product terms, the switching probability for state pairs, and the Hamming distance among pairs of states. Some algorithms are based on simulated annealing for optimizing area and/or power. In [128], the approximate fitness function is used to optimize the area. In [129], both area and power are optimized. To do it, a fitness function is based on three characteristics: (1) the number of product terms, (2) the switching probability for state pairs, and (3) the Hamming distance. Also, approaches such as binary particle swarm and cuckoo search are used for optimizing the static power consumption (the circuit area) [130; 131].