# A Review of Advanced CMOS RF Power Amplifier Architecture Trends for Low Power 5G Wireless Networks
## Advanced RF PA Architectures
### Traveling Wave RF PA (TWA)  
One particularly effective topology for enhancing communication speed and bandwidth is called distributed amplifier (DA), which is also known as the traveling wave amplifier (TWA). A simplified TWA/DA diagram is presented in Figure 6. Due to cost and integration considerations CMOS offers a higher level of integration at a lower cost compared with other high-speed semiconductor technologies such as _GaAs_ and _SiGe_. Distributed amplification is considered as a major technique for broadband PAs and with the scaling of CMOS process the achievable unity power gain frequency \(f_{\mathrm{t}}\) is tops 100 GHz and allows one to design microwave or millimeter wave amplifiers [53]. The theoretical maximum _PAE_ of the conventional TWA can be expressed as  
\[\eta_{PAE,\mathrm{max}}<\left(1-\frac{1}{A_{\mathrm{v}}}\right)\cdot\frac{1}{8 }n\frac{Z_{0}}{R_{L}} \tag{4}\]  
where \(A_{\mathrm{v}}\) is the gain of a single TWA segment, \(Z_{0}\) is the characteristic impedance of the RF chain, \(R_{L}\) is the load impedance, \(n\)--number of TWA segments. However, a conventional TWA has disadvantages; half of the input power is wasted in the left termination of drain transmission line and each FET operates under different efficiency conditions. Another issue is the noise of the input termination. For maximum power transfer, a 50 \(\Omega\) passive resistor is usually employed in to terminate the input transmission line of the low noise TWA [54]. A summary of papers reporting TWA research results and parameter improvement solutions in CMOS process is presented in Table 5. The reported TWA topologies can be divided into two main groups: conventional and cascaded single-stage (CSSDA). CSSDA topology reports the highest bandwidths of up to 30 GHz in micro-scale processes and up to 80 GHz in nano-scale processes. The TWA is the only advanced PA architecture (comparing ET/EER, DPA and outphasing architectures), which clearly emphasizes an increase in one or several of its parameters (in this case the bandwidth) when shifting to smaller CMOS process scale. Moreover, CMOS TWAs are on par with _III-V_ semiconductor based ones bandwidth-wise, which makes CMOS even more attractive in the design of low power (nano-, pico-, femto-cells) cells and which subsequently further aids the affordability of small scale CMOS process development. Although, at the same time, reported TWA papers concentrate on increasing bandwidth and rather than increasing _PAE_. This sets the TWA _PAE_ at a level, which is directly dependent upon the biasing class of each segment. TWA architecture advantages:  
1. Very high bandwidth. TWA architecture provides an unprecedented bandwidth comparing all other advanced PA architectures;
2. Can be implemented in both discrete form and integrated into an ASIC. The unmatched bandwidth of the TWA is achieved using both discrete components, a combination of discrete components and PCB microstrips as well as integrated into an ASIC;  
Figure 6: Simplified TWA architecture diagram. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Ref.** & **Process** & **\(V_{\text{DD}}\), V** & **Frequency Range, GHz** & **Gain, dB** & **NF, dB** & **Topology** \\ \hline
[55] & 180 nm CMOS & 2.8 & 1.5-35.5 & 25 & 6.5-8 & CSSDA \\ \hline
[54] & 180 nm CMOS & 1.8 & 0.1-12 & 16 & 0.9-3.8 & Conventional \\ \hline
[56] & 130 nm CMOS & 2.4 & 0.05-32.5 & 8.8 & – & Conventional \\ \hline
[57] & 130 nm CMOS & 1.2 & 3-10 & 14 & 1.8-3.3 & Conventional \\ \hline
[58] & 90 nm CMOS SOI & 2 & 0.1-25, 0.1-40 & 10.8 & 4.5-9 & Conventional \\ \hline
[59] & 90 nm CMOS & 2.2, 15, 0.66 & DC-40 & 14 & 6–8 & Gate-drain transformer coupling \\ \hline
[60] & 65 nm CMOS & – & DC-70 & 25 & 5-7.5 & LC-CSSDA \\ \hline
[61] & 65 nm CMOS & 2.4 & 4.7-11.7 & 12 & – & Conventional \\ \hline
[62] & 40 nm digital CMOS & 1.7 & DC-80 & 15 & – & CSSDA \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Summary of reviewed TWAs in CMOS process.