# Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol
## 4 Results and Comparisons
### Comparisons with State-of-the-Art  
The ECPM designs of [12; 17; 19] support only the PM operation, without the consideration of the topmost layer of ECC (protocol layer). In other words, there are very few hardware designs that enfold the implementation of ECDH protocol on a reconfigurable FPGA. The comparison to state-of-the-art architectures is shown in Table 3. Column one indicates the reference to existing hardware implementations of the ECDH protocol. Column two offers the implemented ECC model in addition to the used algorithms for the execution of either public or shared key generation. The targeted FPGA device used for the \begin{table}
\begin{tabular}{c|c|c|c|c|c|c|c|c|c} \hline \multirow{2}{*}{**Device**} & \multicolumn{2}{c|}{**Utilized Area**} & \multicolumn{2}{c|}{**Public Key**} & \multicolumn{2}{c|}{**Shared Key**} & \multirow{2}{*}{**FoM**} \\ \cline{2-3} \cline{5-10}  & **Slices** & **LUTs** & **FFs** & & & **CCs** & **Lat (in \(\upmu\)s)** & **CCs** & **Lat (in \(\upmu\)s)** & \\ \hline Virtex-7 & 5102 & 12,339 & 2459 & 318 & 4942 & 15.54 & 9886 & 31.08 & 6.30 \\ Spartan-7 & 5634 & 12,891 & 2463 & 312 & 4942 & 15.83 & 9886 & 31.68 & 5.60 \\ Artix-7 & 5957 & 13,105 & 2461 & 316 & 4942 & 15.63 & 9886 & 31.28 & 5.36 \\ Kintex-7 & 6102 & 13,258 & 2466 & 304 & 4942 & 16.25 & 9886 & 32.51 & 5.04 \\ \hline \end{tabular}  
* Lat: determines the time (or latency) to compute either one public or shared key.  
\end{table} 
Table 2: Implementation results after place-and-route over \(GF\)(\(2^{233}\)) on different FPGA devices. implementation is shown in column three. We have evaluated the FPGA slices for hardware resource comparisons. The corresponding hardware resources are presented in column four. The timing details (in terms of clock frequency (MHz) and latency (\(\upmu\)s)) for generating a single shared key are presented in the last two columns (five and six) respectively. Comparison with [17; 19; 31] over \(GF(2^{163})\) on Virtex-7 and Kintex-7 FPGA. On Virtex-7 FPGA, our ECDH architecture takes 2.28 (ratio of 11,657 over 5102) times lower FPGA slices as compared to the low-latency ECPM design of [17]. Moreover, our design with a 233-bit key length achieves a 2 (ratio of 318 over 159) times higher clock frequency. When comparing the latency, the architecture of [17] is 5.49 (ratio of 15.54 over 2.83) times more efficient as compared to our work. The reason for this efficiency is the different supported key lengths (233 in our work while a 163 in [17]--see column two in Table 3). Another ECPM architecture on Virtex-7 is reported in [19]. Due to distinct key lengths, their design consumes lower FPGA slices (3657) when compared to our 233-bit design (5102). On the contrary, our ECDH architecture achieves 2.35 (ratio of 318 over 135) times higher clock frequency. Additionally, the ECPM design of [19] requires 2 (ratio of 25.3 over 15.54) times higher computational time (latency) as compared to our ECDH design. On Kintex-7 FPGA, the architecture of [31] utilizes 2.70 (ratio of 6102 over 2253) times lower FPGA slices as compared to our Kintex-7 implementation. The cause for the use of lower slices in [31] is the use of lower key-length (i.e., 163). An additional reason is the use of a simple Double and Add PM algorithm which is vulnerable to simple power analysis attacks (a type of side-channel attack) for the general Weierstrass form of elliptic curves. On the other hand, we employed a Montgomery PM algorithm which is inherently subjected to simple power analysis attacks even if the Weierstrass form of elliptic curves is used. Although we utilize a higher key length (i.e., 233), our design achieves a comparable clock frequency of 304 MHz while 306 MHz is obtained in [31] over a 163-bit key length. Moreover, our proposed PM architecture requires lower computational time because we used projective coordinates for the execution of PM operation whereas a simple affine coordinate system is used in [31]. Comparison with [12] over \(GF(2^{233})\) on Virtex-7 FPGA.