## 1 Introduction
### Low-Area Hardware Implementations with Limitations  
Concerning the aforementioned selections, several PM ECC designs exist in the literature; however, we preferred to include only those implemented and optimized for area-efficient realizations. Examples of the most recent hardware accelerators are available in [12; 13; 14; 15; 16; 17; 18]. A two-stage pipelined PM architecture of ECC is described in [12], where pipelining is utilized to decrease the critical path delay and carefully schedule the computations associated with PA and PD to reduce the number of clock cycles required; these two characteristics combine to decrease the time needed for a single PM operation, and the minimum utilization of area results in a higher throughput/area ratio. For \(GF(2^{233})\), the implementation results on Virtex-7 demonstrate that their design can operate at frequencies of up to 369, 357, and 337  MHz for \(m=163\), 233, and 283 bit key lengths, respectively. Similarly, another two-stage pipelined architecture is designed in [13] to reduce overall computation time by rescheduling PA and PD instructions. The hardware resources are reduced by efficiently utilizing memory locations and employing a digit-serial multiplier with a digit length of 41 bits. The FPGA and ASIC implementation results are provided and compared to state-of-the-art implementations, demonstrating their proposed accelerator's significance in latency and area. An efficient hardware implementation of a 256 bit ECC processor over a \(GF(P)\) is presented in [14], where Jacobian coordinates have been utilized to avoid the costly modular inversion operation. In addition, an interleaved modular multiplier reduces the area and delay in modular multiplication. The PA and PD design is realized with the minimum arithmetic unit, utilizing the efficient modular multiplier algorithm. The implementation results are reported on FPGA. A low-area efficient implementation of ECC over \(GF(2^{163})\) is described in [15], where authors investigate area--time and area--2-time performances utilizing a digit serial multiplier architecture on different FPGA devices. Moreover, an 8 bit input-output interface is utilized for low-cost cryptographic applications and can easily be embedded with 8 bit processors. Their Montgomery PM implementation on Virtex-5 shows the best result, achieving 0.11 ms using only 473 slices in the area. Another low-area PM implementation is illustrated in [16], where a Lopez Dahab PM algorithm is used over \(GF(2^{163})\). On different FPGA devices, they have realized low area using a bit parallel hybrid Karatsuba multiplier; they implemented the hybrid multiplier using a simple Karatsuba multiplier for multiplying longer bits, whereas they generated simple partial products to execute multiplication on smaller bits. Specific to wireless sensor nodes, we found an interesting work in [17], where an ECC-based crypto engine is described over \(GF(2^{233})\). The crypto engine targets digit-by-digit computations to execute finite field arithmetic operations of ECC. In addition, they have reused the hardware resources of the targeted FPGA device to keep less area. The crypto engine has been validated through hardware/software codesign of the Diffie-Hellman key exchange protocol deployed in the IoT MicroZed FPGA board. For PM computation over 233 bit key length, their design utilizes 442 slices and executes one PM computation in 15,53,782 clock cycles at 190 MHz. We found another compelling work in [18], where the authors utilize a coprocessor design technique to obtain the advantages of symmetric and PKC simultaneously. More precisely, an advanced encryption standard (AES-128 [19]) algorithm is incorporated to perform the symmetric cryptography; ECC over \(GF(2^{163})\) is utilized to operate elliptic-curve operations for PKC; and a secure hash algorithm (SHA-256) is considered to perform a hash computation for digital signature, authentication, and random-keys generation--they used a MicroBlaze processor to supervise these coprocessors.