## 2 Materials and Methods  
A standard FF was designed to act as reference when comparing data between the proposed DICE designs. This reference design used master and slave latches with clocked transmission gates, as shown in Figure 2.  
The latches used in the reference design were standard back-to-back inverters. The proposed FF designs presented in this paper used a similar master-slave design, except that in each DICE design, the back-to-back inverter latches were replaced with the respective DICE latches. Note that DICE stored both the original data and the complemented version of the data in the cell. Nodes A1 and A3 stored the uncomplemented data, whereas nodes A0 and A2 stored the complemented version. In the design of DICE-based FFs, both versions of the data need to be available so to be written into the cell; therefore, the flip-flop designs were modified with the addition of extra transmission gates and. A schematic of the DICE flip-flop design is shown in Figure 3.  
The figure above shows the DICE schematic that all three proposed designs in this work followed. Note that for the three proposed designs, any changes were only introduced in the DICE latch and not in the rest of the flip-flop circuitry. As previously discussed, DICE has intrinsic single-node upset immunity due to the inherent interlocked feedback loops present within the circuit. However, the charge track caused by a single ionized particle could still affect two or more adjacent transistors when the spacing between adjacent devices is small enough, even for the FD SOI technology. This scenario could worsen with angular particle strikes that are likely to impact more than one transistor at a time. For example, if nodes A1 and A2 are placed next to each other in the layout, an angular particle strike could cause a SET at both nodes, thus flipping the data stored in the cell. It is therefore beneficial to add additional hardening techniques to a DICE design. Transistor interleaving purposely separates transistors that share a common input to different location in the layout to help prevent multiple sensitive nodes from being struck at the same time. Only a particle with a sufficiently large Linear Energy Transfer (LET) at a steep incidence angle would be able to strike both nodes. This type of layout hardening  
Figure 3: Master–slave flip-flop design with DICE latches presented in this work. Figure 2: Reference master–slave flip-flop design using standard back-to-back inverter latches. does make the routing of metal layers slightly more complex, but the performance penalties are expected to be limited. Shown in Figure 4 is a comparison between a non-interleaved DICE latch design and an interleaved design. In the interleaved design, the second and third inverters were swapped to increase the distance between sensitive nodes. In real designs, the actual spacing between adjacent sensitive nodes may be larger or smaller depending on the inclusion of other logic elements or other layout changes. All presented DICE designs in this article made use of the interleaved layout shown in Figure 4b. The 22 nm FDSOI technology node makes use of Embedded Silicon Germanium (eSiGe) in the channel of PMOS transistors to help enhance their performance [14]. However, the Length of the Oxide (LOD) diffusion can reduce the performance benefits gained by the inclusion of the eSiGe. When the lengths of the active diffusion layer on each side of the gate of the device are too short, the mobility of holes becomes reduced [15]. In order to have competitive standard cell designs for dense logic applications in the 22 nm FD SOI node, the Continuous Active (CnRx) diffusion construct can be used. In this construct, the active diffusion layer for PFET devices in a standard cell are kept continuous with no breaks in the layout. This helps retain the performance benefits that eSiGe offers.