## 4 The Development of the Bit-Serial Systolic Array  
To establish the bit-serial systolic array layout, it is necessary to carefully determine the suitable scheduling and projection vectors for the dependency graphs (DGs). Following the method outlined in previous works [13; 34; 35], we can select the scheduling vector, denoted by \(\mathbf{S}\), and the projection vector, denoted by \(\mathbf{P}\), that will effectively guide the design of the serial systolic structure [36; 37]. Specifically, the recommended vectors are \(\mathbf{S}=[2\ -1]\) and \(\mathbf{P}=[1\ 0]^{T}\). Through the application of these vectors to the individual DG nodes \(\mathbf{p}(i,j)\), we are able to derive the associated scheduling function, referred to as \(t(\mathbf{p})\), in addition to the projection function, denoted by \(PE(\mathbf{p})\), as illustrated below. These functions play crucial roles in assigning time values to each DG node and mapping them to the appropriate PE within the systolic array [13; 34; 35]. Through this integration of scheduling and projection functions, the efficient coordination and execution of computations are achieved within the serial systolic array framework [36; 37]. \[t(\mathbf{p})=2i-j \tag{13}\]  
\[PE(\mathbf{p})=i \tag{14}\]  
The application of the scheduling function \(t(\mathbf{p})\) on the DGs yields the node timing depicted in Figures 3 and 4. These timing values demonstrate the sequential progression of input application and the subsequent generation of DG products. In a step-by-step manner, the input bits \(c_{k-1-j^{\prime}}\), \(f_{k-1-j^{\prime}}\), \(c_{j}\), \(f_{j+1}\), \(a_{k-1-j^{\prime}}^{0}\), and \(b_{j+1}^{0}\) are successively applied, where \(0\leq j\leq k-1\). As a result, the corresponding output bits \(a_{k-1-j}^{(k+1)/2}\) and \(b_{j}^{(k+1)/2}\) are generated. Notably, output \(A\) is computed from the most significant bit (MSB), \(a_{k-1}^{(k+1)/2}\), at time \(k-1\), and progresses to the least significant bit (LSB), \(a_{0}^{(k+1)/2}\), at time \(2k-2\). Similarly, output \(B\) is computed from the LSB, \(b_{0}^{(k+1)/2}\), at time \(k-1\) and progresses to the MSB, \(b_{k-1}^{(k+1)/2}\), at time \(2k-2\). Figure 3: Node timing for \(k=5\). Figure 5 visually depicts the extracted layout of a serial-in/serial-out (SISO) systolic array, which is achieved by applying the projection function \(PE(\mathbf{p})\) to the dependency graphs (DGs). The structure consists of two identical processor arrays, one for the serial computation of coefficients of \(A\) and the other one for the serial computation of coefficients of \(B\). The upper processor array produces the coefficients of output \(A\), \(a_{k-1-j}^{(k+1)/2}\), in a serial fashion and stores them in the upper shift register shown in Figure 5. The lower processor array produces the coefficients of output \(B\), \(b_{j}^{(k+1)/2}\), \(0\leq j\leq k-1\), concurrently with the coefficients of \(A\) and stores them in the lower shift register shown in Figure 5. Notice that bits \(a_{k-1}^{i}\) and \(b_{0}^{i}\) are held in a latch inside the PEs for the proper computation of coefficients \(A\) and \(B\). Therefore, they have a separated serial bus from the remaining coefficient bits, as indicated in Figure 5. Also, the resulting bits \(a_{k-1}^{(k+1)/2}\) and \(b_{0}^{(k+1)/2}\) are stored in a separate latch from the output shift registers to avoid the disordering of the resulting coefficient bits. In order to obtain the final product \(P\), the corresponding bits of coefficients \(A\) and \(B\) are XORed, as illustrated in Figure 5. The processor structure comprises \(k+1\) processing elements (PEs) and operates over a span of \(2k-2\) clock cycles to generate the ultimate output \(P\). Features of the \(A\) and \(B\) PE logic are shown in Figures 6 and 7. Upon closer examination of the SISO systolic arrangement, it becomes apparent that the input signals \(d_{k-i}\) and \(d_{i-1}\) are assigned to their respective PEs.