# A 5 Gb/s Optoelectronic Receiver IC in 180 nm CMOS for Short-Distance Optical Interconnects
## 3 Chip Layout and Post Layout Simulation Results  
Figure 7 presents the layout of the CORIC by using a cost-effective 180 nm CMOS process, incorporating two integrated P\({}^{+}\)/N-well APDs. The upper APD, which is only the actual APD, functions as the light-receiving area, while the bottom APD (i.e., dummy APD) is shielded by a metal layer. Consequently, incoming optical pulses are detected by the on-chip APD, which then converts them into photocurrent signals. The chip area is 260 \(\times\) 101 \(\upmu\)m\({}^{2}\), and the DC analysis indicates a power consumption of 33.7 mW from a 1.8 V supply. Figure 8 illustrates the simulated frequency response of the CORIC, revealing a transimpedance gain of 53.2 dB\(\Omega\) and a \(-\)3 dB bandwidth of 4.83 GHz. The simulation was conducted with the input capacitance set to 490 fF. Notably, a 3 dB peaking is observed near the bandwidth, which might be attributed to the inductive peaking effect introduced by the cross-coupled active loads. Figure 6: Schematic diagram of the \(f_{T}\)-doubler. Figure 7: Layout of the proposed CORIC. Also, a high bandwidth can be acquired by using the CTLE and the \(f_{T}\)-doubler. Furthermore, the CORIC achieves an average noise current spectral density of 47.9 pA/\(\sqrt{Hz}\) within the bandwidth, which corresponds to the optical input sensitivity of \(-25.9\) dBm for a \(10^{-12}\) bit-error-rate (BER) with the assumption of 2.72 A/W APD responsivity [10]. Figure 9 presents the simulated eye diagrams of the proposed CORIC for an input current of 300 \(\mu\)A\({}_{\text{pp}}\) at various data rates of 1 Gb/s and 3 Gb/s, respectively. These results clearly demonstrate that the output amplitudes of the eye diagrams remain consistent across all data rates. Figure 10 shows the simulated pulse response of the CORIC for the input currents ranging from 1 \(\mu\)A\({}_{\text{pp}}\) to 1 mA\({}_{\text{pp}}\). These results confirm that the CORIC achieves an input dynamic range of 60 dB, especially with the aid of a 3-bit DAC gain control mechanism in the CTLE. Also, employing \(f_{T}\)-doubler not only enables the DC offset cancellation at the output nodes, but also ensures symmetric output signals [15]. Consequently, nearly identical amplitudes are achieved at the differential output pulses. Table 1 compares the performance of the proposed CORIC with prior arts. Ref. [16] introduced a preamplifier based on a regulated cascode (RGC) circuit, combined with a single-to-differential (S/D) circuit, a DC-offset cancellation circuit, and an output buffer. Compared to the proposed CORIC, this preamplifier demonstrated a narrower transimpedance gain-to-bandwidth ratio and occupied a larger chip area despite the photodiode being off-chip. Ref. [17] presented a common source (CS) amplifier with active inductive peaking (AP-TIA), followed by a post amplifier and an output driver. While implemented in a 130 nm process, this design showed a narrower transimpedance gain-to-bandwidth ratio and higher power dissipation per channel than the proposed CORIC system. Ref. [18] suggested an inverter-based amplifier paired with an AC-coupled noise-cancellation circuit, along with a single to differential (S/D) and offset cancellation (OC) circuits. Even with a 40 nm process, the power dissipation per channel and chip area of this system exceeded those of the proposed CORIC. Ref. [19] proposed a distributed amplifier featuring simple shunt peaking with additional inductor/transformer peaking in a common source (CS) stage. This system exhibited a narrower transimpedance gain-to-bandwidth ratio compared to the proposed design,  
Figure 8: Simulated frequency response of the proposed CORIC. and its TIA required multiple supply voltages (1.5 V and 3.0 V), complicating the power supply design. Ref. [20] realized a system composed of an under-damped TIA, a low-pass filter, and an output buffer. Although implemented in a 65 nm process, its chip area showed a minimal difference from that of the proposed CORIC system.