## 5 Evaluation and Analysis
### Experimental Results and Analysis with Zynq On-Board Sensor System  
In this section, we present the experimental results with an analysis of Asymmetric Programming with Zynq on-board sensor system. The system architecture of the experimental setup is shown in Figure 10a. The Zynq on-board sensor system is a typical sensor system which includes on-board sensors and a dual 12-bit, 1 Mega sample per second (MSPS) Analog to Digital Converter (ADC) as shown in Figure 10b [40]. On-board sensors support measurement of the power supply voltages of 11 channels and die temperature. The ADC conversion data is stored in dedicated registers called status registers. These registers are accessible through the FPGA interconnect, which is an AXI Slave interface in our design. As shown in Figure 10a, the data of Zynq on-board sensors is read out by the computer through the Ethernet interface and the computer then writes the data back into the NAND flash on the daughter card which is configured as the description of Section 5.1. We store the received data into binary files and each file has the size of 16 KB. All of the sensor data is kept in the space of 256 MB of one NAND flash. When the capacity runs out, we just erase the old data and continue to store the incoming data into this area. As shown in Table 3, the 29F64 GCBAAA MLC NAND flash is baked to 2000 P/E cycles first and 4-bit BCH code is applied. The statistic results of the workload gained from Zynq on-board sensor system are also shown in Table 3.  
We compared Asymmetric Programming with a representative scheme Meta-Cure [17] and the default error correction scheme in the Linux kernel (labeled as \"Baseline\") in terms of three performance \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & \multicolumn{3}{c}{**Workload Characteristic**} & \multicolumn{3}{c}{**NAND Flash Package status**} \\ \cline{2-6} \multirow{2}{*}{**Scheme**} & **Number** & **Percentage of** & **Average** & **Level of Wear** & **ECC Strength** \\  & **of Requests** & **Write Operations** & **Request Size** & **(P/E Cycles)** & **ECC Strength** \\ \hline BL & 282,710 & 93.34\% & 16.09 KB & 2,000 & 4-bit \\ MC & 282,802 & 93.19\% & 16.09 KB & 2,000 & 4-bit \\ AP & 282,464 & 93.23\% & 16.09 KB & 2,000 & 4-bit \\ \hline \hline \end{tabular}
\end{table} 
Table 3: The characteristic of the workload and the status of Micron 29F64 GCBAAA NAND flash memory of Baseline, Meta-Cure, and Asymmetric Programming (BL: Base Line; MC: Meta-Cure; AP: Asymmetric Programming). Figure 10: **(a)** The system architecture and illustration of the data flow (**b**) Zynq on-board sensor system block diagram. metrics: the number of uncorrectable page errors, the I/O performance and the garbage collection efficiency. The experimental results are shown in Table 4.  
Compared with the Baseline scheme, we can observe that the proposed Asymmetric Programming can reduce up to 91.97% uncorrectable page errors while only inducing 0.04% and 0.23% overhead in terms of average response time and number of block erase counts, respectively. The additional block erase operations of Asymmetric Programming are caused by the request feedback operations, but its overhead is negligible compared with that of Meta-Cure. This further proves the effectiveness of Algorithm 1. The overhead of extra block erase operations eventually results in the average response time overhead, but it is still negligible according to Table 4.  
Since Asymmetric Programming enhances the reliability of data directly in the programming process and allocation process and does not require extra program operations like Meta-Cure, therefore, the proposed scheme has much less garbage collection operations. Asymmetric Programming also does not need to read backup pages to search for the correctable page. Thus, it also has less read operations than Meta-Cure. Based on these analysis, it is reasonable for Asymmetric Programming to increase the I/O performance by 9.24% compared with Meta-Cure.