# Compact Model for L-Shaped Tunnel Field-Effect Transistor Including the 2D Region
## 2 Model Development  
Figure 1 shows the schematic of the LTFET. The channel region shown in blue color is found in an L-shape and is sandwiched between the gate and the source. The part of the channel region found in between the source and gate regions is termed as \(C_{\text{overlap}}\) with height (\(H_{\text{overlap}}\)) = 40 nm and length (\(T_{\text{j}}\)) = 4 nm. The source and drain are p\({}^{+}\) (\(N_{\text{a}}\) = 10\({}^{20}\) cm\({}^{-3}\)) and n\({}^{+}\) (\(N_{\text{drain}}\) = 10\({}^{20}\) cm\({}^{-3}\)) doped, respectively, while the channel is lightly n\({}^{-}\) doped (\(N_{\text{d}}\) = 10\({}^{15}\) cm\({}^{-3}\)). The source region height (\(H_{\text{s}}\)) and length (\(L_{\text{s}}\)) are 40 and 50 nm, respectively. The bottom part of the channel, which is not in between the source and gate regions, is termed as \(C_{\text{nonoverlap}}\) and has a height (\(H_{\text{nonoverlap}}\)) = 20 nm, and length (\(L_{\text{nonoverlap}}\)) = 50 nm. An HfO\({}_{2}\) dielectric of thickness (\(t_{\text{ox}}\)) = 2 nm for gate oxide was considered.  
Dynamic nonlocal BTBT model [9], fermi statistics, and constant mobility models were considered in the technology computer-aided design (TCAD) simulation.  
As shown in Figure 1, the source has a sharp corner marked by an X in Figure 1. The electric field from the gate converges at and around this sharp source corner, increasing the potential around this point. The right axis in Figure 2a shows surface potential (\(\varphi_{\text{s}}\)) at \(V_{\text{gs}}\) = 0.15 V and \(V_{\text{ds}}\) = 0.5 V. As shown in Figure 2a, \(\varphi_{\text{s}}\) sharply rises in \(C_{\text{nonoverlap}}\) because of convergence of the electric field, whereas \(\varphi_{\text{s}}\) is less in \(C_{\text{overlap}}\) where this convergence does not take place. This convergence affects the BTBT threshold voltage of \(C_{\text{overlap}}\) and \(C_{\text{nonoverlap}}\). \(C_{\text{nonoverlap}}\) is found to have a lower BTBT threshold voltage because of this increased \(\varphi_{\text{s}}\). Meanwhile, \(C_{\text{overlap}}\) has a significantly higher BTBT threshold  
Figure 1: Schematic of the L-shaped tunneling field-effect transistor (LTFET).  
voltage because of the lower potential [10]. This can be seen in Figure 2b, which shows integrated BTBT tunneling rates [10] (\(G_{\text{tun}}\)s) in \(x\) and \(y\) directions in \(C_{\text{overlap}}\) and \(C_{\text{nonoverlap}}\), respectively; that is, \(\int_{x_{+}+T_{\text{s}}}^{0}\int_{0}^{H_{\text{overlap}}}G_{\text{tun}}dxdy\) in \(C_{\text{overlap}}\) (black triangles) and \(\int_{I_{\text{nonoverlap}}}^{0}\int_{H_{\text{overlap}}}^{H_{\text{ nonoverlap}}}G_{\text{tun}}dxdy\) in \(C_{\text{nonoverlap}}\) (red circles) in the left axis. Figure 2b clearly shows that \(C_{\text{nonoverlap}}\) turns on earlier than \(C_{\text{overlap}}\). The right axis in Figure 2b shows the drain-source current (\(I_{\text{ds}}\)) as a function of gate-source bias (\(V_{\text{gs}}\)) of LTFET. It is shown that in the subthreshold part of the \(I_{\text{ds}}\)-\(V_{\text{gs}}\) characteristics, only the \(C_{\text{nonoverlap}}\) is active. \(C_{\text{overlap}}\) turns on at \(V_{\text{gs}}\) = 0.15 V. When \(C_{\text{overlap}}\) turns on, its \(G_{\text{tun}}\) is significantly higher because of 1D BTBT paths. As a result, it dominates the 2D \(G_{\text{tun}}\) in \(C_{\text{nonoverlap}}\), as can be seen in Figure 2b. Based on this analysis, \(I_{\text{ds}}\)-\(V_{\text{gs}}\) characteristics of LTFET were modeled in two parts, first the 2D model in \(C_{\text{nonoverlap}}\) for the subthreshold region and then the 1D model in \(C_{\text{overlap}}\).