## 4 Comparison of Multiple Types of Delay Frequency  
The aging sensor circuit, whose schematic is presented in Figure 3, produces a single output without aging and six outputs that indicate the delay that occurs at different clock frequencies and offer the aging status of the FPGA. The initial detection phase is from \(0^{\circ}\) and ends with \(300^{\circ}\) with intervals of \(50^{\circ}\) in between. All six of these phase delay detections will go HIGH if the CUT produces any form of delay. For example, if the CUT generates a  
Figure 9: Block diagram for automatic clock correction. delay of 108\({}^{\circ}\), the indicators for 50\({}^{\circ}\) and 100\({}^{\circ}\) are to equal '1,' while the indicators for 150\({}^{\circ}\), 200\({}^{\circ}\), 250\({}^{\circ}\), and 300\({}^{\circ}\) will show a value of '0,' as shown in Figure 10.  
The design was tested using an exhaustive simulation test for all possible delays from 1.0\({}^{\circ}\) to 359\({}^{\circ}\), as shown in Table 2. The results were created in binary and translated into hexadecimal values for more accessible analysis. For the delays between 1.0\({}^{\circ}\) and 50.0\({}^{\circ}\), the output remained at 00\({}_{16}\). The output only started to change when the delay was between 51.0\({}^{\circ}\) and 359.0\({}^{\circ}\). The tabulated results show that when the delay occurred between 51.0\({}^{\circ}\) and 100.0\({}^{\circ}\), the output value was 20\({}_{16}\), while if the delay was between 201.0\({}^{\circ}\) and 250.0\({}^{\circ}\), the output was 3C\({}_{16}\), and so forth. The simulation test discovered all possibilities of delay caused by the HCI and NBTI degradation effects that were monitored through critical path delay, interconnect delay, and propagation delay [59; 60; 61; 62]. [PERSON] and [PERSON] examined all these types of delays and found that the propagation delay on the FPGA is 41.3%, while the interconnect delay is58.7% [63]. These findings are supported by [PERSON] et al., who found that the interconnect delay was between 60 and 70% of the total delays [14], which leads to the lifetime degradation of the FPGA. Based on the seven detection points of the delay degradation, the manufacturer of the FPGA provides a maximum lifespan of the FPGA as a reference purpose only [64] because the percentage utilization of the CLBs depends on the digital system developed. According to the Xilinx manufacturer of the Virtex-6, the lifetime for the 40 nm FPGA technology is 80 months [65]. Compared to other manufacturers, such as Altera and Lattice Semi, they reported that the lifetimes of their products Startix IV and ICE40L are around 36 months [66] and 24 months [67], respectively. Based on this information, the lifetime prediction was tabulated, as shown in Table 3. For example, if the delay detection was between 101\({}^{\circ}\) to 150\({}^{\circ}\), the lifetime of the Xilinx FPGA will have 58.33% of its lifecycle remaining. In other words, the FPGA can be used for another 47 months. According to the desired lifetime specification, this calculation method will help the programmer replace the FPGA if necessary. The complete lifetime prediction calculated for each clock phase delay is shown in Table 3. The following formula was used to calculate the delay:  
\[\%d=f_{d}/360\ \times 100 \tag{6}\] \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Phase Delay**} & \multicolumn{6}{c}{**Output of Aging Detection**} & \multirow{2}{*}{**Hex Value**} \\ \cline{2-2} \cline{4-7}  & **[6]** & **[5]** & **[4]** & **[3]** & **[2]** & **[1]** & **[0]** \\ \hline
1–50 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\
51–100 & 0 & 1 & 0 & 0 & 0 & 0 & 20 \\ \({}^{*}\) 101–150 & 0 & 1 & 1 & 0 & 0 & 0 & 30 \\
* 151–200 & 0 & 1 & 1 & 1 & 0 & 0 & 38 \\
201–250 & 0 & 1 & 1 & 1 & 1 & 0 & 3C \\
251–300 & 0 & 1 & 1 & 1 & 1 & 1 & 0 & 3E \\
301–359 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 3F \\ \hline \hline \end{tabular} \({}^{*}\)Phase range used for auto-correction principle in the proposed circuit.  
\end{table}