# Designed on 0.18 um CMOS Process Small Size Broadband Millimeter Wave Chip Antenna
## 5 Conclusions  
Chip antennas are a good candidate for millimeter wave system applications that require high integration and broadband characteristics. This paper proposes a chip antenna suitable for millimeter wave systems using 0.18 \(\upmu\)m CMOS process, which size is 1.2 \(\times\) 1.2 (mm\({}^{2}\)), using an M6 metal layer for antenna design. Through parameter analysis, it can be seen that the optimization of the feed line length and patch shape is helpful for antenna impedance matching. In addition, by expanding to a 1 \(\times\) 2 array antenna pole and digging three circular slots in the ground, antenna radiation performance is increased. The proposed chip antenna in this paper has a gain of \(-\)0.4 dBi at 64 GHz, maximum. The proposed antenna has a fractional bandwidth 54%. The actual measured bandwidth is 62-100 GHz, and the analog and measured bandwidth are similar. The chip antenna frequency range proposed in this article covers the 5G NR FR2 frequency band and can be used in the fields of the Internet of Things, Industry 4.0, and biomedical electronics. Its small size makes it easy to integrate with other microwave circuits, which can form a highly integrated millimeter wave system. In the future, it will be able to integrate with microwave circuits or combine applications with printed circuit boards to further improve antenna gain performance.  
Conceptualization, M.-A.C.; methodology, M.-A.C.; software, M.-A.C. and S.-R.H.; validation, M.-A.C., S.-R.H. and P.-R.H.; formal analysis, M.-A.C., S.-R.H. and P.-R.H.; investigation, M.-A.C., S.-R.H. and P.-R.H.; resources, M.-A.C.; writing--original draft preparation, M.-A.C. and S.-R.H.; writing--review and editing, M.-A.C.; visualization, M.-A.C.; supervision, M.-A.C.; project administration, M.-A.C.; funding acquisition, M.-A.C. All authors have read and agreed to the published version of the manuscript.  
This research received no external funding.  
**Data Availability Statement:** All data are included within the manuscript.  
**Acknowledgments:** Not applicable.  
**Conflicts of Interest:** The authors declare no conflict of interest.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Reference** & **Process** & *** Freq. (GHz)** & *** FBW (\%)** & **Gain (dBi)** & *** Eff. (\%)** & **Size (mm\({}^{2}\))** \\ \hline This Work & 0.18 \(\upmu\)m CMOS & 64 & 54 & \(-\)0.4 & 40.9 & 1.2 \(\times\) 1.2 \\ \hline
[18] & 0.65 \(\upmu\)m CMOS & 28, 60 & 5.3, 5.9 & \(-\)10, 4 & 45, 30 & 0.25 \(\times\) 0.3 \\ \hline
[19] & 0.13 \(\upmu\)m SiGe CMOS & 81.5 & 12.1 & 1.61 & NA & 1.296 \(\times\) 1.508 \\ \hline
[20] & 0.65 \(\upmu\)m CMOS & 24, 40 & 19, 20 & \(-\)1, 0 & 41, 31 & 2.5 \(\times\) 2.5 \(\times\) 2.5 \\ \hline
[21] & 0.18 \(\upmu\)m CMOS & 60 & 16 & 0.3 & 45 & 5 \(\times\) 5 \\ \hline
[22] & CMOS & 60 & 9.8 & \(-\)2.3 & 21 & 1.5 \(\times\) 0.75 \\ \hline
[23] & 0.13 \(\upmu\)m BiCMOS & 84 & 11.7 & \(-\)0.5 & 41 & 0.32 \(\times\) 0.1 \\ \hline
[24] & MEMS & 28.5 & 13 & 6.6 & 90.9 & 0.52 \(\times\) 0.52 \\ \hline
[25] & 0.28 \(\upmu\)m CMOS & 33 & 16.3 & 14 & 37.3 & 0.66 \(\times\) 0.85 \\ \hline
[26] & 0.18 \(\upmu\)m CMOS & 40 & 53.4 & 3.3 & NA & 1.1 \(\times\) 1.7 \\ \hline
[27] & 0.13 \(\upmu\)m CMOS & 81 & 31.4 & \(-\)0.3 & NA & 0.1 \(\times\) 0.05 \\ \hline \hline \end{tabular}  
* Freq.: Frequency;
* FBW: Fractional bandwidth;
* Eff: Efficiency.  
\end{table}
Table 2: Comparison table with the other research literature.