## 3 Test Environment for TMR Mitigation Structures  
Assessing the effectiveness of the implementation of mitigation mechanisms using TMR voters is a difficult task. It is possible to imagine a whole range of factors on which effectiveness should depend, such as the occupation of logical resources necessary for their implementation and power consumption. From a logic-resource-occupation point of view, more efficient solutions are those that use less logic resources (a smaller silicon area). In the classical approach, the aim is to minimise transistors or gates. In the case of FPGAs, the problem is more complicated because the implemented logic functions are mapped in LUT blocks. These blocks implement simple logic functions with a small number of variables (e.g., 6). Logic functions in a larger number of variables have to be decomposed and then mapped into several suitably interconnected logic blocks [8]. Obviously, looking at the TMR voter, it is apparent that these structures are simple enough that, in theory, a single LUT block should be sufficient to implement them. The resource utilisation of the redundant modules attached to the voter inputs remains an open question. It turns out that synthesis tools can in some cases produce results far from optimal, which can result in a significant growth of the logic structure. In addition, it should be noted that TMR voter inputs are not necessarily single-bit. Each input can be an n-bit bus, making the voter itself much more complex. It is also possible to imagine much more complex voter designs, e.g., using a golden model (a priority model) or designs in which individual inputs are assigned appropriate weights. Theoretically, a voter can have more voting inputs (of course, this is no longer TMR), and the process of selecting the correct data is then more complex, involving a significantly higher number of necessary logic resources. From the point of view of FPGAs, it is also important how the voter and the circuits attached to its inputs are described in the HDL language. It turns out that a combinational circuit can be described in many ways (by arrays, equations and structural descriptions), which often leads to solutions using a different number of logic resources. Taking all this into account, evaluating the effectiveness of mitigation structures in terms of the use of logical resources is an extremely important issue. Of considerable importance from the point of view of mitigation structures using TMR is their power consumption. The power consumed by a digital circuit is the sum of static and dynamic power. Static power depends on the technology in which the circuit is made. Mitigation circuits are not separate ICs, so a comparison in terms of static power makes no sense. The situation is different for dynamic power, which depends on the switching frequency of the digital circuit. The dynamic power \(P_{dyn}\) of an \(n\)-vertex logic network can be expressed by (1):  
\[P_{dyn}=\frac{1}{2}V_{dd}^{2}f\sum_{i=1}^{n}C_{i}SW_{i} \tag{1}\]  
where \(V_{dd}\) is the supply voltage of the digital circuit and \(f\) is the frequency of the clock signal. Additionally, this power depends on the product of the connection capacitance between the nodes of the logic network \(C_{i}\) and the switching activity \(SW_{i}\). In the classical case, the vertices of the logic network are the individual gates, while in the case of FPGAs, they are the LUT blocks. The key parameter from the perspective of power reduction is the switching activity (\(SW\)). The switching activity \(SW_{i}\) is related to the probability of'switching' the considered \(i\)th node to the opposite state, i.e., the transition from 0 to 1 or the transition from 1 to 0. The switching activity can be expressed by (2):  
\[SW_{i}=2P(x)(1-P(x)) \tag{2}\]  
where \(P(x)\) is the probability of the variable \(x\) taking the value one.