# A Novel Active Polyphase Filter Employing Frequency-Dependent Image Rejection Enhancement Technique
## 4 Simulation and Measurement Results  
The 180 nm CMOS process was used to design the proposed novel single-stage APPF. The layout area of the single-stage APPF is 150 \(\times\) 340 \(\upmu\)m\({}^{2}\). The power consumption simulation result for a single-stage APPF is 1.48 mW with a supply voltage of 1.8 V. The simulated results of the single-stage APPF with different operating frequencies in Figure 10 show that the proposed technique significantly improves the image rejection ability. And, the effect of the image rejection improvement does not degrade with the increase in operating frequency, which effectively solves the shortcoming of the insufficient image rejection ability of the conventional APPF in the high-frequency range. At a frequency of several hundred MHz, the proposed single-stage APPF has an optimum IRR of better than \(-60\) dB. Figure 10: Simulated results of the single-stage APPF with different operating frequencies: (**a**) the operating frequency is 100 MHz; (**b**) the operating frequency is 200 MHz; and (**c**) the operating frequency is 300 MHz. Figure 9: Schematic of the novel single-stage APPF with the proposed enhancement technique. Figure 11 shows the image rejection effect of APPF when there is a phase imbalance in the quadrature input signal. Without employing the proposed technique, the phase imbalance of the quadrature input signal may be superimposed with the phase imbalance introduced by the secondary pole, which further worsens the IRR. On the contrary, the APPF with the proposed technique has an excellent IRR regardless of whether the phase of the quadrature input signal is greater than or less than 90\({}^{\circ}\), which proves that the proposed enhancement technique can reduce the strict requirement on the input signal phase. With regard to the PVT variations, nine combinations were selected for simulation. The TT-Typical voltage-Typical temperature combination is set as the control group. The eight experimental groups included FF-Low voltage-Low temperature, FF-High voltage-Low temperature, FF-Low voltage-High temperature, FF-High voltage-High temperature, SS-Low voltage-Low temperature, SS-High voltage-Low temperature, SS-Low voltage-High temperature, and SS-High voltage-High temperature. Figure 12 shows the IRR variations for different PVT combinations, indicating that the IRR can always exceed \(-60\) dB at the operating frequency. Low, typical, and high voltages are set to 1.8 V, 1.62 V, and 1.98 V, respectively. Low, typical, and high temperatures are \(-40\) degrees Celsius, 27 degrees Celsius, and 85 degrees Celsius, respectively. The frequency offset of the operation due to PVT variations can be compensated by adjusting the capacitance or tuning the transconductance by adjusting the tail current. The Monte Carlo simulation results for the IRR are shown in Figure 13. The total number of runs is 500, and the standard deviation of the IRR is observed to be less than 7.65 dB, demonstrating a high robustness. As shown in Figure 14, the simulation result of the output third intercept point (OIP3) of the single-stage APPF is greater than 0.94 dBm. Figure 15 shows the gain simulation result of the single-stage APPF near 100 MHz operating frequency is around 3.75 dB. Furthermore, the input-referred noise (IRN) simulation result of the single-stage APPF is 34.5 \(\upmu\)V.  
The proposed enhancement technique can also be used in multistage APPF, where each stage can be tuned independently to improve the image rejection ability of broadband signals. The different rejection frequencies in each stage are obtained by adjusting the main capacitors. Figure 16 shows the simulated result of the two-stage APPF employing the proposed technique. It can achieve an IRR of better than \(-53.4\) dB at a bandwidth of 26 MHz.