## 5 The Hardware Implementation of the Dual-Axis-Based Solar Tracking System
### Reconfigurable BILBO Architecture for Stuck-At Fault Detection
Conversely, when a LOW signal is applied, the vertical motor becomes fully operational for rotating the PV panel according to the firmware. The four control signals--Enable, Relay, Step, and Direction--are activated when the inputs of the Arduino Mega MCU receive analog values from the photoresistors. The initial phase of designing the BIST architecture for the ASPCB involves test pattern generation. Here, a pseudo-random pattern generator (PRPG) is developed to generate test patterns, which will subsequently be linked as stimulus signals to the DUT's input. Leveraging the Arduino Mega 2560's ADC module for instantaneous translation of analog data into digital format enables us to emulate these sensor values efficiently using an LFSR-based device and a reduced set of test vectors, as depicted in Figure 10.  
The hardware design of the 5-bit LFSR is implemented according to the non-primitive polynomial \(P(x)=x^{5}+x^{4}+x^{3}+x^{2}+x+1\) and requires only five clock cycles to generate distinct test patterns for its outputs. Moreover, since one memory component can output two Boolean values (one binary digit and its complement), we can generate the required test vector length using only five DFF units. However, since it is necessary to inject test patterns on two 10-bit digital channels (west and east photoresistors for the horizontal rotation and, respectively, north and south photoresistors for the vertical rotation), only one 5-bit LFSR component may not suffice. Therefore, our complete PRPG architecture is composed of a pair of 5-bit LFSRs, whose outputs will be tethered, in turn, to each of the digital channels. Regarding the seed value of the LFSR device, we included two command lines: reset and set. When the asynchronous reset line is active low, the 5-bit shift register will output the seed value '1010101010' on the first positive edge of the clock signal, representing a random digital value (682). On the other hand, a second 5-bit LFSR with the same characteristics could be employed with a distinct seed value '1001010101' (597) generated by the asynchronous set line on the same clock edge. Thus, we can simulate the horizontal and vertical movement of the solar tracking system by generating higher values on the  
Figure 10: Proposed PRPG Architecture for test vector generation comprising four D-type Flip Flops denoted with D0–D4, one clock signal, one reset signal, and one set signal. first TPG unit and lower values on the second TPG unit, in a parallel manner. Based on the digital values' concurrent generation, the horizontal and vertical modules of the solar tracking device will output a binary sequence equal to the axis rotation step. The second phase of constructing the BIST design is a multifaceted process comprising three sub-steps: signature generation, compression, and analysis. The binary sequences provided by the DUT undergo further processing through a signature analyzer, referred to as an ORA unit. The RBILBO architecture can serve as both a TPG and an ORA unit, contingent upon the configuration of control signals, as depicted in Figure 11. The primary signals, B and P, govern the dataflow within the modified IBILO design through five AND gates and a multiplexer. While the first input, B, manages the LFSR/MISR functionality of the architecture, the second input, P, comprising 2 bits, configures the expression of the generator polynomial on the negative feedback paths of the RBILBO. The RBILBO architecture, similar to the PRPG design illustrated in Figure 10, introduces a set and reset signal to each of the five DFF units to establish the initial seed value of the shift register. When the set signal is activated and reset is inactive, the entire content of the register is set to a non-zero value, indicating that the architecture can function as an LFSR. Conversely, when the set signal is deactivated and reset is activated, the register's content is cleared, preparing the architecture to operate as a MISR.