## 4 Equalization Technologies
### Ffe/Dfe
#### 4.1.2 Improved Algorithms Based on FFE/DFE
The BER performance versus the received optical power is shown in Figure 12[37]. Compared with the FFE case, of which the BER is \(9\times 10^{-3}\), the ID-FFE/ID-DFE reaches \(2\times 10^{-3}\). When the pre-FFE is used before ID-FFE/ID-DFE, the performance is improved by almost an order of magnitude and the BER reduce to \(2.6\times 10^{-4}\). From the received eye diagrams of ID-FFE with and without pre-FFE, we observe that the pre-FFE can completely suppress the residual eye skewing effect of the ID-FFE and dramatically remove the ISI. When the transmission distance increase to 43 km, only the ID-FFE/ID-DFE assisted by pre-FFE can reach a BER of \(3.6\times 10^{-3}\) below the HD-FEC. Therefore, the chirp of the modulator can be well addressed by the novel proposed ID-FFE/ID-DFE. \(\bullet\) CR-FFE  
The problem of incompatible prerequisites between impairment equalization and clock recovery also reduces the performance of PAM4 transmission [74]. A joint clock recovery and feed-forward equalization algorithm is proposed recently, which estimates timing error based on the difference  
Figure 11: (a) The detailed structure of (P-1)-tap ID-FFE and Q-tap ID-DFE. (b) The block diagram of the pre-FFE + ID-FFE/ID-DFE (reprinted from [37] with open access from OSA). Figure 12: The BER performance of 56 Gbps PAM4 signal (a) after 35.9 km transmission and (b) after 43 km transmission (reprinted from [37] with open access from OSA). between two tap coefficients of T/2-spaced FFE. The proposed algorithm can eliminate the ISI induced by linear impairments and track large sampling clock offset (SCO) simultaneously. The structure of the CR-FFE is plotted in Figure 13, where we notice that the timing error is derived from the difference between two tap coefficients [39]. For the comparison of complexity, the timing error of CR-FFE is calculated by one time subtraction, while the conventional CR algorithm needs an additional multiplication. Considering the total multiplication operations, the computational complexity of CR-FFE is similar to or slightly lower than that of the original scheme. The BER performance of CR-FFE over different SCO is studied as shown in Figure 14a [39]. The traditional clock recovery cascaded by FFE (noted as scheme II) cannot counteract large SCO, while the CR-FFE (noted as scheme III) can ensure stable and reliable performance as SCO increase from 0 to 1000 ppm. From Figure 14b,c, we observe that the two tap coefficients for timing error detection are basically equal and the fractional interval has a stable changing process, which indicates that clock recovery and equalization are accomplished simultaneously after 40 km transmission when SCO reaches 1000 ppm. Therefore, the CR-FFE can solve the problem of incompatible prerequisites between impairment equalization and clock recovery, and provide significant system performance improvement for PAM4 transmission. Figure 14: (**a**) The BER performance vs. sampling clock offset at received optical power of -8 dBm for 50 Gbps PAM4 signal; (**b**) the tap weights and (**c**) fractional interval of proposed CR-FFE after 40 km transmission when sampling clock offset is 1000 ppm (reprinted from [39] with open access from OSA). Figure 13: The structure of proposed joint clock recovery and FFE (CR-FFE) (reprinted from [39] with open access from OSA).