## 1 Introduction  
The rapid growth of information in recent years has highlighted the limitations of existing systems in efficiently processing large datasets, prompting the exploration of various technological solutions [1, 2, 3]. Traditional von Neumann computing architectures, which transfer data between memory and the central processing unit (CPU), offer versatility and practicality. However, the von Neumann architecture is limited by a memory bus bandwidth bottleneck, which slows data transfer between memory and the CPU, particularly during sequential processing for memory updates [4, 5]. To address these limitations, neuromorphic devices have emerged as a promising alternative by configuring neural networks directly in hardware. Neuromorphic devices emulate biological neurons and synapses through mechanisms like spike-based signaling and synaptic weight adjustment, enabling parallel processing operations with low power consumption and high speed [6, 7, 8]. Typical neuromorphic devices include memristors and field-effect transistors (FETs) [9, 10, 11, 12, 13]. Memristors, developed in various forms such as resistive random-access memory (RRAM),phase-change random-access memory (PCRAM), and magnetic random-access memory (MRAM), are considered promising synaptic devices due to their simple structure and suitability for crossbar array (CBA) architectures [14]. However, CBA structures suffer from sneak currents, where current flows in undesired directions, necessitating the integration of three-terminal structures to mitigate these issues. Furthermore, achieving long-term reliability remains challenging due to the degradation of resistance states over time. In contrast, FETs offer precise control of current flow through gate voltage modulation, effectively eliminating sneak path issues. Additionally, their standardized manufacturing processes facilitate large-scale production and integration. Flash transistors, characterized by non-volatile behavior, can emulate synapses by implementing learning and memory functions through output signal modulation via floating gates [15; 16; 17; 18]. Among floating gate devices, nanoparticle floating gate (NPFG) structures have been developed with a focus on discrete charge trapping. NPFG transistors exhibit superior durability, low power consumption, and multi-level capability compared to continuous (conventional) floating gate transistors. Materials such as gold, quantum dots, aluminum and silicon carbide are employed as nanoparticles, with their charge storage capacity tunability based on material type, size, and density, enabling extensive comparative analyses [19; 20; 21; 22; 23; 24]. In our previous work, we developed an NPFG device using InP quantum dots and demonstrated excellent performance [25]. However, the non-uniform size and dispersion of quantum dots adversely affect carrier mobility and device reproducibility, and their low thermal stability further compromises device stability at high temperatures. [26; 27]. In this study, to address these limitations, the uniform size and dispersion of the floating gate were controlled through photolithography, and the limitations of NPFG were addressed by utilizing platinum, which exhibits high thermal stability. In addition, by ensuring spatial uniformity and structural precision of the charge storage locations, this work aims to implement a synaptic device with high reproducibility. This structure presents a unique approach not discussed in the previous literature, namely the regularized spatial control of charge storage regions, and it is meaningful in that it considers both scalability to nanoscale structures and expandability to neuromorphic array architectures. The minimum pattern size achievable using a contact aligner (i-line, 365 nm) was set to 3 \(\upmu\)m \(\times\) 3 \(\upmu\)m for each floating gate, which was implemented in a mesh-type arrangement. The detailed structures, processes, and their electrical characteristics are discussed in subsequent sections.