# Structure and Principles of Operation of a Quaternion VLSI Multiplier
## 5 Hardware Implementation of Quaternion Multiplication  
### Implementation on FPGA  
The fast quaternion multiplication shown in Figure 5 was implemented on Artix-7 xc7a100 tfgg484-1. The project was realized using the Vivado 2016.4 tool. This multiplication was carried out in two ways: based on regular and pipeline processing. In the first case, the clock frequency achieved was 50 MHz, and in the second, 250 MHz was achieved. Due to the buffering occurring in pipeline processing, an additional 768 flip flops (FFs) were used, which, however, constitute only 0.61% of the matrix resources. In the case of the direct pipelined implementation of quaternion multiplication, the multiplications were separated from the additions by inserting registers after each operation. In the case of the fast pipelined implementation, registers were added between each operation, and additional registers in some signal paths were added to synchronize the signals at the output. These changes allowed the clock frequency to be increased from 50 MHz to 250 MHz. An important comparison criterion, apart from clock frequency and power consumption, is the use of processors (DSPs). As mentioned in the previous sections, the developed algorithm reduces the number of required multiplications, which should translate directly into the number of DSPs. The operations of multiplying by 2 and dividing by 4 in Figure 5 do not involve additional DSPs because they are implemented as shifts in registers. For comparison, a direct algorithm resulting from the notation in Equation (5) was implemented. According to this relationship, 16 multiplication operations are required. This algorithm was also implemented in two versions: pipeline processing, with a clock frequency of 250 MHz, and regular processing, with a clock frequency of 50 MHz. The number of processors requiring the largest area on the chip has doubled (16 DSPs). The power consumption in the case of direct multiplication is practically the same as in the case of fast multiplication. The simulation results are summarized in tables. Table 1 compares resource utilization and power consumption for a pipelined implementation of direct and fast quaternion multiplication. In Table 2, a similar comparison was made for the regular implementation. Apart from achieving a 5-times higher frequency, regular and pipelined implementations are comparable in terms of resource utilization. Higher dynamic energy consumption in a pipelined implementation is associated with obtaining a higher clock frequency. However, the fast and direct multiplication methods differ in both cases by twice the number of processors (DSPs). \begin{table}
\begin{tabular}{c c c c} \hline \hline \multirow{2}{*}{**Resources**} & \multicolumn{2}{c}{**Utilization**} & **Available** \\  & **Direct Multiplying** & **Fast Multiplying** & **Resources** \\ \hline LUT & & & 640 (1.01\%) & 63,400 \\ \hline FF & 96 (0.08\%) & 768 (0.61\%) & 12,680 \\ \hline DSP & 16 (6.67\%) & 8 (3.33\%) & 240 \\ \hline IO & 256 (90.18\%) & 257 (90.18\%) & 258 \\ \hline BUFG & 1 (3.13\%) & 1 (3.13\%) & 32 \\ \hline _Energy_ & & & \\ _consumption_ & & & \\ \hline clocks & 0.003 W (1\%) & 0.01 W (2\%) & \\ \hline signals & 0.019 W (5\%) & 0.037 W (10\%) & \\ \hline logic & \(<\)0.001 W (\(<\)1\%) & 0.016 W (4\%) & \\ \hline dsp & 0.04 W (11\%) & 0.02 W (5\%) & \\ \hline io & 0.302 W (82\%) & 0.305 W (79\%) & \\ \hline dynamic (sum of the above) & 0.364 W (80\%) & 0.388 W (81\%) & \\ \hline static & 0.092 W (20\%) & 0.092 W (19\%) & \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Pipeline implementation of direct and fast quaternion multiplication obtained for a 250 MHz clock.