## 1 Introduction  
As the Fourth Industrial Revolution has continued to develop, the semiconductor market has also continued to grow rapidly. In addition, the emergence of 5G, artificial intelligence (AI), and the Internet of Things (IoT) have contributed to further driving demand in the semiconductor market. High-performance integrated circuit (IC) chips are currently used in many industries that are receiving a considerable amount of attention, such as AI, IoT, autonomous vehicles, smartphones, and smart devices. Accordingly, the demand for high-performance IC chips has significantly increased. To meet this demand, the modern semiconductor manufacturing industry has developed to include mass production systems that entail numerous processes. Since the productivity of semiconductors derives from the yield of the involved wafers, various studies have been conducted to increase this yield [1, 2, 3]. Since the manufacturing processes for semiconductor ICs are sequential, minor anomalies in a given process can lead to potential yield degradation in the subsequent process. Therefore, it is important to effectively control the manufacturing process to achieve high yields [4]. In particular, for semiconductors, the time from design to production is relatively long; thus, if errors cause delays, significant losses accumulate. Therefore,quickly identifying the root causes of process anomalies and solving problems early are important tasks for achieving a high yield in semiconductor manufacturing. However, as semiconductor ICs continue to be miniaturized and design complexity increases, many defects continue to occur in the semiconductor manufacturing process [5]. Various methods are being studied to determine the root cause of such errors so that they can be corrected quickly. One such method uses the wafers generated during the overall manufacturing process. Prior to performing the packaging process, various electrical tests are performed on a generated wafer to ensure the function of the semiconductor product. As a result, a wafer bin map (WBM) can be obtained from the test result. A wafer is composed of a large number of dies, and a WBM refers to a wafer map that records spatial information of good and failed chips on a wafer, as determined through probe testing. In semiconductor manufacturing, WBMs are used to visualize defect patterns and identify potential process anomalies. Failed dies on wafers tend to form clusters [6], and the type of defect pattern that appears on the wafer provides process engineers with indirect information regarding the root causes of errors in the manufacturing process. Figure 1 shows examples of the various potential defect patterns of a wafer map. Here, failed dies are shown in yellow, good dies are shown in green, and non-wafer areas are shown in purple. As can be seen in Figure 1, the defect patterns in a WBM can be visually classified according to the spatial shape in which defect clusters are located on the wafer. These classified defect patterns provide information related to issues encountered in the semiconductor manufacturing process based on the defect type [7]. For example, 'center' patterns can occur when there is a problem with wafer thickness uniformity during the chemical-mechanical planarization process; an 'edge ring' pattern can occur because of a problem during the etching process; an 'edge location' pattern can occur when there is a problem in the thin film deposition process; and'scratch' patterns can occur due to improper handling of the wafer [8; 9]. Engineers can infer how defect patterns arise based on the visual information obtained through WBMs and their domain knowledge. Based on this inference, an abnormal process can be corrected to improve the yield. Therefore, accurately and efficiently classifying defect patterns is an effective means for identifying the root cause of a defect and improving both the yield and process reliability. However, most companies rely on the eyes and experience of skilled engineers to identify specific WBM defect patterns.