# Hardware Update through Digital TV Signals
## 2 Related Work  
The usage of FPGA-based systems in the telecommunication industry is widespread, with typical applications in the development of general transmission decoders [16; 17], video decoders [18; 19], security approaches like parity checks [20; 21], satellite issues [22; 23], and digital TV systems [24]. The modern usage of those devices includes machine learning proposals [25], cloud computing [26], and 5G communication networks [27].  
Recent studies presented related work based on intelligent hardware architectures, with hardware reconfiguration as a core technology to build more compact and efficient systems. Indeed, structures with hardware resource management are compelling solutions for embedded and discrete event systems [28; 29].  
In many approaches, pre-synthesized hardware unit functions can execute runtime reconfiguration of FPGA cores according to user interaction [15; 30]. The mentioned work presented a hybrid architecture that used a CPU and a reconfigurable device (FPGA) for performing tasks controlled by a resource manager, which used a decision algorithm to choose among pre-synthesized hardware cores or software modules [31]. When the mentioned resource manager indicated the use of a hardware module, its FPGA was reconfigured; otherwise, a software module was run by the CPU and performed the desired task. In other words, in those works, a good splitting algorithm of the system into the dynamic (reconfigurable) and static (non-reconfigurable) partitions is proposed [32; 33].  
Intelligent embedded systems can make use of partial dynamic hardware for runtime reconfiguration. Like a microprocessor multi-task system, such a feature allows a multiplex of distinct hardware modules to run simultaneously. Thus, functional pre-synthesized hardware blocks (i.e., logical blocks) can be reconfigured or not reconfigured according to the system's needs [34; 35]. The associated system architecture is coordinated by a microcontroller device in charge of reconfiguring the pre-synthesized hardware blocks in FPGA devices [36]. Aside from that, a list of pre-synthesized hardware blocks is kept in flash memory. This way, the use of partial dynamic reconfiguration causes a considerable reduction in power consumption [37], in addition to a significant decrease in device costs [38].  
The reconfigurable architecture presented by [PERSON] et al. [39] allowed the inclusion of signal-processing pre-synthesized cores into hardware description language (HDL) sources to be runtime reconfigurable. This feature is significant, considering that state-of-the-art FPGA devices require large amounts of time and memory for their compilation processes. In those cases, pre-synthesized cores minimize the synthesis processes and allow the design of adaptive reconfigurable system architectures.  
A complete multicore reconfigurable platform can provide a rich and flexible environment for application programmers [40]. Each processor core has a coupled reconfigurable coprocessor unit in that architecture, which allows the extension of a processor's instruction set to run applications.  
A streaming-based partially reconfigurable architecture and programming model may be used to simplify the development of streaming applications. Thus, programmers could describe such operations with a suitable software/hardware multithread model. The efficiency presented by such a reconfigurable architecture demonstrates that its power efficiency is much better than that of state-of-the-art graphics processing units [41].  
The presented related works are based on pre-synthesized cores, which must be present on their embedded file systems. Those modules are used according to system demands for updating several devices or even due to user interaction. However, HARD is based on broadcast networks, through which pre-synthesized cores can be sent. Therefore, several core modules from different manufacturers can be delivered simultaneously to a large number of receivers.