# Chaos-Based Physical Unclonable Functions
## 4 Testing and Results  
The preliminary verification was based on the implementations in five Xilinx Cool-Runner II CPLDs (three XC2C256 devices and two XC2C64) as well as nine devices of Xilinx Artix-7 XC7A100T FPGAs (CSG324 ABX1625/1629). The \(s_{\text{N}}[m]\) bit-strings were acquired with the use of the Texas Instruments DK-TM4C123G board (Dallas, TX, USA) connected to the PUF output as well as PD output signals were observed and measured with both oscilloscope and Agilent 53230A timer (currently Keysight, Santa Rosa, CA, USA). We have evaluated series of circuit's architectures by changing the numbers of inverters (implemented as look-up tables--LUTs) in each type of delay lines (DLa, DLb, FB). Consequently, we have selected for the following research the architecture that consists of: 13 LUTs in the DLa (DLa1, DLa2), six LUTs in the DLb (DLb1, DLb2) and nine LUTs in the FB (as \(\tau\)). It is worth mentioning that the circuit's architecture, which can be seen just as numbers of standard delays in each of the chains (DLa, DLb, FB), is perfectly scalable and can be used in various devices made in various technology processes. For that reason, we have chosen for tests two quite faraway models of devices: 0.18 \(\upmu\)m CPLDs and 28 nm FPGAs. Every circuit was initiated with eight different PUF challenges (eight different SCRO elements placement or routing) and the implementations were exactly copied to each of instances (\(k\in K\)). The number of steps, after which the entropy (\(H_{k}\)) abruptly increases, was estimated as a distance between the system initialization and the moment when \(H_{k}>0.5\) (see Figure 4). The distance, measured as a number of consecutive \(\delta\) comparisons was used as a PUF response. Analysis of five CPLDs and nine FPGAs indicated a linear correlation between challenges and responses within one device (intra-class correlation). On the other hand, the same implementations in different devices showed a uniqueness of each device (lack of inter-class correlation). Figure 9 demonstrates a few examples of PD output bit-strings (\(s_{N}[m]\)) in a form of binary bitmaps--50 runs (\(n\)) of 200 steps (\(m\)) for eight example FPGA instances (K1-K8) and three challenges (C1, C2, C3). Derived keys are basically the numbers of steps (\(m\)) after which the deterministic chaos  
ends and the non-deterministic chaos begins. In the tests, the PUF time window (depicted in Figure 4) began at the value \(m\!=\!9\) and ended with \(m\!=\!197\) (therefore the observation window was shortened to \(m\!=\!200\) steps). Such a range (in binary representation) results in 7,6 bits of a key. The dispersion of the moment when \(H\) leads effectively to \(\sim\!6\)-\(7\) bits of entropy with just a single challenge. The difference in the PUF time window between simulations and the physical implementations likely involves two factors. First, the model did not result from the actual technological spread that occurred at manufacture of devices. Second, the research involved only several devices--we cannot conclude about PUF statistical occurrences nor keys randomness based on such a small number of instances. For that reason, future research should follow. Taking into consideration practical aspects of retrieving PUF keys from a single instance, it is apparent that multiple bit-strings are required, but both the number of the streams as well as the required length of the stream vary. Since the 0.5 Shannon's entropy level is not very demanding in terms of variance or Hamming distance (the half value of \(H\) is reached when only one of nine bits differs), basically the first different bit-string can indicate the beginning of non-deterministic chaotic operation--as a matter of fact, the first different \(s[m]\) value between the bit-strings. After the first difference occurs, the remaining part of the bit-string is redundant (nevertheless, it should be generated because of the vulnerability to timing SCAs).