# A Low-Latency Fair-Arbiter Architecture for Network-on-Chip Switches
## 4 Implementation and Experiment  
To evaluate the arbiter's performance, we selected some classical arbitters to analyze their critical paths and fairness [28]. Generally, the maximum delay path of the arbiter is  
Figure 7: Internal node and root node structure. (**a**) Internal node. (**b**) Root2 node. (**c**) Root4 node. from the time a leaf node launches an arbitration request to the upper layer to the time the upper layer responds to the authorization signal. We calculated the number of 2-input logic gates (3-input logic gates are counted as 1.5 unit gates) in the arbiters' critical path. The result is shown in Table 2. The SA and the FSA use 4-input cells to ensure that the maximum delay increases with \(log_{4}N\) and others grow with \(log_{2}N\). In order to assess their performances on ASICs, all arbiters were implemented in structural RTL Verilog code and synthesized in a 90 nm process [29]. Since the synthesis result depends on the target clock frequency, we employed the clock with different periods and selected the worst path as the latency of the arbiters. Considering that most arbiters use combinational logic as the input and output, the synthesis tool cannot correctly report the worst path. Therefore, we implemented the D flip-flop before and after the structure. The experimental module is shown in Figure 8.  
The obtained delay is presented in Table 3 and Figure 9a. We list the most classic PPA structures as a basis in the table in order to make it easier to find the advantages of each structure. As shown in Figure 9a, the timing delays of SA and FSA grow with \(log_{4}N\), and others grow with \(log_{2}N\). Except for PRRA, the other results were generally in line with our expectations. The PRRA was optimized by the synthesizer using the 3-input logic gate, so its critical path becomes \(3 log_{2}(n)-1\). On a small scale, the FSA has a slightly longer delay than SA; however, it has better latency on a large scale. Averagely, the FSA obtains the best latency. Compared to the PLA, the FSA only keeps the locking structure at the leaf nodes, and its complexity does not increase as the tree structure level increases. The FSA is faster than other architectures on a wide scale, with a timing improvement of 8.1% over SA and one of 22.2% over PLA, on average. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Arbiter** & **Critical Path** &
\begin{tabular}{c} **Arbiter Logic Gate** \\ **(N = 256)** \\ \end{tabular} & **Fairness** \\ \hline PPA & \(2 log_{2}(n)\) & 16 & unfair \\ SA & \(3 log_{4}(n)+3\) & 15 & unfair \\ PRRA & \(4.5 log_{2}(n)-1\) & 35 & fair \\ IPRRA & \(2.5 log_{2}(n)\) & 20 & fair \\ PLA & \(2 log_{2}(n)-1\) & 15 & fair \\ FSA & \(3 log_{4}(n)+2\) & 14 & fair \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Complexity analysis of the arbiters. Figure 8: Experimentalmodule. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Port** & **PPA [19]** & **SA [21]** & **PRRA [23]** & **IPRRA [23]** & **PLA [25]** & **FSA** \\ \hline \(N=4\) & 0.15 & 0.14 & 0.20 & 0.20 & 0.19 & 0.14 \\ \(N=8\) & 0.21 & 0.20 & 0.26 & 0.25 & 0.24 & 0.21 \\ \(N=16\) & 0.27 & 0.23 & 0.34 & 0.30 & 0.28 & 0.23 \\  
The achieved areas are presented in Table 4 and Figure 9b. As shown in Figure 9b, since the arbiters mentioned are decentralized structures, the area of each arbiter is grown linearly with \(N\). Owing to the more complex structure of the FSA's leaf nodes, the proposed arbiter did not achieve better outcomes in comparison to simple arbiters. The area reduction in ASIC implementation was obtained using the parallel prefix FPA structure, which simplified the structure of the upper node. Averagely, the PRRA has the smallest area owing to its simple structure. The FSA performed better than SA, with 12.2% area reduction on average. Furthermore, we implemented the arbiters on Xilinx's VC709 [30,31] development board to evaluate the performance of the arbiter on the FPGA.