## 1 Introduction  
Data traffic exponential growth has pushed forward the demand for high speed, high performance, energy-efficient and cost-effective data transmission [1]. Due to the large number of transmitters required, the current InP-monolithic integration platform used to fabricate photonic integrated circuits (PICs) is challenged [2]. The silicon (Si) photonics platform holds a great promise to ensure PICs fabrication scalability since it allows benefitting from the mature complementary metal oxide semiconductor (CMOS) industry [3]. However, it is highly challenging to fabricate a laser source only from Si due to the intrinsic nature of its indirect bandgap. Alternatives based on strained Ge, Ge-Sn materials grown on Si wafers have permitted band-gap engineering and even laser demonstration [4], but performance is still far behind the one that can be obtained in the III-V conventional approach. III-V integration on Si is facing a booming development phase since the last 30 years due to the perspectives offered by combining III-V's emitting properties with Si-photonics. Hybrid integration of finished III-V laser die on Si photonic chip using flip-chip technique is the current commercialized solution [5]. It has the advantage of independent optimization of III-V and Si parts. However, both chips do not benefit from the same fabrication line. Assembly costs are also not optimized since it requires butt-coupling. Therefore, the full potential of Si photonics is not exploited. III-V-on-Si heterogeneous integration platform consists in bonding a III-V gain region, previously grown on InP wafer, on a silicon-on-insulator (SOI) wafer [6; 7]. This approach benefits from low-loss evanescent light coupling therefore reducing packaging costs. It can also take full advantage of large-scale Si fabrication process since the latter is done on large Si wafers [8]. Another attractive strategy consists in the direct growth of III-V gain materials on large Si wafer. In this approach, epitaxy and fabrication can be done using Si large-scale fabrication line. However, it is the most exposed to physical incompatibilities between III-V and Si materials in terms of lattice mismatch, polarity and coefficients of thermal expansion (CTE) differences inducing dislocations, AntiPhase Domaines (APDs) and cracks [9; 10]. In order to overcome these limitations, two main strategies have been developed. The first one consists in a planar growth using intermediate buffer layers in order to minimize the dislocations propagation through the active region [11]. In 2019, a successful laser demonstration based on a GaInAsP-MultiQuantum Well (MQW) active structure grown on Si was achieved under continuous-wave (CW) regime [12]. The latter involved a 3.9 \(\upmu\)m-thick buffer layer enabling the reduction of dislocation density to \(10^{8}\) cm\({}^{-2}\). The use of quantum dots (QDs) active region is favorable since it is much less sensitive to dislocations as compared to MQWs structures [13; 14]. Impressive laser demonstrations have been achieved with low threshold and high maximum power operation [15]. However, the use of a thick defective buffer layer underneath the active region may compromise efficient light coupling through Si waveguide. The second strategy consists in a selective regrowth of small-volume III-V materials on patterned SOI wafers to block dislocation propagation [16; 17; 18]. In this approach, there is no need for a thick buffer layer. Although high quality material has been achieved, the growth of complex MQW-based active region seems challenging. For now, no electrically pumped laser has been demonstrated. What is more, light coupling quality might be impacted if light has to go through a highly defective zone. Another emerging approach consists in transferring III-V finished components onto Si chips using micro transfer printing (\(\upmu\)TP). Proof-of-concept PICs demonstrations have successfully been achieved [19].