# Three-Level Hybrid Envelope Tracking Supply Modulator with High-Bandwidth Wide-Output-Swing
## 3 Circuit Design
### Three-Level Switching Stage  
The switching stage of three-level structure buck converter with two pairs of complementary power devices is shown in Figure 8. The drive capability of the logic signal transmitted by the control loop to 3L-SWR is relatively weak, and the size of the power device is usually large, so the buffer stage is needed to improve the driving capability of the control logic signal. Another function of the buffer stage is to prevent the power devices from being turned on at the same time to cause shooting-through phenomenon.  
The PWM waveform output by the control loop is responsible for the turn-on or turn-off of the switching device, and the specific implementation is shown with four operation states in Figure 9. Each state has two transistors on. The four situations of the control loop output are shown in Table 1, where high and low represent \(V_{DD}\) and 0 V, respectively.  
Figure 6: The AC simulation of the LA: (**a**) output Impedance of the LA at different CM voltages; (**b**) the linear amplifier frequency response simulation.  
Figure 8: Block diagram of 3L- SWR.  
Figure 7: The transient simulation result of the LA.  
Figure 9: The four situations of V\({}_{\rm SW}\) correspond to case 1–4, respectively.  
Case 1, when the control loop output sets P1N1 and P2N2 to logic high, MP1 and MP2 are turned off, MN1 and MN2 are turned on, the output node V\({}_{\text{SW}}\) is GND. The result is that the inductor current I\({}_{\text{SW}}\) decreases.  
Case 2, when the control loop output P1N1 is logic 0 and P2N2 is logic high, turning MP1 and MN2 on, MP2 and MN1 off, the output node V\({}_{\text{SW}}\) is \(V_{DD}/2\), increasing I\({}_{\text{SW}}\), and the capacitor C\({}_{\text{F}}\) is in a charging state.  
Case 3, when P1N1 is logic high and P2N2 is logic low, MP2 and MN1 are turned on, and MP1 and MN2 are turned off. At the same time, the capacitor C\({}_{\text{F}}\) is discharged, the I\({}_{\text{SW}}\) continues to increase, and the output node V\({}_{\text{SW}}\) is \(V_{DD}/2\).  
Case 4, when P1N1 and P2N2 are both logic low, MP1 and MP2 are turned on, MN1 and MN2 are turned off, the output node V\({}_{\text{SW}}\) is \(V_{DD}\), and the I\({}_{\text{SW}}\) continuous output, ensuring that SWR provides more load current. The four states are regarded as a cycle, and the V\({}_{\text{CF}}\) is stabilized around \(V_{DD}/2\) under the action of the control loop.  
As described in Section 2.2, the power loss of 3L-SWR is related to parasitic capacitor and on-resistance, and the loss can be minimized by choosing the appropriate capacitor C\({}_{\text{F}}\) and the size of MP and MN. Generally, there are three types of capacitors: metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, and MOS capacitors. Large capacitors increase losses and take up chip area. According to the capacitor density, parasitic capacitor percentage and linearity of the capacitor, nMOS capacitors are more suitable, as discussed in [29]. In order to make the voltage variation range of the capacitors smaller, nMOS capacitor C\({}_{\text{F}}\) is selected as 10 nF.  
The buffer stage in Figure 8 consists of a chain of inverters, which gradually increase the size and slowly increase the driving capability without wasting too much power loss.