## 3 Optimal Controller Design Using SDCS  
The principle of the control theory of discrete event systems is based on the principle that the desired properties of two Mealy machines are obtained by a third Mealy machine, that is, the controller, through an encapsulated signal. The control theory of discrete event systems is shown in Figure 4.  
As exemplified in Figure 4, the control theory of discrete event systems illustrates the scenario where two Mealy machines, denoted as \(\mathrm{M_{A}}\) and \(\mathrm{M_{B}}\), are involved, and the desired specification entails both machines being concurrently in state 0 and state 1. The theory demonstrates that a third Mealy machine, denoted as the controller, can achieve this through the synchronous parallel composition of \(\mathrm{M_{A}}\), \(\mathrm{M_{B}}\), and \(\mathrm{C_{a,b}}\), facilitated by encapsulating the signal b. Thus, employing the controller depicted in the figure enables the attainment of desired system properties over a given plant [48]. However, in most cases, the objective of discrete control synthesis is to derive this controller from a given plant and the desired specifications. In other words, discrete control synthesis endeavors to generate this controller. Figure 5 presents the principle of discrete control synthesis, where a controller C is obtained through relevant synthesis algorithms for a given system S and objectives O. Here, outputs are designated as X, and inputs as Y. \(\mathrm{Y_{c}}\) and \(\mathrm{Y_{uc}}\) are controllable and uncontrollable inputs, respectively. Thus, the controller, through controllable inputs, ensures the desired behavior of the system. Moreover, the discrete control synthesis method also serves as a model checking tool, thus always guaranteeing the desired system properties. Figure 4: Representation of the control theory of discrete event systems [28]. Figure 3: FOPID controller structure. In this study, discrete control synthesis was utilized using the ReaX tool. ReaX is a compiler with its own modeling environment, utilized for synthesizing a controller through relevant synthesis algorithms. In Figure 6, the steps for synthesizing a controller using ReaX's DCS are provided. Initially, the desired properties of a yet uncontrolled system are given as the logical negation of BAD states over an X state space. The set of states entering these BAD states with any uncontrollable signal is defined as IBAD. Ultimately, the remaining state space, with controllable variables, constitutes the portion where the desired system properties can be satisfied. However, in this scenario, input signals may not be singleton, and to bring behaviors to a deterministic level, the default values of input signals are determined. Additionally, as observed, the presented computational steps demonstrate that the legal state space is structured to be minimally restrictive, i.e., maximally permissive. The modeling environment of ReaX consists of parallel data flow equations, where all equations are compiled simultaneously during compilation to synthesize a controller. In this environment, the plant, specification, controllable, and uncontrollable inputs are encoded. The system is composed of arithmetic and logical expressions, akin to languages in the C-like family. Additionally, similar to Hardware Description Languages (HDLs), two types of variables can be defined: memoryless placeholders used to construct combinational circuits, and memory-based variables representing states such as registers. After the modeling process is completed, the relevant synthesis algorithms are employed to compile and generate the desired controller. The resulting controller is in a loadable form, and through  
Figure 5: Principle of the discrete controller synthesis [29]. Figure 6: Computational steps of DCS. additional tools like ctrl2 hdl and ctrl2C, it can be translated into C and HDL languages, facilitating its transfer to other environments seamlessly.