# Design Trends and Comparative Analysis of Lightweight Block Ciphers for IoTs
## 4 Related Work
### Hybrid
The cipher offers an average software throughput of 1.47 MB/s and passes standard statistical and avalanche tests, proving its randomness and effectiveness for securing resource-constrained IoTs devices. Despite its strong security and efficiency in software environments, RAZOR has limitations in hardware implementations. The use of rotation and XOR operations in its diffusion layer, although optimized for software, is less efficient in hardware compared to simpler bit-permutation techniques commonly used in other lightweight ciphers. This could restrict RAZOR's suitability for ultra-low resource or hardware-constrained environments. Additionally, while its security is validated against several attacks up to a specific number of rounds, its resilience beyond 10-15 rounds in the presence of advanced cryptanalytic techniques remains theoretical and would benefit from further empirical validation. SPISE [66] is an LWBC designed specifically for ultra-constrained environments such as RFID tags and wireless sensor networks. It employs a hybrid structure combining generalized Feistel network (GFN) and SPN-like fast diffusion, which enhances its security and efficiency. Supporting a 256-bit data block and a 258-bit key (including 2 control bits for subkey selection), SPISE replaces traditional S-boxes with bit-jumbling and permutation techniques, achieving confusion and diffusion with minimal logic. Its gateless key schedule is compact and efficient, modeled on Rubik's Cube-style operations. Notably, SPISE achieves just 728 gate equivalents (GEs)--one of the lowest recorded for such high data and key lengths--along with a fast delay of 1.364 ns and low-power consumption of 32.16 uW, making it highly suitable for secure low-power embedded systems. While SPISE boasts excellent hardware efficiency and strong resistance to major cryptanalytic attacks, it does carry certain practical limitations. Its use of a non-conventional S-box-free design--relying entirely on bit-jumbling and control-based key scheduling--may pose challenges for integration with cryptographic systems that expect more traditional SPN or Feistel structures with well-analyzed components. Additionally, its large block and key sizes (256 bits), while advantageous for future-proof security, may not align well with the needs of ultra-low latency or bandwidth-sensitive IoTs applications where 64- or 128-bit configurations are more common. Hence, while SPISE offers strong security and compactness, its high parameter sizes and unconventional operation flow might limit adoption in certain scenarios without further adaptation or standardization. GFSPX [67] is a 64-bit LWBC with a 128-bit key, designed for resource-constrained IoTs nodes. It uses a hybrid structure combining generalized Feistel network (GFN) and SPN architecture to overcome the diffusion limitations of classical Feistel ciphers. GFSPX introduces a dual-round function: F1 uses ARX (addition, rotation, XOR) operations for simplicity and efficiency, while F2 employs compact 4 \(\times\) 4 S-boxes and a P-layer for strong diffusion. The cipher achieves strong avalanche properties in just 6 rounds and demonstrates robust resistance to differential, linear, algebraic, structural, and key schedule attacks. Its hardware implementation cost is only 1715 gate equivalents (GEs) on a 0.13 \(\upmu\)m process, making it more efficient than PRESENT (1886 GE) and many SPN-based ciphers. GFSPX also performs well in software, reaching an encryption speed of 12.31 Mb/s, showing suitability for both hardware and software applications in lightweight environments. Despite its strong performance and low area cost, GFSPX has some limitations. While its hybrid GFN-SPN structure enhances diffusion and reduces round count, this added architectural complexity increases design and verification overhead compared to simpler Feistel or pure ARX designs.