## 3 Circuit Design  
For demonstration, a full 360\({}^{\circ}\) phase-shifting range VSPS employing the proposed architecture is implemented in the 130 nm SiGe BiCMOS GlobalFoundries process. Figure 5 shows an implementation of the architecture proposed in Figure 3c based on bipolar transistors. First, a balun converts the single-ended input signal into differential mode, and then a differential quadrature generator provides the in-phase and quadrature differential versions of the input signal. To improve input matching and noise figure (NF), an LC matching network is inserted between the quadrature generator and the input of the VGAs. The VGAs in this circuit are built using cascode amplifiers (QII-QIA and QQ1-QQ4), with the addition of four pairs of transistors (QS1-QS8) at the top that are selectively activated to select the quadrant. These transistors function as switches and are controlled by the voltages applied to their bases: \(VI^{+}\), \(VI^{-}\), \(VQ^{+}\), and \(VQ^{-}\). Within each quadrant, the phase is chosen using the current steering technique to control the gain of each of the branches (QCS1-QCS4). This is accomplished by acting on the DACs associated with each of the branches: \(DACI^{+}\), \(DACI^{-}\), \(DACQ^{+}\), and \(DACQ^{-}\). The advantage of using this technique is that the tail current is always the same and, therefore, the transconductance (\(gm\)) of the input transistors remains constant for all phase values. This results in a constant input impedance, so the input matching remains unchanged. Figure 4: Constellations: (**a**) generated from Figure 3b circuit; (**b**) generated from Figure 3c circuit. Figure 3: Differential vector-sum phase shifters: (**a**) 360\({}^{\circ}\) based on a double Gilbert-cell; (**b**) 360\({}^{\circ}\) based on a single Gilbert-cell and an adder at the output; (**c**) 360\({}^{\circ}\) based on a single Gilbert-cell, a subtracter at the output, and four switches to control the quadrant (proposed architecture). In the circuit design process, one of the most challenging components is the input balun, which allows the conversion of single-ended signals to differential signals at the input. Various types of passive baluns, including transformer baluns, rat-race baluns, and Marchand baluns, have been utilized in MMIC designs. Among these options, the Marchand balun stands out as the preferred choice for millimeter-wave designs due to its simplicity and wideband performance [35]. As depicted in Figure 6a, a conventional distributed-element Marchand balun consists of two quarter-wavelength coupled lines. This configuration ensures balanced signals across the load impedances (\(Z_{out}\)) at the two output ports when driven by an unbalanced signal at the input port (\(Z_{in}\)). Typically, the load impedances differ from the driving impedance (\(Z_{0}\)) at the input port. The primary limitation of distributed-element Marchand baluns arises from their size when applied to the relatively low frequencies used in LEO constellation receiver gateways (17.8 to 20.2 GHz). This limitation is attributed to the significant size of the required \(\lambda/4\)-lines, making it challenging to achieve compact designs. To address this size limitation, we employ a lumped-component Marchand balun based on the structure proposed by [35], as shown in Figure 6b. The \(\lambda/4\)-lines are replaced with \(\pi\)-type lumped component equivalents, and the inductances (\(L_{s}\)) are coupled together to introduce additional mutual inductance and reduce  
Figure 5: Implementation of the architecture proposed in Figure 3c based on bipolar transistors: (**a**) schematic of the VGAs; (**b**) input balun, differential I/Q generator, and matching network; (**c**) output subtractor based on a differential amplifier and buffer. the overall area requirement.