## 5 Broadband 6-Bit High-Accuracy Digital Step Attenuator  
Combining the aforementioned broadband compensation technologies with an on-chip level shifter structure, a novel 6-bit 10-20 GHz high-accuracy DSA was proposed and designed using 0.15 \(\upmu\)m GaAs pHEMT technology, and its schematic and corresponding layout are shown in Figures 14 and 15, respectively. It has a total area of 1200 \(\upmu\)m \(\times\) 1800 \(\upmu\)m, including six on-chip integrated level shifting circuits and all RF/DC pads, with the ATT having a core area of only 520 \(\upmu\)m \(\times\) 1800 \(\upmu\)m. During cascading of the units, deterioration in matching conditions can contribute to variations in performance, and hence, all the initial parameters are optimized (according to the electromagnetic simulation results) over several iterations to ensure overall quality and stability. In addition, in order to make RF performance as close to the real situation as possible, the data for the on/off states of  
Figure 12: (**a**) Schematic and (**b**) layout of the level shifting circuit.  
Figure 13: The time domain transient simulated results of the level shifting circuit.  
the switching transistors were measured and are provided by an on-wafer measurement system based on a four-port vector network analyzer Ceyear 3672E.  
Figure 16a illustrates the relative attenuation for all 64 states, from which it can be seen that the attenuator has a dynamic range of 31.5 dB and an amplitude resolution of 0.5 dB. In addition, there is no overlap between these various states, which exhibits a favorable monotonic amplitude control performance. Figure 16b shows the phase variation of each state with respect to operation frequency. All curves were limited to within \(\pm 3^{\circ}\) from 10 to 20 GHz, demonstrating precise phase control and verifying the validity of the proposed method.  
Figure 16: Performance results of the proposed DSA with measured switching transistors. (**a**) Relative attenuation and (**b**) phase error versus frequency for all the 64 attenuation states.  
Figure 14: Schematic of the proposed ultrawideband high-accuracy DSA.  
Figure 15: Overall view of the DSA with on-chip level-shifting circuit.  
As observed in Figure 17a, the root-mean-square (RMS) error of attenuation had a smooth response of 0.12 dB to 0.2 dB across the whole band, which also presented superior amplitude control. Moreover, it can be noticed that the maximum RMS phase error within the range of 10-20 GHz did not exceed \(2^{\circ}\), which verifies the feasibility of the proposed structure for phase compensation. Figure 17b illustrates the IL of the design, i.e., \(S_{21}\) in the reference state. Profiting from the prominent performance of the simplified T-structure in the 0.5 dB to 2 dB units, the maximum IL is below 5.3 dB, with an average insertion loss of 4.65 dB. Moreover, according to the results of Figure 17c,d, the return losses of input and output better than 15 dB in all states (cascading causes a deterioration of standing waves, but still maintains the specification for engineering applications). Table 2 summarizes the performance of the designed broadband DSA and compared with other reported attenuators with state-of-the-art methods. Based on the reference data, it can be noticed that the proposed positive voltage control DSA has a more compact core circuit with the same or more attenuation units. Despite the addition of six on-chip logic circuits, the overall size remains within acceptable limits, achieving the desired goal of significantly reducing the phase error and insertion loss of the DSA without an appreciable increase in area.  
Figure 17: Performance results of the proposed DSA with measured switching transistors. (**a**) RMS amplitude errors; (**b**) IL at the reference state; (**c**) \(S_{11}\); and (**d**) \(S_{22}\).