## 2 STFT Algorithm and Hardware Architecture  
\[X_{STFT}\left[k,n\right]=\sum_{m=0}^{N-1}x\left[m+nH\right]w\left[m\right]W_{ N}^{km},\ \ \ \ \ 0\leq k\leq N-1\,\ 1\leq H\leq N \tag{1}\]where \(x[m]\) is the input signal, \(w[m]\) is the window function, \(N\) is the length of the window, \(n\) is the time frame index, and \(k\) is the frequency index. Here, \(H\) denotes the hop length, and the overlap length between adjacent frames is \(N-H\). In addition, the overlap ratio between consecutive frames is \((N-H)/N\). At a specific time \(nH\), the signal \(x[m]\) is multiplied by the window function \(w[m]\). Therefore, Equation (1) can be defined as the FFT operation of \(x[m+nH]w[m]\). The STFT processor measures the frequency over time by moving the window function \(w[m]\) along the signal \(x[m]\) according to the hop length and performing the FFT operation on samples inside the window. The flow of the algorithm is shown in Figure 1.  
The STFT processor should be capable of varying the overlap ratio according to the window type to minimize the data loss due to the tapering window. Therefore, the STFT processor needs a windowing module that overlaps the input data stream at a certain overlap ratio and multiplies the signal by the window function. Figure 2 shows how windows are overlapped at ratios of 0%, 25%, 50%, and 75% in the windowing module. Figure 2b,c shows window overlaps at ratios of 25% and 50%, respectively, and that the windowing module requires at least two output channels to overlap a single data stream by 25% and 50%. Figure 2d shows a window overlap of 75%. In this case, the windowing module requires at least four output channels to overlap a single data stream by 75% overlap ratio. In addition, when the windowing module supports a 75% overlap ratio, channels 1 and 3 of the windowing module have a 50% overlap ratio, channels 1 and 4 have a 25% overlap ratio, and channel 1 has a 0% overlap ratio. In other words, a windowing module that supports a 75% overlap ratio also includes 0%, 25%, and 50% overlap ratios. Therefore, to support a variable overlap ratio, the windowing module should be able to receive a single data stream and create four data streams overlapped by 75% between each channel. Figure 1: Short-time Fourier transform (STFT) overview. The 75% overlapped data streams are output through the four channels of the windowing module as input to the FFT processor, which performs the FFT operation to measure the frequency content changes over time. As previously stated, current FFT hardware architectures that can be considered for designing an STFT processor are generally classified as single butterfly architectures, pipeline architectures, and parallel architectures. The parallel architecture has the most significant advantage in terms of throughput rate but has high hardware complexity. The single butterfly architecture has the lowest hardware complexity, but offers a low throughput rate. In contrast, the pipeline architecture offers a good tradeoff between throughput and complexity and is consequently used in many fields [20; 21; 22]. Pipeline architectures in FFT processors are classified as SDF and MDC. In the SDF architecture, the input sequence goes through a single channel and is reordered by a modified butterfly computational unit. Since this architecture requires only one complex multiplier per butterfly unit, it has low complexity and is commonly used in STFT processors. However, as shown in Figure 3, four FFT processors are required to design an STFT processor with a variable overlap ratio of maximum 75% using an SDF FFT processor. Thus, a large hardware area is required. In contrast, MDC FFT processors process data through multiple channels and perform an alignment of the data according to a signal-flow graph (SFG) using delay elements [23]. In the case of four-channel FFT, the R4 MDC FFT processor can be implemented in a lower area than four radix-2 SDF (R2 SDF) FFT processors [24].