# Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation
## 4 Hardware Evaluation for Iterative Decoding of Product Codes
### Experimental Results Based on Field Programmable Gate Array  
The FPGA for our hardware platform is XC6 VLX240T FPGA of Virtex-6 series manufactured by Xilinx (San Jose, CA, USA), considering the inner hardware resources needed by our encoders and decoders. The performance of product codes constructed by three Hamming codes and LDPC codes in IEEE 802.16e with code length of 576 bits and code rate of 0.5 is tested using the implemented platform. For the LDPC decoder, we adopt the OMS algorithm and the number of iterations is 30. For the Hamming decoder, we use the error-trapping decoding algorithm. For the prior probability information and extrinsic information, six bits fixed-point quantization is adopted, in which the integer and decimal parts are both three bits. In our implementation, the circuit can work at the clock frequency of 150 MHz. When the clock frequency is fixed, the throughput is mainly determined by the number of iterations of product codes. The throughput of different product codes calculated according to the data before decoding is shown in Table 1. It can be observed that, for the decoder using different Hamming codes, the maximum throughput without global iteration is similar, though, for longer Hamming codes, the throughput is a little larger. When global iteration between LDPC decoders and Hamming decoders is used, the throughput is linearly scaled by an iteration number. For the codec of product codes, the outer code length and the number of iterations have little effect on the logical resources occupied. Thus, different codecs for different product codes occupy almost the same logical resource. It can be observed that the increased complexity due to the outer codes is quite limited, especially for the decoder. For example, nine Hamming decoders only use 385 slices, which can be neglected compared with six LDPC decoders. Unfortunately, the memory resource is greatly increased in order to store the intermediate codewords or probability information. The logical resources usage of the hardware evaluation platform of the product code with Hamming code (1023, 1013) is shown in Table 2.  
The hardware test result of iterative decoding of the product code with Hamming (127, 120) is shown in Figure 12. It can be observed that, when BER is \(10^{-6}\), the product code without iteration has 0.45 dB coding gain compared with the LDPC code. In addition, the product code with two iterations has the coding gain of 0.45 dB over the product code without iteration. In addition, the product code with five iterations has the coding gain of 0.2 dB compared with the product code with two iterations. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Outer Code** & **Iteration Number** & **Throughput** \\ \hline \multirow{4}{*}{Hamming (127, 120)} & 1 & 151 Mbps \\  & 2 & 83 Mbps \\  & 5 & 36 Mbps \\ \hline \multirow{4}{*}{Hamming (255, 247)} & 1 & 166 Mbps \\  & 2 & 93 Mbps \\  & 5 & 41 Mbps \\ \hline \multirow{4}{*}{Hamming (511, 502)} & 1 & 175 Mbps \\  & 2 & 98 Mbps \\  & 5 & 41 Mbps \\ \hline \multirow{4}{*}{Hamming (1023, 1013)} & 1 & 180 Mbps \\  & 2 & 101 Mbps \\ \cline{1-1}  & 5 & 44 Mbps \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Throughput of the iterative decoders for different product codes. In addition, the hardware test results of product codes using outer codes with different code rates and code lengths are also illustrated, as shown in Figures 13-15. The performance of product codes with iterative decoding has obvious gain over the product code without iteration. It also can be observed that only very few iterations are needed for the proposed schemes, for when the iterative number increases, the additional gain becomes smaller. In summary, the test results verify the superior performance of iterative decoding methods for LDPC-based product codes.