## 1 Introduction  
The Fourth Industrial Revolution, characterized by the widespread use of smart factories and three-dimensional (3D) printers and scanners, has led to the release of new products within short development times. To ensure product quality, there are various types of tests that need to be conducted, such as conformity, performance, and operational feasibility checks, among others. However, some of these tests can cause damage to the product prototype during environmental testing, while others do not. Additionally, the number of prototypes available is generally insufficient, placing the designer or engineer in a situation where they need to strategize for the efficient use of prototypes in practice. At the same time, the requirements for product reliability and safety are higher than ever, making it challenging to obtain reliable information within a relatively short development period. To address this challenge and obtain precise reliability information that satisfies the requirements quickly, AT plans are widely used in practice. Although ATs are implemented along with the abovementioned strengths, they have some limitations in practical product development. At first, ironically, prior reliability information on the parameters of the acceleration model is necessary to plan an accelerated test for obtaining the reliability information of the product (see [PERSON] and [PERSON] [1], [PERSON] and [PERSON] [2], and [PERSON] and [PERSON] [3]). However, a newly developed product may not have enough prior reliability information for designing optimal AT plans. Prior information is essential for designing classical accelerated test plans, as the accuracy of the reliability information depends on the quality of the prior information. To solve this issue of prior information, the pre-estimation method is introduced in [1; 2; 3]. However, there is no clear method provided for selecting the stress levels, test durations, and allocation ratio for each stress level to address this issue. Second, with respect to the optimization of AT plans, the determined stress levels commonly exceed the normal use conditions. Additionally, it is also challenging to determine the suitable maximum level of stress variables in practice. Furthermore, when more than two stress levels are required, the reliability test requires a relatively large number of test units that cannot be used for other purposes at the same time due to the nature of the reliability test. Normally, the reliability test causes damage to the product and cannot be used to test the product for other purposes. Therefore, a strategic approach is required to solve these practical limitations. That is, the lowest stress level is fixed as the usage condition to address the issue of the unrealistic high stress levels of AT plans. PATs can be a solution to this problem. In the PAT concept, the lowest stress level is set as the normal use condition, enabling the acquisition of reliability information, as well as other general V&V test information, which is conducted under the normal use condition. In addition, some environmental tests are basically conducted at severe stress levels rather than under the normal use conditions. These environmental tests are well defined in the representative standards or specifications of the product field (e.g., high-temperature operating life (HTOL) tests in JEDEC). In the memory business, the HTOL specification is widely used, and the HTOL test for memory chips is conducted at high temperatures, with the test unit required to survive for a fixed period of time at a minimum. This provides a clue for resolving the limitation of AT plans. Specifically, the temperature specified in the HTOL specification can be considered the maximum stress level of AT plans.