# Harnessing FPGA Technology for Energy-Efficient Wearable Medical Devices
## 6 Analyses and Discussion
DPR is highly beneficial in scenarios where the algorithm can be broken down into sequential, functional blocks using a modular approach. In these scenarios, the output of the first block triggers the activation of subsequent blocks. This allows DPR to delay deployment until necessary, reducing static power consumption. Such deployments, based on fine-grained power modes and DPR, may also introduce some latency due to the gating-up or deployment time. However, they do not directly affect the accuracy of the results, which is extremely crucial in healthcare. **Development Complexities and Financial Barriers:** Despite the need for power optimization, developers also face several other difficulties, particularly regarding tools, programming languages, licenses, and costs. Development tools like Xilinx Vivado and Intel Quartus are complex and have steep learning curves, making them difficult to master. Debugging FPGA designs is also more challenging compared with software debugging due to the less intuitive tools. Programming FPGAs typically involves using hardware description languages (HDLs) like VHDL or Verilog, which require a different mindset focused on hardware parallelism and timing. While high-level synthesis (HLS) tools allow for programming in higher-level languages like C or C++, they are not as mature and can produce less efficient designs if proper design space exploration for suitable optimization directives is not performed, which is also time-consuming. Additionally, the cost of licenses for FPGA development tools can be prohibitive, especially for small companies or individual developers. The reliance on vendor-specific tools and IP cores can lead to vendor lock-in, limiting flexibility and increasing costs. Moreover, FPGAs remain expensive devices due to their high degree of flexibility and relatively limited production volumes compared with microcontrollers. **Shortcomings and Future Research Directions:** It has been observed that most researchers targeted high-end FPGAs, which inherently have higher power consumption. Ultra-low power flash-based FPGAs, along with hybrid model FPGAs, could be explored for power-sensitive WMDs. Moreover, some fundamental features of FPGAs, such as reconfigurability, customizability, and fine-grained control, are underutilized. The partial reconfiguration capability of FPGA helps save power by delaying the implementation of a specific part until it is needed during operation [80]. Specifically, when addressing the relaxed sampling deadlines associated with physiological monitoring [19], there is an opportunity to leverage _fine-grained power modes_ and _custom clock-gating_ techniques. These features could be useful when adopting a modular approach to achieve power reduction:  
* _Flash-based and hybrid FPGAs_, which are designed for low-power applications, should be further explored for power-sensitive WMDs. * _Dynamic partial reconfiguration_ should also be further exploited in scenarios where the algorithm can be decomposed into sequential functional blocks. In such cases, the output of the first block determines the activation of the subsequent block, a characteristic inherently present in physiological monitoring. By leveraging DPR, the implementation of a subsequent block can be delayed until it is needed to avoid static leakage. * The capability of _power gating_ was also found to be underutilized in the reviewed literature related to WMDs for physiological monitoring. This can also be explored in conjunction with _fine-grained power modes_ to significantly reduce static power consumption. This approach works by cutting power to inactive logic blocks, thereby minimizing leakage currents. This approach can introduce latency but does not directly impact the accuracy of the results. * Exploring external _voltage scaling_ for physiological monitoring is also essential.