## 3 Results and Discussion
This revelation indicates the practicality of deploying multilevel cells (MLCs) that necessitate shorter durations of programming, thereby augmenting both the capacity and efficiency of data storage in memory devices. An increase in the programming voltage leads to a significant increase in the amount of charge injected into the charge trapping layer, which greatly contributes to a higher \(\Delta\text{V}_{\text{th}}\). This suggests that the intensity of the programming voltage, along with the programming span, plays an integral role in bolstering the memory functionalities of the device. Precisely, prolonging the programming interval results in a commensurate rise in \(\Delta\text{V}_{\text{th}}\), owing to the aggregation of an enhanced volume of charge within the charge trapping layer. It is important to understand that achieving a desired \(\Delta\text{V}_{\text{th}}\) target of 1.5 V requires different programming durations depending on the voltage polarity. A positive  
Figure 2: **(a)** Transfer characteristics observed when the memory device is subjected to a range of positive gate biases, applying such biases for a short programming duration of 5 ms. **(b)** Transfer characteristics under a spectrum of negative gate biases, also conducted over a programming time of 5 ms.  
voltage of 11 V can be programmed in 10 ms, while a negative voltage of \(-12\) V requires a longer period of 30 ms. This observation highlights the exceptional programming efficiency manifested when leveraging a positive gate bias within memory devices [16]. In contexts entailing negative voltages, the necessity for both an augmented voltage and an extended duration of programming to replicate the \(\Delta V_{\text{th}}\) observable under positive voltage conditions becomes apparent. This requisite predominantly stems from the intrinsic properties of IGZO as an n-type semiconductor, which impedes the conduction of holes. Consequently, this culminates in a reduction in the efficiency of negative erasure within IGZO TFT memory devices, chiefly due to a scarcity of holes within the channel layer [17]. The facilitation of hole transfer from the channel to the charge storage layer through F-N tunneling is notably hindered under a negatively biased gate. Conversely, the exposition of the device with a positive gate bias unveils its exceptional programming proficiency. For instance, maintaining a programming voltage at 12 V facilitates a notable  
Figure 3: (**a**) Relationship between the threshold voltage shift (\(\Delta V_{\text{th}}\)) and programming duration, with applied voltages for positive scenarios and for negative ones. (**b**) Relationship between the absolute value of \(\Delta V_{\text{th}}\) and the quantity of programming/erasing cycles, highlighting results for both a 12 V positive voltage and a \(-14\) V negative voltage. (**c**) Transfer properties of the memory unit when subjected to a programming sequence at positive 12 V, subsequently followed by an erasure process at negative 14 V. (**d**) Transfer properties when the memory unit is initially programmed at negative 14 V and then erased at positive 12 V.  
augmentation in \(\Delta\)V\({}_{\text{th}}\), escalating from approximately 2.4 to 3.7 V as the programming period extends from 5 to 30 ms, mirroring the behavior delineated under a \(-\)14 V scenario as exhibited in Figure 3a. To further probe into the program/erase (P/E) dynamics of these memory devices, the influence of P/E cycle frequency on \(\Delta\)V\({}_{\text{th}}\) was meticulously evaluated. Figure 3b accentuates the results of consecutive P/E operations, where, notably, post 400 P/E cycles, the devices consistently display a stable storage window of about 3 V, irrespective of voltage polarity. This constancy serves as a testament to the devices' fluid switching faculties and their robust electronic program-erase attributes [18].