## 3 Proposed LDPC Architecture
### Block Diagram  
In the field of 5G-NR LDPC decoding, our proposition is based on a code word rate of 2/3. A code rate of 2/3 offers a good balance between throughput, decoding complexity, and error correction capability. At this rate, 2 out of every 3 bits in the codeword carry information, resulting in a relatively high data transmission rate. The proposed design achieves area efficiency while exhibiting strong potential for high-throughput data transmission, which is a key requirement for 5G-NR. The block diagram has the following components: a control unit, interconnection blocks (Reading network and Writing network), processing units (Subs_Unit, MSU, and Add_Unit), shifting blocks (Shift_block and Shiftback_block), and memory units (MSU_RAM and Lyr_RAM). Each component within the decoder meticulously tailors its architectural design to perform a distinct and well-defined function in the global decoding pipeline. The decoder operates based on BG1. As previously stated, the base matrix entries (Shamt) vary within the range \(-1\leq\) Hp(i,j) \(\leq 383\). The message bits are associated with the first 22 columns of BG1 entries, while the subsequent 46 columns link to the parity bits. The rate-matching process determines the appropriate quantity of  
Figure 2: Blocks structure of 5G-NR base graph BG1. parity bits to combine with the message bits. This ensures the decoding process aligns with the specific application requirements and performance goals. This architecture, with the maximum expansion factor (Shamt) and post-matrix expansion, enables the maximum information length of 8448 bits (22 \(\times\) Z) in 5G-NR communication. Figure 3 displays a simplified diagram of the architecture. During the initial iteration, the control unit's first output In-Adr, provides the decoder with the channel's received LLRs by sending a binary \"1\" to the \"2:1 Mux\". Subsequently, In-Adr feeds a binary \"0\" to the \"2:1 Mux\" for the subsequent decoding iterations of the processed frame until the correction is completed or a maximum number of iterations is reached. The subsequent frames received from the channel repeat this process. The control unit's second output, Lyr-Ctrl, indicates the current processing layer for all blocks. Once fed into the decoder, the Reading network separates the received LLRs into processed and unprocessed (raw) data, based on the current processing layer (row). Data are categorized as processed or raw based on whether base graph entries are non \(-1\)'s or \(-1\)'s, respectively. The row weight \(dc\) varies between \(dc_{min}=3\) and \(dc_{max}=19\); hence, the processed data are passed using 19 \"Mp:1 Mux\" during each layer process. Following this, the raw data are concurrently sent via a group of Np-3 \"Mp:1 Mux\" directly to the Writing network. Once the layer decoding process is complete, the Writing network facilitates the concatenation of the raw with the processed data. Each 384 (Z) LLRs sequence is shifted using a chain of [Z \(\times\) b] multiplexers, with the condition that \(Z\leq 2^{b}\). Once converted into binary addresses, the Shamt data flow directly to the Shift_block. Simultaneously, the Shift-back_block receives the base graph's entries subtracted from the expansion factor (\(Z-Hp_{(i,j)}\)). The group of \(dc_{max}\) Subs_Unit receives the check node output values from the previous iterations of the same layer, which are referred to as OCN_msgs, and stores them in MSU_RAM. In the first iteration, the data remain unchanged throughout the Subs_Unit block, because there is no stored data in the memory yet, as the MSU process has not yet  
Figure 3: Comprehensive architecture of the proposed 5G-NR LDPC decoder. The blue lines represent the control data, while the black lines denote the data flow. occurred. In the other iterations of the same layer process, the Subs_Unit subtracts the OCN_msgs from the shifted LLRs. We restructured the Sub-Optimal Low-Latency technique outlined in [16] to suit the 5G-NR LDPC decoding.