# A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit
## 4 The Proposed Parallel-Cascade Configuration  
This paper proposes a parallel-cascade configuration to solve the variable phase alignment problem caused by voltage fluctuations during mode switching in the serial-cascade configuration. The configurations of the de-skew circuit and four-phase circuit are shown in Figure 8.  
Figure (a)a shows the traditional serial-cascade configuration of the DLL system. In this configuration, the system first enables the de-skew circuit for the phase-alignment mode to generate a stable clock output CLKII and then enables the four-phase circuit for the four-phase outputs generation mode. However, a potential problem has been discovered during post-layout simulation: when switching between different modes, this configuration causes a variable phase error related to the clock frequency due to power integrity issues. The root cause of this problem is that during the four-phase output generation mode, a large number of delay units and control units in the four-phase DLL are enabled, and the total system current increases significantly. The obvious increase of the operating current causes a larger IR drop on the supply network, which means that the supply voltage of the delay unit is reduced. Since the gate delay of a delay unit is closely related to the supply voltage, the delay of units in the delay path all change, including the units that generate skew and compensate for skew, thus causing an additional alignment error between SCLK and CLK0. At 25 \({}^{\circ}\)C, 1.2 V, tt, \(f_{clock}\) = 800 MHz, Figure 9 shows that the average power current of the system is 4.09 mA during the de-skew mode, which increases to 9.58 mA during the four-phase outputs generation mode after switching, which leads to an increase of 40.12 ps in the alignment error between SCLK and CLK0. This phase error varies with the total number of units activated in the four-phase output generation mode at different frequencies, so it cannot be eliminated by only improving the matching of circuit and layout. To solve this problem, a parallel-cascade configuration is proposed in this paper, as shown in Figure (b)b. The DLL system first operates in parallel mode with both de-skew and four-phase circuits enabled and then changes to cascade mode after the four-phase circuit is locked. By working in parallel, the delay and control units required for locking at this frequency are enabled, so the total current of the power supply network remains stable during the loop locking process, thus solving the variable alignment error caused by serial-cascade configurations. As shown in Figure 10, the average power current keeps stable at around 10 mA during the locking process, and the alignment error after locking keeps at 8.12 ps. In addition, another advantage of the parallel-cascade configuration is that it reduces the total locking cycles compared to the serial-cascade configuration by working in parallel. Figure 8: The configuration of the de-skew circuit and four-phase circuit. (**a**) Serial-cascade configuration; (**b**) parallel-cascade configuration. In order to support the proposed configuration, as shown in Figure 11, a mirror path is added to the input of 4P-DCDL to make the de-skew path and the four-phase path independent of each other, providing a stable input clock to two loops, respectively, which enhances the robustness of the system; a MUX is added to control the mode switching, and the error caused by switching is minimized by matching the path delay of CLK0 and its mirror output DCLK0. In addition, with the feature that the locking cycles of de-skew circuit are larger than that of four-phase circuit, the loop of the de-skew circuit can track the skew during the remaining locking cycles. After the four-phase circuit is locked, its control codes are fixed to maintain the phase relationships between the four-phase clocks. The input clock of the four-phase circuit is then switched from CLKI to CLKII, which is not yet fully de-skewed.