# Cybersecurity Comparison of Brain-Based Automotive Electrical and Electronic Architectures
## 4 Architectures
### Two-Brain (Zonal) E/E Architecture  
The two-brain architecture is the name given to the approach where modern vehicle functions (estimated at approximately 800) are evenly distributed on two HPCs. Each of these HPCs are further connected to telematics. The typical representation of the two-brain architecture is presented in Figure 13. Whenever, the architecture having more than one HPCs is sometimes referred to as Zonal architecture. The reason for the name is that, it is necessary to define the exact place of the vehicle to deploy the HPC due to its size and weight requirements. Possible places to deploy the HPCs of the two-brain architectures are the front left and the front right side of the vehicle. Some OEMs use the term Zonal architecture to refer to the placement of the ECUs (left front, right front, left back, right back, and center/roof to manage the local sensors and actuators) which are then connected to the HPCs. The architecture can have many sensors and actuators evenly distributed on a load capacity basis to two HPCs either directly connected to HPCs or connected through ECUs in between. * **Use Case:** The use case of two-brain architecture is shown in Figure 14 where RKE function is provided by Brain1 HPC and Autonomous Driving (AD) function is provided by Brain2 HPC. For providing RKE function, Brain1 HPC needs to interact with the Keyfob. To provide AD function, Brain2 HPC needs to interact with the 360 camera. The communication between the Telematics and Brain1 HPC/Brain2 HPC is done over Ethernet links. Normally, the interactors (Keyfob, RKE, 360 camera, AD) uses bus systems to communicate with the Brain1 and Brain2 HPC. Figure 13: Representation of Two-Brain E/E Architecture. The two-brain architecture has been modelled using Medini Analyze and is shown in Figure 15.  
The assumption of the two-brain architecture is that the load is evenly distributed in two HPCs. HPC 1 and HPC 2 are the two processors which have even loads (for example, 400 each, in case of 800 total functions). In this example, two functions, one for the remote keyless entry (RKE) and another one for Autonomous Driving (AD) are directly connected with the HPCs, which are represented in Figure 14.  
The performance of the two Brains can be homogeneous or heterogeneous based on the functional, security and safety requirements of the architecture. In this article, the assumption of having Brain2 HPC with more performance and memory capacity enables us to host Autonomous Driving (AD) functions, such as, to capture 360\({}^{\circ}\) camera images, and then detect objects. **Advantages of the Two-Brain Architecture:**  
* It provides redundancy to the one-brain architecture. If the same functions are hosted in both HPCs, then the failure of one HPC will not make the vehicle non-functional. If  
Figure 14: Use Case Representation of Two-Brain Architecture. Figure 15: Realization of Two-Brain Architecture in Ansys Medini Analyze. different functions are hosted in both HPCs, then the failure of one HPC will make the vehicle probably partially non-functional. * It has a higher performance and efficiency compared to the one-brain architecture. * It provides the possibility for load-balancing, which provides redundancy of the functions which are safety and security critical. * When two heterogeneous HPCs are deployed, the vulnerabilities of one HPC might not be available in the other HPC, thereby, it makes the architecture more secure than the one-brain architecture. * Two HPCs allow more software run-time environments to functions. Therefore, it is easier to design homogeneous and heterogeneous functions. * The architecture can be cost effective compared to the one-brain architecture when two HPCs with lower configuration are used, rather than having higher configuration in one HPC. **Disadvantages of the Two-Brain Architecture:**  
* Increased complexity in the network due to the interconnection of brains. * More communication nodes and cables due to the additional HPC.