## 2 III-V-on-Silicon Integration Technology  
### Adhesive Die-to-Wafer Bonding and Wafer-to-Wafer Bonding Technology  
While there are various methods of transferring compound semiconductors onto a silicon-based waveguide platform (molecular bonding, adhesive bonding, anodic bonding, metallic bonding), adhesive bonding offers some significant advantages. Since the adhesive planarizes the surface, the cleanliness requirements are more relaxed, resulting in a significant reduction in bonding preparation. In addition, surface roughness requirements are relaxed.  
The adhesive of choice in our work is DVS-BCB (divinylsiloxane-bis-benzocyclobutene), because of its low curing temperature, high degree of planarization, high optical clarity, good thermal stability, excellent chemical stability, low moisture absorption, and wide applicability, as will be shown in the examples below. Diluting the DVS-BCB with mesitylene, thin bonding layers can be achieved (\(<\)50 nm). The largest disadvantage of DVS-BCB is probably the low thermal conductivity, especially in the context of power consuming devices such as semiconductor lasers or optical amplifiers. However, with sub 100 nm thick bonding layers, the several micron thick buried oxide of the silicon-on-insulator photonic integrated circuit (PIC) is dominant in the thermal resistance of the device.  
The bonding process is schematically depicted in Figure 1. It starts with cleaning both III-V and silicon-on-insulator (SOI). The SOI cleaning is performed by immersing the sample for 15 min into a Standard Clean (SC-1) solution, _i.e._, NH4 OH:H2O2:H2O 1:1:5, heated to 70. Alternatively, one can also use a microwave O\({}_{2}\) plasma. To achieve thin bonding layers, mesitylene is added to the DVS-BCB (Cyclotene 3022-35). The dilution depends on the required bonding layer thickness and the topography of the silicon PIC. Prior to bonding, the spun DVS-BCB is pre-cured to evaporate all the solvents. In this step, the DVS-BCB is already partially polymerized, making it more solid-like, thereby improving the bonding layer thickness uniformity. For the III-V preparation one or more sacrificial layers are etched. The etch chemistry depends on the material system. Afterwards, a thin (\(<\)10 nm) silicon oxide layer is deposited to improve the adhesion to BCB. Alternatively one can use the native oxide of the III-V surface. The III-V dies are then brought into contact with the DVS-BCB coated silicon  
Figure 1: III-V on silicon heterogeneous integration process flow (reproduced from [1]).  
photonics substrate and loaded in a Suss MicroTec ELAN CB6L wafer bonder. After pumping to vacuum and heating the sample to 150 \(\,\mathrm{\SIUnitSymbolCelsius}\), 300 kPa pressure is applied. After 10 min, the temperature is further increased to 280 \(\,\mathrm{\SIUnitSymbolCelsius}\) and the DVS-BCB is fully cured for one hour. The III-V substrate is removed by grinding and wet etching. The III-V membrane is now transferred to a Si sample. Because of the simplicity of the bonding process, it is very versatile. Virtually any compound semiconductor can be transferred, as will be discussed later on in the paper. In addition, multiple die bonding and full wafer bonding has been demonstrated [4].