# Design and Verification of Multiphase Multilevel Traction Inverter
## 1 Introduction  
Multilevel converters have been widely used in many industrial scenarios for medium and high-power applications, such as electric drive, electric traction, and new energy power generation, in recent years due to the rapid growth of power electronics technology [1, 2]. The advantage of multilevel inverters over two-level inverters (classical VSI) is characterized by lower \(\mathrm{d}v/\mathrm{d}t\) stress on the switches caused by the staircase output voltage waveform [3] and by the ability to create higher output voltage with a lower total harmonic distortion [4, 5, 6]. Existing multilevel converters can be categorized into four groups based on the circuit structure: modular multilevel (MMC), cascaded H-bridge (CHB), flying capacitor (FC), and neutral-point clamp converters (NPC) [1, 7, 8]. However, as the number of levels rises, integrating multilevel converters presents a variety of difficulties. In addition, fault-tolerant modules, circulating current suppression techniques, and capacitor voltage-balancing procedures are the primary considerations when running multilevel converters. Therefore, massive research has been done to solve these issues by upgrading circuit topologies [9, 10] and developing control mechanisms to solve these shortcomings [3, 5, 11, 12, 13].  
Another critical factor for multilevel inverters is the modulation techniques. The well-known modulation techniques are pulse width modulation (PWM), space vector pulse width modulation (SVPWM), sinusoidal pulse width modulation (SPWM), phase shifted carrier PWM (PSC-PWM) and the selective harmonic elimination pulse width modulation technique (SHE--PWM). Many articles for improving modulation strategies have been investigated [1, 14, 15]. The researchers [16, 17] have adopted a SiC technology instead of Si semiconductor switches. This technology contributes to lower switching losses and fast switching speed, improving efficiency and power density [18, 19].  
Despite the great use of multilevel inverters, these inverters suffer from their shortcomings. As the number of levels in the FC multilevel converter increases, the difficulty of controlling and designing also increases. Therefore, these shortcomings limit their application in this field. Also, in high-voltage and high-power applications, the disadvantage of CHB and MMC is the large number of modules [2; 5], large volume, and low efficiency [8; 9]. Based on the previous results [20], the TNPC topology was selected based on the simulation results. This topology offers the best results across multiple investigated topologies [21; 22]. Investigated topologies were standard six-phase Voltage Source Inverter (VSI), six-phase Neutral Point Clamped (NPC) topology, and six-phase TNPC inverter. The simulation results show that NPC topology has lower losses. On the other hand, the TNPC technology has slightly higher power losses, but from the components point of view, it uses 48 MOSFETs in total. The NPC topology uses 48 MOSFETs, but it contains an additional 24 diodes. All MOSFETs and diodes are doubled due to the power output of the inverter. Based on these simulation results, the TNPC topology was selected for practical verification. Due to its higher complexity, it offers better performance results and better control of the semiconductors. Table 1 shows summary of the different inverter topologies analysis.  
Due to the inverter to be able to deliver required output power, design and simulations in papers calculates with two power components in parallel. Due to this fact, Table 1 shows number of components for this case.  
This paper deals with the design and detailed description of the hardware parts of the 6-phase three-level TNPC inverter. Measurements with efficiency evaluation for different voltage levels and modulation indexes are presented at the end of the paper. The paper addresses a novel design of the TNPC inverter for six phase loads utilizing SiC semiconductor technology. Target of the design is maximizing power density.