# Real-Time Simulator for Dynamic Systems on FPGA
## 4 Development of the Prototype and Results
### Netlist Analysis  
In the approach of scenario 1, the shortest possible implementation time was 218.283 ns (maximum frequency of 4.581 MHz). For scenario 2, the shortest time was 196.622 ns (maximum frequency of 5.086 MHz), which was the shortest time among all the implementations. These values contrasted to those reported in the literature, where the time periods were in the region of microseconds. The time periods found for the system in question were more than sufficient for performing all the computations of the simulated model. However, the simulation could be accelerated, since there was a delay between the time for computing the next value and the data deadline. This became much clearer with analysis of the worst-case slack value, which represents the period of time that the system remains idle. Tables 4 and 5 provide the values obtained for the implementations in each of the scenarios. It can be seen that there was a large excess of time for implementations with click time of 1 ms. The negative values in Tables 4 and 5 indicate that the system was unable to achieve the set time, informing the time still required. This was precisely the inverse of the period described as the idle time. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Method** & **Mean Error** & **Mean Square Error** & **Error Variance** \\ \hline Euler & \(0.0477\) & \(0.4531\) & \(6.553\times 10^{-7}\) \\ Improved Euler & \(-0.1442\) & \(0.7013\) & \(1.8618\times 10^{-6}\) \\ Third-order Runge–Kutta & \(-0.1472\) & \(0.5983\) & \(2.8418\times 10^{-7}\) \\ Fourth-order Runge–Kutta & \(-0.4462\) & \(0.4435\) & \(6.3756\times 10^{-6}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Data analyses for scenario 1. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Method** & **Mean Error** & **Mean Square Error** & **Error Variance** \\ \hline Euler & \(0.0473\) & \(0.4521\) & \(6.5167\times 10^{-7}\) \\ Improved Euler & \(0.0477\) & \(0.4531\) & \(6.553\times 10^{-7}\) \\ Third-order Runge–Kutta & \(-0.1442\) & \(0.7013\) & \(1.8618\times 10^{-6}\) \\ Fourth-order Runge–Kutta & \(-0.1472\) & \(0.5983\) & \(2.8418\times 10^{-7}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Data analyses for scenario 2. Figure 25: Result obtained in the RTSDS-FPGA for scenario 2. The signal represents the vehicle’s speed as a function of time, \(v(t)\), and also corresponds to the differential equation presented in Equation (17). (**a**) Result obtained in the RTSDS-FPGA with the Euler method. (**b**) Result obtained in the RTSDS-FPGA with the improved Euler method. (**c**) Result obtained in the RTSDS-FPGA with the third-order Runge–Kutta method. (**d**) Result obtained in the RTSDS-FPGA with the fourth-order Runge–Kutta method. A study of occupation was also undertaken (Netlist). Tables 6 and 7 show the values for the use of LUTs, registers, memories, and multipliers, obtained by analysis of the reports generated by the ISE (the development environment used by Xilinx) for each scenario. The amount of area occupied by the entire system was approximately 53%, taking into account the multiple system replies required to implement the various ODE solution methods. This area could be reduced if time was invested to research simpler solutions (for example, using only one solution method) or to avoid creating multiple replies. Nevertheless, the fully parallel implementation was an important differentiating feature of the proposed method. It is useful at this point to provide a summary of the results. The first observation that can be made concerns the first point set out at the start of the paper; execution of the simulation in real time was achieved. This is clear from the graphs presented in Sections 4.4.1 and 4.4.2, where it can be seen that the behavior of the system implemented using the RTSDS-FPGA was in agreement with the validation data obtained using Matlab/Simulink and Matlab/System Generator. The graphs show that the signal increases and decreases were executed in very similar time periods.