# A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis
## 3 TSV Reliability
### Stresses  
Through heating and cooling processes, the through-silicon via (TSV) undergoes volume changes which can result in induced stresses. The TSV processing temperature is typically higher than the post-operating temperature, leading to residual stresses that can impact both the silicon and the TSV. The magnitude of the induced stresses in the TSV depends on several factors, including the diameter of the TSV and the difference between the processing and operating temperatures. Larger TSV diameters tend to have greater stress magnitudes because the equivalent force and deformation increase as the distance from the center of the TSV to the edge of the silicon increases [28] (Figure 10). This residual stress can lead to delamination and even cracking during the lifetime of the component, which can lead to the failure of the entire integrated system [51]. The through-silicon via (TSV) copper experiences elasto-plastic deformation and creep during the manufacturing process, which exposes it to high thermal loads. As a result, the stress distribution during the service process may differ significantly from the previous process, which leaves behind thermal residual stresses that do not cause deformation at stress-free temperatures. Moreover, different components of the IC have distinct thermal residual stresses due to variations in their package flatness planarity (PFP), thermal loads, locations, and structures, as well as elasto-plastic deformation mechanisms. PFP-induced thermal residual stresses can substantially impact the TSV's future deformation [13; 18; 31]. Residual stresses are an important factor that affects the shape, size, and performance of devices, especially integrated devices (IDs) and micro-electromechanical systems (MEMS). These systems may undergo plastic deformation when subjected to thermal residual stresses that exceed the yield strength of the material. Additionally, when thermal residual stress surpasses the material limit, it may lead to crack formation and growth, which is highly undesirable. Therefore, it is crucial to reduce and eliminate thermal residual stresses to improve the mechanical properties and service life of these devices. To achieve this, optimizing the distribution of residual stresses by properly controlling the package flatness planarity, shape, and size of the ID can extend the mechanical properties and service life. Researchers have also investigated the relationship between residual stresses and fatigue life, focusing on improving the relationship between residual stresses and the PFP. Furthermore, analyzing and optimizing the PFP of 3D integrated circuits (ICs) can be performed through an effective and convenient finite element method. By utilizing this method, it is possible to achieve optimal PFP and improve the performance and longevity of the 3D ICs. Therefore, understanding and controlling residual stresses is critical to ensuring the reliable and efficient operation of microsystems, IDs, and MEMS [18; 52]. In addition, due to its higher coefficient of thermal expansion (CTE), copper mainly generates tensile radial stresses within the silicon, while compressive circumferential stresses occur within the silicon. Consequently, the interface between the TSV and the silicon substrate experiences the highest stresses, making it the most vulnerable to failure. The stress distribution also exhibits quadruple symmetry due to the cubic symmetry of the silicon crystal. At higher temperatures, such as during TSV annealing, copper expands, resulting in increased compressive stresses around the TSV laterally and additional pumping out along the TSV towards the chip surface. This can cause additional stresses and potentially delaminate the functional layers atop the TSV. However, annealing and chemical mechanical polishing (CMP) of the copper protrusions can mitigate this effect. Moreover, the radial and circumferential stresses generated by the CTE mismatch between the copper and silicon also impact the mechanical and electrical properties of the TSVs.