## 2 Unit Cell Design  
In this study, a combination of two types of unit cell geometries arranged in the same MS reflector were designed. Figure 1a-d shows a typical unit cell design consisting of a front side, back side, profile, and 3D view of two adjacent unit cells. This unit cell is composed of two PCB layers made by the Rogers Company, model RT/Duroid 5880 with \(\varepsilon r=2.2\)[21], and three copper layers of 0.5 oz thickness. The unit cell is composed of two vertical stripes in the top layer with each electrical connected to a pad, in conjunction with a varactor diode (used in this study) by a horizontal appropriate microstrip line. The varactor diode, model MAVR-011020-1411 of Macon [19], is used in this MS design due to its extremely low capacitance. The varactor diode is placed on the pad between the strips (see Figure 1 in green), adding variable capacitance _Cdiode_ to the unit cell. The dynamic range of the capacitance is _Cdiode max_ = 0.216 pF to _Cdiode min_ = 0.032 pF for 0-15 V reverse bias voltage, respectively. One of the vertical stripes has the same length as the unit cell width, W (used for the DC ground), while the second strip, \(S_{\text{L}}\), has a shorter length by 0.05 mm and is connected through a via to the back side of the PCB for the DC bias circuit. The middle copper layer acts as a metal ground for the unit cell, and it is separated by clearance (CD) from the via, as shown in Figure 1d. To have a symmetrical unit cell design, a mirror unit cell was added, as seen in Figure 1, where polarization- and propagation-instated reduction hits are perpendicular to the surface, as shown in Figure 1a. In this study, we propose a new concept referred to as the stripes configuration. The proposed configuration is composed of three stripes (1, 2, and 3) of two types of MS reflectors (Type A and type B) arranged side by side, as can be seen in Figure 2. Each type has a different unit cell design as shown in Table 1. The designed MS has three stripes with each stripe composed of four unit cell columns (Figure 2). Each stripe has a different dielectric substrate thickness, h, yielding a smaller dynamic phase range improving the reflected gain. Stripe one and stripe three are identical stripes with a thickness of h = 0.6 mm. The thickness of stripe two, in the middle, is h = 0.75 mm. Using the 3D electromagnetic simulation software CST, three different unit cell parameters were investigated and optimizedfor best performance. The final dimensions are summarized in Table 1. Two different MSs for 28 GHz were designed and investigated, based on the unit cells given in Table 1. The first is a typical uniform MS (one stripe) based on a uniform unit cell. The second MS is composed of two types of unit cells, type A and type B, arranged in three stripes, as shown in Figure 2.  
There are three absorption-loss mechanisms in the proposed tunable MS: varactor diode losses caused by internal resistance of the diode (R_diode_), dielectric losses, and ohmic  
Figure 1: The design of two adjacent unit cells. (**a**) Unit cell top layer. (**b**) Unit cell back layer. (**c**) Side view of the unit cell. (**d**) 3D view of the unit cell [8]. Figure 2: MS structure with three stripes stuck together. losses [8]. The dielectric losses and ohmic losses are well defined and quantified in the CST simulation. On the other hand, the varactor serial resistance R_diode_ is unknown, therefore experimental measurements from similar studies were used [22; 23], taking manufacturing process imperfections into consideration. The approximate value of R_diode_ was found to be 4 \(\Omega\)[22; 23]. Table 2 summarizes the electrical parameters that were used in the simulations. The proposed MS reflector was simulated using the TEM plane wave port with CST simulation software [24].