# Compressive Sensing-Based IoT Applications: A Review
## 4 CS-Based IoT Applications
### Processing Layer
Although the implementation of CS-based edge computing on the FPGA for IoT applications have never been addressed in the literature, we present herein some of the efforts which can be explored to provide powerful computing platforms. For any CS-based edge computing platform, efficient implementation of data reconstruction algorithms is the main task to realize. While a software implementation of these algorithms can be time-consuming due to the massive matrix multiplications requirements, an FPGA-based solutionpresents an attractive alternative to accelerate the reconstruction process by leveraging the high level of parallelism of FPGA platforms. Therefore, the hardware implementation for the different reconstruction algorithms has been investigated by the CS research community. In fact, greedy algorithms gained most of the attention compared to convex optimization approaches due to the high complexity of the latter. Nevertheless, from all the greedy algorithms, OMP has been the focus of most researchers due to its computing efficiency, stability and relative simplicity. Besides, in contrast to advanced greedy algorithms such as SP and CoSaMP, OMP does not require any inputs except for the compressed signal and the sensing matrix. OMP recovery algorithm includes two computationally expensive steps, namely, coefficients selection and signal estimation. Coefficients selection step requires intensive matrix-vector multiplication operations in order to find the closely correlated atoms to form the signal proxy. For high dimensional signals, matrix-vector multiplication is a very time-consuming process. The signal estimation step consists of solving a least squares problem which is both time and resources consuming as it includes both matrix inversion and matrix-vector multiplication. Therefore, all efforts have been made to provide an FPGA-based implementation for OMP rely on the optimization of these two fundamental steps. [PERSON] et al. presented the first implementation of OMP on Xilinx Virtex-5 FPGA [98] where the implementation was validated on a signal of length \(N=128\) and a maximum sparsity of 5. Although the size of the signal and its sparsity are small, the obtained results showed that adopting FPGA-based OMP implementation has great promises for real-world applications. Furthermore, the same authors further optimized their implementation by adopting Q-R decomposition (QRD) to solve the LS problem in [99]. The obtained results revealed three times faster execution time than their first implementation. Thereafter, various efforts have been made to provide more efficient FPGA implementation for OMP. [PERSON] et al. [100] proposed a solution to the LS problem based on QR decomposition using a vector multiplication unit (VMU) which consists of a large number of parallel computing channels. The proposed solution has been implemented on a Xilinx Virtex-6 FPGA. The authors evaluated their implementation on an image block of size \(32\times 32\) pixels achieving reconstructed quality with signal-to-noise ratio (SNR) of 23.5 dB with an execution time of only 0.63 ms. In [101] single-precision floating-point CS reconstruction engine implemented on a Kintex-7 FPGA is presented. The author fully explored the maximum hardware resources available to achieve high performance by deploying highly parallel architecture that shares computing resources among different tasks of OMP by using configurable processing elements (PEs). [PERSON] et al. [102] presented a descriptive analysis to OMP algorithm where they conducted a detailed study on the complexity of each step in the OMP algorithm. In addition, they adopted a Cholesky factorization method to solve the LS problem. A four-block architecture has been implemented on MATLAB-SIMULINK and Xilinx system generator (XSG) has been used to map the system-level design to a high-level description language (HDL). Subsequently, more efforts have been made to implement OMP for real-world signals. [PERSON] et al.