# Secure ECDSA SRAM-PUF Based on Universal Single/Double Scalar Multiplication Architecture
## 6 Conclusions  
This paper proposes a universal ECSM/ECDSM architecture for constructing the secure ECDSA SRAM-PUF presented herein. Initially, the paper outlines an attack scheme for PUFs constructed from conventional SRAM and ROM within SoCs. This scheme demonstrates that by repeatedly powering the system on and off and exploiting the SoC's processor to access SRAM and ROM to tamper with the \(P\) value, the PUF's unclonability can be compromised. This paper leverages the ECDSA to counteract this attack scheme and designs an SRAM-PUF architecture based on a custom ECDSA, ensuring the \(P\) value remains untampered with through the custom ECDSA. The paper proposes a universal architecture for critical operations, such as ECSM and ECDSM. For ECSM calculations within ECDSA, iterations of PA and PD can be performed directly; for the more time-consuming ECDSM calculations within ECDSA, a two-dimensional DAC is constructed through precomputation, followed by iterations of PA and PD based on the two-dimensional DAC. The ECDSM based on a two-dimensional DAC theoretically saves 16.7% of the computational overhead compared to executing ECSM twice, significantly increasing computation speed. Moreover, this universal architecture saves a significant amount of hardware resources due to the high similarity in the datapaths of ECSM and ECDSM. The secure ECDSA SRAM-PUF proposed in this paper is implemented on ASIC and FPGA. This design exhibits lower BER  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Design** & **Clock Cycle** & **Freq.** & **\#LUT** & **\#Silce** & **Latency** & **ATP** \\ \hline
[15] & 547 & 320.5 & 28,911 & 8460 & 3.413 & 28,878 \\
[16] & 4168 & 397 & 4271 & 1476 & 20.997 & 30,992 \\
[17] & 450 & 159 & 41,090 & 11,657 & 5.660 & 65,983 \\
[31] & 780 & 223 & 27,105 & 8736 & 6.995 & 61,113 \\
[32] & 3960 & 369 & 9965 & 2207 & 21.463 & 47,370 \\
[18] & 3960 & 351 & 10,955 & 3107 & 22.564 & 70,107 \\
[19] & 13,000 & 320.8 & 6169 & 2201 & 81.047 & 178,385 \\
[33] & 52,012 & 800 & \(-*\) & 4665 & 130.03 & 606,590 \\
[34] & 3426 & 135 & \(-\) & 3657 & 50.076 & 185,613 \\ This Work & 1958 & 296 & 13,912 & 3902 & 6.615 & 25,812 \\ \hline \hline \end{tabular}  
* Not reported in the literature.  
\end{table}
Table 3: FPGA implementation results on Vertex-7 series over \(GF(2^{163})\).  
and better ATP performance compared to existing research. In the future, we will further exploit DAC-based ECDSA over \(GF(p)\).  
Conceptualization, J.Z. and Z.C.; methodology, J.Z. and X.H.; software, J.Z. and K.L.; validation, J.Z., X.H., K.L. and Y.H.; formal analysis, J.Z. and M.M.; investigation, J.Z. and X.H.; resources, W.W. and H.D.; data curation, J.Z.; writing--original draft preparation, J.Z.; writing--review and editing, W.W. and H.D.; visualization, J.Z.; supervision, W.W., H.D. and X.L.; project administration, X.L.; funding acquisition, W.W. All authors have read and agreed to the published version of the manuscript.  
This work was supported in part by the Chongqing Natural Science Foundation under grant cstc2021 jcyj-msmxmX1090.  
Not applicable.  
All data can be provided upon reasonable request to the corresponding author.  
The authors declare no conflict of interest. [PERSON] is employee of UNISOC (Shanghai) Technology Co., Ltd. The paper reflects the views of the scientists, and not the company.