# A Novel Reconfigurable Vector-Processed Interleaving Algorithm for a DVB-RCS2 Turbo Encoder
## 1 Introduction
### Related Work  
The demand for ever-higher data rates has driven the development of specialized turbo-encoding hardware. Texas Instruments TCI6618 multicore DSP, for example, delivers up to 582 Mbps, while NXP MSC8157 SoC sustains 330 Mbps on similar workloads [28]. Beyond DSPs, FPGA-based implementations on Xilinx Zynq UltraScale+ platforms have achieved throughputs exceeding 800 Mbps by exploiting deeply pipelined, parallel interleaver designs [29]. More recently, heterogeneous SoCs like Intel's Versal ACAP--with its onboard AI engines--have demonstrated Turbo Encoder rates up to 1.2 Gbps by offloading interleaving and encoding kernels to dedicated vector units [30].  
On the software side, fine-grained SIMD optimizations on AVX-512 and ARM-NEON architectures yield performance improvements of over 60% compared to scalar implementations [31]. Building on these advances, our work introduces a novel algorithm that entirely eliminates modulo operations via vector-coalesced indexing, further boosting the interleaver throughput on modern VP architectures.  
In addition to DSP and FPGA solutions, general-purpose GPUs have been leveraged to accelerate turbo encoding for scenarios requiring ultra-low latency. \"GPU acceleration for Turbo encoding on modern architectures such as NVIDIA Ampere has been explored. Existing implementations achieve multi-hundreds of Mbps to low-Gbps throughput by parallelizing interleaver and Max-Log-MAP kernels across thousands of threads--providing sub-millisecond latency suitable for highly responsive communication systems [32].  
Recent ASIC research on Turbo and related channel coding has emphasized energy-efficient, high-throughput designs suited to next-generation radio systems. For instance, LTE-compliant Turbo decoder ASICs fabricated in 65 nm and 130 nm CMOS arrayed parallel architectures to achieve 300-400 Mbps throughput with under 200 mW power consumption [33]. Similarly, ASN-coset code ASIC implementations in advanced nodes have demonstrated area efficiencies of 120 Gbps/mm\({}^{2}\) and power consumption near 100 mW [29]. On the memory front, 3D-stacked logic-in-memory systems show that integrating near-memory compute tightly with high-bandwidth stacked DRAM can deliver substantial memory-bound performance gains [34]. Taken together, these results indicate that custom memory hierarchies and 3D-stacked Turbo encoder ASICs designed with folded inter leavers and near-memory compute could realistically achieve multi-gigabit throughput under sub-200 mW power budgets.  
The organization of this paper is as follows: Section 2 describes the specific TE implemented set by the DVB-RCS2 standard. Section 3, describes the original serial permutation algorithm and implementation. This algorithm serves as a reference for the speedup factor calculations. Section 4, describes the proposed vectorial and parallel permutation algorithm. Section 5 describes portability and architectural considerations. Section 6 describes the simulation-based analysis and depicts the results graphically. Finally, Section 7 concludes the results and achievements and proposes future research possibilities.