## 3 Proposed DC-GCDRAM Architecture
### Logic-Arithmetic Mode  
The configurable DC-GCDRAM can perform a certain logical and arithmetical operations between the row-wise stored DRAM words. In Figure 8, we show their computation schemes. During this operation mode, the CIM macro employs two row address decoders to activate two RWLs simultaneously and utilizes a NOR sense amplifier (NOR-SA) and a NAND sense amplifier (NAND-SA) within the computing logic to produce bit-wise Boolean logic primitives and addition results. The 8-bit-wide computation is realized by 16:1 column multiplexing. The logic-arithmetic operation begins by turning on the RBL switches and the read column gates after the BL and dellen (DL) prechargers are disabled. Then, two RWLs (RWL<i> and RWL<j>), which correspond to the memory cells storing operands 'A' and 'B', are activated. Depending on the status of the operands, the RDL will discharge, as shown in Figure 9, at three different levels. If AB = 00, the RDL does not discharge. Hence, the corresponding RDL voltage (VRDL0) is VDD. If AB = 10 or 01, one bit discharges the RDL. The resulting RDL voltage is VRDL1. If AB = 11, the RDL discharges more quickly, resulting in a lower RDL voltage (VRDL2). Comparing the RDL level against a NOR reference voltage (VREF_NOR) with the NOR-SA (SANOR) generates the NOR/OR results. Simultaneously, comparing the RDL level against a NAND reference voltage (VREF_NAND) with the NAND-SA (SANAND) produces the NAND/AND results. Moreover, the XOR operation is implemented by wiring the NOR and AND results to a NOR circuit. Similarly, the XNOR result is obtained by wiring the NAND and OR results to a NAND circuit. In addition, these Boolean logic primitives permit a full adder (FA) to be realized. A traditional FA produces SUM and carry-out (COUT) by adding three input operands A and B and carry-in (CIN). The Boolean equations for the SUM and carry-out can be expressed as follows:  
\[SUM\ =\ (A\oplus B)\oplus C_{IN} \tag{1}\]  
\[C_{OUT}\ =\ \overline{\overline{AB}*\overline{(A+B)*C_{IN}}} \tag{2}\]  
These indicate that a primitive A \(\oplus\) B can implement the FA's sum using a XOR gate, and that two primitives, (A + B) and \(\overline{\text{AB}}\), can implement COUT using two additional NAND gates. In Figure 9a, we have shown a circuitry implementing the bit-wise FA operation by the name of FA-logic. By cascading FA-logics, we realized an eight-bit ripple-carry  
Figure 8: Schematic of logic and arithmetic operations. (MDL: main dataline). adder (RCA), as shown in Figure 10. This 8-bit RCA operation is fully performed in one operating cycle. One thing to be designed with care might be the voltage reference scheme. In order to produce the correct logic functions, the reference voltages should satisfy the following conditions:  
\[V_{RDL1}+V_{OS}<V_{REF\_NOR}<V_{DD}-V_{OS} \tag{3}\]  
\[V_{RDL2}+V_{OS}<V_{REF\_NAND}<V_{RDL1}-V_{OS} \tag{4}\]  
where VOS is an offset voltage of the latch-isolation NOR/NAND-SAs in Figure 9b,c. In this design, we set the target levels of VREF_NOR and VREF_NAND to 0.86 VDD and  
Figure 10: Implementation of 8-bit ripple-carry adder. Figure 9: Computing logic: (**a**) circuit schematic (BSA: block sense amplifier), (**b**) NOR-SA, and (**c**) NAND-SA. The BSA consists of gated skewed inverters for single-ended RDL sensing. It is activated only during the read operation of the memory mode. \(0.38\)V\({}_{\text{DD}}\) as shown in Figure 11. In Figure 11(a), we show the reference circuits for the NOR/OR and NAND/AND operations. They form a ratioed circuit with two resistors. When the control signals (VREN_NOR, VREN_NAND) transit from low to high, the V\({}_{\text{REF}}\) voltage levels are simply determined by the ratio of two poly-silicon resistors: \(V_{\text{REF\_NOR}}\cong R_{2}V_{DD}/(R_{1}+R_{2})\) and \(V_{\text{REF\_NAND}}\cong R_{4}V_{DD}/(R_{3}+R_{4})\) where the equivalent resistances of transistors MP1, MN1, MP2, and MN2 are negligible. To obtain robust reference levels, the resistors were sized carefully across all specified temperature and process variations.