# DFT-Low-Latency Bit-Slice Design of Discrete Fourier Transform
## 5 Hardware Architecture of the FPGA-Based System: An Application Example
### The Proposed FPGA-Based Architecture
#### 5.2.1 The Timing Block  
This module generates all the timing signals, which regulate/control the system operation (Figure 7). Figure 5: The 16-QAM OFDM modulation scheme. Figure 6: The block diagram of the proposed architecture. The three inputs of the timing module, named clock, start, and reset, are the timing signal for the system provided by an oscillator/phase locked loop (PLL), a binary signal, which controls the processing starting and the signal for the reset, respectively. The nine outputs are  
* clk, which is the system clock, looked at the START signal. In fact clk is equal to 0 if START is 0 whatever the clock logic value;
* ROM_address, which is a 10-bit word. It addresses all the signal_ROM memory locations in which a function with 1024 samples is stored. Each sample is coded with 4 bits;
* END_ROM, which is a binary signal that takes a logic value of one after all the 1024 samples of the signal_ROM have been analyzed;
* K_clock, which is a timing signal for the sum block;
* K_value, which is a 10-bit word whose numerical value in decimal code indicates the current value of the \(k\) index in the expression for the BFT calculation;
* Count (twiddle address), which is a 10-bit word able to address the twiddle coefficients for their reading. * Twid_end, which is a binary signal that reaches the logic 1 value once all the 1024 twiddle coefficients have been sent to the processing block. Selection of 1024 twiddle coefficients is necessary for each processing cycle. * Sum_enable, which is a timing signal that controls the operation of adders in the processing block and the correct transmission of both test function samples and twiddle coefficients. * End_DFT, which is a binary signal that takes the logic value 1 once all the processing cycles have ended and the BFT values are outputs. The timing block consists of the below modules/circuits which perform the following functions (Figure 8). Figure 7: Black box representing the timing block with the relevant input and output signals. AND gate for the implementation of the clock gating technique. The system clock (named ck) is obtained as output only when the START input is equal to 1;
* only_Address (whose inputs are the system clock and the system reset) is a counter which generates the addresses of the ROM that stores the test signal. For each clock pulse, a 4-bit signal sample is available at the output. This module has been designed in-house by Authors adopting the Verilog hardware description language. * AND_reset which is a timed AND gate whose inputs are the system clock and the ROM addresses. The output (named end_ROM) achieves the logic 1 value once all the ROM addresses have been generated that is once all the 1024 samples of the stored function are sent to next stages for processing. Furthermore, this module is designed in-house by Authors in Verilog. * k_block which generates ROM addresses (in which twiddle coefficients are stored), a signal for sum block enable and an acknowledge signal to indicate the end of the DFT calculation. The schematic of the k_block is indicated in Figure 9.  
The index to extract the twiddle factor to be used at the generic step can be computed as the reminder of the integer division of the product \(k\cdot n\) by \(N\):  
\[index=mod(k\cdot n,N) \tag{9}\]  
This feature can be implemented using a circular register. In our implementation, instead, the proper selection of twiddle factors has been implemented by a \(mod-N\) counter that computes the indexes with step \(k\) and goes on until the \(N\) values needed in the calculation are reached:  
\[TwidVec=[1,W_{N},W_{N}^{2},...,W_{N}^{N-1}] \tag{10}\]  
Specifically, the k_block updates the twiddle factor for the \((kin)\)-th step of the computation by readressing: the twiddle factor for a generic \(k\cdot n\) value is extracted from the vector  
Figure 8: Schematic design of the timing block. defined in Equation (10) selecting the index placed \(k\) steps ahead the current position, at each change of the \(n\) value.