# Analysis and Design of a Diplexing Power Divider for Ku-Band Satellite Applications
## 3 Diplexing-Power Divider: Design and Performance  
The geometry of the proposed diplexing structure demonstrates its seamless integration potential with various planar microwave components, serving as a versatile modular device. This integration capability positions it favorably for inclusion in communication systems such as space applications when the necessitating dual operating frequency bands are met. The configuration of the ultimate diplexing power divider is depicted in Figure 6. This arrangement involves the interconnection of two pairs of Y-junction power dividers with the output ports of the aforementioned diplexing structure. In Figure 6a, the output ports for each power divider are denoted as SMA connectors 3 and 4. Notably, the structure geometry was optimized using the CST software suite. Figure 5: Simulated scattering parameters for the proposed diplexing structure. (**a**) Port 1 is excited. (**b**) Port 2 is excited. (**c**) Port 3 is excited. Figure 6: _Cont._  
The simulated S-parameters of the proposed diplexing-power divider are presented in Figure 7, originating from the simulation software. They show that the amplitude of the transmission coefficients from port 1 to port 3 or 4 surpasses the \(-\)4.5 dB threshold (Figure 7a). The same result is obtained when observing the transition from port 2 to ports 3 and 4 (Figure 7b). Given the inherent necessity to distribute power across two distinct ports, we can conclude that the achieved insertion loss was less than 1.5 dB. The impedance bandwidths for amplitudes of S\({}_{11}\) and S\({}_{22}\) less than \(-\)10 dB is 10.2% (13 GHz to 14.4 GHz) and 9.2% (16.6 GHz to 18.1 GHz), respectively. Isolation between uncoupled ports (ports 1 and 2) is more than 17 dB in the low-frequency band and more than 15 dB in the high-frequency band, based on the achieved charts in Figure 7. If port 1 is excited in the low-frequency band, the RF signal propagates into the lower power divider. After that, the propagated signal is vertically transitioned into the vertical transition. Once the signal is propagated into the vertical transition, ports 3 and 4 become active. The amplitude and phase of the signal at ports 3 and 4 are equal. In this situation, ports 1 and 2 are isolated from one another. On the other hand, if port 2 is excited in the high-frequency band, the RF signal is transmitted in the top power divider and it enters the vertical transition at the end of the top power divider. After it reaches the vertical transition, ports 3 and 4 become active. In this configuration, channel 1 and channel 2 are again isolated. For further assessment of the operational dynamics of the final power divider employing this compact module, an analysis of electric fields and their trajectories is prepared in Figure 8. In particular, Figure 8a portrays the scenario wherein port 1 serves as the designated input port, effectively isolating it from any potential interference between port 2. This configuration illuminates the transmission path of the wave reaching the output ports with equitably distributed power. Similarly, Figure 8b captures another electric field distribution path. This time port 2 is the input source and equal power is divided between the two outputs and no coupling to the other input connector is observed. Figure 6: Different views of the final diplexing-power divider system working at the Ku frequency band. (**a**) Configuration of the proposed architecture, and (**b**) top views of each layer (all dimensions are in mm). (Xoffset: 1.7 mm, Y\({}_{1}\): 5.9 mm, Y\({}_{2}\): 10.1 mm). As the last step towards validating the simulated performance of the proposed diplexer-power divider, a tangible prototype was fabricated and tested, as shown in Figure 9. During the assembly process, the layers were placed on top of each other and then screwed together (via threaded connections). The metal pins of the SMA connectors 3 and 4 enter the top PCB layer and pass through the copper and the second PCB layer.