# Architecture and Process Integration Overview of 3D NAND Flash Technologies
## 3 Fabrication Methods of 3D NAND Flash  
Gate-stacked 3D NAND architectures can be fabricated using two methods: gate-first and -last, and the most representative structures fabricated by the gate-first and -last methods are BiCS [1] and TCAT [4], respectively. Figure 14a shows the gate-first process, in which WLs are stacked first, and subsequently, channel holes are etched. The channel holes are filled with a charge-trapping dielectric and poly-Si channel layers [31]. Figure 14b shows the gate-last (gate replacement) process, in which oxide/nitride multilayers are deposited, which is followed by hole etching and channel poly-Si deposition. An additional process step, called the WL cut, is performed between the channel poly plugs. The WL cut is performed by dry etching; the nitride layer is removed, and the gate dielectric layers and metal gate are deposited. In general, the use of metal gate provides a faster erase speed, lower program/erase voltage, and a wider \(V_{\text{T}}\) margin by suppressing unwanted backward Fowler-Nordheim tunneling current [44]. The gate-first method of the BiCS [1] structure has a problem in that the hole-etch size is affected by the gate dielectric layers. In contrast, the biconcave produced by the WL cut process of the gate-last method prevents lateral charge loss [45] but increases a process difficulty [4]. Figure 13: (a) Aerial view of and (b) unit structure of STAR NAND flash [43], Copyright IEEE, 2012. Figure 15a shows the fabrication process of the BiCS structure. LSG, memory string, and USG transistors are fabricated separately, and poly-Si is used as the gate material. A transistor channel and a memory plug are formed by hole etching, using a punch-through method. Silicon nitride and tetraethoxysilane (TEOS) layers are formed by low-pressure chemical vapor deposition (LPCVD) for an ONO stack in the etched hole. Arsenic ions are implanted and activated in the LSG source and drain. The CG formation proceeds in the reverse order of the conventional SONOS deposition. The edge of the CG is etched in the form of stair-like steps by reactive ion etching. The entire layers are separated into two blocks through a slit to minimize disturbance. The USG operates as a row address selector using a line pattern and is simultaneously connected to the via hole, BL, and peripheral circuit [29]. Figure 14: (**a**) Gate-first method of BiCS flash and (**b**) gate-last method of TCAT with a WL cut process. Figure 15: Process flow of (**a**) a BiCS structure [29], Copyright IEEE, 2007, and (**b**) a PBiCS structure with a pipe connection. Figure 15b shows the process flow of the PBiCS structure string and the PC formation. A memory hole is formed by hole etching, and a sacrificial film is deposited. A PC is formed on the sacrificial film, which is followed by memory layer deposition. After the SG formation, the U-shaped sacrificial layer is removed and the memory films and silicon-body layer are deposited for CG formation on the memory hole, which allows for the pipe-shaped NAND string structure with better reliability characteristics [2]. Figure 16a shows the process flow of the VRAT structure. Firstly, oxide-nitride stacks are deposited on the Si mesa in order, and an active region is defined by patterning and etching. An undercut is created in each oxide layer by wet etching using a buffered oxide etchant (BOE), where each flash cell would be placed. All the gate stacks, including oxide-nitride-oxide and the poly-Si gate are sequentially deposited by LPCVD, with an improved step coverage. Subsequently, only the WL electrodes remain in the undercut region by the etch-back process, and they are separated from each other. The exposed part of the multi-stacked layers on the formed Si mesa is flattened by the CMP process, and the WL electrode is exposed. Then, each string is isolated by a poly-Si etch, followed by the contact process for WLs and BLs [35]. The VSAT structure simplifies the overall process compared with the VRAT by adopting a gate-first method, as shown in Figure 16b.