# Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing
## 2 Materials and Methods
### The \"SIMPLY\" Architecture  
To overcome the issues of the traditional IMPLY architecture, SIMPLY was introduced in [20]. SIMPLY is based on the implication logic and originates from the observation that Q must change its state only when P = Q = 0 (case 1 of the truth table in Figure 3d). SIMPLY detects this condition by applying a small V\({}_{\text{READ}}\) voltage pulse (200 mV in this work) to both P and Q, Figure 4b. The voltage at node N (V\({}_{\text{N}}\), Figure 4a) is compared against a threshold (V\({}_{\text{TH}}\)) to determine if P = Q = 0. If so, the control logic which is equipped with tri-state buffers, as in the IMPLY architecture, pulses V\({}_{\text{SET}}\) on Q, keeping the driver of P at high impedance; Figure 4b, blue lines. Otherwise, both P and Q are kept at high impedance; Figure 4b, dashed red lines. The condition P = Q = 0 is easily detectable since V\({}_{\text{N}}\) is lower in this case than in all other cases, ensuring a sufficient margin (i.e., read  
Figure 3: (a) Schematic of the IMPLY gate. (b) Pulses applied to the top electrodes of P (V\({}_{\text{P}}\) = V\({}_{\text{COND}}\)) and Q (V\({}_{\text{Q}}\) = V\({}_{\text{SET}}\)) to execute the IMPLY operation. (c) Pulse applied at the top electrode of P (V\({}_{\text{P}}\) = V\({}_{\text{FALSE}}\)) to perform the FALSE P operation. (d) Truth table of the IMPLY operation where the conflicting V\({}_{\text{SET}}\) and V\({}_{\text{COND}}\) requirements for gate functionality (*) and reduced degradation (#) for the four input combinations are evidenced. margin--RM) also when considering RTN and variability, as shown in Figure 4e. Moreover, the RM increases with V\({}_{\text{READ}}\), Figure 4e, which allows trading a higher RM (i.e., lower Bit Error Rate--BER) for power, thus setting precise parameter tradeoffs. SIMPLY requires no V\({}_{\text{COND}}\) and no fine control of the voltage pulses, overcoming the tradeoff between V\({}_{\text{SET}}\) and V\({}_{\text{COND}}\) and the need for very precise voltage control. The problem of logic state degradation is virtually resolved, as only V\({}_{\text{READ}}\) is applied to the devices that must retain their logic state. In fact, no degradation is observed up to (at least) 10\({}^{8}\) cycles, reducing BER by at least 10\({}^{8}\) compared to IMPLY, with no energy penalty (see Figure 5). Besides, SIMPLY needs significantly less energy as, for 3 out of 4 input combinations, only the two V\({}_{\text{READ}}\) pulses are delivered instead of the much larger V\({}_{\text{SET}}\) and V\({}_{\text{COND}}\) pulses, Figure 4b. To ensure high energy efficiency, we use the low-power and compact comparator design from [30], implemented in a 45-nm technology [34] (Figure 4d), which consumes 8f per comparison when T is in the range 0 to 85 \({}^{\circ}\)C and V\({}_{\text{DD}}\) is 2 V. The energy breakdown, including the comparator contribution, for all input combinations for IMPLY and SIMPLY, stresses the remarkable performance improvement, as SIMPLY reduces the energy per operation by 4\(\times\) on average and up to 57\(\times\) for the P = 0 Q = 1 input configuration, when considering technology 3 as an example (see Table 1). Depending on the RRAM technology, the energy consumption of the FALSE operation may be higher or lower than that of the IMPLYoperation (see Tables 1 and 2). So, it is important to also reduce the energy of the FALSE. This can be easily done in the SIMPLY architecture, by preventing the use of the high \(\mid\)V\({}_{\text{FALSE}}\mid\) when a device is already in HRS. The state of the device is read using the same V\({}_{\text{READ}}\) and comparator threshold used for the IMPLY operation, and the analog buffers are enabled by considering the inverted output of the comparator, see Figure 4c. This smart FALSE (sFALSE [30]) operation results in relevant energy savings (see Table 2). Figure 4: **(a)** Schematic of the SIMPLY architecture implemented on a linear RRAM array.