# Adaptive Coherent Receiver Settings for Optimum Channel Spacing in Gridless Optical Networks
## 3 Proposed Clock Recovery Circuit and Method
### Phase Detector  
The second key component is the phase error detector at the Rx to estimate the jitter. It is worth noting that the method re-uses the circuits available in typical Rx for clock recovery (including jitter approximation) and BER/FER estimations. For the former method such as Gardener-based detector [26] can be used, where the timing error detected for the \(\mathrm{k^{th}}\) symbol is given by:  
\[e(k)=\ a_{I}(k)+\ a_{Q}(k) \tag{7}\]  
where:  
\[a_{I}(k)=\{y_{I}((k-1)T+\ d_{k-1})-\ y_{I}(kT+\ d_{k})\}y_{I}\Big{(}kT-\ \frac{T}{2}+\ d_{k-1}\Big{)}\]  
\[a_{Q}(k)=\Big{\{}y_{Q}((k-1)T+\ d_{k-1})-\ y_{Q}(kT+\ d_{k})\Big{\}}y_{Q}\Big{(} kT-\ \frac{T}{2}+\ d_{k-1}\Big{)}\]  
And \(T\) is the period of symbol, \(d_{k}\) is the estimate of the phase at \(kT\) and \(y_{I}\) and \(y_{Q}\) are the received in-phase and quadrature components. \(\tau_{0}\) corresponds to positive zero crossing point and the expectation is normalized to unit interval. In addition, jitter rms is estimated as where:  
\[Jitter_{rms}=\ \frac{1}{T}\ \frac{\left\{E[e(\tau_{0})^{2}]\right\}^{1/2}}{slope (\tau_{0})} \tag{8}\]  
The phase-domain (\(\phi_{\mathrm{dBc}}\)) spectral density of the different contributors at the receiver is depicted in Figure 7. As can be seen, lowering the clock recovery bandwidth effectively helps in filtering out the impact of the adjacent channel interference (in yellow) and would provide better signal integrity with respect to the transmitter clock extraction. A scheme that takes into consideration phase noise induced by channel and where the effective clock recovery bandwidth and gain can be digitally programmed, to optimize the spacing, can be integrated into SDN framework.  
Figure 7: Phase-domain spectral density of different contributors.  
To elaborate further, we note that when measuring SNR, and while noise is uncorrelated with zero mean, if the signal (phase error) is averaged over \(L\) observations the estimate is smoothed-out. That is the equivalent of lower loop' bandwidth prior to producing a control signal. As we will see in the results, the system performance gets better if there is no high-frequency noise source that goes untracked. In addition, optimizing the clock recovery bandwidth reduces the effective tracking by the receiver of the other sources of jitter. As shown in Figure 7, we assume \(\mathrm{J_{rx}}\) (jitter induced by Rx) is tracked by the receiver PLL and \(\mathrm{J_{channel}}\) can be estimated from neighboring channels in the same MC. For the cases of low transmitter clock standard deviation in the total phase error (\(\mathrm{J_{rx}}\)), we can simply base the optimized parameters (bandwidth and gain) on the specification (i.e., targeted jitter to guarantee no guarantee no cycle slip in the ADC sampling) in order to perform a fitting to extract optimal channel spacing. The \"Digital LPF\", shown in Figure 6, is implemented as simple proportional/integral control scheme, as in [27]. The higher the gain, the faster the loop reacts to changes. However, there is a trade-off between amounts of noise let through versus the agility in tracking higher frequency components.