## 6 Simulated and Experimental Results  
### Simulated Results  
To validate the theoretical notion, the PT's modeling and simulation results were taken using MATLAB/Simulink software. The modeling and experimental factors are enumerated in Table 4.  
Figure 5 illustrates the time-varying outcomes of line voltages and pole voltages for a PT. The source configuration is held constant at \(Vdc\) = 100 V, while the modulation index is held at \(M\) = 0.95. Each phase leg's pole voltage output is depicted in Figure 5a. The maximum voltage at the poles is 200 V. Figure 5b-d show the line voltages \(V_{RY}\), \(V_{YB}\), \(V_{\text{BR}}\), line current (\(I_{R}\), \(I_{Y}\), \(I_{B}\)), and the capacitors' voltages \(V_{CR}\), \(V_{CY}\), and \(V_{CB}\) when the load isvaried. This dynamic load current change is indicative of relatively stable load voltages. When the load current rises, the voltage ripples of the capacitors also grow.Figure 5d illustratesthat the capacitor voltage for phase R is self-balanced with small voltage ripples when the load varies suddenly. As can be seen in Figure 5d, the voltage across the capacitors tends to stabilize at its nominal value, \(V_{CX}\) = 100 V. This equilibrium is maintained in the presence of varying loads. As can be seen in Figure 5e, the blocking voltages for \(S_{R1}\), \(S_{R2}\), and \(S_{R3}\) are all 100 V DC. The stress voltages applied to \(S_{R4}\) should also total 200 V. Each leg switch has a stress voltage or blocking voltage of 500 V.  
IRFP460 MOSFETs were utilizedas controlled switches on the PLECS SIMULINK platform, and the IRFP460 datasheet was brought in to quantify the power loss. This is seen in Figure 5f, which depicts the power loss distribution under full load.  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Specification** \\ \hline Supply voltage (\(V_{DC}\)) & 100 V \\ Supply frequency & 50 Hz \\ Carrier frequency & 2 kHz \\ Capacitors (\(C_{R}\) = \(C_{Y}\) = \(C_{B}\)) & 1100 \(\mu\)F \\ Load & \(R\) = 40 \(\Omega\), \(L\) = 30 mH \\ Switch & IRFP460 MOSFETs \\ Diodes & VS-20 ETFO2-M3 \\ Controller & dSPACE D51104 \\ Modulation index & 0.95 \\ \hline \hline \end{tabular}
\end{table}
Table 4: Simulation and experimental results: Useful parameters.  
\begin{table}
\begin{tabular}{c c c c c c c c c c c c} \hline \hline
**C** & **PN** & **R** & **UP** & \multicolumn{6}{c}{**Topology**} \\ \cline{6-13}  & & & **[7]** & [5] & [12] & [13] & [14] & [16] & [18] & **[P]** \\ \hline MOSFET \({}^{\star}\) & IRFP240 PBF & 100 V, 23 A & 2.2 & - & 6 & 6 & 6 & 6 & - & - & - \\ \hline  & IRFP350 PBF & 200 V, 20 A & 2.68 & 6 & 24 & 21 & 21 & 24 & 18 & 18 & 9 \\ \hline  & IRFP21N60 LPBF & 400 V, 16 A & 3.48 & 12 & - & - & - & - & 12 & 3 \\ \hline  & IRFP9140 NPBF & 600 V, 21 A & 8.16 & - & - & - & - & - & - & - \\ \hline  & & VS-20 ETF02-M3 & 200 V, 20 A & 3.68 & 3 & - & - & - & 6 & - & 3 \\ \hline Capacitor & 23M252F200 BH1H1 & 200 V, 2500 \(\mu\)F & 23.61 & 6 & 12 & 9 & 9 & 9 & 9 & - & 3 \\ \hline Gate Driver & IR2110 & - & 1.8 & 18 & 27 & 24 & 24 & 27 & 18 & 27 & 12 \\ \hline Total Cost (USD) & & & & 240.6 & 409.4 & 325.6 & 325.6 & 338.6 & 315.2 & 138.6 & 138.03 \\ \hline  & & & & & & & & & & & \\ \hline \hline \end{tabular} \({}^{\star}\) www.digikey.com, www.galco.com (accessed on 20 December 2022).  
\end{table}
Table 3: Cost analysis of the proposed topology compared with the existing topologies.