# Thermomechanical Stresses in Silicon Chips for
## 2 Materials and Methods  
### Materials and Sample Preparation  
The assembly structure of the developed samples consists of a substrate, above which an interconnection material is located, and a Si chip, which is placed above it, as represented in Figure 1.  
In this work, two types of substrate were adopted: a copper substrate, with dimensions (5 \(\times\) 5 \(\times\) 1) mm\({}^{3}\), and an Al\({}_{2}\)O\({}_{3}\) ceramic substrate, with dimensions (2.4 \(\times\) 2.4 \(\times\) 1) mm\({}^{3}\), covered with gold metallization, reported in Figure 2a,b.  
The copper substrates were mechanically treated first by rubbing the surfaces on abrasive discs with different grains, taking care not to avoid scratches; then they were placed in an ultrasonic bath of 4% hydrochloric acid, and finally in an ultrasonic bath with isopropanol. Ceramic substrates were used without any prior treatment.  
Silicon chips were adopted with dimensions 1500 \(\times\) 1500 \(\times\) 120 \(\upmu\)m\({}^{3}\), (001) oriented, and with gold metallization at the bottom. An interconnection material, for the soldering process, was used to build the devices: it consists of a thin layer of Au80 Sn20 eutectic alloy with a thickness of 25 \(\upmu\)m [21; 22]. The soldering procedure was carried out following two different working processes, depending on the application or not of an external pressure. All Si-chips were soldered to the substrate using a vacuum-assisted closed reflow oven (Unitemp, RSS-160). For efficient soldering, surface oxides and undesired residuals were removed using formic acid vapor, which has strong reducing effects. The assemblies were prepared at 320 \({}^{\circ}\)C, using a bonding time of 80 s (for the samples without additional pressure) and 30 s (for the samples with additional pressure). Several assemblies were prepared to confirm the reproducibility of the experimental results. Figure 3 shows the temperature profiles in the reflow oven. Before proceeding with the Raman measurements, the final assemblies were optically inspected by a 3D digital microscope (Keyence VHX-900F).  
For the samples prepared under pressure, the soldering process was carried out at 5 N, both in air and in N\({}_{2}\) atmosphere, according to the scheme reported in Figure 3b. Pressure was applied through a Fineplacer bonder (FineTech(r) AP2.4 145/FP 145 Pico ma), placing the chip and applying an established pressure perpendicular to the substrate surface by heating and controlling the environment of the system together. The value of 5 N was selected because it represents the maximum applicable pressure to avoid damaging the silicon chip during the assembly process.  
Figure 1: Schematic illustration of an assembled device showing three main components: Si chip on top, substrate on bottom, and interconnection material in between. The cartesian axis system reflects the geometric symmetry of the Si crystal.  
Figure 2: Images of (**a**) copper and (**b**) Al\({}_{2}\)O\({}_{3}\) ceramic substrates.  
The list of all the assembled and investigated samples is specified in Table 1. Four types of Si chip samples were prepared via a soldering process: samples mounted on Cu substrates, without any pressure (A_AuSn) or using a pressure of 5 N (A_AuSn_p), or on ceramic substrates, without any pressure (B_AuSn) or using a pressure of 5 N (B_AuSn_p). Together with the mounted samples, the starting silicon chip (Si_unmounted) was also analyzed, which has not been assembled to a device.