## 2 Proposed SoC-Balancing Strategy without Saturation
### Basic Principle of SoC-Balancing Strategy  
If boost converters function as the interfaces between distributed ESUs and loads, they are actually independent of the input side and parallel (or series) circuit connected on the output side. Owing to this feature, the individual SoC can be regulated by its own PCU. The corresponding configuration is outlined in Figure 2, where the ESUs are batteries. Inductor \(L_{k}\), power switch \(S_{k}\) and diode \(D_{k}\) constitute the PCU#\(k\), where \(k=1,2,\ldots,m\). Capacitor \(C\) and load \(R\) are shared by the PCUs on the output side. The input voltage of PCU#\(k\) is denoted as \(u_{ik}\). Moreover, \(u_{\text{dc}}\) and \(i_{0}\) are the dc-bus voltage and load current, respectively. As seen in Figure 3, dual-loop control is used to coordinate multiple units. A common outer loop is used for voltage regulation, while multiple inner loops are used for current control and SoC equalization. Here, \(i_{\text{rk}}\), \(i_{\text{k}}\), \(d_{\text{kr}}\) and \(CDR_{k}\) are reference current, feedback current, duty cycle, and the current distribution ratio of the PCU#\(k\), respectively. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{\begin{tabular}{c} **Balancing** \\ **Method** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Suitable** \\ **Application** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Style of SoC** \\ **Estimation** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Accuracy of** \\ **SoC** \\ **Estimation** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Number of** \\ **Voltage** \\ **Sensors** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Number of** \\ **Current** \\ **Sensors** \\ \end{tabular} } & \multirow{2}{*}{\
\begin{tabular}{c} **Total** \\ **Number of** \\ **Sensors** \\ \end{tabular} } & \multirow{2}{*}{
\begin{tabular}{c} **Sensor** \\ **Cost** \\ \end{tabular} } \\ \hline
[1] & parallel & calculation & High & \(m\) & \(2m\) & \(3m\) & High \\
[2] & parallel & approximation & Not high & \(2m\) & \(2m\) & High \\
[10] & parallel & approximation & Not high & \(m\) & \(m\) & \(2m\) & High \\
[15] & series & calculation & High & \(1\) & \(m+1\) & \(m+2\) & Not high \\
[17] & series & approximation & Not high & \(m\) & \(2m\) & \(3m\) & High \\
[22] & series & approximation & Not high & \(m+1\) & \(1\) & \(m+2\) & Not high \\ proposed & both & calculation & High & \(1\) & \(m\) & \(m+1\) & Low \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Comparisons with the existing balancing methods. Figure 2: Configuration of the distributed battery ESUs interfaced with boost converters: (**a**) Series application; (**b**) parallel application. The parallel form helps to enhance system capacity, while the series form enables applications at higher voltage levels. In terms of discharge, the proposed method is valid for both parallel and series applications. When the PCUs are paralleled on the output side, \(u_{\text{dc}}\) is constant, and thus the load current can be reasonably distributed by CDRs according to the individual SoC level. When the PCUs are connected in series, the load current is unchanged and shared by all units. Then, the individual output voltages can be flexibly regulated while \(u_{\text{dc}}\) is fixed. In fact, the individual voltage gains are modified little by little, and the phase currents thereupon vary towards a consistent SoC status. To fulfill this strategy, the CDRs are introduced, which are expressed as  
\[CDR_{k}=\frac{SoC_{k}^{n}}{\sum_{k=1}^{m}SoC_{k}^{n}},k=1,2,\cdot\cdot\cdot,m \tag{1}\]  
where \(n\) is an accelerating factor used to shorten the SoC-balancing duration. The output of the voltage regulator is the common input of all the current loops and acts as the reference of the sum current \(i_{\text{sum}}\).