# Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions
## 3 Device Characteristics  
In this part, we will evaluate the effect of implantation and fabrication parameters on the optimized performance of TFETs for high I\({}_{\text{on}}\) current and minimum average SS. The first set of devices (Set 1) were implanted with P\({}^{+}\) ions to a dose of 1 \(\times\) 10\({}^{15}\) cm\({}^{-2}\) at an energy of 3 keV and B\({}^{+}\) ions to a dose of 5 \(\times\) 10\({}^{14}\) cm\({}^{-2}\) at 1.5 keV both at 45\({}^{\circ}\) tilt. The reason for a lower B\({}^{+}\) dose is to suppress the n-branch of the ambipolar behavior. Samples were activated at two different temperatures of 500 \({}^{\circ}\)C and 600 \({}^{\circ}\)C for 20 s. Figure 3a depicts the measured transfer characteristics I\({}_{\text{d}}\)-V\({}_{\text{gs}}\) of the device for a p-TFET. As evident from the figure, the TFET activated at the higher temperature shows degraded SS and lower I\({}_{\text{on}}\) current compared to the device activated at 500 \({}^{\circ}\)C. This is due to the fact that the higher temperature annealing causes more extended diffusion of dopants, hence decreasing the steepness of the tunneling junction. Figure 3b shows the output I\({}_{\text{d}}\)-V\({}_{\text{ds}}\) characteristics for devices at V\({}_{\text{ov}}\) = \(-\)1 V, which is defined as V\({}_{\text{ov}}\) = V\({}_{\text{gs}}\) - V\({}_{\text{off}}\) = \(-\)1 V for an I\({}_{\text{off}}\) = 1 nA/um. The typical super-linear onset of drain current I\({}_{\text{d}}\) at small V\({}_{\text{ds}}\) is present in the I\({}_{\text{d}}\)-V\({}_{\text{ds}}\) curves. The super-linear onset stems from drain-induced barrier thinning (DIBT) [12], which can be mitigated by increasing the dopant concentration at the tunneling junction [13]. In other words, for both temperature cases the dopant concentration at the source is lower than the optimum value and needs to be further increased. To optimize the device performance, another set of TFETs (Set 2) were fabricated with different implantation and activation parameters. P ions with a dose 5 \(\times\) 10\({}^{15}\) cm\({}^{-2}\) and at an energy of 3 keV  
Figure 3: Measurement results of Set 1 devices. (**a**) I\({}_{\text{d}}\)-V\({}_{\text{g}}\) transfer characteristics for p-TFETs annealed at two different activation temperatures. (**b**) I\({}_{\text{d}}\)-V\({}_{\text{ds}}\) output characteristics for the corresponding devices, showing the super-linear onset of the I\({}_{\text{d}}\)-V\({}_{\text{ds}}\) curves. Figure 2: (**a**) Top view of a scanning electron microscope (SEM) image of a suspended silicon NW before gate fabrication process. (**b**) Side view of the final single NW TFET. It is clear that the gate metal completely wraps around the NW creating a gate-all-around (GAA) structure. The NW cross-section amounts to 35 nm \(\times\) 10 nm. and B ions with a dose of 1 \(\times\) 10\({}^{15}\) cm\({}^{-2}\) at 1.5 keV were implanted at a tilt of +/\(-\) 45\({}^{\circ}\), respectively. The implantation doses were increased to provide enough dopant concentration at the junctions after activation. The annealing was carried out at 550 \({}^{\circ}\)C for 10 s to drive out the dopants to the silicide/channel interface for dopant segregation. The annealing time and temperature were decreased in order to achieve sharper junctions. Figure 4a,b shows the measured transfer characteristics I\({}_{\text{d}}\)-V\({}_{\text{gs}}\) for the Set 2 devices of both p- and n-TFETs, respectively. A TFET works in both modes, p- and n-type, due to the presence of tunneling junctions at both the source and drain side, which causes undesired ambipolar switching, a typical behavior of a TFET.