# Prototype of 5G Integrated with TSN for Edge-Controlled Mobile Robotics
## 4 Discussion and Results
### Dejittering of the Transmission  
In Section 4, the scheduled traffic and traffic shaping for the integrated 5G and TSN communication pipeline has been shown, especially the shaping of the PC output and the shaping of the over-the-air transmission time. To validate the shaping of the output, measurements with cyclic data traffic and a fixed message size have been performed. A message size of 50 bytes and a cycle time of 2 ms have been tested with at least one hundred thousand samples. To determine the performance of the 5G-TSN bridge independent of the PC performance, the jitter has been measured at the output of the PC sending the data, the egress gate of TSN-Switch 1 and the egress gate of TSN-Switch 2. The performance of the URLLC testbed can be found in Section 3.2.1. Figure 11: Time synchronization error measurements of 5G integrated with TSN. The shaping of the PC output can be seen in Figure 12. On the left side, the jitter of the PC output is shown, and on the right side, the jitter at the egress gate of TSN-Switch 1 is shown. Since the PC is not a dedicated real-time system, the computation of the application and the cyclic sending of the data generates a certain output jitter that can go up to 50 us and with a 99.9% value at \(\approx\)21 us. Using the TSN-Switch 1 to reduce the jitter by holding the messages for a certain time and allowing the PC to send within a certain time window, the probability distribution of the messages is reduced to a 99.9% value of 125 ns, as shown on the right side of Figure 12. This is a significant reduction in the jitter caused by the PC, thereby enabling deterministic communication with narrow time arrival windows. Especially for fieldbus systems or scheduled traffic in industrial Ethernet networks, the time windows are short to enable fast communication. Our empirical results signify that without requiring expensive real-time hardware, factory cloud and edge systems could satisfy real-time application requirements with appropriate traffic shaping. In Figure 13, the measurement results of the integrated 5G and TSN communication pipeline without IEEE 802.1 Qbv are shown. On the left side, the output jitter of the PC is shown with a 99.9% value of \(\approx\)35 us, and on the right side, the jitter measured at TSN-Switch 2 is shown with a 99.9% value of \(\approx\)373 us. Considering the latency values of the 5G-URLLC-testbed presented in Section 3.2.1, it can be seen that the jitters of the PC and the URLLC-testbed are accumulated in the pipeline. The overall end-to-end jitter is increasing with each node in the communication chain. As a consequence, in a large-scale network without traffic shaping mechanisms to reduce the jitter, such as traffic scheduling according to IEEE 802.1 Qbv, significant jitter can accumulate over the network and make it possibly unsuitable for certain jitter-sensitive industrial usage. In Figure 14, the measurement results of the integrated 5G and TSN communication pipeline with IEEE 802.1 Qbv scheduled traffic are shown. Again, the PC is introducing a jitter with a 99.9% value of 16 us but the egress jitter of TSN-Switch 2 is reduced to a 99.9% value of \(\approx\)920 ns. With the reduction in jitter, it can be seen that not only the jitter introduced by the PC but also the jitter introduced by the 5G system is compensated by the traffic scheduling mechanism. Using IEEE 802.1 Qbv, the wireless 5G bridge can be integrated in the network in a way that the value of the transmission jitter is similar as in a wired connection; see Figure 12. By decoupling components introducing larger jitter with TSN switches, the jitter can be significantly reduced, making 5G suitable for jitter-sensitive deterministic communication for industrial usage. Compared to Figure 13 with the 99.9% value of the jitter being at 372 us, the 99.9% jitter over the integrated 5G and TSN network can be reduced by a factor of 400 to only 922 ns by applying IEEE 802.1 Qbv, as shown  
Figure 12: Left: Jitter of the PC output at the network card of the PC.