## 1 Introduction  
In-memory computing (IMC) is a promising paradigm that addresses the von Neumann bottleneck of conventional computing systems [1, 2, 3, 4]. By enabling computations directly within memory arrays, IMC avoids the need for energy/time-consuming data transfer between memory and processing units [5, 6]. While traditionally implemented with conventional CMOS-based technologies [7, 8], IMC architectures have also been extensively explored using non-volatile memory (NVM) technologies, such as resistive RAM (RRAM) [9, 10], magnetic RAM (MRAM) [11], and ferroelectric field-effect transistors (FeFETs) [12, 13, 14]. Within the realm of IMC, NVM-based logic-in-memory (LIM) has emerged as a reliable, low-power, and high-performance solution [15]. Among the various LIM schemes proposed in the literature [16, 17, 18], material implication (IMPLY) logic has been demonstrated to be a compelling choice due to the low additional complexity required to perform logical operations directly within memory arrays. In the IMPLY approach, memory devices are used simultaneously as computing and storage elements. When performing a logic operation, inputs are pre-encoded as resistance states of memory devices, and specific voltage pulses determine if the resistance of the output memory cell changes based on the input combination. However, IMPLY-based designs suffer from reliability issues, including the degradation of logic states and severe sensitivity to driving voltage variations [19]. To address these concerns, the smart IMPLY (SIMPLY) architecture was introduced, also demonstrating enhanced energy efficiency in executing logic operations [19; 20; 21; 22]. Although proposed for RRAM technology [19; 21; 23; 24], IMPLY and SIMPLY logic schemes have recently been evaluated for implementation with spin-transfer torque MRAMs (STT-MRAMs) [15]. Compared to RRAM, STT-MRAM offers several benefits for the SIMPLY logic scheme, including higher energy efficiency, better write endurance, and lower bit error rates [15]. However, the STT-MRAM-based SIMPLY scheme, typically based on single-barrier magnetic tunnel junction (SMTJ), suffers from long write access times, mainly due to the relatively high switching currents [25]. Double-barrier MTJ (DMTJ) offers a potential solution for faster and more energy-efficient switching [26]. However, DMTJ presents a lower resistance ratio, which results in a reduced read margin [26], especially critical for reliable SIMPLY operation. In this work, we propose Cryo-SIMPLY, a reliable STT-MRAM-based LIM scheme leveraging cryogenic electronics [27] and an in-memory computing paradigm [28]. More specifically, we used cryogenic operating temperatures (liquid nitrogen boiling point, 77 K) to address the limitations of DMTJ-based SIMPLY designs. Prior research [29; 30] has shown that STT-MRAMs at cryogenic temperatures are a good choice for reliable and energy-efficient computing. We leveraged this concept by applying a cryogenic operation to STT-MRAM-based SIMPLY logic. Cryo-SIMPLY aims to address the memory and power limitations of conventional von Neumann computing architectures while offering a compelling solution for future computing systems. SIMPLY designs were evaluated using our macrospin-based Verilog-A temperature-dependent compact models reported in [26] of 30 nm perpendicular STT-MTJs and a commercial cryogenic-aware 65 nm CMOS process. Through comprehensive circuit and application level simulations, we characterized and benchmarked the performance of both SMTJ and DMTJ SIMPLY designs. The key contributions of this work are as follows:  
* To our knowledge, this is the first study presenting a circuit-to-application level characterization and comparative analysis between SMTJ- and DMTJ-based SIMPLY schemes operating at 77 K.
* The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X.