## 5 Experimental Results  
A key element in assessing the effectiveness of a test-environment implementation is to evaluate that implementation in terms of the occupation of logic resources and the dynamic power consumption of the corresponding logic structures. The method of determining both the number of logic resources required and the dynamic power consumption boils down to synthesising appropriately described circuits in HDL languages (Verilog HDL) in selected synthesis tools. In this paper, both commercial tools (Vivado from AMD) and the academic ABC [46] were used for synthesis. In order to carry out the experiments, it is necessary to identify the circuits that will be mitigated. A popular set of benchmarks [48] was chosen, which contains both combinational and sequential circuits. The individual benchmarks contain a description of the function in Verilog, which was subjected to an initial minimisation targeting multioutput function. Before proceeding to the actual experiments, it is extremely important to determine the occupancy of the logical resources and to determine the dynamic power of a single voter. Various voter designs were considered (described in Section 2). After synthesis in the Vivado tool targeting seven-series FPGAs, as expected, each voter can be realised on a single LUT block regardless of the solutions presented in Section 2. Similarly, the dynamic power in each case was 0.086 W. Taking this into account, a classical voter design was used in further experiments in the mitigation circuits (Figure 3a). The first series of experiments was carried out in the ABC academic system. The synthesis was targeted at LUT blocks with four inputs. We decided to choose blocks with as few inputs as possible in order to highlight the differences between the different series of experiments as clearly as possible. The approaches without mitigation (Bench. column) and with mitigation (Bench.+vot. column) were compared. The results for the combinatorial systems are summarised in Table 1 and for the sequential systems in Table 2.  
In both tables, the first columns describe each benchmark: the name of the benchmark (Name), the number of inputs (IN), the number of outputs (OUT) and, in the case of sequential circuits, the number of internal FSM states (ST). For each series, the number of vertices of the logic network (nd) is specified. This number directly corresponds to the number of LUT blocks with four inputs. In addition, the switching activity value (\(SW\)), which is directly related to the dynamic power, was specified. The last row is the sum of the individual values, as shown as graphs in Figure 11.  
Looking at the graphs in Figure 11a,b, it can be seen that the results obtained are practically the same regardless of whether triple redundancy was implemented or not. The expected result is a situation where the number of blocks and the dynamic power will be about three times higher in the approach where there is TMR (Bench.+Vot.) than for the approach without TMR (Bench.). Such a relationship can be observed for sequential systems. For the number of blocks (Figure 11c), the growth of the logic structure due to the implementation of TMR is 2.73 times. In the case of power, on the other hand, it is 2.71 times. Looking at combinational circuits, it can be seen that the expected redundancy was removed in the optimisation process during the synthesis process. In this situation, the question of methods for describing mitigating systems remains open. In the case of sequential circuits, the relationship between the number of blocks in the cases is less than three, indicating that the synthesis process was carried out in such a way that there must