# All-Digital Computing-in-Memory Macro Supporting FP64-Based Fused Multiply-Add Operation
## 4 Simulation and Discussion  
The model of the proposed **DCIM-FF** macro was implemented using Verilog. Simulations with extensive testing data were performed to verify the functionality of the proposed design. DCIM-FF was tested by the testbench, which produces a large number of random FP64s as incentives, and the corresponding codes were tested by a hardware description language (HDL) compiled simulation tool, where we verify the functionality of DCIM-FF by observing the waveform of each signal over time. We have verified that the **DCIM-FF** macro can provide the correct rounded implementations for normalized/denormalized inputs in round-to-nearest-even mode and round-to-zero mode, respectively. In order to show the accuracy of the **DCIM-FF** operating FMA, several complicated FP64 numbers were adopted as inputs to verify the correctness of the results. The srand and rand functions of the C99 stdlib library and the time function of C99 time library were used to generate the random FP64. In order to make the number of random FP64s reach millions in magnitude, the malloc function of the C99 stdlib library was used to allocate a specified amount of memory space for a large number of random data in the heap area. The FMA function in the C99 math library was used as the standard reference during the verification process. In addition, the model of DCIM-FF was built using C language at software level, which runs faster than the HDL-based hardware model. The C model will also be taken as a comparative reference for the simulation results of DCIM-FF at hardware level. Two million sets of complicated FP64 input data were tested through the random-number  
Figure 5: The paradigm of the mantissa multiplication in **DCIM-FF**. testing device, and the results were consistent with the standard reference. As shown in Table 1, the 4 representative sets of tested results were extracted for display; we use hexadecimal numbers starting with 0x to represent 64b operands. At the set of normalized numbers, a is 0x405676f4 ede9 dbd4, which is approximately 89.8586993011 in decimal representation; b is 0x40340 aa015402a80, which is approximately 20.0415051729 in decimal representation; c is 0x407726f04 de09 bcl, which is approximately 370.4336680197 in decimal representation; and d is 0x40a0f6 acacac57 ff, which is approximately 2171.337254892 in decimal representation. At the set of denormalized numbers, a is 0 xac7e15859290f, which is approximately 1.4992522965 \(\times\) 10\({}^{-308}\) (scientific notation) in decimal representation; the value of the exponential part in FP64 is 0 for number a, which is quite close to zero; b is 0x3 fd9 fbf6f3f7 eefd, which is approximately 0.4941251869 in decimal representation; the value of the exponential part in FP64 is non-zero for number b; c is 0x4375c9a74d3d, which is approximately 1.1487166967 \(\times\) 10\({}^{-309}\) (scientific notation) in decimal representation; the value of the exponential part in FP64 is 0 for number c, which is quite close to zero; d is 0x6272 fbb808f07, which is approximately 8.5568999093 \(\times\) 10\({}^{-309}\) (scientific notation) in decimal representation; the value of the exponential part in FP64 is 0 for number d, which is quite close to zero. Equation (2) can be verified from decimal arithmetic. The guard bit, round bit, and sticky bit are used to determine whether to carry when removing some trailing bits from the binary number. The guard bit is the least significant of the valuable bits. The first two of the bits to be removed are the round bit and sticky bit, respectively. The remaining bits are the bits to be removed except for the round bit. In round-to-zero mode, the available bits are kept and the rest are thrown away, which has the effect of making the value represented closer to 0.0. Compared with round-up mode, round-to-nearest-even mode works differently when the calculated value is exactly half-way between the two possible final results.