## 5 Conclusions and Future Work  
In this paper, we demonstrated efficient operation using both hardware and software to execute a TinyML audio classification in an embedded system using limited resources. The experimental results showed that the time and energy consumption decreased when executing the functions in the embedded board. In the audio classification application that goes through a lot of preprocessing on raw data input from external, we proved that co-designing with hardware and software reduces execution overhead rather than processing all operations with software. Previously, the I\({}^{2}\)S module that received external audio raw data performed only the role of data collection. This paper designed a custom I\({}^{2}\)S unit that added a windowing module, which is one of the audio preprocessing operations, and was \begin{table}
\begin{tabular}{c c c c c} \hline \hline  & \multicolumn{2}{c}{**Conventional**} & \multicolumn{2}{c}{**Proposed**} \\ \cline{2-5}  & \(\Delta\)**SystemClk** & **Time (ms)** & \(\Delta\)**SystemClk** & **Time (ms)** \\ \hline Windowing & 452,808 & 2.717 & **416,412** & **2.498 (\(-\)8.06\%)** \\ FFT & 805,188 & 4.831 & 764,384 & 4.583 (\(-\)5.13\%) \\ Log Scale & 381,476 & 2.289 & 371,264 & 2.228 (\(-\)2.66\%) \\ Frontend & 3,345,885 & 20.075 & 3,251,249 & 19.507 (\(-\)2.83\%) \\ \hline Energy Consumption (mJ) & 2.541 & \multicolumn{2}{c}{**2.458 (\(-\)3.27\%)**} \\ \hline Cell Area (gate) & 55,350 & \multicolumn{2}{c}{**107,042 (93.39\%)**} \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Comparison of time, energy, and the logic area between the conventional and proposed structures. Figure 7: Synthesis result cell area comparison according to Hann window coefficient length and quantize precision degree. (**a**) Design Compiler synthesis result according to coefficient length and quantization degreeu (**b**) FPGA synthesis result with the smallest cell area (**c**) FPGA synthesis result with the largest cell area. able to reduce operation time and energy consumption in software. When designing the custom I\({}^{2}\)S module, coefficient length and quantization degree were used as parameters for the windowing module. According to the combination, it was possible to design the custom I\({}^{2}\)S module while minimizing the increase in the hardware area size. The proposed preprocessing technique using the hardware is suitable and can be applied in TinyML applications that require a lot of raw data preprocessing besides audio classification. In this paper, among the entire TinyML framework flow, software and hardware are partitioned based on the windowing operation. Optimized partitioning between hardware and software co-design may provide us with a new topic for future research. [PERSON] designed the entire core architecture and performed the numerical analysis; [PERSON] was the corresponding author. All authors have read and agreed to the published version of the manuscript. This study was supported by the BK21 FOUR project funded by the Ministry of Education, Korea (4199990113966, 10%), and the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (NRF2019R1A2C2005099, 10%), and Ministry of Education (NRF2018R1A6A1A03025109, 10%), and Institute of Information & communication Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (no. 2021-0-00944, Metamorphic approach of unstructured validation/verification for analyzing binary code, 70%), and the EDA tool was supported by the IC Design Education Center (IDEC), Korea. The authors declare no conflict of interest. The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, and in the decision to publish the results. The following abbreviations are used in this manuscript: