# Building Reliable Massive Capacity SSDs through a Flash Aware RAID-Like Protection +
## 2 Background and Related Work
### Reliability of Flash Memory  
Although SSDs are widely used in various fields, errors including hardware and firmware are still being reported including enterprise area [29; 30; 31; 32; 33]. The occurrence of such errors is mostly due to the characteristics of the flash memory introduced below.  
The flash memory has a limited number of allowed P/E times, depending on the process technology (e.g., SLC, MLC, TLC, or QLC). The increased density by storing multiple bits per cell provides larger storage capacity. However, it sacrifices reliability as the number of allowable P/E cycles is drastically reduced [28; 34]. The permitted P/E cycles for SLC is around 100,000, whereas the P/E cycles for MLC, TLC, and QLC are 35,000-10,000, 5000, and 1000, respectively [28; 35; 36]. The technique of storing multiple bits per cell not only reduces P/E cycles, but it also increases the bit errors [37]. The bit error rate (BER) of the flash memory increases in proportion to the cumulative P/E count. The bit error rate is a representative measure of the reliability of the flash memory due to these characteristics. [PERSON] et al. and [PERSON] et al. measure the bit error rates of flash chips of various manufacturer and reports relationship between bit error rate (BER) and P/E cycles [38; 39].  
Recently, V-NAND or 3D NAND has been introduced on the market by major manufacturers. The technology allows for stackings memory cells vertically in order to increase capacity without reducing cell size. Although the cell stack structure of 3D and planar (i.e., 2D) NAND are different, the bit error characteristics of two types of flash memories are similar [40; 41]. The BER of 3D NAND is generally lower than that of 2D NAND. Particularly, the relationship between the number of P/E cycles and increase of BER is the same for both [40; 42; 43; 44]. In this paper, we use BER as the reliability criterion for flash memory storage. Therefore, our proposal aiming to lower BER is universally applicable, regardless of the NAND flash memory type. For 2D and 3D NAND flash memories, the absolute values of BER of these two types of memory are different, but this does not affect the design of our proposed scheme.  
The Error Correction Code (ECC), which is stored in out of band (OOB) area in each page, is a basic method for detecting and correcting errors in flash memory [45; 46; 47; 48]. ECC has the capability to detect and correct a fixed number of bit errors, regardless of the error rate of flash memory since the ECC code size is fixed. Therefore, ECC cannot cope with bit errors exceeding the detectable range [45; 46; 48]. Studies for addressing the limitation of ECC have been proposed, but they require additional hardware and complex management overhead [49; 50].  
RAID-like protection architectures have been introduced in order to complement the limitation of the ECC [11; 12; 14; 51]. The RAID-like architectures significantly reduce BER of flash memory. However, it requires redundant data for the protection [9; 14; 28], and this overhead could be more prominent in a large capacity of SSD. Several studies present how the data protection of RAID affects BER reduction through numerical analysis models [9; 14; 51; 52; 53; 54]. In this paper, we also analyze the reliability of RAID configuration inside SSD through the same BER analysis model [14; 52; 53].  
In this work, we address this redundant overhead of RAID architecture while improving the reliability of flash memory for a massive capacity of SSD.