# Real-Time Optimization of RISC-V Processors Based on Branch Prediction and Division Data Dependency
## 3 Optimization of Real-Time Performance for RISC-V Processors
### Optimization of the Bran_Pre Module (Branch Prediction Module)  
#### 3.2.1 Introduction to Branch Jump Instructions  
In a three-stage pipeline processor, the execution stage is the third stage. When the execution stage resolves the correct target address of a branch, if the instructions in the first two stages of the pipeline are not the instructions at the target address, the pipeline needs to be flushed. Therefore, when the processor executes a conditional branch, a correct prediction of a single instruction saves two clock cycles compared to an incorrect prediction. We will use a specific set of instructions corresponding to a program segment to explain this. In Figure 2, the instruction at PC address \"32'h00000038\" is a jump instruction (32'hfc5e8e3), which specifies a jump to the instruction at PC address \"32'h00000028\". In Figure 3, the processor makes an incorrect prediction and does not perform the jump. It only determines the correct jump address and direction in the third stage, thus incurring an additional two clock cycles. This results in the processing of two incorrect instructions. In Figure 4, the branch predictor correctly anticipates the jump result and the target address, so the PC value directly jumps to 32'h00000028. Compared to the scenario in Figure 3 where the prediction was incorrect, this saves two clock cycles. We use compilation tools such as Eclipse to compile test programs like CoreMark. In the generated execution instructions, conditional branch instructions account for approximately 20% of the total instructions (detailed data are shown in Figure 5). If all conditional branch predictions are correct, it can save about 10% of the processor's execution time. Therefore, adding a branch prediction module can significantly improve the processor's execution speed. \begin{table}
\begin{tabular}{c c} \hline
**Module Name** & **Description** \\ \hline Clk & Provides the clock signal for the processor’s operation. \\ \hline PC\_IF & Calculates and retrieves the Program Counter value. \\ \hline ID & Decodes the instructions. \\ \hline EX & Performs data operations and instruction execution. \\ \hline Pi\_ctrl & Responsible for controlling the pause and resumption of the pipeline. \\ \hline DIV & Performs division operations. \\ \hline Jtag & Used for circuit testing and debugging. \\ \hline Bran\_Pre & Predicts the outcomes of conditional branch instructions. \\ \hline CLINT & Arbitrates interrupt signals. \\ \hline Regs & Stores general-purpose register data. \\ \hline Custom\_Bus & Connects the CPU to peripheral modules. \\ \hline Rom & Stores the instruction information corresponding to the software. \\ \hline Ram & Stores the data information corresponding to the software. \\ \hline Timer & Performs timing and generates timer interrupts. \\ \hline Gpio & Provides basic input/output functionality. \\ \hline Spi & Connects SPI interface devices. \\ \hline Uart & Executes serial data transmission and reception. \\ \hline \end{tabular}
\end{table} 
Table 1: Introduction to the various modules of Rev-riscv. 0: 10001197 auipc gp,0x10001
4: f5818193 addi gp,gp,-168
8: 10004117 auipc gp,0x10004  
c: ff810113 addi gp,sp,-8
10: 00005517 auipc a0,0x5
14: 57850513 addi a0,a0,a100
18: 10000597 auipc a1,0x10000
1c: fe858593 addi a1,a1,-24
20: 80818613 addi a2,gp,-2040
24: 00c5 rc63 bgu a1,a2,3c _start+0x3c>
28: 00052283 lw t0,(0a0)
2c: 0055a023 sw t0,0(a1) Conditional branch
30: 00450513 addi a0,a0,4 jump instruction
34: 0045593 adjdi a1,a1,4
38: fec5e63 bltu al,a2,28 < start+0x28>
3c: 00810513 addi a0,gp,-2040
40: 00010593 mv al,gp
44: 005763 bgu a0,a1,54 _start+0x54>
48: 00052023 sw zero,0(a0)
4c: 00450513 addi a0,a0,4  
Figure 4: The figure of pc_o values (instruction addresses) in the case of a correct prediction. Figure 5: The proportion of conditional branch instructions to unconditional branch instructions. Figure 3: The figure of pc_o values (instruction addresses) in the case of an incorrect prediction.