# A Low-Power ECG Processor ASIC Based on an Artificial Neural Network for Arrhythmia Detection
## 1 Introduction  
Arrythmia refers to an abnormal heart rhythm, which is a common heart disease that can lead to heart attacks, strokes, and even death [1]. Traditional methods for detecting arrhythmia include electrocardiogram (ECG) examinations and echocardiography. These methods have the following shortcomings: (1) Limitations of location: Due to the requirement of specialized equipment available only in hospitals, patients cannot perform rapid ECG monitoring at home or elsewhere; (2) Limited monitoring time: Traditional methods of examination usually only provide a limited time window, and sudden arrhythmia may not be captured, which requires long-term monitoring to detect; (3) Reliance on professionals: The detection methods in hospitals rely on the assistance and analysis of doctors. This requires professional experience and additional time for manual analysis. These limitations prevent patients from detecting arrhythmia in a timely manner, thus missing the best time for treatment. Early portable ECG monitoring devices wirelessly transmitted the raw ECG data for analysis. However, wireless transmission consumes high power, which limits the battery life of these devices [2]. In recent years, with the development of semiconductormanufacturing technology, ECG processors for wearable or implantable devices have been widely used [3]. Some proposed ECG processors, cardiac sensors, and ECG classifiers are assisted by artificial intelligence (AI) algorithms to perform on-chip classification and detect heart diseases, effectively reducing the data transmission time and saving valuable treatment time. The typical methods used for ECG classification in hardware include support vector machines (SVM), decision logic (DL), and neural networks (NN). A machine-learning-assisted cardiac sensor SoC is proposed in [4]; a switchable classification engine that can perform maximum likelihood classification (MLC) and SVM is applied to detect arrhythmia, achieving an accuracy of 95.8%. An SVM-based classifier is used as a strong classifier for arrhythmia detection in [5]. To improve energy efficiency, this design proposes a weak linear classifier, which first classifies heart beats based on simple features to reduce the activation rate of the SVM classifier. However, this SVM classifier can only achieve two-class classification, and the specific types of arrhythmia cannot be obtained. An adaptive derivative-based detection algorithm for potential arrhythmia recording is proposed to detect arrhythmia with the occasional abnormal heart beats [6], while it is also not applicable to the classification with multiple types. Neural network (NN)-based classifiers are widely adopted in ECG processors. In [7], the ECG recordings are digitalized by a level-crossing ADC, which is used to detect the position of R peaks, and the converted data are fed to a neural network for classification. However, this design requires up to 64 kB of memory capacity for storing parameters and weights. A Deep Neural Network (DNN)-based cardiac arrhythmia classifier is proposed in [8], which can detect five types of ECG rhythms with a classification accuracy of 91.6%. In [9], an arrhythmia classification processor using heartbeat difference encoding and an event-driven NN was presented, while the complex network architecture required a high hardware cost. An inference engine based on an extreme learning machine for robust ECG anomaly detection is presented in [10]; the intensive computation decreases the power efficiency, and the power of this design is 2940 mW. The authors in [11] proposed a biomedical AI processor with a reconfigurable NN engine that supports multifunctional bio-signal processing. An adaptive learning architecture is utilized to address inter-patient variations. However, the complex architecture leads to increased hardware costs and power consumption. A hardware architecture based on a Convolution Neural Network (CNN) for arrhythmia classification is proposed in [12], which increases the throughput at the cost of consuming more hardware overhead.