# A Unified PUF and Crypto Core Exploiting the Metastability in Latches
## 5 Results  
This section shows the implementation results in a Xilinx Artix-7 XC7A100 TCSG324-1 FPGA. The uniqueness, uniformity, and reliability are measured in three different FPGAs. The inter- and intra-chip Hamming distances (HMD) and Hamming weights are measured in nominal conditions. The occupied resources are compared with other PUF implementations in FPGAs, which are based on different physical phenomena.  
Figure 11: Structure of the column and diagonal rounds, along with the initial states of the PUF-ChaCha20 core.  
Figure 10: Implementation of the quarter round (QR) operation [31].  
The quality of the presented PUF implementation is estimated using \(uniformity\), _uniqueness_, and _reliability_[42; 43; 44]. The \(uniformity\) represents the average Hamming weight in the PUF response, as calculated by (3), where \(a\) is the total number of measured responses of the PUF and \(r_{i}\) is the number of ones in each response. The \(uniqueness\) denotes the PUF's capability to generate different responses between distinct devices measured using the average inter-die Hamming distance as shown in (4). There, \(b\) is the number of chips measured, and \(R_{(i,j)}\) denotes the n-bit response with a particular challenge, which is the same for each chip of the two that are compared. \(Reliability\) indicates the ability of the PUF implementation to reproduce the same response for a particular challenge under different conditions and is measured by the intra-die Hamming distance (5). Here, \(c\) is the total number of measurements with the same challenge applied to a particular PUF. Additionally, \(R_{f}\) and \(R_{i}\) are the n-bit reference iteration responses for the same challenge, respectively. Table 1 compares the quality of the PUF responses of our implementation and the quality of the PUF responses of other implementations based on different physical phenomena. The ideal values for \(uniformity\), \(uniqueness\), and \(reliability\) are 50%, 50%, and 100%, respectively. The \(uniformity\), \(uniqueness\), and \(reliability\) values in Equations (3)-(5) are presented as normalized values.  
Figure 12 illustrates the intra- and inter-chip Hamming distances in our PUF implementation. The intra- and inter-chip Hamming distances are measured in three different FPGAs using 1000 different challenges. The challenges used in the test are randomly selected and are not repeated. The PUF exhibits an average intra-chip Hamming distance of 0.75% with a 0.2% standard variation. Additionally, the implementation exhibits an average intra-chip Hamming distance of 49.85% with a 2.2% standard variation.  
\[Uniformity=\frac{1}{a}\sum_{i=1}^{a}r_{i} \tag{3}\]  
\[Uniqueness=\frac{2}{b(b-1)}\sum_{i=1}^{b-1}\sum_{j=i+1}^{b}\frac{HMD(R_{i},R_{ j})}{n} \tag{4}\]  
\[Reliability=\frac{1}{c}\sum_{i=1}^{c}\frac{HMD(R_{i},R_{f})}{n} \tag{5}\]  
Table 2 shows the resources occupied in the PUF-ChaCha20 implementation in an FPGA. The implementation presents a 3.1% resource overhead caused by the unified functions compared to [31]. On the other hand, the performance is compared with other ChaCha20 implementations, denoting a 0.8% performance reduction in comparison to [31] caused by the cycle necessary to configure the mode of the PUF implementation. The implementation exhibits 0.343 cycles/byte in the crypto core mode.  
\begin{table}
\begin{tabular}{c c c c} \hline  & **This Work** & [36] & [45] \\ \hline
**Uniformity [\%]** & 49.15 & 49.61 & 47.20 \\ \hline
**Uniqueness [\%]** & 49.85 & 49.95 & 39.10 \\ \hline
**Reliability [\%]** & 99.25 & 99.13 & 98.89 \\ \hline
**Topology** & Unbalanced Latches & RO with Hybrid Logic & Galois RO \\ \hline \end{tabular}
\end{table}
Table 1: Summary and comparison of the PUF quality.