# High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing
## 3 Method
### Buffer Architecture in D-SWIM  
#### 3.2.1 BRAM Organization of Line Buffer  
Similarly to SWIM, the D-SWIM buffer is composed of BRAM that saves the FPGA hardware resource and avoids the complex routing requirement. This section describes the BRAM-centric technique for the D-SWIM buffer construction.  
**BRAM Configuration:** D-SWIM directly employs the BRAM primitive for the buffer. The port width of BRAM can be configured. To accommodate the parallel pixels access of the input block and fully utilize the BRAM bandwidth, we configured all the BRAMs to a port width of 64 bits in the simple  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Design Parameters** & **Description** & **Use Scope** \\ \hline \(N_{blk}\) & Number of pixels in one stream block & HW \& SW \\ \(N_{line}\) & Number of pixels in the image line (image width) & SW \\ \(N_{height}\) & Image height & SW \\ \(N_{line-max}\) & Largest possible value of \(N_{line}\) & HW \\ \(H\) & Height in the vertical axis of the 2D stencil pattern & HW \\ \hline \hline \end{tabular}
\end{table}
Table 1: Design parameters in D-SWIM framework.  
Figure 4: Overview of D-SWIM framework.  
dual-port (SDP) mode. Note that the real maximum port width is 72 bits, whereas only 64 bits are under the control of the byte-wise write-enabling signal. The conventional usage of BRAM considers all bits in one address as an element in memory access. As Figure 5a shows, the store of the input block should align to the BRAM boundary--otherwise, the misaligned store will overwrite the other bits in the same address. To avoid interference between two consecutive blocks which is misaligned with the BRAM, we used the BRAM primitive instantiation within Xilinx Vivado that provides a _byte-wise write-enable signal_[13]. For instance, in Figure 5b, the input block (8 pixels, 8 bits/pixel) is misaligned to the BRAM boundary because the 4 pixels in the head of BRAM0 are stored along with the previous block. With the byte-wise write enable, the specific control bits in BRAM0 and BRAM1 are set to indicate the store positions of the incoming 8 pixels and the 4 remainder pixels ahead will not be overwritten. In summary, with the BRAM primitive instantiation, the controlling of the pixel-block store becomes more fine-grained. Furthermore, the write enable signal can be changed in the FPGA run-time such that the LB accommodates arbitrary writing offset introduced by the remainder pixels.  
**Number of BRAM in LB:** The number of BRAM invoked by one LB (denoted as \(N_{bram}\)) is determined by the system parameters in Table 1. D-SWIM targets minimizing the BRAM consumption under the constraints in Equation (1). Firstly, the capacity of the LB should be larger than \(N_{line-max}\). Secondly, the overall port width of the LB should be large enough to tackle the pixel block and ensure that only one address in each BRAM will be accessed in one cycle, such as the minimum \(N_{bram}\) is 2 in the Figure 5b case. Otherwise, two addresses of BRAM0 will be accessed in the same cycle that violates the port limitation of BRAM in the SDP mode.  
\[\begin{split}\text{minimize}& N_{bram}\\ \text{subject to}& N_{bram}\times D_{bram}\times W_{bram} \geq N_{line-max}\times 8(bits/pix)\\ & N_{bram}\times W_{bram}\geq(N_{remain-max}\%(W_{bram}/8)+N_{blk}) \times 8\\ & N_{bram}\in\mathbb{Z}_{>0}.\end{split} \tag{1}\]  
In Equation (1), \(D_{bram}\) and \(W_{bram}\) is the depth and width of a BRAM that is equal to 512 and 64, respectively, in Xilinx FPGA. \(N_{remain-max}\) is the largest possible number of the remainder pixel which is equal to \(N_{blk}-1\). % is the modulo operation. Therefore, we obtained the value of \(N_{bram}\) as Equation (2).  
\[N_{bram}=\max(N_{line-max}/4096,\lceil((N_{blk}-1)\%8+N_{blk})/8\rceil) \tag{2}\]