## 4 Results and Discussion
For the power MOSFET used in the high frequency field, the switching losses is the most important part of the total power loss. The time period associated with the increase of the drain current and decrease of the drain voltage is determined by the charging of the device capacitances. The Figure 8a shows the input capacitances (\(C_{\text{iss}}\)) and reverse transfer capacitances (\(C_{\text{rs}}\)) of both structures when \(V_{\text{GS}}\) = 0 V and \(f\) = 1 MHz. The \(C_{\text{rs}}\)s of the HDSGRSO UMOSFET has a slight increase in comparison with the ordinary structure because of the highly doped epitaxial layer. However, the capacitances difference between the two structures is gradually reduced as the drain voltage increases. When the drain voltage exceeds 120 V, the \(C_{\text{rs}}\)s of the two structures are almost same. The \(C_{\text{rs}}\)s of HDSGRSO and SGRSO UMOSFETs is 2 pF and 0.8 pF, respectively, at V\({}_{\text{DS}}\) = 140 V. On the other hand, the doping concentration of the p-body is slightly reduced under the same boron dose due to the highly doped  
Figure 6: BV and FOM (BV\({}^{2}\)/\(R_{\text{SP}}\)) at different (**a**) doping concentration of n-drift region; (**b**) \(L_{2}\) (height of high doped epitaxial layer); (**c**) \(L_{3}\) and (**d**) doping concentration of high doped epitaxial layer for HDSGRSO UMOSFET. Figure 7: BV and FOM (BV\({}^{2}\)/\(R_{\text{SP}}\)) of HDSGRSO UMOSFET at different n-drift region thickness. epitaxial layer, which causes a slight reduction of the \(C_{iss}\) for HDSGRSO UNOSFET. It can be seen that the HDSGRSO UMOSFET has lower \(C_{iss}\) contrast to the SGRSO UNOSFET when the drain voltage increases from 0 to 140 V. The \(C_{iss}\) of HDSGRSO and SGRSO UMOSFETs is 1400 pF and 1490 pF, respectively, at \(V_{\text{DS}}=140\) V, which is of benefit to improve the switching speed of the HDSGRSO UMOSFET. The FOMs of \(R_{\text{SP}}\times Q_{\text{gd}}\) have been adopted to compare the dynamic characteristics of two structures. The FOM (\(R_{\text{SP}}\times Q_{\text{gd}}\)) of HDSGRSO and SGRSO UMOSFETs is 180 and 250 m\(\Omega\)-nC, as shown in the Figure 8b. The FOM of devices with high doped epitaxial layer structure was reduced by 27.9% in contrast to SGRSO UMOSFET because the introduction of the high doped epitaxial layer increases the doping concentration in the drift region, which makes the \(R_{\text{SP}}\) decrease greatly. Table 2 shows the switching time and switching energy loss of two structures at 120 V, 4 A. The HDSGRSO UMOSFET has a lower turn-on delay time (\(t_{d(out)}\)) because of the smaller input capacitance, however, the rise time(\(t_{r}\)) of the HDSGRS UMOSFET is slightly higher due to the larger \(C_{rss}\), which causes results in the turn-on loss (\(E_{\text{on}}\)) to be very close. On the other hand, the layer \(C_{rss}\) causes a certain increase of the turn-off delay (\(t_{d(off)}\)) time and fall time (\(t_{f}\)), which leads to an increase of turn-off loss (\(E_{off}\)) in contrast to the SGRSO UMOSFET, and this needs more research in the future. The performance of the HDSGRSO UMOSFET has been compared with the one-dimensional silicon limit and other works in Figure 9. The HDSGRSO UMOSFET has the lowest \(R_{\text{SP}}\) and the highest BV compared with the previous power UMOSFETs. Figure 8: The \(C_{rss}\) and \(C_{iss}\) (BV\({}^{2}\)/\(R_{\text{SP}}\)) at different drain voltage (**a**) and (**b**) comparison of gate charge and \(R_{\text{SP}}\times Q_{\text{gd}}\) for HDSGRSO and SGRSO UMOSFETs. Figure 9: Performance comparing of one-dimensional silicon limit, two-dimensional charge-coupling limits for the pitches of 2 and 8 \(\upmu\)m. Some references are [10; 24; 25] and this work.