## 2 Proposed BPSK Demodulator and Clock Recovery Circuit  
Figures 2 and 3 depict the block diagram of the designed demodulator as well as its essential theoretical waveforms, respectively. It should be noted that placing an automatic gain control as the first stage of the receiver is needed in applications where orientation and matching between the transmitting and receiving blocks are lost [17]. However, please note that as with fixed-in position implantable biomedical applications [1] where the link properties such as distance between receiver and transmitter, orientation, and alignment are easily available, it is not needed to use automatic gain control in the receiver. In these cases, the minimum required level of received signal for correct operation of the circuit is provided by the power amplifier in the external part according to the link properties. Moreover, in these cases, as the received BPSK signal level is high enough, power can also easily deliver wirelessly to the implant through the energy contained in the incoming BPSK data signal [18; 19]. In this architecture, the rectified BPSK signal is digitized by logic inverters, to be used as an auxiliary clock with twice the BPSK frequency, and is called \"2 XClock\". The digitized BPSK signal is then fed to the half-cycle delay block, containing a D flip-flop [20] which operates with 2 XClock signal. For extracting data, a low-power data detector proposed in this work will retrieve original data from the digitized BPSK signal and a delayed digitized BPSK signal whose operation is described later  
Figure 1: Simplified general block diagram of an Implantable Biomedical Microsystem (IBM). in this section. In addition, through comparing the digitized BPSK and data recovered signals, only by a low-power XOR logic gate [21], clock recovery will take place. It can be understood from Figure 3 that to retrieve the original data from the digitized BPSK and delayed digitized BPSK signals, a circuit is needed so that when \"0, 0\" (\"digitized BPSK, delayed digitized BPSK,\" respectively) state is received, the output signal changes its value to \"0\" and remains unchanged while inputs are constant, and when \"1, 1\" state is received, the output signal changes its value to \"1\" and remains unchanged while inputs are not changed to \"0, 0\". It is important that in two another states (\"0, 1\" and \"1, 0\"), the output must not change and should retain its previous  
Figure 3: Key waveforms of the proposed demodulator. Figure 2: Block diagram of the presented binary phase-shift keying (BPSK) demodulator. value. As it is shown in Figure 3, some logical states between the digitized BPSK signal and delayed digitized BPSK signal never happen, for example, \"0, 0\" and \"1, 1\" after each other or \"0, 1\" after \"0, 0\" state. All situations that are possible to happen are illustrated in Figure 4.  
According to above mentioned hints, a simple low-power circuit for retrieving data from existing signals is proposed (Figure 5). For understanding the operation of the proposed data detector, suppose that both digitized BPSK and delayed digitized BPSK signals are in low logic level. In this case, M\({}_{1,8,9}\) transistors are ON and M\({}_{3,4,6}\) devices are OFF. Therefore \"B\" node will be shortened to ground and accordingly, \"A\" node is connected to Vdd via M\({}_{1,2}\) transistors. Likewise, M\({}_{10}\) will be ON and M\({}_{5}\) will be OFF. In this state, the output level is low, and it will remain unchanged. According to Figure 4, after \"0, 0\" state, only \"1, 0\" state can happen. In this case, again, M\({}_{1,2,10}\) Mosfets are ON and the output voltage retains its previous value. Now, when \"1, 1\" signals are received at data detector inputs, opposite the \"0, 0\" state, M\({}_{3,4}\) transistors are ON and \"A\" node will be shortened to ground, and then M\({}_{7}\) will be ON and given that the M\({}_{6}\) was ON, \"B\" node will be connected to Vdd. Consequently, M\({}_{5}\) will be ON and makes \"A\" node unchanged at the low level.