# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 1 Introduction  
Currently, humanity is literally immersed in a sea of various VLSI-based digital systems. As can be seen, for example, from the rapid development of the Internet of things, robotics, and mobile technologies, this sea will deepen and expand. Obviously, the number of digital systems around us will only increase. On the other hand, the modern world is characterized by the need for a reasonable use of electrical energy. This characteristic feature is also evident in the field of information technologies, which has led to the concept of \"green computing\" [1].  
So modern digital systems should be power-efficient. They should consume as little power as possible [2]. It means that power consumption has become a primary concern in the design of integrated circuits [3]. Two main issues are connected with this demand. Thefirst of them can be formulated as follows: the less the power consumption, the longer the life of various mobile and autonomous devices. The second issue is connected with the increase in heat dissipation.  
The vast majority of digital systems consist of both combinational and sequential blocks [4; 5]. In this paper, we consider the problem of reducing power consumption by sequential blocks of digital systems. The behavior of a sequential block can be represented using a finite state machine (FSM) model [6; 7]. These models are widely used for representing, for example, such sequential blocks as (1) the control units of computers and microcontrollers [8; 9; 10; 11; 12; 13]; (2) the hardware-software interfaces and communication protocols of embedded systems [14; 15]; (3) various cryptoprocessors [16]; (4) hypertangent and exponential functions [17]; (5) various integral stochastic computing blocks [18]; (6) the activation functions of deep neural networks [19; 20]; (7) different stages of cascaded digital processing systems [21; 22].  
To optimize the power consumption of FSM circuits, it is necessary to take into account the main technological specifics and other main features of logic elements implementing FSM circuits [8; 9]. Since the late eighties of the last century, field programmable gate arrays (FPGAs) [23; 24; 25] have been used more and more to implement electrical circuits of various systems [26; 27]. In this survey, we mostly analyze various approaches used for improving the power consumption of FPGA-based FSM circuits.  
Currently, the vast majority of VLSI chips (including FPGAs) are manufactured using the complementary metal-oxide-semiconductor (CMOS) technology [1; 28]. In this regard, we are considering methods of reducing the energy consumption aimed at this technology.  
The main purpose of the article is a non-analytical review of possible solutions to the problem of reducing power consumption in FSM circuits. The review also shows the results of studies on the effectiveness of these methods. The review considers methods that have appeared in the last 40 years. We did not perform a comparative analysis of these methods and did not conduct additional studies of their efficiency (hence, the review is non-analytical). All research results are owned by the authors of articles and monographs listed in the Section \"References\".  
The rest of the paper is organized as follows: Section 2 briefly shows the theoretical background of FPGA-based FSM synthesis. Section 3 contains the analysis of power dissipation sources in CMOS integrated circuits and gives a classification method for reducing power consumption. Section 4 presents methods for saving power consumption based on clock gating and a decomposition of the initial FSM. Section 5 includes methods for saving power consumption based on various outcomes of state assignment. The methods based on replacing LUTs by EMBs are discussed in Section 6. A brief conclusion ends the paper.