## 5 Experimental Results and Discussion
### Error Sequence Measurement Results  
Conventionally, a communication system's bit error rate (BER) performance is used to evaluate its effectiveness. However, the bit error rate (BER) does not provide details about the distribution of channel errors; it does provide important first-order statistical data that are helpful in evaluating channels. In contrast, the bit error pattern provides insights regarding the statistical distribution of errors across a communication channel [36]. The bit error sequence is a sequence of 1's and 0's, with 1's indicating where errors have occurred and 0's indicating error-free bits. This sequence is created when the received sequence is compared to the transmitted sequence and is distinct from the string of 1's and 0's initially transmitted. Next, the M-QAM-based SD-PLC impulse noise error is modeled by applying the three-state FMMs that have been adopted and the BWA to the error sequences that the M-QAM-based SD-PLC has generated. When the error sequence is plotted against the bit number, the statistical distribution of bit errors across the channel can be observed. The scientific community often uses the term \"error sequence pattern\" to describe this representation. In this experimental investigation, an error sequence consisting of 50,000 bits was obtained by comparing the bits transmitted with those received using the M-QAM-based SD-PLC transceiver system developed in this study. For the weakly interrupted noise scenario, Figures 8 and 9 depict the error bit positions of device 1 (laptop charger in a 16-QAM SD-PLC system) and device 2 (computer monitor in a 16-QAM SD-PLC system), respectively. For the case of strongly interrupted noise, \begin{table}
\begin{tabular}{c c} \hline \hline
**Items** & **Values and Configurations** \\ \hline USRP hardware (TX and RX) & USRP N210 \\ TX daughterboard model & LFTX, (0–30 MHz) \\ RX daughterboard model & LFRX, (0–50 MHz) \\ TX computer/USRP TX IP & 192.168.20.1 and 192.168.20.2 \\ RX computer/USRP RX IP & 192.168.40.1 and 192.168.40.2 \\ Constellation order & 4, 8, 16 QAM \\ Transmitter and receiver gain & Non-tunable (default) \\ USRP FPGA and firmware rev & 003.005.003 \\ CENELEC C frequency & 130 kHz \\ Sample time & 6 \(\mu\)s \\ Sample frequency & 200 kHz \\ TX and RX bit length & 50,000 \\ Host PC TX and RX OS & Windows 10 Pro, 64 bits. \\ Host PC TX and RX Processor & Intel Core i5-4300u. \\ Host-based software version & MATLAB R2017a (9.2.0.538062) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Hardware, software, and transmission parameters. Figures 10 and 11 depict the error bit positions of a laptop charger and a computer monitor together in a 16-QAM SD-PLC system, and a CFL-bulb and a hairdryer in a 16-QAM SD-PLC system, respectively. The study found that impulse noise power affects burst error rates in data transmission. Weakly interrupted noise causes fewer noticeable burst errors, while strongly interrupted noise causes more noticeable ones. Burst errors occur when consecutive bits are corrupted, which can cause synchronization loss and jeopardize data integrity. High-power impulse noise can spread burst errors widely, even across data packets. The investigation also revealed that prolonged burst errors in SD-PLC 16-QAM were significant in both cases and scenarios. Higher-order QAM exhibits a comparatively higher error rate than lower-order QAM and is characterized by reduced efficiency despite its capacity to transmit more data. Using higher-order QAM and experimenting with strongly interrupted noise showed a noticeable rise in the error rate when the impulse noise power was increased. The accurate retrieval of transmitted data was made more difficult due to the heightened impact of the impulse noise, ultimately leading to burst errors in the received data. Using the developed M-QAM SD-PLC test bed, error sequences of length 50,000 were generated with varying error probabilities and recorded under a variety of experimental measurement conditions.