## 3 Proposed Architecture for Muti-Level 2-D DWT
### Proposed Multi-Level DWT Architecture  
For the first-level 2-D DWT, in which the clock-to-data ratio is 1:1, since the clock match the input data, we adopt an internal unfolded structure. Namely, four basic operation structures mentioned in the previous presentation, are connected in turn to constitute the 1-D 9/7 DWT structure, as demonstrated in Figure 4. In it, the term \(x(2n+1)\) with \({}^{*}\) is the item which is fetched ahead and \(D_{x}\) means the data obtained at the _Xth_ clock cycle. And this architecture can be implemented in the column and row filter by correctly selecting the RAM or Buffer. Moreover, the 2-D DWT consists of column filter, transposing buffer, row filter and scaling module. Meanwhile, if multiple 2-D DWT modules are carried out in parallel, the intermediate variables, \(y(2n+1)\), \(y(2n)\) and \(H(2n+1)\), will be transferred to the next column filter in parallel without being stored in RAM. So the intermediate variables fetched from RAM previously will be obtained directly from the preceding column filter. Given the above, the structure of a single-level 2-D DWT with parallelism S is presented in Figure 5. And the 2-D DWT structure is shown in the dotted box of Figure 5.  
For the second-level 2-D DWT, since a set of data is valid every two clock cycles, the 1-D 9/7 DWT structure can be partially folded. That is, for the four basic calculations of a set of data, two basic operation modules are needed. As in the 1-D DWT module shown in Figure 6, after \(x(2n)\), \(x(2n+1)^{*}\) and \(x(2n+2)\) enter the first basic module, \(y(2n+1)\) will be obtained at the second clock cycle through (1). Meanwhile, the intermediate variable \(y(2n+1)\) will be re-entered into the first basic module as input. Then, \(y(2n)\) can be figured out through (2) at the third clock cycle. Similarly, the Formulas (3) and (4) also use this method to reuse the basic operation module. This ensures that the processing of data in each clock cycle is effective against adopting multi-clock. Furthermore, this architecture can be applied for the column and row filter by properly selecting the RAM or Buffer. It should be noticed that the Buffer in the second level has four buffers. Moreover, transposing module is needed to adjust the order for the output data onto the column filter. Figure 4: The 1-D discrete wavelet transform (DWT) structure for the first level. Note: The items with \({}^{*}\) are the multiplication terms that should arrive ahead of time. Figure 5: Architecture of a single-level 2-D DWT with parallelism S.  
For the third-level 2-D DWT, since a set of data is valid every four clock cycles, the 1-D DWT module can be fully folded. Namely, for the four basic operations of a set of data, only one basic operation module is used, as shown in Figure 7. After a set of valid data entering the module, the L and H coefficients can be obtained from the reused basic operation module within four clock cycles. And once the four basic operations completed, the next set of valid data exactly arrives and the same processing will be done. Moreover, by accurately selecting the RAM or Buffer, the 1-D module can be applied in the column and row filter. Similarly, the Buffer here has eight buffers. Meanwhile, the transposing module is also demanded. As mentioned above, in order to achieve the right clock-to-data ratio and meet the order for the data flow required by the row filter, the transposing buffer is needed in each 2-D DWT. Hence, it is necessary to design suitable transposing modules for the DWT architectures of different clock-to-data ratios, as shown in Figure 8, where the blanks represent the invalid data. Once the output data onto the column filter successively enter the transposing buffer, they will be temporally stored by different numbers of registers, and selected by the multiplexers according to the sequence demanded by the row filter. Besides, only one scaling module is used to finish the scaling computation in each level of the 3-level DWT architecture.