## 5 Achieved Results and Performance Comparison
### Performance Comparison
#### 5.3.1 Virtex-4 Platform Comparison  
Our solution, when compared to [20], obtained 6.49 times higher throughput/area efficiency while still having a slice reduction of 85.4 percent. However, it might run a little bit more slowly, with 1.05 times higher latency than [20]. Similar to this, when compared  
\begin{table}
\begin{tabular}{l l l l l l} \hline \hline
**References \#** & **Platform** & \
\begin{tabular}{l} **Frequency** \\ **(in MHz)** \\ \end{tabular} & **Slices** & **LUTS** &
\begin{tabular}{l} **Time** \\ **(in μs)** \\ \end{tabular} & **T/Slices** \\ \hline
**Virtex-4 Results** & & & & & \\ \hline GBEC: \(d=59\)[20] & Virtex-4 & 127.261 & 17,158 & 2663 & 25.5 & 2.28 \\ BEC[14] & Virtex-4 & 48 & 21,816 & 35,003 & - & - \\ BEC halving[14] & Virtex-4 & 48 & 22,373 & 42,596 & - & \\ GBEC: \(d=59\)\(-\)\(3M\)[19] & Virtex-4 & 255.570 & 29,255 & - & 14.83 & 2.38 \\ GBEC: \(d=59\)\(-\)\(1M\)[19] & Virtex-4 & 257.535 & 12,403 & - & 32.81 & 2.45 \\ GBEC: \(d=59\)[21] & Virtex-4 & 195.508 & 3302 & 2723 & 32.1 & 9.43 \\ BEC: \(d=59\)[25] & Virtex-4 & 277.681 & 31,702 & - & 13.39 & 2.35 \\ \hline
**Virtex 5 Results** & & & & & \\ \hline GBEC: \(3M\)\(d1=d2=59\)[18] & Virtex-5 & - & 4581 & - & 51.46 & 4.24 \\ BEC: \(d_{1}=d_{2}=1\)[19] & Virtex-5 & 205.1 & 1397 & 4340 & 4560 & 0.1569 \\ GBEC: \(d=59\)[21] & Virtex-5 & 245.669 & 2714 & 2502 & 25.59 & 14.39 \\ GBEC: \(d=59\)\(-\)\(3M\)[26] & Virtex-5 & 337.603 & 9233 & - & 11.22 & 9.67 \\ GBEC: \(d=59\)\(-\)\(1M\)[26] & Virtex-5 & 333.603 & 4019 & - & 25.03 & 9.94 \\ \hline
**Virtex 6 Results** & & & & & \\ \hline GBEC: \(d=59\)[20] & Virtex-6 & 186.506 & 2664 & 22,256 & 17.39 & 21.5 \\ BEC: \(d1=d2=1\)[19] & Virtex-6 & 107 & 1245 & 3878 & 6720 & 0.119 \\ GBEC: \(d=59\)[21] & Virtex-6 & 290.92 & 1770 & 3597 & 21.61 & 26.14 \\ \hline
**Virtex 7 Results** & & & & & \\ \hline GBEC: \(d=26\)[20] & Virtex-7 & 179.81 & 2662 & 24,533 & 18.04 & 20.82 \\ GBEC: \(d=59\)[21] & Virtex-7 & 320.584 & 1771 & 4470 & 19.61 & 28.79 \\ \hline
**Our Work** & & & & & \\ \hline
**GBEC: \(d=26\)** & Virtex-4 & 112 & 2502 & 2133 & 26.97 & 14.819 \\
**GBEC: \(d=26\)** & Virtex-5 & 163.119 & 2114 & 2308 & 18.52 & 25.5 \\
**GBEC: \(d=26\)** & Virtex-6 & 198.223 & 1897 & 2797 & 15.24 & 34.58 \\
**GBEC: \(d=26\)** & Virtex-7 & 212.244 & 1895 & 2970 & 14.233 & 37.07 \\ \hline \hline \end{tabular}
\end{table}
Table 4: State of the art Comparison.  
to the study published in [14], our design shows 88.5 percent performance improvement despite operating at a noticeably accelerated operational clock frequency, completing tasks 2.48 times faster. Even when compared to [14], where a halving technique within BEC is investigated, this improved performance holds true. Additionally, our architecture utilizes 91.44 percent less hardware resources and achieves a higher throughput/area ratio (6.23) compared to [19]. However, it operates 1.81 times slower. It is crucial to remember that this analysis only applies to the first solution offered in [19]. Our architecture uses 79.8% less hardware, operating 1.21 times faster, and achieves 6.04 times higher throughput/area efficiency, setting new benchmarks for computational power. Our architecture, which employs cutting-edge control flow techniques, performs 1.19 times quicker, achieves a stunning 1.57 times higher throughput/area efficiency, and uses 24.2 percent fewer hardware resources than [21]. Finally, our architecture effectively manages resources and control flow compared to [25]. Despite having a latency that is 2.01 times greater than [25], it shines due to its remarkable 6.35 times higher throughput/area efficiency. These noteworthy accomplishments demonstrate the creative thinking behind our architectural solution, guaranteeing clarity while emphasizing its revolutionary effects on the field.