## 3 Enhanced SoC-Balancing Strategy with Saturation
### Selection of the Accelerating Factor in CDRs  
With an increasing \(n\), the related execution time of CDR calculation is prolonged. As the duration required to execute entire program in the microprocessors must be shorter than the control period, \(n\) cannot be too large. This is indicated by  
\[t_{\text{else}}+n\times t_{\text{mul}}<t_{\text{ctrl}} \tag{8}\]  
where \(t_{\text{mul}}\) is the required time of a single multiplication and \(t_{\text{else}}\) is the rest time of the whole program. Moreover, \(t_{\text{ctrl}}\) is the control period; here, it is equal to the switching period. The closed-loop control and data communications are accomplished using DSP28335 chips. The power function can be used to calculate high-order terms of SoC, but it takes much more time than continuous multiplication. Thus, continuous multiplication was utilized to reduce the execution time. Based on Inequation (8), the maximum \(n\) is confirmed.  
Under the enhanced strategy, the minimum \(n\) for parallel applications should make \(g\geq 1\) so that the current capacity of the converter is fully utilized. If \(i_{\text{sum}}-i_{\text{satu}}<i_{\text{satu}}\), that is, \(i_{\text{sum}}<2i_{\text{satu}}\), the following requirement should be satisfied:  
\[\frac{\max(SoC_{k0}^{n})}{\sum_{k=1}^{m}SoC_{k0}^{n}}\times i_{\text{sum}}>i_{ \text{satu}} \tag{9}\]  
The ESU current with lowest \(SoC_{k0}\) decreases when \(n\) increases. But it cannot be lower than the least significant current (LSC), which is decided by the range of current sensor and the bit number of analog-to-digital converter in microprocessors. The maximum \(n\) should correspond to the following:  
\[(i_{\text{sum}}-i_{\text{satu}})\times\frac{SoC_{3}^{n}}{SoC_{2}^{n}+SoC_{3}^ {n}}>1\text{ LSC} \tag{10}\]  
Inequations (8) and (10) are both considered for a maximum \(n\).  
If \(i_{\text{sum}}-i_{\text{satu}}>i_{\text{satu}}\), that is, \(i_{\text{sum}}>2\)\(i_{\text{satu}}\), it is possible that two units are saturated. To establish the above situation, the minimum \(n\) can be found, which is formulated as  
\[CDR_{11}|_{t=0}>i_{\text{satu}}/i_{\text{sum}},CDR_{22}|_{t=0}>i_{\text{satu} }/i_{\text{sum}} \tag{11}\]  
In addition, the maximum \(n\) is derived according to Inequation (8).  
As for series applications, the minimum \(n\) should let \(g+h=2\) so that the high current deviations help shorten the balancing duration. In Figure 6a, four potential paths exist, and they are separately expressed as  
\[CDR_{11}|_{t=0}>i_{\text{satu}}/i_{\text{sum}},CDR_{22}|_{t=0}>i_{\text{satu }}/i_{\text{sum}} \tag{12}\]  
\[\left\{\begin{aligned} & CDR_{11}|_{t=0}\leq i_{\text{satu}}/i_{ \text{sum}},CDR_{31}|_{t=0}<i_{\text{satt}}/i_{\text{sum}}\\ & CDR_{32}|_{t=0}<i_{\text{satt}}/i_{\text{sum}}\end{aligned}\right. \tag{13}\]  
\[\left\{\begin{aligned} & CDR_{11}|_{t=0}>i_{\text{satu}}/i_{ \text{sum}}\\ & CDR_{22}|_{t=0}<i_{\text{satt}}/i_{\text{sum}},CDR_{23}|_{t=0}<i_ {\text{satt}}/i_{\text{sum}}\end{aligned}\right. \tag{14}\]  
\[\left\{\begin{aligned} & CDR_{11}|_{t=0}\leq i_{\text{satu}}/i_{ \text{sum}},CDR_{13}|_{t=0}<i_{\text{satt}}/i_{\text{sum}}\\ & CDR_{32}|_{t=0}\geq i_{\text{satt}}/i_{\text{sum}},CDR_{31}|_{t=0 }>i_{\text{satt}}/i_{\text{sum}}\end{aligned}\right. \tag{15}\]  
In fact, only one of the above four expressions is feasible if a specific set of \(i_{\text{sum}}\), \(SoC_{k0}\), and current limits is adopted. And Inequation (8) is applied to acquire maximum \(n\).