# Supply-Scalable High-Speed I/O Interfaces
## 1 Introduction  
Nowadays, there are huge demands on a smarter world for better human convenience and happiness (i.e., manufacturing, smart city, autonomous vehicle, security... ). In order to realize those, it is inevitable that we have to create, replicate, and process tremendous amount of data [1]. For example, ref. [2] forecasts that the amount of data will increase by more than 3\(\times\) in five years. Handling those explosive data is a large burden on computer communications in the current computer architecture [3]. As a result, high-speed input/output (I/O) standards used for computer communications are evolving very rapidly, and moreover, new I/O standards are also being introduced to address various needs. In accordance with those trends, multi-standard I/O transceivers (transmitter and receiver) are getting a huge attention from industry to provide considerable flexibilities to IC products [4; 5; 6; 7; 8; 9; 10; 11]. To support multiple standards with a single transceiver design, it needs to be flexible for a variety of specifications, especially for a wide range of operating data rates. In addition, even for the cases of dealing with a single I/O standard, many standards require backward compatibility to their own legacy generations; for example, PCI Express, USB, serial ATA, etc. ; thus, the wide-range operation is also very important [12; 13]. However, implementing such wide-range capability introduces a large burden on the I/O design. Before deep diving into what the burden is, we briefly review the overall I/O transceiver architecture and how it works. As shown in the overall block diagram in Figure 1, the I/O transceiver is composed of three big parts: clock generation, a transmitter (TX), and a receiver (RX) [14]. In the clock generation, a phase-locked loop (PLL) is generally used to generate a high-frequency clock for the high-speed I/O from a low-frequency reference clock. These days, a half-rate clock (e.g., 14 GHz for 28 Gb/s NRZ datastream, also referred to as a double-data rate (DDR) clock) and a quarter-rate clock (i.e., 7 GHz for 28 Gb/s NRZ, also referred to as a quarter-data rate (QDR) clock) are generally used. The clock generation circuitry can be shared across multiple transmitter and receiver lines to amortize the areaand power consumption [15; 16; 17]. The high-frequency clock is distributed to the individual transmitters and receivers with a clock buffer chain. Depending on the macro floorplan, the distribution distance can be a few hundred \(\upmu\)m or even longer; a long chain of buffers needs to be used so that the distribution circuit consumes a significant amount of power. In addition, the high-speed clock may experience duty-cycle distortion and phase skew across the chain because of inherent device mismatch and duty-cycle error amplification [18; 19]. As a result, a duty-cycle correction (DCC) circuit or a quadrature error correction (QEC) circuit is frequently used at the transmit side to correct such distortions for better eye opening at the transmitter output. Based on the timing information from the corrected clock, parallel input data are serialized into a high-speed bitstream (serializer). The serialized data stream is transmitted through the transmission line driven by the TX output driver, whose output impedance is supposed to match with the characteristic impedance of the transmission line for signal integrity. To compensate inter-symbol interference (ISI) due to the channel loss at high frequency, a feed-forward equalizer (FFE), which combines multiple adjacent bits to cancel out the ISI effect, is frequently implemented at the transmit side. To adapt with various channel conditions and receiver sensitivity, the output voltage swing is configurable. On the receiver side, the received data is usually highly distorted by the ISI due to the limited channel bandwidth. Therefore, a continuous time linear equalizer that boosts high-frequency gain is generally placed at the front-end of the receiver.