## 3 Measurement Results  
A die photograph of the proposed readout IC for ECG recording is shown in Figure 12. The circuit was fabricated using a TSMC 180 nm CMOS process, and the active area of the proposed circuit was 856 \(\times\) 1523 \(\upmu\)m. The proposed circuit comprises a main block (CMCP, CFIA, and QRS peak detector), timing generator, bias block, and SPI in a single chip. Figure 13 shows the test board with a chip-on-board (CoB) process and the measurement environment used to evaluate the performance of the proposed readout IC using a printed circuit board (PCB). The gain error measurement results are shown in Figure 14. The CFIA gain was set as 46 dB (\(\times\)200). When CMCP is enabled and disabled, the gain error is within 0.5% at a 1-50 Hz bandwidth. Figure 11: Structure of the QRS peak detector. Figure 12: Die photograph of the proposed readout IC. Figure 15 shows the measurement results of the CMCP operation. A 20-V\({}_{\text{PP}}\) at 60 Hz sinusoidal signal was applied as the CMI. The CMCP comparators were set to V\({}_{\text{COMP}\_H}\) = 1.1 V and V\({}_{\text{COMP}\_L}\) = 0.7 V. When the CMI increased, the CMCP created downward-level shifts so that the V\({}_{\text{CMCP}}\) maintained a 1.1 V. In addition, when the CMI was rising, the CMCP created downward-level shifts so that the V\({}_{\text{CMCP}}\) maintains a 1.1 V.  
When the common-mode range was between 1.1-0.7 V, the CMCP operation was not performed, which has an advantage in terms of power consumption. The level-shifting voltage (V\({}_{\text{C}}\)) was maintained between 30-34 mV. It can be seen that the value is similar to the calculated value (32 mV) in Section 2. The measured tolerance to the CMI result was a 20 V peak-to-peak V\({}_{\text{CMI}}\). Figure 16 shows the measured input-referred noise of the proposed readout IC. The input-referred voltage noise was 119 nV/\(\sqrt{\text{Hz}}\) at 1 Hz and 57 nV/\(\sqrt{\text{Hz}}\) at 1 kHz. The measured integrated noise in the ECG signal band (1-100 Hz) was 0.59 \(\upmu\)V\({}_{\text{RMS}}\). Figure 14: Gain error measurement results when the CMCP is enabled and disabled. Figure 13: Measurement setup of the proposed ECG recording circuit. Figure 17 shows the signal quality measurement results when the CMCP operation was enabled and disabled. A differential input of 2 mV, 10 Hz sinusoidal signal, and a CMI input of 1 VPP, 60 Hz sinusoidal signal were applied. When the CMCP converts from the disabled state to the enabled state, the noise floor changed from \(-\)38 dB to \(-\)69 dB. The CMCP can have a good signal quality when the CMI voltage is presented. The common-mode rejection ratio (CMRR) measurement results are shown in Figure 18. The average CMRR for 1-100 Hz was 51.4 dB. The CMRR is mainly determined by the impedance mismatch, and the CMRR of the CFIA has a small effect [4]. Figure 15: CMCP operation with 20-VPP compliant measurement results. (**a**) Compare with VCMI and VCMCP at same amplitude range; (**b**) magnified waveform. Figure 19 shows the ECG signal acquisition results. Figure 19a shows the waveform when the CMCP is disabled. When the CMCP is disabled, the ECG signal is saturated by the CMI, and the CFIA output does not exhibit any P-Q-R-S-T complex. Figure 19b shows  
Figure 16: Input-referred noise measurement result of readout circuit. Figure 17: Signal quality measurement result when the CMCP operation is enabled and disabled. Figure 14.0 Common-mode rejection ratio measurement result of proposed readout circuit. the waveform when the CMCP is enabled. An LPF with a cut-off frequency of 40-Hz was applied to the CFIA output. When the CMCP is enabled, the CMI is reduced by the CMCP operation and the CFIA output clearly shows the P-Q-R-S-T complex. Table 1 summarizes the performance of the proposed readout IC for ECG recording using the CMCP [4; 5; 8; 11; 30; 31]. The proposed readout circuit has low power consumption and low noise characteristics. In addition, the 20-VPP CMI tolerance characteristics can be verified.