# Antenna-on-Chip for Millimeter Wave Applications Using CMOS Process Technology
## 2 Structure, Mechanism, and Design  
To miniaturize the millimeter wave antenna, the characteristics of a compact size and small assembly components are realized, having performance advantages such as a high gain and high directivity. Figure 2 shows that the patch antenna is the most common design style because of its simple structure. Moreover, structural changes can be designed efficiently for design applications such as cone beams and fan beams, and they are also easy to control. The following is the basic formula for designing a microstrip patch. The width W of a rectangular patch is obtained by the following Formula (1); the effective dielectric constant can be calculated using (2); the length L is obtained by the following Formula (5):  
\[W=\frac{c_{o}}{2f_{r}}\sqrt{\frac{2}{\epsilon_{r}+1}} \tag{1}\]  
\[\epsilon_{\text{eff}}=\frac{\epsilon_{r}+1}{2}+\frac{\epsilon_{r}-1}{2}\Big{[} 1+12\frac{h}{W}\Big{]}^{-\frac{1}{2}} \tag{2}\]  
\[\Delta L=0.412\frac{(\epsilon_{\text{e}}+0.3)\Big{(}\frac{W}{h}+0.264\Big{)}}{ (\epsilon_{\text{e}}-0.258)\Big{(}\frac{W}{h}+0.8\Big{)}} \tag{3}\]  
\[L_{\text{eff}}=L+2\Delta L \tag{4}\]  
Figure 1: Layer stack of a typical six-metal-layer TSMC 0.18 \(\upmu\)m CMOS process: (**a**) Cross-section view of the adopted TSMC 0.18 \(\upmu\)m CMOS process; (**b**) The number of layers used in the antenna design on this chip. Figure 2: The geometry of the patch antenna. \[L=\frac{c_{o}}{2f_{r}\sqrt{\epsilon_{eff}}}-2\Delta L \tag{5}\]  
where \(W\) is the width of the patch antenna, \(c_{o}\) is the speed of light, \(\epsilon_{r}\) is the dielectric constant of the substrate, \(f_{r}\) is the frequency, \(\epsilon_{\rm e}\) is the effective dielectric constant, \(\Delta L\) is the length difference affected by the edge effect, \(L_{\rm eff}\) is the effective length, and \(L\) is the actual length of the patch antenna. In addition, the antenna element is fed by a microstrip transmission line with a characteristic impedance of 50 \(\Omega\). It can be expressed using Formula (6):  
\[\frac{W_{f}}{h}=\frac{2}{\pi}\left\{\frac{60\pi^{2}}{Z_{o}\sqrt{\epsilon_{r}}} -1-\ln\left(\frac{120\pi^{2}}{Z_{o}\sqrt{\epsilon_{r}}}-1\right)\right\}+ \frac{\epsilon_{r}-1}{2\epsilon_{r}}\left[\ln\left(\frac{60\pi^{2}}{Z_{o}\sqrt {\epsilon_{r}}}-1\right)+0.39-\frac{0.61}{\epsilon_{r}}\right] \tag{6}\]  
As shown by the above documents, patch antennas have many advantages. Therefore, considering the above documents, this paper designs an antenna-on-chip using TSMC 0.18 \(\upmu\)m CMOS process technology, having a high bandwidth in the millimeter wave band. As shown in Figure 3, the overall structure comprises a triangular patch monopole antenna and a transmission line. In addition, the design of the AMC on the M1 layer is designed to enhance the gain of the antenna-on-chip, to prevent electromagnetic waves from spreading to the bottom and damaging the Si substrate, and to reduce the loss of electromagnetic waves [21]. The grounding of the antenna and the transmission line fed into the monopole antenna form a coplanar waveguide (CPW). The radiation gain and direction of the antenna-on-chip can be controlled by adjusting the size of the grounding area to achieve high-gain, high-directivity antenna performance. The geometric size of the antenna-on-chip and the overall size of the chip are marked with parameters, as shown in Figure 4. The values of all parameters are summarized in Table 1. The geometric size and detailed parameter values of the M1-layer AMC single structure are shown in Figure 5 and Table 2 and are simulated by high-frequency electromagnetic simulation software. The simulated reflection coefficient and radiation gain of the antenna-on-chip are shown in Figures 6 and 7. In this simulation, the antenna has the minimum reflection coefficient at 45 GHz, a coverage frequency band from 37.5 GHz to 69.5 GHz, and a maximum gain value of \(-2.64\) dBi at 62 GHz.