# Effects of Fractional Time Delay as a Low-Power True Time Delay Digital Beamforming Architecture
## 2 Theory of Operation
The proposed fractional delay filters utilize adjustable sinc impulses in the time domain [15] by delaying a rational number of samples, \(N\), as shown in (3)  
\[h(n,u)=\frac{\sin(\pi(n-u))}{\pi(n-u)},-\frac{N}{2}\ <n<\frac{N}{2}\,-0.5\leq u \leq 0.5, \tag{3}\]  
Figure 1: (**a**): Antenna patterns for two independent systems steering to \(\theta_{RES}\), \(10\) GHz \(F_{s}\), and \(4\) GHz signal. Ideal fractional delay (orange) vs. integer only delays (blue), and (**b**): FIR impulse response with \(0\) sample fractional delay (top) vs. \(0.4\) sample fractional delay (bottom). where \(h\) is the impulse response of the filter, \(n\) is the number of taps, and \(u\) is the fractional delay. Using Equation (3), a fractional delay of 0.4 samples in the impulse response is plotted in Figure 1b. The proposed method of fine delay tuning produces an excellent least-squares approximation error; however, group delay errors occur at the Nyquist bandwidth extremes due to the Gibbs phenomenon, producing quantization sidelobes [14; 15]. The Gibbs phenomenon is shown to be mitigated by both implementing lowpass architectures rather than allpass and windowing the impulse response with a bell-shaped non-negative weighting function, further supporting the proposed lowpass FIR architecture [14]. In order to analyze the worst-case sidelobe levels of the system, a case study was designed to maximize quantization error and maximize the periodicity of error. A simulation was performed such that every other element was assigned zero error with the alternate elements being assigned \(\frac{LSB}{2}\) error [25]. The DBF was then steered using Equation (4) to produce the maximum possible quantization sidelobe levels (QSLL),  
\[\theta_{MAXQSLL}=\sin^{-1}\frac{\pm x}{2^{BITS}}, \tag{4}\]  
where \(\theta_{MAXQSLL}\) is the steering angle that produces the maximum QSLL, and \(BITS\) is the number of time delay bits in the system. Note that \(x\) is a scalar that must be odd and satisfy the condition \(n<2^{BITS}\). As the proposed architecture utilizes fractional time delay rather than phase shift, the system gains resolution from two factors: (1) the oversampling factor (OSF) of the system and (2) the number of fractional delay bits. This is described in Equation (5), as follows:  
\[ENOB=log_{2}\Big{(}OSF*2^{BITS}\Big{)}, \tag{5}\]  
where \(ENOB\) is the Effective Number of Bits. Oversampling improves \(ENOB\) by lowering the noise floor which increases the signal to noise ratio (SNR) of the sampled signal. In the specific case of this work, a 3-fractional bit system with a 10 GHz sampling rate and 4 GHz bandwidth would produce a system ENOB of 4.32 bits. As a result, Equation (4) can be rewritten, substituting \(ENOB\) for \(BITS\), as follows:  
\[\theta_{MAXQSLL}=\sin^{-1}\frac{\pm n}{2^{ENOB}}, \tag{6}\]  
The \(ENOB\) will then be used to analyze the system. Finally, proper system resolution is critical to ensure sufficient sidelobe suppression. The maximum QSLL of the proposed system can be determined using Equation (7) [25]. \[QSLL\ \alpha\ 20\log_{10}2^{-ENOB} \tag{7}\]  
In order to produce a maximum QSLL of \(-34\) dB for a 10 GHz sampling rate and a 4 GHz bandwidth, the system must have an \(ENOB\) of at least 5.65 bits.