# A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis
## 3 TSV Reliability
### Copper Contamination
This phenomenon can lead to the formation of voids, which can eventually result in open circuits, causing a malfunction or failure of the interconnect. The void formation is mainly caused by the accumulation of metal atoms, which is driven by the electron wind and the thermal energy generated by the current flow. The resulting voids may initiate or propagate cracks in the surrounding dielectric layers, compromising the electrical conductivity of the interconnect. Therefore, it is essential to understand and mitigate the effects of atomic migration to enhance the reliability of BEOL interconnects. Notably, atomic migration can also be a significant reliability issue for through-silicon vias (TSVs), where the mass transport of metal atoms can cause voids, leading to the failure of the interconnect [44]. The behavior of electrons and the copper lattice in backend of line (BEOL) interconnects can lead to atomic migration, which has significant impacts on the reliability of the interconnects. Specifically, the momentum exchange between electrons and copper atoms causes the migration of copper atoms, leading to void formation in their original positions. Furthermore, copper atoms can accumulate in the silicon layer, causing contamination and the formation of mound-like protrusions. This phenomenon can be driven by a variety of physical mechanisms, including electric currents, stress gradients, and temperature gradients. Atomic migration can be classified into three types: electromigration (EM), stress migration (SM), and thermal migration (TM), which are governed by the mass balance equation. Research by [PERSON] et al. [35] has shown that stress migration occurs earlier than electromigration in copper through-silicon vias (TSVs), regardless of the presence of Bosch scallops. This finding suggests that stress is a key factor in the early migration failure of copper tsv. Moreover, significant atomic migration can be observed at both ends of the tsv and in the region around the Bosch scallop. Concentration fluctuations with a maximum amplitude of 0.38 can also be induced along the Bosch scallop interface, which increase with the width of the Bosch scallop. However, reducing the Bosch scallop width to below 20 nm can avoid significant atomic migration and stress concentration. Additionally,optimizing the working and process temperatures can minimize the migration failure of copper TSVs. Overall, atomic migration is a complex phenomenon in BEOL interconnects that can lead to the failure of the interconnects. Understanding the physical mechanisms driving atomic migration is crucial for designing reliable interconnects. Proper design and fabrication techniques should be employed to prevent or minimize the effects of atomic migration in TSVs, including optimizing the working and process temperatures, reducing the width of the Bosch scallop, and reducing stress concentrations. The effect of copper contamination caused by TSV on the reliability of 3D-IC devices was electrically characterized by [PERSON] et al. [17] The effect was measured by capacitance time (C-t). Cu/Ta gate trench capacitors with two types of Ta barrier layers were fabricated with thicknesses of 10 and 100 nm. The C-t curve of the trench capacitor with a 100 nm thick Ta layer did not change after annealing at 300 \({}^{\circ}\)C for up to 60 min. However, the C-t curve of the trench capacitor with a 10 nm thick Ta layer was severely degraded even after 5 min of initial annealing. This means that Cu atoms diffuse from the Cu-TSV into the active region through the scalloped portion of the TSV with a very thin Ta layer, and, therefore, the lifetime of minority carrier generation is significantly reduced. C-t analysis is a useful method to electrically characterize the effect of Cu contamination of Cu-TSVs on the reliability of devices in fabricated wafers [17].