## 4 Main Idea of Proposed Method  
Let a Mealy FSM be represented by an STT with \(H\) rows. Let us possess only a single EMB to implement the FSM circuit. Let us have FPGA chip with LUTs with \(S_{L}\) inputs. Let the terms \(F_{h}\) (\(h\in\{1,\ldots,F_{H}\}\)) form a set \(F=\{F_{1},\ldots,F_{H}\}\). Let us use the encoding of terms \(F_{h}\in F\) to reduce the number of LUTs in the FSM circuit. Let us find the value of \(K\) for given STT and value of \(S_{L}\), where:  
\[K=\lceil H/2^{S_{L}}\rceil. \tag{21}\]  
Let us discuss a case, when \(K>1\). It means that \(R_{H}>S_{L}\). Therefore, both LUTer\(\Phi\) and LUTerY of \(U_{4}\) are represented by multi-level circuits. In this article, we propose a method allowing: (1) to diminish the number of LUTs in comparison with equivalent FSM \(U_{4}\) and (2) to regularize the interconnections. The method is based on dividing the initial STT by \(K\) sub-tables with up to \(2^{S_{L}}\) rows. Let us illustrate this method using the STT of \(S_{1}\) (Table 1). Let us use an EMB such that the condition (7) is violated for \(S_{1}\). Let the EMB have the configuration \(\langle S_{A},t_{F}\rangle\) such that the following conditions are true:  
\[S_{A}-1<L+R\leq S_{A}; \tag{22}\]  
\[N+R>t_{F}\geq R_{H}. \tag{23}\]  
The condition (22) shows that it is enough a single EMB to implement SBF (16). The condition (23) shows that it is not possible to implement an FSM circuit using a single EMB. Let us find a partition \(\Pi_{F}=\{F^{1},\ldots,F^{K}\}\) of the set \(F\) such that the following condition takes place:  
\[R_{k}\leq S_{L}\quad(k\in\{1,\ldots,K\}). \tag{24}\]  
Let it be \(H_{k}\) elements in the set \(F^{k}\). The value of \(R_{k}\) is determined as:  
\[R_{k}  
Let us encode the term \(F_{h}\in F^{k}\) by a binary code \(C(F_{h})\) with \(R_{k}\) bits. Let us use variables \(z_{r}\in Z\) for the encoding. These variables are the same for all classes \(F^{k}\in\Pi_{F}\). To distinguish the classes, let us encode classes \(F^{k}\in\Pi_{F}\) by binary codes \(C(F^{k})\) with \(R_{C}\) bits:  
\[R_{C}=\lceil log_{2}K\rceil. \tag{28}\]  
Let us use the variables \(v_{r}\in V\) to encode the classes, where \(|V|=R_{c}\). Now, the code \(K(F_{h})\) is represented as  
\[K(F_{h})=C(F^{k})*C(F_{h}), \tag{29}\]  
where \(*\) is a sign of concatenation. Of course there is \(R_{H}=R_{k}+R_{C}\). Let the following condition take place:  
\[\Delta_{t}=t_{F}-R_{H}>0. \tag{30}\]  
In this case, some functions \(D_{r}\in\Phi\) and \(y_{n}\in Y\) could be implemented by EMB. Let they form sets \(\Phi_{E}\) and \(Y_{E}\), respectively. Therefore, LUTs should be used for implementing the remained functions. Let it be \(\Phi_{L}=\Phi\setminus\Phi_{E}\) and \(Y_{L}=Y\setminus Y_{E}\). Using these preliminaries, we propose the model of Mealy FSM \(U_{5}\) (Figure 6). In FSM \(U_{5}\), the EMB generates functions (16) and the following SBFs:  
\[V=V(T,X); \tag{31}\]  
\[\Phi_{E}=\Phi_{E}(T,X); \tag{32}\]  
\[Y_{E}=Y_{E}(T,X). \tag{33}\]  
The LUTerk \((k\in\{1,\dots,K\})\) generates functions:  
\[S_{A}-1<L+R\leq S_{A}; \tag{22}\]0  
\[S_{A}-1<L+R\leq S_{A}; \tag{22}\]1  
The LUTer\(\Phi\)Y implements functions \(D_{r}\in\Phi_{L}\) and \(y_{n}\in Y_{L}\) where  
\[S_{A}-1<L+R\leq S_{A}; \tag{22}\]2  
\[S_{A}-1<L+R\leq S_{A}; \tag{22}\]3  
In (36) and (37) the superscript \(k\) means that the corresponding function is generated by LUTerk. The \(C_{rk}(C_{nk})\) is a Boolean variable equal \(1\) if and only if \(D_{r}\in\Phi_{L}^{k}\), \(y_{n}\in Y_{L}^{k}\). Also, functions  
\[S_{A}-1<L+R\leq S_{A}; \tag{22}\]4 Structural diagram of Mealy FSM \(U_{5}\). enter LUTerQY. Each function requires a flip-flop, so it uses a single LUT. The symbol \(V_{k}\) stands for the conjunction corresponding to \(C(F^{k})\):  
\[S_{A}-1<L+R\leq S_{A}; \tag{22}\]5  
In (38), \(l_{kr}\) is a value of the r-th bit of \(C(F^{k})\), \(l_{kr}\in\{0,1\}\), \(v_{r}^{0}=\sigma_{r}\), \(v_{r}^{1}=v_{r}\) (\(r\in\{1,\ldots,R_{c}\}\)).