## 3 The Design Process for an Aging Sensor with Multiple Points of Frequency Detection
### Proposed Automatic Clock Correction  
The delay degradation on the FPGA is continuously affected [54; 55]. Therefore, it is crucial to correct the circuit automatically. Although the correction does not fully recover the chip, it is essential to maintain the efficiency and stability to provide a correct output. Automatic clock synchronization is a process of a centralized system that depends on the synchronized clock input. The clock synchronization is widely used in a wireless sensor network for correction purposes. Recent studies proposed several methodologies for performing clock correction, along with error correction for circuit design. [PERSON] et al. digitized an analog signal and compared the signal to a reference value to maintain a near-zero error signal while focusing on the duty cycle obtained from the digital clock manager [56]. [PERSON] et al. supported this finding by developing a built-in error correction for the same clock cycles in FPGA cells [57]. Two clock correction algorithms called a Kalman filter and weighted-average-based NIST AT1 were investigated by [PERSON] et al. to detect failures and perform corrections from developed clock monitoring and a control unit [58]. This present work focused on automatic clock correction for an aging circuit, as shown in Figure 8. The circuit is illustrated in Figure 3 as a CUT module that aged or was injected with a substantial amount of delays was used to demonstrate the correction process. If aging is detected, the user can select either to enable the automatic clock correction input or not. The input signal then passes through the automatic clock correction circuit, which performs as a feedback circuit. The output waveform needs to be validated on the timing diagram to show that the correction process was made correctly. The output must indicate that there is no aging delay detected after a correction has been made. In order to validate this automated clock correction design, the proposed circuit was tested and evaluated experimentally for various types of combinational and sequential logic circuits, such as encoders, decoders, adders, and multiplexers. A top module block diagram for the automated clock correction circuit is shown in Figure 9. The module consists of four inputs called _Vi_, _enable_, _Clk_, and _rst_ and produces an output called _out_as_. First, the circuit is synchronized using a global clock that is fed with a standard clock signal _Clk_. The output of this global clock is fed into multiple clock generators, an automatic clock selector, the circuit under test, and enhanced phase shift \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{**Sample _Vi_ Phase**} & \multicolumn{6}{c}{\(\theta_{2}\) **Values for Different Types of Clock Delay**} & \multirow{2}{*}{**Hex**} \\ \cline{2-2} \cline{5-8}  & & \(\mathbf{0^{\circ}}\) & \(\mathbf{50^{\circ}}\) & \(\mathbf{100^{\circ}}\) & \(\mathbf{150^{\circ}}\) & \(\mathbf{200^{\circ}}\) & \(\mathbf{250^{\circ}}\) & \(\mathbf{300^{\circ}}\) \\ \hline
220\({}^{\circ}\) & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 3C \\
270\({}^{\circ}\) & 0 & 1 & 1 & 1 & 1 & 1 & 0 & 3E \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Sample aging detection process. Figure 8: Flow chart for automatic clock correction. detector modules. The combination of comparator and phase shift detector modules from Figure 3 are integrated into this enhanced phase shift detector module. Subsequently, the multiple clock generators module generates various types of stable clock signals, which were \(0^{\circ}/360^{\circ}\), \(50^{\circ}\), \(100^{\circ}\), \(150^{\circ}\), \(200^{\circ}\), \(250^{\circ}\), and \(300^{\circ}\). This module also has a reset signal _rst_ for safety precautions and an input signal for the initialization process. An automatic clock selector module selects the appropriate clock signal input according to the circuit specifications. By default, a phase of \(0^{\circ}/360^{\circ}\) is set to trigger the circuit. This module consists of three inputs and produces a single output.