# A Review of Research on Signal Modulation Recognition Based on Deep Learning
## 5 Hardware Implementation of Modulation Recognition Algorithm Based on Deep Learning  
In the previous introduction, we learned that the modulation identifiers based on deep learning are all completed by simulation. However, if you want to better apply the modulation identifiers based on deep learning in actual communication systems, you need to use hardware circuits to implement related algorithms. Through literature review, this paper understands that the use of hardware circuits to implement DL-based AMR algorithms can be roughly divided into three processes, which can be represented by Figure 14.  
According to Figure 14, if you want to use a hardware circuit to implement a modulation recognizer based on deep learning, you first need to use a computer programming language, such as Python, C, or MATLAB, etc., to design a deep neural network, and then use simulation software to train the neural network to optimal. Then use hardware description language, such as VHDL, Verilog, etc., to describe the trained modulation recognizer, and use hardware language simulation software, such as ModelSim, etc., to simulate. Next, download the hardware description language to the hardware circuit for debugging, and finally realize the modulation and identification of the signal. At present, the commonly used hardware platforms for signal modulation and identification algorithms include central processing unit (CPU) + image processing chip (GPU), programmable array logic (FPGA), etc., of which FPGA can achieve acceleration and can also simulate parallel operations of CPU and GPU. It has powerful computing power and flexibility. Using hardware circuits to implement deep learning-based modulation identifiers has important research significance in practical engineering, attracting many scholars to conduct research. Current research includes results by the authors of [109] who proposed an FPGA-based convolutional neural network modulation recognition method. The authors first designed a convolutional neural network in TensorFlow, then used VHDL language to describe the CNN and download it to the FPGA to achieve accelerated modulation recognition. It has been proved by experiments that the recognition accuracy of FPGA reaches more than 80% at 4 dB, which is close to the recognition accuracy of a CPU, but the recognition speed of FPGA is 10 times that of a CPU, which greatly improves the recognition speed. The authors of [110] used FPGA to implement AMR algorithm based on stacked convolutional autoencoders (CAE). In this work, a deep neural network needs to  
Figure 14: Using hardware circuit to implement the DL-based AMR algorithm. be trained on a GPU, and then the trained neural network is transformed into an FPGA configuration file. Finally, the configuration file is transferred to the FPGA SDR platform to realize the function of AMR. In the final experiment, it is shown that the average score accuracy on FPGA is 70%-80%. Research by the authors of [111], different from the above two works, proposed a real-time modulation recognition system based on software-defined radio and multi-hop residual neural network (MRNN). The authors use RadioML2018.01A to optimize the performance of MRNN and then embed the neural network into the SDR platform composed of GNU radio and USRP radio to achieve real-time modulation recognition. Among them, the USRP model selected by the authors is the USRP B210. The final experiment shows that the system can complete the real-time recognition of modulated signals. The average recognition time is 4.1 ms, and the average recognition accuracy is greater than 90%. The authors of [112] proposed a classification convolutional neural network model for modulation recognition and implemented the proposed classification convolutional neural network on FPGA. The experimental results show that the network is well implemented on the FPGA. When the signal-to-noise ratio is greater than 5 dB, the recognition accuracy of the radioml2016.10a dataset is greater than 80%.