## 2 Simulation
This finding highlights the significant influence of the via length-to-width ratio on resistance and suggests that extending the via length parallel to the current flow while reducing its width is an effective strategy for resistance reduction. These results indicate that even when the via area is the same, the current density is not uniform. If the current density were uniform, there would be no difference in resistance values. Therefore, the difference in current density suggests that charge does not distribute evenly within the via region. To verify this, simulations were also conducted to analyze resistance variations by changing the interconnect-via contact area (in this study, by gradually reducing the contact area to simulate increasing misalignment). The misalignment condition was implemented by shifting the upper metal interconnect in 2.5 \(\upmu\)m increments, gradually reducing its contact area with the via, and analyzing the total resistance under these conditions. According to the simulation results in Figure 3, resistance remained relatively stable, with a variation of less than 3%, up to a misalignment of 5 \(\upmu\)m. However, beyond this point, as the contact area decreased further, the resistance  
Figure 3: Total resistance as a function of misalignment for different via structures: 10 \(\upmu\)m \(\times\) 10 \(\upmu\)m, 5 \(\upmu\)m \(\times\) 20 \(\upmu\)m, and 20 \(\upmu\)m \(\times\) 5 \(\upmu\)m.  
increased sharply. Additionally, the structure with a larger initial resistance--where the via was elongated in the transverse direction (resulting in a longer current path through the via)--exhibited a more significant increase in resistance. These results indicate that insufficient contact area leads to electrical performance degradation, and the extent of this degradation is also influenced by the shape of the via. Additional simulations were performed to examine the distribution of current density and analyze conditions where the interconnect-to-via contact area decreases due to misalignment. Using the same settings as in the previous Ansys Workbench simulations, a 3 V horizontal voltage was applied to model the current flow from the interconnect through the via and back to the interconnect, as shown in Figure 4a. The mesh size was set to 1 \(\upmu\)m to maintain high simulation accuracy, as depicted in Figure 4b. The simulated structures were based on Figure 2a,b, with contact area reductions ranging from fully overlapped to 90% misaligned. The impact of contact area variation on current density and resistance was then analyzed. Based on the structure shown in Figure 4, the simulation was conducted, and the cross-sectional current distribution is presented in Figure 5. The simulation results indicate that current density flows along the metal interconnect and concentrates diagonally within the via after reaching it. Even as the contact area decreases, current density remains concentrated at the via-interconnect contact edges, suggesting that the primary current path through the diagonal via direction is maintained despite contact area reduction. Additionally, negligible current density was observed in interconnect regions that were not in contact with the via. This finding implies that unnecessary interconnect regions that do not contribute to the current flow can potentially be eliminated from the design. The analysis of current density flow patterns revealed that as the interconnect-to-via contact area decreases, current density within the via increases. However, the overall current flow pattern remains consistent. Current enters the via from the interconnect, flows diagonally within the via, and exits through the interconnect. Notably, even if the interconnect length is sufficiently long, current does not flow significantly in areas not directly contacting the via. This suggests that longer interconnects do not necessarily enhance current conduction efficiency and that current flows primarily through areas where interconnects are physically connected to the via.