# A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver
## 4 Small-Signal DBB-CDR Model  
An intuitive understanding of the performance of a CDR circuit is whether it can provide an optimal sampling phase for an ADC to allow the wireline transceiver system to achieve the lowest bit error rate (BER). In the testing stage, we could obtain the performance of the CDR circuit using the BER results. However, in the simulations, it was hard for us to verify the communication protocol requirements of a BER of \(10^{-12}\) or even \(10^{-15}\). Thus, we could not verify the performance of the CDR circuit via time-domain simulations during the design stage. Therefore, during the design stage, we could only analyze the performance of the CDR circuit by linearizing it. However, the performance of MM-CDR  
Figure 10: A timing diagram of the 32 TI-SAR ADC T/H clock with the edge sampling clock CK<1.5\(\succ\). Figure 9: The 32 TI-SAR ADC T/H clock buffer and time interpolator for our partial oversampling system. circuits is hard to analyze because of the lack of a linearized MMPD model, so most studies have only focused on the application of MM-CDR circuits without systematic analysis. Different from MM-CDR circuits, it is easy to perform linearization analysis on DBB-CDR circuits because the linearization of the BBPD has been well analyzed. In order to analyze the performance of our DBB-CDR circuit, it needed to be linearly modeled and then we could proceed to analyzing its jitter transfer function (JTF) and jitter tolerance (JTOL). The linearized model that was equivalent to the architecture in Figure 7 is shown in Figure 11.  
In the figure, \(K_{PD}\) is the gain of the DBBPD, \(K_{P}\) is the gain of the proportional path, \(K_{I}\) is the gain of the integral path, \(K_{PI}\) is the gain of the phase interpolator and \(z^{-N}\) is the delay of the digital CDR circuit. These parameters are listed in Table 3 and are described in the following content. The values of \(K_{PD}\) were calculated according to Equation (6) under different variance values \(\sigma\) of Gaussian jitter. We assumed that \(\sigma\) equaled to 0.04 UI, 0.03 UI and 0.02 UI, to demonstrate the circuit performance under different Gaussian jitter values. The values of \(K_{P}\) and \(K_{I}\) could be set within certain ranges to meet the requirements of the CDR loop circuit characteristics, such as the bandwidth of the CDR circuit and the range of the frequency deviation tracking. The element \(K_{PI}\) corresponded to the resolution of the phase interpolator in UI per bit. Considering the performance and complexity of the circuit, we chose a phase interpolator resolution of 5 bits. The performance of the CDR circuit under consideration was mainly analyzed in terms of jitter transfer function and jitter tolerance. The circuit gain of this linearized model could be analyzed as follows:  
\[L\Big{(}z^{-1}\Big{)}=\frac{\boldsymbol{\varphi}_{OUT}}{\boldsymbol{\varphi}_{ E}}=\frac{K_{PD}K_{PI}}{1-z^{-1}}\bigg{(}K_{P}+\frac{K_{I}}{1-z^{-1}}\bigg{)}z^{ -N} \tag{7}\]  
The expression of the jitter transfer function was:  
\[H\Big{(}e^{-j\omega}\Big{)}=\frac{\boldsymbol{\varphi}_{OUT}}{\boldsymbol{ \varphi}_{IN}}=\frac{L\big{(}e^{-j\omega}\big{)}}{1+L\big{(}e^{-j\omega} \big{)}} \tag{8}\]  
Figure 11: The linearized DBB-CDR model. \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameter** & **Value** \\ \hline  & 14.4 per UI when \(\sigma=0.02\)UI \\ \(K_{PD}\) & 9.6 per UI when \(\sigma=0.03\)UI \\  & 7.2 per UI when \(\sigma=0.04\)UI \\ \(K_{P}\) & \(2^{-7}\) \\ \(K_{I}\) & \(2^{-18}\) \\ \(K_{PI}\) & 1 UI/\(2^{5}\) bit \\ \(N\) & 5 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: The parameters of the linearized DBB-CDR model DBB-CDR. Jitter tolerance is required under a specific bit error rate requirement. The CDR circuit in this study needed to meet the JESD204C protocol, which has a bit error rate requirement of \(10^{-15}\).