## 2 Buck Converter Modeling

Table 5: \(i_{L}\) and \(v_{C}\) error values with Algorithm 4 at \(dt=1\) us, fixed-point representation. the algorithm for the proposed target device XC7A35T from the Xilinx Artix-7 series, which is a low-cost FPGA of around 100 USD. A pipelined implementation will perform these actions in sequential stages:

1. Fetch status of \(S1\) and \(S2\), and initialize values. 2. Calculate successively \(K1C\), \(K1L\) to \(K4C\), and \(K4L\) and accumulate the state variable increments \(\Delta i_{L}\) and \(\Delta v_{C}\) at each step. 3. Raise a \"zero-crossing\" flag if the new \(i_{L}\) value creates a zero-crossing during the deadtime. 4. Input dividend and divisor to the divider. 5. With the result of the division, obtain \(dt1\) and \(dt2\). 6. Recalculate new state variable increments using the time steps \(dt1\) and \(dt2\), again by successive calculation of \(K1C\) and \(K1L\) to \(K4C\) and \(K4L\) and accumulation of increments \(\Delta i_{L}\) and \(\Delta v_{C}\) at each step. 7. Assign the new value of state variables depending on the value of the \"zero-crossing\" flag. The first stage starts by deciding which values of \(v_{in}\), \(i_{L}\), \(v_{C}\) and \(\Delta t\) will be used in one cycle. Calculation of \(K1C\), \(K1L\) to \(K4C\), \(K4L\) is performed in four cycles using a \"K-calculator\" block described below, with one extra cycle for calculating the next value of \(v_{C}\) and \(i_{L}\). The next cycle calculates the inputs to the divider and raises or does not raise the \"zero-crossing\" flag to be used later. The divider was configured for a latency of seven clock cycles, as the best compromise between resource usage and speed. The second stage starts with a cycle for calculating \(\Delta t\) values to be used for every semi-step and performs the calculation of \(KnC\) and \(KnL\) of item 6 using nine cycles. In the last cycle, depending on the \"zero-crossing\" flag, either these values or those calculated at the end of the first stage are used for updating the state variables. In total, 25 clock cycles are used to perform these operations. ### K-Calculator Generic Block

One can take advantage of the structure of successive calculations of \(KnC\) and \(KnL\) values, which is very similar in all cases. The only difference is a factor of 2 present in the calculation of \(K2L\), \(K2C\), \(K3L\), and \(K3C\) values. A \"K-calculator\" generic block performing these operations can be defined as follows (Figure 7):

\[K_{out}C = \frac{iL+K_{in}L\times\Delta t}{C}-\frac{vC+K_{in}C\times\Delta t} {R\times C} \tag{12}\] \[K_{out}L = \frac{v_{in}}{L}-\frac{vC+K_{in}C\times\Delta t}{L} \tag{13}\]

If this K-calculator is fed with the appropriate inputs in each case, then a single calculation block can be reused for all the computation cycles of the \(KnC\) and \(KnL\) values. These will be computed in four successive cycles. The inputs \(i_{L}\), \(v_{C}\), \(v_{in}\) and \(\Delta t\) are kept unchanged during the four cycles. The voltage \(v_{in}\) can be \(v_{s}\) or zero depending on the operating state. The value of \(i_{L}\) can be the inductor

Figure 7: K-calculator generic block. current or zero also depending on the state. \(\Delta t\) can be either the reference value used for the calculation or \(\Delta t1\) and \(\Delta t2\) in succession, if the calculation is made for two semi-steps during a deadtime. The first cycle has as inputs \(K_{in}C=0\) and \(K_{in}L=0\). This gives \(K1C\) and \(K1L\) as the outcome of the calculation. They are the initial values of accumulators that at the end of the fourth stage will contain the \(\Delta v_{C}\) and \(\Delta i_{L}\) values. They are also multiplied by \(1/2\) and are fed again into the \"K-calculator\" block as \(K_{in}C\) and \(K_{in}L\). The calculator block delivers \(K2C\) and \(K2L\) at the following cycle.