## 7 Results
### Experimental Validation  
Finally, in order to validate the implementation capabilities of the proposed design methodology, where the performed tests are documented in the nominal operation values discussed in Table 2. Furthermore, it is important to highlight that as discussed in Section 6, all the control signals are given by the FRDM-K64F development board. Moreover, Figure 21 shows how the testbeds from Figure 14 (with the optimized and the non optimized inductor values), were simultaneously tested using a constant nominal load (90 [\(\Omega\)]). The main objective of this test, is to validate the ripple reduction in the current of the optimized designed. Therefore, Figure 22 shows the screenshot from the oscilloscope during the current evaluation, where it can be clearly seen the ripple reduction in the optimized design (Red Channel 2 in Figure 22). Nevertheless, since (as discussed in Section 6) the current profiles were obtained by measuring the analogic output in the Current-Sense amplifier (MAX44285H), post-processing of the acquired data is required for a correct evaluation in terms of [A]. Henceforth, after the data acquisition and voltage to current conversion (as recommended in [31]), Figure 23 shows the experimental results processed and plotted in MATLAB;  
Figure 21: Simultaneous current evaluation of the experimental testbeds. Figure 22: Control signals in the optimized design. feature to be highlighted is the ripple reduction in the current of the optimized design compared to the non-optimized converter. Therefore, the measured ripple of the optimized converter is 0.014 [A], meanwhile a 0.048 [A] ripple was achieved by the non-optimized design, which is traduced into a 70.833% of ripple reduction. Hence, the ripple reduction is validated as one of the main contributions of the proposed model. On the other hand, each converter was individually tested in their nominal operation parameters, but this time seeking to acquire precise data regarding the output voltage performance of the converters through different control signals (duty cycle); where the duty cycle changes allow to evaluate how aggressive the output voltage changes, which allows evaluating the real achievable precision of the converter designs, since a more robust response can be achieved if the converter can make more precise adjustments in terms of its control signal. Thus, Figure 24 shows how the testbeds were individually tested using a BK Precision 8601 (B&K Precision Corporation, Yorba Linda, CA, USA). DC Electronic Load, which allowed to safely manipulate the duty cycle of the converters in order to acquire precise voltage data regarding the duty cycle variations. Hence, Figure 25 presents the experimental validation of the output voltage compared to the Simscape Simulink Model, which allows by inference to also validate that the mathematical models  
Figure 23: Control signals in the optimized design. Figure 24: Precision output voltage against duty cycle evaluation. used for optimization were correctly developed, since the transfer functions model showed high fidelity compared to the Simscape model in Section 5. Moreover, from the performed analysis through the simscape simulations, it was clear that the dynamic behavior of the output voltage of the converter did not have a significant change compared to the current ripple. Nevertheless, it is worth to analyze the performance of the converter through different duty cycle perturbations, since it allows to analyze the precision of the converter and how it will react against perturbations around nominal conditions (since the duty cycle is the control input of the system). Thus, Figure 26 presents a comparative analysis of both designed converters (optimized and non-optimized), wherein both cases it is highlighted in black the profile that represents the nominal conditions of the converter. Hence the output voltage against different duty cycle curves were obtained with a 5% difference between each profile, in order to analyze a wider range of operation in both converters.