## 2 Background
### Emulation-Based Fault Injection  
A variety of emulation-based fault injection testing tools that provide highly accessible testing environments are under development [13]. This section introduces an emulation fault injection tool capable of accurately and precisely specifying fault injections in specific areas of the design under test.  
For example, the methodology for configuring the tool and integrating it with the new FPGA family is also presented [14]. In this study, we establish a fault injection platform based on SEM IP and conduct fault injection tests on a 16K-point FFT (fast Fourier transform) function.  
In another study, faults are injected during the runtime environment, and the resulting effects on soft errors at the system level are analyzed by comparing them with golden runs [10]. Furthermore, this study implements a fault injection test program using MATLAB and SEM IP. It establishes an environment that can inject errors during the runtime into the configuration memory by controlling the SEM IP core from MATLAB on an external host PC.  
Additionally, [11; 12] present test results using emulation methods that access the configuration memory of the FPGA and inject bit-flip faults. These tools conduct testing by  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Method** & **Description** & **Cost** & **Testing Time** & **Accessibility** & **Reproducibility** & **Realistic** \\ \hline \multirow{2}{*}{Hardware} & Injects faults via pin connection or & & & & & \\  & neutron ion radiation & & & & & \\ \hline \multirow{2}{*}{Software} & Introduces faults through code or & & & & & \\  & trigger mechanisms & & & & & \\ \hline \multirow{2}{*}{Simulation} & Injects faults in design simulation & & & & & \\  & via sabotage, ’force,’ or & & & & & \\  & kernel access & & & & & \\ \hline \multirow{2}{*}{Emulation} & Induces soft-error-like phenomena & & & & & \\  & in circuits synthesized on the & & & & & \\  & target board & & & & & \\ \hline \hline \end{tabular}
\end{table}
Table 1: Comparison of fault injection methods: hardware-based, software error, simulation-based, and emulation fault injection.  
configuring a statistical fault injection test environment for a wide range of configuration memory bits.  
The above-mentioned test tools primarily focus on soft fault injection testing for various FPGA configuration memories. However, the scope of these tests is unclear, making it difficult to accurately characterize the errors within the target circuit. Additionally, potential issues like injection side effects can complicate the failure analysis by introducing faults in areas other than the target circuit.  
To address the problem of injection side effects, where faults may unintentionally impact areas containing fault injection functions, this paper restricts fault injection to predefined DUT (design under test) regions, where faults are not intended to occur. An approach has been implemented to effectively prevent the spread of false faults. The objective is to conduct fault injection tests without the risk of contaminating other parts of the system and to contribute further to system reliability analysis by conducting statistical fault injection tests on specific target circuits and presenting target failure rates.