# Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing
## 3 Results and Discussion
### Binarized Neural Networks Applications
Compared to an analog implementation, the SIMPLY architecture trades reconfigurability for larger computation latency. To address the higher latency issue, the multi-input IMPLY operation can be used as discussed below. As shown in [30], in BNNs, multiplications between the inputs and each neuron's weights are implemented with bitwise XNOR operations, the accumulation as the popcount operation, and the activation as a comparison with a trained threshold. In addition, batch normalization layers can be implemented with full adders for which we have already discussed the optimized n-SIMPLY implementation. The effectiveness of the multi-input IMPLY operation in reducing the number of computing steps is analyzed for each logic function since it is strongly dependent on the associated specific sequence of operations. As shown in Figure 9, by using the 3-SIMPLY the XNOR operation is computed in 5 steps while using a single additional device, instead of requiring 9 steps and 2 additional support devices when using only the 2-SIMPLY. For the popcount and activation function operations, different optimization strategies that minimize the number of computing steps for different fan-in (i.e., n) of the n-SIMPLY operation can be employed. As shown in [30], the accumulator can be implemented as a chain of log\({}_{2}\)(#input bits) 1-bit half adders (HAs) where the first HA receives in input the bit that needs to be accumulated and its current output (i.e., \(S_{0}\) in Figure 10a), while the following HAs receive at their inputs the carry-out from the previous HA and their current output (i.e., as in in Figure 10a but also for more than two HAs). When accumulating a sequence of bits, all the bits are input sequentially to the HA representing the LSB. The operations of the subsequent HAs are performed only after a number of input bits equal to their relative bit position have been summed (e.g., HA with bit position 3 is activated only after 2\({}^{3}\) input bits have been summed). Thus, the length of the HA chain grows as more input bits have been summed. By using the 3-SIMPLY operation, the number of steps for each HA operation is reduced from 13 to 11, see Supplementary Figure S1. An effective strategy that can further reduce the total number of computing steps involves the use of the n-SIMPLY operation to compute the equivalent logic function resulting from a sequence of more than one 1-bit HAs. Thereby, the equivalent carry-out of a sequence of more than 1 HA (output C in Figure 10a), can be computed in a single step by exploiting the n-SIMPLY operation (with n = #HAs + 2). For instance, the carry-out can be computed with a 4-SIMPLY or a 5-SIMPLY when a sequence of 2 or 3 HAs is considered, respectively. Moreover, the number of intermediate computing steps required to calculate the output bits \(S_{i}\) (see Figure 10a) is reduced using the n-SIMPLY, as shown in Figure 10b and Supplementary Figure S2-S4, where the sequence of operations computing the result of a sequence of 2, 3, and 4 HAs are reported. Specifically, 19 (see Figure 10c), 28 (see Supplementary Figure S3), and 37 computing steps (see Supplementary Figure S4), for a sequence of 2, 3, and 4 HAs, respectively, are required instead of 26, 39, and 52 steps when using only the 2-SIMPLY. The overall number of computing steps scales rapidly with the number of output bits, but the use of n-SIMPLY with n up to 3 (i.e., only the chain of 2 HAs is optimized) provides a saving of around 15% of steps while for n > 3 leads to a step saving above 25%. However, most of the reduction in the number of computing steps is achieved when using n-SIMPLY with n up to 4 while the use of n > 4 provides only a limited improvement, as shown in Figure 10d, that does not justify the risk of reducing the reliability of the circuit due to the smaller available RMs.