# High Linearity DC-38 GHz CMOS SPDT Switch
## 2 Circuit Design  
Figure 2 shows the circuit diagram and chip microphotograph of the SPDT switch. The SPDT switch occupies a chip area of 0.619 \(\times\) 0.633 mm\({}^{2}\), i.e., 0.392 mm\({}^{2}\). The SPDT switch is design and implemented by a 1P6M 0.18 \(\upmu\)m CMOS process with top metal (M\({}_{6}\)) thickness of 2.34 \(\upmu\)m. The interconnection lines and inductors are mainly implemented by M\({}_{6}\). Only the underneath interconnection lines are implemented by the fifth-layer metal (M\({}_{5}\)). Traveling-wave (CLCL) matching is used for isolation and output-port (ports 2 and 3) matching enhancement. \(\pi\) (CLC)-matching is used for the input-port (port 1) matching. Positive/negative gate-bias is used for linearity enhancement because larger input power P\({}_{\text{in}}\) (i.e., AC signal with larger negative input voltage V\({}_{\text{in}}\)) is required to conduct the off-state series switch transistor. Negative-body bias is adopted for insertion-loss reduction mainly due to the off-state series switch transistor being closer to an open-state. Figure 3a-c shows the simulated scattering parameters (S-parameters) versus frequency characteristics of the SPDT switch in the condition of P1-to-P2 being on and P1-to-P3 being off. The bias conditions are V\({}_{\text{DD}}\)/V\({}_{\text{SS}}\) = 1.8 V / \(-\)1.8 V and V\({}_{\text{DD}}\)/V\({}_{\text{SS}}\) = 2.5 V / \(-\)2.5 V. Figure 3a shows the simulated input reflection coefficient at port-1 (S\({}_{11}\)) and port-2 (S\({}_{22}\)). At V\({}_{\text{DD}}\)/V\({}_{\text{SS}}\) of 2.5 V / \(-\)2.5 V, the SPDT switch achieves minimum S\({}_{11}\) of \(-\)29.2 dB at DC, \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & **Frequency (GHz)** & **Insertion Loss (dB)** & **Isolation (dB)** & **IP\({}_{\text{abs}}\) (dBm)** & **CMOS Process** \\ \hline \multirow{4}{*}{This Work} & 0–6 & 0.4–1.4 & 37.5–59.4 & NA & \\  & 21–29 & 3.6–4.3 & 25.7–28.7 & 25.6 (028 GHz) & 0.18 \(\upmu\)m \\  & 31–38 & 4.5–5.9 & 24.3–25.2 & NA & \\  & 35–70 & 2.2–2.9 & \(\gtrsim\)40 & 17.3 (045 GHz) & 0.1 \(\upmu\)m PHEMT \\  & 0–20 & 0.4–1 & 20–42.7 & 15 (010 GHz) & 0.18 \(\upmu\)m SOI \\  & 20–40 & 1–5 & 17–20 & NA & 0.18 \(\upmu\)m SOI \\  & 24 & 3.5 & 16 & 28.7 & 90 nm \\  & 15–25 & 0.6–2 & 15–31.5 & 22.1 \(\upmu\)m (20 GHz) & 28 nm \\  & 5 & 2 & 42.7 & 21 & 0.18 \(\upmu\)m \\  & 0–10 & 0.4–1.8 & 23–42 & 20 (05.8 GHz) & 0.18 \(\upmu\)m \\ \hline \hline \end{tabular} \({}^{\star}\) Simulation. \({}^{\star}\) 0.3 dB compression point.  
\end{table} 
Table 1: Summary of this work and recently reported SPDT switches. Figure 2: Circuit diagram and chip photo of the DC-38 GHz SPDT switch. and S\({}_{11}\) smaller than \(-\)10 dB for 0-34.1 GHz, corresponding to \(-\)10 dB input matching bandwidth (f\({}_{10 dB}\)) of 34.1 GHz. The result is close to the simulated one (f\({}_{10 dB}\) of 33.8 GHz (0-33.8 GHz)) for V\({}_{\rm DD}\)/V\({}_{\rm SS}\) of 1.8 V /\(-\)1.8 V. Moreover, at V\({}_{\rm DD}\)/V\({}_{\rm SS}\) of 2.5 V /\(-\)2.5 V, the SPDT switch achieves minimum S\({}_{22}\) of \(-\)29.3 dB at DC, and S\({}_{22}\) smaller than \(-\)10 dB for 0-39.9 GHz, corresponding to f\({}_{10 dB}\) of 39.9 GHz. The result is close to the simulated one (f\({}_{10 dB}\) of 40.5 GHz (0-40.5 GHz)) for V\({}_{\rm DD}\)/V\({}_{\rm SS}\) of 1.8 V /\(-\)1.8 V.  
Figure 3b shows the simulated S\({}_{21}\) and S\({}_{31}\). The magnitude of S\({}_{21}\) is the insertion loss between port 1 and port 2. For V\({}_{\rm DD}\)/V\({}_{\rm SS}\) of 2.5 V /\(-\)2.5 V, the SPDT switch achieves S\({}_{21}\) lower than 2.4 dB for 0-28 GHz and 5.6 dB for 0-38 GHz. The result is slightly better than the simulated one (insertion loss lower than 2.6 dB for 0-28 GHz and 5.9 dB for 0-38 GHz) for V\({}_{\rm DD}\)/V\({}_{\rm SS}\) of 1.8 V /\(-\)1.8 V because transistors M\({}_{1}\) and M\({}_{2}\)/M\({}_{3}\) are closer to being short and open, respectively. Moreover, the magnitude of S\({}_{31}\) is the isolation between port 1 and port 3.