# Effective Implementation of Edge-Preserving Filtering on CPU Microarchitectures
## 7 Experimental Results
### Effective Implementation on CPU Microarchitectures  
In this subsection, we verify the effective vectorization of the bilateral filter and the non-local means filter on the latest CPU microarchitectures. The proposed methods for denormalized numbers have already been applied to these filters. Figures 12 and 13 show the computational times of the bilateral filter and the non-local means filter for each CPU microarchitecture. These filters were implemented using float. Notably, in the RqLSL/RqL and MqL implementation, sqrt was used as the quantization function and \(n=1\). The RqLSL/RqL implementation is the fastest in these CPU microarchitectures. This implementation has a lower computational cost than the MC/RC implementation. Moreover, the number of LUT accesses is lower than that in the case of the RLSL/RL implementation. The computational time of the MC/RC implementation is almost the same as that of the RLSL/RL and RqLSL/RqL implementation or faster than that of the RLSL/RL implementation. This tendency can be stronger in the latest CPU microarchitectures because computational time is limited by the memory reading/writing latency. Besides, the computation time of the RqLSL implementation is almost the same as that of the MqL implementation, but that of the RqLSL implementation is slightly faster than that of the MqL implementation. The size of the merged quantization LUT is larger than that of the range quantization LUT. The effects of the size of the quantization LUT and the quantization function are discussed in the following paragraph. The RLSL/RL, RqLSL/RqL and MqL implementations in which the _gather_ instruction is employed are faster than the implementations in which the _set_ instruction is employed. However, on the Intel Core i7 5960X and AMD Ryzen Threadripper 1920X CPUs, the implementations in which the _gather_ instruction is used are slower than the implementations in which the _set_ instruction is used. In the bilateral filter and the non-local means filter, when the SIMD's vector length increases, all types of implementations with longer SIMD instructions are faster than that with shorter SIMD instructions. Furthermore, in a comparison of the implementations with/without FMA3, the FMA3 instruction improved computational performance slightly. These results indicate that effective vectorization of the bilateral filter and the non-local means filter are different for each CPU microarchitecture. Figures 14 and 15 show the speedup ratio of the bilateral filter and the non-local means filter for each CPU microarchitecture. If the ratio exceeds one, the corresponding implementation is faster than the scalar implementation for each CPU microarchitecture. Multi-core threading parallelized both the scalar and the vectorized implementations for focusing on comparing vectorized performance. In the case of the bilateral filter, the fastest implementation is 170-times faster than the scalar one. Moreover, in the case of the non-local means filter, the fastest implementation is 200-times faster than the scalar one. The speedup was determined by the management of denormalized numbers and effective vectorization. Thus, the effect of using a multi-core CPU is not evaluated in the verification. Figure 12: Computational time of the bilateral filter in various CPU microarchitectures: (**a**) SSE; (**b**) AVX/AVX2; (**c**) AVX/AVX2 with FMA3; (**d**) AVX512; (**e**) AVX512 with FMA3. \(\sigma_{\tau}=4\), \(\sigma_{s}=6\) and \(r=3\sigma_{s}\). Image size is \(768\times 512\). Figure 13: Computational time of non-local means filter in various CPU microarchitectures: (**a**) SSE; (**b**) AVX/AVX2; (**c**) AVX/AVX2 with FMA3; (**d**) AVX512; (**e**) AVX512 with FMA3. \(h=4\sqrt{2}\); template window size is \((3,3)\); and search window size is \((37,37)\). Image size is \(768\times 512\). Figure 14: Speedup ratio of bilateral filter in various CPU microarchitectures: (**a**) SSE; (**b**) AVX/AVX2; (**c**) AVX/AVX2 with FMA3; (**d**) AVX512; (**e**) AVX512 with FMA3.