# An FPGA-Based Performance Analysis of Hardware Caching Techniques for Blockchain Key-Value Database
## 3 Implemented Caching System  
Cache memory is more expensive but it is faster than the main memory. This paper explored three different caching systems for Blockchain applications and implemented them on the FPGA NIC. These include the traditionally used direct-mapped cache, 2-way set-associative cache, and 4-way set-associative cache. The set-associative cache system increases the cache complexity compared with the direct-mapped caching; however, it reduces the conflict miss and increases throughput. Table 3 shows a summary of proposed cache characteristics. In this paper, we implemented direct-mapped, 2-way, and 4-way set-associative cache techniques on BRAM and examined their performance by calculating the cache misses versus cache hits. The capacity of BRAM is 11,664 Kb. The memory capacity of BRAM is less than that of RLDRAM; however, the processing speed of BRAM is faster than that of RLDRAM. Therefore, BRAM can accelerate work further as an intermediate cache system. \begin{table}
\begin{tabular}{c c} \hline \hline
**Key Idea** & **Results Obtained** \\ \hline Throughput improvement of Blockchain & Throughput improved by 6.04 times \\ operations [18] & Latency reduced by 15.4 times \\ \hline FPGA NIC for Caching in Blockchain [20] & FPGA NIC of 10 GB used \\  & FPGA cache hits improvement by 13\% \\ \hline  & Improved scalability \\ FPGA-based caching for Blockchain [28] & Improved throughput \\  & Reduced area utilization \\  & Reduced power consumption \\ \hline FPGA-based caching for Blockchain [20] & Throughput improved by 1.97 times \\  & Decreased power consumption by 18.5 W \\ \hline Improved Blockchain full node search & Higher throughput than CPU-based search \\   using GPUs [30] & Higher throughput than other GPU-based searches \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Summary of recent state-of-the-art Blockchain implementations to accelerate Blockchain. Figure 1: Hardware cache system for a cache hit and cache miss. BRAM will act as a first-level cache and RLDRAM will act as a second-level cache in Blockchain systems. The controller will search first in the level one cache: if it hits, it will reply; otherwise, it will go to the next level. The frequently used data will save in the level one cache. Figure 2 shows the hardware implementation of the implemented caching system on FPGA NIC for Blockchain. FPGA NIC has three states to manage the KVS system. These include packet forwarding, access onboard BRAM, and key extraction. * Key extraction: The User Datagram Protocol (UDP) packets have requested addresses with pre-specified destination port numbers. From these requesting packets, the FPGA NIC extracts the payload. Figure 3 shows the format of requesting packets. The requesting packet consists of a header and payload. The requesting packet's length is 74 bytes with which the length of the header is 42 bytes and the length of Transaction ID (TXID) is 32 bytes. The Advanced Extensible Interface (AXI) bus width is 32 bytes; so, FPGA needs 3 cycles to extract the payload from a 74-byte packet. * Access Onboard DRAM: The single cache line is 512 bits and includes \"Tag\", \"Index\", and \"Value\". The value is 256 bits Merkle Root, whereas the lower 12 bits of the payload are \"Index\" and the upper 244 bits of payload are \"Tag\". Valid registers are used corresponding to every index, which shows valid flags to check whether the cache hit or missed. The BRAM controller accesses onboard BRAM upon receiving a requesting packet and finds if it is a hit or a miss. When the server saves data in the cache line, it enables the valid flag. The BRAM controller judges cache hits when the tag value saved in the cache is equal to the 244-bit value generated from the requesting packet. On the other hand, it