# Speed Optimization in DEVS-Based Simulations: A Memoization Approach
###### Abstract
Our goal is to develop a co-simulation system that performs expensive functions in the RTL-DEVS environment that are relatively easy to develop, without requiring the use of commercial RTL design tools or the development of additional branches of open-source simulators. Therefore, even for incompatible features, it must be ensured that the results of simulation in DEVS space are equivalent to the results of simulation in the Verilog simulator. It requires a stepping stone to provide compatibility between Verilog and DEVS. It has \begin{table}
\begin{tabular}{c c c} \hline
**Compatibility** & **Function** & **Description** \\ \hline \multirow{4}{*}{Functionally Compatible} & Event-based behavior & DEVS: Discrete event-based. \\  & & Verilog: Response to digital signals. \\  & & Modulization & Support modularized structure. \\  & & State-based behavior & Operates around transitions between states. \\  & & Time-driven & Delay; timer; event scheduling for system behavior modeling. \\ \hline \multirow{4}{*}{Functionally Incompatible} & Language structure & DEVS: Set theoretical formalism. \\  & & Verilog: Programming language style syntax. \\ \cline{1-1}  & & DEVS: Complex event scheduling and processing mechanisms. \\ \cline{1-1}  & & Verilog: Operates according to signal changes. \\ \hline \end{tabular}
\end{table} 
Table 1: Compatible and incompatible features of DEVS and Verilog. been verified through various research and joint development projects that the Verilog description can be transmitted to other tools or FPGA tools through XML [19; 20], and that the biggest problem, the difference in language structure, was resolved through the direct development of an XML-based Verilog parser. However, the DEVS simulation engine's scheduling mechanism is more complex than Verilog's, and a serious level of overhead occurs depending on the node depth of the layered modules. Recently released high-performance semiconductor chips have already become complex in structure, containing anywhere from billions of transistors to over 10 billion depending on their purpose. To design and verify such complex chips, a vast amount of logic and modules are required, and the code complexity of Verilog has also increased. Due to the module complexity of the RTL design stage, numerous atomic models and coupled models are used when performing an HDL simulation with a DEVS-based simulation engine. The entire model is designed hierarchically, so one module (coupled model) contains another coupled model, and this is repeated recursively. When performing a simulation based on an existing simulator or scheduling algorithm, the time for simulation increases exponentially depending on the complexity of the model. In other research, the issue that hierarchical simulations generate significant overhead depending on their depth was already raised, and performance improvements of up to seven times were obtained by using event lists and flattening [21; 22]. Extracting recurring patterns from systems that use event-based state transition models can have a significant impact on performance improvements [23]. However, for an HDL simulation, the extended RTL-DEVS model uses two buffers to process RHS and LHS separately, and the wire model that connects logic also has one buffer. In this process, an event with a lifetime of 0, which is a scenario called zero-time transition, occurs repeatedly to ensure signal transmission without delay. As a result, a bottleneck occurred in the process of searching for the node that should perform the next event. The challenge is to improve simulation speed while maintaining the hierarchical structure of the model. The memoization method, which caches the results of a function call and allows for a quick response to the same input, is a very classic technique. Nevertheless, due to the high efficiency of the idea, it continues to be actively discussed in the overall hardware/software field [24].