## 3 Future CONERSTONE Platforms
### Electronic-Photonic Integration
#### 3.4.1 Codesign of CMOS Driver and Si Modulator for Si Photonics Transmitters  
In our previous work [150], we have presented an example where a carrier depletion based optical modulator is designed in a U-shape MZM configuration allowing access to both the input and termination pads of the MZM on one side of the chip. This allows both ends of the modulator to be electrically connected to the CMOS driver with short bonds. By terminating the travelling wave electrode on the CMOS chip (resistor R1 in Figure 17a), further control and dynamic tuning of the termination impedance is possible allowing fine tuning of the performance. The results shown in [150] were performance-limited by the parasitic effects of the bonding wires that coupled the CMOS driver and Si modulator. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Device** & **Wavelength (\(\upmu\)m)** & **Parameter** & **Value** \\ \hline straight waveguide & 3.8 & propagation loss & 0.82 dB/cm \\ S-bend & 3.8 & propagation loss & 0.01 dB/bend \\
90\({}^{\circ}\) bends & 3.8 & propagation loss & 0.02 dB/bend \\
2 \(\times\) 2 MMI & 3.8 & insertion loss & \textless{}0.3 dB \\
2 \(\times\) 2 MMI & 3.8 & imbalance & \textless{}0.3 dB \\ straight waveguide \({}^{\ast}\) & 7.7 & propagation loss & 3.1 dB/cm \\ S-bend \({}^{\ast}\) & 7.7 & propagation loss & 0.06 dB/bend \\
90\({}^{\circ}\) bends\({}^{\ast}\) & 7.7 & propagation loss & 0.08 dB/bend \\ \hline \hline \end{tabular} \({}^{\ast}\) Devices operating at \(\lambda\) = 7.7 \(\upmu\)m using thick SOI will not be part of the standard CORNERSTONE MPW calls.  
\end{table} 
Table 6: Experimental performance of suspended Si photonic components, which will be available in the CORNERSTONE PDK. More recently, we developed a comprehensive flip-chip bonding process that is compatible with the SOI based CORNERSTONE platforms and will be offered as a standard CORNERSTONE process alongside the MPW calls. CORNERSTONE users will be responsible for the design and sourcing of the electronics chips, which can then be bonded to CORNERSTONE SOI photonics chips. Compatibility of the bonding processes with the new platforms described above (Sections 3.1-3.3) will be confirmed in due course. As shown in Figure 17b, the CMOS driver has been flip-chip bonded onto a 2.47 mm long U-shape carrier depletion modulator, using a modified CORNERSTONE PDK modulator. Measurement results show that the integrated transmitter can operate at 40 Gb/s with an extinction ratio of \(>\)3.6 dB (Figure 17c). Based on the 3-tap feed forward equalization (FFE), 64 Gb/s optical eye diagrams can be observed with extinction ratios of \(>\)6 dB (Figure 17d). 4.2 Codesign of Differential Transimpedance Amplifier and Balanced Photodetector for Si Photonics Receivers  
In this work [151], we present the design and characterization of an optical receiver that is composed of a 28 nm CMOS transimpedance amplifier (TIA) and a balanced Si-Ge photodetector (PD). The electrical and optical units were codesigned and packaged, providing fully differential output signals (Figure 18a). The TIA circuit operates with the standard CMOS supply (1.0V). Without using any equalization or digital signal processing (DSP) techniques, the receiver can operate up to 54 Gb/s non-return-to-zero (NRZ) with a bit error rate (BER) of less than the KP4 limit (\(2.2\times 10^{-4}\)) with an optical modulation amplitude (OMA) of \(-\)8.6 dBm, whilst the power efficiency was 0.55 pJ/bit (or 0.98 pJ/bit including the output buffer), as shown in Figure 18c. Besides the carefully design and modeling of the optoelectronic circuit, the device packaging process plays a dominant role in enabling the receiver's performance. Figure 17: The integrated Si photonics transmitter. (**a**) Circuit diagram of the Si MZM integrated with the complementary metal oxide semiconductor (CMOS) driver, (**b**) microscope image of the integrated Si photonics transmitter, (**c**) measured optical results at 40 Gb/s and (**d**) measured optical results at 64 Gb/s with 3-tap feed forward equalization (FFE).