# A Hardware-Efficient Vector Quantizer Based on Self-Organizing Map for High-Speed Image Compression
## 4 Experimental Results and Discussion  
### Hardware Implementation  
The hardware of our proposed vector quantizer has been described by Verilog HDL(verilog hardware description language) and implemented on FPGA. Table 1 summarizes the hardware resource usages of the proposed vector quantizer. Similar to the previous hardware implementations, the learning rate \(\alpha\) in our design is set as a constant value to simplify the control circuits. In addition, considering the trade-off between the memory resource usage and the visual quality degeneration, we define the codebook size as 256. To improve the processing speed, we set the number of sub-block as 32. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Resources** & **Used** & **Available** & **Utilization** \\ \hline Combinational ALUTs & 74,368 & 182,400 & 40\% \\ Memory ALUTs & 0 & 91,200 & 0\% \\ Total registers & 62,784 & N/A & N/A \\ Total block memory & 36,864 & 14,625,792 & \textless{}1\% \\
\begin{tabular}{c} DSP block 18-bit \\ elements \\ \end{tabular} & 0 & 1288 & 0\% \\ Total PLLs & 1 & 8 & 12.5\% \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Hardware resource usages of the proposed vector quantizer. Figure 4: Block diagram of the winner-takes-all circuit. Under such conditions, the synthesis results indicate that the obtained maximum clock frequency is 79.8 MHz. Furthermore, to verify our design, an image compression system based on the proposed vector quantizer is developed for high-speed target tracking application and exhibited in Figure 5. As shown in Figure 5, the demonstration system is composed of a high-speed image sensor, a FPGA development board, a display, and a PC. The camera link connector and DVI (digital visual interface) transmitter connector are inserted into the FPGA board for image capture and display. We have conducted several experiments to intuitively evaluate the compression performance of our proposed vector quantizer. To make the experimental results comparable, three standard grayscale 512 \(\times\) 512-pixel images from the USC-SIPI (University of Southern California-Signal and Image Processing Institute) image database, respectively--Lena, Peppers, and Tank--were adopted as the test data. As mentioned before, the codebook size is set as 256, and the number of multi-parallel processing sub-blocks is set as 32. In this way, the 256 weight vectors are equally distributed into 32 blocks, and thus the processing speed is greatly improved. During the codebook generation phase, the pixel values of Lena are utilized as the training data. Once the phase of codebook generation is completed, Lena, Peppers, and Tank are encoded by the trained codebook in sequence. Moreover, several sizes of pixel-block including 4 \(\times\) 4, 4 \(\times\) 8, 8 \(\times\) 8, 8 \(\times\) 16, and 16 \(\times\) 16 are employed to judge the visual quality of the reconstructed images with different compression ratio. Figure 6 shows the visual quality comparisons between the compressed images with various compression ratios. It can be seen that the compressed images are able to keep relatively acceptable visual quality even if the pixel-block of 8 \(\times\) 8 is employed (the corresponding compression ratio is 64). Finally, the visual qualities of the compressed images with different compression ratios are quantified by the metric of peak signal-to-noise ratio (PSNR) and plotted in Figure 7. Figure 7 indicates that the PSNR of Lena in our work is about 30.69 dB as the compression ratio keeps to 16, which is slightly worse than that in [11]. That may stem from the truncation error in the fixed-point calculation when different types of word-precision are adopted. Finally, benefiting from the mechanism of PVCS, we can adjust the compression ratio by changing the value of \(m\), which has been discussed in Section 3.2. Figure 5: A prototype of the image compression system based on the proposed vector quantizer. FPGA: field programmable gate array; LCD: liquid-crystal display; DVI: digital visual interface.