# Research Progress on Modulation Format Recognition Technology for Visible Light Communication
## 4 Deep Learning-Based Modulation Recognition Methods
### Prospects for the Practical Hardware Deployment of VLC MFR  
During the evolution of VLC technology towards practical applications, the hardware implementation of MFR technology is still in the exploratory stage. We believe this situation is primarily due to two issues: First, VLC technology has not yet formed a large-scale commercial application. Research on its hardware implementation has mostly focused on innovations in modulation schemes and the optimization of basic links, while the hardware deployment of advanced algorithms like modulation recognition has not yet attracted widespread attention. Second, the unique optoelectronic hybrid architecture and dynamic channel characteristics of VLC systems pose special requirements for hardware implementation: it needs to meet the demands of real-time signal processing while also achieving low-power design on resource-constrained mobile terminal platforms. Existing VLC hardware systems have shown a trend towards modular development. The transmitter typically adopts an integrated design of LED arrays and driving circuits, while the receiver uses a photodetector in conjunction with an analog front-end (AFE) to achieve optoelectronic conversion. Digital baseband processing is mostly accomplished using field-programmablegate arrays (FPGA) or ARM architecture processors. Such architectures, while supporting traditional modulation formats like OOK [43; 44] and PPM [45; 46], are gradually expanding to higher-order schemes such as OFDM [47], PAM4 [48], and QPSK [49]. The hardware implementation experience of MFR technology in the RF communication field provides important references for VLC systems. In RF scenarios, deep learning-based modulation recognition has been realized through the deployment of quantized convolutional neural networks (QMCNet) and residual networks (RUNet) on FPGAs. For example, the RUNet (6,6,6)p model with 6 bit quantized weights and iterative pruning technology achieves a classification accuracy of 94.46% and a throughput of 527 K classifications per second on the Xilinx ZCU111 FPGA platform [50]. The ternary weight quantization technique in [51], which restricts neural network parameters to {-1, 0, +1} at inference, combined with the MobileNetV3 architecture, achieves an average recognition accuracy of 90.1% on an ASIC. The authors reduced the number of multiply and accumulate (MAC) operations using a common subexpression elimination algorithm. However, the essential differences between VLC and RF systems lead to some distinctions in hardware implementation paths: the light-intensity fluctuation characteristics of VLC channels require the hardware front-end to have a stronger dynamic range adaptation capability, while the nonlinear response characteristics of LEDs necessitate the design of more complex digital predistortion techniques and feedback compensation mechanisms. Deploying VLC-MFR technology faces multiple challenges. The primary difficulty lies in the contradiction between hardware resource constraints and algorithm complexity. FPGAs have a limited number of logic units (LUTs) and digital signal processing (DSP) modules, while deep neural networks required for high-order MFR may consume more hardware resources. Although the RUNet (6,6,6)p model [50] reduces storage requirements through weight pruning, additional hardware resources are still needed in VLC scenarios to handle channel estimation and equalization operations. The requirement for real-time performance constitutes the second challenge. Existing FPGA-based MFR implementations can achieve a classification latency of 7.5 \(\upmu\)s under a 30 dB SNR [50], but they have not fully considered the need for resynchronization caused by sudden light changes in VLC applications. Anti-interference capability is the third major bottleneck.