# A Model-Based Engineering Approach for Evaluating Software-Defined Radio Architecture
## 3 Analytical Models
### Thermal Analysis  
Heat can be generated due to signal processing and can build up inside the SDR-MM. Some failures due to elevated temperatures or overheating could be loss of electronic function of components due to thermal fracture of mechanical support, internal connection failure, or failure in semiconductor materials [28]. Therefore, the thermal management model was developed to predict the AEST inside the SDR-MM. Integrating the thermal model with the system model provides bi-directional connectivity and higher levels of thermal performance to better inform the design decision for optimizing system architecture that meets the stakeholder needs and design constraints. The power dissipation from the SDR-MM is used in the thermal management model to ensure the system operates below the specified maximum temperature. Correlating the signal output band to the power dissipation establishes a causal relationship between signal processing and thermal management. First, the total power dissipation (\(PD\)) is approximated using Equation (3). \[PD=N_{NB}\times PD_{NB}+N_{WB}\times PD_{WB}+N_{FPGA}\times(PD_{FPGA}+PD_{bas-FPGA })+PD_{eth-elem} \tag{3}\]  
where \(N_{NB}\) and \(N_{WB}\) represent the number of NB and WB output channels, respectively. \(N_{FPGA}\), \(PD_{FPGA}\), and \(PD_{bas-FPGA}\) represent the number of FPGAs, the power dissipation per FPGA, and the base power dissipation per FPGA, respectively. The \(PD_{bas-FPGA}\) is assumed to be 10 W and depicts the case of FPGA operating without a load. The power dissipation of all non-FPGA related SDR-MM elements (\(PD_{eth-elem}\)) is assumed to be 40 W when they are in the ON state. The PD values are estimated based on inputs from the SDR and FPGA subject matter experts (SMEs). Figure 4a depicts the power dissipation of SDR-MM elements for a single FPGA configuration. A thermal resistance method [29] was used in developing the thermal management model with the following assumptions: (1) steady-state conditions, (2) constant thermal conductivity of the enclosure subsystem material, and (3) only conduction and convection heat transfer. The main purpose of this model is to predict AEST under given design variables and operational air conditions. The inputs to this model are the design variables for the enclosure (enclosure dimensions and material thermal conductivity), the heat generated (or power dissipation) by the signal processor, and the air characteristics of the CEAE. Figure 5 shows a schematic of both thermal management models. Figure 5a depicts a thermal model where the heat generated by the internal SDR-MM electronic components is conducted through the Enclosure and then dissipated to the CEAE through a free convection heat transfer. First, the thermal resistances for conduction and convection heat transfer are calculated using Equations (4) and (5), then the total resistance is calculated by Equation (6). Figure 4: (**a**) The model shows the power dissipation from a single FPGA along with the power dissipation from the remaining other SDR-MM elements. (**b**) The Average Electronic Surface Temperature (AEST) versus power dissipation for each architecture. The thermal resistances of a PCB and a thermal interface material are estimated and added to depict an actual system configuration. Finally, the total power dissipation from all SDR-MM elements, the total calculated resistance, and the air characteristics inside the CEAE are used in Equation (7) to calculate the AEST. \[R_{t,enc}=t/k\times A \tag{4}\]  
\[R_{t,conv}=1/h_{c}\times A \tag{5}\]  
\[R_{total}=R_{t,PCB}+R_{t,TIM}+R_{t,enc}+R_{t,con} \tag{6}\]  
\[T_{AES}=T_{a}+PD\times R_{total} \tag{7}\]  
where \(R_{t,enc}\) is the conduction thermal resistance of the enclosure in K/W, while \(R_{t,con}\) is the convection thermal resistance in K/W.