# Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division
## 1 Introduction  
Modern applications comprise several floating-point (FP) operations including FP addition, multiplication, and division. In recent FP units, emphasis has been placed on designing ever-faster adders and multipliers, with division receiving less attention. Typically, the range for FP addition latency is two to four cycles, and the range for FP multiplication is two to eight cycles [1]. In contrast, the latency for double precision division in modern floating point units ranges from less than eight cycles to over 60 cycles [2]. Literature exists describing division algorithms, of which digit recurrence, functional iteration, variable latency, very high radix, and look-up table are five typical division implementations [3]. Digit-recurrence algorithm is based on iterative subtraction, including restoring [4], non-restoring [5], and Sweeney-Robertson-Tocher (radix-n SRT) algorithm (SRT is in fact one of non-restoring algorithms) [6]. It works digit by-digit with an iterative-type subtraction and produces a quotient in sequence [7]. According to [8], digit-recurrence algorithm of low radix is likely to cause long latency when encountering high-precision calculation due to its linear convergence speed. In contrast, high-radix digit-recurrence algorithm can reduce latency at the expense of multifold area consumption. Functional iteration algorithm is mainly comprised of Newton-Raphson [9; 10], Goldschmidt [11; 12], Series expansion [13], and Taylor series algorithm [14; 15]. A functional iteration divider computes the quotient of division by prediction; thus, based on multiplication instead of subtraction, it can give more than one digit of the quotient in oneiteration, which ultimately reduces the iterations greatly [8; 9; 12]. According to [8], since they have square convergence, the faster convergence speed brings low delay. However, higher hardware requirements are put forwards at the same time. The Digital Equipment Corporation (DEC) Alpha 21164 [16] is one of the best examples of variable latency class algorithm implementation. It is found in [17] that the average number of quotient bits retired in one iteration varies from 2 to 3 depending on the stream of bits in the partial remainder. There are certain ways in [17] to provide a variable conversion time in variable latency algorithm: self-timing, result cache, and speculation of quotient digit. Generally, a divider retiring more than 10 quotient digits in one iteration qualifies as a very high-radix algorithm [2; 18; 19]. As with low-radix SRT algorithm, a very high-radix algorithm also uses a look-up table. In [20], the main difference between SRT and very high-radix algorithm is that it has a more complex divisor multiple processing and quotient-digit selection hardware, which increases the cycle time and area. A look-up table algorithm [21; 22; 23; 24; 25] can be used along with digit recurrence, functional iterative, and very high-radix algorithms. Take SRT radix-n division algorithm, the approximation can be achieved by a look-up table that can provide a faster option at the expense of an increased area [26; 27]. Additionally, the look-up table area also increases as the number of bits increases. Our research focuses on the architecture design of configurable precision FP arithmetic units. Several papers have proposed FP architectures on the idea of multi-precision FP arithmetic processing. Most prior works are focused on the adder architectures [28; 29; 30; 31; 32] and multiplier architectures [33; 34; 35; 36]. This paper focuses on the design of configurable multi-precision FP divider. The proposed architecture is based on very high-radix algorithm [18], which can work out much more than 10-bit quotient in one clock cycle. The proposed architecture is designed for normal as well as subnormal computational support, which also includes the exceptional case handling and processing. The major building blocks (like PRECONFIG, MANTISSA_DIVIDE, and NORMALIZE) are designed and optimized for the low-latency and bit-accurate purpose.