# Single EX-CCCII-Based First-Order Versatile Active Filter
## 2 Circuit Description  
### Ex-Cccii  
Figure 1a shows the symbolic representation of the EX-CCCII, and Figure 1b shows the equivalent circuit. From Figure 1b, it can be seen that this EX-CCCII has two intrinsic resistances, \(R_{x1}\) and \(R_{x2}\), on terminals x\({}_{1}\) and x\({}_{2}\), respectively. The characteristics of the EX-CCCII ports in Figure 1 are given by  
\[\begin{pmatrix}I_{y}\\ V_{x1}\\ V_{x2}\\ I_{z1}\\ I_{z2}\end{pmatrix}=\begin{pmatrix}0&0&0&0&0\\ 1&R_{x1}&0&0&0\\ 1&0&R_{x2}&0&0\\ 0&\pm 1&0&0&0\\ 0&0&\pm 1&0&0\end{pmatrix}\begin{pmatrix}V_{y}\\ I_{x1}\\ I_{x2}\\ V_{z1}\\ V_{z2}\end{pmatrix} \tag{1}\]  
The plus (+) and minus (-) signs here mean that the EX-CCCII can provide plus and minus z-terminals in a single device.  
Figure 2 shows the structure of the CMOS EX-CCCII [50]. The transistors M\({}_{1}\)-M\({}_{6}\) are connected in the so-called translinear loop configuration [51], while transistors M\({}_{\rm b}\), M\({}_{7}\), M\({}_{8}\), M\({}_{19}\), M\({}_{20}\), and the biasing current I\({}_{\rm set}\) provide the bias current required for the circuit. Assuming that the NMOS (M\({}_{1}\)-M\({}_{3}\)) and PMOS (M\({}_{4}\)-M\({}_{6}\)) transistors are matched (i.e., \(V_{\rm GS1}=V_{\rm GS2}=V_{\rm GS3}\) and \(V_{\rm GS4}=V_{\rm GS5}=V_{\rm GS6}\)), and the transistors M\({}_{\rm b}\), M\({}_{5}\), M\({}_{6}\), M\({}_{17}\), and M\({}_{18}\) are identical, the relationship \(V_{y}=V_{x1}=V_{x2}\) can be obtained and the intrinsic resistances at the x\({}_{1}\)- and x\({}_{2}\)-terminals (\(R_{x1}\) and \(R_{x2}\)), assuming operation in strong inversion, can be determined by [50]  
\[R_{x1}=R_{x2}=\frac{1}{\sqrt{2I_{set}C_{ox}}\bigg{(}\sqrt{\mu_{p}\left(\frac{ W}{L}\right)_{p}}+\sqrt{\mu_{n}\left(\frac{W}{L}\right)_{n}}\bigg{)}} \tag{2}\]  
where \(I_{set}\) is the biasing current, \(C_{ox}\) is the oxide capacitance per unit area, \(\mu_{n}\) and \(\mu_{p}\) are the mobilities of the electrons and holes, respectively, and \((W/L)_{n}\) and \((W/L)_{p}\) are the channel width and length ratios of the NMOS and PMOS transistors, respectively. \(R_{x1}\) and \(R_{x2}\) can be controlled by the setting current \(I_{set}\).  
At the output, the circuit consists of current mirrors. Transistors M\({}_{7}\), M\({}_{8}\), M\({}_{19}\), and M\({}_{20}\) are used to mirror the current from the x\({}_{1}\)- to z\({}_{1+}\)-terminals, and transistors M\({}_{7}\), M\({}_{9}\)-M\({}_{11}\), M\({}_{19}\), and M\({}_{21}\)-M\({}_{23}\) are used to mirror the current from the x\({}_{1}\)- to z\({}_{1-}\)-terminals. The multiple z\({}_{1+}\)- and z\({}_{1-}\)-terminals can be obtained using complementary current mirrors. Here, transistors M\({}_{12}\), M\({}_{13}\), M\({}_{24}\), and M\({}_{25}\) are used to mirror the current from the x\({}_{2}\)- to  
Figure 1: EX-CCCII: (**a**) symbol, (**b**) equivalent circuit.  
\(z_{2+}\)-terminals, and transistors M\({}_{12}\), M\({}_{14}\)-M\({}_{16}\), M\({}_{24}\), and M\({}_{26}\)-M\({}_{28}\) are used to mirror the current from the x\({}_{2}\)- to z\({}_{2-}\)-terminals. Similarly, complementary current mirrors can be used to obtain multiple z\({}_{2+}\)- and z\({}_{2-}\)-terminals. Thus, the relations of \(I_{x1}=I_{z1+}=-I_{z1-}\) and \(I_{x2}=I_{z2+}=-I_{z2-}\) of the EX-CCCII can be obtained.