# DFT-Low-Latency Bit-Slice Design of Discrete Fourier Transform
## 1 Introduction  
The adoption of the discrete Fourier transform (DFT) is widespread in digital-signal-processing systems. The DFT maps the time-domain sequence to the frequency-domain sequence of the same length, with a computational cost proportional to \(N^{2}\) for a DFT of length \(N\). The fast Fourier transform (FFT) algorithm is generally used to effectively perform the DFT so as to partition the whole procedure into smaller procedures [1]. The field of applications of FFT is very broad and diversified, and new uses are surfacing. There is no question that FFT plays a crucial role in several applications, such as audio/speech processing and recognition [2]. Moreover, it is a relevant functional block in modern digital communication systems, for applications in orthogonal frequency-division multiplexing (OFDM) systems [3, 4], such as digital worldwide interoperability for microwave access, wireless metropolitan-area networks, and in the areas of next-generation wireless systems, radar signal processing, spectra sensing of cognitive radio, etc. FFT is also used in medical imaging for image filtering, analysis, and image reconstruction [5, 6]. Various algorithms have been developed to perform the software version of FFT to maximize the execution time and reduce the computational complexity [7]. Instructions of these procedures are generally executed serially, and, as a result, their execution speed is heavily bound by processor throughput. Hardware implementation of FFT approaches is still a challenging issue, even if it is useful for real-time and high-speed processing. Several architectures for the hardware design of FFT have been suggested in the literature over the years [8, 9]. They vary from fully parallel structures with high throughput, low latency, and a significant number of processing elements, to sequential structures with few processing elements and nonoptimized computation times. The basic aim of hardware designers is to achieve cost-effective implementations in terms of high performance, low hardware resource utilization, high accuracy, and low power consumption. Array architectures consisting of a certain number of independent processing elements, with local buffersconnected through a network, are characterized by their high performance because of spatial parallelism, but are hardware-consuming and require further routing resources. Spatial development of these structures becomes impractical as the size increases because of the area and power commitments related to the presence of complex interconnections [9; 10]. Pipeline architectures are a proper choice for high throughput and real-time applications. The flexibility of these regular architectures indicates an excellent potential for seeking more efficient designs [8]. To achieve better hardware efficiency, memory-based architectures are generally used. They pass data multiple times through either a single butterfly processing element or a set of processing elements, with several memory banks to hold intermediate results. Nevertheless, the throughput of memory-based FFTs is usually restricted by butterfly radix and concurrent data-access contentions [11]. Hardware implementation of FFT procedures can be performed by adopting integrated circuits, such as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), which are similar in their circuit designs because logic functions, which are yet to be synthesized, are specified using hardware description languages. FPGA circuits are preferred because of their specific-purpose circuits, low cost, and reconfigurable characteristics (which have architectural flexibility and fast development times) when new functionalities are added [12]. The FPGA design of FFT is often customized to achieve higher speeds on low-power specifications since FPGAs have risen in capacity and performance and reduced in cost. Several FPGA-based architectures are indicated in the literature for the design of circuits that are able to produce the FFT.