## 8 Conclusions  
Contemporary FPGA devices include a lot of look-up table elements. It allows the implementation of very complex digital system using only a single chip. But LUTs have rather small amount of inputs (\(S_{L}\) does not exceeds 6). This value is considered to be optimal [6]. Such a limitation leads multi-level circuits representing, for example, sequential blocks of digital systems. To design multi-level circuits, the methods of functional decomposition are used. But these blocks can be synthesized using different methods of structural decomposition. As our studies [26] show, the structural decomposition can lead to FSM circuits with better characteristics than their counterparts based on functional decomposition. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Benchmark** & \(\mathbf{U_{1}}\) & \(\mathbf{U_{3}}\) & \(\mathbf{U_{4}}\) & \(\mathbf{U_{5}}\) \\ \hline ex1 & 3.560 & 3.290 & 3.014 & 2.918 \\ \hline kirkman & 4.922 & 3.562 & 2.811 & 2.476 \\ \hline planet & 3.222 & 3.756 & 1.727 & 1.527 \\ \hline planet1 & 3.222 & 3.756 & 1.727 & 1.527 \\ \hline pma & 4.778 & 4.915 & 4.257 & 3.683 \\ \hline s1 & 3.694 & 3.813 & 3.578 & 3.058 \\ \hline s1488 & 1.586 & 2.412 & 1.449 & 1.785 \\ \hline s1494 & 1.730 & 2.398 & 1.453 & 1.302 \\ \hline s208 & 3.005 & 3.544 & 2.574 & 2.248 \\ \hline s420 & 1.604 & 3.384 & 1.543 & 1.292 \\ \hline s510 & 1.883 & 1.996 & 1.878 & 1.682 \\ \hline s820 & 2.465 & 2.161 & 1.756 & 1.843 \\ \hline s832 & 2.515 & 2.504 & 2.193 & 1.732 \\ \hline sand & 2.579 & 2.578 & 2.385 & 2.017 \\ \hline styr & 1.467 & 1.556 & 1.307 & 1.112 \\ \hline Total & 42.232 & 45.625 & 33.652 & 30.202 \\ \hline Percentage & 139.8\% & 151\% & 111.4\% & 100\% \\ \hline \hline \end{tabular}
\end{table} 
Table 10: Results of experiments (the consumed energy, Watts). The aim of this article is a presentation of a novel method of logic synthesis targeting Mealy FSMs implemented with LUTs and a configurable EMB. It is the method of structural decomposition based on encoding of product terms of Boolean functions representing FSM logic circuits. The essence of our approach is a splitting of the set of terms in a way minimizing the number of LUTs in FSM circuits. The proposed method is technology depended because it takes into account the number of inputs of LUT elements. The experiments conducted using the Xilinx CAD tool Vivado 2019.1 clearly show that the proposed approach leads to reduction for such values as the number of LUTs, propagation time and consumed energy in comparison with FSM circuits based on known methods of terms encoding. There are three directions in our future research. The first is connected with development design methods targeting FPGA chips of Intel (Altera). The second direction is connected with using our approach in real devices such as PDMS micro-optofluidic chip [29; 30]. The last direction targets sequential blocs represented by Moore FSMs. Conceptualization, analysis of FPGA-based design methods, A.B., L.T. ; the design methodology, M.M. ; the algorithm of finding the partition for the set of FSM terms, investigations, K.K. All authors have read and agreed to the published version of the manuscript. This research received no external funding. The authors declare no conflict of interest. The following abbreviations are used in this manuscript: \begin{tabular}{l l} BIMF & block of input memory functions \\ BOF & block of output functions \\ COF & collection of output functions \\ DST & direct structure table \\ EMB & embedded memory block \\ FSM & finite state machine \\ FPGA & field-programmable gate array \\ LUT & look-up table \\ SBF & systems of Boolean functions \\ SOP & sum-of-products \\ STT & state transition table \\ \end{tabular}   
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