## 2 Design and Fabrication
### Fabrication  
The IPDs were manufactured using standard wafer fabrication techniques combined with thin-film and photolithography processing, which makes the integration of discrete passive electronic components into a chip feasible [24; 25]. The BPF proposed in this study was developed using a total of 24 steps and five masks, and the fabrication flow is illustrated in Figure 5.  
First, a 6-in GaAs wafer was cleaned using the lift-off machine with acetone solution to create a flat surface as shown in step 1. Plasma-enhanced chemical vapor deposition (PECVD) technology was used to generate a 200 nm seed metal layer of Ti/Au SiNx passivation layer as shown in step 2; this technique was employed to improve adhesion between the metal layer and the GaAs wafer. Then, a seed metal layer consisting of 20 nm Ti and 80 nm Au was deposited by sputtering, as illustrated in step 3. In step 4, a positive photoresistor (PR) was formed by spin coating and then exposed using mask 1. Then, the first metal layer was formed with Cu/Au using electroplating technology with a thickness of 4.5/0.5 \(\upmu\)m, as shown in step 6. Next, the PR was stripped off using acetone solution, as illustrated in step 7. In steps 8-9, the positive PR was subsequently coated again and then exposed using mask 2, which was used to protect the first metal layer from the next etching process. Next, the unused part of the seed metal layer was etched using SF\({}_{6}\)/Ar plasma with an inductively coupled plasma (ICP) etcher, as illustrated in steps 10-12. In step 13, the positive PR was coated again and then exposed using mask 3 to prepare for the second metal layer deposition. Then, the second metal layer of Cu/Au was formed with a thickness of 1.8 \(\upmu\)m using electroplating technology, as given in step 15. In step 16, a negative PR, instead of a positive PR, was subsequently coated and then exposed using mask 4 to define the pattern of the third metal layer. Then, in step 17, the third metal layer was electroplated using Cu/Au with a thickness of 4.5/0.5 \(\upmu\)m, which is the same as the first metal layer. In step 19, the air-bridge structure was formed, and the PR was removed using acetone solution and wet etching technology. At the same time, other normal three-metal layer structure-like intertwined coils and the center capacitor were also produced. Then, a 300 nm SiNx passivation layer was deposited using PECVD to protect the device from moisture and oxidation, as given in step 20. Subsequently, a positive PR was coated and then exposed using mask 5 to etch the passivation layer via the ICP dry etch process with SF\({}_{6}\)/O\({}_{2}\) to connect the contacts for further performance testing, as illustrated in steps 21-22. Finally, in step 24, polishing, dicing, and wire-bonding processes were performed to mount the BPF device on the PCB, such that the RF performance of the fabricated device can be measured. The manufacturing techniques used in the IPDs process are explained in detail in Table 1.  
Figure 4: (**a**) S\({}_{11}\) and S\({}_{21}\) of the circuit model and full-wave simulations. (**b**) Current density at 2.2 and 5 GHz.  
Figure 5: GaAs-based integrated passive device (IPD) technology fabrication flow.