# Quantum Circuit-Width Reduction through Parameterisation and Specialisation
## 9 Demonstration of Reduction of Integer Divider
### Discussion of Results--Implication for Wider Range of Circuits  
As discussed in Section 1, the present work on circuit reduction steps for quantum arithmetic operations is motivated by the fact that such arithmetic operations are often an important part of a wide range of larger and more general quantum algorithms. The development and evaluation of these larger quantum algorithms typically involves large-scale full-state vector circuit simulations, e.g., to check correctness, sensitivity of quantum gate errors and effect of quantum decoherence errors. High-performance computing resources commonly available to quantum algorithm developers typically limit the qubit count to 30-35, so that reductions of multiple qubits that are only involved in quantum arithmetic operations create much needed reduced memory requirements. Considering the small example problems discussed here, for the integer divider the quantum circuit width was reduced from 17 qubits in the original circuit (going down to 16 when parameterised, since a carry qubit used in the Cuccaro adders could be removed) to 12 in the 'fully' reduced circuit (i.e., specialised for a specific value of divisor). For a circuit simulator using full state vector, this results in a useful reduction in memory by a factor of 32. The FQT toolchain was also used to inspect the gate complexity of the circuits that result from the various eDSL definitions above. To summarise the results of proposed transformation, the previously considered integer division circuit for a 7-qubit dividend and 4-qubit divisor is detailed in Table 3. The baseline circuit uses Cuccaro modulo adders. For a 4-qubit divisor, the reduction step can then reduce the qubit count by 5 since the carry qubit from the Cuccaro adder can also be removed. The gate count reduction relative to the baseline is dependent on the particular choice of the divisor value, as shown in the table for two example values. The baseline long division circuit without parameterisation requires 674 gates to implement. The implemented parameterised long division circuit produced by the listing in Figure 24 requires 1612 gate operations, while the fully reduced divider generated by Figure 25 requires only 252 gates for the dividing by 9 example and 296 gates for dividing by 11. \begin{table}
\begin{tabular}{r c c c c} \hline  & \(|out3|out2|out1|out0|test|b3|a3|b2|a2|b1|a1|b0|a0|qinj2|qinj1|qinj0|\) & \\ \hline \multicolumn{2}{c}{**Operation**} & \multicolumn{2}{c}{**Input**} & \multicolumn{2}{c}{**Output**} & \multicolumn{2}{c}{**Unpacked \(|out\rangle\)**} \\ \hline
64/9 & \(|0|0|0|0|0|1|1|0|1|0|1|0|0|0|0\) & \(|01|1|1|0|0|1|1|0|1|0|0|0\) & \(|01111\rangle\) (7) \\
72/10 & \(|00|0|0|0|1|1|0|1|0|0|0\) & \(|01|1|1|0|0|1|1|0|0\) & \(|01|1|1|0|0|1|1|0|0|0\) & \(|01111\rangle\) (7) \\
96/11 & \(|00|0|0|0|0|1|11|1|0|0|0\) & \(|10|0|0|0|1|1|1|0|1|0|0\) & \(|10|0|0|0|0\) & \(|101|1|1|0|0|1|0\) & \(|0111\rangle\) (7) \\
104/12 & \(|00|0|0|00|1|11|0|0|0|0\) & \(|10|0|0|0\) & \(|00|0|0|1|11|0|0|0\) & \(|100|0|0\) & \(|100|0\) (8) \\
112/13 & \(|00|0|00|0|1|01|1|1|0|0|0\) & \(|10|0|0|0\) & \(|10|0|0|0|1|1|1|0|0\) & \(|100|0\) & \(|100|0\) (100|0\) (8) \\
80/14 & \(|00|00|0|0|1|0|0|1|1|0|0|0\) & \(|01|0|0|1|0|0|1|0|0\) & \(|01|0|0|1|0|1|1|0|0\) & \(|0101|\) (5) \\
104/15 & \(|00|00|0|0|1|0|1|0|0|1|1|0|0|0\) & \(|01|1|0|0|1|0|1|0|0\) & \(|011|0|0|1|0|1|0|0\) & \(|0110\rangle\) (6) \\ \hline \end{tabular}
\end{table} 
Table 1: Full Design 3 long division divider testing results sample.