## 2 Proposed TSP Readout System
### Dot-Matrix C\({}_{\text{S}}\)-Compensator  
There have been numerous studies on self-capacitance (C\({}_{\text{S}}\)) sensing front-ends, with various compensation techniques proposed. The compensation using chip-integrated capacitors has been identified as one of the most accurate topologies, as demonstrated in [14]. However, this approach requires an increasing number and size of integrated capacitors proportional to the number of sensing channels, which significantly increases the chip area and makes it unsuitable for cost-sensitive applications. To address this, current-mode compensation schemes employing static sinking or sourcing currents have been utilized [15, 16], offering an area-efficient solution for realizing the compensation charge. However, this method is highly susceptible to process and temperature variations. Temperature sensitivity presents a critical challenge in smartphone applications, where operational conditions are heavily affected by environmental factors, such as ambient weather variations. Figure 3: Circuit diagram of the TSP sensing front-end, its timing diagram, and frequency response of the second-generation current conveyor + capacitance-to-voltage converter. The proposed C\({}_{5}\)-sensing circuit achieves a balance between accuracy and area efficiency by utilizing both integrated capacitors and a current-mode scheme. As shown in Figure 4, the compensator incorporates three main blocks: an integral reference capacitor (C\({}_{\rm REF}\)), adjustable from 13 pF to 20 pF in 1 pF increments, connected to the negative input of the OTA (-)IN, an OTA configured as a unity-gain amplifier, which transfers charges from C\({}_{\rm REF}\) (Q\({}_{\rm SC}\), Q\({}_{\rm SK}\)) to its output, and 10 current output cells, which amplify Q\({}_{\rm SC}\) and Q\({}_{\rm SK}\) to compensate the channel-dependent C\({}_{\rm S}\). When the (+) input of the OTA, (+)IN is driven by the AC-modulated V\({}_{\rm DRV}\) at a frequency of \(t_{\rm TSP}\), C\({}_{\rm REF}\) is alternately charged to V\({}_{\rm H}\) or V\({}_{\rm L}\), delivering equivalent charges of Q\({}_{\rm SC}\) and Q\({}_{\rm SK}\) to the OTA's output. The absolute variation in these charges is equal to C\({}_{\rm REF}\times({\rm V}_{\rm H}-{\rm V}_{\rm L})\), which modulates the gate voltages (V\({}_{\rm GP}\) and V\({}_{\rm GN}\)) of the PMOS/NMOS transistors (M\({}_{\rm P2}\), M\({}_{\rm N2}\)) in the current sources. Since the current copying output cell shares the V\({}_{\rm GN}\) and V\({}_{\rm GP}\) with the output of the OTA, it generates and amplifies C\({}_{\rm REF}\times({\rm V}_{\rm H}-{\rm V}_{\rm L})\) at its output (V\({}_{\rm CS,O}\) [9:0]) by ratio M to compensate for the baseline C\({}_{\rm S}\). This cell includes both a 4b fine compensation unit (1/16Q\({}_{\rm SC}\) to 1/2Q\({}_{\rm SC}\)) with 1/16Q\({}_{\rm SC}\) steps and a 3b coarse compensation unit (Q\({}_{\rm SC}\) to 4Q\({}_{\rm SC}\)) with Q\({}_{\rm SC}\) steps controlled by GCTR<6:0>. For instance, with a C\({}_{\rm REF}\) of 20 pF, the compensation range for C\({}_{\rm S}\) spans from 1.25 pF to 160 pF with a 7b resolution. Although the OTA has a single dominant pole (w\({}_{\rm don}\)) at its output formed by C\({}_{\rm REF}\) and PMOS/NMOS cascade resistors in parallel (R\({}_{\rm op}\)//R\({}_{\rm on}\)), its stability is degraded by parasitic capacitance from the 10 output cells connected to V\({}_{\rm GN}\) and V\({}_{\rm GP}\) in parallel. Since the size of each output current cell is approximately eight times that of OTA, the gate capacitance of each cell (C\({}_{\rm G,OUT}\)) is also eight times that of M\({}_{\rm N2}\)'s gate capacitance (C\({}_{\rm G,MN2}\)). Consequently, the total parasitic capacitance at V\({}_{\rm GN}\) (C\({}_{\rm P}\)) can increase by approximately 80 times compared to a conventional OTA of the same device size without output current cells.