# A High-Conversion Ratio Multiphase Converter Realized with Generic Modular Cells
## 5 Simulation and Experimental Results  
The verification and proof-of-concept demonstration of the design methodology are carried out by a simulation and experiments of a three-phase buck converter. A steady-state simulation waveforms of 40 W, 48 V-to-1 V converter for an output current of 40 A with equal duty ratios of \(1/12\) is shown in Figure 7. The output voltage, inductors currents, and the sum of the inductor currents in the CCM mode are shown in Figure 7a. Note that due to the three-phase interleaved operation of the converter, the effective switching frequency at the output of the converter triples from 500 kHz to 1.5 MHz. From the results, natural current sharing is observed between phases and a ratio of 2:1 between \(I_{L2}\) to \(I_{L1}\) and \(I_{L3}\) can be seen. The simulation includes switch resistances \(R_{DS\ (on)}\) as outlined in Table 3, so that the output voltage and current are slightly lower than theoretically expected. The maximum voltage stress of \(V_{\text{in}}/2\) on the switches \(S_{2\text{H}}\), \(S_{2.3}\), and \(S_{3\text{H}}\) is demonstrated in Figure 7b. A simulation of a multiphase converter with two \(1\times 3\) modules is shown in Figure 8. The converter is rated at 80 W, steps the voltage down from 48 V-to-1 V, and operates at a switching frequency of 500 kHz per-phase. The converter consists of two modules (\(m=2\)) that are connected in parallel, each with a chain of three cells (\(n=3\)). Both converters are identical and operate with the same duty ratio that results in an output voltage of 1 V. Simulation results of Figure 8 demonstrate equal current levels and shapes for each of the modules, and the total output current is the sum of the two currents from each module, i.e., \(I_{\text{outT}}=I_{01}+I_{02}\). \begin{table}
\begin{tabular}{c c c c c c c} \hline
**Switch** **\# of Cells** & **2** & **3** & **4** & **5** & **6** & **7** & **8** \\ \hline \(S_{xL}\) (\(x\geq 1\))\({}^{1}\) & \((1/3)V_{in}\) & \((1/4)V_{in}\) & \((1/5)V_{in}\) & \((1/6)V_{in}\) & \((1/7)V_{in}\) & \((1/8)V_{in}\) & \((1/9)V_{in}\) \\ \hline \(S_{xH}\) (\(x>1\))\({}^{2}\) & \((2/3)V_{in}\) & \((2/4)V_{in}\) & \((2/5)V_{in}\) & \((2/6)V_{in}\) & \((2/7)V_{in}\) & \((2/8)V_{in}\) & \((2/9)V_{in}\) \\ \hline \end{tabular} \({}^{1}\) Includes \(S_{1\text{H}}\); \({}^{2}\) includes the switch between the last cell to the previous one, \(S_{(n-1)-(n)}\).  
\end{table} 
Table 2: An example of maximum switch voltages vs. the number of cells. Figure 6: The voltage ratio \((1/M)\) of the presented topology according to Equation (6): (**a**) a continuous combination of \(D_{1}\) and \(D_{2}\) ranging from 0.05 to 0.25, with two constant values of \(D_{3}\) (0.05 and 0.25); (**b**) a case where \(D_{1}=D_{3}\) and are the \(x\) axis, and black solid traces represent several \(D_{2}\) values. Dashed red traces represent some conversion ratios and demonstrate the flexibility of the converter to achieve the same conversion ratio with several different duty ratio options. To demonstrate the current sharing robustness of the topology in a presence of inductors mismatch, a simulation of the converter operating under heavy load conditions of \(V_{\text{in}}\) = 48 V, \(V_{\text{out}}\) = 1 V, and \(I_{\text{out}}\) = 100 A, with equal duty ratio and different inductance values of \(L_{1}\) = 0.6 \(\mu\)H, \(L_{2}\) = 0.2 \(\mu\)H, and \(L_{3}\) = 0.5 \(\mu\)H is shown in Figure 9. The simulation demonstrates a difference between \(L_{1}\) and \(L_{3}\) on the level of a component tolerance mismatch, and a major inductance disproportion is demonstrated using a very low inductance of \(L_{2}\) comparing to \(L_{1}\) and \(L_{3}\).