# Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
## 1 Introduction  
The traditional Von Neumann architecture inherently separates the arithmetic logic unit (ALU) from memory, resulting in a significant computational bottleneck due to the frequent data transfers required between these two components. This constant movement of data primarily leads to increased energy consumption and latency, as operations are stalled waiting for data to travel between memory and the ALU. This bottleneck is particularly pronounced in modern computing systems, where applications demand extensive memory read/write operations to handle data-intensive tasks, such as those in machine learning, big data processing, and high-performance computing [1]. In contrast, the compute-in-memory (CIM) architecture integrates multiple processing functionalities directly into the memory array, thereby minimizing the need for extensive memory access and substantially reducing the associated energy costs [2]. Beyond its energy-saving advantages, the CIM structure enables large-scale parallel processing by allowing operations to be performed within an extensive array of memory bit-cells equipped with built-in analog multiplication and accumulation (MAC) functions [3]. This architecture dramatically enhances computational performance by executing operations in parallel across memory cells. Unlike traditional Von Neumann-based systems, which require multiple clock cycles to complete MAC operations on a single layer, the CIM architecture can simultaneously activate multiple rows of bit-cells, calculating all connections between two layers in a single clock cycle, thereby yielding substantial improvements in both speed and energy efficiency [4]. The application of edge devices has become increasingly widespread across diverse fields, including smart cities, industrial automation, agriculture, healthcare, and transportation [5]. Recently, edge devices have evolved significantly, integrating artificial intelligence (AI) technologies and thus transforming into sophisticated AI edge devices capable ofreal-time data processing [6]. AI has established itself as an innovative technology for addressing real-time computational challenges, such as speech and facial recognition, where immediate data interpretation is critical. CIM structures are particularly advantageous for processing AI neural networks (NN) and have become highly suited for use in AI edge devices, where both memory and power resources are limited [7]. By replacing traditional Von Neumann architectures, CIM offers effective solutions to various optimization and mathematical problems, enabling AI edge devices to perform more efficiently within their constrained environments and meet the demands of real-time, data-intensive applications [8]. [PERSON] [2] presents an 8 transistor (8T) SRAM design that enhances the read noise margin by strategically adjusting the channel length of transistors within the cell. While this approach successfully improves noise tolerance during read operations, it introduces the drawback of increased power consumption, which arises from the incorporation of complex circuits needed for effective voltage control. [PERSON] [3] proposed an alternative 8T SRAM design focused on achieving low power consumption and enhanced stability, particularly through the use of additional transistors to improve operational robustness. However, this approach inevitably leads to an increase in both cell size and power consumption, presenting trade-offs between power efficiency and memory density. [PERSON] [6] introduced an 8T SRAM-based CIM macro with integrated analog computing capabilities, specifically targeting compute-in-memory (CIM) applications. Nevertheless, [PERSON]'s design relies on high-resolution analog-to-digital converters (ADCs) to interpret analog outputs, which significantly increases both the system's complexity and its power requirements. Similarly, [PERSON] [9; 10] proposed a multi-bit CIM structure based on a twin 8T SRAM configuration, designed to enable parallel processing across multiple bits and thereby improve throughput.