# A Deep Reinforcement Learning Floorplanning Algorithm Based on Sequence Pairs +
## 5 Experimental Results
### Experimental Results and Analysis
#### 5.2.1 Experimental Results of MCNC and GSRC Test Sets  
First, a synergistic optimization of area and wirelength was performed on the MCNC test set, and the experimental results are presented in Table 4. The dead space (DS) represents the proportion of gaps between macro-modules within the floorplan border to the total floorplan area. As shown in the table, the proposed algorithm generated a floorplan in the MCNC test circuits with a smaller area, DS, and wirelength compared to the simulated annealing algorithm. In terms of layout area and DS, the proposed algorithm also outperformed the approach described in Reference [36]. However, a direct comparison of wirelength was not made due to the different estimation method used in Reference [36]. Regarding DS and wirelength, the proposed algorithm achieved an average improvement of 2.7% and 9.1%, respectively, compared to the simulated annealing algorithm. Furthermore, compared to Reference [36], the proposed algorithm achieved an average improvement of 1.1% in DS. Therefore, the proposed algorithm demonstrates certain advantages over the simulated annealing algorithm and Reference [36] in area optimization for small-scale circuits, as well as outperforming the simulated annealing algorithm in wirelength optimization.  
Table 5 presents the experimental results comparison for three GSRC test circuits, revealing that the proposed algorithm outperforms the simulated annealing algorithm and Reference [36] in terms of floorplan area and DS and is also superior to the simulated annealing algorithm in wirelength. In comparison with the simulated annealing algorithm, the proposed algorithm achieves an average improvement of 7.0% in DS and 8.8% in wirelength. Furthermore, when compared to Reference [36], the proposed algorithm obtains an average improvement of 3.7% in DS. From both tables, it can be observed that, as the size of the test circuits increases, the DS for all three methods also increases, indicating an increased difficulty in floorplan placement. However, the proposed algorithm demonstrates a further improvement in performance compared to the simulated annealing algorithm and Reference [36] for large-scale circuits, offering more pronounced advantages in floorplan area and wirelength optimization.  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**MCNC**} & \multicolumn{3}{c}{**Area (\(\times\)10\({}^{6}\))**} & \multicolumn{3}{c}{**DS (\%)**} & \multicolumn{3}{c}{**Wirelength (\(\times\)10\({}^{5}\))**} \\ \cline{2-9}  & **Ours** & **SA** & **Ref. [36]** & **Ours** & **SA** & **Ref. [36]** & **Ours** & **SA** \\ \hline apte & 46.94 & 47.65 & 47.08 & 0.81 & 2.29 & 1.10 & 0.45 & 0.51 \\ xerox & 20.40 & 20.91 & 20.42 & 5.15 & 7.46 & 5.24 & 0.49 & 0.55 \\ hp & 9.20 & 9.42 & 9.21 & 4.02 & 6.26 & 4.13 & 0.32 & 0.47 \\ ami33 & 1.22 & 1.27 & 1.24 & 4.92 & 8.66 & 6.45 & 0.61 & 0.75 \\ ami49 & 37.31 & 38.86 & 38.65 & 4.99 & 8.78 & 8.28 & 6.33 & 6.65 \\ Average & 23.01 & 23.62 & 23.32 & 3.98 & 6.68 & 5.04 & 1.64 & 1.79 \\ Normalization & 1.000 & 1.027 & 1.014 & 1.000 & 1.027 & 1.011 & 1.000 & 1.091 \\ \hline \hline \end{tabular}
\end{table}
Table 4: Comparison of experimental results of MCNC test circuit.  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**GSRC**} & \multicolumn{3}{c}{**Area (\(\times\)10\({}^{5}\))**} & \multicolumn{3}{c}{**DS (\%)**} & \multicolumn{3}{c}{**Wirelength (\(\times\)10\({}^{5}\))**} \\ \cline{2-9}  & **Ours** & **SA** & **Ref. [36]** & **Ours** & **SA** & **Ref. [36]** & **Ours** & **SA** \\ \hline n100 & 1.93 & 1.99 & 1.95 & 6.99 & 9.91 & 7.95 & 1.87 & 1.99 \\ n200 & 1.99 & 2.25 & 2.15 & 11.71 & 21.91 & 18.14 & 3.37 & 3.62 \\ n300 & 3.25 & 3.58 & 3.40 & 15.95 & 23.70 & 19.71 & 4.95 & 5.49 \\ Average & 2.39 & 2.61 & 2.50 & 11.55 & 18.51 & 15.27 & 3.40 & 3.70 \\ Normalization & 1.000 & 1.092 & 1.050 & 1.000 & 1.070 & 1.037 & 1.000 & 1.088 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Comparison of experimental results of GSRC test circuit.