# The Challenges of Advanced CMOS Process from 2D to 3D
## 3 Process Integration of New Transistor Architecture
### Stress Engineering  
Stress engineering is a crucial issue for Si MOSFETs. There are three commonly used methods for stress engineering in nano-scaled transistors e.g., stress memorization technique (SMT), SiN contact etch stop layers (CESL) stressors and epitaxy of SiGe on S/D regions are used to create stress in the channel region. Among these methods SMT and CESL are less effective for FinFETs and nano-wire FETs. SMT is grounded on growth of a highly tensile-stressed SiN followed by a thermal annealing step \(>\)1000 \({}^{\circ}\)C. In this process, the SiN capping layer is deposited on the whole Si wafer and it is kept on the n-type metal oxide semiconductor (nMOS) region while it is selectively removed from the p-type metal oxide semiconductor (pMOS) area. Stress is mainly memorized during the anneal step for activation step in S/D areas. A wet etching is applied after SMT process to remove the SiN layer before silicide formation. In SMT, the stress memorization is originated from compressive stress which is induced by the n-type poly-Si gate under the SiN capping layer. The volume of polycrystalline material expands during the annealing step and induces a tensile stress along the longitudinal direction, as shown in Figure 3.  
A more innovative way to induce stress in planar transistors is CESL. This technique consists of a SiN\({}_{\mathrm{x}}\) layer deposited around the gate stack as shown in Figure 4. By tuning the process parameters the stress amount and its type: tensile or compressive can be determined [34]. The most effective method to induce stress in S/D is embedded SiGe (compressive stress for pMOS), Si:C (tensile stress for nMOS) or trench contact, and in metal gate [34]. More aggressive scaled nodes have tighter contacted poly pitch (CPP), resulting in less room for gate and S/D. Effectiveness of the gate and S/D stressors depends on the trade-off between reducing stressor volume and enhancing stressor proximity to channel [35]. To further enhance the channel mobility in planar MOSFETs, the Ge content in SiGe S/D has been continuously increased from 17% to 40% in 90 nm to 22 nm node, respectively [36; 37; 38; 39; 40]. Further strain could be induced when the shape of recessed S/D changed from a round shape to sigma (\(\Sigma\)) shape where the SiGe layers locate deeper in the channel region as shown in Figure 5[41; 42; 43]. Figure 3: Schematic of stress memorization technique (SMT) in n-type metal oxide semiconductor (nMOS) with a stressor cap layer. The epi-layers may suffer from several problems e.g., facet formation [44; 45], defects, micro/loading, non-uniform strain distribution, surface roughness and pattern dependency effect [46; 47; 48; 49; 50]. The pattern dependency happens when the density and size of the transistor vary in a chip. The reason for the pattern dependency of selective epitaxy is mainly non-uniform consumption of reactant gas molecules when the exposed Si area varies in chip. This problem can be decreased by optimizing the growth parameters (high HCl partial pressure, low total pressure and high hydrogen carrier gas pressure) and by designing chip layouts where the exposed Si is uniformly distributed over the chip's area to create uniform gas consumption [50]. The evolution of Ge content in S/D and stress created in channel for different technology nodes is shown in Figure 6. The 3D architecture was designed and manufactured for 22 nm node. SiGe layers are selectively grown by reduced pressure chemical vapor deposition (RPCVD) technique by using SiH\({}_{2}\)Cl\({}_{2}\), GeH\({}_{4}\) as Ge and Si precursor, respectively. During epitaxy, HCl gas is introduced for etching the formed nuclei on the SiO\({}_{2}\) surface to ensure the selectivity of the growth. The big challenge when the planar transistors are redesigned to 3D is uniformity of strain and the control of the defect density in the channel region. Figure 7 shows how the epitaxy occurs for planar and 3D transistors.