# Analysis of Circuit Simulation Considering Total Ionizing Dose Effects on FinFET and Nanowire FET
## 3 TID Simulation Results and Procedure of Compact Modeling with TID  
Figure 2 shows the PMOS device's electrical characteristics according to the total dose. \(V_{\mathrm{T}}\) was extracted when the drain absolute current was 0.1 \(\upmu\)A using the constant current method, as shown in Figure 2. As the holes were trapped in the insulator region, \(V_{\mathrm{T}}\) was shifted. The electrical properties further changed with the increase in the radiation dose.  
Figure 1: Technology computer-aided design (TCAD) structures of the FinFET and Nanowire FET (NW-FET). (**a**) FinFET 3D structure; (**b**) FinFET’s cross-section of gate; (**c**) FinFET’s cross-section of channel length; (**d**) NW-FET 3D structure; (**e**) NW-FET’s cross-section of gate; (**f**) NW-FET’s cross-section of channel length.  
Figure 3 shows the \(V_{T}\) shift for each TID for both FinFET and NW-FET. The result before 10 Mrad shows a large change in the \(V_{T}\) of PMOS devices, but the result is reversed at 100 Mrad. Also, the \(V_{T}\) variation of n-type and p-type devices is about several mV. In the case of planar MOSFET, it is known that the PMOS device is affected more by the TID effect due to the interface trap. However, in the case of nanoscale 3D-structure devices, the influence of the interface trap is reduced because of the short channel length, and the \(V_{T}\) variation of n-type and p-type is similar. In addition, the more a device has a strong gate controllability, the less variation in the TID effect [32, 33]. The NW-FET exhibits a smaller \(V_{T}\) shift than that of the FinFET. The NW-FET has a wider oxide area than FinFET. Thus, NW-FET had to be more affected by a TID effect and exhibit a larger \(V_{T}\) shift than FinFET. However, the NW-FET was less affected due to the superior gate controllability. This is suppressed not only the SCE problem, but also the TID effect issue [34]. Structurally, the NW-FET insulator area was larger (96.1 nm\({}^{2}\)) than that in the FinFET. However, contrary to the expectations, the NW-FET had a smaller TID effect than that of FinFET. Therefore, the gate controllability is more important in the TID effect suppression than the oxide area.  
Figure 2: \(I_{D}\)–\(V_{G}\) curve shift with the increase in the radiation dose up to 100 Mrad. The simulation method sweeps \(V_{G}\) from 0 to 0.7 V when the total dose is reached. (**a**) PMOS FinFET; (**b**) PMOS NW-FET.  
The simulation of TID circuits requires a very long time period because of the numerous calculations. However, the spice circuit simulation method, which extracts and executes BSIM parameters, can check results faster than the conventional TCAD circuit simulation. Thus, for the circuit simulation, parameters of the BSIM, widely used in the industry as a standard compact model, were extracted. Figure 4 shows a flow chart of parameter extraction considering the TID characteristics. TID simulation data from the Vicitory Device platform were extracted using various BSIM CMG parameters. The extracted data were applied to the circuit simulation considering the TID.