# A Manycore Vision Processor for Real-Time Smart Cameras +
## 5 Results and Analysis
### Performance Evaluation  
The performance experiment was set to capture 500 frames, where the camera is set to a free-capture mode, saving all the frames in the acquisition frame buffer. The ARM processor controls the MPSoC to wait for the camera VSYNC signal and guarantee correct frame processing. As image transfer time from the acquisition FB to PM  
Figure 8: Motion estimation using a corner detector. \begin{table}
\begin{tabular}{l l l l l l} \hline \hline  & Device & 1 Tile & 4 Tiles & 9 Tiles & 16 Tiles \\ \hline PL Max. Freq. (MHz) & - & 134.77 & 128.85 & 122.80 & 122.88 \\ LUT & 230,400 & 9841 & 16,057 & 26,117 & 39,765 \\ LUTRAM & 101,760 & 789 & 1557 & 2837 & 4629 \\ FF & 460,800 & 9733 & 15,219 & 24,164 & 36,843 \\ BRAM & 312 & 195 & 197 & 198 & 205 \\ URAM & 96 & 1 & 4 & 9 & 16 \\ DSP Blocks & 1728 & 6 & 18 & 38 & 66 \\ \hline  & 25 Tiles & 36 Tiles & 49 Tiles & 64 Tiles & 81 Tiles \\ \hline PL Max. Freq. (MHz) & 120.61 & 122.01 & 122.56 & 122.70 & 111.42 \\ LUT & 56,837 & 80,944 & 110,941 & 141,772 & 178,582 \\ LUTRAM & 6933 & 9749 & 13,077 & 16,917 & 21,269 \\ FF & 53,240 & 73,421 & 97,350 & 124,997 & 156,400 \\ BRAM & 195 & 219 & 234 & 237 & 207 \\ URAM & 25 & 36 & 49 & 64 & 81 \\ DSP Blocks & 102 & 146 & 198 & 258 & 326 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Resources for the complete IP/CV processing chain, QVGA image, different manycore’s sizes. which is similar to the DMA transfer time, there is no pixel loss in free-capture with the camera producing 60 fps. To determine the processing delay, the timer starts to count when the ARM finishes the setup and initialize peripherals (the MCVP, DMA, camera, and Acquisition FB) and stops to count after writing the last pixel in ARM's DRAM through the DMA. Five algorithms are implemented: the Harris, Sobel, 3 \(\times\) 3, 5 \(\times\) 5, and 7 \(\times\) 7 convolutions. Figure 9 (left) shows a chessboard captured image from the sensor and read from ARM DRAM through an UART interface, for evaluation purposes. Figure 9 (right) depicts the final CoM computed over an HCD output image. Figure 10 shows the performance of the manycore system in simulation (up to 400 tiles) and implemented alone in the FPGA-fabric (up to 81 tiles) [4]. The implementation could reach only 81 tiles, due to the device physical limitations. However, through simulation, we can see the scalability and performance improvement by exploring the natural parallelism of the IP/CV algorithms. Figure 11 shows time performance results for the algorithms executed, from 1 to 81 PEs, in frames per second (_fps_) [4]. The results differ from Figure 10 due to the synchronization  
Figure 10: Performance in frames per second comparing implemented and simulated results for the Harris Detector. Figure 9: **Left: real image acquired by the pixel sensor; right: center of mass (red cross) calculated by the ARM processor over an HCD output from the manycore. **  
with the image sensor. The sensor configuration could only be used to output single-shot images (1 and 4 tiles), 30 fps (9 to 36 tiles), and 60 fps (49 to 81 tiles). The processing architecture is able to reach the performance depicted in Figure 10; however, the pixel sensor was the system's main bottleneck. It is important to highlight that the processing architecture was designed to fulfill the real-time constraints given by the sensor frame rate. It is not easy to compare different architecture types, as well as systems designed with different VLSI technologies. To have a kind of normalization, we computed the \(cycles/pixel\), which is a metric that shows how efficiently a computing architecture implements an IP/CV application. This metric is independent of the VLSI technology and the operating frequency. We believe that, with this normalization, we can fairly compare the architectural designs from several years ago until now. A comparison, only for the Sobel edge detector against our 81 tiles implementation, is shown in Table 4[4]. We can see that our architecture provides a good performance, while still being flexible.