# Bit Streaming Processing Algorithms for Intelligent Hardware Converters
## 3 Results
### Algorithm Implementation  
We use VerilogHDL to implement and verify the considered algorithms. The VerilogHDL behavioral descriptions can be used to synthesize hardware modules. The input signals of the pulse frequency sweep module are the reference frequency signal clk and the input code \(\mathrm{Nk}\). The pulse stream Fout is generated at the output of the synthesized module. Figure 4 shows the result of the Verilog module simulation with the ModelSim. Figure 4: Result of pulse-frequency sweeping algorithm simulation. To test the module, we used a TestBench. It is a non-synthesizable fragment of the VerilogHDL program that continuously generates the clock signal clk with frequency f click as well as the changing input code Nk. The function $\mathrm{\SIUnitSymbolMicro}$random\_range is used to generate the input code in a bit grid i; the frequency of code Nk changing during the test is f\({}_{\mathrm{clk}}\)/(3 \(\times\) 2i). The bit width of the processed codes Nk is 4, so the pulse-frequency sweeping algorithm generates 4 pulse streams P\({}_{\mathrm{v0}}\)-P\({}_{\mathrm{v3}}\). The lines DF_vlg_tst/i1/P\(\mathrm{[3...0]}\) of the diagram show the generation of these streams. The total number of pulses in these streams during one period corresponds to the maximum possible value of the code represented in the 4-digit grid, and this value is equal to 15. Three periods of algorithm operation are highlighted in Figure 4. The first period (time marks 9.967-9.999) shows the code Nk = 7 conversion. The number of pulses generated during the period of algorithm is 7 (line DF_vlg_tst/Fout). The second period is transitional. In this period the input code Nk is changed, so part of the period the output pulse stream is formed on the basis of the code Nk = 7, and then for Nk = 12. The third period (time marks 10.031-10.063) shows the code Nk = 12 conversion. The number of pulses generated per the period of the algorithm at the DF_vlg_tst/Fout output is 12. The streaming multiplication-division module calculates the function using formula (1). We simulate it with the use a 10-bit implementation. A generalized block diagram of the module is shown in Figure 5.  
The scheme contains the following sub-modules:  
* two code-to-bit-stream converters performing the conversion of codes N\({}_{1}\) and N\({}_{\mathrm{out}}\) into a bit stream using the Figure 2 algorithm and implementing the operations of blocks 1 and 5 of the algorithm shown in Figure 3;
* two code-to-PWM converters performing the conversion of N\({}_{2}\) and N\({}_{3}\) codes into a stream of PWM signals; they implement the operations of blocks 2 and 6 of the Figure 3 algorithm and can be implemented by known methods, for example, using counters;
* two <<<< elements performing multiplication of bit stream by PWM signal (blocks 3 and 7 of the Figure 3 algorithm);
* increment/decrement counter, which counts the pulses generated in the positive and negative branches of the unit (blocks 4 and 8 of the Figure 3 algorithm). Figure 5 shows the processes in the multiplication-division module. Figure 5: Generalized block diagram of the streaming multiplication-division module. To test the streaming multiplication-division module, we used TestBench, in which the clock signal clk was formed continuously and the input codes N1, N2 and N3 were formed using the function \(\mathsf{Surandom\_range}\). The frequency of change of input codes was chosen so that on the time diagram we could observe the transient process when the device tends to an equilibrium state, as well as the process of holding the stable state. The input code N1 is converted into a pulse stream (line MDU_st/i1/F_plus). The codes N2 and N3 are converted into PWM signal streams (line MDU_st/i1/PWM_Active2 and MDU_st/i1/PWM_Active3). Figure 6a shows the transient where the resulting signal (MDU_st/i1/r_count) increases on each cycle, coming closer to the result. The corresponding pulse stream becomes more intense on each cycle (MDU_st/i1/F_minus).