## 3 Smart Material Implication (SIMPLY) Logic Scheme  
The SIMPLY logic scheme stands out as a promising STT-MRAM-based LIM approach [15]. Notably, SIMPLY and sFALSE (a logic operation always resulting in 0) form a universal logic set, enabling the implementation of any logic gate using these two operations alone [21]. Figure 3a shows the STT-MRAM-based SIMPLY scheme, which consists of 2 MTJs, **P** and **Q**, control logic, an nMOS tail transistor, _Mn_ (a SIMPLY array [15] requires a single _Mn_ transistor per row), and a precharge sense amplifier (PCSA). Inputs are pre-stored as resistance states of MTJs, whereas the operation result eventually overwrites the MTJ **Q**. SIMPLY operation is orchestrated by the control logic block, which includes analog tri-state buffers (TSBs) responsible for applying the necessary voltages to the MTJs. The read voltage (\(V_{\text{READ}}\)), reset voltage (\(V_{\text{RESET}}\)), set voltage (\(V_{\text{SET}}\)), bias voltage (\(V_{\text{bias}}\)), and reference voltage (\(V_{\text{REF}}\)) are the voltage values set during SIMPLY and sFALSE operations. Note that \(V_{\text{bias}}\) voltage is used to implement a load resistor. SIMPLY operation is based on the observation that according to the truth table for the IMPLY logic operation (shown in Figure 3a), the only input configuration that actually leads to **Q**'\(\
eq\)**Q** and therefore requires MTJ **Q** to switch from '0' to '1' is the one for which \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Parameter** & **Description** & **DMTJ-300 K** & **DMTJ-77 K** & **SMTJ-300 K** & **SMTJ-77 K** \\ \hline \(d\) & Diameter & 30 nm & & 30 nm \\ \(t_{FL}\) & FL thickness & 1.2 nm & & 1.2 nm \\ \(t_{OX,T}\) & Top barrier thickness & 0.85 nm & & 0.85 nm \\ \(t_{OX,B}\) & Botton barrier thickness & 0.4 nm & & 0.85 nm \\ \(\text{P}\) & Spin polarization factor & 660 m & 730 m & 660 m & 730 m \\ \(\alpha\) & Gilbert damping factor & 30 m & & 30 m \\ TMR(0) & Tunnel magnetoresistance & \(\sim\)130\% & \(\sim\)200\% & \(\sim\)140\% & \(\sim\)220\% \\ LRS & Low resistance state & 15.5 k\(\Omega\) & 15.6 k\(\Omega\) & 14.2 k\(\Omega\) & 14.4 k\(\Omega\) \\ HRS & High resistance state & 37 k\(\Omega\) & 47 k\(\Omega\) & 35 k\(\Omega\) & 46 k\(\Omega\) \\ \(I_{CP}\) & Critical switching current parallel & 8.6 uA & 10.4 uA & 30.7 uA & 44 uA \\ \(I_{AP}\) & Critical switching current antiparallel & 8.6 uA & 10.4 uA & 12.1 uA & 13.6 uA \\ \(\Delta\) & Thermal stability factor & 40 & 175 & 40 & 216 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Parameters and characteristics of SMTJ-based and DMTJ-based devices. \(\mathbf{P}=\mathbf{Q}=\) '0', while in all the other cases, it must be \(\mathbf{Q}^{\prime}=\mathbf{Q}\) which makes energy-hungry MTJ \(\mathbf{Q}\) switching unnecessary. So, being able to distinguish this input configuration from the others would be profitable. To accomplish this, the SIMPLY operation comprises a preliminary read, followed by a set phase (see Figure 3b). During the preliminary read operation, a \(V_{\text{read}}\) pulse with width \(t_{\text{read}}\) is applied to MTJs \(\mathbf{P}\) and \(\mathbf{Q}\). This produces a \(V_{\text{G}}\) voltage that is compared to \(V_{\text{REF}}\) by a PCSA. The output (\(V_{\text{out}}\)) of the PCSA discriminates the case \(\mathbf{P}=\mathbf{Q}=\) '0' from all the others. In the subsequent phase, a SET pulse, with amplitude \(V_{\text{SET}}\) and width \(t_{\text{SET}}\), is applied on \(\mathbf{Q}\) only when \(\mathbf{P}=\mathbf{Q}=\) '0' to switch \(\mathbf{Q}\) from '0' to '1'. During the SET phase, \(\mathbf{P}\) is connected to a high impedance (HI-Z), regardless of the result in the preliminary reading [21; 22]. As shown in Figure 3c, the sFALSE operation is performed on a single MTJ device and stores the output within the same MTJ. The sFALSE execution always results in a logic '0' being stored in the MTJ. Figure 3d shows the sFALSE operation applied to \(\mathbf{Q}\), i.e.,'sFALSE \(\mathbf{Q}^{\prime}\).