# Variable Delayed Dual-Core Lockstep (VDCLS) Processor for Safety and Security Applications
## 4 Results
### Execution Correlation Results  
The execution trace presented in Figure 9 shows that, indeed, the slave core delay does not have to be constant and the VDCLS implementation can execute software correctly. On the other hand, the presented figure shows only a very time-limited trace that is hard to analyze. To overcome this problem, we implemented test logic in the processor core that counts DFFs toggles in the execution stage. We choose the execute stage as the most representative one in the processor pipeline. The execute stage is responsible for the calculation of instruction results, address generation, interrupt and exception evaluation. In the real ASIC design, the toggle count will transform into power consumption trace, the tool that is most commonly used for power analysis attacks [32]. By having toggle count traces, we could use formula (1) to calculate their correlation with different delays. The first and second formula variables are the toggle count traces of the master and slave cores, respectively. The number of samples represents the simulation time in clock cycles. The function argument \(d\) is the offset in clock cycles between the master and slave core traces. We can anticipate that in the classic DCLS approach the execution correlation between the two cores will reach the maximum at the value equal to the number of clock cycles of slave core to master core delay. \[r(d)=\frac{n(\sum x_{i}y_{i+d})-(\sum x_{i})(\sum y_{i+d})}{\sqrt{(n\sum x_{i} ^{2}-(\sum x_{i})^{2})(n\sum y_{i+d}^{2}-(\sum y_{i+d})^{2})}} \tag{1}\] \begin{table}
\begin{tabular}{c c c c} \hline \hline  & **Dhrystone** & **CoreMark** \\  & **[DMIPS/Hz]** & **[CoreMark/MHz]** \\ \hline Multicore (2 cores) & 1.38 & 2.10 \\ VDCLS & 1.24 & 2.04 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Performance comparison between regular and VDCLS implementation. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline  & **Multicore (2 Cores)** & \multicolumn{4}{c}{**VDCLS**} \\ \hline  & **LUTs** & **FFs** & **LUTs** & **FFs** & **\% LUTs** & **\% FFs** \\ \hline processor system & 38842 & 27583 & 39460 & 28693 & +1.59 & +4.02 \\ processor coreplex & 28796 & 20932 & 29425 & 22042 & +2.18 & +5.30 \\ core 0 & 3102 & 2165 & 3162 & 2169 & +1.93 & +0.18 \\ core 1 & 3105 & 2165 & 3149 & 2169 & +1.42 & +0.18 \\ d where: \begin{tabular}{l l} _r(d)_: & correlation coefficient; \\ _x\({}_{i}\)_: & values of first variable; \\ _y\({}_{i}\)_: & values of second variable; \\ _n\({}_{i}\)_: & number of samples; \\ _d_: & the second variable offset. \\ \end{tabular}   
The comparison of the execution correlation between master and slave cores in classic DCLS and VDCLS implementation using PC simulation is shown in Figures 10-15. For test purposes we choose several algorithms, such as AES (Advanced Encryption Standard), SHA (Secure Hash Algorithm), ECDSA (Elliptic Curve Digital Signature Algorithm) and GF (Galois Field) used in security and cryptographic applications. As predicted, the classic DCLS shows a single strong peak with the maximum value at the delay of two clock cycles. It is caused by the fact that the slave core performs, cycle-by-cycle, exact the same toggles as the master core shifted by two clock cycles. On the other hand, in the VDCLS, even though the slave core executes the same software, the microarchitectural states are changing with more freedom. We can see more or less visible correlation peaks that never reach the maximum value and are located at different delays. Figure 11: Comparison of the execution correlation between master and slave CPUs using VDCLS and legacy DCLS technique while executing the HMAC-SHA algorithm. Figure 10: Comparison of the execution correlation between master and slave CPUs using VDCLS and legacy DCLS technique while executing the SHA algorithm. Figure 14: Comparison of the execution correlation between master and slave CPUs using VDCLS and legacy DCLS technique while executing the EDCSA key compression algorithm.