## 1 Introduction  
Polycrystalline silicon (poly-Si) thin film transistors (TFTs) [1; 2; 3; 4] and oxide semiconductor TFTs [5; 6; 7; 8] are suitable for use in system-on-panels (SoP) or system-on-glass (SoG) displays because of their higher electron mobility compared with that of amorphous silicon (a-Si). The attraction of using poly-Si TFTs in displays lies in their ability to integrate peripheral functional components such as a controller, a high-voltage driver, and memory into the display panel. Improving the breakdown characteristics of poly-Si TFTs has become an important issue for realizing SoP. To improve these breakdown characteristics, methods such as lightly doped drain [9; 10], offset drain [11; 12], and semi-insulating field plate [13; 14] were proposed. However, these methods increase the series resistances, and the ON-state current is sacrificed. A field-plate (FP) structure can increase the breakdown voltage, as well as the ON-state characteristics [15]. In this study, an FP was adopted to improve the breakdown characteristics without sacrificing the ON-state current. The carrier mobility of poly-Si TFTs can be improved by scaling the channel length, which results in a decrease in the number of grain boundaries, i.e., an increase in the grain size in the active region [16]. However, the short channel effect is exacerbated as the channel length decreases. Three-dimensional (3-D) multi-gate structures, such as double-gate, tri-gate, and gate-all-around (GAA) structures, have been proposed to improve gate controllability and protect against the short-channel effects of nanoscale transistors [17; 18; 19; 20; 21; 22; 23; 24]. Therefore, a tri-gate fin-like structure with a channel length (\(L\)) of 0.2 \(\upmu\)m was employed in this study. For a two-dimensional conventional planer structure, transverse band-to-band tunneling (T-BTBT) in the gate/drain overlap region is the dominant mechanism for gate-induced drain leakage (GIDL)in the OFF-state [25; 26; 27]. However, for a 3-D structure such as a fin-like TFT (FinTFT) with a narrow channel wire width, band overlap between the valence band of the body and the conduction band of the drain region enables substantial lateral band-to-band tunneling (L-BTBT) of electrons from the body to the drain in the OFF-state [28; 29]. This indicates that the mechanism of GIDL is L-BTBT for a 3-D structure. Recently, some studies have focused on minimizing L-BTBT in 3-D structures [30; 31; 32; 33; 34]. A dual-metal gate-stack architecture for nanowire field-effect transistors (FETs) [30] or nanowire junctionless FETs [31] can lead to a reduction in the electric field at the channel-drain extension interface width, which reduces L-BTBT-induced GIDL. In addition, a nanowire junctionless-mode FET with a long extension (the length between the source/drain electrode and the gate edge) has a lower GIDL current than does a nanowire inversion mode FET owing to a low doping concentration at the drain and thus a broad tunneling width [32]. The effect of a gate sidewall spacer on GIDL was investigated by [PERSON] and [PERSON] [33]. A nanowire metal-oxide--semiconductor FET with high-\(\kappa\) spacer-like HfO\({}_{2}\) has a low OFF-state current because of the low-peak electric field at the channel-drain extension interface; the OFF-state current increases as the dielectric constant of the spacer is reduced [33]. Because the GIDL current largely depends on drain extension doping, the influence of the lightly doped drain on L-BTBT is crucial. A nanowire FETs with a lightly doped drain (LDD) has a low OFF-state current because of its increased tunneling width; the OFF-state current decreases as the LDD length increases [34]. In our previous studies, a lateral double-diffused metal oxide semiconductor (LDMOS) and an FP high-voltage TFT with multi-gate and a wide drain have been proposed. Both devices show a high breakdown voltage; low specific on-resistance; and superior electrical characteristics [35; 36].