# Compact Design and Impact Ionization: Utilizing Small-Sized Thyristors in a 4-Stage Marx Generator
## 2 Materials and Methods
The process to find the right impedance value for each stage was performed using LTSpice simulations, which allowed us to adjust said values for each stage. In the LTSpice model, all parameters--except for the impedance values of the transmission lines (\(Z\) in the model in Figure 5)--were fixed based on the schematic. The transmission line impedances were swept to identify the values that minimized signal reflections and improved current continuity. The time delay (Td) values for each stage were determined by the geometry of the setup and remained constant. Once the impedance values were determined, the trace widths were calculated accordingly to match the simulated impedance. Table 1 presents the calculated impedances and delays of the PCB pads on which the thyristors and capacitors were soldered. The impedance values (Z) were obtained using a FEMM model calculation [32] with the corresponding dimensions. The resulting values are design approximations, as the calculations do not account for the thyristors and capacitors that bridge the gaps between pads. The method for calculating the delay along an outer stripline on a PCB is based on the method outlined in [33]. The adjustment of the pad width was made to address variations in the characteristic impedance of the transmission lines. The modulation of impedance was performed to ensure smooth current continuity across the stages. For the initial stage comprising six SiC thyristors, the impedance was calculated as \(21/6=3.5\,\Omega\), resulting in a current of \(\approx\)371 A at a voltage of \(1.3\,\mathrm{kV}\). In the first Marx stage, the voltage doubles (\(1.3+1.3=2.6\,\mathrm{kV}\)), necessitating the impedance to also double to maintain the same current. Similarly, the second Marx stage doubles the voltage again (\(2.6+2.6=5.2\,\mathrm{kV}\)), requiring the previous impedance to double. The third stage adds \(3.9\,\mathrm{kV}\), resulting in a final voltage of \(9.1\,\mathrm{kV}\), which would require an impedance of \(24.5\,\Omega\) to maintain the same current. In practical implementation, however, losses such as voltage drops across thyristors and capacitors were observed, resulting in slightly lower voltages than the calculated values. Consequently, \begin{table}
\begin{tabular}{l c c c c c} \hline \hline  & **Width (mm)** & **Length (mm)** & \(\mathbf{Z_{calculation}}\) (\(\Omega\)) & \(\mathbf{Z_{femm}}\) (\(\Omega\))** & **Delay (ps)** \\ \hline \(1\times\) SiC MOSFET trace & 10 & 120 & 21 & 21 & 780 \\ \(6\times\) SiC MOSFET traces & \(6\times 10\) & 120 & 3.5 & 4 & 780 \\ First [PERSON] stage & 30 & 60 & 7 & 8 & 125 \\ Second [PERSON] stage & 20 & 60 & 14 & 12 & 226 \\ Third [PERSON] stage & 13 & 60 & 24.5 & 17 & 345 \\ Fourth [PERSON] stage & 13 & 60 & 24.5 & 17 & 345 \\ \hline \multicolumn{5}{c}{PCB} \\ \multicolumn{5}{c}{parameters} \\ \hline Dielectric constant FR4 & 4.5 \\ FR4 thickness (mm) & 1.55 \\ Copper thickness (\(\mu\)m) & 35 & & \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Summary of impedance values from LTSpice calculations (\(Z_{calculation}\)) and field calculations using FEMM for the PCB design (\(Z_{FEMM}\)). the impedance was deliberately set approximately 5% lower than the theoretical value at each stage to account for these losses. Figure 6 illustrates the physical layout of the Marx generator stages, including the placement of capacitors C3\({}_{1}\) to C3\({}_{5}\), which connect the D2 PAK thyristors \(T3_{1}\) to T3\({}_{9}\), as well as the charging resistors (\(R3_{1}\) to R3\({}_{9}\)). The load \(R3_{10}\) is not shown in this figure. The traces connecting these thyristors are routed with controlled impedance to ensure consistent signal transmission, following the dimensions specified in Table 1.  
To determine whether an impedance-controlled solution would benefit our design by reducing reflections within the circuit, we conducted an LTSpice simulation comparing a non-controlled configuration with a controlled transmission line impedance configuration (Figure 5).