## 3 Our Dedicated and Scalable Multiplier Architectures
### Scalable Multiplication Architecture  
For NIST-defined binary fields over \(GF(2^{163})\) to \(GF(2^{571})\), our scalable polynomial multiplication architecture is shown in Figure 7. It consists of a finite state machine (FSM), a multiplier block and a reduction block. Details of these blocks are as follows. Figure 5: Digit-parallel multiplier over \(GF(2^{409})\). Figure 6: Least significant digit-parallel multiplier over \(GF(2^{571})\). **FSM. ** The FSM of our scalable architecture incorporates four states, i.e., (i) \(RESET\), (ii) \(START\), (iii) \(MULT\) and (iv) \(RED\). Before starting polynomial multiplication, the \(RESET\) state is responsible for setting the corresponding pipeline registers of input polynomials \(A(x)\) and \(B(x)\). The purpose of the \(START\) state is to load \(m\)-bit right input polynomials into the corresponding pipeline registers (\(A_{REG}\) and \(B_{REG}\)). After providing the correct input polynomials, the next state, i.e., \(MULT\), specifies the execution of two \(m\)-bit polynomial multiplication to generate a \(2\times m-1\)-bit polynomial. Finally, the \(RED\) state confirms the computation of a polynomial reduction based on a three-bit \(sel_{RED}\) signal. Each state of the FSM bears one clock cycle for computation. Therefore, our scalable architecture performs one NIST-recommended polynomial multiplication in four clock cycles. **Multiplier block. ** Similar to our dedicated digit-parallel multiplication architecture over \(GF(2^{571})\), a total of seventeen 32-bit and one 25-bit digit(s) have been used in our scalable architecture for the implementation of a polynomial multiplication over \(GF(2^{163})\) to \(GF(2^{571})\), as presented in Figure 7. The use of seventeen 32-bit and one 25-bit digit(s) allows us to perform multiplications over the remaining NIST-defined binary fields, i.e., 163, 233, 283 and 409. As mentioned earlier, before starting multiplication, it is essential to reset the pipeline registers (\(A_{REG}\) and \(B_{REG}\)) used in our scalable architecture. After resetting these pipeline registers, the correct input operands will be loaded. The length of input operands is not relevant to our multiplier architecture. However, for each respective binary field length (i.e., 163, 233, 283, 409 and 571), our scalable architecture will operate on 571 bits. For example, for a 163-bit operand length, our scalable architecture takes two 571-bit operands as input and results in \(2\times 571-1\) bit as output. Out of these 571-bit inputs, the initial 163 bits (from the least significant side) are correct, while the remaining bits from 164 to 571 will be 0. Similarly, in the output polynomial of length \(2\times 571-1\), the first 326 bits are correct while other bits from 327 to the end will be 0. Based on this principle, our scalable architecture performs polynomial multiplication. Inside M1 to M18 multipliers, a schoolbook logic of Equation (2) is inferred for multiplications. More precisely, we have generated dedicated partial products using logical AND operation. In the end, an exclusive (OR) operation has been performed on the corresponding bits of each generated partial product to produce a resultant polynomial of length \(32+571-1\) (for M1 to M17 multipliers) and \(25+571-1\) (for M18 multiplier), respectively. After the multiplication of each digit of polynomial \(B(x)\) with the 571-bit input  
Figure 7: Block diagram of our proposed scalable multiplier architecture for NIST-recommended binary fields. Our scalable multiplier design incorporates the least-significant digit-parallel multiplication approach. polynomial \(A(x)\), we have performed a concatenation operation to generate the resultant polynomial of length \([(2\times 571)-1]\) bits. **Reduction block. ** The reduction block of our scalable architecture incorporates five instances each for Algorithms A1-A5. Each instance takes the same polynomial of length as input and results one polynomial as an output. Thus, we have five instances, and then we have five outputs.