## 3 Results
The FSM synthesis is continued using Quartus software version 23.1, which utilizes the Verilog description generated previously. This Verilog file is then synthesized using Quartus with the User Encoded mode selected to ensure that the state encoding adheres to the specified Verilog code. During the synthesis process, Quartus Prime compiles the Verilog code, optimizes the logic, and maps it onto the FPGA architecture. The software generates detailed reports covering various aspects of the synthesized design, including area utilization and performance metrics. The area utilization report indicates the number of logic elements, registers, and other FPGA resources used by the FSM implementation, providing insights into resource efficiency. The timing analysis report includes the maximum operating frequency of the synthesized FSM, highlighting the performance capabilities of the design. This research involved comparing the synthesis results obtained using the custom state encoding application with those achieved using the built-in Sequential encoding mode offered by Quartus. The comparison focused on key parameters, highlighting the differences in area and performance, demonstrating the effectiveness of the proposed methods in optimizing FSM implementations. The experimental results are summarized in Tables 1 and 2. Both tables include columns corresponding to different encoding modes, determined by combinations of SS_mode, which refers to the state selection mode (P, C, P_C, max_C, or max_X), and CS_mode, indicating the code selection mode (FPGA, CPLD, diff_w, max_w). The results in both tables summarize the following rows: Best, which denotes the number of best solutions; Unique, which counts the number of unique best solutions not achieved by other encoding methods; Avg, representing the mean value of the parameter; and Max, the maximum value of the parameter. Table 1 is dedicated to evaluating area efficiency. It includes metrics such as Ls, which represents the area value (number of FPGA logic elements) for Quartus Sequential mode encoding, and Lmin, the minimum area value for the given example. The ratio Ls/Lmin indicates the area efficiency compared to the Sequential mode. Table 2 focuses on performance metrics. The specific columns in Table 2 are Fs, which represents the performance value (maximum operating frequency in megahertz) using the Sequential mode of Quartus, and Fmax, the maximum performance value for the example. The ratio Fmax/Fs indicates the performance improvement compared to the Sequential mode. The Sequential mode is the state encoding method provided by Quartus. In this mode, the FSM states are sequentially encoded using binary codes of minimum length. This mode serves as a baseline for comparing the results obtained by the proposed state encoding methods. It should be noted that the max_P_FPGA method yielded unsatisfactory results and has therefore been omitted from the experimental findings. For the FSM examples considered, the results were identical for the CPLD and ASIC modes. Therefore, Tables 1 and 2 solely showcase the outcomes for the FPGA and CPLD modes. Furthermore, the state selection mode max_X was exclusively explored in conjunction with the FPGA code selection mode.