# Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division
## 4 General Architecture and Main Parts
### Part 2 Mantissa_Divide  
MANFISSA_DIVIDE is intended to accelerate the calculation and to reduce the number of multipliers (i.e., to increase the use rate of multipliers employed in MANFISSA_DIVIDE). Since SP, DP, and QP are three common FP formats in our architecture, 23, 52, and 113 are mantissa bit numbers of SP, DP, and QP with an implicit bit \"1\". Furthermore, customized precision can be adjusted into our architecture only if adjusting module Exception Judgement in PRECONFIG, 3:1 multiplexer (MUX) in MANFISSA_DIVIDE, and module Rounding Unit in NORMALLIZE. As the Predict-Correct algorithm demonstrated, first, MANFISSA_DIVIDE is to calculate the value of \(B\). Since \(m=11\) and \(t=3\), \(B=1/Y_{h}-\Delta Y/Y_{h}{}^{2}+(\Delta Y)^{2}/Y_{h}{}^{3}\). Traditional fast division algorithm looks up \(1/Y_{h}\), \(1/Y_{h}{}^{2}\), \(1/Y_{h}{}^{3}\),... in the table \(G_{1}\), \(G_{2}\), \(G_{3}\),... at the same time, which costs more areas and power. In our implementation, to accelerate the calculation of \(B\), Finite State Machine unit is employed with a Reciprocal Look-up Table. The least significant partial products can be truncated for high-order terms. The state transition diagram of Finite State Machine unit appearing in Figure 2 is listed in Figure 4.  
Figure 3: The architecture of Exception Judgement module. To be detailed, the procedure of every cycle is presented in Figure 5. Critical path of the design in this paper lies in a 34-bit \(\times\) 34-bit multiplier and Quotient Selection Unit, as demonstrated with red dotted lines in Figure 5.  
Figure 4: The state transition diagram of Finite State Machine unit. Figure 5: The procedure of cycles in Finite State Machine unit. The first cycle only looks up \(1/Y_{h}\) with low-10-bits of the divisor \(Y^{\prime}\)s high-11-bits in the Reciprocal Look-up Table, calculates  
\[deltaY\_Y=\Delta Y\times(1/Y_{h}) \tag{24}\]  
with a 116-bit \(\times\) 34-bit Multiplier where the product \(deltaY\_Y\) is truncated to 34-bit, and, then calculates  
\[B\_1\_Y2=deltaY\_Y\times(1/Y_{h}) \tag{25}\]  
with a 34-bit \(\times\) 34-bit Multiplier. In the second cycle, the 34-bit \(\times\) 34-bit Multiplier is employed again to calculate  
\[B\_1\_Y3=deltaY\_Y\times B\_1\_Y2. \tag{26}\]  
After that, we can obtain  
\[B=B\_1\_Y+B\_1\_Y2+B\_1\_Y3. \tag{27}\]  
In the next cycles, compute intermediate value \(X_{h}\times B\) with the 34-bit \(\times\) 34-bit multiplier where \(X_{h}\) is the leading 32 bits of \(X\), and, round the product result to obtain a 29-bit intermediate value \(q\_h\). Quotient Selection Unit, which contains the 116-bit \(\times\) 34-bit multiplier, realizes the multiplicative quotient selection method in order to attain the most approximative 32-bit quotient \(q\_32\) and the partial product \(tmp\_product\). The architecture of Quotient Selection Unit is shown in Figure 3:0 In Figure 6, the 116-bit \(\times\) 34-bit multiplier is employed again to calculate the product of 29-bit intermediate value \(q\_h\) and divisor \(Y\),  
Figure 3:1  
Merging module is used to generate a series of 8 sequential 32-bit possible quotients,  
Figure 3:2 Figure 3:3 Figure 3:4 Figure 3:5 Figure 3:6  
Figure 3:7 The architecture of Quotient Selection Unit module. Through addition and subtraction operations, 6 minor possible quotients  
\[ \begin{split} quotient\_m1&= quotient\_0-32^{2}d1,\\ \ldots\\ quotient\_m6&= quotient\_0-32^{2}d6,\end{split}  \tag{30}\]  
and 2 major possible quotients  
\[ \begin{split} quotient\_p1&= quotient\_0+32^{2}d1,\\ quotient\_p2&= quotient\_0+32^{2}d2\end{split}  \tag{31}\]  
are generated afterwards. All in all, there are 16 possible 32-bit quotients. The architecture of Partial Product Comparator is presented in Figure 7.  
1 in Figure 7 expresses different judging conditions for 16 MUX. For example, for the first MUX of _compare_0_, 1 expresses: _tmp_0_[19] && (_tmp_0_[18] | (_tmp_0_[17:0]) | _tmp_0_[20]); for the second MUX of _compare_1_, 1 expresses: _tmp_1_[19] && (_tmp_1_[18] | (_tmp_1_[17:0]) | _tmp_1_[20]).