# Understanding the Light Detection in an Integrated Novel Electrophotonic Wavesensor Photodetector
## 4 Electrical Behavior and Photodetection  
### Electrical Current  
In Figure 3a, the applied voltages on the drain, source, and substrate are 0 V (\(V_{B}=V_{S}=V_{D}=0\) V). The gate is biased in accumulation regime and its effect is just to avoid surface currents. The light is detected through the variation of the source to drain current produced by the absorption of the light directly into the depletion layer, below the extended waveguide core. The proposed device operates in Punch-Through regime. The lateral depletion zones of the source and drain overlap when the drain-source voltage \(V_{DS}\) reaches the Punch-Through voltage \(V_{PT}\), as illustrated in Figure 3c. An electric current from source to drain is established under this bias condition. As an approximation, the analysis  
Figure 2: Schematic of the wavesensor (WS). The red arrows represent the lighting from the nitride waveguide directly into the depletion layer. of the physics will be carried out in a substrate depth corresponding to the middle of source and drain. This reduces the analysis to two PN junctions separated by the depleted substrate below the gate area, as illustrated in Figure 3.  
Figure 3a shows the charge (Q), electric field (E), and voltage (V) profiles obtained under equilibrium conditions using the depletion approximation [26, 27, 28]. Donor and acceptor profiles are assumed to be constant in the N and P zones. The p-n junctions (drain-substrate and source-substrate) are considered abrupt. Under these assumptions, the charges on the depleted zones are as show in Figure 3, and comply with charge neutrality condition (1):  
\[qN_{A}x_{p}=qN_{D}x_{n} \tag{1}\]  
where \(x_{n}\) is the depletion width on the n-regions (drain and source) and \(x_{p}\) the depletion width on the substrate region. As drain and source are heavily doped, the depletion width has a larger extension inside the substrate. The junctions produce a built-in voltage \(V_{bi}\), as shown in Figure 3a. Since the electric charge is constant in the depletion zone, the electric field presents a linear profile with a maximum in the metallurgical junction. Calculating the integral of the electric field, a parabolic voltage profile can be obtained. Figure 3b shows the profiles when drain is biased. When drain-substrate junction is reversely biased, the depletion width is increased. The depletion width under reverse bias can be calculated using (2) [27,29]:  
\[W_{D}=x_{n}+x_{p}\approx\sqrt{\frac{2\epsilon_{S}(V_{bi}+V_{DS})}{qN_{A}}} \tag{2}\]  
When \(V_{DS}\) = 0 V, the depletion width has an initial value called \(x_{j0}\), also showed in Figure 3. As \(V_{DS}\) increases, the depletion regions grow wider, to the point where Punch-Through is reached at \(V_{DS}\) = \(V_{PT}\). That is, both depletion regions overlap. The Punch-Through voltage (\(V_{PT}\)) can be calculated using (3). \[V_{PT}=\frac{qN_{A}L^{2}}{2\epsilon_{S}}-V_{bi} \tag{3}\]  
Figure 3c shows the profiles when \(V_{DS}\) > \(V_{PT}\) and Punch-Through is assured. The substrate region under the gate is fully depleted. If \(V_{DS}\) continues increasing beyond \(V_{PT}\), the electric field increases enough to act on the source-substrate junction. The drain voltage induces a reduction of the potential barrier between source and substrate, as depicted in the bottom of Figure 3c. This can be interpreted as an induced forward voltage on this junction. The barrier reduction and the high drain voltage promotes a current flow towards the drain  
Figure 3: Idealized scheme of the WS showing the charge, electric field and voltage profiles for the WS under thermal equilibrium (**a**), biased with \(V_{DS}\) < \(V_{PT}\) (**b**), biased with \(V_{DS}\) \(\geq\)\(V_{PT}\) (Punch-Through) (**c**). on Punch-Through regime.