# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 7 Conclusions  
Modern digital systems should be power-efficient. They should consume as little power as possible [3]. This is true for each block of a digital system. Obviously, this is true for various sequential blocks which play very important roles in digital systems. For example, control units operate in each cycle of a digital system operation. Very often, the sequential blocks are represented by finite state machines. In this survey, we mostly analyzed known methods of saving power for FPGA-based FSMs. There are two sources of power dissipation in CMOS-based circuits: static and dynamic. They have a different nature. The static power dissipation is connected with the imperfection of MOS transistors, which leads to the presence of leakage currents in the stable state of an FSM circuit. To decrease the static power consumption, it is necessary to reduce the chip area occupied by an FSM circuit. There are thousands and thousands of methods developed to solve this problem. Their analysis can be found, for example, in the survey [136]. The dynamic power consumption is connected with the existence of parasitic capacitors which must be charged or discharged during the state change of combinational and sequential elements creating FSM circuits. To reduce this component of the power consumption, it is necessary to diminish the switching activity of an FSM. Finally, the third approach for saving power is associated with an increase in the granularity of the circuit elements. In the case of FPGA-based FSMs, this path leads to the replacement of LUTs with embedded memory blocks. The existing methods can be divided into two groups: coarse-grained and fine-grained methods. The coarse-grained methods are general for all CMOS-based systems. The most popular coarse-grained methods are the voltage scaling and clock frequency scaling. These methods have some disadvantages. The main ones are: (1) the area overhead (to execute scaling, it is necessary to have some additional circuitry) and (2) the time overhead (to switch from reduced voltages or frequencies to normal ones, some time is needed, which is added to the total operation time required to complete the task of a digital system). Therefore, the coarse-grained methods can be used if a digital system based on them is able to complete the required task in a given time (the time should not exceed some deadline). The fine-grained methods take into account specifics of both FSMs and FPGAs. Three groups of these methods exist. The first of them is clock gating. The method is based on disconnecting synchronization pulses from some blocks of the FSM circuit. This can be achieved by either a decomposition of an initial FSM or by disabling the input. The second approach is based on a proper state assignment leading to reducing the switching activity of flip-flops. The third approach is based on replacing LUTs by EMBs. All these methods were analyzed in our current survey. The power saving could be reached by a twofold state assignment [137; 138], but this approach was out of the scope of our survey. We hope that the review will help broaden the horizons of experts in the field of sequential circuit design. A good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. All these methods were presented in our current survey. We hope that the review provides an extensive analysis of the history and current state of affairs in the field of reducing power consumption in FSM-based blocks of digital systems. In this regard, we think that the review may be used by designers of digital systems to (1) select the method most suitable for a particular project and (2) develop new methods to solve this problem. Conceptualization, A.B. and L.T. ; methodology, A.B. ; software, J.B.; validation, A.B. and L.T. ; formal analysis, A.B. ; investigation, J.B. and K.K. ; resources, J.B. and K.K. ; data curation, A.B. ; writing--original draft preparation, A.B. and L.T.