## 5 Implementation of Duffing Circuit Based on FPGAs  
In this section, an FPGA circuit is designed to simulate the periodic activity of Duffing oscillators and verify the periodic characteristics under the above parameters. The semi-analytic method is used to accurately judge the state and bifurcation point of the model, but it is not easy to implement in the FPGA circuit because of its large computation amount. The forward Euler method requires fewer resources and has a faster response time. The Euler method is used to discretize the dynamics equations of the Duffing model as follows:  
\[ \begin{cases}x(k+1)=y(k)\Delta t+x(k)\\ y(k+1)=(-\delta y(k)+x(k)-x^{3}(k)+Q_{0}\cos(\Omega\Delta t))\Delta t+y(k)\end{cases}  \tag{11}\]  
In Equation (11), \(x(k)\) and \(y(k)\) are discrete values of state variables at the current moment, \(x(k+1)\), \(y(k+1)\) are discrete values of state variables at the next moment, and \(\Delta t\) is the integration step size. \(\delta\) is the system parameter, and \(Q_{0}\cos(\Omega\Delta t)\) is the driving force signal. Due to the lack of direct support for decimal and differential operations in FPGA hardware, we utilize single-precision floating-point numbers in accordance with the IEEE-754 standard [26] for our computations. The model block diagram of the Duffing model in FPGAs is shown in Figure 8. In Figure 8, the function of the clock division module is to divide the external input clock (clk) into clk1 clock signals by internal count. The clk1 is connected to the DAC driver module as the clock signal for the DAC chip; clk is the clock signal for the variable-solving module and \(Q_{0}\cos\) module, respectively. The \(Q_{0}\cos\) module is used to store \(\cos\) values in a ROM register and continuously provide the corresponding \(\cos\) value based on the clock signal. The value of the cosine function is calculated according to the set integration step. Then, the pre-calculated internal driving force of the Duffing oscillator is converted into a \(\cdot\)mif file and stored in the fixed-size ROM. This allows for quick access through the look-up table method. Then, the \(Q_{0}\cos\) variable value is entered into the \(y\) variable-solving module for solving.The fdt data conversion module receives 32-bit data \(x(k+1)\) and \(y(k+1)\) from the variable-solving module as input. Then, it performs appropriate bit-width conversion, converting the 32-bit data into 14-bit data x_k1 and y_k1, often including truncation to ensure the output data range aligns with the range of the DAC chip. The task of the DAC driver module is to provide the clock signal for the DAC chip and output the variable value. The variable-solving module realizes the solution of Equation (11). In the design, the two state variables \(x(k+1)\) and \(y(k+1)\) are solved separately. The state variables at the current moment \(x(k)\) and \(y(k)\) are fed back to the variable-solving module as input for solving the state variable value at the next moment. Figure 7: Dual-parameter map (\(\Omega\), \(Q_{0}\)). In the computation module shown in Figure 9, three floating-point multipliers, one floating-point summator, and one floating-point subtractor serve as shared resources for all data operations. The solution for the discrete system is structured into five steps. Given that the 32-bit multiplier requires substantial area, we store data in registers after each calculation step. This approach enhances the module's maximum operating frequency by ensuring data stability and optimizing pipeline efficiency. The designed circuit model was simulated by Modelsim SE 10.5. The Modelsim simulation result of Duffing at period-1 motion is shown in Figure 10.  
We constructed a validation environment for the Duffing system as seen in Figure 11. The DAC module of the Duffing chaotic digital system is connected to an oscilloscope via a dual-ended cable with BNC connectors. The output of state variable x and y are connected to the oscilloscope.