# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 2 FSMs and FPGAs: Background Information
The register includes \(R\) memory elements (flip-flops) having shared inputs of synchronization (_Clock_) and reset (_Start_). Very often, master-slave D flip-flops are used to organize state registers [38; 39]. The pulse _Clock_ allows the functions \(D_{r}\in\mathrm{D}\) to change the RG content. After the execution of the state assignment, we should create a direct structure table. A DST includes all columns of an STT and three additional columns. These columns include the current state codes \(K(a_{m})\) and the codes \(K(a_{s})\) of the states of transitions. At last, a column \(\Phi_{h}\) includes the symbols \(D_{r}\in\Phi\) corresponding to ones in the code \(K(a_{s})\) from the row \(h\) of a DST (\(h\in\{1,\ldots,H\}\)). A DST is a base to construct the following SBFs:  
\[\Phi=\Phi(T,X); \tag{5}\]  
\[Y\ =\ Y(T,X). \tag{6}\]  
SBF (5) corresponds to function (1), SBF (6) to function (2). Systems (5)-(6) determine a structural diagram of a so-called P Mealy FSM (Figure 1) [39]. The combinational part consists of two blocks. The block of input memory functions generates functions (5). The block of outputs generates system (6). The pulse _Start_ writes the code of the initial state to RG. The pulse of the synchronization _Clock_ allows information to be written to the register. In this survey, we mostly discuss the RPC methods for FPGA-based Mealy FSMs. Let us shortly describe the peculiarities of FPGAs. As a rule, modern FPGAs have an \"island-style\" architecture [40]. They include different configurable logic blocks (CLBs) and a matrix of programmable interconnections [23; 24; 25]. To implement an FSM circuit, we can use either CLBs consisting of look-up table (LUT) elements or embedded memory blocks (EMBs). The output of a LUT can be connected with a flip-flop through a dedicated multiplexor. The flip-flops are necessary for implementing register circuits of sequential blocks [6]. This register is distributed among the LUTs implementing IMFs. The EMBs are synchronous blocks; thus, there is no need for an additional register to keep FSM state codes. A LUT consists of SRAM cells and can keep a truth table of an arbitrary Boolean function having up to S\({}_{L}\) arguments [40; 41]. The main feature of a LUT is an extremely small number of inputs, S\({}_{L}\). In modern FPGAs, the number of LUT inputs does not exceed six [23; 24; 25]. If some Boolean function depends on more than S\({}_{L}\) arguments, it should be transformed using some methods of functional decomposition [41]. It results in multi-level FSM circuits with irregular systems of interconnections. Such circuits resemble programs based on an intensive use of \"go-to\" operators [42]. Using terminology from programming, we can say that the functional decomposition produces LUT-based circuits with \"spaghetti-type\" interconnections. A chip area occupied by a LUT-based FSM circuit is determined mostly by the number of LUTs and the system of their interconnections. Obviously, to reduce the occupied area, it is necessary to reduce the number of LUTs in a circuit. The number of LUTs also influences the power consumption. As noted in [43], \"process technology has scaled considerably... with current design activity at 14 and 7 nm\". Hence, interconnection delay now dominates logic delay [43]. Also, it is known that interconnections are responsible for consuming up to 70% of the energy [40; 44]. Thus, to reduce the consumed energy, it is necessary to reduce the number of interconnections. This improves both the operating frequency and power consumption. Modern FPGAs include a lot of configurable embedded memory blocks [25]. The EMBs allow the implementation of systems of regular functions [45]. The replacement of LUTs by EMBs allows one to significantly improve the characteristics of resulting FSM circuits [46]. Because of it, there are a lot of design methods targeting EMB-based FSMs [22; 46; 47; 48; 49; 50; 51; 52; 53; 54; 55; 56]. The survey of different methods of EMB-based design can be found in [45].