## 1 Introduction  
The reliability of aerospace electronic equipment is increasingly crucial as its role in various applications expands. With advancements in semiconductor processing technology, the prevalence of both permanent and temporary faults, including transient and permanent errors, has risen significantly [1, 2]. This issue is particularly acute for electronic equipment operating in space, where exposure to various types of radiation is a major concern. Failures in electronic equipment due to radiation are primarily classified into the following two types: total ionizing dose (TID) and single-event effect (SEE) failures [3]. While regular replacement cycles can mitigate the hard errors caused by TID, soft errors resulting from SEE are random and temporary, rendering them unresolvable through replacement cycles alone. Consequently, evaluating the impact of soft errors in advance becomes crucial. The soft error rate (SER) is a key metric used to assess the likelihood of soft errors occurring per hour [4]. The most direct and traditional method of calculating SER is testing at a radiation facility [5; 6; 7]. These methods evaluate the soft error of a board by exposing it to ionized particles using a particle accelerator. This is called the Hardware Fault Injection Approach and is mainly divided into ion and laser methods, depending on the type of particle. The Hardware Fault Injection Approach provides benefits in terms of speed, low complexity, and the ability to perform accurate SER evaluations from a system perspective. However, there are also challenges associated with this evaluation method, such as its high cost, the inability to reproduce test results, and difficulties in conducting a detailed analysis, such as fault propagation analysis. To reduce the issue of high radiation test costs, various approaches to simulation fault injection are being studied. The software fault injection method evaluates the soft error rate (SER) by implementing a fault model in a circuit simulator, such as TCAD or SPICE, at the Verilog/VHDL RTL level [8; 9]. The methods are low-cost and can provide more accurate sensitivity analysis because they can calculate both the defect injection rate and the injection location. However, recent System-on-Chip (SoC) level components have high circuit complexity, which increases the analysis time and complexity. To address the limitations inherent in hardware and software approaches, the development of emulation-based fault injection tools is underway. This method entails the artificial simulation of single-event upsets (SEUs) on the actual target board [10; 11; 12]. Emulation fault injection offers results that are comparable to hardware methods, while also providing the cost efficiency and test reusability commonly associated with software methods. Nonetheless, this approach presents its own set of challenges, including the need to establish an emulation testing environment, the requirement of a comprehensive understanding of the target board, and complexities in implementation. To overcome these challenges, more user-friendly and accessible emulation-based fault injection tools are under development [13; 14]. These tools are designed to enable fault injection testing across a wide variety of FPGA configuration memories. However, the extensive range of this fault injection testing method may introduce difficulties in analyzing the failures that specifically reflect the characteristics of the target circuit. In this study, we developed an Automatic Configuration Memory Fault Injection (ACMFI) tool to estimate the SER of an avionics board. The tool injects a bit-flip error into the configuration memory of an SRAM-based FPGA board. The ACMFI tool optimizes the fault injection process in FPGAs and allows for the easy creation of a test environment by utilizing an open library (SEM IP) without the need to modify the target circuit.