# Interference Mitigation for GNSS Receivers Using FFT Excision Filtering Implemented on an FPGA
## 2 Related Work
The performance of transform domain interference suppression in GNSS receivers based on fractional Fourier transform (FrFT) with an adaptive threshold was presented in [34]. However, the limitation of their proposed algorithm is the adaptive selected threshold, which was unable to handle a wide bandwidth of inter ference. As a result, this distorts the desired signal when spectral components suppress the interference. The results of the proposed algorithm worked with up to 45 dB (_J/No_) of the CW jammer. On the other hand, our proposed FFT mitigation algorithm works with wideband interference and the results demonstrated that our algorithm has the capability to suppress more than 100 dB (J/No) of the CW jammer without distortion of the original signal. The disadvantage of the FFT excision has been related to the complexity of the implementation in the receiver hardware. However, efficient computation of FFTs is now common in almost all receiver architectures and possible in low-power ASICs for the mass-market [35]. The hardware implementation of interference mitigation using FFT algorithms has not been extensively explored in the literature. It can be deduced from the literature review that the current studies have focused on interference mitigation algorithms in terms of software simulations and only a few studies have focused on hardware implementations. In [36], the authors proposed a high-rate DFT-based data manipulator (HDDM) algorithm with different FPGA-based GNSS dual-band receivers. These receivers were pre-selected based on the number of bits ADC. They used 4, 8, and 14 bits ADC. This algorithm only works against the pulsed interference, with suppression of 50 dB JSR. However, HDDM has shown disappointing results for simple CW interference due to its limited selectivity of frequency and limited robustness of HDDM. The authors mentioned that to overcome this challenge, a notch filter has to be combined with the HDDM algorithm. This research work is extended in [37] by suggesting HDDM with AGC instead of pulse blanking (PB) to overcome the challenge of removing parts of the signal in the presence of wideband noise interference. HDDM-AGC has real-time FPGA implemented on a wideband receiver. The limitation of this study is the test setup by 1-bit DAC used by the R&S up-converter. This introduces a significant quantization loss, which results in a \((C/No)\) loss of 6 dB. Therefore, the main aim of this paper was to assess the complexity and feasibility of the FFT excision filter implementation in current FPGA technology. Additionally, we aimed to overcome the challenges encountered in the previous research. The proposed FFT excision filter algorithm has the capability to work with different types of GNSS interference such as narrowband interference, wideband interference, CW interference, pulsed CW interference, and sweeping interference. The estimation of jammer characteristics often requires FFT even if a different technique is used for interference removal. Compared to the EMD and wavelet filter, they have not convincingly shown better performance results than the FFT excision filtering algorithm. Additionally, the complexity is expected to be much higher due to their high computing requirements, so they were not considered for hardware implementation. For these reasons, FFT excision filtering was used in this research work to mitigate the influence of interference on the GNSS receiver and enhance its performance for tracking and navigation operations. The proposed interference mitigation algorithm demonstrated a significant performance improvement \((~{}C/No~{})\cong\) 40 dB) compared to other algorithms, developed in the software simulations, and implemented in FPGA hardware.