# Charge Carrier Distribution in Low-Voltage Dual-Gate Organic Thin-Film Transistors
## Materials and Methods  
### Device Fabrication  
Schematic structure and photograph of the fabricated OTFT devices are shown in Figure 1. Single- and dual-gate OTFTs were integrated on a glass substrate, as shown in Figure 1a,b. Note that for the DG devices, the bottom- and top-gate electrode was connected each other. All layers except the gate dielectrics were formed by printing processes at process temperatures below 150 \({}^{\circ}\)C [21; 22]. 140-nm-thick parylene films that were formed by chemical vapor deposition (CVD) were used as the gate dielectric and encapsulation layer. Parylene is good for low-voltage operation due to its low trap density [23] and fine thin-film formation [24]. The electrodes were fabricated by inkjet printing of a silver nanoparticle ink. Formation of the short-channels was enabled by separate printing of the source/drain electrodes as reported [25]. In this work, the standard deviation in channel length was \(\pm\)2 \(\upmu\)m. A printed fluoropolymer layer was used as a confining bank layer, whereby the semiconducting layer was printed in the area defined by the bank layer using dispenser equipment. These device fabrication processes used drop-on-demand printing techniques such as ink-jet printing and dispenser printing for ease of the layout customization.  
Figure 1: (**a**) Schematic structures, (**b**) photograph and (**c**) layout of fabricated organic thin-film transistor (OTFT) devices.  
Cross-linked poly(4-vinyl-phenol) (PVP) was formed on 0.5-mm-thick glass substrates to modify the surface wettability. PVP (\(M_{\rm W}\approx\) 25,000, Sigma-Aldrich, St. Louis, MI, USA) and poly(melamine-co-formaldehyde) (\(M_{\rm N}\approx\) 432.84 wt %, Sigma-Aldrich, St. Louis, MI, USA) were dissolved in propylene glycol monomethyl ether acetate (PGMEA), and spin-coated onto the substrates, followed by annealing process at 150 \({}^{\circ}\)C for 30 min. in ambient air to produce thermal-crosslinking. Next, a silver nanoparticle ink in hydrocarbon-based solution (NPS-JL, Harima Chemicals, Chuo-ku, Tokyo, Japan) was printed as bottom-gate electrodes using an inkjet printer (DMP2831, Fujifilm Dimatix, Santa Clara, CA, USA) with 10 pl nozzles. During the inkjet printing process, the substrates and cartridge were kept at 50 and 40 \({}^{\circ}\)C, respectively. The substrates were then heated at 150 \({}^{\circ}\)C for 15 min. in ambient air to sinter the silver nanoparticles. A 140-nm-thick parylene (diX-SR, KISCO, Tokyo, Japan) gate dielectric layer was then formed by chemical vapor deposition. Source and drain electrodes were subsequently printed in the same manner as the gate electrodes. The conditions of S/D printing and sintering process were same as those for the gate electrodes. Fluoropolymer (DuPont, Teflon AF1600) bank layers (70 nm thick) were then printed using a dispenser system (MUSASHI Engineering, Image Master 350 PC) at a pattering speed of 20 mm\(\cdot\)s\({}^{-1}\) and with a discharge pressure of 6 kPa. During the dispensing process, the plates and nozzle temperatures were kept at 60 and 30 \({}^{\circ}\)C, respectively. A p-type donor-acceptor polymer semiconductor ink (0.03 wt %, mestilbene solvent, Mitsubishi Chemical, MOP-01) was then printed onto the area defined by the bank layer by the dispenser system at a patterning speed of 20 mm\(\cdot\)s\({}^{-1}\) and discharge pressure of 2 kPa, while keeping the stage and nozzle temperatures at 60 and 30 \({}^{\circ}\)C, respectively, followed by an anneal at 150 \({}^{\circ}\)C in nitrogen globe box for 1 h to remove the solvent. 10-nm-thick semiconducting layer was obtained. Then, a 140-nm-thick parylene (diX-SR, KISCO, Tokyo, Japan) gate dielectric layer was then formed by chemical vapor deposition. Finally, top-gate electrodes were printed and sintered in the same manner as the bottom-gate electrodes.