# Two-Terminal Electronic Circuits with Controllable Linear NDR Region and Their Applications
## 3 Two-Terminal NDR Circuits  
Figure 1 shows a two-terminal electronic circuit with a controllable NDR region. The circuit comprises a voltage divider \(R_{c}\), \(R_{d}\), an n-channel FET \(T_{0}\), a current mirror with \(m\) (\(m\) = 0, 1, 2,...) additional outputs (mirrored current sources), and a power supply \(V_{1,2}\)  
The circuit of Figure 1 has N-type current-voltage characteristics between nodes 1 and 2, as shown in Figure 2. The slope of the NDR region in the current-voltage characteristics depends on the number (\(m\)) of the additional mirrored current sources \(I_{2}\). In Figure 2, the green curve corresponds to \(m=0\), the blue curve to \(m=1\), and the red curve to \(m=2\). As seen in Figure 2, the current-voltage characteristics have four regions. In the first (\(0\), \(V_{X}\)) and fourth (\(V_{Z}\), \(\infty\)) regions, the current \(I_{1}\) depends only on the voltage \(V_{1,2}\). In these regions, all transistors are off. In the second region (\(V_{X}\), \(V_{Y}\)), all transistors are on. Transistor \(T_{0}\) operates in the ohmic region, and current \(I_{1}\) increases. We should also note that the voltage \(V_{Y}\) does not depend on the value of \(m\), i.e., \(V_{Yi}=V_{Y}\), \(i=0\), \(1\), \(\ldots\), \(m\). In the third region (\(V_{Y}\), \(V_{Z}\)), transistor \(T_{0}\) operates in the saturation region and current \(I_{1}\) decreases due to a decrease in the gate-source voltage. The current \(I_{1}\) consists of two currents in the NDR region: the current through resistor \(R_{c}\) and \(m+1\) currents \(I_{2}\). The current through resistor \(R_{c}\) is due to power supply \(V_{1,2}\) and the drain-current \(I_{D}\) of transistor \(T_{0}\). Thus, the current \(I_{1}\) is given by  
\[I_{1}=(m+1)I_{2}+\frac{I_{D}R_{d}}{R_{c}+R_{d}}+\frac{V_{1,2}}{R_{c}+R_{d}}. \tag{1}\]  
Outside the region (\(V_{X}\), \(V_{Z}\)), the current \(I_{1}\) is only due to the power supply voltage \(V_{1,2}\). Figure 1: General two-terminal NDR circuit with multiple-output current mirror. Figure 2: Current-voltage characteristics of a two-terminal NDR circuit with multiple-output current mirror; \(m=0\)—green curve, \(m=1\)—blue curve, \(m=2\)—red curve. Further, we assume the matching of all transistors in the multiple-output CMs. As is well-known [40], for large transistor dc gain \(h_{FE}\), the currents \(I_{2}\) and \(I_{D}\) are approximately identical. The magnitude of the difference in currents \(I_{2}\) and \(I_{D}\) depends on the selected CM. Figure 3 shows a two-terminal NDR circuit with the multiple-output cascode CM (MCCM). The following relation links currents \(I_{2}\) and \(I_{D}\)[41]:  
\[I_{2}=I_{D}\Bigg{(}1-\frac{4h_{FE}+2}{h_{FE}^{2}+4h_{FE}+2}\Bigg{)}. \tag{2}\]  
By substitution (2) to (1), we obtain the total current in the NDR region:  
\[I_{1}=I_{D}\Bigg{[}\frac{(m+1)}{1+4/h_{FE}+2/h_{FE}^{2}}+\frac{R_{d}}{R_{c}+R_{ d}}\Bigg{]}+\frac{V_{1,2}}{R_{c}+R_{d}}. \tag{3}\]  
The advantage of using cascode CM in the two-terminal NDR circuit is its high output resistance. The disadvantage is a mismatch between currents \(I_{2}\) and \(I_{D}\). Figure 4 shows a two-terminal NDR circuit using MWCM. With finite Early voltage \(V_{A}\), the currents \(I_{2}\) and \(I_{D}\) are related as follows [41]:  
\[I_{2}=I_{D}\Bigg{(}1-\frac{2}{h_{FE}^{2}+2h_{FE}+2}\Bigg{)}\left(1-\frac{V_{EB3 }}{V_{A}}\right), \tag{4}\]  
where \(V_{EB3}\) is the emitter-base voltage of transistor \(T_{3}\). Substituting (4) to (1) gives the following equation for the total current in the NDR region:  
\[I_{1}=I_{D}\Bigg{[}(m+1)\Bigg{(}1-\frac{2}{h_{FE}^{2}+2h_{FE}+2}\Bigg{)}\left( 1-\frac{V_{EB3}}{V_{A}}\right)+\frac{R_{d}}{R_{c}+R_{d}}\Bigg{]}+\frac{V_{1,2} }{R_{c}+R_{d}}. \tag{5}\]  
The advantage of using MWCM in the NDR circuit of Figure 1 is high output resistance and a slight mismatch between master branch current (\(I_{D}\)) and slave branch current (\(I_{2}\)). The disadvantage is the difference in collector-emitter voltages \(V_{EC1}\) and \(V_{EC2}\), which is equal to voltage \(V_{ER3}\).