## 5 Experimental Results  
The proposed circuit was fabricated in a 130 nm CMOS process. A photograph of the manufactured die is shown in Figure 4. As in Figure 1, one column of ID cells shared a single SA, with 32 ID cells per column. A shift register is used to generate the row select signal, and each shift register is shared by 32 columns to for a 32 \(\times\) 32 array. Fifteen of these arrays are contained on each die, for a total of 15,360 ID bits per die. One 32-bit column, including the SA, occupies an area of 68.5 \(\times\) 4.3 \(\upmu\)m. For measurement, the value of \(V_{DD}\) was 400 mV. For each ID cell, the value of \(p\) was determined by reading from the cell 1000 times, and counting the number of results equal to \"1\". To find the value of the threshold voltage mismatch, \(\Delta V_{T}\) in the ID cell, the gate of M1 was held fixed, and the gate of M2 was swept in 1 mV increments. At each increment, the ID cell was read 100 times. From these two measurements, the relationship between \(p\) and \(\Delta V_{T}\) was  
Figure 4: Photograph of random ID chip with 15,360 ID bits, fabricated in 130 nm CMOS process. determined, and plotted in Figure 5. From this data, the value of the input referred voltage noise, \(\sigma_{V_{in}}\), was determined to be 1.5 mV. If a reliability threshold of \(\epsilon=10^{-10}\) is chosen, Equation (10) indicates ID cells with \(|\Delta V_{T}|>10\) mV will behave reliably. Of the fabricated ID cells examined, \(82\%\) satisfy this inequality and can be classified as reliable (\(p_{U}=0.18\)). More generally, Figure 6 shows the relationship between \(|\Delta V_{T}|\) and the reliability threshold, and Figure 7 shows the fraction of unreliable bits for a given reliability threshold. The location of unreliable cells for an arbitrarily chosen 32 \(\times\) 32 array is shown in Figure 8. The unreliable cells are shown in black. The magnitude of \(\Delta V_{T}\) is also shown for the same array. This indicates that unreliable bits have random spatial distribution in the array. The measured distribution of \(\Delta V_{T}\) is shown in Figure 9, along with a Monte Carlo simulation of the same distribution. This shows the distribution of \  
The relationship between \(|\Delta V_{T}|\) and the reliability threshold depends on the value of \(\sigma_{V_{in}}\), which will vary in different technologies. Equation (9) shows that the required \(|\Delta V_{T}|\) is linearly related to \(\sigma_{V_{in}}\), _i.e._, a 10\(\times\) increase in \(\sigma_{V_{in}}\) would require a 10\(\times\) increase in the difference threshold \(|\Delta V_{T}|\) to maintain the same error threshold. This may reduce the yield, if the standard deviation of the threshold voltage is not also higher in the alternate technology. The energy consumption was measured to be 39 fJ/bit at a readout rate of 40 kBps. This is 23\(\times\) less than the next lowest published value of 930 fJ/bit [16]. The decreased energy consumption is likely due to the lower supply voltage, sharing of a single SA (which amortizes the SA leakage current), and the use of a shift register for sequential access rather than a row decoder. The effective area per bit (32-bit column and sense amplifier divided by 32), is 9.2 \(\upmu\)m\({}^{2}\). Figure 8: (**A**) Location of unreliable bits (\(|\Delta V_{T}|<10\) mV), shown in black, in a 32 \(\times\) 32 array of random ID cells. (**B**) Magnitude of \(|\Delta V_{T}|\) in the same array, where black is 0 mV and white is 50 mV. Figure 7: Fraction of manufactured bits that can be expected to be unreliable for a given threshold of reliability, \(\epsilon\). As previously noted, having a non-zero number of unreliable bits, \(U\), reduces the maximum number of addressable chips from the theoretical maximum of \(2^{N}\).