## 3 Design of the Proposed Solution
### Initial Network Discovery and Path Setup  
Initially, at time t\({}_{0}\), the port numbers of switches and links connecting them are discovered through the LLDP packet. Once this network information is discovered at t\({}_{1}\), the list of adjacent switches connected to each switch are formed and stored in a local data structure implemented in Algorithm 1 (line 1-4). Upon topology discovery, all the adjacent switches are obtained. For each switch, \(S_{i}\) a path routing table is maintained with a list of adjacent switches and all possible sets of \(P_{i}\) from source \(S_{i}\) to destination \(S_{j}\) as demonstrated in Algorithm 1 (line 5-7). For each adjacent switch, \(S_{i}\) to \(S_{j}\) the Link Latency (\(LL\)) and Link Delivery Ratio (LDR) is estimated and stored on each link as shown in Algorithm 1 (line 7-9). To calculate the \(LL\) and LDR, the controller creates a Special Ping Packet (SPP) and sends it to \(S_{i}\)-containing sequence no and time stamp. Consequently, \(S_{i}\) sends the SPP to \(S_{j}\) while \(S_{j}\) will forward the SPP back to the controller. These special packets are measured through the probe message at the discovery stage which is transmitted using a dedicated link before actual data transmission. The total LL time can be summarized as a combination of four parameters: Controller SPP generation time (\(T_{Pc}\)), controller to switch SPP creation time (\(T_{Pc,\text{-}Si}\)), \(S_{i}\) to \(S_{j}\) SPP forwarding time (\(T_{Psi\text{-}j}\)), \(S_{i}\) to controller SPP forwarding time (\(T_{Psi\text{-}c}\)). The \(LL\) for \(L_{i,j}\) is the summation of a lower and upper bound of the four parameters as shown in Equation (1). \[LL=\sum_{S_{i}}^{S_{j}}(\frac{T_{Pc}+T_{P,S-Si}+T_{P,Si-Sj}+T_{P,S-C}}{2}-C)+1 \tag{1}\]  
The \(LDR\) is defined as the ratio of received \(SPP\) to the sent \(SPP\) on both directions of a particular link as shown in Equation (2). Thus, the routing of delay-sensitive flows required the design of realistic metrics that incorporate link quality to meet up the application demand via a path with lower latency and a set of switches incurring lightweight update operation. As such, the total path latency \(PL\) is obtained by the summation of the \(LL\) on the set of links connecting source switches \(S_{i}\) link to the last link connecting destination switch \(S_{j}\) and the LDR as presented in Equation (3). \[LDR=\frac{No.\,of\,sample\,SPP_{Ack}}{No.\,of\,Sample\,SPP_{sent}} \tag{2}\]  
Figure 1: Architecture of the Route path selection Optimized scheme. \[PL=\sum_{src}^{dst}(min(LL))+(min(LDR)) \tag{3}\]  
Arrivals of new flow will trigger the scheme to compute a set of \(k\) = {P1, P2,..., Pn} such that \(P_{i}\in k\) is based on the summation of lower and upper bound from source switches to destination which in turn give the \(PL\). The values of \(LL\) and LDR are assigned to each \(P_{i}\) (Algorithm 1, line 19-24) and the updated set \(k\) is returned. The set \(k\) of \(P_{i}\) satisfying QoS requirement with minimum \(PL\) are considered as candidate paths which are used in the critical switches detection phase to choose the \(P_{i}\) with min set of switches.