# Smart Embedded System for Skin Cancer Classification
## 2 Background and Related Work
### Mapping CNNs on FPGAs  
Several custom designed FPGA accelerators have already been proposed in the past using hardware description languages with very efficient core units. In [13], a CNN accelerator with an average performance of 400 GFLOPS was implemented in a low-density ZYNQ7020 FPGA. These handwritten hardware accelerators are very efficient in terms of performance and energy. However, the design of hardware accelerators using hardware description languages to run a deep learning model is a time-consuming task and difficult to redesign for other network models. To avoid these long design times, designers started using high-level synthesis (HLS), which allows for the generation of hardware descriptions from the high-level specification of the algorithm in a programming language, like C, C++, OpenCL. Examples include the Xilinx Vivado HLS and the Intel FPGA OpenCL SDK. Convolutional neural networks are well-defined structures with well-defined configurable layers. This regularity permits the development of domain-specific tools to map CNN on FPGA and the exploration of the design space. The framework DNNWEAVER [14] automatically generates a Verilog description of an accelerator given a neural model and a target FPGA. The model is specified in Caffe [15] and the Verilog description uses hand-optimized templates. The framework includes an optimization tool to reorganize and batch the model operations to improve the utilization of internal resources of the FPGA. fpgaConvNet [16] is another framework that automatically maps CNNs onto FPGAs. The tool receives a high-level description model in a custom representation and maps the layers in a streaming architecture with one processing unit per layer. It considers the most common type of layers, like convolutional, dense and pooling, and accepts application constraints, including throughput and latency. DeepBurning [17] follows a similar structure but, instead of a fixed schedule generated at compile time, like in fpgaConvNet, it requires control logic to dynamically schedule the operations. FINNN [18] was designed by Xilinx and supports the automatic mapping of neural models onto ZYNQ SoC FPGAs. The tool generates a streaming architecture in HLS and is particularly efficient for the design of low-quantization network models. The computing resources per layer can be customized to specific throughput requirements of the designer. ALAMO [19] is a compiler that produces a configurable accelerator for the sequential implementation of layers in both FPGAs and application-specific integrated circuits (ASICs). The compiler automatically integrates computing primitives that accelerate the operations of deep neural models. It also optimizes the throughput for a given resource constraint. HLS4 ml [20] is an open-source software-hardware workflow used to automatically implement DNNs in FPGA or ASIC. The flow includes optimization techniques, like quantization and pruning, whose outcomes are supported by the automatic mapping on the target technology. The last version extends the tool to consider low-power implementations and a better reusability of the hardware. The designer controls the type of implementation to be generated, parallel or serial, and different precisions of the model are allowed. The performance, latency and resource utilization are the metrics considered in the design of the accelerator. Vitis-AI ([[https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html](https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html)]([https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html](https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html)), accessed on 22 January 2023) is a development platform for Xilinx devices used to generate an accelerator for the inference of deep neural network models. It supports models specified in Pytorch, TensorFlow and Caffe. The approach considers a specialized configurable hardware core that supports the sequential execution of the most common layers.