## 2 Circuit Design  
### Assembly and Interconnect Design  
For a quasi-MMIC PA design, the authors have the option to choose between flip-chip and CoB wire-bond assembly methods, as depicted in Figure 1. However, considering the target output power of 10 W, it becomes crucial to account for heat dissipation capabilities. Due to the complexity of attaching a heat sink on a flip-chip assembly during RF probing measurements, the authors opt for split and stack CoB wire-bond assembly methods, as shown in Figure 1b,c. In this approach, the substrate printed circuit board (PCB) and heat sinks will efficiently dissipate heat for the output-stage GaN transistors.  
For the Class-J output matching network (OMN) design, harmonic frequencies should be considered. In order to minimize the bandwidth impact of bond wire interconnects, a proper wire-bond configuration should be employed. There are several bond wire interconnect designs that can improve bandwidth [21; 22; 23]. However, those designs are for low-power signal traces. When it comes to high-power high-current design, multiple bond wires should be used. The different bond wire topologies are simulated using the Keysight Advance Design System (ADS) Momentum 3D finite element method (FEM). Figure 2 shows simulation settings of 300 \(\upmu\)m length bond wires with different quantities ranging from 1 to 5. The bond wire diameters are 1.0 mil, and the bond ball diameters are 55 \(\upmu\)m. As a result, the designed spacing between the bond wires is 100 \(\upmu\)m. Therefore, the designed bond pad lengths are 50 \(\upmu\)m, and the widths range from 50 \(\upmu\)m to 450 \(\upmu\)m.  
The 3D FEM simulated results of 300 \(\upmu\)m length bond wire designs are shown in Figure 3. Figure 3a,b displays the \(\left|\text{S}_{11}\right|\) and \(\left|\text{S}_{21}\right|\) of different designs with different quantities of bond wire. At first, one-bond-wire design, which has the highest inductance, is the worst in \(\left|\text{S}_{11}\right|\) and \(\left|\text{S}_{21}\right|\). When the quantity is increased to 2 and 3, the results  
Figure 1: The candidates for assembly method: (**a**) flip-chip assembly; (**b**) split CoB wire-bond assembly; and (**c**) stack CoB wire-bond assembly.  
Figure 2: The 3D FEM simulation settings of different quantities of 300 \(\upmu\)m length bond wires: (**a**) one bond wire; (**b**) two bond wires; (**c**) three bond wires; (**d**) four bond wires; and (**e**) five bond wires.  
are better. When the quantity is increased to 4 and 5, the results are worse. Thus, the three-bond-wires design has the best results both in \(\mid\)S\({}_{11}\)\(\mid\) and \(\mid\)S\({}_{21}\)\(\mid\). Figure 3c displays the \(\mid\)S\({}_{11}\)\(\mid\) trajectory in the Smith chart, which is similar to [21]. The bond pad widths increase with the bond wire quantity. Therefore, the parasitic capacitances also increase. The imaginary parts of one- and two-bond-wires designs go positive. On the other hand, the imaginary parts of four- and five-bond-wires designs go negative. The three-bond-wires design has the best combination of inductances and capacitances. Although the three-bond-wires design's bandwidth is narrower than [21], the total chip area is much smaller. Therefore, the 300 \(\upmu\)m length three-bond-wires design can facilitate high-current capacity and wide bandwidth at the same time.  
Figure 4 shows the 3D FEM simulated results of 400 \(\upmu\)m length bond wire designs with different bond wire quantities ranging from 1 to 5. The three-bond-wires design yielded the best results both in \(\mid\)S\({}_{11}\)\(\mid\) and \(\mid\)S\({}_{21}\)\(\mid\). Although the bandwidth of 400 \(\upmu\)m length design is narrower than that of 300 \(\upmu\)m length design, it is still appropriate for current circuit design. Thus, the following design steps could use three bond wires with 300-400 \(\upmu\)m lengths.