## 2 Circuit Design
\begin{table}
\begin{tabular}{c c c c c} \hline \(L_{eq1}\) & \(k_{1}\) & \(C_{in}\) & \(L_{eq2}\) & \(k_{2}\) \\
751 pH & 0.73 & 57 fF & 312 pH & 0.66 \\ \hline \(C_{m}\) & \(L_{eq3}\) & \(k_{3}\) & \(C_{out}\) & \(L_{s}\) \\
195 fF & 475 pH & 0.81 & 79 fF & 161 pH \\ \hline \end{tabular}
\end{table} 
Table 1: Component values used in the proposed LNA. Figure 1: Schematic of the proposed fully differential 2-stage LNA with transformer-based interstage matching networks. The Global Foundries 45-nm RFSOI PDK is used to design the layout of the transformers. The design kit offers 7 copper (Cu) layers (M1-M3, C1, UA, OA, OB) and a 4.125-\(\upmu\)m thick aluminum (Al) layer. The OB and OA metal layers are used to implement all the inductors since they are composed of copper lines with the same thickness (3 \(\upmu\)m), which facilitates the equalization of inductors. That is, it facilitates the obtention of the same inductance and quality factors of the windings of the primary and secondary inductors [16]. Since the transistors are placed on the substrate and the passive components are generally implemented in the top metal layers to obtain the highest quality factor (\(Q\)) possible, a number of vias and interconnections have to be added to bring the connections of the gate, source, and drain terminals from the low, thin metal layers to the top, thick layers. So as to account for the effect of these metal interconnections on the LNA performance, we developed the layout of the selected transistor early in the design procedure to consider these effects [17]. The 3D view of the developed layout is presented in Figure 3a and the front view of the same layout is shown in Figure 3b. To prepare the layout of the active device, we sliced it down to 4 instances of 15 \(\upmu\)m with 30 fingers each, which allows gate, drain, and source interconnections complying with the design kit physical rules, since low metal layers have very restrictive constraints related to their maximum width and area. To minimize parasitic capacitances at the gate, drain, and source nodes we employed a staircase configuration. This implementation also caters to the reduction of the gate resistance and parasitic capacitances to optimize the achievable minimum noise figure (\(NF_{min}\)) of this device. In this sense, the \(NF_{min}\) for a MOS device can be expressed as (1), where \(K\) is a constant value, \(g_{m}\) is the transconductance of the device, \(R_{G}\) is the gate resistance, \(R_{S}\) is the source resistance, \(f\) is the working frequency and \(f_{T}\) is the unity current gain frequency [4]. Hence, maximizing \(f_{T}\) (by minimizing parasitic capacitances) and minimizing \(R_{G}\) and \(R_{S}\) allows the reduction of \(NF_{min}\). \[NF_{min}=1+K\cdot\sqrt{(g_{m}\cdot(R_{G}+R_{S}))}\cdot\frac{f}{f_{T}} \tag{1}\]  
The new, complex model of the FET is composed of the intrinsic PDK FET device, an RC parasitic extraction of the interconnections from M1 to C1 layers using Calibre xRC, and an EM simulation model generated with EMX of the interconnections from UA to OB metal layers. Figure 2: Simulated \(NF_{min}\) and \(G_{max}\) as a function of the device current density \(J_{DS}\) at 22.5 GHz. The design of the 0.38 V low-power LNA is possible thanks to the CS current density design approach, which is detailed as follows. The active device provides an excellent noise performance at \(J_{Dop}=0.1286\) mA/\(\upmu\)m. Hence, the device provides optimal noise performance when it is biased with \(I_{DS}\) of 7.71 mA. We can then search for a combination of \(V_{D}\) and \(V_{G}\) that yields the desired \(I_{DS}\). Since the LNA is formed by two cascaded CS stages, we can reduce the nominal 0.9 V drain DC voltage required by the PDK and increase the gate DC voltage accordingly to maintain the same \(J_{DS}\), which results in a severe reduction in power consumption without significantly compromising the LNA performance. This would not be possible if a cascode topology had been used.