## 7 Experimental Results
The amplitudes at each subcarrier frequency (the second-last row labeled as \"power\") correspond to the theoretical separate amplitudes in Figure 13(c), which indicates that the subcarriers are orthogonal to each other. The latency is measured using the FPGA signal tap that sends back real-time logic signals from the FPGA to a computer. The throughput latency of the communication (i.e., from the input of digital bits in modulation to the output of digital bits in demodulation) consists of 5.12 us from IFFT in modulation, 5.12 us from FFT in demodulation, 2.56 us from the digital filter, as shown in the first and second rows in Figure 13(b), and several short delays due to a signal buffer and operations in the FPGA. The total latency of communication was measured at about 15.36 us. By reducing the symbol duration, the latency can be further improved. The demodulation is processed in the FPGA, and the receiver signal is first segmented based on the synchronization position and symbol positions; then, the FFT of the segmented signal is calculated. Finally, the results of the FFT (the real and image parts) are used for bit decisions. Figure 15 shows the constellation diagrams of subcarriers at 1.96 MHz and 3.13 MHz, recorded from FPGA signal taps. The distribution of subcarriers with a higher frequency is wider than that of the subcarriers with a lower frequency because the same time offset results in a greater phase offset for subcarriers with a higher frequency. Comparing the red and blue marks revealed that misalignment resulted in a decrease in amplitude (i.e., closer to the origin) and had approximately no impact on the angle and, thus, no impact on the bit decision. The amplitude variation can be further re-used for the positioning of the GA and the VA.  
Based on the near-field communication between the primary and secondary sides, the WPT system was measured at different operating points to simulate the charging process. Figure 16 shows the WPT waves of some typical operating points. In the first row (a.1), (a.2) and (a.3) show the waves for the CC stage; with \(U_{\mathrm{2 DC}}=40,60,70\) V presented,  
Figure 15: Distribution of subcarriers at 1.96 MHz (**a**) and 3.13 MHz (**b**) in constellation diagrams. The blue circles and crosses are the sampled points with bit 0 and bit 1 for a perfectly aligned position; thus, they are located on the unit circle. When the angle of the sampled point ranges from \(-90^{\circ}\) to \(+90^{\circ}\), the bit is determined to be 0; otherwise, the bit is 1. The red marks show the sampled points’ distribution when the primary and secondary coils are misaligned; the amplitudes are decreased because of the decrease in the voltage transfer function of the communication coil system via a weak coupling factor. The angle is calibrated using the second symbol “Calib”, as shown in Figure 8.  
the current is constant near 9.3 A, and 1.2 kW charging power is captured, as shown in (a.4), with increased DC-link voltages, \(U_{\text{1 DC,2 DC}}=90\) V. In the second row, from (b.1) to (b.4), the waves of the CV stage are presented. The secondary DC voltage is constant, \(U_{\text{2 DC}}=70\) V, and the current is reduced step by step using control parameters. Figures in the second row show four typical currents ranging from 9.3 A to 6.2 A. Figure 17 shows an overview of the charging power variation due to the battery voltage increasing during the CC stage. The duty cycles of both full bridges are used to adjust the charging power. Three different values of the phase difference between the primary and secondary voltages are applied, which shows that setting the phase difference away from \(\pm 90^{\circ}\) results in a reduction in the active power. Besides the charging power, the efficiencies (i.e., AC efficiency and DC efficiency) are presented in Figure 18. The required charging current for all three battery voltage levels was achieved by tuning the duty cycles according to the optimal voltage ratio, as given in (27).