# Low Power QC-LDPC Decoder Based on Token Ring Architecture
## 3 Implementation of the QC-LDPC Decoder Based on the Token Ring Architecture with Clock Gating  
It has been assumed that in the designed implementation of a decoder with an architecture based on Token Ring, the set of implementable QC-LDPC codes should not be limited. The proposed general concept of the decoder in the form of a block diagram is shown in Figure 4. The flexibility of the proposed architecture results from the fact that it is easy to design a decoder for various parameters of the parity check matrix \(\mathbf{H}\). Such configurable parameters of the \(\mathbf{H}\) matrix are: regular or irregular matrices, with different block lengths (\(N\)), code rate (\(R\)) and the size of the submatrix, \(P\). The decoder comprises five separate memory blocks, \(P\) control node computing units, \(P\) bit node computing units, a control equation verification module and modules responsible for initialization and communication with the environment. In the developed decoder structure, memories constitute a specific interface between the computing module. The message passing between the nodes is done via memory \(\mathbf{Q}\) (messages \(Q_{mm}\) in (2)-(3)) and memory \(\mathbf{R}\) (messages \(R_{mn}\) in (2)-(3)). The communication support module receives the data to be decoded in the form of the LLR and saves it in the proper order in the memory \(L(c|y)\). The received data is also passed to the decoder initialization module as in (1), which fills the memory \(\mathbf{Q}\). Starting the initialization while the data transmission is in progress can slightly reduce the time in which the QC-LDPC decoder completes the decoding process. After finishing initialization, the process of calculating the control node messages begins. The computing unit of the control nodes takes the input data (messages) from the memory \(\mathbf{Q}\), performs the computations according to the algorithm step (2) and stores results in the memory \(\mathbf{R}\). The computing unit core consists of \(P\)-computing units responsible for parallel computations corresponding to output messages of \(P\) nodes. Figure 3: General idea of token passing in the designed partially-parallel QC-LDPC decoder architecture. In the next processing time slot, the messages of bit nodes (3), total beliefs (4) and hard decisions (5) are computed. Due to an obvious similarity in expressions (3) and (4), we found that a single complex decoder element can jointly realize these computations. The current hard decisions as in (5) are equivalent to the sign bits of the result of computations in (4). Therefore, computations according to (5) can also be integrated into this complex computing block, which we will call the bit node computing unit. The whole computation core consists of \(P\) such complex bit node computing units. Every bit node computation retrieves data (messages) from memories \(\mathbf{R}\) and \(L(c|y)\), determines the bit node messages and saves results in memory \(\mathbf{Q}\) as well as current hard decisions in memory \(\mathbf{X}\). After the bit node processing step is completed, verification of the control equations module for current hard decisions is performed according to expression (6). This is done in the verification of the control equations module by checking each of the control equations defined by rows of \(\mathbf{H}\) in (6). When all controls are satisfied for current hard decisions, the final decoding result is sent to the decoder output via the communication of the result module. If the control equations are not satisfied, the next iteration in the decoder starts. The communication of the results module contains a counter that is incremented with each iteration. If the counter reaches a predetermined maximum value, the decoding is aborted and the decoder signals an erroneous decoding result. Figure 4 shows the idea of a token passing between elements of the QC-LDPC decoder based on the Token Ring architecture.