## 3 Characteristics of FBFET  
The theoretical limit of SS is defined as 60 mV/decade at 300 K [2]. However, surpassing the theoretical limit of SS can be achieved with novel device structures and/or new materials. Various steep-switching devices have been explored to overcome this limit [4; 5; 6; 7; 8; 9; 10; 11; 12; 13; 14; 15; 16; 17; 18]. Among them, devices relying on the positive feedback mechanism have been proposed and demonstrated with extraordinary abilities [21; 22; 23; 24; 25; 26; 27; 28; 29; 30; 31; 32]. FBFETs show excellent subthreshold swing (\(\sim\)0 mV/decade at 300 K) and high on-/off current ratios (\(\sim\)10\({}^{10}\)) [18; 19]. When the temperature or the \(V_{\text{DS}}\) value increases, the on-/off current ratio increases. As the depth of the channel decreases, the device exhibits features that have characteristics more suitable for \begin{table}
\begin{tabular}{l l l l l l l l l} \hline \hline
**Ref.** & \multirow{2}{*}{**Structure**} & \multirow{2}{*}{**Potential**} & \multirow{2}{*}{**
\begin{tabular}{} \end{tabular}**} & **Channel** & **SS at 300 K** & \(\mathbf{V_{\text{DD}}}\) & \(\mathbf{I_{\text{on}}}\) & \multirow{2}{*}{**\(\mathbf{I_{\text{on}}/I_{\text{off}}}\)**} & \multirow{2}{*}{**Year**} \\
**No.** & & & **Barrier Type** & & **(nm)** & & & & \\ \hline \multirow{3}{*}{[63]} & P+I-Si-N+ & \multirow{3}{*}{Trap charge spacors} & \multirow{3}{*}{Trap charged} & \multirow{3}{*}{310–1000} & \multirow{3}{*}{-2} & \multirow{3}{*}{1.2} & \multirow{3}{*}{-10\({}^{-4}\)} & \multirow{3}{*}{-10\({}^{7}\)} & \multirow{3}{*}{2008} \\  & FinFET & & & & & & & & \\ \hline \multirow{3}{*}{[64]} & P+I-Si-N+ & \multirow{3}{*}{Trap charge spacors} & \multirow{3}{*}{Trap charged} & \multirow{3}{*}{350–400} & \multirow{3}{*}{0.35} & \multirow{3}{*}{1.25} & \multirow{3}{*}{-1} & \multirow{3}{*}{-10\({}^{6}\)} & \multirow{3}{*}{2009} \\  & FinFET & & & & & & & & \\ \hline \multirow{3}{*}{[23]} & P+I-Si-N+ & \multirow{3}{*}{Trap charge spacors} & \multirow{3}{*}{Trap charged} & \multirow{3}{*}{200–500} & \multirow{3}{*}{-1} & \multirow{3}{*}{1–1.5} & \multirow{3}{*}{-10\({}^{-3}\)} & \multirow{3}{*}{-10\({}^{8}\)} & \multirow{3}{*}{2012} \\  & FinFET & & & & & & & & \\ \hline \multirow{3}{*}{[69]} & P+I-Si-N+ & \multirow{3}{*}{Trap charge spacors} & \multirow{3}{*}{Trap charged} & \multirow{3}{*}{400} & \multirow{3}{*}{18.4} & \multirow{3}{*}{1} & \multirow{3}{*}{-10\({}^{-6}\)} & \multirow{3}{*}{-10\({}^{5}\)} & \multirow{3}{*}{2014} \\  & Si NWFET & & & & & & & & \\ \hline \multirow{3}{*}{[74]} & P+I+I-Si-N+ & \multirow{3}{*}{50–300} & \multirow{3}{*}{0.005} & \multirow{3}{*}{1} & \multirow{3}{*}{-10\({}^{-4}\)} & \multirow{3}{*}{-10\({}^{11}\)} & \multirow{3}{*}{2016} \\  & Si NWFET & & & & & & & & \\ \hline \multirow{3}{*}{[76]} & P+I-Si-N+ & \multirow{3}{*}{P-I-N- } & \multirow{3}{*}{3.79 (Si FBFET)} & \multirow{3}{*}{1} & \multirow{3}{*}{-10\({}^{-5}\)} & \multirow{3}{*}{-10\({}^{9}\)} & \multirow{3}{*}{2017} \\  & Trap charge spacors & & & & & & & & \\ \cline{1-1}  & FinFET & & & & & & & \\ \cline{1-1}  & S/sub\({}_{30}\)-\(\text{Ge}_{0,3}\) & \multirow{3}{*}{2017} & \multirow{3}{*}{600} & \multirow{3}{*}{6.15} & \multirow{3}{*}{2} & \multirow{3}{*}{-10\({}^{-6}\)} & \multirow{3}{*}{-10\({}^{6}\)} & \multirow{3}{*}{2018} \\  & S/sub\({}_{30}\)-\(\text{Ge}_{0,3}\) & & & & & & & \\ \hline \multirow{3}{*}{[70]} & P+I-Si-N+ & \multirow{3}{*}{Gate bias} & \multirow{3}{*}{400} & \multirow{3}{*}{P-type 1.36} & \multirow{3}{*}{1} & \multirow{3}{*}{-10\({}^{-7}\)} & \multirow{3}{*}{-10\({}^{5}\)} & \multirow{3}{*}{2019} \\  & Si NWFET & & & & & & & \\ \hline \multirow{3}{*}{[72]} & P+I-Si-N+ & \multirow{3}{*}{Gate bias} & \multirow{3}{*}{500} & \multirow{3}{*}{3.7} & \multirow{3}{*}{1} & \multirow{3}{*}{-10\({}^{-7}\)} & \multirow{3}{*}{-10\({}^{5}\)} & \multirow{3}{*}{2019} \\  & Si NWFET & & & & & & & \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Comparison of various FBFET structures. FDSOI structures.