Compared to conventional deep convolutional networks (CNNs), and the task of video processing, SNNs require much less computational resources, hence lower power consumption and lower reaction latency compared to CNN. Hardware solutions for neuromorphic computing have been developed to simulate large-scale SNNs in real-time, such as TrueNorth [6], Neurogrid [7] and SpiNNaker [8; 9], and they use asynchronous processing of spike-events. In conventional chip designs, the speed of all computations is set by a global clock. However, SNNs are inherently sparse and calculations are only performed when an event signal is present. Thus, the asynchronous model is more suitable for SNNs computations. Furthermore, neuromorphic chips have a routing network, which applies time-division multiplexing to send data packets. This networks-on-chip design increases the extent of connectivity since the multi-layered two-dimensional connection topologies are mainly used in silicon chip [8]. Additionally, neuromorphic chips use distributed on-chip memory to reduce the influence of memory bottleneck, and non-volatile technology to implement synaptic strength and plasticity [9]. The neuromorphic processor used is SpiNNaker [8], which has one ethernet port to communicate with the host PC and it does not support direct communication with external devices. To solve this, advanced processor technologies (APT) group at University of Manchester (UM) uses a PC to convert communication protocols between SpiNNaker and external devices [10], which is not suitable for mobile robotics. APT group also designed a field programmable gate array (FPGA) interface to convert the data received from DVS to spikes and then inject these spikes into SpiNNaker [11]. It is a unidirectional data flow and cannot be applied for closed-loop execution. Apart from the FPGA interface, UM and Technical University of Munich (TUM) developed a microcontroller interface that supports bidirectional data transmission [12]. In this solution, an additional complex programmable logic device (CPLD) is used for the converting protocol between SpiNNaker and the microcontroller. The data bus in SpiNNakerLink is 7 bits, and it becomes 9 bits after the conversion of the CPLD [11]. This solution also has five pre-defined ports for two DVSs and three motors, which simplifies the connection of DVSs and motors, but also results in a limited capacity for other external devices and sensors, such as optical flow sensor. Furthermore, the two chips applied in this solution also mean higher power consumption and increased difficulty for further development. TUM applies their interface to the robot called 'PushBot' or 'SpOmnibot', which uses Wi-Fi access point to relay the robot and a host machine [13; 14]. The Wi-Fi connection increases the mobility of the robot at the expense of higher reaction latency. Another event-driven platform which combines SpiNNaker with a spiking silicon retina (such as ATIS) has been demonstrated on real-time object recognition task, specifically to classify 26 class characters [15], as well as for object tracking [16]. In addition to the applications where SpiNNaker was combined with a vision sensor, it has been used in multiple physical autonomous robots, such as musculoskeletal robotic hardware with neural control implemented on SpiNNaker [17]. Another application area of SNNs run on SpiNNaker is in the context of cognitive robotics, where the goal is identifying the approach and strategy how to compute. It has been demonstrated on a robot called 'iCub' and SpiNNaker, which has been developed to grasp the task of object-specific attention [18]. Neuromorphic systems controlled by SNNs, but implemented on VLSI chips (instead of SpiNNaker), have been also demonstrated, such as an open-loop motor controller [19], which offer lower power consumption and simplified motor control.