# Low-Latency QC-LDPC Encoder Design for 5G NR
## 3 Design of 5G QC-LDPC Encoder
### QC-LDPC Encoder Architecture  
The encoding algorithm discussed earlier is based on the structural characteristics of the 5G QC-LDPC code; it has the same linear complexity with the RU method. Herein, this paper uses the proposed algorithm for hardware implementation, not only mapping the algorithm to the circuit architecture but also considering the selection and optimization of the circuit architecture in the mapping process and approaching the limit of the LDPC encoding latency. The overall hardware structure of the encoder is shown in Figure 5. In this encoder, the memory and functional modules are considered as the major influencing factors of the overall area, latency, and power performance of the hardware design. The encoding algorithm used and the operating frequency of the hardware determine the throughput of the overall architecture. According to the aforementioned high parallel encoding algorithm, the encoding calculation is actually to complete the multiplication of the PCM and the information vector. PCM is composed of \(Z\times Z\) zero matrix and unit cyclic shift matrix; the multiplication of these submatrices and the information vector is actually a bit-level cyclic shift. Thus, the encoder designed in this paper is implemented by cyclic shift network and combinational logic circuits. The encoding calculation is mainly composed of two parts in parallel, Part I calculates \(AS^{T}\) in Equation (5), and Part II calculates \(CS^{T}\) and \(DP_{1}^{T}\) in Equation (6). In order to realize low latency encoding, \(64\) (\(22+42\)) cyclic shift network (CN) modules are  
Figure 5: Low latency encoder architecture of 5G QC-LDPC codes. used, which are barrel shift logic. The encoder mainly consists of the following functional modules:  
(1) Message buffer SRAM: The transmission information of the media access control (MAC) layer is stored in this module; the information is converted through first input first output (FIFO) to perform multi-byte fast CRC check calculation. Then, the information and its generated CRC bits are transferred to the TBS buffer. (2) Memory blocks: In Figure 5, the matrix ROM stores the cyclic shift coefficient values of the PCM corresponding to the \(A\), \(C\), and \(D\) submatrices. (3) Encoder parameter calculation module: calculating some parameters required by the encoder according to the code length and the original code rate. Meanwhile, the selected encoding parameters will affect the control signal and state machine of the encoder. (4) CRC calculator module: executing the CRC calculation of the transmission block with high parallelism. (5) Transport blocks size buffer: combining information bits and CRC into \(K_{b}\) block code words, each code word length is \(Z\). (6) Cyclic shift network Part I and Part II: cyclic shift network is used to implement the cyclic shift of \(Z\) length code words, according to the cyclic shift coefficient provided by the control signal. CNs is a configurable barrel shift register; corresponding to the \(Z\) value that does not meet the hardware scale, the input and output of the cyclic shift will be adapted. (7) \(P_{1}\) calculation module: this module consists of combinational logic circuit and memory and configurable circular shift registers. Each \(H_{BG}\) has two kinds of \(B\) submatrices, so this module can flexibly implement different computation processes of different \(B\) submatrices. Herein, the calculation of Equations (8)-(11) is also parallelized to speed up the process of obtaining \(P_{1}\). (8) Codeword output processing module: punching and shortening the parity code blocks. Connecting the information code block and the parity check code block and output according to the code rate. According to the column number of matrix \(A\), Part I is designed using 22 CN for \(K_{b}\) code blocks, which are inputs into each CN sub-module. Meanwhile, one row elements in operations have the current value of \(\text{CN}_{1-22}\), equaling to a binary addition operation.