## 4 Design Consideration and Simulation
### HPLDDC Current Loop Analysis and Simulation
In addition, in the switching-mode DC-DC converters,\(f_{cf}\) can be lower than the\(f_{s}/10\)[24]. According to these circumstances,\(f_{cf}\) was 50 Hz for the HPLDDC operation. According to Figure 12, at 50 Hz, \(G_{op(bt)}\) should be promoted from \(-\)5.52 to 0 dB. Therefore, the magnitude of Equation (18) can equal to a constant, 1.89 (20 log 1.89 = 5.52 dB). Moreover, \(g_{p}\) can be select as a suitable constant value. Hence, substitution of \(g_{p}\) = 2.2, \(\mid G_{con(Pt)}[j(2\pi f_{\zeta})]\mid\) = 1.89 and \(f_{\zeta}\) = 50 Hz into Equation (18) can obtain \(g_{i}\) = 1.11 \(\times\) 10\({}^{3}\). Therefore, substitution of \(g_{i}\) = 1.11 \(\times\) 10\({}^{3}\) and \(g_{p}\) = 2.2 into Equation (18) can rewire \(G_{con(Pt)}\) (\(s\)), whose TF can be expressed as follows:  
\[G_{con(Pt)}(s)=g_{p}+g_{i}/s=2.2+1.11\times 10^{3}/s. \tag{21}\]  
In this study, the CLC TF using the PI control can adopt Equation (21). The CLC TF using the P control can employ the \(g_{p}\) gain from Equation (18) that is given by:  
\[G_{con(P)}(s)=g_{p}=2.2. \tag{22}\]  
Figure 11: \(d\)–\(v_{con}\) characteristics: (**a**) Boost mode; (**b**) buck mode. Figure 12: Open-loop frequency responses: (**a**) No PI control; (**b**) using PI control. In Figures 9 and 10, \(k_{c}\) is equal to \(g_{sa}\times k_{cv}\), \(g_{sa}\) is the SA's amplifier gain, \(k_{cv}\) is the C-V converter gain. In this study, \(g_{sa}\) and \(k_{cv}\) were set as 16 and 0.05, respectively; hence \(k_{c}\) equaled to 0.8. Moreover, an open-loop gain \(G_{op(htcan)}\) (s) equaled to \(k_{c}\times G_{op(ht)}\) (s) \(\times G_{can(Pt)}\) (s). Therefore, use of the MATLAB could simulate the frequency response of \(G_{op(htcan)}\) (s), as shown in Figure 12b. From Figure 12b, the LFG was promoted to 38.3 dB, and the phase was \(-33.6^{\circ}\) at 50 Hz. Furthermore, an open-loop gain, \(G_{op(htcan)}\) (s), equaled to \(k_{c}\times G_{op(bb)}\) (s) \(\times G_{can(Pt)}\) (s). Hence, \(G_{op(htcan)}\) (s) simulation using the MATLAB is illustrated in Figure 12b. From Figure 12b, LFG was promoted to 44.7 dB, and the phase was \(-107^{\circ}\) at 50 Hz. According to the frequency responses of \(G_{op(htcan)}\) (s) and \(G_{op(htcan)}\) (s), the HPLDDC using the designing CLC PI control can address the system stable requirement for buck and boost operations. Incorporating \(G_{op(htcan)}\) (s) with \(G_{ss}\) (s) of (15) and using Matlab, the simulation of HPLDDC start-up current for the boost mode is illustrated in Figure 13a. In addition, incorporating \(G_{op(htcan)}\) (s) with \(G_{ss}\) (s) and using MATLAB, the simulation of the HPLDDC start-up current for the buck mode is illustrated in Figure 13b. Several situations can be observed in Figure 13:  
1. Boost mode: No current spike occurred. The settling time was 40 ms. The final current was 1.2 A; and  
2. Buck mode: Maximum start-up current peak was 1.65 A. The settling time was 230 ms. The final current was 1.2 A. From both figures, although the final current, 1.2 A, could correspond to the specification, a start-up current spike occurred in the buck mode operation. From these simulations, several disadvantages can be identified when the CLC uses the PI control. First, the peak current of 1.65 A already overstepped the specified 1.5 A, and this situation was harmful for HPLDs. Second, although the CLC using PI control had an outstanding ability to regulate steady-state errors, the PI control caused the start-up current spike when the SBBC operated in the buck mode. To depress the start-up current spike, the CLC using the PIAP control method was employed. Simulations are presented in Figure 14. From Figure 14, despite the SBBC operating mode, the use of P control method cannot achieve the target final current of 1.2 A. Thus, a CLC using the PIAP control method could be adopted in the HPLDDC. Figure 14 simulations show several benefits: First, the start-up current spike mitigated effectualness.