# An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System
## 2 Analysis of Storage and Exchange Efficiency for SAR Data
### Analysis of Storage Access Characteristics for DDR3 SDRAM  
As mentioned in Section 1, the massive amount of raw data and the result data from each processing step must be stored during spaceborne SAR imaging processing, and DDR3 SDRAM is the ideal off-chip storage medium for the current spaceborne SAR real-time processing. DDR3 can be regarded as a large warehouse. The specific location of  
Figure 1: The schematic flowchart of CS algorithm processing. the stored data must be uniquely determined by the row, column, and bank addresses. Therefore, DDR3 is, internally, a three-dimensional (row, column, bank) storage array. Current DDR3 memory chips are essentially designed with eight banks, each of which contains thousands of rows and columns. To determine the final memory cell, the DDR3 addressing process appoints the bank address first, then the row address, and finally the column address. DDR3 read and write accesses are accomplished through a burst transaction of consecutive storage cells in the same row. The burst length is the number of cycles of continuous transmission, and in the case of burst transaction, as long as the starting column address and the burst length are specified, the memory will automatically read or write the corresponding number of memory cells in sequence, without the need for the controller to continuously provide column addresses. The DDR3 burst length can be configured to 4 or 8 on demand. In most cases, to enable higher DDR3 access bandwidth, the burst length is set to 8, indicating that the memory cell data are read and written at 8 consecutive column addresses on the rising and falling edges of 4 clock cycles. In DDR3 read and write operations, the \"row activation\" command must first be executed, followed by the logical Bank address and the corresponding row address to activate the need to read and write the row. DDR3 must send the \"activation\" command to the row in order to read and write the data in a row. Following that, the \"read or write command activation\" is executed, which contains both column addresses and the specific operation command (read or write). After reading the data, the memory chip will perform a pre-charging operation to turn off the active working row in order to address and transfer data to other rows in the same bank. Therefore, row activation, the read or write command activation, the data reading or writing process, and pre-charging constitute the order of operations for DDR3 memory read or write operations. Row activation time, read or write command activation time, data reading or writing process time, pre-charging time, and the interval delay between them are all deterministic values for DDR3 SDARM chips, while the factors influencing the DDR3 read/write access time are primarily the number of times that continuous burst access is performed. The burst length is typically eight, and the number of consecutive bursts is assumed to be \(n\). The interval of time between the current row activation command and the next row activation command during a write operation is:  
\[t_{WRITE}=t_{RCD}+t_{CWL}+n\times 4t_{CK}+t_{WR}+t_{RP} \tag{1}\]  
The interval of time between the current row activation command and the next row activation command during a read operation is:  
\[t_{READ}=t_{RCD}+t_{RTP}+n\times 4t_{CK}+t_{RP} \tag{2}\]  
where \(t_{CK}\) is the DDR3 chip's working clock period; \(t_{RCD}\) is the interval delay time between when the row activation command is valid and when the read or write command activation is valid; the delay from the effective write command to the effective write data is called \(t_{CWL}\); the time from the completion of the write operation to the pre-charging is called \(t_{WR}\); \(t_{RP}\) represents the delay time between pre-charging and the activation of the next row; \(t_{RTP}\) represents the time interval between the read data command and the pre-charging [35]. The raw echo data from SAR are stored and processed as a matrix.