## 1 Introduction  
Deep learning (DL), particularly through convolutional neural networks (CNNs), has driven significant advancements in image classification, achieving state-of-the-art results across numerous datasets. However, deploying these computationally intensive models on edge devices for real-time applications poses unique challenges. Limited computational resources, memory, and energy efficiency restrict the direct use of conventional DL models on edge platforms like autonomous systems, the Internet of Things (IoT), and mobile applications [1, 2, 3]. Field-Programmable Gate Arrays (FPGAs) have emerged as a compelling solution for signal and image processing [4, 5, 6, 7], and edge artificial intelligence (AI) acceleration [8, 9]. These devices offer a unique combination of low power consumption, reconfigurability, and high parallelism, making them suitable for resource-constrained environments. Frameworks like Xilinx Vitis-AI further simplify FPGA deployment by integrating software tools with hardware acceleration. Despite these advancements, optimizing pretrained CNN architectures, such as VGG16 and VGG19, for FPGA inference remains challenging due to their high computational demands, large memory footprint, and hardware-specific constraints [10, 11]. While existing research has explored custom-designed CNNs and hardware-aware optimization techniques such as quantization and model pruning, limited attention has been paid to integrating transfer learning with FPGA acceleration [12; 13]. Transfer learning allows the reuse of pretrained models, significantly reducing the training time and computational cost while maintaining accuracy. However, challenges in adapting these models for FPGA deployment, including quantization-induced accuracy degradation and resource utilization constraints, require careful consideration. Despite the advancements in integrating transfer learning with FPGA acceleration, several limitations persist in previous studies. Many existing works rely on custom Hardware Description Language (HDL) or High-level Synthesis (HLS) implementations, which, while offering flexibility, are time-intensive and require substantial expertise, limiting their accessibility for broader use cases [14; 15]. Additionally, the models often prioritize either latency or accuracy, failing to achieve a comprehensive balance. Furthermore, limited exploration has been conducted on leveraging framework-based FPGA deployment for pretrained CNNs, restricting scalability and practical applicability in real-time edge AI scenarios. Recently, researchers have focused on facilitating the transfer learning-based implementation of CNN models on FPGA using Xilinx Vitis AI. For example, [16] presents FPGA implementations of basic CNN models such as AlexNet and GoogLeNet, while recent studies, such as [17; 18], explore the deployment of lightweight architectures like ResNet, MobileNet, and EfficientNet on FPGA. Although these works achieved notable improvements in latency and power efficiency, they often trade off accuracy to reduce computational costs or compromise resource efficiency to achieve high precision. This trade-off highlights a gap in achieving an optimal balance among high precision, efficient resource utilization, and low inference latency. This research addresses these gaps by leveraging the Xilinx Vitis-AI framework to streamline FPGA deployment for pretrained models such as VGG16 and VGG19. Our approach achieves a compelling balance between inference latency, resource utilization, and accuracy, making it highly suitable for edge applications. By avoiding the complexities of custom implementations and focusing on framework-driven efficiency, our work offers a scalable and practical solution for deploying DL models in resource-constrained environments. In this study, we implement VGG16 and VGG19 for classifying the CIFAR-10 dataset [19] using transfer learning on FPGAs.