## 2 Circuit Implementation
### Amplifying Stage  
The amplification stage comprised a floating HPF, chopper-stabilized CFIA, and QRS peak detector. Figure 8 shows the structure of the floating high-pass filter. DC offset occurs during the chopper and CMCP operations. Therefore, a floating HPF was adopted to prevent a large DC offset. The high-pass filter is implemented using four pseudo resistors and two large capacitors (C\({}_{\text{HPF}}\)) on the chip [24; 25; 26].  
Figure 9 shows the block diagram of the chopper-stabilized CFIA. The CFIA comprised an input transconductance stage (G\({}_{\text{m1-1}}\), G\({}_{\text{m1-2}}\)) and a Miller integrator (G\({}_{\text{m2}}\), G\({}_{\text{m3}}\)). At the G\({}_{\text{m2}}\) and G\({}_{\text{m3}}\) stages, nested Miller compensation was implemented to achieve a fine frequency response [27; 28].  
Figure 8: Structure of the floating HPF.  
Figure 7: Schematic of the comparator.  
Figure 9: Block diagram of the proposed potentiostat readout circuit.  
The transfer function of CFIA is expressed as:  
\[\frac{\mathrm{V_{OUT}}}{\mathrm{V_{IN}}}=\frac{\mathrm{G_{m1-1}}}{\mathrm{G_{m1-2 }}}\cdot\frac{2\mathrm{R_{2}}+\mathrm{R_{1}}}{\mathrm{R_{1}}} \tag{2}\]  
where \(\mathrm{G_{m1-1}}\) is the input transconductance stage, \(\mathrm{G_{m1-2}}\) is the input feedback transconductance stage, and \(\mathrm{R_{2}}\) and \(\mathrm{R_{1}}\) are the feedback resistors. If \(\mathrm{G_{m1-1}}\) and \(\mathrm{G_{m1-2}}\) are well-matched and the ratio remains equal to one, the transfer function is given by:  
\[\frac{\mathrm{V_{OUT}}}{\mathrm{V_{IN}}}\approx 1+\frac{2\mathrm{R_{2}}}{ \mathrm{R_{1}}} \tag{3}\]  
In Figure 10, the proposed CFIA adopts the input and feedback stages of the PMOS differential pair. The intermediate stage was implemented using folded-cascode topology with Monticelli class-AB biasing, and the output stage was implemented in class-AB.  
In addition, a common-mode feedback (CMFB) circuit was implemented to stabilize the output common-mode voltage. Chopper stabilization was adopted to reduce the low-frequency 1/f noise. Choppers were implemented in front of the input stage and in front of the common-gate stage. The individual switch in the chopper was implemented using a CMOS transmission gate, and the chopping frequency of this circuit was 15 kHz.  
The structure of the QRS peak detector is illustrated in Figure 11. The QRS peak detector comprises a comparator, AND gate, low-pass filter (LPF), and buffer [29]. A QRS peak was detected in the P-Q-R-S-T complex of the ECG signal. When comparing the ECG signal at INP and \(\mathrm{V_{COMPOUT}}\), when the R-term signal becomes higher than \(\mathrm{V_{REF}}\), \(\mathrm{V_{COMPUT}}\) alternates from \(\mathrm{V_{REF}}\) (0.8 V) to the high state (1.8 V); when the comparator output voltage transitions from a high state (1.8 V) to a low state (0 V), the \(\mathrm{V_{COMPUT}}\) signal changes back to VREF. Similarly, when comparing the ECG signal at INN and \(\mathrm{V_{COMPUT}}\), when the R signal becomes lower than \(\mathrm{V_{REF}}\), \(\mathrm{V_{COMPUT}}\) alternates from \(\mathrm{V_{REF}}\) (0.8 V) to the high state (1.8 V); when the comparator output voltage transitions from a low state (1.8 V) to a low state (0 V), the \(\mathrm{V_{COMPUT}}\) signal changes back to \(\mathrm{V_{REF}}\). Finally, when the two comparator outputs passed through the AND gate, a QRS peak was detected.  
Figure 10: Schematic of the proposed potentiostat readout circuit.