## 4 A Survey on Cognitive Radio Implementation Research
### Cognitive Radio Platform from UC Berkeley  
The BWRC (Berkeley Wireless Research Center) cognitive radio testbed hardware architecture consists of Berkeley Emulation Engine (BEE2) [97], reconfigurable 2.4 GHz radio modems, and fiber link interface for connection between BEE2 and radios. The software architecture consists of Simulink-based design flow and BEE2 specific operating system that provide an integrated environment for implementation and simple data acquisition during experiments [94]. The BEE2 contains 5 Vertex-2 Pro FPGAs, each FPGA embeds a PowerPC 405 core, which minimizes the latency between the microprocessor and reconfigurable logic while maximizing the data throughput. Furthermore, with FPGAs running at clock rates similar to that of the processor cores, sys \begin{table}
\begin{tabular}{|l|l|l|l|} \hline Board & Rx / Tx & Frequency Range & Tx Power \\ Basic Tx/Rx & Tx/Rx & 1 MHz to 250 MHz & N/A \\ LF Tx/Rx & Tx/Rx & DC to 30 MHz & N/A \\ TVRX & Rx & 50 MHz to 860 MHz & N/A \\ DBSRX & Rx & 800 MHz to 2.4 GHz & N/A \\ WBX0510 & Transceiver & 50 MHz to 1 GHz & 100 mW (20 dBm) \\ RFX900 & Transceiver & 750 to 1050 MHz & 200 mW (23 dBm) \\ RFX1200 & Transceiver & 1150 to 1450 MHz & 200 mW (23 dBm) \\ RFX1800 & Transceiver & 1.5 to 2.1 GHz & 100 mW (20 dBm) \\ RFX2400 & Transceiver & 2.3 to 2.9 GHz & 50 mW (17 dBm) \\ XCVR2450 & Transceiver & 2.4 to 2.5 GHz, and 4.9 to 5.9 GHz & 100 mW (20 dBm) \\ \hline \end{tabular}
\end{table} 
Table 1: USRP daughterboard list with specifications. Figure 8: USRP architecture. tem memory, and communication subsystems, all data transfers within the system have tightly bounded latency. BEE2 is therefore well suited for high throughput real-time applications [97]. In order to interface this real-time processing engine with radios and other high throughput devices, multi-gigabit transceivers (MGTs) on each FPGA are utilized together with physical XAUI 4X electrical connection to form a 10 Gbps full-duplex links. There are a total of 18 such interfaces per BEE2 board allowing independent connections of 18 radios. Each individual MGT channel is software configurable to communicate and exchange data at any rate below 10 Gbps. The board also contains USB and JTAG interfaces. Figure 9 shows the architecture and a picture of the BEE2 board. Details about BEE2 can be found in [97]. The reconfigurable wireless modem consists of the filters, ADC/DAC chips and a Xilinx Vertex-II Pro FPGA. Digital-to-analog conversion is performed by a 14-bit DAC running at 128 MHz, while analog-to-digital conversion is performed by a 12-bit ADC running up to 64 MHz. The FPGA performs data processing and control, and supports 10 Gbps full duplex XAUI link for transmitting and receiving data to/from BEE2. The RF modem module is capable of up/down converting 20 MHz RF bandwidth at 2.4 GHz. The RF frequency is fully programmable in the entire 80 MHz ISM band using LMX2326 synthesizer [98]. Top level block diagram and implementation of the wireless modem are presented in Figure 10. Both received signal strength (RSSI) and automatic gain control (AGC) are measured in real-time to support optimal signal conditioning on the receiver end. It also features dual antenna configuration for switched antenna diversity [98]. Figure 10: The BWRC Reconfigurable wireless modem. Figure 9: BEE2 system architecture (left) and BEE2 implementation (right). Software design is built around Matlab/Simulink from Mathworks [99] coupled with the Xilinx System Generator [100] for mapping high-level block diagrams and state machine specifications to FPGA configurations. This environment supports simultaneous development of signal processing algorithms and digital design description for their hardware realization. Therefore no translation is required and allows signal processing researchers to realize hardware implementation of developed algorithms [94, 98, 101].