## 4 Hardware for Near-Field-Based Communication in the WPT System  
The main challenge of integrating near-field-based communication into a WPT system is the crosstalk from the WPT system, in which the kilowatt-WPT field and the milliwatt-communication signal share the same space and time. First, the fundamentals of the WPT system could induce a voltage on the coils of near-field-based communication. However, in the frequency domain, the frequency of this induced voltage is much lower than the carrier frequency used for communication, so it can be easily filtered out and, therefore, does not interfere with demodulation. Nonetheless, the high amplitude of the induced voltage may overflow the voltage range of the ADC, preventing the overlaid high-frequency communication signal from being sampled. This leads to the loss of information or even damage due to the high induced voltage on the electronics. Second, high-frequency noises generated via the switching of MOSFETs could lead to errors in communication. To deal with the crosstalk from the WPT fundamentals, the double-D coils of the wireless communication are designed to be center-aligned with the WPT coils so that the induced voltages from the same side of the WPT coil on the left and right parts of the double-D coils cancel each other out, as shown in Figure 6. This layout minimizes the crosstalk from the WPT coil to the communication coil on the same side. However, the crosstalk from the WPT coil on one side to the communication coil on the other side is only minimized when they are well aligned. Therefore, an extra analog filter in the low noise amplifier (LNA) is used to suppress the induced voltage via misalignment to ensure the received signal on the ADC does not overflow. And in the FPGA program, the WPT system can be turned off when the ADC of the communication system receives a high amplitude greater than the threshold, which will protect both the WPT system and the communication system when the coils are largely misaligned. Additional high-order digital filters are implemented in the FPGA to improve the quality of demodulation. To deal with the high-frequency noise from the switching of MOSFETs, the power of communication can be enhanced, which improves the signal-noise ratio (SNR). As shown in Figure 7, the FPGA-modulated digital signal is generated via the transmitter DAC, amplified via the first LNA, and then goes through the double-D coil system, amplified via the second LNA, and it is finally sampled by the receiver analog-to-digital converter (ADC) for demodulation. Therefore, the gain of the signal path can be expressed as follows:  
\[G_{\text{signal}}=G_{1}+G_{\text{coils}}+G_{2}. \tag{28}\]  
Since the voltage range of DAC and ADC is 2V peak-to-peak, the total signal gain \(G_{\text{signal}}\) should be less than 0 dB; otherwise, the input of ADC will overflow. The maximal gain of the NFC channel is measured at a perfectly aligned position; therefore, the gain of  
Figure 6: Double-D coils for communication are aligned with WPT coils on each side to minimize crosstalk from WPT. both low noise amplifiers in the communication frequency band should meet the following condition:  
\[G_{1}+G_{2}\leq-G_{\text{coils,max}}. \tag{29}\]  
The noise from the WPT primary and secondary sides is coupled with the communication chain. The first noise path starts from the primary WPT coil, which is then coupled to the secondary NFC coil and transmitted through the primary NFC coil and LNA; finally, it is received by the receiver ADC. The second noise from the secondary WPT is merged into the communication path directly from the primary NFC coil. The crosstalks of the primary WPT coil to the primary NFC coil, as well as the secondary WPT coil to the secondary NFC coil, is minimized and, thus, negligible, as mentioned above.