## 2 Silicon Nano-Ridge Qubit Device  
### Device Concept  
We invented a new silicon qubit device design consisting of a linear array of electrostatically-defined and tunnel-coupled QDs with source and drain reservoirs at both of its ends as shown in Figure 1. It is based on a one-dimensional silicon channel on top of a fully-depleted silicon-on-insulator wafer and exhibits a back-gate, two TiN side-gates, and an array of thin TiN top-gates. In contrast to the modified FinFET devices of [24; 25; 27], the channel is anisotropically wet-etched by tetramethylammonium hydroxide (TMAH), which results in a trapezoidal nano-ridge with atomically-flat [111] facets [30; 31]. The angle of the tip of the trapezoidal nano-ridge can be further tuned by the local-oxidation of silicon (LOCOS) process of the [111] silicon facets. Two TiN side-gates insulated by SiO\({}_{2}\) cover the two sidewalls of the silicon nano-ridge and control the perpendicular QD confinement of the nano-ridge. As the nano-ridge sidewalls are atomically flat, the disorder impact from side-gates or interface defects is low. The side-gates are realized by covering the nano-ridge with TiN and subsequent chemical mechanical polishing. This provides electrical insulation of the two side-gates, yielding a highly-tunable QD potential. In addition, the planarized sample surface is indispensable for the fabrication of multiple top-gate electrodes with spacer and damascene processes. For the top-gate array, we target a gate pitch of 45 nm (metal gate width of 30 nm and 15 nm of SiO\({}_{2}\) insulation). The gates are used alternatingly to accumulate QDs and tunnel barriers by applying voltages \(V_{\text{P,n}}\) and \(V_{\text{B,n}}\), respectively. Thus, an arbitrarily-long array of QDs can be formed, where each QD can be filled with a single electron, the spin of which encodes one qubit (Figure 1). Such linear arrays of tunnel-coupled QDs are suitable for quantum error correction [32]. At both ends of the silicon nano-ridge, two large top-gates accumulate two-dimensional source and drain reservoirs (Figure 1). Applying voltages to the various independently-tunable top-, side-, and back-gates allow for a flexible control of the potential landscape. For instance, the valley splitting of the QD and the tunnel-coupling of adjacent QDs can be tuned by applying suitable voltages at the various gates [22; 33]. Moreover, using a split top-gate array, we can also form two capacitively- or tunnel-coupled arrays of QDs (i.e., double-array) in each corner of the nano-ridge. Alternatively, an array of QDs is formed on one side of the silicon nano-ridge, while on the other side, a single electron transistor (SET) biased by \(V_{\text{SD}}\) applied across the source and drain reservoirs is formed. The SET can be operated as a charge detector for the whole QD array, since its QD is capacitively coupled to a few QDs of the opposing array. Furthermore, the SET can be formed at an arbitrary position along the nano-ridge. Such a charge  
Figure 1: Schematic of the envisioned qubit device showing the silicon nano-ridge and the TiN gate array for electron spin localization. The trapezoidal silicon nano-ridge is fabricated on a fully-depleted silicon-on-insulator (FDSOI) substrate, providing a global back-gate set on voltage \(V_{\text{BG}}\) underneath the buried oxide (Box). Buried TiN side-gates are used to tune the confinement of the electron wave function along the [\(\bar{1}\)10] crystal axis. TiN gates, perpendicular to the silicon nano-ridge, tune the chemical potential within each quantum dot by applying a voltage \(V_{\text{P,n}}\) and the potential barrier between adjacent quantum dots by applying a voltage \(V_{\text{B,n}}\). Two electronic reservoirs, each tunnel-coupled to one end of the nano-ridge, are induced by applying a positive voltage to large top-gates covering the area adjacent to the ends of the nano-ridge (here, \(V_{\text{S}}\) for the source reservoir is shown). The dashed line indicates a symmetry axis with respect to the gate structure.