## 5 Simulation Results and Discussion
Furthermore, the input voltage has no limitations as long as the selected switches and other components in the inverter can tolerate that voltage. Consequently, the proposed topology can be used at higher voltages, given that the semiconductors can tolerate that voltage and can comply with the standard norms in terms of leakage current requirements. The current stresses represented in the simulated waveform of Figure 15 illustrate the current experienced by each semiconductor switch of the proposed transformerless inverter during the positive and negative power cycles, in addition to the freewheeling period (zero voltage state). Figure 15a shows that \(S_{1}\) carries the current injected to the grid \(lg\) during the positive cycle (active), while \(S_{2}\) carries \(I_{g}\) in the negative cycle (active), as can be seen in Figure 15b. Additionally, Figure 15c,d exhibit the simulation waveforms of the currents carried by \(S_{3}\) and \(S_{4}\) during the positive and negative freewheeling cycles to permit output inductor current freewheeling and achieve the zero voltage state for unipolar SPWM. As illustrated in Figure 16, the unipolar SPWM modulation technique is achieved. The simulated waveform \(V_{an}\) presents \(+V_{dc}\) and \(0\)\(V\) in the positive power cycle and \(-V_{dc}\) and \(0\)\(V\) during the negative power cycle. Hence, the three states required to implement the unipolar SPWM are conducted at \(+V_{dc}\), \(-V_{dc}\), and _zero_ voltage. Therefore, the proposed inverter generates a unipolar output voltage, which reduces the current ripple and filter inductor losses. Hence, smaller filter inductors are required as compared to other topologies with the bipolar SPWM modulation technique. The grid voltage and currents of the simulated proposed inverter topology are illustrated in Figure 17. A sinusoidal voltage waveform with very low distortion is presented in the grid side \(V_{g}\). The simulated waveforms show a unity power factor, whereby the currents are in phase with the grid  
Figure 15: Current stresses in the semiconductor switches compared with grid current \(I_{g}\): (**a**) \(S_{1}\); (**b**) \(S_{2}\); (**c**) \(S_{3}\); (**d**) \(S_{4}\). voltage. Figure 17a shows the grid voltage \(V_{g}\) with the inverter side current \(I_{inv}\) before the LCL output filter. As shown in Figure 17a, it contains some distortion, while Figure 17b shows \(V_{g}\) with the injected grid current \(I_{g}\) after the LCL, where the effect of the LCL filter is shown clearly in smoothening the grid current \(I_{g}\). The performance of the proposed transformerless inverter is evaluated in terms of the efficiency using the power loss calculations mentioned in Section 4 and compared with the simulated results obtained using the PSIM thermal module. There is a slight difference between the simulation and theoretical results, as shown in Figure 18. This is mainly due to the approximation made in simplifying the power loss equations of the buck-boost circuit, as explained previously. Figure 16: Output voltage of the proposed inverter \(V_{an}\). Figure 17: Grid voltage and injected current before and after LCL filter: (**a**) simulated grid voltage \(V_{g}\) with inverter side current \(I_{inv}\); (**b**) simulated grid voltage \(V_{g}\) alongside grid current \(I_{g}\). Figure 14:0 The efficiency of the proposed transformerless inverter. The weighted efficiency was calculated according to California Energy Commission (CEC). The value was found to be 97.29% and 98.33% for the calculated and simulated efficiency, respectively. The CEC equation is given by  
Figure 14:1  
There are two circuit configurations that can be implemented in the freewheeling path of the inverter, either using two branches consisting of two MOSFETs with external diodes, as suggested in the proposed topology, or using one branch consisting of two MOSFETs and utilizing the internal antiparallel diodes. Each circuit has its own pros and cons.