## 2 TDC Architecture
### Online Calibration  
Online calibration is performed to track and compensate PVT variations. Due to process, the delay element is not as uniform as the dedicated delay line in the ASIC. Some delay elements may have a small delay, whereas some delay elements may have a large delay. If the delay of each delay element is consistent, the bin width of each tap is uniform. The bin width of each tap is obtained by a code density test [16; 20; 29; 30]. To balance resources and a correction effect, 1,024,000 is chosen as the number of test N in this design. The bin width of each delay element is determined using the following equation:  
\[W_{i}=\frac{N_{i}}{N}T_{clk} \tag{1}\]  
where \(W_{i}\) is the bin width of \(i\)-th tap, \(N_{i}\) is the hit number of each tap, and \(T_{clk}\) is the clock period. The DNL and INL are usually used to represent the linearity of the TDC. The DNL is the difference between the actual bin width and ideal bin width. The INL is the cumulative value, which indicates the deviation from the ideal value. The DNL and INL of the i-th tap are defined as follows:  
\[DNL_{i}=\frac{W_{i}-W_{LSB}}{W_{LSB}} \tag{2}\]  
\[INL_{i}=\sum_{k=1}^{i}DNL_{k} \tag{3}\]  
To make the TDC more linear, [PERSON] explained the bin-by-bin calibration structure [31]. The DNL and INL are derived from the histogram in this method and the bin-by-bin calibration using the DNL values. Instead of the edge of the bins, [PERSON] proposed that the center of the bins should be corrected. Therefore, the INL after this correction is determined from the following:  
\[INL(k)=\sum_{i=1}^{k-1}DNL(i)+\frac{DNL(k)}{2} \tag{4}\]  
Figure 5 shows the timing diagram of the online calibration. To improve precision and reduce power consumption, the calibration signal uses the hit instead of the ring oscillator. Firstly, the fine count associated with each binary code is retrieved and stored in the histogram through N hit events, which estimates the width of each bin. This step is also known as a code density test. After the histogram is established, the data are sent to the lookup table for bin-by-bin calibration. After the lookup table is built completely, the system starts measuring the hit events and the following hit events are corrected with the lookup table. \begin{table}
\begin{tabular}{c c} \hline \hline
**Hex Numbers** & **Binary Numbers** \\ \hline
6996966996696996 & 01101001101010101011001 \\
100101100110100101010101001100110 \\
8117177E17E7E28 & 10000001001110010111111110 \\
0001011101111001111111111011000 \\ FEESE880E808000 & 111111101010001100000000000 \\
11101001000000010000000000000000000000 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: The initialization contents of three 6-LUTs. When the temperature changes, some parameters of the transistor will change, such as leakage current and carrier migration speed. The threshold voltage of the transistor decreases linearly with the temperature. The influence of power fluctuation can be ignored due to the low dropout regulator (LDO) providing low noise power for the FPGA core. Therefore, in the actual circuit, the voltage has little impact on the delay time. However, it is difficult to reduce the impact of temperature on the FPGA in many applications. It is necessary to calibrate the TDC online without affecting normal operation. A novel method, which consists in using a frequency counter to measure the ring oscillator frequency, is adopted to extrapolate and compensate its effect on the delay line. In this work, a ring oscillator based on 31 NOT gates and an AND gate is placed adjacent to the tapped delay line as shown in Figure 6. While the system is working, the ring oscillator frequency is measured and compared with that acquired at the beginning of the measurements.