# Low-Latency QC-LDPC Encoder Design for 5G NR
## 5 Results and Discussions  
### Discussions and Comparison with Related Work  
Presently, there are seldom studies on the hardware implementation of 5G QC-LDPC encoder. In this section, we discuss and compare our proposed scheme with the published state of art to show the differences of related work and explain the novelty of this work.  
Reference [19] proposed a 5G QC-LDPC parallel encoding algorithm based on an improved RU method. The encoder uses multiple cyclic shift networks to perform parallel encoding operations. A high throughput and low latency encoding architecture is implemented. Synthesis results on TSMC 65 nm CMOS technology with different submatrix sizes were carried out. The encoding delay is 48 clock cycles, and the throughput ranges from 22.1 to 202.4 Gbps. However, the CRC calculation was not included, and the parallelism of LDPC encoding can be further improved.  
Reference [20] adopted the same encoding algorithm as [19] and performs simulation on a single GPU platform. Compared with FPGA and ASIC implementation, GPU-based applications can be flexibly modified and adjusted. The experimental results achieved a maximum throughput of 62.6 Gbps at the BG2 8/9 code rate. This research verifies the parallelism and throughput of the QC-LDPC encoding algorithm. The implemented encoder is a solution for communication link hardware simulation, which is not applicable to hardware implementation.  
For Reference [21], when compared with [19], the maximum encoding latency is reduced by 20 clock cycles. Reference [21] implemented nine encoders for distributed lifting sizes of BG1 and BG2, the application specific integrated circuit (ASIC) synthesis for different lifting sizes. Encoders implemented for different lifting sizes have different performance parameters. Therefore, this work lacks the complete flexibility and configurability for 3 GPP standards and cannot meet the needs of all application scenarios.  
Reference [22] improved the QC-LDPC encoding algorithm in order to improve the utilization of hardware resources. The proposed architecture is built around the shift network, which improves the original serial encoding structure. The designed flexible shift network has different lifting factors and is divided into three working modes. Partial parallel implementation can provide a compromise between the achievable throughput and the utilization of hardware resources. This paper proposes an optimized coding algorithm and hardware scheduling scheme. Compared with [19; 21], the flexibility of the coding architecture has been greatly improved, but the coding delay has not reached the minimum. Under the operating frequency of 580 Mhz, the maximum delay is 875 ns and the peak BG1 throughput is 18.51 Gbps.  
In the existing related works, the design of the 5G QC-LDPC encoder is mainly to improve the coding algorithm and design a higher parallel architecture. There are some issues to be solved. There is no design for the complete LDPC encoding chain, such as the design a CRC calculation module. The encoder lacks flexibility and compatibility and the overall architecture cannot satisfy all the lifting sizes, which means that the encoder cannot encode for all PCM.  
In the work of this paper, in order to implement a lower latency 5G QC-LDPC encoder, we use more CN modules and increase the calculation speed of the second group of parity check bits (described in Section 4.2). We designed and implemented a higher degree of parallelism encoder architecture. The latency of the proposed encoder is only 33.75 ns at 800 Mhz, compared with the existing work, achieved a significant shortening. Meanwhile, the encoder fully meets the variable code length and code rate in the 5 Gscenario and improves the compatibility of the CNs to meet all the lifting sizes. Finally, the encoder designed a parallel acceleration structure for CRC calculation, so that the encoder can execute a complete 5G QC-LDPC encoding process.