# Single Photon Counting Performance and Noise Analysis of CMOS SPAD-Based Image Sensors
## 2 Solid-State Single Photon Counting Imaging Background  
Since the late 1980s, single photon counting (SPC) and time-gated imaging have been dominated by photo-cathode based intensifier techniques achieving high signal amplification through the \"photo-intensification\" of the generated electron cascade through the photo-electric effect using existing charge-coupled device (CCD) and CMOS image sensors (CIS) [1]. However, there are a number of drawbacks which limit their usage dependent on the application. Namely, the wavelength (colour) and spin properties of the photons are lost. Systems have high cost and are physically bulky due to the requirement of operation in a vacuum. Furthermore, photo-cathodes are sensitive to magnetic fields, they have high (kV) operating voltage and also cannot be used in vivo. Solid-state photon counting image sensor technologies, developed over the last 16 years, address some of these issues. The electron-multiplying CCD (EMCCD) was first demonstrated in 2001 [20], and has recently achieved 0.45 \(\mathrm{e^{-}}\) RN [21]. However, dark current is amplified through the electron multiplication process, and therefore external cooling is employed [22]. The first solid-state CIS pixel array with DSERN appeared in 2015, achieving best-case 0.22 \(\mathrm{e^{-}}\) RN in a remarkable 1.4 \(\mathrm{\SIUnitSymbolMicro m}\) pixel pitch (PP) with 403 \(\mathrm{\SIUnitSymbolMicro V/e^{-}}\) CVF [10]. Later, the first photon-counting CMOS imager achieved 0.27 \(\mathrm{e^{-}}\) RN, by external cooling and a high CVF of 220 \(\mathrm{\SIUnitSymbolMicro V/e^{-}}\) was realised by removing the reset transistor [23]. Oversampling ADCs have been employed in CIS to reduce all sources of readout noise (1/_f_, systematic temporal, source follower thermal, etc.) by correlated multiple sampling (CMS). The lowest published CIS RN in voltage (estimated by the author as CVF multiplied by RN) through four sample CMS is 31.7 \(\mathrm{\SIUnitSymbolMicro V}\) RMS [24]. Therefore, with CVF surpassing 400 \(\mathrm{\SIUnitSymbolMicro V/e^{-}}\) and RN as low as 31.7 \(\mathrm{\SIUnitSymbolMicro V}\) RMS, CIS with sub 0.15 \(\mathrm{e^{-}}\) RN appears not an unreasonable assumption in the near future. Single photon avalanche diode (SPAD) image sensors emerged in 2002 with bump-bonded SPADs [25] onto a digital counter or time-to-digital converter (TDC) per SPAD device recording the time of arrival of single photons. High temporal resolution (\(\approx\)50 ps [26]) permits time resolved imaging such as capturing light-in-flight [27], and seeing round corners [28]. These time correlated single photon counting (TCSPC) sensors have favoured the temporal precision of the photon's arrival over spatial resolution (>44 \(\mathrm{\SIUnitSymbolMicro m}\)) and fill-factor (<4%) which has, so far, restricted the wider adoption of these sensors. The digital circuit providing photon counting or timing occupies the majority of the pixel area to the detriment of photon detection. Chip stacking technology and the use of advanced digital CMOS process technologies are two methods that pitch reduction and fill factor increase will be achieved for SPAD-based image sensors in the future. Regardless of the technology, to realise high fill factor SPAD pixels, a trade-off is made between optical efficiency versus in-pixel functionality or the number of in-pixel transistors; low-transistor count analogue circuits will always be more compact than digital circuits. Our recent research has focused on time resolved photon counting applications using alternative analogue pixel designs that achieve higher fill factor and smaller pixel pitch, namely analogue counters [15], time-to-amplitude converters (TAC) [29; 30] and single bit binary memories [17]. Binary SPAD-based imagers, with the capability of recording one SPAD avalanche within an integration time, were first published in 2011 [31] and have recently been published at 65 k binary pixels [32] and in our work at 77 k binary pixels [17].