# Hardware Update through Digital TV Signals
## 4 DTV-Receiver Architectures and FPGA Reconfiguration Schemes
### FPGA Stand-Alone Reconfiguration Schemes  
The standard hardware development process begins with a design entry (e.g., hardware schematics or HDL) [54]. Then, an HDL is used to develop hardware specifications to configure an FPGA or a complex programmable logic device (CPLD). The most well-known HDLs are VHDL and Verilog. In the final step of standard design flows, a bitstream file (e.g., raw binary file (RBF)) is generated and then used to reconfigure an FPGA device. Typically, this is performed by an electronic design automation (EDA) tool, which is also provided by FPGA manufacturers [54]. Thus, it is possible to validate final design behaviors before delivering bitstreams.  
On the one hand, FPGA reconfiguration is typically performed with a tool provided by the hardware manufacturer. On the other hand, users may also develop it in a stand-alone reconfiguration scheme. In general, stand-alone strategies employ two modes (e.g., master or slave mode) to reconfigure FPGAs using a bitstream (pre-synthesized binary code). In master mode, an FPGA is typically used to control a reconfiguration process. However, in slave mode, FPGA configuration is controlled by an external device (e.g., a microcontroller, CPLD, or another FPGA). Additionally, the standard IEEE 1149:1 [55], a joint test action group (JTAG), is another mode commonly used by FPGA manufacturers. Typically, the latter provides a JTAG cable and a programming tool, which are used to reconfigure their FPGA development boards. Those cables can work with different communication interfaces, such as USB, parallel or serial ports, or ethernet. They are an attractive way to construct a host/target communication interface, which has been commonly adopted by several embedded systems and already largely tested and validated. JTAG has four control signals--test data input, test data output, test mode selects, and test clock--which are used to configure devices through a test access port controller [55].  
The available literature also presents stand-alone open-source JTAG libraries [56; 57], which enable a variety of JTAG-based manufacturer communication cables. Those libraries can use the serial vector format (SVF) [58] to configure several FPGA models. SVF files, which describe actions over JTAG interfaces, are standard for exchanging descriptions of high-level IEEE 1149.1 (JTAG) bus operations [58]. Then, a stand-alone program can parse and play an SVF file, thus reconfiguring an FPGA.  
SVF files can be obtained from other formats through a converting tool or even an FPGA manufacturer tool. Indeed, most FPGA manufacturers commonly provide this file, used as a standard format to reconfigure devices. A reference DTV receiver was used as a host device and a commercial FPGA board as a target device to create a host/target physical connection. Based on the JTAG program mode, the USB manufacturer's programmer cable connects both sides, as seen in Figure 4.  
Figure 3: Receiver architecture comprises an air interface (frontend), demultiplexer, H.264 decoder, and memory.  
The stand-alone FPGA programming system was based on an open-source JTAG reference code adapted to fit the chosen DTV receiver (i.e., the module responsible for reconfiguring the FPGA). Some third-party libraries were integrated into the receiving system so that the open-source code could work properly. Therefore, a resident application (reconfiguration module) becomes able to control the FPGA board's read and write (R/W) operations.