## 4 Efficiency Boundary Prediction of PSiP  
Power losses of PSiPs mainly include power losses of switches and inductors. Only considering power losses of inductors and power switches, the PoL power supply efficiency is expressed as  
\[\eta=\frac{P_{o}}{P_{o}+P_{ind}+P_{switch}}=\frac{1}{1+\frac{P_{ind}}{P_{o}}+ \frac{P_{switch}}{P_{o}}}, \tag{21}\]  
where \(P_{o}\), \(P_{ind}\) and \(P_{switch}\) are the output power, power losses of inductors and power switches, respectively. In order to calculate the power losses of switches and inductors with the consideration of switching frequencies and power levels, \(V_{in}\) = 5 V, \(V_{o}\) = 1.8 V, \(f_{s}\) = 1\(\sim\)100 MHz, \(\bigtriangleup\)\(i_{L}\)/\(I_{L0}\) = 0.4 and \(P_{o}\) = 0.1-10 W are used in calculations. For the power loss of integrated Si LDMOSFETs, optimized sizes of integrated Si LDMOSFETs at 350 nm, 180 nm and 90 nm processes are calculated at different switching frequencies and output currents according to (7) and (10). The parameters of optimized integrated Si MOSFETs are given in Table 5. As the switching frequency increases, the \(R_{DS}\) of integrated Si MOSFET increases, and \(C_{ISS}\), \(C_{RSS}\) and \(C_{OSS}\) decrease, which trades off power losses among switching loss, driving loss and conduction loss. Furthermore, based on the parameters of Si LDMOSFETs, the power losses of Si LDMOSFETs, \(P_{switch}\), at 350 nm, 180 nm and 90 nm are shown in Figure 10(a). Furthermore, the efficiency boundary, \(P_{switch}\)/\(P_{o}\), is calculated as shown in Figure 10(b). In Figure 11a, the optimized power loss of the integrated Si LDMOSFET is proportional to \(f_{s}^{1/2}\) instead of \(f_{s}\), which shows the potential for high-frequency switches. As the switching frequency increases, the power loss of the integrated Si LDMOSFET increases at a rate of \(f_{s}^{1/2}\). As the power level increases, the power loss of the integrated Si LDMOSFET increases at a rate of \(P_{o}\). In addition, the power losses of the integrated LDMOSFET under more advanced processes are reduced due to reductions of the parasitic capacitors and resistors. For the power loss of air-core inductors, the required inductance value is calculated according to the switching frequency and ripple ratio of the inductance current. Then, with consideration of the optimized winding structures, the geometric parameters (\(D\), \(d\), \(\phi\)) are estimated based on the inductance value according to (13) and (17). Furthermore, based on (14) and (18), the coil length is calculated according to inductance geometric shapes. Finally, based on (11), the power losses of air-core inductors, \(P_{ind}\), with winding structure optimizations are shown in Figure 12a. Furthermore, the efficiency boundary, \(P_{ind}/P_{o}\), is calculated as shown in Figure 12b. The following assumptions are introduced into the calculations according to common engineering values:  
* For the tightly winding solenoid inductor, its wire width and coil turn are set as 1 mm and 10. * For the planar spiral inductor, its thickness and coil turn are set as 100 \(\upmu\)m and 10. Since it has a wide outside winding and narrow inside winding structure, its width is set as 1-2 mm. In Figure 12a, as the switching frequency increases, the coil-wire length, \(l\), and skin depth, \(\delta\), both decrease. Based on calculations, since the effect of coil-wire length reduction on power loss is greater than that of skin effect at 1-100 MHz, the power losses of air-core inductors decrease as the switching frequency increases. As the power level increases, the inductance current, \(I_{L}\), and ripple, \(\triangle i_{L}\), increase. The increase of \(\triangle i_{L}\) results in reductions of inductance, \(L\), and coil-wire length, \(l\). Therefore, the power losses of air-core inductors are at the minimum value as the power level increases. Combined with power loss calculations, \(P_{switch}/P_{o}\) and \(P_{ind}/P_{o}\) are shown in Figures 11b and 12b.