## 5 MASSIVE Test-Bed
### Receiver Implementation Architecture  
Given the nature of the operations in the ME-SSA receiver blocks, the implementation was carried out in a mixed CPU/GPU architecture in order to optimize the performance and to support real-time processing. The performance of the digital signal processing algorithms performed with general-purpose processors, both CPUs and GPUs, depends on how much the operations can be executed using a vector algebra. In the state-of-the-art CPUs architectures, single input multiple data (SIMD) extensions can be exploited to run batches of floating-point vector operations on contiguous memory, with a single operation that is loaded in the execution pipeline. On the other hand, GPUs are inherently designed to execute the same (or very similar) operations on large batches of memory using a multitude of (logical) threads efficiently. In the MSD algorithm, all the basic elementary blocks (de-spreading, re-spreading, weight computation, phase rotation, frequency shift) can be implemented in a vector  
Figure 11: Real rack configuration of the MASSIVE test-bed. Figure 10: Block diagram of the MASSIVE test-bed. wise manner; however, in a mixed CPU/GPU application, a decision has to be made on partitioning of the functions among different units. While the final decision depends on fine-level design choices and on the final hardware architecture, the following guidelines can be established:  
* Sample-level operations are better suited for implementation on the GPU,
* Symbol-level operations are better suited for implementation on the CPU. While the copy, typically occurring via the PCIe bus, happens with a relatively high throughput, in the order of hundreds of GB/s, the copies are scheduled in a lazy manner by the GPU driver to achieve an uninterrupted flow of operations. This leads to unpredictable latencies in the digital processing chain. Therefore, the trade-off between copying memory back and forth between the CPU and GPU for faster execution in the GPU while introducing unpredictable latency has been studied, but it needs further careful investigations. At a system level, the MSD operations cannot be executed all together with a single command in an ideal processing pipeline. This is due, mainly, to the asynchronous nature of the chosen transmission protocol. The incoming asynchronous bursts overlap only partially in time. The weight computation in Equation (1) depends on the number of overlapping bursts. Therefore, it is required to iterate at every boundary between bursts, preventing a massive parallelization. The actual number of boundaries for each sample window increases with both the throughput and the spreading factor. Therefore, two fundamental trade-offs exist:  
* First, as the throughput increases, the advantages of utilizing MSD become more prominent, but processing is more demanding and the MAI due to the cancellation residual is also increasing,
* Second, as the spreading factor increases, the use of vector operations becomes more beneficial because of the burst sizes, therefore, the associated contiguous memory becomes bigger, but there are more burst boundaries per sample window, leading to more operations needing to be performed per second. Finally, the GPU memory could be a limiting factor to be considered as part of the implementation trade-offs. The CPU memory size is not a major constraint, since modern CPUs/systems allow for a large memory. On the contrary, all operations executed by the GPU must reside in the internal memory of every GPU card. Compared to that of CPUs, the available memory of GPU cards is much more limited and not easily upgradable. It is therefore of paramount importance that all data structures are initialized before the digital processing starts. This is because allocating new memory in both the CPU and the GPU is an expensive operation that may lead to an unpredictable latency. Therefore, as part of the MSD operation, a balance between the sample window size and the number of maximum branches executed concurrently should be drawn.