# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 3 Methods of Reducing Power Consumption in CMOS Integrated Circuits
If \(f_{op}=0\), then an FSM is in the idle mode (it is \"sleeping\"). To \"wake up\" an FSM, it is  
Figure 4: Providing RPC for a digital system. Figure 3: Classification of reduced power consumption methods. necessary to start the clock generator. In turn, the generator takes some time to stabilize the operating frequency. An increase in the latency time is the second negative effect of DVFS. Therefore, DVFS is connected with a so-called power overhead [70]. The power overhead includes the three following components: the extra chip area, additional power consumption, and increased latency time. It is necessary to find a reasonable trade-off between the inevitable overhead and the required characteristics of a digital system. We do not discuss these methods in this paper. As follows from Figure 3, there are three groups of fine-grained methods of RPC. The clock-gating (CG) approach is connected with interrupting connections between the clock generator and synchronization inputs of flip-flops. There are two approaches based on CG: (1) the decomposition of an FSM and (2) the input disability. This approach is connected with using additional blocks \(RPC1-RPC1\) to control the timing of automata \(FSM1-FSM1\) (Figure 4). Thus, this approach is connected with an RPC overhead. The second group of FGMs consists of special methods of state assignment. The states \(a_{m}\in A\) are encoded in a way that reduces the value of switching activity \(\alpha\). From (10), this reduces the value of \(P_{dyn}\) (if \(C_{par}\), \(V_{dd}\), and \(f_{op}\) have constant values). Sometimes, this leads to increasing the value of the bit depth of state codes, \(R\), compared to its minimum value determined by (4). This growth is the RPC overhead for this group of FGM. The third group is based on the replacement of LUTs by EMBs. In fact, we are moving from fine-grained LUTs to coarse-grained EMBs. As follows from Figure 5, some group consisting of four LUTs and their interconnections is replaced by a single EMB. The circuit (Figure 5a) consists of 4 LUTs and 11 interconnections. It is replaced by the circuit having a single EMB and six interconnections (Figure 5b). These interconnections correspond to inputs and outputs of this circuit. There are no additional interconnections which can be found in the LUT-based circuit (Figure 5a). Obviously, the EMB-based circuit has better area, time, and power characteristics than the equivalent LUT-based circuit. It does not require any power overhead. But this approach has two limitations. First, it can be used if there are \"free\" EMBs (very often, EMBs are used for implementing operational blocks of a system). Second, an EMB can be used if the number of arguments of an SBF does not exceed the number of address inputs, \(S_{A}\). Now, we discuss the most known fine-grained methods of reducing power consumption in the next three Sections of this survey. These methods are the clock-gating, FSM decomposition, state assignment restricting the switching activity, and replacing LUTs by EMBs.