# Real-Time Optimization of RISC-V Processors Based on Branch Prediction and Division Data Dependency
## 4 Experiment and Result Analysis
### Processor Real-Time Testing and Performance Analysis
#### 4.3.3 Summary of Real-Time Testing  
The resource usage comparison between the two processors is shown in Table 14.  
Based on the comprehensive analysis of the experimental results, when executing the Task A test program (CoreMark test program), the hardware real-time parameter H\({}_{\text{rtp}}\) before optimization was 4.4001 (mean: 77.01907 s, variance: 3.47505). After optimization, under the same program execution conditions, the H\({}_{\text{rtp}}\) value decreased to 4.3651 (mean: 74.69959 s, variance: 2.95681). Analyzing from the perspective of mean and variance, there is an improvement in the processor's real-time performance.  
The improvement is not significant for the following reasons:  
* The final H\({}_{\text{rtp}}\) value undergoes a logarithmic operation. During the design of H\({}_{\text{rtp}}\), considering that the execution time for embedded processors running test tasks is generally less than 1 s, a logarithmic operation was adopted to highlight small optimizations.
* In the CoreMark benchmark test program, the improvement in time data is not significant (approximately only a 3 s reduction, with a total duration exceeding 70 s), leading to less noticeable optimization in program execution speed. In the subsequent division test case, however, there is a more substantial change in the H\({}_{\text{rtp}}\) value.  
When executing the Task B test program (division test program), the hardware real-time parameter H\({}_{\text{rtp}}\) was \(-8.2173\) before optimization. After optimization, under the same program execution conditions, the H\({}_{\text{rtp}}\) value decreased to \(-8.9997\), showing an improvement of 0.7824, indicating an enhancement in the processor's real-time performance.  
In conclusion, the analysis demonstrates that the optimized Rev-riscv-II processor shows improved hardware real-time performance under the assumed real-time system requirements for an automotive autonomous driving system. This aligns with the expected theoretical results, suggesting that H\({}_{\text{rtp}}\) is a reliable metric for evaluating the real-time performance of hardware processors.  
In addition, we used the CoreMark benchmark suite to test the performance of the two processors. We also compared their performance with that of similar-level processors, as shown in Table 15. The performance of the Rev-riscv-II processor is superior to that of the Hummingbird E203 [22] and lies between that of Cortex M0+ [24] and Cortex M3 [24]. Compared to the Rev-riscv processor before optimization, the performance improvement is approximately 5.1%.  
\begin{table}
\begin{tabular}{c c c} \hline
**Test Item** & **Rev-Riscv** & **Rev-Riscv-II** \\ \hline Number of Tests & 100 & 100 \\ Mean Runtime & 269.85 μs & 123.24 μs \\ Variance of Runtime & 2.74826 \(\times\) 10\({}^{-11}\) & 2.47469 \(\times\) 10\({}^{-11}\) \\ H\({}_{\text{rtp}}\) Value & & \\ (Convert the unit from & \(-8.2173\) & \(-8.9997\) \\ microseconds to seconds) & & \\ \hline \end{tabular}
\end{table}
Table 13: Test data for Rev-riscv and Rev-riscv-II when running the division test program.  
\begin{table}
\begin{tabular}{c c c} \hline
**Resource Name** & **Rev-Riscv** & **Rev-Riscv-II** \\ \hline LUT & 11,203 & 15,161 \\ LUTRRAM & 4200 & 4241 \\ FF & 6211 & 6428 \\ IO & 18 & 18 \\ \hline \end{tabular}
\end{table}
Table 14: Resource consumption data for Rev-riscv and Rev-riscv-II.