# Hardware-Accelerated Data Readout Platform Using Heterogeneous Computing for DNA Data Storage
## 7 Conclusions  
We present a hardware-accelerated DNA data readout architecture based on heterogeneous computing. To address the challenges of large-scale DNA data storage, particularly the high complexity of readout recovery and the vast number of sequencing reads, we propose a multistage pipelined primer sequence identification and index check module implemented in hardware to achieve high data throughput. Our design features a parallel hardware architecture for majority voting and error correction decoding, ensuring efficient and reliable data processing. Additionally, we optimized the deinterleaver module using a ping-pong structure, further enhancing the throughput and overall system performance. The performance of the system was evaluated using simulated sequencing datasets with varying error rates and coverages. The results showed a peak speedup of up to 373.1 times, allowing 59.4 MB of stored data to be read in 12.40 s. These results demonstrate the potential of the proposed architecture for large-scale DNA data storage applications. Future work will focus on extending the system to support multi-core and multi-board concurrency for the efficient scheduling and processing of multiple readout tasks. The current hardware kernel successfully processed a single data block containing approximately 59.4 MB of valid payload, demonstrating the scalability of the proposed design. For future scaling to larger datasets, the entire data stream can be partitioned into multiple \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Platform** & **Average Power (W)** & **Time (s)** & **Energy (J)** \\ \hline CPU & 15.22 & 898 & 13,662.56 \\ FPGA & 7.39 & 9.85 & 72.81 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Comparison of average power consumption and runtime energy cost for processing 50 M reads. \begin{table}
\begin{tabular}{l c c c} \hline \hline
**Module** & **LUTs** & **Registers** & **Block RAM** \\ \hline Primer sequence identification module & 751 & 639 & – \\ Index check module & 41 & 20 & – \\ Copy count memory & 2620 & 1691 & 684 \\ Majority voting module & 1448 & 724 & – \\ Valid-sequence filtering module & 109 & 33 & 16 \\ Deinterleaver module & 486 & 1066 & 21 \\ LDPC decoding module & 68,302 & 71,178 & 115 \\ \hline Total & 78,897 & 81,047 & 911 \\ Utilization (\%) & 6.67 & 3.43 & 42.18 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Resource usage of each module in acceleration kernel. independent blocks of this size. Since each data block can be processed independently, parallel execution can be achieved by distributing the sequencing data across multiple FPGA boards and scheduling concurrent kernel instances on each board. This strategy will significantly improve the throughput of the proposed system when deployed in large-scale DNA storage scenarios. [PERSON] conceived the project. [PERSON] and [PERSON] designed the storage system and heterogeneous computing architecture. [PERSON] wrote the hardware acceleration programs. [PERSON] wrote the encoding and decoding programs. [PERSON], [PERSON] ([PERSON]), [PERSON] ([PERSON]), [PERSON], [PERSON] and [PERSON] wrote the manuscript. [PERSON] validated the results and revised the manuscript. All authors have read and agreed to the published version of the manuscript. This research was partly supported by the National Key Research and Development Program of China (2023 YFA0913800). Not applicable. The data presented in this study are available on request from the corresponding author. The authors declare no conflicts of interest. The following abbreviations are used in this manuscript: