# GaN-on-Si: Monolithically Integrated All-GaN Drivers for High-Voltage DC-DC Power Conversion
## 3 The Proposed Gate Driver for Buck Converter
### Buffer Stage  
The buffer stage design uses three stages of stacked inverters in series [23]. The first two stages are D/E stacked inverters, and the last stage is E/E stacked inverters. In order to  
Figure 2: The proposed integrated buck converter using high\(-\)voltage GaN process. The components in the dash box are off-chip.  
Figure 6 shows the switching waveforms of the IC tested in buck mode with a drive signal switching frequency of 1 MHz, a duty cycle set to 50%, and an input voltage of 200 V. The gate voltage, Vgd, of the low-side driver is slightly affected by the high-side driver during the rise/fall of Vsw. However, no overshoot or ringing was observed in Vsw, even though the high-side gate voltage, Vgu, exceeds the input voltage due to bootstrapping. The rise and fall times of the 200 V switching pulse are 54.4 ns and 57.6 ns, respectively. Table 4 compares the performance of high-speed GaN drivers with the latest published work using Si-based technology. Our implementation demonstrates high voltage operation for such an application, and ease of integration with power devices.  
The efficiency performance of the designed buck converter was measured under the following conditions. The load is from 19 to 160 ohms, 1 MHz drive signal and its duty cycle is set to 49-51%, and the input DC voltage is given 40 V, the auxiliary voltage is 5 V and \(-\)5 V, respectively. Figure 7 shows one of the measured output voltages of the converter and the switching waveforms. The propagation delay between VH (high-to-low) and Vsw (low-to-high) is less than 10 ns. The output voltage of the buck is close to 20 V DC as expected.  
System efficiency is calculated as the ratio of DC output power to DC input power. The measured DC power consumption of the EED driver and the system efficiency of the buck converter are shown in Figure 8. When the output power exceeds 8 W, the efficiency of the system exceeds 90%. Due to the shoot\(-\)through current inside the EED driver from the 5 V to \(-\)5 V supply when M1 is off, the power consumption will increase slightly as the load becomes heavier. The measured DC power dissipation is about 0.4 to 0.6 W, which accounts for most of the power loss in the buck converter. After efficiency analysis [27], the conduction loss and output capacitance loss of the GaN power devices is about 124 mW. This shows another advantage of using GaN as a switch for high-speed switching power converters. The crossover loss of the hard-switched converter is estimated to be about 307 mW under a 40 ohm resistive load. Figure 9 shows a pie chart of the estimated percentage power loss for each device in the converter at 90.7% efficiency. Table 5 summarizes the integrated buck converter performance with other previously published works. Our implementation exhibits high efficiency at 8 to 15 W output power, and this architecture can be extended to high power switching converters with better package support.  
\begin{table}
\begin{tabular}{c c c c c} \hline
**Parameter** & **[14]** & **[15]** & **[18]** & **This Work** \\ \hline Structure & Active BST balancing & BGRCC & Current-mode (SSFD + GR) & EED \\ Technology & Si-based & Si-based & BCD & GaN on Si \\ Switching frequency (MHz) & 10–30 & 2–10 & 10 & \(>=\)1 \\ Level-shifter & Yes & Yes & Yes & No \\ Slew-rate (V/ μs) & 26 K & 1.8 K & 5.7 K & 3.7 K \\ Maximum operating voltage (V) & 40 & 18 & 40 & 200 \\ \hline \end{tabular}
\end{table}
Table 4: Performance comparisons between different types of high-speed GaN drivers.  
Figure 7: The half-bridge operated with Vin = 40 V, iL1_avg = 1 A, Vsw switching at 1 MHz and \(\sim\)50% duty cycle.