## 2 Circuit Design  
Figure 1a shows the illustrative diagram of the proposed low-VDD and low-PDC down-conversion mixer. In theory, the \(Z_{\rm in}\) of a grounded lossless \(\lambda\)/4-TL (denoted TL\({}_{\rm QW}\)) is infinite at the operation frequency of f0 (=\(\omega_{0}\)/2\(\pi\)) and the odd-harmonic frequencies (3f0, 5f0, etc.) and is zero at DC and the even-harmonic frequencies (2f0, 4f0, etc.). Instead of the transformer coupling approach [7], two \(\lambda\)/4-TL-C-based couplers are used to achieve near perfect coupling from the RF transconductance (gm) stage to the LO switch transistors. The \(\lambda\)/4-TL-C-based coupler has the merits of a straightforward design and layout, as well as harmonic suppression. The low VDD and optimized noise, gain, and linearity design of the mixer become possible due to the separate DC bias of the RF gm stage and the LO-transistors/IF loads. In brief, the bias currents of transistors M\({}_{3}\)/M\({}_{4}\) and M\({}_{5}\)/M\({}_{6}\) flow to the ground through TL\({}_{\rm QW}\) instead of the RF gm stage or transformer secondary coil. The outputs of the RF gm stage transmit to M\({}_{3}\)/M\({}_{4}\) and M\({}_{5}\)/M\({}_{6}\) near perfect through the \(\lambda\)/4-TL-C-based couplers instead of direct transmit or the transformer coupling. This is the way to achieve low VDD and optimized design. Moreover, CCPT-RL-based core IF load is used for load-impedance (Z\({}_{\rm L}\))/CG enhancement while keeping a low P\({}_{\rm D}\) and wide IF bandwidth. The BSFB technique, i.e., connection of the gm-stage transistors' body to their drain via a large body resistance R\({}_{\rm B}\) (13.1 k\(\Omega\) in this work) is used for threshold voltage (V\({}_{\rm th}\)) and VDD reduction, in addition to substrate leakage suppression. CG and NF enhancement at the same or even a lower P\({}_{\rm D}\) is achieved because of the lower VDD and higher gm due to larger overdrive voltage (V\({}_{\rm ov}\)) or bias current [11]. Figure 1: Illustrative diagrams of (**a**) a mixer using a \(\lambda\)/4-TL-C-based coupler, and (**b**) the current-source load. (**c**) Layout and (**d**) simulated results of the coupler. Figure 1b shows the current-source-load design of the gm stage. A lossless TLqw with an electrical length (\(\theta\)) of 90\({}^{\circ}\) and characteristic impedance (\(Z_{\rm C}\)) of \(Z_{\rm TD}\), such as the one in Figure 1c (with \(Z_{\rm T0}\) of 89.7 \(\Omega\)), can be modeled by an inductance (L\({}_{\rm L}\)) and two parallel end-capacitance (C\({}_{\rm L}\)) as follows [12]. \[{\rm L}_{\rm L}=\frac{Z_{\rm T0}}{\omega_{0}} \tag{1}\]  
\[{\rm C}_{\rm L}=\frac{1}{Z_{\rm T0}\omega_{0}} \tag{2}\]  
On the condition that \(Z_{\rm in1}\) is equal to zero, \(Z_{\rm in2}\) is infinite at \(\omega_{0}\) since the parallel of L\({}_{\rm L}\) and C\({}_{\rm L}\) exhibits an infinite impedance at \(\omega_{0}\) from Equations (1) and (2). In the design of the current-source load of the gm stage, the parasitic capacitance (C\({}_{\rm d}\)) at drain nodes D1/D2 of M\({}_{1}\)/M\({}_{2}\) should be considered. In theory, a TLqw with \(Z_{\rm C}\) of \(Z_{\rm T0}\) is equivalent to a TL (with smaller \(\theta\) (of \(\theta_{1}\)), larger \(Z_{\rm C}\) (of \(Z_{\rm T1}\)), and the same inductance (L\({}_{\rm L1}\) = L\({}_{\rm L}\))) and two extra parallel end-capacitance C\({}_{\rm d}\) values (=\({\rm C}_{\rm L}-{\rm C}_{\rm L1}\)). One of the required C\({}_{\rm d}\) values is provided by the parasitic C\({}_{\rm d}\) and the other has no effect (due to in parallel with a short-circuit). \(Z_{\rm T1}\) and C\({}_{\rm d}\) are given by  
\[Z_{\rm T1}=\frac{Z_{\rm T0}}{\sin\theta_{1}} \tag{3}\]  
\[{\rm C}_{\rm d}=\frac{\cos\theta_{1}}{Z_{\rm T0}\omega_{0}} \tag{4}\]  
Suppose \(Z_{\rm T0}\) is 65 \(\Omega\), then L\({}_{\rm L}\) is 369.6 pH and C\({}_{\rm L}\) is 87.4 fF at f\({}_{0}\) of 28 GHz according to Equations (1) and (2).