# Constrained Optimization of FPGA Design for Spaceborne InSAR Processing
## 1 Introduction
Many technical challenges need to be addressed to build an FPGA-based on-board InSAR processing system, including the matrix transpose structure [36] and the trade-off between processing capacity and resources. The matrix transpose module realizes the mapping to the Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) from the partitioned matrix, including two-dimensional mapping [36; 37; 38; 39; 40] and three-dimensional mapping [41; 42; 43; 44]. With the increasing complexity of spaceborne processing functions, the software-hardware co-design method has been adopted to shorten the development and maintenance cycle of the System on Programmable Chip (SoPC). The SoPC system is based on the Advanced eXtensible Interface (AXI). However, the existing matrix transposition scheme is unsuitable for the system under the condition of AXI for the following reasons. Firstly, most of the existing transposition schemes use native interfaces, and the address space of the native interface differs from that of the AXI. To combine the two modes, additional steps are needed to change the address between the two modes, thus occupying more FPGA resources. Secondly, the existing method of matrix transposition of the native interface improves the storing efficiency by analyzing the difference in storage efficiency of data in the row, column, and bank, which requires a three-dimensional storage space. However, the storage space of the AXI is performed as a two-dimensional storage space, which is not compatible with the three-dimensional mapping structure of the native interface. Therefore, to address the compatibility issue, it is necessary to study the matrix transpose structure under AXI conditions. In on-board processing, given the limited resources and high-performance requirements, the FPGA design is faced with the contradiction between processing capacity and resource usage. Researchers have developed many FPGA design techniques to improve processing capacity and reduce resource consumption, which could be classified into three categories. First, utilize FPGA resources fully. [PERSON] et al. [45] implemented two int8 multiplications with one DSP48E2 in a new module. The DSP resources were fully used to improve the system processing capacity. However, although such a method can increase processingcapacity, the field of application is limited. For example, it cannot work in high-bit data widths, such as 32 bit. Second, integrate heterogeneous processors perfectly. To take advantage of different processors, some researchers [43; 46; 47] moved the operations that consume many FPGA resources to the DSP so that the FPGA resources are significantly saved with processing capacity improved. However, this method increases the complexity of the system. The scale of the system increases the difficulty of control. Moreover, the communication rate between heterogeneous processors probably hampers the system processing capacity. Third, modify algorithm flow correspondently, such as quantization and compression. Many researchers [48; 49] used the quantization method to reduce the data bit width and the resources by converting the floating-point data into low-bit data. By pruning algorithm steps, [PERSON] et al. [50] used the compression method to reduce the overall computation, thus reducing the resources of FPGA. This method can fundamentally lessen the computation in the FPGA. However, it may lead to the loss of algorithm accuracy and not directly address the issue between resources and processing capacity. In summary, the existing technical solutions do not directly address the contradiction between processing capacity and resources. Little research has explored the trade-off relationship between processing capacity and resources based on the FPGA system without modifying the algorithm and structure. Therefore, faced with the dual constraints between resources and processing capacity, this paper proposes an FPGA design method based on the gradient descent theory.