# Low-Latency QC-LDPC Encoder Design for 5G NR
## 5 Results and Discussions
### Evaluation Results  
The RTL code of our designed encoder has been validated using Modelsim, synthesized using Synopsys Design Compiler, and placed and routed using Synopsys IC Compiler. Two scenarios are for simulation. Scenario 1 is encoded under BG1. Two information code block lengths are used, \(A_{1}\) = 8424 bits and \(A_{2}\) = 1920 bits. After attached TB-CRC, and \(K_{1}\) = 8448 bits, \(K_{2}\) = 1936 bits, the initial code rate is \(R_{1}\) = 1/3, \(R_{2}\) = 8/9. Scenario 2 information length is 3824 bits, code rate is 1/5, and encoding is under BG2. The system clock is 800 MHz, the total encoding delay of Scenario 1 is 33.75 ns, and the total encoding delay of Scenario 2 is 18.75 ns. Similar to [25], Table 1 compares the hardware parameters and performance indicators of the proposed encoder implemented by the ASIC with similar references. Throughput in the table is calculated according to Equation (17), where \(N\) represents the total encoded output that has not undergone codeword processing, \(R\) is the code rate, \(f_{max}\) is the highest frequency of the system clock, and \(CC\) is the cycle clocks consumed to obtain all parity checks. \[Throughput=\frac{N\times R\times f_{\max}}{CC} \tag{17}\]  
The layout based on the CMOS technology synthesis with SMIC 28 nm is shown in Figure 11, because SRAM is replaced by register file; it is a scattered flattening place and routing layout, so the functional module division is not marked in the Figure 11. The silicon layout shows that the total equivalent gates are about 1126K cells, and the total silicon area is 0.712 mm\({}^{2}\). The peak dynamic power consumption under 800 Mhz is 123.5 mW. The throughput/area is defined as the normalized throughput area ration (TAR), which is 362 Gpbs/mm\({}^{2}\) in this design. The area shows the resource usage of the encoder, and the number of equivalent gates represents the complexity of the implementation. Under BG2, when \(Z\) = 384, 3840 information bits are encoded to output 19,200 bits, and the encoder achieves the largest equivalent bit operations per clock: 1280 bit/cycle. \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline
**Encoder** & **Standard** & **Technology** & **Implemented** & **\(f_{\max}\)** & **CC** & **Throughput** & **(Gpbs)** & **Area** & **Gate Counts** & **Equivalent Bit** \\
[19] & 5G NR & ASIC 65 nm & (BG1,Z14) & 645 & 48 & 89.0 & 0.171 & 214K & 198 \\
[19] & 5G NR & ASIC 65 nm & (BG1,Z352) & 600 & 48 & 202.4 & 0.389 & 486.4K & 484 \\
[19] & 5G NR & ASIC 65 nm & (BG1,Z96) & 714 & 48 & 43.8 & 0.117 & 146.3K & 132 \\
[20] & 5G NR & CUDA GPU & (2178,1936) & 1770 & 48 & 62.6 & - & - & 41.5 \\
[21] & 5G NR & ASIC 65 nm & (BG1,Z384) & 575 & 28 & 173.7 & 0.511 & 639.5K & 905 \\
[21] & 5G NR & ASIC 65 nm & (BG2,Z352) & 586 & 16 & 128.9 & 0.435 & 545.2K & 1100 \\
[26] & GF(2*)QC & ASIC 28 nm & (2016,1764) & 400 & 256 & 6.3 & 0.007 & 8.66K & 7.875 \\
[27] & IRA-LDPC & ASIC 28 nm & (568,512) & - & 57 & 3.57 & - & 58.5K + (512 \(\times\) 64) & 9.96 \\ Proposed 1 & 5G NR & ASIC 28 nm & (BG1,25344,8448) & 800 & 27 & 257.9 * & 0.712 & 1126K & 938 \\ Proposed 1 & 5G NR & ASIC 28 nm & (BG1,2178,1936) & 800 & 27 & 62.0 * & 0.712 & 1126K & 80.7 \\ Proposed 1 & 5G NR & ASIC 28 nm & (BG2,19200,3840) & 800 & 15 & 213.0 * & 0.712 & 1126K & 1280 \\ \hline \hline \end{tabular}  
* Encoder implementation satisfies full lifting size \(Z\) and includes CRC calculation.
* Based on Equation (17), other throughput is derived from references  
\end{table} 
Table 1: Comparison of hardware implementation of 5G QC-LDPC and other standard LDPC encoders. In the proposed architecture, a configurable barrel shift register uses approximately 13.45K equivalent gates; the encoder uses 64 CNs, so CNs and configurable circuits utilize the largest hardware resources. In addition, the LUT and XOR tree structure of 256-bit parallel CRC calculation uses the remaining resources.