## 2 Proposed SoC-Balancing Strategy without Saturation
### Selection of the Accelerating Factor in CDRs  
To be convenient and general, \(m\) is set as 3 in this paper. Then, the value of \(n\) is discussed in detail. At first, \(n\) should be a positive integer to reduce the computing burden of the microprocessors. Assuming that each phase current can follow its reference immediately, this is an ideal case. Combining Equations (1)-(3), the ideal curves with the proposed strategy in parallel applications are plotted in Figure 5 when \(i_{\text{sum}}\) remains constant. The system parameters are given in Table 2. Under the same conditions, \(n\) mainly affects the balancing time and initial current distribution. If a higher value of \(n\) is used, the required time to realize SoC consistency is shorter, but the ESU with a higher SoC releases a higher current, and this threatens the safe operation of the relevant unit. For the shortest balancing time, it is essential to confirm the maximum \(n\). Its selection process is described as follows.  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Parameters** & **Symbol** & **Value** \\ \hline Switching frequency & \(f_{\text{s}}\) & 20 kHz \\ Inductance & \(L_{1},L_{2},L_{3}\) & 4 mH \\ Capacitance & \(C\) & 2200 uF \\ Load current & \(i_{\text{o}}\) & 20 A (parallel) \\ DC-bus voltage & \(u_{\text{dc}}\) & 6 A (series) \\  & \(u_{\text{dc}}\) & 30 V (parallel) \\  & & 90 V (series) \\ Initial SoC & \(SoC_{10};SoC_{20};SoC_{30}\) & 0.9; 0.8; 0.7 \\ Battery capacity & \(Q\) & 45 Ah \\ Magnitude of carrier waves & \(A_{\text{m}}\) & 37,500 \\ Proportional gain of voltage loop & \(k_{\text{pv}}\) & 0.5 \\ Integral gain of voltage loop & \(k_{\text{iv}}\) & 5 \\ Proportional gain of current loop & \(k_{\text{pi}}\) & 1000 \\ Integral gain of current loop & \(k_{\text{ii}}\) & 10,000 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Key system parameters.  
Figure 4: Curve of OCV versus SoC.  
In parallel scenarios, the upper limitation of \(n\) is governed by \(i_{\text{allow}}\), the maximum allowable current of the PCU. For our testing platform, the allowable currents of the power switch, battery, and inductor are 120 A, 450 A, and 40 A, respectively. Thus, \(i_{\text{allow}}\) is set as 40 A to ensure the safe operation of the overall system. Then, \(n\) should satisfy the following inequality:  
\[\frac{\max(SoC_{\text{k0}}^{n})}{\sum_{k=1}^{m}SoC_{\text{k0}}^{n}}\times i_{ \text{sum}}\times(1+\eta)<i_{\text{allow}} \tag{5}\]  
where \(\max(\,)\) is the maximum function. Positive \(\eta\) is a margin coefficient used to prevent overcurrent in real applications. Here, the actual upper limit of the current \(i_{\text{allow}}/(1+\eta)\) is denoted as \(i_{\text{satu}}\). According to Figure 5, the highest peak current appears at the initial stage of discharge. Then, \(i_{\text{sum}}\) can be roughly estimated according to energy conservation. Here, \(i_{\text{sum}}\) is 50 A, and \(\eta=0.2\). Consequently, \(i_{\text{satu}}\) is 33 A, and the maximum \(n\) is 8.  
As for series scenarios, the load current in a boost converter also serves as the lower limit of the phase currents, \(i_{\text{satt}}\). Thus, both \(i_{\text{satu}}\) and \(i_{\text{satt}}\) should be considered to achieve a maximum \(n\). In a system with three units, it is evident that \(3i_{\text{satt}}\leq i_{\text{sum}}\leq 3i_{\text{sattu}}\). Besides Incubation (5), the following restriction also needs to be fulfilled, which is expressed as  
\[i_{\text{sum}}\times\frac{\min(SoC_{\text{k0}}^{n})}{\sum_{k=1}^{m}SoC_{\text {k0}}^{n}}\geq i_{\text{satt}} \tag{6}\]  
where \(\min(\,)\) is the minimum function. Combing Inequation (6) with Inequation (5), the maximum \(n\) is 5 when \(i_{\text{sum}}=45\) A and \(i_{\text{satt}}=6\) A. Due to the similarity of the ideal curves in the two applications, the corresponding curves in series applications are omitted.