# Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA
## 6 HW/SW Implementation
### Acceleration Results  
The processing of raw PPG signals by the PPG sub-system comprises two main stages: preprocessing and periodicity search. The first stage is executed by the designed IP core, present at the PL. The second stage is executed by the PS and recurring calls of the IP core. Table 3 shows the total elapsed time of a complete execution of the PPG algorithm, discriminating the split times of both stages. The times are referred to input PPG signals comprising two buffers of 1024 16-bit samples. These buffers are shared  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Group** & **Block Name** & **LUT** & **FF** & **BRAM** & **DSP** \\ \hline \multirow{4}{*}{\begin{tabular}{c} PPG \\ sub-system \\ \end{tabular} } & ppg\_stream1\_0 & 1319 & 995 & 2 & 16 \\ \cline{2-6}  & ps7\_0\_axi\_periph\_1 & & & & \\ \cline{2-6}  & axi\_dma\_1 & 2409 & 3318 & 3 & 0 \\ \cline{2-6}  & axi\_mem\_intercon\_1 & & & & \\ \hline \multirow{4}{*}{EEG} & eeg\_calc\_dist\_0 & 2913 & 3307 & 1 & 0 \\ \cline{2-6}  & eeg\_sort\_0 & 1225 & 1325 & 1 & 0 \\ \cline{2-6}  & ps7\_0\_axi\_periph\_0 & & & & \\ \cline{2-6}  & axi\_dma\_0 & 1101 & 1549 & 1.5 & 0 \\ \cline{2-6}  & axi\_mem\_intercon\_0 & & & & \\ \hline \multirow{4}{*}{\
\begin{tabular}{c} Processing \\ system \\ \end{tabular} } & processing\_system7\_0 & 0 & 0 & 0 & 0 \\ \cline{2-6}  & rst\_ps7\_0\_100M & 16 & 33 & 0 & 0 \\ \hline \multirow{4}{*}{
\begin{tabular}{c} Access \\ (Zynq-7010) Total available \\ \end{tabular} } & Total used & 8983 & 10,527 & 8.5 & 16 \\ \cline{2-6}  & 17,600 & 35,200 & 60 & 80 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Hardware resources used by the complete monitoring system.  
with the channels of an optoelectronic sensor that collects PPG data. The values of the table include the application of 00 and 03 optimizations. Regarding the non-optimized versions, the embedded system (HW/SW 00) outperforms the results of the software-only version (SW 00). The overall execution time was reduced by 64%, while the preprocessing and periodicity search stages were respectively reduced by 86% and 58%. These values correspond to a speedup ranging between 2.4 and 7.4. The 03 optimization applied to the HW/SW design (HW/SW 03) increased the overall execution time of the equivalent software-only (SW 03) by 58%. This is due to the 90% increase in the execution time of the periodicity search stage. However, the preprocessing stage is outperformed, and its execution time reduced by 50% (speedup of 2 times).  
The EEG embedded system is a KNN classifier composed by a pair of IP cores, dedicated to the calculation and sorting of Canberra distances between sets of EEG features. Because of the direct connection between first core's output and second core's input, the PS does not interact with the results obtained by the first core. Therefore, the measurement of the execution time of calculation and sorting stages is performed jointly. The PS is responsible for assessing the classification given the results produced by the IP cores pair. Table 4 summarizes the execution times of the processing steps, applied to optimized and non-optimized implementations. The high number of operations to be executed over a memory (training set) containing 1024 sets of 160 EEG features created an opportunity for acceleration via HW. The results show that the HW/SW co-design outperforms the SW-only 00 baseline by 100 times and the 03 version by 40. The problem of calculating distances was approached by launching eight instances of _Canberra_ blocks to execute in parallel the correspondent arithmetic instructions. Moreover, the sorting task was unlocked by the concept of a chain of sorting cells through which data (distances) propagated continuously.