## 5 Case Study: Cryptographic Hardware Coprocessor for the Secure Subsystem of Rhea GPP
### Physical Implementation  
Regarding the physical implementation and according to the security partitioning model in Figure 4, the Crypto-Tile has an impact on both the circuit level and the hardware micro-architecture level. For this reason, we provided our module with countermeasures for both timing and power analysis attacks.  
We integrated a clock randomization mechanism to counteract timing attacks [54; 55]. In this way, the execution of each cryptographic operation is unpredictable and an attacker cannot gain information by observing it. For instance, the usage of 128-bit or 256-bit keys in the AES operations determines a different execution time, because the former requires 10 processing rounds, while the latter requires 14 processing rounds. With the clock randomization approach, an attacker is no longer able to distinguish between the key size from the execution time of an AES operation. In addition, such a mechanism aids also in lowering the success rate of power analysis because DPA and CPA require the time alignment of the power traces [88]. It is worth pointing out that the utilization and the configuration of the clock randomization mechanism are strictly regulated by specific authorization procedures at the interface security policy level because its usage has direct effects on the security strength of the cryptographic coprocessors, hence also it must considered as a security-critical asset.  
Concerning power analysis attacks, we integrated also other dedicated protections to make them ineffective. For instance, the ECC operations are very vulnerable to SPA, i.e., by observing just one power trace, an attacker can retrieve the secret key without additional statistical computations such as in DPA and CPA [16]. Thanks to the methodology described in [88], we were able to analyze and evaluate the resistance of our ECC coprocessor against Single Power Analysis (SPA) without the necessity of the physical chip and using gate-level simulations, concluding that the dedicated countermeasures are able to guarantee the required protection and defeat successfully these kinds of attacks [16]. Indeed, by exploiting the same gate-level simulations on the netlist that we used to measure the power consumption of the Crypto-Tile (Section 5.1), we were able to gather and analyze the power consumption profile of the engines during the execution of the cryptographic operations. As an example, in Figure 9 we report the power consumption profile of the ECC engine before the integration of dedicated security mechanisms against power analysis attacks.  
As illustrated in Figure 9, without equipping the cryptographic ECC engine with specialized countermeasures, it is possible to distinguish if the bit of the key processed by the engine is 0 or 1, because according to its values, the engine shows a different power profile. Hence, an attacker can retrieve the value of the secret private key with a single SPA attack, i.e., by analyzing only a single power trace. In Figure 10, it can be noted how the power profile of the ECC engine changed after the integration of the dedicated countermeasures; after the modifications, the power profile is invariant with respect to the value of the key bits.