## 4 Simulation Results  
Figure 13 shows the PSIM software (Powersim, Rockville, USA) simulation circuits for the conventional and interleaved PFC circuits with the designed power components values. The EMI filter in both topologies was designed as an LC filter with common mode coupling inductor of about 2.4 mH and suppression capacitors of about 2.2 nF [43]. For the practical simulation results, which were closest to the experimental results, the boost diode is considered as SiC Schottky diode to ignore the switching losses, the forward voltage of the boost diode is about 1.5 V, and the parameters of bridge diode, the boost converter switches for both topologies are obtained from the datasheets of the selected components. Figure 12: Bode plots for the control loops for the interleaved CCM PFC converter: (**a**) voltage control loop; (**b**) current control loop. At the rated input of (220 Vrms, 60 Hz) and rated load of Po = 2000 W and Vo = 400 V, the power performance for both topologies is simulated. Figures 14 and 15 show the waveforms of the input and output currents and input and output voltages as well as the circuit power factor (PF) for the conventional and the interleaved CCM PFC converters respectively. We observed that the designed conventional PFC converter offers input power factor at full load condition of 2 kW with minimum value about 0.9955 and maximum value about 0.9970. On the other hand, the interleaved converter offers a power factor with a minimum value of about 0.9975 and a maximum value of about 0.9991 during the full load operating condition. The peak to peak ripple value in the output voltage is measured of about 12.00 V in the conventional and 12.10 V in the interleaved converter which is less than the design specified value (Vrpp = 20 V) for the output voltage ripple contents in both topologies. Additionally, the output ripple current peak to peak value is measured of about 0.153 A in the conventional and 0.151 A in the interleaved converter which is less than 4% in both topologies. To show the operation performance of the designed current control loops for both PFC topologies, the operation waveforms of inductor currents and the reference current are simulated. Figures 16 and 17 show the inductor's current and the reference current generated from the outer voltage control loop for the conventional and the interleaved PFC converters, respectively. It can be observed that the inductors currents successfully follow the reference current in both topologies which ensure input current follows input voltage, and offer higher input power factor values. Figure 14: Voltages, currents, and input power factor for the conventional CCM PFC at full load condition. Figure 13: PSIM simulation circuit for the PFC topologies: (**a**) conventional boost PFC; (**b**) interleaved boost PFC. Figure 16: Inductor current and reference current for the conventional CCM PFC at full load condition. Figure 17: Inductors current and reference current for the interleaved CCM PFC at full load condition. Figure 15: Voltages, currents, and input power factor for the interleaved CCM PFC at full load condition. The dynamic performance of the outer voltage control loop to regulate the output voltage to the specified value (400V) with different input voltage conditions is simulated as shown in Figures 18 and 19 for the conventional and the interleaved PFC converters, respectively. Three operation conditions of the lower voltage, steady state voltage, and higher voltage conditions of the input supply voltage are used to test the operation of the outer voltage control loop. It can be observed that the designed outer voltage control loops based on the proposed small signal stability modeling succeed to regulate the output voltage to the specified value with very small transition time with different wide range of the input voltage conditions.