## 1 Introduction
This method supports high data rates of 0.5 Gbps [25], provides an excellent CMTI (650 kV/\(\upmu\)s) [26], and offers a great isolation voltage of 7.5 kV\({}_{\text{rms}}\)[27]. In addition to data transmission [28; 29], isolated DC-DC converters use transformers for power transfer because of their high-quality factor compared to capacitive coupling, which usually requires off-chip elements to construct subharmonic resonant peak efficiency [30; 31; 32; 33]. Figure 1 shows the typical block diagram of an inductive-based digital isolation system for industrial sensor interfaces. Transceiver blocks are implemented on the low-voltage and high-voltage sides, each with their respective supply and ground rails: \(\text{VDD}_{\text{L}}/\text{VDD}_{\text{H}}/\text{VDD}_{\text{1}}/\text{VDD} _{\text{2}}/\text{VDD}_{\text{3}}\) and \(\text{GND}_{\text{L}}/\text{GND}_{\text{1}}/\text{GND}_{\text{2}}/\text{GND }_{\text{3}}\). Two differential signals are transmitted from the microcontroller logic unit (MLU) on the low-voltage side to the gate driver on the high-voltage side, while the read-back signal is transmitted from the off-chip load through the analog-to-digital converter (ADC) on the high-voltage side to MLU. To ensure a fully isolated environment, the system incorporates an isolated DC-DC converter that takes the input voltage source from the low-voltage side and generates required voltage levels in the high-voltage domain. A fully integrated digital isolation system attempts to combine the communication links into a single compact die to further minimize power consumption and reduce fabrication costs. This design utilizes edge-based modulation [34] due to its lower power consumption compared to on-off-keying (OOK) architecture [35; 36], which uses a single chip area at the cost of higher power consumption during the logic high state of the signal modulation process. A set/reset architecture with a dual transformer is an example of edge-based communication with a high isolation rating. It, however, occupies twice the transformer area compared to single transformer architectures. Another example is the pulse count method [19; 20], where the chip area and the power consumption stand in an acceptable range. When compared to the single-pulse method, the power is 1.5 times higher, the propagation delay is longer, and it operates at lower data rates since it requires more time to evaluate the pulse count. Although the currently available maximum achievable data rate is sufficient for the current applications, future demands are expected to require higher data rates, lower latency, and lower BER. To the best of our knowledge, the maximum speed achieved with the minimum propagation delay for fully integrated inductive digital isolators in a 0.18 \(\upmu\)m CMOS is 0.5 Gbps and 3.6 ns, respectively. Moreover, to operate at higher speeds, two transformers are utilized, which increases the fabrication cost [25]. This work proposes high data rates, reduced delay, and a low BER fully integrated inductive digital isolation system based on the pulse polarity modulation scheme in a high-voltage 0.35 \(\upmu\)m CMOS process. The rest of this paper is organized as follows: design and implementation of the inductive-based digital isolation system are given in Section 2. Measurement results are presented in Section 3. Discussion and comparison with prior state-of-the-art are illustrated in Section 4, and final conclusions are drawn in Section 5.