# 25-34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver
## 2 Design of the Single-Pole, Double-Throw (SPDT) Switch
For the CB switch selector, when both S\({}_{0}\) and S\({}_{1}\) are set high or low, the switch control voltages (\(V_{c1\_CB}\) and \(V_{c2\_CB}\)) become 0 V and block all RF signals. When S\({}_{0}\) is high and S\({}_{1}\) is low, \(V_{c1}\) is given by \(V_{DD}\), and \(V_{c2}\) goes to 0 V. In contrast, when S\({}_{0}\) is low and S\({}_{1}\) is high, \(V_{c1}\) and \(V_{c2}\) become 0 V and \(V_{DD}\), respectively. The DSB switch selector turns off the switch in two ways. When both S\({}_{0}\) and S\({}_{1}\) are set as low, the switch control voltages (\(V_{c1\_DSB}\) and \(V_{c2\_DSB}\)) become \(-V_{NN}\). Alternatively, both S\({}_{0}\) and S\({}_{1}\) are set to high to turn off the NVG by blocking the oscillator current source and setting the control voltages to 0 V. When S\({}_{0}\) is high and S\({}_{1}\) is low, \(V_{c1}\) goes to \(V_{DD}\) and \(V_{c2}\) goes to \(-V_{NN}\). In contrast, when S\({}_{0}\) is low and S\({}_{1}\) is high, \(V_{c1}\) and \(V_{c2}\) become \(-V_{NN}\) and \(V_{DD}\), respectively. \begin{table}
\begin{tabular}{c c c c c c c} \hline \multicolumn{2}{c}{**Select Signal**} & \multicolumn{2}{c}{**CB (Cross-Biasing)**} & \multicolumn{3}{c}{**DSB (Dual-Supply Biasing)**} \\ \hline S\({}_{1}\) & S\({}_{0}\) & \(V_{c1}\) & \(V_{c2}\) & \(V_{c1}\) & \(V_{c2}\) & NVG \\
1 & 0 & 0 & \(V_{DD}\) & \(-V_{NN}\) & \(V_{DD}\) & On \\
1 & 1 & 0 & 0 & 0 & 0 & Off \\ \hline \end{tabular}
\end{table} 
Table 1: Switch control voltages according to switch control mode. NVG: negative voltage generator. Figure 8: Transient simulation result of the output voltage of negative voltage generator (NVG). Figure 7: Schematics of the (**a**) CB switch selector, and (**b**) the DSB switch selector, including the negative voltage generator. The top view of the layout of the proposed CB and DSB SPDT switches, which displays the inductors and ground planes, is illustrated in Figure 9. Both switches are identical, with the exception of the switch cores. All the active circuits are concentrated on the area of the core. Interference between the active devices and the inductors, through electromagnetic coupling, is minimized by separating the switch core from the inductors. The electro-magnetic (EM) characteristics were extracted using Sonnet, a 2.5-D EM simulator. Excluding the core circuit, all the inductors, metal connections, pads and ground planes except the core circuit were included in the EM simulation, to reduce the differences between the results from simulations and measurements. The inductance and Q-factor of \(L_{DS}\) were simulated as 643.5 pH and 21.6 at 28 GHz, respectively. The simulated inductance of \(L_{TRX}\) was 212.6 pH, and the Q-factor was 14.9, at 28 GHz. The simulated inductance and Q-factor of \(L_{ANT}\) were 208.1 pH and 13.7 at 28 GHz, respectively. The contribution to the total insertion losses of the proposed switches was analyzed. Figure 10a shows the simulated insertion loss of the CB SPDT switch. The insulation loss at 28 GHz is 1.92 dB, of which 40.6% occurred in the core cell, 21% occurred in the transceiver (TRX) matching circuit, and 38.4% occurred in the antenna matching circuit, as shown Figure 10b. Figure 11a shows the simulation insertion loss of the proposed DSB SPDT switch. The insulation loss at 28 GHz is 1.93 dB, of which 41.3% occurred in the core cell, 20.9% occurred in the TRX matching circuit, and 37.8% occurred in the antenna matching circuit. Figure 10: (**a**) Simulated insertion loss of a CB switch, and (**b**) insertion loss contribution at 28 GHz. Figure 9: Top view of the layout of the switch.