# A Real-Time Numerical Decoupling Method for Multi-DoF Magnetic Levitation Rotary Table
## 3 Real-Time Decoupling Unit Implemented on FPGA
### Current Decoupling Unit Implementation  
The numerical decoupling process is given in the left flowchart of Figure 4. The dashed block represents the summation item in Equation (3) using the POV \({}^{\text{s}}\)**p**, coil index \(i\), and loop index \(n\) as input variables. In the program, the loop amount is \(N\) estimated by the coil node number in one coil times the magnet node number:  
\[N=1792=2\times 2\times 2\times 4\times 7\times 8, \tag{13}\]  
where the first 2, the middle \(2,2,4\), the following 7, and the last 8 respectively represent the two integral regions for one coil, the coil node amount in each integral region, the required magnet number for a magnetic field solution, and the magnetic node number in the cubic permanent magnet. Then, the force and torque solution are summed up to obtain the current-wrench transformation matrix \(\mathbf{\Gamma}\) for the later matrix operation of Equation (12). Through the HLSTM tool, the summation item in Equation (3) and the matrix operation in Equation (12) are exported as a **FT** (Force & Torque) IP core and **MO** (Matrix Operation) IP core. As the aforementioned derived wrench model shares the same expression with different input variables, it is suitable to work with the pipelined architecture. In order to develop throughput, the interval for the pipelined **FT** IP core should be 1 so that the processing of each loop is independent from the others and cannot contain the _for_ statement. Force and torque solutions of the same coil are summed up, and the summation is the wrench vector in \(\mathbf{\Gamma}\). Therefore, six independent **SUM** IP cores from LogicTM are also required for the corresponding summing operation. Finally, the **MO** IP core is employed to calculate the current vector for the desired force and torque, in which the Gaussian elimination realizes the matrix inversion operation. The matrix operation is also optimized by the internal pipeline and array partition in the HLSTM tool to maintain latency and computation resources. The entire decoupling unit was designed based on these RTL modules on the FPGA platform shown in the middle column of Figure 4. The module in the dashed block was used for the numerical wrench model realized by the IP cores and a counterproducing loop index \(n\) and coil index \(i\). The solutions from the **FT** IP core should be sent to the **SUM** IP core, also owing to a pipelined architecture, one by one. The final results from the **SUM** are stored in a bipolar RAM constructed in FPGA whose other side directly connects with the **MO** IP core. The outputs of the **FT** IP core are actually continuous due to the pipelined structure, so the timing sequence of the data communication between each IP core should be elaborately designed or the solution will be faulty. As illustrated in the right column of Figure 4, if all of loop index \(n\) for one coil is accomplished, there exists an idle clock for the next coil. The reason is that **SUM** IP cores are required to reset for the wrench vector computation of the next coil. Observing the timing sequence flow, the total delay clock of the numerical wrench model for the magnetically levitated rotary actuator is estimated below. \[n_{\text{wm\_latency}}=n_{\text{FT\_latency}}+n_{\text{SUM\_latency}}+7 \times n_{\text{idle}}+8\times N, \tag{14}\]  
where \(n_{\text{FT\_latency}}\), \(n_{\text{MO\_latency}}\), and \(n_{\text{SUM\_latency}}\) represent the inherent delay of **FT**, **MO**, **SUM** IP cores, \(N\) is number of computation units for the wrench vector of each coil, and \(n_{\text{idle}}\) is the idle clock after all variables for one coil having been sent to the **FT** IP core. The \(n_{\text{idle}}\) is larger than \(n_{\text{sum\_latency}}\) as the **SUM** IP core should reset after the wrench vector computation for one coil is accomplished. Once the current-wrench transformation matrix \(\mathbf{\Gamma}\) is obtained, the **MO** IP core is started, and then the FPGA RTL implementation will wait for the end of the matrix operation.