# Transmitter and Receiver Circuits for a High-Speed Polymer Fiber-Based PAM-4 Communication Link
## 3 Design of the Power Detector  
As shown in Figure 8, a common-emitter configured transistor, Q1, and a common-base configured transistor, Q3, are used as nonlinear components for power detectors. Their collector currents are added and applied at the stacked transistor Q4, to amplify the output signal. The output of the power detector is taken at the collector of Q4. The collector and base of Q2 are connected to form a diode, which provides a DC path for Q3, and DC-bias for Q1.  
Figure 6: S11 and S22 for the modulator for different frequencies.  
Figure 7: ADS simulation result of the RF output power level depending on the LO input power. The LO frequency is 130 GHz.  
The collector current of a transistor is given by  
\[I_{\rm c}=a_{0}+a_{1}V_{be}+a_{2}V^{2}+\ldots \tag{1}\]  
where \(a_{0}\) is a function of amplitude of \(V_{be}\) in an ideal case, \(V_{be}\) for common-emitter configured transistor is equal to \(-V_{be}\) for commonbase configured transistor.  
The single-ended input signal is applied at the base of Q1 and the emitter of Q3 simultaneously. Due to the transistor's nonlinearity, the outputs of Q1 and Q3 contain DC component and harmonics. The odd-order harmonics at Q1 and Q3's outputs are 180 degrees out of phase, since the transistor Q1 is common-emitter configured and Q3 is common-base configured. Thus, connecting Q1 and Q3's outputs, the odd-order harmonics will be suppressed. This is a desired feature for a power detector, since all harmonics create ripple at the output waveform; among them, the 1 st harmonic makes the most contribution [6].  
The emitter length of transistor Q4 is 15 \(\upmu\)m, and for Q1, Q2, and Q3, the emitter length is 3 \(\upmu\)m. The desired function of Q4 is amplification of the data signal, which is why a relatively large device is selected to get sufficient gain. Due to parasitic action, the device will have a lower gain for the RF-signal, which will help to suppress undesired fundamental and higher order harmonics. Three different bias voltage supplies are used (Vc = 4.5 V, Vb2 = 2.2 V, Vb1 = 1.5 V).  
A photo of the fabricated PD can be seen in Figure 9. The RF input signal port is located on the left side of the MMIC, while the output port is located on the right side. The DC bias is supplied at the top. The total size of the MMIC including pads is 0.28 mm\({}^{2}\), and 0.11 mm\({}^{2}\) without pads.  
The PD was measured on wafer. The input sinusoidal signal was swept over frequency and input power using a Keysight N5261A PNA-X microwave network analyzer.  
The output of the PD (DC voltage) was measured by a multimeter. The output voltage corresponding to different input power is plotted in Figure 10 for 120 GHz, 130 GHz, 140 GHz, and 150 GHz. As the input power increased from 0 to 1 mW, the output voltage changed 1.1 V, which agreed with the simulation.  
The DC consumption for the PD was measured to be 11 mW.  
The suppression of the fundamental frequency at the output of the PD was measured and simulated using ADS. The measured suppression is more than 24 dB for the entire D-Band. The results can be seen in Figure 11.  
Figure 8: A schematic of the power detector.  
Figure 11: Simulated and measured suppression of the fundamental at the output of the PD. Six different values for the input power were used, from \(-20\) dBm to \(5\) dBm during the simulation, and four different values for the input power were used, from \(-20\) dBm to \(-5\) dBm during the measurement.  
Figure 10: Incremental output voltage change for different input powers applied. Each trace core spends to a different frequency (120 GHz, 130 GHz, 140 GHz, and 150 GHz).  
Figure 9: A photo of the fabricated power detector. The chip size including pads is 700 \(\upmu\)m by 400 \(\upmu\)m.  
A time domain simulation of the input signal and corresponding output signal can be seen in Figure 12. The carrier frequency was 140 GHz.