## 6 Conclusions  
The new VVC standard comes with various advanced features compared to existing video codecs. However, these features come with higher computational complexity. In this study, the complexity analysis of a VVC decoder was revealed. In this presentation, a VTM8.0 decoder was instrumented and implemented over two different architectures: a homogeneous multicore HGPP integrated in an AMD processor and a heterogeneous ARM+GPU embedded platform. The goal of this work was to guide future work focusing on acceleration processes over the brand new state-of-the-art codec, especially over embedded systems and platforms with limited computational resources. First, coarse-grain profiling was implemented. Here, the computational load of the main coding blocks, ED, TX, IP, EP, and filters, was outlined. The coding blocks consuming the most time, the  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Platform** & **Scenario** & **Configuration** & **Average** & **Min** & **Max** \\ \hline \multirow{6}{*}{HGPP} & Un-optimized (fps) & AI & 2.1 & 0.9 & 4.2 \\  & RA & 6.0 & 1.8 & 13.8 \\  & Optimized (fps) & AI & 8.4 & 4.0 & 16.3 \\  & \multirow{2}{*}{Speedup} & RA & 33.6 & 10.9 & 66.5 \\  & & AI & 4.1 & 3.3 & 5.6 \\  & & RA & 5.6 & 4.8 & 9.1 \\ \hline \multirow{6}{*}{EGPP} & Un-optimized (fps) & AI & 0.9 & 0.4 & 1.8 \\  & \multirow{2}{*}{Optimized (fps)} & RA & 1.8 & 0.6 & 3.9 \\  & & AI & 3.8 & 1.6 & 6.6 \\ \cline{1-1}  & \multirow{2}{*}{Speedup} & RA & 6.6 & 5.7 & 9.3 \\ \cline{1-1}  & & AI & 3.8 & 3.2 & 4.9 \\ \cline{1-1}  & & RA & 6.6 & 5.7 & 9.0 \\ \hline \hline \end{tabular}
\end{table}
Table 10: Optimistic (max) and pessimistic (min) estimation of the performance achieved in future optimized solutions, resulting speedup for those scenarios is also provided.  
EP, DBF, and ALF, were then fine-grained analysed. The computational load distributions outlined where optimization efforts should be carried out. Moreover, these results were compared with the available implementation of VVC over other architectures, which showed that the influence of processor hardware architecture greatly affected the ALF and DBF blocks. In this work, the correlation between HGPP and EGPP was also calculated, and it was shown that the processing time of all decoder blocks was roughly \(\times\)2 over the EGPP with respect to the HGPP except for the ALF block, which was approximately \(\times\)7 greater, and the EP block, which was \(\times\)3.5 greater. In addition, the performance results showed \(\times\)2.5 and \(\times\)3.3 fps ratios running the decoder over the HGPP compared to the EGPP for the AI and RA configurations, respectively. Finally, a rough estimation analysis was presented based on software-level optimization and hardware platforms. It can be foreseen that an average improvement of \(\times\)4.8 and \(\times\)5.2 in decoding time could be achieved using the estimation analysis over the HGPP and EGPP, respectively.  
[PERSON], [PERSON], [PERSON], [PERSON], [PERSON] and P.L.C. have contributed equally to the conceptualization and the preparation of the manuscript. All authors have read and agreed to the published version of the manuscript. This work was supported by the Spanish Ministerio de Economia y Competitividad under Grant TEC2016-75981-C2-2-R.  
**Institutional Review Board Statement:** Not applicable.  
**Informed Consent Statement:** Not applicable.  
**Data Availability Statement:** Contact with corresponding author.  
**Conflicts of Interest:** The authors declare no conflict of interest.