# A 11 mW 2.4 GHz 0.18 \(\upmu\)m CMOS Transceivers for Wireless Sensor Networks
## 3 Circuit Implementation  
### Low Noise Amplifier and Power Amplifier  
As illustrated in [12], since the TX and RX share an antenna, the PA and LNA can be co-designed to share the matching network. The basic consideration is that when the LNA is in the off mode, the system is working as a transmitter. However, the LNA simultaneously contributes parasitic capacitance. Similarly, in the RX mode when the PA is powered off, the parasitic capacitance of the PA should be included in the simulation of LNA. The off-chip connection of the LNA/PA to the antenna is shown in Figure 2.  
Figure 3 shows the topology of the low noise amplifier and the power amplifier. It is an inductor reuse topology proposed in [12]. As mentioned above, the key considerations in this transceiver are low cost (small silicon area) and flexibility in functionality subject to acceptable performances, such as noise figure, gain, and linearity. Hence, it is necessary to maintain less off-chip component and small silicon area. Additionally, it would be more attractive if the transceiver is able to be re-configured for different applications, since the WSN applications cover a wide range of operating frequencies.  
Figure 1: The architecture of the proposed work.  
Figure 2: The off-chip matching network of the RFIO.  
Thus, the strategy in this design is that the RX and TX are inductor-less and only one off-chip inductor is shared by the RX and TX. The silicon area of the transceiver will, therefore, be ultra-small. Moreover, since the matching network is determined by the inductor and capacitor, it will be very convenient to make the RX and TX work properly at the desired frequency range.  
The PA in this design is a conventional class-E topology as shown in Figure 3. It consists of three stages of inverters, the output stage has an output matching network with an on-chip capacitance and an off-chip inductor with capacitances, which forms a PI-matching topology. This topology, which is widely used in short-range communication exhibits a high efficiency and small silicon area. Additionally, the external matching network make it possible to re-configure the system at different working frequencies. Figure 4 shows the simulation results of the PA, the maximum output power reaches 2.1 dBm, while the power added efficiency (PAE) is 21.2%.  
Similarly, the LNA is designed to maintain a good balance among the required performances. To achieve a wide operating band, a common gate topology is implemented since a higher noise figure is acceptable in this system. The parallel resonant circuit shared with the power amplifier forms a band-pass frequency response which improves the robustness against interferences. Another important trade-off is the load of the amplifier. A resistive load, instead of a commonly-used inductive load, is implemented in this design in considering a small silicon area. The drawback of this design is the lower high-frequency gain, sizing of the transistors and resistors is, thus, carried out to ensure acceptable performances in noise figure, gain, and linearity at desired operating frequencies.  
Figure 4: The simulation results of the PA (**a**) output power; and (**b**) PAE.  
Figure 3: Topology of the LNA and PA (**a**) low noise amplifier; and (**b**) PA with control circuit.  
Figure 5 shows the simulation results of the low noise amplifier. It has a wide-band of gain performance, which is over 12 dB from several hundred megahertz to 3 GHz. The noise figure of the LNA is about 6-7 dB within the band of interest. The performances are quite acceptable for a complete receiver with a noise figure budget up to 20 dB. The Third Order Intercept Point (IP3) of the amplifier is higher than 0 dBm, which suggests that the RX exhibits good linearity.