# Updates on Impact Ionisation Triggering of Thyristors
## 2 Materials and Methods  
Previous literature establishes that ultra-fast thyristor triggering requires a significant slew rate and an overvoltage at least twice the static breakdown voltage of the thyristor ([9; 10; 11; 12]); all whilst ensuring that enough current is available to guarantee the charging of the thyristor's internal parasitic capacitance at the required dU/dt (Section 1). Therefore, we need to first know the parasitic capacitance of the thyristors in use.  
To assess the relationship between the internal parasitic capacitance and voltage for the 2.4 kV rated thyristor MPPCT750D240 [23], a test was conducted as depicted in Figure 1a. The biasing voltage applied via the DC power supply was gradually increased to facilitate the charging of both the thyristor's parasitic capacitance and the series coupling capacitor. Placing a resistor \(R_{p}\) in parallel with the RLC meter is intended to protect it from the charging current of the coupling capacitor during voltage changes. It should be noted that this resistance will only be active during voltage transitions, serving as a protective measure for the RLC meter.  
The thyristor's parasitic capacitance was measured by applying a blocking DC voltage on the anode-cathode of the component, on a range from 200 V to 3 kV. The RLC meter measurement was set at 10 kHz. We incorporated a coupling capacitor between the thyristor anode (at positive \(U_{bias}\)) and the RLC meter. By ensuring that the value of the coupling capacitor exceeds the parasitic capacitance of the thyristor under measurement, we have addressed its influence by calculating its effect in series arrangement, resulting in \(C\_c=3.3\) nF.  
The voltage dependence of the parasitic capacitance of the thyristor is illustrated in Figure 1b. In order to address radiation tolerance, specifically single-event burnout, we intend to implement a voltage derating strategy, limiting the applied voltage to no more than 60% of the nominal rated voltage--equivalent to 1.4 kV for a 2.4 kV rated component. At this biasing voltage, the thyristor exhibits a parasitic capacitance of 220 pF.  
Taking as a starting point a small thyristor stack generator, with the previously studied thyristors we know the operating point that the present pulse generator needs to reach:  
1. Slew rate at turn-on \(\frac{d\Pi}{dt}>1\) kV/ns.
2. Considering the static breakdown voltage \(U_{BD}=3\) kV, doubling it and substracting the biasing voltage \(U_{bias}=1.4\) kV, the output voltage needs to be \(U_{out}>4.6\) kV.
3. Current \(I=C_{pansitic}\cdot\frac{d\Pi}{dt}>220\) A.  
In order to give an overview of how this can be achieved, the methods, materials, and results are hereby presented in a trickle-down way: starting from the output of gate-boosted  
Figure 1: Assessing the thyristor’s parasitic capacitance. (a) Setup to measure the parasitic capacitance of a thyristor in relation to bias voltage using an RLC meter. (b) Voltage dependance of the MPPCT750D240 thyristor’s parasitic capacitance.  
SiC MOSFETs that achieve the aforementioned current output requirements (Section 2.1), we will delve into the driving methods that make it possible, all the way back to a standard pulse generator that could be found in any electronics laboratory (Section 2.2).