## 4 Discussion  
The results of the study indicate the effectiveness of the proposed sequential state encoding methods in optimizing FSM implementations. Through a systematic evaluation of each state and code selection mode across various FSM benchmarks, the research demonstrated that tailored encoding strategies could lead to notable improvements. Comparing the synthesis results with those obtained using Quartus's built-in Sequential encoding mode, this study highlighted the benefits of the new encoding methods. An analysis of Tables 1 and 2 reveals that, compared to the Sequential mode, the proposed FSM state encoding methods significantly improve both area and performance. In Tables 1 and 2, the columns provide detailed insights into the metrics used for evaluation. Specifically, the column Ls represents the area value, measured as the number of FPGA logic elements used when applying Quartus's Sequential mode encoding. The column Fs indicates the performance value, measured as the maximum operating frequency in megahertz (MHz), achieved with the Sequential mode of Quartus. Meanwhile, Lmin denotes the minimum area value, representing the lowest number of logic elements used among all tested methods for a given FSM example, while Fmax signifies the maximum performance value, representing the highest operating frequency achieved among all tested methods. The ratios Ls/Lmin and Fmax/Fs are crucial for assessing the efficiency of the proposed methods. These ratios compare the outcomes of the proposed FSM state encoding methods against the Sequential mode of Quartus. A higher Ls/Lmin ratio suggests a greater reduction in area utilization, highlighting the effectiveness of the proposed encoding methods in minimizing FPGA resources. Similarly, a higher Fmax/Fs ratio indicates an improvement in performance, showcasing how the proposed methods enhance the maximum achievable operating frequency compared to the Sequential mode. On average, these methods reduce the area by 19.7%, and in some cases, such as the _shiftreg_ example, the reduction can be as much as twofold. Additionally, the performance of FSMs is enhanced by an average of 21.2%, with certain examples like _pma_ experiencing performance increases of up to 69.3%. In Tables 1 and 2, the best solutions are highlighted in bold. It is important to note that the best solution can be achieved using multiple encoding methods. For some methods, the best solution is unique in comparison to other methods, meaning it cannot be obtained using alternative encoding methods. Figure 4 presents graphs depicting the state selection modes based on the number of best and unique solutions in terms of both area and performance. These graphs illustrate the effectiveness of different state selection modes in achieving optimal results. Figure 4: The number of best and unique solutions for the state selection modes (**a**) in terms of area, and (**b**) in terms of performance. As shown in Figure 4a, the P_C mode is the most effective state selection mode in terms of area, with the max_C mode following closely. In contrast, Figure 4b indicates that the max_C mode excels in performance, with P_C as the second-best option. Therefore, the optimal solutions for both area and performance are most likely to be found using the P_C and max_C modes. Figure 5 presents graphs illustrating the effectiveness of various code selection modes based on the number of best and unique solutions in terms of area and performance. Figure 5a indicates that the FPGA mode is the most effective code selection mode for minimizing area, followed by the CPLD mode. However, Figure 5b shows that the FPGA mode is the least effective for optimizing performance. As expected, the max_w mode excels in performance optimization, with the CPLD mode being the second-best, similarly to its performance in area optimization. Therefore, to optimize area, the FPGA and CPLD code selection modes are recommended; for optimizing performance, the max_w and CPLD modes should be used.