## 3 Proposed Hardware Architecture
### Arithmetic Logic Unit
#### 3.3.1 Efficient Data Routing for Enhanced Performance  
To optimize data routing within the ALU, we employed multiplexers (muves). For the addition operation within the ALU, we implemented a pair of \(2\times 1\) muxes. In the first of these muxes, one input is linked to the output of the multiplier module. The other input is connected to the Data_RN_1 output, representing OP1. Selection bit ALU_CNTRL_1 governs the direction of data flow to the first input of the adder. This selection bit is controlled by the Finite State Machine (FSM). Correspondingly, in the second mux, one input is coupled to the multiplier module's output. The second input is connected to the Data_RN_2 output. Control signal ALU_CNTRL_2 manages the selection between these inputs, thereby directing the appropriate data to the second input of the adder. The rationale behind employing these muxes is to optimize the execution of instructions. Particularly, the emphasis is made on enhancing the efficiency of two instructions. These instructions are \(instr_{14}\) and \(instr_{15}\), as shown in column four of Table 3.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline \(\boldsymbol{G}\boldsymbol{F}(\boldsymbol{2^{m}})\) & **Initial** & \(\boldsymbol{\text{PA}}+\boldsymbol{\text{PD}}=\boldsymbol{13}\times(\boldsymbol{m }-\boldsymbol{1})\) & **Inv** & **Total Cycles** \\ \hline
233 & 5 & 2784 & 232 & 3021 \\ \hline \hline \end{tabular}
\end{table}
Table 2: A holistic view of the computational demands for effectively implementing Algorithm 1.  
This innovative approach reduces the number of instructions, particularly for Instructions 14 and 15. Consequently, the required number of clock cycles decreases which in turn increases the overall throughput and operational capacity. It is worth noting that these enhancements are accomplished with judicious consideration of minimal additional hardware requirements. Moreover, the same optimization paradigm is judiciously applied to the squaring unit embedded within the ALU. In this context, a \(2\times 1\) mux is deployed to facilitate a seamless choice between the multiplier module's output and the adder output sourced from the memory unit. This strategic maneuver results in a notable reduction in the number of instructions, specifically addressing the efficiency of \(instr_{11}\), thereby further solidifying the operational efficiency of our ALU architecture.  
In order to save clock cycles and maximize data flow during essential computations like addition and squaring, our architecture incorporates \(2\times 1\) multiplexers within the ALU. The inclusion of multiplexers enables the selective routing of inputs based on FSM control signals. For instructions such as \(instr_{14}\) and \(instr_{15}\), which are essential in cryptographic operations, the ALU utilizes these multiplexers to streamline the processing of data. This strategic use of multiplexers minimizes the need for additional hardware while significantly increasing throughput. By dynamically selecting the appropriate inputs based on the current state of the FSM, the ALU efficiently executes instructions, contributing to the overall optimization of the cryptographic point multiplication process.