## 3 MOSFET Circuital Model
The GO voltage increases until V\({}_{\text{GS}}\) (voltage imposed between gate and source); the capacitances are constant (\(v_{DS}\) is constant), but with a different value compared with the initial one, so the current flows in both the capacitances. When the gate signal is removed (T\({}_{1}\) open, T\({}_{2}\) closed), an analogue situation occurs. As can be seen, the major losses in commutations are during \(t_{3}\) and \(t_{5}\), which will be considered in this work as the unique responses of, respectively, rise time and fall time. Note that the trends reported in Figure 5 are referred to a MOSFET alone; they have been shown to explain the phenomena which occur, in general, during commutations. For the LCC-S converter considered in this work, the situation, in terms of waveforms, is different since the current has a periodic trend and it does not reach a constant value. Below, the procedure to analytically evaluate rise time and fall time will be shown. During \(t_{3}\), according to the considerations made in the previous lines, the currents are \(i_{gd}=i_{g}\) and \(i_{gs}=0\). Considering Figure 4, the equations referred to circuit are as follows:  
\[v_{DS}=V_{GS}+R_{g}i_{g}+v_{cg} \tag{11}\]  
\[i_{g}=C_{gd}\frac{dv_{cd}}{dt}=C_{gd}\frac{d(v_{DS}-v_{AO})}{dt}=C_{gd}\frac{d \big{(}v_{DS}-V_{gp}\big{)}}{dt}=C_{gd}\frac{dv_{DS}}{dt} \tag{12}\]  
Substituting (12) in (11), the following is obtained:  
\[V_{GS}-V_{gp}+R_{g}C_{gd}\frac{dv_{DS}}{dt}=0 \tag{13}\]  
Figure 5: Typical trends of drain–source voltage, GO voltage and drain–source current during commutations [23]. The derivative term \(\frac{dv_{DS}}{dl}\), according to Figure 5, can be written as \(-\frac{V_{DC}}{t_{3}}\) (under the hypothesis that, when the MOSFET is in ON state, \(v_{DS}\) = 0). Finally, the expression of \(t_{3}\) can be derived as follows:  
\[t_{3}=R_{g}C_{gd}\frac{V_{DS}}{V_{GS}-V_{gp}} \tag{14}\]  
In analogue way, but under the condition T\({}_{1}\) open, T\({}_{2}\) closed, the expression of \(t_{5}\) can be derived:  
\[t_{5}=R_{g}C_{gd}\frac{V_{DS}}{V_{gp}} \tag{15}\]  
The last consideration is that, as previously said, \(C_{gd}\) is a function of \(v_{DS}\), which varies both during \(t_{3}\) and \(t_{5}\). For this reason, it is commonly accepted to divide the gate charge \(Q_{GD}\) stored during the Miller Plateau by the voltage swing seen on the drain connection. According to Figure 5, the voltage swing can be approximated as V\({}_{DC}\); in this way, the final relationships for rise and fall times can be derived:  
\[t_{3}=R_{g}\frac{Q_{GD}}{V_{GS}-V_{gp}};\quad t_{5}=R_{g}\frac{Q_{GD}}{V_{gp}} \tag{16}\]  
The values of the quantities reported in (16) can be found in the MOSFET datasheet. Note that in general, rise and fall times are directly reported in the datasheets, but they are provided for a specific set of working conditions (\(R_{g}\), \(V_{GS}\), \(V_{gp}\)), and when they vary, the times also need to be updated. The results of this section allow us to run the proposed model of the converter, supposing an input voltage with a trapezoidal waveform instead of square one due to the rise and fall times of MOSFETs. This model will be compared in the next section with the performances of the converter in Simulink environment, where the real behavior of MOSFETs can be reproduced. In Figure 6, a flowchart which sums up the main steps required to reproduce the proposed model is presented.