## 2 Basic Structure of the System  
As shown in Figure 3, \(C_{a}\) is the equivalent capacitor of the VLF antenna, \(R_{a}\) is the equivalent radiation resistor of the VLF antenna, \(L_{0}\) is the fixed tuning inductor, and \(\Delta L\) is the variable inductor, which is specifically composed of different combinations of controlled inductor arrays (\(L_{cn}\)) in this paper. When the frequency of the MSK signal is \(f_{\rm h}\), the tuning inductance required for this system is \(L_{0}\) and \(\Delta L=0\). When the frequency of the MSK signal is \(f_{l}\), the required tuning inductance for this system becomes \(L_{0}+\Delta L\), \(\Delta L=1/(\omega_{l}^{2}C_{a})-L_{0}\).  
Figure 4 shows the structure diagram of the synchronous Tuning Control described in this paper. The system is mainly composed of the controlled inductance matrix, the driver and switch matrix, and the control matrix. \(L_{0}\) is the fixed inductor and \(L_{C1}\) and \(L_{C2}\) are the controlled inductors, which form the primary loop through the MSK signal, and when the MSK signal carrier frequency is \(f_{h}\), all IGBTs are in the conduction state [22; 23]. At this time, only the inductor \(L_{0}\) is in operation in the system. Then, the resonant frequency of the antenna feeder system is adjusted to \(f_{h}\) when the MSK signal carrier frequency is \(f_{l}\). The IGBT of the corresponding numerical inductor \(Lcn\) is controlled to be turned off, so that the inductance in the antenna feeder system is \(L_{0}+\sum\limits_{i=1}^{n}L_{cn},n\in N+\), and the resonant frequency of the antenna feeder system is adjusted to \(f_{l}\).  
Figure 4: Schematic diagram of the synchronous control system described.  
Figure 3: Equivalent circuit diagram of VLF signaling system (ignoring loss resistance) [17].  
As shown in Figure 4, the key part of the system is the control matrix, and the controller is used to control the enable state of each logic unit. Now, the function of the logic control unit is mainly expounded. As shown in Figure 5, each output port of the controller corresponds to one logic control unit, and each logic control unit is composed of two XOR gates and one AND gate. The AND gate input is the control signal output from the controller port and the demodulated MSK symbol signal, the XOR gate input to the left of the AND gate is logic 1 and the control signal output from the controller port, and the XOR gate input above is the AND gate and the logic output of the XOR gate to the left of the AND gate. The logic truth table is as follows [24]:  
As can be seen from Table 1, when the controller outputs logic 0, the logic output of F is always 1, which is not affected by the symbol signal. At this time, the IGBT always remains in the conduct state, and the logic 0 output by the controller is called the failure instruction.  
When the controller outputs logic 1, the logic output of F is controlled by the symbol signal. When the symbol is 1, F is 1, and when the symbol is 0, F is 0. At this time, the IGBT is in the symbol signal control state, and the logic 1 output by the controller is called the enabling instruction.  
After \(\Delta\)L is calculated, the corresponding controller port is determined by the table look-up method, and the corresponding port will always remain in the enabled state.