## 3 DSSS in Electric Field Communication
### Design of the Electric Field Communication System  
In the pursuit of achieving a compactly integrated underwater electric field communication system, we present the design and implementation of the communication system depicted in Figure 7. All relevant calculations for digital signal processing are executed using an FPGA.  
Figure 6: Implementation of pseudocode synchronization in FPGA.  
Figure 7: DSSS BPSK communication system.  
The hardware platform of the system is depicted in Figure 8, comprising a PC (including Raspberry Pi), an FPGA, and an analog circuit. In this configuration, the Raspberry Pi serves as the terminal for the communication system, allowing users to send source information to the FPGA via a serial port. The FPGA functions as the digital signal processing and acceleration platform for the communication system, facilitating data transfer with the analog circuits through A/D and D/A.  
The transmitting end is composed of a transmission system and transmitting electrodes. The PC host sends information to the transmitting FPGA host through UART. The structure of the transmitter system is illustrated in Figure 9. Within the FPGA, channel encoding is employed as the initial step to combat white noise. A (15,7) Reed-Solomon channel code is utilized, incorporating eight parity bits into the information code to correct up to four symbol errors [26].  
The generation of the pseudocode sequence is a crucial step in direct sequence modulation systems. The pseudocode generator can be implemented based on a fifth primitive polynomial, constructing a linear feedback shift register with a period of 31. The initial values and tap positions of the shift register are set to fixed values. Under clock drive, a complete cycle of the pseudocode is sequentially read out. The original signal is then spread by the pseudocode signal, with one data symbol period aligning with one pseudocode period, ensuring that a complete pseudocode period precisely encompasses one original data symbol.  
The receiving end primarily consists of receiving electrodes, a receiving processor, and a PC. The electric field information generated by the transmitting electrodes is sensed using a pair of titanium electrodes. The structure of the receiver system is shown in Figure 10. At the forefront of the receiving system is a first-stage low-noise Automatic Gain Control (AGC) [27] amplifier circuit. The amplified signal is then converted into a digital signal through an Analog-to-Digital Converter, and subsequently transmitted in parallel to the FPGA for digital signal processing.  
Figure 8: The hardware platform.  
Figure 9: BPSK DSSS transmitter structure.  
The demodulation system of the direct sequence system is essentially a BPSK demodulation system. The demodulation circuit continues to use the Costas loop; however, it requires the addition of a pseudocode synchronization step within the Costas loop. The pseudocode synchronization module, as detailed in Section 3.2, is designed specifically for this purpose and can be directly invoked as a file in the top-level hierarchy. The depend signal enters the modem for demodulation and decoding, thereby recovering the transmitted signal.  
The decision outcome of the signal is decoded to obtain the original baseband data, which is then transmitted via UART to the PC for printing and error rate counting.