# Effect of Thermal via Design on Heat Dissipation of High-Lead QFN Packages Mounted on PCB
## 1 Introduction  
The quad-flat no-lead package (QFN), as one of the primary packaging forms for integrated circuits, has gained widespread adoption in industrial applications due to its remarkable performance and cost advantages. Compared with the BGA package with the same I/O count, the QFN package not only features smaller dimensions and a lighter weight but also demonstrates superior thermal and electrical performance [1]. These characteristics have facilitated extensive utilization of the QFN package in cutting-edge fields such as 5G. However, as the power of modern electronic products continues to increase, the heat generated by the QFN package has also risen progressively. Failure to effectively dissipate this heat may lead to product damage [2; 3]. Therefore, in order to ensure the reliability of QFN products, a thorough analysis of their thermal performance is essential and of significant importance. Most QFN packages are equipped with copper-based thermal pads on their undersides, which directly contact the silicon chip. The QFN package is soldered onto the copper-based thermal pad on the PCB. This design facilitates the efficient transfer of heat generated by the chip's operation to the PCB, thereby reducing the internal temperature of the package. The QFN package employs surface mount technology (SMT) for connection with PCB. The selected PCB material predominantly employs flame retardant (FR-4) for its cost-effectiveness and relatively minor environmental impact. However, the low thermal conductivity of FR-4 material results in elevated overall thermal resistance of the PCB, limiting heat conduction [4]. To enhance thermal exchange between the PCB and its surroundings, a certain number of vias are typically designed beneath electronic components [5]. Over the past decades, numerous scholars have conducted in-depth research on the thermal performance of QFN packages. At present, FEA has become the theoretical basis for engineering calculations and analysis. The finite element method can not only simplify complex problems but also save a lot of time and money. [PERSON] [6] designed a new type of QFN package with better thermal performance by using chip attachment film material attached to the chip. [PERSON] [7] predicted the effect of different convective conditions on the junction temperature of QFN packages using the finite element method. [PERSON] [8] introduced 3D simulations of multi-chip QFN systems for thermal analysis, employing CFD-based thermal modeling to predict heat behavior under temperature cycling. [PERSON] [9] established a thermal resistance network between the chip and PCB through finite element modeling and associated simulations. [PERSON] [10] directly affixed carbon nanotubes as micro-scale heat sinks onto chips, significantly improving chip heat dissipation. [PERSON] [11] employed Flotherm computational fluid dynamics (CFD) software to predict the thermal performance of dual-row and conventional QFN packages. [PERSON] [12] affirmed the positive effect of wire bonding technology on temperature regulation in QFN16b packages. [PERSON] [13] designed an integrated silicon-based microchannel heat dissipation module, shortening the heat conduction path and enhancing heat dissipation efficiency. [PERSON] [14] proposed a thermal resistance network analytical model for calculating the average chip temperature of QFN-packaged chips on PCB. [PERSON] [15] presented an enclosed cooling system integrating micro-pumps, heat exchangers, and silicon-based microchannel substrates to enhance cooling rates for high-power chips. [PERSON] [16] used analytical equations to study the influence of metal lead length, the ambient temperature, the solder area, the power dissipated in the device, and heat sink size on the thermal resistance of the device, and the calculated and measured results are basically the same.