## 4 Implementation and Measurement Results  
To verify the effect of the proposed layout methods, three DCOs were implemented in then 55 nm CMOS process, as shown in Figure 6, and measured by a digitally controlled, embedded system. The DCOs were designed with the same inductor, capacitor banks, g\({}_{\text{m}}\) cell, and output buffers. The NDCO on the left of Figure 6 had a g\({}_{\text{m}}\) cell in the neck of inductor and the TDCO in the middle had a g\({}_{\text{m}}\)-cell in the tail of the capacitor bank. The Al-metal DCO (AlDCO) on the right of Figure 6 had a g\({}_{\text{m}}\) cell in the tail of the capacitor bank, which was applied to the Al metal layer for high linear frequency tuning.  
Figure 7 shows a chip picture of the designed DCOs. The NDCO and TDCO were designed with a layout area of 0.072 \(\upmu\)m\({}^{2}\) and the AlDCO with a layout area of 0.06 \(\upmu\)m\({}^{2}\), all integrated into one chip for comparison. For accurate performance comparison, the main inductor, capacitor bank, and g\({}_{\text{m}}\) cell in the DCO were used identically.  
Figure 6: The layout of the designed DCOs.  
Figure 7: The die photo of the designed DCOs.  
Figure 8 shows the oscillation frequency range and the change in frequency according to the digital code. As shown in Figure 8a, the difference of measured maximum oscillation frequency was only 23 MHz between NDCO and TDCO. However, AlDCO presented a 347 MHz difference in maximum oscillation frequency compared to NDCO. The oscillation frequency range of NDCO and TDCO was about 923 MHz, and AlDCO was measured as having an oscillation frequency range of 775 MHz. Figure 8b shows the slope of the frequency according to the digital code. AlDCO showed a relatively linear frequency change compared to NDCO and TDCO, as expected, due to the additional Al layer. However, the maximum oscillation frequency was 148 MHz lower than that of other DCOs. In general, capacitor banks have small capacitor values at low digital codes. It becomes difficult to attain linear frequency control given the parasitic inductance of the layout. As shown in Figure 8b, the AlDCO produced a linear result at a relatively low digital code compared to the other DCO layouts. The results showed that the additional Al metal layer produced a linear frequency change effect but had a lower maximum frequency due to the parasitic capacitor generated between the capacitor banks. As such, when designing a DCO using an Al metal layer, a sufficient frequency margin should be considered.  
Figure 9 shows the phase noise of the designed NDCO at 4.8 GHz. The DCO exhibited low phase noise of \(-116.1\) dBc/Hz at 1 MHz with a 0.8 V supply voltage. The overall performance of the DCOs can represented by a figure-of-merit (FoM) as follows [11]:  
\[FoM=-PN(f_{offset})+20\log\left(\frac{f_{0}}{f_{offset}}\right)-10\log\left( \frac{P_{DC}}{1 mW}\right) \tag{5}\]  
The \(FoM\) of the designed NDCO was superior to that of the other DCOs. Since the NDCO had a \(\mathrm{g_{m}}\) cell in the neck of the inductor, the Q-factor of main inductor degraded less than that of the tail of the capacitor bank. The high Q-factor of the LC-tank resulted in the high performance of the NDCO.  
Table 1 compares the performance of the measured DCOs, showing that the DCO consumed less power and had superior phase noise compared to existing designs, with a high FoM index.  
Figure 8: Measurement of three test DCOs: (**a**) oscillation frequencies and (**b**) linear frequency control.