## 4 The Development of the Bit-Serial Systolic Array
Additionally, the intermediate signals, including \(c_{k-1-j^{\prime}}\), \(f_{k-1-j}\), \(a_{k-1}^{i}\), \(a_{k-1-j^{\prime}}^{i}\), \(c_{j^{\prime}}\), \(f_{j+1}\), \(b_{0}^{i}\), and \(b_{j}^{i}\), are efficiently pipelined between adjacent PEs. Notably, the tri-state buffers in Figures 6 and 7 are controlled by the signal \(t\) to ensure that the most significant bit (MSB) of \(A\), \(a_{k-1}^{i}\), and the least significant bit (LSB) of \(B\), \(b_{0}^{i}\), remain accessible throughout the subsequent clock cycles in the succeeding PE. Furthermore, to maintain proper timing, the control signal \(t\) is carefully propagated through two D-Latches before being applied to the next PE. This meticulous handling guarantees accurate synchronization within the systolic array. Importantly, prior to the operation of the SISO systolic layout, it is imperative to clear all D-Latches to establish an appropriate initial state. This preparatory step ensures the reliable and consistent functioning of the structure. Figure 4: Node timing for \(k=5\). Figure 5: Suggested SISO systolic multiplier. Figure 6: The \(\mathrm{PE}_{i}\) logic circuit for the A systolic array. The square blocks represent D-Latches. \[PE(\mathbf{p})=i \tag{14}\]0 The \(\mathrm{PE}_{i}\) logic circuit for the B systolic array. The square blocks represent D-Latches. The functionality of the SISO systolic layout can be described as follows:  
1. Initially, at time instance \(t=0\), the first processing element (PE1) of the upper systolic array receives input signals \(d_{k-1}\), \(c_{k-1}\), \(f_{k-1}\), \(a^{0}_{k-1}\), and \(a^{0}_{k-2}\) to compute the intermediate signal \(a^{1}_{k-1}\) using the AND-XOR construction depicted in \[PE(\mathbf{p})=i \tag{14}\]1 Simultaneously, during the same time instance, the first PE (PE1) of the lower systolic array takes input signals \(d_{0}\), \(c_{0}\), \(f_{1}\), \(b^{0}_{0}\), and \(b^{0}_{1}\) to compute the intermediate signal \(b^{1}_{0}\) using the AND-XOR layout displayed in \[PE(\mathbf{p})=i \tag{14}\]2 By the end of this time instance, the tri-state buffers in both systolic arrays are enabled to store the computed values of \(a^{1}_{k-1}\) and \(b^{1}_{0}\). 2. At time instance \(t=1\), input signals \(d_{k-1}\), \(c_{k-2}\), \(f_{k-2}\), \(a^{0}_{k-1}\), and \(a^{0}_{k-3}\) are applied to the first PE (PE\({}_{1}\)) of the upper systolic array to compute the intermediate signal \(a^{1}_{k-2}\) utilizing the AND-XOR construction shown in \[PE(\mathbf{p})=i \tag{14}\]3 Also, at the same time instance, input signals \(d_{0}\), \(c_{1}\), \(f_{2}\), \(b^{0}_{0}\), and \(b^{0}_{2}\) are applied to the first PE (PE\({}_{1}\)) of the lower systolic array to compute the intermediate signal \(b^{1}_{1}\) utilizing the AND-XOR configuration shown in \[PE(\mathbf{p})=i \tag{14}\]4 Through this time instance, tri-state buffers in both systolic arrays are disabled to prevent writing the updated values \(a^{1}_{k-2}\) and \(b^{1}_{1}\) on the previous values of \(a^{0}_{k-1}\) and \(b^{0}_{0}\), respectively. At the end of this time instance, signals \(a^{1}_{k-1}\), \(a^{1}_{k-2}\), \(b^{1}_{0}\), and \(b^{1}_{1}\) will be available at the inputs of the second PE (PE\({}_{2}\)). 3. As the second and third time instances (\(t=2\) and \(t=3\)) occur, the second PE (PE2) in both systolic arrays continues its normal operation, similar to PE1, by preserving the most significant bit (MSB) of \(A\) (\(a^{2}_{k-1}\)) and the least significant bit (LSB) of \(B\) (\(b^{0}_{0}\)). It also updates the signals \(a^{2}_{k-2}\) and \(b^{2}_{1}\) accordingly. 4. In the general case, at time instances \(t=2i\), where \(2\leq i\leq\frac{k+1}{2}\), the processing elements (PE\(i\)) function similarly to PE1 and PE2 to sustain the most significant bits (MSBs) of \(A\) (\(a^{i}_{k-1}\)) and the least significant bits (LSBs) of \(B\) (\(b^{i}_{0}\)). They also update the signals \(a^{i}_{k-2}\) and \(b^{i}_{1}\).