# Constrained Optimization of FPGA Design for Spaceborne InSAR Processing
## 1 Introduction  
Synthetic aperture radar (SAR) is an all-weather and all-time system that can obtain high-resolution images. Interferometric Synthetic Aperture Radar (InSAR) is a new interferometry technology introduced into the field of SAR due to its high precision. After obtaining two or more SAR images of the same scene from slightly different angles, InSAR could detect minor topographical changes by processing the interferometric phase of those SAR images. In recent years, InSAR has played a vital role in geological research, including earthquakes [1, 2, 3], volcanoes [1, 2, 4, 5, 6], landslides [7, 8, 9], ground subsidence [10, 11, 12], etc. Moreover, with the ability to acquire three-dimensional elevation information, InSAR also demonstrates potential in forest height estimation [13, 14], space planetary exploration [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17], and ocean observation [18, 19, 20]. On-board processing, among other research areas of InSAR, attracts much research attention as it can reduce the volume of mission data through satellite-ground communication and improve the proportion of valid data [21]. Owing to the advancement of rad-hardened/tolerant FPGAs, SAR on-board processing has been realized [22], which provides a solid foundation for implementing InSAR. InSAR on-board processing is advantageous in fields with real-time requirements since it could reduce output data rates and downlink volume. For example, it has been employed in many oceanic studies, including ocean topology and surface water topography, which require the processing of a large amount of ocean observation data [23, 24]. As for fields that require high accuracy instead of real-time performance, such as planetary missions, on-board InSAR processing is not the ideal choice compared with the ground processing system at the currentstage. Therefore, this paper focuses on applying InSAR on-board processing technology in oceanic observation. Existing research on InSAR processing can be loosely grouped into two categories: the first type looks at the optimization of the InSAR algorithm under specific scenarios from theoretical perspectives [25; 26; 27; 28]; the second type focuses on the implementation and optimization of the InSAR engineering system [29; 30; 31; 32; 33; 34]. This paper belongs to the second type and works for the betterment of InSAR engineering. As the processing speed of the Central Processing Unit (CPU) is relatively low, GPU and Digital Signal Processor (DSP) are used as the mainstream processors in InSAR engineering. Since 2015, GPU has been applied to InSAR processing. The processing time of GPU is only one-tenth that of CPU, demonstrating its fast-processing capacity [29; 30; 31; 32; 33]. Some scholars implement the InSAR algorithm with DSP as the central processor. In 2016, [PERSON] et al. [34] built an InSAR system based on TMS320C6678 DSP. However, the above research was conducted with in-ground or airborne scenarios with no power constraints and low throughput. Due to the strict conditions on satellites, the volume power consumption is limited, and the image data volume is large, so it is challenging to meet the requirements of spaceborne real-time processing using DSP or GPU. Compared with DSP, FPGAs have the advantage of high processing capacity. Compared with GPU, FPGAs consume lower power consumption. Thus, FPGA has excellent potential in the field of spaceborne real-time processing. In addition, with the development of FPGA technologies, especially the advancement of rad-hardened FPGAs, such as Xilinx (San Jose, CA, USA) Virtex-5 QV and Zynq UltraScale+, on-board SAR processing has become a reality [21; 35], which prepares conditions for InSAR on-board processing. Yet, as on-board InSAR processing based on FPGA is a relatively new research area, this paper attempts to conduct exploratory research.