## 1 Introduction  
Three-dimensional stack-dies integrated circuit (3D-IC) is a technology used for multi-functionality and high-speed circuit devices [1]. 3D-IC has received much interest recently because of its small form factor, high performance, and heterogeneous integration in system-in-package technologies [2; 3; 4]. Three-dimensional technologies can provide higher chip-to-chip bandwidths at lower power levels that cannot be accomplished with available conventional packaging techniques. Additionally, they also offer the potential for low cost through heterogeneous integration. Interposers offer the first step to 3D integration of ICs, which simplifies physical planning and thermal management [4]. To achieve higher performance and reliability in 3D-IC, new design rules have to be developed because of the specific electrical, mechanical, and thermal constraints of 3D stacks [5; 6; 7]. Although stacking of chips began from memory and later on extend to logic chip, the technology of stacking is now also extending to radio frequency applications, which consist of mixed-signal IC to benefit from the 3D integration including shorter propagation delay; full isolation between analog and digital circuits in mixed-signal 3D-IC [8; 9]; and lower parasitic, which can reduce power consumption. With the 5G chip, this will be a trend. Despite the above-mentioned advantages, there are several challenges associated with 3D-ICs. The two most significant challenges are the quality of the wafer-wafer bonding and thermal management. Three-dimensional technology poses a major challenge in thermal management owing to the increase in power density and number of vertically stacked active layers [10; 11]. Therefore, researchers have made efforts to solve for the thermal stress issue in 3D-ICs through thermally aware floor planning or task scheduling [12]. Besides these challenges, there is another emerging challenge that has been rather overlooked, namely the electromagnetic coupling between stack dies [13; 14; 15]. These electromagnetic couplings are known as electromagnetic interferences (EMIs), which are a consequence of high frequency switching currents, complex power delivery paths, and an increase in parasitic couplings in comparison with 2D integration. The increase in the parasitic couplings between stacked dies is the result of the decreasing stack up distances between them, as shown in Figure 1, as extracted from the works of [16; 17; 18; 19; 20; 21; 22; 23]. In 2017, this distance decreased to 15 \(\upmu\)m [16] from 150 \(\upmu\)m in year 2000 [22], which is a 10-fold decrement. This decrease is necessary in order to maximize the advantages of 3D vertical integration including shorter interconnect lengths, greater integration density, and lower power consumption, which enhances the overall performance of the system with such technologies. The main driving forces to keep the stack distance lesser between the stacked dies are the increased demand of dies with faster data exchange rate, lower power consumption, and smaller size, and such a decreasing trend is expected to continue in the future. With this decreasing trend of the distance between the dies, one limitation will be the thermal dissipation of the 3D-IC, and another one will be the electromagnetic interference between them. If  
Figure 1: Three-dimensional stack-dies integrated circuits (3D-ICs) trend for vertical distance between ICs [16; 17; 18; 19; 20; 21; 22; 23]. one of the dies in the 3D-IC stack is the source of EMI, it could affect the nearby dies when the distance between them is small. This work explores the latter limitation. This limitation depends on two factors. One is the circuit susceptible to EMI and another one is the parasitic coupling. The former one requires ingenious circuit design, which is beyond the scope of this work. To reduce the parasitic coupling with the decreasing distance between the dies, several possibilities are available.