# Effects of Fractional Time Delay as a Low-Power True Time Delay Digital Beamforming Architecture
###### Abstract  
True time delay digital beamforming enables large squint-free bandwidths and high beamcounts, ideal for Low Earth Orbit (LEO) satellite communication links. This work proposes a true time delay architecture using Variable Fractional Delay (VFD). True time delay eliminates many analog beamforming performance constraints including inaccurate beam steering and limited beamcounts, while managing system quantization error. This article presents a method of implementing true time delay using a VFD digital filter with sufficient time resolution to minimize quantization error and enable both gigahertz bandwidths and sampling frequencies. Simulations of antenna patterns utilizing the proposed VFD digital filters demonstrate satisfactory LEO beamforming performance with only a 29-tap filter. The VFD filter was implemented using a Xilinx Virtex Ultrascale FPGA and demonstrated a 1077% reduction in dynamic power and a minimum 498% reduction in logic resources, with only a modest increase in multipliers required when compared to Farrow-based architectures previously proposed in the literature. digital beamforming; true time delay; phased array; variable fractional delay; quantization sidelobes +
Footnote †: journal: _Electronics_  
0000-0001-6000-00001-6000][PERSON]  
0000-0001-6000-0001-6000-00001-6000-0001-6000-0001-60000-0001-60000-0001-60000-0001-60000-0001  
baseband for digital processing [7; 8]. At baseband, a coarse integer sample delay is applied, and then phase shifters are implemented to reduce quantization error. While this method does reduce beam squint, phase shifter stages only approximate time delay and thus the architecture is limited to a relatively narrow bandwidth of 100 MHz [7; 9]. In order to overcome the bandwidth constraints, other works have expanded upon traditional integer delay techniques by using fractional delay [10; 11; 12; 16; 17; 18]. Farrow architecture filters are commonly used for Variable Fractional Delay (VFD) filter designs; however, their complexity increases significantly at higher sampling rates [10; 11; 12; 13; 16; 17]. [PERSON] et al. avoid this constraint by utilizing a multirate Farrow architecture that increases bandwidth through the addition of an upsample and downsample element at each VFD filter [10]. However, this technique also adds complexity to the design that can be costly to integrate into silicon processes. [PERSON] et al. propose a peak-to-average power ratio (PAPR)-focused architecture using Lagrange interpolation filters in order to achieve maximum energy efficiency of the output signal [18]. As with any interpolated filter architecture, Lagrange filters suffer from increased computational complexity and frequency response error when compared to lowpass or allpass filters [14; 15]. [PERSON] et al. state that real-time coefficient updates can become too computationally expensive to be realistic for complex Farrow filters, further supporting an alternative architecture [14]. Alternatively, traditional Finite Impulse Response (FIR) lowpass filter structures can be a desirable architecture due to their excellent least-squared approximation error [14; 15]. Additionally, FIR filter structures are extremely computationally efficient and can be optimized heavily. In order to overcome the complexity, bandwidth, and beam squint constraints of present VFD and DBF methods, this work will utilize a lowpass FIR filter designed specifically for direct implementation into standard CMOS processes. This novel architecture will use a unique approach to VFD that focuses on minimum power and resource consumption optimizations of the delay unit for use in SATCOM applications. Results will show that the architecture boasts exceptionally low power and resource consumption when compared to similar designs available in the literature, at the expense of some filter and bandwidth performance. The FIR filter design in this work will target a 10 GHz sampling rate (\(F_{s}\)) and 4 GHz bandwidth for LEO applications.