# Understanding the Light Detection in an Integrated Novel Electrophotonic Wavesensor Photodetector
## 5 Results  
Figure 7 depicts a cross-section of the device in the Punch-Through regime as obtained by fabrication process simulation using SILVACO-Athena. The drain and source diffusions are heavily doped and have a depth junction of around 4 \(\upmu\)m. This is due to the thermal treatment necessary in SRO-based light emitters, which is 1100 \({}^{\circ}\)C for 180 min [5]. As mentioned, the fabrication process was simulated using these thermal treatment conditions because the device is intended to work with an embedded SRO emitter, for full and monolithic integration. To simulate its photoelectric behavior, the gate was biased at \(V_{GS}=-5\) V, in order to promote hole accumulation in the surface. This way, the drain current can be exclusively controlled by the drain-source voltage, and current effects due to surface phenomena are avoided. The drain-source voltage applied was \(V_{DS}=5\) V, causing the overlap of the depletion zones around drain and source (Punch-Through condition). For the wavelengths of interest, the absorption depth in silicon is located inside the depletion region, approximately from 0.1 \(\upmu\)m to 10 \(\upmu\)m for respective wavelength limits of 400 nm and 800 nm [27, 41]. Figure 8 shows the electric field profile for the WS under the mentioned bias conditions. Figure 7: WS obtained in Athena-Silvaco. Red lines show the edge of the depletion width when the drain is biased on Punch-Through. The strongest electric field is located close to the drain zone, caused by the \(V_{DS}\) voltage. If electron-hole pairs are produced in the space charge region, the electric field transports the electrons into the drain terminal, and the holes are separated towards the substrate. Note the accumulated region in the surface, indicating no surface current can go through. Figure 9 shows the drain current as a function of drain voltage, considering both dark and light stimulation conditions. As mentioned, a negative value of \(V_{GS}\) prevents carrier transport through the surface, and the current is dominated by carrier generated in the substrate. The drain current-voltage behavior under this condition fits a quadratic curve. This is consistent to the mechanism of space charge limited current. If drain current in dark condition \(I_{Dark}\) is subtracted from the total observed current when there is light \(I_{D}\), it can be obtained the contribution of light to the drain current \(I_{Dopt}\). If the ratio of this value to the ideal photocurrent (\(I_{ph}\)) is larger than one, it can be concluded that the device exhibits an optical gain \(\beta_{opt}\), as predicted by the previous analysis. This is presented in (17):  
\[\beta_{opt}=\frac{I_{D}-I_{Ddark}}{I_{ph}} \tag{17}\]  
Figure 10 shows such photocurrent ratios for different optical powers and drain voltage. Figure 8: Electric Field inside the simulated WS. The direction is showed with arrows and the magnitude is represented in logarithmic scale with color levels. \(V_{DS}\) was 5 V, \(V_{BS}\) was 0 V and \(V_{GS}\) was \(-5\) V.  
\(\beta_{opt}\) is approximately 100 for \(V_{DS}\) = 2 V when light power is 10 nW. It reaches 400 when \(V_{DS}\) = 5 V. Note that, although the gain increases with the drain voltage, the dark current is  
Figure 10: Photocurrent ratio, \(\beta_{opt}\), for different optical power as a function of drain voltage. Figure 9: Drain current as function of drain voltage under illumination for different optical powers. also incremented. Then, there is a compromise between photocurrent gain and keeping the dark current low. It can be seen that the obtained gain is reduced when the optical power is increased. In spite more research is needed to better understand this phenomenon, this can be related to the variation of the Fermi quasi-level produced by the photo generated carrier excess. That is, the higher the input light power, the more influential the effect of photogeneration on the source barrier.