# Design of Multifunctional Mesosphere-Ionosphere Sounding System and Preliminary Results
## 2 System Description
### Multichannel Receiver  
The receiving subsystem of MAI system is a 6-channel digital intermediate frequency (IF) receiver. After filtering, amplifying, mixing, and A/D sampling at the analog front-ends, the six digital IF signals are input into the DDC module in parallel. Through the digital IF processing for demodulation at the DDC module, the baseband signals are uploaded via USB bus for further analysis. The algorithms of the pulse compression and the physical parameter inversions of the baseband signals are realized by software on the host computer.  
The circuit design of each analog channel is shown in Figure 6. A suppression switch isolates the fade zone through timing control. And the multi-channel suppression switches constitute the switch array to suppress the near field coupling of the transmitting antenna during the transmission. Considering the need of MAI system to ensure the receiving performance of both MF and HF bands, the preferred filter of the first stage chooses a larger bandwidth, which is 0-30 MHz, covering the whole working frequency band. Two-stage amplification mode is employed in this system. The first low noise amplifier (LNA) is placed before the mixer, while the second stage is an IF amplifier. The total gain of the front-end can reach 53.1 dB. In order to effectively suppress the mirror frequency, the intermediate frequency is selected at a higher frequency band of 71.4 MHz.  
As the range resolution of the MAI system is 1.92 km, corresponding to the duration of each code bit \(T_{p}=12.8\)\(\upmu\)s, the IF bandwidth \(B\) of the radar is selected as Equation (7) [31]:  
\[B=1.5/T_{p}=117.1875\;\mathrm{kHz}\approx 120\;\mathrm{kHz} \tag{7}\]  
To realize the impedance matching of two-port network between the different levels, \"\(\pi\)\" resistance networks with an attenuation value of 1 dB are added. Therefore, when the filter insertion losses are included, the total noise figure (NF) of each analog front-end is about 10 dB. Then the sensitivity of the analog front end can be determined as Equation (8) [31]:  
\[S{=-114\;\mathrm{dBm}+NF+10\log B(\mathrm{MHz})\approx-113\;\mathrm{dBm}} \tag{8}\]  
For the MAI system, the selected sampling digit of ADC is \(N=14\) bits with a 2.5 \(V_{pp}\) full voltage range. When the sampling rate is \(f_{s}=20\) MHz, the maximum SNR of ADC can be calculated as Equation (9) [31]. Further, the dynamic range \(DR\) can be determined as Equation (10), which can also be considered as the dynamic range of the receiver [31].  
\[SNR(dB)=6.02N+1.76+10\log(f_{s}/2B)=105.2\;\mathrm{dB} \tag{9}\]  
\[DR=V_{\mathrm{max}}/V_{\mathrm{min}}=77.5\;\mathrm{dB} \tag{10}\]  
where \(V_{\mathrm{max}}\) and \(V_{\mathrm{min}}\) represent the maximum sampled voltage and voltage resolution of ADC, respectively.  
In the DDC module, as shown in Figure 7, the 8.6 MHz orthogonal signals are generated by the numerically controlled oscillator (NCO) for digital mixing. Through the cascade integrator comb (CIC) and finite impulse response (FIR) filters, the echo signals are converted into the baseband I/Q data. The simple structure of CIC filter reduces the difficulty of design [33], and FIR filter compensates for the irregularity of CIC filter's passband. Due to the 256 times downsampling during the process of the two-stage anti-aliasing filters, the output data rate of the digital signal of each channel is reduced from 40 Mbps to 156.25 kbps. The whole DDC module is implemented in a field-programmable gate array (FPGA) chip for easy modification and high-speed operation.  
Figure 6: The circuit design of the analog channel. Between the levels, several “\(\pi\)” networks are employed to match the impedance and adjust the gain consistency of each channel.