# A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Sredes Receiver
## 3 Crucial Techniques
### Lower-Power Techniques
#### 3.2.2 Sigma-Delta-Based Average  
Averages are frequently utilized in the DSP to perform the digitalized common-mode voltage, including offset calculation, amplitude detection, and threshold computation. The parallel multi-bit data processing requires a large number of averages, such as 64 averages are required to perform the 64 offsets corresponding to the 64 sub-ADC. This makes a significant portion of the total power consumption consumed in calculating the average. Traditional averaging can be achieved with a typical moving average filter [5]. However, the implementation of the moving average filter is based on delay, summation, and averaging, which consumes a lot of flip-flops and adders (see Figure 9a), and as the average data \begin{table}
\begin{tabular}{c c c c c c} \hline
**Type** & **Sum Factor** & **Sum Pipeline** & **Technology** & **Clock (Hz)** & **No.Adders** & **Power** \\ \hline Full & 63 & 3 & 28 nm & 1 G & 12,676 & 20.5 mW \\ Random & 1 & 1 & 28 nm & 1 G & 1290 & 2.0 mW \\ \hline \end{tabular}
\end{table} 
Table 2: The resource comparison in LMS DFE. Figure 8: LMS adaptation for the DFE. (**a**) Traditional implementation utilizing all parallel data. (**b**) Proposed implementation using randomly-selected data. Figure 7: LMS adaptation for the FFE. (**a**) Traditional implementation utilizing all parallel data averaging. (**b**) Proposed implementation using randomly-selected data averaging. depth increases, the hardware consumption will be rise linearly. In this design, we propose to utilize the 1 st-order sigma-delta modulators to replace traditional moving average filters. Figure 9b shows the simplified diagram of the sigma-delta-based average, where 1/N of the integrator output is subtracted from the input data. This error is directly applied to the integrator to calculate the averaging result. Here, N is selected as an integer power of 2, which makes the feedback value can be obtained by truncating the integrator output. It is obvious this sigma-delta-based average only needs an adder and an integrator, which prominently reduces the hardware resources in contrast to the moving average filter. Moreover, this hardware consumption does not change as the averaging number N increases. The transfer function and frequency response of the sigma-delta-based average be given by the following two equations:  
\[y(t)=(x(t)-n*y(t))*h(t) \tag{2}\]  
\[y(t)=\frac{h(t)}{1+n*h(t)}*x(t) \tag{3}\]  
\[Y(jw)=\frac{1}{jw+n-1}*X(jw) \tag{4}\]  
In the above formula, h(t) is the transfer function of the integrator, which can be expressed as 1/(t - 1), and n represents the coefficient. It can be seen from the expression that the value of n can limit the output bandwidth to achieve make the output stable. Table 3 displays the comparison of traditional 4 th-order moving average filter and 1 st-order sigma-delta-based average in terms of adder number and power consumption. It can be seen that the proposed averaging algorithm based on \(\sigma\)-\(\delta\) only requires 1/3 of the power consumption of the traditional moving average filter. Obviously, the sigma-delta-based average has a great advantage in reducing resources and power consumption. From the Equation (1), it can be obtained that the data required by the LMS is the output decision level (-3, -1, 1, 3) and the ideal level, both of which can be obtained by the DFE through the decider. Therefore, the DFE decider needs to calculate three intermediate value levels through the input data, and then obtain four decision levels and four ideal levels through these three intermediate value levels. Therefore, in order to obtain the above data, the average operation is performed on the input data to obtain three intermediate value levels, and then the obtained three intermediate value levels are judged and calculated to obtain four decision levels and four ideal levels.