# High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA
## 3 The ASMD-FSMD Technique
The central step in this design approach is creating an ASMD chart that represents the behavior or operational algorithm of the digital device. This approach avoids strict separation between the datapath and control unit. However, the ASMD chart establishes FSM states corresponding to the control unit's states. This linkage helps synchronize the device's operation with clock cycles, enabling developers to track the clock cycle count for each branch of the algorithm. Additionally, the ASMD chart does not directly specify the datapath's structure, leaving its implementation flexible. Note that the ASMD language provides more possibilities for describing the behavior of the device than the traditional approach. For example, for a Mealy FSMD in one ASMD block, it is possible to perform various variable operations sequentially, compare the obtained values with each other or with constants, and, depending on the results of the comparison, perform some operations with the same variables. Moreover, all these operations are performed in one clock cycle. Thus, with ASMD, it is possible to describe a digital device on a behavioral level, which is impossible with the traditional approach. **Hypothesis 1. ** Using the ASMD-FSMD technique allows one to perform multiple operations on the same variable in a single clock cycle, which leads to an increase in device performance compared to the traditional approach. Experience with the ASMD-FSMD technique [14; 15; 16] shows that the ASMDs of Mealy FSMDs are better suited for building high-performance digital devices. As an example, let us consider the ASMDs for the Mealy FSMD, which describes multipliers c and d (Figure 6). The ASMD chart of the multiplication algorithm c (Figure 6, on the left) consists of two ASMD blocks, which correspond to the states \(S_{0}\) and \(S_{1}\) of [PERSON]'s FSMD. State \(S_{0}\) waits for the signal run, when run = 1 the variables are initialized. State \(S_{1}\) corresponds to the multiplication loop. When rb[\(N-1\)] = 1, the multiplicand value is added to the content of the register rp; otherwise, nothing is added. The counter cnt value is then incremented, and the content of the register rb is shifted to the left. The value of the counter cnt is checked in the same ASMD block. If cnt = \(N-1\), then the flag done is set, and the multiplication process ends. Otherwise, the content of the register rp is shifted to the left, and the multiplication cycle is repeated. The ASMD chart of the multiplication algorithm d (Figure 6, on the right) is very similar to the ASMD of algorithm c. The differences are not significant, and they concern the register shift direction, the addition range, and the rb register bit, which should be checked. When rb[0] = 1, the multiplicand value is added to the content of the upper part (\(2N-1:N\)) of register rp; otherwise, nothing is added. During the incrementation of the counter cnt value, the content of the register rb is shifted to the right. If cnt is not equal to \(N\)-1, then the content of the register rp is shifted to the right, and the multiplication cycle is repeated. Note that in one ASMD block, the value of the register rp is added, the content of the register rp is shifted, and the value of the counter cnt is increased, and this value is compared with \(N-1\). Thus, when using the ASMD-FSMD technique, the multiplication of \(N\)-bit numbers A and B by algorithm c is performed in \(n=N+1\) clock cycles. Directly from the ASMD charts in Figure 6, we can write the Verilog code of the sequential multiplier in the form of the FSMD, which implements the multiplication algorithm c (Appendix A, module mult_c_Mealy_FSMD). The variables in the ASMD charts for the multiplication algorithms presented in Figure 6 are described in the following:  
* ra: multiplicand (value of register ra);
* rb: multiplier (value of register rb);
* rp: result (value of register rp);
* cnt: counter (value of register cnt);
* done: the value of the output signal done (from cnt).