# Analysis of Pre-Driver and Last-Stage Power--Ground-Induced Jitter at Different PVT Corners
###### Abstract
For example, \(h_{vdd}(t)\) and \(h_{vddq}(t)\) are defined as the impulse response of the pre-driver and last stage's off-die PDN. Moreover, \(I_{Hp}(t)\) and \(I_{H}(t)\) are the switching current of the pre-driver and last stage IO buffers, as shown in Figure 2. Therefore, the power supply voltage (PSV) ripples induced at the on-die pre-driver and buffer's last stage can be written in the time and frequency domains in Equation (1). The equiv  
Figure 1: Illustration of timing distortion known as jitter occurring at the rising and falling transition of the output signal. Reference signal (solid blue line). Distorted signal (red dashed line). Figure 2: IO buffer circuit diagram with separate PDN for the pre-driver and last stage. voltage noise is formulated as a multiplication of the current spectrum and the PDN impedance \(Z_{PDN}\)  
\[\left\{ \begin{array}{rcl}v_{dd}(t)=\int_{0}^{+\infty}\ h_{vdd}(t-\tau)\cdot I_{ Hp}(\tau)\ d\tau&\Leftrightarrow V_{DD}(f)=Z_{vdd}^{PDN}(f)\times I_{ Hp}(f)\\ v_{ddq}(t)=\int_{0}^{+\infty}\ h_{vddq}(t-\tau)\cdot I_{H}(\tau)\ d\tau& \Leftrightarrow V_{DDQ}(f)=Z_{vddq}^{PDN}(f)\times I_{H}(f)\end{array} \right. \tag{1}\]  
Similar to Equation (1), it can be derived for the ground supply voltage variations  
\[\left\{ \begin{array}{rcl}v_{ss}(t)=\int_{0}^{+\infty}\ h_{\rm ss}(t-\tau) \cdot I_{Lp}(\tau)\ d\tau&\Leftrightarrow\ V_{SS}(f)=Z_{vss}^{PDN}(f)\times I_{ Lp}(f)\\ v_{ssq}(t)=\int_{0}^{+\infty}\ h_{vssq}(t-\tau)\cdot I_{L}(\tau)\ d\tau& \Leftrightarrow V_{SSQ}(f)=Z_{vssq}^{PDN}(f)\times I_{L}(f)\end{array} \right. \tag{2}\]  
The PDN characteristics in terms of the resonance frequency, bandwidth, loop inductance, etc. (i.e., \(Z_{vdd}^{PDN}(f)/Z_{vss}^{PDN}(f)\) and \(Z_{vddq}^{PDN}(f)/Z_{vssq}^{PDN}(f)\)), and switching current spectrum (i.e., \(I_{Hp}(f)/\ I_{Lp}(f)\) and \(I_{H}(f)/\ I_{L}(f)\)) are different for both \(V_{DD}/V_{SS}\) and \(V_{DDQ}/V_{SSQ}\). Therefore, the jitter/timing distortions induced by the IO buffer pre-driver and the last-stage PGSV variations present different mechanisms and performance numbers (e.g., [3,6]). Previous IO buffer-modelling methodologies, which can be classified either based on the equivalent circuit input-output buffer information specification (IBIS) or parametric curve fitting [8,9], have not clearly addressed the PVT corner simulation and its importance in the model's generation steps, worst corner identification, and in the validation of model performance. In fact, the standard multiport behavioral model structure that describes the electrical behaviors of the IO buffer circuit, while considering the PGSV variables [7, 8, 9], is:  
\[i_{2}(t)=w_{L}(t)F_{L}\bigg{(}\mathrm{x}_{dd}(t),\frac{d\mathrm{x}_{dd}}{dt} \bigg{)}+w_{H}(t)F_{H}\bigg{(}\mathrm{x}_{ss}(t),\frac{d\mathrm{x}_{ss}}{dt} \bigg{)}+i_{ddq}(t)+i_{ssq}(t) \tag{3}\]  
where voltage differences \(\mathrm{x}_{dd}(t)=v_{dd}(t)-v_{2}(t)\) and \(\mathrm{x}_{ss}(t)=v_{2}(t)-v_{ss}(t)\) are applied to the \(F_{L}(\cdot)\) and \(F_{H}(\cdot)\) functions that model the nonlinear dynamic output admittances of the driver's last stage under low and high input logic levels, respectively. This model considers not only the static contribution of the FG voltage fluctuation of the last stage, but also the delay introduced by the pull-up (PU) and pull-down (PD) capacitances, which are represented by the derivatives. \(i_{ddq}(t)\) and \(i_{ssq}(t)\) are timing current (I-\(t\)) tables, that include crow-bar, on-die decoupling, pre-driver, and current contributions, which are provided by the IBIS power-aware enhancement to predict the voltage ripple introduced at the IO buffer's circuit supplied by \(V_{DDQ}\), [8, 9, 10, 11, 12, 13, 14, 15, 16]. \(w_{L}(t)\) and \(w_{H}(t)\) are switching timing signals that capture the IO timing behavior of the pre-driver stage, which is powered by \(V_{DD}/V_{SS}\) supplies.