## 4 Adaptive Method of Improving the Processing Parameters in the Frequency-to-Code Converter  
The presented method is not intended to compete with the systems realizing high-speed analog-to-digital processing. Rather, it is recommended for using in a measurement channel with a frequency information carrier in which the integrating nature of the operation of the X/f converter allows the processing of signals with low frequencies [14]. The discussed author's method allows for the adaptive improvement of the processing parameters in the frequency-to-code converter of successive periods of the input signal with a variable frequency into its digital representation in a manner adapted to the performance of the processor used in the frequency-to-code converter. Frequency-to-code converters are often based on a counter system [3] that allows for a continuous reading of the status without stopping the counter operation. Typically, the counter circuit works with a processor with attached RAM memory. The reason is the lack of the possibility of the clear, direct presentation of the current, rapidly changing measurement results on a simple indicator (e.g., LED, LCD). Consequently, it is necessary to process and store the obtained results, for example, in RAM or on a memory card, for analyses performed with a certain delay, imposed by the adopted technical solutions in a specific device. The presentation of the method is based on the previously shown structure of the microprocessor system of the f/N converter (Figure 1). The modification of the circuit is shown in Figure 7. The basic circuit in Figure 1 has been supplemented with a clock frequency divider/multiplier module \(f_{0}\). The method allows reducing the error made during the measurement of successive periods of the variable frequency signal, thus increasing the measuring range of the device in which the measurement will be carried out with a similar processing error. The implementation of the method is possible with processor  
To simplify the considerations, it was assumed that a square wave signal with logical levels adapted to the voltage levels required by the processor is fed into the input of the f/N converter. Changes in the logic states at the processor input allow the processor software to determine the beginnings of subsequent \(T_{xi}\) periods. At the moment of detecting the beginning of the next \(T_{xi}\), the processor reads the current state of the counter, summing the pulses formed by the signal periods from the prescaler/frequency multiplier module and changing the frequency of the reference signal \(f_{0}\) from the clock signal generator. The read state from the counter system is stored in RAM memory until the next state is read, corresponding to the detection by the processor software of the beginning of the next period \(T_{xi}\). Then, the processor calculates the difference of the successive states read from the counter, representing the period length \(T_{xi}\) of the variable frequency signal. At this point, the second phase of the frequency-to-code converter operation begins, carrying out the procedure correcting the frequency change factor \(f_{0}\) of the signal from the reference frequency generator. The difference of states read from the counter system reflects the period value that takes into account the frequency change factor in the prescaler/multiplier module and the frequency of the signal from the clock signal generator. The computed difference \(N_{xi}\) is used to determine the value of the maximum processing error (8) made when measuring the period \(T_{xi}\)[14]. The value of \(N_{xi}\) is stored in the RAM at the index \(i\). After detecting that the permissible value of the quantization error has been exceeded (option \"Y\" in Figures 8 and 9), the procedure determines the frequency change factor that allows reducing the processing error to the limit set in the program and sets the required frequency change factor in the prescaler/multiplier module.