## 5 Experimental Results
As written in the previous chapter, the proposed solutions were used in a project of considerable complexity (the Quasar project [47]). The synthesis targeting the XCKU035-2 SFVA784I chip was realised in the Vivado tool (due to the support of the FPGA chip manufacturer, AMD). In this vendor's devices, LUT blocks are grouped into more advanced CLB (Configurable Logic Block) cells, which can operate in well-defined configurations. In the first instance, synthesis was carried out without any mitigation. This led to the use of 113,347 LUT blocks, representing 55.80% of all blocks (corresponding to 26,027 complex CLB blocks (85.90%)). The described TMR mitigation was then carried out in the report of the encryption modules. This led to the use of 137761 LUT blocks, representing 67.82% of the total blocks (corresponding to 30,300 complex CLB blocks (99.49%)). It should be noted here that the system had to perform resynthesis several times for the synthesis to be successful. The bitstream was then generated and the FPGA device was programmed \begin{table}
\begin{tabular}{l c c c c c c c c} \hline \hline  & & & \multicolumn{3}{c}{**Bench.**} & \multicolumn{2}{c}{**Bench.+vot.**} & \multicolumn{2}{c}{**Bench.+vot.+El**} \\
**Name** & **IN** & **OUT** & **ST** & **LUT** & **POWER** & **LUT** & **POWER** & **LUT** & **POWER** \\ \hline bbtas & 2 & 2 & 6 & 3 & 0.473 & 3 & 0.467 & 74 & 0.878 \\ beecount & 3 & 4 & 7 & 7 & 1.074 & 7 & 1.072 & 88 & 1.546 \\ dk14 & 3 & 5 & 7 & 7 & 2.885 & 7 & 2.89 & 91 & 3.383 \\ dk15 & 3 & 5 & 4 & 4 & 2.475 & 4 & 2.475 & 88 & 2.985 \\ keyb & 7 & 2 & 10 & 48 & 0.774 & 48 & 0.774 & 121 & 1.207 \\ lion & 2 & 1 & 4 & 2 & 0.245 & 2 & 0.245 & 69 & 0.636 \\ lion9 & 2 & 1 & 9 & 2 & 0.265 & 2 & 0.265 & 69 & 0.636 \\ mc & 3 & 5 & 4 & 4 & 2.481 & 4 & 2.481 & 86 & 2.775 \\ train11 & 2 & 1 & 11 & 4 & 0.265 & 4 & 0.263 & 71 & 0.662 \\ train4 & 2 & 1 & 4 & 2 & 0.183 & 2 & 0.183 & 68 & 0.567 \\ \hline \multicolumn{2}{c}{Sum} & & 83 & 11.12 & 83 & 11.115 & 825 & 15.275 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Results of the synthesis of sequential circuits in the Vivado system. \begin{table}
\begin{tabular}{l c c c c c c c c} \hline \hline  & & & \multicolumn{3}{c}{**Bench.**} & \multicolumn{2}{c}{**Bench.+vot.**} & \multicolumn{2}{c}{**Bench.+vot.+El**} \\
**Name** & **IN** & **OUT** & **LUT** & **POWER** & **LUT** & **POWER** & **LUT** & **POWER** \\ \hline
9 sym & 9 & 1 & 6 & 0.441 & 6 & 0.442 & 73 & 0.851 \\ alu2 & 10 & 8 & 14 & 2.703 & 14 & 2.702 & 103 & 3.26 \\ alu4 & 14 & 8 & 286 & 5.978 & 286 & 5.978 & 373 & 6.493 \\ b12 & 15 & 9 & 14 & 2.29 & 13 & 2.305 & 110 & 2.817 \\ clip & 9 & 5 & 20 & 2.924 & 27 & 3.083 & 110 & 3.547 \\ cm162a & 14 & 5 & 7 & 1.435 & 7 & 1.433 & 91 & 1.944 \\ cm163a & 16 & 5 & 7 & 1.351 & 7 & 1.349 & 93 & 1.85 \\ cm85a & 11 & 3 & 6 & 0.793 & 6 & 0.793 & 81 & 1.29 \\ con1 & 7 & 2 & 2 & 0.799 & 2 & 0.799 & 74 & 1.236 \\ ex1010 & 10 & 10 & 170 & 8.11 & 170 & 8.121 & 279 & 8.95 \\ f51m & 8 & 8 & 10 & 3.925 & 10 & 3.923 & 99 & 4.487 \\ inc & 7 & 9 & 10 & 2.963 & 10 & 2.963 & 105 & 3.533 \\ rd53 & 5 & 3 & 2 & 1.491 & 2 & 1.491 & 77 & 1.946 \\ rd73 & 7 & 3 & 6 & 1.953 & 6 & 1.953 & 81 & 2.423 \\ rd84 & 8 & 4 & 11 & 2.11 & 11 & 2.115 & 94 & 2.578 \\ sao2 & 10 & 4 & 30 & 1.182 & 34 & 1.251 & 110 & 1.667 \\ sqrt8 & 8 & 4 & 6 & 1.536 & 6 & 1.535 & 87 & 2.025 \\ t481 & 16 & 1 & 5 & 0.721 & 5 & 0.721 & 72 & 1.135 \\ x2 & 10 & 7 & 8 & 1.671 & 8 & 1.639 & 94 & 2.146 \\ vor5 & 5 & 1 & 1 & 0.776 & 1 & 0.776 & 68 & 1.191 \\ \hline \hline \multicolumn{2}{c}{Sum} & & 621 & 45.152 & 631 & 45.372 & 2274 & 55.369 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Results of the synthesis of combinatorial circuits in the Vivado system. and tested using prototype DPU. This shows that the solutions proposed in this paper can be applied to practical applications of considerable complexity, which is crucial when designing devices aimed at space missions.