# A High-Gain CNTFET-Based LNA Developed Using a Compact Design-Oriented Device Model
## 5 Simulation Results  
Extensive simulations have been performed using the complete Verilog-A CNTFET model to ensure that the amplifier, designed with the simplified model, actually performs according to its designed specifications. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Node \(n\)** & \(V_{\text{Lr}}\) & \(V_{\text{DD}}-V_{\text{Hr}}\) & \(x_{n}\) **(\%)** & \(V_{n}\) **(V)** \\ \hline D1 & \(V_{\text{G2}}+V_{\text{P}}\) & \(V_{\text{P}}\) & 50 & 1.3559 \\ G1 & \(V_{\text{G2}}+V_{\text{TH}}\) & \(V_{\text{P}}\) & 90 & 1.6302 \\ G2 & \(V_{\text{TH}}\) & \(V_{\text{P}}+V_{\text{TH}}\) & 30 & 0.7118 \\ G3 & 0 & \(V_{\text{TH}}\) & 0 & 0.0000 \\ G4 & 0 & \(V_{\text{TH}}\) & 0 & 0.0000 \\ G5 & \(V_{\text{TH}}\) & 0 & 10 & 0.6716 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: LNA biasing constraints and optimized values. \(V_{\text{Lr}}\) is the minimum allowed node voltage, and \(V_{\text{Hr}}\) is the maximum. The last two columns report the final optimized node voltage as a percentage of the allowed swing (\(x_{n}\)) and in volts (\(V_{n}\)). \begin{table}
\begin{tabular}{c c c} \hline \hline
**FET** & \(W\) **(\(\mathbf{\mu}\)m)** & \(I_{\text{D}}\) **(mA)** \\ \hline \(M_{1}\) & 250.6 & 7 \\ \(M_{2}\) & 150.4 & 2 \\ \(M_{3}\) & 19.1 & 2 \\ \(M_{4}\) & 67.0 & 7 \\ \(M_{5}\) & 669.6 & 7 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: CNTFET sizes as determined by numerical optimization of the LNA. As a first test, Figure 7 reports the voltage gain of the amplifier. From the design data reported in Table 2, its nominal value should be around 25.7 dB, and as can be seen, the achieved gain is pretty close, with a \(-3\) dB bandwidth of about 2.5 GHz. The noise factor depends, of course, on the parameters used for the noise model, for which, unfortunately, we could not find enough experimental data to validate the value we used in our model and on the biasing of the input transistor, as discussed earlier. Nevertheless, with the values reported in the main text, the amplifier achieves around 1 dB of noise figure within the amplifier bandwidth, as shown in Figure 8.  
Figure 8: LNA noise factor. Figure 7: Overall LNA voltage gain with a 500 \(\Omega\) load. Its linearity is also very good, due to the intrinsically linear input characteristics of the above CNTFET threshold, as demonstrated by the input-referred 1 dB compression point shown in Figure 9, which, considering the high gain of the amplifier, is essentially limited only by the swing of the output node. Finally, the stability of the amplifier was also evaluated by a pole-zero analysis, reported in Figure 10, from which it is clear that the amplifier is indeed stable (all poles have negative real parts). It is also clearly visible that the amplifier bandwidth is limited by the pair of complex conjugate poles at around 2.5 GHz. Figure 10: Pole-zero diagram of the amplifier showing LNA stability. Figure 9: LNA linearity: 1-dB input-referred compression point. A summary of the achieved performance is shown in Table 3, together with a comparison with those obtained by similar works, also taking into account some results relative to conventional CMOS LNAs, as there are still not many works that focus on LNAs made with CNTFET. In particular, with respect to the two CNTFET LNAs reported in the table, our architecture has the highest gain, which could be obtained without sacrificing bandwidth due to the gm-boosting technique adopted. The high gain also helped in achieving a low NF, of the same order as the best CNTFET LNA reported in the table and at a comparable power dissipation level, and much lower than the CMOS alternatives, due to the intrinsic lower noise of the carbon nanotubes versus conventional transistors. Of course, due to the relatively young stage of the CNT technology we are designing, and to the fact that the model used was fitted to simulated data, we expect that it might not capture all the details of the manufactured transistor.