## 3 Results and Discussions
Figure 7a shows the gate-to-drain capacitance characteristics with the symmetric high-\(\kappa\) spacer (\(\kappa\) = 25) and the asymmetric high/low-\(\kappa\) spacer (\(\kappa\) = 25/3.9). It is clearly shown that the outer-fringing capacitance decreases due to the reduced dielectric constant with the negligible effects on the source-side. In terms of the switching speed, inverter characteristics are analyzed with the symmetric and the asymmetric spacers, as shown in Figure 7b. Through transient simulations, the falling delay, which is defined by the time difference between input and output voltages at half supply voltage, is extracted as the indicator of an inverter response. As a result, each falling delay is 0.38 ns, 0.20 ns, and 0.18 ns for the symmetric low-\(\kappa\) spacer (\(\kappa\) = 3.9), the symmetric high-\(\kappa\) spacer  
Figure 5: (**a**) 2D contour mapping of electron tunneling rate at V\({}_{\text{GS}}\) = \(-\)0.3 V and V\({}_{\text{DS}}\) = 1.0 V for the spacers with \(\kappa\) = 3.9 and \(\kappa\) = 25. (**b**) One-dimensional (1D) energy band diagram along the channel direction and electron tunneling rate between the channel and drain. Figure 6: Gate-to-drain capacitance-voltage characteristics at V\({}_{\text{DS}}\) = 0.0 V with different \(\kappa\) values of spacer. Outer fringing gate-to-drain capacitance (C\({}_{\text{of}}\)) can be extracted at V\({}_{\text{GS}}\) = \(-\)1.0 V based on ideal junction. (\(\kappa=25\)), and the asymmetric high/low-\(\kappa\) spacer (\(\kappa=25\)/3.9). By using the symmetric high-\(\kappa\) spacer, switching characteristics get improved by 47% due to the on-current enhancement. Furthermore, the additional 10% improvement is achieved by the reduced gate-to-drain capacitance using the drain-side low-\(\kappa\) spacer. The proposed tunnel FET structure can be integrated as shown in Figure 8. First, oxide/poly-Si are sequentially deposited on silicon-on-insulator (SOI) wafer for the asymmetric spacer process (Figure 8a). After the drain-side is opened by photolithography and etching, the low-\(\kappa\) spacer is formed using deposition and etching. Then, self-aligned drain is defined using ion implantation process (Figure 8b). To passivate the drain side during subsequent processes, oxide is deposited on the whole region and the oxide planarization is performed by the chemical mechanical polishing (CMP) process. For the line tunneling region under a part of gate region, nitride spacer is formed on the oxide as a hard mask after the poly-Si is fully removed by using chemical etchant (Figure 8c). The oxide and partial SOI etching are carried out in sequence, and ion is implanted for the source region. On the partially etched SOI region, the selective epitaxy growth (SEG) layer, which can enhance tunneling current, can be deposited without doping (Figure 8d). After that, dopant activation is adapted and nitride spacer formation is applied again, which can determine the line tunneling area with self-alignment. Then, source-side high-\(\kappa\) spacer is formed to boost the tunneling current (Figure 8e), and oxide is deposited and planarized as interlayer dielectric (ILD). Finally, nitride and oxide are selectively etched out and replaced with ALD interfacial oxide, high-\(\kappa\) insulator, and metal gate (Figure 8f). Back-end-of-line (BEOL) flows are skipped because it is the same as the conventional complementary MOS (CMOS) process. Figure 7: (a) Gate-to-drain capacitance-voltage characteristics at V\({}_{\text{DS}}\) = 0.0 V with symmetric high-\(\kappa\) spacer (\(\kappa=25\)) and asymmetric high/low-\(\kappa\) spacer (\(\kappa=25\)/3.9). (b) Inverter response characteristics with symmetric low-\(\kappa\) spacer (blue), symmetric high-\(\kappa\) spacer (green), and asymmetric high/low-\(\kappa\) spacer (red).