# Updates on Impact Ionisation Triggering of Thyristors
## 3 Results  
### Gate-Boosting of SiC MOSFETs  
The results for a single IMBF170R450M1 SiC MOSFET (as per [22]) are depicted in Figure 9, illustrating three charging voltages in the range representing the later operation from 1.3 kV to 1.5 kV. The measurements were performed using a 50 \(\Omega\) load and with an identical driver to the one detailed in Section 2.2. As previously described in Section 2.1, and represented in Figure 3, presently each SiC MOSFET has its own microstrip with \(\approx\)15 \(\Omega\) impedance (FEMM calculation [36]) and \(\approx\)0.78 ns length which aims to mutually decouple the individual drains of the SiC MOSFET triggered by a common driver to cope with the spread of the switching times of each individual SiC MOSFET (Figure 3). Figure 8: The triggering pulse. **(a)** Schematic of the pulse booster for the Philips PM5786B pulse generator. **(b)** Output pulse on a 50 \(\Omega\) load, labeled _“Boosterout”_, with a charging voltage of 50 V. Maximum amplitude of 45 V, with a 10–90% rise time of 425 ps. Figure 9: Output voltages obtained on a single IMBF170R450M1 SiC MOSFET on a 50 \(\Omega\) load, at different charging voltages. \[v_{p}(outer)=\frac{v_{c}}{\sqrt{e_{r,eff}}} \tag{2}\] \[t_{d}(outer)=\frac{length}{v_{p}}\] \[\epsilon_{r,eff}=\frac{\epsilon_{r}+1}{2}+\frac{\epsilon_{r}-1}{2} \cdot(1+12\cdot\frac{h}{W})^{-\frac{1}{2}}-\frac{\epsilon_{r}-1}{4.6}\cdot \frac{t/h}{\sqrt{W/h}}\]  
The delay calculation on an outer stripline on a PCB is described in Equation (2) [37], where  
* \(v_{p}\) is the propagation speed, in this case on the outer layer of the PCB. * \(v_{c}\) is the speed of light in vacuum. * \(\epsilon_{r,eff}\) is effective dielectric constant for microstrips. * \(\epsilon_{r}\) is the dielectric constant of the PCB material. * \(h\) is the height of the substrate. * \(t\) and \(W\) are respectively the thickness and width of the microstrip. * \(t_{d}\) is the propagation delay due to the length of the microstrips in the outer layer of the PCB. The outcome of this step is depicted in Figure 10, capturing the performance characteristics of our pulse generator with six SiC MOSFET transistors operating simultaneously. This test was performed with a charging voltage of 1.7 kV on an attenuator's 50 \(\Omega\) load. The maximum amplitude of the output voltage is 3.2 kV and a 10-90% slew rate of 2 kV/ns. The impedance mismatch of the microstrips with respect to the 50 \(\Omega\) output load causes the reflection of the signal, almost doubling its voltage due to the superposition of the incident and reflected waves (reflection factor \(\Gamma=0.9\)). This is the reason why the output voltage is higher than the feeding voltage of the SiC MOSFETs. Given that the core intention of increasing the quantity of SiC MOSFETs primarily aims to amplify the output current of the pulse generator's driving phase, a focused experiment was undertaken specifically under the condition of a 4 \(\Omega\) load. This testing procedure was performed to comprehensively evaluate the performance enhancement attributed to  
Figure 10: Output voltage of the six parallel IMBF170R450M1 SiC MOSFETs on a 50 \(\Omega\) load (TP5, Figure 3), different charging voltages. At a 1.7 kV charging voltage, the maximum voltage amplitude is 3.2 kV and a 10–90% slew rate of 2 kV/ns. the increased number of SiC MOSFETs. Moreover, we have reduced the feeding voltage according to the recommended derating in irradiated facilities [38]. The obtained results, for a test at 1.7 kV charging voltage on a 4 \(\Omega\) resistive load with minimized inductive elements, graphically represented in Figure 11, show this. The output voltage on a less mismatched load (4 \(\Omega\) for six 15 \(\Omega\) microstripes in parallel) is reduced. However, the output curve exceeds the threshold of 220 A after calculation, delivering 400 A, making it 66 A per SiC MOSFET.