## 5 Influence of Date Synchronization Errors on Protection
### Analysis of ACDP Anti-Synchronization Error  
The time difference between the startup delay and the two-end protection determines the error of the FDSS. When a fault occurs outside the protected feeder section, the fault currents detected by the protective startup element at both ends of the protected section are equal in magnitude and opposite in direction. Even though there is an unavoidable delay in detecting faults, the startup delay of the two-end protection is the same. The time difference is zero, which is approximately synchronous. The fault currents flowing through the startup elements at both ends are independent when a fault occurs in the protected feeder section. There may be a large delay time difference in fault detection, especially when one end of the protected feeder section is connected to the GRID and the other to the IBDG.  
Taking the feeder \(MN\) section in Figure 14 as the protected section, the DG in Figure 14 is the IBDG. Assuming that a three-phase short-circuit fault with 2 \(\Omega\) fault resistance occurs on the feeder \(MN\) at 0.396 s and the sampling frequency is set to 10 kHz, the startup delay of protection is at least 0.1 ms. The waveforms of the phase current and mutation of the phase current detected by the two-end protection are shown in Figure 15.  
From (a) and (b) in Figure 15, after the fault occurs, the fault currents increase rapidly at R\({}_{1}\). The fault currents reach more than ten times the rated current, and the protective startup element based on the mutation of phase currents can detect the fault quickly, and the fault detection delay is very short. The fault currents increase slowly at R\({}_{2}\), which is less than two times the rated current and is not conducive to rapid fault detection. The protective startup element has a longer fault detection delay. This situation will cause a larger time difference in the fault detection delay at both ends of the protected section. They are assuming that the startup threshold of the fault detection algorithm based on the mutation of phase currents is set to 0.1 times the rated current.  
According to Figure 15c, the protection startup delay at R\({}_{1}\) is 0.1 ms. The C-phase protective device at R\({}_{2}\) is the first to start with a start delay of 3.8 ms, taking it as a synchronous reference. The time difference of the startup delay of the two-end protection is about 3.7 ms. The angle error caused by the time asynchrony is 66.6\({}^{\circ}\), which may lead to a decrease in sensitivity or even rejection of the TCDP.  
The proposed ACDP can effectively solve this problem. In the above fault scenario, the amplitude ratio of the PSCFCs on both sides is relatively large when the fault occurs inside the protected feeder section. At this time, the ACDP will compensate the phase of the measured current on the DG side so that the phase after compensation is equal to the phase of the measured current on the GRID side, and the ACDP can trip reliably and has  
Figure 14: Schematic of FDSS for active distribution network feeder protection.  
high sensitivity. The proposed protection scheme can adaptively compensate the measured current according to the amplitude ratio of the PSCFCs on both sides of the protected feeder and overcome the inherent defects of the FDSS.