## 1 Introduction  
In CPU and MCU applications, there is a consistent pursuit of high-frequency point-of-load (PoL) power supplies [1; 2; 3]. The switching frequency has been increasing in the past few decades [4]. This miniaturizes switches and inductors that primarily dominate the system size and weight. As a result, the integration level has evolved into a 3D stacked power supply (3D-SPS, discrete switch and discrete inductor), power supply in package (PSiP, integrated switch and discrete inductor), and power supply on chip (PwrSoC, integrated switch and integrated inductor) [5; 6; 7]. These integration levels differentiate in switching frequency and power rate and applications, as shown in Table 1. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Integration Level** & **3D-SPS** & **PSiP** & **PwrSoC** \\ \hline Switching Frequency & \textless{}10 MHz & \textless{}100 MHz & \textless{}100 MHz \\ Power Level & \textless{}100 W & \textless{}10 W & \textless{}2 W \\ Application & Primary PoL power supply & Compact primary & Secondary PoL power supply (on chip) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Switching Frequencies and Power Levels of Different Integration Levels. The 3D-SPS adopts discrete switches and inductors, which allows for high power conversion (up to 100 W) [8; 9; 10]. It carries out a 3D stacking structure on the PCB, and usually places magnetic components above or below the entire PCB board. With relative high inductance, the 3D-SPS approach can operate at a switching frequency below 10 MHz. The reduced switching frequency benefits the overall efficiency, since the switching loss is proportional to the switching frequency. The PSiP integrates all components in one package, which achieves single chip power conversion [7; 11]. Typically, it integrates power switches, drivers and control modules on a single die, whereas discrete inductors with low profile are packaged into the chip. Owing to the reduced inductance, the PSiP approach usually operates at a frequency above 10 MHz that leads to high switching loss and reduced efficiency. Due to limited power devices and heat dissipation, the power range is restricted to under 10 W.  
The PwrSoC integrates all components on a single die, which achieves the highest integration level [12; 13; 14]. The integrated on-chip power supply can be placed as near to the load as possible, which reduces the transmission loss in power lines [15]. However, with a low on-chip inductance, the switching frequency usually increases above 100 MHz to reduce ripples. As a result, power loss and heat dissipation are hard to optimize and that limits the power rate to below 2 W.  
In comparison to 3D-SPS, the PSiP saves the interconnecting area of the control chip, which drives chip and power transistors in 3D-SPS. In comparison to PwrSoC, the PSiP generally adopts the standard CMOS process and does not require the CMOS process with power inductors, which is more mature and compatible with technology. Therefore, the PSiP power supply is more widely applied in communication, server automatic systems and so on. For all integration levels, switching frequency and power levels are usually contradictory, and the major challenges toward high frequency are power losses of switches and inductors, as shown in Figure 1.  
Among the major challenges, the power switch dominates conduction and switching losses. Conduction and switching losses are primarily determined by the on-resistance value (\(R_{\text{om}}\)) and total gate charge value (\(Q_{G}\)), respectively. Figure-of-merits (FOM = \(R_{\text{om}}\times Q_{G}\)) of the Si vertical trench, Si lateral trench and GaN lateral trench are shown in Figure 2[16; 17; 18]. Due to the wider bandgap, higher electron mobility and electron velocity of GaN HEMT, its FOM is several times lower than that of Si MOSFET. These material characteristics result in lower power losses in GaN HEMT in high-frequency applications.