# Architecture and Process Integration Overview of 3D NAND Flash Technologies
## 2 Three-Dimensional NAND Flash Architectures  
The architectures of 3D NAND flash can be typically classified into gate-stacked structure [1; 2; 4; 5; 7; 8; 10; 11; 18; 19; 20; 21; 22; 23; 24] and channel-stacked structure [3; 6; 9; 12; 13; 14; 15; 16; 17], which are illustrated in Figure 2. In the gate-stacked structure, a channel is formed after stacking gate layers, and the current flows in the vertical direction. The cell structure is mostly based on gate-all-around (GAA), because a channel hole is filled with polycrystalline silicon (poly-Si) and a gate dielectric stack; inherently, this structure has several issues arising from the hole diameter. In contrast, in a conventional planar NAND array in a channel-stacked architecture, the current flows in the lateral direction. Although the scaling of a channel-stacked structure is limited by the ONO thickness in the bit line (BL) pitch, it is necessary to maintain the word line (WL) channel length to maintain an effective memory window. Moreover, it is difficult to connect the BLs with each layer, owing to their horizontal and parallel orientations. Currently, most commercialized 3D NAND architectures use the gate-stacked structure, owing to the abovementioned problems in the channel-stacked structure [25; 26]. Figure 1: Chronological development of 3D NAND flash technologies. Figure 3a,b compare the cross-sectional views of the BiCS and PBiCS flash structures, respectively, based on the gate-stacked structure and gate-first fabrication method. The BiCS flash structure was the first proposed 3D NAND architecture with a high density and cost per bit. In the BiCS structure, the vertically stacked gates are composed of a lower select gate (LSG), an upper select gate (USG), and control gates (CGs), as shown in Figure 3a. Because the channel pillars are not directly connected to the p-well in this structure, gate-induced drain lowering (GIDL) is used as the erase mechanism [1; 27; 28; 29; 30]. The PBiCS architecture improves the limitations of the BiCS flash, including the program/erase window, retention properties, high resistance of the source line (SL), and multibit operation. PBiCS flash has a U-shaped string structure, instead of a straight shape, and a pipe connection (PC) is formed at the bottom between two adjacent gates. This structural difference lowers the SL resistance because it can be accessed by the first and second metal layers, similar to a conventional planar NAND flash array. In terms of reliability, the PBiCS flash has better retention characteristics thanks to less damage to the trapping layer during the fabrication process, and the low resistance of metal wiring and steeply controlled diffusion profile at the SL allows the PBiCs to have better cut-off characteristics [2; 31; 32]. Figure 3: Cross-sectional views of **(a)** BiCS structure and **(b)** PBiCS structure. Figure 2: (**a**) Gate-stacked (vertical channel) and (**b**) channel-stacked (vertical gate) 3D NAND architectures [26], Copyright IEEE, 2014. Figure 4a shows a cross-sectional view of the TCAT architecture. The TCAT uses metal CGs, owing to the use of the gate-last fabrication method. Poly-Si channel holes are formed using the punched-through method like that in the BiCS structure; however, a notable difference is that the TCAT is connected to a p-type substrate, which allows the bulk erase operation. The two poly-Si channels in the structure share a common source line (CSL) formed by the WL cut. Figure 4b shows that the circuit diagram of the TCAT cell array is equivalent to that of a 90\({}^{\circ}\)-rotated planar flash array per string layer, and its bottom end is connected to the CSL. The ground selection line (GSL) and string selection line (SSL) transistors are at the top and bottom of a string, respectively, and flash cells are placed between them in series [4; 33]. Figure 5a shows the VRAT architecture containing a planarized-integration-on-the-same-plane (PIPE) structure for effective vertical interconnection [5].