# NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method
## 3 Methodology
### Minimum NBTI Vector Selection Considering Power Effect  
The SVA method can alleviate NBTI-induced delay degradation by increasing the supply voltage of the circuit. However, increasing \(V_{dd}\) will also result in the increase of dynamic power as well as static power. From Equation (9), we can find that there exists a quadratic relationship between dynamic power dissipation and supply voltage. In addition, the leakage power of the circuit will also increase exponentially with a supply voltage increase. Figure 4 illustrates the leakage power dissipation for an NAND2 gate under different combinations of input signal and supply voltage. Figure 4 shows that the leakage power of the NAND gate will increase greatly when the supply voltage increases. Moreover, the high supply voltage will also accelerate the aging process of a pMOS transistor in the logic circuit. Using the PTM 65 nm model, we have obtained the relationship between the \(V_{th}\) change for a pMOS transistor and supply voltage (\(V_{gs}=-V_{dd}\)) in ten years by HSPICE simulation. The result is shown in Figure 5.  
Figure 4: Leakage power change of an NAND gate under different supply voltage. Figure 5: Threshold voltage change for a positive-channel Metal Oxide Semiconductor (pMOS) transistor with different \(V_{gs}\). Figures 4 and 5 show that although increasing \(V_{dd}\) can compensate for the NBTI-induced delay degradation, a high \(V_{dd}\) will also result in high power dissipation and a fast aging process. In order to slow down the \(V_{dd}\) adjustment speed for SVA, the circuit designer should find the input vector in standby mode which could reduce the NBTI effect on the circuit. In addition, the leakage power which corresponds to that input vector should also be controlled to be as low as possible when the \(V_{dd}\) is in the initial state, so that the total power dissipation during the circuit's lifetime will be reduced. Therefore, the input vector should park the circuit in a state which corresponds to the minimum NBTI effect, as well as the minimum leakage power. However, the impacts of the input vector on delay degradation and leakage power are not in a same direction; the optimal input vector for minimizing the postaging delay may not be the best one to minimize the leakage power and vice versa. [PERSON] et al. proposed a probability-based (PB) method to find the best input vector that has the minimum NBTI effect and/or leakage for the circuit [33]. However, the PB method is based on heuristic and random simulations, so the computation cost is high and the result may not be the optimal. [PERSON] et al. presented an IVC method based on LP to co-optimize the NBTI and leakage in standby mode [27]. They have specified the constrain of one issue and managed to find the minimum value for another issue. Their method is effective when using IVC alone, however, since IVC is often combined with other methods to further reduce NBTI and leakage, the approach to choosing the optimal input vector for the subsequent method has not been discussed in detail. In this paper, we have proposed a simple form of co-optimization criterion function. First, we normalize the degradation and leakage to their potential minimum result obtained by ILP formulations for NBTI mitigation and leakage reduction only, respectively. Then, the sum of these two parts is minimized. It should be noted here that the ILP formulation for NBTI mitigation in Equation (16) is a path-based process, and the potential distribution range for postaging delay (the maximum propagation delay on all critical paths after aging) with different input vectors is smaller than the range for leakage power. So, if we build a co-optimization ILP formulation for postaging delay and leakage power minimization, the ILP solver will be biased to finding the input vector that can obtain the minimum leakage power, and the NBTI mitigation result will not be satisfactory.