## 1 Introduction  
The most critical requirements when designing an low-noise amplifier (LNA) include high power gain, low noise, and high reserve isolation, while these are high efficiency and high linearity when designing a PA. It has been shown that these requirements for both LNA and power amplifier (PA) are hardly to improve simultaneously. When designing LNA and PA, stacked circuit configurations are usually employed to enhance the circuit performance. Among the stacked configurations for design of the LNA and PA, cascode [1] and Darlington [2] configurations are two most important ones which can deliver various promising advantages over a single-stage configuration. The cascode configuration which offers high gain, high reverse isolation, and high frequency operation suits the design for both LNA [3; 4; 5; 6; 7; 8; 9; 10; 11] and PA [12; 13; 14; 15; 16; 17; 18; 19; 20; 21; 22; 23; 24; 25; 26; 27; 28; 29; 30; 31; 32; 33; 34; 35; 36; 37; 38; 39; 40; 41; 42; 43; 44  
noise and power gain are hardly to be improved at the same time. In [4; 6; 7] although the noise of the designed LNA can be reduced by employing an inductor which is added at the drain of the main transistor, the power gain of the resulting LNA is relatively low. On the other hand, [5] enhances the power gain of the LNA by using a forward bias and a capacitive divider but the noise figure is degraded accordingly. Additionally, it is obvious that the stacked configurations with more than three transistors are seldom developed for LNA design due to the significant increase of noise including shot noise and thermal noise caused by the added transistors. Besides LNA design, for the PA design two key parameters including efficiency and linearity are also hardly to be improved simultaneously. In [12; 13] the efficiency of PA is enhanced by using a sliding bias technique and a new circuit topology, respectively. However, linearity is not mentioned in these articles implying that it is not considered. Although linearity is improved for cascode CMOS PA in [14; 15] by employing an adaptive bias control and a pre-distorter, respectively, the efficiency of these PAs is poor. In addition to using the cascode and Darlington configurations for the design of the PA, recently stacked configurations have been also developed for this purpose [26; 27; 28]. In these articles, output power, power gain, and efficiency of the designed PAs are improved significantly at a very high operation frequency for both bipolar junction transistor (BJT)-type and field-effect transistor (FET)-type. Nevertheless, the two-tone linearity is still not considered for these stacked circuit configurations. From these above considerations, this study aims to propose a novel stacked circuit topology which can be employed to improve critical performance of both LNA and PA simultaneously. It can be seen that one of the most serious issues of the mentioned stacked configurations, including the cascode, Darlington, and other typical stacked topologies, is that they have a floating potential at the connection points between two transistors. This means it is impossible to make operation of each transistor independent. This results in a degradation of performance of these circuits since operation condition of each transistor becomes inter-dependent. To surmount this, we propose an independently biased 3-stack GaN high-electron-mobility transistor (HEMT) configuration which is realized by connecting the traditional cascode circuit with an additional common-gate (CG) transistor. Moreover, two additional bias terminals are inserted at the floating points between transistors. The idea of the proposed topology is to keep the promising advantages of the cascode topology while making an adaptive control of bias condition for the 3 transistors. Figure 1 illustrates how to realize such a circuit, along with other typical circuit configurations to be investigated.