# A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS
## 3 Transmitter System Architecture
### High Speed 4:1 MUX Circuit Design  
The key to the high-speed serial transmitter is the high-speed analog MUX, which provides an adequate timing margin to ensure the accuracy of the timing of the whole circuit. The traditional 1/2 speed architecture MUX provides only a timing margin of 1 UI, when the data rate is 112 Gb/s, 1 UI is about 8.9 ps. To ensure the accuracy of the overall circuit timing, the 4:1 MUX based on 1/4 speed architecture is designed, which can extend the timing from 1 UI to 3 UI [5; 22; 23; 24].  
The structure of the traditional pulse generating unit is shown in Figure 8a. Clock signals CK0 and CK90 control transistors M1, M4, and M3 to sample the signal. When the input data are at a high level, if CK0 is at a low level, M2 cuts off, and the output terminal charges the parasitic capacitor \(C_{X}\) at X. The level at X is determined by the previous data. When CK0 is at a high level, M2 turns on, and the input data are sampled. When CK90 is at a low level, the M3 is in a cut-off state, the Y point is suspended before CK90 high level arrives, and its level is determined by the last input data and remains in the original state. When CK90 becomes high, the voltage at X is sampled, the voltage at Y becomes low, and the Y point remains low until the low level of CK0 arrives. When CK0 becomes low, the Y node extracts current from the output terminal to charge the parasitic capacitor \(C_{Y}\) at Y, which leads to a charge-sharing effect and increases the longitudinal noise. At the same time, the charge sharing effect will slow down the rising edge of the output signal, which is presented on the eye diagram as the lateral jitter increases.  
Inspired by [7], our design adds the precharging auxiliary transistor PM7/PM8 on the traditional structure to eliminate the charge-sharing effect caused by parasitic capacitance. The specific circuit is shown in Figure 8b. Under the action of PM7/PM8, when CK0 and CK90 are at low level, PM7 and PM8 turn on, and the parasitic capacitance at X and Y is charged to high level. When CK0 changes from high level to low level, there is no  
Figure 8: Pulse generation unit: (**left**) conventional structure; (**right**) structure designed in this paper.  
Figure 7: Proposed precoding sequence diagram.  
need to extract current from the output end, thus eliminating the charge-sharing effect. The red curve in Figure 9 shows the waveform of the output signal simulation after adding PM7/PM8. From the simulation, it can be found that the pulse unit designed in this paper can significantly optimize the glitch and slow rising edge caused by the charge-sharing effect. The red-eye diagram in Figure 10 shows that intersymbol interference (ISI) decreases from 286 fs to 154 fs, and the glitch of 103 mV is eliminated. The quality of eye diagram has been improved obviously.  
Figure 11 shows the differential output eye diagram of the proposed 4:1 MUX. The simulation is the layout poststimulation, and the next-level load is set to 30 f in the simulation process. As can be seen from the simulation result, the output eye width of the structure is about 17.8 ps, the four eyes are uniform, and the maximum jitter is 285 fs.  
Figure 10: Simulation comparison of the output eye diagram of 4:1 MUX with and without PM7/PM8.  
Figure 9: Simulation waveforms of output nodes with and without PM7/PM8.