## 2 DUT and Modelling Methodologies  
The DUT is an on-wafer GaN HEMT with a gate length of 0.25 \(\upmu\)m (see Figure 1). This transistor is based on an interdigitated layout consisting of ten fingers, each with a length of 150 \(\upmu\)m, resulting in a total gate periphery of 1.5 mm. The fabrication process is the GH25-10 technology by United Monolithic Semiconductors (UMS) [61]. The DUT was realized using an AlGaN/GaN heterostructure grown on a SiC substrate with a field plate for power applications. This foundry process, entitling a power density of 4.5 W/mm with a typical \(f_{\mathrm{T}}\) of 25 GHz, was optimized for X-band (i.e., 8-12 GHz) high-power applications. The \(S\)-parameters were measured with a frequency range spanning from 200 MHz to 65 GHz with a 200 MHz step at different \(T_{a}\), namely 35 \({}^{\circ}\)C, 90 \({}^{\circ}\)C, 145 \({}^{\circ}\)C, and 200 \({}^{\circ}\)C. In order to move the reference planes from the instrument ports to the probe tips, an off-wafer calibration was performed with line-reflect-match standards on a commercial impedance standard substrate (i.e., a GGB Industries CS-5 ISS). The temperature-dependent experiments were carried out without any heat sink, and a software-controlled thermal chuck was used to set the die temperature. The comparative analysis was performed by considering the bias point given by \(V_{DS}\) = 30 V and \(V_{GS}\) = \(-\)3.1 V. This operating bias condition implies a dissipated power of 5.1 W when considering the ambient temperature of 35 \({}^{\circ}\)C.  
It should be underlined that the experiments were performed up to 65 GHz in the V band since the operating frequency of the GaN HEMT technology keeps extending further into the millimeter-wave region, driven by the ever-increasing market demand (e.g., 6G, inter-satellite links) for very high-frequency applications. The measurements were carried out on the GaN HEMT device operating without any heat sink at an elevated ambient temperature of 200 \({}^{\circ}\)C, albeit the recommended operating ratings indicate 200 \({}^{\circ}\)C as the  
Figure 1: Photograph of the tested GaN HEMT on silicon carbide substrate. peak junction temperature. This allowed for achieving experimental validation of the performance of the studied GaN technology, even beyond the constraints imposed by the device foundry. Furthermore, the Joule heat generated by the high dissipated power leads to a significant rise in the operating channel temperature inside the transistor. Figure 2 shows the small-signal equivalent-circuit model [32]. This model consists of a physically sound representation since each element of the equivalent circuit is aimed at modeling the electrical characteristics of a particular transistor region. As illustrated in Figure 2, the adopted circuit is composed of eight extrinsic elements, which are assumed to be biased independent and are determined from the \"cold\" pinch-off \(S\)-parameters (i.e., \(V_{DS}\) = 0 V and \(V_{GS}\) = \(-\)4 V), and eight intrinsic elements, which are bias dependent and are evaluated from the intrinsic admittance (\(Y\)-) parameters at the bias point of interest. At such a bias condition, the complexity of the equivalent circuit can be considerably reduced, thereby allowing extraction of the extrinsic equivalent-circuit elements. After applying the de-embedding of the eight extrinsic equivalent-circuit elements by using simple matrix manipulations, the intrinsic \(Y\)-parameters were calculated from the corresponding \(S\)-parameters by using the well-known conversion formulas, thereby allowing for the calculation of the intrinsic equivalent-circuit elements. MATLAB software environment is used for implementing the extraction of the equivalent-circuit elements from \(S\)-parameter measurements. Figure 3 illustrates the ANN temperature-dependent model adopted for modeling the tested GaN-based HEMT [48]. Each \(S\)-parameter was modeled with a separate neural model.