## 2 High Data Rate Modulator Design Description
### SCCC Encoding  
There is a need to protect the system with a flexible coding and modulation scheme in order to adapt to different channel conditions. This capability is provided by an SCCC encoder illustrated in Figure 3. The SCCC encoder is designed as a serial turbo code that generates at its output a constant number of 8100 modulation symbols regardless of the information block size \(K\) and current ACM format. The reason for this is to allow the efficient implementation of the encoding process and thus reduce its complexity. As in most systems, the encoder has a fixed rate and the different code rates are obtained by puncturing. CC1 is a rate 1/2 recursive, systematic convolutional code whose structure is shown in Figure 4. In this diagram, the subsequent variables appear:  
* \(u[n]\) denotes the n-th uncoded input bit;
* \(C_{1}[n]\) denotes the n-th coded systematic output bit;
* \(C_{2}[n]\) denotes the n-th coded parity output bit. Notation follows that square brackets in \(u[n]\) denote the n-th vector position or equivalently the n-th clock cycle at which the operation takes place in the logical circuit. Thus, in the first clock rising edge, the input \(u[1]\) yields two output bits: the systematic bit \(C_{1}[1]\) and a parity bit \(C_{2}[1]\), etc. In summary, the convolutional encoder processes the information block of length \(K\); when processing finishes, the switch moves into the upper position to terminate the trellis during an extra 2-bit period. Trellis termination is necessary to reset all registers to a known state, which is all-zeros by default. To transform the CC1 1/2 rate into 2/3 rate, a fixed-puncturing scheme is used. A CC1 puncturing scheme is only fed with parity output bits from CC1 to be decimated by a factor of 1/2. Meanwhile, all systematic output bits are transmitted bits. This is better illustrated in Figure 5.  
Figure 3: Serial turbo code architecture. As in all the turbo codes, the interleaver is a fundamental block to construct a random code in order to spread out burst errors created by temporal fluctuations in the channel. In this standard, the interleaver implements an ad hoc permutation that could be visualized as a memory block with its size denoted by interleaver length, \(I\). In particular, the memory block is split in such a way that it always keeps 120 rows and a variable width, such as \(I=120\times W\). Remember that \(W\) denotes a variable number of columns in the interleaver memory. The \(120\times W\) memory must be written row by row, from left to right. Once the interleaver memory is filled, its content must be scrambled. For this purpose, a column bit vector with dimensions of \(120\times 1\) is extracted from a general column denoted by variable \(c\). Thus, each column in the memory will be cyclically shifted by a different parameter denoted by the function \(\beta(c)\). Now, on a second step, each column \(c\) is consistently displaced to a new column position within the memory block--a position which is different for each column and specified by the function \(\alpha(c)\). When the mixing process finishes, the memory is read row by row, from left to right. The reader may notice that there are only 19 distinct values of \(I\), implying that only 19 unique possible permutation laws exist. The interleaver parameters change according to the ACM format: these are \(W\) (total number of columns); \(\alpha(c)\) (new column position for each column \(c\)); \(\beta(c)\) (cyclical shift for each column \(c\)). Their values are provided in tables located in [2] ANNEX B. In our implementation, several registers and shifts have been used to obtain an efficient yet reduced block. It is worth noting that this block will be made redundant in order to guarantee proper decoding, so any effort to reduce its complexity will be very useful in the future. CC2 systematic/parity output lines are fed to two different puncturing algorithms with the aim of enabling a set of variable coding rates.