# Flexible Wearable Heart Rate Monitoring System and Low-Power Design: A Review
## 5 Design of the Flexible Wearable Heart Rate Signals Computation Module
### Low-Power Hardware Design of the Computation Module for Flexible Wearable Heart Rate Signals  
From a hardware perspective, efficient microcontroller units (MCUs) are typically employed for heart rate computation and processing. However, to achieve low-power operation of the MCU, researchers need to meticulously design the MCU and circuit structure according to system requirements.  
[PERSON] et al. [45] developed the low-power BioAIP processor module for flexible wearable health monitoring through a reconfigurable design. Its system framework is shown in Figure 5a. The BioAIP combines a reconfigurable neural network engine (RNNE) with five parallel processing elements and optimized SRAM units to support multi-mode neural operations. The processor innovatively reuses RNNE resources for FIR filtering by storing coefficients in the existing weight/bias SRAM, reducing hardware overhead. The reconfigurable design curbs hardware overhead and leakage power. The pre-classification circuit reduces the activation frequency of the CNN, and the approximate data compression technology significantly reduces the energy consumption of memory access. Ultimately, the average power consumption of the entire system is approximately 46.8\(\upmu\)W, making it the lowest-power system of its kind.  
Figure 5: (**a**) Heart rate calculation processor based on the BioAIP structure. Reproduced with permission [45], copyright 2023, IEEE. (**b**) The electrocardiogram processor circuit, based on the ternary neural network. Reproduced with permission [67], copyright 2022, IEEE. (**c**) Schematic framework of the electrocardiogram computing and processing structure based on the deep neural network (DNN). Reproduced with permission [109], copyright 2022, IEEE.  
[PERSON] et al. [67] developed an ultra-low-power ECG processor module for flexible wearable systems based on ternary neural networks [65] by optimizing the processor design, and its system framework is shown in Figure 5b. In the optimization of the processor, the ternary weight adjustment of the ternary neural network (TNN) reduces storage and power consumption, the pipeline design improves efficiency, and the probability-estimated sigmoid function reduces on-chip consumption. Meanwhile, the TNN-DL hybrid micro-classifier cuts down the amount of computation and storage, and the optimized moving average (MVA) filtering simplifies operations. The processor adopts 65 nm CMOS technology and 2.5 V thick-gate transistors to minimize leakage current and static power consumption, requiring only 1 KB of on-chip memory and consuming as low as 746 nW.  
In summary, from the BioAIP proposed by [PERSON] et al. to the ternary neural network-based ECG processor by [PERSON] et al., we have witnessed multi-level hardware optimizations through circuit structures. These hardware design methods not only ensure the functionality of the heart rate calculation module but also effectively achieve the goal of low-power consumption through innovative approaches, such as constructing reconfigurable hardware designs, adopting pipeline designs, and implementing event-driven designs.