# An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks
## 3 Architecture of the E-ML-SpFi Core
### Key Technologies
#### 3.2.3 Fast Alignment  
Due to differences in physical mediums, transmission distances, and interference factors, data row misalignment appears. The misalignment may cause the failure of data consistency. Therefore, it is necessary to ensure receiving-row alignment. However, the SpaceFibre protocol [11] and existing designs [20; 21; 22; 23] only describe the alignment of FSM and do not illustrate the concrete architecture of the alignment process.  
To overcome the limitation, we propose the architecture of a fast alignment subsystem. The architecture, shown in Figure 7, includes an alignment FSM, condition module and \(L\) lane-locking modules. Each lane-locking module contains a locking unit, a detection unit, an examination unit, a pre-detection unit, and a three-position FIFO buffer. Each lane has a separate FIFO buffer to store the words from a data-receiving lane. In the following, we focus on the lane-locking module, which plays an important role in speeding up the alignment process.  
The pre-detection unit directly recognizes ACTIVE words in the incoming data traffic from a Lane layer, without having to extract ACTIVE words from the words read out of a FIFO buffer. At the same time, the unit extracts the information regarding active lanes at the far-end and transfers the information to the condition module. In the module, the information is utilized to form the signal flag_align and the signal flag_misalign, which are important conditions of the alignment FSM. If the value of the signal flag_misalign is 1, a misaligned condition occurs. By reducing the time used to generate conditions, the unit makes it possible to shorten the time required by alignment operations.  
The detection unit divides the words from an alignment FIFO buffer into three groups based on characteristic bits, so that the unit balances the resource utilization and speed of the fast alignment subsystem. The groups are data words, ALIGN control words, and other control words. PAD control words in this unit are considered data words. Characteristic  
Figure 6: Description of the modified word re-ordering block.  
bits are the minimum number of bits distinguishing different groups of words. For instance, data words have only two characteristic bits: bit 33 and bit 32. If a word is not recognized as an ALIGN control word and the alignment FSM is in the Not Ready state, the word shall be read out of the buffer. Once an ALIGN word is found, the detection unit asserts the signal getAlign to notify the examination unit.  
The examination unit checks the validity and correctness of an ALIGN control word at the same time, instead of a serial examination, for the fact that only the correct and valid ALIGN control words can be used for alignment. The results of parallel examination are sent to the condition module to generate the signal flag_align. By reducing the time spent on forming conditions, the unit makes the alignment process much faster.  
The locking unit allows one to lock a valid ALIGN word, correctly received, to form a valid data-receiving row by de-asserting the signal en_ed of the buffer when the Alignment FSM is in the Not Ready state. An ALIGN word constituting a valid data-receiving row is identified by the examination results from the examination unit. Associated with the buffer forbidden to read, the data-receiving lane is regarded as an aligned lane. After all lanes are aligned, each locking unit reads the ALIGN control word simultaneously.  
The basic idea of fast alignment consists of accelerating the generation of conditions. Both advance extractions and parallel examinations respect the idea. In addition, the usage of characteristic bits reaches a compromise between speed and resource consumption.