## 2 SPDT Switch Design
This leads to \(Z_{C1}\) and C\({}_{P}\), given by  
\[Z_{C1}=\frac{R_{0}}{\sin\theta_{1}} \tag{10}\]  
\[C_{P}=\frac{\cos\theta_{1}}{R_{0}\omega_{0}} \tag{11}\]  
In this work, \(\theta_{1}\) is equal to 45\({}^{\circ}\) (i.e., length of \(\lambda/8\)). From (10) and (11), the required \(Z_{C1}\) of the \(\lambda/8\)-TL is 70.7 \(\Omega\), and the required additional parallel capacitance, C\({}_{P}\), is 80.4 fF. Figure 4b shows the equivalent circuit of the SPDT switch in the RX mode. The control voltage V\({}_{\mathrm{sw1}}\) is equal to 1.8 V and V\({}_{\mathrm{sw2}}\) is equal to \(-1.8\) V. That is, transistors M\({}_{1}\) and M\({}_{2}\) are in the on-state and M\({}_{3}\) is in the off-state. Ideally, R\({}_{\mathrm{on1}}\) and R\({}_{\mathrm{on2}}\) are low-resistance (close to 0) and R\({}_{\mathrm{off3}}\) is high-resistance. The \(\pi\)-network consisting of parallel end-capacitance (C\({}_{L1}\) + C\({}_{\mathrm{dSI,on}}\) + C\({}_{\mathrm{gd1,on}}\)), series inductance (L\({}_{L1}\)), and parallel end-capacitance (C\({}_{L1}\) + C\({}_{\mathrm{ant}}\) + C\({}_{\mathrm{gd2,on}}\)) in the TX path is roughly equivalent to a \(\lambda/4\)-TL with characteristic impedance of 50 \(\Omega\). \(Z_{in}\) looking from the antenna node to the TX node is infinite (i.e., an open circuit) since a short-circuit-loaded \(\lambda/4\)-TL exhibits an infinite \(Z_{in}\). The parallel R\({}_{\mathrm{on2}}\) and L\({}_{1}\) in the RX path is low-impedance (close to  
0). This leads to decent input impedance matching at the RX and antenna nodes (i.e., a decent S\({}_{11}\) and S\({}_{22}\)), a low IL, and high antenna-to-TX isolation. In the TX path of the SPDT switch, the series \(\lambda\)/8-TL has a Z\({}_{\rm C}\) of 70.7 \(\Omega\). The \(\lambda\)/8-TL in conjunction with the end-capacitance contribution from the DTMOS-R transistors, M\({}_{1}\) and M\({}_{2}\), and capacitance, C\({}_{\rm ant}\), constitutes a \(\lambda\)/4-TL with a Z\({}_{\rm C}\) of 50 \(\Omega\) (according to Equations (10) and (11)). Figure 5a shows the simulated equivalent electrical length (\(\theta_{\rm eff}\)) versus the frequency characteristics of the TL in the TX path of SPDT SW1 according to Equation (3). The simulated ABCD parameters are converted from the simulated S-parameters. At 28 GHz, the corresponding \(\theta_{\rm eff}\) is 45.1\({}^{\rm o}\) (about \(\lambda\)/4), consistent with the theoretical analysis. Figure 5b shows the simulated Z\({}_{\rm C}\) versus the frequency characteristics of the TL in the TX path of SPDT SW1 according to Equation (2). At 28 GHz, the corresponding Z\({}_{\rm C}\) is 70.7 \(\Omega\); the same applies to the theoretical value. Figure 6a shows the simulated P\({}_{\rm 1 dB}\) of SPDT SW1 in the TX mode using the proposed DTMOS-R switching transistors and the traditional NMOS switching transistors. In the case of using DTMOS-R switching transistors, SPDT SW1 achieves a simulated IL of 0.52 dB (at a low P\({}_{\rm in}\) of \(-\)10 dBm) and P\({}_{\rm 1 dB}\) of 30.6 dBm. These results are better than those (simulated IL of 1.75 dB (at a low P\({}_{\rm in}\) of \(-\)10 dBm) and P\({}_{\rm 1 dB}\) of 11.6 dBm) using traditional NMOS switching transistors. Figure 6b shows the simulated P\({}_{\rm 1 dB}\) of SPDT SW1 in the RX mode using the proposed DTMOS-R switching transistors and the traditional NMOS switching transistors. In the case of using DTMOS-R switching transistors, SPDT SW1 achieves a simulated IL of 1.9 dB (at a low P\({}_{\rm in}\) of \(-\)10 dBm) and P\({}_{\rm 1 dB}\) of 25.4 dBm. These results are better than those (simulated IL of 3.8 dB (at a low P\({}_{\rm in}\) of \(-\)10 dBm) and P\({}_{\rm 1 dB}\) of 23.7 dBm) using traditional NMOS switching transistors. Overall, these results show that the proposed body-floating technique, i.e., the DTMOS-R switching transistors technique, in this work is effective for the IL and P\({}_{\rm 1 dB}\) enhancement of SPDT SW1 in both the TX and RX modes.