# Effective Implementation of Edge-Preserving Filtering on CPU Microarchitectures
## 4 CPU Microarchitectures and SIMD Instruction Sets  
[PERSON]'s law [44] states that the number of transistors on an integrated circuit will double every two years. In the early stages, CPU frequencies were increased by increasing the number of transistors. In recent years, owing to heat and power constraints, the use of a larger number of transistors has become difficult [45], such as chips with multiple cores, complicate cache memory and short vector units. The latest microarchitectures used in Intel CPUs are presented in Table 1. The table indicates that the number of cores is increasing, cache memory size is expanding and the SIMD instruction sets are growing. SIMD instructions simultaneously calculate multiple data. Hence, high-performance computing utilizes SIMD. Typical SIMD instructions include streaming SIMD extensions (SSE), advanced vector extensions (AVX)/AVX2 and AVX512 in order of the oldest to newest [46]. Moreover, fused multiply-add 3 (FMA3) [46] is a special instruction. FMA3 computes \(A\times B+C\) by one instruction. \begin{table}
\begin{tabular}{l l l l l l l} \hline \hline
**Generation** & **1 st** & **2 nd** & **3 rd** & **4 th** & **Sh** & **6 th** \\ \hline codename & Gulflowflow & Sandy Bridge & Ivy Bridge & Haswell & Broadwell & Skylake \\ model & 990X & 3970X & 4960X & 5960X & 6950X & 7980 XE \\ launch date & Q1’11 & Q4’12 & Q3’13 & Q3’14 & Q2’16 & Q3’17 \\ lithography & 32 nm & 32 nm & 22 nm & 22 nm & 14 nm & 14 nm \\ base frequency [GHz] & 3.46 & 3.50 & 3.60 & 3.00 & 3.00 & 2.60 \\ max turbo frequency [GHz] & 3.73 & 4.00 & 4.00 & 3.50 & 3.50 & 4.20 \\ number of cores & 6 & 6 & 6 & 8 & 10 & 18 \\ L1 cache (\(\times\)number of cores) & \multicolumn{4}{c}{64 KB (data cache 32 KB, instruction cache 32 KB)} \\ L2 cache (\(\times\)number of cores) & \multicolumn{4}{c}{256 KB} & \multicolumn{4}{c}{256 KB} & \multicolumn{4}{c}{256 KB} & \multicolumn{4}{c}{1 MB} \\ L3 cache & \multicolumn{4}{c}{12 MB} & \multicolumn{4}{c}{15 MB} & \multicolumn{4}{c}{20 MB} & \multicolumn{4}{c}{25 MB} \\ memory types & DDR3-1066 & DDR3-1600 & DDR3-1866 & DDR4-2133 & DDR4-2133 & DDR4-2666 \\ max number of memory channels & 3 & 4 & 4 & 4 & 4 & 4 \\ \hline \multirow{2}{*}{SIMD instruction sets} & SSE4.2 & SSE4.2 & SSE4.2 & SSE4.2 & AVX/AVX2 \\  & & AVX & AVX & AVX/AVX2 & AVX/AVX2 \\  & & & & FMA3 & FMA3 & FMA3 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: CPU microarchitectures of Intel Core series Extreme Editions. In each CPU generation, the Extreme Edition versions offer the highest performance on the consumer level. The specifics of these are as follows: 990X ([[https://ark.intel.com/products/52585/](https://ark.intel.com/products/52585/)]([https://ark.intel.com/products/52585/](https://ark.intel.com/products/52585/))); 3970X ([[https://ark.intel.com/products/70845/](https://ark.intel.com/products/70845/)]([https://ark.intel.com/products/70845/](https://ark.intel.com/products/70845/))); 4960X ([[https://ark.intel.com/products/77779/](https://ark.intel.com/products/77779/)]([https://ark.intel.com/products/77779/](https://ark.intel.com/products/77779/))); 5960X ([[https://ark.intel.com/products/82930/](https://ark.intel.com/products/82930/)]([https://ark.intel.com/products/82930/](https://ark.intel.com/products/82930/))); 6950X ([[https://ark.intel.com/products/94456/](https://ark.intel.com/products/94456/)]([https://ark.intel.com/products/94456/](https://ark.intel.com/products/94456/))); 7980 XE ([[https://ark.intel.com/products/126699/](https://ark.intel.com/products/126699/)]([https://ark.intel.com/products/126699/](https://ark.intel.com/products/126699/))). There are three notable changes in SIMD. First, the vector length is growing. For example, the lengths of SSE, AVX/AVX2 and AVX512 are 128 bits (4 float elements), 256 bits (8 float elements) and 512 bits (16 float elements), respectively. Second, several instructions have been added, notably, _gather_ and _scatter_ instructions [42]. These instructions load/store data of discontinuous positions in memory.