# A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits
## 6 Test Pattern Generations for Delay Faults
### Faster-than-at-Speed-Based ATPG for SDD and HDD  
The small delays due to the defect can exist on short paths and will escape the at-speed testing. This delay will not fail the circuit during at-speed functional operation but can grow over time due to aging effects, causing reliability problems. Various methods are suggested in the literature to ensure IC reliability. Burn-in [38] is one such method, where the IC is subjected to increased temperature than the nominal conditions. This method is expensive, time-consuming, and may sometimes damage the chip. So, a cost-effective method for detecting the reliability defects was proposed, say FAST [23,39]. Testing the chips at a test frequency higher than the functional at-speed frequency is called FAST. Despite the advantage of N-detect TDF ATPG and the pattern selection methods for generating a reduced pattern set, the LOC and LOS-based methods cannot produce certain functional test patterns that can propagate the fault effect through the longest path possible. Thus, leading to test escapes of SDDs. For such cases, the FAST method is suggested. The selection of the proper FAST clock and pattern combination is a major challenge in this type of testing. Various methods generate optimized test patterns and select the appropriate FAST clock for capturing the small delay faults. They include (i) testing the small delays due to the faults at predefined frequencies; and (ii) based on the delay location caused by the fault, the FAST frequencies are selected. The methods available in the literature are discussed here. Figure 7: Example of path weight assignment [21] for the pdf of different path delay. In [23], the transition delay-based patterns having almost the same pattern delay (maximum path delay for each pattern) distribution are grouped, and a suitable predefined FAST clock frequency is selected for the particular group. Still, there will be a lot of SDD test escapes as the path delay of specific patterns in the group can be smaller than that particular group's FAST test clock period. In [40] the transition pattern set is copied repeatedly for each clock frequency, and the endpoints that do not meet the required path delay and have hazards in the output are masked. But this increases the number of pattern counts, and more FAST clocks are required to have a better SDD coverage. Single path sensitization PDF model is proposed in [41] to reduce the masking of paths with path delay lengths longer than test clock frequency during FAST. This increases the number of patterns because of single path sensitization and also, sometimes it may lead to undertesting. Using a predefined set of frequencies will not guarantee the detection of all SDDs and HDDs as it may miss specific delay effects that can only be detected at a particular clock period. In [42] a hybrid approach is used to detect the small delay faults that occur in shorter paths using predefined and optimal frequencies. The fault effect will be visible only at a particular observation time. The optimal frequencies are selected based on this observation time. Especially for in-field testing, the resources will be limited, so the number of different clock frequencies should not be more. Thus, a hypergraph algorithm is used to produce a set of optimized frequencies through fault simulation with a fixed fault size to detect the SDD. But the problem is that in real scenarios, defects cannot be of fixed size, and simulating all the fault sizes and finding the observation time based on the delay location is difficult and time-consuming, especially for larger industrial designs. Another method of \(WeSPer\) factor guides FAST clock test generation in [43]. Here the method uses a predefined frequency and pattern set and tries to generate the most optimized test option (FAST clock, test pattern, masking vector) by selecting the test option that maximizes the \(WeSPer\) factor.