# Adaptive Coherent Receiver Settings for Optimum Channel Spacing in Gridless Optical Networks
## 2 Clock Recovery in Coherent Optical Receivers
### PLL Basics  
A detailed look at PLL, as shown in [23; 24], allows us to elaborate on the limitations of the existing clock recovery architectures in optical modems. Both control theory and signal processing are required tools to study the stability of PLLs. The basic structure of PLL is depicted in Figure 3. A typical PLL consists of a PD, a low-pass loop filter (LPF) and a VCO in the feed-forward path and a frequency divider (N\({}_{\text{PLL}}\)) in the feedback path. The need for divider is that reference clocks, crystal-based ones, are stable and have low jitter at low frequencies. Therefore, we adjust the input voltage of the VCO as part of the feedback loop.  
Figure 3: Block diagram representation of a PLL (**left**) and third order PLL loop filter governing representing F(s) (**right**) ([25]).  
Under steady-state conditions, the PD creates an output that is proportional to the phase/frequency difference of its two inputs with a gain of _Kp_:  
\[V_{e}(s)=\ K_{p}\left(\theta_{i}(s)-\ \theta_{f}(s)\right) \tag{3}\]  
The loop filter (LPF) is assumed to be a low-pass filter with general transfer function _F(s)_. The order of the filter depends on the configuration of the resistors (R) and capacitors (C). The higher the order of the PLL, the more rejection of high-frequency components is achieved in the forward path. If \(n\) is the number of cascaded resistor-capacitor (RC) stages, the resulting frequency domain filter response, have a roll-off of (_n_ x -20 dB)/decade. Figure 4 shows our simulation of the frequency response for a 2 nd, 3 rd, and 6 th order PLL implementation. Filters of high orders achieve more rejection of noise and spurs from both VCO and reference.  
The VCO is responsible for generating the high-frequency clock used to drive the ADC. It converts a voltage to frequency with a gain of \(K_{VCO}\) and frequency offset \(w_{FR}\). Since the input and output variables of a PLL are best described in terms of instantaneous phase, the VCO operation can be described in the Laplace domain as:  
\[\theta_{o}=\frac{K_{VCO}}{s}\ V_{e}(s)+\ \frac{w_{FR}}{s^{2}} \tag{4}\]  
Finally, the divider in the feedback path NPLL reduces the frequency or phase of the signal feedback to the PD:  
\[\theta_{f}(s)=\ \frac{\theta_{o}(s)}{N_{PLL}} \tag{5}\]  
When deriving the closed-loop form reflecting input-output behavior of the PLL, we get an aggregation of a low-pass filter that governs the reference to output response and high-pass filter that governs the noise from the VCO viewed from the output. Presented in Equation (6) below:  
\[\frac{\theta_{o}(s)}{\theta_{i}(s)}=\left\{\frac{N_{PLL}W_{FR}}{s\left(N_{PLL }s+\ K_{VCO}K_{p}F(s)\right)}+\ \frac{N_{PLL}K_{VCO}K_{p}F(s)}{N_{PLL}s^{2}+\ K_{VCO}K_{p}F(s)\ s}\right\} \tag{6}\]  
Typical reference clocks have their phase noise at low frequencies; Hence decreasing the forward-path loop bandwidth does not add much noise from the reference. However, decreasing  
Figure 4: Frequency response of three PLLs with different filter order and same 3-dB bandwidth.  
bandwidth of the low-pass means increasing bandwidth of the complementary high-pass, shown in our simulation presented in Figure 5, and causing high-frequency VCO noise through unfiltered. This is a key ingredient in the optimization process discussed in the next section.