# Harnessing FPGA Technology for Energy-Efficient Wearable Medical Devices
## 5 Power Optimization Strategies
### Designing an Energy-Conscious Algorithm
#### 5.1.1 Simplification of Arithmetic Operations  
Arithmetic operations, such as multiplication and division, are resource-intensive and consume significant FPGA logic and power. These operations can often be replaced by simpler shift and add operations. Similarly, logic-wise multiplication can be substituted with XNOR operations [70; 71]. These simplifications reduce computational complexity and resource consumption, leading to lower power usage.  
For example, the authors of [72] binarized the weights, allowing logic-wise multiplication operations using XNOR instead of the power-consuming MAC operation. This resulted in simplified computations, thereby reducing resources and dynamic power consumption, but at the cost of a slight reduction in accuracy due to the simplification of arithmetic operations. Similarly, in [67], the authors used a binary hyperbolic tangent as an activation function to allow a logic-wise multiplication operation (XNOR) in their bCNN-based ECG classifier, resulting in significant resource and power consumption at the cost of a small degradation in accuracy. Likewise, in [69], the authors replaced the multiply-accumulate operation with bitwise XNOR operation, exploiting the fact that weights and feature maps are constrained to negative or positive one and thereby enabling one-bit operations. This significantly reduces memory access and computational resources, leading to a reduction in power consumption with acceptable accuracy.  
Another approach is to replace multiply-accumulate (MAC) operations with shift-accumulate (SAC) operations [73; 74; 75]. Using shift-add operations instead of multipliers can reduce hardware complexity and power consumption because shift-and-add operations are generally simpler and require fewer resources than multiplication, though this may affect the overall speed. These simplifications significantly reduce the complexity of computations and the corresponding hardware, thereby lowering power consumption. For instance, the authors of [66] replaced the DSP block with shifters by choosing filter coefficients with a power of two, resulting in significant area and power reduction without compromising the functionality. Filters with coefficients of the form \(2^{n}\) can be implemented using addition and shift operations instead of multipliers, resulting in reduced resource and power consumption [76].  
Similarly, the authors of [77] converted the MAC operations with SAC. According to the authors, the dynamic power consumption of a 12 bit multiplier is approximately 13\(\times\) times higher than that of the 15 bit shifter. Likewise, the authors of [78] replaced the multiplier with shift-and-add operations in their lifting-based discrete wavelet transform (LDWT) PVC recognition system. In another approach, an integer Haar wavelet transform (IHT) was used by the author of [79] for denoising the ECG signal, where division by a \"2\" operation was also implemented using a simple shift operation. This resulted in lower complexity and thereby lower power consumption.