## 4 Extraction of the Word-Based SISO Semisystolic Processor
### Word-Based SISO Projection Function
These signals are used to calculate the words of the final products \(Q\) and \(R\). The partial signals \(x_{j}^{d}\), \(y_{j-1}^{c}\), \(p_{j}^{d}\), and \(s_{j-1}^{c}\) resulting from the semisystolic array block are provided at the proper time to the corresponding inputs of the postprocessing array using the tristate buffers \(\text{T}_{x}\), \(\text{T}_{y}\), \(\text{T}_{p}\), and \(\text{T}_{s}\), as shown in Figures 8 and 9. For an odd field size \(n\), the value of \(d\) will be less than the value of \(c\) (\(d\
eq c\)), and in this case, the partial signals of \(y_{j-1}^{c}\), \(s_{j-1}^{c}\) should be provided one clock cycle earlier than the signals \(x_{j}^{d}\), \(p_{j}^{d}\). Figure 5: Word-based SISO semisystolic processor. Figure 6: Logic details of the dark orange PEI. \[o = i\bmod k\]0 Logic details of the light orange PE. The following provides the operation summary of the developed word-based SISO semisystolic array processor for different parameters of \(n\) and \(k\) as follows:  
1. Through clock periods \(1<t\leq\left\lceil\frac{n}{k}\right\rceil\), the control signals of MUXes \(M_{e}\), \(M_{g^{\prime}}\), and \(M_{g}\), presented in Figure 5, are set to one to serially transfer the words of input operands \(E\),  
\[o = i\bmod k\]1 Logic details of the dark blue PE. \[o = i\bmod k\]2 Logic details of the light blue PE. \(G\), and \(G^{\prime}\) to the corresponding inputs of the semisystolic array block (one word at each clock period) starting from the most significant words. Through the first clock period, the FIFO buffers of \(X\), \(Y\), \(P\), and \(S\) are cleared to maintain zero initial values as denoted in Algorithm 1. As we notice from Figure 5, the FIFOs of \(X\), \(Y\), \(P\), and \(S\) have a width size of \(k\) bits and a depth size of \(W-1\), where \(W=\left\lceil\frac{n}{k}\right\rceil\). The depth size of these buffers guarantees that the variables \(X\), \(Y\), \(P\), and \(S\) have zero values through the intended clock periods, \(1<t\leq\left\lceil\frac{n}{k}\right\rceil\);
2. At clock periods \(t=z\lceil\frac{n}{k}\rceil+1\), \(0\leq z<\left\lceil\frac{n}{k}\right\rceil\), the control signal \(u\) in all dark orange PEs of the semisystolic array shown in Figure 3 should be assigned a zero value (\(u=0\)) to enable the tristate buffers designated in Figure 6 to serially transfer the updated words of \(E_{n-1}^{i-1}\) and \(E_{n-2}^{i-1}\) to the remaining light orange PEs in the array (one word at each clock period). Furthermore, through these clock periods, the words of \(E_{2i-2}\), \(E_{2i-1}\), \(E_{2i-2}\), and \(F_{2i-1}\) should be serially transferred to all the PEs in the semisystolic array. The words of \(E_{2i-2}\), \(E_{2i-1}\), \(F_{2i-2}\), and \(F_{2i-1}\) are transferred to the corresponding inputs in the semisystolic array block through the registers allocated at the left side of Figure 5;
3. At clock periods \(t=z\lceil\frac{n}{k}\rceil\), \(1\leq z<\left\lceil\frac{n}{k}\right\rceil\), the control signal \(v\), shown in Figure 3, should be forced to have a zero value (\(v=0\)) to force the least significant \(\zeta\) bits of \(E\), through the AND gates, to have zero values as indicated at the rightmost edge of the DG shown in \[o = i\bmod k\]3 Notice that in our case example of \(n=7\) and \(k=3\), \(\zeta\) should equal two;
4. At clock periods \(t>\left\lceil\frac{n}{k}\right\rceil\), the control signals of MUXes \(M_{e}\), \(M_{g^{\prime}}\), and \(M_{g}\) are assigned zero values to transfer the following words to the corresponding inputs of the semisystolic array block: updated \(E\) words saved in FIFO-E, \(G^{\prime}\) words saved in FIFO-G', and \(G\) words saved in FIFO-G. All of these words are transferred to the semisystolic array in a word-serial fashion (i.e., one word at each clock period).