## 4 Transistor Feedback through the Source Inductance  
With the aim of investigating the effects of the source inductance, the analyzed circuit is shown in Figure 6a, where the topology previously shown in Figure 4a is complemented with the source inductance \(L_{\rm s}\), and the corresponding switching waveforms are shown in Figure 6b. In \(\rm t=t_{0}\), the rising edge of \(v_{\rm DRV}\) triggers the \(T_{\rm HS}\) turn-on, so the voltage \(v_{\rm GS}\) starts to increase up to reach its threshold value \(V_{\rm th}\) at \(\rm t=t_{1}\). The input driver loop comprises a series RLC circuit, i.e., the \(L_{\rm s}\) inductance in series with the \(T_{\rm HS}\) input capacitance \(C_{\rm iss}=C_{\rm gs}+C_{\rm gd}\). At \(\rm t=t_{1}\), \(T_{\rm HS}\) enters its saturation region, thus \(i_{\rm sw}\) increases, as well as the voltage across \(L_{\rm d}\) (\(v_{\rm Ld}\)), across \(L_{\rm s}\) (\(v_{\rm Ls}\)), and the voltage \(v_{\rm DS}\) eventually decreases. Under the hypothesis that the \(v_{\rm GS}\) voltage is approximately constant due to the [PERSON]'s effect, the KVL in the input driver loop results in  
\[v_{\rm DRV}-v_{\rm GS}=v_{\rm LS}+R_{\rm g}i_{\rm G}\approx const, \tag{5}\]  
meaning that, if \(v_{\rm LS}\) increases, then \(R_{\rm g}i_{\rm G}\) decreases. The gate current decreases up to reach \(i_{\rm G}=0\) in \(\rm t=t_{2}\). It is worth noticing that, even though the gate current is negative, \(T_{\rm HS}\) is still in saturation provided that \(v_{\rm GS}>V_{\rm th}\). This point (\(\rm t=t_{2}\)) also corresponds to a maximum on \(v_{\rm LS}\) and \(di_{\rm sw}/dt\). From \(\rm t=t_{3}\), \(i_{\rm G}\) comes negative, thus \(dv_{\rm DS}/dt>0\). The drain current, however, will still increase up to reach its peak value, in \(t_{3}\). This corresponds to \(d^{2}v_{\rm DS}/dt^{2}=d^{2}v_{\rm sw}/dt^{2}=0\), i.e., a concavity change. From \(t_{3}\) on, the \(i_{\rm G}\) current is again positive, thus \(dv_{\rm DS}/dt<0\). The transistor will exit the Miller's plateau and enter the triode region, eventually.  
Depending on the value of \(L_{\rm s}\), \(R_{\rm g}\), \(L_{\rm d}\) and of the \(T_{\rm HS}\) and \(T_{\rm LS}\) parasitics, the negative feedback introduced by \(L_{\rm s}\) can slow down the transistor and suppress the oscillations. Even though the power dissipation of the high-side transistor increases when an extra source inductance is inserted [23], it prevents the oscillation from taking place.  
The exploitation of the source inductance to mitigate the turn-on oscillations, however, comes at the cost of worsening the switching performance during the turn-off, as highlighted in [24, 25, 26]. Indeed, the unavoidable presence of the source inductance and of the gate-drain capacitance is the root cause of a cross-talk phenomenon between the input loop (gate driver) and the output loop (power loop). The most dangerous side effect of this crosstalk is the self turn-on at the turn-off transient [27], which may result in self-sustained undampened oscillations [28]. The self turn-on phenomenon takes place  
Figure 6: **(a) Simplified model of a single leg for the analysis of the turn-on when the high-side transistor is driven by a convention gate driver and the source inductance is considered, and (b) the corresponding switching waveforms.**when the transistor is already off, i.e., \(v_{\text{GS}}<V_{\text{th}}\), but the current flowing in the drain-gate parasitic capacitance (\(C_{\text{gd}}\)) drives the gate voltage above the threshold [27]. However, such a phenomenon can be avoided by a proper choice of the gate driver resistance, as discussed in what follows.