## 4 Device Optimization  
In Section 3, we confirmed that the hump behavior in SCNW TFET is mainly attributed to the two BTBT paths (i.e., vertical and lateral) which have different \(V_{\text{ON}}\) and BTBT rates. Therefore, a design optimization is needed to achieve maximum electrical performance (low \(S\) and high \(I_{\text{ON}}\)). In this Section, the influences of \(L_{\text{TUN}}\) and \(T_{\text{TUN}}\) on SCNW TFET's electrical characteristic are investigated since the vertical-BTBT mostly occurs in the tunnel region. Figure 6a shows transfer curves with 50, 80, 100 nm of \(L_{\text{TUN}}\) and 2, 3, 4, 5 nm of \(T_{\text{TUN}}\). As shown in the inset of Figure 6a, the \(V_{\text{HUHMP}}\) is clearly decreased as \(T_{\text{TUN}}\) increases. The results can be quantitatively analyzed and calculated by voltage division model in which the gate oxide and depletion capacitors (\(C_{\text{ox}}\) and \(C_{\text{Si}}\)) are connected in series (Figure 6b) [13]. Since \(T_{\text{TUN}}\) is ultra-thin (\(<10\) nm) and source is highly doped, it can be assumed that the tunnel region is entirely depleted; the \(C_{\text{Si}}\) is constant. Therefore, surface potential (\(\psi_{S}\)) is expressed as (2), where \(\varepsilon_{\text{Si}}\) and \(\varepsilon_{\text{ox}}\) are permittivity of Si and SiO\({}_{2}\), respectively. If \(T_{\text{TUN}}\) increases, \(\psi_{S}\) becomes large and vertical-BTBT occurs with the smaller \(V_{\text{GS}}\) which results in the decrease of \(V_{\text{HUHMP}}\) as discussed in Figure 6a. \[\psi_{\text{s}}=\frac{C_{\text{ox}}}{C_{\text{ox}}+C_{\text{Si}}}V_{\text{GS} }=\frac{\frac{T_{\text{ON}}}{T_{\text{ON}}}}{\frac{T_{\text{ON}}}{T_{\text{ max}}}+\frac{S_{\text{Si}}}{T_{\text{min}}}}V_{\text{GS}}\psi_{\text{s}}=V_{ \text{GS}}-\frac{3T_{\text{max}}}{T_{\text{min}}+3T_{\text{max}}}V_{\text{GS }},\text{ where }\varepsilon_{\text{Si}}\approx 3\varepsilon_{\text{ox}} \tag{2}\]  
Figure 7 shows transfer curves with various \(T_{\text{TUN}}\) from 2 to 8 nm, where \(L_{\text{TUN}}\) and \(V_{\text{DS}}\) are fixed at 20 nm and 0.5 V, respectively. According to the results, the \(I_{\text{D}}\) is clearly increased, and \(S\) is deteriorated as \(T_{\text{TUN}}\) becomes thinner. It is attributed to the enhanced vertical-BTBT rate with the smaller \(T_{\text{TUN}}\), because the tunnel resistance (i.e., tunnel barrier width) of SCNW TFET is geometrically determined by the \(T_{\text{TUN}}\)[39]. However, an aggressive scaling-down of \(T_{\text{TUN}}\) is contradictory to the process capability and the \(S\) which gets worse as the \(T_{\text{TUN}}\) decreases due to an increased \(V_{\text{HUHMP}}\). Consequently, an optimization of \(T_{\text{TUN}}\) can be a strategy for SCNW TFET to compensate its weakness (i.e., low \(I_{\text{ON}}\) and hump effect) and/or enhance its strength (i.e., under 60 mV/dec-\(S\) at room temperature). Finally, \(T_{\text{TUN}}\) is optimized as 4 nm. Then, the performances of planar TFET, SCNW TFETs and nanowire TFET are compared. Figure 8a shows the average subthreshold swing (\(S_{\text{avg}}\)) and point-to-point minimum subthreshold swing (\(S_{\text{min}}\)) of SCNW, nanowire and planar TFETs. The \(S_{\text{avg}}\) is defined as the average inverse slope of the transfer curve while \(I_{\text{D}}\) changes from \(10^{-12}\)\(\mu\)A/ \(\mu\)m to \(10^{-2}\)\(\mu\)A/ \(\mu\)m. For \(S_{\text{min}}\), the planar TFET, SCNW TFETs and nanowire TFET show similar values, all of which are less than 60 mV/dec. For \(S_{\text{avg}}\), SCNW TFET shows the lowest value. Figure 8b shows transfer curve of planar TFET, SCNW TFETs and nanowire TFET. For fair comparison, the \(I_{\text{OFF}}\) of these devices should be adjusted to the same level. The above adjustment is achieved by changing the work function and channel doping concentration. The adjusted \(I_{\text{OFF}}\) is \(10^{-7}\)\(\mu\)A/\(\mu\)m, referring to actual \(I_{\text{OFF}}\) in nanowire TFET [40].