## 4 Applications of FBFET
### Memory Cells  
The traditional 1T-1C DRAM has allowed the reduction of device sizes to improve the performance and density of cells. The conventional 6-transistor static random-access memory (6T-SRAM) exhibits high performance with low density [83; 84; 85; 86; 87; 88; 89], while DRAM exhibits relatively low performance but provides high density [90]. FBFETs can be used for next-generation DRAM and SRAM to overcome the technical limits of each. A large amount of research has been carried out to demonstrate the competitive characteristics in the field of DRAM, and the capacitor-less DRAM (1T-DRAM), which was first proposed twenty years ago, has received much attention [33]. 1T-DRAM utilizes side effects such as hysteresis, which some studies consider harmful and have tried to remove. When the parasitic carriers that generally cause hysteresis are stored in the body and increase the potential, the threshold voltage is lowered and high current can be achieved--this is defined as the '1' state. The '0' state features a lower current achieved by removing the carriers from the body [34; 35; 36; 43; 44; 45; 46; 47; 48; 88]. The 1T-DRAM has remained stalled in its current state as a potential next-generation candidate. While the 1T-DRAM has great structural advantages, it is necessary to demonstrate its ability to be fully commercialized in order for it to replace the conventional DRAM. Unfortunately, fatal drawbacks such as low reliability, high power consumption, or incompatibility with standard process technologies have emerged for various proposed models [37; 38; 39; 40; 41; 42]. Most importantly, the traditional DRAM continues to succeed in the development process without serious problems. At present, the conventional 1T-1C DRAM memory cell is reaching its scaling limit. One of its biggest problems is that scaling the cell capacitor can no longer keep up with the transistor [41; 42]. To ensure correct memory cell operation, a minimum space is required to store a certain amount of charge. The conventional methods  
Figure 8: Illustration of an FBFET-based inverter circuit. for improving performance through scaling are thus now stagnating in the 1T-1C DRAM device architecture. In addition to devising various technologies to overcome these difficulties, it seems reasonable to consider a new DRAM structure. One promising candidate is memory cell types that store charges in the body of the transistor, thus modulating the threshold voltage and exhibiting distinct drain currents without the capacitor facing scale limitations. The body of the memory cell is then fully depleted of the accumulated carriers to obtain two distinct current levels corresponding to the complementary logic states. There are some device structures, such as MSDRAM [34] and A2 RAM [37; 38], that can meet most of the DRAM requirements: the ability to work under low voltage, low power consumption, long retention times, and scalability. Among 1T-DRAM cell candidates, the devices containing FBFETs exhibit excellent possibilities with a steep subthreshold swing owing to their positive feedback mechanism. These devices stand out for their performance and feasible integration with the standard fabrication process for ultra-thin body structures (see Figure 9). There are reasons why FBFET devices should command particular attention. First, the MSDRAM uses a mechanism based on the meta-stable dip hysteresis effect, which requires hysteresis [34]. However, the super-coupling effect, which occurs below 10 nm, makes it difficult for the electrons and hole channels to coexist [35; 36]. Secondly, A2 RAM considers the high state as that when sufficient holes are stored in the body to create a current bridge from the source to the drain [37]. The other state is defined by the disconnected bridge in the fully depleted state [38]. However, the fabrication and variability of bridges in films is limited when the overall thickness is less than 10 nm. The operation mechanism of the FBFET as 1T-DRAM is as follows.