# Reducing LUT Count for FPGA-Based Mealy FSMs
## 6 Experimental Results
To clarify this dependence, we have created Table 7 (experimental results for category 0), Table 8 (experimental results for category 1) and Table 9 (experimental results for categories 2-94). Furthermore, we present these results by graphs on Figures 9-11, respectively. As follows from Table 7 and Figure 9, the proposed method produces FSM circuits having more LUTs than it is for other investigated methods. Our method has the following loss: (1) 30.34% regarding Auto; (2) 3.37% regarding One-hot; (3) 31.46% regarding JEDI-based FSMs and (4) 28.09% regarding DEMAIN-based FSMs. So, there is no sense in using our approach for designing trivial FSMs. However, it gives an economy in LUTs starting from simple FSMs (category 1). As follows from Table 8 and Figure 10, the \(U_{4}\)--based FSMs of category 1 required fewer LUTs than it is for other methods. There is the following economy: (1) 23.03% regarding Auto; (2) 65.52% regarding One-hot; (3) 3.47% regarding JEDI-based FSMs and (4) 12.62% regarding DEMAIN-based FSMs. So, for the category 1, our approach produces FSM circuits slightly better than JEDI-based FSMs. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Benchmark** & **Auto** & **One-Hot** & **JEDI** & **DEMAIN** & **Our Approach** & **Category** \\ \hline bbtas & 5 & 5 & 5 & 5 & 8 & 0 \\ dk17 & 5 & 12 & 5 & 6 & 8 & 0 \\ dk27 & 3 & 5 & 4 & 4 & 7 & 0 \\ dk512 & 10 & 10 & 9 & 10 & 12 & 0 \\ ex3 & 9 & 9 & 9 & 9 & 11 & 0 \\ ex5 & 9 & 9 & 9 & 9 & 10 & 0 \\ lion & 2 & 5 & 2 & 2 & 6 & 0 \\ lion9 & 6 & 11 & 5 & 5 & 8 & 0 \\ mc & 4 & 7 & 4 & 5 & 6 & 0 \\ modulo12 & 7 & 7 & 7 & 7 & 9 & 0 \\ shiftreg & 2 & 6 & 2 & 2 & 4 & 0 \\ \hline Total & 62 & 86 & 61 & 64 & 89 & \\ \hline Percentage,\% & 69.66 & 96.63 & 68.54 & 71.91 & 100 & \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Experimental results for category 0 (the number of LUTs). Figure 9: Experimental results for category 0 (the number of LUTs—total percentage). Our method produces best results for FSMs from categories 29-4 (Table 9 and Figure 11). It is very interesting that the gain respectively the one-hot approach is approximately the same as it is in the previous case. However, we provide a bigger gain for other investigated methods as compared to FSMs of the category 1. There is the following economy: (1) 46.93% regarding Auto; (2) 19.63% regarding JEDI-based FSMs and (3) 29.39% regarding DEMAIN-based FSMs. So, our approach produces FSM circuits with better amount of LUTs for Mealy FSMs having \(L+R\geq 12\). Till now, we compared our approach with \(U_{1}\)-based FSMs. However, we also compared the \(U_{4}\)-based FSMs with FSMs having two levels of logic. The structural diagrams of these FSMs are shown in Figure 12. The FSM \(U_{5}\) is based on the replacement of inputs (Figure 12a). There is no \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Benchmark** & **Auto** & **One-Hot** & **JEDI** & **DEMAIN** & **Our Approach** & **Category** \\ \hline bbara & 17 & 17 & 10 & 9 & 10 & 1 \\ bbsse & 33 & 37 & 24 & 26 & 26 & 1 \\ beecount & 19 & 19 & 14 & 16 & 14 & 1 \\ cse & 40 & 66 & 36 & 38 & 33 & 1 \\ dk14 & 10 & 27 & 10 & 12 & 12 & 1 \\ dk15 & 5 & 16 & 5 & 6 & 6 & 1 \\ dk16 & 15 & 34 & 12 & 14 & 11 & 1 \\ donfile & 31 & 31 & 22 & 26 & 21 & 1 \\ ex2 & 9 & 9 & 8 & 9 & 8 & 1 \\ ex4 & 15 & 13 & 12 & 13 & 11 & 1 \\ ex6 & 24 & 36 & 22 & 23 & 21 & 1 \\ ex7 & 4 & 5 & 4 & 4 & 6 & 1 \\ keyb & 43 & 61 & 40 & 42 & 37 & 1 \\ mark1 & 23 & 23 & 20 & 21 & 19 & 1 \\ opus & 28 & 28 & 22 & 26 & 21 & 1 \\ s27 & 6 & 18 & 6 & 6 & 6 & 1 \\ s386 & 26 & 39 & 22 & 25 & 20 & 1 \\ s8 & 9 & 9 & 9 & 9 & 9 & 1 \\ sse & 33 & 37 & 30 & 32 & 26 & 1 \\ \hline Total & 390 & 525 & 328 & 357 & 317 & \\ \hline Percentage,\% & 123.03 & 165.62 & 103.47 & 112.62 & 100 & \\ \hline \hline \end{tabular}
\end{table} 
Table 8: Experimental results for category 1 (the number of LUTs).