# A 11 mW 2.4 GHz 0.18 \(\upmu\)m CMOS Transceivers for Wireless Sensor Networks
## 3 Circuit Implementation
### Frequency Synthesizer  
The frequency synthesizer has been a major bottleneck of fully-integrated transceivers [14; 15]. Due to this large silicon area and power consumption, it is usually an off-chip sub-system in many ultra-low-power solutions. However, in this work, to ensure the robustness and maximized flexibility, it is designed as a fully-integrated sub-system which provides frequency outputs fractional to the reference clock. It includes a voltage-controlled oscillator, a fractional-N frequency divider, a phase-frequency detector, a charge pump and a loop filter as shown in Figure 1.  
The voltage-controlled oscillator is the key building block in terms of working range, phase noise, and output power of the PLL. The key considerations are acceptable phase noise with low power consumption and small silicon area. To improve the power efficiency, the PMOS-NMOS cross-coupled negative-G\({}_{\text{m}}\) LC oscillator is used as shown in Figure 7. The optimization is mainly focused on the high-performance LC tank. The oscillator has a start-up condition which is determined by the quality of the tank and the negative G\({}_{\text{m}}\) to compensate the tank loss, which suggests that low power is only possible for a high quality factor (Q) tank. At 2.4 GHz range, the low quality factor of inductor is the major concern. A high Q can be obtained using an off-chip inductor, but it is susceptible to additional parasitic effects in the package and on the PCB. In this work, properly sizing of this on-chip fully-symmetrical inductor is used to ensure a high-quality factor (around 10) at the desired frequency range. The overall quality factor of the LC tank is about 6-7. After optimization, the biasing current of 0.7 mA is able to ensure a robust operation of the oscillator (three times higher than the start-up condition in G\({}_{\text{m}}\)). In additional to the varactors for continuous frequency  
Figure 7: The topology of the VCO. tuning, a three-bit digitally-controlled capacitance bank is implemented so that the proposed VCO can work properly from 2.2 GHz to 2.6 GHz. The gain of the VCO (K\({}_{\text{VCO}}\)) is designed to be less than 100 MHz/V to maintain a good phase noise performance, while covering the 2.4 GHz operating band with certain redundancy. The output power of this VCO (with an output buffer) is around 3 dBm. The simulated F-V curve of the VCO is shown in Figure 8. As shown in Figure 8, the simulated phase noise of the VCO is \(-113\) dBc/Hz at 1 MHz offset. Another key building block is the frequency divider. As shown in Figure 9, it includes a divide-by-two prescaler, a divide-by-4/5 prescaler, and the P counter with division ratios of 14, 15, and 16. The total division ratio is 2 \(\times\) (52 + M), where is M is fractional number, which is controlled by a 10-bit sigma-delta modulator (configured as Mash 1-1-1); considering the short-range communication with low power and small silicon area, even the fractional spur can be quite high due the insufficient random dithering. Another key consideration is the power consumption [14]. In this work, the blocks in the frequency divider are designed to be power efficient at the certain working frequencies. The prescaler is the most challenging building block in the frequency divider since it works at the highest operating frequency. The MOS current mode logic (MCML) is the most popular solution at the operating frequency above 1 GHz. However, it is quite power consuming compared with dynamic digital logic such as true-single-phase-clock (TSPC). Therefore, it is preferred that the MCML circuit is only implemented at the highest operating frequency, while the lower frequency division is performed with single-ended logic. In this work, to maintain a good balance between operating frequency and power consumption, the input signal is firstly divided by two using a MCML divider followed by a differential-to-single-ended buffer (CML-Dig in Figure 9). The MCML divide-by-two unit is shown in Figure 8b, which consists of two D-latches.