# PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA
## 3 Proposed P4-Programmable Parser
### Software Overview
#### 3.1.2 P4 Compiled JSON File
The hardware design follows a straightforward principle: extract key information from a specific location within a header, match it against predefined key values, transition to the next state upon a match, and forward the information as a Packet Header Vector (PHV) for subsequent processing stages. To simplify the hardware design, the critical \begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline \multirow{2}{*}{**Work**} & \multirow{2}{*}{**FPGA**} & \multicolumn{4}{c}{**Performance**} & \multicolumn{4}{c}{**Resources**} & \multicolumn{2}{c}{**Programmability**} \\ \cline{3-10}  & & **Bus Size** & **Freq.** & **TP** & **Max Latency** & **LUTs** & **FFs** & **Total Logic** & **Method** & **Time** \\ \hline
[22] & Alveo U200 & 64 & 125 & 8 & 23 & 3538 & 1578 & 5116 & Instr. & Hours \\
[18] & Virtex-7 & 64 & 173.4 & 11.1 & 10 & 312 & 1135 & 1447 & Memory & Min. \\ Proposed & Alveo U280 & 64 & 237.69 & 15.2 & 9 & 1028 & 1873 & 2901 & Register & Sec. \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Results comparison for base block. Figure 3: Base Block. pieces of information are generated via software data structures essential for initializing the processing objects. The Software Overview section provides a detailed discussion of how this information is generated from P4 code. These configurations include protocol keys, masks, next protocol IDs, multiplexer selections, and hierarchical sets of bitmaps, all crucial for determining the processing path. The base parser block also includes two critical sub-blocks designed to efficiently determine the next protocol header in the graph hierarchy with minimal dependencies and a low area footprint. When the protocol investigator unit identifies the next protocol to be parsed, it requires only bitmap updates to propagate to the block in the following cycle, enhancing the parser's efficiency and reducing the time and resources needed for protocol transitions. The two main components of the base parser block are the _Prism Controller_ and the _Protocol Navigator_. The Prism Controller manages control signals by calculating potential transition sets and using multiplexers to select protocol bitmaps and control signals based on clock cycles and comparison results, ensuring accurate control signal generation. As the guiding force, the Protocol Navigator directs the parser through both parsed and impending protocols. This block contains several Protocol Investigators sub-blocks, each tailored to specific protocols and responsible for retrieving header details from software-generated header configurations. The number of Protocol Investigator units corresponds to the transitioning nodes in the parsing graph, allowing detection of all possible protocols within the same clock cycle. As depicted in Figure 4, each Protocol Investigator is designed to be generic and extendable, adapting to diverse network protocols. It retrieves essential information, such as masks, keys, and next protocol IDs, under the control of the Prism Controller. It determines whether to activate its functionalities during each cycle and specifies which 2-byte input data segment to process. Using a protocol mask in a bitwise AND operation allows the extraction of relevant key bits from the input data. At the same time, a parallel search identifies a matching key through the Match Detector unit, which executes an XOR operation followed by a bitwise NOR operation to generate the match found signal. Additionally, the Bitmap Generator decodes the following protocol ID into a Protocol Bitmap, a vector with bits corresponding to the graph nodes. This newly encoded bitmap is combined with the previous cycle's protocol bitmap and outputs from other decoders using a bitwise OR operation. This process ensures a comprehensive representation of parsed protocols, facilitating efficient select operations in processing control stages. The protocol bitmap is an \(n\)-bit vector, where the position \(i\) indicates whether the _protocol ID \(-\) 1 = \(i\)_ has been detected.