## 2 Design Consideration
### Tia  
A trade-off exists between the suitability of the DC operating point and performance at low frequency in this conventional \(g_{\mathrm{m}}\) transimpedance structure. The bandwidth \(f_{\mathrm{w}}\) and transimpedance \(g_{\mathrm{m}}\) in TIAs are decoupled. High-feedback resistance is necessary for good noise performance. Figure 6 presents a schematic of a TIA topology with a feedback resistor \(R_{\mathrm{f}}\). The input impedance is extended by a factor of \(A+1\), where \(A\) is the amplifier gain, and the transimpedance is approximately \(R_{\mathrm{f}}\)[1; 14; 15].  
For a fixed-bandwidth amplifier, the equivalent transfer function T(s) is as shown in Equation (10):  
\[\mathrm{T(S)}=\frac{V_{out}}{\mathrm{I_{in}}}=-\frac{\mathrm{A}}{1+\mathrm{A}} \frac{\mathrm{R_{f}}}{1+\mathrm{\frac{RC}{1+A}}}=-\frac{\mathrm{A}}{1+\mathrm{ A}}R_{\mathrm{f}} \tag{10}\]  
To achieve the desired DC operating point, transistor size (\(W/L\)) must be increased. However, bandwidth decreases, and large parasitic capacitances occur at the output nodes [15; 17]. To overcome this problem, the SF state is introduced along with a shunt feedback resistor in the TIA as preferred in [14]. To increase the frequency bandwidth, a differential out-phase circuit is included in the TIA as shown in Figure 7.  
Figure 5: Single-ended Bode Plot of the Proposed CTLE.  
Figure 6: Simple TIA Topology with feedback resistor \(R_{\mathrm{f}}\).  
A two-input differential TIA with resistor feedback along the inductor in series is implemented. The TIA can facilitate data transfer at all speeds tolerated by the interface. The architecture has three parts that each corresponds to a stage. The first part is a shunted feedback resistor, the second part is a simple buffer, and the third part is an entirely differential output phase. A single-ended schematic is presented in Figure 7[14; 17]. Specifically, the shunt feedback resistor in the first stage converts a current to a voltage. \(M_{\text{S1}}\) and \(R_{\text{D}}\) are simple common sources, whereas \(M_{\text{SB}}\) is the tail current. The second-stage \(M_{\text{B1}}\) acts as a buffer and inverter with two SFs enabling isolation between the input and output of the amplifier. The third stage, \(M_{\text{O1}}\), is the output phase, which increases the phase and increases the amplifier gain in which \(M_{\text{OB}}\) is the tail current.  
Figure 8 shows a single-ended TIA circuit with a common source stage and SF. The SF isolates \(R_{\text{D}}\) from the loading effect of both \(R_{\text{f}}\) and \(L_{t}\). The output impedance of the SF is less than the resistor feedback [17; 20; 21].  
Figure 8: Single end of the TIA.  
Figure 7: Schematic of Single-ended TIA.  
The open-loop gain of the amplifier is as follows:  
\[\mathrm{T(S)}=-\frac{\mathrm{A}}{1+\mathrm{A}}\frac{\mathrm{G_{Ms}R_{D}}}{1+ \mathrm{G_{Ms}R_{D}}}\frac{1}{\mathrm{Z}} \tag{11}\]  
where \(Z\) is the impedance, which is the total resistance to current flow in a circuit containing both resistance \(R_{\mathrm{f}}\) and inductor reactance \(X_{\mathrm{L}}\). \(Z\) is defined as \(\sqrt{\mathrm{R_{f}}^{2}+\mathrm{X_{L}}^{2}}\).  
The input and output impedances of the resistor feedback at low frequencies are as follows.  
\[\mathrm{R_{Zin}}=\frac{\mathrm{Z}}{1+\mathrm{G_{Ms}R_{D}}} \tag{12}\]  
\[\mathrm{R_{Zout}}=\frac{\frac{1}{\mathrm{G_{ME}}}}{(1+\mathrm{G_{ME}R_{D}})} \tag{13}\]  
The inductor and resistor in series, gives second order frequency 3 dB bandwidth as follows.  
\[\omega_{-3 dB}=\frac{\sqrt{2}(1+A)}{\mathrm{R_{D}}} \tag{14}\]