# RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool
## 2 Hardware Representation Requirements
### RTL-DEVS Atomic Model
#### 2.3.3 Procedure Block Processing between External/Internal Transition  
Figure 6 describes the situation in which the signal of the out wire is updated by executing the procedure block during the internal/external transition and transition process of the atomic model given the input signal set. The moment the 0-time transition occurs, the atomic model can distinguish the previous state (current value) and the future state (new value). Internal variables in RTL-DEVS are part of the state of the atomic model expressed as integer values in the current implementation, and are updated before the actual time advance occurs. The 0-time internal transition between 0-time external transition and clk time transition is the part that monitors the occurrence of a transition or output event and can mimic the behavior of the procedure block using conditional statements. For output events after clk time transition, all LHS (left hand side) and RHS (right hand side) operations are performed through conditional statements before the output event occurs, and the LHS results are exported through the output wire for the finally determined variable. Figure 5: Edge trigger processing in inner variable of atomic model. Figure 6: Internal state transition representation. It shows 0-time transition for RHS operation. Figure 7 shows the variable assignment of a single atomic model and the behavioral structure of atomic model functions [external transition, internal transition, output function, time advance] in the DEVS-based simulation environment. Basically, the delay time in Verilog is divided into two models: transport delay and inertial delay. Inertial delay has been proposed to model gates or circuits that do not transfer short pulses from input to output. If the gate has a delay time of t, the pulse signal with a width shorter than t is ignored. The transport delay is intended to model the delay time that occurs in the wiring due to various physical factors. In other words, when an input change occurs, the input change is received, but the actual output is scheduled after a defined time. This delay time is processed based on the event queue, RHS, and LHS values that the Verilog simulator has internally. The active event queue performs logical operations on events that the Verilog module must process at the current time and output the result to the output. In DEVS formalism, the state transition of the model can be performed by processing the event of the active state based on each state and time advance. The non-blocking event queue exists to assign the RHS value calculated from the active event queue to the non-blocking assignment. Similarly, since the signal delivered to the input port in the RTL-DEVS model maintains the previous RHS value, it is possible to flexibly respond to non-blocking and blocking. The postponed queue stores the event occurrence time for the corresponding delay when there is a scheduled delay output. Figure 8 shows how the delay time model works in the RTL-DEVS model for a typical time slot in a Verilog simulation. Inertial delay is the default delay of Verilog HDL, and if the width of the change in the input signal is less than the specified delay value, the change in the input signal does not affect the output. In order to apply the inertial delay to the RTL-DEVS model, a transition occurs due to an external transition event, and when a logic operation occurs, it is necessary to evaluate the RHS value and compare it with the value to be assigned to the LHS. After performing RHS evaluation in the current time slot, the process of comparing whether it matches with the RHS value in the postponed queue is performed. If the RHS value is different from the value scheduled to be assigned to the postponed queue, the scheduled assignment event is canceled. If the new RHS value is the same as the current value of the LHS, a separate event does not occur and is added to the postponed queue to reserve the next time slot.