# Thermal Interaction and Cooling of Electronic Device with Chiplet 2.5D Integration
## 2 Thermal Interaction Model of Chiplet 2.5D Integration
### Collective Parameter Model  
To study the thermal interaction between two chiplets, the collective parameter model is established. The nodal method is used to solve the heat conduction equation under steady state conditions, and the thermal resistance between nodes represents the total thermal resistance between the two faces corresponding to the nodes. Depicted in Figure 2 is the collective parameter model. The total thermal resistance of C4 bump layer and the substrate (\(R_{second}\)) is neglected in this model. When chiplet1 is heated and chiplet2 is not heated, we define chiplet1 as the active chip and chiplet2 as the passive chip. The heat transfer direction of the active chip is depicted in Figure 2. The thermal resistances of the heat sink, TIM, chiplet, microbump layer, and interposer are denoted as \(R_{\text{fs}}\), \(R_{T}\), \(R_{D}\), \(R_{b}\), \(R_{inter}\), respectively. The sum of the thermal resistances of the microbump layer and interposer is represented as \(R_{c\_t}\). In addition, \(R_{J1}\) represents the thermal resistance between chiplet1 and the ambient temperature, and \(R_{J2}\) represents the thermal resistance between chiplet2 and the ambient temperature.  
The temperature rise of the passive chip is calculated as Equation (1):  
\[\Delta T_{J2}=Q_{2}\times(R_{\text{D2}}+R_{T2}+R_{\text{fs2}}) \tag{1}\]  
where  
\[Q_{2}=Q\times\frac{1}{1+\frac{R_{c\_t}+R_{\text{D2}}+R_{\text{T2}}+R_{\text{fs 2}}}{R_{\text{D1}}+R_{\text{T1}}+R_{\text{bs1}}}} \tag{2}\]  
Figure 1: Schematic of near-chip cooling for chiplet 2.5D integration.  
Figure 2: Collective parameter model.  
thus  
\[\Delta T_{J2}=Q\times\frac{R_{\rm D2}+R_{\rm T2}+R_{\rm ts2}}{1+\frac{R_{c,t}+R_{ \rm D2}+R_{\rm T2}+R_{\rm ts2}}{R_{\rm D1}+R_{\rm T1}+R_{\rm ts1}}} \tag{3}\]  
According to Equation (3), decreasing \(R_{c,t}\) will increase the temperature rise of the passive chip. Consequently, by increasing the thermal conductivity of the microbump layer, decreasing the thickness of the microbump and the spacing between the chiplets, and increasing the thickness and thermal conductivity of the interposer, \(R_{c,t}\) will decrease and the temperature rise of the passive chip will increase.  
As \(R_{J1}\) increases, \(R_{J2}\) also increases due to the same TIM and heat sink in chiplet 2.5D integration. We can define the increased thermal resistance as:  
\[R^{\prime}_{J1}=\alpha R_{J1}\ R^{\prime}_{J2}=\alpha R_{J2}\ \alpha>1 \tag{4}\]  
where  
\[\Delta T^{\prime}_{J2}=Q_{1}\times\frac{\alpha R_{J2}}{1+\frac{R_{c,t}+\alpha R _{J2}}{\alpha R_{J1}}} \tag{5}\]  
where  
\[\frac{\alpha R_{J2}}{1+\frac{R_{c,t}+\alpha R_{J2}}{\alpha R_{J1}}}>\frac{R_{ J2}}{1+\frac{R_{c,t}+R_{J2}}{R_{J1}}} \tag{6}\]  
and thus  
\[\Delta T^{\prime}_{J2}>\Delta T_{J2} \tag{7}\]  
According to Equations (5) and (7), as \(R_{J1}\) increases, the temperature rise of the passive chip increases. Thus, by decreasing the thermal conductivity of the TIM and the heat sink and increasing the thickness of the chiplet, the temperature rise of the passive chip increases.