## 1 Introduction
### Existing Polynomial Multiplier Architectures and Their Limitations  
Polynomial multiplication is the fundamental unit in modern ECC-based cryptographic devices. Several algorithms and hardware architectures have been proposed in the literature to accelerate area and timing constraints. Some examples of the most frequently used bit-serial designs are given in [14; 15; 16]. Bit-parallel architectures are adopted in [17; 18; 19; 20; 21; 22; 23; 24]. Some digit-serial implementation architectures are proposed in [25; 26; 27]. Similarly, digit-parallel multipliers used for PM computation in ECC are considered in [28; 29]. It is important to note that the computational complexity of bit-serial multipliers is \(x\) clock cycles for two \(x\)-bit operands. The bit- and digit-parallel multipliers result in one multiplication in one clock cycle with an expense of area and power. The cost of digit-serial multipliers is \(\frac{x}{y}\) cycles, where \(x\) is the operand size and \(y\) is the digit size. An interesting evaluation study over various multiplication approaches is shown in [30]. Moreover, an open-source library of several polynomial multipliers is described in [31], where polynomial multiplications for binary elliptic curves are also presented. Additionally, various architectures, such as sequential, parallel, systolic, semi-systolic and pipelined, are proposed based on the requirement of the targeted application. Consequently, bit-serial multiplication approaches are area- and power-efficient and are appropriate for constrained cryptographic applications. **Bit-serial multiplier designs. ** An efficient interleaved modular reduction multiplication algorithm along with its bit-serial sequential architecture is described in [14] for different cryptographic applications. This polynomial multiplication architecture is an appropriate choice for security provision in applications associated with the Internet of Things (IoT). Different multiplication architectures for both bit- and digit-serial Montgomery multiplication using linear feedback shift registers (LFSRs) are investigated in [15]. Their study demonstrates that the use of LFSR results in a decrease in area resources while keeping high performance. A low-complexity scalable serial architecture for polynomial multiplication over \(GF(2^{m})\) is presented in [16]. Their design is more convenient for deployments of cryptographic primitives in resource-constrained applications, such as smart cards, embedded devices related to medical applications, etc. **Bit-parallel multiplier architectures. ** A modular polynomial multiplication algorithm is depicted in [17] to provide an \(m\)-bit parallel systolic multiplier architecture for polynomial basis representations of ECC, where \(m\) defines the length of the polynomials operand. In [18], time-dependent and time-independent multiplication algorithms over the \(GF(2^{m})\) field are presented. They employ interleaved conventional multiplication and folded techniques. Their algorithm allows the efficient realization of the bit-parallel systolic multipliers. The implementation results are reported on a Virtex-7 FPGA. Their results reveal that the time-independent multiplier can save 54% hardware resources as compared to other related multipliers. Versatile polynomial multiplication architectures over \(GF(2^{m})\) field using the Montgomery multiplication algorithm are reported in [19]. With the aim of achieving low-power and low-hardware resource utilizations, a bit-parallel polynomial basis systolic multiplier architecture over \(GF(2^{m})\) is presented in [20]. In [21], a bit-parallel multiplication method is proposed by using an important feature, i.e., concurrency, which makes its execution faster. The multiplication result using this scheme is generated in every clock cycle, after taking '\(m\)' clock cycles in the beginning. The implementation results are reported on FPGAs. A high-throughput, low-complexity systolic Montgomery multiplication architecture over \(GF(2^{m})\) is presented in [22].