## 3 Results and Discussion
### GFET RF Measurement  
S-parameter measurements were carried out on another flexible GFET device with ground-signal-ground (GSG) pads at the gate and drain terminals with the source serving as the common ground. The measurement was done using an Agilent VNA (E8361C) and cascade RF probe station. The intrinsic device data is obtained by employing a two-step de-embedding process. The device under test (GFET) can be modeled as shown in Figure 4a. The \(Y\)-parameters of the device under test were obtained from extrinsic data, and afterwards the parasitics (obtained from open and short test structures) were de-embedded to determine the intrinsic device frequency response (see Equation (2), adapted from [18]). The open structure will help to determine parallel parasitics (\(Y_{\text{P1}}\), \(Y_{\text{P2}}\), \(Y_{\text{P3}}\)) and the short structure will help to determine the series parasitics (\(Z_{\text{11}}\), \(Z_{\text{12}}\) and \(Z_{\text{13}}\)). These series parasitics are very critical for modern small channel FETs. \[Y_{GFET}=((Y_{dut}-Y_{open})^{-1}-(Y_{short}-Y_{open})^{-1})^{-1} \tag{2}\]  
where \(Y_{\text{GFET}}\) is the \(Y\)-parameters of the intrinsic GFET, \(Y_{\text{dut}}\) is the \(Y\)-parameter of DUT (Extrinsic GFET), \(Y_{\text{short}}\) is the \(Y\)-parameter of the DUT with gate, drain and source shorted, \(Y_{\text{open}}\) is the DUT with no graphene channel. Here, the graphene channel is etched by using reactive ion plasma etch tool. \(Y_{\text{short}}\) and \(Y_{\text{open}}\) are deembedded from \(Y_{\text{dut}}\) to obtain the intrinsic GFET performance (\(Y_{\text{GFET}}\)). Figure 4b shows the current gain h\({}_{\text{21}}\) of the intrinsic GFET, from which the 18 GHz \(f\)r is extracted. The extrinsic \(f_{\text{T}}\) of the GFET is 1.8 GHz. Figure 4c shows the power gain U (dB) of the intrinsic GFET. Figure 3: Electrical properties of graphene transistor (**a**) Gate modulation of graphene resistance. The drain voltage is set to 10 mV; (**b**) Drain current (I\({}_{\text{D}}\)) _vs._ Drain voltage (V\({}_{\text{D}}\)). We obtained \(f_{\rm max}\) of \(\sim\)3 GHz. \(f_{\rm T}\) and \(f_{\rm max}\) are given by Equations (3) and (4). They depend upon the transconductance \(g_{\rm m}\), gate capacitance \(C_{\rm gs}\), parasitic gate-drain capacitance \(C_{\rm p,gs}\), parasitic gate-source capacitance \(C_{\rm p\text{-}gd}\) and gate resistance \(R_{\rm g}\). \(f_{\rm T}\) can be improved by reducing channel length and design of better layouts (reduced parasitics) [19]. \(f_{\rm T}\) and \(f_{\rm max}\) are lower for flexible devices compared to devices fabricated on rigid substrates mainly due to poor thermal dissipation of flexible polymer substrate at high fields [19]. Thermo-mechanical breakdown occurs when the local hot spot temperature exceeds the glass transition temperature of the soft substrate [2]. One solution to overcome this challenge is to employ flexible glass substrates, such as Corning \"willow\" glass, which offers a higher thermal conductivity than polymers or elastomers. Indeed, improved high-frequency graphene transistors have been achieved on bendable willow glass with intrinsic \(f_{\rm T}\sim\)100 GHz and record saturation velocity for flexible graphene [14]. \[f_{\rm T}=\frac{g_{m}}{2\pi\big{(}C_{gs}+C_{p,gs}+C_{p,gd}\big{)} \left(\big{(}R_{p,s}+R_{p,d}\big{)}g_{d}+\mathbf{1}\right)+C_{p,gd}g_{m}(R_{p,s }+R_{p,d})} \tag{3}\] \[f_{max}=\frac{f_{\rm T}}{2g_{d}(R_{p,s}+R_{gate})+2\pi f_{\rm T} C_{p,gd}R_{gate}} \tag{4}\]  
Figure 4: (**a**) RF model of GFET under test, where \(Y_{\rm p1}\), \(Y_{\rm p2}\) and \(Y_{\rm p3}\) are parallel parasitics and \(Z_{\rm L1}\), \(Z_{\rm L2}\) and \(Z_{\rm L3}\) are series parasitics (They represent GFET contact pads and interconnects). (**b**) Current Gain (h\({}_{\rm 21}\)) _vs._ Frequency. The intrinsic \(f_{\rm T}\sim\)18 GHz; (**c**) Power gain (U) in dB _vs._ Frequency. \(f_{\rm max}\sim\)3 GHz. These devices are measured at the following voltage conditions (\(V_{\rm drain}\sim\)0.4 V, \(V_{\rm gate}\sim\)0.2 V).