## 2 VCO Implementation with Linearized Transconductance and Capacitive Tuning
The large sized MOS transistor introduces parasitic capacitance, and limits the tuning range of the VCO. Hence, for a wide tuning range, small size transistors are preferred. Figure 4: Swing of the Gate voltage in a conventional VCO and linear transconductance VCO. As shown in Figure 5, the switched capacitor quality factor (\(Q_{C}\)), when the switch is on, is proportional to Equation (6):  
\[Q_{C}\propto 1/R_{sw} \tag{6}\]  
where the value of \(R_{sw}\) can be calculated through Equation (7). \[R_{sw}=\frac{1}{\mu_{n}C_{ox}\Big{(}\frac{W}{L}\Big{)}(V_{GS}-V_{th})}\]  
where \(\mu_{n},\ C_{ox},\ W,\ L,\ V_{GS}\), and \(V_{th}\) are the mobility of the carrier, oxide capacitance, width, length, and the threshold voltage of the NMOS switch, respectively. Also, in the off state, the equivalent capacitance \(C_{off}\) is equal to Equation (7):  
\[C_{off}=C\times Csw/[2\times(C+Csw)] \tag{7}\]  
Therefore, the switch size and the value of \(C\) should be chosen carefully to minimize the on-resistance of the switch, while keeping the frequency range wide. Since the frequency steps and the fixed unit capacitor of the coarse stage are large, the switch sizes in this stage are selected to be large enough to minimize the on-resistance. Besides, the switch sizes for the middle capacitor array are optimized through noise analysis, to make their noise contribution less than 2%. As shown in Figure 3, the discrete frequency tuning of the VCO is realized by using 3-bits coarse and 6-bits middle tunings. The varactor offers a continuous frequency tuning range of 160 MHz/V at the center frequency of 16 GHz. Higher VCO gain (KVCO) needs a larger fixed capacitor inside the varactor, and introduces large AM (Amplitude modulation) to FM (Frequency modulation) noise. Therefore, the size of the capacitance of the varactor, or the value of KVCO, can be relaxed, while this capacitance can be compensated by increasing the size of the switches in both coarse and middle tuning stages. The middle capacitor bank and varactor are located at the Drain since the variation of the capacitance is less than that of the Gate. Two resistors inside the switched capacitor are provided to isolate the AC of the VCO nodes. To lower the thermal noise of the resistor inside the switched capacitor, its size is optimized to make the noise contribution less than 1%. The tail inductor resonates with the parasitic capacitance of the tail node (2w\({}_{0}\)), and prevents the loading of the tank when one of the cross-coupled transistors enters the triode region, thereby improving phase noise. This method also enhances the linearity of the cross-couple transistors and lowers the current harmonics. Figure 6 shows the schematic and simulated environment of the designed inductive buffer. In a transceiver, the buffer isolates the VCO from the other signal path of the transceiver. At both inputs of the buffer, AC coupling capacitors are provided to block the DC components of the AC waveform, so that the buffer remains correctly biased through the provided resistors R1 and R2. The switched capacitor adjusts the output swing of the buffer, with consideration of the carrier frequency and Process, Voltage, and Temperature (PVT) variations. \[dV_{out}{}^{2}[\omega]=KTR_{pur}[1+A]\Big{(}\frac{\omega_{0}}{\omega}\Big{)} ^{2}df \tag{2}\]0 Switch capacitor equivalent circuit in off and on cases of switch. As shown in Figure 7a, the VCO routing introduces parasitic inductance and resistance, which lower the quality factor of the tank. In order to shrink the output routing, the input transistors of the VCO buffer are located as close as possible to the VCO output's routing, as seen in Figure 7b. Thus, utilizing this technique keeps VCO output routings short, and enhances the phase noise performance of the VCO by around 1 dBc/Hz at 1 MHz offset frequency. To suppress the parasitic resistance and inductance, the routing of VCO outputs is stacked through the wide metal 7 and 8. Via and wide metal lines tie the parasitic inductance in parallel.