# Transforming Group Codes in Mealy Finite State Machines with Composite State Codes
## 1 Introduction  
Modern digital systems include a lot of different sequential devices [1, 2]. Very often, to represent these devices, a model of a Mealy finite state machine (FSM) [3] is used. An FSM model is a starting point for creating the electrical circuit of a sequential device. In this paper, we discuss a case where the circuits of Mealy FSMs are created using the internal resources of field-programmable gate arrays (FPGAs) [4]. The choice of this basis is justified by the fact that FPGAs are a very popular tool used for creating the circuits of various digital devices [5]. Moreover, FPGAs will be used in logic design within the next thirty years [6]. As a rule, some optimization problems arise in the process of FSM design. These problems are interrelated. The following characteristics may require optimization [7; 8; 9]: the amount of internal resources used (occupied chip area), or performance, or power consumption. In this article, we propose a method which allows for an increase in the maximum operating frequency of an FPGA-based Mealy FSM circuit. The following internal resources are used to create the circuit: look-up table (LUT) elements, programmable flip-flops, dedicated multiplexers, a synchronization tree, programmable interconnections and programmable input-outputs [4; 8; 10]. We discuss a case where FSM states are encoded by composite state codes (CSCs) [11]. This approach is based on creating groups of compatible states. Both groups and states are encoded using the minimum possible number of variables. The proposed method improves performance without a significant increase in the amount of internal resources used. We use the LUT count [12] to estimate the chip area occupied by the FSM circuit. Modern digital systems are processing larger and larger amounts of information [13]. When implementing digital systems based on FPGAs, very often increasing the system performance without a significant increase in the amount of internal resources consumed is a problem [14]. At the same time, the bottleneck may be the digital system control device, implemented in the form of an FSM. The control device generates control signals at each point in the system's operation. Therefore, the performance of this control FSM significantly affects the performance of the digital system as a whole [15]. One of the ways to increase the performance of an FSM is a state assignment, which allows us to reduce the number of logical levels in the FPGA-based FSM circuit [16; 17]. In this article, we propose a state assignment method allowing us to increase the FSM performance without a significant overhead regarding the internal resources used. The main contribution of this paper is a novel approach improving the cycle time (the operating frequency) of LUT-based Mealy FSM circuits with composite state codes. The improvement is based on transforming the maximum binary codes of groups of compatible states into one-hot codes (OHCs). Within each group, states are encoded by maximum binary codes (MBCs). This approach leads to the development of a new architecture of an FSM circuit different from the architecture where OHCs are not used [11]. The performance improvement is related to the absence of the need to use group codes in the function assembler block. This approach allows the performance to improve for rather complex FSMs. A positive feature of this approach is the total absence of an increase in the amount of the internal resources of the FPGA chip used. Moreover, the proposed approach leads to the creation of circuits with slightly fewer LUTs than their equivalent CSC-based counterparts. The main idea of this article is as follows: the transformation of maximum binary group codes into one-hot codes allows for a decrease in the number of partial Boolean functions generated by LUTs from the first logic level of an FSM circuit.