# A CMOS-Based Terahertz Reconfigurable Reflectarray with Amplitude Control: Design and Validation
## 3 Element Design
### CMOS-Based Switch Design and Parameter Extraction
#### 3.1.1 Switch Design  
Transistors based on CMOS technology exhibit parasitic capacitance effects in the terahertz frequency range. This phenomenon prevents the switch from shutting off in the OFF state, resulting in significant leakage. Therefore, a parallel inductor is usually employed to form a resonance with the parasitic capacitance at the operating frequency [41], converting the circuit into a high-impedance path and thus achieving the desired turn-off functionality.  
A custom-designed inductive loop is constructed to generate the necessary inductance in the M9 layer, enabling resonance with the transistor's parasitic capacitance, as illustrated in Figure 2. The switch's equivalent impedance parameters change depending on the gate voltages of 0 V and 0.8 V. An inductor loop is equivalent to an inductance \(L\). The inductive loop is connected to the source and drain terminals of the N-channel Metal-Oxide-Semiconductor (NMOS) transistor. The gate resistor is used to reduce THz signal leakage. The ground resistors at the source and gate of the switch are placed to prevent floating potential. In Figure 2, \(R_{\text{on}}\) and \(R_{\text{off}}\) represent the equivalent source and drain resistances of the transistor under ON or OFF states in post-simulation results, including channel resistance and parasitic resistances.  
As illustrated in the transistor's small-signal model, in the OFF state, the complex parasitic capacitance can resonate with the external inductance \(L\), presenting a high-impedance state. The equivalent parasitic capacitance in the OFF state (\(C_{\text{off}}\)) can be derived as:  
\[C_{\text{off}}=C_{\text{ds}}+\frac{C_{\text{gs}}\cdot C_{\text{gd}}}{C_{\text{ gs}}+C_{\text{gd}}}+\frac{C_{\text{sb}}\cdot C_{\text{db}}}{C_{\text{sb}}+C_{ \text{db}}}. \tag{1}\]  
Figure 2: Circuit schematic of the THz switch and small signal model of transistor employed in the switch.  
The values of the parasitic capacitances can refer to the post-simulation results of the transistor. To achieve resonance at the frequency of interest \(f\), the required inductance value \(L\) is determined by  
\[L=\frac{1}{(2\,\pi f)^{2}C_{\text{off}}}. \tag{2}\]  
In the ON state, the low-impedance path provided by \(R_{\text{on}}\) replaces the impedance path formed by the parasitic capacitance. The source and drain terminals of the parallel inductive loop are directly connected to the switch's source and drain. The entire switch can be integrated with the RRA element design on the M9 layer using the source (S) and drain (D) terminals.  
In the THz switch design, the dimensions of the inductive loop and the transistor are critical parameters determining switch working frequency. The inductance of the loop is related to its diameter and can be obtained through full-wave electromagnetic simulation. The required inductance for resonance is given by Equation (2). The size of a transistor is usually scaled up by increasing the number of fingers, resulting in an equivalent parallel transistor configuration. This configuration reduces the resistance (\(R_{\text{on}}\)) in the ON state, while simultaneously increasing the parasitic capacitance (\(C_{\text{off}}\)) in the OFF state. Although larger transistor dimensions may degrade the switch OFF-state performance, Equation (2) demonstrates that the increased \(C_{\text{off}}\) actually reduces the required inductance for resonance at the working frequency. This allows for more compact inductor sizing while avoiding excessive space consumption, which is particularly valuable for RRA element design.  
In summary, for switch design in terahertz RRA elements, the process involves the following: first evaluating the appropriate size range of the inductor loop based on the sub-wavelength period of the RRA element; then selecting suitable transistor dimensions to achieve resonance near the target frequency; and finally determining the optimal loop diameter according to the specific transistor dimensions.