## 2 Study of Used Discrete Chaotic Maps: Statistical Test and Hardware Metrics
### Hardware Metrics  
We interpret the implementation of the chaotic maps in regard to the resources utilized (area, DSPs), the speed (WNSi, Max. Freq., throughput), and the efficiency (throughput-to-slices ratio). Furthermore, we give the power consumption.  
\[Max.Freq.=\frac{1}{Ti-WNSi}(MHz). \tag{7}\]  
where \(Ti\) is the target clock period (ns) used during the implementation run \"\(i\)\" and \(WNSi\) is the Worst Negative Slack (ns) of the target clock used during the implementation run \"\(i\)\" and must be positive, and very close to zero.  
The data Throughput is calculated by Equation (8).  
\[Throughput=N\times Max.Freq.(Mbps). \tag{8}\]  
The Efficiency is calculated by using Equation (9).  
\[Efficiency=\frac{Throughput}{Slices}(Mbps/Slices). \tag{9}\]  
The chaotic systems implementation was carried out on the Xilinx-manufactured PYNQ-Z2 FPGA board. To implement the chaotic systems, the code was written in VHDL using 32-bit fixed-point data format, then synthesized and implemented using Xilinx Vivado design suite (V.2017.2). The Vivado design suite tools are a set of tools provided by Xilinx for designing and implementing digital circuits on FPGA boards. These tools enable the complete design flow from creating the RTL design, to implementation, synthesis, and programming of the FPGA. The Vivado design suite includes a powerful integrated development environment (IDE) that allows users to easily design, debug, and test their designs. It also includes various features such as timing analysis, power analysis, and design exploration, which can help in fine-tuning the design for optimal performance and power consumption. As illustrated in Figure 4, we present a summary of the various stages of the conception flow that were executed using Vivado for evaluating the metrics of the discrete  
\begin{table}
\begin{tabular}{l l l l l l l} \hline \hline
**Chi-Square Test** & **Logistic** & **STM** & **PWLCM** & **3D-Ch** & **LFSR** & **3D-Ch with LFSR** \\ \hline \(\chi^{2}_{exp}\) & 38,698.41 & 1113.45 & 1146.92 & 41,865.00 & 989.48 & 999.48 \\ \(\chi^{2}_{th}\) (1000, 0.05) & 1073.64 & 1073.642 & 1073.64 & 1073.64 & 1073.64 & 1073.64 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Chi-square results on the tested histograms.  
Figure 3: 3D-Chebyshev map coupled with the used LFSR using a XOR operator.  
Skew-Tent map as an example of demonstration. Note that the same steps for all studied chaotic systems were repeated since Design entry up to configuration bitstream generation.  
The areas of the implementations of the chaotic systems on FPGA are compared using slices, Flip-Flops (FFs), and lookup tables (LUTs), which are the basic logic block of Xilinx FPGAs. Latency, maximum frequency, and throughput together determine execution speed. The efficiency parameter represents the throughput-to-slices ratio and provides a general understanding of the implementation's hardware performance as measured by the hardware metrics.  
All designs have been tested after place and route using simulation to ensure the correct functionality and produce one sample at each clock cycle.  
At the end of the Place & Route process, we get the hardware metrics of chaotic systems implemented on the PYNQ-Z2 FPGA chip. Table 2, resume the obtained hardware metrics of studied chaotic maps, the 32-bit LFSR, and the 3D-Chebyshev map coupled with the 32-bit LFSR.  
Figure 4: The design flow of the Skew-Tent map on FPGA using Vivado.  
In terms of computing performance, the PWLCM is slower when compared to other chaotic maps and uses approximately three times more hardware resources than the Skew-Tent map. Moreover, the obtained values for the discrete Logistic map show that a high throughput characterizes the Logistic map compared to the throughput of the other studied chaotic maps and uses fewer hardware resources. Furthermore, the 3D-Chebyshev map coupled with the 32-bit LFSR achieves a throughput of approximately 1.5 Gbps.