# NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors
## 7 Conclusions  
The NMR-MPar is a generic software-approach developed to improve the reliability of applications running in multi-/many-core processors by using partitioning, spatial redundancy and redundancy in data. Spatial redundancy is proposed at the system and application levels, surpassing the weakness of classical redundancy approaches that only replicate processes at the application level, leaving the system level unprotected. In addition, partitioning guarantees the isolation needed to certify safety-critical applications. Experimental results demonstrated that there is a significant decrease of the application error-rate, about two orders of magnitude, when implementing the NMR-MPar approach on the MPPA many-core processor.  
Taking into account the improvements obtained by applying the NMR-MPar to the selected benchmarks and considering that (1) no erroneous results and timeouts occurred, (2) all the errors were produced by exceptions, (3) all the exceptions were detected and (4) exceptions can be easily managed by the system through a reset, this approach is very useful for applications that do not have a critical time constraint. Moreover, the reliability of many-core processors could be better improved by implementing SIFT techniques at the application level.  
Lastly, the NMR-MPar can be implemented in other multi-/many-core processors, the implementation being specific for each device. Evaluation results of the implemented case study are encouraging since they open the possibility to use massive parallelism for dependable applications in embedded systems.  
The codes of the implementation of the case study are available upon request to the corresponding author ([EMAIL_ADDRESS]).  
This work was supported in a part by the Universidad de las Fuerzas Armadas ESPE and by the Secretaria de Educacion Superior, Ciencia, Tecnologia e Innovacion del Ecuador (SENESCYT) through the grant PIC-2017-EXT-004 and STIC -AmSud (Science et Technologie de l'Information et de la Communication en Amerique du Sud) - Energy-aware Scheduling and Fault Tolerance Techniques for the Exascale Era (EnergySFE) Project PIC-16-ESPE-STIC-001 and by the French authorities through the \"Investissements d'Avenir\" program (CAPACITES project). The authors thank [PERSON] from the Societe Kalray for his valuable contribution to solving the MPPA programming issues and to [PERSON] from Universidad de las Fuerzas Armadas ESPE for his helpful comments and suggestions.  
[PERSON], [PERSON] and [PERSON] conceived of and designed the experiments. [PERSON] and [PERSON] contributed the fault-injection tool, performed the experiments and analyzed the data. [PERSON] and [PERSON] contributed materials. [PERSON] and [PERSON] wrote the paper.  
The authors declare no conflict of interest. The founding sponsors had no role in the design of the study; in the collection, analyses or interpretation of data; in the writing of the manuscript; nor in the decision to publish the results.  
The following abbreviations are used in this manuscript:  
\begin{tabular}{l l} ACROSS & Advanced Cockpit for Reduction Of StreSs and workload \\ AMP & Asymmetric Multi-Processing \\ CAST & Certified Associate in Software Testing \\ CAPACITIES & Calcul Parallele pour Applications Critiques en Temps et Surete \\ CC & Compute Cluster \\ CEU & Code Emulated Upset \\ COTS & Commercial-Off-The-Shelf \\ CRC & Cyclic Redundancy Check \\ \end{tabular}