## 2 Dead-Time Effect of the Auxiliary Resonant Snubber Inverter (ARSI)
### Principle
#### 2.1.1 Heavy Load Condition  
In the heavy load condition, \"AZVS + NZVS,\" namely achieving AZVS of a set of switches and NZVS of the other set of switches, is realized. One switching cycle of the operating waveforms are shown in Figure 2, where \(v_{ds}\) is the drain-source voltage of a MOSFET, \(i_{d}\) is the drain current of a MOSFET, \(v_{g}\) is the actual gate signal with dead-time, \(v_{g,id}\) is the ideal gate signal, \(i_{L}\) is the resonant inductor current, \(v_{ab}\) is the actual pole voltage across the load with dead-time, \(v_{ab,id}\) is the ideal pole voltage across the load and \(v_{err}\) is the voltage error between \(v_{ab}\) and \(v_{ab,id}\). During the dead-time \(t_{H1}\)-\(t_{H3}\), the resonant capacitors first resonate with the load inductor. Owing to the positive load current, \(\mathrm{C_{r2}}\) and \(\mathrm{C_{r3}}\) are discharged and \(\mathrm{C_{r1}}\) and \(\mathrm{C_{r4}}\) are charged. After \(\mathrm{C_{r2}}\) and \(\mathrm{C_{r3}}\) are discharged to zero-voltage at \(t_{H2}\), the body diodes \(\mathrm{D_{2}}\) and \(\mathrm{D_{3}}\) conduct the current and then the voltage is clamped to zero. Thus, \(\mathrm{S_{2}}\) and \(\mathrm{S_{3}}\) can be turned on at the ZVS condition. Regarding the dead-time \(t_{H1}\)-\(t_{H3}\), it consists of the resonant stage and diode clamping stage. The dead-time causes the pole voltage error. As for the ARSI, the voltage error only occurs in the resonant stage, which is caused by the finite rise- and fall-times of the voltage. During the resonant stage \(t_{H1}\)-\(t_{H2}\), the actual pole voltage can be obtained as follows:  
\[v_{ab}(t)=V_{s}-\frac{i_{o}}{C_{r}}(t-t_{H1}) \tag{1}\]  
Figure 1: Circuit of auxiliary resonant snubber inverter. Conversely, the ideal pole voltage should be as follows:  
\[v_{ab,id}(t)=-V_{s} \tag{2}\]  
Thus, the voltage error can be given as follows:  
\[v_{err}(t)=v_{ab}(t)-v_{ab,id}(t)=2V_{s}-\frac{i_{o}}{\mathcal{C}_{r}}(t-t_{H1}) \tag{3}\]  
For Equation (1) \(v_{ab}(t)=-V_{s}\), the resonant time can be obtained:  
\[\Delta t_{H12}=t_{H2}-t_{H1}=\frac{2C_{r}V_{s}}{i_{o}} \tag{4}\]  
Regarding the next commutation, S\({}_{\text{r1}}\) is turned on at \(t_{H4}\) to charge the resonant inductor, so that the switch current reverses at \(t_{H5}\). Therefore, after S\({}_{2}\) and S\({}_{3}\) are turned off at \(t_{H6}\), the resonant capacitors can resonate with the resonant inductor, which discharges C\({}_{\text{r1}}\) and C\({}_{\text{r4}}\) to zero-voltage at \(t_{H7}\). Subsequently, the body diodes D\({}_{\text{1}}\) and D\({}_{\text{4}}\) conduct the current. Thus, S\({}_{\text{1}}\) and S\({}_{\text{4}}\) can be zero-voltage  
Figure 2: Key waveforms of the the auxiliary resonant snubber inverter (ARSI) in the heavy load condition. turned on at \(t_{H8}\). Regarding the dead-time \(t_{H6}\)-\(t_{H8}\), it also consists of the resonant stage and diode clamping stage. Only the resonant stage \(t_{H6}\)-\(t_{H7}\) brings about the dead-time effect, which is caused by the finite rise- and fall-times. Some equations can be given as follows during the resonant stage. \[v_{d81}\left(t\right)+v_{d83}\left(t\right)=V_{s} \tag{5}\]  
\[i_{c71}\left(t\right)=C_{r}\frac{dv_{d81}\left(t\right)}{dt} \tag{6}\]  
\[i_{c73}\left(t\right)=C_{r}\frac{dv_{d83}\left(t\right)}{dt} \tag{7}\]  
\[i_{c71}\left(t\right)+i_{Lr}\left(t\right)=i_{o}+i_{c73}\left(t\right) \tag{8}\]  
Figure 1:0  
The initial resonant condition is given as follows:  
Figure 1:1  
Figure 1:2  
Figure 1:3  
According to Equations (5)-(12), the inductor current and drain-source voltages of the main MOSFETs can be obtained as follows:  
Figure 1:4  
Figure 1:5  
Figure 1:6  
where \(\omega_{A}=\frac{1}{\sqrt{L_{r}C_{r}}}\), \(Z_{A}=\sqrt{\frac{L_{r}}{C_{r}}}\), and \(I_{Lrm}\) is the initial resonant inductor current. The pole voltage can be obtained as follows:  
Figure 1:7  
where \(I_{boost1}\) is the switch current at the initial resonant time \(I_{boost1}=I_{Lrm1}-i_{o}\).