## 3 Proposed Multi-Modulus Multiplier Based on Radix-8 Booth Encoding
### Proposed Radix-8 Multi-Modulus Multiplier
\begin{array}{ll}C_{1}=&\sum\limits_{i=0}^{\lfloor n/3\rfloor-1}2^{3i+2}[(( m3_{i}+m4_{i})\cdot s_{i})\oplus(K1_{i}\cdot K2_{i})]+\sum\limits_{i=0}^{ \lfloor n/3\rfloor}2^{3i}\big{(}\overline{m2_{i}+m4_{i}}\big{)}\\ &+&\left\{\begin{array}{l}\sum\limits_{i=0}^{\lfloor\frac{5}{3}\rfloor}2^{3 i+1}\left[\underbrace{(m3_{i}+m4_{i})}_{K1_{i}}\oplus\underbrace{((m2_{i}+m4_{i}) \cdot s_{i})}_{K2_{i}}\right]\\ &\text{,when }n\
eq(3k+2)\text{ }bit,k=1,2,3,\ldots\\ &\sum\limits_{i=0}^{\lfloor\frac{5}{3}\rfloor-1}2^{3i+1}\left[\underbrace{( \overline{m3_{i}+m4_{i}})}_{K1_{i}}\oplus\underbrace{((m2_{i}+m4_{i})\cdot s_{ i})}_{K2_{i}}\right]+\sum\limits_{i=\lfloor\frac{5}{3}\rfloor}2^{3i+1}\big{[} \big{(}\overline{m3_{i}+m4_{i}}\big{)}+((m2_{i}+m4_{i})\cdot s_{i})\big{]}\\ &\text{,when }n=(3k+2)\text{ }bit,k=1,2,3,\ldots\end{array}\right.\end{array}  \tag{37}\]For modulo \(2^{n}+1\), the final compensation of \(C_{2}\) (replacing \(C_{2}\)') is obtained as follows:  
\[ \begin{array}{ll}C_{2}=&\sum\limits_{i=1}^{\lfloor n/3\rfloor}2^{3i}\cdot 1+ \sum\limits_{i=0}^{0}2^{3i+1}\cdot(\overline{s}_{i}\oplus 1)+\sum\limits_{i=0}^{0}2^{3i +2}(s_{i}+1)+\sum\limits_{i=1}^{\lfloor n/3\rfloor-1}2^{3i+2}\cdot s_{i}\\ &+\left\{\begin{array}{ll}\sum\limits_{i=1}^{\lfloor n/3\rfloor}2^{3i+1} \cdot\overline{s_{i}},\,when\,n\
eq(3k+2)\,bit,k=1,2,3,\ldots\\ \sum\limits_{i=1}^{\lfloor n/3\rfloor-1}2^{3i+1}\cdot\overline{s_{i}}+\sum \limits_{i=\lfloor n/3\rfloor}^{\lfloor n/3\rfloor}2^{3i+1}[\overline{s_{i}} \oplus(K1_{i}\cdot K2_{i})],when=(3k+2)\,bit,k=1,2,3,\ldots.\end{array}\right. \end{array}  \tag{38}\]  
The final result of \(|Z|_{m}\) can be represented as:  
\[|Z|_{m}=\left\{\left|\sum\limits_{i=0}^{\lfloor\lfloor n/3\rfloor}PP_{i}+C1+C2 \right|_{m}\right. \tag{39}\]  
The compensation value \(C_{2}\) is only needed to compensate for the modulo \((2^{n}+1)\) multiplier. Therefore, two input AND gates are used with the selected signal S1 (Mod S1). The compensation value \(C_{1}\) is needed to compensate for the modulo \((2^{n})\) and modulo \((2^{n}+1)\) multipliers. The compensation circuit for \(n=8\) is shown in Figure 12. It should be noted that the modulo \((2^{n}-1)\) multiplier need not be compensated for by the extra compensation circuit. The final proposed structure of the radix-8 multi-modulus multiplier for 8 bits (\(n=8\)) is shown in Figure 13, which includes a partial product unit, IEAC unit, and parallel prefix adder. The Lander-Fisher [12] structure is used for the improved parallel prefix adder circuit, which is shown in Figure 14 (\(n=8\)). Figure 12: The compensation circuit of the proposed radix-8 multi-modulus multiplier for 8 bits. Taking \(n=8\) as an example for the proposed multi-modulus multiplier based on radix-8 Booth encoding, Figure 15 shows the operational processes of the proposed modulo \((2^{n}-1)\), modulo \((2^{n})\), and modulo \((2^{n}+1)\) multipliers. For \(n=8\), for the modulo \((2^{n}-1)\) multiplication operation with (S1, S0) = (0, 0), A = 141, and B = 221, the final result is 51; for the modulo \((2^{n})\) multiplication operation with (S1, S0) = (0, 1), A = 141, and B = 221, the final result is 185; and for the modulo \((2^{n}+1)\) multiplication operation with (S1, S0) = (1, 0), A = 141, and B = 221, the final result is 64. Figure 13: Proposed structure of the radix-8 multi-modulus multiplier for 8 bits (\(n=8\)). To summarize, this section presents the design for the multi-modulus HMG and proposed a radix-8 Booth-encoding-based multi-modulus multiplier. The experimental results and comparisons of the hardware area, delay time, dynamic power, area-delay product (ADP), and power-delay product (PDP) with other methods reported in the literature are presented in the next section. Figure 14: Proposed improved parallel prefix adder of the radix-8 multi-modulus multiplier for 8 bits (\(n=8\)).