## 5 Findings and Analysis
### Implementation Insights and Results
These comprehensive parameters are indispensable for achieving a synthesis process that is both precise and efficient, finely tuned to the designated technology node. During this phase, the synthesis tool rigorously refines the netlist while adhering to established constraints, including area and power requirements. This meticulous approach ensures that the final implementation not only meets performance benchmarks but also aligns with specified design criteria. Ultimately, this focus on environmental factors, significantly enhances the overall performance and reliability of multiplier designs, thereby ensuring their effectiveness in practical applications. Upon completing the synthesis phase, it becomes imperative to extract vital performance metrics--area, delay, and power consumption--from the synthesized netlists. This quantitative analysis is not just beneficial; it is essential for understanding the operational efficiency of each design. By conducting a systematic comparison, we can uncover the benefits and drawbacks of various multiplier configurations, providing clear insights that are invaluable for real-world applications. Understanding these metrics is essential for accurately evaluating the performance of each design under practical conditions. Consequently, this thorough assessment informs subsequent modifications and optimizations aimed at significantly enhancing overall performance and effectiveness. Such insights are crucial in the design process, ensuring that the chosen configurations align seamlessly with the specific requirements of their intended applications. The compiled findings for the proposed hybrid systolic multiplier design are systematically summarized in Table 3, where they are compared against established configurations [19; 20; 43; 44; 50] for a field size of \(r=283\). This comprehensive table details several key evaluation criteria, including area, delay, power consumption, ADP, PDP, all of which have been meticulously derived from the synthesis outputs to reflect the design's operational characteristics. Furthermore, Figures 6-10 present graphical representations plotted on a logarithmic scale, which enhances the clarity of the comparative analysis by allowing for a more intuitive understanding of these metrics. These representations effectively underscore the strengths and weaknesses of the new design, providing critical insights into its performance across various evaluation criteria that are essential for assessing its suitability for the IoT applications tailored for disabled individuals. A thorough examination of the data presented in Table 3 and Figures 6 and 7 compellingly demonstrates that the proposed hybrid systolic multiplier outshines existing designs in terms of area usage and power consumption. The evidence is striking: area requirements have drastically decreased by an astonishing 99.6% to 99.8%. This remarkable reduction signifies not just a minor improvement but a transformative shift in the physical components required for implementation. Equally impressive are the advancements in power consumption. The proposed design achieves reduction in power consumption ranging from 94.2% to 96.9%. These substantial advancements in energy efficiency are not simply quantitative figures; they signify a design that is genuinely impactful in real-world contexts. This is especially vital in scenarios where resource constraints--like limited physical space and power supply--are critical factors. In summary, these outstanding results confirm that the new design not only optimizes area usage but also dramatically improves energy efficiency. This powerful combination makes it an outstanding choice for addressing the specific needs of resource-constrained IoT edge devices designed for individuals with disabilities. For those pursuing innovative solutions to improve accessibility and functionality, this hybrid systolic multiplier stands out as a compelling option that effectively tackles the challenges presented by modern assistive technologies.