## 2 Theoretical Background  
There are many mitigation methods to reduce the impact of radiation on the performance of a digital device [11; 12; 14]. Of course, technological methods, such as the appropriate doping of silicon, can be discussed to improve the mitigation properties [15]. Naturally, it is also crucial to ensure the adequate shielding of digital devices. Unfortunately, in many cases, these methods are insufficient and SEEs can still occur. In this situation, it is crucial that the digital system is properly designed to resist these phenomena. In many space missions, key digital-system elements are implemented in FPGA devices (telemetry systems, onboard computers and AI systems) [16; 17; 18; 19; 20]. This raises the question of mitigation methods targeting FPGA devices. An extremely important component of FPGA devices is the configuration memory. This is most often SRAM (Static Random-Access Memory), which stores information on how to configure and interconnect the available resources of the FPGA device in the logical structure. As a result of SEUs, the values of selected configuration bits in the configuration memory can be swapped, which will affect the resulting logical structure. This problem is illustrated in Figure 1.  
The primary mitigation method in this case is scrubbing, which involves'refreshing' configuration memory from an external source. Scrubbing techniques are the subject of many research papers [21; 22; 23; 24]. Radiation can also affect the logical structure itself. In this case, there are also mitigation techniques. The primary technique is the use of systems using Error Checking and Correction (ECC) [25]. Correction coding most commonly uses the Hamming code [26] or the Reed-Solomon code [27]. An extremely important method of mitigation is redundancy. The use of redundancy in mitigation processes involves replicating selected functional blocks or circuits several times in order to perform exactly the same task. In extreme cases, where the space mission is specifically exposed to significant radiation, entire units are duplicated. If the duplicated modules, at the same time, function in exactly the same way (the state of their outputs is the same), this means that there have been no SEE-induced errors in the operation of the modules. If, however, the signals on their outputs are different, this means that a fault must have occurred in one of the duplicated modules. Naturally, duplicating parts of a circuit, modules or entire devices several times is expensive. This raises the question of how many times a circuit fragment should be duplicated to ensure effective mitigation. It turns out that replicating the circuit twice only allows statements to be made that an SEE phenomenon has occurred but without the possibility of error correction. For this reason, triple redundancy (TMR, triple modular redundancy) is commonly used. In this approach, three identical and independent modules perform the same functionality. If one of them malfunctions due to an SEE, by comparing the state of the outputs of all three modules, the expected (correct) state of the module's outputs can be unambiguously determined by a voting process. Of course, a single fault is assumed. Thus, in order to realise TMR, it is necessary to have a voter comparing the outputs of the individual modules and realising the voting. The essence of TMR is illustrated in Figure 2.  
TMR is one of the basic mitigation techniques. It is the subject of many scientific papers [28; 29; 30; 31; 32]. It should be noted that one of the main drawbacks of this approach is the significant growth of the logical structure obtained. The use of TMR significantly increases the number of logical resources used. There are methods to reduce them [33; 34]. Naturally, it is also extremely important to adopt a strategy for using TMR in a project [35]. Figure 1: Impact of SEUs on configuration memory. As already mentioned, a key element of TMR is the voters. Voters in the voting process select the majority answer from triplicated modules.