# Performance Improvement of an NMP Mini Segway Using Sample and Hold Inputs
## 1 Introduction  
Non-minimum phase (NMP) systems refer to systems that have at least one unstable zero located in the open right half plane (in continuous-time domain) or outside of the unit circle (in discrete-time domain). Unstable zeros introduce additional phase lag [1] that limits stabilizing control gain and prevents further performance improvement. One way to avoid the NMP characteristics is to convert the continuous time NMP system to a discrete-time minimum phase (MP) system. Zero-order-hold (ZOH) was considered in [2] with a sufficiently large sampling period. The sampling period that results in a discrete-time MP system is called the feasible sampling period. However, the feasible sampling period of ZOH is often too large to capture the characteristics of a continuous-time system [3]; therefore, the technique using ZOH may not be feasible for control purposes. To find a feasible sampling period smaller than that of ZOH, other approaches were used, including impulse generator function [4], first order hold [5, 6], and fraction order hold [7, 8, 9, 10]. However, these approaches also have their limitations. Based on the discrete equivalent (DE) system theory in [11], three sample and hold inputs (SHIs) were proposed and studied in [12], and they are square pulse sample and hold input (SPSHI), forward triangle sample and hold input (FTSHI), and backward triangle sample and hold input (BTSHI). These SHIs have two design parameters: duty cycle (\(p\)) and sampling period (\(\delta\)). These three SHIs are capable of significantly reducing the smallest feasible sampling period over ZOH. Note that the DE system is a continuous-time system with the same state and output variables at sampling time instants as those of the original system, but the zero locations of the DE system depend on the selection of SHI parameters. Experimental validations were performed in [13], using a Quanser single-inverted-pendulum (SIP) system with a prototype controller, to study the capability of the proposed SHIs. It was discovered that by selecting the sampling period and duty cycle within the feasible region, the discrete-time controller with selected SHI is able to improve the closed-loop system performance significantly. Since the controller was implemented into a very sophistic microcontroller, the feasibility of implementing the proposed SHIs into an extremely low-cost microprocessor remains an open question, which is the topic of this paper. To be specific, this paper studies the performance improvement of a mini-Segway (MS) robot with a low-cost microprocessor (Arduino) using a dual-loop control scheme, where the inner-loop continuous-time controller stabilizes the MS system, making it feasible to use the proposed SHI, and the outer-loop discrete-time controller further improves the MS system performance. The MS is a two-wheel self-balanced robot and is a multi-input-multi-output (MIMO) nonlinear system. It is NMP after linearizing about the upright equilibrium point. Due to its under-actuated nature, this platform is widely used for controller design and implementation studies, including PID controllers [14; 15; 16; 17; 18; 19], fuzzy logic controllers [20; 21; 22], Fuzzy combined with PID [23], adaptive control [24], and linear quadratic regulation (LQR) control [19; 25; 26; 27]. There are many articles that have investigated complex and strong control methodologies to NMP systems, such as [28]. In this study, the dual-loop control architecture, proposed in [13], was adopted. The continuous-time inner-loop LQR was implemented at a 100 Hz sample rate, and a discrete-time outer-loop LQR with the selected SHI was implemented at 5 Hz. The idea is to utilize the inner-loop controller to stabilize the MS system and convert the resulting NMP MS system into a discrete-time MP system with the help of proposed SHIs. Consequently, a high gain outer-loop can be used to further improve closed-loop system performance. It is obvious that the overall system performance is affected by both inner and outer-loop controllers.