# An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System
## 3 The Data Storage and Exchange Method Based on Superscalar Pipeline
### The Three-Dimensional Cross-Mapping Method Based on Equal Division of Sub-Matrix with Dual-Channel
#### 3.1.1 The Matrix Block Three-Dimensional Mapping with Dual-Channel  
The amount of both the raw SAR imaging data and the intermediate processing result data is \(N_{A}\times N_{R}\times 64\) bit, i.e., the number of range data points is \(N_{R}\), the number of azimuth data points is \(N_{A}\), and the data width of each point is 64 bit. since the SAR imaging processing requires multiple FFTs, both and are positive integer pwoer of 2.  
Perform matrix block of the raw data as shown Figure 5. The matrix is divided into \(M\times N\) sub-matrices. The size of the sub-matrix is \(N_{a}\times N_{r}\), i.e., \(N_{a}=N_{A}/M\), \(N_{r}=N_{R}/N\). The sub-matrices need to be mapped to one row in both DDR3A and DDR3B respectively, so that, \(N_{a}\times N_{r}=2C_{n}\), where \(C_{n}\) is the number of columns of the storage array in DDR3.  
The SAR data volume of 16 k \(\times\) 16 k \(\times\) 64 bit is the more common data volume in the current SAR real-time processing system, so this paper targets the 16 k \(\times\) 16 k \(\times\) 64 bit data volumes for the study. The sub-matrix size is \(N_{a}\times N_{r}=64\times 32=2048\). The sub-matrix has 2048 points, which is exactly the sum of the lengths of one row in DDR3A and one row  
Figure 5: Schematic diagram of data storage and exchange method based on superscalar pipeline.  
in DDR3B respectively, and can be mapped to DDR3A and DDR3B with an equal division in three dimensions.  
After the matrix is blocked, the matrix are mapped in a dual-channel three-dimensional manner, and the data in each blocked sub-matrix are mapped to a row in DDR3A and DDR3B in equal division. Each row of the SAR data matrix is assumed to be the range and each column is the azimuth. The data in the range direction are called the range line and the data in the azimuth direction are called the azimuth line, so there are \(M\) range lines and \(N\) azimuth lines. Using the three-dimensional mapping method according to Figure 6, firstly, 512 sub-matrices on the 0 th range line are mapped to the 0 th row of bank0 to bank7 in DDR3A and DDR3B, respectively, in a cross-bank mode, and since the number of sub-matrices on the 0 th range line is larger than the number of banks, after mapping to bank7, then return to bank0 and start from bank0 row 1. When starting the mapping; the next is bank1 row 1, bank2 row 1...bank7 row 1. At present, all the rows 0 to 1 of bank0 to bank7 are mapped, and then the mapping continues from bank0 row 2, bank1 row 2, bank2 row 2...bank7 row 2, etc., until the 512 sub-matrices on the range line 0 are mapped.  
By calculation, the 512 sub-matrices on the 0 th range line are mapped, which requires 64 rows in each bank. Therefore, as shown in Figure 6, the 512 sub-matrices on the 0 th range line will be mapped from row R = 0 to row R = 63 in banks0-7 of DDR3A and DDR3B.  
To ensure that the azimuth access also satisfies the cross-bank principle, the sub-matrices on the 1 st range line will be mapped from bank1. bank1 row 64, bank2 row 64... bank7 row 64, bank0 row 64, i.e., mapped to bank1-bank7-bank0, respectively. The mapping starts from line 64 within bank. This is followed by bank1 row 65...bank7 row 65, bank0 row 65, and the subsequent range lines are also mapped according to the above rules. Until then, all data can be mapped to DDR3A and DDR3B at the same time.