## 3 Results  
The simulation was carried out with the University of California, Berkeley's Predictive Technology Model (PTM) 65 nm nodes and a TSMC 28 nm High-Performance Computing (HPC) library. Table 1 shows values of a PTM 65 nm interconnect. Table 2 shows values of a TSMC 28 nm interconnect. Notably, 65 nm node values are used to verify the processes of the SSTC and RSP model. Due to the completed library files of 28 nm nodes, we compare the SSTC model result with parameters extracted from the backend. The simulation adopts the Cadence process to work out. INNOVUS and QRC are used to simulate the backend mentioned in the SSTC model. SPECTRE is used for Hspice simulation. Additionally, MATLAB is used to calculate the parameters mentioned in the models and simulate the frontend mentioned in the RSP model and RSHARQ. Firstly, 65 nm node simulation is presented. The driven voltage is set to 1.2 V, the equivalent drive resistance is set to 156 \(\Omega\), and the equivalent load capacitance is set to 64 fF. The wire length is set as 500 \(\upmu\)m.  
Directional arrows are used to indicate the bestirring source. For example, \"-\" means the signal of the wire is not changing, \"\(\uparrow\)\" means the signal of the wire is changing from low voltage to high voltage, and \"\(\downarrow\)\" means the signal of the wire is changing from high voltage to low voltage. We use directional arrow aggregates to express the bestirring source on the three-wire coupling model, such as (-, \(\uparrow,\downarrow\)). Table 3 shows the three-wire coupling model spice simulation results on a 65 nm node. From Table 3, the delay can be divided into (120, 110, 95, 80, 74, -). For convenience of description, the delay around 120 ps called G6 delay, which occurs in the middle line with two different signals changing direction in the side lines, as (\(\uparrow\), \(\downarrow\), \(\uparrow\)). Similarly, the delay around 110 ps is called G5 delay, the delay around 95 ps is called G4 delay, the delay around 80 ps is called G3 delay, the delay around 74 ps is called G2 delay, and the delay around 0 is called G1 delay. With Formula (8), the G6 frequency, denoted as G6. Freq, is 0.4/120 ps = 3.3 GHz. Similarly, G5. Freq is 3.6 GHz, and G4. Freq is 4.2 GHz. \begin{table}
\begin{tabular}{c c c} \hline \hline  & **Dimensions/\(\upmu\)m** & **Material** \\ \hline w = 0.14 & s = 0.14 & \(\rho=2.2\times 10^{-8}\Omega/\text{m}\) \\ h = 0.20 & t = 0.35 & \(\varepsilon_{\tau}=2.2\) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: PTM 65 nm interconnect values. \begin{table}
\begin{tabular}{c c} \hline \hline  & **Materials** \\ \hline w = 0.05 & s = 0.05 & \(\rho=4.02\times 10^{-8}\Omega/\text{m}\) \\ h = 0.085 & t = 0.09 & \(\varepsilon_{\tau}=2.63/3.55\) \\ \hline \hline \end{tabular} \({}^{1}\) In 28 nm library, the \(\varepsilon_{cc}\) of C\({}_{c}\) is 2.63 and the \(\varepsilon_{\text{eg}}\) of C\({}_{g}\) is 3.55.  
\end{table} 
Table 2: TSMC 28 nm interconnect values. If the working frequency is in the range of (G5. Freq, G6. Freq) and not equal to G6. Freq, all situations of G6 delay lead to error. The system error is denoted as a G6 crosstalk error. Similarly, a system error with a working frequency in the range (G5. Freq, G4. Freq) and not equal to G5. Freq is denoted as a G5 crosstalk error. As shown in Table 3, the G6 crosstalk error rate is 0.97%, and the G5 crosstalk error rate is 5.21%. In Table 4, we simulate the relationship between bandwidth and wire dimensions (spacing and length), which can be modified by the designer. A B1 rate means bandwidth improvement rates between bandwidth, with the wire spacing changing and the original bandwidth with G6. Freq. A B2 rate means bandwidth improvement rates between bandwidth with G5. Freq and bandwidth with G6. Freq under the same spacing. Table 4 shows that both the B1 rate and B2 rates increase with the decrease of wire spacing. However, with spacing decreasing, the maximum frequency is lower as well. Then, we give simulation results on 28 nm nodes.