# Analysis of Pre-Driver and Last-Stage Power--Ground-Induced Jitter at Different PVT Corners
## 5 Conclusions  
This paper has studied and analyzed the PGSIJ contribution of the pre-driver and last stage of a cascaded inverter IO buffer at three different PVT corners. The shared and decoupled power and ground supply cases were also investigated and compared.  
The contribution of the pre-driver's PGSIJ can be as important as that of the last stage at the worst corner. Finally, the IO buffers are more sensitive to jitter noise at the SS corner and it is important to develop a specific IBIS-like model to capture the pre-driver's PGSIJ in order to speed up transient simulation. The impact of the PSIJ TF superposition of a multiple-stage IO buffer powered by distinct power supplies depends on the amplitude of the supply voltage variations. The PSIJ or delay superposition of each stage depends on the amplitude variations where the I-V and C-V functions of the transistor can be linearly approximated.  
The findings which are reported by the analyzed and simulated data in this paper urge the improvement of the equivalent circuit IBIS-like and/or parametric curve fitting nonlinear dynamic behavioral modelling methodology in capturing power and signal integrity distortion under separate power and ground voltage variations in order to not only speed up PSIJ characterization, but also to cope with the advance in recent PDN and IO buffer designs. For example, the characterization of voltage-time IBIS data under different PVT corners can be explored to derive an approximation of the PSIJ TF.  
Figure 16: Last-stage case: correlation between \(J_{m}\) and \(J_{s}\) based on the superposition of (10). (**a**–**c**): small-signal two tones. (**d**): large-signal case.  
**Author Contributions:** Conceptualization and methodology, M.S., R.M., W.D. and H.B.; software and validation, M.S., W.D. and H.B.; formal analysis, M.S. and W.D.; investigation, M.S. and W.D.; data curation, M.S. and W.D.; writing--original draft preparation, M.S.; writing--review and editing, M.S., R.M., W.D., H.B. and E.R.; supervision, R.M., W.D. and H.B. All authors have read and agreed to the published version of the manuscript.  
**Funding:** The Foundation for Science and Technology (FCT) under the ICT (Institute of Earth Sciences) project UIDB/04683/2020; and Portuguese Funds through the Foundation for Science and Technology (FCT) under the LAETA project UIDB/50022/2020.  
**Institutional Review Board Statement:** Not applicable.  
**Informed Consent Statement:** Not applicable.  
**Data Availability Statement:** Not applicable.  
**Acknowledgments:** First author would like to thank reviewers and collaborators from different Institutes and Universities for their comments and suggestions that improve the quality of the manuscript.  
**Conflicts of Interest:** The authors declare no conflict of interest.  
**Abbreviations**  
**IO**: **Input-Output**  
PVT  
Process, voltage, and temperature  
P/G  
Power/ground  
PSV  
Power supply voltage  
PSJJ  
Power supply-induced jitter  
PGSIJ  
Power ground supply-induced jitter  
SiPI  
Signal and power integrity  
PDN
Power delivery network  
PCB  
Printed circuit board  
I-V  
Current-voltage  
C-V  
Capacitance-voltage  
IBIS  
input-output buffer information specification  
TL  
Transistor level  
SS  
Slow-Slow  
TT  
Typical-Typical  
FF  
Fast-Fast  
TF  
Transfer function  
p2p  
peak-to-peak  
EW  
Eye width  
EH  
Eye height