# FPGA-Based Manchester Decoder for IEEE 802.15.7 Visible Light Communications
## 2 Architecture of the Receiver
### The Synchronization of the Receiver
Given that \(s_{i}\) is the first sample of the current slice, affected by the phase error \(\varphi_{e}\), the next positioning is achieved by starting the reading of the slice from the sample \(s_{i+l}\), where \(l\) is obtained as:  
\[l=\text{int}\Big{[}T_{b}f_{c}\Big{(}1+\frac{\varphi_{e}}{360^{\circ}}\Big{)} \Big{]}=N+\text{int}\Big{(}\frac{\varphi_{e}}{360^{\circ}}N\Big{)}=N+z \tag{8}\]  
In (8) \(\varphi_{e}\) is expressed in deg (\({}^{\circ}\)), int(\(x\)) is the nearest integer to \(x\), and \(N\) represents the number of samples per bit. The increment \(l\) is composed by \(N\), i.e., the bit length, plus \(z\) that can be positive or negative depending on the sign of \(\varphi_{e}\), and ranges in \(\pm N/2\). In a practical implementation, it can be beneficial to reduce the variability of \(z\) among subsequent bits. This precaution can avoid, for example, that a sudden noise in a single bit could compromise the synchronization. A simple approach, whose efficacy will be discussed in Section 3, consists in allowing for the next bit a phase correction \(z\) not above a given percentage of \(N\). From Figure 3 we see that, as long as the phase error \(\varphi_{e}\) is between \(-90^{\circ}\) and \(+90^{\circ}\), the decision about the bit value is correct; on the other hand, a higher phase error results in a wrong bit value, an incorrect calculation of the phase error \(\varphi_{e}\), and thus in an incorrect positioning of the next bit. In practice, a phase error higher than \(\pm 90^{\circ}\) causes the receiver to lock over the second commutation edge of the bit, which is an unwanted condition. However, once the correct synchronization is achieved, it is easily maintained as long as the SNR is sufficiently high. Unfortunately, at the beginning of the sequence the synchronization  
Figure 3: Relation between the position of the rising edge with respect to the tentative bit start (phase error \(\varphi_{e}\)) and the phase \(\varphi\) calculated through (7). Blue and magenta curves refer to the bit values of ‘0’ and ‘1’, respectively. A selection of waveforms are reported on top (bit ‘1’) and bottom (bit ‘0’) of the graph in the position of the phase error they represent. \begin{table}
\begin{tabular}{c c c} \hline \hline \multirow{2}{*}{**Calculated Phase \(\varphi\)**} & **Bit** & **Error Estimation** \\  & **Decision** & \(\varphi_{e}\) \\ \hline \(-180^{\circ}\leq\varphi<0^{\circ}\) & 1 & \(\varphi+90^{\circ}\) \\ \(0^{\circ}\leq\varphi<180^{\circ}\) & 0 & \(90^{\circ}-\varphi\) \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Bit decision and phase error derived from calculated phase. has still to be achieved: the receiver has to \"guess\" the position of the first bit without any other info (see Figure 2), and a phase error higher than \(\pm 90^{\circ}\) can happen. The issue is solved by transmitting a known \"synchronization\" sequence of some bits at the beginning of the data packet (for example, eight zeroes). With the knowledge of the bit value, the receiver can correctly calculate the phase error \(\varphi_{e}\) (see Figure 3) over the full \(\pm 180^{\circ}\) range, thus achieving the correct synchronization.