# All-Digital Computing-in-Memory Macro Supporting FP64-Based Fused Multiply-Add Operation
## 5 Conclusions  
This paper presents a novel all-digital CIM macro-**DCIM-FF** to complete FP64-based fused multiply-add (FMA) operations for the first time, which can provide correct rounded implementations for normalized/denormalized inputs in round-to-nearest-even mode and round-to-zero mode, respectively. We have verified the functionality of **DCIM-FF**  
Figure 6: Power consumption of **DCIM-FF** with various supply voltages (**a**). Area overhead of **DCIM-FF** with various supply voltage (**b**).  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**FMA Designs** & **Cycles** & **Delay (ns)** & **Area (\(\mu\)m\({}^{2}\))** & **Power (mW)** & **Throughput (MOPS)** & **Power Efficiency (TOPS/W)** \\ \hline [30] & 3 & 3.40 & 708,590 & - & 294 & - \\ \hline [31] & 3 & 3.34 & 286,766 & 35.2 & 291 & 8.27 \\ \hline [32] & 4 & 3.61 & 1,803,624 & - & 277 & - \\ \hline [33] & 8 & 3.24 & 149,000 & 17.8 & 308 & 17.3 \\ \hline [34] & 1 & 1.08 & 259,005 & 425 & 926 & 2.18 \\ \hline
**This work** & 9 & 60 & 51,703 & **0.62** & 16.7 & **26.9** \\ \hline \hline \end{tabular}
\end{table}
Table 3: Comparison of the proposed **DCIM-FF** with previous works.  
through pre-production simulation, and we have synthesized the **DCIM-FF** macro with a 55 nm technology development kit. The power efficiency of **DCIM-FF** can reach up to 26.9 TOPS/W with 0.12-2.16 mW at 50-150 MHz operating frequency. Circuit-level simulation results show that **DCIM-FF** achieves significant power efficiency improvement and less area overhead compared with previous FMA designs. This work completes FP64 arithmetic based on the digital CIM technology and proposes a novel architecture for accelerating FMA operation, which exhibits approximately a 15-fold increase in power efficiency compared with the previous FMA design (1.64 TOPS/W) [35]. While DCIM-FF is insufficient in terms of throughput, in future work, we can reduce the computation cycles of DCIM in the normalization operation and adopt the pipeline architecture in the adder trees for other long-stage logical operation modules to achieve a higher operating frequency and throughput. Moreover, **DCIM-FF** paves a novel pathway for subsequent implementation of FP64-based MVM operation by CIM. **DCIM-FF** can be used as a MVM computing unit, since MVM is essentially a repeated multiply-add operation. The use of CIM to achieve FP64-based MVM operation will be conducive to the application of CIM technology for hyperscale scientific computing.  
Conceptualization, D.L., K.M. and B.P.; methodology, K.M. and B.P.; software, K.M.; validation, D.L. and K.M.; formal analysis, K.M.; investigation, K.M.; resources, B.P. and W.L.; data curation, K.M. and L.L. ([PERSON]); writing--original draft, K.M., L.L. ([PERSON]) and B.P.; writing--review and editing, K.M., L.L. ([PERSON]), B.P. and L.L. ([PERSON]); visualization, K.M. and W.L.; supervision, B.P. and W.K.; project administration, B.P.; funding acquisition, B.P. All authors have read and agreed to the published version of the manuscript.  
This research was supported partly by The Laboratory Open Fund of Beijing Smart-Chip Microelectronics Technology Co., Ltd., and partly by the National Natural Science Foundation of China (62001019).  
We currently have no data supporting results.  
The authors declare no conflict of interest.