# Hardware Update through Digital TV Signals  
[PERSON]  
1 SIDIA Institute of Science and Technology, Manaus 69000-000, Brazil; [EMAIL_ADDRESS] (R.R.d.O. ); [EMAIL_ADDRESS] (F.A.S.G.) [PERSON]  
1 SIDIA Institute of Science and Technology, Manaus 69000-000, Brazil; [EMAIL_ADDRESS] (R.R.d.O. ); [EMAIL_ADDRESS] (F.A.S.G.) [PERSON]  
4 CTC/LISHA, Federal University of Mana Catarina, Florianopolis 88010-300, Brazil; [EMAIL_ADDRESS]  
[PERSON]  
25 School of Computer Science, University of Manchester, Manchester M13 9 PL, UK 555  
[PERSON]  
36 TPV Technology, Manaus 69000-000, Brazil 56 UTFO  
Given what was presented, one may notice that AVC/H.264-based systems cannot immediately incorporate the benefits of HEVC due to legacy hardware. However, such flexibility could be achieved if DTV receivers could perform tasks through reconfigurable devices (e.g., a field-programmable gate array (FPGA)) instead of ASICs. Currently, the semiconductor industry and open core communities have boosted the use of FPGAs. It is worth noticing that they even provide hardware description source codes (e.g., VHSIC hardware description language (VHDL) [7] and Verilog [8]) for many applications (e.g., crypto cores, DSP cores, and encoder/decoder cores), which are available for download and immediate use in project solutions [9]. Depending on the target market, current FPGA technologies are already a good option. The main reason for this is the amortization of non-recurring engineering (NRE) costs among customers for each integrated circuit (IC) family [10; 11; 12]. Finally, such devices can even be used for implementing entire systems [13; 14]. In addition, specifically regarding the pay TV market, FPGA solutions are already very interesting and present some advantages. As cable and satellite operators must provide devices to all subscribers to offer services in vertical markets, technology advancements usually result in new receivers. Consequently, the proposed approach could decrease the costs necessary for maintaining existing consumers in the long run, since updating receivers may be cheaper than replacing them. Aside from that, this also aligns with the fast development and deployment cycles currently seen in the DTV world, while the legacy hardware problem is also alleviated. Consequently, the possibility of reconfigurable hardware platforms becomes appealing and may devise new directions regarding DTV receiver design. The presented observations are the inspiration for the present work, which proposes a new approach for hardware updates with DTV signals as the transport infrastructure, named hardware reconfiguration through digital television (HARD). In the context of a DTV system, the reconfiguration bitstream can be regarded as a regular data broadcast along with a high-definition television (HDTV) program, as shown in Figure 1.  
A DTV system comprises several subsystems, including data preparation for transmission, complete signal reception, and subsequent content filtering. In the transport stream (TS) step, audio, video, and data, including FPGA bitstreams, are interleaved, engendering a multiplexed DTV streamflow [15]. Finally, in the transmission step, the resulting signal is modulated and sent through a DTV channel. At the receiving side, each device in range detects and decodes the transmitted content. Such a process results in the complete extraction of the FPGA core  
Figure 1: FPGA bitstream broadcast in a DTV environment. data stream, which is then reassembled in a persistent storage module. After this step, the FPGA module is reconfigured. This work deals with a generic hardware update in DTV environments, where receivers do not need to leave the user's premises and extend DTV channels by introducing a way of transmitting synthesized hardware data. It can be employed in a wide range of future designs regarding intelligent hardware architectures, and it can boost the use of hardware reconfiguration in embedded solutions (e.g., DTV receivers).