# Passive Power Line Communication Filter Design and Benchmarking Using Scattering Parameters
## 3 Filter Performance Measurement
### Insertion Loss  
In laboratory environments, the most straightforward method of testing the filters is by measuring its insertion loss (transfer function) using a VNA (vector network analyzer) [22] or an FRA (frequency response analyzer). In general, an FRA will allow lower frequency measurements and are robust to use in conjunction with power line couplers. Figure 5 is an offline insertion loss measurement setup [35] and Figure 6 is an online impedance measurement setup which uses line couplers [36], AC power supply, and load impedance. Figure 4: PLC filters’ insertion loss and SPICE simulation. The practical implementation of the test setup from Figure 6 can be challenging due to non-standardized power supply impedance \(Z_{S}\) and load impedance \(Z_{L}\) values at PLC communication frequencies. Passive impedance matching circuits can be used to measure the insertion loss of the filter when the impedance is different to 50 \(\Omega\). The main problem of passive impedance matching circuits is that the impedance matching is achieved only at a certain frequency; hence, to obtain a proper insertion loss with impedances different to 50 \(\Omega\), several matching circuits should be used. Another way of performing non-50 \(\Omega\) measurements is to use matching transformers also known as baluns [37; 38]. Some of the FRA models available on the market have separate ports for measuring and injecting the signal to the DUT (device under test) [39] so that an impedance matching circuit is not needed and the results with loading impedances different to 50 \(\Omega\) are properly measured. In order to provide a controlled input impedance and noiseless power supply, a line impedance stabilization network (LISN) and two PLC couplers were used. The test setup from Figure 7 is derived from PLC and EMC standards [17; 40] and it has the following features:  
Figure 5: PLC filter offline insertion loss measurement setup. (**a**) Common mode measurement and (**b**) differential mode measurement. Figure 6: PLC filter online insertion loss test setup version 1. * Isolated AC power supply (isolation transformer);
* Symmetrical V-LISN that allows symmetrical measurements on phase and neutral; the unused half of the LISN is terminated with 50 \(\Omega\);
* \(Z_{\text{in}}\) and \(Z_{\text{L}}\) can be adjusted in order to obtain the required impedance at the port of the filter. Power line impedances encountered in real situations are 4 to 15 times lower than those of commercially available LISN. Figure 8 graphically presents the impedance from 20 kHz to 150 kHz of an 50 \(\Omega\)/50 \(\upmu\)H + 5 \(\Omega\) LISN [40] and the power line impedance measured experimentally in five field condition cases [41; 42; 43; 44; 45]. The adaptive impedance circuit from Figure 9 can be used to introduce \(Z_{\text{in}}\) and \(Z_{\text{L}}\) closer to values encountered in field conditions [46]. Figure 10 plots the impedance \(|Z|\) and phase shift \(\varphi\) of half of the circuit (between L' and PE or N' and PE) from Figure 9; ideal components were used in the SPICE simulation. Figure 8: Power line impedance measurements compared to LISN impedance [40; 41; 42; 43; 44; 45]. Figure 7: PLC filter online insertion loss test setup version 2. The power consumption at the mains frequency f = 50 Hz of the adaptive impedance circuit from Figure 9 is P \(\approx\) 1 kW and thus much lower compared to the power consumed if a purely resistive 2 \(\Omega\) load is used, P = 26.45 kW. The power consumption computations are detailed in Equations (1)-(11). \[Z=\sqrt{R^{2}+\left(X_{L}-X_{C}\right)^{2}} \tag{1}\]  
\[R=1\;\Omega \tag{2}\]  
\[X_{L}=2\;\pi\,\mathrm{fL}=1.5\;\mathrm{m}\Omega \tag{3}\]  
\[X_{C}=\frac{1}{2\;\pi\,\mathrm{fC}}=95.5\;\Omega \tag{4}\]  
\[Z=95.5\;\Omega \tag{5}\]  
Figure 5:0  
Figure 5:1  
Figure 5:2  
Figure 5:3  
Figure 5:4  
Figure 5:5  
Figure 5:6 Impedance and phase plot for half of the adaptive impedance circuit. Figure 5:7 Adaptive impedance circuit for \(Z_{\mathrm{in}}\) and \(Z_{\mathrm{L}}\).