# Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications
## 1 Introduction  
Wireless technologies and services based on these technologies have been spreading rapidly in recent years: coverage of 4G networks increases, 5G technologies are being developed, local area networks are advancing and wireless network at home, workplace and public places is a necessity. The number of Internet of Things (IoT) devices and personal wireless gadgets is rapidly growing. Also, Internet of Vehicles (IoV) and intelligent transport system technologies are emerging. As reports show, wireless standards for IoT and IoV applications, similarly to most of other current and developing wireless standards, are using frequency bands, which are spread from hundreds of megahartzes up to 6 GHz [1; 2; 3; 4].  
In order to support the multitude of these frequency bands and standards in a single device, integrated circuits (IC) of multiband wireless transceivers are used. Such transceivers are also used in software defined radio, which is becoming more popular in the light of fast developing wireless technologies due to one of its main ideas--the usage of the same hardware for the implementation of different wireless standards, which enables a fast adaptation of the existing equipment to new and developing technologies while reducing the price of the system [3].  
One of the main blocks of a multiband transceiver is a high tuning range frequency synthesiser, used as local high frequency signal oscillator. Phase locked loop is usually used as a frequency synthesiser and there are two main classes of phase-locked loops: conventional (charge-pump) phase locked loop and all-digital phase-locked loop.  
To save power, chip area and cost, newer integrated circuit manufacturing technologies are being used. But the implementation of the conventional frequency synthesiser, which is analog in most part, in nanometric technologies is becoming more complicated because it is difficult to ensure the parameters of the synthesiser for wireless applications (e.g. operating frequency, frequency tuning range, phase noise level) due to decreasing supply voltage, increasing leakage currents as complementary metal-oxide-semiconductor (CMOS) technology step decreases. Therefore, integrated circuits of all-digital frequency synthesisers are gaining more attention, because these synthesisers, due to their digital nature, don't have the flaws typical of conventional synthesisers.  
However, some of the currently most advanced integrated circuits of multiband transceivers are still using conventional frequency synthesisers [5; 6; 7; 8] and are implemented in technologies no smaller than 65 nm. New commercial transceivers have been introduced in 28-7 nm technologies [9], but due to the small amount of publicly available technical data, it can only be concluded that they have a limited application scope and have a smaller frequency tuning range, compared to transceivers, which are implemented in more mature technology nodes. This shows that structures of the all-digital frequency synthesiser, their constituting blocks and their models are not sufficiently researched and described. Also, there is a lack of research regarding parameter estimations of all-digital frequency synthesisers and their main blocks, especially for applications in the fields of IoT and IoV.  
Therefore, the aim of this work is to present a structure of the all-digital frequency synthesiser for multiband transceiver for IoT and IoV applications that is suitable for implementation in nanometric and submicron technology nodes: the model of \(s\)-domain all-digital synthesiser is discussed, noise sources of the frequency synthesiser and contribution of main blocks to overall phase noise level of the synthesiser are analysed, requirements for main blocks are defined and a structure of synthesisers, which meets defined requirements, is proposed.