# Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions
## 5 Conclusions  
Virtual Coarse-Grained Reconfigurable Architectures can benefit from partial reconfiguration. If certain components can be reconfigured on their own, reprogramming can be drastically accelerated in comparison to changing the configuration of entire FPGA. Furthermore, an excessive overhead associated with spatial distribution of multiple variants within the same configuration can be avoided. Due to the construction of Xilinx FPGAs, the usage of the mechanism is restricted. The generic VCGRA model proposed in this study presents how and under what assumptions overlay designs can be divided into static and reconfigurable partition parts in order to effectively use partial reconfiguration.  
Development productivity can be increased by exploiting module relocation. Same placement and routing results can be reused at multiple positions within the same or across multiple designs. Relocation of partial bitstreams reduces the number of required implementation runs and configuration data storage space. Having numerous instances of identical modules, virtual CGRAs with homogeneous processing elements are prime beneficiaries of these advantages.  
Partial reconfiguration implies assigning logical modules to certain physical structures in the FPGA. VCGRAs, based on the most popular 2-D mesh pattern distribution of individual partition blocks in chip, have a crucial impact on routing feasibility and net delays. Taking that into consideration, proper partition floorplanning is essential in such designs, even more so considering that module relocation is only possible between identical partition blocks.  
The floorplanning problem for virtual CGRA with relocatable partitions can be divided into two separate tasks--finding homogeneous regions in FPGA fabric and assigning  
Figure 10: Normalized values of minimization objective-function (lower is better) and floorplanning times for different array sizes.  
individual partitions to certain locations. The two-stage solution presented in this study is compatible with Xilinx Vivado tools and capable of automated floorplan generation. The proposed partition to the PBlock assignment approach based on modified breadth-first search with penalties for direction inconsistencies followed by a local 2-opt optimization is drastically faster than state-of-the-art solutions and offers comparable quality of results. Although the difference in the floorplanning time for small arrays might be irrelevant in comparison to placement and routing time, a gain of several minutes can be obtained in the case of larger designs. The offered speedup is crucial considering that VCGRAs are usually used either as prototyping platforms or as a method to increase development productivity in FPGA-based systems.  
Although the proposed methodology of mapping CGRAs onto FPGAs with relocatable reconfigurable partitions imposes multiple restrictions on the abstract architecture, it was designed acknowledging trends in CGRA design. Therefore, it should be applicable to many contemporary VCGRAs. In particular, QUKU [4] seems very well fitted to the proposed model, as it uses multiple overlay configurations based on combinations of different variants of processing elements connected in a 2-D mesh.  
Conceptualization, Z.M.; methodology, Z.M.; software, Z.M.; data curation, Z.M.; writing--original draft preparation, Z.M.; writing--review and editing, R.K.; supervision, R.K. All authors have read and agreed to the published version of the manuscript.  
This research received no external funding.  
Not applicable.  
The authors declare no conflict of interest.