# Secure ECDSA SRAM-PUF Based on Universal Single/Double Scalar Multiplication Architecture
## 4 Hardware Architecture
### The Architecture of Soft-Decision RM Code
The data path of the recursive algorithm is illustrated in Figure 3. The likelihood estimate value \(L\) computed by the auxiliary data algorithm serves as the input to the ALU, initiating the recursion process, which is governed by the state machine. During the calculation state, the ALU performs the corresponding calculations, and the results are output into the SRAM cache. Subsequent iterations retrieve the SRAM data, which are then returned to the ALU for further computations. In the jump state, the ALU transfers data from one address in the SRAM to another. The cycle of transitioning between the calculation state and the jump state continues until the soft-decision of the RM code is completed, ultimately outputting \(L^{*}\). The states involving pushing and popping the stack--namely, \(L(1)\) pushing the stack, \(L(2)\) pushing the stack, and popping the stack--serve as jump states responsible for the logic control of the recursive algorithm. In the pushing states, if the current execution transition corresponds to pushing the stack, the parameters of the current recursion round (_next_state_, \(r\), \(m\)) are saved and pushed into the stack. Subsequently, the state machine restarts from the IDLE state, initiating a new round of recursion. Conversely, in the state of popping the stack, the state machine reads the saved parameters (_next_state_, \(r\), and \(m\)) from the previous round of recursion in the stack. The machine then continues the recursion until the entire recursive process is completed. The five states, \(L^{*}_{r=0}\), \(L^{*}_{r=m}\), \(L(1)^{*}\), \(L(2)^{*}\), and \(L^{*}\), belong to the calculation state and correspond to the computation of the variables in Algorithm A3. These states entail the accumulation of the F function, G function, and SoftDecision_Decode_Rep function. The ALU performs these calculations and selects the current operation through the \(opr\) signal associated with the current state. Figure 3: RM code soft-decision state machine. The speed of the RM code soft-decision relies on the amount of SRAM read and write operations, making it essential to evaluate the hardware speed based on these factors. Therefore, an analysis of the data and address allocation of the SRAM is conducted. In each state of the state machine, the addresses and lengths of SRAM read and write operations vary depending on the current \(m\) value and state. Consequently, the address generator module generates SRAM-accessible addresses corresponding to the current state of the state machine and the current \(m\) value. The states \(L^{(1)}\) and \(L^{(2)*}\) exhibit no data dependency under the same round of recursion, enabling them to share the same storage space. With SRAM being 32 bits wide, the selected bit width for \(L\) and each intermediate variable has a 16-bit length, ensuring sufficient data precision without risking overflow. When mapping addresses, two adjacent 16-bit segments are placed into one address. For \(m=8\), the required SRAM space for the RM code soft-decision hardware is \(512\times 4\times 2\) Bytes = 4 KB. Following the SRAM analysis, the soft-decision speed of the RM code can be calculated based on the data volume in the SRAM. For each \(r\), there are 20 reads and writes, resulting in \(512\times 20=10,240\) cycles for all \(m\). Since \(256+128+64+\ldots=512\) groups for all \(m\), the total number of SRAM reads and writes required for the entire recursion is \(512\times 20=10,240\) cycles. Completing four soft-decisions of the RM code takes \(10,240\times 4=40,960\) cycles. Factoring in the extra time for other logic, the total required cycles amount to approximately \(41,000\) cycles.