## 3 MIGOU Platform
### Design and Implementation  
The hardware architecture of the MIGOU platform is presented in Figure 1. This diagram shows the main electronic components that constitute the system, as well as their connections. Both the architecture design and the selection of components were carried out according to the previously presented design criteria. Atmel AT86 RF215 was the component selected to provide the platform with hybrid radio capabilities. As shown in Figure 2, this device is comprised of two highly integrated radio transceivers, which operate in the sub-1 GHz and 2.4 GHz bands. Moreover, each of these transceivers supports two operating modes, which do not need to be the same. The ability to switch between these two modes of operation is what allows our platform to operate as a traditional node or as an SDR system. Figure 1: MIGOU platform hardware architecture. On the one hand, in baseband (BB) mode, the AT86 RF215 works as a COTS transceiver. In this configuration, the selected transceiver is internally paired with an optimized baseband core (BBC) that supports a wide variety of data rates with three modulation schemes. This allows for a highly efficient implementation of multiple PHY layers. In this mode, the BBC controls the radio and processes the data encoding/decoding for transmitting (TX) and receiving (RX) from the internal frame buffers. On the other hand, in the I/Q mode, the radio is controlled from an MCU via a serial peripheral interface (SPI) and the I/Q data stream is routed directly between the selected radio and a serial low voltage differential signal (LVDS) interface. This configuration allows for the use of a baseband processor for implementing custom SDR features. We chose the SmartFusion2 as a control unit and mixed-signal processing backend. This device integrates a microcontroller subsystem (MSS), based on an ARM Cortex-M3 processor, and a flash-based FPGA. This kind of FPGA has been proved to have faster wake-up times and to be more energy-efficient than SRAM-based FPGAs [29]. In addition, the SmartFusion2 family, unlike the SmartFusion, supports a low-power mode of the FPGA fabric, which is known as the Flash*Freeze mode. This is the technology selected to provide our platform with low-power programmable logic resources. Furthermore, the ARM Cortex-M3 and the FPGA communicate internally through an AMBA high-performance bus (AHB). This bus is widely used to connect peripherals, memories, and cores in SoCs, and it provides a bandwidth of up to 16 Gbps, minimizing potential data bottleneck problems, and therefore, guaranteeing a flexible HW-SW boundary. Therefore, most of the required elements of our platform are mainly found in just two chips that can be connected directly, namely the AT86 RF215 and the SmartFusion2. Specifically, as shown in Figure 3, when the platform is in I/Q mode, the ARM Cortex-M3 is responsible for setting and controlling the AT86 RF215 via an SPI, and the I/Q samples are transferred through the LVDS interface between the selected radio and the FPGA, where they are processed. On the other hand, when the platform is in BB mode, the ARM Cortex-M3 controls the AT86 RF215 via an SPI, and the FPGA can be put in Flash*Freeze mode if no other high-speed processing task is required. Figure 2: AT86 RF215 block diagram. Although the platform could already operate autonomously with these two chips, the possibility of using it in conjunction with a computer (PC) during the process of developing and evaluating new techniques is very convenient, since it allows for the use of high-level development and debugging tools. For this reason, the platform has two communication interfaces. On the one hand, the FTDI FT232R UART-USB converter allows the developer to control and receive information from it through a terminal on the PC. On the other hand, the platform also has a synchronous parallel to USB 2.0 hi-speed interface based on the FTDI FT232H chip. This allows the I/Q data stream to be sent to or received from the computer.