## 4 Control Strategy
In steady state conditions the power flow through the MF transformer is linked to the applied time shift through the well-known relation [17]  
\[P=\frac{V_{\Delta 0}\ V_{LV}^{\prime}}{2L_{eq}}f_{R}\ T_{\Delta}\left(\frac{1}{2 f_{R}}-|T_{\Delta}|\right) \tag{9}\]  
while the maximum achievable power can be expressed as  
\[P_{\max}=\frac{V_{\Delta 0}\ V_{LV}^{\prime}}{8f_{R}L_{eq}} \tag{10}\]  
The reference value of the transformer current in correspondence of the \(v_{\Delta 0}\) switching instants \(t_{k}\) can be obtained through the steady state relation  
\[{i_{R}}^{*}=\frac{1}{4L_{eq}f_{R}}(V_{LV}^{\prime}-V_{\Delta 0}\sqrt{1-\frac{|P ^{*}|}{P_{\max}}}) \tag{11}\]  
while a predictive algorithm is used to compute the time delay \(T_{\Delta}\) which ensures the desired condition \(i_{R}(t_{k+2})={i_{R}}^{*}\); the following relation is easily obtained:  
\[T_{\Delta}=\left[\frac{L_{eq}}{2V_{LV}^{\prime}}({i_{R}}^{*}-i_{kk})-\frac{V_ {\Delta 0}-V_{LV}^{\prime}}{4f_{R}V_{LV}^{\prime}}\right]\text{sign}(P^{*}) \tag{12}\]  
where \(i_{Rk}=i_{R}(t_{k})\) is the measured value of the transformer current. Finally, the PSC reference power \(P^{*}\) is obtained as the output of a voltage controller aimed to stabilize the LV-side converter DC-Link around its nominal value \(V_{LV}^{*}\). A simple PI controller is suitable for this purpose. This value can be chosen in order to achieve the optimal condition \(V_{\Delta 0}=V_{LV}^{\prime}\), which guarantees that the transformer current \(i_{R}\), in steady state conditions, is a trapezoidal wave with magnitude \({i_{R}}^{*}\). While the LV-side Full-Bridge AC output voltage depends only on its DC-Link voltage, which is kept practically constant in a modulation time interval, the MMC MF side output voltage strongly depends on the converter operations. Indeed, an ideal square wave voltage can be generated only if all the converter modules are perfectly balanced and no differential voltage is injected in the modules AC outputs. In this case, an ideal square wave is produced if the top and bottom legs of each converter phase are switched in a complementary way, as exemplified in Figure 4 for the generic phase \(k\) of an ideal two modules converter: since the voltage \(v_{Tx,1}\) (\(v_{Tx,2}\)) of the first (second) top module has the same switching instants of the corresponding bottom module's voltage \(v_{Bk,1}\) (\(v_{Bk,2}\)), the differential output \(v_{\Delta k}=(v_{Bk,1}+v_{Bk,2})-(v_{Tx,1}+v_{Tx,2})\) is perfectly constant for the entire switching period. A symmetrical switching of the upper and lower converters is automatically obtained if the upper and lower converters are driven by two Space Vector PWMs (SVPWM) forced with the same voltage reference \(\mathbf{v}_{\Sigma}^{*}\) and if the converters modules are treated as positive charged Half Bridge converters in the positive square voltage half period and as negative charged Half Bridge converters in the negative half period. Therefore, the square wave output period is at least twice the sampling time interval. The actual voltage output behavior deviates from the ideal one depicted in Figure 4 as a consequence of modules voltage unbalancing and asymmetrical modulation of the upper and lower converters. The overall control scheme of the LV-side Full-Bridge converter is shown in Figure 5.  
The balancing between the submodules of the same leg can be obtained through a simple sorting algorithm [16; 20]. Once the leg reference voltage \(v_{leg}^{*}\) has been determined through the SVPWM algorithm, the modules are arranged in increasing (decreasing) order of voltage if the leg power \(p_{leg}=v_{leg}^{*}\)\(i_{leg}\) is positive (negative): the output voltage is obtained through the switching of the first submodules of the array. The leg current \(i_{leg}\) is determined by the average contribution, the differential contribution, and the zero sequence contribution, which respectively depend on the variables \(\mathbf{i}\), \(\mathbf{i}_{\Delta}\), and \(i_{R}\).