# A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs
## 1 Introduction  
The pipeline analog-to-digital converter ADC architecture is the most suitable for high-speed operations with medium-to-high resolution among various ADC architectures. However, because the analog-to-digital conversion of the pipeline ADC is performed in the analog domain, various errors generated from analog circuits, such as charge injection, finite gain error of an operational amplifier (op-amp), and capacitor mismatch error, must be suppressed to achieve high resolution. Most errors, except capacitor mismatch error, can be addressed owing to advances in circuit techniques and CMOS technologies [1, 2, 3, 4, 5]. However, capacitor mismatch significantly depends on the CMOS technology and requires special calibration circuitry to minimize the linearity degradation of the ADC output. The calibration of capacitor mismatch has been investigated for several decades, and numerous techniques have been reported [6, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]. Calibration techniques can be categorized into two types: analog and digital. Digital calibration techniques [6, 7, 8, 9, 10, 11, 12] move analog errors to the digital domain by utilizing different methods and digitally correcting them. However, they increase circuit complexity and power consumption. In contrast, analog calibration has a simpler circuit design compared with digital calibration [3, 13, 14, 15, 16, 17, 18, 19, 20, 21]. The capacitor error averaging technique proposed in [3, 16, 17] is an effective analog calibration technique. In this technique, calibration can be performed in the background, meaning normal operation is not hindered by calibration. However, additional clock phases arerequired to average the capacitor mismatch errors, thereby decreasing the operation speed of the ADC. Self-calibration is another effective analog calibration technique [18; 19; 20; 21]. As suggested by the name, self-calibration utilizes the remaining pipeline stages to correct capacitor mismatch errors in the early pipeline stages, thereby eliminating the need for calibration circuitry and simplifying circuit implementation. Unlike the error-averaging technique, although the calibration is performed in the foreground, the capacitance does not drift or age over time, and the foreground calibration still functions effectively. This study proposes another method to implement self-calibration. Without increasing the circuit complexity, the proposed calibration circuit re-utilizes the multiplying digital-to-analog converter (MDAC) in a pipeline stage to recursively amplify the capacitor mismatch error and then converts it into a digital code by the remaining pipeline stages. The digital error is subtracted from the ADC output. The advantage of the proposed method is that it does not increase circuit complexity and not require additional clock phases, which makes it suitable for high-speed operation. However, it is a foreground method, which means the normal operation has to be stopped during calibration. Although it is known that capacitor mismatch does not change significantly over time, periodic calibration might be required depending on applications. A 12-bit pipeline ADC that employs self-calibration is fabricated by utilizing a 0.18 \(\upmu\)m standard CMOS process. After calibration, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) increase from \(+0.82/-0.75\) and \(+1.12/-1.79\) to \(+0.45/-0.41\) and \(+0.47/-0.91\), respectively. The dynamic performance also improves significantly after calibration. At a sampling rate of 30 MS/s, the ADC achieves a spurious-free dynamic range (SFDR) and a signal-to-noise and distortion ratio (SNDR) of 84.1 dB and 68.9 dB, for an input frequency of 2.09 MHz, respectively. The power consumption of the ADC is 35 mW under a 1.8 V supply and the figure of merit (FOM) is 512 f/conversion step. The remainder of this paper is organized as follows: Section 2 presents the proposed MDAC for self-calibration and its operating principles.