# Flexible Wearable Heart Rate Monitoring System and Low-Power Design: A Review
## 5 Design of the Flexible Wearable Heart Rate Signals Computation Module
### Hardware-Algorithm Co-Design for Flexible Wearable Heart Rate Signal Processing Module  
Hardware-algorithm co-design is also a key solution for realizing heart rate estimation, arrhythmia classification, and low-power module design. This subsection will focus on how to achieve the functionality and low-power design of the heart rate calculation module through hardware-algorithm co-design. Regarding heart rate estimation, [PERSON] et al. [119] through hardware-algorithm co-design, jointly developed a PPG-based power-consuming heart rate estimation processing module for flexible wearable systems. The system consists of a PPG Driver, preprocessing, downsampling, Data Buffer, FFT Module, and HR Estimation. The system adopts a customized processor with parallel computing capabilities and combines it with the R22 SDF-FFT algorithm to achieve computational acceleration and reduce resource requirements. Meanwhile, by integrating the embedded processor with historical heart rate data records, the system minimizes and corrects heart rate estimation errors, thereby reducing the frequency of error generation and further lowering the system's computational power consumption. Finally, validation on the SPC dataset [47] shows that the system exhibits a low mean absolute error in both 12-channel and 22-channel PPG recording sets [120], features short processing latency, and consumes only 34.7 uW of power. Regarding arrhythmia classification, [PERSON] et al. [109] proposed a low-power arrhythmia classification module based on deep neural network (DNN) in flexible wearable systems through hardware-algorithm co-design. The ECG processing flow and the DNN design are illustrated in Figure 5c. At the hardware-algorithm co-design level, the system employs a streaming processing design, integrating filtering, R-peak extraction, and deep neural network (DNN) classification functions in hardware to eliminate power loss caused by data transmission between algorithms and hardware. Meanwhile, through dynamic power management, the finite state machine (FSM) controls the deep neural network (DNN) to enter standby mode when no effective heartbeat signal is detected, achieving a 40% reduction in power consumption. Furthermore, the system adopts a 180 nm bulk CMOS process to minimize leakage power, while a sequential shift multiplier is designed to replace the traditional multiplier. Multiply-accumulate operations are realized through shifting and a single 32-bit addition, reducing the number of registers. Concurrently, the input layer is simplified from 417 dimensions to 210 dimensions, avoiding redundant calculations caused by zero-filling and resulting in an average system power consumption of 8.75 uW. In terms of algorithm optimization, the system simplifies the R-peak extraction algorithm by only using difference comparison and zero-crossing detection, eliminating the need to store intermediate samples. Additionally, a lightweight network with a structure of \(210\times 35\times 25\times 5\) is constructed, where weights are quantized with 16-bit fixed-point numbers to avoid power consumption from floating-point operations. These hardware-algorithmco-design strategies collectively ensure low-power operation while maintaining efficient processing performance. In summary, hardware-algorithm co-design has become a key approach for the low-power design of heart rate computation modules, integrating customized hardware (such as parallel processors and low-power CMOS) with optimized algorithms (such as lightweight DNN and efficient FFT). Case studies of Qiu's PPG system and Janveja's DNN classifier demonstrate that this approach achieves three core objectives: computational acceleration, high-precision estimation, and ultra-low-power consumption. Such co-design proves that low-power consumption and performance can be balanced, making it an ideal choice for next-generation flexible wearable systems.