## 2 Previous Work  
### Radix-8 Multi-Modulus Multiplier in (\(2^{n}-1\), \(2^{n}\), \(2^{n}+1\))  
A structure in which a multi-modulus multiplier can be operated under the same hardware architecture has been reported [20]. This design can greatly reduce the area used. There are three types of modulus multiplication, namely, modulo (\(2^{n}-1\)), modulo (\(2^{n}\)), and modulo (\(2^{n}+1\)) multipliers, which can be processed using two control signals. Let \(X\) be the multiplicand, \(Y\) the multiplier and \(Z\) the binary product. Weighted representation is used for modulo \(m\), \(m=2^{n}-1\), or \(2^{n}\); diminish-\(1\) representation is used for \(m=2^{n}+1\), where m is the modulo parameter. The general expression is as follows [20]:  
\[\left|Z\right|_{m}=\left\{ \begin{matrix}\left|X\cdot Y\right|_{m}&if\ m=2^{n}- 1\ \text{or}\ 2^{n}\\ \left|X\cdot Y+X+Y\right|_{m}&if\ m=2^{n}+1\end{matrix} \right. \tag{1}\]  
where \(\left|X\cdot Y\right|_{m}\) is denoted as the modulo \(m\) residue of \(X\cdot Y\). The partial product (_PP_) can be obtained after taking radix-8 operations of \(X\) and \(Y\). The related equation is expressed as [20]:  
\[|Z|_{m}=\left\{ \begin{array}{ll}\left|\sum\limits_{i=0}^{\lfloor n/3\rfloor}PP_{ i}\right|_{m}&if\ m=2^{n}-1\\ \left|\sum\limits_{i=0}^{\lfloor n/3\rfloor}PP_{i}+\sum\limits_{i=0}^{\lfloor n /3\rfloor}K_{i}\right|_{m}&if\ m=2^{n}\\ \left|\sum\limits_{i=0}^{\lfloor n/3\rfloor}PP_{i}+\sum\limits_{i=0}^{\lfloor n /3\rfloor}K_{i}+X+Y\right|_{m}&if\ m=2^{n}+1\end{array} \right. \tag{2}\]  
where \(K_{i}\) is the extra compensation parameter. The complete equation of \(K_{i}\), where \(KD_{1}\) is a dynamic bias and \(KS_{1}\) is a static bias, is as follows [20]:  
\[ \begin{array}{ll}\sum\limits_{i=0}^{\lfloor n/3\rfloor}K_{i}=& \sum\limits_{i=0}^{\lfloor n/3\rfloor}\underbrace{2^{3i}\left(\overline{m2_{i }+m4_{i}}\right)+\left(\overline{m3_{i}+m4_{i}}\right)\cdot 2^{3i+1}+2^{3i+1} \cdot s_{i}+}_{KD_{i}}\\ &\sum\limits_{i=0}^{\lfloor n/3\rfloor}\underbrace{\left(\left(m2_{i}+m4_{i} \right)\cdot s_{i}\right)2^{3i+1}+\left(\left(m3_{i}+m4_{i}\right)\cdot s_{i} \right)\cdot 2^{3i+2}}_{KD_{i}}\\ &+\sum\limits_{i=0}^{\lfloor n/3\rfloor}\underbrace{-2^{3i}-2^{3i+1}-2^{3i} +\frac{1}{KS_{i}}}_{KD_{i}}\end{array}  \tag{3}\]  
where \(m_{2i}\), \(m_{3i}\), \(m_{4i}\) denote the \(i\)th partial product row of multiplication by 2 bits, multiplication by 3 bits, and multiplication by 4 bits, respectively. The value of the carry bit (\(c_{i}\)) for an even carry bit (Equation (4)) and an odd bit (Equation (5)) are given by [19]:  
\[c_{i}=\left\{ \begin{array}{ll}({g_{i}}^{*},{p_{i}}^{*})\bullet({g_{i-2}}^{* },{p_{i-2}}^{*})\bullet\ldots\bullet({g_{0}}^{*},{p_{0}}^{*})\bullet({g_{i-2}}^ {*},{p_{m-2}}^{*})\bullet\ldots\bullet({g_{i+2}}^{*},{p_{i+2}}^{*});\ if\ m=2^{n}-1\\ ({g_{i}}^{*},{p_{i}}^{*})\bullet({g_{i-2}}^{*},{p_{i-2}}^{*})\bullet\ldots \bullet({g_{0}}^{*},{p_{0}}^{*})\bullet(0,0)\bullet\ldots\bullet(0,0);\ if\ \ if\ m=2^{n}\\ ({g_{i}}^{*},{p_{i}}^{*})\bullet({g_{i-2}}^{*},{p_{i-2}}^{*})\bullet\ldots \bullet({g_{0}}^{*},{p_{0}}^{*})\bullet(\overline{p_{m-2}}^{*},\overline{g_{n- 2}}^{*})\bullet\ldots\bullet(\overline{p_{i+2}}^{*},\overline{g_{i+2}}^{*});\ if\ m=2^{n}+1\end{array} \right. \tag{4}\]  
and:  
\[c_{i}=\left\{ \begin{array}{ll}({g_{i}}^{*},{p_{i}}^{*})\bullet({g_{i-2}}^{* },{p_{i-2}}^{*})\bullet\ldots\bullet({g_{1}}^{*},{p_{1}}^{*})\bullet({g_{n-1}}^ {*},{p_{n-1}}^{*})\bullet\ldots\bullet({g_{i+2}}^{*},{p_{i+2}}^{*});\ if\ m=2^{n}-1\\ ({g_{i}}^{*},{p_{i}}^{*})\bullet({g_{i-2}}^{*},{p_{i-2}}^{*})\bullet\ldots \bullet({g_{1}}^{*},{p_{1}}^{*})\bullet(0,0)\bullet\ldots\bullet(0,0);\ if\ m=2^{n}+1 \end{array} \right. \tag{5}\]  
respectively, where \(({g_{i}}^{*},{p_{i}}^{*})\) is defined as a modified generated-propagated bit pair and \(({g_{i}}^{*},{p_{i}}^{*})\bullet({g_{i}}^{*},{p_{i}}^{*})=({g_{i}}^{*}+{p_{i}}^ {*}{g_{j}}^{*},{p_{i}}^{*})\).