## 1 Introduction  
For decades, the semiconductor industry has advanced through continuous process scaling, maximizing performance by reducing transistor sizes and increasing integration density [1]. The core strategy of semiconductor technology development has been to shrink transistors and enhance integration, leading to improvements in processing speed, power efficiency, and the miniaturization of devices. However, as Moore's Law approaches its physical limits, it is becoming increasingly difficult to sustain performance improvements solely through device scaling [2, 3, 4]. Additionally, challenges such as signal delay, increased power consumption, and heat dissipation have intensified, necessitating new approaches to semiconductor design optimization. Against this backdrop, recent semiconductor technology development has shifted focus beyond simple transistor scaling toward performance enhancement through interconnect and layout optimization [5, 6]. While previous research primarily concentrated on improving transistor performance, inefficient interconnect structures can severely limit the overall system efficiency, regardless of individual transistor advancements. Optimizing interconnect structures with respect to signal transmission characteristics and the current flow has become a critical research area for improving semiconductor device performance. In particular, optimizing semiconductor interconnects and via structures is a key factor directly influencing chip performance and integration density. Interconnects play a crucial role in transmitting signals between transistors, while vias provide electrical pathways between different metal layers [7]. Consequently, the dimensions and placement of interconnects and vias significantly affect the electrical performance and reliability of integrated circuits [8]. Traditionally, semiconductor design methodologies have maintained sufficient contact area between interconnects and via while incorporating generous margins to compensate for potential misalignment and process variations. Figure 1a shows the cross-section of a semiconductor system structure. The Front-end of line (FEOL) region consists of unit devices, while the Back-end of line (BEOL) region is composed of interconnects that implement circuits and vias that connect the wiring layers. The dimensions and shapes of interconnects and vias, commonly referred to as design rules, are determined by considering unit process capabilities such as patterning and deposition. For example, the spacing between adjacent metal lines must account for patterning margins from processes like photolithography and etching to prevent shorts. Similarly, vias must be placed correctly within metal lines, considering photo alignment margins between each layer to ensure proper positioning. Figure 1b illustrates a layout that reflects these margins, showing that metal lines are spaced apart to accommodate patterning margins and vias are positioned with sufficient gaps within the metal lines for proper alignment. These layout margins enhance manufacturing reliability but also consume valuable layout space, thereby limiting integration density [9]. Larger margins increase interconnect spacing, reducing the number of interconnects that can be accommodated within a given area. As interconnect lengths increase, signal transmission paths become longer, leading to greater signal delay, higher power consumption, and uneven current density distribution. As conventional process scaling reaches its limits, semiconductor technology is evolving toward performance enhancement through interconnect and via structure optimization [10]. Recent studies suggest that precisely analyzing the signal transmission characteristics of interconnects and vias can reduce unnecessary margins, enabling more efficient layout designs [11; 12]. This study also aims to propose a method for efficient layout design by eliminating unnecessary margins based on quantitative analysis of the current flow.