# An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling
## 4 Performance Evaluation, Results, and Discussion  
We carried out simulations to evaluate the proposed concatenation code and decoding algorithm. The simulations were performed with FTN signaling, \(\tau=0.703\), and shortened \(\mathbf{v}=[0.553,0.793,-0.084,-0.171,0.154,-0.064]\). We used \(\mathbf{y}=\mathbf{a}*\mathbf{v}\) as in (4) to model the received signal through the AWGN channel, detect it with the 4-BCJR method, and then decode the channel code and perform turbo equalization. Finally, we computed the BER to evaluate each decoding scheme at different SNRs. To reduce storage used for the BCJR trellis, we limited states at each stage to \(M=4\). Moreover, we set the number of turbo equalization iterations to 3 to avoid excessive iterations for the LDPC decoder and decrease the decoding time. The LDPC code used here is a (7680, 3840) code defined by the 5G standard mentioned in Section 2, with 780 data bits shortened (around 10%) to the lower code rate, leading to more definite results. RS (340, 320) is a 0.94 high-rate code with 6% parity redundancy. The shortening of the LDPC and simple hard decision RS concatenation scheme shows the ability to lower the error floor of original LDPC-coded FTN signaling and has an overall code rate of 0.42. All simulations were performed with MATLAB 2022 on a CPU; no GPU was used. Note that the demonstration of the proposed scheme is intended to show its effectiveness in lowering the error floor, and parameters of shortening and RS code can change with different code rates vs. the BER and with different LDPC code. Thus, those parameters can be determined by practical means and trade-offs and are not required to be optimal since the goal of the proposed scheme is to lower the error floor. The BP decoders with maximum iteration limits of 20 and 50 also show an error floor of around \(10^{-5}\). The concatenation code lowers the error floor to \(4\times 10^{-6}\), and no error floor was found in the simulations of the concatenation code with perturbation in the BP decoder down to \(2\times 10^{-7}\) and \(4\times 10^{-8}\), as depicted in Figure 9 and Figure 10, respectively. We found that, for three iterations of turbo equalization, increasing the iteration number of the LDPC code has little effect on the BER performance. The saturation (no more decrease) of the red curve and the blue curve in Figure 9 and the green curve and the red curve in Figure 10 are caused by residual relevance (interference) between symbols. From the view of the decoder, residual relevance leads to error propagation especially with trapping sets in the factor graph. We utilize high-rate RS code to lower the error floor, but it still exists, which means concatenating RS code is helpful, but high-rate RS is inadequate for eliminating the error floor. We introduce perturbation decoding to enhance the proposed LDPC-RS concatenation scheme and eliminate the error floor. Figure 8: Structure of a 4-parallel RS (340, 320) encoder. In [6], LDPC-RS product code and the hybrid error-erasure correction (HEEC) decoding algorithm were proposed. The difference is that our proposed approach utilizes concatenated code, i.e., a whole RS code word is treated as the information part of an LDPC code word. Additionally, [6] utilizes product code, in which multiple RS code words are put in columns and multiple LDPC codes are put in rows. LDPC (576, 288)-RS (255, 51) product code (code length 576 \(\times\) 255) and HEEC decoding in [6] will have better performance than our proposed scheme. However, since product code is deeply coupled, RS decoding can only start after 255 LDPC codes finish decoding. The product code consists of 255 LDPC codes and 36 RS codes. The overall decoding latency is \((255\times Latency(LDPC)+36\times Latency(RS))\times Iteration\), where \(Latency(LDPC)\) and \(Latency(RS)\) may vary from different decoding algorithms. For the LDPC-RS concatenation scheme proposed in this paper, the overall decoding latency is \((Latency(LDPC)+Latency(RS))\times Iteration\).