# An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields
## 2 Lopez-Dahab Projective Form of ECC over \(GF(2^{m})\)
On Virtex-5 FPGA, the high-speed hardware design of [14] utilizes higher slices and LUTs over \(GF(2^{163})\) to \(GF(2^{571})\) binary fields as compared to our hardware accelerator. For \(GF(2^{163})\), the reference design is faster in clock cycles and computation time than our architecture on the same binary field of length 163. On the other hand, the proposed accelerator utilizes lower clock cycles and computation time over \(GF(2^{233})\) to \(GF(2^{571})\) binary fields. This is due to a digit-serial multiplier architecture in the reference design while we employed a bit-parallel modular polynomial multiplier. Additionally, for all binary field lengths of \(GF(2^{163})\) to \(GF(2^{571})\), our accelerator is faster in operating frequency; see column seven in Table 2.

Instead of the binary field hardware accelerators, we will compare our results to some recent prime field accelerators. It is essential to mention that an accurate comparison to prime field accelerators is impossible; however, we will provide the most reasonable comparison. In comparison to the 256-bit prime field accelerator of [19] over Virtex-7 FPGA, our binary field accelerators over \(GF(2^{163})\) to \(GF(2^{571})\) utilizes lower LUTs. The slices are impossible to compare as the slices are not reported in the reference design. Instead of hardware resources, our accelerators over \(GF(2^{163})\) to \(GF(2^{571})\) are faster in clock cycles, operating frequency, and computation time. The reason is the utilization of a digit-parallel multiplier in our work, while in the reference design, authors utilize an interleaved modular multiplier. In comparison to 256-bit prime field hardware accelerators of [20; 21; 22; 23] on Virtex-7 FPGA, our accelerator over \(GF(2^{283})\) is faster in clock cycles, operating frequency and latency. On the other hand, the area utilization in slices and LUTs is also comparable to these accelerators. ### Throughput and Throughput/Area Comparison

To comprehensively compare state-of-the-art designs, we have computed the throughput and throughput/area values, as shown in columns nine and ten of Table 2. The throughput, denoted as Thrpt, is presented in kilobits per second (Kbps) and is calculated using Equation (5). Additionally, the throughput over area values is calculated using Equation (6), where we utilized slices as the area metric. For the designs in [20; 21; 22; 23], slices are not reported; therefore, we have used LUTs as the area metric in Equation (6) to compute the throughput/area ratio. \[Thrpt\;(Kbps)=\frac{1}{Latency\;(\mu s)}=\frac{1}{Latency}\times 10^{3} \tag{5}\]

\[T/Area=\frac{Thrpt\;(Kbps)}{Area}=\frac{Thrpt\;(bps)}{Slices}\times 10^{3} \tag{6}\]

It is crucial to emphasize that a higher throughput/area ratio indicates better performance for the cryptographic circuit. Based on the values in columns nine and ten of Table 2, it is evident that the proposed accelerator over \(GF(2^{163})\), \(GF(2^{233})\), \(GF(2^{283})\), \(GF(2^{409})\), and \(GF(2^{571})\) achieves superior throughput and throughput/area ratio metrics on both Virtex-5 and Virtex-7 FPGA devices. This comparison demonstrates that the proposed accelerator is well-suited for cryptographic applications that require efficient implementations of ECC with a balance between high throughput and optimized area utilization. ## 5 Conclusions

This article has presented a hardware accelerator design for PM computation of ECC over \(GF(2^{163})\), \(GF(2^{233})\), \(GF(2^{283})\), \(GF(2^{409})\), and \(GF(2^{571})\), to optimize throughput and area simultaneously. A digit-parallel multiplier with a digit size of 41 bits is employed to enhance throughput. Additionally, we minimized hardware resources by re-using the hardware area of square and multiplier circuits to compute modular inversions. The implementation results on Xilinx Virtex-7 FPGA demonstrate that an increase in key length results in higher hardware resource utilization, including slices, LUTs, and FFs.