## 4 Results and Comparison
### Comparisons  
We show comparisons with state-of-the-art designs in Table 2, where the first column indicates the reference design (Ref. #). The second column displays the employed PM algorithm or computation method, and the third column specifies the implementation device. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multirow{2}{*}{**Device**} & \multicolumn{2}{c}{**Area Results**} & \multicolumn{3}{c}{**Timing Results**} & \multirow{2}{*}{**Power (mW)**} \\ \cline{2-2} \cline{4-6}  & **Slices** & & & **LUTs** & **Clock Cycles** & **Freq (MHz)** & **Latency (ms)** \\ \hline \multirow{2}{*}{Virtex-6} & \multirow{2}{*}{407} & \multirow{2}{*}{2442} & \multirow{2}{*}{7, 16, 459} & 100 & 7.16 & 73 \\  & & & & 50 & 14.32 & 39 \\  & & & & 10 & 71.64 & 7 \\ \hline \multirow{2}{*}{Virtex-7} & \multirow{2}{*}{391} & \multirow{2}{*}{2346} & \multirow{2}{*}{7, 16, 459} & 100 & 7.16 & 51 \\  & & & & 50 & 14.32 & 28 \\  & & & & 10 & 71.64 & 4 \\ \hline \multicolumn{6}{l}{On Virtex-7 FPGA, maximum @ 161 MHz, our crypto processor takes 4.45 ms latency and consumes 77 mW total power.} \\ \end{tabular}
\end{table} 
Table 1: Implementation results for \(GF(2^{233})\) on Xilinx FPGA devices. Columns four and five exhibit the area results regarding slices and LUTs. The number of clock cycles required for one PM computation is displayed in the sixth column. The operating frequency of the state-of-the-art PM designs is provided in the seventh column. The computation time or latency for a single PM execution is shown in the eighth column. The total power consumption of the designs is presented in the ninth column. Finally, the last column (ten) gives the architectural details of the hardware designs. Column two of Table 2 shows that the reference designs of [12; 13] implement the Montgomery PM algorithm; we also implement the same PM algorithm. If we compare the slices and LUTs of [12] for 163 bit binary field on the same Virtex-7 FPGA devices, our crypto processor design is 5.64 (ratio of 2207 to 391) and 4.24 (ratio of 9965 to 2346) times more efficient. Similarly, if we compare the slices and LUTs of [12] for 233 bit binary field on the same Virtex-7 FPGA devices, our crypto processor design is 13.09 (ratio of 5120 to 391) and 8.07 (ratio of 18,953 to 2346) times more efficient. We utilize a bit-serial modular multiplier, whereas the reference design uses a digit-parallel multiplier. On the other hand, the reference design takes fewer clock cycles than ours (see column six of Table 2). Columns seven and eight of Table 2 show that the reference design over \(GF(2^{163})\) and \(GF(2^{233})\) fields operates on higher circuit frequency and requires less computation time than this work because the reference design uses pipeline registers in the data path, which shortens the critical path delay and improves the circuit frequency. Overall the improvement in circuit frequency decreases the computation time. Similar to [12], another pipelined PM design is described in [13]. If we compare only the slices over \(GF(2^{163})\) and \(GF(2^{233})\) fields, the proposed crypto processor is 3.91 (ratio of 1529 to 391) and 5.23 (ratio of 2048 to 391) times more efficient, respectively. Similarly, if we compare LUTs over \(GF(2^{163})\) and \(GF(2^{233})\) fields, the proposed crypto processor is 1.77 (ratio of 4162 to 2346) and 2.73 (ratio of 6407 to 2346) times more efficient, respectively. The reason includes the use of bit-serial multiplier architecture in our work, whereas a digit-parallel multiplier is used in [13]. Based on column six in Table 2, the reference design requires fewer clock cycles than ours. Additionally, the results displayed in columns seven and eight demonstrate that the reference design operates at a higher circuit frequency and demands less computation time over \(GF(2^{163})\) and \(GF(2^{233})\) fields. This is because the reference design incorporates pipeline registers in the data path, which minimizes the critical path delay and improves the circuit frequency.