# Real-Time Optimization of RISC-V Processors Based on Branch Prediction and Division Data Dependency
## 3 Optimization of Real-Time Performance for RISC-V Processors
### Optimization of the Bran_Pre Module (Branch Prediction Module)
#### 3.2.2 Optimization of the Branch Predictor  
One method to improve the prediction accuracy of conditional branch instructions is to optimize the branch prediction module of the processor. The branch prediction module in Rev-riscv uses a static branch predictor. It is configured such that if the instruction jumps backward (i.e., the target PC value is greater than the PC value of the branch instruction), it always predicts that the jump will be taken. Otherwise, it predicts that the jump will not be taken. The accuracy of static branch prediction is around 60% [22]. To improve the success rate of branch prediction and enhance the overall execution speed and stability of the processor, this paper designs a simplified local branch history predictor (SLBHP) to optimize the branch prediction component of the Rev-riscv processor. The simplified local branch history predictor is an optimized version of the local branch history predictor. In a conventional local branch history predictor [23], the main components are the Branch History Register (BHR), the Branch Target Buffer (BTB), and the Pattern History Table (PHT). The Branch History Register (BHR) stores the historical prediction data for individual branch instructions. The typical structure of a branch history predictor is shown in Figure 6.  
For embedded systems, a branch history predictor consumes relatively large resources. It typically includes 2k index registers, 2k Branch Target Buffers (BTB), and 2k Pattern History Tables (PHTs). Given the limited resources of embedded processors, a branch history predictor is not an ideal choice for branch prediction. \begin{table}
\begin{tabular}{c c} \hline \hline
**Instruction** & **Description** \\ \hline \multirow{2}{*}{beq} & Branch if equal: Jumps to the target address if the values in the two specified registers are equal. \\ \hline \multirow{2}{*}{bne} & Branch if not equal: Jumps to the target address if the values in the two specified registers are not equal. \\ \hline \multirow{2}{*}{blt} & Branch if less than: Jumps to the target address if the value in the first specified register is less than the value in the second specified register (signed comparison). \\ \hline \multirow{2}{*}{bltu} & Branch if less than unsigned: Jumps to the target address if the value in the first specified register is less than the value in the second specified register (unsigned comparison). \\ \hline \multirow{2}{*}{bge} & Branch if greater than or equal: Jumps to the target address if the value in the first specified register is greater than or equal to the value in the second specified register (signed comparison). \\ \hline \multirow{2}{*}{bgeu} & Branch if greater than or equal unsigned: Jumps to the target address if the value in the first specified register is greater than or equal to the value in the second specified register (unsigned comparison). \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Conditional branch instructions and descriptions. We adopt a simplified local branch history predictor (SLBHP) to perform branch prediction for the current processor. The simplified local branch history predictor (SLBHP) is an optimized version of the traditional local branch history predictor. The main optimizations include omitting the Branch Target Buffer (BTB) structure, directly indexing instructions with the index variable without evaluating the 32-bit PC value, and reducing the index size from k bits to 4 bits. The optimized simplified branch history predictor is shown in Figure 7.  
Figure 6: Traditional local branch history predictor principle diagram. Figure 7: Simplified local branch history predictor (SLBHP) principle diagram. The streamlined branch history predictor's internal prediction function workflow is as follows:  
1. Receive the \"PC_inst\" signal and \"PC_number\" signal from the fetch stage. The BHR signal is an internal update signal for the SLBHP (simple loop branch history predictor). 2.