# Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division
## 5 Results and Comparisons
### Related Work and Comparisons  
[PERSON] has proposed a low-latency FP division unit in [8] with radix-64-digit-recurrence algorithm. However, the implementation in [8] lacks necessary parameters such as technology, area, power, and so on. In [57], based on series expansion methodology, [PERSON] et al. has proposed QP FP division with SP and DP support. The proposed multi-precision architecture in [57] is implemented using FPGA device at a frequent of 89 MHz, without matched parameters to perform comparison. In [58], [PERSON] et al. has proposed an iterative dual-mode DPdSP division architecture using the series expansion algorithm, a digit-recurrence method, and synthesized using TSMC 90 nm library. Compared with [8] or [57; 58], this is a more appropriate object for our result comparison as it has provided detailed information after hardware implementation. A comparison with prior paper [58] on FP division architecture is shown in Table 5. Definitions of total energy and efficient average energy are somewhere the same as total \begin{table}
\begin{tabular}{c c c c} \hline \hline  & **SP** & **DP** & **QP** \\ \hline Latency(cycle) & 3 & 4 & 6 \\ \hline Period(ns) & 3.3 & 3.3 & 3.3 \\ \hline Total time(ns) & 9.9 & 13.2 & 19.8 \\ \hline Efficient average time (ns/bit) \({}^{\ddagger}\) & 0.43 & 0.25 & 0.17 \\ \hline Area(\(\mu\)m\({}^{2}\)) & 542,650 & 545,905 & 550,567 \\ \hline Power(mW) & 55.58 & 56.13 & 58.53 \\ \hline \hline \end{tabular} \({}^{\dagger}\) Efficient Length refers to mantissa length of relevant precision: 23 for SP, 52 for DP, and 112 for QP.  
\end{table} 
Table 4: ASIC Implementation Details @ TSMC 90 nm. time and efficient average time. Total energy (power \(\times\) latency \(\times\) period) is defined as the energy needed for a division unit from inputting numbers to outputting results. Efficient average time (power \(\times\) latency \(\times\) period/efficient length) is defined as the energy needed for a division unit to process single bit of input numbers. The two novel metrics measure the computational efficiency of a division unit in terms of power. Since [58] has no QP synthesis results, only cases of DP FP inputs are compared between [58] and the proposed division unit. A technological independent comparison is presented in terms of area, latency, period, and power. Comparison is also made in terms of four unified metrics, total time (latency \(\times\) period), total energy (power \(\times\) latency \(\times\) period), efficient average time (latency \(\times\) period/efficient length) and efficient average energy (power \(\times\) latency \(\times\) period/efficient length), which are supposed to be smaller for a low-latency design. Subnormal computation support is both included for the two division units. The architecture with 1-Stage Multiplier in [58] has a latency of 10 clock cycles for DP, and 8 clock cycles for SP; while that with 2-Stage Multiplier has a latency of 15 clock cycles for DP, and 11 clock cycles for SP. In comparison to [PERSON] et al. [58]'s dual-mode architecture, the proposed Predict-Correct iterative FP division architecture requires much fewer latency and total time. The unified metrics total energy (power \(\times\) latency \(\times\) period) and efficient average energy (power \(\times\) latency \(\times\) period/efficient length) of the proposed architecture are much better than the architecture with 2-Stage Multiplier in [58]. In detail, the proposed FP division unit has \(\approx\)63.6% latency, \(\approx\)30.23% total time (latency \(\times\) period), \(\approx\)31.8% total energy (power \(\times\) latency \(\times\) period), and \(\approx\)44.6% efficient average energy (power \(\times\) latency \(\times\) period/efficient length) overhead over 2-Stage Multiplier in [58]. Table 6 compares the latency and total time of the proposed division unit with these of classic processors for FP SP and DP with normalized operands and result, Intel Penryn [59], IBM zSeries [60], IBM z13 [61], HAL Sparc [62], AMD K7 [63], AMD Jaguar [64].