## 6 Experimental Results  
In this paper, we analyzed the proposed architecture in terms of the simulation execution time and the maximum power consumption for each configuration of hardware architecture, as shown in Table 1. Figure 9 displays the hardware used for the proposed heterogeneous architecture analysis. The simulation of a proposed architecture is computed for eight device configurations as displayed in Table 2. The execution time of the simulation is measured by changing the number of cells, the case of hardware configurations, and the time step size to calculate the differential equations using the Runge-Kutta method. Furthermore, we compared the maximum power consumption and execution time of eight cases under the specific simulation conditions in terms of efficiency. All of the measured execution times in the parts of the experiment are maximum simulation time windows in which the two heterogeneous models are independently evaluated. Figure 10 reveals the execution time of the simulation when changing the number of cells and the simulation target device configurations as parameters. We measure the simulation time for about eight \begin{table}
\begin{tabular}{c c c} \hline \hline
**Devices** & **Model** & **Cores** \\ \hline CPU & Intel Xeon CPU E5-2620 v4 \(\times\) 2 & 16 \\ GPU & NVIDIA GeForce GTX 1080 Ti \(\times\) 4 & 14,336 \\ Memory & 16 GB \(\times\) 8 & - \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Hardware specifications. \begin{table}
\begin{tabular}{c c} \hline \hline
**Case** & **Devices** \\ \hline
1 & 4 CPU cores \\
2 & 8 CPU cores \\
3 & 12 CPU cores \\
4 & 16 CPU cores \\
5 & 4 CPU cores, 3584 GPU cores \\
6 & 8 CPU cores, 7186 GPU cores \\
7 & 12 CPU cores, 10,752 GPU cores \\
8 & 16 CPU cores, 14,336 GPU cores \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Hardware configurations. Figure 9: Target hardware for computing a proposed simulation framework. cases of hardware configurations, and we measure it by increasing the number of cells from 90,000 to 2,880,000. The step size for computing a CS is 0.0001. The result indicates a higher level of performance in terms of the execution time when a large number of cells are used in the simulation. The results of case 4 and case 8, which use the same number of CPU cores, are as follows. When experimenting using 180,000 cells, case 8 shows that the simulation time is about 10% faster than in case 4. In the experiment using 2,880,000 cells under the same hardware conditions, the simulation time of case 8 is about 80% faster and results represent that the simulation time decreases more as the number of cells increases. With this result, the proposed CPU-GPU tightly coupled simulation has an advantage when using a large number of cells. Table 3 represents the simulation time of CUDA MPS-based GPU operations used to reduce overhead due to GPU operation requests on multiple cores. To analyze the performance of MPS for a bottleneck due to GPU access by multiple cores, execution time is analyzed by increasing GPU from 1 to 4 in 16 cores. When 16 tasks are assigned to 16 cores with one GPU device that is requested to operate, a lot of CUDA context switching and underutilization may occur. Therefore, GPU operation takes a lot of time. In this case, the result represents that the GPU operation using CUDA MPS is reduced by 44% or more from the previous 2.206 s to 1.227 s. Likewise, the result reveals that the execution time is reduced to 45.339%, 41.584%, and 12.299% when the CUDA MPS was used for experiment conditions that each have a different number of GPUs. From this result, the use of CUDA MPS in heterogeneous architecture using multi-cores and GPUs improves GPU utilization and reduces the context switching, thereby enabling faster operation by reducing overhead. The accuracy of a differential equation using the Runge-Kutta method depends on the step size of the time-based calculation step. Generally, a small step size can lead to an accurate result.