## 2 System Architecture and Design  
### System Architecture  
Reducing the SerDes power consumption can be carried out only if the chip I/O is physically decoupled from the switch ASIC. In that case, a custom chiplet is assembled next to the switch that handles all I/O tasks (Figure 2). The 64 pluggable transceivers are re-arranged into large silicon photonics (SiP) matrices assembled directly on the chiplet. Fiber ribbons are used to route the traffic to the front panel of the switch chassis. This approach is in-line with the industry's long-term goal of integrating photonics and digital electronics, shown in Figure 1. Starting with pluggable transceivers, the optical interconnect is moved closer to the ASIC with each generation until full integration (Figure 1d,e) will be obtained. On-board (Figure 1b) optics technologies have been widely investigated with several reported demonstrations, including from Intel, Luxtera, Elenion and others (see [12; 13; 14; 15] and references therein). Co-packaging (Figure 1c) is thus the next step after on-board optical engines. Decoupling chip I/O from the switch ASIC implies that the chiplet handles all tasks associated with I/O. Typically, the Medium Access Control (MAC)and Forward error correction (FEC) blocks are moved from the switch to the chiplet. Additional macros can be relocated as well, such as redundancy management, load balancing, etc. The interface between the two chips can be either a parallel bus or a low-power SerDes. In the latter case, an equalizer is not required as the switch and chiplet are only a few mm apart. The power consumption thus drops from 700 mW per 100 Gb/s to less than 200 mW. The SerDes array on the switch ASIC is distributed on the chip perimeter; therefore, 4 or 8 chiplets are used, each handling 6.4 or 12.8 Tb/s and assembled around the switch ASIC. The front panel pluggable transceivers are rearranged into large, 2D SiP matrices that are assembled directly on each chiplet. Using 25 Gb/s per lane, each transmitter cell in a 64 element SiP matrix contains a 25 G modulator and a laser source. The modulated signals from 4 adjacent cells are Coarse Wavelength Division Multiplexed (CWDM) and fiber coupled. The laser source can be integrated within the SiP cell or may be fiber-coupled from an external laser bank. In the former case, the laser may suffer from thermal instability due to the proximity to the very hot switch, while in the external source case, a higher loss is anticipated due to the two additional coupling steps. A receiver SiP matrix is assembled next to the transmitter SiP matrix with integrated photodiodes and wavelength de-multiplexing for every 4 cells. Driving the transmit and receive SiP matrix arrays is carried out using analog drivers and trans-impedance amplifiers within the chiplet. Thus, a modulator driver is located directly below each modulator (Tx), and a trans-impedance amplifier is located directly below each photodiode (Rx). The short (~50 \(\upmu\)m) distance between the analog driver and the optoelectronic component ensures that parasitics are kept to a minimum on the transmission line. A cross-section of this design is shown in Figure 2. As shown in Figure 2, the lasers and modulators are on the lower part of the SiP chip. Since the 2D SOI chip is assembled such that its front side faces the ASIC, the device is back-illuminating with light  
Figure 2: A schematic of the L3 MATRIX Approach: Switch and I/O ASICs co-packaged on a common substrate. Inset: Side-view layout of the chiplet assembly with Tx and Rx SiP matrices; the chiplet is assembled facing down through a cutout hole in the substrate. propagating from the grating coupler (GC) through the Silicon substrate (Figures 2 and 3) to a set of microlenses that couple it to the single-mode fiber. The microlens array is flipchip assembled onto the back surface of the SOI chip. Alignment marks are fabricated on this surface using a dual-side mask aligner. Figure 3 shows a detailed cross-sectional view of the L3 MATRIX integration scheme.