## 4 Comparison of Multiple Types of Delay Frequency

Table 2: Output of aging detection using exhaustive test. Figure 10: Output result for the detection of \(\theta_{1}=108^{\circ}\) of delay for voltage input \(V\). where \(\%d\) is the percentage of delay and \(f_{d}\) is the range of the phase delay. For example, if \(f_{d}\) is between 101\({}^{\circ}\) and 150\({}^{\circ}\), \(\%d\) is equal to 41.67% by using the maximum value within this range, which is 150\({}^{\circ}\). Subsequently, the following formula was used for calculating the remaining lifetime:  
\[T_{r(months)}=L_{m}-(\%d\times L_{m}) \tag{7}\]  
where \(T_{r}\) is the time remaining for the FPGA and \(L_{M}\) is the maximum lifetime data provided by the FPGA manufacturer. For instance, with regard to the 40 nm Virtex-6 FPGA board with a \(\%d\) of 41.67%, the \(L_{M}\) is equal to 80 months; the calculated value of \(T_{r}\) is equal to 47 months. Figure 11 shows the output for the automatic clock correction aging sensor. For this proposed correction circuit, the _enable_ input was set to 8150 ns. It is apparent from this figure that before the automatic clock correction was triggered for \(t<8150\) ns, the output waveform was in degradation mode. Interestingly, after \(t>8150\) ns, the _out_as_ signals stabilized with no aging detected when enabled input was switched ON. These signals are highlighted in red. The automatic clock correction circuit was activated if the _enable_ input was HIGH. During the activation period, the system will compensate for an appropriate clock signal input based on the occurrence of the delay. For example, based on the asterisk symbol (*) in Table 2, if the current delay phase was 108\({}^{\circ}\), the clock signal for the system will automatically switch to 100\({}^{\circ}\). Likewise, suppose the delay phase changes to 220\({}^{\circ}\) after several months or years. In this case, the clock signal will also automatically feed the system with 200\({}^{\circ}\), which is as close to the delay phase without interruption by the user/programmer/designer. This process continues as long as the _enable_ input remains HIGH for 360\({}^{\circ}\) delay degradation, covering all possibilities. Figure 11: Output result for detection with automatic clock correction. \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Phase Delay**} & \multirow{2}{*}{
\begin{tabular}{c} **Percentage of** \\ **Delay** \\ \end{tabular} } & \multicolumn{4}{c}{**Remaining Lifetime (Months)**} \\ \cline{3-5}  & & **Xilinx** & **Altera** & **Lattice Semi** \\ \hline
0 & 0\% & 80 & 36 & 24 \\
50 & 27.78\% & 58 & 26 & 17 \\
100 & 41.67\% & 47 & 21 & 14 \\
150 & 55.56\% & 36 & 16 & 10 \\
200 & 69.44\% & 24 & 11 & 7 \\
250 & 83.33\% & 13 & 6 & 4 \\
300 & 100\% & 0 & 0 & 0 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Lifetime prediction for Xilinx, Altera, and Lattice Semi FPGAs. Figure 12 illustrates aging sensor detection and automatic clock correction processes with valid and invalid correction methods. Initially, the signal input _Vi_ was injected with a 108\({}^{\circ}\) phase shift delay with the original clock input of a 0\({}^{\circ}\) phase shift. Since the 50\({}^{\circ}\) and 100\({}^{\circ}\) phase shifts of the aging sensors were less than the injected signal of the 108\({}^{\circ}\) phase shift, both of these sensors produced HIGH output signals. On the other hand, sensors 150\({}^{\circ}\)/200\({}^{\circ}\)/250\({}^{\circ}\)/300\({}^{\circ}\) had LOW output signals. The automatic clock correction was performed by triggering the _enable_ input and a new clock signal of 100\({}^{\circ}\) phase shift was applied to the entire system. All aging sensors thus produced LOW output signals with a new clock signal used. If the new clock signal is higher than the signal input delay (_Vi_), all sensors will produce HIGH output signals. This invalid correction method is illustrated in Figure 12 with a clock signal with a 150\({}^{\circ}\) phase shift. Regarding the feedback signal obtained, the system performance was stable and did not degrade further.