## 1 Introduction
### Literature Review
This situation underscores the pressing need for resilient architectures capable of embedding robust security functionalities without compromising overall efficiency. Alternatively, the researchers in [20] proposed a unidirectional systolic array design for the Dickson basis multiplier, enabling the effective incorporation of robust error-detection mechanisms. Nevertheless, its quadratic area complexity renders it impractical for compact, ultra-low-power IoT edge nodes, highlighting the ongoing challenge of balancing performance and resource constraints in this field. The selection of irreducible polynomials plays a vital role in optimizing finite field multipliers, as they underpin the arithmetic operations executed. This decision can have a profound effect on overall performance [21; 22; 23; 24; 25]. Although irreducible trinomials and pentanomials are frequently favored for their operational advantages, the flexibility and effectiveness of finite field multiplication are enhanced by a diverse range of polynomial choices. Additionally, some irreducible polynomials, though less commonly adopted, can offer considerable advantages in specific contexts, thereby facilitating the creation of efficient multipliers [26; 27; 28]. This range of polynomial options enriches the versatility and efficiency of finite field multiplication across various technological applications. Different design techniques can lead to a variety of multiplier architectures, each exhibiting distinct characteristics that impact their performance and suitability for specific applications. For instance, bit-serial multipliers are renowned for their compact design and remarkable energy efficiency, making them ideal for low-power devices; however, they necessitate multiple clock cycles to complete a single multiplication operation, which can hinder speed in high-performance settings [29; 30; 31]. In contrast, bit-parallel multipliers can produce results in just one clock cycle, significantly improving throughput, but they often come with greater expenses related to hardware and power usage, making them more suitable for applications where speed is critical and budget constraints are less stringent [32; 33; 34; 35; 36; 37; 38; 39; 40]. Moreover, in the field of Very Large Scale Integration (VLSI), systolic and semi-systolic array designs are increasingly favored due to their modular nature and ability to process data concurrently. These architectures are particularly advantageous for high-speed applications, such as digital signal processing and real-time computing, as they effectively optimize the utilization of available hardware resources while enhancing overall performance and scalability. By leveraging parallelism, they can significantly reduce latency and improve throughput, making them a compelling choice for modern computational demands. A considerable number of researchers have focused on enhancing systolic and semi-systolic multipliers tailored for binary extension fields GF(2\({}^{m}\)), which play a vital role in various computational applications. For example, [PERSON] and [PERSON] [29; 41] have developed advanced semi-systolic array multipliers that include error-detection features to improve the reliability of computations. In a similar vein, [PERSON] et al. [42] have concentrated on optimizing both time and space efficiency in their designs, addressing the limitations of hardware resources. Furthermore, [PERSON] and [PERSON] [33] have contributed to the field by designing systolic array architectures that enable simultaneous multiplication and squaring operations. This innovation significantly enhances the performance of modular exponentiation, a crucial process in many algorithms, while reducing the associated resource requirements. Their methodology also employs least significant bit (LSB)-first multiplication techniques, which additionally improve computing efficiency by optimizing the computation sequence.