# An FPGA-Based Performance Analysis of Hardware Caching Techniques for Blockchain Key-Value Database
## 4 FPGA Implementation Details of Cache Mapping
### Direct Mapping  
A direct-mapped cache is the simplest cache system in which each main memory address can map to exactly one cache block. A direct-mapped cache can mitigate cache complexity. We use \(KmodN\) to find which cache block can map to the main memory address, where \(K\) is the block number of main memory and \(N\) is the number of sets in the cache. For example, if there is a four-block cache, the main memory block number 10 goes to cache line 2 (10 mod 4 = 2). The block diagram of the implemented direct-mapped cache is shown in Figure 7.  
Figure 7 shows that when a valid flag is high and the tag saved in the cache block is equal to the 244-bit tag extracted from the request packet, then it will be cache hit and gets data out. On the other hand, if there is a cache miss, the BRAM controller forwards the request packet to the server. The server checks for the key, replies to the client, and also sends the result to the cache, as shown in Figure 2.  
Figure 8 shows the FSM of the direct-mapped cache system for the cache hit or miss case.  
Figure 8: FSM of direct-mapped cache system for cache hit or miss.  
Figure 7: Direct-mapping block diagram.  
The various states are described in more detail below.
* IDLE: In this state, the incoming cache requests are received and placed in the input registers.
* Valid check and Tag compare: On read request, the cache controller jumps to this state and makes the busy signal of the system high. It checks the tag and makes state transitions based on hit or miss and validity.
* Evict process: If validity is high and the tag comparison miss, then the evicting process starts. In this state, it evicts data in the required cache line, sends them to the main memory, and prepares the required cache line for a refill.
* Evict wait: In this state, it waits until the evict process ends.
* Refill data request: After tag comparison, if it is not valid or valid and miss but the evict process ends and the delay counter is zero, then the cache controller requests for data refill in the desired cache line.
* Wait refill: In this state, it will wait until the refill process ends.
* Data write: In this state, the data fetched through the refill process from the main memory is written in the desired cache line.
* Data read: After the tag comparison, if it is valid and hit, it will read data directly from the cache.
* Output data: It provides data to the processor after data is written in the cache and read from the cache. After that, the cache controller makes the busy signal low and jumps to the IDLE state.  
The FSM of the direct-mapped cache controller unit differs from the basic FSM cache discussed above due to the evict process, waiting for eviction response, and various latency interfaces. The FSM cache controller used in this research has a hit latency of one cycle and a miss latency of three cycles to respond to the request.  
Figure 9 shows the flow chart diagram of the direct-mapped cache system. In direct mapping, when the controller receives the request, it checks the valid register. Based on the valid check result, it decides to go to the tag comparison or refill process. If the valid register is high, it goes to the tag comparison; if the valid register is low, it directly goes to the refill process. After tag comparison, it goes to the evict process if the tag does not match or there is a cache miss. On the other hand, if data are present in the cache, then the cache controller reads data from the cache and sends the output to the processor.