###### Abstract  
Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT attacks. In this regard, we investigate the feasibility of using EHW to mitigate HTs that disrupt normal functionality in CGRA in this paper. When it is determined that HT is inserted into certain processing elements (PEs), the array autonomously reconfigures the circuit structure based on an evolutionary algorithm (EA) to avoid the use of HT-infected (HT-I) PEs. We show that the proposed approach is applicable to: (1) hardware platforms that support coarse-grained reconfiguration; and (2) pure combinatorial circuits. In a simulation environment built in Python, this paper reports experimental results for two target evolutionary circuits and outlines the effectiveness of the proposed method.  
evolvable hardware (EHW) at edge; coarse-grained reconfigurable array (CGRA); hardware security; hardware trojan (HT); field-programmable gate array (FPGA) +
Footnote †: journal: Applied sciences  
methods use testability-based structural features extracted from IC design files to match HTs' features [10; 11; 12; 13; 14]. However, since attackers may create special types/hard-to-activate HTs, there is no complete guarantee that HT circuits can be identified during the detection phase. Once the HTs are activated at runtime, it is common practice to replace the existing HT-infected (HT-I) device. However, in complex and dangerous edge computing applications, manual replacement/repair of hardware devices is almost impossible. As the ideas of artificial intelligence have been incorporated into security and high trust research, evolvable hardware (EHW) is becoming an important approach for fault-tolerant and highly reliable designs [15]. Among them, Virtual Reconfigurable Circuits (VRC) and Coarse-Grained Reconfigurable Array (CGRA) are popular ways to implement EHW architectures that reconfigure the circuit structure in one or a few clock cycles [16]. This offers the possibility to mitigate HT attacks on EHW architectures. However, relevant research in this area is still in the exploratory stage.  
In this paper, we investigate a solution for HT mitigation using EHW on CGRA. Specifically, by using an evolutionary algorithm (EA) to explore and generate new circuit structures that no longer use the PEs infected by HTs. Meanwhile, The new circuit structure must also satisfy resource constraints, namely, minimize the resource overhead. In addition, the process of EA exploration is time-consuming, which is undesirable for most electronic systems. To address this, we optimize the evolvable region (ER) to accelerate the convergence. In summary, we make the following novel contributions:  
* It is the first time employing an EA-based mitigation method against HTs attack in PE of CGRA;
* A method to optimize the evolvable region is proposed for reducing the evolution time;
* The experimental results show the effectiveness of the proposed scheme for mitigating HT attacks and confirm that optimizing the evolvable region can accelerate the evolution efficiency at the edge.  
The paper is structured as follows. Section 2 provides information on HTs in digital circuits, evolutionary algorithms and evolvable hardware. In Section 3, we describe the proposed HT mitigation method. In Section 4, we evaluate the effectiveness of our approach based on two target circuits. Section 5 concludes the paper.