# Design of Static Random-Access Memory Cell for Fault Tolerant Digital System
## 3 Radiation-Hardened SRAM Cell Design
### Quad-Node 10 T or Quatro-10 T Cell and Write-Enhanced Quatro-12 T Cell (WE-Quatro-12 T)  
Figure 3a shows a schematic of the Quatro-10 T cell proposed in [13]. Similar to DICE, four nodes inside the cell--A, B, C, and D--are used to store data. For example, when the datum \"1\" is stored, A = D = 0 V and B = C = VDD. Unlike DICE, only two nodes, A and B, are directly connected to differential bit-lines through two access transistors, N5 and N6, while C and D are not. Thus, the read operation is performed through turned-on access transistors with WL = VDD, which develop differential bit-lines according to the voltages of A and B. For the write operation, the bit-line voltages are first reflected to the nodes A and B; then, the nodes A and B are amplified through the inner positive feedback configuration composed of P1-N1-P3-N3. Then, the amplified A and B are fed back to fully develop the nodes C and D through the positive feedback configuration P2-N2-P4-N4. As in DICE, each of the four nodes in Quatro-10 T is also driven by one nFET and one pFET, where their gates are pinned to different nodes. In this manner, resilience to single node upset can be achieved. For example, when the data are stored as \"1,\" the node B is supposed to be VDD, with A = 0 V, C = VDD, and D = 0 V. In this situation, B can be accidently pulled down due to the upset and becomes 0 V, leading to N1 and N4 being turned off. However, no other node voltages are changed due to the turning off of these transistors. Instead, because D is kept at 0 V, P3 supplies the current to the lowered B. Thus, B is raised back to high, which means that the data \"1\" state is recovered. Figure 2: Schematic of 12 T DIEC SRAM cell. However, Quatro-10 T is not tolerant for 0 to 1 SEU; it is only tolerant for 1 to 0 SEU. For example, when the datum \"1\" is stored, B should be kept as 0 V. In this condition, B can experience SEU of 0 V to V\({}_{\text{DD}}\) (i.e., 0 to 1). This turns on N1 and N4, which pulls down the nodes A and D, respectively. The lowered node D can cause C to rise through P2, which turns off P1. The turned-off P1 and turned-on N1 are combined to accelerate the lowering of the node A. Consequently, there is no option for the cell to recover to the initial state, which means that the data flip occurs. In addition, the write ability of Quatro-10 T is very weak at a low voltage. For example, when the datum \"0\" is written to datum \"1\" in the hold cell, BL = V\({}_{\text{DD}}\) and BLB = 0 V should be well reflected to the nodes A and B, which initially store 0 V and V\({}_{\text{DD}}\), respectively. However, the node A is weakly pulled up through N5 due to the Vth drop; thus, N2 is only weakly turned on and the node C is not well pulled down to raise the node D. This means that P3 remains turned on, which prevents the node B from being sufficiently pulled down by N6. Therefore, the write ability is significantly limited in the Quatro-10 T cell. To mitigate the write ability problem of the Quatro-10 T cell, two transistors are additionally used and a write-enhanced Quatro-12 T cell (WE-Quatro-12 T) is proposed [13], as shown in Figure 3b. Through the two newly added access transistors, N7 and N8, the nodes C and D can also be connected to bit-line pairs. Thus, for the previously mentioned data \"0\" write case, the node D can be easily pulled up to turn off P3. This significantly enhances the write ability. However, as in Quatro-10 T, WE-Quatro-12 T does not have error tolerance for the 0 to 1 flip of the nodes A and B.  
PMOS-Stacked 10 T SRAM Cell (PS-10 T), NMOS-Stacked 10 T SRAM Cell (NS-10 T), and Radiation-Hardened SRAM Cell (RHD-12 T)  
Figure 4a,b show the PMOS-stacked 10 T SRAM cell and NMOS-stacked 10 T SRAM cell for radiation-hardened operation [14]. PS-10 T has a similar structure to Quatro-10 T; the only difference from Quatro-10 T is that the sources of MP3 and MP1 are not V\({}_{\text{DD}}\) but are connected to the nodes D and C, respectively.