## 2 Inductive-Based Digital Isolation System
### Transformer Design  
We performed two case studies to investigate the isolation capability of the technology at different separation distances between the coils. The voltage at the secondary side of the transformer is formed by differentiating the current I\({}_{1}\) generated in the primary coil at the Tx side and can be controlled by proper magnetic coupling between the two coils. Since the design kit does not include inductor or transformer models, we customized the coils on two different metal layers separated by the inter-metal dielectric material. Among other configurations, such as tapped or interleaved, we chose the stacked structure due to its  
Figure 2: Transmitter (Tx) circuit diagram including the operation waveforms.  
highest self-inductance and coupling efficiency. Figure 3a illustrates the lateral parameters of the square spiral coil with a number of turns \(n=3\) and a number of sides \(N=4\). The coil width is denoted by \(w\), while \(s\) is the spacing between the adjacent turns, and inner and outer diameters are \(d_{in}\) and \(d_{out}\), respectively. Square spirals are chosen among other alternative geometries due to their layout simplicity. Also, they have the smallest effective area compared to hexagonal, circular, and octagonal shapes. Figure 3b shows the two versions of the on-chip transformer implemented on the three metal layers of a CMOS process. Higher isolation can be achieved between metal-1 and metal-3 due to the larger insulation material thickness. Our objective is to examine the effect of changing the isolation distance on the performance of the data communication link for the isolation system.  
The isolation transformer is modeled by a non-ideal equivalent circuit consisting of an inductance, parasitic resistance, substrate resistance, and parasitic capacitances. The equivalent circuit of the non-ideal transformer formed by two \(\pi\) models for the primary and secondary coils is shown in Figure 4. The series inductances, resistances, and parallel capacitances are defined by [37]  
\[L_{s}=\frac{2\mu n^{2}d_{avg}}{\pi}\left[ln\left(\frac{2.067}{\rho}\right)+0. 178\rho+0.125\rho^{2}\right], \tag{1}\]  
\[R_{s}=\frac{\rho l}{\delta w\left(1-e^{-\frac{l}{\delta}}\right)}, \tag{2}\]  
and  
\[C_{ox}=C_{ox}=0.5\frac{\varepsilon_{ox}}{t_{ox}}lw, \tag{3}\]  
respectively. The magnetic permeability is denoted by \(\mu\), \(d_{in}\) is the average diameter of turns, \(\rho\) is the fill ratio, \(\delta\) refers to the skin depth, and \(t\) represents the thickness of the metal. \(\varepsilon_{ox}\) is the oxide permittivity, \(t_{ox}\) is the oxide thickness, and the coil length is represented by \(l\). The substrate coupling elements, \(R_{si}\) and \(C_{si}\), can be ignored by considering the pattern ground shield effect. Finally, the mutual inductance is related to the coupling coefficient \(k\) and the primary/secondary inductances \(L_{sp}/L_{ss}\) as [37]  
\[M=k\ \sqrt{L_{sp}\ L_{ss}}. \tag{4}\]  
The typical range of mutual inductance for the stacked spiral configuration is between 0.3 and 0.9, with the highest coupling coefficient being used in this design to ensure the correct functionality of the digital isolator system. In addition, the proper matching of the transformer's inductance value should be considered to avoid distortion of the detected voltage pulse at the secondary side. The detected voltage pulse has been simulated at  
Figure 3: **(a)** Square spiral coil layout [28]; **(b)** the coil implementation on three metal layers of a CMOS process [28].  
different inductance values, where a typical value of 10 nH has been selected based on the desired amplitude and pulse width at the Rx. Then, on-chip spiral coils of the transformer parameters are designed from the obtained inductance value.