# Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices
## 4 3D NAND Reliability
### Retention  
Floating-gate based 3D NAND suffer from anomalous SILC after heavy P/E cycling, though this effect is not expected to be the dominant cause of retention loss. Charge-trap based memories are claimed to be insensitive to such a loss [297], due to the localized nature of storage, although it has been shown [298] that defect build-up in the tunnel oxide eventually leads to TAT mechanism enabling charge loss from the nitride layer. In any case, to our knowledge, there are no published reports of anomalous SILC in 3D NAND, so it seems safe to extend to this technology the conclusion drawn for planar arrays, where other effects are dominating retention.  
A comparison between 2D and floating-gate based 3D NAND with respect to detrapping is reported in Figure 36 (left), showing a smaller \(\Delta V_{T}\) spread for the 3D array, even if subjected to a higher number of P/E cycles [299]. This is once again the result of the larger cell in 3D technology, i.e., larger gate capacitance, minimizing the effect of single-charge detrapping onto \(V_{T}\). Published single-cell data (Figure 36) suggest that a good intrinsic retention can be achieved, as expected from a floating-gate design [289].  
The retention properties of charge-trap based planar devices have been extensively investigated as a function of temperature and bias [300], pointing out the roles of vertical charge loss through the tunnel oxide and lateral charge migration in the nitride [301; 302; 303; 304], which also reduces the stored charge located above the channel region, that determines \(V_{T}\). In 3D devices, the importance of such effects is shown in Figure 37, where lateral diffusion along the nitride is modulated by the state of  
Figure 36: (Left) comparison between 2D and 3D cycled NAND arrays for \(V_{T}\) shift induced by charge detrapping [299], © 2015 IEEE; (Right) retention for different temperatures [289], © 2013 IEEE. All devices are floating-gate based.  
Figure 35: (Left) Endurance figure for a 3D NAND [286], © 2007 IEEE; (Right) \(V_{T}\) distribution after cycling for a planar and a 3D NAND TLC [22], © 2015 IEEE. Devices are charge-trap based.  
adjacent cells [305]: having all cells programmed decreases the concentration gradient, slowing down diffusion and reducing the \(V_{T}\) shift. Similar results obtained via simulations were also presented in [306; 307; 308] and, changing the device size, in [309]. Note also the thermal activation, accelerating both leakage mechanisms and making pattern-dependent charge spreading effects more relevant at high temperatures. The resulting multiple activation energies are discussed in [310]. An analogous charge-gain phenomenon for the low-\(V_{T}\) state was reported in [311]. Such a feature had been already discussed in planar nitride memories and floating-gate devices, being interpreted in terms of recovery of negative bias-temperature instability [312; 313].  
A related effect that was first observed in planar devices [314] is a fast charge loss taking place on a \(\upmu\)s timescale [315]. Currently, there is no consensus on the root cause of this phenomenon, ascribed to either electron detrapping from shallow traps in the nitride [314] or in the tunnel oxide [316], or to lateral electron migration enhanced by holes injected during erase that are not fully compensated by electrons [315]. The effect is however dependent on the nature of the gate stack, being smaller in conventional ONO stacks with respect to band-engineered ones, and its magnitude increases with cycling.