## 1 Introduction  
The semiconductor market is growing at a rapid pace with the advent of the fourth industrial revolution, characterized by the widespread use of the Internet of Things and the use of artificial intelligence technologies in daily life [1; 2]. To connect not only traditional devices such as PCs and smartphones but also other electronic devices such as automobiles and home appliances to networks, and to store and process the huge amounts of data obtained by these devices, the demand for various types of ultra-compact and highly integrated semiconductor products has significantly increased [1]. To meet these requirements, ultrafine process in semiconductor production technology has consistently evolved and has reached the physical limit with the help of advanced manufacturing processes. The semiconductor manufacturing process consists of three main steps: (1) wafer fabrication; (2) wafer test, i.e., circuit measurement for defective die/chip identification; and (3) packaging, i.e., cutting the finished chips to a specific size to assemble them and make the final product such as DRAMs or solid-state drives [3]. Since hundreds of individual equipment are involved in the semiconductor manufacturing process, more than three months of production time is required. The overall yield of th semiconductor manufacturing industry is relatively lower than that of other manufacturing industries [4] because of the highly complex manufacturing processes involved; hence,yield management is one of the key factors to gain a competitive advantage in the market. It is obvious that developing a new product faster than competitors is necessary for market leadership, but a company can also dominate the market when their mass production system is running with a high and stable yield. The company can take an advantage of price competitiveness through cost reduction, which results in increased market share and profits. Since the semiconductor manufacturing process has becoming more precise and highly integrated, it is increasingly difficult to secure high yields for various newly developed products [5]. The electrical die sorting (EDS) test is conducted to check the electrical operation state of each die on a wafer to identify defective dies and determine whether the current wafer can move on to the packaging stage [2]. From the perspective of yield management, it is very important to find the cause of defects in the semiconductor production process by examining the EDS test result [6]. EDS tests are conducted based on predefined conditions, which vary with the characteristics of products. Once a set of EDS tests is completed, a single decimal bin code is assigned to each die on the wafer. This bin code indicates a certain combination of tests that the die passed or failed. Theoretically, if there are 10 different tests, the possible number of bin codes is 1024 (\(2^{10}\)), which is represented as a decimal number ranging from 0 (passed all tests) to 1023 (failed all tests). A wafer bin map (WBM) is an image that shows the relative location of each die and its corresponding bin code. WBMs are commonly used to help engineers understand the overall state of a wafer based on the EDS test results, as shown in Figure 1. The large circles in both images represent a single wafer while the small squares represent individual dies. The only difference between Figure 1a,b is the coloring scheme used for bin codes. All bin codes, except the code indicating that all EDS tests were passed, are presented as the same gray color in Figure 1a, whereas different RGB values are assigned different bin codes in Figure 1b. Once the fabrication step is completed, various EDS tests are conducted for each wafer and the results are visualized by a WBM, based on which experienced engineers with sufficient domain knowledge determine whether the wafer should be delivered to the packaging step (normal/good wafers) or discarded (bad wafers) [7].