# A Secondary Reconfigurable Inverter and Its Control Strategy
## 3 Results and Discussion
### Experimental Results and Discussion  
To further verify the feasibility and effectiveness of the proposed circuit topology of secondary reconfigurable inverter for the islanded microgrid, the experimental platform of the reconfigurable inverter was built. The system parameters were the same as the simulation parameters. DSP(digital signal processor) TMS320F2812 was used to generate pulses for the fault-tolerant inverter. Images of the experimental setups are shown in Figure 8. The main circuit board has a good and compact structural layout. The DC side voltages are provided by the rectifier. The loads are the resistors.  
Figure 8: _Cont._  
Figure 7: Simulation results of the reconfigurable inverter under faulty phase a: (**a**) output voltages; (**b**) currents; (**c**) voltage deviations.  
When the DC side voltage is set as 400 V in the non-reconfigurable inverter that is faulty, in phase a, phase b and phase c, the experimental results are shown in Figure 9. Figure 9a1-a3 show output voltages corresponding, respectively, to faulty phase a, b and c with the vertical axis 100 V/grid and horizontal axis 10 ms/grid. Figure 9b1-b3 show output currents corresponding, respectively, to faulty phase a, b and c with the vertical axis 30 A/grid and horizontal axis 10 ms/grid. Figure 9c1-c3 show the voltage deviations between output voltages and reference voltages corresponding, respectively, to faulty phase a, b and c with the vertical axis 50 V/grid and horizontal axis 10 ms/grid. This can be seen from the waveforms being distorted seriously and three-phase imbalance when the inverter is operating in a faulty state. The voltage deviations between output voltages and reference voltages are too large.  
Figure 8: The experiment setup: (**a**) the main circuit board; (**b**) DSP; (**c**) the rectifier; (**d**) the load.  
Figure 9: The experimental results of the non-reconfigurable inverter (**a1**) output voltages under faulty phase a; (**a2**) output voltages under faulty phase b; (**a3**) output voltages under faulty phase c; (**b1**) currents under faulty phase a; (**b2**) currents under faulty phase b; (**b3**) currents under faulty phase c; (**c1**) voltage deviations under faulty phase a; (**c2**) voltage deviations under faulty phase b; (**c3**) voltage deviations under faulty phase c.  
Take case 1 in Table 1 as an example to verify the feasibility and validity of the proposed topology and the control algorithm. The power switch V\({}_{1}\) is faulty, and the inverter is reconstructed from TPSS to TPFS. Figure 10a1,a2 show output voltages corresponding to faulty phase a with the vertical axis 100 V/grid and horizontal axis 10 ms/grid. Figure 10b1,b2 show output currents corresponding to faulty phase a with the vertical axis 30 A/grid and horizontal axis 10 ms/grid. Figure 10c1,c2 show the voltage deviations between output voltages and reference voltages with the vertical axis 50 V/grid and horizontal axis 10 ms/grid. When the DC side voltage is set as 800 V in the reconfigurable inverter to be fault-tolerant, the experimental results of the changing process from a normal state to fault-tolerant state are shown in Figure 10a1,b1,c1. Since the DC side voltage satisfies all DC voltage conditions, it can be seen that the fault-tolerant waves are similar to the normal ones after the transient state. The inverter output voltages and output currents are standard sinusoidal waves. The deviation among inverter output voltage with reference voltage is small, and the steady experimental results are shown in Figure 10a2-c2. All the output waveforms after the inverter is reconstructed are similar to those in normal states. Other cases in Table 1 have similar results. Experimental results further verified the feasibility and validity of the proposed secondary reconfigurable topology and the control algorithm.