# Keypoint-Based Automated Component Placement Inspection for Printed Circuit Boards
## 4 Conclusions  
Experimental results show that the proposed algorithm is effective for component displacement inspection of PCBs. The algorithm provides a simple labeling process for training. The sizes of the proposed networks are also significantly lower than those of existing networks. The weight the size of the proposed Model 3 network is only 3.96% of that of DETR algorithm (i.e., 1,644,751 vs. 41,487,306, respectively). The two-stage training process is effective in feature extraction to enhance the detection accuracy. For example, for the Model 1 network, the F1 scores are improved from 0.8867 with a single-stage training process to 0.9320 by with a two-stage training process. In addition, the F1 scores for mounting hole achieved by the proposed Model 3 network, DETR, and YOLO v5 are 0.9545, 0.9341, and 0.9220, respectively. Therefore, the proposed algorithm can attain superior detection accuracy relative to existing techniques. Furthermore, the algorithm has high model reusability and low computation complexities for inspection. Even for low-cost edge devices such as Jetson Nano, the inference latency of the Model 3 network is only 146.9 ms. These advantages are beneficial for the deployment of the algorithm on edge devices for accurate and fast component inspection over large varieties of PCBs. Conceptualization, W.-J.H. and T.-M.T. ; methodology, S.-T.C. and W.-J.H. ; software, S.-T.C. ; validation, S.-T.C. and W.-J.H. ; investigation, S.-T.C. and T.-M.T. ; resources, W.-J.H. ; writing--original draft preparation, W.-J.H. ; writing--review and editing, W.-J.H. ; visualization, S.T.-C.; supervision, W.-[PERSON]; project administration, [PERSON]-[PERSON] and [PERSON]-[PERSON]; funding acquisition, W.-J.H. All authors have read and agreed to the published version of the manuscript. The original research work presented in this paper was made possible, in part, by the National Science and Technology Council, Taiwan, under grants MOST 111-2622-E-003-001 and MOST 111-2221-E-003-009-MY2. \begin{table}
\begin{tabular}{l c c c c c c} \hline \hline
**Training Process** & **Inspection Accuracy** & **Screw** & **Mounting Hole** & **Capacitor** & **3-Pin Chip** & **8-Pin Chip** \\ \hline Proposed & AP & 0.9710 & 0.9723 & 0.9605 & 0.9925 & 0.9920 \\ Model 3 & F1 & 0.9435 & 0.9545 & 0.9363 & 0.9739 & 0.9760 \\ \hline Faster RCNN & AP & 0.9680 & 0.9335 & 0.9523 & 0.9734 & 0.9895 \\ \([\)19\(]\) & F1 & 0.9078 & 0.8755 & 0.9018 & 0.9363 & 0.9702 \\ \hline DETR & AP & 0.9800 & 0.9472 & 0.9641 & 0.9944 & 0.9986 \\ \([\)24\(]\) & F1 & 0.9469 & 0.9341 & 0.9389 & 0.9735 & 0.9946 \\ \hline SSD + MobileNet & AP & 0.9218 & 0.8986 & 0.9459 & 0.9585 & 0.9799 \\ \([\)33\(]\) & F1 & 0.8425 & 0.8610 & 0.8930 & 0.9042 & 0.9833 \\ \hline YOLO v5 & AP & 0.9170 & 0.9490 & 0.9530 & 0.9840 & 0.9600 \\ \([\)34\(]\) & F1 & 0.9224 & 0.9220 & 0.9423 & 0.9771 & 0.9450 \\ \hline \hline \end{tabular}
\end{table} 
Table 6: The inspection accuracy of various component classes for various algorithms. \begin{table}
\begin{tabular}{l c c c} \hline \hline
**Algorithm** & **Weight Size** & \multicolumn{2}{c}{**Inference Latency**} \\  & & **PC** & **Jetson Nano** \\ \hline Proposed Model 3 & 1,644,751 & 21.4 ms & 146.9 ms \\ Faster RCNN [19] & 28,337,682 & 56.1 ms & NA \\ DETR [24] & 41,487,306 & 206.5 ms & NA \\ SSD + MobileNet [33] & 2,601,212 & 46.4 ms & 167.6 ms \\ \hline \hline \end{tabular}
\end{table} 
Table 7: The weight size and computation time for inference of various algorithms. **Institutional Review Board Statement:** Not applicable. **Informed Consent Statement:** Not applicable. **Data Availability Statement:** The data are contained within the article. **Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.