# Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications
## 2 Design and Optimization of the Power Amplifier
### Size Determination and Analysis of the Neutralized Capacitor  
Figure 3 shows the small-signal analysis model of the transistor. The admittance of each port is calculated using Equation (1). Each capacitance can be calculated individually, as shown in Equation (2). \[ \begin{array}{l}y_{11}=sC_{gs}+sC_{gd}\,\ \ \ \ \ \ y_{12}=-sC_{gd}\\ y_{21}=g_{m}-sC_{gd}\,\ \ \ \ \ \ y_{22}=g_{ds}+sC_{ds}+sC_{gd}\\ \end{array}  \tag{1}\]  
\[C_{gd}=-\frac{im\ (y_{12})}{\omega},\ \ \ C_{gs}=\frac{im\ (y_{11}+y_{12})}{ \omega},\ \ \ C_{gd}=\frac{im\ (y_{22}+y_{12})}{\omega} \tag{2}\]  
For the transistor with 256 \(\upmu\)m gate width (2 \(\upmu\)m unit finger width \(\times\) 32 fingers \(\times\) 4 multipliers), the parasitic capacitances are estimated as \(C_{gd}\) = 72 fF, \(C_{gs}\) = 145 fF, and \(C_{ds}\) = 149 fF. Among the three parasitic capacitances, \(C_{gd}\) in particular forms a feedback loop, resulting in instability in the PA. Therefore, to cancel out the \(C_{gd}\), a capacitive neutralization method is generally used in the mm-wave PA. In general, the required neutralized capacitance \(C_{neu}\) is extracted by simulation tuning, however, in this study, quantitative \(C_{neu}\) was calculated based on \(C_{gd}\) value. We first utilized a differential structure including \(C_{neu}\) to offset the feedback loop, after which the value of \(C_{neu}\) was extracted and the small-signal analysis was conducted. Figure 4a shows the circuit with \(C_{neu}\) applied to the differential common source structure. Figure 4b shows the schematic representation of the small-signal model of the circuit shown in Figure 4b. The admittance of each port in the small-signal analysis model is calculated as:  
\[ \begin{array}{l}i_{in}=sC_{gs}v_{in}^{\ +}+sC_{gd}\left(\frac{v_{in}^{ +}}{2}-\frac{v_{gd}^{-}}{2}\right)+sC_{neu}\left(\frac{v_{in}^{+}}{2}-\frac{v_ {gd}^{+}}{2}\right)\\ =s\left(C_{gs}+C_{gd}+C_{neu}\right)\frac{v_{in}^{+}}{2}-s\left(C_{gd}-C_{neu} \right)\frac{v_{gd}^{-}}{2}\\ \end{array}  \tag{3}\]  
Figure 3: Small signal analysis model of the common source transistor. Figure 2: Load-pull simulation result of the unit amplifier based on the transistor size. \[i_{out} =(g_{ds}+sC_{ds})v_{out}^{-}+g_{m}\frac{v_{in}^{+}}{2}\] \[+sC_{gd}\left(\frac{v_{out}^{-}}{2}-\frac{v_{in}^{+}}{2}\right)+sC_{neu }\left(\frac{v_{out}^{-}}{2}-\frac{v_{in}^{-}}{2}\right) \tag{4}\] \[=\left(g_{m}-sC_{gd}+sC_{neu}\right)\frac{v_{in}^{+}}{2}+\left(g_ {ds}+sC_{gd}+sC_{ncu}\right)\frac{v_{out}^{-}}{2}\] \[Y=\left[ \begin{array}{cc}y_{11}=\left.\frac{i_{in}}{v_{in}} \right|_{v_{out}=0}&y_{12}=\left.\frac{i_{out}}{-v_{out}}\right|_{v_{in}=0}\\ y_{21}=\left.\frac{i_{out}}{v_{in}}\right|_{v_{out}=0}&y_{22}=\left.\frac{i_{ out}}{-v_{out}}\right|_{v_{in}=0}\end{array} \right]. \tag{5}\]  
When Equations (3) and (4) are substituted in Equation (5) for the arrangement, the admittance of the alternative power cell is obtained and is given as:  
\[ \begin{array}{l}y_{11}=\frac{sC_{gd}+s\left(C_{gd}+C_{neu}\right)}{2}\;, \quad y_{12}=-\frac{s\left(C_{gd}-C_{neu}\right)}{2}\\ y_{21}=\frac{g_{m}-s\left(C_{gd}-C_{neu}\right)}{2}\;,\quad\quad y_{22}=\frac{g _{ds}+sC_{h}+s\left(C_{gd}+C_{neu}\right)}{2}\end{array}  \tag{6}\]  
As seen in Equation (6), the capacitance of the differential structure is halved, as compared to the single-end structure.