## 2 Measurement Functions of the E/A  
In this section, the hardware configuration of the E/A and its measurement functions are in short presented. The configuration of the instrument is shown in Figure 2.  
The voltages from the electrical network (3- or 4-wires) and phase currents from generating sets (up to three) are delivered to the input terminals of the signal conditioning units. The configuration of the signal conditioning units applied in the voltage channels is shown in Figure 3. The voltage dividers (VD) adapt the level of the network voltages to the value acceptable in the next parts of the measurement channels. The galvanic separation (GS) block ensures a safe operation for other circuits of the E/A. The low-pass filter is switched between 10 and 100 kHz, depending on the actual measurement function. The voltage follower (VF) provides the adequate output resistance of this part of the measurement channel. The output signal is fed to the input of the analog-to-digital converter (ADC). The network currents are measured using the current probe type LFR 1/15 (Power Electronic Measurements Ltd., Nottingham, UK) (based on the Rogowski coil). The configuration of the signal conditioning units applied in the current channels is similar to the signal conditioning unit used in the voltage channels, but in the current channels, the VD blocks are missing. The current probe signals are directly fed to the inputs of the GS blocks. The designation of coefficients describing the electrical power quality is carried out using a ADSP-TS201 TigerSHARC (Analog Devices, Norwood, MA, USA) digital signal processor (DSP) embedded on the DSP Subsystem Module (DSM; STSL stands for \"Single TigerSHARC with Logic\") (Kaztek Systems, Acton, MA, USA) [35] (Figure 2). The configuration of the DSM STSL module resources is shown in Figure 4. There is also a field-programmable gate array (FPGA) Xilinx Spartan-3 (Xilinx, Inc., San Jose, CA, USA) which is used for the data exchange between the DSP and other systems of the instrument. For the communication of DSM devices with other E/A circuits, user-defined FPGA input/output (I/O) lines were used. The user interface (Figure 2), designed for the control and selection of individual measurement functions of the instrument, is supported by the general purpose processor (GPP) LPC3250 (ARM926 EJ-S core) (NXP Semiconductors Netherlands B.V., Eindhoven, The Netherlands). This processor also controls the indication and registration of the measurement data. In Figure 5, the main operations carried out in the measurement track of the instrument, connected with data processing, are shown. They differ in the sampling rate of the electrical network signals, as well as in a set of measured quantities and therefore in the set of designated coefficients. The electrical network signals are simultaneously sampled in all voltage channels at the rate of 210 kS/s or in all of the voltage and current channels at the rate of 25 kS/s, depending on the performed measuring function of the E/A. Figure 2: The hardware structure of instrument [30]. ADC: analog-to-digital converter; DSM STSL: DSP subsystem module; FPGA: field-programmable gate array; DSP: digital signal processor; RAM: random access memory; GPP: general purpose processor; USB: universal serial bus; LCD: liquid crystal display. The algorithms of the digital data processing (DDP) used to determine the value of the individual parameters of the electrical power quality are based on the common application of the discrete wavelet transform (DWT), fast Fourier transform (FFT), discrete Fourier transform (DFT), or chirp Z-transform (CZT), performed in a complementary way [30; 36; 37]. Namely, the wavelet coefficients after respective levels of wavelet decomposition are used as the input data for various procedures employed to calculate the rms values and coefficients in the Fourier series, in combination with the transient monitoring algorithm.