# On the Use of LoRa Technology for Logic Selectivity in MV Distribution Networks
## 6 Realized Demonstrator
### Solution for Full-Duplex LoRa Communication  
Unfortunately, a serious technical limitation lies in the fact that the LoRa SX1272 transceiver only allows communication on a single channel at a time (single-band operation, programmable in the 860-1020 MHz range). In other words, only half-duplex communication can be realized by means of this hardware configuration, and it is not possible to transmit and receive simultaneously, as required in logic selectivity when a PR has to transmit a Blind message to the PR upstream and, simultaneously, has to receive the potential Blind message from the PR downstream. To overcome this limitation, two Nucleo-L073 boards plus expansion boards with SX1272 transceivers were used for each PR (as shown in Figure 6), in a master-slave architecture. One transceiver is exploited to communicate between a PR and the upstream protection on a defined channel, while the other transceiver is used to exchange messages between the same PR and the downstream protection on another channel. Master and slave communicate with one another through three dedicated digital lines. In Figure 7, an image of the realized prototype is shown. Figure 5: State machine implemented on the microcontroller of a PR. In this case, the main firmware that controls the state machine is loaded on the microcontroller of the board master and directly controls the transceiver for communication with the PR upstream, while the microcontroller of the slave card is connected to the transceiver for communication with the PR downstream. Initially, the transceivers are both configured to receive and continuously search for a preamble on the respective communication channel. Only the master can detect a fault and, when this occurs, it changes the status of its transceiver from Rx continuous mode to Tx and transmits the Blind message to the upstream PR. While the Blind transmission takes place, the transceiver connected to the slave remains in Rx continuous mode in search of a possible preamble relative to the same Blind message coming from the downstream PR. In this way, all the PRs that detect the fault can send and receive Blind messages simultaneously, as schematized in Figure 8), without the interference and overlapping of LoRa signals. If a Blind message is received from the slave transceiver, the latter alerts its master by raising the line connected to pin PA12 (input for the master and output for the slave), from low to high logic level. This event generates an interrupt of the master microcontroller that stops the \(T_{MBW}\) measurement, turns on the yellow LED to signal the reception of the Blind message, and maintains the controlled CB in a closed state (green LED on) despite the presence of the fault, in accordance with the logic selectivity criteria. On the other hand, if the slave does not signal the reception of a Blind message to the master, at the expiration of \(T_{MBW}\), the master commands the tripping of the CB (turning off the green LED) and communicates to the slave to transmit a Trip message to the downstream PR for isolating the faulty line section. In this case, the master sets the PC6 pin to the high logic level. This event generates an interrupt on the slave, whose ISR modifies the transceiver from the RX mode to the TX mode and starts the transmission of the Trip message. Figure 6: Master-slave architecture that allows the PR (i) to simultaneously communicate with the upstream protection PR (i \(-\) 1) and the downstream protection PR (i \(+\) 1). As mentioned above, under normal operating conditions, the master transceiver, which is in charge of communication with the upstream PR, is also in continuous reception mode. This allows the master to always be aware of a Trip message from the upstream PR. When a Trip message is received, the master turns on the yellow LED to signal the reception of the message and turns off the green LED to signal the tripping of its CB. In addition, the master sets the PC8 pin to the high logic level, which is output for the master and input for the slave.