# Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial
## 7 Emulation Workflow Step by Step  
Next, the different steps required to implement fault injection emulation based on the architecture defined in the previous section will be described. In this section it will be shown that two projects will be necessary. The first one is the main workspace, where the design for the experimental set-up, the UART and the SEM IP controller will be integrated for the target reliability tests. The second one is only necessary to extract and reutilize the SEM IP core files into the first one and it will be removed after this task is completed. Now, a step by step description of the emulation is detailed. First, a new RTL project for Vivado (the first one), is created including the HDL (Table 2) files that refer to both the design for the experimental set-up and UART modules. The inclusion of the SEM IP controller will be shown in detail later. Also, at this point the board model has to be selected. For this tutorial, the board is a Nexys 4 DDR with Artix-7 FPGA. Once the DUT, the golden copy and the checker are implemented, and before continuing with the process, a good practice would be to simulate and check the design for the experimental set-up. For instance, Figure 10a, the CHCK output is included for a sample circuit with no injected errors. In this trivial example both outputs defined as Y0 (CIRCUIT 1) and Y1 (CIRCUIT 2) are equal in the whole simulation, and the checker output (ERR) takes a value of 0, which indicates that no errors occur. On the contrary, the next simulation (Figure 10b) shows an error detected by the checker due to an SEU inserted via force command in the DUT. It can be observed that both outputs are different (Y0 has a value offfff and Y1 has the correct value of 03 ba) and the checker detects the error changing its output, ERR (at 168 ns), with a code different from the right one. After the verification of the experimental environment, the SEM IP controller is required to be instantiated in order to enable and control the fault injection process. This core can be found in the Vivado IP Catalog, and its maximum clock frequency meets the frequency of the board (for Nexys 4 the threshold is 100 MHz). Below this frequency the SEM IP controller works properly. Also, the controller options must be enabled. \begin{table}
\begin{tabular}{c c} \hline \hline
**Modules** & **Files** \\ \hline \multirow{5}{*}{Design for the experimental set-up} & rom.vhd \\  & circuit1.vhd \\  & circuit2.vhd \\  & checker.vhd \\  &uart.vhd \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Projects files before SEM IP core. Figure 10: (a) Simulation without an SEU. (b) Simulation with an SEU. _\"sen_0_sem_cfg, sem_0_sem_example, sem_0_sem_mon, sem_0_sem_mon_fifo, sem_0_sem_mon_piso, sem_0_sem_mon_sipo and \"sem_0_sem_example.xcd\"_. Before the synthesis and implementation processes, the original constraint file (obtained from the SEM example directly) can be customized. Pmod connectors are described for the Nexys 4 in Figure 14 and Table 3, while Figure 15 shows one of the possible configurations for this example. For this tutorial, Pmod JB and Pmod JC have been selected for both SEM IP monitor interface (RX/TX) and UART (S_OUT) respectively. It is important to highlight that this configuration is just an example, any other pin of the Pmod can be assigned to the serial interface without any modification in the final behavior, just two ports need to be available. The Nexys 4 board includes a single 100 MHz crystal oscillator connected to pin E3, which can be used as a master clock for the system. Other examples are both monitor_tx and monitor_rx lines (SEM IP monitor interface or UART) configured in the G16 and F16 belonging to the Pmod JB. Pin C17 is hard-wired and used to send a reset signal to the FPGA configuration reset button when the SEM IP cannot recover the original design after a failure provoked by an SEU. Finally, the DUT serial output that indicates if an error is provoked or not, is registered in the F6 pin.