## 5 Experimental Results
### Dynamic Switching  
The dynamic switching operation of the single WSS (WSS1 in Figure 4) is first investigated. The WDM packets arriving at WSS 1 in Module 1 are de-multiplexed and controlled individually by the gate SOAs. The switch controller will turn on one or multiple gates to forward the packets, and the selected wavelength channels are multiplexed at the WSS output. The traces of the WDM input packets (shown in black) are illustrated in Figure 9. Each packet labelled with the wavelength channel needs to be switched to the Output 1, while packets labelled with \"M\" means that multiple gates are enabled for multicasting operation. The switch controls (Ctrl 1 to Ctrl4) generated by the FPGA and applied to the four SOA gates of the WSS are also illustrated in Figure 9. The signals are synchronized with the packets and \"on\" states correspond to a bias current of 40 mA. The packets of the four channels (CH 1-4) are fast switched (\(\sim\)10 nanoseconds) and the outputs are presented in Figure 9. The traces indicate that the packets are properly switched according to the control signals with a contrast ratio larger than 28 dB. As a second system assessment, the dynamic switching operation of the four WSSs has been investigated. In this case, packets at wavelength Channel 1 (1525 nm) is switched to one of the four output ports by controlling the Channel 1 SOA gates of the four WSS. The traces of the input packets, the control signals, and the switched outputs are reported in Figure 10. The input packets are labelled with the destination output ports and broadcasting (\"B\") to two or more ports is also enabled by turning on multiple SOA gates. It can be seen from Figure 10 that the fast dynamic switching operation in space, wavelength, as well as time domains are fully supported by the WDM fast optical switch PIC. To quantify the performance of the fast optical switch PIC, the BER curves for each WDM channel at different data rates are measured and the results are shown in Figure 11a-c. The back-to-back (B2B) curves are also included for reference. The gate SOA for the channel under test is supplied with a 60 mA driving current and the output is amplified and sent to the BER tester (BERT). When the single wavelength channel is input to the PIC (shown in blue curves), error-free o  
Figure 9: Traces for four channels in WSS1 destined to Output 1. 0.5 dB have been measured for Channel 1 (CH 1) and Channel 3 (CH 3) at different data rates while, for Channel 2 (CH 2) and Channel 4 (CH 4), the penalty was around 1 dB at 10 Gb/s, 20 Gb/s, and 2 dB at 40 Gb/s data rate. The eye diagrams of the switched output are also reported and confirm the signal degradation, mainly due to accumulated noise for CH 2 and CH 4. When all four WDM input channels are fed into the switch, the BER results (shown as red curves) indicate a slight performance degradation with an extra penalty of around 0.5 dB for CH 1 and CH 3 and 1 dB for CH 2 and CH 4 compared with single wavelength operation for the different data rates. Figure 11: BER curves for single channel and WDM channel input at (**a**) 10 Gb/s; (**b**) 20 Gb/s; and (**c**) 40 Gb/s. Figure 10: Traces for Channel 1 in Module 1 destined to four outputs. It can be seen from the assessment results that the WDM fast optical switch PIC can dynamically handle the WDM data traffic within a few nanoseconds in space and wavelength domains. Error-free operation has been measured for 10 Gb/s, 20 Gb/s, and 40 Gb/s in single, as well as multiple, WDM channels with <1.5 dB and <3 dB penalty for CH 1/3 and CH 2/4, respectively. As reported in the characterizations, CH 2 and 4 experience extra losses due to the substantial optical power coupling between the channels caused by the not fully resolved waveguides after the de-multiplexer AWG.