# A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis
## 2 TSV Metrology  
Etching is the basis of the whole TSV preparation process, which directly affects the subsequent seed layer deposition effect and has a great impact on the TSV filling quality and service reliability. TSV etching has many requirements, including good control of through-hole dimensions (through-hole depth and width), sufficient selectivity for etch masks, minimal sidewall roughness, and high throughput. The TSV etch is typically performed using reactive ion etching (RIE) to create high aspect ratio vias. The current mainstream method of etching is deep reactive ion etching (DRIE), invented by Bosch(Robert Bosch GmbH), which uses SF6 as the reactive gas to etch silicon while periodically releasing C4F8 as a passivation gas to protect the sidewalls to achieve high aspect ratio vertical TSV etching [22] (Figure 2). The process alternates between deposition and etch steps to fabricate deep vias [10]. Except for in specific environments, the Bosch process is widely used, which allows deep features to be etched in Si at etch rates ranging from 1 to 3 \(\upmu\)m/min with a 50:1 to 100:1 mask material selectivity for photoresists and a 150:1 to 200:1 selectivity for photoresists for oxide masks [22; 23; 24].  
DRIE or deep reactive ion etching is a popular technique for etching deep and precise holes in silicon wafers. While DRIE offers excellent controllability in terms of creating intricate patterns and structures, there are still some reliability concerns that need to be addressed. One such issue is the occurrence of sidewall defects that can affect the overall quality and integrity of the structure. To ensure the quality of the structures produced by DRIE, TSV inspection is carried out. TSV inspection can be divided into two categories of parameters. The first category is post-RIE inspection, which is performed to measure critical dimensions, depth, and profile, including the sidewall angle and through-hole curvature. This helps ensure that the structures meet the required specifications and tolerances. The second category of TSV inspection is metal fill, which is carried out to check for voids that may be present in the metal layer used to fill the holes. Voids can cause reliability problems, such as electrical shorts or open circuits, so it is essential to identify and eliminate them. By performing both types of TSV inspection, manufacturers can ensure that the structures produced by DRIE are of high quality and reliability [10].  
Because of the finite electron and hole mobility in silicon and because the via MOS junction capacitance will introduce additional distributed parameters, namely, inductance, dissipation, and skin depth, it is very difficult to succinctly describe equivalent electrical parameters. TSVs are essentially metal insulator semiconductor (MIS) devices with a dielectric layer of SiO2 deposited to isolate the metal from the substrate. Due to the extremely wide bandwidth and high frequency, the corresponding TSV modeling and design will be very different from its conventional frequency band counterparts. When TSVs operate in the low frequency range, the metal oxide semiconductor (MOS) effect in TSVs should be carefully considered and modeled as MOS capacitance. When the TSV operates in the UHF and very high frequency (millimeter wave range) range, the effect of MOS capacitance on the TSV electrical performance decreases and some key issues that have a significant impact on the TSV performance need to be considered. One of the important issues is the sidewall roughness, which can generate large leakage currents in the high frequency range and severely affect the current flowing through the TSV. The effect of roughness needs to be considered in the millimeter wave frequency range due to the skinning effect [25; 26].  
Figure 2: (**a**) Etching schematic; (**b**) Bosch process schematic (**c**); TSV samples (adapted from [22]).