## 3 Experimental Results
The maximum recorded quality factor of 1586 was achieved at 1.9 GHz under bias voltages Vctrl = 0.43 V and Vctrl2 = 0.41 V. The measurement trends in Figures 11 and 12 align with those discussed in SS2.2, confirming the design's expected behavior. Nevertheless, due to parasitic effects in the fabricated structure, the measured values of Leq and Q differ slightly from the simulation results. Such discrepancies are typical in practical implementations, where parasitic capacitances, resistances, and layout-related effects influence circuit behavior. The quality factor naturally varies with frequency due to the frequency-dependent characteristics of the transconductors. Slight shifts in equivalent inductance and self-resonant frequency were also observed, with some measured values exceeding simulation predictions. Figure 11: Variation in equivalent inductance and quality factor as a function of (**a**) Vctrl with constant gd85 and (**b**) Vctrl2 with fixed Rf. Figure 12: Input inductance values for the proposed AI’s input impedance under different control voltages Vctrl and Vctrl2: (**a**) simulated and (**b**) measured. A primary factor contributing to variations in the quality factor is the frequency-dependent behavior of the transconductors, wherein the transconductance \(\mathrm{g_{m}}\) decreases slightly at higher frequencies, thereby affecting the impedance transformation. Additional degradation arises from parasitic capacitances, specifically the gate-source (\(\mathrm{C_{gs}}\)) and gate-drain (\(\mathrm{C_{gd}}\)) capacitances, along with the finite output resistance of the transistors, all of which introduce losses that reduce the quality factor across most frequencies. Furthermore, deviations in fabrication processes, such as reduced oxide thickness or variations in interconnect geometry, can alter effective parasitic capacitances, exacerbating this anomaly. In practical RFIC implementations, such fluctuations in the quality factor can impair circuit performance, leading to diminished selectivity in bandpass filters, increased insertion loss in impedance matching networks, and degraded phase noise characteristics in oscillators. Table 2 provides a comparative performance analysis between the proposed active inductor fabricated in this work and previously reported designs in the literature. The proposed design achieves an inductance tuning range of 6.7 nH to 84.4 nH, significantly broader than those reported in prior works, which typically remain below 25 nH. Although the design in Ref. [28] reports an inductance of 191 nH, this value lacks experimental verification and thus remains to be validated. Furthermore, the proposed design achieves a maximum quality factor \(\mathrm{Q_{max}}\) of 1586, which substantially exceeds other reported values, such as the value of 28 in Ref. [36] and the value of 45 in Ref. [37]. The power consumption of the active inductors in Refs. [37; 38] is reported to be 21 mW and 16 mW, respectively, exceeding the 2 mW consumption of the proposed design by more than ten and eight times, respectively. A further advantage of the proposed inductor is its compact layout area of 308 \(\mathrm{\SIUnitSymbolMicro m}^{2}\), which is significantly smaller than those of existing designs (typically ranging from 3200 to 8200 \(\mathrm{\SIUnitSymbolMicro m}^{2}\)), enhancing its suitability for integration in compact RF systems. Nevertheless, certain trade-offs are inherent. The wide tunability and high Q performance render the design more sensitive to variations in bias voltage, necessitating accurate bias stabilization to ensure consistent operation under process and temperature fluctuations. This requirement may increase overall system-level design complexity. Furthermore, the design may exhibit reduced linearity at higher signal amplitudes, which could constrain its applicability in circuits demanding high linearity, such as precision low-noise amplifiers.