# Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions
## 1 Introduction
### Virtual Coarse-Grained Reconfigurable Architectures  
Due to the lack of mature, commonly available physical CGRA architectures and both enormous costs and extremely long development of custom ASIC CGRA, virtual architectures implemented as overlays atop FPGAs are not uncommon [4; 5; 6; 7; 8; 9; 10; 11; 12; 13; 14; 15]. Apart from serving prototyping purposes for architecture development, Virtual Coarse-Grained Reconfigurable Architectures (VCGRAs) can be used to provide a convenient high abstraction layer for FPGA-based systems end users. As the underlying hardware is still fine-grained, the approach does not offer performance gains, energy efficiency improvements, nor reductions of space overhead in silicon. Nevertheless, it can be used to simplify the system description and narrow down the design space, therefore reducing the development cycle (develop, implement, debug) time, which is crucial whenever time-to-market is essential.  
Mapping an application onto an FPGA with an intermediate overlay layer comprises two distinctive tasks: front-end (application onto virtual architecture) and back-end (overlay onto physical FPGA) mapping. Considering that the overlay architecture is only temporarily formed within the FPGA fabric, the entire virtual architecture can be altered and remodeled if it benefits mapping or execution. In other words, there are two levels of reconfigurability--adjustments of VCGRA configuration for minor and entire overlay replacement for major changes. Functional changes of the coarse blocks can be performed by using register-based circuit switching within a single FPGA configuration, dynamic partial reconfiguration for block content swapping, or a combination of the two. The latter approach offers a virtually unlimited number of possible PE variants and resource utilization overhead reduction, but changing functionality takes much longer as it requires reprogramming a section of FPGA. It also entails binding overlay blocks to certain regions of the underlying chip.  
Xilinx FPGAs use module-based partial reconfiguration (also referred to as Dynamic Function Exchange). Top-level logic is divided into a set of individually reprogrammable modules and a static part. On a higher abstraction level the reconfigurable partitions can be treated as processing elements of a CGRA. Normally, each instance of a functional module uses individual, location-specific implementation. Consequently, an array of N \(\times\) M identical PEs requires N \(\times\) M implementations for each configuration. However, it is possible to force relocatability of the modules, so that common implementation results could be used regardless of location.  
This study presents a methodology for mapping custom coarse-grained overlay architectures with fully reconfigurable processing elements onto Xilinx FPGAs. The innovative aspect of the proposed approach is that it uses reconfigurable partition based virtual coarse blocks with module relocation used to reduce the number of location-specific implementations. The proposed design flow can be divided into the following stages:  
* Definition of virtual coarse block interface;
* Specification of its resource requirements;
* Identification of potential partition regions in the target FPGA chip;
* Floorplanning of virtual coarse blocks;
* Implementation of the static part of the architecture with black-box modules;
* Implementation of any desired functionality in a relocatable reference coarse block.  
The methodology allows coarse-grained blocks array scaling and easy migration between different physical platforms. Although the proposed methods were developed for Xilinx 7-Series devices, they should be easily adaptable to Xilinx UltraScale FPGAs, as the architectural differences are mostly low level.