# An Interleaved DC/DC Converter with Soft-switching Characteristic and high Step-up Ratio
## 2 Proposed Circuit Configuration and Operation Analysis
### Circuit Analysis
The voltages \(v_{L1}\), \(v_{L2}\) and \(v_{T}\) are expressed as  
Figure 5:0  
Figure 5:1  
Figure 5:2During this mode, \(C_{DS2}\) is discharged and \(v_{DS2}\) keeps decreasing. From Equations(13) - (15), \(v_{L1}\) decreases. On the contrary, \(v_{L2}\) and \(v_{T}\) both increase. As soon as \(v_{DS2}\) decreases to \(-0.7\) V, \(i_{L2}\) diverts from \(C_{DS2}\) to \(D_{S2}\) and Mode II ends. C. Mode III (\(t_{2}<t<t_{3}\))  
The equivalent circuit of Mode III is shown in Figure 4c. Neglecting the diode conduction voltage (0.7 V), the voltage equations for both converters are  
Figure 5:3  
Figure 5:4  
Adding Equation (16) and Equation (17) results in  
Figure 5:5  
Substituting Equations (4) and (8) into Equation (18) leads to  
Figure 5:6  
Substituting Equation (19) into Equations (16) and (17) results in  
Figure 5:7  
From Equations (19) and (20), \(v_{T}\), \(v_{L1}\), and \(v_{L2}\) are all positive. Since the mutual inductance \(L_{M}\) is usually much higher than the leakage inductance \(L_{l}\), the \(v_{L1}\) and \(v_{L2}\) are very small and the currents \(i_{L1}\) and \(i_{L2}\) rises slowly. During this mode, \(D_{S2}\) is on and the drain to source voltage of \(S_{2}\) is clamped at 0.7 V. The gated voltage \(v_{GS2}\) becomes high level before \(i_{L2}\) rises to zero. When \(i_{L2}\) rises to zero and then becomes positive, \(S_{2}\) is turned on at ZVS and Mode III ends. D. Mode IV (\(t_{3}<t<t_{4}\))  
The voltage equations for \(v_{T}\), \(v_{L1}\), and \(v_{L2}\) are as same as that of Mode III. The voltages \(v_{T}\), \(v_{L1}\), and \(v_{L2}\) are all positive. Therefore, the currents \(i_{LM}\), \(i_{L1}\), and \(i_{L2}\) keep rising. When the gated voltage \(v_{GS1}\) becomes zero volts. \(S_{1}\) is turned off and the circuit enters Mode V.  
E. Mode V (\(t_{4}<t<t5_{4}\))- H. Mode VIII (\(t_{7}<t<t_{8}\))  
The equivalent circuits of Mode V to Mode VIII are shown in Figure 4e-h, respectively. Owing to the symmetrical operation for both boost converters, the operation of Mode V - Mode VIII is similar to the operation of Mode I- Mode IV. As soon as \(v_{GS2}\) drops zero, \(S_{2}\) is turned off and Mode VIII ends. The circuit goes to the first mode of the next high frequency cycle. **3. Design Equations**  
Since the mutual inductance \(L_{M}\) is large enough, \(I_{LM}\) is assumed to be constant. Based on the principle of energy conservation, the output power is equal to  
Figure 5:8  
where \(\eta\) represents the circuit conversion efficiency. From (21), \(I_{LM}\) can be expressed as  
Figure 5:9By assuming that the mutual inductance \(L_{M}\) is much larger than the leakage inductance \(L_{l}\), from Equations (9)-(11), \(v_{T}\), \(v_{L1}\), and \(v_{L2}\) in Mode I are approximately equal to  
\[V_{in}=v_{L1}+v_{T}, \tag{5}\]0  
\[V_{in}=v_{L1}+v_{T}, \tag{5}\]1  
\[V_{in}=v_{L1}+v_{T}, \tag{5}\]2  
In practical circuits, parasitic capacitors are very small. It takes only a short time to fully discharge the parasitic capacitor. It means that the period of Mode II is very short and hence \(i_{L2}\) is near zero at the end of this mode. Based on Equation (3), the peak value of \(i_{L2}\) is approximately equal to \(I_{LM}\). In Mode I, \(i_{L2}\) decreases and the time required for the current \(i_{L2}\) to drop from its maximum value to zero is equal to  
\[V_{in}=v_{L1}+v_{T}, \tag{5}\]3  
The voltage equations for \(v_{T}\) in Mode I and in Mode III and Mode IV are Equations (9) and (19), respectively. At steady state, its average value should be zero. \[V_{in}=v_{L1}+v_{T}, \tag{5}\]4  
where \(t_{f}\) is the period of Mode I and \(t_{r}\) is that of Mode III plus Mode IV. The fall time \(t_{f}\) plus the rise time \(t_{r}\) equals to half of the switching period  
\[V_{in}=v_{L1}+v_{T}, \tag{5}\]5  
where \(T_{s}\) represents the switching period.