# EXPRESS: Exploiting Energy-Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage
###### Abstract  
The density and cost-effectiveness of flash memory chips continue to increase, driven by: (a) The continuous physical scaling of memory cells in a single layer; (b) The vertical stacking of multiple layers; and (c) Logical scaling through storing multiple bits of information in a single memory cell. The physical properties of flash memories impose disproportionate latency and energy expenditures to ensure the high integrity of the data during flash memory writes. This paper experimentally explores this disproportionality on state-of-the-art commercial 3D NAND flash memories and introduces EXPRESS--a technique for increasing the energy efficiency of flash memory writes by exploiting the premature termination of the flash write operations. An experimental evaluation shows that EXPRESS reduces energy expenditures by 20-50%, relative to the traditional flash writes, at the cost of a minimal loss in the data integrity (<1%). In addition, we evaluate the effects of the page-to-page variability, program-erase cycling, and data retention on the implementation of EXPRESS, and we propose enhancements to counter these effects. 3D NAND; flash; MLC; layer variation; energy; memory storage +
Footnote †: journal: _electronics_  
0000-0002-4000-0002-0000-00002-  
Even though NAND flash-memory-based storage solutions require less power than other nonvolatile storage solutions, e.g., hard disk drives, they still account for a significant portion of the total energy expenditures of computing systems [11]. Several recent research proposals have emphasized the prospect of approximate storage for achieving high-energy efficiency in the emerging edge-computing applications [11; 12; 13; 14; 15; 16; 17; 18]. To curb the energy consumption of flash memories in ultra-low-power microcontrollers, [PERSON] et al. [18] propose an energy-saving technique utilizing lower operating voltages, which jeopardize the correct memory operations. To remedy the possible loss of information, they employed: (a) Repeated in-place write operations; (b) Multiple-places write operations; or (c) The RS-Berger coding of data. They report energy savings for in-place write operations of up to 34% on lower-end microcontrollers. Similarly, a study by [PERSON] et al. [12] shows that up to 45% of the energy consumed could be saved using dynamic voltage scaling on the basis of the flash operations being performed. [PERSON] et al. [14] propose an approximate storage technique in solid-state memories by relaxing the threshold voltage margins between different memory states during the write operations by using varying program pulse widths. Through detailed simulation, they show that their proposal would make the memory write 1.7 times faster. However, the implementation of their method on the common-off-the-shelf (COTS) NAND chips requires privileged commands that are not available in the ONFI command set. [PERSON] et al. [16] propose leveraging the approximate data in the NAND flash memory to improve the read performance and enhance the reliability of regular data. [PERSON] et al. [19] find that the energy required by flash write operations heavily depends on data patterns. Thus, they propose an encoding scheme that minimizes the frequency of power-hungry bit patterns in codewords ('10' and '01'), reducing the total energy of the flash write operations by up to 34%. [PERSON] et al. [20] propose a lazy amnesic-compression-based technique for storing data in flash memories. The required energy for the flash write operations is reduced by using a lossy compression; the compression ratio is adjusted on the basis of the age of the data. [PERSON] et al. introduce Capsule [11], a log-structured object storage system for flash memories that supports the fine-grain allocation of space for storage objects, such as streams, files, arrays, and queues. [PERSON] and [PERSON] [13] introduce a technique that reduces the time and energy consumed by the critical flash operations in embedded NOR memories by introducing partial or aborted flash operations.