## 2 Simulation  
To optimize the performance of semiconductor chips, it is essential to conduct a detailed analysis of the structural characteristics of interconnects and vias and derive a design that maximizes current transfer efficiency. This study analyzes the impact of via geometry (length and width) on resistance and current density in metal line-via-metal line structures and investigates the feasibility of reducing the design margin between interconnects and vias. To achieve this, FEM-based simulations were performed using the Ansys Simulation Tool, and the current flow was analyzed under various via structures and misalignment conditions [13]. Although various analytical methods, such as the Monte Carlo approach, are available for analyzing semiconductor structures, the FEM uniquely segments structures into finely divided elements and precisely incorporates conditions for each segment and boundary. Therefore, we determined that the FEM is the most suitable method for accurately capturing detailed current flow patterns within interconnect structures. First, a precise analysis was conducted on how variations in via dimensions and reductions in the interconnect-via contact area affect resistance and current density distribution using FEM-based simulations. The simulations were carried out using Ansys Workbench, and a mesh size of 1 \(\upmu\)m was applied to determine the resolution of the analysis model for accurate current density distribution and resistance values [14]. If the mesh size is too large, changes in current density may not be properly reflected, reducing the reliability of the analysis results. Therefore, to accurately analyze the regions where current is concentrated inside the via, an appropriate mesh size of 1 \(\upmu\)m was chosen. The voltage was applied horizontally at 3 V, modeling a structure where current flows from a metal interconnect through the via and back into the interconnect. To examine the impact of via structure variations on resistance, three different structures were investigated. The upper and lower interconnects each have a length of 40 \(\upmu\)m and a width of 20 \(\upmu\)m. Three different via structures were inserted between them for analysis. The current was applied such that it flowed through the upper interconnect, passed through the via, and then continued through the lower interconnect. A reference structure (10 \(\upmu\)m \(\times\) 10 \(\upmu\)m) was compared with two additional structures: (20 \(\upmu\)m \(\times\) 5 \(\upmu\)m), where current encounters the via the fastest, and (5 \(\upmu\)m \(\times\) 20 \(\upmu\)m), where current encounters the via the slowest. This approach aims to clearly identify the impact of via geometry by ensuring that the current flow direction and via area remain identical, eliminating any variations in current density that might arise solely from area differences. Figure 2a-c illustrate the via structures, which were designed with dimensions of 10 \(\times\) 10 \(\upmu\)m, 5 \(\times\) 20 \(\upmu\)m, and 20 \(\times\) 5 \(\upmu\)m, respectively. All structures maintain an identical area of 100 \(\upmu\)m\({}^{2}\) to minimize differences in current density and isolate the effects of shape on resistance. If the total via area varied, the overall current-carrying capacity of the via would change, potentially altering the distribution of current density. Therefore, by keeping the area constant while adjusting the length-to-width ratio, this study aims to clearly compare the relationship between the current flow direction and via shape and quantitatively evaluate its impact on resistance. The simulation results in Figure 3 reveal that the highest total resistance was observed in the (5 \(\times\) 20 \(\upmu\)m) structure (Figure 2b), whereas the lowest resistance was found in the (20 \(\times\) 5 \(\upmu\)m) structure (Figure 2c). These results indicate that increasing the via length in the direction of the current flow reduces resistance.