# A Review of Advanced CMOS RF Power Amplifier Architecture Trends for Low Power 5G Wireless Networks
## Advanced RF PA Architectures
### Doherty RF PA (DPA)  
Originally proposed in early 1936 by [PERSON], the widely adopted and thoroughly investigated, DPA was resurrected at the beginning of this century [39]. In spite of more than 80 years from its introduction, the DPA actually seems to be one of the best candidates to realize PA stage for current and future generations of wireless systems [9]. The Doherty power amplifier is based on the active load concept, to suitable modulate (decrease) the impedance termination of an active amplifying device, thus forcing the latter to operate at its maximum efficiency condition for a pre-determined range of input and/or output power levels. The standard DPA architecture, presented in Figure 5, is composed of a main amplifier, whose output load is modulated through the auxiliary amplifier. The active load concept is highly dependent on the output impedance inverter therefore the latter receives a lot on researcher attention. DPA power added efficiency can be expressed using the following equation  
\[\eta_{PAE}=\frac{P_{out}-P_{in}}{\sum\limits_{n=1}^{m}V_{DDn}I_{DQn}} \tag{3}\]  
where \(V_{DDn}\) is power supply of the \(n\)-th PA in the DPA configuration, \(I_{DQn}\) is the quiescent current consumed by the latter PA, \(m\)--total parallel PA branches. A summary of papers reporting DPA research results and parameter improvement solutions in CMOS and BiCMOS processes is presented in Table 4. It is to be noted, that all DPAs in the following table are narrowband due to the nature of the architecture and are intended to exhibit maximum performance at a certain frequency. The output power and supply voltages are in the range of portable device specs and the back-off power of 5-10 dB provides overall system _PAE_ of 21-51%. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Ref.** & **Process** & \(V_{\text{DD}}\)**, **V** & **Frequency,** & **Plinear,** & **Overall** & **Back-off Power** \\  & & & **GHz** & **dBm** & _PAE_, \%** & **Range, dB** \\ \hline
[40] & 350 nm _SiGe_ BiCMOS & 5 & 3.5 & 30 & 25 & 10 \\
[41] & 250 nm _SiGe_ BiCMOS & 2.5 & 5.6 & 22 & 25 & 6 \\
[42] & 180 nm CMOS & 3.7 & 3.5 & 24.4 & 36.1 & 6 \\
[43] & 180 nm CMOS & 3.3 & 2.4 & 29.5 & 22 & 5 \\
[44] & 130 nm CMOS & 3.3 & 2.4 & 31.9 & 30.1 & 5 \\
[45] & 130 nm CMOS & 3 & 2.4 & 22 & 45 & 7 \\
[46] & 90 nm CMOS & 3.3 & 2.4 & 30 & 24 & 5 \\
[47] & 90 nm CMOS & 2.4 & 2.4 & 24.8 & 26 & 5 \\
[48] & 65 nm CMOS & 5.5 & 2.535 & 23.4 & 25 & 8.5 \\
[49] & 65 nm CMOS & 2.5 & 2.4 & 23.4 & 24.7 & 7 \\
[50] & 40 nm CMOS & 1.5 & - & 23.4 & 23.3 & 6 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Summary of reviewed DPAs in CMOS and BiCMOS processes. Figure 5: Simplified DPA architecture diagram. DPA architecture advantages:  
1. High efficiency--load-pull concept implemented in the DPA utilizes \(\lambda/4\) microstrips and lets the designer achieve higher overall _PAE_ with less complex additional circuit solutions (opposed to ET architecture) at any single frequency band. Moreover, the DPA is near to its peak efficiency in the whole back-off power range;
2. Linearization techniques, such as feed-forward and predistortion can be implemented without any constraints;
3. Simplicity--no complex circuitry reacting to the input signal required (opposed to ET/EER architecture);
4. A combination of multiple PAs in different biasing classes possible. The traditional DPA consists of the Main linear PA and the Aux nonlinear one. DPA architecture is not restricted to only the latter combination, as multiple-way DPAs are also possible where every PA works in a different biasing class;
5. Lumped and distributed impedance inverters are possible. Both the impedance inverter and the power splitter as well as the delay compensation can be implemented using lumped and distributed approaches [51; 52]. DPA architecture disadvantages:  
1. Increased losses in RF path due to the presence of power splitter and combiner;
2. High synchronization precision between RF paths required. Main and auxiliary RF path lengths (delays) must be equal for maximum efficiency;
3.