# Key Roles of Plasmonics in Wireless THz Nanocommunications--A Survey
## 1 Introduction
Despite the fact that new efficient methods have been introduced based on modern system architectures via the utilization of new technologies for manipulating THz Band signals by the research academia, still there are many challenges to face, such as the very high propagation signal loss, the impedance mismatch between THz link components, the limited size restrictions along with integration potentials, associated with high bandwidth availability and ultrafast operating data rates with minimum latency requirements. Conventional CMOS based electronic interconnects are definitely far from the target to meet THz speed, low propagation signal loss, and the impedance match between THz link components. Current CMOS scaling technology growth has restricted the cut-off frequency and the maximum oscillation frequency of the device to several hundreds of a GHz. Traditionally, the operating frequency should be much below the cut-off frequency when designing  
Figure 1: Applications for wireless THz nanocommunications. mixed-signal circuits at high frequencies, and the CMOS device technology applied, should be capable of continuously scaling down the size and values of on-chip components (e.g., transistors, capacitors, and inductors), in order to achieve higher throughput and reduced circuit footprints [8]. Evidently, at THz frequencies this approach has weak potential for improvements, which are further limited by the loss encountered in on-chip metal structures [9]. The alternatives for such a case, would be either to search for a new implementation technology that offers better scaling prospects and a higher intrinsic transit frequency, or to exploit the non-linearities of the device for efficient power generation at higher-order harmonics. As concerns the latter, there are approaches that use novel circuit to generate, radiate, and control THz frequencies widely adopted in academia and industry [10], however it is high time for other technologies to take this on, at this critical stage. Artificial intelligence (AI) computing with its hot AI chip topic may be an alternative for CMOS wired interconnection and NoC architectures, against CMOS process and device bottleneck and Von Neumann and memory wall bottlenecks. In a broader sense, the AI chip is the adoption of AI principles in computing processing systems in the form of accelerators, in order to boost their computing performance. AI approaches such as processing-in-memory (PIM), machine learning (ML), and especially neural network (NN)-based accelerators, such as FPGA, GPU and ASIC, are considered as mature solutions for speeding up computing performance [11]. PIM or near data computing (NDC), is a promising solution to tackle with the memory wall bottleneck. PIM architectures put additional computation logic in or near memory by leveraging 3D memory technologies to integrate computation logic with memory, thus speeding up NN computations on larger memory capacity and bandwidth, via in-memory data communication, at the same time. The metal-oxide resistive random access memory (ReRAM) has showed great potential to be used for main memory, with its crossbar array structure, capable for performing matrix vector multiplication efficiently, and accelerating NN computations [12]. However, as processing system scalability increases, AI processing loads are getting more and more data-intensive and demand higher bandwidth and heavy data movement between computing logic and memory. Hence, when the scale of the NN computation and accelerator increases, the NoC-based data communication within NN accelerators would evidently have to deal with a performance bottleneck. In addition to performance, the energy consumption of the NoC in an NN accelerator may be also a big challenge to deal with. Particularly, when all this AI processing is done at the edge level, embedded in sensors, smartphones or general IOT equipment, there are more strict power requirements and the need for much more specific hardware implementations [13].