# Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing
## 3 Results and Discussion
### Binarized Neural Networks Applications  
As the adoption of deep learning and neural networks is becoming more and more pervasive, the demand for energy efficient hardware accelerators is rapidly growing. When considering neural networks, the most effective way to improve energy efficiency is to avoid the VNB by performing computations in-memory [45; 46; 47; 48]. A common approach exploits resistive memory crossbar arrays to implement in analog the vector matrix multiplication in a single step [45]. However, reliability issues affecting RRAM devices, such as the large cycle-to-cycle variability, limit the number of bits that can be reliably stored in a single device [49] thus suggesting that low-bit precision neural networks are a more suitable solution for the current state of the art RRAM devices. The extreme case of low-bit precision neural networks are BNNs, which have been shown to retain high classification accuracy despite the use of single-bit neuron weights and activations [5; 50; 51]. While the in-memory computation of the analog vector matrix multiplication is extremely attractive [6; 7; 50; 52], it \begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline  
* Reported means that the value was explicitly reported by the authors in the paper. Estimated means that the corresponding value has been inferred from data in the paper, although not explicitly reported by the authors. **\({}^{**}\)** This information can be trusted only if a physics-based model is used.  
\begin{tabular}{c c c} \hline \hline  & \begin{tabular}{c} **Number of** \\ **Computing Devices** \\ \end{tabular} & **Energy** & **Delay** & \begin{tabular}{c} **Energy-Delay** \\ **Product (EDP)** \\ **of the** **S** \\ **of the** **S** \\ \end{tabular} & \
\begin{tabular}{c} **EDI Improvement** \\ **Normalized** \\ **to** **CMOS w/VNB** \\ \end{tabular} \\ \hline
\begin{tabular}{c} CMOS w/ VNB \({}^{*}\) \\ \end{tabular} & 163840–458752 FET & \(\approx\)85.5 \(\mu\)J & \(\approx\) 2.6 ms & \(\approx\) 2.2 \(\times\) 10\({}^{-7}\) J\({}^{*}\) & 1 \\ CMOS w/o VNB \({}^{**}\) & 163840–458752 FET & \(\approx\)8.8 \(\times\) 10\({}^{-7}\)–107 nJ & \(\approx\) 0.2–1.2 \(\times\) 10\({}^{5}\) ns & \(\approx\) 2.5 \(\times\) 10\({}^{-25}\)-1.4 \(\times\) \\ **This Work \({}^{***}\)** & **18944 RRAM** & \(\approx\)**68.8 nJ** & \(\approx\)**1.3 \(\mu\)s** & \(\approx\)**88.9 \(\times\) 10\({}^{-14}\) J\({}^{*}\) & **2.4 \(\times\) 10\({}^{6}\)** \\ **Projections** \\ **I\({}_{\text{C}}\) = 10 nA f = 1 GHz** & **18944 RRAM** & \(\approx\)**6.88 pJ** & \(\approx\)**0.65 \(\mu\)s** & \(\approx\)**4.5 \(\times\) 10\({}^{-18}\) J\({}^{*}\) & **4.9 \(\times\) 10\({}^{10}\)** \\ *** & & & & & \\ \hline \hline \end{tabular}  
* * *, estimates with (w/) and without (w/o) including the VNB energy and delay overhead for reading and writing 4 kb data [39]. ** CMOS FA performances were estimated projecting the time and energies for different 1-bit FA schemes and different CMOS technologies (i.e., 0.18 \(\mu\)m, 45 nm, and 10 nm) from [40; 41; 42] combined in a ripple carry configuration. ***, *** Worst-case energy estimates considering the maximum energy for each single 1-bit FA operation using Technology 3, see Figure 8b. This results in an energy overestimation that approximately accounts for additional energy overhead possibly introduced by the peripheral circuit (i.e., analog tri-state buffers contributions). *** Projections using optimized devices with IC = 10 nA [43] and f = 1 GHz [44].  
\end{table} 
Table 4: Detailed comparison among the proposed and existing FAs in the literature. SIMPLY, IMPLY, and Hybrid-CMOS LiM solutions (both experimental and simulation works). has some limitations and tradeoffs. In fact, this approach lacks the possibility to reconfigure the type of operation to be computed in-memory. Since neurons in BNNs perform logic operations, the BNNs inference can be implemented in the SIMPLY architecture, as shown in [30] where a BNN was implemented using the 2-SIMPLY.