## 5 Experimental Results and Analysis
### Algorithm Complexity Analysis  
In multi-symbol detection algorithms, the computational load primarily arises from the correlation operations between the signal within the observation interval and the local reference signals. Therefore, this paper analyzes the algorithm's complexity from the perspective of correlation operations. Initially, a theoretical analysis of the correlation operation formulas for three algorithms is conducted. Subsequently, the algorithms are deployed on FPGA boards to verify their actual hardware resource consumption. The details are as follows. Figure 9: Baseband signal algorithm demodulation performance diagram. The resource consumption of three MSD algorithms was evaluated to assess their computational efficiency. In the Tr-MSD algorithm, with an observation interval of \(N\) and \(N_{s}\) sampling points per symbol, the number of local reference signals is \(2^{N+2}\), and the number of multiplications required for correlation operations is \(NN_{s}2^{N+2}\). In the DFB-MSD algorithm, the number of local reference signals and correlation operations are halved by leveraging already-decoded symbols, resulting in \(NN_{s}2^{N+1}\) multiplications. In the Lc-MSD algorithm, the local reference signals are optimized in two stages: the first stage averages the local reference signals, reducing storage and correlation operations by 75%, while the second stage exploits the symmetrical structure of the local reference signals to further reduce storage and correlation operations by 50%. Thus, the number of multiplications required is \(NN_{s}2^{N-1}\). Table 2 compares the number of local reference signals and the multiplication operations among the three algorithms. Using simulation parameters (\(N=5\), \(N_{s}=4\)), the Tr-MSD algorithm requires 128 local reference signals and 2560 multiplications. The DFB-MSD algorithm also requires 128 local reference signals but reduces the multiplication operations to 1280. The Lc-MSD algorithm requires only 16 local reference signals and 320 multiplications, representing an 87.5% reduction in the number of local reference signals and a 75% reduction in multiplication operations compared to the DFB-MSD algorithm. It is noteworthy that for \(N=3\) and \(N=7\), the reduction proportions in local reference signals and multiplication operations are identical to those for \(N=5\). Hardware measuring of the Tr-MSD algorithm and the Lc-MSD algorithm was conducted, with resource consumption on the hardware platform evaluated at \(N=5\), as shown in Table 3. The Lc-MSD algorithm includes two scenarios: with and without FIR filter optimization. The results demonstrate that without FIR filter optimization, the total consumption of DSP resources, which is one of the critical FPGA hardware resources, decreased from 3072 to 384, representing an 87.5% reduction, in accordance with the theoretical analysis of resource consumption. Moreover, since the resource consumption of the MSD algorithm is primarily concentrated in correlation operations, the total consumption of other hardware resources also decreased significantly, approaching an 87.5% reduction. For the optimization of the FIR filter, the proposed algorithm optimizes the single-channel and single-coefficient filters to the four-channel and double-coefficient filters, which does not affect the demodulation performance but further reduces resource consumption. DSP resource consumption decreased from 384 to 320, representing a nearly 25% reduction. Combined, the two optimizations reduced DSP resource consumption from 3072 to 320, achieving a total reduction of approximately 90%. Correspondingly, RAM and register resource consumption were also reduced by about 90%, while LUT resource consumption was reduced by approximately 85%.