# Automatic Configurable Hardware Code Generation for Software-Defined Radios+
## 6 Hardware Model Using Finite State Machines
### FSM Composition  
The composition of FSMs leads to a single FSM with a set of states which is the product of the set of states of FSMs of the HW blocks in the system. For a closed FSM which we use in this work, each composite state has output signals with propagation that is instantaneous. The transition from the present state to the next takes place on every rising edge of the system clock. An example of a composite FSM \(M=M_{X}\times M_{FF}\times M_{Y}\) is shown in Figure 7b. Figure 7a is the black-box representation of M which is composed of the source HW block FSM (i.e., \(M_{X}\)), FIFO buffer FSM (i.e., \(M_{FF}\)) and a sink HW block FSM (i.e., \(M_{Y}\)). Since \(M\) is a Moore machine, it only has outputs signals namely write-enable \(w\), data-valid \(v\) and read-enable \(r\) as defined in Section 5.3. The upper half of each state labels the state \(s_{i}\) where \(i=\{0...N-1\}\) and \(N\) is the total number of states. The lower half of each state is either a single-dimensional or a two-dimensional vector of the output signals \(w\), \(r\), and \(v\). A format \(wrv\) is used  
Figure 6: Timing diagram of a source actor, the FIFO channel and a sink actor (based on Figure 5). to represent a single-dimensional vector and a two-dimensional vector of a single state is represented in a form of \([w_{i}r_{i}v_{i}\,w_{1}r_{1}v_{1}\,w_{2}r_{2}v_{2}\,...\,\,w_{N-1}r_{N-1}v_{N-1}]\) that has a sequential order. This two-dimensional vector is therefore associated with a state that has a _loop_ transition and the vector length equals the number of times iterated by the _loop_ transition in synchronous to the system clock. The values of all the three output signals are obtained using the 1-periodic schedule as explained in Section 5.3. Generally, for every valid execution schedule that leads to a finite buffer size such as the one in Figure 2, the composite FSM can be correctly constructed by matching the source actor execution pattern \(EP*,p\) to the output signal \(w\), and the sink actor execution pattern \(EP*,q\) to the output signal \(v\). Please note that the output signal \(r\) is the \(-180^{\circ}\) phase-shifted version of output signal \(v\). The FSM \(M\) example in Figure 6(b) has features which are key to understanding execution properties of a generated hardware system. First, it is important to note that the order of transitions in \(M\) is sequential where each transition is synchronous to a fundamental system clock. The initial finite sequence of states and transitions is called the _startup phase_, and followed by this is another sequence which repeats infinitely and is referred to as a _periodic phase_. The output signals of the states in the startup phase are in the form of a two-dimensional vector where all their values are set to 0 (i.e., \(w=r=v=0\)). In our example, there is only one state (i.e., \(s_{0}\)) and one transition in this phase. The periodic phase has 12 states and transitions starting from \(s_{1}\) to \(s_{12}\). The iteration period \(T\) is determined by counting the number of transitions in the period phase of FSM \(M\) phase in Figure 6(b). Furthermore, the number of data samples produced (resp. consumed) to (resp. from) the output (resp. input) channel correspond to number of output signal \(w\) (resp. \(v\)) where their values is set high (i.e., \(w=v=1\)). The produced samples are always equal to the consumed samples and in our example we obtain 12. The throughput is determined by dividing the count of one of the output signals (i.e., \(w\) or \(v\) or \(r\) where its value is set to 1) by number of transitions in the periodic phase where in our example we obtain the throughput value of \(6/12=0.5\) measured in samples per cycle (SPC). The iteration latency (\(IL\)) is the sum of all the the transitions in the startup phase and periodic phase and in the example of Figure 7 IL is 13.