## 1 Introduction  
In modern communication systems, analog-to-digital converters play an important role. They can convert analog signals to digital signals. Among many kinds of analog-to-digital converters (ADCs), the successive-approximation-register (SAR) ADCs are widely accepted due to their low design complexity. Additionally, the newest single-channel SAR analog-to-digital converter (ADC) operates at 12-bit, 1 GS/s [1]. However, the center frequency of the 5G signal is above 1 GHz, which requires a higher sampling rate for the SAR ADC. In 1980, a special framework of ADC, which is named time-interleaved analog-to-digital converters (TI-ADCs) has been proposed by [PERSON] [2]. Based on this special framework, an \(M\)-channel TI-ADCs system can achieve a sampling rate M times faster than a single channel. Nevertheless, there are some mismatches between different sub-ADCs in the special framework. Additionally, the mismatches include offset, gain, time skew, and bandwidth mismatch [3, 4, 5, 6]. In the TI-ADCs system, the mismatches lead to a discrepancy between the actual output digital signal and the ideal output digital signal. Therefore, these mismatches should be estimated and corrected to improve the performance of the TI-ADCs system. Background calibration [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] and foreground calibration [19, 20, 21, 22] are two of the categories for the calibration techniques of TI-ADCs. Foreground calibration means calibrating mismatches before sampling the target signal in the TI-ADCs system. Additionally, these techniques generally calibrate mismatches by a specific signal [19; 20; 21]. The whole calibration process is completed before the input signal is sampled. If the changes in pressure, volume, and temperature lead to changes in mismatches after the foreground calibrations are completed, the changed mismatches will not be calibrated. Moreover, the performance of foreground calibration is affected by the accuracy of the specific signal. Based on these reasons, this article aims to research a background calibration in the TI-ADCs system. The background calibration can be divided into the following two steps: mismatches estimation and mismatches correction. The offset and gain can be corrected with digital adders and digital multipliers, respectively [16]. The time skew can be corrected by adjusting the sampling clock [8; 9] or digitally controlled variable delay lines (VDLs) [15] or the derivative filter [10; 11; 14; 16; 17] or the adaptive filter [13]. When the time skew is corrected by adjusting the sampling clock, the effect of the correction depends on the accuracy of the adjustment. Therefore, high-precision circuits are required to adjust the sampling clock in the ultra-high-speed TI-ADCs system. The time skew can be corrected with kinds of filters to avoid demanding hardware circuits. However, the derivative filter is applied to correct the time skew, which limits the size of the time skew [13]. The bandwidth mismatch can be corrected by adjusting the sample and hold circuit [6] or the cascaded derivative filter or the adaptive filter [4]. Compared with digital correction technologies, using analog circuits to correct time skew and bandwidth mismatch does not involve many digital calculation modules. Therefore, analog correction technologies are suitable for on-chip TI-ADCs. However, they require state-of-the-art manufacturing technologies because of the increasing frequency of the input signals. Figure 1 is the conceptual graph of an \(M\)-channel time-interleaved analog-to-digital conversion system. Here, \(\text{CLK}_{i}\) is the sample clock of the sub-ADC, \(M\) is the number of channels, and \(\Phi_{i}\) is the initial phase of \(\text{CLK}_{i}\): \(o_{i}\), \(g_{i}\), \(\tau_{i}\), and \(H_{\omega_{i}}(i\omega)\) are offset, gain, time skew [7], and bandwidth mismatch [21], respectively. Firstly, the \(M\) sub-ADCs convert the input signal into digital signals by a time-interleaved technique [2].