## 3 Results: AGA Logic Variables for Scene Description and Dialog Communications
### Communication Module and the Dialog Protocol
And such tasks traditionally involve low-level programming and detailed modeling of memory resources. Proposed in the paper programs complement a dozen microassembler subroutines, which were earlier presented in [68,69] for LL scheme. These designs provided basic necessary functions of AGA for agent operation and its interface with PC. Presented microassembler software was tested with the help of the dual-chip module [68,69], based on two 24 MHz ATMEL (Taipei, Taiwan) microcontrollers MCS-51. In order to show the prospect of this simple 8-bit platform, Figure 14 demonstrates the design of its cascaded version, designed for further experiments with the communication module. It is formed by the pair of sequentially connected microcontroller dual-chip cascades from [68,69], modified by digital 8-bit feedback bus. Its role is to provide flexible forward/backward data exchange between modules, controlled by means of several control pins. The bidirectional transfer of data is supposed to be used by both \"upper\" and \"lower\"

Figure 13: Two-dimensional logic diagram displays events classified only by logic constants 5 and 6 for the AGA function given in Table 2. This band of constants is limited by the criteria \(C_{k}=\{5,6\}\). To obtain convenient visuality, diagrams for close classes of objects may be preliminarily decoded into the natural-number code. dual-chip modules, in order to expand peripheral modules. Like in [68; 69], the conjugation with the peripheral devices is to use bus registers, triggered on the leading edge. The designed algorithms and software have the platform for further expansion toward dialog communications of agents. The advantage of such device is the pair of conjugated microcontrollers connected to common data and address buses, what provides the possibility to use them in parallel or to exploit the doubled set of operators (500-600 ones per MCS-51 chip) for common data written in SRAM and ROM. Such structure simplifies the design and programming of AGA procedures and helps to separate data acquisition and procession procedures. Besides this, it gives more possibilities to combine connections of pins and to add new trigger registers for alternative memory chips, connected to the common data bus. Two types of integrated memory SRAM and ROM chips are used to separate fixed basic parameters from variative and optional ones. This cascaded scheme currently has 1 MB SRAM and 512 KB EEPROM external memory chips, connected to common data, and addresses 8-bit buses. It provided comparatively free data resending and memory planning for laboratory experiments. That is the reason to use dual-chip schemes instead of commercial kits like Arduino [89], although they can use greater work frequencies. Figure 14: Two dual-chip modules are necessary to process full-scale dialog phrases, based on the proposed vocabulary structure. Blue line is the common addressing 8-bit bus, and green line is the common data 8-bit bus. Bold black line is the output data bus and the digital feedback. For the sake of brevity, we will not discuss here the possible radiofrequency and optoelectronic data channels, or the possibilities to connect them to the dual-chip scheme. In any way, for such designs one needs to describe transmitters/receivers by some words in the vocabulary structure and to reserve memory resources and several free pins in microcontrollers for control signals. These steps can somewhat enlarge the overall time response due to the increased number of control pins and trigger registers. However, for the proposed scheme of vocabularies there is the only requirement, which is to use equal 8-byte parts of phrases and to coordinate all vocabularies. As in [55], trigger registers Rg1, 2, and 3 are intended for SRAM addressing, where pins \(\overline{CE}\), \(\overline{OE}\), and \(\overline{WE}\) control read/write process. Banks P0 in MCI and MCII are used for data exchange with SRAM&ROM. Port P3 in MCII is used for clocking procedures, where direct and inverted signals of pins P3.0-P3.4 control read/write procedures.