## 4 Enhancement Strategy for Decoding  
Since the HSD NAND flash has high storage space but relatively lower read speed, we care more about reading performance than the extra storage space taken up. We hereby proposed the enhancement strategies to accelerate decoding convergence with extrinsic information from the redundancy, making up the rate penalty caused by it. To detect and correct errors in HSD NAND flash, the low-density parity-check codes (LDPC) [23; 24] are usually used, which are suitable for scenarios that the code rates are higher than 2/3 [25]. Typically, the code rate in NAND flash is above 0.8 and even reaches 0.95, and the block length is also very large, up to 8 Kbit or even 20 Kbit [26; 27; 28]. Moreover, the encoding and decoding of LDPC can be easily implemented in parallel to increase throughput [29; 30; 31; 22]. Among types of LDPC codes, quasi-cyclic LDPC (QC-LDPC) code [32] is a structured LDPC code recommended because it satisfies the row/column constraint to make sure no loop iteration in decoding which otherwise can result in decoding failure [33; 34; 35]. The decoding of QC-LDPC can have no error floor down to \(10^{-10}\)[29]. There are two kinds of LDPC decoding algorithms, hard-decision decoding and soft-decision decoding. The hard-decision directly converts received symbols into demodulated bits \"0\" or \"1\", whereas the soft decision is based on the probability of received symbols, expressed using logarithmic likelihood rate (LLR), to decide the most likely value for the corresponding bit. LLR is presented as  
\[L_{v_{j}}=\log\frac{\Pr\left(\hat{y}_{j}=0\mid y_{j}\right)}{\Pr\left(\hat{y}_ {j}=1\mid y_{j}\right)}, \tag{1}\]  
where \(L_{v_{j}}\) is the LLR value, \(\hat{y}_{j}\) is the transmitted bit, and \(y_{j}\) is the received bit. The posterior probability \(\Pr\left(\hat{y}_{j}\mid y_{j}\right)\) is determined by BER of the received codeword. The hard-decision decoding algorithms include majority logic decoding and bit flip decoding [23], which are characterized by low complexity, fast speed, but weak error correction capability. The most widely used soft-decision decoding algorithms are sum-product algorithm (SPA) and minimum sum algorithm (MSA), a simplification of SPA [24; 30]. The computational complexity of soft-decision algorithms is much higher than the hard-decision ones, but their error-correction capability is stronger. Figure 10 represents our enhancement strategies for bit-flip decoding and SPA decoding. The content and position of the true-value sequence are known. For bit flip decoding, as in Figure 10a, denote the position of true-value sequence as \(loc_{tr}\), the number of parity violation for each bit of the read codeword as \(f_{i,i=1,2,3,\dots}\), the positions of the maximum in \(f\) as \(loc_{pv}\), and the position of bit flipping as \(loc_{bf}\). Before decoding starts, fill back the true values to the read codeword. Then, calculate the number of parity violation for each bit. Find the positions where the maximum number of parity violations are, and remove the positions of the true values if there is any to get the position of the bits to be flipped \(loc_{bf}\). While \(loc_{bf}\) is null, give \(loc_{bf}\) the positions of the second maximum in \(f\). Repeat the above procedures until there is no parity violation or the program reaches its max iterations. As shown in Figure 11, the enhancement strategy gives the bit flip decoding better error performance, so more errors can be corrected by hard decision in the same number of iterations. Therefore, \(BER_{th}\) can be slightly increased in switching decoding statuses accordingly, and more decoding can use the hard-decision algorithm. The flash reading speed is thus increased at lower RBER.