# FPGA-Based Methodology for Detecting Positional Accuracy Degradation in Industrial Robots
## 3 Results and Discussion
The resources are referred to in the \"logic utilization\" column. Specifically, the columns \"Used\", \"Available\", and \"Utilization\" indicate the total number of elements implemented, available elements, and the percentage of elements used, respectively. In general, according to the information in Table 6, it is possible to say that the device used half of its resources for this implementation. The hardware-software execution time for the complete system is 564,720 ms. Before the neural network classifier, the average error between the software (e.g., Matlab) and the FPGA calculation for the modules before the classifier amounts to 0.87%. However, the accuracy obtained by the neural network module reaches 83% compared to the accuracy obtained in the software implementation. It should be noted that the accuracy obtained by the neural network and the average error are attributable to the fixed point representation. The results obtained from the hardware implementation validate the use of the proposed method to detect deviations in the robot's joints through the analysis of the motor currents. Regarding the results obtained in this work, it should be noted that specifically for joint five of the real case, the results coincide with those reported in [53], where the same dataset was used, and a manual analysis of velocity and position graphs of the joint was conducted without a systematic approach. In another study [17] MRA and DLSTM are used to obtain the residual error of the end-effector of the robot. However, it is not determined in which joint exhibited deviation causing the error in the end-effector. On the other hand in [18] an expert system based on two neural networks, dimension reduction, and energy and fractal indicators was presented. This system aimed to accurately detect deviations in the robot's joints. However, implementing the fractal approach in FPGA was found to be more complex than the statistical indicators proposed in this current study. It's worth noting that the aforementioned studies were performed using software simulation and offline analysis, which didn't pose resource limitations or fixed-point operation issues, in contrast with an FPGA system. The method proposed identifies in which joint of the \begin{table}
\begin{tabular}{l c c c} \hline \hline
**Logic Utilization** & **Used** & **Available** & **Utilization** \\ \hline Number of Slice Registers & 10,090 & 54,576 & 18\% \\ Number of Slice LUTs & 12,521 & 27,288 & 45\% \\ Number of fully used LUT-FF & 4662 & 17,949 & 25\% \\ Number of bonded IGBs & 128 & 218 & 58\% \\ Number of Block RAM/FIFO & 59 & 116 & 50\% \\ Number of BUFG/BUFGCTRLs & 1 & 16 & 6\% \\ Number of DSP48A1s & 32 & 58 & 55\% \\ \hline \hline \end{tabular}
\end{table} 
Table 6: System resource utilization. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Soft-Core** & **Complete** & **Calculation** & **Complete** & **Calculation** \\
**Processing** & **Processing** & **Processing** & **Processing** \\
**(Clock Cycles)** & **(Clock Cycles)** & **(Time)** & **(Time)** & **(Time)** \\ \hline DWT & 265,577 & 178,280 & 5.53 ms & 3.71 ms \\ Statistical & 7970 & 5400 & 166 μs & 112.5 μs \\ Neural Network & 3940 & 3590 & 82 μs & 78.8 μs \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Module performance in hardware implementation. robot there is deviation, uses techniques and algorithms that are easy to implement on FPGA systems, and employs a low-cost self-designed board that operates independently without the need for external systems which allows for systematic in-situ analysis.