# Research and Implementation of High-Efficiency and Low-Complexity LDPC Coding Algorithm
## 5 Design and Implementation of the Codec
### Decoder Design and Implementation  
#### 5.3.1 Decoder Design  
The decoding process is conducted by MSA algorithm and corresponding serial implementation structure is shown in Figure 12. For detail, the serial structure of the MSA algorithm comprises a variable node processor (VNP), check node processor (CNP), intermediate message RAM, control unit, and all types of data storage devices. \begin{table}
\begin{tabular}{c c c c c} \hline
**Site Type** & **Used** & **Fixed** & **Available** & **Util\%** \\ \hline Slice LUTs * & 10,752 & 0 & 53,200 & 20.00 \\ \hline LUT as Logic & 10,752 & 0 & 53,200 & 20.00 \\ \hline LUT as Memory & 0 & 0 & 17,400 & 0.00 \\ \hline Slice Registers & 12,658 & 0 & 106,400 & 12.00 \\ \hline Register as Flip Flop & 12,658 & 0 & 106,400 & 12.00 \\ \hline Register as Latch & 0 & 0 & 106,400 & 0.00 \\ \hline F7 Muxes & 1904 & 0 & 26,600 & 7.00 \\ \hline F8 Muxes & 888 & 0 & 13,300 & 7.00 \\ \hline \end{tabular}
\end{table} 
Table 4: Encoder resource use report. * represent The name annotation of logical devices in Xilinx Zynq7020 FPGA hardware resources can be deleted. Figure 11: The coder’s hardware test results. The solid boxes represent The data information of the check bit \(p_{2}\) generated during the encoding process. Variable Node Processor (VNP)  
The variable node processor has two functions: one is to input and output data information, and the other is to update the information of variable nodes. During the initialization phase, due to the fact that all data stored in Message RAM is 0, after the first sum operation, the input data is sequentially the corresponding channel information. VNP completes the update function of variable node information according to Equation (30). Verify Node Processor (CNP)  
The function of the verification node processor is to update the information of the verification node, and the CNP completes the update function of the verification node information according to Equation (34). The intermediate information storage is a dual-port RAM, with one port read-only and the other port write-only. VNP and CNP sequentially read and write Message RAM through the control of enable signals. The capacity of Message RAM is set to 24576 bits, which means that the bit width of RAM is 4 and the depth is 6144. The control unit completes the control functions of the decoding system, including controlling the number of iterations, controlling the working state of nodes, and controlling the output of decoding end code words. Interleaver  
During the implementation of the decoder, only one Message RAM is used to store data. When storing VNP and CNP data, an interleaver is needed to interleave and reorder the CNP data to improve the error performance of the decoder. The data relationships in the interleaver are uniquely determined by the check matrix. Other module units  
Initial data storage (Src-Mem): This is used to store data to be decoded, with a data width of 4 bits and a depth of 6144.Decoding Result Memory (Result-Mem): This is used to store the data output after decoding, with a data width of 4 bits and a depth of 6144. In the decoder implementation process, the correctness and feasibility of the decoding algorithm and design flow completely adopt the decoder's design implementation and  
Figure 12: Functional block diagram of the decoder designed through the serial structure of the MSA algorithm. evaluation, meeting the demands and verifying the correctness and feasibility of the research design. 1 MATLAB simulation results  
In order to verify the correctness and feasibility of the decoder design, the M files of each component module of the decoder design were first written on MATLAB, and then the M files of the entire decoder were simulated. Through the research and analysis of the simulation waveform, the correctness of the designed decoder was determined. In the MATLAB simulation process, the input of the decoder is the data information transmitted through the channel after encoding and modulation.