## 1 Introduction  
In recent years, silicon carbide (SiC) has attracted extensive attention and has been gradually applied to power semiconductor devices due to its higher breakdown electric field, electron saturation velocity and thermal conductivity than conventional silicon (Si) materials [1; 2; 3; 4; 5]. In addition, increasing switching frequency has always been a common method to push up the power density and facilitate the miniaturization of switching converters by reducing the size of the passive components [6; 7]. With a significant increase in switching speed, the effect of parasitic elements that mainly result from power semiconductor devices and PCB traces on switching performance can no longer be ignored and the losses become a crucial factor that determines the converter efficiency. Therefore, it is necessary to accurately calculate the loss of power devices and analyze the effects of the parasitic elements on it, helping designers to acquire in-depth knowledge of the switching loss mechanisms. There is considerable research in this filed. As discussed in [8], basically, investigation into loss can be classified into three categories. They are physical model, behavioral model, and analytical model (also called mathematical model). Based on the knowledge of semiconductor physics and microelectronics, the physical model solves the characteristic expression of power devices by conducting the finite element analysis (FEA) [9; 10; 11; 12]. The simulation results of physical model match the experimental results very well. However, this kind of model needs comprehensive parameters of the power device, such as gate oxide thickness, doping concentration in the channel, electron mobility, etc., which are difficult to obtain and the modeling process is rather complex and time-consuming, which is not suitable for circuit-level simulation. The behavior model is widely used in the loss analysis because it has a good trade-off between the accuracy and simulation time. Based on the values obtained from parameter extraction (normally, device manufacturer provides these data or models on their website), the effect of parasitic elements including the junction capacitances of power devices and the stray inductances of the PCB traces on switching loss can be analyzed by circuit simulation software, e.g., PSpice or Saber, in which behavioral model of the MOSFET is used [13; 14; 15]. In [14], with specific modifications of the conventional Si power MOSFET model based on PSpice, an improved behavioral model is proposed for 10-kV SiC MOSFETs to validly predict switching loss. However, it cannot suffice to explain the switching loss mechanisms of the power device behind the simulation results. The last method is the analytical model [16; 17; 18; 19; 20; 21; 22; 23; 24]. Generally, the switching loss expressions are derived from different equivalent circuits according to different stages on switching transients. The simplest and classical analytical model is the piecewise linear model, which is easier to obtain and solve than the aforementioned two model. However, there are many limitations in such a model; for example, ([16]) the analytical model only considers the gate resistance and the junction capacitances (the switching process is equivalent to the charging and discharging process of the RC circuit). In practice, especially in high-frequency operation, the effect of parasitic inductances cannot be totally ignored. Other analytical models that consider both junction capacitances and parasitic inductances have also been proposed. The effect of the parasitic elements on switching performance in low-voltage operation (the voltage lower than 40 V) has been extensively discussed in [17; 18; 19; 20]. In low-voltage operation, the drain-source voltage may reach zero before the drain current reaches the steady-state value during the turn-on transients and the drain current may drop to zero before the drain-source voltage reaches bus voltage during the turn-off transients [19].