# Real-Time Localization of Epileptogenic Foci EEG Signals: An FPGA-Based Implementation
## 3 Hardware Implementation and Computational Method
### Computation of the RT-EPI Algorithm
#### 3.4.1 Algorithm Description
This minimum set of features achieves a classification accuracy of 95% using a Neural Network and five seconds of segment length. In addition, the optimum number of neurons in the hidden layer of the neural network is 25, as it can be shown in the analysis of Figure 3.

Thus, from that point we will assume that the implementation is done by a neural network of type perceptron with just one hidden layer of 25 hidden neurons and two output neurons in the output layer (provided the two classes of this classification problem). In addition, the neural network will have five input neurons, because five is the dimensionality of the selected number of features, which, in turn, would be computed from window lengths of 5 fiveseconds of the input signal. \begin{table}
\begin{tabular}{l c c} \hline \hline
**Features** & \\ \hline Root Mean Square & \(RMS_{x}=\sqrt{\frac{1}{N}\sum_{i=1}^{N}x_{i}^{2}}\) \\ Skewness & \(s=\frac{E(x-\mu)^{3}}{(E(x-\mu)^{2})^{\frac{3}{2}}}\) \\ Derivative Variance Ratio & \(RatioVar=\frac{\sigma_{\Delta}}{\sigma_{|\Delta|}}\) & \(with\ \Delta(i)=x(i)-x(i-1)\) \\ Relative Energy Ratio & \(rE=\frac{\sum_{i=2-8m}P(x)}{\sum_{i=12m}P(x)}\) & with \(P(x)\) the Spectral Power \\ Log Energy Spectral Entropy & \(LogEnt=\sum log2(P(x)^{2})\) \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Set of selected features. \begin{table}
\begin{tabular}{l l c c} \hline \hline
**Acronym** & **Classifier** & **Prediction Speed** & **Memory Usage** \\ \hline \([TreeCoarse]\) & Decision Tree (Coarse Tree) & Fast & Small \\ \([TreeMedium]\) & Decision Tree (Medium Tree) & Fast & Small \\ \([TreeFine]\) & Decision Tree (Fine Tree) & Fast & Small \\ \([DiscrLin]\) & Discriminant Analysis (Linear Discriminant) & Fast & Small \\ \([DiscrQuad]\) & Discriminant Analysis (Quadratic Discriminant) & Fast & Large \\ \([RegrLog]\) & Logistic Regression & Fast & Medium \\ \([SVMLin]\) & Support Vector Machine (Linear SVM) & Fast\({}^{1}\) & Medium \\ \([SVMQuad]\) & Support Vector Machine (Quadratic SVM) & Fast\({}^{2}\) & Medium\({}^{3}\) \\ \([SVMCubic]\) & Support Vector Machine (Cubic SVM) & Fast\({}^{2}\) & Medium\({}^{3}\) \\ \([SVMFineGaus]\) & Support Vector Machine (Fine Gaussian SVM) & Fast\({}^{2}\) & Medium\({}^{3}\) \\ \([SVMMedGaus]\) & Support Vector Machine (Medium Gaussian SVM) & Fast\({}^{2}\) & Medium\({}^{3}\) \\ \([SVMCourseGaus]\) & Support Vector Machine (Coarse Gaussian SVM) & Fast\({}^{2}\) & Medium\({}^{3}\) \\ \([KNNFine]\) & Nearest Neighbor (Fine KNN) & Medium & Medium \\ \([KNNMedium]\) & Nearest Neighbor (Medium KNN) & Medium & Medium \\ \([KNNCourse]\) & Nearest Neighbor (Coarse KNN) & Medium & Medium \\ \([KNNCosine]\) & Nearest Neighbor (Cosine KNN) & Medium & Medium \\ \([KNNCubic]\) & Nearest Neighbor (Cubic KNN) & Slow & Medium \\ \([KNNWeigthed]\) & Nearest Neighbor (Weighted KNN) & Medium & Medium \\ \([BoostTrees]\) & Ensemble (Boosted Trees) & Fast & Low \\ \([BaggTrees]\) & Ensemble (Bagged Trees) & Medium & High \\ \([SubspaceDiscr]\) & Ensemble (Subspace Discriminant) & Medium & Low \\ \([SubspaceKNN]\) & Ensemble (Subspace KNN) & Medium & Medium \\ \([RUSBoostTrees]\) & Ensemble (RUSBoost Trees) & Fast & Low \\ \([NeuralNetwork]\) & Neural Network (3-Layer Perceptron) & Fast\({}^{6}\) & Low\({}^{6}\) \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Acronyms, prediction speed and memory usage characteristics of all the classification models used in this work. Figure 2: Classification accuracy for all the classification models (using the selected set of features) in front of the window length. As can be seen, the neural network model enabled us to achieve 95% accuracy for a window of five seconds. ### Hardware Resources Analysis

Table 4 gathers all the resource analysis results. It also shows resource usage as a percentage of occupation of the Xilinx XC7 VX1140T FPGA, intending to provide an idea of the design occupancy in current FPGAs. It can be seen that the design demands near the same DSP48E slices for both designs, 133 for single precision and 137 for double precision.