## 2 TIA Design
### Post-Amplifier  
A post-amplifier is used to provide additional voltage gain after the TIA stage. First, the inter-stage buffer circuit shown in Figure 5 is used to sense the TIA output voltage and drive the following VGA block. The buffer consists of DC coupled cascaded emitter followers, simultaneously realizing high input impedance and low output impedance, both desirable properties for voltage buffering. The first pair (Q1-Q2) makes use of single finger devices to lower the capacitive loading to the preceding stage, while being able to drive the larger capacitance of the subsequent pair (Q3-Q4) implemented with three finger devices, having a higher driving capability towards the following stages. Current sources at the emitter nodes are realized with a cascaded current mirror at the first EF pair (same sizing as Q1-Q2), while a regular current mirror is used in the second pair (same sizing as Q3-Q4). Additional voltage is dropped by a diode at the collector node of the second pair for proper headroom allocation. All transistors are biased at 1.4 mA per finger. The circuit is subsequently used between the VGA and CGA stages in the post-amplifier. Additionally, it is also used as an output buffer, since it features the optimal driving characteristics towards the envelope detector following the TIA.  
Figure 6 shows the schematic circuit for the VGA and CGA stages. The VGA, represented in Figure 6a, is implemented as a Gilbert cell, where the offset voltage for the center transistor pair in the switching quad (transistors Q5-Q6) is used to control the gain. Emitter degeneration in the bottom transistor pair (Q1-Q2) is used to linearize the response while providing increased input impedance. Values for the collector resistor R\({}_{\text{C}}\) and emitter resistor R\({}_{\text{E}}\) are 174 \(\Omega\) and 35 \(\Omega\), respectively. The tail current source for the bottom pair is implemented with a current mirror providing bias current of 1.4 mA per finger to the active devices (Q1-Q4 when Q5-Q6 are switched off), with all transistors in the stage being two finger devices. The CGA, shown in Figure 6b, follows the same topology, where the center transistor pair from the switching quad is simply removed, leaving out a standard cascode amplifier. Due to both stages featuring a high output impedance, and together with the high input impedance of the inter-stage EF buffers, the top collector for both stages remains a high impedance node. The relatively small parasitic capacitance contributions from the different components, as well as the associated layout interconnects, can thus impose significant bandwidth limitations at this node. To compensate for this effect, shunt inductive peaking is used at the top collector nodes in both stages, provided by inductor L\({}_{\text{C}}\) with an inductance value of 0.22 nH obtained from EM simulation. This helps with  
Figure 5: Schematic of the cascaded emitter followers used as an inter-stage buffer. The same stage is also used as an output buffer for the complete circuit.  
speeding up the critical nodes, effectively overcoming the bandwidth limitations. As can be observed in the different subcircuit schematics, AC coupling is used at different nodes throughout the circuit. The use of AC coupling, enabled by the bandpass characteristic of the TIA, is preferred since it can provide additional voltage headroom clearance while avoiding the need for DC offset cancellation circuitry.