# A Seabed Real-Time Sensing System for In-Situ Long-Term Multi-Parameter Observation Applications
## 5 Test Results  
### System Reliability Verification  
In order to verify the CPLD/FPGA based system design of the anti-crash mechanism, fault detection and automatic isolation mechanism, the simulation method based on Mentor's Modelsim and the actual system test method based on oscilloscope monitoring are adopted respectively. Modelsim is the hardware description language (HDL) simulation software which supports the hybrid simulation of VHDL and Verilog HDL. It is the preferred simulation software for the design of CPLD/FPGA [19].  
(1). System Anti-Crash Mechanism Verification  
Figure 13 shows the Modelsim based simulation results of the system anti-crash logic design. The above timing diagram shows that the CPLD logic detected an abnormal system work status signal to give the system a power-off control signal. The below timing diagram shows that the CPLD logic did not give a power-off control signal because a normal signal was detected.  
In order to further verify the correctness of logical design. The system is debugged online. An oscilloscope is used to observe the system work status signal and the system anti-crash control signal. As shown in Figure 14, the green line is the system work status signal and the yellow line is the system anti-crash control signal. When the system crashes (executing to program breakpoint) for 200 ms, the system anti-crash control signal is given. The test results show that the system anti-crash mechanism is effective.  
(2). Fault Detection and Automatic Isolation Verification  
SRSS/ILMO adopts the overcurrent protection scheme consisting of digital processing logic and fast comparator to realize automatic overcurrent fault isolation of external sensors or other devices. The system external power supply circuit switch uses P-channel MOS IRF5210S which is the weakest part of the power supply circuit. Therefore, the fault detection and automatic isolation design is based on the safe operating conditions of IRF5210S. According to the datasheet, the safe operating condition of IRF5210S is \(\mathrm{i}\,\mathrm{I}\mathrm{D}\)! = 200 A @ duration \(\leq\) 100 \(\mathrm{\SIUnitSymbolMicro s}\). Considering the safety margin and the working current of external sensors, the protection current threshold is set to 3 A, as shown in Table 4. In order to avoid the influence of peak current in the power-on process, CPLD digital logic adopts a time integration algorithm. The integration time is set to 20 \(\mathrm{\SIUnitSymbolMicro s}\).  
Figure 15 shows the Modelsim based simulation results of the system fault detection and automatic isolation design. When the overcurrent comparator output signal is low, the integrator starts working. When the integral value reaches the threshold, the logic gives an over-current protection signal.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Sensors** & **Voltage** & **Normal Working Current** & **Protection Threshold Current** \\ \hline Resistivity & 24 V & 0.375 A & 3 A \\ Modem & 16 V & 0.6 A & 3 A \\ FBG-PPS & 12 V & 1.25 A & 3 A \\ PA200 & 12 V & 0.08 A & 3 A \\ TCM XB & 5 V & 0.02 A & 3 A \\ \hline \hline \end{tabular}
\end{table}
Table 4: Operating parameters of external sensors of SRSS/ILMO.  
Figure 14: System anti-crash function test results.  
In order to further verify the correctness of logical design. The system is debugged online. An oscilloscope is used to observe the overcurrent comparator output signal, over-current protection control signal, and the external power supply signal. As shown in Figure 16, the yellow line is the overcurrent comparator output signal, the green line is the over-current protection control signal, and the blue line is the external power supply signal. The comparator circuit operation is delayed about 30 \(\upmu\)s, and the integrator is set to an integration time of 20 \(\upmu\)s, so it takes about 50 \(\upmu\)s from fault detection to isolation, and the protection time is in the safe operation conditions. The test results show that the system fault detection and automatic isolation design is effective.