## 4 Conclusions  
This research aimed to design and develop an efficient digital FPGA-based SAR processor with consideration of hardware resources, processing speed and several optimization schemes. In-depth exploration and discussion of the architectures of the proposed FPGA-based SAR processor was carried out. A MATLAB-based SAR processing algorithm RDA was developed as the benchmark for the development of the SAR processor. The Altera Stratix IV GX FPGA EP4 SGX230 KF40C2 was used for the design and implementation of an FPGA-based SAR processor. Comprehensive evaluations and analyses were conducted to evaluate all the submodules of the FPGA-based SAR processor. The evaluation shows that overall, the SAR processor is capable of processing SAR images with a \(\pm\)1% difference \begin{table}
\begin{tabular}{l l l l l l l l l l} \hline \hline \multirow{2}{*}{**Area of Hardware Resources**} & \multicolumn{4}{c}{**Range Compression**} & \multicolumn{4}{c}{**Azimuth Compression**} & \multicolumn{1}{c}{**Total**} \\ \cline{2-10}  & **4096 FFT** & \begin{tabular}{c} **Complex** \\ **Multiplier** \\ \end{tabular} & **ROM** & \begin{tabular}{c} **4096** \\ **IFFT** \\ \end{tabular} & **\begin{tabular}{c} **2048** \\ **FFT** \\ \end{tabular} & \begin{tabular}{c} **Complex** \\ **Multiplier** \\ \end{tabular} & **ROM** & \begin{tabular}{c} **2048** \\ **IFFT** \\ \end{tabular} & **\begin{tabular}{c} **Hardware** \\ **Utilisation** \\ \end{tabular} \\ \hline \
\begin{tabular}{l} Combinational ALUTs \\ Total dedicated logic registers \\ Total dims \\ Total block-memory bits \\ M9K block memory \\ DSP block 18-bit elements \\ \end{tabular} & 1602 & 83 & 574 & 1602 & 1088 & 83 & 574 & 1088 & 6694 \\ \hline
\begin{tabular}{l} Total dedicated logic registers \\ Total dims \\ Total block-memory bits \\ M9K block memory \\ DSP block 18-bit elements \\ \end{tabular} & 88 & 8 & 32 & 1085 & 1135 & 88 & 32 & 1135 & 4680 \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Total resources utilisation of the proposed SAR processor. \begin{table}
\begin{tabular}{l l l l l l} \hline \hline \multirow{2}{*}{**Year**} & \multirow{2}{*}{**Schemes**} & \multicolumn{1}{c}{**Data**} & \multicolumn{1}{c}{**Working**} & \multicolumn{1}{c}{**Power**} & \multicolumn{1}{c}{**Processing**} \\  & & **Granularity** & **Frequency** & **Consumption** & **Time** \\ \hline
2020 & PFGA (proposed) & 4096 \(\times\) 2048 & 340 MHz & 0.905 W [14] & 1.38 s \\
2019 & FPGA [20] & 4096 \(\times\) 2048 & 200 MHz & - & 2.1 s \\
2018 & SoC [13] & 16,384 \(\times\) 16,384 & 200 MHz & \textless{}8 W & \textless{}8 s \\
2017 & FPGA + ASIC [17] & 16,384 \(\times\) 16,384 & 100 MHz & 21 W & 12.1 s \\
2016 & FPGA + Microprocess [16] & 6472 \(\times\) 3328 & - & 68 W & 8 s \\
2016 & CPU + GPU [35] & 32,768 \(\times\) 32,768 & - & \textgreater{}330 W & 2.8 s \\
2015 & Multi-DSP [36] & 4096 \(\times\) 4096 & 100 MHz & - & 2.178 s \\
2012 & CPU + ASIC [37] & 1024 \(\times\) 1024 & 100 MHz & 10 W & - \\
2008 & Multi-DSP [38] & 4096 \(\times\) 4096 & 100 MHz & 35 W & 13 s \\
1998 & ASIC [39] & 1020 \(\times\) 200 & 10 MHz & 2 W & - \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Comparison with Previous Work. error as compared to SAR images processed by MATLAB. The investigations also show a reduction in hardware usage via the implementation of an FPGA based FFT/IFFT coprocessor. These promising results have proven that the performance of the proposed processor is satisfactory and the achieved processing time, as well as the power consumption of the processor, outperformed existing implementations. Recommendations for future work include extending the development of FFT/IFFT coprocessors using other FFT algorithms, such as Radix-2 constant-geometry structure, Radix-22 single-path delay feedback and mixed Radix FFT in order to reduce the processing time in the RDA. In this work, a proposed FPGA-based SAR processor was developed based exclusively on RDA.