# Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol
## 4 Results and Comparisons  
### Results  
The proposed ECDH architecture is implemented in Verilog language using the Vivado IDE (Integrated Design Environment) tool. For performance evaluations, the implementation results are presented on different FPGA devices, i.e., Virtex-7 (xc7 vx690 ffg1930-2), Spartan-7 (xc7s100 ffgga676-2), Artix-7 (xc7a200 tsbv484-2) and Kintex-7 (xc7k480 fffv1156-2). The respective details for the targeted FPGA devices are given in [42]. The achieved results are given in Table 2.  
Column one of Table 2 provides the targeted device. The utilized area (in terms of slices, look-up tables (LUTs) and flip-flops (FFs)) is shown in columns two, three and four respectively. The area information is obtained directly from the Vivado tool. Similar to the reported area values, the operational frequency (Freq in MHz) is also acquired from the tool and is presented in column five of Table 2. Columns six and seven show the CCs and latency (in \(\upmu\)s) information for one PM computation. Similarly, columns eight and nine present the clock cycles and latency (in \(\upmu\)s) information for one shared key generation. Theclock cycles for one shared key generation are calculated from Equation (1). Likewise, the clock cycles for one PM computation are calculated from Equation (2).  
The latency is the time required to execute one crypto operation (either public or shared key generation in this work). The latency values are calculated using Equation (3). To provide a realistic tradeoff over different FPGA devices, we have defined a figure-of-merit (FoM) in terms of the ratio of throughput over FPGA slices. The FoM values are reported for the shared key generation, as shown in the last column of Table 2. The throughput is the ratio of one over latency and is calculated using Equation (4). Finally, the FoM values are calculated using Equation (5).  
\[\text{Latency (in $\upmu$s)}\ =\ \frac{\text{Clock Cycles}}{\text{Frequency (in MHz)}} \tag{3}\]  
\[\text{Throughput}\ =\ \frac{1}{\text{Latency (in $\upmu$s)}}\ =\ \frac{10^{6}}{\text{Latency (in s)}} \tag{4}\]  
\[\text{FoM}\ =\ \frac{\text{Throughput}}{\text{FPGA slices}} \tag{5}\]  
Table 2 shows the trend for hardware resource utilization on various 28 nm implementation technologies. Therefore, the minimum hardware resources (5102 slices, 12,339 LUTs and 2459 FFs) are obtained for the Virtex-7 device when compared to Spartan-7, Artix-7 and Kintex-7 devices. The utilized FPGA slices for Spartan-7, Artix-7 and Kintex-7 devices are 5634, 5957 and 6102. Similar to hardware resource utilization, the highest clock frequency of 318 MHz is achieved on Virtex-7 FPGA. On Spartan-7 (312 MHz), Artix-7(316 MHz) and Kintex-7(304 MHz) devices, we also acquired the closest clock frequency to our Virtex-7 implementations. When trading from Virtex-7 to Kintex-7 implementations, the minor increase in the FPGA slices and clock frequency indicates the efficiency of our architecture. The times to generate one public key on Virtex-7, Spartan-7, Artix-7 and Kintex-7 are 15.54 \(\upmu\)s, 15.83 \(\upmu\)s, 15.63 \(\upmu\)s and 16.25 \(\upmu\)s. On similar FPGA devices, the times to generate one shared key are 31.08 \(\upmu\)s, 31.68 \(\upmu\)s, 31.28 \(\upmu\)s and 32.51 \(\upmu\)s.  
The defined FoM determines the performance of our crypto architecture on different 28 nm implementation technologies. The higher the FoM value, the higher will be the performance of the crypto architecture. Consequently, the highest 6.30 FoM value is calculated for Virtex-7 FPGA. For Spartan-7, Artix-7 and Kintex-7 devices, the calculated values for FoM are 5.60, 5.36 and 5.04.