# A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis
## 3 TSV Reliability
### Noise Coupling
As such, it is observed that digital noise leaks from RF circuits to the substrate, which will decrease the RF circuit's performance. The important choice is to enhance the noise among digital and RF circuits. From all this observation, researchers made use of electrode materials for the surface layer of the TSV and a copper material for the outer layer and then verified the results [61]. [PERSON] et al. [62; 63] provided an accurate model for the dynamic crosstalk analysis of coupled multiple on-chip interconnects driven by CMOS inverters. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled _RLC_ interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. Over the random number of test cases, crosstalk-induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results. The finite-difference time-domain (FDTD, Figure 11d)) technique is widely used to solve electromagnetic wave problems. It is a fast, accurate, and powerful technique involving the discretization of electromagnetic fields in the time domain [64]. Several researchers have proposed various improved FDTD techniques to overcome CFL stability criteria based on different algorithms, such as alternating direction implicit FDTD, stepwise FDTD, and Crank-Nicolson FDTD; [PERSON] et al. argue that large-scale integrated (VLSI) interconnects are driven and terminated by nonlinear CMOS drivers and capacitive loads, respectively. Therefore, the existing unconditionally stable FDTD (US-FDTD) technique is not suitable for analyzing the performance of VLSI interconnects. They developed a new model in which the interconnects are driven by nonlinear CMOS drivers that are modeled by an improved alpha power-law model that includes drain conductance parameters [64; 65]. To reduce the degree of cross-coupling between TSVs, a shield can be inserted between them. This shield can be made of any metal piece that hinders the propagation of electromagnetic waves. However, optimizing the placement of the shield requires more work. Previous studies on TSV coupling have mainly presented circuit models of the coupling phenomenon. Figure 11: (**a**) An illustration of TSV-related coupling; (**b**) structure of the TSV-TSV coupling noise; (**c**) an illustration of the 3D victim net; (**d**) schematic of coupled interconnects driven by CMOS drivers and the representation of space discretization of an interconnect line for the US-FDTD technique. (adapted from [1; 64; 66]). For instance, in a study published in [67], the authors proposed a TSV noise coupling model based on the three-dimensional transmission line matrix method (3D-TLM). This model allows for the estimation of the noise coupling transfer functions from TSV to TSV and from TSV to active circuits in a complex 3D structure. In another study published in [68], the authors examined the parasitic substrate coupling effects in 3D-ICs caused by TSVs. They performed electrical characterization by studying some test structures to extract the electrical model of substrate coupling with RF signals. In [69], the authors presented an equivalent circuit model for differential TSV pairs. They calculated and analyzed the key differential characteristics based on the aggregate circuit model of multiple TSVs. However, circuit models are very accurate but take a long time to solve because they require solving a system of differential equations. Therefore, to speed up the optimization process during chip-level shield placement, [PERSON] and [PERSON] et al. [1; 3; 66; 70] proposed geometric models for TSV cross-coupling. These models can be quickly solved, unlike circuit models. In [1], the authors proposed an intelligent method based on genetic algorithms (GAs) and a recent particle swarm optimization (PSO) heuristic model to identify the parameters of TSV-TSV and TSV-contact noise coupling in 3D IC design.