# PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA
## 3 Proposed P4-Programmable Parser
### Software Overview
#### 3.1.2 P4 Compiled JSON File
In Proceedings of the SIGCOMM 2016--Proceedings of the 2016 ACM Conference on Special Interest Group on Data Communication, Salvador, Brazil, 22-26 August 2016. * _[PERSON] et al. (2010)_ [PERSON]; [PERSON]; [PERSON] [PERSON]; [PERSON] [PERSON] Leaping Multiple Headers in a Single Bound: Wire-Speed Parsing Using the Kangaroo System. In Proceedings of the 2010 Proceedings IEEE INFOCOM, San Diego, CA, USA, 14-19 March 2010; pp. 1-9. * _[PERSON] (2011)_ [PERSON]; [PERSON] 400 Gb/s Programmable Packet Parsing on a Single FPGA. In Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems, Brooklyn, NY, USA, 3-4 October 2011; pp. 12-23. * _[PERSON] et al. (2013)_ [PERSON]; [PERSON] [PERSON]; [PERSON]; [PERSON] Design principles for packet parsers. In Proceedings of the Architectures for Networking and Communications Systems, San Jose, CA, USA, 21-22 October 2013; pp. 13-24. * _[PERSON] et al. (2018)_ [PERSON]; [PERSON] [PERSON]; [PERSON] [PERSON] An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks. In Proceedings of the 2018 IEEE 29 th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Milano, Italy, 10-12 July 2018; pp. 1-4. * _[PERSON] et al. (2018)_ [PERSON]; [PERSON]; [PERSON] [PERSON] Low-latency Packet Parsing in Software Defined Networks. In Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, Estonia, 30-31 October 2018; pp. 1-6. * _[PERSON] et al. (2020)_ [PERSON]; [PERSON] [PERSON]; [PERSON] [PERSON]; [PERSON] [PERSON]; [PERSON] [PERSON]; [PERSON] [PERSON] Flexible Software-Defined Packet Processing Using Low-Area Hardware. _IEEE Access_**2020**, \(8\), 98929-98945. [CrossRef]
* _[PERSON] et al. (2020)_ [PERSON]; [PERSON]; [PERSON] [PERSON] A custom processor for protocol-independent packet parsing. _Microprocess. Microsyst._**2020**, _72_, 102910. [CrossRef]
* _[PERSON] et al. (2019)_ [PERSON]; [PERSON]; [PERSON]; [PERSON]; [PERSON] A Fast Approach for Generating Efficient Parsers on FPGAs. _Symmetry_**2019**, _11_, 1265. [CrossRef]
* _[PERSON] et al. (2022)_ [PERSON]; [PERSON]; [PERSON] [PERSON] A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. In Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 27 May-1 June 2022; pp. 672-676. * _[PERSON] et al. (2023)_ [PERSON]; [PERSON] [PERSON]; [PERSON] [PERSON] An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs. In Proceedings of the Proceedings--IEEE International Symposium on Circuits and Systems, Monterey, CA, USA, 21-25 May 2023. * _[PERSON] et al. (2016)_ [PERSON]; [PERSON]; [PERSON] [PERSON] P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. In Proceedings of the 2016 IEEE 24 th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington, DC, USA, 1-3 May 2016; pp. 148-155. * _[PERSON] and [PERSON] (2023)_ [PERSON]; [PERSON] The Design of a Dynamic Configurable Packet Parser Based on FPGA. _Micromachines_**2023**, _14_, 1560. [CrossRef]
* _[PERSON] et al. (2021)_ [PERSON]; [PERSON]; [PERSON]; [PERSON]; [PERSON] HyperParser: A High-Performance Parser Architecture for Next Generation Programmable Switch and SmartNIC. In Proceedings of the ACM International Conference Proceeding Series, Virtual Event, 20-25 June 2021. * _[PERSON] and [PERSON] (2022)_ [PERSON]; [PERSON] The Design of a Configurable and Low-Latency Packet Parsing System for Communication Networks. _SSRN Electron. J._**2022**. [CrossRef]
* _[PERSON] et al. (2018)_ [PERSON]; [PERSON]; [PERSON] P4 to SDNet: Automatic Generation of an Efficient Protocol-Independent Packet Parser on Reconfigurable Hardware. In Proceedings of the 2018 8 th International Conference on Computer and Knowledge Engineering (ICCKE), Mashhad, Iran, 25-26 October 2018; pp. 159-164. * _[PERSON] et al.