# Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate
## 3 Result and Discussion
### SPICE Compatible Compact Modeling
Overall, the negative \(\Delta V_{T}\) component increased, which is attributed to the larger hydrogen migration effect caused by greater charge movement throughout the channel. As shown above, the physical and electrical stresses can cause various \(\Delta V_{T}\) trends, which could affect the operation of the complex circuit. Therefore, based on the DC characteristics of a single device and its appropriate modeling, the \(V_{T}\) instability of the load and driver transistors was predicted for an accurate transient simulation. In detail, the beta (\(\beta\)) and tau (\(\tau\)) were extracted using the measured \(\Delta V_{T}\) and  
Figure 4: Threshold voltage shift (\(\Delta V_{T}\)) of driver transistors in flat and bending conditions. (**a**) Transfer curve change in flat condition when V\({}_{\text{DS}}\) = 0 V and V\({}_{\text{GS}}\) = 4 V, and (**b**) when V\({}_{\text{DS}}\) = 0 V and V\({}_{\text{GS}}\) = 7 V. (**c**) Summarized \(\Delta V_{T}\) of flat driver transistors depending on the stress and recovery time. (**d**) Transfer curve change in bending radius of 10 mm when V\({}_{\text{DS}}\) = 0 V and V\({}_{\text{GS}}\) = 4 V, and (**e**) when V\({}_{\text{DS}}\) = 0 V and V\({}_{\text{GS}}\) = 7 V. (**f**) Summarized \(\Delta V_{T}\) of bending driver transistors depending on the stress and recovery time. detailed SEF model is presented in the below Equation (2), which reflects both negative and positive \(\Delta V_{\text{T}}\) cases. \[ \begin{split} V_{T}=\Delta V_{T0,positive}(V_{OV,positive}) \left(1-e^{-(\frac{t}{t_{positive}V_{OV,positive}})^{\beta}}\right)\\ +\Delta V_{T0,negative}(V_{OV,negative})\left(1-e^{(\frac{t}{t_ {negative}V_{OV,negative}})^{\beta}}\right)\end{split}  \tag{2}\]  
The extracted \(\Delta V_{T0}\) and \(\tau\) for various conditions are shown in Figure 5. The \(\tau\), \(\Delta V_{T0}\), and \(\beta\) functions for every physical and electrical stress condition are summarized in Table 1. Reflecting the repeated stress/recovery in AC bias, a real-time \(\Delta V_{\text{T}}\) was successfully applied in the inverter simulation. In detail, each function presented in Table 1 was entered into the \(V_{T}\) parameters in the analytical I-V model of Verilog-A [30]. After configuring an IGZO NMOS-only inverter in HSPICE, the SEF model and the extracted parameters were used for both device simulation and transient AC simulation. The measured values and simulation results of the load/driver transistors in a flat condition are shown in Figure 6a,b. The measured values and simulation results of voltage transfer curves (VTC) of a flat inverter are shown in Figure 6c. Similarly, the measured values and simulation results of the transistor and inverter in the bending condition are shown in Figure 6d-f. As shown in these figures, it was demonstrated that the simulation results fit very well with the measured values. Figure 5: (**a**) Extracted \(\Delta V_{T0}\) and (**b**) \(\tau\) for load transistors in different electrical and physical stress conditions. (**c**) Extracted \(\Delta V_{T0}\) and (**d**) \(\tau\) for driver transistors in different electrical and physical stress conditions.