## 3 Hardware Design
### Mixed-Signal Processing Module  
The middle-layer of the Marmote SDR platform, called _Teton_, is a mixed-signal processing module that is the main building block of any Marmote SDR application. In the current setup, _Teton_ controls the top-layer radio front-end and provides computational resources for a complete vertical network stack, including PHY layer baseband signal processing. The basis of the mixed-signal processing module is a flash FPGA-based SoC and two external analog front-ends (AFE) that make the module capable of simultaneously processing two sets of analog baseband I/Q signal pairs. Each set of the analog baseband I/Q Rx and Tx pairs is connected to the 10-bit ADCs and DACs of a Maxim MAX19706 type low-power AFE, respectively. While interfacing with two sets of baseband signals renders the _Teton_ board suitable for MIMO application development with an appropriate radio front-end module, the current 2.4 GHz _Joshua_ RF module contains only a single transceiver and does not support MIMO features. The AFE sample clock is driven by the SoC, and it is also used to synchronize the ADC and DAC sample transfers through a 10-bit parallel double data rate (DDR) digital bus at sampling rates up to 22 MHz. Parallel double data rate (DDR) interface was preferred to high-speed serial interfaces, as it matches the SmartFusion FPGA fabric characteristics and allows the FPGA to transfer the I/Q samples in a single clock cycle and, therefore, to operate the entire fabric in a single, low-frequency clock domain. The Microsemi A2F500 SmartFusion SoC comprises flash FPGA fabric and a 32-bit microcontroller subsystem interconnected with an ARM Advanced Microcontroller Bus Architecture (AMBA) Advanced Peripheral Bus (APB). The SmartFusion chip was primarily selected for its FPGA fabric,built with 130 nm, flash-based CMOS process with sufficient logic elements to implement the PHY layer along with portions of the MAC layer. Resource utilization breakdown for a simple FSK modem-based PHY layer is presented in Section 4.1. The advantageous low-power properties of flash-based FPGA technology made the SmartFusion a favorable choice over current SRAM technology FPGA solutions. While SRAM FPGAs store the configuration for programmable interconnects and look-up-tables in volatile SRAM cells, which need to be configured on every powerup, flash FPGAs use nonvolatile flash switches, which has several advantages. First, no external flash memory is needed to store the configuration file, effectively reducing board complexity and saving board space. Second, reconfiguration of the FPGA is not required when applying supply voltage to the fabric, which enables efficient duty cycling operation, as (re)configuration currents are virtually eliminated. This saves not only energy, but also reduces wake-up time, rendering the device more responsive in duty cycling mode. Figure 2 gives a quantitative comparison of the startup process of SRAM and nonvolatile flash FPGA devices and shows that the 108 ms wake-up time (measured from requesting wake-up until the clock generator phase-locked loop locks-in) associated with an SRAM FPGA can be reduced to 476 ns using flash fabric, due to the absence of the reconfiguration phase. Flash FPGAs are also claimed to have lower static current draw than SRAM FPGAs [22], making them a preferable choice for low-power WSN applications. Analysis of our power consumption related experiments is discussed in Section 4.2. The SmartFusion SoC also contains a microcontroller subsystem (MSS) comprising an ARM Cortex-M3-based 32-bit microprocessor with a rich set of communication peripherals and a high-speed, low-latency AMBA APB to interface with the FPGA fabric. This tight connection between the processor and the FPGA fabric, thus, provides flexibility to move the border between hardware and software in a network stack implementation and allows one to accelerate application software components with FPGA cores, which was practically infeasible on former platforms [14].