## 2 Circuit Implementation  
The overall noise of an amplifier is majorly caused by the input differential pair, which means that the input transistors of the differential pair are the noise source of the amplifier. As shown in previous works, the BJT has a better low-noise characteristic than the MOS transistor when the same amount of bias current is supplied [15]. Vertical BJTs are supported by the process design kit (PDK) in a standard CMOS process. The supported vertical PNP of the standard CMOS process, however, has a limitation--for implementing to the input stage of the amplifier, the collector is tied with the substrate, which enables its use only in such cases as bandgap reference circuits [16]. Due to this limitation of the vertical BJT in circuit design, a lateral BJT is designed and implemented in this work. The input differential pair is implemented with lateral PNP in this work. The implemented lateral PNP is shown in Figure 1. The top view and cross-sectional view of the implemented lateral PNP are shown in Figures 1a,b. The lateral PNP is designed in a standard 0.18-\(\upmu\)m CMOS process. The custom lateral PNP is designed with minimum length, satisfying the design rule of the standard 0.18-\(\upmu\)m CMOS process. The lateral PNP is designed as a gated PNP, which is formed by gate polysilicon. The lateral PNP in this work is based on previously reported works [18; 19; 20; 21]. The gate of the design lateral PNP is biased with a supply voltage of 3.3 V. The measured current gain (\(\beta\)) dependence on the voltage across the base and emitter (\(V_{BE}\)) of the implemented lateral PNP is shown in Figure 1c. The \(\beta\) dependence on \(V_{BE}\) shows the trend of \(\beta\) by the voltage sweep of \(V_{BE}\) across 0.4 to 1.0 V. The measured maximum \(\beta\) is 9.3. The low \(\beta\) is caused by the large base current, which causes a low input impedance of the amplifier. The proposed low-noise chopper operational amplifier using a lateral PNP input stage with BJT current mirror base current cancellation is shown in Figure 2. The input stage of the amplifier is implemented with a custom-designed lateral PNP. The base current caused by the lateral PNP differential input leads to low input impedance. The BJT current mirror base current cancellation scheme is implemented to reduce the base current caused by the lateral PNP input stage. The base current cancellation control switches (SW\({}_{1}\) and SW\({}_{2}\)) are integrated for controlling the base current cancellation. The proposed chopper amplifier is adopted with a folded cascode and a class-AB output stage. The integrated compensation capacitors C\({}_{\text{C1}}\) and C\({}_{\text{C2}}\) are 41.8 pF. The chopper clock signals are nonoverlapping clocks, and the chopper frequency (\(f_{c}\)) is 250 kHz. The operation of the proposed BJT current mirror base current cancellation is shown in Figure 3. The BJT current mirror base current cancellation is implemented with a simple scheme using NPN transistors with deep n-well in a generic CMOS process. The base current flow before the base current cancellation operation is shown in Figure 3a. The output base currents \(I_{B1}\) and \(I_{B2}\) of the differential input pair Q\({}_{1}\) and Q\({}_{2}\) cause input bias currents \(I_{N1}\) and \(I_{N2}\). The operation of the proposed BJT current mirror base current cancellation is shown in Figure 3b. The base current cancellation operates when the control switches SW\({}_{1}\) and SW\({}_{2}\) are turned on. The base currents \(I_{B1}\) and \(I_{B2}\) of the differential input pair Q\({}_{1}\) and Q\({}_{2}\) can be compensated by the base current cancellation. The collector currents \(I_{C1}\) and generated by Q1 and Q2 flow through PNP transistors Q3 and Q4. The collector currents \(I_{C1}\) and \(I_{C2}\) are the same as \(I_{C3}\) and \(I_{C4}\) of Q3 and Q4, which can be expressed as (1) and (2).