# Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models
## 6 Conclusions  
Next-generation communication networks require intelligent elements to adapt to their environment by evaluating their quality of service (QoS) and making decisions. One of these QoS factors is the signal quality of the channel through which the data are transmitted, known as the Network Channel Quality Indicator (CQI). In this case, the signal quality can be affected by multiple factors, such as the presence of cosmic rays, lightning, changes in temperature, and/or interferences. We can observe these effects, for instance, within vehicle applications where many devices and several communication networks coexist in the same environment. The signal quality is an important metric that helps to determine when the phenomena mentioned above affect services and generate interferences, causing erroneous behavior, failures, and more significant economic losses and even deaths. Real-time operating systems require continuous operation with great precision on the information exchanged.  
Therefore, this article presented a trade-off analysis of four FPGA hardware architectures that implement the machine learning models of decision trees, MLP, logistic regression, and SVM to determine a high or low CQI. We carry out an analysis in software to obtain the machine learning models implemented. The FPGA hardware architectures trade-off analysis is focused on comparing performance metrics, resources used, and the learning model's accuracy to assess the quality of the channel, which is applied in SDR in this work. So, future implementation in embedded systems will allow its application in larger integral systems within the entire range of communication networks, such as SDVN, SDN, 5G, and VANETs based on SDR. We have used mainly adder, multiplier, and comparator modules for the hardware implementation. We obtained quantitative values of the FPGA hardware implementations such as latency, LUTs, DSP, BRAM, throughput, and efficiency, together with the balanced accuracy metric, help us to select the best model. In this way, the results show that we obtained the best trade-off between balanced precision (ML model result) and performance (hardware result) with the decision tree, which consists of a depth of 5, a precision of 95.01%, and an efficiency of 9.83 Mbps/LUT.  
Finally, our work was not able to carry out a fair comparison against other works since is the first to determine a high or low CQI in a FPGA hardware implementation using ML models, but it will be a reference for future similar works. In addition, it can be replicated in a hardware device such as an ASIC (Application-Specific Integrated Circuit) or FPGA (Field Programmable Gate Array).  
Conceptualization, A.T.-A., L.A.M.-R. and I.A.-B.; data curation, F.L.-H., M.L.-B. and J.C.L.-P.; formal analysis, A.T.-A., L.A.M.-R., I.A.-B. and F.L.-H.; funding acquisition, L.A.M.-R. and I.A.-B.; investigation, A.T.-A., F.L.-H., M.L.-B. and J.C.L.-P.; methodology, A.T.-A., L.A.M.-R., I.A.-B., M.L.-B. and J.C.L.-P.; software, A.T.-A.; supervision, L.A.M.-R.; validation, L.A.M.-R. and I.A.-B.; visualization, F.L.-H., M.L.-B. and J.C.L.-P.; writing--original draft, A.T.-A., L.A.M.-R. and I.A.-B.; writing--review and editing, F.L.-H., M.L.-B. and J.C.L.-P. All authors have read and agreed to the published version of the manuscript.  
This research was funded by the Mexican National Council for Science and Technology (CONACYT) through Research Project 882, and 613.  
Not applicable.  
The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.