## 6 Discussion  
This paper introduces a low-complexity MSD algorithm, which effectively reduces the number of local reference signals by considering the importance of bits at different positions during correlation operations and the symmetrical structure of the signals. This optimization leads to a significant reduction in the computational complexity of correlation operations, making the algorithm more suitable for hardware implementation. Specifically, in the hardware design, the proposed algorithm optimizes the number of channels and coefficients in FIR filters, further reducing hardware resource consumption.  
To validate the effectiveness of the proposed algorithm, simulation experiments were conducted based on the conditions outlined in Table 1. The simulation results demonstrate that the proposed algorithm achieves an 87.5% reduction in computational complexity while maintaining nearly the same demodulation performance as traditional MSD algorithms. This indicates that, despite the significant simplification in computations, the algorithm retains a demodulation performance comparable to traditional MSD algorithms. This advantage is particularly important in real-world applications, especially in telemetry systems that require large-scale real-time processing, where reduced computational complexity and hardware resource requirements can significantly improve system responsiveness and reliability.  
In addition to the traditional MSD algorithms, compared to the decision-feedback MSD algorithm, the proposed algorithm achieves higher demodulation gain while maintaining lower computational complexity. Specifically, although decision-feedback algorithms can offer some performance improvement, they are often affected by error propagation in low SNR environments, which degrades demodulation performance. In contrast, the proposed algorithm reduces the number of branches in the correlation operation and optimizes the local reference signals, preventing such issues. Therefore, the proposed algorithm maintains good demodulation performance even under poor channel conditions.  
The aforementioned algorithm optimizations not only improve computational efficiency in theory but also translate well into hardware implementations. The FPGA implementation of the proposed algorithm validates its hardware-friendly nature. Compared to traditional algorithms, it reduces hardware resource consumption by approximately 90%. This significant hardware optimization indicates that the algorithm has strong potential  
\begin{table}
\begin{tabular}{l l} \hline \hline  & \multicolumn{1}{c}{**WNS/ns**} \\ \hline before optimization & 3.313 \\ after optimization & 3.313 \\ \hline \hline \end{tabular}
\end{table}
Table 4: Comparison of timing parameter before and after optimization of FIR filter.  
for real-world applications. Particularly in programmable hardware platforms such as FPGAs, the parallel design of the algorithm not only improves processing efficiency but also reduces system power consumption and latency. While the hardware implementation reduces resource consumption, the performance loss remains within 1 dB, which is acceptable for practical applications.  
However, there is still room for further optimization. For instance, in more complex channel environments, reducing the impact of error propagation and improving the robustness of the algorithm will be important areas for future research. Additionally, adjusting the algorithm's parameters according to specific hardware platforms to achieve optimal performance could be a key factor in enhancing overall system efficiency.  
In summary, the proposed low-complexity MSD algorithm significantly reduces computational complexity and hardware resource consumption while maintaining excellent demodulation performance. This makes it highly promising for practical applications, particularly in high-performance telemetry systems, where it offers great practical value.