# Transimpedance Amplifier for Noise Measurements in Low-Resistance IR Photodetectors
## 3 Materials and Methods
To address this issue, we resort to the compensation network made of \(R_{C1}\), \(R_{C2}\), \(C_{C1}\), and \(C_{C2}\) in Figure 2. The OPA227 introduces a pole at about 3 Hz as part of its frequency response. The compensation network introduces two poles and two zeroes, which reduce the open-loop gain to zero dB before the high-frequency poles of the OPA227 are able to introduce a further phase shift that would cause instability. Because of the 90\({}^{\circ}\) phase shift introduced by the dominant pole of the OPA227, the compensation network is designed in such a way that its phase contribution is less than 45\({}^{\circ}\) at any frequency. This can be achieved if the frequency of the zero is no larger than 10 times that of the pole. With this constraint, the gain amplitude reduction that is obtained with a single zero-pole compensation network is insufficient to reach the desired goal. For this reason, in our design, we introduce two RC networks between the drain of the JFETs. With the values for \(R_{C1}C_{C1}\) and \(R_{C2}C_{C2}\) listed in Table 1, the pole and zero frequencies are:  
\[ \begin{array}{l}f_{p1}\approx\frac{1}{2\pi(R_{C1}+2R_{D})C_{CA}}\approx 75\; \mathrm{Hz},\qquad f_{z1}=\frac{1}{2\pi R_{C4}C_{CA}}\approx 720\;\mathrm{Hz},\\ f_{p2}\approx\frac{1}{2\pi(R_{CB}+R_{CA}||2R_{D})C_{CB}}\approx 14\;\mathrm{kHz}, \qquad f_{z2}=\frac{1}{2\pi R_{CB}C_{CB}}\approx 72\;\mathrm{kHz}.\end{array}  \tag{9}\]  
With these values, the SPICE simulations show that the open-loop gain reaches 0 dB with a phase margin of about 45\({}^{\circ}\). This ensures that the shunt-shunt configuration possesses the stability required to produce a transimpedance amplifier for resistive DUTs of any value. The super operational amplifier is used in a shunt-shunt configuration, as shown in Figure 1, in order to obtain a transimpedance stage with gain \(A_{R}\) set by the feedback resistance \(R_{R}\), that is:  
\[A_{R}=\frac{v_{O1}}{i_{DUT}}=-R_{R} \tag{10}\]  
Assuming a negligible input offset for the SOA, Equation (10) holds for both the DC component and the fluctuations across the DUT. This means that the DC voltage at the output \(V_{O1}\) can be used to estimate the DC current through the DUT. It is for this reason that this voltage is carried by a buffer (\(OA_{3}\)) to one of the outputs of the system (\(V_{ODC}\)). The amplitude of the noise fluctuations at node \(V_{O1}\) is typically too low to be effectively detected using a spectrum analyzer, and therefore, a second stage is used to obtain high voltage gain (\(O_{A2}\)) after rejecting the DC component using an AC coupling filter (\(C_{A2}R_{A2}\)). Since this amplifier is intended for noise measurements on low-impedance DUTs, typical bias voltages \(V_{B}\) across the DUT are often well below 1 V, and this means that the input offset of the SOA must be maintained low both for the voltage across the DUT to essentially coincide with the external bias voltage \(V_{B}\), and for the output \(V_{ODC}\) to provide the correct value for the DC current through the DUT. With a discrete JFET input stage for the SOA, the offset can be relevant. This offset is essentially due to the mismatch between the two JFETs in the IF3602 device. Offsets as large as \(\pm 50\) mV can easily be experienced in the case of the IF3602 [14], and these values are quite relevant for bias voltages on the order of a few hundred mV. Therefore, the schematic diagram in Figure 2 includes a system for adding a DC voltage at the non-inverting input of the SOA, which is obtained by exploiting a trimmer (\(R_{T}\)) together with a voltage divider (\(R_{O}\), \(R_{A1}\)) and a capacitor \(C_{A1}\) in order to filter out, as much as possible, the thermal noise generated by the offset correction circuit itself. With the approach shown in Figure 2, equivalent offsets below 5 mV were routinely obtained while testing the realized prototype.