## 2 Working Principle of the TIBuck DC/DC Converter
### Working Principle  
Figure 3 shows a representation of the TIBuck DC/DC converter and its control. This DC/DC converter is a modification of the traditional Buck DC/DC converter, in which the diode S\({}_{\text{ti}}\) is connected to an auxiliary input voltage, V\({}_{2}\), instead of the negative terminal of the main input voltage, V\({}_{1}\). For proper operation, V\({}_{1}\) and V\({}_{2}\) must comply with the following inequation  
\[V_{1}>V_{2}, \tag{4}\]  
where the traditional Buck DC/DC converter is a particular case when V\({}_{2}\) = 0 V. Due to the addition of V\({}_{2}\), the switching node voltage v\({}_{\text{sw}}\)(t) varies between V\({}_{1}\) and V\({}_{2}\), as shown in Figure 4. The PWM signal v\({}_{\text{gs-ti}}\)(t) that controls the main switch Q\({}_{\text{ti}}\) is obtained by comparing a sawtooth waveform with the reference signal. This reference is traditionally considered constant in DC/DC converters, whereas it varies in VLC drivers based on DC/DC converters. For the sake of simplicity, in this case the reference is depicted as a sinusoidal waveform, but it could be more complex. The comparison between the sawtooth signal and the reference modulates the duty ratio d\({}_{\text{ti}}\)(t) and consequently, v\({}_{\text{gs-ti}}\)(t) (see Figure 4). In high-switching-frequency converters, this modulation could be implemented in a digital platform, called Digital PWM (DPWM). Analog implementations of high-frequency PWM are also possible, but integration with the communication task makes them unfeasible in practice for VLC drivers. The DPWM consists of a digital counter and a high-frequency clock, as depicted in Figure 3. For the sake of representation, Figure 5 shows an enlargement of two switching periods. From a high-frequency clock CLK, whose frequency is f\({}_{\text{clk}}\), the  
Figure 3: The TIBuck DC/DC converter topology and its control. DPWM counts each clock cycle, Tclk, until a certain Csw value. The frequency of the sawtooth signal is then  
\[f_{sw}=\frac{f_{clk}}{C_{s\text{i}\text{i}\text{i}\text{i}}}, \tag{5}\]  
which will be the switching frequency of the converter. In each clock period (i.e., Tclk), the reference signal and the sawtooth are compared. Due to the discretization of the process, there are only Csw possible values for the duty cycle dti(t), which impacts the resolution of the DC/DC converter for tracking the output voltage. The output voltage of the DPWM, vgs-ti(t), controls the MOSFET Qti of the TIBuck DC/DC converter through its driver. The voltages V1 and V2, together with Qti and the diode 5 ti, make up a switching node whose output voltage is vsw(t), also shown in Figure 4. This square waveform is applied to the input of the low-pass output filter, producing the output voltage vo(t). The output voltage would follow the reference signal if, and only if, certain conditions regarding the frequencies involved and the filter design are met. These conditions have been deduced for the Buck DC/DC converter [18] and are applicable to the TIBuck DC/DC converter. With fsig the centre frequency of the reference communication signal spectrum, and fsig-max its maximum frequency, fc the cutoff frequency of the filter and fsw the switching frequency of the PWM signal, the frequency conditions can be written as  
\[f_{sig-max}>\frac{f_{sw}}{2}, \tag{6}\]  
\[f_{sig-max}<f_{c}<f_{sw}. \tag{7}\]  
Equation (6) is imposed by the Nyquist-Shannon sampling theorem, since the comparison between the sawtooth and the reference works as a sampler. Equation (7) comes from  
Figure 4: Most significant control waveforms of the TIBuck DC/DC converter. Figure 5: DPWM modulator and digital implementation of the sawtooth signal for two switching periods of Figure 4.0  
the filtering action, allowing the filter to separate the communication signal frequencies from the switching harmonics. Equation (7) is effectively the most restrictive, because if Equation (7) is met, Equation (6) is also met.