# Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA
## 2 ECC Background over \(GF(2^{m})\)
\begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline
**Ref. \#** & **Year** & **Device** & **Slices** & **LUTs** & **Clock** & **Freq** & **Latency** & **Thrpt** & **Thrpt/Area** \\  & & & & & & **Cycles** & **MHz** & \(\upmu\)s & **kbps** & **Thrpt/Slices** & **Thrpt/LUTs** \\ \hline
[15] & 2015 & Virtex-7 & 12,965 & 38,547 & – & 250 & 57.61 & 17.35 & 1.33 & 0.45 \\
[16] & 2020 & Virtex-7 & 4560 & 12,691 & 12,329 & 340 & 36.26 & 27.57 & 6.04 & 2.17 \\
[17] & 2018 & Virtex-5 & 20,291 & – & – & – & 18.51 & 54.02 & 2.66 & – \\
[18] & 2021 & Virtex-7 & – & 80,970 & – & 274 & 12.55 & 79.68 & – & 0.98 \\
[19] & 2021 & Virtex-6 & – & 116,241 & 7628 & 135 & 56.50 & 17.69 & – & 0.15 \\
[20] & 2013 & Virtex-5 & 11,640 & 324,332 & 44,047 & 127 & 348 & 2.87 & 0.246 & 0.008 \\
[21] & 2017 & Virtex-7 & 50,336 & – & 3783 & 111 & 34.05 & 29.36 & 0.58 & – \\ \hline Design of Figure 1 & Virtex-5 & 7289 & 17116 & 9165 & 296 & 30.96 & 32.29 & 4.42 & 1.88 \\ Design of Figure 1 & Virtex-6 & 6107 & 15216 & 9165 & 319 & 28.73 & 34.80 & 5.69 & 2.28 \\ Design of Figure 1 & Virtex-7 & 5683 & 14356 & 9165 & 361 & 25.38 & 39.40 & 6.93 & 2.74 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Comparison to most relevant state-of-the-art PM architectures over \(GF(2^{571})\). #### 4.2.1 Comparison to Area, Clock Cycles, Latency, Frequency and Throughput

In this section, on different FPGA devices, we compared our implementation details in the area (slices and LUTs), clock cycles, computation time (i.e., latency), circuit frequency, and throughput with state-of-the-art implemented designs. Comparison to Virtex-5 implementation: The comparison to [20] reveals that our architecture is 1.59 (ratio of 11,640 over 7289) and 18.94 (ratio of 324,332 over 17,116) times more efficient in FPGA slices and LUTs. The reason is an additional polynomial inversion circuit using a digit serial variant of the Kim and Hong method in the reference design. In our implementation, we employed the Itoh-Tsujii inversion algorithm, which is implemented using the hardware resources of our square and multiplier circuits. Moreover, our PM implementation is 4.80 (ratio of 44,047 over 9165) and 2.33 (ratio of 296 over 127) times more efficient in clock cycles and circuit frequency, respectively. The cause is a digit serial multiplier in the reference design while we utilized a bit parallel Karatsuba multiplier for polynomial multiplications. Similarly, if we compare the latency and throughput values, our PM architecture is 11.24 (ratio of 348 over 30.96) and 11.25 (ratio of 32.29 over 2.87) times more efficient. On an identical Virtex-5 device, our slices comparison to [17] shows that the proposed accelerator architecture is 2.78 (ratio of 20,291 over 7289) times efficient. As shown in columns five to seven of Table 3, the comparison to LUTs, clock cycles and circuit frequency is not possible to make, as the corresponding information is not given in the reference design. In latency and throughput, the architecture of [17] is 1.67 (ratio of 30.96 over 18.51) and 1.67 (ratio of 54.02 over 32.29) times more efficient as compared to our proposed accelerator architecture. In summary, we are winning the hardware resources, while the design of [17] is more efficient in latency and throughput. There is always a tradeoff between area and throughput. Comparison to Virtex-6 implementation: The comparison to [19] shows that our architecture is 7.63 (ratio of 116,241 over 15,216) times more efficient in FPGA LUTs. As observed in column four of Table 3, the comparison to FPGA slices is not possible, as the corresponding information is not presented in the reference design. The reason for the use of higher FPGA LUTs in [19] is that it is low latency ECC architecture with three modular multipliers in the datapath. In our implementation, we have only one modular multiplier. Furthermore, our PM architecture takes 9165 clock cycles for one PM computation while the reference design utilizes 7628 clock cycles (as given in column six of Table 3).