## 3 Improved Parallel Architecture
### Parallel Dual Feedback Loop
#### 3.2.1 Parallel Module  
Every PM needs five source signals and each interpolator has four, the three source signals in the middle are used by both interpolators.  
\begin{table}
\begin{tabular}{l l} \hline \hline
**In [10]** & **Associated Index** \\ \hline index(i) & index(i) \\ index(i+1) & index(i)+1 \\ \(\cdots\) & \(\cdots\) \\ index(i+m-1) & index(i)+m-1 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Index Relation.  
\begin{table}
\begin{tabular}{l l l l} \hline \hline
**Parameter** & & **LUT** & **FF** \\ \hline Utilization & In [10] & 21,248(7.00\%) & 3175 (0.52\%) \\  & Proposed & 6881 (2.27\%) & 2531 (0.42\%) \\ Available & & 303,600 & 607,200 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Resource utilization comparison.  
Coefficient Multiplier-Free Interpolator  
As it has been summarized in [15], three multipliers/dividers will be consumed with cubic interpolator while updating the coefficients every time, and two while updating with four-point piecewise-parabolic interpolator (\(\alpha=1/2\)) in serial systems. The coefficients are shown in Equation (2).  
\[C_{-2} =1/2\cdot x^{2}-1/2\cdot x,\] \[C_{-1} =-1/2\cdot x^{2}+3/2\cdot x,\] \[C_{0} =-1/2\cdot x^{2}-1/2\cdot x+1,\] \[C_{1} =1/2\cdot x^{2}-1/2\cdot x, \tag{2}\]  
where \(x\) stands for the input signals. Specifically, \({}^{\prime}3/2\cdot x^{\prime}\) in Equation (2) is separated into \({}^{\prime}1/2\cdot x+x^{\prime}\). Then all Farrow coefficients of four-point piecewise-parabolic interpolator with \(\alpha=1/2\) will be an integer multiple of 2. This makes the multiplier/divider could be implemented with shift operations on FPGA [21]. In other words, four-point piecewise-parabolic with \(\alpha=1/2\) is the best choice for FPGA that could balance the maximum resource savings with minimal performance deterioration.  
The Farrow structure on FPGA is shown in Figure 3.  
where, \(D\) stands for hardware delay, and the symbols are corresponding to those in Equation (2). In particular, one more extra delay is caused by the coefficient \({}^{\prime}3/2^{\prime}\) which is separated into \({}^{\prime}1+1/2^{\prime}\) described above. While each adder brings in 1 delay, and the multiplier brings in 3. So it is easy to find out that the number of delays caused by interpolator is 11. Where,  
2 Error Detector  
Gardner's timing error detector (TED) [16] is shown in Equation (3).  
\[e(n) =I(n-1/2)[I(n)-I(n-1)]\] \[+Q(n-1/2)[Q(n)-Q(n-1)], \tag{3}\]  
where \(e(n)\) is the timing error, \(I(n)\) and \(Q(n)\) are real and image parts of the interpolator's output, \(n-1,n-1/2,n\) are three continuous indexes.  
TED equation in a parallel system is shown in Equation (4) below  
\[e(n,i) =I_{1}(n,i)[I_{2}(n,i)-I_{2}(n,i-1)] \tag{4}\] \[+Q_{1}(n,i)[Q_{2}(n,i)-Q_{2}(n,i-1)],\]  
Figure 3: Farrow structure for piecewise-parabolic interpolator (\(\alpha=1/2\)).  
where \(e(n,i)\) is the timing error of the \(i\)th PM at time \(n\). For I signal, \(I_{1}(n,i)\) is the first interpolator's output of the \(i\)th PM at time \(n\), \(I_{2}(n,i)\) is the second interpolator's output of the \(i\)th PM at time \(n\), \(I_{2}(n,i-1)\) is the second interpolator's output of the \(i-1\)th PM at time \(n\). When \(i\)=1, \(I_{2}(n,i-1)\) stands for the second interpolator's output of the last PM at time \(n\)-1. Q signal has the same explanation.  
For FPGA implementation, each error detector contains two adders and two multipliers. The hardware block diagram is depicted in Figure 4.  
where \(D\) stands for hardware delay, and the symbols are corresponding to those in Equation (4). From Figure 4, it can be seen that the total delay is 5, in which the adders bring in 1 delay each and multipliers bring in 3.