## 1 Introduction  
It has been well known that non-volatile memory (NVM) plays an important role in various systems with the embedded or external structures. For smart data and smart sensor applications, data integrity is of primary importance. From automotive to aerospace fields, research continuously discusses the topic of non-volatile memory's failure models. Experimental results show that the erased and programed cells have different threshold voltage (V\({}_{\text{TH}}\)) shifts [1]. For the programed cells, V\({}_{\text{TH}}\) decreases when the floating gate is hit by an ion, resulting in a reduction of the floating gate stored negative charge. On the contrary, in the case of erased cells, no threshold variation is observed. Figure 1 shows one of the results in [1]. Read only memory (ROM) is a semiconductor memory. Its characteristics is its contents cannot be changed or erased once they have been stored in it. Moreover, its contents will not disappear in spite of power-off. It can be either Electrically-Erasable Programmable Read-Only Memory (EEPROM) or NOR FLASH in implementation. In this study, any floating-gateROMs can match the characteristics in Figure 1. Two ROM devices can be chosen for verification--the AT24 CS of Atmel, and the S25 FL128S of CYPRESS. They are popular and easily available.  
According to Reference [2], Figure 2 specifies how reading error is caused by the shifted V\({}_{\text{TH}}\) (\(\Delta\)V\({}_{\text{TH}}\)). When the cell's V\({}_{\text{TH}}\) is lower than read voltage (V\({}_{\text{read}}\)), read error happens because status \"0\" is read as \"1\". Status \"1\" does not have this side-effect, because the \(\Delta\)V\({}_{\text{TH}}\) of status \"1\" is almost zero according to the conclusion in Reference [1]. Obviously, the error rates caused by radiation are different between erased cells (status \"1\"), and programmed cells (status \"0\"). In Reference [3], a dynamic read reference voltage is used in reading data from non-volatile memory cells. The read reference voltage is calibrated. An Error Checking and Correction (ECC) algorithm is performed to identify whether errors exist in the data for read using the initial read reference voltage level. If errors in the data are identified when read, a pre-determined value is retrieved to adjust the initial read reference voltage level to a new read reference voltage level.  
In this paper, a novel technology called \"Variable Length Error Detection Code\" (VLEDC) for the Non-Volatile Memory (NVM) protection is proposed. Although there have been some methods about variable length coding of memory protection [4; 5], they were developed without considering the error rate difference between status \"1\" and status \"0\" in the memory content. Combined with two-dimensional parity check architecture, the proposed 2D-VLEDC can achieve a high error coverage with significant cost reduction. Compared with the traditional ECC techniques, selectivity can be made  
Figure 1: Cumulative distributions of threshold voltages for exposed cells [1].  
Figure 2: The situation of reading error due to shifted voltage of V\({}_{\text{TH}}\)[2].  
in our design to allow a user to choose either ECC or parity check according to the contents stored in ROM, thereby decreasing the required redundant bits significantly.  
This paper was organized as follows: In Section 2, how the 2D-VLEDC works and is applied to NVM is described. Section 3 discusses the experiments on performance comparison of other methods of memory protection with our 2D-VLEDC. Concluding remarks are given in Section 4.