## 4 Experiments and Discussion
### Lab Test Based on the PVDF Piezoelectrc Film
#### 4.3.2 Experimental Setup  
An appropriately designed interface circuit plays a key role in the optimization of the PVDF sensors. The signal output of the PVDF sensor is expected to be only \(\pm\)10-20 mv, meanwhile, the signal has a high output resistance and a high Gaussian noise, which contributes to the inaccuracies of the sampling process. Considering the frequency range and signal amplitude requirements over the desired dynamic range for the sampling circuit, the voltage of output signal needs to be maintained in the range of 0-3 V. The most critical part of an interface circuit is a proper input resistance. The input resistance affects low frequency measurement capability as well as signal amplitude, which is called the \"loading effect\". To meet the needs of high sampling rate and to improve signal integrity, a  
\begin{table}
\begin{tabular}{c c c} \hline \hline \(\mathbf{AV_{PVDF}/mV}\) & \(\mathbf{\Delta\varepsilon_{strain}/\mu c}\) & \(\mathbf{K(AV/\Delta\varepsilon)}\) \\ \hline
1510 & 226 & 6.68 \\
1970 & 301 & 6.54 \\
2570 & 399 & 6.44 \\
2880 & 448 & 6.43 \\
3160 & 501 & 6.31 \\
3550 & 555 & 6.40 \\ \hline \hline \end{tabular}
\end{table}
Table 6: The output of PVDF and strain gauge (5 Hz).  
Figure 16: Sensitivity of the PVDF (5 Hz).  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Loading frequencies (Hz)** & \(K\) (\({}_{mv/\mu\varepsilon}\)) \\ \hline
0.5 & 5.71 \\
1 & 6.45 \\
2 & 6.34 \\
5 & 6.14 \\
10 & 6.68 \\
15 & 7.38 \\
20 & 7.88 \\ \hline \hline \end{tabular}
\end{table}
Table 7: \(K\) under different loading frequencies (0.5\(\sim\)20 Hz).  
well-designed interface circuit is introduced into the system as shown in Figure 17, including: (1) a RC integral circuit; (2) a voltage follower; (3) a voltage amplifier; (4) a voltage generator; and (5) a voltage adder. A RC integral circuit converts the charges generated by the PVDF into voltage signal. Figure 18 is a photograph of the unit. A voltage follower reduces the loading effect and isolates the input from the output. A voltage amplifier offers an adjustable gain ranged from 1 to 100, facilitating a desired output for sampling purpose. Regarding to the dynamic range requirements, a voltage adder pulls the signal above the ground. By applying the basic circuit principles, the output voltage, \(V_{0}\), can be calculated as:  
\[V_{0}=-\frac{R_{\mathrm{g}}}{R_{\mathrm{i}}}V_{PVDF+}+\frac{R_{\mathrm{g}}}{R_{ \mathrm{g}}+R_{\mathrm{7}}}V_{+SV} \tag{7}\]  
where \(R_{\mathrm{g}}\)is the gain resistance, \(R_{\mathrm{7}}\) regulates the output pull-up, and \(V_{PVDF+}\) is the input of PVDF.  
6061-T6 aluminum alloy is used again as the test material in this lab test. The geometric layout of the test specimen is illustrated in Figure 19, with the test setup shown in Figure 20. Again, the symmetrical stress ratio equals to negative 1 because of fatigue loading, so, \(R=-1\). Meanwhile, the frequency of the load is 10 Hz and a power amplifier is used to control the vibration amplitude. Nine specimens were tested under different stress level.  
Figure 17: Pre-processing circuit of the unit of the PVDF sensor.  
Figure 18: Photo of the pre-processing unit of the PVDF sensor.  
Figure 21 shows a screenshot of the wireless transceiver software of the PVDF sensor tests. The numbers enlarged and framed in red are the consecutively increased counting results of two cycles, which are 1,742 and 1,899. The enlarged numbers in the green frames will increase by one once the cycle counting is cumulative to 10,000. For example, the number in Figure 21 is 41, which means the cycle counting is 410,000. The accuracy of the system is high, with a relative error of less than 5%.