# Efficient QC-LDPC Encoder for 5G New Radio
## 4 Proposed 5G NR QC-LDPC Encoder Design
### Proposed QC-LDPC Encoder Architecture  
Figure 4 details the overall block diagram for the proposed low complexity 5G NR QC-LDPC code encoder. The hardware architectures were designed to conduct the encoding process through steps defined in Equations (29)-(32) and (34). In the first step, the computation of the parity bits in the first portion \(p_{a}\) is carried out. From Equation (28), each \(\lambda_{i}\) value is computed by accumulating all the cyclic shift results of \(s_{j}\). Since the information message \(s\) consists of \(k_{b}\) blocks of \(Z\) bits, a total of \(k_{b}=22\) barrel shifters of size \(Z\), which are denoted by \(CS_{j}\), \(j=1,2,...,k_{b}\), are required for the  
circular shift process. The vector addition of all the \(\lambda_{i}\) components is then carried out by the XOR trees. Each intermediate \(\lambda_{i}\) value corresponding to Equation (28) can be estimated per clock cycle and stored in the \(\lambda\_\)memory to be used later. Thus, the value of \(p_{a_{1}}\) can be obtained in \(g=4\) clock cycles when all \(\lambda_{i}\) values are obtained and stored in memory. The remaining parity bits of \(p_{a}\) can be obtained in 2 clock cycles with the use of XOR gates.The objective of the second step is the calculation of the parity bits in the second portion \(p_{c}\). According to (34), the parity blocks \(p_{c_{i}}\) can be achieved by the vector addition of \(c_{i,j}s_{j}\) and \(c_{i,k_{b}+j}p_{a_{j}}\). The value of \(c_{i,j}s_{j}\) is also computed by accumulating all the cyclic shift results of \(s_{j}\). In this step, the overall hardware complexity can be further decreased by exploiting the sharing technique. More specifically, the barrel shifters and XOR trees are reused for the computation of \(p_{c}\) in this step. Control signals are generated by the controller block. The value of \(c_{i,k_{b}+j}p_{a_{j}}\) is estimated by accumulating all the cyclic shift results of \(p_{a_{j}}\). The required number of \(Z\)-bit barrel shifters is \(g=4\). The main blocks of the proposed architecture can be described as follows. (1) Input/ Output Buffer: the input buffer, which is implemented as a number of serial input parallel output shift registers, is exploited to store the input systematic bits \(s_{i}\) received by the encoder. The output buffer is used to store the encoded codeword. (2) Memory Blocks: two memory blocks are utilized, namely, one for the submatrix permutation values, and the others for the accumulated values \(\lambda\) that correspond to matrix \(A\). In Figure 4, the AROM, C\({}_{1}\)ROM,and C\({}_{2}\)ROM correspond to the ROMs that store the coefficients of matrix \(A\), matrix \(C_{1}\), and matrix \(C_{2}\), respectively. Under the assumption that \(\tilde{q}=\lceil log_{2}Z\rceil\) bits represent the required word length to store the permutation information for each submatrix: \(\tilde{q}gk_{b}\), \(\tilde{q}(m_{b}-g)k_{b}\), and \(\tilde{q}(m_{b}-g)g\) bits are required to store matrix \(A\), \(C_{1}\), and \(C_{2}\), respectively. A significant portion of the hardware complexity of the LDPC encoder consists of the memory required to store the parity check matrix. Unlike the RU method, the proposed algorithm does not require the inverse of the component matrix, which reflects its primary advantage over the RU method. Compared with the Gaussian method, the proposed architecture does not require for block-memories to store the generator matrix \(G\), which further decreases the number of required components. The \(\lambda\_\)memory is implemented as a dual port random access memory (RAM) for storing \(\lambda_{i}\) messages \((i=1,2,\ldots,g)\). Each memory word \(\lambda_{i}\) consists of \(Z\) bits, corresponding to one accumulated message of matrix \(A\). Moreover, a total of \((g\times Z)\) bits of \(\lambda\_\)memory are required for the proposed encoder. (3) Barrel Shifters: barrel shifters are used to implement the cyclic shift permutations, according to the shift values provided by the cyclic shifter controllers.