# A High Gain Modified Quadratic Boost DC-DC Converter with Voltage Stress Half of Output Voltage
## 6 Results and Discussion
### Simulation Results and Potential Verification  
To validate the performance of the converter, the proposed circuit was stimulated in SIMPLIS software. The circuit parameter value was selected exactly as described in Table 2. The only difference in the simulation configuration is the power diode. A different diode model (RF1501 TF3S) has been chosen due to not having the same diode model number of the diode in SIMPLIS simulation software, which has the same specification as compared to the used diode model (i.e., CMPFC86) for experimental verification, The simulation was carried out with an input voltage of 48 V at a switching frequency of 50 kHz. All of the components were selected as ideal components. The load resistance was selected according to the 150-W output power. Figure 12 shows the circuit configuration from SIMPLIS software.  
Simulation Results of the Proposed Boost Converter at Duty d = 0.4, Output Power 150-W  
Though the actual duty cycle was considered 0.4, in the experimental section, the MOSFET was not turned off at exactly at the duty cycle of 0.4; instead, it was turned off at duty 0.402 due to the Miller effect. So, the simulation was carried out by selecting the duty cycle of 0.402 and the corresponding theoretical output voltage, referring to Equation (22) was calculated as 428 V. However, due to the presence of a diode forward voltage drop the actual voltage deviates, and as a result the real voltage gain is always lower than the ideal gain. From the datasheet of the diode's model, the forward voltage drops (i.e., 1.5 V) of the diode were taken into consideration, and referring to Equation (31), the actual output voltage was calculated (i.e., 408 V). However, due to the presence of parasitic resistance in the passive component, the actual voltage is further reduced, which is reflected in the experimental results in the later section.  
In Figure 13, the simulated waveform of the (a) input voltage (\(V_{in}\)), (b) duty cycle (\(V_{gs}\)), (c) switch voltage stress of the switch (\(V_{DS}\)), and (d) output voltage (\(V_{0}\)) are shown, respectively. The results show that the output voltage obtained by the simulation was about 408 V which is matching, according to the previously discussed value. The voltage stress of the diodes is shown in Figures 14 and 15. The voltage across each of the working capacitors is shown in Figure 16, whereas the plot of the inductor currents is shown in Figure 17, respectively.  
Figure 12: Pictorial representation of proposed circuit simulated in SIMPLIS software.  
Figure 14: Simulated waveform of (**a**) duty cycle (\(V_{gs}\)) at duty d = 0.402, (**b**) Voltage stress of diode D\({}_{1}\) (V\({}_{\rm D1}\)), (**c**) Voltage stress of diode D\({}_{2}\) (V\({}_{\rm D2}\)), and (**d**) Voltage stress of diode D\({}_{3}\) (V\({}_{\rm D3}\)).  
Figure 13: Simulated waveform of (**a**) input voltage (\(V_{in}\)), (**b**) duty cycle (\(V_{gs}\)) at duty d = 0.402, (**c**) switch’s voltage stress (\(V_{DS}\)), and (**d**) output Voltage (\(V_{0}\)).  
Figure 16: Simulated waveform of (**a**) duty cycle (\(V_{gs}\)) at duty d = 0.402, (**b**) Capacitor (\(C_{3}\)) voltage (\(V_{C3}\)), (**c**) Capacitor (\(C_{2}\)) voltage (\(V_{C2}\)), and (**d**) Capacitor (\(C_{1}\)) voltage (\(V_{C1}\)).  
Figure 15: Simulated waveform of (**a**) duty cycle (\(V_{gs}\)) at duty d = 0.402, (**b**) Voltage stress of diode D4 (\(V_{\rm Dd}\)), (**c**) Voltage stress of diode D5 (\(V_{\rm D5}\)), and (**d**) Voltage stress of diode D6 (\(V_{\rm D6}\)).