## 4 Implementation Results and Comparisons
### Comparison to State of the Art
#### 4.3.2 Comparison to Karatsuba and Montgomery Multiplier Architectures  
_Comparison of our architectures of Figures 5 and 7 over Artix-7 with [24]._ When considering the FPGA LUTs for comparison, our dedicated and flexible architectures of Figures 5 and 7 utilize 8.03 (ratio of 49,211 with 6128) and 6.13 (ratio of 49,211 with 8019) times lower hardware resources, respectively. As we mentioned earlier in Section 1.2, the Karatsuba multiplication is a bit-parallel multiplication approach where the inputs to the Karatsuba multiplier are split into two smaller polynomials. Then, the smaller polynomials are further split into two additional polynomials. The repetition of this process is essential to obtain enough smaller polynomials to apply the schoolbook multiplication method for the polynomial multiplications. Therefore, to generate a resultant polynomial for the Karatsuba method, the multiplication over smaller polynomials must be performed in reverse order (i.e., from smaller polynomials to larger). Thus, splitting for the Karatsuba multiplier results in higher hardware resources as compared to our architectures, where we use the digit-parallel method instead of bit-parallel. As shown in Table 2, the comparison in terms of clock cycles, clock frequency, latency and power is not possible as the relevant information is not given.  
_Comparison of our architectures of Figures 5 and 7 over Spartan-7 with [27]._ Concerning the FPGA LUTs for comparison, our dedicated and flexible architectures of Figures 5 and 7 utilize 5.90 (ratio of 40,056 with 6784) and 4.62 (ratio of 40,056 with 8653) times lower hardware resources, respectively. This is due to a novel architecture (termed a composite model) based on the m-term Karatsuba-like and schoolbook multiplication method. In their composite solution, the m-term Karatsuba-like method uses all polynomial splits to multiply polynomial coefficients rather than the least split polynomials. A simple schoolbook method is applied for one time to perform polynomial multiplications over the smallest splits. Consequently, the combined use of a schoolbook and Karatsuba multiplier results in higher hardware resources as compared to our designs, where we only use a schoolbook multiplication method. Similar to [24], the comparison in terms of clock cycles, clock frequency, latency and power parameters is not possible as the corresponding information is not available.  
_Comparison of our architectures of Figures 6 and 7 over Virtex-7 with [26]._ The full-word Montgomery modular multiplication architecture consumes 2.98 (ratio of 20,695 with 6943) and 2.77 (ratio of 20,695 with 7461) times higher hardware resources as compared to our dedicated and flexible architectures of Figures 6 and 7, respectively. The use of a Karatsuba algorithm for splitting input polynomials into four parts and deep four parts is the reason for the use of higher hardware resources in the Montgomery multiplier design of [26]. In our multiplication architectures, we have not used any specific algorithm (or protocol) to split the input polynomials. Moreover, the use of a simple schoolbook multiplication method is another reason for the lower hardware resources in our designs. Despite the hardware resources, our dedicated and flexible designs are faster in terms of clock cycles, operational clock frequency and computational time (see columns six to eight of Table 2). The power comparison is not possible as the required information is not available in [26].