## 2 Materials and Methods  
The fabrication process of the device is shown in Figure 1a. A silicon-on-insulator (SOI) wafer is utilized to minimize electron interactions between devices and reduce leakage current. After cleaning the SOI wafer, unnecessary silicon regions were removed through an etching process, and each device was fabricated in an isolated form on top of the BOXlayer. By utilizing the insulating BOX layer of the SOI structure, each device is electrically isolated from the underlying substrate, enabling accurate electrical characterization without interference between devices. The SOI wafer consists of a device (silicon) layer with a resistivity of 8-22 \(\Omega\cdot\)cm and a thickness of 290 nm, a buried oxide (BOX) layer with a thickness of 1 \(\upmu\)m, and a substrate layer with a thickness of 675 \(\upmu\)m.  
The fabrication process starts with cleaning procedure using acetone, methanol, SPM (sulfuric peroxide mixture), and BOE (buffered oxide etchant, 6:1) solutions. Subsequently, lithography and etching processes are conducted to define the active area. The tunnel oxide, which facilitates electron tunneling, is fabricated by forming a 30 A thick SiO\({}_{2}\) layer using thermal dry oxidation in a furnace, followed by the deposition of 50 cycles HfO\({}_{2}\) using atomic layer deposition (ALD) method. The floating gate, serving as the electron storage and erase site, is implemented in a mesh-type structure using chromium (Cr) and platinum (Pt). Image reversal lithography (IR lithography) is employed to pattern the mesh-type floating gates by optimizing UV exposure  
Figure 1: (**a**) Schematic diagram of device fabrication. SEM image of (**b**) mesh-type floating gate and (**c**) Mesh-FGT. (**d**) The SPD process and a comparison of sheet resistance based on RTA temperature and curing time. and development times [28]. A total of 2.5 nm of Cr and 25 nm of Pt are deposited via sputtering, and the mesh pattern is defined using a lift-off process to complete the floating gate. As shown in Figure 1b, the mesh-type floating gate is fabricated with dimensions of 3 \(\upmu\)m \(\times\) 3 \(\upmu\)m, acting as separated floating charge storage node under the control gate. We fabricate the mesh-type floating gate due to its durability and multi-level functionality. The control oxide, which acts as a barrier to prevent electron erasure from the floating gate, is designed to be thicker than the tunnel oxide. This layer was fabricated by depositing 200 cycles of HfO\({}_{2}\) using ALD process. The control gate is then formed by depositing 2.5 nm of Cr and 100 nm of Pt, followed by IR lithography, sputtering, and lift-off processes. Figure 1c shows the SEM image of the manufactured synaptic device with a gate width of 50 \(\upmu\)m and a gate length of 3 \(\upmu\)m, respectively. Before n-type phosphorus doping, an etching process is conducted to remove deposited HfO\({}_{2}\) and oxidized SiO\({}_{2}\) in the areas designated for dopant injection. Phosphorus is subsequently introduced into the device using the solid phase diffusion (SPD) process [29; 30; 31]. Figure 1d shows a schematic of the SPD process and a comparison of sheet resistance according to the temperature and time of RTA (rapid thermal annealing) during the curing process. The RTA temperature and time are chosen as the optimal process conditions to minimize control gate damage and to satisfy a doping concentration of 10\({}^{19}\) cm\({}^{-3}\) or higher. At an RTA temperature of 800 \({}^{\circ}\)C and a duration of 20 min, sheet resistance is measured as 65 \(\Omega\)/\(\square\) and the doping concentration is determined to be 5 \(\times\) 10\({}^{19}\) cm\({}^{-3}\) using the four-point probe system and the Hall effect measurement system. To enhance electrical contact between the probe and the source, drain, and gate during device measurements, the Al pad formation process is performed using IR lithography, sputtering, and lift-off techniques.