# Single EX-CCCII-Based First-Order Versatile Active Filter
## 3 Simulation Results  
To validate the proposed universal active filter, the EX-CCCII was designed in SPICE using standard n-well CMOS 0.18 \(\upmu\)m technology. The supply voltage was set to \(\pm\)0.9 V. The width and length of the MOS transistors for the EX-CCCII are listed in Table 1[50]. Simulated performances of the EX-CCCII are summarized in Table 2. \begin{table}
\begin{tabular}{l c} \hline \hline  & **Transistor** & **W/L (\(\upmu\)m)** \\ \hline M\({}_{1}\)–M\({}_{3}\) & 5/0.36 \\ \hline M\({}_{4}\)–M\({}_{6}\) & 15/0.36 \\ \hline M\({}_{\rm b}\), M\({}_{7}\)–M\({}_{18}\) & 3/0.36 \\ \hline M\({}_{19}\)–M\({}_{30}\) & 6/0.36 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Aspect ratios of the MOS transistors of the EX-CCCII’s structure. The simulated intrinsic resistances \(R_{x}\) (\(R_{x}=R_{x2}=R_{x2}\)) against the setting current \(I_{set}\) are shown in Figure 5. The intrinsic resistances \(R_{x}\) varied in square-root form from 13.49 k\(\Omega\) to 1.13 k\(\Omega\) while the setting current \(I_{set}\) was increased from 1.5 uA to 70 uA. Figure 6 shows the simulated magnitude frequency responses of the HPF and LPF and the magnitude and phase frequency responses of the APF when the circuit was designed as C\({}_{1}\) = 30 pF and \(I_{set}\) = 20 uA (\(R_{x}\) = 1.81 k\(\Omega\)). The simulated pole frequency was 2.91 MHz, whereas the designed pole frequency was 2.93 MHz. The circuit consumed 0.558 mW of power, and the \(-\)3 dB bandwidth of the filter was 600 MHz. The theoretical value was used to confirm the simulation results, showing that the simulation results agree with the theory. \begin{table}
\begin{tabular}{l c} \hline \multicolumn{1}{c}{**Parameters**} & \multicolumn{1}{c}{**Value**} \\ \hline Technology & 0.18 \(\upmu\)m CMOS \\ \hline Power supply & \(\pm\)0.9 V \\ \hline DC voltage range & \(\pm\)200 mV \\ \hline DC current range & \(\pm\)200 uA \\ \hline Voltage gain V\({}_{x}\)/V\({}_{y}\) & 0.964 \\ \hline Current gain (I\({}_{x}\)\({}_{-}\)/I\({}_{x}\)) & 1.01 \\ Current gain (I\({}_{x}\)\({}_{-}\)/I\({}_{x}\)) & 1.04 \\ \hline Bandwidth (\(-\)3 dB) @ I\({}_{\mathrm{set}}\) = 20 uA & \\ Voltage follower (V\({}_{x}\)/V\({}_{y}\)) & 2 GHz \\ Current follower (I\({}_{x+}\)/I\({}_{x}\)) & 61.46 MHz \\ Current follower (I\({}_{x-}\)/I\({}_{x}\)) & 61.46 MHz \\ \hline THD [V\({}_{y}\) = 200 mV @ 10 kHz] & 0.69\% \\ \hline PSRR+ & 32.82 dB \\ PSRR\(-\) & 37.67 dB \\ \hline Parasitic parameters @ I\({}_{\mathrm{set}}\) = 20 uA & \\ - R\({}_{y}\), C\({}_{y}\) & 104 k\(\Omega\), 0.14 pF \\ - R\({}_{x}\), L\({}_{x}\) & 1.81 k\(\Omega\), 62 nH \\ - R\({}_{x}\), C\({}_{x}\) & 221.35 k\(\Omega\), 75.68 fF \\ \hline Power consumption @ I\({}_{\mathrm{set}}\) = [10–50] uA & [0.29–1.24] mW \\ \hline \end{tabular}
\end{table} 
Table 2: Simulated specifications of the EX-CCCII. Figure 5: The intrinsic resistance \(R_{x}\) against the setting current. Figure 7 shows the simulated magnitude frequency responses of the HPF and LPF and the magnitude and phase frequency of the APF when the setting current \(I_{set}\) (i.e., 10, 15, 25, or 60 \(\mu\)A) was used to vary the pole frequency. This result is confirmed by (7). Figure 6: Simulated frequency responses of non-inverting (**a**) HPF, (**b**) LPF, and (**c**) APF. Figure 7: Simulated frequency responses with different setting currents for (**a**) HPF, (**b**) LPF, and (**c**) APF. Figure 8 shows the simulated magnitude frequency responses of the HPF, LPF, and APF when several parameters were varied. Figure 8a shows the magnitude frequency responses when the threshold voltage in the CMOS process was varied by 10% (LOT tolerance); the curves are overlapped here. A Monte Carlo analysis with 200 runs was used for simulation and some simulated magnitude frequency responses were selected to be shown. This is used to represent a process variation.