## 4 Derivation of the Hybrid Compact Systolic Multiplier
### The Explored Multiplier Layout  
The hybrid systolic multiplier architecture, as illustrated in Figure 3, is constructed by applying the derived scheduling and projection functions, \(\Delta(\mathbf{\Gamma})\) and \(\overline{\mathbf{\Gamma}}(\mathbf{\Gamma})\), to the DG nodes. This systematic approach enables an efficient mapping of operations across the PEs. In Figure 3, the systolic structure consists of \(r\) PEs, each designed to perform specific tasks in parallel. Notably, the functional design of the first processing element (PE\({}_{1}\)) is illustrated in Figure 4, highlighting its unique capabilities. In contrast, the functional design for the regular processing elements (PE\({}_{j}\)) is shown in Figure 5, demonstrating the consistent design principles applied across the architecture. Unlike earlier two-dimensional systolic and semi-systolic implementations, the proposed one-dimensional hybrid systolic multiplier demonstrates a significant reduction in area complexity, attaining a linear complexity instead of a quadratic complexity. This reduction not only enhances area efficiency but also contributes to overall performance optimization. Furthermore, when compared to the [PERSON] two-dimensional systolic designs detailed in [18; 19; 20], the resulting architecture exhibits improved space complexity, making it a compelling choice for resource-constrained applications. As illustrated in the findings section, the proposed multiplier configuration significantly surpasses multipliers that utilize traditional field multiplication techniques, such as those presented in [18; 19; 20; 32; 39; 42; 50; 51]. This emphasizes the outstanding performance and efficiency of the proposed architecture, solidifying its potential for enhancing multiplication operations in various computational contexts. The hybrid systolic multiplier employs dedicated input ports for efficient data handling. Input ports \(e_{a}\), \(e_{b}\), and \(e_{c}\) are allocated to the first processing element (PE\({}_{1}\)) and are sequentially fed by the signals \(e_{r-i+1}\), \(e_{i-1}\), and \(e_{r-i}\) for each \(i\) ranging from 1 to \(r\). Initially, input port \(e_{a}\) receives the \(e_{r-i+1}\) signals. After \(r\) clock cycles, input port \(e_{b}\) is similarly fed the \(e_{i-1}\) signals, and after another \(r\) clock cycles, input \(e_{c}\) is fed with the \(e_{r-i}\) signals. In conjunction, input ports \(f_{a}\), \(f_{b}\), and \(f_{c}\) are also assigned to PE\({}_{1}\) and are sequentially fed using the signals \(f_{i}\) and \(f_{r-i+1}\) for each \(i\) ranging from 1 to \(r\). Initially, input port \(f_{a}\) receives the \(f_{i}\) signals. After \(r\) clock cycles, input port \(f_{b}\) follows suit, utilizing the same \(f_{i}\) signals, and subsequently, after another \(r\) clock cycles, input \(f_{c}\) is fed sequentially, this time with the \(f_{r-i+1}\) signals. The output signal \(e_{s}\) from PE\({}_{1}\) is designed to pipeline through all subsequent PEs, while the output signal \(f\) from PE\({}_{1}\) must also be propagated through all PEs. Additionally, the signal \(h\) is computed within each PE and is made available at the output every \(r\) clock cycles. Control signals \(c_{1}\) and \(c_{0}\) are specifically allocated to PE\({}_{1}\) to manage certain tri-state buffers within this PE, as will be elaborated in subsequent sections. Control signal \(c\) is employed to facilitate the selection between signal \(e_{s}\) and those assigned to port \(e_{in}\), as demonstrated in Figure 5. This control signal must propagate through the regular PEs (PE\({}_{j}\)) to ensure its availability in each of these elements.