# A 2.4-GHz Fully-Integrated GaAs pHEMT Front-End Receiver for WLAN and Bluetooth Applications
## 2 Circuit Design
Figure 3: Asymmetrical single-pole triple-throw (SP3T) switch topology. propose a solution to the dilemma of matching the input and noise impedance with the source of 50 \(\Omega\) simultaneously [16; 17]. The effect of the pHEMT M\({}_{1}\) on the input impedance can be minimized by introducing an inductor (L\({}_{\rm g}\)) [18; 19]. The configuration of matching networks and impedance traces of the proposed LNA are depicted in Figure 4. The input impedance of the entire cascode LNA including input and output matching networks, \(Z_{in}\), the input impedance of the common source (CS) amplifier, \(Z_{in1}\), and the input impedance of common gate (CG) amplifier, \(Z_{in2}\), can be written as:  
\[Z_{in}(\omega)=j\frac{\omega L_{g}}{1-\omega^{2}L_{g}C_{g}}+Z_{in1} \tag{1}\]  
\[Z_{in1}(\omega)=\frac{r_{o1}g_{m1}L_{s}+L_{s}}{r_{o1}C_{gs1}}+j\frac{\omega^{ 2}C_{gs1}L_{s}-1}{\omega C_{gs1}} \tag{2}\]  
\[Z_{in2}(\omega)=\frac{r_{o2}}{1+g_{m2}r_{o2}}+j\frac{\omega L_{D}}{1+g_{m2}r_ {o2}} \tag{3}\]  
where \(g_{m1}\) and \(g_{m2}\) are the transconductances, and \(r_{o1}\) and \(r_{o2}\) are the channel resistances of the CS and CG transistors, respectively. \(C_{gs1}\) is the gate-to-source parasitic capacitance of the CS stage. It is easy to prove that the output impedance of the CS stage is given by  
\[Z_{out1}=r_{o1}+j(\omega r_{o1}g_{m1}L_{s}+\omega L_{s}) \tag{4}\]  
Figure 4: (**a**) Small-signal equivalent circuit of proposed low-noise amplifier (LNA) circuit, (**b**) configuration of proposed impedance traces. Thus, the voltage gain of the CS stage without input matching network can be derived as:  
\[A_{v1}=\frac{g_{m1}r_{o1}Z_{in2}}{r_{o1}+j\omega L_{s}r_{o1}+j\omega L_{s}-Z_{in2}} \tag{5}\]  
The voltage gain of the CG stage can be expressed as:  
\[A_{v2}(\omega)=\frac{j\omega L_{D}+j\omega g_{m2}r_{o2}L_{D}}{j\omega L_{D}+r_{ o2}} \tag{6}\]  
Based on Equations (1), (5) and (6), the input impedance can be matched to 50 \(\Omega\) for maximum gain. However, apart from input impedance matching, modern LNA design also adopts noise cancellation to alleviate the trade-off between NF and S\({}_{11}\)[20; 21; 22; 23; 24]. Based on the circuit connection shown in Figure 4, the noise contribution of the transistors including M\({}_{1}\) and M\({}_{2}\) are considered in the design [25; 26]. The contribution of the CS stage to the output noise voltage is expressed as:  
Figure 3:0  
where \(k\) represents the Boltzmann's constant, and \(T\) represents the absolute temperature. The output noise voltage of CG stage can be expressed as:  
Figure 3:1  
Hence, the overall NF of the proposed LNA can be derived as:  
\[ \begin{array}{ll}NF&=1+\frac{\overline{V_{n1}^{2}}}{\left(\frac{Z_{in}}{Z_{ in}}\right)^{2}A_{v1}^{2}}\cdot\frac{1}{4 kTR_{s}}\\ &+\frac{\frac{\overline{V_{n2}^{2}}}{\left(\frac{Z_{in}}{Z_{in}}+R_{s}\right) ^{2}}A_{v1}^{2}\left(\frac{Z_{in}}{Z_{in2}+J\omega L}\right)^{2}A_{v2}^{2}} \cdot\frac{1}{4 kTR_{s}}\end{array}  \tag{9}\]  
Based on Equations (1) and (9), we optimize the input impedance and noise impedance to be close to the source impedance of 50 \(\Omega\) by selecting a periphery of 8 \(\times\) 50 \(\upmu\)m with 0.25 \(\upmu\)m E-mode pHEMT for the CS transistor. Here, L\({}_{s}\) = 0.3 nH, L\({}_{g}\) = 3.1 nH and C\({}_{g}\) = 0.25 pF. It is notable that device cannot be sized too small due to the input P\({}_{1 dB}\) constraint [3]. There is a trade-off between DC power consumption and power handling performance. For the given LNA, the input matching circuit dominates the NF performance, while the output matching has sight effect on the noise [27; 28]. Therefore, the gain is mainly considered in the output matching. The load inductor L\({}_{d}\) (5.2 nH), capacitance C\({}_{2}\) (0.4 pF) and parasitic capacitance of M\({}_{2}\) are resonated at operating frequency of 2.4 GHz. Since the DC power is mainly sensitive to the bias of the CS stage, a current mirror bias circuitry is used for the CS transistor while a resistor divider is utilized for the bias of the CG stage.