# NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method
## 1 Introduction  
As technology scales, reliability issues have become a vital concern in Very Large Scale Integration (VLSI) design. Among these reliability issues, performance degradation induced by negative bias temperature instability (NBTI) is one of the primary failure mechanisms when the feature size approaches the 65 nm scale [1]. NBTI occurs when positive-channel Metal Oxide Semiconductor (pMOS) transistors are negatively biased (\(V_{gs}=-V_{dt}\)), which causes a shift in the threshold voltages (\(V_{th}\)). Meanwhile, under the actual alternating current (AC) stress condition, when the stress voltage is removed periodically (\(V_{gs}=0\)), the magnitude of the \(V_{th}\) partially recovers toward its initial value. However, the recovery phase can only partially compensate for the NBTI effect [2]. Therefore, the threshold voltage of a pMOS transistor will increase over time, and this results in degradation of circuit performance. Once the critical path delay exceeds the limit, the circuit begins to fail. Another critical issue for VLSI design is excessive power consumption as the density of a device is dramatically increased. Traditionally, dynamic power is the main source of the total power of a device. However, as the supply and threshold voltage for VLSI circuits decreases, the leakage power dramatically increases [3]. According to the International Technology Roadmap for Semiconductors (ITRS), leakage power will contribute to over 50% of the total power in next-generation processors [4]. Excessive power dissipation will reduce the service life of an electronic system and result in some potential reliability problems, especially for those devices that require the battery to supply power, such as mobile phone and wireless sensor networks [5]. Both NBTI-induced delay degradation and excessive leakage power will significantly reduce the operational lifetime of VLSI circuits; therefore, many researchers have proposed different NBTI and/or leakage reduction methods from different levels of design abstraction. Power gating [6], internalnode control [7; 8], circuit-aging sensors [9], adaptive body bias and supply voltage techniques [10], and input vector control (IVC) [11; 12] are some representative methods. Among these methods, IVC is commonly used because of its low overhead in terms of performance and area cost. IVC was proposed initially to reduce the leakage power of complementary metal oxide semiconductor (CMOS) devices. It is based on the well-known transistor stacking effect: A CMOS gate's leakage current dramatically varies with the input vector applied to the gate [13]. Additionally, not every practical application requires the underlying hardware to perform at the highest speed all of the time; circuits often periodically switch between active and standby mode, and the standby time is often longer than the active time [7]. Therefore, the concept of IVC is to find the minimum leakage vector (MLV) that can reduce the leakage power when the circuit is in standby mode. In addition to leakage power, the NBTI effect is also dependent on an input vector. Therefore, IVC can also be applied to alleviate the NBTI effect on a VLSI circuit. Similar to leakage power reduction, the idea of IVC in NBTI mitigation is to find the minimum degradation vector (MDV) that can help the pMOS transistors in the circuit stay in a recovery phase as long as possible. However, in a real circuit, there exists logic interdependency between different gates, and we cannot control all of the pMOS transistors in a recovery state. Moreover, experimental results show that the recovery state can only partially alleviate the NBTI effect. Therefore, a circuit will still endure severe NBTI-induced delay degradation using IVC only, especially a large circuit. In an application where timing is critical, some supplemental methods need to be implemented together with IVC to guarantee the performance of the circuit.