## 3 Simulation Results
For instance, with a 120 Hz display refresh rate (8.33 ms per frame), apart from the 160 us scan time, the remaining 8.17 ms can be fully utilized for display driving, allowing the TSP to remain in idle mode, thereby improving the overall power efficiency. Secondly, as shown in Figure 10, external noise immunity was simulated by sweeping the external noise (\(\overline{V_{ND}}^{2}\) in Figure 8) from DC to 400 kHz in \(1\) kHz steps and injecting through C\({}_{\text{S}}\)[n]. To verify the discrete-time Gaussian filter response, the ADC output was demodulated using discrete signals of [1, \(-1\)] after A-D conversion and then decimated to DC to obtain the raw value at each display noise frequency. Compared to the FFT results obtained directly from the 64-tap Gaussian filter coefficients, the simulated noise performance under the noise sweep exhibits a high level of consistency, achieving \(-33\) dB noise rejection at 278 kHz. To evaluate the impact of process variation on the filter response, the metal-insulator-metal (MIM) capacitor in the chip is assumed to vary by \(\pm 15\%\) variation (\(\Delta\)Var) of its nominal value. Consequently, C\({}_{\text{GS,u}}\) in the Gaussian S/H circuit experiences the same variation. Figure 11 compares the Gaussian filter responses obtained from ideal 4-bit quantized filter coefficients and those affected by \(\pm 15\%\) random variations in C\({}_{\text{GS,u}}\). In the worst case, where C\({}_{\text{GS,u}}\) exhibits a \(\pm 15\%\) random mismatch across all nine samples, the attenuation capability degrades by 6.2 dB. However, since C\({}_{\text{GS,u}}\) is placed in close proximity within the same location, the impact of its random mismatch will be further mitigated in practice. Figure 8: Analysis of intrinsic and external noise sources in the readout system. Figure 9: Simulated transient output waveform of Gaussian-shaped S/H circuit (V\({}_{\text{S/H,O}}\)) in 64-tap Gaussian filter coefficient scan time. Figure 11: Frequency response comparison of a 64-tap Gaussian filter: C\({}_{\text{GS}}\) process variations in the S/H circuit (9 samples) vs. ideal 4-bit quantized coefficients. Figure 10: (**a**) Simulation setup with display noise insertion from DC to 400 kHz and (**b**) Comparison of external noise immunity: simulation results with noise frequency sweep and FFT results of 64-tap Gaussian coefficients. Figure 12 shows the simulated results of the C\({}_{\rm S}\) compensator's compensation linearity, where the reference capacitor C\({}_{\rm REF}\) is set to 20 pF, and the current gain (M), corresponding to the compensation capacitance, increases from 1/16 (1.25 pF) to 8 (160 pF) across a 7-bit range. The maximum capacitive error occurs at the midband of the compensation range, reaching 1.24 pF, which corresponds to a 0.078% error in the total 160 pF compensation range. To verify the impact of process variation on the compensation accuracy, the mismatch between source (Q\({}_{\rm SC}\)) and sink (Q\({}_{\rm SK}\)) compensation charges was analyzed using Monte Carlo simulations in the virtuoso tool, with C\({}_{\rm REF}\) ideally fixed, as shown in Figure 13. In the simulation, 500 deviation samples were obtained to evaluate the statistical distribution of compensation charge variations, while the results of Q\({}_{\rm SK}\) in (b) were scaled by the mean value of Q\({}_{\rm SC}\) to facilitate a direct comparison of their absolute value differences. The width and length of NMOS (M\({}_{\rm N2}\), M\({}_{\rm N4}\)) and PMOS (M\({}_{\rm P2}\), M\({}_{\rm P4}\)) cascode current sources are specified in Figure 4, with dimensions scaled in micrometers. With the aid of large channel length (=1.8 \(\upmu\)m), the standard deviation was measured as 0.25% for Q\({}_{\rm SC}\) and 0.24% for Q\({}_{\rm SK}\), while the difference between Q\({}_{\rm SC}\) and Q\({}_{\rm SK}\) is 1.2%, demonstrating high compensation accuracy.