# A Radiation-Hardened Low-Power SRAM with Enhanced Write Capability for Space Applications
## 4 Conclusions  
In this study, a 16-transistor radiation-hardened SRAM cell, named EWS-16T, was proposed to address soft-error issues in space environments. Through comprehensive simulations using a double-exponential current injection model, the cell demonstrated robust self-recovery capabilities when 300 fC of transient charge was individually injected into each sensitive node. This confirms the cell's strong resilience against SEUs. Furthermore, in SEMNU scenarios, the cell successfully recovered in all tested node pair combinations except when both Q and S0 were simultaneously struck. This critical case is effectively mitigated at the layout level by ensuring sufficient physical spacing between sensitive nodes, reducing the likelihood of charge-sharing-induced simultaneous upsets. Given its strong resilience to SEUs and SEMNUs, along with low power consumption, the proposed EWS-16T cell is well-suited for deployment in radiation-critical space applications. It can be effectively utilized in on-board memories of CubeSats, deep-space exploration systems, \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline
**SRAM Cell** & **WAT** & **WWTV** & **RAT** & **RSNM** & **HSNM** & **Hold Power** & **Qc** \\  & **[ps]** & **[mV]** & **[ps]** & **[mV]** & **[mV]** & **[nW]** & **[fc]** \\ \hline QCCS & 41.78 & 82 & 49.87 & 119 & 280 & 113.07 & 38.04 \\ SCCS & 43.08 & 69 & 34.93 & 119 & 280 & 169.6 & 38.04 \\ SAW16T & 34.12 & 159 & 78.48 & 34 & 167 & 56.83 & \textgreater{}300 \\ HP16T & 24.89 & 251 & 121.01 & 139 & 221 & 131.57 & \textgreater{}300 \\ RHSCC16T & 37.29 & 127 & 61.6 & 119 & 290 & 125.78 & 16.67 \\ S8P8N & 28.62 & 214 & 67.64 & 59 & 66 & 63.95 & \textgreater{}300 \\ EWS16T & 22.11 & 279 & 79.54 & 18 & 197 & 53 & \textgreater{}300 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Performance comparison of radiation-hardened SRAM cells. Figure 13: Comparison of (**a**) EQM and (**b**) weighted EQM for different SRAM cells. and embedded caches in launch vehicle controllers, where both energy efficiency and fault tolerance are essential. The proposed EWS-16T cell achieved a critical charge exceeding 300 fC, significantly higher than that of conventional hardened cells such as QCCS, SCCS, and RHSCC16T, demonstrating superior radiation tolerance. In addition, it exhibited the shortest write access time and the highest WWTV among all comparison cells. It also achieved the lowest hold power consumption, indicating excellent energy efficiency. However, due to its dual-access structure and complex internal feedback paths, the cell showed relatively lower performance in terms of read delay, RSNM, and HSNM. Despite these limitations, the EQM evaluation revealed that the EWS-16T cell achieves the highest overall performance among all evaluated designs. This is attributed to its optimized transistor sizing, enhanced feedback architecture, and reduced static power consumption, resulting in a well-balanced trade-off between write efficiency, soft-error resilience, and power performance. To further reinforce these results, future studies will include physical verification, extended charge injection experiments beyond 300 fC, and detailed Monte Carlo simulations to validate the cell's performance under practical operating conditions. The proposed EWS-16T cell is expected to be scalable to advanced technology nodes such as 28 nm CMOS and FD-SOI. These nodes offer advantages such as lower junction capacitance and improved radiation tolerance. In addition, the flexible layout and transistor sizing of the EWS-16T allow effective adaptation to increased variability and leakage current in nanoscale technologies. As a result, the cell can maintain stable operation even under advanced process conditions. In conclusion, the proposed EWS-16T cell offers a highly promising solution for radiation-hardened SRAM applications in space and other extreme environments, combining strong soft-error recovery, low power consumption, and enhanced write capability into a reliable and efficient memory design.