# Design of the Converter Prototype for Powering the Hydrogen Electrolyzer
## 3 Constant Current Source Control Algorithm  
The peak current control offers excellent dynamic performance for buck converters [25]. It operates with a constant switching frequency and variable duty cycle. The current reference and measured values are compared in a comparator. Initially, the measured value is lower than the reference, producing a true output, which triggers the control system to open the upper transistor. The inductor current rises until the measured value matches the reference. At this point, the comparator output switches to false, and the control unit turns off the transistor [18]. The inductor current decreases until the comparator resets to true [15]. This process is illustrated in Figure 6.  
Using a constant reference in the peak current control can cause rapid duty cycle changes, leading to subharmonic frequencies in the inductor current; see Figure 5. These frequencies negatively impact EMC and generate audible vibrations. To mitigate this, a ramp with a negative slope is added to the reference value; see Figure 7[15,18]. Figure 5: MOSFET driver configuration. Figure 6: Principle of peak current control. The condition of the system stability is that if the reference value corresponds to the required current amplitude, then the steepness of the ramp \(m\) in the steady state must be greater than half the difference between the steepness of the fall \(d\) and rise \(u\) of the inductor current \(I\), as shown in Equation (15) [26]. \[m>\frac{1}{2}(d-u) \tag{15}\]  
By substituting the general calculation of the output voltage of the buck converter, the calculation of the minimum steepness of the ramp in Equation (16) can be performed. The steepness of the converter ramp is at least 750 kA/s, which transforms to 6.25 mA/cycle at 120 MHz clock frequency. The ramp drop in one period is, therefore, 1.875 A to prevent the generation of subharmonics. \[m>\frac{U_{in}}{2\cdot L} \tag{16}\]  
If any error occurs, it is necessary to turn off the transistor in the upper branch of the converter to prevent overvoltage in the converter's output. Also, transition events occur during the changing of the conductivity of transistors, which generates overshoots in the current waveform, which can exceed the reference value and cause an undesirable transistor turn-off. According to this, it is necessary to implement a blanking window. However, this leads to minimizing the value of the minimum duty. When controlling the interleaved buck converter in the peak current in the current source mode, creating two separate synchronized systems, each for one branch of the converter, is necessary. The input of such a system is the instantaneous current of the given converter branch. The output is a complementary PWM signal. Separate MCU modules control the individual branches of the inverter with a phase shift of 180\({}^{\circ}\). The base frequency of the processor is 120 MHz. To create a time base with a converter frequency of 400 kHz, the counter in UP counter mode resets every 300 processor cycles. After reset, the time base of the first branch generates a synchronization pulse for the time base of the second branch. Figure 7: The theory of the ramp effect. Figure 8 defines the basic parameters of the waveform of the inverter working cycle: \(T_{pos}\) is the period of a positive impulse, and \(T_{neg}\) is the period of a negative impulse; the duration of these periods is independent. \(t_{pos,imp}\) is the duration of a positive pulse, and \(t_{neg,imp}\) is the duration of a negative pulse. Next, we can introduce \(N_{pos}\) and \(N_{neg}\) as the number of positive and negative pulses in one cycle. The duration of one cycle can be expressed according to Equation (18). Specific timing parameters will be the subject of further extensive research, and the results will be published later.