# Radiation-Hardened 16T SRAM Cell with Improved Read and Write Stability for Space Applications
###### Abstract
For example, the NMOS stack-based NS10T can recover from a '0'-\(\rightarrow\)'1 SEU occurring at the '0'-storing node but cannot recover from a '1'-\(\rightarrow\)0' SEU occurring at the '1'-storing node. Moreover, the PMOS stack-based PS10T has a recovery capability only for a '1'-\(\rightarrow\)0' SEU occurring at the '1'-storing node. [PERSON] et al. proposed the 12T structure DICE, which has recovery capability for all types of SEUs [16]. DICE can recover to its initial state using positive feedback when an SEU occurs due to an ion strike at any sensitive node. Therefore, DICE has recovery capability from SEUs induced at all sensitive nodes but lacks recovery capability for SEUMNUs. [PERSON] et al. proposed two radiation-hardened SRAM cells, QUCCE10T and QUCCE12T, with recovery capabilities from SEUs. However, QUCCE10T and QUCCE12T have issues with read stability. Additionally, both cells cannot recover from a '0'-\(\rightarrow\)1' SEU if sufficient charge accumulates at the \"0\"-storing node. [PERSON] et al. proposed the RHBD10T structure with improved write and read delays [17]. However, RHBD10T does not have improved SEU tolerance, and none of the aforementioned cells have the capability to recover to their initial state from multi-node upsets. To overcome SEMNUs, [PERSON] et al. proposed the RHD12T, which has recovery capabilities from multi-node upsets occurring at internal node pairs [18]. However, RHD12T cannot recover from a '0'-\(\rightarrow\)'1' SEU occurring at the '0'-storing storage node. To address this issue, [PERSON] et al. proposed the RSP14T [19]. While RSP14T can recover from SEUs occurring at the '0'-storing storage node, it still cannot recover from a '0'-\(\rightarrow\)'1' SEU if sufficient charge accumulates at the '0'-storing storage node. Consequently, both RHD12T and RSP14T show reduced read stability because the '0'-storing storage node is directly connected to the bit line through the access transistor during read operations. [PERSON] et al. proposed the RHBD14T, which has recovery capabilities from multi-node upsets occurring at storage node pairs [20]. However, RHBD14T is more vulnerable to SEMNUs because all storage nodes and internal nodes are sensitive nodes. Additionally, RHBD14T uses more PMOS transistors, which are generally known to have higher parasitic bipolar amplification compared to NMOS transistors [21]. Therefore, the increased number of PMOS transistors in RHBD14T can promote charge sharing effects among PMOS transistors [22]. [PERSON] et al. proposed the RHPD14T, which has recovery capabilities from multi-node upsets occurring at storage node pairs [23]. However, RHPD14T shows reduced read stability because both pairs of access transistors are accessed during read operations, directly connecting the storage node to the bit line. Therefore, it is necessary to design the SRAM cell that can recover from SEUs, demonstrate satisfactory performance in both read and write operations, and recover from multi-node upsets caused by charge-sharing effects. In this paper, we propose a radiation-hardened high-stability 16T (RHHS16T) SRAM cell. The proposed cell demonstrates high immunity to SEUs at all sensitive nodes and can recover from multi-node upsets occurring at storage node pairs. Furthermore, the proposed cell shows the highest read stability among all comparison cells while also showing the highest write stability and the shortest write access time. The structure of the paper is as follows: Section 2 describes the basic operation of the proposed RHHS16T cell and its SEU recovery operation. Section 3 presents the measurement results of read delay, write delay, word line write trip voltage (WWTV), read static noise margin (RSNM), hold power, and critical charge for the proposed cell and all comparison cells. Finally, the paper concludes in Section 4.