## 3 The Timepix3 Radiation Monitor
### Setup Description  
The Timepix3 Radiation Monitor setup has been conceptually designed into the following three parts: (i) the detector module hosting the Timepix3 chip and sensor, operating in the radiation field to be measured, (ii) the front-end crate, designed as radiation tolerant in order to operate in the proximity (about 5 m away) of the detector module, and (iii) back-end crate, the data acquisition computer and the power supplies, to be placed far enough from the measurement area to be considered safe for electronics and/or human operation.  
The full block diagram of the setup is presented in Figure 2. The Timepix3 detector module hosts the Timepix3 hybrid pixel detector mounted on a dedicated board and the power regulators for its operation (2 \(\times\) FAESTMP 1.5 V). The board can be powered by a single 8V (5-12V) power supply, and the expected current consumption at this voltage is about 190 mA. For the data (control) signal transmission, the Timepix3 chip uses 8 (10) Low-Voltage Differential Signaling (LVDS) lines, which are routed on the carrier board directly from the chip to six RJ-45 connectors at the front panel of the detector module. To ensure the proper signal quality, category 6a Ethernet cables (double-shielded) are used for the connections between the detector module and the front-end crate. The module has a dedicated detector power supply input, which is a LEMO 00-type connector, located at the front panel. The required power supply depends on the detector type as follows: for the 300 \(\upmu\)m p-in-n type detector, a 50 V supply is used, leading to a partial depletion of the silicon sensor. The expected current consumption depends on the detector illumination and temperature, but it should not exceed several mA at 50 V (with the detector covered, it oscillates around 0.1 \(\upmu\)A).  
The front-end system consists of a single metal crate, responsible for interfacing with the Timepix3 detector module and for the data transmission to the back-end system through optical fibres. Both front-end and back-end use LC-type SFP transceivers. Single-mode optical fibres are used. The front-end system uses FEASTMP power regulators with the allowable input voltage range between 5 V and 12 V. An 8 V power supply with at least 30 W of output power is used, as the expected current consumption at this voltage is roughly 2 A, but can slightly increase for prolonged usage.  
The main element of the back-end system is the VC707 development board from Xilinx, hosting the Virtex-7 FPGA. An FMC mezzanine with ten optical fibre transceivers (SFP) is attached to the board and is used for communication with the front-end system. The transceivers' output power is sufficient to operate at distances up to 10 km, but when (as in most cases) the distance is substantially lower, the receivers at the front-end side are saturated since the signal from the front-end does not face enough attenuation. For this reason, attenuators in the range of 3-5 dB are attached to two of the transceivers, where the signal is transmitted in the direction of the front-end crate. A dedicated firmware was written for the back-end FPGA, implementing the necessary procedures for the data retrieval from the front-end system and interfacing with the control PC. The power delivery to the system is realized via a dedicated 12 V AC/DC power converter. The Ethernet interface is used for device communication with the host PC. The readout and processing software on the host PC are based on the PANDA Graphical User Interface (GUI), allowing the setting of the operational parameters as well as data acquisition.