# FPGA-Based Methodology for Detecting Positional Accuracy Degradation in Industrial Robots
## 2 Materials and Methods
### Positional Accuracy Degradation FPGA Implementation
#### 2.6.3 Neural Network Soft-Core FPGA Module  
The neural network soft-core module performs the process of a trained network for classification; a description of its components is provided below. Figure 14a shows the general diagram of a simple perceptron.  
It is composed of a multiplier where input \(x_{i}\) is multiplied by the weights \(w_{ij}\), where \(i\) represents the input number, and \(j\) is the weight number. A register accumulates the result, and the bias \(b_{j}\) is added. Afterward, the operation result is saturated to maintain the required bit size, and the activation function, contained in a look-up table (LUT), is continued. Finally, the output is delivered via \(y_{i}\).  
Figure 14b shows a general diagram of a set of perceptrons composing a neural network layer. This module comprises different blocks: a block of weights, a block of counters, FMS, bias, and an activation function. The block of weights contains the weights \(w_{MN}\) corresponding to neuron M and N number of neurons in the layer. Furthermore, the counters block counts the number of neurons and their corresponding weights. The bias block contains the biases for M neurons. Additionally, the activation function block performs the procedure described above in the perceptron, and the FMS directs the entire layer process. Signal STR indicates the start of the calculation, RD and WR are signals for  
Figure 14: (**a**) Architecture diagram of a simple perceptron. (**b**) Diagram of neural layer core. (**c**) Neural network layer architecture diagram.  
reading and writing data in memory, and the RDY signal indicates that the calculation is complete. Figure 14c presents the general diagram of the classifier based on neural networks. In this network configuration, an input layer stores the data \(\text{x}_{\text{N}}\) that the network will evaluate in the FIFO 0 register through the Din input and the WR signal to control write enable in memory. The process starts when the STR signal is high, and the \(\text{x}_{\text{i}}\) samples enter the structure presented in Figure 14b through the RD signal. Moreover, the hidden layer's output is stored in FIFO 1 register by the signal WR. Once all the samples are complete, the RDY signal goes high and activates the next layer. The output layer of the network receives the data stored in FIFO 1 and performs the same process as mentioned in the hidden layer. The layer's output is stored in the FIFO 2 register as the input data is processed. These are accessible when the output layer RDY signal is high and are readable by [PERSON] and the RD control signal. Weights and biases of the hidden and output layers and the activation functions are stored in the device's RAM. Neural network configuration consists of an input layer with eight inputs, a hidden layer of 16 neurons, and an output layer with two outputs; the activation functions are sigmoid. Neural network training was carried out in software independently, and the values of weights and bias were stored for use in the FPGA device.