# Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM
## 5 Conclusion and Future Work  
We have developed an adaptive fault-tolerance (AFT) mechanism based on ECC codes to tolerate intermittent faults in RAM. The AFT mechanism is able to detect variations in the error condition and then change its internal configuration to adapt to a new fault hypothesis.  
We have implemented a first version that employs two ([39; 32]) codes, an SEC-DED and an EPB3932 (able to correct all single errors, as well as double and triple adjacent errors that contain a bit which is suspect to have a higher probability of being erroneous because it has already been erroneous for a number of times).  
When an \"error monitor\" detects that a particular bit is repeatedly erroneous, it is marked as \"error-prone\" (i.e., suspect to be suffering an intermittent fault) and switches to the EPB3932 code, thus covering future errors in that bit, as well as other errors.  
We have designed this AFT mechanism in VHDL and integrated it into the memory controller of a 32-bit RISC microprocessor. We have stressed the system injecting single/multiple, random/adjacent, transient/intermittent, and combinations of intermittent and transient faults. From the injection experiments, we can see that the proposed AFT mechanism can detect transient faults, correct them and, in case an intermittent fault is detected, it is able to change the ECC to adapt to the new fault hypothesis.  
We also analyzed the overhead introduced by the AFT mechanism proposed. From the analysis, we can assert that the overhead introduced, if synthesized in a reconfigurable FPGA, is affordable in terms of hardware and temporal overhead and power consumption. If synthesized in a non-reconfigurable FPGA, though, the proposed model introduces a hardware overhead that could be affordable.  
For future work, we intend to implement both versions of the AFT mechanism in FPGA in order to inject faults to calculate their real coverages and latencies. In addition, we are developing other design alternatives studying new ECCs to be incorporated in the AFT mechanism. Another future work line is to design adaptive fault-tolerance mechanisms for other CPU elements, like the register bank.  
**Author Contributions:** Conceptualization, [PERSON]-C.B.-C. and [PERSON]-J.G.-V.; data curation, [PERSON]-C.B.-C.; formal analysis, [PERSON]-C.B.-C.; funding acquisition, [PERSON]-[PERSON] and [PERSON]-[PERSON]; investigation, [PERSON]; methodology, [PERSON]-[PERSON] and [PERSON]; project administration, [PERSON] and [PERSON]; resources, [PERSON]-[PERSON]-C.; software, [PERSON]-[PERSON]-C., [PERSON] and [PERSON]; supervision, [PERSON] and [PERSON]; validation, [PERSON]-[PERSON]-C.; visualization, [PERSON]-C.B.-C.; writing--original draft, [PERSON]-[PERSON]-C.; writing--review and editing, [PERSON], [PERSON], [PERSON] and [PERSON]. All authors have read and agreed to the published version of the manuscript.  
**Funding:** This research was supported in part by the Spanish Government, project TIN2016-81,075-R, and by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), project 20190032.  
**Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.