# A Survey of Analog-to-Digital Converters for Operation under Radiation Environments
## 4 Data Analysis
### Architectures and Applications  
Five architectures can be found among the _selection_: \(\Delta\Sigma\), SAR (successive approximation register), PIP (pipelined), F (flash), and FIF (folded interpolated flash). We have illustrated this diversity by discerning data by architecture in Figures 2-8 (cf. legends). Additionally, we have denoted surmised architectures with a question mark in column 'Arc.' of Table 1. As a briefing, we have collected in Table 3 the number of specimens, the ranges of ENOB, \(f_{s}\) and FOM\({}_{W}\), and the average FOM\({}_{TID}\) and FOM\({}_{SET}\) for each architecture. Flash was dismissed from Table 3, since only one specimen uses this architecture among the _selection_. ADC architectures are similarly distributed along frequency and resolution either the target application operates under radiation or not: \(\Delta\Sigma\) ADCs target low-frequencies high-resolution applications, SAR do low/medium-frequencies medium/high-resolution, PIP do medium/high-frequencies moderate-resolution, and FIF do high-frequencies low-resolution. Radiation hardening can be enhanced at the expense of area and power consumption by including additional blocks (triple redundancy, anti-glitches, anti-bubbles, SEL and/or SEFI watch-dogs, digital error correction, etc.). On the other hand, selecting specific circuit structures for the composing blocks of the randenv-ADC can also enhance its radiation performance without significant impact in area or power consumption (i.e., using auto zeroing comparators against SET). The PIP architecture presents the best \(\overline{FOM}_{TID}\) and \(\overline{FOM}_{SET}\) within the _selection_ (cf. Table 3). In fact, PIP is the preferred architecture for hardened ADCs, with 21 specimens among the _selection_. SAR is also well represented, but it has more COTS among its population (7/19 versus 3/21 for PIP), and worst \(\overline{FOM}_{TID}\) and \(\overline{FOM}_{SET}\). Latency is a major concern for some ADC applications. As a rule of thumb, we can arrange architectures in the following order, from shorter to longer latency: flash \(<\) FIF \(<\) PIP \(<\) SAR \(<\)\(\Delta\Sigma\). Additionally, some ADC applications recur to down-sampling to extend the analogue bandwidth to be digitized; this technique has being lately the tendency in satellite communications where digital down-conversion of L- and S-bands signals relaxes the requirements of the RF front end. On the other hand, the inherent loop filter of \(\Delta\Sigma\) architectures provides an intrinsic anti-aliasing feature that can save additional filtering stages at system level. In addition, the intrinsic oversampling feature of \(\Delta\Sigma\) ADCs can be seen as a redundancy spread in time [79]. Considering the virtues and drawbacks of each architecture briefly discussed in this section, in Table 4 we have linked the more recurrent applications in radiation environments with their most suitable ADC architectures; a higher suitability is emphasized with a double check mark instead of a single one. We can consider SAR the most versatile architecture since it fits in almost all the considered applications. Depending on the target application, some soft error test methods (cf. Table 2) could be more adequate than others. In Table 5, we present our recommendations according to the following criteria: test methods 1P or S are dismissed due to their reduced monitoring of output codes; QS is perfect for slow high-resolution applications; DAC method is discarded for long latency and/or very high resolution applications; the other test methods are similar, and can all fit for medium/high-speed applications.