# Vertical GaN MOSFET Power Devices
## 2 GaN Power Devices
Lastly, the absence of avalanche capability in lateral GaN devices, possibly due to the lack of a p-n junction between the drain and source regions, which aids in hole extraction during impact ionization, poses challenges in preventing the device from short-term overvoltage failure [39]. To address the limitations of lateral GaN devices, there has been a growing exploration and investigation of vertical GaN devices. The primary distinction between vertical and  
Figure 2: The schematic structures of (**a**) a lateral GaN device and (**b**) a vertical GaN device. lateral devices lies in the direction of current flow, as illustrated in Figure 2 with a red arrow for both types. In a vertical device, current flows vertically from the bottom to the top surface (with electrons carrying the current from top to bottom) or in parallel with the direction of the GaN epitaxial layers. Consequently, current conduction occurs through the surface channel and then through a bulk drain drift region formed by a homoepitaxial GaN layer on a GaN substrate. Unlike lateral devices, vertical devices do not have a 2 DEG drain drift region near the surface or a defect-rich buffer layer, as found in GaN HEMTs. As a result, there is less degradation in dynamic \(R_{\text{ON}}\), which often occurs due to trapped impurity charges or bulk traps resulting from lattice mismatch [40]. One of the most significant advantages of vertical devices over lateral ones is their \(V_{BD}\). The \(V_{BD}\) of a vertical device can be increased by augmenting the thickness of the N-drift layer, which is typically a low-doped or unintentionally doped GaN epitaxial layer (also known as the GaN N-drift layer). Consequently, this makes the \(V_{BD}\) independent of the lateral size of the device. Moreover, a vertical GaN device can achieve a \(V_{TH}\) ranging from around 5 to 15 V, making it well suited for high-power applications [41]. Another advantage of vertical GaN devices is their ability to exhibit avalanche breakdown, enhancing device reliability and potentially eliminating the need for overdesigning the device [42; 43; 44]. During transients, avalanche breakdown serves as a failsafe operation, allowing the device to operate closer to its material limits [45]. The \(V_{BD}\) of a vertical GaN device can be significantly higher because the drain is located at the bottom of the device. When a high voltage is applied at the terminal, the electric field is evenly distributed throughout the device in a vertical direction, unlike lateral devices that experience electric field spikes at the gate edge [46]. This even distribution of the electric field within the device, away from the surface, can mitigate the effects of current collapse by countering the influence of surface states and thus slowing down the occurrence of current collapse [47; 48]. Vertical GaN devices also offer the advantage of easily increasing power density. Since there are no electric field spikes, unlike lateral devices, there is no need for the field plate structure, which typically increases gate leakage spacing, to enhance breakdown performance. This makes it simpler to improve wafer utilization and boost power density [49]. The nFET operation of the vertical device is controlled by two primary p-n junctions, forming gate-source and gate-drain diodes. Avalanche breakdown occurs when the drain-source voltage of the device exceeds its \(V_{BD}\). Initially, avalanche breakdown occurs through the reverse-biased drain-gate diode region, leading to an increase in the gate-source voltage and the opening of the channel region. Unlike lateral GaN devices, avalanche breakdown in vertical devices remains within the short-term power dissipation limits. Furthermore, energy dissipation occurs within the drift region of the device rather than on the surface (a sensitive region). This feature helps protect the device from transient spikes and other abnormal operating conditions.