## 2 Model Presentation
### Delay Model  
An ultra-compact cell delay model for cell library characterization is given in [10], using effective current, as follows:  
\[T_{d}=k_{d}\frac{\Delta Q}{I_{eff}} \tag{16}\]  
Variations in input slew \(S_{in}\), output load capacitance \(C_{load}\) and supply voltage \(V_{dd}\) have been taken into consideration in [10]. We validated the delay model with different sets of values for \(\{S_{in},C_{load},V_{dd}\}\). The simple metric cannot follow the experimental inverter delay for partial input sets. To achieve a better fit, the delay model is modified as  
\[T_{d}=k_{d}\frac{CV}{I_{eff}}+\beta S_{in} \tag{17}\]  
where \(k_{d}\) is a scaling factor for a good fit to \(T_{d}\) versus \(CV/I_{eff}\), a linear coefficient \(\beta\) is introduced to compensate for the impact of \(S_{in}\) on delay. The inverter delay (\(T_{d}\)) and output slew (\(S_{out}\)) are modeled using the same format as in (17), with different values for the fitting parameters. The model is generic for any combinatorial logic cell that can be equated to an inverter [10]. On-state current \(I_{ON}(V_{GS}=V_{DS}=V_{dd})\) is used in [19] to represent the effective current \(I_{eff}\). Reference [20] replaces the on-state current with \(I_{eff}=(I_{H}+I_{L})/2\) where \(I_{H}=I_{DS}(V_{GS}=V_{dd},V_{DS}=0.5V_{dd})\), \(I_{L}=I_{DS}(V_{GS}=0.5V_{dd},V_{DS}=V_{dd})\). [21] proposes \(I_{eff}=(I_{H}+I_{M}+I_{L})/3\) as a correlation, where \(I_{M}=I_{DS}(V_{GS}=0.75V_{dd},V_{DS}=0.75V_{dd})\). We extracted the fitting parameters of (17) with effective currents in [20,21], respectively. The one in [20] better follows the experimental delay; thus, we adopted \(I_{eff}=(I_{H}+I_{L})/2\) for the delay model. Note that the simple form of (17) facilitates the implementation of a process-variation-aware delay model, which establishes a direct link between underlying process parameters and delays. The distribution process parameters discussed in this paper are given with nominal values in Table 3.  
With the introduction of the ultra-compact delay model and the effective current, a process variation-aware delay model can be implemented by combining the delay model with the proposed analytical current model. The expression for the cell delay with respect to the process parameters is given as follows:  
\[T_{d}=k_{d}\frac{CV}{I_{eff}(\mathbf{P},\mathbf{V_{i}},\mathbf{M})}+\beta S_{ in} \tag{18}\]  
where \(\mathbf{P}\) is the variable space spanned by process parameters in, \(\mathbf{V_{i}}\) is the variable space composed of the intrinsic node voltages \(\{V_{DI},V_{SI},V_{FGI},V_{BGI}\}\), and \(\mathbf{M}\) represents the space of other model parameters. The derivatives of the effective current with respect to the process parameters are required for the delay prediction model presented later. However, the presence of series resistance affects intrinsic node voltages when the process parameters vary. Consequently, the impact of series resistance needs to be considered. The current expression when considering series resistance satisfies the equations:  
\[\left\{ \begin{array}{l}I_{DS}=f_{I_{DS}}(\mathbf{P},\mathbf{V_{i}},\mathbf{ M})\\ I_{DS}\cdot Rsd=V_{D}-V_{Di}\end{array} \right. \tag{19}\]  
where \(Rsd\) is the series resistance at the source and drain ends, \(\mathbf{V}\) is the variable space consisting of the external node voltages \(\{V_{D},V_{S},V_{FG},V_{BG}\}\). Due to the symmetry of the current model, \(V_{DI}\) can be used as an independent variable in \(\mathbf{V_{i}}\) while other variables in \(\mathbf{V_{i}}\) can be expressed by \(V_{DI}\) or variables in \(\mathbf{V}\). \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameter** & **Description** & **NMOS** & **PMOS** \\ \hline L & Channel length & 26 nm & 24 nm \\ W & Channel width & 80 nm & 80 nm \\ TOX1 & Front gate oxide thickness & 1.33 nm & 1.48 nm \\ TOX2 & Back gate oxide thickness & 20 nm & 20 nm \\ TSI & Silicon body thickness & 6 nm & 6 nm \\ PHIG1 & Work function of the front gate & 4.45 eV & 4.71 eV \\ \hline \hline \end{tabular}
\end{table}