# A Dual Stage Low Power Converter Driving for Piezoelectric Actuator Applied in Micro Mobile Robot
## 5 Experiment Realization
### Circuit Experimental Analyses  
A low-voltage source lithium battery is utilized to generate high drive voltage in the developed topology. The input voltage \(V_{bat}\) of the dual-stage drive circuit is 3.7 V, and the output voltage \(V_{o}\) is regulated at 100 V. One layer of the bimorph actuator can be modeled as a 48 nF capacitor in parallel with a few megaohm resistance. Multiple actuators are cascaded to increase load condition in circuit validation. The dual-stage converter is capable of driving capacitive loads at nanofarad level, with up to 0.5 W (full load) unipolar actuation.  
In the DC/DC stage, the node waveforms of \(V_{gs}\) (driven gate voltage), \(V_{ds}\), and \(I_{p}\) were obtained, as shown in Figure 12. The \(I_{p}\) current is fully provided by the lithium battery. The waveforms are consistent with the theoretical analysis. The maximum instantaneous output power of the lithium battery can reach four watts. The zero current shows that the flyback circuit worked in DCM mode.  
This circuit topology is capable of generating three waveforms (i.e., square, triangle, and sinusoidal waveforms; Figure 13). An oscilloscope probe is used five and ten times to measure a voltage of 100 V.  
Figure 11: Image of the fabricated converter.  
Figure 12: Node waveforms of the flyback converter.  
Figure 14 shows the output waveforms of the three signals and the corresponding control pulses of the two power MOSFETs. When the sinusoidal signal is used as an example, the timing pulses are turned on and the high-side transistor Q\({}_{\rm H}\) is constantly switched during the Charge phase, thereby initiating the transfer of energy to node \(V_{o}\). During the Discharge phase, the low-side transistor Q\({}_{\rm L}\) is turned on and the high-side transistor Q\({}_{\rm H}\) is turned off, thereby lowering voltage \(V_{o}\). As shown in the enlarged view, the switch is only turned on when the capacitor is required to reach the ideal voltage, thereby avoiding unnecessary switching actions and significantly reducing switching loss.  
Figure 13: Output voltages of each node (i.e., \(V_{\rm bat}\), \(V_{c}\) and \(V_{o}\)) in (a) square driving; (b) triangle driving; and (c) sinusoidal driving modes.  
The proposed converter's conversion efficiency can be calculated as follows:  
\[\eta=\frac{P_{load}}{P_{in}}\times 100\%, \tag{12}\]  
where \(P_{load}\) is the average power of the PZT load, and \(P_{in}\) is the average input power of the developed converter.  
Figure 15 demonstrates the efficiency of the proposed interface in terms of various loads and drive signal frequencies.  
Figure 14: Images of the control pulses and output waveforms.  
Figure 15: Efficiency vs. load for the three different driving frequencies.  
The loads continuously increase from 10% to 100% with 10% intervals. The three driving frequencies are 100, 110, and 120 Hz. The peak efficiency (64.5%) can be reached at 60% load and 100 Hz driving frequency (Figure 14), which is higher than the maximum conversion efficiency of 42.4% obtained in [9]. Table 4 outlines the electrical characteristics of the proposed drive circuit.