# Efficient FPGA Implementation of an ANN-Based Demapper Using Cross-Layer Analysis
## 4 Hardware Implementation
### Cross-Layer Exploration Framework  
One of the primary goals of our hardware design is to provide high flexibility, which allows to jointly partition the resources used for inference and training module depending on the environmental conditions (e.g., channel fluctuations) and requirements of the application (e.g., latency, throughput). For example, the frequency of channel variations might increase, therefore faster convergence for the retraining of the network is needed, and the latency of the training module needs to be decreased by utilizing more resources, either through partial reconfiguration or reloading of the bitstream. Theoretically, the reconfiguration of the inference module could even be accomplished without any downtime of the communication by temporally using the resources of the training module as follows:  
1. Initial configuration: initial inference module, initial training module;
2. Temporal configuration: initial inference module, new inference module;
3. New configuration: initial training module, new inference module.  
To fully exploit the potential of our architecture and to bridge the gap between the communication layer and the hardware layer, we propose a framework that can be executed on the PS of the FPGA to automatically calculate the optimal DOP for inference and training module for requirements such as inference latency or convergence latency for a specific target BER. The pseudo-code implemented in the framework to determine the DOPs is given in Algorithm 1, where \(\mathit{Reg}(x)\) is defined by the application requirements, and \(\mathit{Res}(x)\) of the inference and training module for the different DOPs is obtained by extracting the implementation results for the different configurations from Vivado after place and route.  
The objective can either be hardware-related, e.g., minimize power or even take the communication layer into account, e.g., minimize inference latency while satisfying convergence latency requirements for a target BER and an estimated SNR. The algorithm calculates the ideal DOPs by first satisfying the application requirements and afterward optimizing for the given objective under consideration of the available resources given by the hardware constraints.  
Using this algorithm, the framework can load the bitstream corresponding to the calculated parallelization degrees during runtime to adapt to the changing requirements.  
A sample configuration of the framework for the proposed AE is given in Figure 7.  
The framework receives as inputs:  
* The objective, e.g., min. inference latency, min. convergence latency, min. inference power or min. training power;
* Application requirements in form of latency and power demands and, optionally, a target BER for an estimated SNR;
* Hardware constraints based on the available resources of the target platform.  
The outputs of the framework are the DOPs for the inference and training module that are optimized for the given objective and satisfy the application requirements.  
To link the communication-related metrics such as SNR and BER to actual properties of the underlying hardware, the framework internally accesses a database of pre-evaluated characteristics of the hardware modules. Those characteristics include hardware-related properties, such as resource usage, latency and power, as well as a link to the communication layer by mapping different DOPs to convergence times and SNRs, which is further described in Section 5.5.  
This way, our design provides two different levels of flexibility:  
1. Environmental Adaption: The receiver can be fine-tuned to compensate variations of the communication channel by retraining the ANN;
2. Requirement Adaption: The FPGA can be reconfigured to satisfy changing application requirements by adapting the DOP of inference and training module.