# A High-Gain CNTFET-Based LNA Developed Using a Compact Design-Oriented Device Model
## 4 LNA Design
### DC Bias Design Procedure and Optimization  
Due to the separability property of the functional dependence of the drain current with respect to the gate and drain voltages, biasing of the circuit is quite straightforward, and the overall small-signal gain only depends on the input transistor and load, as shown in (15). Nevertheless, the noise performance is indeed influenced by the bias currents and voltages, and so the design can be tailored to optimize such a performance. In particular, from Equation (19), it is apparent that only \(M_{4}\) and \(M_{5}\) make a significant contribution to the output noise, with their noise currents directly flowing into the output conductance (\(g_{\mathrm{o4}}\)). Since the equivalent noise current power spectral density \(\overline{\overline{i_{\mathrm{n}}}}\) of a single transistor is proportional to its drain current:  
\[\overline{\overline{i_{\mathrm{n}}}}\propto I_{\mathrm{D}} \tag{20}\]  
while its transconductance \(g_{\mathrm{m}}\) also depends on gate biasing:  
\[g_{\mathrm{m}}\simeq\frac{I_{\mathrm{D}}}{V_{\mathrm{GS}}-V_{\mathrm{TH}}} \tag{21}\]  
it is possible to optimize \(M_{5}\) for noise performance by maximizing its \(g_{\mathrm{m}}\), while nothing, unfortunately, can be done for the noise added by \(M_{4}\). The noise factor of the input stage, a CS configuration, can thus be computed as:  
\[F=\frac{S_{\mathrm{i}}/N_{\mathrm{i}}}{S_{\mathrm{o}}/N_{\mathrm{o}}}=\frac{ \overline{v_{\mathrm{i}}^{2}}/\overline{v_{\mathrm{n}}^{2}}}{\overline{g_{ \mathrm{m}}^{2}}\,\overline{v_{\mathrm{i}}^{2}}/(\overline{g_{\mathrm{m}}^{2} }\,\overline{v_{\mathrm{n}}^{2}}+\overline{i_{\mathrm{n}}^{2}})}=1+\frac{ \overline{\overline{i_{\mathrm{n}}  
so that it is best to bias the transistor with the lowest possible overdrive voltage, provided that sufficient linearity is retained. Of course, this implies a trade-off with bandwidth, as lower overdrive voltages require larger transistors to sustain the desired drain current. With these considerations in mind, it is possible to proceed with the design optimization after having defined a few constraints that are needed on the node voltages to ensure all transistors are biased in their saturation region. To aid optimization, normalized node voltages are used, i.e., if a node \(n\) must have a voltage \(V_{n}\) constrained so that \(V_{\text{Lr}}<V_{n}<V_{\text{Hr}}\), then we pose \(x_{n}=(V_{n}-V_{\text{Lr}})/(V_{\text{Hr}}-V_{\text{Lr}})\), and the optimizer can (theoretically) explore the whole unitary hypercube \(0\leq x_{n}\leq 1\). To do so, the currents in the left and right branches, \(I_{1}\) and \(I_{2}\), respectively, must also be fixed, but those are usually determined by system-level considerations on the maximum power dissipation of the device. From a noise perspective, the higher the currents, the better. We thus chose to use \(I_{1}=7\,\text{mA}\) and \(I_{2}=2\,\text{mA}\), since the right branch transistors do not contribute much to the total noise of the LNA. To minimize noise, from Equation (23), \(V_{\text{G5}}\) should be as low as possible, which also has the effect of maximizing the transistor \(M_{\text{5}}\) transconductance and hence the gain of the whole amplifier. We thus fixed \(x_{\text{G5}}=0.1\) to allow for some signal excursion without losing linearity. The other transistors can be designed to keep their total size as small as possible, aiding in the frequency response. Since \(g_{\text{m}}\propto W\), transistors widths \(W\) can easily be computed from Equation (21) once the currents and voltages are known, and so a numeric optimizer can be employed. Minimization of the total gate area of the amplifier thus leads to the results shown in Table 1, where the search for internal node bias has been further constrained to the range between 10% and 90% of the possible swing.