## 4 Space-Qualified RF Generator Techniques
### Integrated PLL Design  
The RF generator in which a Phase-Locked-Loop (PLL) design is used, which already has space heritage [21; 25; 26]. The top-level topology of the PLL design in shown in Figure 2. The design uses a reference oscillator (fREF), generating a stable reference signal against which the feedback signal (fDIV) is compared in the Phase-Frequency Detector (PFD). If both signals are out of phase, an error signal is generated by the PFD aligned to the phase difference. This signal is converted by a Low-Pass Filter (LPF) into a voltage level capable of driving the Voltage-Controlled Oscillator (VCO) towards the requested frequency. The \begin{table}
\begin{tabular}{c c c} \hline
**Specific Requirements (Optical Domain Specific)** & **Value** & **Unit** \\ \hline Frequency range (VIS domain) & 60–120 & MHz \\ Power level (VIS domain) & 0.3 & W \\ Frequency range (NIR domain) & 45–90 & MHz \\ Power level (NIR domain) & 0.3 & W \\ Frequency range (UV domain) & 125–250 & MHz \\ Power level (UV domain) & 3 & W \\ \hline \end{tabular}
\end{table} 
Table 2: RF generator specific requirements (depending on the optical domain VIS/NIR/UV). \begin{table}
\begin{tabular}{c c} \hline
**RF Generator Technique** & **Type** \\ \hline Integrated PLL design & Analog \\ DDS inside an FPGA & Digital \\ SSB mixing & Analog \\ DDS and DAC chip repackaging & Digital \\ ASIC & Digital \\ \hline \end{tabular}
\end{table} 
Table 3: RF generator techniques and type classification. latter generates the RF output but also feeds back a divided signal (1/N) to the PFD for comparison. In order to translate this design into a space-qualified setup, the selection of the components has to be carried out in a rigorous way. In Figure 3, the LMX2694 of Texas Instrument (Dallas, Texas, USA) [27] is used as the core of the PLL design. This device has limited space heritage but offers many features. The PLL setup is a fractional N-PLL, using a delta-sigma modulator. The chip houses all the key blocks mentioned in Figure 2. The LMX2694 only needs a reference oscillator of 100 MHz and a 3.3 V power supply, which is common in space designs. The output signal needs additional filtering in order to fulfil the unwanted spectral component suppression requirement of \(<\)\(-\)30 dBc. The LMX2694 uses several internal VCOs, which create the possibility to generate a wide variety of frequencies at the output (f\({}_{\text{OUT}}\)). The internal VCOs operate between 8.1 GHz and 14.7 GHz. By using internal dividers, the frequency is downscaled to a value between 39.3 and 15,100 MHz, which includes the frequency domain 45-250 MHz, applicable for the VIS, NIR, and UV optical range. The chip 'as is' generates harmonics at the output pin, which need further filtering. As an example, the output spectrum of a 100 MHz signal is shown in Figure 4. The results show that especially the third harmonic level needs additional attenuation. The necessary filter design for a third harmonic suppression is less complex than for a second harmonic suppression. Tests also show that the resolution of the device is 1 Hz, which is much more accurate than requested. The output power level of the chip can be varied by changing the output power setting of the chip. The latter can be programmed, using the external microcontroller (Figure 3). The output power level vari  
Figure 3: LMX2694 PLL outline for space applications. Figure 2: PLL principle. In Figure 5, the frequency is varied between 40 and 300 MHz. The internal current setting, which stipulates the output power, can be set at a value between 63 and 0. The results show a variable output power level between \(-\)6 dBm and +5 dBm for the first harmonic. The output power uncertainty is less than 0.01 mW. The power consumption of the chip is around 1 W. The accuracy between 40 and 350 MHz variates between 32 and 115 Hz. The frequency stability is better than 1 Hz, and the stabilization time is less than 5 ms.  
Figure 4: LMX2694 PLL output spectrum at 100 MHz.