# A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Sredes Receiver
## 1 Introduction  
With the data explosion in cloud computing, 5G networking, industrial IoT, and media sharing, the line rate of high-speed serial links has been improved to 56-112 Gb/s, Serializer-Deserializer (Serdes) has become a mainstream communication technology due to its full utilization of channel capacity, fewer device pins and faster transmission speed, while four-pulse amplitude modulation (PAM4) has become a mainstream modulation scheme due to its high spectral efficiency. Benefitting from the development of the CMOS technology, the digital signal process (DSP)-based equalization has become an indispensable component target to compensate for the severe channel attenuation [1]. However, the DSP faces the problems of insufficient compensation ability, massive power consumption, and excessive area occupation. These problems could become more severe as the data rate increases.  
Therefore, how to recover the signal efficiently and quickly is particularly important. The encoding of 4 Pulse Amplitude Modulation (PAM4) for two bits on each symbol is a prominent advantage compared with Not Return to Zero (NRZ). However, compared with NRZ mode, the eye-opening and linearity of data transmission in PAM4 mode are significantly reduced. In order to meet the strict requirements of eye-opening and linearity, a powerful equalizer structure is required [2]. The receiver base of an analog-to-digital converter (ADC) improves this situation nicely [3]. And the fully digital equalizer (feed forward equalizer (FFE), decision feedback equalizer (DFE)) based on ADC has begun to beproposed. However, SerDes receivers have high requirements on the DSP, such as strong equalization capability, low power consumption, and small area [4].  
In this paper, we design a DSP module suitable for ADC+DSP architecture of Serdes receiver, which has high speed, low bit error rate (BER) and other advantages. In this design, least mean square (LMS) algorithm is adopted to provide coefficients to FFE and DFE modules in DSP adaptively, so that the system can balance channels with different attenuations adaptively. In order to reduce the overall power consumption of the system, some optimization is made in the process of implementing LMS algorithm without affecting the overall performance [5]. In this paper, DSP is mainly used to compensate for large channel attenuation (maximum \(-33\) dB). In the implementation process of DSP, the first-order sigma-delta integrator is used to replace the traditional division for average operation, which can optimize the power consumption and area of the system. At the same time, the optimal truncation program would be discussed under the condition of equilibrium intensity and high speed. Besides, the problem of a tense time in traditional DFE was solved by implementing a 1-tap speculative DFE and customized 4-to-1 multiplexer (MUX) unit, and the impact of ADC output width also will be discussed to provide a reference for the design of ADC [6]. Finally, a DSP module with a speed of 100 Gb/s and a maximum attenuation of \(-33\) dB is realized on the 28 nm process node. After silicon test, the BER is \(1\times 10^{-8}\) and the power consumption is 7.22 pJ/bit in a 50 cm channel.  
The rest of the paper is organized into three sections. Section 2 describes the Architecture of DSP. Section 3 covers the Crucial Techniques. Section 4 cover Layout Implementation and Verification Results. The final summary and conclusion are presented in Section 5.