# A Review of Advanced CMOS RF Power Amplifier Architecture Trends for Low Power 5G Wireless Networks
## 3 Advanced RF PA Architecture Comparison  
A summary of up to date advanced CMOS RF PA architectures is presented in Table 1. The latter table contains the main reported emphasized PA parameters, specific to each architecture. A summary of advanced CMOS PA architectures discussed is presented in Table 6. A classic linear CMOS PA is also included as it is the main building block for the intricate topologies. The concluding summary presented in Table 6 is based on more than 75 reviewed advanced PA architecture articles published in 2000-2018 year span, whereas Table 2 through Table 5 present only the latest state of the art papers in each CMOS/BiCMOS process node. Table 6 is organized in a way to compare all discussed architectures by means of emphasizing the main achievable specifications and features as well as pointing out the existing restrictions. The most promising PA architectures for low power cells are reported to be ET/EER, outphasing, DPA and TWA, all of which are suitable to be designed in CMOS process. ET/EER PA architecture can reach operating bandwidths of up to 40 MHz with an efficiency of 17-48%, but has a high level of complexity and additional noise injected from the supply modulator. The outphasing architecture provides bandwidths of up to 40 MHz with an efficiency of 20-60%, but has a low potential of increasing bandwidth. The DPA architecture provides bandwidths of up to 500 MHz with an efficiency of 20-45% and has an inherent back-off power region, where the efficiency doesn't deviate from its highest value. The downside of the DPA architecture its limitations due to the output impedance inverter. TWA provides an outstanding bandwidth of up to 80 GHz and is the only advanced PA architecture that is comparable to that of _III-V_ group semiconductor PAs. Nevertheless, its disadvantages are the large number of inductors (usually more than 4) which increases the occupied area and offers no improvements in efficiency compared to that of basic PA classes. It has also been observed, that CMOS scaling doesn't always lead to an increase in low power RF PA parameters. PAs implemented in 130 nm-180 nm CMOS processes exhibit the highest gain,  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Classic Linear** & \multirow{2}{*}{**CMOS PA**} & \multirow{2}{*}{**CMOS ET/EER PA**} & \multirow{2}{*}{**CMOS**} & \multirow{2}{*}{**CMOS TRA/DA**} \\  & & & & **Outphasing PA** & \\ \hline \multicolumn{5}{c}{**Process(es) and supply voltage reported to exhibit highest PAE**} \\ \hline \multirow{3}{*}{–} & 130 nm–180 nm, & \multirow{3}{*}{150 nm–320 nm, \(V_{\text{DD}}\) \(\sim\) 33 V} & \multirow{3}{*}{\ \begin{tabular}{c} Dependent on the DSP \\ algorithms and \\ wireless standard. \\ \end{tabular}  } & \multirow{3}{*}{–} \\  & & & \multirow{3}{*}{ \begin{tabular}{c} **PA\({}_{\text{average}}\), \(P_{\text{D}}=\text{{P}}_{\text{back-off}}\), \(\ldots\), \(P_{\text{total}}\)** \\ \end{tabular}  } & \multirow{3}{*}{–} \\  & & & & \\ \hline
5–30\% & 20–45\% & 17–48\% & 20–60\% & Same as classic linear \\ \hline \multicolumn{5}{c}{**V\({}_{\text{DD}}\) range**} \\ \hline
2 V–5.5 V & 2.5 V–5.5 V & 2 V–5 V & 1.8 V–3.6 V & 0.66 V–2.8 V \\ \hline \multicolumn{5}{c}{**Operating bandwidth**} \\ \hline \(<\)500 MHz. Can be & \(<\)500 MHz. Can be & \(\leq\)500 MHz. Can be & \(\leq\)40 MHz. The supply regulator forms a bottleneck. & \(\geq\)40 MHz. \\ introducing & \(V_{\text{DD}}\) \(\sim\) 33 V & \(V_{\text{DD}}\) \(\sim\) 33 V & The power combiner forms a bottleneck. & \(\geq\)5 GHz \\ negative feedback. & \multicolumn{5}{c}{**Architecture features**} \\ \hline \hline \multirow{4}{*}{Is the basis for all advanced architectures} & Average PA/EER doesn’t deviate from highest value at input signal power back-off of & Different architecture variations available, PA improvements of up to & Very high PAE due to utilizing & Different architecture variations available, PA nonlinear PAs to form a linear signal; & \begin{tabular}{c} Different architecture \\ variations available. \\ \end{tabular}