# A Tile-Based Multi-Core Hardware Architecture for Lossless Image Compression and Decompression
## 4 Validation and Analysis
### Performance of Proposed System
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Work** & **Technology** & **Resource** & **Frequency (MHz)** & **Throughput (Mpixel/s)** & **Algorithm** \\ \hline
2009 [17] & Spartan-3 & 36k equivalent gates & 21 & 21 & LOCO-I \\
2018 [30] & Virtex-6 XC6 VCX75T & 8354 slices & 51.684 & 51.684 & LOCO-I \\
2021 [14] & Virtex-7 XC7 VX485 & 18.7k LUT & 264 & 263.98 & JPEG-LS \\
2022 [13] & Kintex-7 XC7K70T & 10.25k LUT & 103 & 100 & JPEG-LS \\
2024 [12] & Zynq-7000 XC7Z020 & 1.3k LUT & 108.6 & 43.03 & JPEG-LS \\ Proposed & Zynq-7000 XC7Z045 & 8437 slices & 300 & 480 & - \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Compression performance comparison with existing implementations. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Work** & **Technology** & **Resource** & **Frequency (MHz)** & **Throughput (Mpixel/s)** & **Algorithm** \\ \hline
2002 [31] & - & 20k equivalent gates & - & 7.14 & JPEG-LS \\
2015 [32] & Virtex-6 XC6 VSX315T & 1.4k LUT & 66.66 & 21.07 & JPEG-LS \\
2024 [12] & Zynq-7000 XC7Z020 & 1.1k LUT & 128.5 & 37.02 & JPEG-LS \\ Proposed & Zynq-7000 XC7Z045 & 7422 slices & 400 & 372 & - \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Decompression performance comparison with existing implementations. demonstrated further gains, with a throughput of 37.02 Mpixels/s at 128.5 MHz, utilizing just 789 LUTs. The proposed system, implemented on a Zynq-7000 XC7Z045, significantly outperforms all previous designs. It achieves a throughput of 372 Mpixels/s at 400 MHz, representing an order-of-magnitude improvement over the next best result. In conclusion, the proposed decompression architecture demonstrates a substantial advancement in both speed and efficiency. Our analysis of the performance of the proposed implementation also focuses on throughput, resource utilization, other resources, energy consumption, consistency, the impact of image patterns, and the effect of tile size. * Throughput: Significant improvements were achieved by the proposed architecture. The compression module operates at a clock frequency of 300 MHz, with a maximum throughput of 480 Msubpixel/s. Pipelining is utilized in the implementation, ensuring that runtime throughput is not affected by the data themselves. One compression core processes a subpixel every five clock cycles. Throughput is calculated based on the clock frequency and the number of compression cores. Latency varies depending on the type of pixel data. When run-length coding is applied, latency is 7 clock cycles. When non-coding is applied, latency increases to 11 cycles. When predictive coding is used, latency reaches 25 cycles. Under conditions of full-speed pipelined operation, latency is effectively masked by continuous processing. The execution time is estimated using the throughput and image size. Specifically, the total data size of the image is divided by the throughput to approximate the processing duration. However, the actual processing time is influenced by the content of the image. The decompression module operates at a clock frequency of 400 MHz, achieving a maximum throughput of 372 Msubpixel/s, which is more than three times that of naive implementations. The throughput of the decompression module is influenced by the data, with varying numbers of clock cycles required for processing by different decompression cores. * Resource utilization: The resource utilization of the proposed system is detailed in Table 4. In addition to reporting the overall resource usage of the proposed system, Table 4 provides a comprehensive breakdown of the resource utilization for both the compression and decompression modules. * Other resources: The system effectively minimized memory consumption by employing FIFO for tile buffering and DDR3 SDRAM for tile and parameter storage, optimized for various tile sizes. In total, four AXI-STREAM interfaces with widths of 128 bits, 256 bits, and 512 bits were utilized in both the compression and decompression modules.