# Could We Realize the Fully Flexible System by Real-Time Computing with Thin-Film Transistors? +
## 4 Circuit Design
### The Basic Circuit Unit Design of MLP  
As mentioned in Section 3, input signals that from the flexible pre-processing (FPP) circuit are connected with multiplying circuit of the first layer directly in the form of voltage, where the Gilbert multiplier [25] is applied because of its high linearity. Because the weights of MLP have been trained off-line, it is load beforehand on the differential ports of multipliers from the on-chip memory. That is, once the data is loaded, results of multiplier-accumulator (MAC) in the first layer, which is contained in the differential voltage of the output, can be calculated directly. Without digital clock, the computing circuit's performance has direct correlation with the setting time of the circuit path. As shown in Figure 7, addition in analog circuit is achieved by directly connecting the input nodes, nevertheless, amounts of input nodes would introduce a high voltage output node (\(V\)a or \(V\)b) that causes the input MOS working in the linear region. Therefore, the differential outputs of multiplier are subtracted to obtain single-end output first by current mirror. When considering the complexity of circuit design, ten multipliers with one current mirror to form a processing unit (from \(\text{PU}(1,1)\) to \(\text{PU}(1,m)\)), which is shown in Figure 6. For the dataset MNIST, the dimension of input image is \(28\times 28\), thus the value of m in \(\text{PU}(1,m)\) is \(\frac{28\times 28}{10}=79\). Then, the single-end outputs of multipliers are accumulated to the input  
Figure 5: Gaussian convolution unit in analog signal domain.  
of hidden layer. When considering the tradeoff between power consumption and accuracy, the size of hidden layer is 50, which means that the value of n in \(\mathrm{PU_{n}}\) is 50.  
After the computation in the fully connection layer, intermediate results, or usually called hidden layer, are processed by nonlinear function Sigmoid. As shown in Figure 7, there are two transistors in sigmoid structure, whose grids connect input voltage and differential of drains represent output voltage, which can be written as [21]:  
\[V_{\mathrm{od}}\ =\ I_{\mathrm{ss}}\ \times\ \frac{2\mathrm{R}}{1\ -\ \mathrm{exp} \left(-\frac{2V_{\mathrm{id}}}{\pi V_{\mathrm{T}}}\right)} \tag{8}\]  
where \(V_{\mathrm{id}}\) is the differential input voltage between two gates of transistors, R is the resistance, \(I_{\mathrm{ss}}\) is the tail current, and \(n\), \(V_{\mathrm{T}}\) is the subthreshold-slope parameter and thermal voltage. Then, the signals come into the second MAC, where multiplying unit in the output layer is the same structure with the first one except the parameters of the circuit, for instance, source voltage, resistance value, and breadth length ratio of each transistor and tail current. At last, the computation results are sent to post-processing unit for further application.  
Figure 6: The computation process of multi-layer perception (MLP) based on flexible devices.  
Figure 7: The circuit implementation of multiplier-accumulator (MAC) and Non-linear activation.