## 3 Results
The driven voltage is set to 0.9 V, the equivalent drive resistance is set to 156 \(\Omega\), and the equivalent load capacitance is set to 4.5 pF on 28 nm nodes. The wire length is set to 800 \(\upmu\)m. We build a real three-wire model in the Cadence process, as Figure 4 shows. \begin{table}
\begin{tabular}{c c c c} \hline
**Signal** & **Left Wire/ps** & **Mid Wire/ps** & **Right Wire/ps** \\ \hline (-,-,-) & - & - & - \\ (-,-,-) & - & - & 76.17 \\ (-,-,-) & - & - & 76.17 \\ (-,-,-) & - & 93.7 & - \\ (-,-,-) & - & 72.95 & 56.97 \\ (-,-,-) & - & 110.2 & 95.38 \\ (-,-,-) & - & 93.7 & - \\ (-,-,-) & - & 110.2 & 95.38 \\ (-,-,-) & - & 72.95 & 56.97 \\ (-,-,-) & 76.17 & - & - \\ (-,-,-) & 73.43 & - & 73.43 \\ (-,-,-) & 80.23 & - & 80.23 \\ (-,-,-) & 56.97 & 72.95 & - \\ (-,-,-) & 53.91 & 53.56 & 53.91 \\ (-,-,-) & 60.52 & 93 & 98.63 \\ (-,-,-) & 95.38 & 110.2 & - \\ (-,-,-) & 94.04 & 122.4 & 94.04 \\ (-,-,-) & 98.63 & 93 & 60.52 \\ (-,-,-) & 76.17 & - & - \\ (-,-,-) & 80.23 & - & 80.23 \\ (-,-,-) & 73.43 & - & 73.43 \\ (-,-,-) & 95.38 & 110.2 & - \\ (-,-,-) & 98.63 & 93 & 60.52 \\ (-,-,-) & 94.04 & 122.4 & 94.04 \\ (-,-,-) & 56.97 & 72.95 & - \\ (-,-,-) & 60.52 & 93 & 98.63 \\ (-,-,-) & 53.91 & 53.56 & 53.91 \\ (-,-,-) & - & 93.7 & - \\ (-,-,-) & - & 110.2 & 95.38 \\ (-,-,-,-) & - & 72.95 & 56.97 \\ (-,-,-) & 76.17 & - & - \\ (-,-,-) & 73.43 & - & 73.43 \\ (-,-,-) & 80.23 & - & 80.23 \\ \hline \end{tabular}
\end{table} 
Table 3: Wire delay of 65 nm three-wire coupling model. Figure 4c is the layout and top view of the wire model design. In Figure 4c, INV11, INV12, INV13, INV21, INV22 and INV23 are library standard cells, which are displayed as gray areas located in the space between VSS and VDD. Table 5 shows the three-wire coupling model spice simulation results and real model extraction results on 28 nm nodes. The spice model results are recoded as \"-S\", while the real model results are recoded as \"-R\". \begin{table}
\begin{tabular}{c c c c c c c c c} \hline  & **Original** & **0.9 Spacing** & **0.8 Spacing** & **0.7 Spacing** & **0.6 Spacing** & **0.9 Length** & **0.8 Length** & **0.7 Length** \\ \hline Delay & 124.6 ps & 129.4 ps & 137.1 ps & 146.0 ps & 159.1 ps & 112.0 ps & 101.0 ps & 89.9 ps \\ \hline G6 Delay & 103.0 ps & 107.0 ps & 113.0 ps & 123.0 ps & 135.0 ps & 93.8 ps & 84.4 ps & 75.3 ps \\ \hline G6. Freq & 3.21 GHz & 3.09 GHz & 2.92 GHz & 2.75 GHz & 2.51 GHz & 3.58 GHz & 3.96 GHz & 4.45 GHz \\ \hline G5. Freq & 3.90 GHz & 3.74 GHz & 3.53 GHz & 3.27 GHz & 2.96 GHz & 4.27 GHz & 4.74 GHz & 5.31 GHz \\ \hline B1 rate & 0.000 & 0.069 & 0.136 & 0.223 & 0.303 & 0.070 & 0.136 & 0.223 \\ \hline B2 rate & 0.216 & 0.209 & 0.209 & 0.189 & 0.179 & 0.190 & 0.197 & 0.193 \\ \hline \end{tabular}
\end{table} 
Table 4: SSTC SPICE simulation and bandwidth change on 65 nm node. Figure 4: Real three-wire model realization with INNOVUS: (**a**) is the circuit diagram; (**b**) is the standard cell logic diagram; (**c**) is the layout graph. Table 5 shows that the delay with spice simulation is close to the delay with INNOVUS extraction, which means the three-wire coupling spice model is close to the real circuit model. Additionally, the frequency, error rate and bandwidth are analyzed. From Table 5, the delay can be divided into (874, 701, 494, 334, 236, -). For convenience of description, the delay around 874 ps is called G6 delay, which occurs in the middle line with two different signals changing direction in the side lines, as (\(\uparrow\), \(\downarrow\), \(\uparrow\)). Similarly, the delay around 701 ps is called G5 delay, the delay around 494 ps is called G4 delay, the delay around 334 ps is called G3 delay, the delay around 236 ps is called G2 delay, and the delay around 0 is called G1 delay. With Formula (8), the G6 frequency, denoted as G6. Freq, is 0.457 GHz. Similarly, G5. Freq is 0.570 GHz. If the working frequency is in the range of (G5. Freq, G6. Freq) and not equal to G6. Freq, all situations of G6 delay lead to errors. The system error is denoted as G6 a crosstalk error.