# VLSI-Friendly Filtering Algorithms for Deep Neural Networks
## 2 State of the Art  
Since we are talking mainly about convolutional and capsular neural networks, it is clear that linear convolution is the main operation in their implementation. In general, convolutional layers tend to be the most time-intensive component, often accounting forover half of the total computation time in a typical implementation [16; 17]. The convolution itself is also a time-consuming operation. For this reason, deep neural network builders are looking for and creating efficient ways to minimise convolution computation complexity [11]. Another opportunity to speed up calculations in deep neural networks is by utilising high-performance field-programmable gate arrays (FPGAs) [18; 19; 20; 21; 22; 23; 24; 25; 26; 27; 28; 29; 30; 31; 32; 33], graphics processing units (GPUs) [34; 35; 36; 33], and specialised application-specific integrated circuits (ASICs) [37; 38; 33; 39]. When modern stationary data processing systems possess ample computing power, the design of mobile on-board systems powered by batteries encounters various conflicting factors that hinder peak performance. The conventional approach of parallelising computations to enhance data processing speed increases the data processing unit's size, weight, and power consumption. Consequently, there is a necessity for solutions that effectively leverage computational parallelisation while concurrently optimising hardware costs. Extensive research is being conducted on algorithms and structures for high-performance computing devices intended to process digital signals and images with practical applications in embedded systems. Developing micro-miniature processing units tailored for image processing and recognition in on-board mobile neural networks, known as Tiny ML or Edge AI, is of particular interest. These cutting-edge applications are at the forefront of modern technology. For these reasons, the Tiny ML Summit has been held since 2019, bringing together experts from major companies and universities. The primary focus of this conference is to discuss the potential of transitioning machine learning from high-performance mainframes to small battery-powered signal microprocessors. The Tiny ML concept is continually evolving, driven by the development of dedicated chips designed for these applications. Notably, digital signal processing algorithms are pivotal in the systems under discussion. Over time, numerous algorithms and processor structures have been developed to address the challenges posed by these systems. With a focus on flexibility and versatility, the prevailing approach involves using universal signal microprocessors and FPGAs. However, the high flexibility of the developed processors contradicts a highly efficient implementation. For example, a programmable signal processing unit is flexible, scalable and upgradable but highly inefficient in terms of performance, die area, weight, and power consumption. Therefore, developing ASIC-centric solutions is best suited for portable applications as minimising power consumption, weight, and size of the processing unit in battery-powered systems has become an essential aspect of on-board processing. At the algorithmic level, methods for reducing the above parameters usually focus on minimising the number of arithmetic operations, especially multiplications. In this regard, developing algorithms for performing the main filtering operations, characterised by minimal multiplicative complexity, is an urgent task. So, we again emphasise that convolution calculation is an essential mathematical macro operation in DNNs. And usually (though not always) it is computed using [PERSON]'s minimum filtering algorithm [1; 12; 14; 18; 20; 21; 22; 24; 40; 41; 42]. However, since, as already noted [43], this algorithm can only calculate two adjacent dot products, it is not suitable for all possible situations that can arise in neural networks. For example, [PERSON]'s minimum filtering algorithm is redundant for \(M=3\) and tile size (\(5\times 5\)) or for \(M=5\) and tile size (\(9\times 9\)).