## 6 Hardware Accelerators on Homogeneous Structures
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameter** & **TPU Systolic Array** & **Eyeriss** & **Proposed Model** \\ \hline \multirow{4}{*}{Processing element (PE)} & \multirow{4}{*}{8-bit MAC} & 16-bit MAC with memory & \multirow{2}{*}{16-bit unit, supporting 7 simple} \\  & & block and partial sums & \\  & & accumulator & operations \\ \cline{1-1} \cline{3-4} \multirow{2}{*}{PE memory} & None & 448 KB SRAM + 72 KB & \multirow{2}{*}{21 bits} \\ \cline{1-1} \cline{3-4} \multirow{2}{*}{PE size} & Very small & \multirow{2}{*}{Relatively large} & \multirow{2}{*}{Average} \\ \cline{1-1} \cline{3-4} \multirow{2}{*}{Number of PEs} & A lot of & \multirow{2}{*}{A few} & \multirow{2}{*}{A lot of} \\  & 256 \(\times\) 256 = 65,536 & 12 \(\times\) 14 = 168 & \multirow{2}{*}{depends on the task} \\ \cline{1-1} \cline{3-4} \multirow{2}{*}{Reconfigurable PE} & No & No & Yes \\ \cline{1-1} \cline{3-4} \multirow{2}{*}{A role of homogeneous structure} & Matrix multiplication & \multirow{2}{*}{Matrix multiplication} & \multirow{2}{*}{Complete processing} \\ \cline{1-1} \cline{3-4} \multirow{2}{*}{Dataflow} & Weight-stationary & \multirow{2}{*}{Row-stationary} & \multirow{2}{*}{Hybrid (weight-stationary or no reuse)} \\ \cline{1-1} \cline{3-4} \multirow{2}{*}{Intermediate results storage} & Buffer & Buffer & PEs (inside the environment) \\ \cline{1-1} \cline{3-4} \multirow{2}{*}{Post-processing units (activation, subsampling)} & Dedicated blocks & Dedicated blocks & PEs (inside the environment) \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Comparison of accelerators based on homogeneous structures. Figure 8: Neuron on the proposed RCE architecture. Reprinted from [34], with permission 2021 IEEE. * Improves resource utilization;
* Increases performance by processing multiple signals simultaneously and eliminating reconfiguration time cost;
* Introduces temporary reuse of weights (short-term stationary dataflow). To implement a multi-cycle architecture, a \"1-cycle latch\" operation must be added to the operations set. This is necessary to store intermediate results between segments. A 90 deg signal rotation operation is included in the MAC. The key disadvantage of the proposed segmented architecture is the limitation of the maximum supported layer size. After segmentation, only some parts of the RCE can be used to implement a layer. This is a significant drawback for the first hidden layers of CNNs, which consist of a large number of neurons. To handle this case, an integral operating mode can be used. In this mode, the entire RCE implements only one layer of a NN and the signal is transmitted in one direction. Disadvantages of the mode are the lack of pipelining and need for external control unit to route the input signal and store intermediate results (Figure 10). Timing simulations of the proposed models showed acceptable results [34; 35]. However, one of the operations, sigmoid activation, is computationally difficult in its natural form (Figure 11). As a result, the processing elements and the entire environment become large, complex, and slow. The piecewise linear approximation proposed in [36] partially solves the problem, but the operation remains complicated compared to others. This paper presents centralized and distributed modifications of the sigmoid activation for implementation in the described RCE architecture. Figure 10: RCE in integral mode. Figure 9: Multi-cycle processing of NN in the segmented RCE.