## 2 GaN on SiC HEMTs  
Gallium arsenide (GaAs) and GaN materials are used for NDPA design. The GaN HEMT, with higher breakdown voltage and higher output power, is more suitable for making UWB and high-power amplifiers [28]. The 0.25 um GaN/SiC HEMT process on 4-inch wafers with 100 um SiC substrates was used for this design. In order to provide a reliable operating breakdown voltage at high-drain bias conditions, the process utilizes a source-coupled field plate design. Additionally, this process offers two interconnected metal layers, high-reliability metal-insulator-metal (MIM) capacitors and precision TaN resistors for full monolithic microwave integrated circuit (MMIC) designs. The process employs through-substrate vias for ground connections and provides an optional transistor layout with low-inductance via connections under each source pad. Figure 1 shows two versions of the process; one is ISV (transistor with individual back-via) and the other is OSV (transistor with outside back-via). Since the DA needs a larger ground area for heat dissipation, the ISV structure is chosen for the design, but at the same time, the size of the FET is also increased. Figure 1: Transistor model: (**a**) ISV model, (**b**) OSV model. According to the work manual [29], when the gate width is 0.25 \(\upmu\)m, the saturation output power at 10 GHz is 5 W/mm with V\({}_{\text{d}}\) = 28 V and I\({}_{\text{d}}\) = 100 mA/mm. When the drain bias voltage is at 28 V, the cut-off frequency is 25 GHz, the maximum oscillation frequency is 75 GHz, and the maximum stable gain at 10 GHz is 19.5 dB. A typical transfer curve is shown in Figure 2a with the device exhibiting transconductance with a peak of approximately 180 mS/mm at V\({}_{\text{d}}\) = 28 V and the gate width at 4 \(\times\) 100 \(\upmu\)m. When the drain bias voltage is 28 V and the gate width is 4 \(\times\) 50 \(\upmu\)m, the transconductance is more than doubled to 75 mS/mm. Under the same drain bias voltage, it can be seen that the current of 0.4 \(\upmu\)m gate width is twice as large as that of 0.2 \(\upmu\)m gate width, and it increases with the increase in gate bias voltage. The full I-V curve with 0.4 \(\upmu\)m FETs for the technique is shown in Figure 2b. Figure 2b exhibits well-behaved characteristics and a maximum current density over 325 mA/mm (at V\({}_{\text{g}}\) = 0 V, V\({}_{\text{d}}\) = 28 V). It can be seen that, under the same drain bias voltage, changing the gate voltage greatly changes the output current. The different gate and drain bias voltages of the transistor represent different working states of the power amplifier. When the drain bias voltage is at \(-\)1.5 V, it means that the power amplifier is working in a class AB working state. Compared with the gate bias voltage at \(-\)0.2 V, the efficiency is increased, but the linearity is reduced. It is known that the maximum cut-off frequency of this process is 24.5 GHz. In order to obtain the best matching transistor performance, the large signal parameters of the transistor are obtained. The saturated output power density of the transistor is 5 W/mm, the PAE is 65%, and power gain is 14.1 dB. When the input power of GaN devices is 27 dBm at 10 GHz, the transistor's PAE reaches its maximum, but the gain is severely compressed at this time. The small-signal equivalent circuit of the GaN HEMT device is shown in Figure 3. R\({}_{\text{s}}\), R\({}_{\text{d}}\), and R\({}_{\text{g}}\) represent the source, drain, and gate parasitic resistances, respectively. C\({}_{\text{gs}}\), C\({}_{\text{gd}}\), and C\({}_{\text{ds}}\) represent the capacitance between gate-source, gate-drain, and drain-source, respectively. L\({}_{\text{g}}\), L\({}_{\text{s}}\), and L\({}_{\text{d}}\), respectively, represent the parasitic inductance of leads between gate-source, gate-drain, and drain-source. Through the frequency response characteristics of a single GaN transistor, we can intuitively identify the factors that affect the bandwidth of the amplifier.