# A Software Defined Radio Evaluation Platform for WBAN Systems
## 3 Proposed SDR Evaluation Platform for WBAN Systems
### Hardware Architecture  
In the proposed SDR evaluation platform, the information source generated from the user interface can be transmitted through three different hardware components in a designated sequence. As illustrated in Figure 7, after the information is sent from the user interface, it will be first transmitted \begin{table}
\begin{tabular}{c c c c} \hline \hline  & & **863–870 MHz** & **2360–2400 MHz** \\
**402–405 MHz** & **420–450 MHz** & **902–928 MHz** & **2400–2483.5 MHz** \\  & & **950–958 MHz** & **2400–2483.5 MHz** \\ \hline \multicolumn{4}{c}{**Data Rate (kbps)**} \\ \hline
75.9 & 75.9 & 101.2 & 121.4 \\
151.8 & 151.8 & 202.4 & 242.9 \\
303.6 & 187.5 & 404.8 & 485.7 \\
455.4 & & 607.1 & 971.4 \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Data rate supported on each frequency band. into the protocol stack for frame formation implemented in the MCU. Then, these frames will be authenticated and encoded following the given security scheme of the IEEE 802.15.6 standard on an FPGA. Once the encoding process is done, the encrypted data go into the baseband processing step implemented in an FPGA. Here, the encrypted message will be modulated and filtered through a Square Root Raised Cosine (SRRC) filter under the specified settings. After that, this signal will be passed into an FPGA Mezzanine Cards (FMC) 111 RF board. In this RF module, the digital signal will first be converted into an analog signal and will then be stepped up to the radio frequency for transmission through the antenna. On the receiver side, once the antenna receives the transmitted signal and the signal passes the Low-Noise Amplifier (LNA), it will downconvert the RF signal to a Medium Frequency (MF) of 30.72 MHz to meet the relatively low sampling rate of the Analog to Digital Converter (ADC). After getting the digital signal, the signal will be passed into the Digital Down-Converter (DDC) to shift the MF down to the baseband. Once the baseband signal is obtained, it is passed through a low-pass filter to filter out the harmonic frequencies. The remaining processes are just the inversion of the previous processes. Once the signal is passed through the SRRC filter, which is compatible with the sending end SRRC, it is demodulated in the baseband receiver module. Then, the security scheme applied to FPGA decodes the data and sends it to the protocol stack for de-framing. Finally, the extracted data are sent back to the user interface. The detailed configurations of the proposed evaluation platform are demonstrated in Figure 8. As can be seen from the figure, every individual block is reconfigurable as needed. Once the configuration of a certain block is determined, the corresponding modules will be activated, while other modules that are not utilized will be disabled to reduce the hardware cost of the platform. For example, assume that the security level of a certain communication has been determined to be Level 1, which requires authentication, but not encryption. In this case, the authentication module of the security scheme in the evaluation platform is activated, while the encryption module is disabled. Based on the types of communications, different operating frequencies are distributed. For NB communication, the proposed evaluation platform supports seven RF bands from 400 MHz-2.4 GHz, while it also supports 11 RF bands from 3494.4 MHz-9984.0 MHz for the UWB communications. Meanwhile, even though both NB and UWB utilize BCH as the coding method for the communication, there are still various configurations for them. The proposed platform supports all the configurations for BCH encoding and decoding required by the standard, as demonstrated in the figure. Moreover, there are eight methods of modulation that can be configured in the platform: \(\frac{\pi}{2}\)-DBPSK, \(\frac{\pi}{2}\)-DBPSK, \(\frac{\pi}{4}\)-DQPSK, and GMSK for NB communications and on-off signaling, CP-BPSK, wideband FM,  
Figure 7: Architecture overview of the proposed Software-Defined Radio (SDR) platform.