## 4 Discussion  
In this section, the results obtained for the three previously defined tests will be analyzed and discussed. Following the order of the tests, the results of the steady-state behavior evaluation tests, tests 1 and 2, will be analyzed and discussed first. First, as a naked-eye analysis, the DM shows excellent performance, with the best results of all the models in all the performed tests. This is clearly reflected by the evolution of the converter output voltage and current variables (Figures 5-7). In more detail, compared to IM and RM, Figures 5 and 6 show that DM performs considerably better in both tests for both output variables. In fact, the responses of DM and the real converter (Exp) practically overlap. With respect to the results obtained for IM and RM, it is observed that, in all cases, the output voltages and, therefore, the output currents, are higher than those of the DM and the real converter. These differences, or steady-state errors, are explained by the fact that the IM and RM models do not consider all voltage drops inside the converter due to their non-idealities. Namely, and among others,  
Figure 7: Test 3. Dynamic analysis of the converter output voltage and current for a duty cycle step. (**a**) Real converter, (**b**) developed model (DM), (**c**) ideal model (IM) and (**d**) reference model (RM). internal losses are obtained in the parasitic resistors of electronic switches and other passive components, as well as in the forward voltage drop of across the rectifier diodes. According to the obtained results, and as would be expected, the magnitude of the steady-state error is closely related to the number of simplifications made in the definition of the model. The smaller the number of non-idealities in the model (the greater the simplifications), the greater the steady-state error. This behavior is noticeable in Figures 5 and 6 and is also evident from the statistical analysis of model error for both output variables in Table 3.  
For the correct interpretation of the statistical analysis, it is necessary to consider that both the mean absolute error (MAE) and the root mean square error (RMSE) provide information on absolute, not relative, errors. This makes the behavior of all models appear better for the output current variable than for the output voltage. However, this is due to the different magnitudes, and therefore scales, in Figures 5 and 6. Consequently, to ensure a better appreciation of the magnitude of the error and comparison between models, the mean absolute percentage error (\(MAPE\)) is included (69). The application of this statistic shows that the behavior is the opposite, which is logical: the lower the internal voltage drops for the same input voltage, the higher the current available at the output. \[MAPE=\frac{100\%}{n}\sum_{n=1}^{n}\left|\frac{Real-Model}{Real}\right| \tag{69}\]  
In view of the above, and as expected, the completeness of the DM definition guarantees a close approximation of the actual converter behavior. In the opposite direction, the error rate of RM and IM is closely linked to the number of simplifications adopted, with IM clearly showing a higher deviation. The results of the dynamic response test, test 3, will now be analyzed and discussed. Based on the results obtained for test 3, the dynamic behavior of the output variables for an increasing duty cycle jump (at t = 15.40 s, Figure 7) is characterized by an underdamped response in the real converter, as shown in Figure 7a. This dynamic response is mainly imposed by the second-order low-pass filter at the converter output, while the overshoot, settling time and steady-state value are defined by the effect of the converter's non-idealities. This behavior is also observed in all models, although it should be noted that, in the case of the IM, there is a noticeable overshoot, followed by a long-lasting oscillatory response (Figure 7c). As in tests 1 and 2, the dynamic behavior of the converter is strongly influenced by the effect of the non-idealities considered during the modelling phase.