# A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation
## 4 System Measurement
### Full-Duplex Measurement
For the receiver side, the image frequency is located at 2 \(\times\) IF, which is beyond the working frequency band of the receiver baseband DVGA. The detailed performance of the integrated receiver baseband DVGA is provided in [16], which suggests that the baseband DVGA has a low pass filter response with a stopband suppression better than 50 dB at 2 \(\times\) IF frequency. Furthermore, in the transmitter chain, the differential sub-harmonic modulator, as illustrated in [24], indicates an image rejection of \(-15\) dBc, which together helps to reduce the image signal component. Figure 13: The time domain signal before and after the DSIC: (**a**) the signal captured by the oscilloscope and (**b**) the MATLAB output after the DSIC. The received signal is a combination of the signal received from the wireless channel and the leakage signal from the transmitter. The process technology is the standard BiCMOS process, and the leakage power from the transmitter to the receiver is quite large. Figure 12 shows the measured received signal against the local leakage signal, resulting in an SINR of 12.2 dB, which is not enough for the QAM16 operation. After introducing a digital filter to suppress the leakage signal by 6.7 dB, the system is made operable. The above measurement covers three different working modes: HD, FDD, and FD. Firstly, based on the measurement results, the design satisfies the specification to support the 802.11 ad communication standard at 1.5 m up to MCS12. The transceiver covers the design specifications of 3 m for MCS9, as the power can further increase, and the PA linearity is not an issue for the QPSK-modulated signal. Secondly, the FDD and FD measurements are completed at a 0.8 m communication distance, as the maximum transmitter power is 6 dB lower than that in the HD. Thirdly, the FD is measured at 0.8 m to fulfill the 12 dB SINR before the DSIC processing. The FD baseband data cannot be demodulated directly by using Keysight VSA software without the DSIC. The MATLAB-based DSIC is introduced to suppress the SI, and it achieves a 6.2 dB SINR gain. Table 2 summarizes and compares the measured performance of the proposed design with the state-of-the-art works. As can be seen in Table 2, this work realizes the fully integrated low-power 802.11 ad-compatible RF transceiver with FDD and FD support, which simultaneously achieves 7.04 Gbps and 4 Gbps for both the transmitter and receiver in the FDD and FD modes, respectively. The system can achieve a simulated interference cancellation of 6.7 dB. \begin{table}
\begin{tabular}{c c c c c c c c c} \hline  & **This Work** & **[1]** & **[2]** & **[3]** & **[8]** & **[10]** & **[11]** \\ \hline Process & 180 nm SiGe & 40 nm & 65 nm & 65 nm & 45 nm & & 45 nm \\ technology & & BiCMOS & & CMOS & CMOS & SOI CMOS & – & SOI CMOS \\ \hline Operation & \multirow{2}{*}{HD} & \multirow{2}{*}{FDD} & \multirow{2}{*}{FD} & \multirow{2}{*}{HD} & \multirow{2}{*}{HD} & \multirow{2}{*}{HD} & \multirow{2}{*}{HD} & \multirow{2}{*}{FD} & \multirow{2}{*}{FDD} & \multirow{2}{*}{FDD} \\  & & & & & & & & & \\ \hline SIC Mode & RF & RF & RF + DSIC & – & – & – & & & \\ \hline SIC (dB) & 54 & 54 & 60.7 & – & – & – & 70 & 50 & 60 \\ \hline Silicon Area & \multirow{4}{*}{12 + 12} & \multirow{4}{*}{14 + 14} & \multirow{4}{*}{14 + 14} & \multirow{4}{*}{4.2 + 4.2} & \multirow{4}{*}{5.0 + 5.0} & \multirow{4}{*}{31 + 31} & \multirow{4}{*}{–} \\ RF (mm\({}^{2}\)) & & & & & & & & \\ \hline Antenna & \multirow{4}{*}{2.7} & \multirow{4}{*}{14 + 16} & \multirow{4}{*}{16 + 14} & \multirow{4}{*}{4.2 + 4.2} & \multirow{4}{*}{5.0 + 5.0} & \multirow{4}{*}{31 + 31} & \multirow{4}{*}{–} \\ \cline{1-1} \cline{5-