## 1 Introduction  
Digital filtering is the core of digital signal processing since it is the foundation of the solution to most practical problems in this area: noise reduction [1], amplification and suppression of frequencies [2], interpolation [3], decimation [4], equalization [5] and many others. The tool for digital signal processing is a digital filter (DF), which is usually divided into filters with either finite impulse response (FIR) or infinite impulse response (IIR). In digital circuit design, there is a need to increase device performance. Usually, the two approaches for improving the performance of digital devices are distinguished as pipelining [6] and parallelization [7]. The implementation principle of IIR filters is similar to that of FIR filters in terms of arithmetic units. The difference is the recursive connections, which do not affect system performance in terms of frequency [8]. Therefore, in this article, we will consider the architecture of FIR filters. FIR filters are usually components of complex digital signal processing systems; therefore, FIR filter performance affects the performance of the entire system. For instance, FIR filters were applied to image filtering [9]. In that paper, the authors propose a vectorizing pattern that accelerates FIR filters. The authors of [10] proposed a method of separable two-dimensional FIR filter design to increase device performance. In [11], an adaptive FIR filter was developed and the authors performed a simulation for the various device parameters. The authors of [12] proposed a constant multiplier based on the vertical-horizontal binary common sub-expression elimination algorithm and its application in FIR filter implementation. This multiplication technique allowed for the improvement in area, delay and power consumption of the device. Another way to improve the technical characteristics of FIR filters is the use a residual number system, which allows for parallelization of the computation across multiple channels [13]. The main tool of digital filtering is the multiply-accumulate (MAC) unit [14; 15]. In [16], the authors propose a MAC unit architecture based on truncated multipliers and approximate adders. The authors of [17] designed an approximate MAC unit based on input awareness, which consisted of approximate multipliers and input-aware conditional blocks. This approach allowed for the achievement of high energy efficiency. In [18], the authors proposed a modified MAC unit that had a novel partial product reduction block. The authors of [19] conducted a comparative analysis of different precision-scalable MAC unit architectures. The form of number representation has a great influence on the performance of blocks. In [20], MAC units were proposed, in which the technique of generating partial products combined the multiplier and the adder. Two's complement arithmetic was used to perform operations on negative numbers in these units. The effectiveness of this approach for application in deep neural networks was considered. Another way to represent numbers is in posit format. In [21], the authors presented a generator of posit MAC units and their use in deep-learning applications. In [22], for the implementation of DFs, single precision floating point Vedic multipliers were used. In order to reduce the latency and hardware cost of devices containing MAC units, researchers have used various compression techniques. The authors of [23] proposed a 4:2 compression technique to add partial products in MAC units. In [24], the authors proposed a low-latency MAC unit architecture using the column bit compression technique. In the present study, a new modified MAC unit called truncated MAC (TMAC) was developed to increase the performance of FIR DFs. This paper contains a theoretical analysis and hardware simulation on field-programmable gate array (FPGA) FIR DFs containing the proposed modified TMAC units and a comparative analysis with FIR DFs using traditional MAC units.