## 3 Experimental Result  
Figure 8 shows the top layout of the proposed VCO. It consists of VCO core, tail inductor, VCO buffer and test buffer, and occupies a layout area of 0.14 mm\({}^{2}\). The circuit is implemented in a 40-nm CMOS process. The VCO core consumes 24 mW from the power supply of 0.8 V, while inductive buffers consume 21 mW from the power supply of 1.1 V. The VCO operation is verified through the Electro-Magnetic (EM) based post-layout simulation. The proposed VCO satisfies the frequency range of 13 GHz to 19 GHz in all corner cases and temperatures, while the target frequency range is from 14 GHz to 18 GHz. The additional 2 GHz frequency range is considered for variation of the capacitors inside the switch capacitor bank during the fabrication process. The tuning range of the VCO can be calculated through Equation (8):  
\[F_{TR}(\%)=(F_{max}\_F_{min})\times 100/F_{center} \tag{8}\]  
Therefore, the proposed VCO offers the tuning range of 37.5%. Figure 9 demonstrates the linearity and discrete tuning of the coarse and middle switched capacitor banks of the proposed VCO. In this simulation, the binary controlling bits of the coarse bank are changed from 001 to 100 (1 to 4 decimal), while the 6 bits of the middle capacitor array are adjusted from all \"0\" to all \"1\", within each code of the coarse bank. The maximum frequency resolution of the middle capacitor bank at 18 GHz is 100 MHz, while with a decreasing frequency this frequency step decreases. To avoid any blind zones inside the frequency range, there are overlapped frequencies between the coarse and middle tunings. The weights of the capacitors inside the middle stage are 1, 2, 3, 4, 8 and 16. One redundant bit with the weight of 3 is considered to avoid any blind zones inside the middle-frequency range. Figure 10 indicates the continuous tuning of the VCO through controlling the voltage of VC. As the simulation results show, the VCO gain is 120 MHz/V, 180 MHz/V and 300 MHz/V, at 14 GHz, 16 GHz and 18 GHz, respectively. Figure 8: Top layout pattern of the proposed VCO. Figure 11 shows the phase noise performance of the linear transconductance VCO at 14 GHz and 18 GHz carrier frequencies. The post-layout simulation results of phase noise at 14 GHz are \(-\)87.2 dBc/Hz, \(-\)113 dBc/Hz and \(-\)134 dBc/Hz at 10 kHz, 1 MHz and 10 MHz offset frequencies, respectively. The VCO offers phase noise performance of \(-\)87.4 dBc/Hz, \(-\)110 dBc/Hz and \(-\)130 dBc/Hz for 10 kHz, 1 MHz and 10 MHz offset frequencies at 18 GHz carrier frequency. Figure 12 shows the transient simulation result and output swing of the VCO with output buffers at 14 GHz and 18 GHz, respectively. In this simulation, the load condition for the test buffer is the  
Figure 11: Phase noise performance of the VCO at 14 GHz and 18 GHz carrier frequencies. Figure 10: Continuous tuning of the VCO (KVCO). Figure 9: Linearity of the discrete tuning of VCO by coarse and middle capacitor banks. coupling capacitance and a 50-ohm load, and the VCO buffer is simulated considering the input load of the divider. Table 1 summarizes the performance of the proposed VCO in different corners and temperatures. The results show that the variation of the phase noise in all corner conditions is less than 3 dBc/Hz, at the start and end of the frequency. Table 2 features the proposed VCO as well as the recent works. It should be noted that the comparison with the fabricated works is not fair. However, the phase noise is calculated in the presence of the Low Dropout regulator (LDO) noise, considering the loading effect of the coupling capacitance, 50-ohm load, and the input load of the divider inside the PLL. Further, the frequency range of the VCO is optimized using the EM-based post-layout simulation results. Therefore, the provided simulation environment provides a fairer evaluation compared to the practical conditions. To evaluate the performance of the VCO, the Figure of Merit (FoM\({}_{T}\)) is presented in Equation (9).