# Multilevel Bipolar Electroforming-Free Resistive Switching Memory Based on Silicon Oxynitride
## 3 Results and Discussion
### Effect of Write-Current Level and Silicon Oxynitride Thickness  
The amount of current that passes through the device needs to be controlled to avoid permanent breakdown during the switching process of the device. It has also been reported that the size and number of conductive filaments can be controlled by the write current in filamentary switching mode [51; 52]. The influence of the write current on the resistive switching characteristics of the Au/Ni/SiO\({}_{\text{x}}\)N\({}_{\text{y}}\) (10 nm)/p\({}^{+}\)-Si device is shown in Figure 6, with four write current limits of 0.1, 0.15, 0.25, and 100 mA. Figure 6: I-V characteristics of Au/Ni/SiO\({}_{\text{x}}\)N\({}_{\text{y}}\)/p\({}^{+}\)-Si memory device with various I\({}_{\text{COMP}}\) levels. The device shows stable multilevel resistive switching states, and the two SET voltages and the second RESET voltage are almost the same regardless of the write currents of 0.1, 0.15, 0.25 mA. This can be attributed to the presence of enough defects in the SiO\({}_{x}\)N\({}_{y}\). As the write current increases, the LRS current of the device also increases at the same second SET voltage. This implies that multiple states can be programed by using different levels of write currents. Even at the same SET voltage, the resistance states can be altered by changing the write current level. However, the device loses multilevel operational characteristics and shows only bistable resistive switching behavior when the device is subjected to the write current of 100 mA. The IRS state does not exist anymore. This indicates that the resistive switching mechanism may change completely from charge trapping and trap-to-trap hopping to filamentary switching inside the bulk SiO\({}_{x}\)N\({}_{y}\) after the device conducts current as high as 100 mA. The most apparent reason could be that the intrinsic defect sites involving charge hopping conduction in the IRS are damaged by the formation of large conductive filaments. The effects of write current on the resistance switching mechanisms were also observed by other researchers [53; 54]. Based on these results, it is inferred that the resistive switching from the HRS to LRS is correlated with the filamentary model. The I-V characteristics of SiO\({}_{x}\)N\({}_{y}\)-based memory devices having various SiO\({}_{x}\)N\({}_{y}\) thicknesses are compared in Figure 7. The device with a 15-nm-thick silicon oxynitride layer shows a higher HRS, IRS, and LRS current than the devices with thinner layers, which implies that the 15-nm-thick SiO\({}_{x}\)N\({}_{y}\) switching layer more likely hosts more nitride-related traps and oxygen vacancies. A similar phenomenon was reported in [35] and [55], where a thicker oxide layer and silicon nitride layer hosted more oxygen vacancies and more nitride-related traps, respectively. Therefore, the conductivity of the 15-nm-thick SiO\({}_{x}\)N\({}_{y}\) layer is higher than those of the thinner layers. As a result, the formation of conductive paths is easier in the 15-nm-thick SiO\({}_{x}\)N\({}_{y}\) layer than in a 10- or 7-nm-thick layer [56]. The SET and RESET voltages for the IRS of the device increase with the increased SiO\({}_{x}\)N\({}_{y}\) layer thickness, which is attributed to the increased number of nitride-related traps and oxygen vacancies in the layer [35]. Meanwhile, the device with a 7-nm-thick silicon nitride layer does not show multilevel switching behavior but rather an electroforming-free bistable resistive switching behavior. The thickness dependency of the multilevel resisting switching of the RRAM can be explained with the proposed model presented in Figure 5. According to the resistive switching model, the conduction mechanism for the HRS to IRS is due to the trap-to-trap hopping process of the charge carriers and the IRS to LRS is the filament formation at the interface of the Ni and SiO\({}_{x}\)N\({}_{y}\) layers. A certain thickness of  
Figure 7: I-V characteristics of Au/Ni/SiO\({}_{x}\)N\({}_{y}\)/p\({}^{+}\)-Si memory devices with various SiO\({}_{x}\)Ny thicknesses.