## 4 Applications of FBFET
### Memory Cells
The FBFET has potential barriers controlled by the gate voltage that blocks the flow of electrons or holes along the channel. The mechanism by which hysteresis occurs is that the voltage applied to the gate causes a small collapse owing to the band modulation at the potential barrier [43; 44; 45; 46; 47; 48]. A flow of carriers then occurs, which are sequentially trapped in the potential wall. The potential walls affected by the accumulated carriers cause a constant change in the height of the opposite potential barrier, which controls the flow of the other carriers. As a result, there is a huge difference in the current flowing to the source and drain repeatedly, which eventually collapses both potential barriers through the carriers trapped in the potential walls [46]. The condition in which carriers are trapped in the potential wall to allow the current to flow well is defined as \"1\". Accordingly, the process of trapping the carriers in the potential wall is referred to as the process of \"writing\", whereas \"holding\" is the process of maintaining the data value, and \"reading\" is the current value in the trapped state [43; 44; 45; 46; 47; 48]. In contrast, the carrier is released from the potential wall, and thus the height of the potential barrier is high, and the current is blocked. In this case, the state can be written by removing the trapped carrier by adding applied voltage to the opposite gate voltage to release the carrier. Figure 9: Illustration of a capacitorless dynamic random-access memory (DRAM) circuit composed of an FBFET [43; 44]. To write the state of '0', the gate voltage is dropped to 0 V to remove the carrier from the channel region located below the gate. Holding state '0' involves returning to a highly negative V\({}_{\text{G}}\) (V\({}_{\text{Ge}}\)) range, the device is not in equilibrium because there are no carriers that can be pulled to construct the inversion layer (deep depletion). The rapid change in potential makes the hole injection barrier very steep. To read the '0' state, data is read with a negative pulse. V\({}_{\text{D}}\) should be allowed to select between the measured V\({}_{\text{De}}\) values in the DC and transient modes, so that the diode does not turn on to ignore uncalled current. State '0' must be refreshed constantly because the energy barrier and V\({}_{\text{De}}\) are lowered by trapped carriers that are generated to recharge the channel region under the gate (see Figures 10 and 11) [46]. As the gate voltage is set to 0 V to remove the potential barrier, state '1' is written. The V\({}_{\text{A}}\) pulse causes the forward bias of the P-I-N diode, allowing electrons and holes to flow into the channel region when the FBFET is viewed separately from the gate. To hold state '1', V\({}_{\text{G}}\) is applied such that carriers flowing through the channel region are attracted to a certain space under the gate. The barrier is lower  
Figure 11: Diagram of a capacitor-less DRAM equivalent circuit with logic values “0” and “1” in three states: writing, holding, and reading (logic). The arrow line at Hold “0” corresponds to the leakage current of the reverse-biased drain junction limiting the hold time [43]. Figure 10: Illustrated waveform of a capacitor-less DRAM’s operation. The DRAM is composed of a \(Z^{2}\)-FET with V\({}_{\text{BG}}\) = 2 V [43; 44]. than that in the state of holding '0', and VON is reduced. Reading state '1' uses the pulse on the source of the FBFET to create a current in the device, which should be high [46]. In summary, in the '1' state, carriers are stored in the potential wall located in the channel on the body and increase the potential, thus lowering the potential barrier, which leads to a reduced threshold voltage and a high current. In state '0', carriers are removed from the trap located in the channel region on the body and reduce the affordable current [43; 44; 45; 46; 47; 48]. In addition, a novel FBFET-based SRAM cell has been proposed.