## 3 Test Environment for TMR Mitigation Structures
In the general case, the error injector consists of two blocks: an error-sequence generator and an error selector, as shown in Figure 6.  
In the simplest case, the selector can be implemented based on OR, AND or XOR gates. In the case of the OR function, the values for which the injector has generated a high state are blocked in the high state; in the case of the AND function, those for which the injector  
Figure 5: Impact of resource sharing on the mitigation properties of TMR. Figure 6: Block diagram of the error injector. has generated a low state will be blocked in the low state. In the case of an XOR function, those values for which the injector has generated a high state are negated. In the case of the error-sequence generator, two concepts can be distinguished: a concept in which the error is triggered at fixed cyclic and specified intervals, and a concept in which the error is triggered at random. The concept with randomness seems to better reflect SEU phenomena, which is why the authors focus on it later in this article. There are various forms and possibilities for building such an error-sequence generator. One solution may be to use a module that generates a Pseudo-Random Bit Sequence (PRBS). To generate the PRBS, a shift register with feedback implemented by an XOR-type logic gate is usually used. Each shift register is associated with some polynomial over a finite body. The maximum length is for shifting registers associated with primitive (non-decomposable) polynomials over the body. Such registers include the polynomial \(X^{15}+X^{14}+1\), which is associated with the sequence denoted PRBS15. It uses a 15-bit ring register and involves \(2^{15}-1\) combinations (32,767 combinations). Since the polynomial is prime, the number of states includes all but zero. The micro-architecture of the error injector using the XOR function and the PRBS15 module is shown in Figure 7. When PRBS[15] returns a high state, the data bits are negated and thus an error is injected into the data stream. An injection circuit built in this way provides a very high error rate because the distribution of zeros and ones is practically comparable in the output stream of the PRBS block (all possible states from the 15-bit space without the 0..00 state). It is very common that a single voter input (the input channel) corresponds to an \(n\)-bit vector (bus) rather than a single bit. In this situation, the error injector should provide randomness when injecting an error with respect to both the channel and the bus bit. This type of operation is provided by the circuit shown in Figure 8. An input demultiplexer redirects a single PRBS15 stream to one of the channels, while a second layer of demultiplexers ensures that this stream is redirected to a specific bit on the k-bit bus. XOR gates ensure that the specified bit is negated, thus infecting the channel at that point in time. Such an architecture ensures that an error is injected into a randomly selected bit of a randomly selected channel. In this case, only one PRBS15 module is implemented, from whose output the stream for error injection is taken. Naturally, the demultiplexers are also controlled from individual registers (PRBS[1]-PRBS[15]). The error injector presented in Figure 8 ensures that a single error is injected into a randomly selected bit of a randomly selected channel. The error injector is a key component of the hardware-test environment and can be used in the process of testing the correctness of the mitigation of a design using TMR, implemented in FPGAs. This concept is discussed in Section 4. \[SW_{i}=2P(x)(1-P(x)) \tag{2}\]0 Micro-architecture of a fault injector module using PRBS for a single channel. The Essence of Using a Hardware-Test Environment Based on an Error Injector to Test the Correctness of Design Mitigation  
From a mitigation point of view, it is crucial to identify the circuit locations where TMR voters should be placed. It is extremely important to secure the memory elements appropriately.