## 5 Achieved Results and Performance Comparison
### Performance Metrics and Evaluation  
In evaluating the performance metrics of our implemented designs, we adopt a comprehensive approach that encompasses crucial factors such as latency, slices, and throughput. Latency measures the time taken for a computation to complete, providing insights into the speed of our FPGA-based architecture. The number of slices utilized in the design signifies the physical resources employed within the FPGA, reflecting its efficiency and resource utilization. To calculate throughput/area, we employ Equation (5), where throughput is inversely proportional to both the latency (or time) required for computation and the number of slices utilized. This equation encapsulates the trade-off between computational speed and resource utilization, offering a quantitative measure of the overall efficiency of our FPGA-based implementations. By considering the aforementioned performance metrics, we gain valuable insights into the effectiveness and optimization potential of our designs, ensuring that they meet the rigorous demands of their intended applications.  
\[\frac{throughput}{area}=\frac{\frac{10^{6}}{time\left(or\right)latency\left(Q=k.p\,ins\right)}}{slices}. \tag{5}\]  
Equation (5) serves as a crucial definition for throughput, expressed as the reciprocal of the time required to perform a single PM, denoted as Q = k.p, measured in seconds. The term \"Slices\" in this context signifies the area of FPGA resources utilized in the implementation. To facilitate the calculation of throughput in Equation (5), we employ a conversion factor of \(10^{6}\) to transform time measurements from microseconds to seconds. To calculate the latency or the time necessary for a singular Point Multiplication (PM) operation, Equation (6) stands as the principal tool.  
\[time\left(or\right)latency=\frac{required\ (CCs)}{operational\ clock\ frequency}. \tag{6}\]  
Equation (6) outlines the calculation of necessary clock cycles (CCs) required for a single PM operation. These CC values are detailed in Table 2, offering a clear insight into our computational process. Additionally, the operational clock frequency, measured in megahertz (MHz), is conveniently listed in Column 3 of Table 4. This exposition of timing metrics fulfills the purpose of furnishing a holistic perspective on our system's performance attributes in an easily comprehensible manner. The consideration of metrics encompassing throughput, slices, latency, clock cycles, and operational clock frequency underpins the development of systems that are not only more efficient but also more effective. This optimization endeavor, at its core, ensures the judicious employment of hardware resources, thereby expediting computational processes. The resultant enhancements in both performance and efficiency render our designs exceptionally competitive and impactful within their respective domains.  
Equation (7) explains the method for the computation of various performance values (in percentages) in different performance factors.  
\[percentage=(1-(\frac{\text{Obtained results with the proposed architecture}}{\text{Obtained results with state of the art architectures}}))\times 100. \tag{7}\]  
In Equation (7), the values for the proposed architecture are taken from Table 4. Similarly, the values for state-of-the-art architectures are taken from the corresponding articles.