## 3 Hump Effect in SCNW TFET  
Figure 2 shows drain current (\(I_{\text{D}}\)) versus gate voltage (\(V_{\text{GS}}\)) curves with 2 nm-\(T_{\text{TUN}}\) and 0.5 V-drain voltage (\(V_{\text{DS}}\)) while \(L_{\text{TUN}}\) is varied from 20 to 60 nm. The \(I_{\text{ON}}\) is extracted at 2.0 V-\(V_{\text{GS}}\) and 0.5 V-\(V_{\text{DS}}\). The \(I_{\text{ON}}\) increases linearly proportional to the \(L_{\text{TUN}}\) which confirms that the BTBT junction area of SCNW TFET is determined by the \(L_{\text{TUN}}\). Generally, the FETs based on a NW channel have a disadvantage for enhancing current drivability, which can be achieved by increasing a NW radius or using a multi-channel structure [38]. On the other hand, SCNW TFET can easily adjust \(I_{\text{ON}}\) by controlling a \(L_{\text{TUN}}\). However, as shown in Figure 3a, there is a hump in the subthreshold region of SCNW TFET. The transfer curves are simulated with various \(V_{\text{DS}}\) values. At all the \(V_{\text{DS}}\) values, the hump current appears. In addition to this, with the higher the doping concentration, the better the ON-current is shown however, the hump effect is noticeable from 5\(\times\)10\({}^{19}\)-\(N_{\text{S}}\) cm\({}^{-3}\) as shown in Figure 3b. The hump effect should be addressed for TFET's low-power application since it deteriorates average \(S\) which results in the degradation of \(I_{\text{ON}}\)/\(I_{\text{OFF}}\) and/or supply power (\(V_{\text{DD}}\))-scaling. Therefore, optimization for other parameters is needed to achieve high ON-current and hump-less transfer curve. In order to analyze the cause of hump effect, the electron BTBT generation rates (e\({}^{\text{BTBT}}\)) are examined by 2D contour plots with different \(V_{\text{GS}}\) conditions (Figure 4). When \(V_{\text{GS}}\) is applied near a turn-ON voltage (\(V_{\text{ON}}\)), defined as \(V_{\text{GS}}\) when BTBT starts to occur, a lateral-BTBT is predominant. As \(V_{\text{GS}}\) increases, a vertical-BTBT starts to occur at 0.4 V-\(V_{\text{GS}}\) and finally surpasses the lateral-BTBT at 1.2 V-\(V_{\text{GS}}\). Therefore, the current of SCNW TFET can be decoupled into two different BTBTs. In addition, transfer curves with various \(L_{\text{TUN}}\) are plotted in Figure 5. The \(I_{\text{D}}\) at low \(V_{\text{GS}}\) (\(<\) 0.9 V) is unchanged regardless of \(L_{\text{TUN}}\), while \(I_{\text{D}}\) increases with longer \(L_{\text{TUN}}\) at high \(V_{\text{GS}}\) (\(>\) 0.9 V). The \(V_{\text{GS}}\) at this point is defined as hump voltage (\(V_{\text{HUMP}}\)). Since the tunnel junction area of vertical-BTBT component is only affected by \(L_{\text{TUN}}\). \begin{table}
\begin{tabular}{l l} \hline \multicolumn{1}{c}{**Parameters**} & **Value** \\ \hline Source doping concentration, \(p\)-type (\(N_{S}\)) & 10\({}^{20}\) cm\({}^{-3}\) \\ \hline Drain doping concentration, \(n\)-type (\(N_{D}\)) & 10\({}^{20}\) cm\({}^{-3}\) \\ \hline Body doping concentration, \(p\)-type (\(N_{\text{CH}}\)) & 10\({}^{17}\) cm\({}^{-3}\) \\ \hline Gate work function & 4.05 eV \\ \hline Channel length (\(L_{\text{CH}}\)) & 30 nm \\ \hline Nanowire radius except tunnel region (\(T_{\text{B}}\)) & 7 nm \\ \hline Gate oxide thickness (\(T_{\text{OX}}\)) & 1 nm \\ \hline Length of tunnel region (\(L_{\text{TUN}}\)) & Variable \\ \hline Thickness of tunnel region (\(T_{\text{TUN}}\)) & Variable \\ \hline Drain voltage (\(V_{\text{DS}}\)) & 0.5 V \\ \hline \end{tabular}
\end{table} 
Table 1: SCNW TFET design parameters used for TCAD simulation. Figure 2: (Simulation) \(I_{\text{D}}\)-\(V_{\text{GS}}\) curves of SCNW TFET with 2 nm-\(T_{\text{TUN}}\) and 0.5 V-\(V_{\text{DS}}\) depending on the \(L_{\text{TUN}}\). The inset shows \(I_{\text{ON}}\) as a function of \(L_{\text{TUN}}\). For the SCNW TFET, the \(I_{\text{ON}}\) increases proportional to \(L_{\text{TUN}}\). Figure 3: (Simulation) Log(\(I_{\rm D}\))-\(V_{\rm GS}\) curves of SCNW TFET depending on the (**a**) \(V_{\rm DS}\) (**b**) \(N_{\rm S}\).