# An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields
## 1 Introduction
### Pm Hardware Accelerators and Limitations  
The latest advancements in hardware accelerators for PM computation in ECC are detailed in the state-of-the-art literature [12; 13; 14; 15; 16; 17; 18; 19; 20; 21; 22; 23]. In [12], a highly efficient implementation of ECC is presented over \(GF(2^{163})\) with a focus on minimizing area utilization. They used a digit serial multiplier architecture for modular multiplication computation, which reduces hardware resources. To cater to low-cost cryptographic applications and enable integration with 8-bit processors, they incorporate an 8-bit input-output interface. Notably, their implementation of Montgomery PM on Virtex-5 utilizes 473 slices and computes one PM in 0.11 ms. Similar to [12], an interesting work is found in [13], where low-areaimplementation of PM for ECC over \(GF(2^{163})\) is illustrated. The authors employ the Lopez-Dahab algorithm and achieve low area utilization on FPGA. The optimization is achieved due to the use of a hybrid Karatsuba multiplier. With different digit sizes, a digit serial modular multiplier is utilized in [14] over \(GF(2^{m})\) with \(m=163,233,283,409\) and \(571\) to realize the PM computation. A crypto engine over \(GF(2^{233})\) is described in [15] for wireless sensor nodes. Here, the authors have focused on digit-by-digit computations for arithmetic operations while optimizing hardware resource utilization on the targeted FPGA device. Another notable work is described in [16], where a coprocessor design technique is employed to simultaneously leverage the advantages of symmetric and public-key cryptography. Their approach incorporates an Advanced Encryption Standard (AES-128) algorithm for symmetric cryptography, ECC over \(GF(2^{163})\) for elliptic curve operations in PKC, and a secure hash algorithm (SHA-256) for hash computations in digital signature, authentication, and random key generation. A pipelined architecture with two stages is presented in [17]. The authors have proposed an efficient scheduling scheme for point addition and point doubling operations. It has minimized the total number of required clock cycles. The results have shown that the achieved frequencies are 369, 357, and 337 MHz for key lengths of 163, 233, and 283 bits, respectively. Similarly, the work in [18] is also based on pipelining technique with two stages. The authors have focused on reducing the total processing time. The reduction in total processing time is achieved through an optimized scheduling policy for point addition and point doubling operations. The efficient utilization of memory locations and an efficient multiplier, working on the principles of the digit-parallel scheme, contribute to reducing the area. Instead of the binary field accelerators, a prime field processor is proposed in [19]. The size of the proposed processor is 256 bits. The authors employed Jacobian coordinates to overcome the computational overhead of modular inversion. Additionally, the design incorporates an interleaved modular multiplier, contributing to reductions in both area utilization and delay. The point addition and point doubling operations are optimized along with the multiplication algorithm. On prime fields, high-speed PM accelerators are described in [20; 21]. In the hardware accelerator of [22], a particular model of ECC (i.e., Edward curves) is utilized for PM computation which offers unified PA and PD formulations, which are secured against side-channel attacks. Another high-speed PM accelerator over \(GF(p)\) field with \(p=256\) is illustrated in [23]. In the existing PM accelerators, throughput has been optimized by employing various optimization techniques such as pipelining [17], digit-serial modular multipliers [14], bit-parallel Karatsuba-based modular multiplications, combined Karatsuba and schoolbook-based modular multiplications [13], rescheduling of PA and PD operations [17; 18], and many more. For area optimizations, the existing accelerators use bit-serial and digit-serial-based modular multiplication approaches [12].