## 1 Introduction  
Mains-interfacing power conversion systems are typically obliged by power quality standards to interchange sinusoidal-shaped current with the utility grid [1; 2; 3]. As a result, alternating instantaneous power is exchanged between the two entities, formed by a DC component and a power component pulsating at twice the mains base frequency [4; 5; 6]. While the DC component is transferred to/from the load/source in order to carry the energy, the pulsating power constituent should not be allowed to reach the load/source to avoid lifetime reduction and excessive losses [7; 8; 9]. Consequently, DC link capacitors are typically employed to compensate instantaneous power mismatch between grid-side and load/source-side both in steady state and during transients [10; 11; 12]. This is accomplished by regulating the average DC link capacitor voltage (reflecting the stored energy) to a constant reference value employing a PI or type-2 compensator [13; 14; 15; 16] without counteracting the pulsating power component. As a result, pulsating current flows through the DC link capacitor, giving rise to an uncontrolled DC link voltage ripple [17; 18], which is proportional to the total power processed and inversely proportional to the DC link capacitance value and DC link voltage reference value [19; 20]. Upon sensing the DC link voltage and feeding it back to the regulation loop, the ripple distorts the grid-side current magnitude reference signal (created by the loop compensator), leading to an increased total harmonic distortion (THD) of utility-side current [21; 22]. In order to limit the THD, the gain of DC link voltage loop compensator should be restricted in the vicinity of double the base utility frequency [23], implying a trade-off between AC-side current THD and DC link voltage dynamics in case compensators with monotonically decreasing frequency response characteristics (e.g., PI or type-2) are employed [24; 25; 26]. Typically, around 10 Hz DC link voltage loop bandwidth is attained under 5% grid-side current THD restriction. Such a relatively low bandwidth imposes a high value of the required DC link capacitance in order to cope with sharp load-side power variations, since the DC link voltage value should always remain above the maximum of grid-side voltage to retain converter controllability [22; 24]. Many solutions aiming to improve the trade-off have been suggested. Utilizing line voltage and/or load current feedforward to compensate against parameter variations does not increase the DC voltage loop bandwidth, yet it requires additional sensors [27; 28; 29; 30]. The ripple estimation and cancellation techniques proposed in [31; 32; 33; 34; 35; 36] indicated an improved performance, yet requiring a relatively complex circuitry and a significantly increased computational burden. The implementation of approaches based on nonlinear and/or time-varying control proposed in [37; 38; 39; 40] call for a high-performance microcontroller. On the other hand, linear filtering-based methods proposed in [41; 42; 43; 44; 45; 46; 47] seem to be much simpler in terms of analysis and implementation. In particular, compensators combining a PI or type-II term with a notch filter may be easily realized either digitally or by a simple analog network. As mentioned above, the value of DC link voltage loop gain should be restricted in the vicinity of double the base utility frequency in order to limit the THD. A notch filter was combined with the current loop controller in [48] to enhance transient responses at both the DC bus voltage and the output current. Introducing a notch filter tuned to double the mains base frequency allows for local DC-link voltage loop gain minimization without restricting the corresponding PI or type-II controller gain, thus attaining an increased crossover frequency. Disturbance observer-based approaches, employing notch terms, were shown to yield a similar effect [49; 50].