## 4 Results and Comparison
### Comparisons
Hence, the improvement in circuit frequency leads to a reduction in computation time. An accurate comparison is difficult to provide as the reference design of [14] targeted the prime field, i.e., \(GF(P)\) with \(P=256\), for implementation, whereas we adopted a binary field, i.e., \(GF(2^{m})\) with \(m=233\). Moreover, the supported key lengths differ; the \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**Ref. \#**} & **Algorithm (or)** & \multirow{2}{*}{**Device**} & \multirow{2}{*}{**Slices**} & \multirow{2}{*}{**LUTs**} & **Clock** & **Freq** & **Latency** & **Power** & **Details** \\  & & & & & **Cycles** & **MHz** & **(μs)** & **(mW)** & \\ \hline
[12] & Montgomery & Virtex-7 & 2207 & 9965 & 3960 & 369 & 10 & - & 163 bit binary field \\
[12] & Montgomery & Virtex-7 & 5120 & 18,953 & 5634 & 357 & 15 & - & 233 bit binary field \\
[13] & Montgomery & Virtex-7 & 1529 & 4162 & 3798 & 383 & 9 & - & 163 bit binary field \\
[13] & Montgomery & Virtex-7 & 2048 & 6407 & 5402 & 379 & 14 & - & 233 bit binary field \\
[14] & Double and Add & Virtex-7 & - & 50,789 & 65,783 & 91 & 722 & - & 256 bit prime field \\
[15] & Montgomery & Virtex-5 & 473 & - & - & 359 & 110 & - & 163 bit binary field \\
[15] & Binary & Virtex-5 & 420 & - & - & 362 & 830 & - & 163 bit binary field \\
[15] & Frobenius Map & Virtex-5 & 710 & - & - & 165 & 300 & - & 163 bit binary field \\
[16] & Lopez Dahab & Virtex-7 & 3657 & 10,128 & 3426 & 135 & 25 & - & 163 bit binary field \\
[17] & Montgomery & Artix-7 & 442 & - & 1,553,782 & 190 & 8177 & - & 233 bit binary field \\
[18] & Frobenius Map & Artix-7 & - & 8577 & 55,068 & 150 & 367 & 379 & 163 bit binary field \\ \hline TW & Montgomery & Virtex-5 & 411 & 1758 & 716,459 & 139 & 5154 & 84 & 233 bit binary field \\ TW & Montgomery & Virtex-7 & 391 & 2346 & 716,459 & 161 & 4450 & 77 & 233 bit binary field \\ \hline \hline \end{tabular}  
* In [18], ECC-163, AES-128, and SHA-256 algorithms have been implemented in a coprocessor design. For [14; 17], we have calculated the latency value by the ratio of clock cycles over circuit frequency. TW means for this work.  
\end{table} 
Table 2: Comparison to state-of-the-art hardware designs of PM. reference design uses 256 bits, whereas we utilized 233 bits. Despite the field selections and supported key lengths, the implemented PM algorithms also differ; we incorporated the Montgomery algorithm, whereas the reference design utilizes the double and add PM algorithm. Comparatively, our design utilizes 21.64 (ratio of 50,789 to 2346) times fewer LUTs and is 1.76 (ratio of 161 to 91) times more efficient in clock frequency. On the other hand, the reference design employs an interleaved modular multiplier, which takes fewer clock cycles (shown in column six of Table 2) and (also) utilizes lower computation time (shown in column eight of Table 2) than ours, where we used a bit-serial multiplier design. As shown in Table 2, the performance of three PM algorithms (Binary, Frobenius Map, and Lopez Dahab) are compared in [15] on Virtex-5 FPGA. For all the PM algorithms implemented in [15], our crypto processor design outperforms in slices on identical Virtex-5 FPGA. The reason is the use of a digit-serial multiplier in the reference design of [15], whereas we preferred to use a bit-serial multiplier. The comparison to LUTs, clock cycles, and power cannot be provided, as the relevant information is not provided in the reference implementation (see the corresponding columns in Table 2). The reference design outperforms ours if we examine the frequency and latency columns in Table 2. Our objective was to realize an area-efficient ECC implementation, and our design outperforms in slices; therefore, there is always a trade-off. A Lopez Dahab-based PM design over \(GF(2^{163})\) is described in [16] on Virtex-7 FPGA. On an identical Virtex-7 FPGA, our proposed crypto processor over \(GF(2^{233})\) is 9.35 (ratio of 3657 to 391) and 4.31 (ratio of 10,128 to 2346) times more efficient in slices and LUTs.