# Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
## 3 Gate-Level Hiding Countermeasures
RCDDL was designed to improve WDDL in terms of security strength and average power consumption, but making it compatible with WDDL gates, so they could be used in conjunction to achieve improved logic functionality. In RCDDL, the complemented output \(\overline{Q}\) is implemented by reusing part of the non-complemented output  
Figure 6: Gate-level hiding logic styles: (**a**) BCDL and (**b**) RCDDL. logic tree \(Q\). As in WDDL, to ensure dynamic operation, the precharge phase is propagated as a wave along the circuit. RCDDL has two operation phases: (i) precharge phase, where the logical \"0\" is propagated as a wave through all differential inputs of the circuit; and (ii) evaluation phase, which produces the output \(Q\) and its complement \(\overline{Q}\). The structure of an RCDDL gate is depicted in Figure 6b, where four parts can be identified. Segments 1 and 2 constitute the uncomplemented logic designed as a sum of products of the expression; segments 1, 3, and 4 constitute the complementary logic, where the outputs from segment 1 are inverted and provided to segment 4, then segment 3 generates the precharge signals and segment 4 is the force gate generating the complement of the function in segment 2. The main drawback of RCDDL is that when connecting in serial several RCDDL gates, there is a differential delay introduced between the inputs to the force gate (segment 1) during evaluation state, which, for certain inputs, causes glitches in the output. Moreover, the design complexity (gate design is not straightforward and force gates need resizing) as well as the area penalty make RCDDL not a good logic style option for low-power secure applications. The authors in [33] present the low-power variant of the metal-oxide semiconductor (MOS) current mode logic (MCML) for DPA-resistant applications (initially designed for low-power and high-speed applications) achieving low switching noise due to its reduced output voltage swing and differential operation. The structure of an MCML gate, depicted in Figure 7a, is composed of three different blocks: (i) the current source, implemented by the bottom n-channel metal-oxide semiconductor (NMOS) transistor providing a constant bias current; (ii) the DPDN implemented with NMOS transistors and realizing the functionality of the gate; and (iii) the load resistors, implemented with two p-channel metal-oxide semiconductor (PMOS) transistors serving as active resistors. The main drawback is the high static power consumption of the gate, which is not a good option for portable devices and medium- and low-frequency applications. To solve this problem, the authors in [34] present the logic style called power-gating MCML (PG-MCML). This logic style is based on the power-gating technique in which sleep transistors are inserted into the power supply. The main drawback of this logic style is the design complexity, but it has the advantage of having reduced power consumption values. In [35] the authors present a dynamic logic style called 3-state dynamic logic (3 sDL) based on signals with three possible states: logical \"1\" with the value of \(V_{dd}\), logical \"0\" with the value of \(GND\), and finally a third state with the value of \(V_{dd}/2\). The structure of this logic style is depicted in Figure 7b, where the differential outputs \(Q\) and \(\overline{Q}\) go from \(\{1,0\}\) or \(\{0,1\}\) for the function value \"1\" or \"0\", respectively, in the evaluation phase with \(CLK=1\), and then to \(V_{dd}/2\) in the precharge phase with \(CLK=0\). The main advantages of this logic style are that the operation frequency is faster than other DPL styles because the swing required for the transition is halved, starting from \(V_{dd}/2\), and the direct cascability of 3 sDL gates. The main drawbacks are the need for differential routing and the design of the capacitance \(C_{DUMMY}\) exactly equal to the value of \(C_{OUT}\). Figure 7: Gate-level hiding logic styles: (**a**) MCML, (**b**) 3 sDL, and (**c**) 3 sDDL.