## 2 Background and Related Work  
The WSN communication protocol stack has been extensively investigated in the past decade, with a special focus on the MAC layer. [PERSON] _et al._ summarize former research efforts and optimization criteria in [6] and give suggestions on future directions. They argue that as energy consumption of computing chips falls more sharply than that of the radio front-ends, the wireless interface becomes the primary consumer of energy in WSN nodes. Therefore, designing the wireless protocol stack for energy efficiency should be treated with the utmost importance in WSNs among other traditional goals, such as fairness, delay or bandwidth utilization. They also point out that research tools should be carefully chosen and real-world experiments should be preferred over ns-2 and OMNeT++ simulations that often make unreasonably simplified assumptions. For the former, [PERSON] _et al._ advocates the use of SDRs, which would give access to the stack layers below the MAC. One significant step towards SDR-based experimentation was the SoftMAC [7] software architecture developed by [PERSON] _et al._ on top of an IEEE 802.11 compliant Atheros network card. They reverse-engineered portions of the Atheros AR5212 chip interface and wrote a software driver that gives extensive access to the MAC layer and partial control over the PHY layer. The greatest benefit of this approach is the reduced SDR hardware cost, due to the use of commodity chips. However, the flexibility of SoftMAC is limited compared to a full-stack SDR, as the former has control over only a small part of the PHY layer. Full-stack SDRs saw a constant rise in popularity during the past decade. Complete software tool suites, such as Matlab and Simulink or the open-source GNU Radio [8], are available for researchers to develop complete vertical protocol stacks with reasonable development effort and design cycle. These software tools can seamlessly connect to mid-priced SDR hardware, such as the USRP [9] SDRs from Ettus Research. The USRP N210 hardware contains an SRAM FPGA responsible for a fixed set of low-level baseband signal processing tasks, while the rest of the wireless stack is processed on an Ethernet or USB connected desktop PC. Simulink also allows one to target high-end general FPGA development platforms from Xilinx and Altera connected to an FPGA mezzanine card radio front-end and a PC, to generate prototype FPGA configuration from model blocks in an automated fashion [10]. The clear advantage of such desktop SDRs is that they allow full control of the entire network stack, including the complete baseband processing, at the cost of an affordable development time. The cost and power consumption of such platforms and the need for a PC connection, however, severely limits their use in deployed WSN scenarios. The flexibility and the ASIC-class parallel processing capability made SRAM FPGAs attractive for WSNs, as well. Several WSN nodes utilizing SRAM FPGAs have been developed and extensively used in various applications, such as human body movement tracking [11], safety-related systems [12] and shooter localization [13]. [PERSON] _et al_. recently investigated the performance and energy consumption of a mid-size SRAM FPGA-based WSN platform in [14]. Thus, it is clearly indicated that FPGAs are an emerging alternative to high-end microcontrollers and digital signal processors in computationally-intensive WSN applications. Furthermore, SDR hardware designs of SDR4 All [15] and OsmoSDR [16] demonstrate that even relatively small-size SRAM FPGAs are capable of significant baseband signal processing. SRAM FPGAs, however, offer very limited options when it comes to low-power duty-cycle modes. Transitioning from sleep to active mode is delayed and energy demanding, because the volatile SRAM configuration cells need to be reconfigured on every wake-up. Furthermore, their static power consumption is relatively large compared to FPGAs manufactured with flash and antifuse technologies.