# Supply-Scalable High-Speed I/O Interfaces
## 3 Design Considerations of Supply-Scalable I/O
### On-Chip Supply Control  
From the surveys shown in Figures 3 and 6, we observe there have been many works relying on off-chip supply control rather than on-chip control, and generally those works exhibit a better efficiency than those with on-chip control. It is mainly because they do not include any power overhead of supply control (either of on-chip and off-chip), so it is important to understand what the overhead is. In addition, ultimately, the supply control circuit must be integrated with the core circuits. The supply control scheme can be divided into two types: a switching regulator (DC-DC converter) and linear regulator (specifically, a low-dropout (LDO) regulator), which are depicted in Figure 8. Generally, the switching regulators exhibit higher efficiency compared to linear regulators, because there is a non-negligible voltage dropout in the linear regulators [24]. However, because of their switching behavior, the switching regulators have a periodic switching ripple on the output voltage whereas the linear regulators offer power supply noise rejection (PSR). Since most of the building blocks of high-speed I/O are very sensitive to the supply noise [49; 50], the linear regulators can be more suitable for high-performance applications [12; 31]. For example, [31] reveals that the link bit-error-rate (BER) degrades when a switching regulator is used. In addition, the supply sensitivity increases at a lower  
Figure 7: Comparison of CMOS and current-mode logic (CML) circuit.  
supply voltage, so it is more critical in supply-scalable I/O compared to fixed-supply I/O. For example, the transition delay of a CMOS inverter is approximately expressed as to  
\[\tau_{d}\ =\ \frac{CV_{DD}}{\beta(V_{DD}-V_{TH})^{\alpha}}, \tag{3}\]  
where \(\tau_{d}\) is the transition delay of the CMOS inverter [19]. By differentiating (3) with \(V_{DD}\), we can obtain the supply sensitivity of the transition delay, which represents the jitter induced by supply noise of \(\Delta V_{DD}\) as  
\[\frac{d\tau_{d}}{dV_{DD}}\ =\ \tau_{d}\bigg{(}\frac{1}{V_{DD}}-\frac{\alpha}{V_{DD }-V_{TH}}\bigg{)}, \tag{4}\]  
where \(\alpha\) equals two in long-channel devices but becomes smaller in short-channel devices, as mentioned in the Section 2. (4) is illustrated in Figure 9 for \(\alpha\) = 2.0 and 1.5, where we find the supply sensitivity dramatically increases as the supply voltage scales [19; 51]. As a result, for the case of using a switching regulator, the switching frequency and CDR bandwidth should be carefully chosen to minimize the impact of supply ripple on the link BER [22; 33]. Figure 8b shows one of the design considerations of a linear regulator regarding PSR. The linear regulator is based on a negative feedback loop with two poles, one is at the output of the amplifier (\(\omega_{1}\), gate of pass transistor) and the other is at the output (\(\omega_{2}\), regulated supply voltage). Depending on the pole locations, the regulator exhibits different PSR characteristics. For example, if \(\omega_{1}\) is the dominant pole (\(\omega_{2}>\omega_{1}\)), the PSR has a peaking, whereas the opposite case exhibits a plain low-pass filter characteristic [19; 52]. However, making \(\omega_{2}\) dominant requires a huge capacitance because of low output resistance at the \(V_{DD}\) node due to the circuit load. It costs a huge silicon area and frequently needs an off-chip capacitor, and it also severely constraints the supply transition time. To summarize, there are lots of design trade-offs (e.g., PSR versus efficiency, PSR versus silicon area), which need to be carefully examined to find the best topology and design parameters for a given application.  
Figure 8: Block diagrams of (**a**) switching regulator (buck converter) (**b**) linear regulator.  
Figure 9: Supply sensitivity of transition delay of CMOS circuit.