## 3 Results and Discussion
Additionally, the devices with CPTS-treated gate insulators show a smaller increase in the drain current for the variation of the gate voltage, compared to the devices with PETS-treated gate insulators. These results clearly indicate that short-channel effects are more pronounced in the short-channel P3 HT FETs fabricated on CPTS-treated gate insulators. This can be attributed to the improved injection of holes associated with the enhanced hole accumulation by CPTS SAMs, which increases the SCLC and reduces the modulation of the drain current by the gate voltage [8; 9]. Figure 4 shows the output and transfer characteristics of short-channel F8T2-based FETs with \(L\) = 5 \(\upmu\)m, 500 nm, and 30 nm that were fabricated on 200-nm-thick SiO\({}_{2}\) gate insulators treated with PETS and CPTS SAMs. In contrast to the P3 HT FETs, the short-channel F8T2 FETs exhibit no parabolic output characteristics when the channel length is reduced, and the saturation of drain current is clearly observed in F8T2 FETs with \(L\) = 30 nm despite the use of thick SiO\({}_{2}\) gate insulators (200 nm). These results are attributed to the formation of Schottky barriers for hole injection because of the large potential difference between the work function of the source Au electrodes (4.8 eV) and ionization potential of the F8T2 semiconductors (5.5 eV) [29], which leads to contact-limited charge transport and, hence, suppresses the SCLC. The formation of Schottky barriers also causes the voltage drop at the source electrode/organic semiconductor contact, which reduces the net source-drain electric field at the channel region. The resulting increased effectiveness of the gate electric field at the channel region has been shown to enhance the current modulation in OFETs with nanometer channels [8; 9; 11]. It can be seen in Figure 4a,b that the large voltage drop at the Au/F8T2 contact causes a nonlinear increase in \(I_{D}\) in the low \(V_{D}\) region in the F8T2 FETs with PETS-treated gate insulators, whereas the nonlinearity of the \(I_{D}\)-\(V_{D}\) characteristics is decreased for short-channel F8T2 FETs with CPTS-treated gate insulators. These results are consistent with those observed for the short-channel P3 HT FETs of Figure 2, which clearly indicates that a shift in the threshold voltage of transfer characteristics by CPTS SAMs involves the hole injection barriers at the source electrode/organic semiconductor interface being lowered. Such effects can manifest as the smaller modulation of the drain current by the gate voltage in F8T2 FETs with CPTS-treated gate insulators. This is because a lower hole injection barrier leads to a higher source-drain electric field and prevents the effective application of the gate electric field to the channel. To clarify the difference in effects of the built-in electric field produced by the dipole SAM and increased gate electric field with thinner gate insulators, we investigated the electrical characteristics of short-channel P3 HT and F8T2 FETs fabricated on thinner SiO\({}_{2}\) insulators (50 nm thick) treated with the PETS SAMs (Figure 5). As shown in Figure 5a, P3 HT FETs with \(L\) = 5 \(\upmu\)m fabricated on 50-nm-thick gate insulators exhibit clearer current saturation behavior compared to devices on 200-nm-thick gate insulators (Figure 2a). Further, linear \(I_{D}\)-\(V_{D}\) characteristics in the low \(V_{D}\) region are obtained even for the device with \(L\) = 500 nm because of the increased gate electric field. Since OFETs require thin gate insulators (the thickness of a gate insulator is typically \(<\)\(L\)/10) to suppress the short-channel effects [4], P3 HT FETs with \(L\) = 30 nm exhibit parabolic \(I_{D}\)-\(V_{D}\) characteristics even when 50-nm-thick SiO\({}_{2}\) insulators are used. For the F8T2 FETs shown in Figure 5b, good transistor characteristics with saturation of the drain current are observed in devices with \(L\) = 30 nm. This results from the formation of voltage drops at electrode contacts, as mentioned above.