# Implementation of a Lossless Moving Target Defense Mechanism
## 6 Implementation  
### Environment Description  
The P4 language specification defines the PSA architecture, which is illustrated in Figure 5. This architecture can be considered a blueprint for P4 switch architecture, and it may vary depending on the device in which it is implemented. Several products on the market facilitate the creation of a data path using the P4 language. Among these are Intel's Application-Specific Integrated Circuit (ASIC) devices, such as Tofino I, Tofino 2, and Tofino 3 [45; 46; 47]. Additionally, there is the option to implement an SDN switch in FPGA circuits, for which the special NetFPGA SUME [48], AMD Alveo [49], or Intel [50] platforms have been designed. The models defined for these products vary in the number of blocks on the packet processing path. A significant drawback of all these listed products is their cost. Therefore, in the proposed solution, it was decided to utilize a widely available and free  
Figure 4: Data and instruction streams in MISD and MIMD systems. Figure 5: PSA architecture. option, the Mininet environment [51], the main component of which is the SimpleSwitch software switch with V1 model implemented. Similar to SimpleSwitch, the V1 model also programmatically realizes the entire pipeline structure [52; 53]. The V1 model is depicted in Figure 6. Comparing it to the PSA architecture, shown in Figure 5, differences are easy to identify. The parser block appears only once, at the switch's input, whereas the deparser block is implemented at the switch's output. In contrast, in the PSA architecture, both blocks appear in both the input and output pipelines. Additionally, in the input pipeline, there is also a checksum verification block (IP header), while the output pipeline includes a checksum update block. Both blocks must be utilized when implementing layer 3 functions, where the SDN switch acts as a router. The implementation uses external objects, which can be perceived as built-in functions. Their usage is limited to passing on function call parameters only; therefore, they are not presented in the following description of the implementation. The V1 model architecture is is known as the target architecture for the P4 language. Each target architecture is supported by one or more targets. In the V1 model, the most commonly used target is the Behavioral Model v.2 (BMv2), which is implemented as a programmable switch in the Mininet environment for simulating computer network functions [51; 54; 55]. It is important to note that not every target architecture may fully implement the P4 language, or the implementation might not fully comply with the language standard. This means that implementing the presented solution may require changes, even at the conceptual level, when used with a different target architecture. Before applying the presented solution to another target architecture, readers are encouraged to familiarize themselves with the BMv2 documentation and the documentation of the selected target architecture. The BMv2 software switch and Mininet run on PC-class computers and are used for development, testing, and debugging new functionalities, both in the data plane and control plane. Although designed for use in a multithreaded environment, they exhibit significant limitations, affecting its performance. One such limitation is the use of only one thread to handle the input pipeline for all packets arriving at all ports of the switch, while output pipeline processing is, by default, carried out by four threads. Figure 7 shows the structure of the network, which serves as the basis for preparing algorithms that implement the considered MTD technique. The presented structure includes four hosts and six switches. From the perspective of the functions performed by the switches, we can identify two types of switches:  
* Core switches, which are connected only to other switches;
* Border switches, which have connections both to hosts and other switches. All switches also have a connection to the SDN controller, which controls the operation of the entire network.