# Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm CMOS FD-SOI and 40 nm GaN HEMT
###### Abstract  
Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different state-of-the-art device technologies and are presented in this work. First, a single-ended broadband PA that employs a third-order input matching network is designed in a 40 nm GaN/SiC HEMT (High Electron Mobility Transistor) technology. Good agreement between the measurement and post-layout parasitic extracted (PEX) electromagnetic (EM) simulation data is observed, and it achieves a measured 3-dB BW (bandwidth) of 18.0-40.3 GHz and \(>\)20% maximum PAE (power-added-efficiency) across the entire 20-44 GHz band. Expanding upon this measured design, a differential broadband GaN PA that utilizes neutralization capacitors is designed, laid out, and EM simulated. Simulation results indicate that this PA achieves 3-dB BW 20.1-44.3 GHz and maximum PAE \(>\) 23% across this range. Finally, a broadband mm-Wave differential CMOS PA using a cascade topology with RC feedback and neutralization capacitors is designed in a 22 nm FD-SOI (fully depleted silicon-on-insulator) CMOS technology. This PA achieves an outstanding measured 3-dB BW of 19.1-46.5 GHz and \(>\)12.5% maximum PAE across the entire frequency band. This CMOS PA as well as the single-ended GaN PA are tested with 256-QAM-modulated 5G NR signals with an instantaneous signal BW of 50/100/400/9 \(\times\) 100 MHz at a PAPR (peak-to-average-power ratio) of 8 dB. The data exhibit impressive linearity vs. \(P_{\mathit{OUT}}\) trade-off and useful insights on CMOS vs. GaN PA linearity degradation against an increasing BW for potential mm-Wave 5G applications. 25 January 2025 16 February 2022 23 February 2022  
mm-Wave PAs. In 5G user equipment (UE) and femto/picocells, the PA's \(P_{OUT}\) will only need to be in the sub-Watt range of less than 20 dBm [2]. Thus, in this proposed work, we will investigate the design of mm-Wave PAs with excellent broadband peak PAE and good linearity that can cover the key 5G FR2 band in two state-of-the-art technologies that target this medium output power range. Output power, frequency performance, size, and cost are inherent characteristics in every technology. For instance, even though devices in smaller technology nodes can generally achieve higher \(f_{T}\), and thus better frequency performance, they have limited output power due to lower breakdown voltage (i.e., Johnson's Limit [3]) compared to larger technology nodes. Additionally, wide-bandgap III-V technologies tend to have higher breakdown voltages and larger carrier transport mobilities compared to silicon technologies. Thanks to the thicker process layers and their semi-insulating substrates, III-V technologies also provide better low-loss on-chip passives, which is crucial for the high Q needed to achieve great power efficiencies and on-chip EM structures (e.g., baluns). Thus, silicon designers must devise ways to work around these intrinsic device limitations to provide power-efficient and robust designs comparable to those of best III-V technologies. However, silicon-based technologies offer more integrability and significantly lower costs, allowing for switches, LNA, and PA to easily coexist in the same die, providing the possibility for a one-chip solution and reducing the need for SiP (system-in-package) or heterogeneous integration. The GaN technology used in this work is HRL Laboratories' T3 40 nm GaN HEMT (High Electron Mobility Transistor) technology on a SiC substrate, which achieves \(V_{BR}\) of 50 V, \(f_{T}\) of 220 GHz and \(f_{MAX}\) of 400 GHz with a knee voltage of \(\sim\)2 V, and \(I_{D,MAX}\) of \(\sim\)1.6 A/mm [4]. This technology will be used in a single-ended PA design (i.e., GaN PA #1), as well as a differential design (i.e., GaN PA #2).