## 4 Light Sources
Research on other carrier confinement concepts is ongoing. We, therefore, also investigate another concept based on lateral current injection as indicated in Figure 13c. This concept is already successfully applied for thin laser stacks [27]. In this case, we regrow the p- and n-doped regions after the etching of the quantum-well mesa. This demands an excellent control of the InP surface and the mesa sidewalls. First, experimental data on detectors is very encouraging [28], and within L3 MATRIX, we have confirmed that the InP membrane bonding process can co-exist with AMS ion implantation for the Si side (for E-O modulators), which makes this structure particularly promising. In addition, we have investigated QD-based active media, suitable for future applications in optical interconnects. While QDs are far less common in the industry than quantum wells and are, therefore, less developed to date, they exhibit certain properties that make them advantageous for certain SiP applications. In fact, SiP would highly benefit from integrated laser sources exhibiting a higher temperature insensitivity combined with a low threshold current. As previously shown, low-dimensional nanostructures may exhibit these properties well owing to their lower density of states and smaller active volumes [29; 30; 31]. Indeed, QD lasers with a low threshold current [32] and high-temperature insensitivity have been demonstrated in conventional InAs/GaAs diodes (not integrated on Silicon) by several groups, as for example in [33]. In addition, in recent years, significant progress is being made in integrating QDs lasers on CMOS-compatible Si and SOI substrates, either by direct growth or wafer bonding [34] techniques. These attempts have shown some very promising results, such as high-temperature CW operation up to 120 \({}^{\circ}\)C, [35] and, more recently, compact photonic crystal designs [36]. These results are very promising, but it should be noted that the high-temperature performance of these Si-based III-V lasers should still be further significantly enhanced at the needed high-temperature regime (>75 \({}^{\circ}\)C) if they are to be implemented in future DC architectures, and this is currently being intensively investigated in various settings. In addition to the performance enhancement requirements, QD-based material also exhibited certain additional challenges with respect to co-integration, which we addressed within L3 MATRIX. The first one arises due to the relatively higher refractive index of the InAs/GaAs QD material system compared to InP-based QWell materials [23; 24; 25]. This made the coupling between the III-V and Si waveguides inefficient for many of the QD III-V structures, so special designs were required. The second major challenge concerned the fact that previous QD demonstrations [29; 30; 31; 32; 33] always utilized thick gain stacks (epitaxial III-V thickness > 2 \(\upmu\)m) in order to provide sufficient material gain and low losses [37]. From the L3 MATRIX perspective, considering thin gain stacks that would be compatible with industrial production lines is highly desirable. However, for QDs, substantially reducing the cladding width was especially challenging due to their lower modal gain as compared to QWells. This means that a very high degree of QD quality and uniformity must be achieved to overcome the additional free carrier absorption losses when they are placed nearer to the highly doped contact layers. To address these combined challenges, we performed an integrated experimental and theoretical study, including numerical simulations of the III-V to Si coupling using the modelling software CST [38], MBE material growth and material characterization. Initial simulations demonstrated that the coupling efficiency of the conventional stack, in which GaAs intermediate barriers are placed between successively grown QD layers, was very poor. Therefore the barrier material had to be replaced with ternary Al\({}_{\text{x}}\)Ga\({}_{(1-\text{x})}\)As to lower the refractive index of the III-V waveguide (Figure 14).