# The Challenges of Advanced CMOS Process from 2D to 3D
## 3 Process Integration of New Transistor Architecture
### Stress Measurements in Nano-Scaled Transistors  
The stress in nano-scaled transistors can be measured by Nano-beam diffraction (NBD) technique in high-resolution transmission electron microscope (HRTEM). The diffraction pattern from the selected areas varies depending on the stress amount and the analysis can be performed in combination with True Crystal program package. In NBD analysis, the interplanar distance of (220) planes is measured and later compared by the calculated data. Afterwards, the stress amount (\(\varepsilon\)) is transformed into the strain (\(\sigma\)) by using the relationship: \(\varepsilon=\sigma/E\) where \(E\) is Young's Modulus. As an example, Figure 8 illustrates the NBD images from a 22 nm planar transistor with atomic layer deposition tungsten (ALD W) metal gate formed by B\({}_{2}\)H\({}_{6}\) doping source. The analysis was performed by a nano beam on the metal gate, channel and the body regions of a transistor. The diffraction images from the metal gate materials illustrate a pattern with weak intensity which is a sign of poor polycrystalline or likely an amorphous phase. The strain in the channel region is estimated to \(\sim\)0.5 GPa [52]. It is important to note that a careful sample preparation is necessary since the stress may partially relax during the ion milling or any other mechanical force. This problem becomes a real challenge to prepare 3D FinFET samples for strain analysis by HRTEM. Another method to measure stress (or strain) is X-ray diffraction (XRD). This technique applies scanning of incident beam (\(\omega\) angle) and the detector follows to detect the diffracted beam (angle \(2\theta\)) in a configuration so called \(\omega-2\theta\) rocking curve (RC) scans. The Si substrate and SiGe layer satisfy the Bragg law condition for a certain \(\omega\) and \(2\theta\) resulting in peaks [53]. The strain can be determined from the split of the peaks. A more accurate strain measurement can be performed by using high-resolution reciprocal lattice map (HRRLM) where the misfit in-parallel and perpendicular to the growth direction (\(f_{//}\) and \(f_{\perp}\), respectively) can be obtained. The position of Si and SiGe peaks in the reciprocal space are the parameters which are obtained from HRRLMs and are used to calculate the misfit parameters. Due to a limited X-ray spot size the strain measurements provide a mean value over an array of transistors rather than individual transistor compared to HRTEM analysis [54]. HRRLMs have been widely used to determine the boron concentration in SiGe or Si as well as strain relaxation in process line [54; 55]. The analysis can reveal the formation of silicides in S/D regions  
Figure 8: Nano-beam diffraction (NBD) micrographs from metal gate, channel and the body regions of a 22 nm planar transistor [52]. (for the reducing contact resistance) results in strain relaxation in SiGe layers [56]. This is because of the silicide formation generates significant amount of point defects during the consumption of Si atoms. During the silicide formation, the Ge atoms diffuse out and create a SiGe layer with rich Ge content beneath the silicide layer. As a consequence, the strain in SiGe beneath the silicide layer partially relaxes. A remedy to this problem is the growth of a Si sacrificial layer [57]. As an example, Figure 9a-c show three HRRLMs around (113) reflection from chips containing arrays of 22 nm planar transistors with intrinsic Si\({}_{0.65}\)Ge\({}_{0.35}\), B-doped Si\({}_{0.65}\)Ge\({}_{0.35}\) and B-doped Si\({}_{0.65}\)Ge\({}_{0.35}\)/NiSiGe in S/D regions, respectively [49]. The silicide layer has been formed on a sacrificial SiGe layer with lower Ge content (20%). In Figure 9a, both Si and SiGe peaks are aligned along \(K_{\perp}\) direction showing a minor strain relaxation in SiGe layer. Meanwhile, in Figure 9b, there is a shift of B-doped SiGe peak compared to intrinsic ones in Figure 9a.