# Design and Performance Analysis of Hardware Realization of 3 GPP Physical Layer for 5G Cell Search
## 3 Downlink Transmitter PHY for CS  
In this section, we present the design details and architecture of the downlink transmitter PHY for CS. As shown in Figure 2, the PHY consists of multiple scheduling and baseband signal processing tasks such as frame scheduler, SS scheduler, SS generation, 4096-IFFT, CP addition, and windowing or filtering. Among them, the last three blocks perform convectional OFDM modulation and are designed using FFT and filter IPs shared publicly by AMD-Xilinx. As discussed in Section 2, the CP size depends on the location of the OFDM symbol in a slot, and hence, slot and OFDM symbol indexes are given as input to the CP addition block. SS scheduler is the most important unit of the CS PHY and it is responsible for generating the stream of OFDM symbols with embedded SS sig  
Figure 2: Block diagram of CS transmitter PHY. and frequency locations as shown in Figure 1. The SS scheduler mainly consists of a frame scheduler, generation blocks for PSS, SSS, DMRS, and PBCH, memory to store one instance of SS and a resource mapper. The output of the SS scheduler is modulated using OFDM modulation. The 5G frame scheduler block is designed to generate multiple signals to keep track of frame, sub-frame, slot, and OFDM boundaries. This is done using a modulus-4096 counter which is configured by the MAC layer. At the end of each cycle of this counter, the OFDM symbol index is incremented by 1. OFDM symbol index is tracked using the Modulus-14 counter and at the end of its cycle, the slot index is incremented by 1. In this way, slot index, sub-frame index, and frame index are generated using modulus-2, modulus-10, and modulus-1024 counters, respectively. The frame scheduler also generates the SS index, \(SS_{i}\), to generate appropriate SS signals and keep track of active SS transmission. The \(SS_{i}\) is calculated using the OFDM symbol and frame indices as discussed in Section 2. The final task of the frame scheduler is to generate the address generator so that 960 symbols corresponding to an upcoming instance of SS are stored in the memory. It is designed using a modulus-960 counter as shown in Figure 2. Though each counter is shown as an independent unit in Figure 2, all counters are carefully implemented to maximize the shared hardware reuse and counters are synchronized so that the signals are generated as per the 3 GPP timing requirements. For SS generation, PCI and GSCN values are configured by the MAC layer in the internal register via the AXI-Lite interface. The first sub-block is the PSS generator which outputs a 127-length binary phase shift key (BPSK) modulated sequence for a given PCI. It is based on the 3 GPP specification in [16] and given by  
\[\text{PSS}(n)=1-2\text{PSS}_{ref}((n+43N_{ID}^{Cell}\%3)\%127)\quad n\in\{0,1,\ldots,126\} \tag{1}\]  
where  
\[\text{PSS}_{ref}(i+7)=[\text{PSS}_{ref}(i+4)+\text{PSS}_{ref}(i)]\%2\quad i \in\{0,1,\ldots,126\} \tag{2}\]  
Here, \(\text{PSS}_{ref}(6:0)\) = {1,1,1,0,1,1,0}. The first step is to obtain a reference PSS binary sequence, \(\text{PSS}_{ref}\) of 127 length, using the first seven fixed bits. As shown in (1), \((i+7)\)th bit of the \(\text{PSS}_{ref}\) depends on the \((i+4)\)th and \((i)\)th bits. Since \(\text{PSS}_{ref}\) is fixed, we can pre-calculate it and store it in the memory as shown in Figure 3. Thereafter, PSS is obtained by reading the reference PSS sequence in the particular order, and this order is based on the input PCI, \(N_{ID}^{Cell}\) as shown in Figure 3. For instance, when \(N_{ID}^{Cell}=0\), PSS is BPSK modulated version of \(\text{PSS}_{ref}\) since \(X=0\) and for \(N_{ID}^{Cell}=1\), PSS is BPSK modulated version of 1-bit shifted version of the \(\text{PSS}_{ref}\) since \(X=1\). Also, the modulus by three operations indicates that there are three different PSS sequences.