## 3 System Design  
### High Sensitivity GNSS Receiver Architecture  
The HS-GNSS receiver outlined in this paper is implemented using the SoC-FPGA receiver architecture presented in [21]. Comprehensive details of the proposed architecture can be found in the same reference, with only a brief overview provided here. This section primarily focuses on detailing the design aspects of the receiver that contribute to its high-sensitivity capabilities. Figure 1 shows a block diagram of the receiver architecture. The receiver is implemented in an SoC FPGA, which is internally divided into Programmable Logic (PL) and a Processing System (PS). The PL consists of FPGA logic, while the PS houses an embedded processor. The FPGA receives incoming samples from the Radio Frequency Front End (RFFE) and implements a hardware accelerator for the acquisition process, as well as multiple hardware accelerators for the tracking multicorrelation tasks. The embedded processor executes GNSS-SDR, a widely recognized open-source software-defined GNSS receiver available online [25; 26]. GNSS-SDR operates on an embedded GNU/Linux Operating System (OS) and controls the hardware accelerators in real-time. It implements various receiver channels, which encapsulate acquisition, tracking, and telemetry decoder blocks. The acquisition and tracking blocks in the software receiver offload part of the acquisition and tracking processes to the FPGA, enabling the execution of the GNSS engine in an embedded processor. GNSS-SDR handles the hardware accelerators in the FPGA using memory-mapped registers and interrupt request lines going from the hardware accelerators to the embedded processor. Additionally, GNSS-SDR computes the observables and the Position, Velocity, and Time (PVT) solutions. The observables include pseudorange, carrier phase, and Doppler shifts. The SoC FPGA architecture and design methodology is explained in detail in [21]. The GNSS-SDR software receiver is explained in detail in [25; 26]. Figure 1: Block diagram of the SoC-FPGA GNSS receiver architecture. The proposed HS-GNSS receiver prototype is based on Advanced Micro Devices' (AMD) ZCU102 development board [27], featuring an AMD Zynq UltraScale+ XCZU9 EG-2 FFVB1156 All-Programmable Multi-Processor SoC (MPSoC) [28]. A block diagram of the concept demonstrator is shown in Figure 2. The XCZU9 EG MPSoC features Programmable Logic (PL) equipped with 600k logic cells and 2520 DSP slices and a Processing System (PS) that houses a Quad ARM Cortex-A53 MultiProcessor Core (MPCore) running at 1.3 GHz. It also includes several peripheral interfaces, such as a Local Area Network (LAN) interface, enabling the remote control of the receiver. The receiver incorporates an Analog Devices AD-FMCOMMS5-EBZ analog front-end [29], connected to the ZCU102 evaluation board. The AD-FMCOMMS5-EBZ includes two AD9361 Radio Frequency (RF) transceivers ([30]) covering the full 6 GHz range. Specifically, one RF transceiver is tuned to the E1/L1 frequency band, and the other is tuned to the E5a/L5 frequency band. This platform enables the implementation of a Dual-Band GNSS receiver, offering end-to-end functionality from the RF output of the antenna to real-time generation of navigation products on a portable board. The receiver uses a Tallysman TW8825 antenna ([31]), which provides dual-band GPS L1/L5, GLONASS G1, Galileo E1/E5a, and BeiDou B1 coverage. The local oscillator included with the AD-FMCOMMS5-EBZ board, an RXO3225M IC crystal by Rakon clocked at 40 MHz, has a stability of \(\pm\)25 parts per million (ppm), which is insufficient for GNSS signal processing. Therefore, an external oscillator is needed. The proposed receiver implementation was tested using two external oscillators: a TCXO and an OCXO. The selected TCXO was the AST3 TQ-50 by Abracon, in its 40 MHz version [32]. This device features a frequency stability of \(\pm\)50 parts per billion (ppb) over a temperature range of \(-\)40 \({}^{\circ}\)C to +85 \({}^{\circ}\)C, making it well-suited for GNSS applications.