# MAToC: A Novel Match-Action Table Architecture on Corundum for 8 \(\times\) 25G Networking
## 6 Conclusions  
In this paper, we propose MAToC as a high throughput, low latency, MAT-based packet processing scheme for 200 Gbps network based on the open source NIC Corundum. Moreover, we also design a full-featured, low latency TCAM based on FracTCAM and a compact frame merging deparaser, supporting the merger of two variable length frames. Performance and resource utilization are also analyzed in detail. The throughput test shows that MAToC has realized line rate processing and IP forwarding for packets larger than 76 bytes. The overall latency of the processing pipeline is 19 clock cycles that results in 76 ns using a 250 MHz clock signal.  
There are two major limitations to this design. One is that the processing capability cannot cope with small packets. One possible solution is to increase the clock rate for the entire application block, which would also bring the challenge of timing closure. The asynchronous crossing between different clock domains is addressed by an asynchronous FIFO buffer in this project. It is built from the dedicated logic in block RAM, which can provide two accessing ports for asynchronous read and write. The speed should be high enough that the pipeline can handle the smallest packets of 64 bytes at line rate. For a board  
\begin{table}
\begin{tabular}{c c} \hline \hline
**Module** & **Latency (Cycle)** \\ \hline Adapter ahead & 4 \\ \hline Parser & 1 \\ Multiplex & 1 \\ Match Stage & 4 \\ Action Stage & 5 \\ Demultiplexer & 1 \\ Deparser & 1 \\ Adapter after & 1 \\ Switch & 1 \\ Total & 19 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Latency.  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Resources** & **Number** & **Percentage \%** \\ \hline LUT as logic & 76453 & 14.63 \\ \hline LUT as Memory & 3640 & 1.64 \\ Block RAM & 72 & 7.33 \\ Flip-Flops & 73537 & 7.03 \\ CARRY8 & 57 & 0.09 \\ F7 Muxes & 6595 & 2.52 \\ F8 Muxes & 2406 & 1.84 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Utilization.  
Figure 7: Utilization of deparisers in different variation range.  
with eight ports in 25 GBASE-R, the total throughput is about 200 Gbps. The lower bound on the clock rate is the total throughput divided by the sum of IFG, preamble and packet length, which is approximately 300 MHz. The other limitation is that TCAM cannot be implemented in a larger size due to limited resources and timing issues. We plan to design a multi-layer match table that uses on-board DDRs, which have much more capacity and longer latency than the memory for FPGA. This will be a future work.  
Conceptualization, Z.G. and X.C.; methodology, implementation and validation, J.L; writing-original draft preparation: J.L.; writing-review and editing, Z.G., X.C. and J.L.; supervision, Z.G. All authors have read and agreed to the published version of the manuscript.  
This work was supported by Strategic Leadership Project of Chinese Academy of Sciences: SEANET Technology Standardization Research and System Development (Project No. XDC02070100) and IACAS Frontier Exploration Project (Project No. QYTS202006).  
The authors would like to thank the reviewers for their valuable feedback. The authors also would like to thank [PERSON] for his helpful comments.  
The authors declare no conflict of interest.