# An 8 kb RRAM-Based Nonvolatile SRAM with Pre-Decoding and Fast Storage/Restoration Time
## 4 Experimental Results  
The memory cell and array are the core of the whole nvSRAM. Additionally, the control voltage of the memory cell must first be determined, so as to design the peripheral circuit. The proposed nvSRAM was fabricated using a 28 nm 1P9M CMOS process. The material of the RRAM was Ti/Al\({}_{2}\)O\({}_{3}\)/HfO\({}_{2}\), and its size was 110 nm \(\times\) 110 nm with a three-layer structure. The test was performed separately for 1T1R RRAM and nvSRAM [31]. Figure 11 shows a micrograph of all test chips. The nvSRAM die and test environment are  
Figure 10: RWL driving circuit. Figure 9: RRAM read/write drive circuit. To more accurately test the conditions of the set and reset operations of RRAM with 1T1R structure, a pulse mode is used. Then, RRAM in different dies was tested with the cycle test, and the current distribution of high/low resistance was counted. Figure 13(a) is the original data of cycle test. The current of the RRAM was about 15 \(\upmu\)A when the resistance was low and about 5 \(\upmu\)A when the resistance was high. At the same time, there were few resistance differences. Figure 13(b) shows the current distribution after removing the data with high-resistance current greater than 8 \(\upmu\)A and low-resistance current lower than 15 \(\upmu\)A, respectively. Figure 13(c) shows the current distribution after removing the data with high-resistance current greater than 5 \(\upmu\)A and low-resistance current lower than 13 \(\upmu\)A, respectively. The current distribution diagram was transformed into the corresponding resistance value distribution, as shown in Figure 15. It can be seen from the distribution of resistance values that 90% of the resistance values of high resistance and low resistance were about 10 times the resistance of the window, and the data had good stability. Figure 13: DC test results for 1T1R RRAM: (a) 20 cycles (current:100 \(\upmu\)A); (b) 10 cycles (current: 150 \(\upmu\)A); (c) 10 cycles (current: 200 \(\upmu\)A). Figure 14: Pulse test results for 1T1R RRAM: (**a**) original data; (**b**) the data after removing the data of high-resistance current greater than 8 \(\mu\)A and low-resistance current lower than 15 \(\mu\)A; (**c**) data with high-resistance current greater than 5 \(\mu\)A and low-resistance current lower than 13 \(\mu\)A after data removal. At room temperature, the resistance values of 1024 bit HR and LR were counted, respectively, as shown in Figure 16. The average value of HR was 94.7 K, and the average value of LR was 12.7 K. The resistance windows of HR and LR indicated that the RRAM had good storage characteristics. From the DC test results for the RRAM, it was determined that when a separate RRAM performed a set operation, a voltage of about 0.7 V was required to complete the set operation, and the voltage for the reset was 0.9 V. According to the test results for the 1T1R RRAM, when VWL = 1.5 V, the set voltage was 1.3 V, the current limit was 100 \(\upmu\)A, and the reset voltage was 1.5 V. Based on above data analysis, and considering the influence of signal loss, the basic principle of circuit design in this paper was that the Vset and Vreset voltages of the RRAM were 1.6 V, and the voltage of VWL was controlled by a separate RWL driving circuit. Based on the VTC test method, the noise margin of the memory cell was as shown in Figure 17. When the power supply voltage was 0.9 V, the static noise margin (SNM) was 0.35 V, read noise margin (RNM) 0.16 V, and write noise margin (WNM) 0.41 V. After adding the 1T1R RRAM, the memory cell still had good data anti-interference ability. Figure 16: Distribution of HR and LR values. Figure 15: Resistance distribution diagram of RRAM. The simulation results for the data storage and restoration circuit are shown in Figure 18. First, a data 0 is written into the selected memory cell through the write mode of the SRAM. When the system fails, nvSRAM enters the data storage mode.