# Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS
## 3 Execution Models for Multicore RTOS
### Multicore RTOS for Avionics Systems  
In this study, we used VxWorks 653 (version 3.1, Wind River, Alameda, CA, USA, 2019) [31], a commercial RTOS applied in aircraft, such as the Boeing 787 Dreamliner. The structure of the OS is shown in Figure 6.VxWorks 653 is an AMP system. In AMP systems, each core operates independently and is also applied for robust execution in multicore avionics systems [1,2]. However, since each core shares memory, interference can occur between the cores despite using the AMP system.  
VxWorks 653 is a hypervisor-based multicore OS called module operating system (MOS) [31], as shown in Figure 6. This OS is an AMP system; therefore it allocates the MOS for each core. The MOS runs in privileged mode, providing spatial and temporal separation of the system. The MOS consists of an MMU manager and a TLB handler to allocate memory space for each partition that is executing on the hypervisor. During system initialization, the MOS determines each partition and associated scheduling information based on predefined configurations. After being initialized, the MOS operates on an event basis. When events occur such as inter-partition communications within  
\begin{table}
\begin{tabular}{c c c} \hline \hline  & \multicolumn{2}{c}{**Execution Model**} \\ \cline{2-3}  & **Time-Division Multiple Access (TDMA)** & **Acquisition Execution Restitution (AER)** \\ \hline
**Description** & \(\bullet\) Only one core runs at a time & \(\bullet\) Separates tasks into three phases (A-E-R) \\  & & - The A and R phases access the memory \\  & & - E phase operates using only the values stored in the local memory \\
**Advantage** & \(\bullet\) No interference with the use of hardware resources between tasks & \(\bullet\) Allows parallel execution between cores \\  & \(\bullet\) Code reuse is possible & \(\bullet\) Only E phase can be executed in parallel with other phases \\  & & \(\bullet\) Higher utilization than TDMA \\
**Disadvantage** & \(\bullet\) Utilization is same as the single core & \(\bullet\) Reuse of existing code is not possible \\ \hline \hline \end{tabular}
\end{table}
Table 1: Comparison of execution models.  
Figure 5: Major time frame comparison of TDMA and AER execution models.  
a core or interrupts that send messages to a partition on another core, the MOS handles the requests and calls the inter-processor interrupt (IPI). This IPI is also a significant cause of cache misses.  
Each core of the VxWorks 653 is composed of one or more partitions, as shown in Figure 6. Each partition consists of a partition operating system (POS) and one or more processes. The POS is a hypervisor guest OS and supports VxWorks 6.3. POS manages processes and provides APIs, such as buffers and blackboards, for intra-partition communication (inter-process communication). The processes are pre-allocated to the appropriate partition memory. Further, inter-process communication continues through the corresponding memory space.  
VxWorks 653 uses hierarchical scheduling for the time separation of partitions and processes in the IMA structure. The MOS of each core manages the execution time of each partition. For hierarchical scheduling, this consists of a partition scheduler and a process scheduler. The partition scheduler schedules partitions to the RR policy based on the time slice. The process scheduler applies priority-based preemptive and RR scheduling. For memory separation in VxWorks 653, the MOS allocates a predefined memory area during the initial system configuration.