# Low-Power Two-Phase Clocking Adiabatic PUF Circuit
## 5 Discussion  
We investigate the power efficiency of the proposed adiabatic PUF cell and reliability of the PUF circuit using PUF evaluation metrics (uniqueness and reliability). The supply voltage in our adiabatic PUF design has a trapezoidal shape with a time-ramped voltage of \(\tau\), which aids in achieving a high energy efficiency and simultaneously improving the reliability [35] to overcome authentication and piracy issues in cryptographic devices. Reliability of the proposed PUF was examined through Monte Carlo simulation-based temperature variations, and uniqueness was evaluated using CMOS process (V\({}_{\text{TH}}\) and T\({}_{\text{OX}}\)) variations. The proposed adiabatic PUF is designed based on the SRAM cell topology, which is technically utilized for cryptographic key generation (a weak PUF model) [4]. To balance the PUF logic for constant charging and discharging processes, the challenge bit is driven by the static CMOS inverter transistors (P1 and N1 in Figure 3a). In addition, to lower the peak of supply current traces, the evaluation transistor N4 (Figure 3a) is inserted to control the current flowing to the ground, resulting in a low peak current, as shown in Figure 14.  
Figure 12: Uniqueness of the proposed adiabatic PUF (labeled as Prop.) versus QUALPUF under the V\({}_{\text{TH}}\) variation (4-bit PUF). Figure 13: Reliability of the proposed adiabatic PUF (labeled as Prop.) versus QUALPUF under the V\({}_{\text{TH}}\) variation (4-bit PUF). The challenge-response pairs occur through pull-up networks, as shown in Figure 4b, in which the network is established by PMOS transistors. Additionally, we investigated the body effects of PMOS transistors. In our simulation, the bulk of PMOSs are tied to Vdd (constant voltage), Vpc power clock, and source of each PMOS (Figure 3a). Simulation results confirmed that the proposed adiabatic PUF cell consumes low energy when all the PMOS bulks are connected to Vpc, as shown in Figure 8. However, the output logic \"0\" level remains at a voltage \(\geq\) VTHN in this connection model, which affects the logic function in further cascaded large scale integrated (LSI) circuits. To avoid this phenomenon, a proper connection method is established by connecting the bulk of each PMOS to each drain, thereby reducing the output logic \"0\" level to below VTHN, as indicated in Figure 5b. We confirmed this connection method using a CMOS buffer circuit, which yielded stable input-output logic functions (stable as logic \"1\" (or 1.8 V) and \"0\" (or 0 V)). Table 2 summarizes the merits of the proposed adiabatic PUF in comparison with the PUFs presented in previous studies. The PUF circuits introduced in [29; 32] were considered as the benchmarks for comparison purposes because they implemented the same technology and both adopted an adiabatic logic topology. The energy values (f)/bit/cycle) listed in Table 2 were taken from the power supply of Vpc (with clock frequency \(f_{\text{Vpc}}\) = 100 MHz) during one period of Cb cycle (10 MHz). Moreover, the average energy and PUF start-up power values of [PERSON] [29] and [PERSON] [32] are identical because they investigated the same PUF circuit topology (QUALPUF). Table 2 presents that the proposed adiabatic PUF cell reduces energy by approximately 59% and enables safe start-up power of the SRAM PUF behavior by approximately 85%, compared to the conventional QUALPUF cell. \begin{table}
\begin{tabular}{l l l l} \hline \hline
**PUF** & **[PERSON] [29]** & **[PERSON] [32]** & **This Work** \\ \hline Year & 2016 & 2019 & 2021 \\ Topology & Adiabatic SRAM & Adiabatic SRAM & Adiabatic SRAM \\ Transistor-number/bit & 5 & 5 & 7 \\ Process (nm) & 180 & 180 & 180 \\ Start-Up power (u\(W\)) & 3.08 & 3.08 & 0.47 \\ Energy (f)/bit/cycle) & 39.18 & 39.18 & 15.98 \\ Uniqueness (\%) & 40.50 & 47.58 & 49.82 \\ Reliability (\%) & 96.20 & 95.10 & 99.47 \\ \hline \hline \end{tabular}
\end{table}