# Mdpj _sciences_
## 1 Introduction  
With the evolution of Moore's Law, the feature of the semiconductor device continues to shrink [1]. It is essential to reduce the edge placement error (EPE) to maintain the performance and high yield of a device [2; 3]. EPE serves as a metric for quantifying the fidelity of lithography technology and the EPE budget decreases with the iteration of the logic node [4; 5; 6]. EPE is a combination of critical dimension (CD) errors and overlay errors [5; 6; 7]. With the increase of the process complexity, more space has been reserved for components such as optical proximity error and photon and resist stochastics [5]. In particular, for the most advanced node (e.g., EUV lithography), typically, EPE is dominated by stochastics (>50%) [3; 8]. In contrast, the overlay consumption decreases from 34% (for 9-13 nm logic nodes) to 21% (for 5-7 nm logic nodes) of the EPE budget [2; 6]. Therefore, the improvement of overlay performance is an efficient approach to reducing EPE. Overlay refers to the alignment deviation of the patterns between different layers, which has a significant impact on the quality of integrated circuits (e.g., short circuits and open circuits) [9]. For single exposure, the overlay budget typically amounts to a quarter of the half pitch, while for double patterning, the overlay budget is one-sixth of the half pitch [5]. Currently, the accuracy required for measuring overlay needs to meet the demand of the sub-nanometer level for chip manufacturing [10]. The control of overlay mainly involves three steps: alignment, after-development inspection (ADI), and after-etch inspection (AEI) [11]. The sampling requirement for ADI is relatively high (~4 wafers per lot, with 800 measurement points per wafer); the sampling requirement for AEI is slightly low (~2 wafers measured within a few days, with 10\({}^{4}\) measurement points oneach wafer) [12]. Overlay metrology can be used to detect unwanted positional shifts and process variation between layers. It is an important part of the process control in advanced semiconductor manufacturing [13]. To ensure high yield, inline metrology is crucial in high-volume manufacturing (HVM) [14]. HVM overlay advanced process control is mainly based on optical metrology at the ADI step, such as imaging-based overlay (IBO) and diffraction-based overlay (DBO) [15]. In addition, a high-voltage scanning electron microscope (SEM) was used at the ADI and AEI steps, as well as AEI in die overlay measurement [15; 16]. However, SEM has the problem of low throughput and destructive testing. IBO has played a crucial role in overlay metrology, but it faces numerous challenges [17]. DBO is receiving the most attention because of its superior measurement accuracy [18; 19]. Various methods have been proposed for DBO, such as multi-wavelength measurement [20] and DBO target design (e.g., \(\mu\)DBO and cDBO) [21]. DBO is traditionally performed by measuring the interference signal of the \(\pm\)1 st diffraction order light that is diffracted by the top and bottom structures to obtain the value of overlay [22]. The accuracy of the overlay could be influenced by the asymmetry of the overlay target [13; 23]. It is essential to decouple the overlay target asymmetry from the wafer deformation, ensuring that overlay metrology is free from the influence of process-induced asymmetry (e.g., grating asymmetry and grating imbalance) [6]. Optimizing overlay target design is an accepted way to reduce the impact of the process (e.g., etching, deposition, and chemical mechanical polishing) [13; 24]. This method is designed before exposure and process-induced asymmetric deformation of the overlay target occurs often. Therefore, it is significant in improving the measurement accuracy for the asymmetric grating that is produced after exposure. Herein, we use an asymmetric grating as a model and demonstrate that using high-diffraction-order light can mitigate the measurement impact of asymmetric grating.