## 3 Proposed Distributed Secondary Control Technique
### Case Three: Proposed Control Capability during Constant Power Load (CPL) Variations  
The response of the proposed FDSC to CPLs is examined in this case study. The simulation was divided into four stages, as described in _case two_, and carried out for a duration of 26 s. During \(t\in[0,2)\), representing the first stage, only the droop control in each DER is activated at \(t=0\) s, with resistive load, \(R_{L1}\), \(R_{L2}\) and a CPL, \(R_{CPL1}\), connected. The proposed FDSC for all DERs is enabled at \(t=2\) s during the second stage, \(t\in(2,9)\). Another CPL, \(R_{CPL2}\), is connected to the microgrid at \(t=9\) s during the third stage, \(t\in(9,16)\) and disconnected from the common bus at \(t=16\) s during the last stage, \(t\in(16,26]\). Figures 16-18 show the results obtained from this case study, which are also \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & \multicolumn{2}{c}{**Stage 1**} & **Stage 2** & **Stage 3** & **Stage 4** \\  & \multicolumn{2}{c}{\((t\in[0,2))\)} & \multicolumn{2}{c}{\((t\in(2,9))\)} & \multicolumn{2}{c}{\((t\in(9,16))\)} & \multicolumn{2}{c}{\((t\in(16,26])\)} \\ \hline \multirow{2}{*}{DER 1} & Output Current & 6.7 A & 7.2 A & 9.6 A & 7.2 A \\ \cline{2-6}  & Output Voltage & 41.2 V & 49.5 V & 49.7 V & 49.5 V \\ \hline \multirow{2}{*}{DER 2} & Output Current & 5.7 A & 7.2 A & 9.6 A & 7.2 A \\ \cline{2-6}  & Output Voltage & 42.2 V & 50.9 V & 51.6 V & 50.9 V \\ \hline \multirow{2}{*}{DER 3} & Output Current & 5.3 A & 7.2 A & 9.6 A & 7.2 A \\ \cline{2-6}  & Output Voltage & 42.6 V & 51.6 V & 52.5 V & 51.7 V \\ \hline \multirow{2}{*}{DER 4} & Output Current & 6.2 A & 7.2 A & 9.6 A & 7.2 A \\ \cline{2-6}  & Output Voltage & 41.8 V & 50.2 V & 50.6 V & 50.2 V \\ \hline DC Bus & Output Voltage & 39.9 V & 48 V & 48 V & 48 V \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Voltage and current outputs of DERs under case two. Figure 14: Currents output of DERs under resistive load. Figure 15: Signal output of proposed FDSC under resistive load. tabulated in Tables 7 and 8. The results for the first and second stages exhibit similarities to those examined in _case one_. Figure 16 displays the output voltages of each DER and the common bus voltage. It clearly demonstrates that the droop control alone is unable to sustain the DC voltage at the common bus to its rated value in the presence of a CPL. However, during the third stage, when the new CPL, \(R_{CP12}\) was connected, a short voltage transient that attains a steady-state value of 48 V within 0.9 s, with a voltage undershoot of 6.25%, is observed at the common bus, as shown in Table 7. However, disconnecting the load from the microgrid during the fourth stage, a short transient having a voltage overshoot of 6.66% is observed. This transient dampens out quickly within 0.9 s, restoring the bus voltage to its steady state (48 V), thereby stabilizing the system. Therefore, our proposed FDSC approach maintained the bus voltage at its nominal value. In addition, from Figure 17, at the connection of \(R_{CP12}\), an abrupt step increase in output current from 4.8 A to 5.8 A and a short transient are observed. This transient has a maximum current overshoot of 8.62% with DER 1 while attaining consensus within 0.5 s. However, when \(R_{CP12}\) is disconnected, the current decreases swiftly from 5.8 A to 4.8 A with a short transient, with a minimum current undershoot of 10.4% from DER 1 while attaining consensus within 0.5 s. Therefore, it can be deduced that our proposed control approach attained and maintained the current sharing objective with the connection and disconnection of CPL and with the correction signal reacting to meet the objectives at the appropriate time, as shown in Figure 18.  
The results demonstrate that our proposed FDSC is reliable and robust under constant power load disturbances by accurately sharing the current and restoring the bus voltage in line with the capacities of the DERs operating within the MG.