## 1 Introduction  
For decades, von Neumann architecture has been the foundation of modern computing systems. However, with the explosive growth in data scale, the physical separation between the computation and memory units leads to serious energy and latency issues due to the massive data movement between them [1]. The memory wall problem has become a major constraint for developing high-performance processors, especially for data-intensive applications. Recently, computing-in-memory (CIM) technology has garnered interest as a promising method to break the memory bottleneck existing in the traditional computing architecture, which integrates the computing logics into the memory array and enables in situ data processing without extra data movements [2]. According to the previous works, CIM architecture has demonstrated great advantages in improving energy efficiency, reducing latency, and boosting parallelism [3, 4]. Distinguished from the computing paradigm, there are mainly two categories of CIM: analog CIM (ACIM) and digital CIM (DCIM) [5, 6, 7]. ACIM performs computation by applying voltage or current signals directly to the bit cells, possessing high on-chip bandwidth and computing parallelism. However, ACIM suffers from limited computingaccuracy caused by transistor variation and the analog-to-digital converter (ADC), which consumes a large area and energy overhead as well [5]. In contrast, a DCIM encodes data as discrete states and executes arithmetic through a digital logic unit inside the memory array, enabling high computing precision and versatile application scenarios [6,7]. To date, various DCIM implementations have been explored based on different memories. Static random-access memory (SRAM) is one of the most prevalent candidates for DCIM, which can achieve superior speed and flexibility owing to its mature fabrication techniques with advanced CMOS technology [8]. Nonetheless, a volatile SRAM bit cell suffers from unavoidable static power dissipation, which is caused by the leaking current. Furthermore, a basic SRAM cell contains at least six transistors (6T), incurring considerable area overhead as the array size is scaled up. In contrast, nonvolatile memories like resistive random-access memory (ReRAM), phase-change memory (PCM), and magnetoresistive random-access memory (MRAM), allow for the CIM arrays to preserve data without static power dissipation. In addition, among these emerging memories, MRAM exhibits excellent performance in terms of fast speed, high endurance, CMOS compatibility, etc., making it an ideal candidate for DCIM. MRAM based on new mechanisms has made rapid progress in CIM design. On one side, spin-transfer-torque MRAM (STT-MRAM) exhibits significant scalability with the bit cell structure of one transistor and one MTJ (1T-1 MTJ) and holds vast potential for a wide range of CIM applications. For example, [PERSON] et al. [9] proposed a tandem STT-MRAM-based CIM scheme to perform analog multiply and accumulate (MAC) operations through resistance summation of serial MTJs, acquiring a 2 Kb array size and achieving an energy efficiency of 63.7 TOPS/W for 8-bit precision. On the other side, spin-orbit-torque MRAM (SOT-MRAM), characterized by a three-terminal device (2T-1 MTJ), decouples the read-and-write path with heavy metal and offers better stability, shorter switching latency, and lower write current. [PERSON] et al. [10] constructed an optimized SOT-MRAM for weight memory and demonstrated the feasibility of implementing DNN inference with an ACIM scheme. Nevertheless, most prior research on MRAM-based CIM primarily focuses on the analog computing paradigm, while investigations into MRAM-based DCIM are still in the exploratory stages. In order to support high-precision computations (as illustrated in the above example, with precision not exceeding 8-bit), especially for floating-point (FP) computation, along with the progressively rising demand for computation accuracy in AI applications, the research into MRAM-based DCIM circuits has become more and more critical.