# Quantum Circuit-Width Reduction through Parameterisation and Specialisation
## 1 Introduction  
In recent years, research in Quantum Computing (QC) [1] has developed into a large-scale global activity aimed at creating ever more capable quantum computing hardware, as well as quantum computing applications, with the potential to revolutionise computational science. Despite this progress, current and near-future quantum computers (commonly referred to as Noisy Intermediate-Scale Quantum (NISQ)-era quantum computers [2]) are still limited in their capability. Realising the potential of quantum computers requires that certain features of quantum mechanics not available in classical computing are exploited. The potential computational benefit of quantum computers relies on information being processed while encoded in a coherent quantum state in the qubit register. In NISQ-era hardware, information is encoded in a relatively small number of qubits, with limited connectivity between qubits and a limited extent of quantum error correction techniques. Quantum error correction is needed to maintain this coherent state for a sufficiently long time so that meaningful computations can be performed. Recently, quantum computers with \(O(100)\) 'noisy' qubits (e.g., prone to significant quantum errors and decoherence) have been realised [3]. This is projected to grow to \(O(10^{4})\) or \(O(10^{5})\)[4] in the coming decade. This way, future quantum hardware with more fault-tolerance can be built, where the quantum error correction is used on the many implemented qubits to create \(O(100)\) fault-tolerant or 'functional qubits' (as termed by IBM). In addition to the challenges involved in realising quantum hardware, it is also clear that major challenges exist in devising suitable applications and algorithms for quantum computers. Theoretical aspects of quantum algorithms, as well as the implementation in terms of quantum circuits represent major research areas. A key role in developing quantum algorithms and their realisation on quantum hardware is played by quantum computing simulation on classical computing hardware. Applications requiring a number of qubits not yet available on hardware can be evaluated provided sufficient classical computing resources are available. This type of simulation also allows to evaluate for example the performance and reliability of an algorithm in the presence of simulated quantum errors. As reviewed later this section, the representation in a classical simulation of a coherent quantum state involving \(n\) qubits in its most general form requires \(2^{n}\) degrees of freedom. This characteristic forms a key aspect of the huge potential of quantum computers (\"exponential speed-ups\"). At the same time, it means that even for relatively small quantum computer applications, the classical computing resources required for simulation become excessive. For illustration, the Intel Quantum Simulator [5] was demonstrated recently for simulations using 42 qubits on a state-of-the-art supercomputing facility. Reducing the computational cost of simulating quantum circuits on classical hardware forms the main motivation of the present investigation. Specifically, the present work introduces transformations to quantum algorithms represented in terms of a quantum circuit, leading to _more compact representations_ involving fewer qubits and, thus, reduced storage needs for the simulation. Quantum circuit transformation methods represent a broad and active research area. One type of transformations map quantum circuits to specific quantum hardware. In the quantum circuit model (detailed later), quantum algorithms can be expressed in terms of quantum gate operations, such that all qubits can access all other qubits. For more limited connectivity in specific hardware configurations, a transformation of the circuit representation is then required. [PERSON] et al. [6] present a recent review of such transformations.