# A Fast Acquisition Algorithm for Hybrid Signals of 5G and BeiDou B1
## 3 Results and Discussion  
### Hybrid Signal Receiver Hardware Design  
The mainstream hardware architectures of current communication systems are based on the software defined radio (SDR) design. The hybrid signal receiver designed in this paper also follows the same principle, as shown in Figure 10, which is the hardware of the hybrid signal receiver designed in this work. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Calculation Steps** & **Multiplier Computation Cost** & **Adder Computation Cost** \\ \hline
**Downsampling** & \(\frac{2f_{\text{ds}}}{f_{s}}\) & \(\frac{2f_{\text{ds}}}{f_{s}}\) \\ \hline
**Coherent Integration** & \(2\times PMF_{-}FFT_{-}D\times PMF_{-}FFT_{-}L\) & \(2\times PMF_{-}FFT_{-}X^{2}\times PMF_{-}FFT_{-}D\) \\ \hline
**FFT** & \(2\times PMF_{-}FFT_{-}D\times PMF_{-}FFT_{-}L\) & \(3\times PMF_{-}FFT_{-}D\times PMF_{-}FFT_{-}L\) \\  & \(\times\log_{2}PMF_{-}FFT_{-}L\) & \(\times\log_{2}PMF_{-}FFT_{-}L\) \\ \hline
**Total** & \(\frac{2f_{\text{ds}}}{f_{s}}+2\times PMF_{-}FFT_{-}X^{2}\times PMF_{-}FFT_{-}D\) & \(\frac{2f_{\text{ds}}}{f_{s}}+2\times PMF_{-}FFT_{-}X^{2}\times PMF_{-}FFT_{-}D\) \\  & \(+2\times PMF_{-}FFT_{-}D\) & \(+3\times PMF_{-}FFT_{-}D\) \\  & \(\times PMF_{-}FFT_{-}L\times\log_{2}PMF_{-}FFT_{-}L\) & \(\times PMF_{-}FFT_{-}L\times\log_{2}PMF_{-}FFT_{-}L\) \\ \hline \hline \end{tabular}
\end{table} 
Table 10: SC-PMF-FFT Algorithm for computation cost analysis. \begin{table}
\begin{tabular}{c c c c c c c c c c c} \hline \hline  & \begin{tabular}{c} **Coherent** \\ **Integration** \\ **Time (ms)** \\ \end{tabular} & **Search Data** & **X** & **D** & **N** & \begin{tabular}{c} **Doppler** \\ **Range (KHz)** \\ \end{tabular} & \begin{tabular}{c} **Effective** \\ **Doppler** \\ **Range (KHz)** \\ \end{tabular} & \
\begin{tabular}{c} **Doppler** \\ **Rate (KHz)** \\ \end{tabular} &
\begin{tabular}{c} **Code** \\ **Calculation** \\ **Resolution (Hz)** \\ \end{tabular} \\ \hline B1I & 1 & 12,000 & 600 & 20 & 128 & \(-10\)\(\sim\)\(+\)\(10\) & \(-2.5\)\(\sim\)\(+2.5\) & 156.25 & 0.1705 \\ B1C & 1 & 60,000 & 600 & 100 & 128 & \(-50\)\(\sim\)\(+50\) & \(-12.5\)\(\sim\)\(+12.5\) & 781.25 & 0.1705 \\
5G n50 & 1 & 12,000 & 600 & 20 & 128 & \(-10\)\(\sim\)\(+10\) & \(-2.5\)\(\sim\)\(+2.5\) & 156.25 & 0.1705 \\ \hline \hline \end{tabular}
\end{table} 
Table 11: SC-PMF-FFT algorithm for different signal acquisition performance analysis. In the RF circuit design, a dedicated RF chip is used instead of traditional discrete devices so that the LNA, filtering, mixing, analog AGC, and other functions in traditional RF can be completed by one chip, which significantly simplifies the design and debugging difficulties of the RF part and ensures consistent receiver performance. In the baseband circuit design, using the SOPC architecture the FPGA chip replaces the traditional FPGA+DSP/ARM scheme, simplifying the design difficulty and reducing the overall power consumption. Moreover, with the SOPC architecture design methodology, the real-time signal processing and information decoding are performed by the PL and PS sides of the FPGA chip, respectively, which can bring great convenience to the baseband algorithm development and software/hardware intermodulation. In the clock circuit design, the choice of a multi-channel, low jitter, frequency, phase-adjustable clock management chip for RF, ADC sampling, and FPGA to provide a homogeneous coherent clock can ensure the baseband performance is not degraded because of the clock. The power supply circuit design uses a hybrid DC-DC and LDO chips scheme. An LDO power supply is used for power supply parts requiring low ripples, such as the clock part and RF part, and for high power requirements, such as the baseband part, a DC-DC power supply is used to balance the power supply quality and power requirements fully. Several interfaces, such as RS-232, RS-485, RS-422, CAN, and 1 PPS pulse are designed to suit different applications in the interface circuit design.