# Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices
## 4 3D NAND Reliability
### Cell Current Fluctuations
#### 4.3.2 Polysilicon Grains  
The temperature dependence of RTN in 3D NAND that can be seen in Figure 38 (left) is quite different with respect to what is reported for planar devices (see Figure 11): while RTN in planar NAND is temperature-independent, its slope decreases at higher temperatures in 3D NAND (similar dependences were also reported by [326; 327]) and affect all cells in the array (see the unique exponential distribution in 3D NAND compared to the exponential tails departing from a central Gaussian distribution in the 2D case). The explanation for the exponential distribution of the RTN \(\Delta V_{T}\) that was put forward in Section 3.2.3 ascribes such fluctuations to current percolation around the charged traps, meaning that different conduction mechanisms and/or trap locations should now be considered and reminding us that RTN remains a powerful tool for probing electron conduction in microscopic devices. In 3D NAND devices, in particular, the vertical string is usually made of polycrystalline silicon, because of the fabrication process. Such a material is composed of many single-crystal \"grains\" having different orientations, separated by grain boundaries that are highly-defective regions [328]. As a matter of fact, since its early use in analog resistors or thin-film transistors, it was recognized that polysilicon characteristics such as low-frequency noise are dominated by capture/emission at the grain boundary interfaces [329; 330]. More recently, the effect of polysilicon grain traps charging and discharging on the transient BL current has been addressed [331; 332].  
Figure 38: (**Left**) RTN cdf after cycling for a planar and a 3D NAND as a function of temperature [324]; (**Right**) \(\Delta V_{T}\) cdf for a planar and a 3D NAND [299], © 2015 IEEE. Devices are floating-gate based.  
Figure 39: Contributions to the \(V_{T}\) distribution width in planar and 3D NAND [299], © 2015 IEEE.  
A characterization of electron conduction in vertical poly-Si channels was presented in [333], comparing different technological processes and concluding that charge capture/emission from traps within the poly-Si is the main source of current fluctuations, as opposed to traps at the silicon/oxide interfaces. RTN improves for larger cells and smaller average grain size, as shown in Figure 40[326; 334] (where it was measured above the threshold). Other works also reported poor reliability and higher variability in 3D NAND for large poly-Si grain size [335; 317]. This is because the larger number of grains associated with their smaller size results in a self-averaging effect, as discussed in [336] for the case of a polysilicon gate in a planar transistor.  
These features call for a thorough analysis of the conduction mechanism in poly-Si channels, accounting for grain boundaries and related traps. The current understanding of the phenomenon is that defects at grain boundaries can trap electrons and act as percolation centers, while causing a degradation in the carrier mobility with respect to its bulk value [337; 338]. Charge transport is actually limited by the energy barriers at the grain boundaries (due to the trapped charge) rather than by transport within the grains, except for very large grain size [339]. Several works have exploited numerical simulations to investigate the effect of grain boundaries on variability in nanowires [340; 341; 342; 343; 344; 345] and 3D NAND devices [346; 347]. However, several important features of such models still have to be assessed, such as the grain size [348; 349], the density and energy distribution of grain boundary traps [350; 351], and the mobility degradation and conduction process at the grain boundaries [352; 353].