# SatEC: A 5G Satellite Edge Computing Framework Based on Microservice Architecture
## 3 System Framework
### Hardware Platform  
All nodes in the hardware platform are built in an embedded platform. A typical choice is Xilinx Zynq UltraScale+(tm) MPSoC. The nodes in the hardware platform can be divided into two types: management nodes and resource nodes. Figure 2 shows the framework of the hardware resource platform. The management node is responsible for the user access, resource management and scheduling, service deployment and management, network scheduling, and security strategy, among other functions. It is the core of the whole system. Under management node control, the resource nodes support multiple types of device access. Basic resource nodes include central processing unit (CPU) nodes, graphics processing unit (GPU) nodes, FPGA nodes, storage nodes, and network resource. Meanwhile, the resource management interface is open to the user, and users can create resource nodes of new types easily. This framework not only improves the scalability of systems significantly, but also provides a friendly interaction for users. 1. Master node: The master node is the core of the system, so it is designed with high reliability systems. Multiple control nodes are deployed in the system, and the data consistency is guaranteed by a high availability database based on the paxos protocol [40]. There is only one leader node at a time. When the leader node is unavailable for some reason, the system automatically selects a new leader from the following nodes, allowing the system to keep running. 2. Common resource node: The common resource source nodes provide common resources such as CPU, memory, and storage to the SetEC system. Considering the power consumption constraints of on-board devices, the hardware system of these nodes is made of ARM CPU, which is based  
Figure 1: The framework of 5 GsatEC. on the Reduced Instruction Set Computer (RISC) architecture. Compared with the Intel X86 processor, the ARM process has small instruction sets: the hardware logic is relatively simple. Therefore, it has fewer transistors than the X86 processor. The power consumption is consequently relatively low. Using container-based virtual technologies (such as Docker), common resource nodes can easily be used for virtualization. 3. GPU resource node: This kind of nodes provide GPU computing resources, which are mainly used in image processing, deep learning computation, and other compute-intensive applications. GPU resource nodes are based on GPU NVIDIA jetson chips. This series of chips contains several GPU cores and several ARM CPU cores. Using container virtual machines installed in the ARM CPU, the master node can control and schedule GPU resources. 4. FPGA resource nodes: This node provides FPGA computing resources for the system [41]. It is used for hardware acceleration in the fields of video/image processing, deep learning, gene detection, financial data analysis, and so on. The FPGA resource node is built on the Xilinx Zynq UltraScale + MPSoC FPGA platform, which contains multiple CPU cores and FPGA programmable logic (PL) resources. The PL logic can be dynamically reconfigured. Using container virtual machines installed in the ARM CPU, the master node can control and schedule FPGA programmable logical resources. 5. Storage resource nodes: The storage resources of SatEC are distributed in each node, and hard disks in all resource nodes can be used as storage resources in the SatEC resource platform. However, other types of resource nodes have limited storage capability. Their storage resource is mainly for their own use. The storage resource node is composed of ARM CPU and a large capacity solid-state hard disk, which is mainly used for the storage of massive data. Storage resource nodes support a variety of storage protocols: they can provide data access interfaces for files, objects, and data blocks. Database system can also be deployed in the storage resource nodes, and the database access interface is provided to the users. 6.