## 2 FM-ACSK Communication System
### Timing Recovery
At first (see Figure 9), the \(\Delta\)sync (\"err_delta_in\") signal is logically shifted left by 3 bits (multiplied by \(2^{3}=8\)) to increase its amplitude variation, after which it is integrated over the first and second half of the assumed clock timing (the early and late gate, respectively). The signal SYNC_CLK is the assumed clock, which forces the accumulator to reset each half-period. Digital integration in the simplest design consists of two parts--the N bit accumulator and the division by \(2^{\text{N}}\). The accumulator in the present design accumulates approximately \(2^{12}\) samples (this may slightly vary due to the SYNC_CLK phase adjustments in the feedback loop); hence, the accumulated signal is arithmetically (keeping the sign) right-shifted by 12. The operation of bit shifting takes practically no hardware resources, while division with a variable number would require quite a lot of hardware resources, so accuracy in this case has been slightly subdued for the sake of efficient usage of FPGA resources. A simple, but partial way of obtaining the timing error would be as follows:  
\[\text{{partial}}\text{{timing}}\text{{error}}=|E|-|L|, \tag{5}\]  
where E is the early gate's registered value and L is the late gate's value. However, when applied to the \(\Delta\)sync signal, (5) will only give useful results for timing phase errors below 25% of the symbol length. Meanwhile, the maximum timing error occurs at a shift equal to 50% of the symbol length--if such a shift occurs on the region where \(\Delta\)sync changes its sign, (5) results in a near-zero value. To make this TED implementation viable across all possible timing shifts, the timing error is obtained in two steps, calculating the timing phase shift magnitude and direction separately:  
\[\text{{timing}}\text{{error}}=|E-L|\times sign(|E|-|L|). \tag{6}\]  
When both gate integration results are being registered and compared, a slightly modified approach than that of (6) is used to turn the timing error into phase adjustment information, as well as scale the magnitude of the required phase adjustment step:  
\[\text{{PHASE\_ADJUST}}=2^{6}\times|E-L|\times sign(|L|-|E|). \tag{7}\]  
The scaling (\(2^{6}\)) directly affects the performance of the early-late gate timing synchronizer, as it defines the magnitude of the phase adjustments for each SYNC_CLK period. Too large a scaling number could \"jump over\" the desired phase, resulting in timing error oscillation and increases in gate integration inaccuracies. On the other side, too small a  
Figure 8: Early–late gate timing error detection method, which compares early and late gate accumulations for \(\Delta\)sync signal at various assumed clock phases for case when received bit “1” is in between bits “0”. Green and red areas visualize the amount of positive and negative values, respectively. scaling number would make the timing recovery too slow. The chosen number empirically shows a better-balanced performance than other bit shift values. The PHASE_ADJUST signal is used to adjust the output phase of a free-running 12-bit counter, which is responsible for SYNC_CLK signal generation. Another 13-bit counter is used to prevent SYNC_CLK from alternating too soon in cases when the phase jumps forward, but fewer than 2048 samples have passed since the last alteration. The obtained phase clock is passed along to the bit detector module, which is described next.