## 5 Simulation Results  
In this section, the simulation results from the encoding, the interleaving and the sample substitute policy described in the previous sections will be presented for a diversity of data sparseness degrees and substituted samples. The system has been described in MATLAB and includes all the OFDM stages that have been described by Figure 1. The input to the FEC encoder at the transmitter is a data packet of 1536 bits and the RSC encoder described in Section 3 that is used as the FEC encoder of Figure 1 generates 1536 parity bits mapped to 384 data and 384 parity 16-QAM symbols by the \(Q\)-QAM modulator (\(Q=16\)). The interleaver of Figure 1 is a simple 4-bit reordering unit. No channel interleaver is used. Four pilots are inserted (by the Pilot Symbol Insertion module of Figure 1) at the beginning of segments that contain 192 data and parity 16-QAM symbols placed either as described in Figure 3b or Figure 3c so that the data symbols are always placed in odd positions. The resulting packet contains 772 symbols padded (by the Guard Insertion module of Figure 1) with 96 symbols at the beginning and 156 at the end in order to form a 1024 symbol input for the Inverse DFT module of the transmitter. A 25% cyclic prefix (CP) is appended at the output of the IDFT before transmitting the packet over the AWGN channel and this CP is simply ignored at the receiver (CP removal module of Figure 1). For this reason, the size of the CP is not critical in the simulations. The function of (a) the Digital Control of Sampling Speed and Sample Replacement, (b) the ADC, and (c) the Buffer modules at the receiver are simulated as follows: a different number of samples are substituted at the receiver (256, 128, 86 or 64, _etc._) before the DFT operation (implemented with the standard MATLAB FFT function) in order to test the efficiency of the proposed undersampling method. The samples that are substituted by others correspond to the ones that would have not been sampled at all in a real system during the time intervals where the ADC operates at lower speed as described in Section 3. The tested numbers of substituted samples (256, 128, 86, 64) correspond to a draft FFT memory reduction by 25%, 12.5%, 8%, or 6.25%, respectively. The implementation of the Digital Control of Sampling Speed and Sample Replacement unit could have been based on a simple Finite State Machine that would deactivate the ADC for as long as the padding symbols are received (assuming its size is known) or sample them and let the Guard Removal module of the receiver (see Figure 1) to reject them. It is clear that the first option is more efficient in terms of ADC power consumption and the Guard Removal module that appears at Figure 1 is mainly used for symmetry reasons with the transmitter. However, the known values of the padding symbols should be used by the DFT module since the DFT at the receiver should be applied to a set of 1024 symbols that include padding. If the first option is followed the DFT can assume the constant values of the padding. At the output of the DFT, the pilot symbols are removed by the Pilot Symbol Removal unit and a 16-QAM demodulation takes place. The resulting bit stream is de-interleaved and decoded either using Viterbi or Reed Solomon (RS) algorithm by the module FEC Decoder of Figure 1. The recovered data are compared to the original input of the transmitter and the BER is extracted. Figure 6 shows the Bit Error Rate (BER) against the channel SNR when averaging the BER of 10,000 packets. As can be seen from Figure 6 the error curves do not evolve smoothly in some cases especially when BER falls below \(10^{-2}\). This is owed mainly to the high sparseness of the data. For example, if the sparseness degree is less than 2% this means that the 1536-bit packets have less than 30 bits with non zero value. When SNR is high enough (e.g., 10 dB or higher) the errors are caused by the inversion of some of these non-zero bits or the inversion of their adjacent zero bits.