# A Phase Error Correction System for Bioimpedance Measurement Circuits
## 3 Experimental Results  
### Phase Error Detection before and after Compensation  
Figure 6a,b shows the phase compensation mechanism used in the proposed system outlined in this paper. To showcase the error phase, measurements were obtained before and after phase compensation.  
The output of the type II phase detector Phase-det-pulse generates a pulse of 0.184 us at 300 kHz. This pulse corresponds to the phase difference between the demodulator signal V\({}_{\text{in}}\) and the measured signal Vsense. Accordingly, applying Equation (14), this pulse width corresponds to an erroneous phase shift of approximately 19.44\({}^{\circ}\).  
\[\theta=\Delta t*f*360 \tag{14}\]  
where, f is the frequency of V\({}_{\text{in}}\).  
This value has significant clinical implications. In applications where tissue phase values serve as critical diagnostic indicators, as in cancer and bioelectrical impedance myography, a misinterpretation of such a substantial phase shift could lead to potential misdiagnoses and potentially endanger the patient [28]. Diagnostics must be interpreted with utmost precision and caution.  
However, with phase compensation feedback activated, it is worth mentioning that V\({}_{\text{in}}\) is delayed until in phase with Vsense. At this point, the Phase-det-pulse settles to zero, indicating no phase error between V\({}_{\text{in}}\) and Vsense, as illustrated in Figure 6b.  
Figure 7a shows the impedance magnitude for various resistive loads and their respective percentage errors in Figure 7b. Notably, the bandwidth consistently measures 10 kHz for all loads, beyond which the circuit performance degrades, particularly at loads greater than 1 k\(\Omega\). It is worth highlighting that phase compensation has minimal effects on the SD system's impedance magnitude.  
Figure 6: Vsense and V\({}_{\text{in}}\) before and after phase compensation. (**a**). Phase shift between Vsense and V\({}_{\text{in}}\) at 300 kHz before phase compensation. (**b**). Phase shift between Vsense and V\({}_{\text{in}}\) at 300 kHz after phase compensation.  
Figure 8 demonstrates a considerable enhancement in phase error correction, particularly at higher frequencies. In the absence of compensation, a resistive load of 5 k\(\Omega\) at 300 kHz exhibited significant phase errors of up to 38\({}^{\circ}\). Though the frequency here exceeded the optimal bandwidth limit of operation for this system at loads greater than 1 k\(\Omega\) and frequencies greater than 10 kHz, as seen in Figure 7a, it stands in contrast to the significantly reduced phase error of 17\({}^{\circ}\) observed in the SD system with compensation applied for the same load and frequency.  
While achieving the ideal correction of an erroneous phase shift to 0\({}^{\circ}\) is theoretically desirable, it may prove challenging for resistive loads due to the potential difficulty in attaining a zero imaginary output from lock-in amplifiers. The reason for this may be mixer-induced errors in the form of differential lags between inputs and offsets [22; 29; 30].  
Figure 8: Impedance phase errors for compensated and uncompensated SD systems as a function of frequency for resistive loads.  
Figure 7: (**a**) Impedance magnitude vs. frequency for resistive loads. C = compensation; NC = No compensation. (**b**) Impedance magnitude percentage error vs. frequency for resistive loads. C = compensation; NC = No compensation.