# An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder
## 4 Results and Discussion
### Implementation Results  
In this section, we evaluate the hardware resources of the proposed LDPC decoder on the FPGA platform. The design is synthesized and implemented on the Xilinx Kintex UltraScale+ FPGA by using Vivado software. We investigate a 5G LDPC code with a codeword length of 8832 bits and a code rate of \(1/2\). The decoding iteration number is set to 10, and the quantization bits \((q,\tilde{q})\) are (4, 6). The throughput computed is given by the formula [23]:  
\[T=\frac{N\times F_{\max}}{L\times n_{iter}\times n_{cyc}}[\text{Mbps}] \tag{2}\]  
Figure 10: BER performance of various LDPC decoders for the (6720, 2496), code rate \(2/3\). Figure 9: BER performance of various LDPC decoders for the (8832, 4608), code rate \(1/2\). where \(L\) is the number of decoding layers, \(n_{cyc}\) is the number of clock cycles necessary to complete one layer, \(n_{iter}\) is the maximum number of iterations, \(N\) is the codeword length, and \(F_{\text{max}}\) [MHz] is the maximum operating frequency. The proposed 5G LDPC decoder achieves a throughput of 2.82 Gbps while decoding a code with code length \(N=8832\) bits, \(L=24\) layers at a code rate \(1/2\). The decoding iteration number is set to 10 and the number of clock cycles per layer is 2. Since LDPC decoder designs have varying implementation characteristics such as code length, quantization bits, algorithm, and iteration number, the performance normalization is required for a fair comparison. Therefore, the Hardware Usage Efficiency (HUE) parameter is used. The HUE metric is defined as the hardware resources needed for each layer of the base matrix to produce a throughput of 1 Mbps. It is measured in hardware resources/layer/Mbps. A lower HUE value implies a better hardware-efficient design. The HUE metric is calculated as follows [23]:  
\[\text{HUE}=\frac{H_{u}}{L\times T} \tag{3}\]  
where \(L\) is the number of decoding layers, \(T\) [Mbps] is the throughput, and \(H_{u}\) reflects the FPGA hardware utilization, which is the number of F7 MUXes, F8 MUXes, Flip-flops, LUTs, and BRAMs in bits used by the LDPC decoder. Note that, for BRAM, we need to calculate its size in bits. This means each bit of BRAM is considered to be the same weight as one flip-flop or one MUX. In Table 4, the implementation results are compared with the other related 5G designs: [21; 23; 28; 29]. \begin{table}
\begin{tabular}{l c c c c c} \hline \hline
**Specifications** & **This Work** & **2023**[23] & **2022**[29] & **2021**[28] & **2020**[21] \\ \hline FPGA Board & Xinlinx Kintex & Xinlinx Zynq & Xinlinx Virtex-7 & Xinlinx Kintex-7 & Xinlinx Kintex \\  & Ultrascale+ & Ultrascale+ & & & Ultrascale+ \\ \hline Quantization Bits & (4,6)-bit & 7-bit & 8-bit & 8-bit & 8-bit \\ \hline Throughput (Gbps) & 2.82 & 3.6–13.31 & 2.85 & 0.391–1.1 & 3.2–4.9 \\ \hline Code Length & 8832 & 10,368–26,112 & 10,368 & 3456 & 10,368–26,112 \\ \hline Expansion Factor & 192 & 384 & 384 & 384 & 384 \\ \hline Clock Frequency (MHz) & 153.5 & 128.36 & 255 & 160 & 404.8 \\ \hline Code Rate & 1/2 & 1/3–8/9 & 22/27 & 1/2–5/6 & 22/68–22/27 \\ \hline Number of Layers & 24 & 5–46 & 7 & 5–46 & 7–46 \\ \hline Number of Iterations & 10 & 10 & 11 & 8 & 10 \\ \hline Pipeline Stages & 2 & 3 & 13 & - & 13 \\ \hline Memory Size (kb) & 173.25 & 765.8 & 3888 & 7146 & 4914 \\ \hline Decoding & HOMS & SOMS & OMS & OMS & OMS \\ \hline Hardware & Utilization & 314,968 & 1,200,394 & 4,204,122 & 7,438,394 & 5,233,977 \\ \hline Memory Type & BRAM & Registers & BRAM & BRAM & BRAM \\ \hline Permutation & \multirow{2}{*}{Barel Shifter} & Bit Rotational & \multirow{2}{*}{Barel Shifter} & \multirow{2}{*}{Barel Shifter} \\ Network & & & & & \\ \hline HUE * & 4.65 & 1.96 & 20.85 & 147.54 & 23.12 \\ \hline \hline \end{tabular}  
* Hardware utilization efficiency (HUE) in hardware resources/layer/Mbps.  
\end{table} 
Table 4: Implementation results and comparison with related works.