# Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA
## 2 ECC Background over \(GF(2^{m})\)
\begin{table}
\begin{tabular}{l l l l} \hline
**I/O Pin** & **Description** & **I/O Pin** & **Description** \\ \hline clk & input clock signal & rst & input reset signal \\ ld & load data & din & load the data in 8-bit chunks \\ st & start signal & lk & load a key in 8-bit chunks \\ rp\_addr & read parameter address & wp\_addr & write parameter address \\ rw\_en & read/write parameter enable & rd1\_addr & read address one \\ rd2\_addr & read address two & wd\_addr & write data address \\ rw\_en & read/write enable & op\_sel\_1 & select first operand \\ op\_sel\_2 & select second operand & wb\_sel & select an operand for written back \\ dout & receives an output in 8-bit chunks & dn & done signal \\ \hline \end{tabular}
\end{table} 
Table 1: Description of the I/O pins and control signals of our proposed PM design. _Modular square (SQE)_. Like modular addition, the polynomial squaring in the binary field is relatively simple. Therefore, a 0-bit is required to place between two consecutive input data bits as explained in [10; 12; 17; 23]. We also used this method to implement the modular square operation. It takes two 571-bit operands as input and results in a \(2\times 571\) bit as output. Moreover, it bears one clock cycle for square implementation. _Proposed modular multiplier design_. Before describing our proposed modular multiplier architecture, it is essential to provide the frequently utilized modular multiplication approaches in the literature. According to [27], four different modular multiplication methods, i.e., (i) bit-serial, (ii) digit-serial, (iii) bit-parallel, and (iv) digit-parallel, are frequently adopted. Moreover, an open-source tool is described in [28] to generate Verilog HDL implementations of different modular multipliers (schoolbook, Booth, 2-way Karatsuba, 3-way Toom-Cook and 4-way Toom-Cook). Moreover, their tool automatically generates the synthesis scripts to facilitate the ASIC designers. Therefore, the aforesaid multiplication techniques have their unique benefits and some disadvantages as well. The bit and digit serial methods are useful for implementing the area and power-optimized circuits [15; 20]. For high-performance implementations, bit-parallel and digit-parallel multipliers are more useful [12; 16; 26; 27]. The computational cost of these multiplication approaches is different. For example, for two \(l\)-bit sizes of polynomial operands to the multiplier as input, the bit-serial methods require \(l^{2}\) cycles. The digit-serial approaches require \(\frac{l}{m}\) cycles, where \(l\) is the operands length and \(m\) is the digit size. The computational cost of digit and bit-parallel approaches is a one clock cycle with area and power overheads. There is always a tradeoff between area, power and performance. We direct readers to [27; 28] for more comprehensive comparisons over different multiplication architectures. As shown in Figure 2, we have used a bit-parallel Karatsuba multiplier for modular multiplication computations. The cause of the implementation of the Karatsuba multiplier is to achieve a throughput/area-optimized circuit for PM computation. The one clock cycle requirement of Karatsuba for one polynomial multiplication allows us to reduce the overall clock cycles, which eventually increases the throughput. The hardware resources of the Karatsuba multiplier for square and inversion computation help to decrease the overall area requirement for the ECC point multiplication, which ensures that the proposed PM architecture is well-suited for the area-optimized applications. [PERSON] follows a divide-and-conquer approach for polynomial multiplications. For example, let us have two polynomials of length \(m\)-bit. To operate the Karatsuba multiplier, the polynomials length of \(m\)-bit needs to divide into two \(\frac{m}{2}\)-bit smaller polynomials. Then, the Karatsuba multiplier operates on the smaller polynomials to generate the final polynomial.