# All-Digital Computing-in-Memory Macro Supporting FP64-Based Fused Multiply-Add Operation
## 3 The Proposed Architecture of DCIM-FF  
As shown in Figure 4, the **DCIM-FF** macro contains a 16 \(\times\) 13b memory array, a divider module, two parallel adder trees (adder_tree_1 and adder_tree_2) and a FP64 adder module. The mantissas of inputs (a, b, and c) are represented by Mant_a, Mant_b, and Mant_c, and the mantissa of output (d) is represented by Mant_d. R represents the 13b register, while operands a, b, c, and d meet the equation:  
\[\text{a}\times\text{b}+\text{c}=\text{d} \tag{2}\]  
FMA is the single-instruction execution of the formula a \(\times\) b + c. In order to map the FP64-based FMA algorithm to the digital CIM circuit, some improvements were made to this algorithm, that is, splitting the operation of a \(\times\) b into 16 multiplications and 15 additions, as shown in Figure 5; part0-part16 represent the 16 multiplication results from memory array. The 52b mantissas of inputs (a and b) are split into 13b in four parts: M0, M1, M2, and M3, respectively. A multiplication of 4 \(\times\) 4 = 16 times is required due to the multiplication of 4 split mantissa parts of input a and b. As each split mantissa part is  
Figure 3: The algorithm diagram of FMA operator. used 4 times in the 16 multiplications, each part is stored twice in a sub-CIM cell that is composed of a 13b register and a digital multiplier and is transmitted twice in the memory array, which contains 16 sub-CIM cells, to complete the 16 multiplications. Each sub-CIM cell obtains the split mantissa part as the multiplier from input a/b through the in_1 port connecting the 13b register and obtains the split mantissa part as the multiplicand from the other sub-CIM cell through the input_2 port connecting the digital multiplier. This cell outputs the split mantissa part from the 13b register to the other sub-CIM cells through the out_1 port and outputs part0-part16 to the divider module through out_2 port. In order to make the 16 outputs of the memory array meet the bit-width requirements of adder trees for input data, a divider module is placed to split 16 groups of data into 20 groups, which transforms the original required 15 additions into 18 additions. Moreover, an n \(\times\) 13b left shift is required for part0-part16 before being split in the divider module, as shown in Figure 5; a 13b left shift is required for part1; a 26b left shift is required for part2; a 39b left shift is required for part3; a 13b left shift is required for part4; a 26b left shift is required for part5; a 39b left shift is required for part6; a 52b left shift is required for part7; a 26b left shift is required for part8; a 39b left shift is required for part10; a 65b left shift is required for part12; a 52b left shift is required for part13; a 65b left shift is required for part14; and a 78b left shift is required for part15. These shifted data will become partial products. The bit-width of the longest partial product reaches 104, and large bit-width adders will be required in the adder tree if these partial products are summed directly, which consumes a lot of area. Instead, we divide each partial product into two segments (high 52b and low 52b) from the middle line, and the actual bit-width of each segment will be no more than 52. In that way, the smaller area adders are adopted to combine these partial products, and two adder trees are required to add the two sets of partial products that come from high bits and low bits, respectively. The results of that divider module are fed into two parallel adder trees, which perform those 18 additions above. Each adder tree adopts a 4-stage pipelined structure to add 10 small bit-width data into a large bit-width partial mantissa in 4 computation cycles. The mantissa of a \(\times\) b consists of the highest 56 bits and lowest 52 bits from those two adder trees, respectively. The mantissa of a \(\times\) b  
Figure 4: Illustration of the **DCIM-FF** macro.