## 3 Technology Modules
### Characterization of the Si/SiO\({}_{2}\) Interface Quality
Further measurements of the Al/SiO\({}_{2}\)/Si capacitor on \((100)\) silicon substrates show similar defect concentrations. The presented Si/SiO\({}_{2}\) interface using our CVD-deposited SiO\({}_{2}\) exhibits a similar fixed defect and interface defect concentrations as our thermally-grown high-temperature RTP layers. Furthermore, CVD processes offer a lower thermal budget, while the characterized SiO\({}_{2}\) layer indicates higher concentrations of incorporated hydrogen than thermally-grown SiO\({}_{2}\) layers. For electron spin qubit experiments, the total amount of defects within the SiO\({}_{2}\) layer can be minimized by reducing the thickness of the SiO\({}_{2}\) layer while still preserving the insulating properties. In addition, defect concentrations on the order of \(10^{10}\,\text{cm}^{-2}\) can be compensated electrostatically by applying suitable voltages to the respective gates [15]. The frequency-dependent response of the measured defects are measured up to frequencies of 1 MHz limited by the setup. Qubit manipulation experiments are typically performed with voltage signals applied to gates at a frequency of 20 GHz (electron spin resonance with an externally applied magnetic field) [21]. For increasing frequencies, the effect of defect-induced charge noise is negligible compared to Johnson noise sources. To compensate the static effect of charged interface defects, the development of a high-density gate structure in close vicinity with the interface is mandatory to preserve the necessary tunability. Figure 4: Electrical characterization of the Si/SiO\({}_{2}\) layer stack with respect to defect densities and post-metal annealing. (**a**) Schematic of a metal-oxide-semiconductor capacitor with a structured top metal electrode with an area \(L^{2}\). (**b**) Equivalent circuit of the measurement setup tuned in depletion. The device under test (DUT) is modeled by an oxide capacitance \(C_{\text{ox}}\) and a parallel capacitance \(C_{\text{it}}\) and conductance \(G_{\text{it}}\). Additional contact resistances are modeled by \(R_{\text{s}}\). The parallel capacitance \(C_{\text{P}}\) and conductance \(G_{\text{p}}\) are measured. (**c**) Measurement of Al/SiO\({}_{2}\)/Si capacitor. SiO\({}_{2}\) is deposited by CVD on a <111>oriented substrate with a measured thickness of \((17.0\pm 0.1)\) nm and an aluminum top electrode with an area of 0.52 mm\({}^{2}\). Darker curves indicate higher frequencies and lighter curves lower frequencies. The dashed curves indicate voltage backward sweeps. The red dashed line corresponds to the calculated theoretical quasi-static CV-curve. (**d**) Measurement of the parallel conductance over angular frequency \(G_{\text{p}}/\omega\) corresponding to (**c**). (**e**) Measurement of annealed Al/SiO\({}_{2}\)/Si capacitor. SiO\({}_{2}\) is deposited by CVD on a <111>oriented substrate with a measured thickness of \((16.0\pm 0.1)\) nm and an aluminum top electrode with an area of 1.05 mm\({}^{2}\). Post-metal annealing is carried out in N\({}_{2}\)H\({}_{2}\) at 400 \({}^{\circ}\)C for 30 min. (**f**) Measurement of the parallel conductance over angular frequency \(G_{\text{p}}/\omega\) corresponding to (**e**). For frequencies \(f\leq 100\) Hz, ground oscillations are visible.