# A Wideband Hybrid Envelope Tracking Supply Modulator with Slew-Rate-Enhanced Linear Amplifier
## 2 Circuit Design
### LA Design with an SRE Structure
#### 2.2.1 The Proposed SRE Circuit  
Figure 5a depicts the overall circuit of the proposed LA with the SRE circuit, which corresponds to the diagram in Figure 4. Figure 5b illustrates the concrete SRE circuit. Figure 4: Diagram of the proposed LA design with an SRE structure. Figure 5: (**a**) The entire LA circuit. (**b**) The proposed SRE circuit. In the first stage of the SRE circuit shown in Figure 5b, the input voltage difference, \(V_{INP}-V_{INN}\), is converted into the primary SRE currents, \(I_{SR1}\) and \(I_{SR2}\), as demonstrated in the subsequent derivation. For \(I_{SR1}\), it is determined by the dynamic bias voltage \(V_{SRb1}\) and the input voltage \(V_{INP}\), and the dynamic bias voltage \(V_{SRb1}\) is determined by the fixed bias current \(I_{B2}\) and the input voltage \(V_{INN}\). By observing the branch circuit composed of transistors M\({}_{1P}\) and \(M_{1N}\), we can obtain Equation (4):  
\[V_{SRb1}=V_{INN}+|V_{GS1P}|+V_{GS1N} \tag{4}\]  
where:  
\[\left\{ \begin{array}{rcl}|V_{GS1P}|&=&\sqrt{\frac{2I_{B2}}{\mu_{p}C_{ox}(W/L )_{1P}}}+|V_{thP}|\\ V_{GS1N}&=&\sqrt{\frac{2I_{B2}}{\mu_{N}C_{ox}(W/L)_{1N}}}+V_{thN}\end{array} \right. \tag{5}\]  
In Equation (4) and the following equations, \(V_{GSip}\) and \(V_{GSiN}\) are the gate-source voltages of transistors \(M_{iP}\) and \(M_{iN}\), respectively; \((W/L)_{iP}\) and \((W/L)_{iN}\) are the aspect ratios of transistors \(M_{iP}\) and \(M_{iN}\), respectively; \(\mu_{P}\) and \(\mu_{N}\) are the mobilities of electrons in PMOS transistors and NMOS transistors, respectively; \(V_{thP}\) and \(V_{thN}\) are the threshold voltages of PMOS transistors and NMOS transistors, respectively; and \(C_{ox}\) is the gate oxide capacitance per unit area. Similarly, by observing the branch circuit composed of transistors \(M_{4P}\) and \(M_{4N}\), we can obtain Equation (6):  
\[\left\{ \begin{array}{l}V_{SRb1}=V_{INP}+|V_{GS4P}|+V_{GS4N}\\ |V_{GS4P}|=\sqrt{\frac{2I_{SR1}}{\mu_{p}C_{ox}(W/L)_{4P}}}+|V_{thP}|\\ V_{GS4N}=\sqrt{\frac{2I_{SR1}}{\mu_{p}C_{ox}(W/L)_{4N}}}+V_{thN}\end{array} \right. \tag{6}\]  
Then, by substituting Equation (4) into Equation (6), we can figure out the expression of \(I_{SR1}\), as illustrated in Equation (7). \[I_{SR1}=\frac{1}{2}[\frac{1}{\sqrt{\frac{1}{\mu_{p}C_{ox}(W/L)_{4P}}}+\sqrt{ \frac{1}{\mu_{N}C_{ox}(W/L)_{4N}}}}(V_{INN}-V_{INP}+\sqrt{\frac{2I_{B2}}{\mu_{ p}C_{ox}(W/L)_{1P}}}+\sqrt{\frac{2I_{B2}}{\mu_{N}C_{ox}(W/L)_{1N}}})] \tag{7}\]  
In this design, the dimensions of the transistors satisfy the relationships: \((W/L)_{1P}=(W/L)_{2P}=(W/L)_{3P}=(W/L)_{4P}\), and \((W/L)_{1N}=(W/L)_{2N}=(W/L)_{3N}=\)(\(W/L)_{4N}\). Therefore, we can simplify Equation (7):  
\[I_{SR2}=\left\{ \begin{array}{l}\frac{1}{2}(\frac{1}{\sqrt{\frac{1}{\mu_{p} C_{ox}(W/L)_{1P}}}+\sqrt{\frac{1}{\mu_{N}C_{ox}(W/L)_{1N}}}}(V_{INN}-V_{ INP})+\sqrt{2I_{B2}})^{2},V_{INP}-V_{INN}\leq V_{A}\\ 0,V_{INP}-V_{INN}>V_{A}\end{array} \right. \tag{8}\]  
where \(V_{A}\) denotes the threshold input voltage difference of the SRE circuit:  
\[V_{A}=\sqrt{\frac{2I_{B2}}{\mu_{p}C_{ox}(W/L)_{1P}}}+\sqrt{\frac{2I_{B2}}{\mu _{N}C_{ox}(W/L)_{1N}}} \tag{9}\]  
It is worth noting that in Equation (8), when the condition \(V_{INP}-V_{INN}\leq V_{A}\) is satisfied, transistors \(M_{4P}\) and \(M_{4N}\) are operating in the saturation region. Outside this range, the transistors \(M_{4P}\) and \(M_{4N}\) are cut off, and as a result, \(I_{SR1}=0\). Similarly, we can derive the other primary SRE current, \(I_{SR2}\), as illustrated in Equation (10):\[I_{SR2}=\left\{ \begin{array}{l}\frac{1}{2}(\frac{1}{\sqrt{\frac{ \pi_{P}C_{\text{var}}(W/L)_{1\text{IP}}}{+}}}(V_{IN}-V_{IN})+\sqrt{2I_{B2}})^{2 },V_{IN}-V_{INN}\geq-V_{A}\\ 0,V_{INP}-V_{INN}<-V_{A}\end{array} \right. \tag{10}\]  
According to the calculation results, the corresponding curves of the primary SRE currents, \(I_{SR1}\) and \(I_{SR2}\), are drawn in Figure 6a. We can see, relative to the value of the quiescent bias current \(I_{B2}\), that the primary SRE currents can be very large when needed.