# A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits
## 12 Conclusions and Future Directions  
The brief survey of a set of research papers has pronounced the importance of testing SDDs and HDDs. The primary motivation for most of the research papers is the growing need for the industry to produce high-quality chips. Small and hidden delay testing, CA delay testing, and diagnosis of defects are growing research fields to reduce the DPPM. To avoid the functional failures and returns from the infield usage of chips, focusing on structural testing and enhancing it, by all means, is very much necessary. Moreover, developing test quality evaluation metrics and diagnosis algorithms for SDDs and HDDs is still an ongoing research field. Hence, the focus on this research direction can contribute to the VLSI testing industry for further progress. However, many effective techniques have evolved to detect most of the defects in the chip. But still, there are a lot of test escapes that happen. This survey will be a great insight for the researchers in the field of VLSI testing by giving a brief overview of the existing works and the progress to be explored in the future.  
By analyzing various methodologies that exist in the literature and techniques already employed in commercial EDA tools, the researchers can focus on addressing the following key issues:  
1. Addressing the challenges of FAST-based method like X handling, On-chip clock generation, and IR drop to develop a more cost-effective solution, especially for BIST, to catch reliability defects.
2. Developing a more accurate test quality metric for SDD and HDD testing by considering several other parameters like clock skew, latency, uncertainty, etc., can be a future research direction.
3. The effect of process variations and IR drop can be included as a parameter in the calculation of test quality metric to precisely evaluate the test quality.
4. The CA based testing for targeting the SDD and HDD in order to furthur reduce the DPPM can be explored by the researchers.
5. Developing more efficient diagnostic algorithms to improve diagnostic resolution can be a prospective research direction.
6. The complex manufacturing process, the multi-fin structure, and the small feature size make the FinFETs more prone to defects. If a single fin has a defect, then the high leakage current causes small delays in the circuit without actually failing the circuit [96]. Moreover, the reliability risk during in-field operations is due to the temperature increase. This finding could give researchers a new way to look at how to address these challenges in FinFETs and develop better CA-based fault modelling to reduce the DPPM.  
Conceptualization, P.M.; methodology, P.M. and S.S.; formal analysis, P.M. and S.S.; data curation, P.M.; writing--original draft preparation, P.M.; writing--review and editing, P.M. and S.S.; supervision, S.S. All authors have read and agreed to the published version of the manuscript.  
The first authour receives financial assistance from the University Grants Commission, New Delhi, India, in the form of Junior Research Fellowship. The article processing fee is funded by Vellore Institute of Technology, Vellore, and EDA tools are sponsored by Seimens EDA India.  
Not applicable.  
All the data presented in this manuscript were derived from the indicated articles, which are published in the literature and listed in the Reference section.  
**Acknowledgments:** The authors would like to acknowledge Vellore Institute of Technology, Vellore, Tamil Nadu, India, for providing all the necessary facilities for the research and Siemens India for providing necessary EDA tool support for the research.  
**Conflicts of Interest:** The authors declare no conflict of interest.