## 2 System Overview
### FPGA and Signal Processing  
In our work, the digital signal processing of the UWVLC system was designed based on the FPGA, as shown in Figure 6.  
The functions implemented by the FPGA in the system include:  
* Optical communication data is transmitted and received with raspberry PI based on the serial peripheral interface (SPI) protocol and the general purpose input/output (GPIO) port;
* The transmitting part performs Reed-Solomon (RS) encoding on the original data, and the receiving part performs RS(255,239) decoding on the 8B/10B decoded data;
* The transmitting part performs 8B/10B encoding on the RS-encoded data, and the receiving part performs 8B/10B decoding on the synchronized data.
* The transmitting part inserts a preamble and a synchronization header into the channel-encoded data; then, it performs the parallel-serial conversion and outputs it to the visible light signal transmitting circuit. The receiving part performs bit synchronization and frame synchronization on the digital binary signal after the ADC output by the visible light signal receiving circuit and outputs the 10-bit parallel signal after serial-parallel conversion.  
In the designed optical communication system, the transmitter adds the timing pulse signal for bit synchronization and the frame synchronization header sequence for frame synchronization. The bit timing pulse signal is a periodic square wave signal in which \"1\" and \"0\" appear alternately, and the time width of each \"1\" and \"0\" signal is consistent with the time width of each bit in optical communication. The frame synchronization header adopts the 16-bit Barker code with sharp autocorrelation single peak characteristics [21]. In order to ensure the sampling time is in the middle of the received signal symbols, bit synchronization is required. The function of the frame synchronization module is to identify the 16-bit frame synchronization header in a frame of data and write the following data part into the First Input First Output (FIFO) memory.  
The RS code [22] belongs to the forward error correction (FEC) method. It is a nonbinary Bose-Chaudhuri-Hocquenghem (BCH) code, and, of course, it also belongs to a cyclic code and a linear block code, which is especially suitable for dealing with burst errors. The purpose of using the RS code is to improve the reliability of channel transmission through redundant codes. In the system proposed in this paper, RS(255, 239) is used as the channel error correction code. The valid information of RS (255, 239) is 239 bits, and the check digit is 16 bits.  
In the VLC system, if the modulated sequence has continuous \"0\" or continuous \"1\" for a long time, the energy ratio of the low-frequency part in the signal will be increased, which will increase the inter-symbol interference at the receiver, leading to a poor receiving eye diagram. These problems will eventually affect the clock recovery and timing judgment of the signal. In order to avoid this situation, the DC-balanced 8B/10B coding is introduced into the system [23]. The 8B/10B encoding converts every 8 bits in the data into 10 bits for output. In each group of 10 bits output, there will be no more than 6 bits of \"1\" or \"0\", and no more than 5 consecutive \"1\" and consecutive \"0\" in the entire output data stream. By sacrificing 20% of the bit rate, 8B/10B coding ensures that the number of \"1\" and \"0\" in the entire data is balanced as much as possible. Most of the energy in the encoded data stream is concentrated in the high-frequency band, which effectively alleviates the inter-symbol interference and expands the receiving eye diagram.  
Figure 6: Schematic diagram of the FPGA data processing.