## 4 LUT-Oriented Technology Mapping  
The BDD representation of logic operations in the controller enables not only its optimization but also enables the technology mapping procedure for selected FPGA architecture. This allows for building a tool capable of delivering the synthesizable description with partially-mapped structures. The proposed implementation optimizes the logic part of the controller and enables the implementation of arithmetic operations that do not limit the implemented functionality range. In many cases, the proposed implementation is limited to logic operations only [9, 12, 13, 21]. The basis of efficient technology mapping is the division of the logic structure between configurable logic blocks (CLBs), contained within the FPGA device. These blocks perform any logic function with a limited number of \(k\) inputs. A characteristic feature of the blocks (CLB) is their configurability, thanks to which a slight modification of the \(k\) value is achieved. The core of these blocks are the LUT (look-up table) blocks, which, in the simplest case, may be directly CLB (which is especially visible, in the case of combinational circuits). The mathematical model of the division of the logic structure between logic blocks is the decomposition of a function. In the classical approach, the simplest decomposition model (simple serial decomposition) is based on the division of the decomposed function into a free function and a bound function [30, 31]. This divides the arguments of the decomposed function into free set (\(X\!f\)) and bound (\(X\!b\)). These functions are implemented in the free block and in the bound block, respectively. The key to the efficiency of the obtained division of the logic structure is to limit the number of wires between these blocks. It turns out, the number of these connections (\(p\)) corresponds to the number of bound functions (\(num\_of\_g\)) performed in the bound block. One should, therefore, strive to minimize the number of bound functions. Thus, the methodology of determining the necessary number of bound functions becomes extremely important. Depending on the method of function description, there are various methods that allow for determining this parameter. Consider a logic function described in the form of BDD (reduced ordered form-ROBDD), as shown in Figure 10A. The decomposition corresponds to the horizontal cut of the BDD diagram. Its top (above the cut line) is associated with the bound set \(X\!b=\{c,d,e\}\). On the other hand, the lower part has the free set \(X\!f=\{\text{a},\text{b}\}\). As a result, the division can be distinguished by the so-called cut nodes [32, 33], i.e., the nodes below the cutting line, to which the edges from the top of the diagram are connected. In the case at hand, two such nodes, associated with the variable \(b\), can be distinguished. To distinguish them, a single bound function (\(g\)) is required. This means that the top part of the diagram can be replaced  
Figure 9: The logic optimization of EFG—possibilities (**A**) and limitations (**B**). by a single node, associated with the bound function (_g_), as shown in Figure 10B. The logic structure associated with the considered decomposition is shown in Figure 10C. The key problem is to choose the level at which the cut has been made, and therefore, to determine the cardinality of the bound set (_card_(_Xb_)). It turns out that, from the perspective of the effective mapping of the function, the cardinality of the bound set should be equal to the number of inputs of a single logical block (_card_(_Xb_) = _k_). They assume a mapping in blocks with 3 inputs, as in Figure 10, the cut level was selected below the variable \(e\) in Figure 10A. An alternative method of performing decomposition, in the case of BDD description, is the method that uses multiple cutting BDD [34; 35]. The essence of this method is to introduce more than one horizontal cut line, which leads to the division of the BDD into slices, contained between the cut lines.