## 2 Implementation of FPGA-Based On-Board SAR Processor
### SAR Processor Implementation  
As described in Section 2.2, an SAR image-formation algorithm is a computationally intensive task that involves several complex operations and algorithms. FFT and IFFT play an important role in SAR processing, which motivates extensive study of FFT/IFFT algorithms for hardware implementation. FFT and IFFT coprocessors have been successfully developed and will be deployed in the implementation and integration of FPGA-based SAR processors [33]. The overall development of the SAR processor was based on hardware blocks described in Section 2.1. The submodules of the FFT coprocessor, IFFT coprocessor, complex multiplier and ROMs were integrated and used to implement the RDA into the Altera Stratix IV GX FPGA EP4 SGX230 KF40C2 device, which is located on the Altera DE4 development board. The overall block diagram for the hardware implementation of the FPGA-based SAR processor is illustrated in Figure 3.  
Implementation and evaluation were carried out by a full setup for the SAR processor. The baseband transmit chirp IQ signals (Channel A & B) were generated internally by the embedded SAR processor. They were converted into analog form by DAC and fed into the TX port of the RF module for transmission. The RF module mixes the IQ signals and up-converts them to the carrier band. After mixing, the signal is transmitted to the delay line, which simulates the existence of point targets, as it delays the transmitting signal. The delayed signal is returned to the RX port of the RF module and down-converted into  
Figure 2: RDA block diagram.  
an IQ baseband signal. The baseband-received signals are captured and digitised by the dual-channels analogue-to-digital-converter. This captured signal is the SAR raw data and is loaded into the proposed FPGA-based SAR processor for processing operations in order to form the SAR image.  
The captured SAR raw data with point targets is fed into the SAR processor in order to process and form an SAR image through the processing operations. Figure 4 portrays the block-diagram partitioning of the embedded FPGA-based SAR processor architecture that is implemented by instantiating the proposed FFT, IFFT, complex multiplier and ROM. Based on the specific SAR parameters, the range-reference function and the azimuth reference function are precomputed in MATLAB, and these precomputed functions are stored in the ROM of FPGA so that the matched filtering operation can be performed later.  
In Figure 4, dotted labelling represents the sections implemented in FPGA. The complex multiplier, as designed by [PERSON], is used in the implementation of the matched-filtering operation in the range of compression, as well as complex multiplication in the azimuth compression [34]. Range and azimuth compression share a similar architecture, except for the data stored in the ROMs and the transform length for FFT and IFFT. For range compression, the FFT and IFFT transform lengths are 1024 points, as every range bin consist of 1024 samples, while for azimuth compression, the FFT and IFFT transform lengths are 2048 points, as there are a total of 2048 azimuth bins.  
Figure 3: Overall block diagram for the hardware implementation of the FPGA-based SAR processor.