# JFET Integration Using a Foundry SOI Photonics Platform
## 2 JFET Design and Characteristics  
We use the IME Silicon Electronic Photonic Integration Circuit (SiEPIC) technology to achieve the photonic and electronic integration. The process is intended for the integration of passive photonic devices (waveguide, grating couplers, multiplexer, etc.) and active photonic devices (modulators, Ge photodiodes, resonators, etc.) onto a monolithic chip. Various \(n\)-type and \(p\)-type ion implants for \(pn\) junction formation used in optical modulators and epitaxial Ge photodetectors are available [9]. It starts with a sequence of selective etching, hard mask deposition, waveguide formation, ion implants for modulators and photodetectors, Ge epitaxy, Ge top implant, and ends with metal connections and bond pads. Although the process was not intended to create transistors, it occurred to us that these implants could be used to create JFETs that could be used in transimpedance amplifiers and other circuits. We estimated the doping and dimensions for each active region of the JFET based on the given implant dosages and energies, the Si film thicknesses offered by the process, and the minimum feature sizes allowed by the design rules. The implants could also be used to implement lateral bipolar junction transistors (LBJTs), but our previous experiments indicated the maximum LBT common-emitter current gain is less than unity, and therefore, these devices do not provide useful amplification [10]. The perspective view of the \(n\)-JFET structure is shown in Figure 1[3]. An \(n\)-channel device is used since the electron mobility in silicon is roughly three times that of holes. Two ohmic contacts are connected at the ends of the channel, with one acting as the source and the other as the drain. When a positive voltage is applied to the drain with respect to the source, electrons flow from the source to the drain. Two electrically connected \(p+\) regions on both sides of the channel form the gate. Here, the device width \(Z\) is 10 \(\upmu\)m, and the length \(L\) is 18 \(\upmu\)m. The gate-channel width \(2a\) is 0.8 \(\upmu\)m, and the depth \(d\) is 0.22 \(\upmu\)m. A reverse bias applied to the gate channel \(pn\) junction widens the junction depletion region, modulating the width of the undepleted channel, and hence controlling the current flow between the source and drain. SPICE model parameters were calculated using the theoretical analysis of [11]. The most significant parameters include the pinch-off voltage \(Vp\) and cut-off frequency \(f_{\mathrm{T}}\). The \(Vp\) is the gate-channel voltage at which the depletion region extends completely across the channel and the current flow between the source and drain is cut off. The cut-off frequency \(f_{\mathrm{T}}\) refers to the maximum operating frequency, above which the JFET can no longer amplify an input signal. Here, \(Vp\) and \(f_{\mathrm{T}}\) were computed using Equations (1) and (2) [11]. \[V_{p}=\Phi_{0}-\frac{qN_{D}a^{2}}{2\varepsilon_{si}} \tag{1}\]  
Figure 1: Perspective view of an NJFET. \[f_{\rm T}=\frac{g_{m}}{2\pi C}\ \leq\ \frac{g_{m}}{\left(\frac{2\pi\epsilon_{si}Z \Gamma}{2a}\right)}=\ \frac{2\mu_{n}qN_{D}a^{2}}{\pi\epsilon_{\rm si}L^{2}} \tag{2}\]  
\(\varphi_{0}\) is the built-in potential voltage, \(N_{D}\) is the doping concentration in the \(n\)-type channel, \(\epsilon_{si}\) is silicon permittivity, \(q\) is the electron charge, and g\({}_{m}\) is transconductance. According to Equation (2), an \(n\)-channel JFET is preferred for obtaining a good frequency response due to the high mobility of electrons compared to holes. Frequency response is also improved by using a short channel length. The pinch-off voltage is typically in the range of \(-1\) V to \(-5\) V for \(n\)-type JFETs [12]. Here, Equation (1) predicts a value of \(-7.7\) V at the n-type doping level specified by the IME process. The channel width was set at the minimum value of \(0.8\)\(\upmu\)m allowed by the IME layout design rules.