# Design of Nanosecond Pulse Laser Diode Array Driver Circuit for LiDAR
## 2 Circuit Principle
### Scanning Control  
Figure 8 is a circuit schematic diagram of a multiplexer, which utilizes two 4-channel multiplexer chips ADG704 from Analog Devices (ADI) (Wilmington, MA, USA) to drive an 8-channel LD. One input pulse signal (Pulse In) can be output as 8 pulse output signals (Pulse Out 0-Pulse Out 7). The NOT-gate is used to select the two ADG704 chips and form a 3-bit address (Addr2, Addr1, Addr0) together with the address pins of ADG704. Controlling the voltage levels of these three pins can determine the output channel. Since the channel switching speed of ADG704 is less than 50 ns, fast switching within a 50 ns range can be achieved.  
Figure 9 is a schematic block diagram of the scanning test circuit, which consists of a pulsed laser emission circuit, a FPGA, and a power supply. The FPGA outputs three-bit addresses (Addr2, Addr1, Addr0) to sequentially select 8 LDs to output optical pulses. The three-bit address signals are switched in sequence from 000, 001, 010, 011, 100, 101, 110, and 111. Each time an address is switched, the FPGA outputs a pulse to the pulsed laser emission circuit. Setting the switching frequency of the three-bit address signals to 1 MHz, the time to complete one scan is 8 \(\mu\)s, and the emission frequency of each LD is 125 kHz.  
Figure 10 is a state transition diagram of the FPGA test signals, implemented using a two-layer state machine model. The states of the first layer include L1_IDLE (initial state), L1_CH0 (channel 0), L1_CH1 (channel 1), L1_CH2 (channel 2), L1_CH3 (channel 3), L1_CH4 (channel 4), L1_CH5 (channel 5), L1_CH6 (channel 6), and L1_CH7 (channel 7). In each channel state, a three-bit address (Addr2, Addr1, Addr0) is output to select the output channel. L1_F is a state transition flag that changes during each channel state to jump to  
Figure 8: High speed analog multiplexer.  
Figure 7: LD pulse drive circuit. (**a**) Circuit schematic diagram. (**b**) Partial PCB layout.  
the second layer state. The states of the second layer include L2_Delay1 (delay, waiting for channel switching to stabilize), L2_PH (pulse output at a high level), L2_Delay2 (delay, pulse at a high level for a period of time), L2_PL (pulse output at a low level), L2_Delay3 (delay), and L2_End (pulse output ends, jumping to the channel state of the first layer). The state machine cycles through these states to achieve a pulse output for each channel.  
Figure 11 shows the timing diagram of the FPGA pulse output signal. The state machine of the FPGA is driven by a 50 MHz clock signal, with a cycle \(T\) of 20 ns. The state L1_CHx (x = 0, 1, \(\ldots\), 7) remains for 1\(T\), which is 20 ns. The state L2_Delay1 remains for 21\(T\), which is 420 ns. The state L2_PH remains for 1\(T\), which is 20 ns. The state L2_Delay2 remains for 4\(T\), which is 80 ns. The state L2_PL remains for 1\(T\), which is 20 ns. The state L2_Delay3 remains for 21\(T\), which is 420 ns. The state L2_End remains for 1\(T\), which is 20 ns. In one cycle, there are a total of 50\(T\), which is 1 \(\upmu\)s. During the periods of L2_PH, L2_Delay2, and L2_PL, pulses are output with a pulse width of 6\(T\), which is 120 ns. That is, the FPGA outputs pulses with a frequency of 1 MHz and a pulse width of 120 ns. During the periods of L1_CHx and L2_Delay1, channel switching is implemented, with a duration of 22\(T\), which is 440 ns.  
Figure 11: FPGA pulse output signal timing.  
Figure 9: Schematic diagram of scanning test circuit.