# Adaptive Coherent Receiver Settings for Optimum Channel Spacing in Gridless Optical Networks
## 1 Introduction  
The cloud computing era is pushing operators to upgrade to more autonomous and agile management of traffic demands. With optical fibers providing the backbone of modern networks, dense wavelength division multiplexing (DWDM) links should therefore be more flexible. Optical networks evolved from point-to-point links, to fixed add/drop where multiplexing ports are specified per wavelength, to fixed 50 GHz bandwidth reconfigurable optical add-drop multiplexers (ROADMs) with internal variable optical attenuators (VOAs) and now with the current high-end generation of Wavelength Selective Switches (WSSs), such as the one based on Liquid Crystal on Silicon (LCOS) technology [1]. The latter will enable elastic spectral resolution in multiples of 12.5 GHz. Such flexibility in the photonics transport layer is completed with advancement in software-defined coherent transponders. The latter are typically dual-polarization coherent optical receivers coupled with high-speed data converters with intelligent digital signal processing [2]. With centralized control and high-level applications, software-defined networking (SDN) is emerging as the preferred network architecture approach. The paradigm is based on monitoring, provisioning, and running networks with zero touch. Since performance metrics are collected from existing channels in the network, network managers can take advantage of this information to optimize the process of adding new capacity. Managing gridless channels is by far the biggest challenge in photonic systems. The level of complexity in planning and assigning resources grows exponentially with available ports and directions. The main goal is to fit more channels in the same C-band (or C+L bands) by allowing more agility inassigning traffic to signals with various spectral widths. The red areas, appearing in Figure 1, are dead bands on the edges of each Media Channel (MC); they can have up to 6.25 GHz roll-off as defined in international telecommunication union (ITU) standard [3]. When multiple signals are multiplexed onto channels, referred to as Network Media Channels (NMC), are transmitted simultaneously from one source to same destination, we pack them into one MC (as defined in ITU G.870). Gridless channels are subject to interference from their neighbors. When excess bandwidth is used as part of clock recovery scheme, spectral energy from adjacent channels first leaks in the edge bands which hinders the integrity of the extracted transmitter clock manifested by an increase in clock jitter. The clock jitter reduces the certainty in the sampling moment and the effective number of bits (ENOB) of the interleaved high-speed analog-to-digital converters (ADC) [4]. The clock recovery loop is built around a Phase Detector (PD) implemented in the digital processing domain, along with a voltage-controlled oscillator (VCO) gain and filtering elements which work in tandem to reduce the sources of noise. One of the most important aspects to enable high-speed optical networks for 400 Gb/s and beyond, is the performance of data converters. Therefore, jitter is a key impairment to be studied as circuits are required to operate with high-speed clocks, while having higher ENOB to support rich modulation formats and reduce power dissipation. With samplers operating at 100 Gsample/s, as demonstrated in [5], the unit interval of transmitted symbols is 10 ps. Therefore, better systems and practices to control and mitigate jitter are crucial for future optical (coherent and non-coherent), wireless (such as 5G) and wireline (such as backplane serializer/de-serializers). The authors in [6] and [7] studied digital clock recovery in time and frequency domains, respectively. They focused on single channel propagation in dual-polarizations coherent system, where jitter tolerance versus differential group delay (DGD) and Polarization Dependent Loss (PDL), as fiber optical impairments, was studied. It was shown that certain combination of DGD and State of Polarization (SOP) rotations cause loss of clock lock.