## 3 Monolithic Photonic Integration for Optical Memories
When access to the memory is blocked, the _Inverted Access_ signal features a logical \"1\" pulse, which enters the SOA-MZI AG as the control signal, switching the complementary data signals to the S-port and blocking communication with the outer world, allowing for the FF-memory to retain its logic state and memory content. The experimental setup used to evaluate the complete RAM functionalities is illustrated in Figure 3b. A signal generator (SG) was used to drive a Programmable Pattern generator (PPG) at 5 GHz. The PPG drives two Ti: LiNbO\({}_{3}\) modulators using complementary bit-patterns in order to produce 5 Gb/s \(2^{7}-1\) Pseudorandom Binary Sequences (PRBS) Non-Return-to-Zero (NRZ) signals. One modulator is responsible for producing the _Inverted Access_ signal at 1554.8 nm and the _bit_ signal at 1558.7 nm, and the other is used for the \(\overline{bit}\) signal at 1557.9 nm. For the evaluation of the Write operation, the three signals were coupled together to form the complementary _bit_ and \(\overline{bit}\) pair and one access signal, while the two coupler outputs were amplified using erbium-doped fiber amplifiers (EDFA). The first branch incorporated a 0.6 nm 3 dB-bandwidth Optical Bandpass Filter (OBF) centered at 1554.8 nm to properly filter the _Inverted Access_ signal, while the second branch incorporated a 1 nm 3 dB-bandwidth OBF centered at 1558.3 nm, to filter the _bit_ and \(\overline{bit}\) pair. The AWG used has a 0.65 nm 3-dB channel bandwidth. The stored logical value of the FF and the \(Set/Reset\) signals could be monitored through the auxiliary ports FFOut1 and FFOut2 at any time of the experiment, which were amplified in respective EDFAs and filtered by suitable Optical Bandpass Filters (OBPFs), before being analyzed by a digital Optical Sampling Oscilloscope (OSC) and Bit Error Rate Tester (BERT). The blue-highlighted areas of the setup were only used during the evaluation of the Write operation, while the red-highlighted part of the setup was only used during the evaluation of the Read operation. To evaluate the READ operation, the FF was set to one of its logic memory states each time by properly adjusting the external CW signal power-levels, meaning that either only \(\lambda\)1 or \(\lambda\)2 was the dominant wavelength of the FF, providing a high FF output power level at either the FFOut1 or FFOut2 port, respectively. A monitor branch was connected at the Data I/O port of the RAM cell comprising an EDFA as a preamplifier and a 0.6 nm 3 dB-bandwidth Tunable OBPF (T-OBPF) that can be tuned at either one or two in order to evaluate one of the two wavelengths. Polarization controllers (PC) were used at several stages of the setup to control signal polarization. Variable optical attenuators (VOA) were also used to properly adjust the power levels of the optical signals, while optical delay lines (ODLs) were employed to ensure signal decorrelation and bit-level synchronization among the signals. The experimental results obtained from the 5 Gb/s operation can be seen in Figure 4. Figure 4a-g depict synchronized time traces/eye diagrams of the Write operation. Figure 4a shows the _Inverted Access_ signal and Figure 4b,c show the _bit_ and \(\overline{bit}\) signals that were launched in the RAM cell, respectively. Figure 4d,e illustrate the \(Set/Reset\) signals originating from the incoming _bit_ and \(\overline{bit}\) signals, after the access-controlling operation of the AG, where it is clear that they only imprint the logical \"1\" _bit_ and \(\overline{bit}\) pulses, respectively, when there is no logical \"1\" pulse at the _Inverted Access_ signal. The proof-of-principle of the Write operation is then verified by monitoring the FF stored content through the signals emerging at the respective FFOut1 and FFOut2 ports in Figure 4f,g, where it can be seen that the FF changes its logic state when there is an incoming _Set_ or _Reset_ pulse and maintains its state until the next \(Set/Reset\) pulse arrival.