## 3 Experimental Results  
The full Ka-band amplifier was fabricated using a 65 nm CMOS technology. The chip micrograph is shown in Figure 8. The whole chip area including the probing pads and the core chip area were 1 \(\times\) 0.7 and 0.5 \(\times\) 0.75 mm\({}^{2}\), respectively.  
The measured S-parameters are shown in Figure 9. A peak gain of 13.2 dB was measured at 39.2 GHz. The 3 dB bandwidth was 18.2 GHz from 23.5 to 41.7 GHz, which covered the entire Ka-band frequencies. Specifically, from 26.2 to 40.2 GHz, the gain exhibited a flat response with a small variation, i.e., 13 \(\pm\) 0.2 dB. The measured 1S\({}_{11}\)1 and 1S\({}_{22}\)1 were smaller than \(-\)10 dB from 26.3 to 40.1 GHz. The stability K-factor was calculated from the measured S-parameters, as shown in Figure 10. It was observed that the Ka-band amplifier was stable over the frequencies from DC to 50 GHz, which include both the operation and the out-of-band frequencies. The measured group delay is shown in Figure 11. The group delay was fairly flat in the frequency range between 22 and 46 GHz. The power measurement of the amplifier at 34 GHz is shown in Figure 12. The input 1 dB compression point (IP1 dB) was \(-\)13.2 dBm. Figure 13 shows the measured IP1 dB over the frequency. The IP1 dB ranged from \(-\)13.2 to \(-\)16.6 dBm between 26 and 40 GHz.  
In Table 2, the measured performances are summarized and compared with those of the previously reported CMOS Ka-band amplifiers. The amplifier in this study exhibited a superior gain flatness in the full Ka-band frequencies to the other state-of-the-art amplifiers.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Parameters** & **Values** & **Parameters** & **Values** \\ \hline L\({}_{1}\) & 0.6 nH & C\({}_{1}\) & 0.41 pF \\ \hline L\({}_{2}\) & 0.68 nH & R\({}_{1}\) & 200 \(\Omega\) \\ \hline L\({}_{3}\) & 0.8 nH & R\({}_{2}\) & 1000 \(\Omega\) \\ \hline L\({}_{4}\) & 0.45 nH & TL\({}_{1}\) & 265 \(\mu\)m \\ \hline L\({}_{5}\) & 0.3 nH & TL\({}_{2}\) & 120 \(\mu\)m \\ \hline L\({}_{6}\) & 0.7 nH & M\({}_{1}\)–M\({}_{3}\) & \(1\times 30\)\(\mu\)m \\ \hline L\({}_{7}\) & 0.2 nH & V\({}_{61}\) & 1.1 V \\ \hline L\({}_{8}\) & 0.65 nH & V\({}_{62}\) & 1.1 V \\ \hline L\({}_{9}\) & 0.27 nH & V\({}_{63}\) & 0.9 V \\ \hline Lneut & 1.3 nH & V\({}_{d1}\) & 1.1 V \\ \hline C\({}_{\text{bypass}}\) & 1.36 pF & V\({}_{d2}\) & 1.1 V \\ \hline C\({}_{\text{dc}}\) & 1.36 pF & V\({}_{d3}\) & 1.1 V \\ \hline \hline \end{tabular}
\end{table}
Table 1: Design parameter values of the full Ka-band amplifier.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Ref.** & **Technology** & **Peak Gain** & **1S213-dB** & **1S11 –10** \\  & **(dB)** & **BW** & **dB BW** \\  & **(GHz)** & **(GHz)** & **over Frequency** \\ \hline This work & 65-nm CMOS & 13.2 & 18.2 & 13.8 \\  & & (23.5–41.7) & (26.3–40.1) & 26.2–40.2 GHz \\ \hline \hline \end{tabular}
\end{table}
Table 2: Performance comparison with previous CMOS-based Ka-band amplifiers.  
Figure 8: Chip micrograph of the full Ka-band amplifier.  
Figure 10: Stability factor based on the measured S-parameters.  
Figure 9: Measured S-parameters of the full Ka-band amplifier.  
Figure 11: Measured group delay.  
Figure 12: Measured output power and gain versus input power at 34 GHz.