# NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors
## 4 Results  
The validation of the proposed approach was done by SWIFI, which is a useful technique to emulate SEU effects. The adopted approach was proven in our previous works concerning fault-injection for multi-core processors [7; 37; 38; 39]. It is important to note that the objective of this approach is to reproduce the SEUs effects, which are bit-flips in memory cells caused by natural radiation. Details of the implementation of the fault-injector are described in Section 6.3.  
This case-study implements one core of the device as the fault-injector, the RM3 core being of IO Cluster 0. Fault-injection campaigns for both applications are devoted to inject faults in the General Purpose Registers (GPRs) and 15 System Function Registers (SFRs) of the PEs belonging to the compute clusters. The fault-injection campaigns consider the emulation of one SEU per execution. The authors decided to run fault-injection campaigns only in accessible processors' registers due to the following:  
In the authors' previous work [8] was presented an SEU error-rate prediction method that combines radiation experiments with fault-injection. The method was evaluated on the same target device (MPPA-256) implementing a parallel matrix multiplication running on bare-metal without OS. From the radiation experiment results, it was observed that all upset events produced in the internal memories (SMEMs) of the compute clusters of the MPPA were detected and corrected by a combination of ECC and bit-interleaving. ECC detects two errors and corrects one. However, if two or more errors are produced in the same word (Multiple Bit Upset (MBU)), ECC may fail. To solve this problem, the manufacturer implements bit-interleaving in the SMEMs to spread the bits of data onto  
Figure 3: Proposed configuration for case-study (Part 2).  
several addresses. In this way, no MBUs was produced. In addition, all upsets on cache memories were detected by parity, and the corresponding cache memory was invalidated. For prediction purposes, fault-injection campaigns were performed on the internal memory and processors' registers. However, results concerning fault-injection in the internal memories were not useful since upsets in memories do not contribute to the cross-section during radiation tests.  
To analyze the experimental results, the consequences of a bit-flip in a memory cell were classified in:  
* Silent fault: There is no apparent effect on the system; all the system and application processes are terminated in a normal way, and the results are correct.
* Application erroneous result: The result of the application is not the expected one.
* Timeout: The program does not respond after a duration equal to the worst-case execution time.
* Exception: The application triggers an exception routine.  
The erroneous results, timeouts and exceptions were considered as errors. Among them, the most critical one is the \"application erroneous result\" because it is not detected by the system and may cause unpredictable consequences. The timeouts and exceptions are not so critical since they are detected and the application/system is able to manage them.  
The error-rate of an application is derived from SEU fault-injection campaigns. This quantity is defined as the average number of injected faults needed to produce an error in the application results.  
\[\tau_{Inj}=\frac{Number\ of\ Errors}{Number\ of\ Injected\ Faults} \tag{1}\]