# Vertical GaN MOSFET Power Devices
## 2 GaN Power Devices  
GaN-based power devices are primarily categorized into two fundamental structures: planar (lateral) structure devices and vertical structure devices, as depicted in Figure 2. Planar devices are typically manufactured on Si or SiC substrates, while vertical devices are homoepitaxially grown on GaN substrates. GaN HEMTs are the most commonly employed among GaN power devices. Si substrates are favored in their production to optimize cost-effectiveness and yield. However, epitaxially growing GaN on Si presents considerable challenges due to significant lattice mismatch and a substantial thermal expansion coefficient disparity between the two materials. The lattice mismatch can lead to dislocation propagation and defect generation throughout the GaN epitaxial layers, while thermal mismatch may cause cracking in the GaN layer during cooling after epitaxial  
Figure 1: The distribution of wide bandgap power devices is based on voltage range [19]. growth [20; 21; 22]. To mitigate defect propagation and attain high-quality, defect-free GaN on Si, a meticulous optimization of the buffer region is imperative. Additionally, it is essential to limit tensile stress during both the growth and cooling phases of the process [23; 24]. In addition to challenges related to epitaxial layer mismatch, the quality of the top surface becomes a critical concern for achieving optimal performance in lateral GaN devices. The presence of surface states on the AlGaN layer significantly influences the formation of the two-dimensional electron gas (2 DEG) [25]. These states can have adverse effects on device performance by unintentionally depleting the 2 DEG. This depletion can create a virtual gate between the gate and drain regions, leading to degradation in device performance and reliability. To counteract the depletion of the 2 DEG, a well-optimized silicon nitride (SiN) passivation layer is typically employed. Currently, commercially available GaN HEMTs offer a \(V_{BD}\) of approximately 650/900 V, coupled with a maximum output DC rating of 150 A [26]. These devices find applications across various fields, including onboard battery chargers, high-efficiency power converters, and dense solar panel inverters. However, lateral GaN devices face specific limitations when it comes to scaling \(V_{BD}\) and ensuring reliability. These limitations are primarily associated with lateral carrier flow from the source to the drain, with the electron density in the channel being highly sensitive to surface traps and buffer defects. Furthermore, these imperfections in the device can lead to phenomena such as current collapse and dynamic degradation of \(R_{ON}\)[26; 27; 28]. The severity of these adverse effects increases as \(V_{BD}\) ratings rise. Moreover, the lateral electron transport nature results in a nonuniform distribution of the electric field within the device, leading to a higher electric field concentration in specific regions such as the gate, field plate, or drain edges. This nonuniform electric field distribution may result in premature semiconductor and dielectric breakdown, along with increased electron trapping at the surface. These factors contribute to performance degradation and limit the device's voltage-blocking potential [28; 29]. Furthermore, the \(V_{BD}\) of lateral devices is directly proportional to the distance between the gate and drain, which increases both the device size and cost. Another significant concern with lateral GaN HEMT devices is that they are typically normally-ON devices. While various methods exist to create normally-OFF devices, such as using fluorine ion implantation [30; 31; 32], recess gates [33], p-GaN gates [34], trigate structures [35; 36], cascode configurations [37; 38], etc., the threshold voltage (\(V_{TH}\)) achieved is typically around 1-2 V in many cases, including commercial devices. This characteristic makes the device less than ideal for failsafe operation.