# A Self-Testing Platform with a Foreground Digital Calibration Technique for SAR ADCs
## 2 Proposed Self-Test Platform
### Proposed Calibration Method  
A previous work [8] derived the proposed calibration formula using the FFT and a cosine wave input signal. The third harmonic distortion value \(\mathrm{a}_{3}\) can be detected by an RDFT processor. The error factor \(\Delta_{\mathrm{n}}\) can be further calculated for the calibration. In addition, the calibration code was only used for the first-time test to reduce the complexity. This calibration method can not only compensate for the error caused by the capacitor mismatch and DC offset in the traditional ADC but it can also be applied to calibrate the \(\mathrm{T}/\mathrm{H}\) circuit in the multi-mode SAR ADC (Figure 2). The main calibration equation can be written as follows:  
\[a_{3}=20\mathrm{log}\left(\frac{A\times\Delta_{\mathrm{n}}\times 1.696\times C _{\mathrm{n}}}{2048}+1.696\times V_{\mathrm{os}}\right), \tag{1}\]  
where \(A\) is the amplitude of the cosine wave, \(C_{\mathrm{n}}\) is the value of each capacitor ratio, \(\Delta_{\mathrm{n}}\) is the error factor of each capacitor mismatch, and \(V_{\mathrm{os}}\) is the DC offset. The DC offset voltage of the comparator circuit can be expressed as:  
\[V_{\mathrm{os}}=\sqrt{\left(\frac{V_{\mathrm{ov}}}{2}\frac{\Delta R_{\mathrm{ D}}}{R_{\mathrm{D}}}\right)^{2}+\left(\frac{V_{\mathrm{ov}}}{2}\frac{\Delta \left(\
icefrac{{W}}{{L}}\right)}{\left(\
icefrac{{W}}{{L}}\right)}\right)^{ 2}+\left(\Delta V_{\mathrm{t}}\right)^{2}}, \tag{2}\]  
where \(V_{\mathrm{ov}}\), \(W/L\), and \(V_{\mathrm{t}}\) are the overdrive voltage, transistor size, and threshold voltage of the differential pair, respectively. According to Equation (2), the threshold voltage is a static offset, which does not affect the dynamic performance of the ADC. Meanwhile, both the overdrive voltage and transistor size will degrade the ADC performance. Some approaches have been used to overcome this problem and improve the DC offset, such as reducing the overdrive voltage or increasing the comparator size. However, the drawbacks of these methods are the decrease in the comparison speed and higher power consumption, respectively. Therefore, the problem can be overcome using the RDFT processor in a system-on-a-chip to calibrate the ADC error [8]. Generally, if a DC offset value will be very small, it will not affect the performance of the ADC. However, if a DC offset is a bigger value,  
Figure 1: Traditional successive approximation register (SAR) Analog-to-Digital converter (ADC) structure. Figure 2: Multi-mode SAR ADC structure. the performance of the ADC will be decreased. Figure 3 shows the MATLAB simulation results with different DC offset variations. The calibration equation can be rewritten as (3). Here, we assume that \(A=1\) V, and the DC offset (\(V_{\text{os}}\)) is 2 mV:  
\[\Delta_{\text{n}}=\frac{(10^{\text{a}_{3}}-0.0033)\times 2048}{1\times 1.696 \times C_{\text{n}}},n=11\,\sim 0, \tag{3}\]  
In addition, the input signal of the RDFT processor can be a sine or cosine wave signal. Therefore, the power spectra of the RDFT have real (Re) and imaginary (Im) part energies, respectively, in which a\({}_{3}\) is equal to:  
\[20\text{log}\sqrt{\left(\text{Re}\right)^{2}+\left(\text{Im}\right)^{2}}, \tag{4}\]  
The value of a\({}_{3}\) can be substituted as the real and imaginary parts. Therefore, Equation (3) can be further simplified as follows:  
\[\Delta_{\text{n}}=\frac{\left(10^{\frac{1}{2}\log\sqrt{\left(\text{Re}\right)^{ 2}+\left(\text{Im}\right)^{2}}}-0.0033\right)\times 2048}{1\times 1.696 \times C_{\text{n}}},n=11\,\sim 0, \tag{5}\]  
where C\({}_{\text{n}}\) is the value of each capacitor array. Equation (5) can be used to evaluate the error factor (\(\Delta_{\text{n}}\)).