## 4 Result and Discussion
### Active Power Reduction of PV Based Excess Energy Control During Fault at PCC1  
While transferring solar energy to the AC grids through the HVDC line, a three-phase-to-ground fault is applied at the PCC1 as depicted in Figure 13. It reduces the MMC1 converter's power transfer capacity to zero, as illustrated in Figure 14. Although the converter injects maximum real and reactive current, HVDC link voltage is increased, which proportionally increases the PCC voltage. Usually, a dynamic braking resistor (DBR) is used in the HVDC link to dissipate the surplus energy in the HVDC link. DBR is connected in parallel with the transmission line and remains inactive during normal conditions. However, any increase of HVDC link voltage beyond threshold due to excess energy under fault in the point of common coupling of AC grids activates the DBR to keep the HVDC link voltage below limits. As can be seen from Figure 12, HVDC link voltage is regulated around the threshold limit (1.2 pu) during the period of single line to ground (SLG), double line to ground (DLG) and three line to ground (3 LG) faults employing conventional dynamic braking resistor (DBR). DBR is active when the HVDC link voltage exceeds 1.2 pu. DBR is turned off when the HVDC link voltage goes below 1.1 pu. A large number of series-parallel combination semiconductor switches are required to let the current flow through the dissipating resistor to dissipate a large amount of HVDC power (hundreds or thousands of megawatt) during the three-phase-to-ground fault at the point of common coupling of AC grids. Dynamic braking resistor also introduces several switches in the HVDC voltage, as shown in Figure 12, which could result in fluctuation in the real power flow. Instead of a DBR to dissipate the excess energy, this work reduces the PV array power proportionally with the PCC voltage increase. One second duration three line to ground (3 LG) fault is applied at PCC1 at 1 s,  
Figure 21: PCC voltage, PV voltage and power, and MMC1-HVDC voltage for the period of SLG fault. as presented in Figure 13. Figure 14 shows that the delivered real power of MMC1 has been reduced to zero due to 3 LG fault. As can be seen from Figure 15, PV voltage starts increasing when the PCC voltage exceeds 1.05 pu and rises to around its open circuit voltage, which dramatically reduces the PV power. Hence, HVDC link voltage is restricted to maximum 1.2 pu and then gradually decreases to normal. After fault clearance, the PV voltage comes back to the optimum point. Thus, the controller is able to control excess energy in the HVDC link voltage during the fault without using the DBR. The line current for the Y-\(\Delta\) transformer remains limited to 1.33 pu, as presented in Figure 13. Due to the balanced fault, both side currents have a similar shape with equal magnitude. Apart from excess energy control in the HVDC link, the control system also injects reactive current for voltage support at the point of common coupling. During the fault at PCC1, maximum 1.1 pu real current and 0.7 pu reactive current are selected for the MMC1 current controller in this work. Figure 14 illustrates that the maximum 1.1 pu real current (Id) and 0.7 pu reactive current (Iq) have been injected during the 3 LG fault. Figure 22: PCC voltage, Battery and PV power, SOC, and MMC1-HVDC voltage in the course of 3 LG fault. Figure 23: Id and Iq current and power of MMC1 for the duration of 3 LG fault. Figure 24: PCC voltage, Battery and PV power, SOC, and MMC1-HVDC voltage in the course of DLG. Similarly, double-line-to-ground (DLG) fault and single-line-to-ground (SLG) fault are applied at PCC1. Figures 16-18 illustrate the response during the DLG fault, whereas Figures 19-21 illustrate the response during the SLG fault. Note that 3 LG, DLG and SLG faults are 1s duration faults and are applied at 1s separately. As can be seen from Figures 17 and 20, the real power delivery is reduced to average 50 MW during DLG fault, but no average power reduction is observed during SLG fault due to higher capacity of the converter.