# High Performance GAA SNWT with a Triangular Cross Section: Simulation and Experiments
## 3 Experiments
### Fabrication of GAA SNWT with Triangular Cross Section  
Based on the above analysis, we adopted the TMAH wet etching technique to fabricate a P-type inverted triangular cross-sectional GAA FET on a bulk-si substrate, as shown in Figure 7. The process flow is given as follows:  
1. Channel Engineering * thermal oxidation on a bulk silicon substrate to produce a silicon oxide buffer layer; * chemical vapor deposition to produce a silicon nitride hard mask layer; * optical lithography, anisotropic dry etching, and oxidation to produce LOCOS isolation, and active regions are achieved; * chemical vapor deposition to produce a polysilicon hard mask layer; * electron beam lithography and anisotropic dry etching to produce a polysilicon hard mask; * electron beam lithography and anisotropic dry etching to form a silicon nitride hard mask and Si Fins; * remove the native oxide on the silicon surface by the diluted hydrofluoric acid solution at room temperature; * Si Fin anisotropic wet etching by TMAH solution to form inverted triangular nanowires under the silicon nitride hard mask; * high-energy ion implantation is performed on the active region to generate N\(-\) doping as an N\(-\) well of PMOS; * low-energy ion implantation is performed on the active region, and only the exposed area in the trench can generate N+ doping, preventing the bottom parasitic transistor from turning on; * remove the silicon nitride hard mask and the silicon oxide buffer layer by phosphoric acid and diluted hydrofluoric acid, and suspended silicon nanowires are obtained; * sacrificial oxidation to round the corner of triangular nanowires; * remove sacrificial oxide by diluted hydrofluoric at room temperature;
2. Gate Engineering * thermal oxidation to produce gate oxide; * chemical vapor deposition to generate a polysilicon gate material layer;  
Figure 6: 35 \({}^{\circ}\)C, 25% TMAH solution is used to etch a silicon Fin with a 50 nm width. The SEM images obtained after different etching times (**a**–**c**): 0 s/20 s/30 s.  
* polysilicon gate ion implantation and rapid thermal annealing;
* electron beam lithography and anisotropic dry etching to produce the polysilicon gate;
* Source and drain Engineering
* high-dose implantation is performed on large fan-out regions of source and drain, followed by rapid thermal annealing;
* chemical vapor deposition to produce the isolation layer;
* optical lithography and dry etching to form the contact holes;
* metal contacts and interconnections formation.  
There is a bottom parasitic transistor below the silicon nanowire device, and we need to effectively suppress it. A common practice is to insert an isolation layer between the gate material and the parasitic transistor, but chemical planar polishing (CMP) equipment is required to complete the planarization treatment. Due to the lack of CMP, high-dose implantation in the trench is used here, which can greatly increase the channel doping concentration and the threshold voltage of the parasitic transistor, thereby preventing it from turning on. The silicon nanowire channel can still maintain a low doping concentration due to the protection of the silicon nitride hard mask. After the suspended silicon nanowires are formed, the triangular silicon nanowires are sacrificially oxidized slightly to make their sharp corners round, avoiding the reliability issues of the device.