## 5 Experimental Evaluation  
The Matrix-DSP supports two programming modes, which are the assembly mode and C mode. Assembly programming has the advantage of being manually pipelined, but the workload is high. Computation-intensive programs rely on good assembly programs to obtain high performance. The C programming model involves a relatively low workload. However, for access-intensive programs, the percentage of computation time is low and is masked by double buffering, so the C language mode can achieve a similarly high performance. Therefore, we chose the C programming mode. We chose the sparse matrices, which are from a 27-point discrete format with three DOFs at each point, for the test. The tests are performed on three scale grids: \(32\times 32\times 32\), \(64\times 64\times 64\), and \(128\times 128\times 128\). The \(32\times 32\times 32\) scale grid can put the vector x in the GSM without blocking, while the block sizes of the other two grids are \(64\times 64\times 32\), and the memory of \(Local\_x\) in the GSM is \((64+2)\times(64+2)\times(32+2)\times 3\times sizeof(double)=3.390\) MB. Some other parameters can be obtained by the formula in Section 4.3. \(nnz\_row=3\times 27=81\), \(AM\_row=576\), and \(vec\_n=36\). Figure 10 depicts the results of the optimized SpMV and Gauss-Seidel. The peak performance of the SpMV without any optimization was only 0.128 Gflops/s, 0.128 Gflops/s, and 0.126 Gflops/s on \(32\times 32\times 32\), \(64\times 64\times 64\), and \(128\times 128\times 128\) grids, respectively, and 0.127 Gflops/s, 0.128 Gflops/s, and 0.127 Gflops/s for the Gauss-Seidel, respectively. After multicore acceleration, the performances of the SpMV, which reached 1.88 Gflops/s, 1.91 Gflops/s, and 1.88 Gflops/s, respectively, were improved by about \(14\times\) for all three grids. As for the Gauss-Seidel, the peak performance was improved by \(8.5\times\) on the small-scale grid and about \(13\times\) on other larger-scale grids, thus reaching 1.08 Gflops/s, 1.78 Gflops/s, and 1.64 Gflops/s, respectively. Vectorization optimizations on the SpMV and Gauss-Seidel share common properties in that the smaller the cores used, the higher the FLOPS percentage increase, and the performance plateaus when the core number exceeds six. This is mainly because the computational performance grows linearly with the number of DSP cores, but the bandwidth of the DDR has reached the bottleneck early. The performance results on three different scale grids were 2.18 Gflops/s, 1.96 Gflops/s, and 1.95 Gflops/s for the SpMV, respectively, and 2.11 Gflops/s, 2.37 Gflops/s and 2.33 Gflops/s for the Gauss-Seidel, respectively. The blocking method makes efficient use of the high bandwidth features of the GSM. It can be seen from Figure 10 that the performance improvement of the blocking method for the two functions became more obvious as the number of DSP cores increased. This is mainly because, when the number of DSP cores is large, the DDR memory bandwidth allocated to each DSP core is limited, thus making the advantage of the GSM's high bandwidth very remarkable. On three scale grids, from small to large, the SpMV achieved \(2.41\times\), \(2.75\times\), and \(2.70\times\) in speedups, respectively, with FLOPSs of 5.26 Gflops/s, 5.41 Gflops/s, and 5.27 Gflops/s, respectively. The Gauss-Seidel achieved \(2.21\times\), \(2.58\times\), and \(2.56\times\) in speedups, respectively, with FLOPSs of 4.67 Gflops/s, 6.13 Gflops/s, and 6.00 Gflops/s, respectively. As shown in Figure 10, the performance improvement from the double buffering was very small, with neither the Gauss-Seidel nor the SpMV improving by more than 2%. However, when only 1-2 DSP cores were used, the double buffering could result in performance increases of 30-40%. This is because when the number of DSP cores is small, each DSP core is allocated with a higher DDR bandwidth and higher computation ratio. If the Matrix-DSP can be equipped with a higher bandwidth external memory, the effect of double buffering will be more significant.