## 2 Schematic and Set-Up of the Frequency Synthesis Chain  
Figure 1 presents the block diagram of the frequency synthesis chain, which utilizes a dual-PLL circuit. The dual-loop mode helps maintain a high phase-detector frequency and loop bandwidth in the clock generation PLL, especially when the greatest common divisor of the reference source frequency and the output clock frequency is small. This approach prevents a low phase-detector frequency and minimizes the output phase noise of the clock. In Figure 1, a 20\(\times\) frequency multiplier is used to multiply the 10 MHz reference source to 200 MHz. Then, the 200 MHz clock is phase detected with the clock output from the 200 MHz OCXO in the first phase detector (PD1) at a frequency of 200 MHz. The output signal from the 200 MHz OCXO drives a frequency comb generator to produce harmonics of 200 MHz. In the second PLL (PLL2), the 46 th harmonic of 200 MHz is selected by a narrow-band bandpass filter, and then the 9.2 GHz is mixed in the second phase detector (PD2) with another 9.192 GHz produced by the DRO. By a direct digital synthesis (DDS) module, a 7.368 MHz signal is generated. Then, the 7.368 MHz and the 9.192 GHz are compared in PD2. When the two PLLs are both phase-locked, a precise frequency at 9.192 631 770 GHz is ready. Considering the frequency precision error of 10 MHz reference, the final output signal will have a certain frequency deviation. Figure 2a illustrates a more detailed architecture diagram of the frequency synthesis chain, consisting of four main parts. Part (1) involves a 10 MHz OCXO source with ultra-low phase noise. In Part (2), a 200 MHz clock from the 20\(\times\) frequency multiplier is filtered and amplified before being compared with the 200 MHz OCXO output clock in PD1. The phase error signal generated by PD1 is filtered and then fed back to the proportional-integral controller to drive the 200 MHz OCXO. The signal from the 200 MHz OCXO output is split into two paths using a coupler. In the first path, the output clock is amplified with a low-noise amplifier, filtered, and sent to PLL2 as the reference source. In the other path, the 200 MHz clock is amplified, filtered, and used to drive a comb generator. The 46 th harmonic of the comb generator's output is band-pass filtered, amplified with a microwave amplifier in part (3), and then sent to the mixer in part (4). In PLL1, a splitter is used to generate two 200 MHz signals, with one of them serving as the sampling rate of the DDS (AD9854), to generate a 7.368 230 MHz clock [20]. In part (4), the 9.2 GHz microwave generated by the comb generator is mixed with the 9.192 GHz microwave generated from the DRO, and the resultant signal is passed through a power splitter. This process generates a 7.368 230 MHz clock. The two 7.368 230 MHz clocks are compared with each other to produce a phase error signal [21; 22]. The phase error signal is then low-pass filtered, conditioned by the PID2, and used to drive the DRO [19]. When the frequency synthesis chain is in a phase-locked state, the 9.192 GHz microwave is directed to an amplitude control module for precise amplitude adjustment. Figure 1: Basic architecture of the frequency synthesis chain. The photograph of the microwave frequency synthesizer is presented in Figure 2b. The miniaturized commercial cesium beam atomic clock requires a compact and high-performance frequency synthesizer for its operation. To optimize space utilization, a two-layer stacked structure is implemented. The two circuit boards, displayed in Figure 2b, are positioned in the upper and lower layers of the shielding cavity, with a total size of 19 mm (length) \(\times\) 15 mm (width) \(\times\) 5.5 mm (height). The phase noise of the output in the loop bandwidth of a PLL is primarily caused by the input reference source, following the deterioration according to the 20 \(\times\) logN rule. Outside of this bandwidth, the phase noise performance is mainly determined by the internal voltage-controlled oscillator (VCO) of the PLL.