# Supply-Scalable High-Speed I/O Interfaces
## 4 Survey on State-Of-The-Art Supply-Scalable I/O  
In this section, we attempt to compare the previously published supply-scalable I/O designs in terms of various aspects we discussed in the previous sections. Tables 1-3 show the comprehensive review of supply-scalable transmitters, receivers, and transceivers, respectively. Note that they are sorted with oldest publication first, and the clock generation (PLL) power is included in the transmitter  
Figure 13: Clocking architectures of the I/O interface. Throughout the surveys, we can find various meaningful trends. First, the data rate tends to increase continuously. Second, the figure-of-merit (FoM, energy efficiency) gap between the minimum and maximum data rates has been converging as the process technology scales down. It can be interpreted as the dynamic switching power occupied the dominant portion of I/O power in older technologies (e.g., [22; 24]); however, it has been significantly reduced owing to the technology scaling, whereas the others (the static current and the signaling power) have not [41; 43]. Third, the quarter-rate clocking has become the major clocking architecture and tends to exhibit better energy efficiency. Lastly, as we already discussed in Figures 3 and 6, the works relying on off-chip sources for supply scaling do not consider the overhead due to the supply scaling circuitry, such as non-zero energy loss, they tend to exhibit better efficiency. Only five works include the on-chip supply scaling, where the regulator efficiencies of around 80-90% have been reported. Specifically, looking at Table 1, we can observe that the voltage-mode driver has become the mainstream topology for the transmitters for the reasons we discussed in Section 3.4. On the other hand, more than half of the transmitter works rely on the external clock source to mitigate the design complexity due to the supply sensitivity of PLL. [12; 16; 22; 31] managed to cover the entire range with a single PLL; however, [16] uses an LC-PLL followed by a programmable divider but provides only a few quantized frequencies. [12; 22; 31] use a ring-PLL to cover the entire range; however, their supply voltages are separated from the other building blocks, which can also imply that it is difficult to scale the clocking circuit with the other building blocks because of its sensitivity to the supply voltage. The energy efficiency achieved from the highest data rate of each design ranges from 0.44 pJ/bit [27] to 43.3 pJ/bit [22], but we have to note that [27] does not include an equalizer, PLL, and on-chip supply scaling. If we narrow down the scope to the transmitters having at least two of them, the best energy efficiency becomes 1.97 pJ/bit at 32 Gb/s [16]. Looking into Table 2 where the survey of supply-scalable I/O receivers is presented, we can observe that mesochronous clocking has been a mainstream architecture [15; 24; 25; 26; 27], as we discuss in Section 3.5. The receiver designs that rely on external CDR/deskew calibration tend to exhibit better energy efficiency, which implies the hardware overhead of robust operation with the on-chip CDR/deskew. For example, [27] achieves 0.22 pJ/bit at 8 Gb/s from the 0.75-V supply, but [16] exhibits 1.06 pJ/bit at 8 Gb/s from the 0.72-V supply. Note that it does not mean the overhead is almost 80% of a complete receiver, because there are many differences in the level of completeness between [16] and [27]; for instance, [16] has much more extensive equalization and wider eye opening. Therefore, we have to be sure of whether a design includes such on-chip circuitry or not, while evaluating the performance of a receiver. Table 3 shows the performance survey of the scalable I/O designs where complete transceivers have been presented. The energy efficiency ranges from 0.51 to 15 pJ/bit for the lowest data rates and from 0.66 to 76 pJ/bit for highest data rates. A few notable works are as follows.