## 5 Conclusions  
This paper presented a heuristic approach for encoding states of FSMs by sequentially selecting states for encoding and assigning the most appropriate codes. The approach introduces several state selection modes (P, C, P_C, max_C, and max_X) and code selection modes (FPGA, CPLD, diff_w, and max_w). The state selection modes account for the internal relationships between the FSM states and input variables, while the code selection modes consider the architectural features of the electronic component (FPGA, CPLD, or ASIC) in which the FSM is implemented. Various sequential FSM state encoding methods were developed by combining state and code selection modes. The efficacy of these methods was evaluated using MCNC benchmarks with FSM implementations on FPGA. This study put forward the following hypotheses: (1) the results of FSM state encoding depend on the order in which the codes are assigned to the states; (2) FSM states that are most linked to already encoded states should be encoded first; (3) the mode diff_w contributes to minimizing the implementation cost of FSMs; and (4) the mode max_w contributes to increasing the performance of FSMs. Hypotheses 1 and 4 are fully supported by the findings. Hypothesis 2 is only partially substantiated, as the mode max_C, which considers states not linked with already encoded states, also provides satisfactory outcomes. Although Hypothesis 3 is not entirely confirmed, it is worth noting that the diff_w mode frequently appears in state coding methods that deliver optimal solutions. The experimental results demonstrated that the proposed FSM state encoding methods reduced the area by an average of 19.7%, with some examples showing a twofold reduction. Performance improvements averaged 21.2%, with some cases showing a 69.3% increase. Future research in FSM state encoding will emphasize the development of parallel and iterative algorithms, alongside exploration into varying the number of bits in state codes. Additionally, there is potential in investigating the integration of output function realization with state encoding, marking a promising direction for further study. Conceptualization, V.S. ; methodology, V.S. ; software, V.S. ; validation, V.S. and W.B. ; formal analysis, V.S. and W.B. ; investigation, V.S. and W.B. ; writing--original draft preparation, V.S. and W.B. ; writing--review and editing, V.S. and W.B. ; visualization, V.S. and W.B. All authors have read and agreed to the published version of the manuscript. The APC was supported by the Bialystok University of Technology grant number W/WI-IIT/1/2024 financed from a subsidy provided by the Ministry of Science and Higher Education of Poland. Not applicable. The data supporting the findings of this study are derived from FSM benchmarks provided by the Microelectronics Center of North Carolina (MCNC). These benchmarks are openly accessible, with references and links included within the article. The authors declare no conflicts of interest. This appendix presents an example of a Verilog description for the _shifting_ test case, generated by the _robust_0_ converter from the ZUBR package. This example utilizes FSM state encoding with the P_C_max_w method.