## 6 Conclusions  
Hardware authentication is critical for edge computing and extremely important to instill trust and confidence among end users about their data privacy. The APUF leverages delay variations from inherent manufacturing variations, generating an exponential number of CRPs and, thus, making it suitable for authentication in numerous IoT applications. In this paper, we conducted a security analysis of silicon-based APUF devices. Due to the lack of standardized benchmark datasets for the performance evaluation of PUFs and establishing their resilience against authentication breaches, we designed an experimental setup that extracts CRPs from an FPGA-based APUF. The integration of PUFs with FPGAs provides a strong synergy, combining the security benefits of PUFs with the natural flexibility and rapid time-to-market advantages of FPGAs. The relationship between the CRP is established through ML analysis and modeling. Using the Scikit-learn framework, we launched attacks on the APUF using SVM, LR, and ensemble GB algorithms, achieving prediction accuracies of 61.1%, 63.5%, and 63%, respectively. The SVM working principle is based on maximum-margin classification, LR estimates outcomes based on probabilities using the logistic function, and ensemble GB builds a powerful model by iteratively combining multiple weak learners. The APUF design implemented on an Altera Cyclone IV FPGA was subjected to 64-bit input challenges from a Linear Feedback Shift Register  
Figure 15: ML accuracy against CRP numbers. (LFSR). A single-bit response from APUF was collected and saved against each challenge bit. This setup uses only 129 registers and 81 LEs, consuming less than 1% of the total resources of the FPGA. Approximately 100K CRPs were extracted and analyzed against security-based evaluation metrics such as uniformity, reliability, and ML-based model accuracy. APUFs are the natural choice for device authentication and cryptographic key generation in resource-limited environments of IoTs, and they are on the verge of notable advancements. Future research on APUFs should focus on areas targeted to enhance their performance and capabilities, including the following:  
* A robust approach against temperature and voltage variations, in addition to aging-induced errors in APUF responses. * APUFs are vulnerable to newer attack forms, such as ML-based modeling. Research should focus on incorporating nonlinear or complex designs to complicate ML modeling attempts. * APUFs design approaches should be scalable and optimal in terms of area, power, and latency. Integration with 5G/6G networks, blockchains, and ML supports scalable, intelligent, and resilient security architectures. * The integration of APUFs with different PUF types can create hybrid systems that leverage complementary strengths to enhance the uniqueness and unpredictability of responses. * Advances in APUF technology will require standard evaluation and benchmarking metrics. Future research should be focused on creating testing frameworks that define comprehensive performance indicators for assessing uniqueness, reliability, and security. * Future works should focus beyond traditional silicon-based designs, as emerging materials and technologies could redefine APUFs. Conceptualization and design flow, A.M.S., M.R.I. and M.H.H. ; methodology, A.M.S., M.H.H., M.R.I. and A.K. ; formal analysis, A.M.S., S.A.Z. and M.H.H. ; investigation, implementation, debugging, A.M.S., S.A.Z. and A.R.B.N. ; resources, A.M.S., M.R.I. and A.K. ; data curation, A.M.S. and M.H.H. ; writing--original draft preparation, A.M.S. and M.H.H. ; writing--review and editing, A.M.S., M.R.I., M.H.H., A.K., S.A.Z. and A.R.B.N. ; visualization, A.M.S. and M.H.H. ; supervision, M.R.I., M.H.H. and A.K. ; project administration, A.M.S. ; funding acquisition, A.M.S. and A.K. All authors have read and agreed to the published version of the manuscript.