# A 11 mW 2.4 GHz 0.18 \(\upmu\)m CMOS Transceivers for Wireless Sensor Networks
## 2 System-Level Design of a Short-Range Transceiver  
The architecture of a transceiver greatly depends on the applications of the system. For short-range applications, the data rate and the distance of the transferring signal are quite limited, hence, the key considerations are low power consumption and small silicon area (low cost). The link budget, as well as the sensitivity of the receiver, are given by [4]:  
\[\mathrm{P_{RX,in}}=\mathrm{P_{TX,out}}-20\mathrm{log}(4\mathrm{d}\pi/\lambda) \tag{1}\]  
\[\mathrm{Sens_{RX}}=\mathrm{NoiseFloor}+10\mathrm{logBW}+\mathrm{NF}+\mathrm{ SNR_{out}} \tag{2}\]  
where \(\mathrm{P_{TX,out}}\) is the output power of the transmitter, \(\mathrm{d}\) is the distance of communication, and \(\lambda\) is the wave length of the carrier. Since the distance of communication is at metre level, a lower output power of PA or received power of RX is applicable. As illustrated in [4], at the distance within one metre, even a \(-40\) dBm received power, is possible with a 40 GHz carrier. The requirement of received power can be even relaxed for a 2.4 GHz carrier, which has with much less attenuation of propagation. Moreover, as shown in Equation (2), for a fixed noise floor, to accommodate a lower data rate transfer, it is possible to use a narrow signal bandwidth and a simpler modulation scheme, hence it is possible to make compromises in system specifications such as sensitivity or noise figure.  
Figure 1 shows the architecture of the proposed system. It includes three key sub-systems, namely, the receiver (RX), phase-locked loop (PLL), and transmitter (TX). The receiver includes a low noise amplifier, mixer, low pass filter with an amplifier stage (IF amplifier), and the buffer for test purposes. The local oscillator (LO) signal is provided by a PLL, which includes a crystal driver as the reference clock, a phase-frequency detector (PFD), charge pump (CP), loop filter, voltage controlled oscillator (VCO), and a fractional-N divider. The output signal of the PLL is also used as the input signal of power amplifier (PA) after a buffer stage, which generates the frequency shift keying (FSK) or amplitude shift keying (ASK)/on-off-keying (OOK) output signals of the TX. When the TX is working in ASK/OOK mode, the input of the TX (output of the PLL) is fixed to a certain frequency, while the biasing of the PA is modulated by the input DATA signal as an on-off (high gain or low gain) state. Thus, the transceiver performs a dual-mode operation. The target performances of this system are determined as follows, based on the above-mentioned strategy.  
The system is designed using a 0.18 \(\upmu\)m CMOS technology, which is a popular solution for industrial applications. For simplicity, the transceiver is designed to support FSK and ASK systems since the data rate requirement is quite low (usually considerably lower than 1 Mbps) in a typical WSN system. If more complex modulation schemes are needed, digital baseband systems can be added in this proposed work. The specifications of the subsystem can be determined based on the operating frequency and technology in use since many individual building blocks have been reported in the literature [12]. In this scenario, the maximum noise figure of the receiver can be as high as 20 dB [12]. This makes it possible to achieve a low power consumption in the design of the RX (mW level). At a distance of around 10 m, the output power of 0 dBm or less is a reasonable choice, even higher output power is possible with CMOS technology [11]. For a power amplifier with a power efficiency of 20%, the DC power consumption of the TX will be less than 5 mW [12]. To improve the performance, an accurate LO is needed, even though the requirement of phase noise performance is not a difficult one to meet. For example, \(-\)96 dBc/Hz at 1 MHz offset will be enough in such a system [12].