# Low-Latency QC-LDPC Encoder Design for 5G NR
## 4 Encoder Design Details
### Design for Flexible Configuration  
To adapt to variable code length and the eight code rates in the standard, we design a configurable circuit. Code length and code rate as dynamic parameters input into module, configuring static parameters for the following encoding calculations. The encoder parameter module performs parameter calculation via selection and output to the remaining  
Figure 9: CRC module architecture for 256 bits parallel computing. modules after receiving code length and code rate information. The parameters are the base graph BG, the number of kernel matrix columns \(K_{b}\), the lifting size \(Z\), and the corresponding sets \(i_{Ls}\) of \(Z\). BG and \(K_{b}\) determine the number of iterations for CN. The lifting size reads the memory module for parity check matrix information used in this encoding based on the group to which \(Z\) belongs. The codeword output processing module punches and shortens the information bits according to the code rate and \(K_{b}\), as well as the parity bits. The encoder hardware scale is designed according to the maximum parity check matrix under BG1, the matrix \(H\) is constructed by \(Z\times Z\) size submatrix, and each submatrix is multiplied by the corresponding \(Z\) length information vector or \(P_{1}\) vector. Therefore, the number of CN is set according to the maximum matrix dimension and the fixed length of the barrel shift is set to \(Z_{max}\). \(Z_{max}\) is used as the CN hardware length to adapt to multiple \(Z\times Z\) size submatrix. A \(Z\)-bits as the information or parity is input into CN, if \(Z\) is less than \(Z_{max}\), the LSB vacant bits will be filled with 0 bits, only \(Z\) significant bits are shifted during cyclic shift, and only \(Z\) significant bits of each code word are as the output at the end of encoding. Meanwhile, the parity codeword can be achieved according to \(Z\) as a group. It can also meet the redundancy version requirement of QC-LDPC IR-HARQ transmission. The encoder hardware shall adapt to changes of code rates. When the code rates are less than \(2/5\), \(C\), \(D\) matrix has more rows than columns. In order to design a more parallel \(P_{2}\) hardware, the multiplication operation between the \(H\) matrix and the vector is converted as shown in Figure 10. For high code rate, the encoder uses the code word output processing module to punch the corresponding number of \(Z\)-bits parity codes. With [\(C\)\(D\)] matrix row number as the degree of parallelism, the number of Part II calculation modules is configured. The increase of the CN parallelization degree reduces the encoding delay and improves the throughput. Therefore, the encoder can achieve code rate compatibility, but the encoding latency of different code rate under different BG depends on the encoding time at the lowest code rate. The proposed encoder needs \(K_{b}+4\) clock cycles to generate parity sequences under BG1 (\(K_{b}=22\)) and BG2 (\(K_{b}=10\)); it also needs one clock to output the encoded codeword. Therefore, the proposed encoder needs a total of \(K_{b}\) and 5 clock cycles to complete the encoding of an information sequence. The configurable barrel shift register design allows the encoder to be code length configurable. It avoids the waste caused by changing the hardware scale of the encoder for different lifting size. More CN numbers further shorten the encoding latency. The design of the configurable circuit makes the encoder fully meet the requirements of 5G NR flexibility. Although these schemes increase the hardware complexity of the encoder, they have achieved greater improvements in the performance of the encoder such as latency and throughput. Thus it achieves a balance between hardware complexity and encoder performance. We are constantly approaching the limit of the performance of the encoder within the complexity limit that the IC can achieve. Based on encoding algorithms, we have studied the dynamic configurable scheme of the encoder in this section.