# A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit
## 3 Critical Circuit Description  
### The Specific Structure of the De-Skew Circuit  
Figure 3 shows the specific structure of the de-skew circuit, which consists of a fall-edge-judgment phase adjuster (FPA), a three-stage digitally controlled delay line (3S-DCDL), a phase detector (PD), an edge generator (EG), a timing controller (TC) and a delay line controller. The 3S-DCDL consists of three sub-lines cascaded, namely the coarse delay line (CDL), medium delay line (MDL) and fine delay line (FDL). The delay line controller adopts a coarse-medium-fine structure. The CDL delay is controlled by TDC, and the delays of MDL and FDL are controlled by shift registers.  
Figure 4 shows the timing diagram of the de-skew circuit. After being enabled, the de-skew circuit operates the adjustment, measurement and synchronization stages sequentially until the loop is locked.  
The purpose of the adjustment stage is to reduce the delay for skew compensation (\(t_{de-skew}\)) by adjusting the phase of the input clock of 3S-DCDL. In this stage, the 0\({}^{\circ}\) of  
Figure 4: The timing diagram of the de-skew circuit.  
Figure 3: The specific structure of the de-skew circuit.  
SCLK passes through the initial delay path to generate DCLK0, which is fed back to FPA to compare the phase with SCLK. The comparison result determines whether the input clock phase of 3S-DCDL is the 0\({}^{\circ}\) or 180\({}^{\circ}\) of SCLK. Figure 4 shows that \(t_{de-skew}\) is reduced by half a cycle when 180\({}^{\circ}\) of SCLK is adopted.  
The goal of the measurement stage is to measure and quantify \(t_{de-skew}\), which is the interval between the edges of SCLK and DCLK0. In this stage, EG captures the edge of DCLK0 and the subsequent edge of SCLK as the start and end edges of TDC, which are noted as TDCS (TDC Start) and TDCE (TDC End), respectively, as shown in Figure 4. Then, TDC quantifies the interval between these two edges into coarse code.  
In the synchronization stage, the delay line controller gradually achieves alignment by the coarse-medium-fine tuning mode. First, the coarse code is assigned to the CDL. Because of the measurement error of TDC [15], the DCLK0 is ahead of SCLK after coarse tuning, and the coarse tuning error is limited to a coarse unit delay. After that, the circuit adjusts the delay of MDL by the medium tuning controller, and the medium code increases bit by bit to increase the delay until DCLK0 lags slightly behind SCLK. At this moment, a falling edge appears in the comparison result of the phase detector (COMP), and the medium tuning error is limited to a medium unit delay. Finally, the circuit turns on fine tuning and adopts the fine tuning controller to adjust the delay of FDL. The fine code decreases bit by bit to reduce the delay until DCLK0 is slightly ahead of SCLK, and the COMP has a rising edge. At this point, the de-skew circuit completes loop locking, and the alignment error is limited to a fine unit delay.  
At extremely wide operating frequencies, the de-skew circuit may face a situation where the clock skew is longer than one clock cycle, as shown in Figure 5. In this case, since the proposed de-skew circuit is an edge-triggered system, the skew will be cut off by the clock edge, producing an equivalent skew (\(t_{skew,eq}\)) that is always less than the clock period. This can be expressed as Equation (1):  
\[t_{skew,eq}=t_{skew}-\lfloor\frac{t_{skew}}{T}\rfloor\times T<T \tag{1}\]  
where \(\lfloor\rfloor\) is the mathematical rounding down symbol, and \(T\) is the clock period. As long as the equivalent skew is eliminated, the de-skew circuit can achieve clock alignment, and the \(t_{de-skew}\) is determined by \(T\) and \(t_{skew,eq}\), which can be given by  
\[t_{de-skew}=T-t_{skew,eq}<T \tag{2}\]  
In theory, any value of clock skew can be eliminated as long as the delay range of the de-skew circuit covers one clock period. This presents a great solution to solve the unpredictable skew in synchronous interfaces.