# FPGA-Based Methodology for Detecting Positional Accuracy Degradation in Industrial Robots
## 2 Materials and Methods
### Positional Accuracy Degradation FPGA Implementation  
Figure 9 shows a block diagram of the hardware implementation of the proposed methodology to determine if there is a deviation in the joints of the robot through the analysis of motor currents.  
Starting from the fact that there is a dataset of current signals from the robot's motors, as previously mentioned, the signal to be processed is divided into windows; these windowed signals are stored in the RAM of the processing card. The signal information corresponding to its first window is loaded into the FPGA. Then DWT coefficients corresponding to the first stage are loaded, and the DWT process is performed in the FPGA for that particular stage. Subsequently, information on the frequency band obtained in this process is moved to the calculation process of the RMS and variance statistical indicators. The indicators obtained are saved in the device's RAM at the end of the calculation. Later, the previously described procedure is repeated until the four stages, which correspond to the approximation and detail of decomposition levels three and four, are completed.  
When the calculation and storage of the statistical indicators of the approximations and details of levels three and four have been completed, they are moved to the FPGA processing of the classifier based on neural networks, where the classification obtained with the network is stored in the memory of the device. Subsequently, the window signal for the next joint is loaded, and the entire process is repeated until all six articulations have been completed.  
Figure 9: General scheme of the FPGA implementation of the proposed method.  
Figure 10 shows the general configuration of the system used to carry out the hardware implementation.  
The system comprises firmware processing containing 16-bit microprocessor modules, direct memory access (DMA), and Static Random Access Memory (SRAM). Whereas the hardware processing part comprises the DWT, statistical, and neural network models connected to the firmware processing through the data bus. Below are the modules corresponding to the main processes implemented in the FPGA, such as the DWT, the calculation of statistical indicators, and the neural network.  
The proposed methodology was implemented in a digital system using a low-cost proprietary designed board that is based on an FPGA. This framework is specifically designed for in-situ online data processing, eliminating the need for external communication with other systems for data processing. The board is equipped with a low-cost Spartan 6 XC6 SLX45 FPGA with a clock frequency of 48 MHz; it also features static random-access memory (RAM), communication ports such as the universal serial bus (USB), and universal asynchronous receiver transmitter (UART), power management, and flash memory. A 16-bit xQuP01v0 processor is embedded in the FPGA, besides an interconnection in-system bus (ISB), both proprietary designs; a broader description of the applications of the FPGA-based proprietary board can be found in [51; 52]. The input data used in the system is scaled to an input range of \([-2,2)\), and signal data are converted to a binary stream in 2.14 fixed-point format saved in onboard flash memory. As the process is executed, the microprocessor embedded in the FPGA uploads the data from the flash to the hardware calculation units and, when finished, reports the result via a USB to a user interface.