## 4 Implementation and Comparison
### Performance Comparison for the Softsign Function  
In this part, we compare the performance of the softsign function in the range of independent variables (\(-8\),8). The data of ML-PLAC are obtained from [29] and the data from [30] are used as a supplementary comparison. We use the same iw, qw, Node and MAE\({}_{\text{def}}\) (12, 10, 40 and 3.91 \(\times\) 10\({}^{-3}\), respectively, except that MAE\({}_{\text{def}}\) in [30] is 5.86 \(\times\) 10\({}^{-3}\)) for the comparison experiments. According to the particularity of the function, we use two methods to implement in this paper based on OML-PLAC method. Method a is implemented in the same way as the previous functions, and the independent variables are segmented from \(-8\) to 8. Method b uses the parity of the function to consider only the case when the independent variable is positive. When the independent variable is negative, the absolute value of the independent variable is taken as the input, and the corresponding negative complement code of the result is taken as the final output. Therefore, the range of independent variables for method b is [0,8) and the results are list in Table 9.  
The kw of the ML-PLAC method is 4 while the number is 2 in methods a and b. As a result, methods a and b require one less multiplier and one less adder each compared to ML-PLAC, which has a positive effect on the area and delay of the circuit. Method a gets 20 segments, and the critical path includes 1 16-bit comparator, 1 16:1 multiplexer, 1 14-bit adder and 1 16-bit adder. The design saves 36.32% area, 16.67% delay and 11.88% power. Method b gets 10 segments, and the critical path includes 1 16-bit comparator, 1 8:1 multiplexer, 1 14-bit adder and 1 16-bit adder. The performance of this design is much better and the design costs 59.92% less area, 25% less delay and 55.06% less power. The comparison results between the method in this paper and [30] are shown in the table, which will not be described in detail. \begin{table}
\begin{tabular}{c c c c c c c c c c c c c c c} \hline \hline \multicolumn{1}{c}{**Method**} & \multicolumn{1}{c}{**No.S**} & \multicolumn{1}{c}{**IO.F**} & \multicolumn{1}{c}{**NO.M**} & \multicolumn{1}{c}{**NO.A**} & \multicolumn{1}{c}{**qw**} & \multicolumn{1}{c}{**kw**} & \multicolumn{1}{c}{**Node**} & \multicolumn{1}{c}{**(**mm**)**} & \multicolumn{1}{c}{**(**GHz2**)**} & \multicolumn{1}{c}{**Area**} & \multicolumn{1}{c}{**Delay**} & \multicolumn{1}{c}{**Power**} & \multicolumn{1}{c}{**Energy**} & \multicolumn{1}{c}{**MAE\({}_{\text{Bord}}\)**} & \multicolumn{1}{c}{**MAE\({}_{\text{Bord}}\)**} & \multicolumn{1}{c}{**MAE\({}_{\text{Bord}}\)**} & \multicolumn{1}{c}{**MAE\({}_{\text{Bord}}\)**} & \multicolumn{1}{c}{**MAE\({}_{\text{Bord}}\)**} & \multicolumn{1}{c}{**MAE\({}_{\text{Bord}}\)**} & \multicolumn{1}{c}{**MAE\({}_{\text{Bord}}\)**} \\ \hline \multirow{3}{*}{This paper} & a & 20 & 12/12 & 3 & 2 & 10 & 2 & 40 & 1 & 3820.80 & 1 & 0.0653 & 0.065 & \(3.91\times 10^{-3}\) & \(3.91\times 10^{-3}\) \\ \cline{2-13}  & b & 10 & 12/12 & 3 & 2 & 10 & 2 & 40 & 1.111 & 244.67 & 0.9 & 0.0443 & 0.040 & \(3.91\times 10^{-3}\) & \(3.91\times 10^{-3}\) \\ \hline ML-PLAC & 42 & 12/12 & 4 & 3 & 10 & 4 & 40 & 0.83 & 600 & 1.2 & 0.0741 & 0.089 & \(3.91\times 10^{-3}\) & \(3.91\times 10^{-3}\) \\ \cline{2-13}  & \multicolumn{1}{c}{} & Compared to a & & & & & +20.48\% & \(-36.32\%\) & \(-16.67\%\) & \(-11.88\%\) & \(-26.97\%\) & - & 0\% \\ \hline  & \multicolumn{1}{c}{} & Compared to b & & & & & +33.73\% & \(-59.22\%\) & \(-25\%\) & \(-40.22\%\) & \(-55.06\%\) & - & 0\% \\ \hline
[30] & 32 & 12/12 & 2 & 1 & 10 & - & 40 & 0.50 & 1354 & 2 & 0.2132 & 0.430 & - & \(5.86\times 10^{-3}\) \\ \hline  & \multicolumn{1}{c}{} & Compared to a & & & & +100\% & \(-71.78\%\) & \(-50\%\) & \(-69.66\%\) & \(-84.88\%\) & & \(-33.28\%\) \\ \hline  & \multicolumn{1}{c}{} & Compared to b & & & & +122\% & \(-81.93\%\) & \(-55\%\) & \(-79.41\%\) & \(-90.70\%\) & & \(-33.28\%\) \\ \hline \hline \end{tabular}
\end{table}