# Implementation of a Lossless Moving Target Defense Mechanism
## 5 Protocol-Independent Packet Processors Programming  
The first version of the P4 language was developed by a team from Stanford University in 2014 [43]. The first language specification was also published in 2014, and was designated P414. Two years later, in 2016, the P414 standard was replaced by the P416 standard, which is currently in use. The latest version of the P416 standard is version 1.2.4 [44]. The P4 language is a programming language for the data plane in SDNs, meaning it is a programming language for SDN switches (although code written in P4 indirectly affects the control plane as well). Systems that use central processing units (CPUs) are Multi-Instruction stream Multidata stream (MIMD) systems. In contrast, data processing in programs written in the P4 language is of the Multi-Instruction stream Single-Data stream (MISD) type. The differences between these types are presented in Figure 4. Programs and data processing in the P4 language closely resemble the operation of EasyChip network processors, which are divided into Task-Optimized Processors (TOP), specialized for performing specific tasks. To enhance the performance of network processors, individual tasks are parallelized. The TOP processors include the following:  
* TOPparser: processors responsible for extracting relevant operations from processed protocol units. * TOPsearch: processors optimized for data search, such as finding the next hop for a packet or the port number through which a specific MAC address is accessible. * TOPselove: processors optimized for making decisions based on data provided by TOPSearch processors. * TOPmodify: processors optimized for modifying the structure of processed protocol units. The P4 language specification not only includes the definition of command syntax, control instructions, built-in functions, and data structures but also outlines two types of architectures:  
* Portable NIC Architecture (PNA): This architecture describes the common capabilities of Network Interface Cards (NICs) in network devices that process and transmit packets between one or more network interface and the host system. * PSA: An architecture that details the common capabilities of network switches in terms of packet processing and forwarding. PNA and PSA architectures facilitate the construction of any computer network (although they do not support the construction of access networks built on specific technologies like Passive Optical Networks (PONs)). They are used to build hosts and network nodes. Each architecture is associated with a defined platform, known as a target. This platform can range from general-purpose CPU, Field Programmable Gate Array (FPGA) devices, specialized Intel Tofino devices, or even Raspberry Pi boards. A significant difference among targets is their achievable performance, which varies from 10 Mbps (for Raspberry Pi devices) to 12 Tbps (when using Intel Tofino devices). The general PSA architecture, as presented in Figure 5, can be divided into three parts:  
* Ingress processing blocks;
* Egress processing blocks;
* A buffering and replication block. Depending on the target, the number of blocks may be smaller. Not all platforms support the implementation of all processing stages, and implementing all blocks may reduce performance without significantly affecting achievable functionality. The parser blocksshown in the figure are used to extract data relevant to applications. Fields of constant length are straightforward to extract from headers. It is sufficient to define the header of interest by specifying the number of bits the particular field occupies, and individual fields can be retrieved with a single command. However, for variable-length fields, the process is more complex, especially since there are many methods for determining the length of header fields. The last block in the packet path for both ingress and egress processing is the deparser block. Its task is reassembling the entire message.