# Updates on Impact Ionisation Triggering of Thyristors
## 2 Materials and Methods
### Boosted Gate Driver
Figure 6: Schematic of the driver with its main stages: \(NM1\_1\) and \(PM1\_1\) as the fist level-shifting step, then the two-stage Marx generator with \(Av1\_1\) and \(Av1\_2\), and finally the normally-off \(GH1\_1\) in source-follower configuration. The NMOS transistor \(NM1\_1\) in Figure 6 serves as the first level-shifting element, activated by a 45 V pulse at the \"Booster\" terminal. The capacitor C1_2 is in series with the gate capacitance of the NMOS, which serves as a gate-boosting element to ensure fast switching. The resistors \(R1\_1\) and \(R1\_2\) form a voltage divider that keeps the voltage in the steady state at <20 V. Following this, we find a similar configuration for the PMOS transistor \(PM1\_1\), with capacitor \(C1\_3\) acting as a gate-boosting element for the PMOS like C1_2 does for the NMOS, in series with its gate capacitance, and resistors \(R1\_3\), \(R1\_4\) and \(R1\_5\) as the voltage divider that keeps the steady state voltage <25 V in this case. The capacitor C1_1 serves as the bias voltage decoupling capacitor, whereas \(C1_4\) is placed to add the output signal of \(PM\_1\) to the 150 V feeding voltage of the avalanche transistor \(Av1\_1\) that follows. The avalanche transistors \(Av1\_1\) ([28]) and \(Av1\_2\) ([34]) work in a two-stage Marx generator configuration. Accordingly, the fast-rising pulse of the PMOS drain (voltage on C1_1 = 150 V) is added to the collector-emitter voltage of the avalanche transistor \(Av1\_1\) (biased to 150 V, which is the voltage on its energy storage capacitor C1_4) and triggers it in avalanche. The sum of voltages of C1_1 and C1_4 is then added to the collector-emitter voltage of the avalanche transistor \(Av1\_2\) (biased to 320 V, which is the voltage on its energy storage capacitor C1_5) and triggers it also in avalanche. At the end, the sum of the voltages on C1_1, C1_4, and C1_5 appears on the \(Av1\_2\) emitter, minus the corresponding voltage drops on \(PM\_1\), \(Av1\_1\), \(Av1\_2\) and on the series resistances of the energy storage capacitors C1_1, C1_4 and C1_5. It should be noted that the actual limitation of \(Av1\_1\) is approximately 165 V, as determined through laboratory testing. However, this is not the recommended producer use and therefore the biasing is limited to 150 V.  
After this two-stage Marx generator, its output voltage drives the 650 V rated GaN HEMT via its coupling capacitor C1_7. A decoupling capacitor for the GaN HEMT drain biasing C1_8 is grounded as close as possible to the SiC MOSFET source to reduce its gate current loop length and, therefore, inductance. This is carried out to maximize the speed of the SiC MOSFET gate charging. The driving circuit in Figure 6 employs a pulse trigger of 45 V, with a rise time of 425 ps and a slew rate of approximately 80 V/ns, as depicted in Figure 8b. This result stems from a custom voltage level-shifting process applied to the 10 V, 2 ns output signal from a Philips PM5786B (Fluke Co., Everett, WA, USA) pulse generator [35]. Utilizing gate-boosting, the input signal undergoes sharpening and amplitude amplification through the circuit shown in Figure 8a. Figure 7: Dimensions of the driver. A more compact layout allows for a reduced stray impedance.