# Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
## 2 Proposed SRAM Structure and Operation Principles
### MAC Operation  
The multiplication of two values within the proposed bit-cell architecture is achieved through binary multiplication, which is facilitated by assigning binary representations to the weight and input values, as demonstrated in Table 1. Specifically, the weight and input values are represented as binary 0 and 1, respectively. When the weight is 0, the word line left (WLL) is set to 0, and the word line right (WLR) is set to 1. Conversely, when the weight is 1, the WLL is set to 1, and the WLR is set to 0. This dynamic control of the word lines is managed through the word line driver, as depicted in Figure 2, which precisely modulates the word line signals based on the binary values of the assigned weight. In parallel, the input value is stored within the memory cell by manipulating the values stored in the storage nodes Q and QB. These input values are written into the respective storage nodes through a standard write operation, which is facilitated by the bit line (BL) and complementary bit line bar (BLB) drivers. The BL and BLB drivers modulate the voltages of the bit lines to write the correct input values into the storage nodes, ensuring that node Q holds the binary input and node QB holds its complement. Once both the weight and input values have been correctly stored in the memory bit-cell, the multiplication process is executed within the bit-cell itself. The multiplication result, which is the product of the input and weight, is output through the signal R2. R2 effectively represents the result of the binary multiplication, and this value is then utilized in subsequent operations. The values from multiple bit-cells within a column are summed through the voltage differences along a common line connected to R2, allowing the multiplication results to be accumulated across the column. Figure 4 provides a more detailed depiction of the multiplication process that occurs within the bit-cell during the execution of MAC (multiply and accumulate) operations. For the output from R2 to represent a value of 1, it is necessary for the NMOS transistor within the bit-cell to be turned on. In this scenario, the pre-charged value of BLB is subsequently discharged and output, allowing the multiplication result to be read. This process underscores the importance of precise transistor control in ensuring accurate binary multiplication within the bit-cell. The output of R2 thus serves as the intermediate result of the MAC operation, contributing to the final accumulation. \begin{table}
\begin{tabular}{c c c} \hline \hline
**Input (Q, QB)** & **Weight (WL)** & **0** & **1** \\
**(WLL = 0, WLR = 1)** & **(WLL = 1, WLR = 0)** \\ \hline
0 (Q = 0, QB = 1) & 0 & 0 \\ \hline
1 (Q = 1, QB = 0) & 0 & 1 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: In-memory binary multiplication of proposed 8T SRAM-CIM bit-cell. The final MAC operation, which aggregates the multiplication results from each bit-cell within a column, is performed by summing the outputs of R2 using the voltage differences generated between the bit-cells. This summation is performed through a differential voltage mechanism that takes advantage of the shared line connected to R2 across multiple cells. The outputs on R2 are accumulated through voltage differentials that are converted into a current form across a shared line allowing for an efficient summation across multiple cells. Back biasing plays a critical role here by adjusting the threshold voltages dynamically, which stabilizes the voltage levels across the cells and reduces variations in the output current. This not only supports a more accurate summation but also aids in maintaining low power consumption throughout the SRAM-CIM array, which is particularly beneficial for power-sensitive applications. To enhance both the accuracy and the low-power characteristics of the MAC operation, we apply the body voltage effect to the transistors P3 (a PMOS transistor) and N5 (an NMOS transistor), both of which are directly connected to the output node R2.