# An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields
## 1 Introduction  
The two well-known examples of public-key cryptography (PKC) are Elliptic curve cryptography (ECC) [1] and RSA [2]. Comparatively, the advantages of ECC include but are not limited to power efficiency, bandwidth optimization, and improved area utilization. The reason behind these advantages is the ability of ECC to provide a similar amount of security as RSA but with smaller lengths of the target key [3]. Considering larger key lengths contribute to maximizing security, however, for hardware accelerators, operating larger lengths of the target key with a low-area constraint poses serious challenges. Examples of these environments (operating larger lengths of the target key with a low-area constraint) include ubiquitous computing [4; 5; 6], radio-frequency-identification (RFID) networks [7; 8], and safe autonomous robots [9]. Therefore, this work aims to provide a hardware accelerator optimizing both throughput and area simultaneously for elliptic curve point multiplication. The point multiplication is the most computationally intensive part of ECC. Many organizations have accepted ECC as a standardization. One such organization is the National Institute of Standards and Technology (NIST). The NIST has offered two fields forECC to ensure secure and efficient communications [10]: prime fields, denoted as \(GF(P)\), and binary fields, represented as \(GF(2^{m})\). Moreover, NIST has specifically recommended various key lengths for these fields. For deployments, ECC includes a four-layer model [3]. The first layer encompasses essential operations such as encryption, decryption, signature generation, signature verification, and so on. The second layer operations are point addition (PA) and doubling (PD). The third-layer operation is the crucial operation in ECC, known as point multiplication (PM), and relies on the second-layer operations. Finally, the first layer is built upon modular arithmetic operators, including adders, squares, multipliers, and inversions. The performance of ECC's PM operation depends upon the implementation of first-layer operations. In addition to the four layers of ECC, there are two main alternatives for implementing ECC: a software implementation and a hardware implementation. Generally, software implementations such as microcontrollers offer higher flexibility with limited performance. On the other hand, field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) are used for hardware implementations [11]. The FPGAs are reconfigurable, while ASICs are application-specific. These hardware implementation platforms provide higher performance with limited flexibility. Moreover, hardware implementations are also beneficial for higher security because optimizing hardware circuits is much more crucial than software implementations written in C/C++, Python, or assembly. There is always a trade-off between performance and flexibility. Concerning the aforementioned advantages, we have preferred FPGA-based hardware implementations. The NIST-recommended binary fields are better suited for hardware implementation, while prime fields offer advantages in software-based platforms [3]. Prime fields require a carry bit when implementing polynomial addition. In addition, implementing polynomial additions with a carry bit utilizes a more complex circuit, increasing the hardware resources and maximizing the critical path delay. Polynomial addition can be performed for binary fields using a bitwise exclusive-OR operation, which avoids the carry bit during the implementation. The carry-free polynomial additions lead to improved computation time with optimized hardware resources and critical path delay. Thus, binary fields are implemented in this work. Another important aspect of ECC is the choice of a basis for point representation. Consequently, polynomial and normal [3] bases are employed. As far as the polynomial basis is concerned, it is generally preferred for optimized modular multiplications.