## 1 Introduction
This high number of iterations translates to a slow decoding process (fmax = 163.9 MHz), potentially limiting the algorithm's suitability for real-time communication scenarios that demand low-latency data transmission. Moreover, the fully parallel architecture was presented in [13]. While achieving parallelism, it suffers from increased hardware complexity due to its reliance on a 19-parallel 68:1 bulky multiplexer. These resource-intensive multiplexers significantly impact the overall decoder complexity. Furthermore, the design's dependence on column-wise addressing for cyclic shift operations limits its ability to process diverse base graph structures efficiently in terms of hardware resources. This limitation hinders its flexibility for deployment across a broader range of communication applications. These resource-intensive multi  
Figure 1: 5G-NR block diagram of the communication system. plexers translate to a substantial hardware burden, with the design requiring a staggering 1,448,762 lookup tables (LUTs) and 211,238 registers. These limitations suggest a need for a decoder architecture that balances complexity reduction with flexibility and faster decoding speeds. The proposed decoder architecture uses Mp:1 multiplexers for the reading network and 1:Mp demultiplexers for the writing network. This is because 5G-NR base graphs are naturally sparse, meaning that there are fewer rows than columns [15]. This makes sure that data transfer is fast. These multiplexers operate on individual rows, enabling a row-oriented design that significantly reduces the complexity of interconnection blocks compared to traditional column-based approaches. Our design leverages a highly adaptable shifting block. This block dynamically handles variable shifting values specified within the base graph entries, eliminating the need for pre-defined configurations for different shift amounts. This inherent flexibility empowers the decoder to seamlessly adapt to the diverse structures encountered in the BG1. Consequently, the proposed architecture offers broad applicability across a wide range of communication scenarios characterized by varying base graph structures. We leverage the benefits of a well-established low-latency decoding method proposed by [PERSON] [16]. This method is strategically implemented and incorporated for the first time within the check node processing block of our 5G-NR decoder. This innovative integration achieves remarkable results, showcasing the potential of this method for accelerating decoding in future communication technologies. The proposed decoder architecture achieves a balance between hardware efficiency and high-speed operation. It exhibits a resource footprint of 380,737 lookup tables (LUTs) and 32,898 registers, demonstrating efficient utilization of hardware resources. Furthermore, the design boasts the clock rate of 304.5 MHz, enabling significant throughput for real-time decoding applications. The remaining sections are structured as follows: Section 2 lays the groundwork by presenting essential background information on LDPC codes within the context of 5G-NR standards. Section 3 delves into the technical details, providing a detailed description of the proposed architecture and including digital representations of its internal blocks. Section 4 details the implementation results. Section 5 builds upon the technical foundation, thoroughly discussing the results and their analysis. Section 6 summarizes the key findings and potential implications of our work.