# Design and Application Space Exploration of a Domain-Specific Accelerator System
## 6 Results Analysis
### Performance Analysis  
To certify the performance advantage of RASP, the comparison of a representative algorithm-FFT is made. To compare the computation time of FFT, we choose the following processors as the references: a reconfigurable processor MorphoSys [28], a commercial DSP, and a multicore commercial processors Freescale T4240 [29; 30], the result is listed in Table 3 below. In the reference proposals, in order to obtain the clock cycles, Freescale T4240 \"assumed that all required instructions and data are present in the L1 cache\", and MorphoSys and TI DSP only count the cycles of computation too. It means that the data used for comparison are about computation phase, so we use the computation time of RASP as the comparison. We can infer from the table that the cycle count of MorphoSys is just a little bigger than RASP; however it should be noted that the computation resource of MorphoSys is two times more than RASP. As for the TI DSP, which has similar computation resources compared with RASP, the RASP can achieve 2.13x speedup. The power consumption is also listed in the table. As a dedicated accelerator, the RASP can achieve speedup with power savings. The RASP can achieve better performance improvement when dealing with complex tasks. Take STAP as an example, the decomposition of STAP is described in Table 1 and these steps are executed on different platforms. Table 4 below lists the detailed cycles of each step of STAP with the dimensions of 32 \(\times\) 1024. \begin{table}
\begin{tabular}{l l} \hline \hline Process Tech & 40 nm CMOS \\ \hline Die Size & 19.2 mm\({}^{2}\) \\ \hline Total SRAM & 2 MByte \\ \hline Data Precision & 32-bit Floating-point \\ \hline Power Supply & 0.9 V (nom.) \\  & 0.8–1.1V (operational) \\ \hline F\({}_{MAX}\) & 1.0 [EMAIL_ADDRESS] V \\  & 800 [EMAIL_ADDRESS] V \\ \hline Power Consumption & 1.2 W@FFT \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Chip summary of a single RASP core. \begin{table}
\begin{tabular}{c c c} \hline \hline \multicolumn{2}{c}{**Time Consumed for 1 K FFT**} & \multicolumn{1}{c}{**Power Consumption**} \\ \hline RASP & 2.57 μs@1 GHz & 1.2 W@FFT (75\% FU utilization ) \\ \hline MorphoSys & 5.8 μs@450 MHz & 4 W (peak MAC) \\ \hline TI DSP C6672 & 5.47 μs@1 GHz & 5.45 W (75\% MAC utilization) \\ \hline Freescale T4240 & 22.22 μ[EMAIL_ADDRESS] GHz & — \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Performance and power consumption comparison. \begin{table}
\begin{tabular}{l l l l l l} \hline \hline  & \multicolumn{3}{c}{**RASP**} & \multicolumn{1}{c}{**T1 DSP C6672**} &
\begin{tabular}{c} **Freescale** \\ **T4240** \\ \end{tabular} \\ \cline{2-6}  & **Computation** & **Transmission** & **Configuration** & & \\ \hline \(32\times 1024\) matrix covariation & 262,179 & 79,210 & 993 & 661,929 & 2,988,840 \\ \hline \(32\)-order matrix inversion & 56,384 & 9971 & 861 & 285,634 & 119,816,456 \\ \hline \(32\times 32/32\times 1\) matrix multiplication & 1058 & 9380 & 1129 & 1257 & 10,897 \\ \hline \(32\times 1\) matrix conjugation & 20 & 8117 & 924 & 32 & 37 \\ \hline \(1\times 32/32\times 1\) matrix multiplication & 56 & 9303 & 1161 & 64 & 65 \\ \hline \(1\times 1\) matrix conjugation & 17 & 6499 & 894 & 25 & 31 \\ \hline \(1\times 1\) dot product & 22 & 6427 & 990 & 46 & 31 \\ \hline \(32\times 1/1\times 1\) matrix multiplication & 56 & 6467 & 1167 & 469 & 65 \\ \hline \(32\)-point division & 344 & 6355 & 996 & 99 & 252 \\ \hline \(32\times 1\) matrix conjugation & 20 & 8117 & 924 & 32 & 37 \\ \hline \(1\times 32/32\times 1024\) matrix multiplication & 8226 & 72,707 & 1207 & 26,662 & 84,730 \\ \hline \multirow{2}{*}{Total} & 328,382 & 221,553 & 11,246 & 976,249 & 122,901,441 \\ \cline{2-6}  & \multicolumn{3}{c}{561,181} & \multicolumn{3}{c}{} \\ \end{tabular}
\end{table} 
Table 4: STAP execution on different platforms, the unit of the numbers is “cycle”.