## 4 Optical CAM Technology
### Ternary CAM Cell and Matchline Architecture
On the contrary, the final XOR output depends on the comparison result between the TCFF output and _search bit_ values when the XFF output equals a logical _\"1\"_: when both the TCFF output and _search bit_ signals have the same value, the XOR output is _\"0\"_, while in the opposite case, i.e., when they have different values, the XOR output equals _\"1\"_ and is imprinted on the XFF output at \(\lambda a\). By assigning a different wavelength for carrying the optical XOR output at every individual T-CAM cell within a row, all four of the T-CAM cell outputs can be combined at the row output by  
Figure 7: All-optical T-CAM cell architecture with two FFs (TCEFF & XFF) and a XOR gate and a T-CAM row’s AWG multiplexer for four indicative T-CAM cells. using an AWG multiplexer, as presented at the right side of Figure 7; \(\lambda a\) through \(\lambda d\) are used for the different cell outputs, while \(\lambda e\), \(\lambda f\), and the wavelengths used for the \(Set/Reset\) signals are employed in all T-CAM cells. This leads to a WDM-encoding scheme that produces the corresponding _ML signal_ at the final row output. In this way, an _ML signal_ of a logical value \"0\" indicates a completely matched comparison result since all the individual XOR outputs will be equal to a logical \"0\". On the contrary, a non-zero optical power level obtained at the encoder input indicates that at least one individual XOR output produces a comparison miss, denoting a non-completely matched row. A more generic representation of the proposed T-CAM row architecture is presented in Figure 8.  
Figure 9 presents the simulation results of the T-CAM row architecture for both Search and Write operations and at a line-rate of 10 Gb/s. The simulation models have been developed using the VPI Photonics suite and both the XOR gate and FF models are based on experimentally verified building blocks. The SOA model used in both the XOR gates and FFs is identical to the one presented and experimentally validated in [52]. The wavelengths used in the four-cell arrangement of Figure 7 are equal to: \(\lambda a\): 1564.19 nm, \(\lambda b\): 1562.56 nm, \(\lambda c\): 1559.31 nm, \(\lambda d\): 1557.36 nm, \(\lambda e\): 1554.78 nm, \(\lambda f\): 1546.12 nm, \(Set\): 1548.35 nm, and \(Reset\): 1551.88 nm. Figure 9a,b illustrate the \(Set/Reset\) pulse traces that are fed into the XFFs and determine whether the XFF has to define an \"X\" state for the T-CAM cell. Figure 9c,d illustrate the \(Set/Reset\) pulse traces that are fed into the TCFFs of the four cells dictating the logical content of every TCFF. Figure 9e depicts the XFF output signal, while Figure 9f illustrates the TCFF content transitions for every T-CAM cell. As can be seen in both Figure 9e,f, a successful bit storage operation is achieved according to the  
Figure 8: T-CAM row architecture comprising an indicative number of four T-CAM cells. Figure 9: 10 Gbps simulation results for the T-CAM row architecture of Figure 8: **(a)** the XFF Set; **(b)** the XFF Reset; **(c)** the TCFF Set; **(d)** the TCFF Reset; **(e)** the XFF; **(f)** the TCFF; **(g)** the Search Bit; **(h)** the XOR output; **(i)** the Matchline output signals, all with a time scale of 100 ps/div for traces and **(j)** the eye diagrams of the four TCAM cell outputs at 50 ps/div. respective _Set_/_Reset_ pulse traces; the presence of a _Set_ pulse leads to an FF content transition to the 0 logical state, while the presence of a Reset pulse leads to an FF content transition to the logical state of 1. Figure 9g presents the _search-bit_ pulse traces that are fed into the XOR gates of the four T-CAM cells as parallel streams in order to be compared with the respective T-CAM cell contents. The _search-bit_ pulse traces are NRZ \(2^{7}-1\) PRBS at a line-rate of 10 Gb/s. Figure 9h shows the XOR output signals that also form the T-CAM cell outputs and Figure 9i illustrates the power level of the final ML signal that is produced at the row output and just after the AWG multiplexer.