## 4 Case Study of Industrial Control Systems
### Modeling and Simulation Results  
This subsection applies the CPS resilience quantitative assessment framework proposed in Section 3 to the case of the diversity-redundancy security PLC. The framework follows the four-step modeling and simulation procedure described in Section 3.4.2. In Step 1, the key parameters to be assigned include the failure rate (\(\lambda\)), recovery rate (\(\mu\)), and malfunction consistency (\(\sigma\)). As shown in Table 3, we define these parameters based on their theoretical meanings, empirical knowledge, and penetration test results specific to the PLC under study. The parameter \(\sigma\) is determined by analyzing the historical software and hardware version data as well as known shared vulnerabilities across heterogeneous  
Figure 10: Photograph of the MCU physical device. Manufacturer: Purple Mountain Laboratories, Nanjing, China. Figure 9: Heterogeneous multi-core MCU architecture. The MCU architecture comprises 4 key subsystems: (1) heterogeneous multi-core CPU subsystem, (2) lightweight voting and decision subsystem, (3) bus and peripheral subsystem, and (4) application software and integrated development environment (IDE) subsystem. components. The recovery rate \(\mu\) is estimated using white-box fault injection tests, where artificial faults are introduced into redundant execution units to assess their average recovery speed. The testing methodology generally follows the process proposed in [17], and the test environment topology is shown in Figure 11. For brevity, detailed procedures are not repeated here. According to Step 2, we define three levels of the failure rate \(\lambda\) to represent high-risk, medium-risk, and low-risk operational environments. With fixed design parameters \(\mu\) and \(\sigma\), we perform simulations of the CTMC model under each threat scenario. The state transition probabilities and steady-state distributions are computed accordingly. The results of the simulations are summarized in Table 4, providing insight into how the PLC behaves across different environmental conditions. These results also serve as the foundation for subsequent parameter normalization and performance curve construction. In Step 3, we standardize the key performance-influencing parameters derived from the CTMC model. This enables their integration into the coupled cyber-physical resilience model. The normalized values of critical parameters (e.g., duration of each segment and maximum response capacity) are calculated based on the outputs from Step 2 and are shown in Table 5. This step facilitates the transition from abstract stochastic models to \begin{table}
\begin{tabular}{c c c} \hline
**Adverse Conditions** & **Metrics** & **Values** \\ \hline \multirow{3}{*}{\(\lambda=10\) s} & AP & 0.7436 \\  & EP & 0.0021 \\  & DP & 0.2543 \\ \hline \multirow{3}{*}{\(\lambda=30\) s} & AP & 0.9189 \\  & EP & \(6.09\times 10^{-4}\) \\  & DP & 0.0805 \\ \hline \multirow{3}{*}{\(\lambda=1\) min} & AP & 0.9901 \\  & EP & \(5.93\times 10^{-5}\) \\ \cline{1-1}  & DP & 0.0098 \\ \hline \end{tabular}
\end{table} 
Table 4: Simulation results of CTMC model under different adverse conditions. Figure 11: The MCU test environment topology. dynamic performance simulations, bridging the gap between cyber-layer behavior and physical-layer impact. Finally, leveraging the mathematical modeling framework in Section 3.2 and the parameter set established in the previous steps, we simulate and visualize the PLC's resilience response under cyber disturbances. The resulting resilience curves are shown in Figure 12, demonstrating the time-varying performance trajectory of the system in different adverse conditions. The resulting resilience curves reveal that, due to the relatively low failure probabilities in all three simulated conditions, the primary differences lie in the time proportions spent in degraded and available states. Typically, system resilience can be evaluated through multiple aspects, including the area under the degradation phase of the curve, recovery time, and robustness.