## 3 Unit Cell and MS Reflector Concept and Design  
The unit cell design was adopted and optimized for the X-band and Ku-band using mushroom geometry combined with a varactor diode. Such an MS structure is also known as a reconfigurable high impedance surface due to its reflection properties compared to a metal surface [36]. The geometry and dimensions of the optimized unit cell and the standard unit cell are shown in Figure 5.  
Figure 5a,b shows the unit cell structure, with the varactor diode marked in a green rectangle. The unit cell area sizes are 4.2 mm \(\times\) 4.2 mm, with a thickness of 1.68 mm. The unit cell sizes in wavelength units are 0.168\(\lambda_{0}\)\(\times\) 0.168\(\lambda_{0}\)\(\times\) 0.065\(\lambda_{0}\), where \(\lambda_{0}\) is the free-space wavelength at the operation frequency of 12 GHz. The main unit cell dimension parameters are shown in Figure 5a. The unit cell comprises two dielectric substrates of the Rogers company, model 5880 LZ, with a thickness of 0.762 mm and a dielectric constant \(\varepsilon_{r}=2\)[41], and three copper layers (in yellow), each with a thickness of 0.0175 mm. The top copper layer is the square patch. The middle copper layer is for metal ground purposes, separated by a clearance from the via that crosses it. The back-side copper layer is for DC biasing purposes, which is connected by a via with a diameter of 0.3 mm to the top copper layer, thus, to the varactor (shown in Figure 5b). The unit cell geometry, dimensions, materials, varactor, and the PCB manufacturing process quality determine the total capacitance \(C\) and the inductance \(L\). The surface area and the patch size of the unit cell are proportional to the unit cell's intrinsic capacitance \(C_{int}\). The thickness of the dielectric substrate is proportional to the unit cell's intrinsic inductance \(L_{int}\)[8; 11]. Adding the variable varactor capacitance \(C_{d}\) to the MS changes the total unit cell capacitance \(C\) to \(C=C_{int}+C_{d}\). The total unit cell inductance is defined as \(L=L_{int}\) for the equivalent circuit model in Figure 1b and Equations (1)-(5). Reducing the unit cell's dimensions decreases the \(LC\) product in Equation (3), which is necessary for high \(f_{res}\) values. As shown in Equation (5), reducing \(C\) decreases the \(Q\) and thus the total unit cell losses \(R\times Q\). Therefore, reducing \(C_{int}\) values rather than \(L\) is required to decrease the \(LC\) product in Equation (3), allowing for a high operation frequency. Furthermore, the decrease in \(C\) values increases the bandwidth and minimizes the phase errors (see Equation (4)). The unit cell's low capacitance and the high tuning capacitance  
Figure 5: Unit cell design: (**a**) unit cell side view, (**b**) unit cell front side, and (**c**) standard patch unit cell design. ratio are the fundamental requirements for allowing high-frequency implementation of the reconfigurable phase gradient MS reflector with continuous reflection phase control. Following these requirements, a varactor diode of MACOM model MAVR-011020-11411 was chosen as a tuning element. It allows for a continuous and high dynamic range regarding the capacitance value. To the best of our knowledge, this varactor diode has the lowest capacitance in the market. The varactors enable high-frequency operation; a continuous, high-capacitance dynamic range; low power consumption; and simplicity in manufacturing [42]. Decreasing the value of \(C_{int}\) makes the value of \(C_{d}\) more dominant in the total unit cell capacitance \(C\) and increasing its dynamic tuning range. Using a dielectric substrate with \(\varepsilon_{r}=2\) and reducing the unit cell and patch sizes reduces the value of \(C_{int}\)[11; 17; 18; 19; 36]. The reduction in the patches prevented the varactor from being placed directly on the adjacent patches' edges (blind pad), as in other works [8; 15; 28; 30]. In this design, the distance between the unit cell patches edges was 1.34 mm, while the varactor length dimension is 0.76 mm [42].