# Research on Tracking Technique Based on BPSK-CSK Signals
## 3 Results
### Verification Results  
The architecture of the verification platform for the BPSK-CSK signal tracking method is shown in Figure 11, which mainly consists of the 7Z100 SOC chip and two ADRV9009 RF chips and the corresponding peripheral devices. The 7Z100 SOC chip adopts the ARM Cortex-A9 core and kintex 7 FPGA, and extends the interfaces of FMC, fibre optic, and IO  
Figure 10: Code-tracking error. Figure 9: Carrier-tracking error. through the FPGA at the PL side. The ARM at the PS side extends the interfaces of network, USB, and RS232 etc. The 7Z100 SOC chip integrates various functional modules such as high-speed data interface, digital signal processing module, memory control module etc. The ARM on the PS side extends interfaces such as network, USB, RS232, etc. The 7Z100 SOC chip integrates a variety of functional modules, such as high-speed data interfaces, digital signal processing modules, memory control modules, etc. The ADRV9009 is a dual-channel RF transmitter and receiver with an observation receiver. Operating over the frequency range of 75 MHz to 6 GHz, the device's transmitter supports a synthesis bandwidth of up to 450 MHz. The receiver portion of the device can operate either as a dual-channel receiver supporting bandwidths up to 200 MHz or as a single-channel observation receiver supporting bandwidths up to 450 MHz. Data transmission is accomplished through eight JESD204B dedicated high-speed interface channels. There are four interface channels, each for transmitter data and main receiver/observer data. The platform can be divided into the processor system part (PS) and programmable logic part (Programmable Logic, PL). The PS side and PL side of the platform respectively hang two pieces of the 1 GB high-speed DDR3 SDRAM chip, so that the ARM system and the FPGA system can independently process and store the data function. PS side of the FPGA expansion of the Ethernet RJ45 interface, SD card interface, UART serial interface, 256 Mb QSPI FLASH chip. PL side of the ARM expansion connected to the 10 G. The ARM expansion on the PL side is connected with the 10 G SFP+ module, 40 GB QSFP interface, 80-pin GPIO, and two ADRV9009 RF chips. A 256 Mb QSPI FLASH is used for the static storage of ZYNO's operating system, file system, and user data. The clock generator AD9528 accesses the SYSREF signal and connects to the TXCO/EXFREF interface, which is used to synchronise multiple devices such as ADRV9009 and ADF5356. In the experiments using the 7Z100 SOC chip and the ADRV9009 RF chip for signal tracking, the Doppler value was 1000 Hz, the sampling time was 10 s, and the parameters of the carrier- and code-tracking loops are shown in Tables 1 and 2 in the previous section. We tested three different methods, the output data for the output tracking results, and recorded their respective signal convergence processes using Origin. The curves of the i-branch integral values over time for the three methods are shown in Figure 12, and the experimental results demonstrate the differences in signal convergence among the three methods. Figure 11: BPSK-CSK signal tracking program verification platform. Figure 12: Tracking loop handling in three scenarios: (**a**) is Tracking Loop Processing for Method 1; (**b**) is Tracking Loop Processing for Method 2; (**c**) is Tracking Loop Processing for Method 3. By comparing the convergence processes of the three methods, we find that the tracking method proposed in this paper performs well in terms of convergence time. Compared with Methods 1 and 3, the method in this paper is able to converge to the steady state more quickly, showing its superior convergence performance. This fast convergence property makes this paper's method have higher real-time and response speeds in practical applications, which can better meet the demand for fast tracking. Compared with Methods 1 and 3, the method in this paper exhibits good signal convergence characteristics and demodulation performance in addition to a fast convergence time.