# A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit
## 3 Critical Circuit Description
### The Proposed Fall-Edge-judgment Phase Adjuster  
The traditional HDSC architecture requires a clock duty cycle of 50%, but the clock may be seriously distorted due to the mismatch between the pull-up and pull-down of clock drivers in the transmission path, making the HDSC lose the advantage in shortening the  
Figure 5: The relationship between the real skew and equivalent skew.  
length of the delay line. The proposed fall-edge-judgment phase adjuster is independent of the clock duty cycle and can be easily applied to the HDSC-based de-skew circuit to widen the frequency range. Figure 6 shows the structure and adjustment strategy of FPA, where signal CLKI is the delayed version of SCLK, the signal CLKI' is the phase-adjusted version of SCLK, and SEL is the judgment signal in the FPA. In the adjustment stage of the de-skew circuit, FPA selects 0\({}^{\circ}\) or 180\({}^{\circ}\) of CLKI for CLKI' according to the relationship between the falling edge of DCLK0 and the high/low levels of SCLK.  
As shown in Figure 6, when the falling edge of DCLK0 samples the low level of SCLK, the FPA outputs 180\({}^{\circ}\) of CLKI. The new DCLK0 rising edge will appear at the position of the previous falling edge; then, \(t_{de\text{-}skew}\) rapidly changes from greater than the low-level pulse width of clock (\(t_{low}\)) to less than \(t_{low}\). This can be expressed as Equation (3):  
\[t_{de\text{-}skew}=T-(t_{skew,eq}+t_{high})\leq t_{low} \tag{3}\]  
where \(t_{high}\) is the high-level pulse width of the clock. Conversely, when the falling edge of DCLK0 falls into the high level of SCLK, FPA outputs the 0\({}^{\circ}\) of CLKI, and \(t_{de\text{-}skew}\) is less than \(t_{high}\). It can be expressed as Equation (4):  
\[t_{de\text{-}skew}=T-t_{skew,eq}\leq t_{high} \tag{4}\]  
Thus, \(t_{de\text{-}skew}\) is less than \(\max(t_{high},t_{low})\) after phase adjustment. At a defined clock frequency with a duty cycle distortion level of \(x\), \(\max(t_{high},t_{low})\) is \((50\%+x\%)\) of the clock period, so the delay range of de-skew circuit only needs to cover \((50\%+x\%)\times T\) to ensure locking. If the sampling is based on the rising edge, DCLK0 samples high level and FPA selects 180\({}^{\circ}\) of SCLK in both cases of Figure 6. Obviously, in the second case, if FPA selects 180\({}^{\circ}\), \(t_{de\text{-}skew}\) will be greater than \(t_{high}\), and the delay line range needs to cover the entire cycle to ensure locking, which indicates that HDSC has lost the advantage in shortening the delay line. The falling edge contains information of the duty cycle distortion, which is the basis of the FPA judgment strategy.  
According to the basic principle of the de-skew circuit, the maximum delay of the delay line (\(T_{DCDL,max}\)) determines the minimum operation frequency of circuit (\(f_{min}\)). Thus, without the phase adjustment stage, \(f_{min}\) can be expressed as Equation (5):  
\[f_{min}=\frac{1}{T_{DCDL,max}+t_{int}} \tag{5}\]  
Figure 6: The structure and adjustment strategy of FPA. (**a**) Structure; (**b**) adjustment strategy.  
where \(t_{int}\) is the intrinsic delay of other logic units and buffers in the delay path. With the same length of the delay line, when the phase adjustment stage is added, \(f_{min}\) is given by  
\[f_{min}=\frac{50\%+x\%}{T_{DCDL,max}+t_{int}} \tag{6}\]  
In summary, with a certain delay line length, the HDSC-based de-skew circuit with a duty-cycle-independent FPA can widen the operating frequency range.