# A Forwarding Latency Optimization Method for Software Data Plane Based on Spin-Polling
## 4 Model Analysis  
In this section, we qualitatively analyze the experimental results in Section 3.2 through a simple model. Our model is based on a single Rx queue, but the conclusions can be easily generalized to scenarios with multiple Rx queues. The analysis in this section also inspires  
Figure 4: The performance of data plane with different Batch Size. (**a**) \(\theta_{Tx}=64\). (**b**) \(\theta_{Rx}=64\). Figure 5: The average latency under different input rates and different \(\theta_{Tx}\). us to propose an optimization method to optimize the packet latency of the data plane based on the spin-polling system and the batch mechanism. Note that the experiments in Section 3.2 use fixed-length packets, so when we discuss the experimental results in Section 3.2, we do not need to distinguish between the packet arrival rate and the traffic arrival rate. However, in actual scenarios, since the packet lengths cannot be the same, the packet arrival and the traffic arrival rates cannot be confused. Table 2 represents the main notations used in this section. The packet arrivals can be regarded as a batch arrival process, as shown in Figure 6. The packet arrivals can be described by a sequence \(\{\cdots,(b_{j-1},t_{j-1}),(b_{j},t_{j}),(b_{j+1},t_{j+1}),\cdots\}\), where \(b_{j}(b_{j}\in\mathbb{Z}^{+})\) represents the number of packet in this batch and \(t_{j}(t_{j}>0)\) is the time interval between this batch and next batch of packets. The available data buffer addresses are stored in the Rx queues. When the packets arrive at the port, the NIC will write them to the memories where the data buffer addresses point to. The CPUs do not participate in this procedure and therefore do not wait for the packets to be written to memories. We assume that the CPU checks the Rx queues \(m\) times between packets forwarding, and the number of packets received is \(B_{1}\), \(B_{2}\), \(\cdots\), \(B_{m}\), and \(B_{i}\) satisfies the following formula:  
\[B_{i}=\sum_{j=1}^{n}b_{ij},b_{ij}\in\mathbb{Z}^{+}\quad\text{when}\quad B_{i} \
eq 0(1\leqslant i\leqslant m) \tag{1}\]  
where \(b_{ij}\) is the \(j\)-th small batch packets of \(B_{i}\). Formula (1) means that if the number of packets polled by the CPU is not equal to 0, then these packets are composed of multiple small batches. The residence time \(RT\) of the \(b_{ij}\)'s packets in the data plane can be expressed by the following formula:  
\[RT_{ij}=QR_{ij}+P_{i}+QT_{i} \tag{2}\]  
where \(QR_{ij}\) is the queuing time of \(b_{ij}\)'s packets in Rx queues, \(QT_{i}\) is the queuing time of \(B_{i}\)'s packets in Tx queues and \(P_{i}\) is the time taken by CPUs to process \(B_{i}\)'s packets. As mentioned in Section 2.3, there are two packet forwarding modes in the data plane: regular burst mode and timeout flush mode. The data plane will mainly use the timeout flush mode when the packet arrival rate is low, and the regular burst mode will be the primary mode when the packet arrival rate is high. Assuming that \(N\) is the polling counter threshold, \(\tau\) is the time interval for CPU polling when no packets arrive, which means that when \(B_{i}=0\), \(P_{i}=\tau\). \begin{table}
\begin{tabular}{c l} \hline \hline
**Notation** & **Description** \\ \hline \(b_{i}\) & The number of packets in small batch \\ \(t_{i}\) & The time interval between \(b_{i}\) and \(b_{i+1}\) \\ \(B_{i}\) & The number of packets received by the CPU at one time \\ \(m\) & The number of times the CPU receives packets between packets forwarding \\ \(N\) & The polling counter threshold \\ \(RT\) & The residence time of packets on the data plane \\ \(P\) & The time taken by CPUs to process packets \\ \(QT\) & The queuing time of packets in Tx queues \\ \(QR\) & The queuing time of packets in Rx queues \\ \(\tau\) & The time interval for CPU polling when no packets arrive \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Summary of Notations. Figure 6: Schematic diagram of packets arrival in batches. Now we consider the case where the packet arrival rate is very low.