# Building Reliable Massive Capacity SSDs through a Flash Aware RAID-Like Protection +
## 6 Analysis of Reliability and Lifetime of SSDs  
In this section, we analyze the reliability and lifetime of the SSD through deriving equations of the error rates for mSAPL and the state-of-the-art flash aware RAID technology, called eSAP [14]. The raw bit error rate (\(RBER\)) of the flash memory increases exponentially with respect to the P/E cycle, as follows. In this equation, \(x\) denotes the P/E cycle of a block, and \(A\) and \(B\) are constant values according to the type of flash memory and process [38]. \[RBER(x)=A\cdot e^{Bx} \tag{1}\]  
In order to reduce the error of a page, the flash memory records the ECC in the spare area whenever the page is written [45,48]. The ECC code is capable of correcting up to \(k\) bit errors per specific code word (\(n\)). Correctable page error rate (\(CPER\)) and uncorrectable page error rate (\(UPER\)) can be calculated as binary distributions, as follows [10,51]. \[ \begin{split} CPER(n,k,x)&=\sum_{i=0}^{k}\binom{n} {i}\ RBER(x)^{i}(1-RBER(x))^{n-i}\\ UPER(nk,x)&=1-CPER(n,k,x)\end{split}  \tag{2}\]  
However, the ECC has a limitation, in that, if the number of error bits exceeds \(k\), then the error can not be corrected by the ECC. To solve this problem, a method for correcting page errors through RAID-like technologies have been introduced [11,14]. A RAID stripe consist of a certain number of multiple pages, including a fixed number of parity pages for recovering errors. Therefore, errors that cannot be corrected by ECC are recovered through RAID parity. However, in order to perform error recovery through RAID parity, errors must first be detected through ECC. ECC can correct errors up to \(k\) bits and detect errors up to \(2k\) bits. Therefore, the detectable page error rate (\(DPER\)), which can not be corrected, but detected by ECC, is defined, as follows. \[DPER(n,k,x)=\sum_{i=k+1}^{2k}\binom{n}{i}\ RBER(x)^{i}\cdot(1-RBER(x))^{n-i} \tag{3}\]  
In case of one parity per stripe (i.e., a RAID5 type configuration), failures can be recovered for the following two cases: (1) pages in a stripe have correctable error bits by ECC. (2) detectable errors by the ECC occur in one page in a stripe and correctable errors by the ECC occur in the remaining pages. Therefore, the uncorrectable page error rate with the ECC and RAID5 configuration are derived is as follows. \[ \begin{split} UPER_{RS}(n,k,x)=&\frac{1}{N}\bigg{(} 1-\binom{N}{0}\ CPER(n,k,x)^{N}\\ &-\binom{N}{1}\ CPER(n,k,x)^{N-1}\\ &\cdot DPER(n,k,k)\bigg{)}\end{split}  \tag{4}\]  
Let us consider a case where two parities per stripe are maintained (i.e., a RAID6 configuration). In case of the RAID6 configuration, two pages can be recovered when errors in two pages that canbe detected by ECC occur simultaneously. Therefore, the uncorrectable page error rate is calculated, as follows. \[UPER_{R6}(n,k,x)= \frac{1}{N}\bigg{(}1- \begin{pmatrix}N\\ 0\end{pmatrix} CPER(n,k,x)^{N} \tag{5}\] \[- \begin{pmatrix}N\\ 1\end{pmatrix} CPER(n,k,x)^{N-1}\] \[\cdot DPER(n,k,k)\] \[- \begin{pmatrix}N\\ 2\end{pmatrix} CPER(n,k,x)^{N-2}\] \[\cdot DPER(n,k,k)^{2}\bigg{)}\]  
mSAPL has lower WAF than that of eSAP for all three workloads, as shown in Figure 5. Figure 7 compares the page error rates of mSAPL and eSAP when running the Financial workload on the SSD simulator. The uncorrectable page error rates in the figure are derived from Equation (5), which means that mSAPL and eSAP maintain two parities per stripe (i.e., employing RAID6 configuration). Table 3 presents the parameters of the equations for calculating the _UPER_. mSAPL shows lower _UPER_ than that of eSAP until about 19,000 P/E cycles. The reason of the lower _UPER_ of mSAPL is that mSAPL reduces WAF as compared to the state-of-the-art RAID technology, called eSAP. Assuming that the acceptable error rate is the error rate of hard disk (1.0 \(\times\) 10\({}^{-15}\)), the lifespan of the SSD while using mSAPL technique is increased by 1.16 times when compared to eSAP. parity management, a parity update policy should be designed to minimize a GC overhead in SSDs.