# Updates on Impact Ionisation Triggering of Thyristors
## 2 Materials and Methods
### Boosted Gate Driver  
To achieve the SiC MOSFET boosting presented in Section 2.1, we previously designed a specialized driver (Figure 4) capable of delivering 430 V/ns to a 50 \(\Omega\) load, with a maximum output voltage exceeding 300 V. The resulting output voltage was first presented in [19], as seen in Figure 5. We profit from the rapid switching capability of an avalanche transistor (Av0_1, [28]) to increase the output pulse dU/dt. The first aspect when choosing the transistors for this driver is their rise time as declared on the datasheet. The faster the transistor, the better for our purposes: potentially, a fast transistor will reach a higher dU/dt and will therefore deliver a pulse that has more chances of resulting in driving the subsequent switching components in gate-boosting mode. Secondly, the total gate charge of the transistors is taken into account. Choosing a transistor with a lower total gate charge \(Q_{g}\) is advantageous because it leads to faster switching speeds and a lesser strain to the driver that switches it on, since it will need to provide less current. After reviewing our prior research, we pinpointed a potential limitation in the driver's output current, if it was to be used to drive one or more parallel SiC MOSFETs with a significant gate charge. To tackle this challenge, we propose enhancing the driver with a GaN HEMT [29] current-boosting stage configured as a source follower (Figure 6). This upgrade is designed to amplify the output current while simultaneously reducing the stage's output impedance. Its placement on the PCB aims to minimize the loop surface and thereby  
Figure 4: Schematic of the previous version of the SiC MOSFET gate-boosting driver. Figure 5: Output voltage of the gate-boosting driver on Figure 4, on a 50 \(\Omega\) load at a charging voltage of 320 V. Maximum amplitude of 300 V and \(t_{r}=1\) ns, measured between 10–90%. decrease stray inductance, as seen in Figure 7. Consequently, one of the criteria in choosing the driver's transistors is based on the shape and size of the package. The decision to employ a GaN HEMT in the setup on Figure 6 is driven by the parameters detailed in Table 1. In comparison to alternative options with identical datasheet drain-source voltage and continuous drain current, the GaN HEMT demonstrates a significantly reduced total gate charge. During the switching process, the gate charge is required to be supplied to the switch's gate. A lower total gate charge corresponds to faster switching. Additionally, opting for a switch with a lower gate charge simplifies the design of the driving circuit, resulting in a compact solution, as the one presented in this paper. Regarding the package size criterion, the smaller form factor of the GaN HEMT results in decreased stray inductance. Overall, it is the most suitable component to meet our requirements. Presently, on Figure 6, the initial stage involves a driving mechanism intended to elevate the triggering voltage while simultaneously refining the turn-on characteristics of the driving pulse. This driver comprises three essential components, seen in Figure 6: a level-shifting MOS circuit, a two-stage avalanche transistor Marx generator, and a source-follower GaN HEMT. The circuit up to the two-stage avalanche transistor Marx generator has been presented in previous works ([19; 20; 21; 22]). The level-shifting circuit comprises two main components: an NMOS transistor (FDN86246 [32]) and a PMOS transistor (FDMC8626P [33]). \begin{table}
\begin{tabular}{l c c c} \hline \hline
**Parameter** & **GaN GS66508T [29]** & **Si TK099V65Z [30]** & **SiC NVBG095N065 SC1 [31]** \\ \hline Package & GaNPX® & DFN8\(\times\)8 & D2 PAK7L \\ \hline \(U_{DS}\) (V) & 650 & 650 & 650 \\ \hline \(l_{D}\) (25 \({}^{\circ}\)C) (A) & 30 & 30 & 30 \\ \hline \(l_{DM}\) (25 \({}^{\circ}\)C) (A) & 60 & 120 & 79 \\ \hline \(Q_{Sac}\) (nC) & 6.1 & 47 & 50 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Comparison of choice criteria for GaN HEMT, Si MOSFET, and SiC MOSFET devices.