## 5 Results and Discussion  
To analyze the impact of the contact area between the interconnect and via on resistance, various structures implemented in the simulation were fabricated through an actual process, and their resistance values were measured. Pads were formed at both ends of the interconnect, and resistance measurements were conducted using a probe station in a two-probe configuration. For electrical characterization, the MST4000 probe station (MSTECH, Gwangju, Republic of Korea) and the Keithley 4200 parameter analyzer (Keithley, Cleveland, OH, USA) were used, and the measurements were conducted under room temperature and atmospheric pressure conditions. The measurement conditions involved sweeping the voltage while recording the corresponding resistance values. The voltage sweep range was set from \(-0.5\) V to \(0.5\) V, and resistance values for each structure were  
Figure 8: Process flow for metal line formation on a SiO2 substrate.  
Figure 9: Optical microscope (OM) images of the metal line–via–metal line structure with via lengths of (a) 10 \(\upmu\)m and (b) 100 \(\upmu\)m.  
calculated using [PERSON]'s law (V = IR) based on the extracted voltage-current data [15]. To analyze how the measured resistance values vary with changes in the via-interconnect contact area, measurements were conducted on a total of eight different structures.  
Figure 10 presents the resistance measurement results for the via structure with a length of 100 \(\upmu\)m. The \(x\)-axis represents different structural configurations based on variations in the contact area. The label 'Over' indicates an excessive contact area, while '0' represents a perfectly aligned via and interconnect. The subsequent labels, '25', '50', '60', '70', '80', and '90', denote structures where the contact length was progressively reduced to 25%, 50%, 60%, 70%, 80%, and 90% of the fully aligned state (0). The results indicate that resistance increases as the contact area decreases. Notably, beyond the '50' mark, where only 50% of the via and interconnect are in contact, the resistance exhibits a sharp increase. This trend aligns with the predictions from the simulation, confirming that the simulation results are applicable to real fabrication processes.  
'Over' indicates a state where the interconnect is fabricated larger than the via, extending beyond the via position, while '0' represents a state where the ends of the via and interconnect are perfectly aligned. The values from 25 to 90 represent the degree of misalignment (20% to 90% misalignment). The results show that resistance increases as the contact area decreases, exhibiting an exponential trend. Notably, beyond the '50' mark, where only 50% of the via and interconnect are in contact, the resistance increases sharply by more than 15%. This trend aligns with the predictions from the simulation, confirming that the simulation results are applicable to real fabrication processes. Therefore, even when an interconnect-to-via misalignment of up to 25% occurs, the actual increase in resistance is less than 10%, not proportional to the 25% misalignment. Utilizing these results, the margin allocated to account for interconnect-to-via misalignment can be reduced. In other words, it is possible to propose a design rule that allows for higher integration density by considering acceptable resistance loss limits.  
This study experimentally verified that the current density and resistance characteristics of interconnect-via structures derived from simulations can be consistently applied to actual fabrication processes. Additionally, it demonstrated that optimizing design rule margins through process parameter adjustments can contribute to scaling down. These  
Figure 10: Measured resistance values for the metal line-via-metal line structure with a via length of 100 \(\upmu\)m as a function of misalignment.  
findings can serve as critical guidelines for margin allocation in future semiconductor interconnect design.