## 2 Electronic Address Look-Up Memory Architectures  
Internet routers forward the data packets of an incoming port to an outgoing port based on an AL comparison function of the destination address of the header. To achieve this, they are equipped with a hardware look-up table that maintains the RIB-list of the destination addresses and their associated outgoing ports for next-hop routing, as depicted in the AL memory table architecture of Figure 1a. The architecture comprises a two dimensional CAM table inter-connected to a two dimensional RAM table. The CAM table stores the prefix-list with the destination addresses, while the RAM table maintains the outgoing port. Each entry of the RIB prefix-list is stored in a mutli-bit memory line, widely known as CAM ML. Upon the arrival of a packet, the header containing the destination address bits is broadcasted to all MLs of the CAM table, where it gets bitwise compared with the contents of the CAM cells. When the stored word of a specific ML matches the incoming search bits of the destination address, a match-signal is generated at the output of the ML, activating the specific line; otherwise, the CAM ML is not enabled. The activated CAM ML can then be mapped though the intermediate encoder-decoder network to the associated RAM table line, where the next-hop routing information is stored, so as to retrieve the outgoing port of the data packet. An example operation of the AL table is described by the RIB table shown at the right side of Figure 1a, assuming an incoming packet designated with a destination address [0111] and an RIB-list with four entries, namely [001[010\(X\)], [011\(X\)], and [10\(XX\)]. By broadcasting and bit-wise comparing the destination address with all the RIB-entries, the third prefix of [011\(X\)] matches the packet's destination address. This matching will in turn activate the third line of the RAM forwarding table where port C is stored, indicating the next hop to which the incoming packet has to be forwarded. A more detailed view of the block diagram describing the logical circuit operation of the 1 \(\times\) 4 ML is shown in Figure 1b, comprising four parallel CAM cells. The CAM cells have their outputs combined at an inline Sense Amplifier (SA) and are then inter-connected to the encoder/decoder network for communication with the RAM table. Every CAM cell stores a bit of a RIB prefix entry and bears a logical XNOR gate for comparison with the incoming search bits of the destination address. If the search bit and the stored bit are equal, the logic XNOR gate transmits a signal of logic \"1\" value to the end of the respective ML. Equivalently, when all CAM cells of the line provide a logical match, the SA identifies the exact word match with the stored content and emits a proper signal towards the encoder. On the contrary, when there is a mismatch at any of the bits of the ML, the XNOR gate of the CAM cell provides a logical \"0\" value at the output, and de-activates the SA and the ML, denoting that a mismatch between the incoming destination address and the stored prefix has occurred. At this point, it is worth noting that MLs consist of Ternary T-CAM cells, in order to support ternary features with masked wildcard bits of \"logical \(X\)\", as used in subnet masks, rather than simpler Binary CAM cells that store only bits of logical \"1\" or \"0\". The conventional architecture of the most typical 16T NOR-based electronic T-CAM cell is illustrated in Figure 1c [10], comprising two D-type flip-flops operating as storage cells and marked with a blue highlight. The first memory cell is responsible for storing the actual data-bit [0 or 1] and the second one stores the ternary state information for the \"Care\" or \"Don't Care\" state of the logical \"X\" value. Each memory cell is typically built on the configuration of two cross-coupled inverters, similar to 6T RAM cells [11], while another two pairs of transistors, (M1, M3) and (M2, M4), form short-circuits to the ground.