# A Survey of of Side-Channel Attacks and Mitigation for Processor Interconnects
## 4 Interconnect Contention Side Channel
### Ring Bus Contention  
The ring interconnect, commonly referred to as a ring bus, is a high-bandwidth on-chip interconnect that first appeared in Intel's Nehalem-EX microarchitecture [57]. As illustrated in Figure 3, it facilitates internal communication among the cores, LLC, system agent (or Uncore), and GPU within the processor. When a core executes a load operation and experiences a cache miss in its private cache (L1-L2), the load must traverse the ring interconnect to reach the LLC and/or memory controller. Different CPU consumers/producers communicating via the ring interconnect are known as ring agents [63]. Each ring agent participates in ring communication through a ring stop (sometimes referred to as interface block, node router [64; 65], or ring station [66]). Each core shares its ring stop with an LLC slice. To minimize latency, traffic on the ring interconnect always follows the shortest path, meaning the ring stop can inject/receive traffic in both clockwise or counterclockwise directions and always selects the direction of the shortest path to the destination (clockwise or counterclockwise in the figure). The communication protocol on the ring interconnect utilizes four physical rings: request, snoop, acknowledge, and data rings.  
The contention-based interconnect side-channel attack relies on a crucial observation: the ring stations always prioritize existing traffic on the ring bus over new traffic entering from their agents. When new ring traffic is delayed due to existing ring traffic, contention occurs in the ring. Hence, When one agent bombards an LLC slice with requests, other agents loading from the same slice observe a delay.  
**Covert Channel.** In the scenario of cross-core covert channels, the sender and receiver share a segment of the ring interconnect. When sending a bit \"1\", the sender sends loads to cause contention on the ring interconnect, while no action is taken when sending \"0\". The receiver decodes the signal by timing the loads passing through the ring interconnect segment, which are prone to contention due to the sender's loads. Therefore, when the sender sends \"1\", the receiver's load experiences a delay. To differentiate between \"0\" and \"1\", the receiver can simply use the average load delay: smaller load delays are assigned to \"0\", while larger load delays are assigned to \"1\". Synchronization between  
Figure 3: Ring bus architecture.  
both parties can be achieved using a shared timestamp counter or extended to use other clock-independent techniques.  
**Side Channel.** For side channels, the attacker (receiver) sends loads through a fixed segment of the ring interconnect and measures their delays. The attacker collects the load delay of each measurement as a sample and refers to the collection of many samples (i.e., one run of the attacker/receiver) as a trace. If, during the attack, the victim (sender) performs a memory access operation that meets certain conditions, the attacker will measure a longer load delay. Typically, slices accessed by unsuspecting victims are evenly distributed across the entire LLC. Many implementations of encryption algorithms select different functions based on the key bits, a common pattern exploited in many existing side-channel attacks. Different functions may exhibit different memory access patterns, resulting in varying degrees of load on the ring bus, which increases the delay of the attacker's load, allowing the attacker to infer the key.