# Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM
## 4 Assessment of the Adaptive Fault Tolerance Mechanism
### Analysis of System Overhead
As a reconfigurable FPGA, we have used a Zynq-7 ZC702 (Xilinx, San Jose, CA, USA) evaluation board, which incorporates a Xilinx XC7Z020-1 CLG484C SoC [61]. This FPGA includes an integrated ARM(r) Cortex(r)-A9 MPCore(tm), which is able to perform the logic reprogramming. As a non-reconfigurable FPGA, the same device can be used, just ignoring the ARM microprocessor. Please note that we have used this FPGA only to test the performance of the design proposed. Finding the best device for a particular application of the AFT mechanism is out of the scope of this paper. Tables 1 and 2 show, respectively, the comparison of the syntheses of the three models in the two devices (i.e., the XC7Z020 FPGA configured as non-reconfigurable in Table 1 and as reconfigurable in Table 2). Obviously, even though only synthetizing the dynamic version of Plasma_ADAPTIVE core (see Section 3.1) makes sense, we have synthesized all the designs in the reconfigurable FPGA for comparison purposes only. In tables, we distinguish the data synthesis of the full model and of the memory controller and RAM components. From the synthesis report, we can obtain the hardware resources required by the whole system as by selected components. However, the maximum speed is reached, and the power consumption is only available for the full system. At a glance, we can observe in tables that the operation of the ARM processor in the reconfigurable FPGA introduces an important increment in the power consumption (over 1.5 watts). In addition, we can note the increment in the hardware required to implement the RAM from the original Plasma core to the other fault-tolerant cores (see \"RAM\" column in tables). Regarding the cores, we can note that the overhead introduced by the ECC encoding and decoding circuits in the Plasma_SEDED core is not very important in terms of hardware or power consumption. On the contrary, the maximum operating frequency gets reduced (although only in the non-reconfigurable FPGA). Note that the \"Mem_ctrl\" column shows the hardware required by the memory controller component, including all the ECC-associated circuitry, the write-back management and the \"Error manager\" component (in Plasma_ADAPTIVE cores). Remark that, in fact, the fault-tolerant and all adaptive versions reduce the power consumption in both FPGAs. On the other hand, the static version of Plasma_ADAPTIVE core introduces a very high increment in the hardware required (about 5 \(\times\) LUTs and 1.5 \(\times\) FFs compared to Plasma_SEDED core), as well as a strong reduction of the maximum operating frequency. As explained in Section 3.1, in this version, all the encoding and decoding circuits are physically implemented in the memory controller (see Figure 5). Nevertheless, the increment of the power consumption is very subtle (only one milliwatt). This trend occurs in the two FPGAs. \begin{table}
\begin{tabular}{c c c c c c c c c c c c} \hline \hline  & \multicolumn{6}{c}{**Full Model**} & \multicolumn{6}{c}{**Mem\_Ctrl**} & \multicolumn{2}{c}{**RAM**} \\ \cline{2-11}  & \multicolumn{2}{c}{**Hardware**} & \multicolumn{2}{c}{**Max. Speed**} & \multicolumn{2}{c}{**Power Consumption (W)**} & \multicolumn{2}{c}{**Hardware**} & \multicolumn{2}{c}{**Hardware**} \\ \cline{2-11}  & **LUTs** & **FFs** & \(\mathbf{f_{max}}\) (MHz) & \(\mathbf{T_{min}}\) (ns)** & **Dynamic** & **Static** & **Total** & **LUTs** & **FFs** & **LUTs** & **FFs** \\ \hline Plasma & 1834 & 448 & 100 & 10 & 0.009 & 0106 & 0.115 & 189 & 103 & 281 & 0 \\ Plasma\_SCED & 2040 & 380 & 83.33 & 12 & 0.005 & 0103 & 0.108 & 344 & 35 & 341 & 0 \\ Plasma\_ADAPTIVE (static) & 10,652 & 586 & 58.82 & 17 & 0.006 & 0103 & 0.109 & 8985 & 241 & 341 & 0 \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Synthesis of Plasma cores in the non-reconfigurable FPGA.