# An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields
## 2 Lopez-Dahab Projective Form of ECC over \(GF(2^{m})\)
The total clock cycles for our accelerator can be calculated across different field lengths of 163, 233, 283, 409, and 571 using Equation (3). The corresponding values for clock cycles are 2653, 3775, 4575, 6773, and 9187. It is essential to mention that these clock cycles are for our PM-core, excluding the loading parameters' cost. \[Total\ Clock\ Cycles\ (TCC)=5+(14\times m)+2\times(inversion)+24 \tag{3}\]

## 4 Achieved Results and Performance Comparison

The achieved results are presented in Section 4.1, while a comprehensive performance comparison is given in Section 4.2. ### Achieved Results

We have implemented our accelerator architecture over binary fields. The employed key lengths are 163, 233, 283, 409 and 571. The Verilog is chosen for functional modeling. As previously mentioned, the input parameters, namely \(x_{p}\) and \(y_{p}\), along with the value of constant \(b\), have been taken from the NIST [10]. The achieved implementation results after the post-place-and-route level on the Xilinx Virtex-7 FPGA platform are summarized in Table 1. The table provides implementation details across each key length in the following manner: the initial column represents the implemented length of the key. The next three columns (two, three, and four) display the utilized area in terms of slices, look-up tables (LUTs), and flip-flops (FFs). Similarly, the next three columns (five, six, seven) present the implementation results that are related to timing. These are presented in terms of total clock cycles (TCC), operating frequency (Freq) in MHz, and computation time (latency) in microseconds (\(\upmu\)s). Lastly, column eight indicates the implemented PM algorithm within our accelerator. The area results are extracted from the synthesis tool. The total clock cycles are computed from Equation (3). The operating frequency is the ratio of one over provided time period to the Vivado tool for synthesis. Latency is the computation time and can be calculated using Equation (4). \[Q=k.P=k.(P+P\cdots+P) \tag{2}\]0

If we consider only the hardware resources for comparison, the utilized FPGA slices over the binary fields of \(GF(2^{163})\), \(GF(2^{233})\), \(GF(2^{283})\), \(GF(2^{409})\), and \(GF(2^{571})\) are 1479, 1998, 2573, 3271, and 4469. Our accelerator utilizes 3862, 6079, 6341, 9583, and 11871 LUTs for similar binary fields. This increase in slices and LUTs is due to the increase in the implemented key lengths (i.e., 163, 233, 283, 409, and 571). If we consider the increase in the key lengths, i.e., from 163 to 233 (ratio of 163 with 233), this increase results in a value of 1.42, which means that the 233-bit key length is 1.42 times higher than the 163-bit key length. Using the same method, 283-bit key length is 0.82 times higher than 233; 409-bit key length is 0.69 times higher than 283; and the 571-bit key length is 0.71 times higher than 409-bit key length. Similarly, for all key lengths, if we consider the increase in the FPGA slices, i.e., from 163 to 233, this increase results in a value of 0.74 (ratio of 1479 with 1998), which means that the slices for 233-bit key length are 0.74 times higher than the utilized slices for 163-bit key length. With this strategy, the slices for 283-bit key length are 0.77 times higher than the slices of 233-bit key length; the slices for 409-bit key length are 0.78 times higher \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline \multirow{2}{*}{\(m\)} & \multicolumn{3}{c}{**Area Utilization**} & \multicolumn{3}{c}{**Results for Time**} & \multirow{2}{*}{**PM Algorithm**} \\ \cline{2-2} \cline{4-7}  & **Slices** & **LUTs** & **FFs** & **TCC** & **Freq (MHz)** & **Latency (\(\upmu\)s)** & \\ \hline
163 & 1479 & 3862 & 1749 & 2653 & 371 & 7.15 & \\
233 & 1998 & 6079 & 2431 & 3775 & 356 & 10.60 & Montgomery \\
283 & 2573 & 6341 & 2925 & 4575 & 345 & 13.26 & (Algorithm 1) \\
409 & 3271 & 9583 & 3981 & 6773 & 323 & 20.96 & \\
571 & 4469 & 11871 & 5692 & 9187 & 302 & 30.42 & \\ \hline \hline \end{tabular}
\end{table}