# Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs
## 5 Evaluation of DNN Accelerators under Delta-Based MINs
At the pooling layer level, the operations performed are either average or max types of operations among the input feature map lying data. The amount of operations depends on the input feature map size, the layer scale and stride parameters. For the fully connected layer level, the output neurons bear inputs corresponding to the size of the input feature map. In this context, we consider establishing a 1 : \(n\) mapping between PEs and neurons, denoting that a PE can process multiple neurons. Thus, every PE is required to fetch a number of weights, from the main memory that corresponds to the input feature map size, as shown in Figure 10.  
Designing an efficiently reliable and resilient interconnection for NoC architecture remains an important challenge, especially for applications with real-time constraints, high throughput, and power efficiency needs. To resolve these issues, various specific NoC technologies, particularly Photonic NoC, Hybrid, and Wireless, have been proposed, each displaying proper trade-offs in terms of throughput, communication latency, and programming complexity. A survey of NoC technologies developed to meet industrial requirements is presented in refs. [27; 57]. With respect to our study context, our focus of interest lies mainly in investigating the area of Wireless NoC [58; 59; 60] (WiNoCs), initially designed to provide promising solutions to the challenges faced by traditional NoC architectures. In general, Wi-NoCs involve an enhanced model of radio-hub switches with a wireless interface, allowing for radio transmission to be maintained within the chip. While Wi-NoCs have been explored for common direct topologies, their implementation in Delta MIN-based topologies still remains an unexplored domain, to the best of our knowledge. A key advantage of Wi-NoCs is their low power consumption, which can be further improved by effectively managing power-off wireless routers when they are in an idle state, as highlighted in ref. [61]. Indeed, WiNoCs offer high bandwidth availability and reliability, and the reliability of wireless links can be improved by implementing an optimum-radiation phased array antenna, as demonstrated in ref. [62]. While hybrid wired/wireless links are more common in WiNoCs, a distinctive pure wireless link topology has been introduced in ref. [63]. The special feature distinguishing these solutions lies mainly in the graph of links substitution and/or the distinct architecture of the mapping of wireless nodes. The Experimental platform is a reconfigurable NoC-based machine learning, used to as sess different configurations of communication architectures in terms of performance and energy. A refined version of a high throughput accelerator for pervasive convolutional neural networks (CNNs) and Deep Neural Networks (DNNs), baptized DianNao [49], has been mapped into the computing module of Noxim [50] simulator. We focused on this accelerator, due to the wide range set of applications. Also, considering the implementation of large-scale layers composed of millions of synapses, the flexibility of interactions with memory, and by exploiting locality at the registers placed close to processor elements, our study broadly evaluates WiNoC-based DNN accelerators by investigating the design space that encompasses various reconfigurable parameters. The analysis is organized under the form of a function of latency and energy consumption in communication, computation and memory access (local memory and main memory access). Figure 11 displays the average latency spent in every layer relevant to the neural network AlexNet. Regarding the memory interfaces' (MIs) locations, they are placed at the four NoC corner levels for the traditional Mesh architectures. As for the Delta MIN topology, the four MIs are uniformly spread into the MINs cores. It is worth recalling that the latency is split into three essential elements, namely, communication, computation, and memory.