## 3 DCO Design  
Figure 4 shows a simplified schematic with three capacitor banks, i.e., the MSB, LSB, and fine bank. All capacitor banks were designed with unit-weighted instead of binary-weighted structures to ensure linearity in the frequency step. Even though the area of the unit-weighted capacitor bank is slightly larger than that of the binary capacitor bank, it presents many merits in terms of linearity and flexibility in design [10]. For example, to change the capacitor required for linear oscillation frequency control, all unit capacitor sizes in the capacitor bank were changed, maintaining constant the ratios of capacitor sizes, such as unit \(\times 1\), \(\times 2\), \(\times 4\), and \(\times 8\)[10]. However, in the unit-weighted structure, the optimum capacitor unit value considering the parasitic components generated in the layout can be individually applied to optimize performance. For linearity and reliability, the unit capacitor contains inverter logic to bias the source and gate of the switch. Assuming a voltage swing (V\({}_{\text{PP}}\)) of 0.8 at the output node and a supply voltage for the inverter logic of 1.2 V, when the switch was turned off, the turn-off-resistance of the switch was a few mega ohms, and the V\({}_{\text{gs}}\) of the switch produced a voltage swing from \(-1.6\) to \(-0.8\) V based on the 1.2 V supply. Ensuring the V\({}_{\text{gs}}\) reliability of a low-voltage threshold (LVT) switch with low turn-on resistance is difficult, therefore, a thick-oxide metal-oxide semiconductor FET (MOSFET) switch was used for the large signal swing of the DCO. However, the thick-oxide MOSFET switch increases the turn-on resistance and layout area, which complicates the design of the capacitor bank. To solve the reliability problem [8], if it is possible to supply a voltage lower than 1.2 V on the source voltage, an LVT switch with a low turn-on-resistance can be used. For this purpose, the supply voltage of the source inverter was 0.8 V, the same as the voltage of the DCO, and a different supply voltage from the inverter voltage for the gate was applied, as shown in Figure 4. This helped to improve the linearity and reliability of the DCO through a simple configuration power separation scheme. To reduce the mismatch between unit capacitors, the unit capacitor and control circuit should be  
Figure 3: Layout and equivalent circuit using a metal Al layer.  
arranged separately in the layout. This separation makes the arrangement conditions of all unit capacitors the same.  
Figure 5 depicts a useful method for reducing the mismatches between unit capacitors. In this design, the electrical control part and the unit capacitor cells were separated. The circles in Figure 5 represent a unit capacitor cell, which consisted of a switch, two capacitors, and two DC-blocking resistors. All these unit cells were located inside the capacitor dummy guard. The dummy was composed of unit cells that were the same size as those used for oscillation frequency tuning. This capacitor dummy layout was a layout technique for making all the coupling effects generated by the metal layer the same. In addition, the control logic blocks were located as far as possible outside the dummy for separation. When the electrically isolating layout was adopted, the randomness of the oscillation frequency was reduced, as shown in earlier studies of fabricated DCOs [8]. This layout method was applied to all capacitor banks, such as the MSB, LSB, and fine frequency tuning banks.  
Figure 4: Structure and operation principle of the switch and control circuit for tuning the capacitor in a capacitor bank.  
Figure 5: Layout for high isolation between the unit capacitor cell and the control circuit.