# A Reconfigurable Framework for Hybrid Quantum-Classical Computing
###### Abstract
Reconfigurable computing and FPGAs can play a critical role in hybrid quantum-classical computing [12] by providing the speed and flexibility needed for tasks like real-time feedback, high-bandwidth post-processing, and implementing optimization kernels, while QPUs handle compute-intensive quantum tasks. For example, variational quantum algorithms (VQAs) often employ hybrid quantum and classical resources. In VQAs, output samples from a quantum circuit are used in a classical feedback loop that optimizes the parameters of the quantum circuit such that some loss function is minimized. Here, the quantum circuit behaves as the model that learns patterns from the data variationally and produces predictions, while classical techniques such as stochastic gradient descent or Bayesian optimization are used for optimization [13]. In this work, we propose a framework that combines reconfigurable processing pipelines with quantum computation for accelerating hybrid quantum-classical (HQC) computing. Keeping in mind the challenges in HQC computing, we propose an FPGA-based solution that offers a cost-effective pathway to address the aforementioned limitations through hardware-level parallelization, customizable interfaces, and data flow architectures. By leveraging low-latency and power-efficient FPGA architectures, this research aims to develop an efficient framework that can significantly reduce the computational burden on traditional processors while enabling seamless integration with quantum processing units (QPUs). We focus on developing specialized FPGA kernels that can streamline iterative tasks in HQC computing, such as parameter optimization for variational quantum classifier circuits [14]. The FPGA kernels communicate with the QPUs through a host that synergizes the workload distribution in a unified software environment. The proposed framework also contains hardware kernels for quantum circuit simulation for cases where quantum processing hardware is unavailable. We use high-level synthesis [15] to accelerate FPGA hardware kernel development and integrate high-level software frameworks such as PYNQ [16] and Qiskit [17] for managing quantum and reconfigurable resources. We demonstrate that the proposed reconfigurable framework can be a cost-effective and user-friendly platform for deploying and testing HQC algorithms by performing quantitative comparison with a server-grade CPU. In this work, we emphasize integration and acceleration at the system level of quantum-classical systems, rather than innovation at the quantum algorithm level. Our contribution lies in designing a general-purpose, FPGA-accelerated framework capable of integrating with QPUs at a high-level of abstraction, to speed up the classical components of hybrid workflows. The use of well-known variational quantum classification serves as a proof-of-concept to validate the performance and feasibility of the proposed framework. The remainder of the manuscript is organized as follows. Section 2 contains background concepts and discussions of work related to the intersection of HQC computing and reconfigurable computing. Section 3 details the framework proposed and used in this work. The experimental evaluations, results, and analysis are contained in Section 4. Section 5 provides the conclusion and discussion of future work.