## 2 Results  
### Small-Signal Investigation for LNA Design  
In this section, key SS characteristics including power gain, noise figure, reverse isolation, and stability of the proposed configuration, which are critical for the design of LNA, are investigated in comparison with other typical configurations. These characteristics are evaluated through S-parameters of the configurations. The investigations are performed by employing an S-parameters analysis in a Keysight advanced design system (ADS) simulator [33]. The GaN HEMT SS models are provided by WIN Semiconductor Corp, Taoyuan City, Taiwan [34]. The schematics of the configurations are created inside the simulator. The simulation setup which is implemented in the Keysight ADS for S-parameters simulation is shown in Figure 2.  
Although the figure shows the simulation setup for the proposed 3-stack GaN HEMT configuration, the simulation setups for the other configurations are implemented in a similar way by placing a specific configuration to the schematic and connecting both its input and output to a same 50 \(\Omega\) termination. The high frequency small-signal equivalent circuit of the proposed 3-stack configuration shown in Figure 1e is illustrated in Figure 3 below. The equivalent circuit is realized by connecting the first SS equivalent circuit of the CS transistor and the second and third equivalent circuit of the CG transistors. It is worth noting that the gate-to-source conductance has been ignored in the figure because of its  
Figure 1: Circuit configurations: (**a**) single-stage; (**b**) conventional cascode; (**c**) independently biased cascode; (**d**) conventional 3-stack; (**e**) independently biased 3-stack. Figure 2: Simulation setup for S-parameters simulation in Keysight advanced design system (ADS). negligible value. Here, \(v_{1}\), \(v_{2}\), \(v_{3}\) and \(i_{d1}\), \(i_{d2}\), \(i_{d3}\) are gate-to-source voltages and drain currents of the first, second, and third transistor, respectively; \(g_{d1}\), \(g_{d2}\), \(g_{d3}\) and \(g_{m1}\), \(g_{m2}\), \(g_{m3}\) are drain conductance and transconductance of the first, second, and third transistor, respectively; \(C_{gs1}\), \(C_{gs2}\), \(g_{gs3}\) and \(C_{gd1}\), \(C_{gd2}\), \(g_{gd3}\) are parasitic gate-to-source and drain-to-gate capacitance of the first, second, and third transistor, respectively. This equivalent circuit will be used to derive critical SS parameters of the proposed configuration including reserve isolation, power gain, and stability. This equivalent circuit will be used to derive critical SS parameters of the proposed configuration including reserve isolation, power gain, and stability. Firstly, regarding Figure 3, transmission (ABCD) matrix of the CS and CG transistors are derived as follows:  
ABCD matrix of the CS transistor:  
\[A_{\text{CS}}\approx-\frac{g_{d}+j\omega\text{C}_{\text{dg}}}{g_{\text{m}}} \tag{1}\]  
\[B_{\text{CS}}\approx-\frac{1}{g_{\text{m}}} \tag{2}\]  
\[C_{\text{CS}}\approx-\frac{j\omega\text{C}_{\text{dg}}\left(g_{\text{d}}+j \omega\text{C}_{\text{gs}}\right)+g_{\text{d}}\left(j\omega\text{C}_{\text{gs }}\right)}{g_{\text{m}}} \tag{3}\]  
\[D_{\text{CS}}\approx-\frac{j\omega\text{C}_{\text{gs}}}{g_{\text{m}}} \tag{4}\]  
ABCD matrix of the CG transistor:  
\[A_{\text{CG}}\approx\frac{g_{d}+j\omega\text{C}_{\text{dg}}}{g_{\text{m}}} \tag{5}\]  
\[B_{\text{CG}}\approx\frac{1}{g_{\text{m}}} \tag{6}\]  
\[C_{\text{CG}}\approx\frac{j\omega\text{C}_{\text{dg}}\left(g_{\text{m}}+j \omega\text{C}_{\text{gs}}\right)+g_{\text{d}}\left(j\omega\text{C}_{\text{gs }}\right)}{g_{\text{m}}} \tag{7}\]  
Figure 1:0  
ABCD matrix of the configuration depicted in Figure 3 can be derived as below:  
\[ \begin{pmatrix}A&B\\ C&D\end{pmatrix} = \begin{pmatrix}A_{\text{CS1}}&B_{\text{CS1}}\\ C_{\text{CS1}}&D_{\text{CS1}}\end{pmatrix}\begin{pmatrix}A_{\text{CG2}}&B_{ \text{CG2}}\\ C_{\text{CG2}}&D_{\text{CG2}}\end{pmatrix}\begin{pmatrix}A_{\text{CG3}}&B_{ \text{CG3}}\\ C_{\text{CG3}}&D_{\text{CG3}}\end{pmatrix}