# Automatic Initialization Methods for Photonic Components on a Silicon-Based Optical Switch
## 1 Introduction
The IRIS architecture drives 48 optical channels, 200 GHz-spaced in the C-band, in 4 different directions, through 12 add/drop ports [11]. A fully packaged prototype has been completed and tested at 25 Gbps into the operational environment, with 12 wavelengths, 4 directions, and 8 add/drop ports [15]. The system has been optically accessed through the V-groove assembled fiber array, vertically coupled to the input/output single polarization grating couplers. The electronic control of the switch fabrics, combined with an intelligent management plane implemented on a microcontroller, enabled a complete system reconfiguration in microseconds [14]. Compared to conventional ROADMs, which use free space optics 1 xN wavelength selective switches for the optical line switching, the IRIS switch has the competitive advantage of a more than one order of magnitude lower cost (a few hundred euros) and an overall 60 times smaller device volume (few cm\({}^{3}\)). This device can also play a key role into data centers, due to its capability to manage a large throughput in a single chip with a low power consumption. In fact, today's major challenges in data centers are related to the topology and scalability issues [16]. On the one hand, the typical rigid architecture, based on cascaded switches of limited bandwidth, requires an arbitration stage, which, in turn, contributes to the switching latency. On the other hand, the distribution of huge amounts of power and the complexity of cooling, limit the scalability of the infrastructures. Exploiting the  
Figure 1: Integrated reconfigurable silicon photonics based optical switch (IRIS) architecture where the photonic-electronic 3D stack is shown in the vertical direction. In the dark green layer, a portion of the optical layout is sketched with double micro-ring resonators (MRR) as switching elements, interleavers, and arrayed waveguide gratings (AWGs) as mux/de-mux elements. Both interleavers and switching nodes can be electrically trimmed so that the add/drop function is enabled on the chip. In this specific representation, we show the device acting in the drop mode, where the pink wavelength is taken off from the line port and directed toward the second local port. On the top right, we have outlined the fact that the automatic optimizer for all the components of the IRIS chip has been implemented on an external microcontroller. embedded photonics approach, IRIS acted on both sides. The flat all-to-all (NxN) topology supports the contention-free interconnection at full throughput. The reconfigurable architecture adapts to the workload with ease, for a higher efficiency. This last point is the focus of this paper, which details the optimization methods used to initialize/reconfigure the whole IRIS chip, and the performance figures, before and after the optimization. This paper is structured as follows. In Section 2, we detailed the architecture of the optical switch used for our tests. Section 3 describes the optimization method exploited to automatically initialize/reconfigure all optical elements on the optical switch. In particular, Section 3.1 describes the core optimization engine, Section 3.2 presents the convergence and degeneration criteria, and Section 3.3 deals with probabilistic restarts set to avoid faults during the initialization. In Section 4, we benchmark the optimization method, both on a ring resonator and on an interleaver. Section 5 reports the overall performances achieved during the switch operation. Finally, Section 6 gives the conclusions.