# High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA
## 4 Experiments and Discussion  
The Quartus Prime 21.1 software tool was used for implementation in FPGA Cyclone 10 LP of the multipliers c and d. The multiplication algorithms c and d were implemented using the traditional approach in the form of the datapath and the FSM, as well as using the ASMD-FSMD technique. The designs were investigated with input word widths of 4, 8, 16, 32, 64, and 128 bits. The experimental results are shown in Table 1, where mult_c_N and mult_d_N are projects that implement multiplication algorithms c and d, respectively; \(N\) is the width of the input words A and B in bits; \(L_{T}\) and \(L_{A}\) are the numbers of used FPGA logic elements (the implementation cost) in case of the traditional approach and when using the ASMD-FSMD technique, respectively; \(t_{T}\) and \(t_{A}\) are the time of multiplication operation in nanoseconds in case of the traditional approach and when using the ASMD-FSMD technique with operating frequency 100 MHz; \(L_{T}/L_{A}\) and \(t_{T}/t_{A}\) are relations of corresponding parameters. Table 1 shows that using the ASMD-FSMD technique allows, on average, to increase the performance of the algorithm c by a factor of 1.96 (1.99, for example, mult_c_4) and the algorithm d by a factor of 2.45 (2.96, for example, mult_c_16). In addition, the ASMD-FSMD technique allows, on average, for algorithm d to reduce the implementation cost by a factor of 1.23 (for example, mult_c_16 by a factor of 1.31) [16]. A comparison of area (\(L_{T}/L_{A}\)) and time (\(t_{T}/t_{A}\)) ratios can also be seen in Figure 11. \begin{table}
\begin{tabular}{l c c c c c c} \hline
**Example** & \(L_{T}\) & \(L_{A}\) & \(L_{T}/L_{A}\) & \(t_{T}\) & \(t_{A}\) & \(t_{T}/t_{A}\) \\ \hline mult\_c\_4 & 35 & 35 & 1.00 & 40.25 & 20.22 & 1.99 \\ mult\_c\_8 & 60 & 65 & 0.92 & 93.11 & 47.82 & 1.95 \\ mult\_c\_16 & 112 & 138 & 0.81 & 183.55 & 97.72 & 1.88 \\ mult\_c\_32 & 208 & 270 & 0.77 & 452.46 & 238.75 & 1.98 \\ mult\_c\_64 & 405 & 540 & 0.75 & 1267.69 & 639.39 & 1.98 \\ mult\_c\_128 & 793 & 1006 & 0.79 & 8216.11 & 4200.59 & 1.96 \\ mult\_d\_4 & 32 & 29 & 1.10 & 41.77 & 20.67 & 2.02 \\ mult\_d\_8 & 58 & 48 & 1.21 & 82.48 & 36.41 & 2.27 \\ mult\_d\_16 & 98 & 75 & 1.31 & 159.26 & 53.86 & 2.96 \\ mult\_d\_32 & 176 & 141 & 1.25 & 410.87 & 158.33 & 2.59 \\ mult\_d\_64 & 338 & 271 & 1.25 & 940.51 & 355.62 & 2.64 \\ mult\_d\_128 & 663 & 528 & 1.26 & 4851.80 & 2178.69 & 2.23 \\ \hline \end{tabular}
\end{table} 
Table 1: The experimental results of the implementation of multipliers c and d by the Quartus tool. Figure 10: The simulation results of the multiplier (algorithm d) are built using the traditional approach. Similar studies were also performed using the software tool Vivado 2021.1 in the implementation of multipliers in FPGAs of the family Kintex UltraScale. The experimental results are given in Table 2.  
When implementing multipliers using the software tool Vivado, the ASMD-FSMD technique allows to increase the performance by a factor of 2.04 (2.38 for the example mult_d_4) and decrease the implementation cost by a factor of 1.39 (1.98 for the example mult_d_128). A comparison of area (\(L_{T}\)/\(L_{A}\)) and time (\(t_{T}\)/\(t_{A}\)) ratios can also be seen in Figure 12.  
The results provided in Tables 1 and 2 and Figures 11 and 12 show that in most examples, the area and the time are decreasing significantly. The results obtained with the Vivado tool were better than the results from the Quartus tools according to area ratio (geometric mean equal to 1.35 for Vivado and 1.01 for Quartus), but according to time ratio, the Quartus tool was better (geometric mean equal to 2.18 for Quartus and 2.03 for Vivado).