# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 4 Saving Power by Clock-Gating and FSM Decomposition  
In Mealy FSMs, outputs \(y_{n}\in Y\) are unstable [39]. Because outputs \(y_{n}\in Y\) depend on inputs \(x_{l}\in X\), then changing inputs during the clock cycle may cause short-term changes in outputs (glitches). This may cause a malfunction of a digital system. To stabilize the outputs, it is sufficient to stabilize the FSM inputs. This can be achieved by entering a special register \(RGX\) as shown in Figure 6. This figure also depicts the interaction of an FSM with other digital system blocks. Figure 5: Replacing four LUTs by a single EMB. To generate correct output values, an FSM should analyze the outputs of other blocks. They form the set \(X=\{x_{1},\ldots,x_{L}\}\). When values of the inputs are correct, the pulse _Clock1_ is generated. The values of FSM inputs are loaded into _RGX_. Now, they correspond to registered inputs from a set \(X_{R}\). The elements of \(X_{R}\) are stable during the cycle of _Clock_. Thus, an FSM generates the following SBF:  
\[Y=Y(T,\ X_{R}). \tag{11}\]  
Now, the outputs are stable after the completion of various transients in the FSM circuit. Let us point out that there is no need of RGX if the model of a Moore FSM is used. This is connected with the nature of outputs (3). From (3), there is no direct dependence between the inputs and outputs of a Moore FSM. The outputs depend only on states. Thus, the outputs are registered. The state register outputs (state variables) are stable during each cycle of operation. Therefore, if some input is changed between two pulses of synchronization, the outputs are unchangeable. Thus, in reality, there are two registers in the circuits of Mealy FSMs. The register \(RG\) includes \(R\) flip-flops, the register \(RGX\) consists of \(L\) flip-flops. These registers are synchronized by different pulses (Figure 7). The pulses _Clock1_ and _Clock_ are generated by the special block of synchronization. This block contains a quartz generator, delay circuit, and a single vibrator generating the pulse _Start_. It is known that clock trees usually consumes up to 50% of the dynamic power [71]. The internal switching power of flip-flops is responsible for 45-50% of the clock tree's power consumption [72]. As a result, it is very important to deliver synchronization pulses only to flip-flops whose states will be changed in a particular cycle of FSM operation. This can be achieved by using the clock-gating approach. CG assumes using an additional clock logic (CL) block [3]. This logic is based on the precomputation of inputs being disabled [73; 74]. In this case, some precomputation logic is added to the CL. It analyzes inputs and state codes to disable the loading of all or a subset of flip-flops of RGX (Figure 8). Figure 6: Interaction of an FSM with other blocks of a digital system. Figure 7: Registers of a Mealy FSM. The CL generates loading control signals as functions of \(X_{C}\subseteq X\) and state variables. These signals either allow or prevent the passage of _Clock1_ to inputs of synchronization of flip-flops creating RGX. It is very important to choose the subset of \(X\) which enters the CL. The smaller the difference \(|X|-|X_{C}|\), the higher the probability that the CL is active. It leads to reducing the power consumption of both RGX and FSM logic block. Of course, this is connected with a CL-based overhead: this block requires some chip area, consumes additional power, and increases the FSM cycle duration. Thus, it is very important to find a set \(X_{C}\subseteq X\) that reduces the negative influence of the CL and provides the minimum power consumption of an FSM circuit. As noted in the monograph [75], 20% of program operators are responsible for 80% of the program execution time. The same may be true for FSM states. If a state \(a_{m}\in A\) is a waiting state, then an FSM may remain in that state for a long time. If a state register consists of \(D\) flip-flops, then the code \(K(a_{m})\) should be reloaded during a lot of clock cycles.