# Hardware Update through Digital TV Signals
## 5 The Proposed Hardware Reconfiguration Scheme Based on the DTV Signals
### Discussion about HARD  
Figure 9 summarizes HARD, as explained in Sections 5.1-5.4. As shown in Figure 9, HARD provides the transmission of pre-synthesized hardware cores through MPEG-2 TSs  
Figure 8: Steps involved in obtaining broadcast hardware core streams include verification of each private section, downloading, and content reassembling. in such a way that the FPGA devices integrated into the commercial receivers are addressed. Aside from that, the same content transmission strategy already used for general data and SI (e.g., tables and sections) in digital television systems [56; 57] is employed. The presented reconfiguration system is based on JTAG communication, the SVF files retrieved from digital TV signals, a newly created SI table (UIT), and its associated descriptors (see Section 5.2). The SVF format is a standard used by almost all FPGA manufacturers and is compliant with the JTAG communication protocol. Additionally, HARD's SI extension carries all necessary FPGA devices (e.g., manufacturer, part number, and family identification) under update, which allows complete identification of a given unit. Consequently, it is not restricted to a specific manufacturer or FPGA model, and it is also flexible enough to be adapted to other scenarios. For instance, nearly any given format can be sent in private sections, as long as the related content is regular data flow. Regarding content reception, pre-synthesized cores will be accepted if there is a match between the transmitted information, which was filtered from UIT, and the locally available FPGA devices; otherwise, the receiving systems simply ignore the acquired content and wait for suitable data. It is worth noticing that HARD presents some overhead related to encapsulation in private sections (i.e., the private section header and SVF file format), including JTAG commands. The total overhead is given by  
\[\text{overhead}=(\text{N}\times 16\text{ bytes}+3\text{ Kbytes})\]  
where N is the total number of sections necessary to carry the hardware reconfiguration content, 16 bytes is the size of the private section headers (\(4096-4080=16\)), and 3 Kbytes is related to the SVF syntax and header file. HARD is based on an extension of SI standards [59; 60] without modifying current structures. It uses a new table (UIT) and associated descriptors inspired by AIT's architecture. Although that may seem intricate, its implementation is transparent and can be performed without formally modifying the related standards as a proprietary framework. Apart from that, the present approach addresses its complete update chain and provides a comprehensive and complete solution, which is still more feasible and more straightforward than isolated proprietary solutions or on-site maintenance. Another exciting research topic about this work is security. Although not its focus, given that the main goals were to prove feasibility and provide a complete and consistent framework which could be readily used and further extended, some ideas may be tackled. There is a trend toward adopting security-by-design approaches, where built-in security tools are already available within frameworks; that is, systems are designed from the ground up to be secure [61]. Another initiative is proof-carrying hardware (PCH), which may mitigate malicious code's addition to IP modules by providing functional specifications and security properties [62; 63]. An automatic proof checker validates the modules  
Figure 9: All steps performed in HARD. through a device code and property proof. In summary, regarding HARD, security tools can be added later to host systems and other parts of the present framework (e.g., SI) to prevent hardware trojans or attacks on embedded systems. Finally, the present proposal deals with evolution and standard updates directly related to resource availability for future hardware modules. Complexity measurements depend on many issues, like the chosen platform and desired performance.