## 4 Modeling and Linearization Stage Setup
### Indirect Learning Approach for the Proposal Modeling Stage  
Behavioral modeling of the medium-high RF-PA was developed through the MPM expressed by Equation (1) and the W-MPM expressed by Equation (2). The coefficient extraction process was done using the LSE method. The development structure depicted in Figure 2b corresponds to the W-MPM proposed as the adaptive modeling taking into account the electrical factor of P1 dB; a similar structure is performed for the MPM. This \begin{table}
\begin{tabular}{c c} \hline \hline \multicolumn{1}{c}{**PA ZHL-42W+ @ 2.00 GHz**} \\ \hline
**Parameter** & **Values** \\ \hline Gain & 34 dB @ 2.00 GHz \\ Maximum power & 1.25 W \\ DC Supply & 15 V, 1 A \\ Bandwidth & 10–4200 MHz \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Features of the ZHL-42W+ PA at 32.24 dBm. Figure 2: Indirect learning approach (ILA) algorithm block diagram: **(a)** DSP-FPGA physical link for data conditioning, **(b)** adaptive weighted memory polynomial model (W-MPM) modeling stage, and **(c)** proposed ILA system control-based scheme. schematic is used to model the NXP 10 W at 2.34 GHz and ZHL-42W+ at 2000 MHz 32.24 dBm RF-PAs. The experiments conducted are specified below:  
1. An algorithm is performed for the offline training of the model (PA) and the predistorter (PD) block using the MPM and W-MPM approaches (running on MATLAB-PC with DSP blockset system environment) as defined in the overall block diagram in Figure 2.
2. At every iteration, the model searches for a weighting subset of parameters to contribute in the minimization the LSE and NMSE. 3. The developed chain through DSP Builder tool allows us to transfer the input signal compared with the amplification process by the DAC of the FPGA development board Cyclone V.
4. Both signals are sampled using 10-bit resolution related to the address bus capability; the magnitude signals are sampled for the maximum resolution of the HSMC card with 14 bits. We evaluate in this work both conversion curves that present a notable presence of highly nonlinear behavior. The achieved error was \(-\)32.72 dB for the MPM and \(-\)38.03 dB in NMSE for the W-MPM. Additionally, it was performed a modeling stage obtaining \(-\)44.34 dB NMSE based on the MPM and \(-\)44.90 dB NMSE for the device ZHL-42W+ at 2000 MHz, and it should be noted that the devices have a very high nonlinear behavior and strong data dispersion. Both models contain more than 65 K data samples for each conversion curve. The W-MPM showed a better accuracy compared with the traditional MPM, and it can even be updated if the conversion curves change with time due to its intrinsic adaptability based on the P1 dB detecting the compression region in the amplification stage. During hardware implementation, the total resources used for each model is compared. In this case, it obtained a slightly reduced amount of the available resources in the FPGA board Cyclone V during the W-MPM compared with the MPM, as it can be seen in Table 3. The W-MPM had a reduction in the adaptive logic module (ALM) using 340 compared with the required 378 used by the MPM. Table 4 summarize the Halstead metrics based on the two developed modeling stages W-MPM and MPM. The following estimation was calculated based on the developed code for the extraction coefficient method and the implementation chain. As it can be seen, the complex operations associated with the program length indicate the difficulty and effort during both processes, which is considerably bigger for the MPM compared with the W-MPM. However, both cases were resolved in a considerable reduced time for this type of implementation, where the model has a big data dispersion between short value intervals. A Halstead complexity analysis was done for both modeling stages where the W-MPM requires less offline training before implementation compared with the MPM in this study case, which required 11.85 s compared with 13.33 s.