## 1 Introduction  
Designing complex digital systems implemented in FPGA (Field Programmable Gate Array) devices is a challenging task. In most cases, there are a number of constraints to consider. As a rule, these constraints may relate to power consumption [1; 2; 3; 4; 5], the availability of logic resources [6; 7; 8] or speed of operation [9]. In many cases, it is also necessary to consider in the design process the specific characteristics of the environment in which the device will operate. It is often the case that an FPGA device is exposed to ionising radiation, which can lead to a number of errors in the operation of the implemented functionality. Application areas where increased levels of radiation can be expected include aerospace, medical diagnostics, nuclear power plants and most importantly, space applications. FPGA devices are often used in space missions [10; 11]. A deeper analysis of this environment therefore becomes necessary. As shown in [12], three main sources of radiation for space missions within the solar system can be distinguished, and these are galactic cosmic rays, solar radiation and radiation belts. Galactic cosmic rays are high-energyprotons from interstellar space that reach the solar system. Solar radiation is a stream of plasma emitted in all directions by the sun. This emission can be quite violent during Coronal Mass Ejections (CMEs). The last source of radiation is radiation belts. These are areas of increased radiation resulting from accumulations of energetic particles in the magnetic field of planets. From a technological point of view, an FPGA device is a semiconductor device. Radiation effects impact semiconductors in the following ways: Single-Event Effects (SEEs) and Dose effects. Dose effects correspond to a permanent change in selected parameters due to prolonged exposure to radiation. SEEs are associated with phenomena resulting from the impact of a single particle on a logic structure. Such an event is random and instantaneous. It can cause a change in the value of individual bits. The work [13] divides SEEs into Soft Error (no physical damage) and Hard Error (physical damage) phenomena. Soft Errors are upsets to the device operation. The most important types of Soft Errors are single-event transients (SETs), single-event upsets (SEUs) and single-event function interrupts (SEFIs). A SET event corresponds to the generation of additional pulses in combinational logic that can be propagated throughout the logic structure. SEU-type events correspond to a change in the state of a memory element due to the impact of a high-energy particle. SEFIs, on the other hand, correspond to a change in the normal functioning of the device (a change in the circuit functionality). Also in the case of Hard Errors, several types of events can be distinguished. These can be distinguished as a single-event latch-up (SEL), which is a circuit latch-up induced by radiation; single-event burnout (SEB), which is short-circuiting caused when a high-energy ion impacts a transistor source; and single-event gate rupture (SEGR), which involves physical damage to the gate oxide insulation in a silicon structure. The main contribution of this paper is a novel test circuit for mitigation circuits using TMR (triple modular redundancy) voters, based on the PRBS (Pseudo-Random Bit Sequence) register. The solution proposed in this paper will allow for more efficient testing of the mitigation capability of TMR circuits with a slight increase in the number of logic resources and power consumption required. This is of particular importance in space applications where such limitations are particularly relevant. Section 2 discusses the mitigation methods used in FPGA devices. Particular attention is paid here to triple redundancy. The design of different voter models is also discussed. Section 3 presents the concepts of a test environment for mitigation circuits using the PRBS. The focus is on the efficiency problem of implementing these circuits in FPGA devices.