# Method for Improving the Reliability of SRAM-Based PUF Using Convolution Operation
## 5 Conclusions  
This paper introduces a novel method consisting of a one-layer convolution scheme and a lightweight scheme for SRAM PUF that improves the reliability and hardware efficiency. The novel convolution generates standard and verification matrices during initialization. The verification matrix is obtained from the standard matrix and the PUF response is generated by comparing the verification matrix and unverified matrix values. Moreover, the lightweight scheme uses one-sixteenth of the one-layer convolution scheme hardware resources to generate the same length results; however, it has a larger redundancy coefficient, which reduces its discrimination and the inter-chip HD range. The results of the three chips obtained at 30,000 data sets demonstrate the proposed scheme's performance in terms of 256-bit response outputs. The reliability of all responses was shown to be able to reach 100%, with an inter-chip HD of around 50%. Moreover, the hardware cost per bit for the light-weight scheme was half that for traditional BCH, greatly reducing resource usage. The SRAMs used in the novel convolution method can work like normal SRAMs following SRAM PUF; therefore, the method can be combined with lightweight IoT devices under different conditions. In addition, the identity verification process requires only the initial value of the SRAM to be processed on the verifier's server and does not need MCU resources. The aging problem can, therefore, be avoided. Further development of the scheme represents a promising direction for future research. Conceptualization, R.C. and N.M.; methodology, R.C. ; software, R.C. ; validation, R.C. ; formal analysis, R.C. ; investigation, R.C. ; resources, R.C. ; data curation, R.C. ; writing \begin{table}
\begin{tabular}{c c c c c c} \hline \hline  & **This Work** & **JUNE [6]** & **TCAS I [16]** & **Access [17]** & **ISSCC [18]** & **ISSCC [19]** \\ \hline Technology (nm) & 90 & 130 & 65 & 65 & 65 & 28 \\ Topology & SRAM & EE SRAM & SRAM & SRAM & EE SRAM & SRAM \\ Stabilizing & Convolution & \multirow{2}{*}{\begin{tabular}{c} Vss bias dark-bit \\ technique \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} Capacitive digital \\ protection \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} Capacitive digital \\ protection \\ \end{tabular} } & \multirow{2}{*}{\
\begin{tabular}{c} Capacitive Automatic self-checking \\ and healing \\ \end{tabular} } & \multirow{2}{*}{
\begin{tabular}{c} SMV, BCH \\ 10.5\% \\ \end{tabular} } \\ Native unstable cells & 10\% & 2.14\% & 19.6\% & 42.1\% & 2.8\% & 10.5\% \\ Stabilized BER & 0\({}^{\text{a}}\) & 0\({}^{\text{b}}\) & \(<\)1.4\(\times\)10\({}^{-9}\) & 2.6\(\times\)10\({}^{-6}\) & \(<\)3.3 \(\times\)10\({}^{-8}\) & 8.9 \(\times\)10\({}^{-4}\) \\ Measure temp. (\({}^{\text{c}}\)C) & \(-\)40\(\cdot\)80\({}^{\text{c}}\) & \(-\)40\(-\)150 & \(-\)10\(-\)80 & \(-\)10\(-\)85 & \(-\)40\(-\)125 & \(-\)40\(-\)150 \\ \%17s in the qualified cells & 52.85\% & \(-\) & 51.5\% & 50.1\% & \(-\) & 48.5\% \\ Inter-chip HD & 50.5\% \({}^{\text{d}}\) & \(-\) & 49.9\% & 49.3\% & \(-\) & 49.8\% \\ \hline \hline \end{tabular}  
\end{table} 
Table 4: Performance and comparison with prior studies. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**The Absolute** & & & & & \\
**Address 0X10004A00** & **Output Result (HEX)** & **BER at \(-\)40 \({}^{\text{o}}\)C** & **BER at 80 \({}^{\text{o}}\)C** & **Inter-Chip HD** \\ \hline No. 1 chip (20 \({}^{\text{o}}\)C) & e3 cI 138f 03 be 07 fc 3e4f 3937 fd1e ec07 & 0 & 0 & 51.56\% (No. 1 to No. 2) \\  & fbl 489e 083e 966 f3e6 867e 16b 677 960 & & & & \\ No. 2 chip (20 \({}^{\text{o}}\)C) & 1 cf c7/7113 64f 062e 80e 1 cf 1c1 & & & & \\ No. 3 chip (20 \({}^{\text{o}}\)C) & 3 cI 1 fc 73 fc 160f 9346 7101 3013 11c3 & & & & \\ No. 3 chip (20 \({}^{\text{o}}\)C) & 7c19 7539 2 se1 8360 6 eftf 281 9380 8 fe2 & & & & \\ cfe1 e0e2 9283 1837 3 be0 7f81 0798 9 be0 & & & & & \\ \hline \hline \end{tabular}  
\end{table} 
Table 3: The performance of absolute address 0X10004A00 in three chips. original draft preparation, R.C.