## 3 Proposed Overload Control Algorithm
This efficiency directly supports the development of lightweight and scalable control logic, which is essential for reliable and energy-efficient DCS operation. In conventional memory management, the standard storage unit is the byte, whereas the proposed CFP (compressed function processor) utilizes the bit as the fundamental unit, allowing for more fine-grained memory efficiency. Additionally, the NFP (non-functional processor) module integrates a test bench circuit that includes an AFP (analog function processor) to enable virtual operation simulations. While DCS system logic algorithms may be optimally designed, unforeseen operational issues can still arise during runtime. To address this, we designed the AFP using a flash ADC architecture, selected for its superior conversion speed compared to other ADC types such as pipeline and sigma delta ADCs. Although flash ADCs are known for high power consumption and extensive chip area usage [8; 11], we implemented a low-power variant of the AFP to mitigate these \begin{table}
\begin{tabular}{c c c} \hline \hline
**Equation** & **Conventional Compression Algorithm 2(n – 1)** & **Proposed Algorithm 2(n – 1)(d + 1)** \\ \hline Calculation & 2(n – 1) = 2(8 – 1) & 2(n – 1)(d + 1) = [2(8 – 1)(3 + 1)]/8 \\ \hline Total & & \\ memory & 14 byte & 7 byte \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Comparison of conventional and proposed compression algorithms in terms of memory utilization and execution complexity. Figure 2: Screenshot processor utilization monitoring within a distributed control system (DCS) using the automation architect environment. drawbacks. As shown in Table 4, the proposed AFP design achieves significant power reductions compared to conventional flash ADCs--approximately 15.38%, 42.37%, 57.20%, 63.86%, and 72.58%--for resolutions ranging from 4 to 8 bits, respectively [11; 12]. These improvements result from the fact that the number of components required in the AFP is governed by the expression defined in Equation (3). \[T_{Mp}=2^{(N-1)}-1+C \tag{3}\]  
where \"\(T_{Mp}\)\" is the number of components used for the AFP architecture and \"C\" is the number of components used to design the proposed circuits. Table 4 presents a comparative analysis between a conventional flash ADC and the proposed analog function processor (AFP) across resolutions from 4 to 8 bits. While both architectures exhibit identical power consumption at each resolution level, the AFP achieves a significant reduction in the number of required comparators--up to 72.58% at 8 bits--resulting in substantial hardware efficiency. This reduction is critical in DCS environments, where minimizing circuit complexity directly contributes to improved scalability, reduced power density, and lower thermal stress. The ability of the AFP to maintain performance while reducing hardware overhead makes it highly suitable for real-time control applications, particularly in overload-prone or resource-constrained embedded systems. The AFP achieves identical power levels with significantly fewer comparators across resolutions from 4 to 8 bits, yielding efficiency improvements up to 72.58%. This reduction in hardware complexity contributes to enhanced power efficiency and scalability in embedded DCS environments. The test conditions were a 3.3 V supply voltage, 1.65 V reference voltage, 1 GHz sampling rate, and 100 ns transient time [13]. As shown in Table 4, the proposed analog function processor (AFP) significantly outperforms the conventional flash ADC in terms of hardware efficiency, without compromising power consumption. The efficiency, defined as the percentage reduction in comparator count, is calculated using the following expression:  
\[Efficiency\left(\%\right)=\left(1-\frac{N_{AFP}}{N_{Conventional}}\right) \times 100 \tag{4}\]  
where \(N_{AFP}\) is the number of comparators used in the AFP, and \(N_{Conventional}\) is the number of comparators required by the conventional flash ADC.