# A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits
## 8 Cell-Aware Based SDD Testing  
The traditional fault models like stuck-at, bridging [57], and transition model [9] consider faults only at the ports of the cells. But in most realistic scenarios, the defects that exist inside the cell cause test escapes. Opens, shorts, or bridges that occur in the interconnects or transistors within the cell are the intra-cell defects [9; 58; 59]. Standard fault models can detect many defects inside the cell. But still, to detect certain specific intra-cell defects, unique test patterns are needed that are not detected by standard fault models. The most commonly considered faults models for intra-cell defects are transistor stuck open [60], cross wire open [61], resistive open [62] and resistive shorts [63], which depend on SPICE simulation on a transistor level fault model without using parasitic information. When the size of the circuit grows (millions of transistors), the test pattern generation at the transistor level is inefficient. This motivates the researchers to develop a novel fault model based on cell layouts that can be generated totally automatically and enables the ATPG tool to develop a set of input patterns that identify all cell-internal defects. For this purpose a new method called CA-based testing was introduced [64]. The SPICE transistor-level netlist and the RC (Resistance, Capacitance) parasitics information from the layout are used to identify the possible defect location. The resistance location in the SPICE netlist denotes the possibility of an open or short defect, and the capacitance location indicates the possibility of a bridge defect. In [65] the CA-based testing is proved to be more efficient in testing the cell's internal faults with reduced test cost (reduced test patterns, runtime) than gate exhaustive [66] and N-detect testing [67]. The importance of 2-time frame CA test patterns to test intra-cell delay defects is discussed in [68]. The 2-time frame fault represents the intra-cell defect, which causes a delay in the transition of the signal. To target these faults, the patterns are generated. The 2-time frame CA-based delay test performed on an AMD 32 nm notebook processor proves  
Figure 9: Comparison of maximum path delay of a pattern in each test group for at-speed test, FAST with IR drop effect [23]. that most chips that fails the test are defective, as shown in [69]. This test can detect both large and small delay defects. Hence, the classification of delay defects based on their size is essential to extract the essence of the test. In [70], the CA-based small delay fault is identified by considering the amount of voltage deviation from the supply voltage due to the fault effect in the cell output at a particular strobe time. The fault is considered to be a small delay fault when the voltage level at the cell's output is less than 50% of the supply voltage. But the measurement of voltage deviation is not an accurate way to categorize the delay fault size. Also, the fault consideration is based on the per cell of the standard cell library and does not consider all the cell instances. Different cell instances in a design have different output capacitive loads, which in turn have different timing impacts on the slack of the instance. Based on this observation in [70], the classification of small and large delay faults can be more accurate when the timing impact is considered on a cell instance basis. The problem is dealt with in [71] to improve the accuracy of classifying the small and large delay faults. Instead of considering the output voltage deviation at the cell's output, the excess delay due to the fault for each cell instance slack is considered for delay fault classification. This method [71] reduces the number of small delay faults to be detected as compared to the method in [70]. The decrease in the number of faults is due to the accuracy of the method used.