# Neuromorphic Neural Engineering Framework-Inspired Online Continuous Learning with Analog Circuitry
## 3 Results
### Circuit Design
#### 3.1.2 Learning Core  
We propose a novel analog circuitry with which OZ neurons could be utilized to learn neuromorphic representations, transformation, and dynamics using the realization of the PES learning rule. This circuit design aims at online learning with neuromorphic analog circuitry, and it is scalable to comprise numerous OZ learning cores. The system schematic is shown in Figure 2A. In each learning core, a normalized input signal is preprocessed to drive positively and negatively encoded neurons. The preprocessing module is slightly differently configured for each encoding modality, simplified here for clarity. See [15] for a full description.  
With OZ neurons, the input signal is rate-coded (following the neuron's tuning curve) and temporally integrated. The integrated signal is driven into a learning block alongside a normalized error signal and a learning rate. The learning block (Figure 2B) processes the signal and transforms it to an optimized value by minimizing the error signal using hardware realization of PES learning. The learning block is also responsible for the maintenance of the neuron's weight. Finally, all learning blocks' outputs are summed up by an adder block achieving an estimated signal. The estimated signal is subtracted from the desired signal, providing the error signal. The error signal is divided by the number of neurons (via a voltage divider, not shown in the diagram) and sent back to the learning block.  
The electrical circuit constituting the learning block is shown in Figure 2C. The learning block circuit comprises a voltage divider (accounting for a learning rate, colored blue), two multipliers (colored purple), and a weight update module (colored orange). Analog multipliers were implemented by subtracting the outputs of two analog squaring circuits. One squaring circuit is driven by the summation of the two signals (\(x\), \(y\)) and the other by their difference, following: \((x+y)^{2}-(x-y)^{2}=4 xy\). A differential amplifier further modulates the resulting value to factor out the constant. The diode bridge operates in an extensive frequency range, and its square law region is at the core of the squaring circuit. The left diode bridge handles \(x+y\) and the right bridge handles \((x-y)\) (\(y\) is negated with an inverting op-amp). The squaring circuit's output current can be approximated with Taylor's series. As the differential output across the diode bridges is symmetric, each bridge's output comprises the even terms of the combined Taylor expansions. Odd terms are removed due to the four diode currents, as they produce frequency components outside the multiplier's passband. Therefore, the resulting output of the circuit is proportional to the square of its input.  
The first multiplier multiplies the normalized error with the neuron's temporally integrated spikes, constituting a weight update. Weights are implemented with a memory cell (transistor-capacitor), allowing the maintenance of negative values at low overhead. Using a recurrently connected summing amplifier, the weight update circuit sums the updated value with its current weight value. The second multiplier multiplies the weight with the neuron's temporally integrated spikes providing the neuron's output.