# Effect of P+ Source Pattern in 4H-SiC Trench-Gate MOSFETs on Low Specific On-Resistance
## 3 Results and Discussion  
The output characteristics of conventional TMOSFETs with square and stripe patterns are compared with those with a grid P+ source at V\({}_{\text{gs}}\) = 9 and 20 V and V\({}_{\text{ds}}\) = 10 V in Figure 3. A grid pattern with a half-cell pitch of 1.5 \(\upmu\)m provides a larger current than a square pattern with a half-cell pitch of 2.3 \(\upmu\)m and a stripe pattern with a half-cell pitch of 2.0 \(\upmu\)m. The difference in R\({}_{\text{on,sp}}\) originates from the cell pitch. Thus, the R\({}_{\text{on,sp}}\) of a grid pattern with a P+ source length (L\({}_{\text{PP}}\)) of 0.5 \(\upmu\)m is less than the R\({}_{\text{on,sp}}\) with a square pattern or stripe pattern, approximately 4.5% and 2.4% less, respectively. Figure 4a shows the output characteristics of grid P+ source TMOSFETs with different L\({}_{\text{PP}}\) at V\({}_{\text{gs}}\) = 9 and 20 V and V\({}_{\text{ds}}\) = 10 V. Maintaining a cell-pitch of 3.0 \(\upmu\)m including the trench width, the N+ source width, P+ source width, and L\({}_{\text{PP}}\) values of 0.5 to 2.5 \(\upmu\)m with 0.5 \(\upmu\)m steps, respectively, were used to examine the impact of L\({}_{\text{PP}}\) on the specific on-resistance (R\({}_{\text{on,sp}}\)). As L\({}_{\text{PP}}\) increased, the reduction in channel area produced an increase in R\({}_{\text{on,sp}}\). Figure 4b shows the measured R\({}_{\text{on,sp}}\) with different half-cell pitches for the grid pattern and different P+ source lengths. As expected, a smaller cell pitch resulted in a lower R\({}_{\text{on,sp}}\). With a cell pitch of 3.0 \(\upmu\)m, TMOSFETs with a grid pattern produce a lower R\({}_{\text{on,sp}}\) than a square pattern for all L\({}_{\text{PP}}\) values. A grid pattern with L\({}_{\text{PP}}\) = 2.5 \(\upmu\)m reduced the channel area approximately 50%; with a cell pitch of 3.0 \(\upmu\)m, the channel area was reduced approximately 35%. Although the percentage decrease in the channel area was larger than the percentage decrease in cell pitch, R\({}_{\text{on,sp}}\) for the grid pattern was less than that for the square pattern because the effect of the cell pitch was dominant. Compared with a stripe pattern, TMOSFETs with a grid pattern have a lower R\({}_{\text{on,sp}}\) except with an L\({}_{\text{PP}}\) of 2.5 \(\upmu\)m. Thus, cell pitch is critical for determining the specific on-resistance. The grid pattern TMOSFETs with the cell-pitch of 4.0 \(\upmu\)m and 4.6 \(\upmu\)m were fabricated to investigate the influence of the reduced channel areas. Maintaining the cell-pitch of 4.0 \(\upmu\)m or 4.6 \(\upmu\)m, the R\({}_{\text{on,sp}}\) of grid pattern TMOSFETs compared to the R\({}_{\text{on,sp}}\) of stripe pattern TMOSFETs or the R\({}_{\text{on,sp}}\) of square pattern TMOSFETs, respectively. As a results, the stripe pattern or the square pattern have a lower R\({}_{\text{on,sp}}\) than the grid pattern in the same cell-pitch because of the effect of the reduced channel areas in Figure 4b. Figure 3: Output characteristics of TMOSFETs with square, stripe, and grid pattern. Figure 5a shows the forward blocking behaviors of all simulated TMOSFETs with stripe, square, and grid patterns with different cell pitches and \(\mathrm{L_{PP}}=0.5~{}\upmu\)m. The grid and stripe patterns produced a higher forward blocking voltage than the square pattern. In the TMOSFETs with a square pattern, a high impact ionization rate was observed at the P+/N+ junction at all edges of the square, and each point in the square pattern produced an increase in the electric-field stress, leading to a reduced breakdown voltage. To examine the impact of \(\mathrm{L_{PP}}\) on forward blocking characteristics, \(\mathrm{L_{PP}}\) of 0.5 \(\upmu\)m, 1.0 \(\upmu\)m, 1.5 \(\upmu\)m, 2.0 \(\upmu\)m, and 2.5 \(\upmu\)m were designed to maintain the cell pitch. The role of the P+ source is to restrain a punch-through across the junction formed between the P-well and the N-drift region in forward blocking conditions [4].