# Transforming Group Codes in Mealy Finite State Machines with Composite State Codes
## 6 Experimental Results  
We conducted experiments to compare four characteristics of \(U_{3}\)-based FSM circuits with the characteristics of FSM circuits based on other state assignment methods. These characteristics were the cycle times, maximum operating frequencies, LUT counts and area-time products. As an example of an MBC-based method, we use [PERSON]'s Auto method [36]. Let us point out that the number of code bits used by Auto may exceed the minimum value determined by (1). [PERSON]'s one-hot method [36] was used as an example of OHC-based state assignment. Also, we compared our approach with the algorithm JEDI [30], which is an MBC-based algorithm creating cubes covering the codes of some states [3]. Finally, we executed a comparison of \(U_{3}\)-based FSM circuits with their \(U_{2}\)-based counterparts [11]. In the experiments, we used benchmark FSMs from the well-known library LCSynth93 [38]. There are 48 Mealy FSMs (benchmarks) in the library. The benchmarks are represented in the KISS2 format. These benchmarks have a wide range of basic characteristics (numbers of states, inputs, outputs and transitions). A lot of scientists have been using these benchmarks as a basis for the comparison of various design methods [39, 40, 41]. The characteristics of the benchmarks are shown in Table 7. The last column of this table includes the sum of the number of FSM inputs and the minimum number of bits in the maximum binary state codes. We used this additional column to select benchmarks where structural decomposition made sense. To conduct the experiments, we used a platform including the FPGA chip from the Virtex-7 family. This was a VC709 Evaluation Platform (xc7 vx690 ffg1761-2) [22]. The CLBs used included basic LUTs with six inputs (\(S_{L}=6\)). To implement a CLB-based circuit of _LUTerY_\(\tau\), the dedicated multiplexers could be used. Each CLB included four basic LUTs and three dedicated multiplexers. We use theed industrial CAD package Vivado v2019.1 (64-bit) [36] to execute the step of technology mapping. Using the Vivado reports, we created four tables showing the results of the conducted experiments. Each Boolean function, \(f_{i}\in D\cup Y\), depended on \(NL_{i}\) arguments. If condition (4) was violated for all IMFs and FSM outputs, then the circuit of FSM \(U_{1}\) consisted of exactly \(R+N\) LUTs. So, each function, \(f_{i}\in D\cup Y\), was generated by a single-level circuit. In this case, the \(U_{1}\)-based FSM circuit possessed the best spatial and temporal characteristics. This model provided the minimum values of the LUT count and propagation time. So, if condition (4) is violated for all input memory functions and FSM outputs, there is no need to use either functional or structural decomposition. Obviously, the states may be encoded in a way minimizing the power consumption [24,27]. As follows from the results of the experiments shown in article [11], condition (4) only held for some benchmarks. These benchmarks had the following common property:  
\[L+R>2S_{L}. \tag{28}\]  
For FSMs satisfying (28), it made sense to replace \(U_{1}\)-based FSMs with FSMs with composite state assignment. We could use either the \(U_{2}\) or \(U_{3}\) models. For FPGAs from the Virtex 7 family, the basic LUT had \(S_{L}=6\) inputs. Due to this, in our research, we only usedbenchmarks for which \(L+R>12\). The experimental results are shown in Table 8 (cycle times, nanoseconds), Table 9 (maximum operating frequency, MHz), Table 10 (LUT counts) and Table 11 (area\(-\)time products).