# A 5 Gb/s Optoelectronic Receiver IC in 180 nm CMOS for Short-Distance Optical Interconnects
## 2 Circuit Description
### 3-Bit Continuous-Time Linear Equalizer (CTLE)  
A 3-bit continuous-time linear equalizer (CTLE), illustrated in Figure 5, is utilized to achieve adaptive equalization through the integration of advanced techniques such as source degeneration, inductive peaking, and negative capacitance [12]. These techniques strategically shape the transfer function by introducing a programmable zero-pole pair, which enhances the high-frequency gain and compensates for the frequency-dependent loss of the preceding channel. Specifically, inductive peaking extends the bandwidth by mitigating the effect of the dominant pole, while negative capacitance cancels parasitic capacitance to maintain gain at higher frequencies. The CTLE operates in a fully analog manner without requiring any clock signal, making it suitable for high-speed, low-power applications.  
To enable dynamic adaptation to varying channel conditions, a 3-bit digital-to-analog converter (DAC) is incorporated to control the NMOS resistor array used for source degen  
Figure 4: Schematic diagram of the CCD-TIA.  
eration. In conjunction with programmable capacitors, the DAC adjusts Rs and Cs values in real time, allowing the CTLE to autonomously tune its gain and bandwidth. This results in a fully adaptive equalization mechanism that optimizes signal integrity across different levels of inter-symbol interference (ISI) and channel attenuation [13].  
In terms of noise performance, the CTLE introduces thermal noise primarily from the source degeneration resistor and the active devices in the signal path. While inductive peaking and negative capacitance improve bandwidth, they may also contribute additional noise or affect noise shaping depending on the design topology. Careful optimization of the resistor values and device sizing is required to minimize the overall input-referred noise and maintain a high signal-to-noise ratio (SNR), especially at high frequencies.  
The input-referred noise voltage density can be approximated as  
\[\overline{v}^{2}_{n,in}\approx 8 kTRs+\frac{8 kT\gamma}{g_{m}\gamma}+\frac{8 kT \gamma}{g_{m}8}\]  
The input dynamic range of the CTLE is defined as the range of input voltage swings for which the circuit remains in its linear operating region. This can be expressed in terms of the Input Referred 1 dB Compression Point (\(V_{in,1 dB}\)), beyond which the gain drops by 1 dB due to nonlinearity.  
A rough estimate of the maximum linear input swing (\(V_{in,max}\)) for a differential input pair with source degeneration is given by  
\[V_{in,max}\approx\frac{2I_{bias}\Big{(}R_{s}+\frac{1}{8\pi\sigma}\Big{)}}{ \sqrt{2}}\]  
Figure 5: Schematic diagram of the 3-bit CTLE.  
This shows that adding source degeneration increases the linear input range, at the cost of reduced transconductance and possibly lower gain. Therefore, \(R_{S}\) and \(g_{m7}\) must be co-optimized to balance linearity, gain, and noise.  
The filter's transfer function incorporating the capacitive degeneration can be given by  
\[H(s)\approx\left(\frac{g_{m7}R_{L}}{1+\frac{g_{m7}R_{L}}{2}}.\frac{1+\frac{s}{ \omega_{z}}}{\left(1+\frac{s}{\omega_{p1}}\right)\cdot\left(1+\frac{s}{\omega_ {p2}}\right)}\right)^{2},\]  
where \(\omega_{z}=\frac{1}{R_{s}C_{S}},\omega_{p1}=\frac{1+\frac{g_{m7}R_{L}}{2}}{R_{ s}C_{s}}\), and \(\omega_{p2}=\frac{1}{R_{s}C_{L}}\)[13].