# Automatic Configurable Hardware Code Generation for Software-Defined Radios+
## 8 Experimental Results
### A Case Study  
In this section, we present a case study on the design and implementation of eight typical SDR applications using our Scala-based compiler framework. These applications comprise the two Orthogonal Frequency Division Multiplexing transmitters (OFDM-TX) which are both based on a modified IEEE 802.11a standard [25] and IEEE 802.22 standard [26] respectively and the two receivers (OFDM-RX) which are also based on IEEE 802.11a standard and IEEE 802.22 standard respectively. Additionally, the multiple input multiple output (MIMO) system is implemented in combination with OFDM which is based on IEEE 802.11a standard, for which the complete system is referred to as MIMO-OFDM in our results [27]. The MIMO-OFDM system is composed of two typical SDR subsystems namely the MIMO-OFDM transmitter (MIMO-OFDM) and receiver (MIMO-OFDM RX) where each of these have four output ports and four input ports respectively. The last two applications derive from a Digital Down Converter (DDC) whereby the first one implements Frequency Modulation (FM) (i.e., the FM-DDC design) and the second one realizes a Global System for Mobile communication (GSM) design (i.e., GSM-DDC). All these applications are specified as a SDF-AP model using Scala in our framework. The IP cores that compose the applications are largely described by hand in VHDL and the corresponding access patterns for each IP core are determined through low-level simulations using the Xilinx ISim Simulator. In some cases, where the third-party IP cores are incorporated into the implementation, we made use of the data-sheets documentation of these cores to determine appropriate access patterns for their use. The eight SDR applications, namely **OFDM TX (IEEE 802.11a)**, **OFDM RX (IEEE 802.11a)**, **OFDM TX (IEEE 802.22)**, **OFDM RX (IEEE 802.22)**, **MIMO-OFDM TX (IEEE 802.11a)**, **MIMO-OFDM RX (IEEE 802.11a)**, **GSM DDC and FM DDC** are depicted in Figure 11 and the SDF-AP properties of each application are summarized in Table 2. These properties include the number of Actors, the total  
Figure 10: The proposed compiler framework. number of FIFO channels and the number of FIFO channels which are allocated the buffer size of 1. The applications are briefly described below:  
1. **OFDM TX (IEEE 802.11a)**: As shown in Figure 11a, the IEEE 802.11a standard transmitter receives a frame of 48 real-valued data samples which are sent by the source block at the rate of one sample on every cycle of 48 successive clock cycles using the output pattern \([1]\). The Quadrature Amplitude Modulation (16-QAM) block (**Mod**) uses pattern \([010]\) to receive the frame where a single data sample is consumed on every second cycle. The _Mod_ modulates the 48 data samples from the source block into 48 I/Q samples in a frequency domain and outputs them on every third clock cycle using the pattern \([001]\). This is followed by a zeropad insert (**ZP-I**) that appends 16 zeros to the 48 samples which are consumed with pattern \([(1)^{48}(0)^{17}]\), whereafter the _ZP-I_ produces 64 samples with pattern \([0(1)^{64}]\). The 64-sample frame serves as an input to the 64-point Inverse Fast Fourier Transform (**IFFT**) block which receives samples with pattern \([(1)^{64}(0)^{64}]\) (i.e., 64 samples are consumed in the first 64 cycles of ET=128). The _IFFT_ transforms the 64 samples from the frequency domain to the time domain and sends out the output samples with pattern \([(0)^{64}(1)^{64}]\) (i.e., 64 samples are produced in the last 64 cycles of ET=128). The _IFFT_ is followed by a cyclic prefix insert (**CP-I**) block which prepends the cyclic prefix (last 16 _IFFT_ samples) to the 64 _IFFT_ samples received with pattern \([(1)^{64}(0)^{65}]\). The 80 samples are then produced by the _CP-I_ using pattern \([(0)^{49}(1)^{80}]\), followed by the sink block which receives the 80-sample frame at the rate of one sample per cycle using input access pattern of \([1]\). 2.