## 5 Experimental Results and Discussion
### ASIC Implementation Results  
ASIC designs of the published works of [PERSON] (2017), [PERSON] (2017), [PERSON] (2017), [PERSON] (2018), as well as our proposed design were implemented using VHDL for field size \(n=409\) and embedded applications word sizes \(k\) of 8, 16, and 32. The developed code was synthesized using Synopsys design compiler 2005.09-SP2 with the NanGate (15 nm, 0.8 V) Open Cell Library. The simulations used Mentor Graphics ModelSim SE 6.0a tools and produced a Switching Activity Interchange Format (SAIF) file to obtain the power report. The simulations went through 300 possible 32 bit input combinations. Post-layout simulations were used to accurately model the delays, power, and area. Table 2 summarizes the ASIC implementation results for the proposed design and the previously published designs. The design performance metrics were: (1) latency: the total time steps required to produce the final results; (2) Area (A): the required hardware resources estimated in terms of the two-input NAND gate; (3) Time (T): the execution time required to produce the output; (4) Area-Time product (AT): the product of A and T  
\begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline
**Multiplier** & \(k\) & **Latency** & **Area (A)** & **CPD** & **Time (T)** & **AT** & **Power (P)** & **Energy (E)** \\ \hline \multirow{3}{*}{Xie (2017)} & 8 & 324 & 92.98 & 56.4 & 18.27 & 1699.0 & 225.56 & 4.12 \\ \cline{2-8}  & 16 & 172 & 146.96 & 56.4 & 9.70 & 1425.5 & 375.5 & 3.64 \\ \cline{2-8}  & 32 & 98 & 195.13 & 56.4 & 5.53 & 1078.5 & 477.4 & 2.64 \\ \hline \multirow{3}{*}{Pan (2017)} & 8 & 48 & 97.46 & 206.3 & 9.90 & 964.9 & 252.91 & 2.50 \\ \cline{2-8}  & 16 & 36 & 123.93 & 244.4 & 8.80 & 1090.6 & 320.07 & 2.82 \\ \cline{2-8}  & 32 & 24 & 164.34 & 282.5 & 6.78 & 1114.2 & 425.09 & 2.88 \\ \hline \multirow{3}{*}{Hua (2017)} & 8 & 259,584 & 7.99 & 73.4 & 19,053.47 & 152,237.2 & 4.35 & 82.88 \\ \cline{2-8}  & 16 & 129,792 & 10.40 & 73.4 & 9526.73 & 99,077.9 & 5.85 & 55.73 \\ \cline{2-8}  & 32 & 64,896 & 19.91 & 73.4 & 4763.37 & 9  
(5) Power (P): the power consumption; (6) Energy (E): the consumed energy obtained as the product of P and T.  
It is important to note that the published word-serial multipliers of [45; 50; 60; 61] only perform multiplication operation, while the proposed word-serial multiplier-squarer concurrently performs both multiplication and squaring operations. Therefore, to have a fair comparison, the word-serial multipliers of [45; 50; 60; 61] should sequentially compute both operations. The execution of multiplication and squaring operations in sequence resulted in doubling the latency, T, P, and E.  
Examining Table 2, we note the  
Figure 14: Consumed energy results. Figure 12: AT results. Figure 13: Consumed power results. From Figure 10, we notice that the multiplier structure of Hua [60] achieved a lower area (A) at word sizes \(k=8\) and \(k=16\), by at least 21.3% and 23.0%, respectively. In contrast, at the word size of \(k=32\), the proposed multiplier-squarer structure achieved the smallest area by at least 22.95%. The reduction of the proposed structure's area was mainly attributed to the significant decrease in the number of flip-flops as the word size increased, as we discussed before in the previous subsection. From Figure 11, we notice that the multiplier structure of Pan [45] achieved a significant reduction in time (T) at word sizes \(k=8\) and \(k=16\) due to its significantly lower latency. On the other hand, the multiplier structure of Xie [50] realized a slight reduction in T, at word size \(k=32\), compared to that of Pan [45]. Due to the fluctuations in the obtained results of the latency, A, and T among the different multiplier structures at different word size, we added the Area-Time product (AT) metric to Table 2. The AT metric enabled us to discover the optimal multiplier structures in terms of area and time. From Figure 12, we notice that the proposed multiplier-squarer structure achieved the lowest AT for word sizes \(k=16\) and \(k=32\).