# A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS
## 3 Transmitter System Architecture
### Precoding Design  
In the process of signal transmission, the two-level input signal generates the three-level DB signal through the DB conversion circuit. The DB conversion circuit realizes \(y_{n}=x_{n}+x_{n-1}\), and the signal judgment \(x_{n}=y_{n}-x_{n-1}\) is the reverse operation of the sending end. Therefore, the sampled decision value \(x_{n}\) is closely related to \(x_{n-1}\) at the previous moment. Assuming that the sampled decision value \(x_{n-1}\) at the previous moment is wrong, error codes will appear at the next moment, and error codes will be transmitted continuously, resulting in an error transmission. Therefore, in order to have no correlation between the front and back codes, a precoding circuit is used before the DB conversion circuit.  
The precoding module is usually behind the MUX, as shown in Figure 3. Considering the power, area, and PVT variations, it is not advisable to cascade active or passive devices to obtain an accurate delay in an open loop. Traditionally, the clock-driven flip-flop is used to ensure the delay time, but it also has strict phase requirements. Its timing diagram is shown in Figure 4; data experience \(T_{XOR}\) and \(T_{D-Q}\) delays through the XOR gate and flip-flop, respectively, [21]. For the precoder to work properly, the two delays must contain an exact bit period \(T_{b}\), that is, \(T_{XOR}+T_{D-Q}=T_{b}\), where \(T_{XOR}\) is the delay time after the XOR gate, \(T_{D-Q}\) is the delay time after the flip-flop, and \(T_{b}\) is an exact bit period.  
The input clock has very little phase margin to generate the appropriate \(D-Q\) delay for the flip-flop. This timing problem becomes more serious at high speed. When the data rate rises to 112 Gb/s or above, 1 UI is only 8.93 ps, which makes the change of PVT difficult to resist. Therefore, when the data rate reaches 112 Gb/s, the data should be precoded before the MUX, as shown in Figure 5.  
Figure 2: Transmitter system architecture.  
Figure 4: Sequence diagram.  
Figure 5: Proposed precoding structure diagram.  
Figure 3: Traditional precoding structure diagram.  
\(D_{\text{out3}}\) calculated from the previous loop is  
\[D_{\text{out3}}=D_{0}\oplus 0\ OR\ D_{0}\oplus 1. \tag{1}\]  
The resulting \(D_{out0}\) signal and \(D_{out1}\) signal are  
\[\text{D}_{\text{out0}}=D_{\text{out1}}=D_{1}\oplus(D_{0}\oplus 0)\ OR\ D_{1}\oplus(D_{0}\oplus 1). \tag{2}\]  
The timing sequence diagram of the proposed precoder is shown in Figure 7. The critical path of the circuit is controlled by the 1/2 clock from \(D_{x}\) to \(D_{y}\), and its timing expression is  
\[\frac{T_{qclk}}{2}=2T_{b}>T_{y\_lat}+T_{d\_muux}+T_{d\_setup}, \tag{3}\]  
where \(T_{qclk}\) is the clock period, \(T_{b}\) is an exact bit period, \(T_{d\_lat}\) is the time difference between the data and the clock, \(T_{d\_muux}\) is the delay time of the MUX, and \(T_{d\_setup}\) is the hold time.  
Assume that \(D_{k}\) stabilizes in half a cycle, or the cycle path of the whole cycle starts and ends at \(D_{y}\), and its sequence expression is  
\[T_{qclk}=4T_{b}>T_{d\_diff}+2T_{d\_muux}+T_{d\_setup}, \tag{4}\]  
where \(T_{d\_diff}\) is the delay time after the flip-flop, \(T_{d\_muux}\) is the delay time after the MUX, and \(T_{d\_setup}\) is the hold time.  
Figure 6: Proposed precoding structure diagram.