## 5 Experimental Validation  
This section describes the validation process of simulation testing through experiments. After the simulation was implemented onto the FPGA board, the bit file was generated and downloaded onto the 40 nm Virtex-6 FPGA chip. The input and output configuration is shown in Table 4. First, the _rst_ input was enabled for 1 s, followed by the _Vi_ input signal. Subsequently, the automatic clock correction input called _enable_ triggered the clock correction procedure for the entire FPGA system. This process was repeated for 100 random samples without a specific injected delay signal to validate the proposed design. The output observation on the 40 nm Virtex-6 ML605 FPGA board is shown in Figure 13. Figure 13 shows the initial setup for the experiment. Initially, all light-emitting diodes (LEDs) were in the OFF condition. Figure 13 shows that the _rst_ input pin was enabled. This function was used to reset the entire FPGA system for preventive purposes. Figure 13 shows the input signal _Vi_ as being enabled, which generated the random percentage delay aging to the multiple-point aging sensor module. For example, when the percentage delay was between 301\({}^{\circ}\) and 359\({}^{\circ}\), the LEDs showed the values of 3\(F_{16}\). The LEDs were turned ON according to the aging detection, as stated earlier in Table 2. Finally, Figure 13 represents the automatic clock correction mode, whereby all LEDs were turned OFF and provided the best clock signal to the entire FPGA system. The percentages of _hex_ output hits for the random signal generated for _Vi_ are shown in Figure 14. The aging simulation was done for all possibilities of aging delays ranging from 1\({}^{\circ}\) to 359\({}^{\circ}\), as illustrated in Figure 11. Furthermore, the exact design of the proposed aging sensor was embedded into FPGA, as described in Figure 13. The percentages of output hits were obtained through an experimental study. Initially, the _Vi_ signal was randomly generated between 1\({}^{\circ}\) and 359\({}^{\circ}\) of aging with the delay signal. Then, this process was repeated and recorded with all potential aging signals generated. For the consistency verification of the aging sensor, the distribution of the measured seven _hex_ outputs was repeated three times. From the chart, the coefficient of variation and standard variation were calculated to be 0.02% and 1.33%, respectively. Since the standard deviation was low, this implies that the data was close to the mean value, which verifies the reliability of the aging sensor proposed. \begin{table}
\begin{tabular}{c c c c c c c c c c} \hline \hline \multicolumn{1}{c}{**Input of the DIP Switch**} & \multicolumn{6}{c}{**Output**} \\ \hline
**SW1** & **SW2** & **SW8** & **LED6** & **LED5** & **LED4** & **LED3** & **LED2** & **LED1** & **LED0** \\ \hline Vi & enable & rst & out\_as[6] & out\_as[5] & out\_as[4] & out\_as[3] & out\_as[2] & out\_as[1] & out\_as[0] \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Input and output configuration for the Virtex-6 ML605 FPGA board. Figure 13: Output result for the experiment on automatic clock correction. Table 5 provides the mean percentage hit for different kinds of _hex_ outputs, representing seven points of phase detection in line with the aging degradation based on the result obtained in Figure 14. The example stated earlier shows that the value of \(3F_{16}\) occupied approximately 13.90% of hits during the experimental testing. It shows that the design could be implemented for different aging processes. The results obtained covered all types of detection ranging from 0\({}^{\circ}\) to 360\({}^{\circ}\) according to the _hex_ output. As discussed earlier in Figure 2, the lifetime degradation was proportional to the delay degradation for the ring oscillator. It is known that the fundamental ring oscillator is constructed using CMOS, which is the same as the FPGA architecture.