# Research and Implementation of High-Efficiency and Low-Complexity LDPC Coding Algorithm
## 5 Design and Implementation of the Codec
### Coder Design and Implementation
#### 5.2.2 Coder Implementation  
The correctness and feasibility of the coding algorithm and design flow are first verified via MATLAB simulation during the coder implementation process. Then, each module is designed and implemented in the Vivado integrated environment according to the coder's functional block diagram, followed by the hardware design for this coder. Finally, the functional simulation and board-level test are conducted for the designed and implemented coder, thus completing the coder implementation that meets the demands and verifies the effectiveness and feasibility of the research design. MATLAB simulation results  
In order to verify the correctness and feasibility of the designed encoder, the M files of each module in the encoding process are first written in MATLAB. Then, a string of 1024 bit binary metadata information is input in MATLAB for encoding processing. After the encoding is completed, the 1536 bits data output is compared and analyzed with theoretical values to determine the correctness of the design. Figure 9 shows the simulation diagram of the input and output data of the designed encoder during the simulation verification process. Through the diagram, the input information of the encoder, the verification information generated by the encoder, and the output codeword information after encoding can be seen. By comparing and analyzing the software simulation results and theoretical calculation results, it was found that the two are completely identical, which further verifies the correctness and feasibility of the encoder designed in this article. Figure 8: Principle diagram of codeword generator. FPGA Implementation Results  
The correctness and feasibility of the encoder design process were verified through MATLAB simulation implementation. On the basis of software simulation implementation, first, according to the encoder implementation schematic, we performed Verilog HDL programming on each module in Vivado2018.2; then, we called each module through the top-level file to complete the hardware design of the encoder; and finally, through functional simulation and board level testing, the implementation of an encoder that meets the performance requirements of the project was completed. The performance indicators during the encoder testing and verification process are as follows: the input data transmission rate was 2 Mbps and the system clock frequency was 150 MHz (the highest operating frequency of the system is 250 MHz). The functional simulation diagram during the hardware design and implementation process of the LDPC encoder is shown in Figures 10 and 11 and Table 4.  
Figure 10 is the RTL-level simulation implementation diagram of the encoder. In order to simulate and verify the designed and implemented encoder, a signal source module was added during the encoder design process to generate input data for the encoder verification testing process. Table 4 shows the resource usage report of the encoder. Through observation and analysis, it can be seen that the encoder implementation process requires 10752 LUTs, accounting for 20.00% of the total quantity, and 12658 Registers, accounting for 12.00% of the total quantity. Figure 11 shows the simulation test results of the encoder, which is designed using an efficient and low-complexity encoding algorithm. The system clock frequency clk is 150 MHz, where \(u\) represents the 1024 bit data input by the encoder, \(p_{1}\) and \(p_{2}\) represent the 64 bit and 448 bit verification data generated by the encoder, and \(u_{1}\) represents the 1536 bit data output after encoding. According to the observation and analysis in Figure 11, it can be seen that the encoder takes 5632 clock cycles to complete the encoding of a frame of data. During the encoding process, using the  
Figure 10: RTL-level simulation diagram of LDPC encoder. Figure 9: The coder’s MATLAB simulation results. ping-pong pipeline operation mode can save a lot of time and improve the encoding speed.