## 6 Evaluation and Results
Figure 17: Xilinx Zynq UltraScale+ based hardware design for the plenoptic camera system. The initial implementations of the design were not able to meet the timing constraints, such as setup time. Moreover, the latency of first implementable design was more than 1 hour. However, after repeatedly improving the system, the latency dropped and timing constraints were met. The actual execution time of the algorithm measured in milliseconds with respect to different optimizations is arranged in Table 3. \(\mathrm{BS_{n}^{P}}\) in the first column of the table refers to the bottleneck segments listed in Table 1, whereas optimization corresponds to the approaches described in Section 5. Hence, the group of both represents the optimization used at specific \(\mathrm{BS_{n}^{P}}\). Moreover, this table includes the maximum latency obtained from Xilinx HLS as well as the utilization results acquired from Xilinx Vivado design suite. The utilization was measured by the consumption of LUTs, FFs, BRAMs and DSPs. To measure the accuracy of the results, percentage of bad pixels (BPR) that corresponded to the error \(\geq 1\) and the absolute relative error were used. The maximum achieved clock frequency that met implementation timing constraints was 200 MHz. \begin{table}
\begin{tabular}{l l c c c} \hline \hline  & & **Std. Deviation** & **Density** & **Valid Pixels** \\ \hline \multirow{3}{*}{_chair_} & Presented Alg. & 0.161 & 0.842 & 882,533 \\  & [PERSON] et al. [6] & 0.178 & 0.64 & 676,763 \\  & RxLive & 0.124 & 0.016 & 16,851 \\ \hline \multirow{3}{*}{_cup_} & Presented Alg. & 0.181 & 0.501 & 525,385 \\  & [PERSON] et al. [6] & 0.173 & 0.413 & 433,148 \\  & RxLive & 0.160 & 0.072 & 75,108 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Sparse depth map images statistics. Figure 18: Raw image (**left**), filtered RxLive sparse depth map (**middle**) and filtered sparse depth map calculated by the presented algorithm (**right**). \(\text{BS}_{1}^{\text{PP}}\), \(\text{BS}_{2}^{\text{PP}}\) and \(\text{BS}_{1}^{\text{ct}}\) were adapted to use the temporal parallelization, and the respective execution time of the algorithm consequently dropped to 1121.25 ms. Similarly, temporal parallelization on \(\text{BS}_{2}^{\text{bc}}\) and \(\text{BS}_{3}^{\text{bc}}\) resulted in gain of 394.24 and 122.89 ms respectively. The execution time was further reduced by using spatial parallelization on \(\text{BS}_{2}^{\text{bc}}\) and \(\text{BS}_{3}^{\text{bc}}\). The combination of temporal and spatial parallelization on \(\text{BS}_{1}^{\text{bc}}\), \(\text{BS}_{2}^{\text{bc}}\) and \(\text{BS}_{3}^{\text{bc}}\) caused the execution time to dramatically decrease to 334.41 ms. Subsequently, Hamming distance optimization together with arbitrary length fixed point numbers shrank down the execution time by \(\approx\)8%, which was at the cost of \(\approx\)3% additional LUTs, almost twice the BRAMs and \(\approx\)20 times more DSPs, whereas the FFs consumption was slightly improved by \(\approx\)0.25%. The overall resource usage increased due to the length of the fixed point numbers. Finally, memory optimization brought the execution time down to 27.18 ms. The corresponding gain was 283.92 ms, whereas the number of BRAMs raised to 1797 that corresponded to \(\approx\)98.5% utilization. The presented algorithm was additionally adapted, optimized, implemented and tested on a mobile GPU. It was achieved by refining bottleneck segments to exploit parallelization. The algorithm was realized using CUDA programming model. The respective specification of each execution platform employed in the evaluation process is listed in Table 4. The comparison of executing the modified single recording algorithm on the PC-system, on mobile GPU based system and on FPGA MPSoC is arranged in Table 5. The GPU was configured in 6-core 15 watt mode. The power consumption was calculated by measuring the current drawn and voltage with the help of digital multimeter (Protek 506).