## 5 Experimental Results
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline  & & & \multicolumn{2}{c}{**Bench.**} & \multicolumn{2}{c}{**Bench.+Vot.**} \\
**Name** & **IN** & **OUT** & **nd** & **SW** & **nd** & **SW** \\ \hline btbas & 2 & 2 & 6 & 6 & 3.22 & 15 & 8.47 \\ beecount & 3 & 4 & 7 & 18 & 6.48 & 53 & 19.77 \\ dk14 & 3 & 5 & 7 & 40 & 28.23 & 118 & 78.04 \\ dk15 & 3 & 5 & 4 & 26 & 15.3 & 77 & 46.67 \\ keyb & 7 & 2 & 10 & 124 & 41.01 & 313 & 96.9 \\ lion & 2 & 1 & 4 & 3 & 1.13 & 10 & 3.79 \\ lion9 & 2 & 1 & 9 & 5 & 1.77 & 16 & 6.29 \\ mc & 3 & 5 & 4 & 8 & 4.54 & 23 & 14.03 \\ train4 & 2 & 1 & 11 & 3 & 1.46 & 8 & 4.41 \\ train11 & 2 & 1 & 4 & 17 & 4.76 & 50 & 14.39 \\ \hline  & & Sum & & 250 & 107.90 & 683 & 292.76 \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Results of the synthesis of sequential circuits in the ABC system. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline  & & & \multicolumn{2}{c}{**Bench. **} & \multicolumn{2}{c}{**Bench.+Vot. **} \\
**Name** & **IN** & **OUT** & **std** & **SW** & **nd** & **SW** \\ \hline
9 sym & 9 & 1 & 118 & 48.47 & 118 & 46.99 \\ alu2 & 10 & 8 & 43 & 18.62 & 43 & 19.59 \\ alu4 & 14 & 8 & 756 & 251.86 & 759 & 253 \\ b12 & 15 & 9 & 26 & 12.18 & 26 & 11.65 \\ clip & 9 & 5 & 156  
be resource sharing between the individual modules attached to the voter inputs. Given the nature of TMR, it is an open question whether this is a beneficial phenomenon. The \(SW\) relationship in Figure 11d directly reflects the relationship of the number of resources used, so it is difficult to speak of power optimisation. Having analysed the effects of the implementation of the mitigation circuits, it is possible to move on to an analysis of the implementation of the test environment, of which the error injector (EI) is a major component. A comparison was made between the benchmarks given the mitigation (Bench.+Vot.) and the benchmarks to which the test environment containing the error injector (EI) was additionally added. Due to the complex description of the EI, the synthesis for both series was realised in the Vivado system for the logic blocks contained in the seven-series FPGAs. The results obtained are shown in Table 3 for the combinational circuits and Table 4 for the sequential circuits. In both tables, the number of LUT blocks (LUT) was determined for each series. In addition, the dynamic power (Power) value is specified. The last row is the sum of the individual values, as shown as graphs in Figure 12.  
Analysing the graphs in terms of the number of blocks used, it can be seen that for the considered set of benchmarks, the implementation of a test environment containing an error injector significantly increases the number of LUT blocks used (3.6 times for combinational circuits and almost 10 times for sequential circuits). However, it should be noted here that the benchmarks considered describe very small test circuits, so the relationships described are not entirely reliable for describing the implementation efficiency. It is worth noting that between 66 and 109 LUT blocks are required to implement the error injector, so the more complex the circuit, the lower the potential cost of EI implementation. It is very interesting to compare the dynamic power in both cases (Figure 12b,d). Despite the significant growth of the logic structure in the case with the EI, the dynamic power increases only slightly (by 22% for combinational circuits and by 37% for sequential circuits). This indicates a good implementation efficiency of the test environment, even for small circuits. Figure 11: Summary results of the synthesis in ABC: for combinational circuits, number of logic network vertices (**a**) and \(SW\) value (**b**); for sequential circuits, number of logic network vertices (**c**) and \(SW\) value (**d**). Comparing the power consumption results between Bench. and Bench.+vot., it can be seen that the results obtained are practically the same. Minor differences are due to the nature of the synthesis tool in the placement and routing stages.