# Active Clamp Boost Converter with Blanking Time Tuning Considered
## 5 Results and Discussion  
At a rated load, Figure 15 shows the gate driving signals for \(S_{1}\) and \(S_{2}\), called \(v_{gs1}\) and \(v_{gs2}\), respectively. Figure 16 shows the gate driving signal for \(S_{1}\), called \(v_{gs1}\); the voltage on \(S_{1}\), called \(v_{ds1}\); and the current in \(S_{1}\), called \(i_{ds1}\). Figure 17 shows the gate driving signal for \(S_{2}\), called \(v_{gs2}\); the voltage on \(S_{2}\), called \(v_{ds2}\); and the current in \(S_{2}\), called \(i_{ds2}\). Figure 18 shows the voltage on \(C_{c}\), called \(v_{c}\), and the current in \(L_{r}\), called \(i_{Lr}\). Figure 19 shows the voltage on \(D_{o}\), called \(v_{D0}\), and the current in \(L_{r}\), called \(i_{Lr}\). Figure 20 shows the efficiency comparison.  
Figure 14: Auto-tuning technique with X and Y called the first blanking time and the second blanking time, respectively: (**a**) with X = Y ; (**b**) with X \(\
eq\) Y.  
Figure 15: Experimental waveforms: (1) \(v_{gs1}\); (2) \(v_{gs2}\).  
Figure 16: Experimental waveforms: (1) \(v_{g81}\); (2) \(v_{d81}\); (3) \(i_{d81}\).  
Figure 17: Experimental waveforms: (1) \(v_{g82}\); (2) \(v_{d82}\); (3) \(i_{d82}\).  
From Figure 15, it can be seen that \(v_{gs1}\) and \(v_{gs2}\) are complementary to each other. From Figure 16, before \(S_{1}\) is turned on, \(i_{ds1}\) flows in the opposite direction, causing \(C_{s1}\) to be discharged to zero, making \(D_{s1}\) forward biased. At this moment, \(S_{1}\) is switched on with ZVS. From Figure 17, before \(S_{2}\) is turned on, \(i_{ds2}\) flows in the opposite direction, causing \(C_{s2}\) to be discharged to zero, making \(D_{s2}\) forward biased. At this moment, \(S_{2}\) is switched on with ZVS. From Figure 18, it can be seen that \(v_{c}\) is almost kept constant at about 60 V, close to Equation (62). In addition, according to Equation (30), the ideal value of \(T_{9}\) can be figured out to be  
\[T_{9}=\frac{Iin}{V_{o}}L_{r}=\frac{I_{o,rated}L_{r}}{V_{o}(1-D)}=\frac{2.38 \times 1\ \upmu}{42(1-0.43)}=1\ \upmu \tag{64}\]  
From Equation (64), the ideal value of \(T_{9}\) is smaller than the ideal value of \(t_{on}\) of \(v_{gs1}\), i.e., 4.3 \(\upmu\)s. Moreover, from Figure 18, the calculated value of \(T_{9}\) is 1.36 \(\upmu\)s, which is located between 1 \(\upmu\)s and 4.3 \(\upmu\)s. Therefore, we can confirm that the output diode has ZCS turn-off.  
In the following, an efficiency test bench will be described as shown in Figure 19. First of all, the input current \(I_{in}\) is attained by measuring the voltage on one current-sensing resistor according to one digital meter. Afterwards, the input voltage \(V_{in}\) is also attained by another digital meter. Therefore, the input power can be attained. As to the output power, the output current \(I_{o}\) is read from one electronic load and the output voltage \(V_{o}\) is also attained by the other digital meter. Thus, the output power can be attained. Eventually, the required efficiency can be attained. In Figure 20, there are three cases used for efficiency comparison. Case 1 is under soft switching with auto tuning of the turn-off time point of the auxiliary switch. Case 2 is only under soft switching without auto tuning of the turn-off time point of the auxiliary switch. Case 3 is only under the hard switching without auto tuning of the turn-off time point of the auxiliary switch. Therefore, at 10% load, all three have the same the second blanking time, leading to the efficiencies for cases 1 and 2 being the same. As the load is increased, only the second blanking time in case 1 is changed. From  
Figure 19: Efficiency test bench. (DC: direct current; FPGA: field programmable gate array).  
Figure 20: Efficiency comparison.  
Figure 20, it can be seen that the proposed soft switching with auto tuning of the cut-off time point of the auxiliary switch has the best performance in efficiency among them.