# Real-Time Optimization of RISC-V Processors Based on Branch Prediction and Division Data Dependency
## 4 Experiment and Result Analysis
### Processor Real-Time Testing and Performance Analysis
#### 4.3.2 Division Real-Time Testing and Comparative Analysis  
Since the division operations constitute a very small portion of the CoreMark test, a high-density division test case (Task B) written in C language is used for testing.  
The T\({}_{\text{wect}}\) data for the three processors executing Task B and the deadline time (T\({}_{\text{d}}\)) for Task B specified by the real-time system are shown in Table 12.  
For the Rev-riscv-III processor, T\({}_{\text{wect}}\) > T\({}_{\text{d}}\), indicating that in this case, T\({}_{\text{k}}\) = 0 and H\({}_{\text{rtp}}\) = 0. This means the processor cannot meet the real-time metrics allocated by the real-time system, making it unsuitable for this real-time system.  
For the other two processors, T\({}_{\text{wect}}\) < T\({}_{\text{d}}\), and T\({}_{\text{k}}\) = 1; therefore, a detailed calculation of H\({}_{\text{rtp}}\) can be performed to evaluate the real-time performance metrics of Rev-riscv and Rev-riscv-II under these conditions.  
Assuming that the real-time system places little importance on fluctuations in processor execution time during Task B (division computations), the value of A is set to 1 under these conditions.  
The H\({}_{\text{rtp}}\) parameter calculation formulas are modified as shown in Equations (5) and (6):  
\[\text{H}_{\text{rtp}}\text{=T}_{\text{k}}\text{ln}\left(\mu+\frac{\sigma^{2}} {\mu}\right) \tag{5}\]  
\[\text{T}_{\text{k}}=\left\{\begin{array}{l}1\left(\text{T}_{\text{wect}}< \text{T}_{\text{d}}\right)\\ 0\left(\text{T}_{\text{wect}}\ \geq\ \text{T}_{\text{d}}\right)\end{array}\right. \tag{6}\]  
Because there are no standard test cases for division operations, a self-developed test case is used for the division test. The corresponding C language program is shown in Figure 16. The test case primarily uses inner and outer loops to perform 200 division operations on the processor.  
The part of the main function from the disassembled file generated by compiling with the RISC-V toolchain (Eclipse) is shown in Figure 17.  
\begin{table}
\begin{tabular}{c c c} \hline
**Processor Name** & \
\begin{tabular}{c} **T\({}_{\text{wect}}\) of Processor for** \\ **Task B** \\ \end{tabular} &
\begin{tabular}{c} **The System-Specified T\({}_{\text{d}}\)** \\ **for Task B** \\ \end{tabular} \\ \hline Rev-riscv & 300 \(\upmu\)s & \\ Rev-riscv-II & 200 \(\upmu\)s & 400 \(\upmu\)s \\ Rev-riscv-III & 500 \(\upmu\)s & \\ \hline \end{tabular}
\end{table}
Table 12: The Processor’s WCET and the system-required maximum task execution time for Task B.  
Figure 16: C language test program code for division test case.  
00000018c <main>:
10c: fe010113 addi sp,sp,-32 #Stack frame setup
190: 00812423 zw w0.20(w0)
191: 02010413 addi, sp,sp.32
199: 0100793 lid #5,1 #Variable initialisation
19c: fe42423 zw zw0.20(40)
1a0: fe042423 zw zw0.20(40)
1a1: 08000647 <22c main<=08>4 ump the end of the outer loop
1a1: 06402223 zw zw0.20(40)
1a2: 02000067 lid 140m<=08>4 ump the end of the multiplication loop
1b1: 06402703 zw4.20(80)
1b4: 00207073 zw #5,4a
1b6: 00173973 sl14 s5,s5,0c1
1b2: 0047803 add #5,s5,s4
1c0: 010173973 all #5,s5,s0c1
1d: fe42423 zw #5,-20(80)
1e: fe42423 zw #5,-20(80)
1e0: 01017393 addi, #5,s5,1
1d0: fe42223 zw #5,-20(80)
1d: fe424203 zw #4,-20(80)
1e1: 090070373 lid #5,s5
1d: fe04243
1b: 09007033 lid #5,s4,1b0 mamin<024>
1e0: fe042023 zw zero.32(240) #Division Loop Initialization
1e1: 020000647 <2000647 <200064780>dump to the end of the division loop
1e2: 0642783 zw5,-20(80) division loop
1e0: 0207883 bcg45,21c <main<03>
1f0: fe42703 lw #4,-20(80)
1f1: 03000793 #1 a5,s5
1f1: 020774730 div #5,s4,s5
1f1: 0642623 zw5,-20(80)
200