## 5 Simulation Results and Discussion  
PSIM software was used to simulate the proposed inverter and evaluate its performance. The parameters used in the simulation are shown in Table 3.  
As can be seen in Figure 12, the stresses on the switches are in accordance with the theoretical stresses mentioned in Section 3, where the maximum drain to source voltage across switches \(S_{1}\) and \(S_{2}\) equals \(+2V_{dc}\), and across \(S_{3}\) and \(S_{4}\) equals \(+V_{dc}\), whilst the buck-boost switch and diode voltage stresses equal \(+2 Vds\). Thus, switches \(S_{1}\), \(S_{2}\), \(S_{5}\), and \(D_{1}\) must be rated with the ability to withstand at least double the input voltage, and switches \(S_{3}\) and \(S_{4}\), as well as diodes \(D_{2}\) and \(D_{3}\), must be rated to withstand at least the input voltage. The flying capacitor voltage \(V_{FC}\) waveform shown in Figure 13 represents a stable voltage during all periods of inverter power cycles. It presents the advantage of the buck-boost circuit in the proposed inverter topology, where it can charge the capacitor at all times irrespective of the inverter mode of operation. This leads to the minimization of the size of the flying capacitor (330 uF) as compared with similar inverters that utilize the flying capacitor concept, and it reduces the current spikes experienced by the other topologies that charge the flying capacitor directly without limiting the current, as achieved in the proposed topology by the buck-boost inductor. Another feature of this proposed inverter is shown in Figure 14: CMV is clamped to a constant value (400 V) across \(C_{PV1}\); therefore, the leakage current is almost eliminated, and only a negligible current value of 57 nA rms is flowing in the circuit, as seen in Figure 14a,b. On the other hand, Figure 14c,d show the CMV and leakage current through the parasitic capacitance \(C_{PV2}\). It is noted that CMV is 0 V and the leakage current is eliminated completely. \begin{table}
\begin{tabular}{c c} \hline \hline
**Parameters** & **Value** \\ \hline DC Bus Input Voltage \(V_{dc}\) & 400 Vdc \\ \hline Grid Voltage \(V_{g}\) & 220 Vac \\ \hline Grid Frequency \(f_{g}\) & 60 Hz \\ \hline Switching Frequency \(f_{sw}\) & 60 kHz \\ \hline PV Array Parasitic Capacitance \((C_{PV1},C_{PV2})\) & 80 nF \\ \hline Rated Power & 2 kW \\ \hline Output Current (peak) \(I_{g}\) & 12.86 A \\ \hline Flying Capacitor \(C_{FC}\) & 330 uF \\ \hline Buck–Boost Inductor \(L_{b}\) & 870 uH \\ \hline Inverter Side Filter \(L_{f}\) & 860 uH \\ \hline Grid Side Filter \(L_{g}\) & 280 uH \\ \hline Filter Capacitor \(C_{f}\) & 4.7 uF \\ \hline Switches & C3M0021120K \\ \hline Diodes & C4D20120A \\ \hline \hline \end{tabular}
\end{table} 
Table 3: System design parameters used for the simulation. Figure 14: Common mode voltages and leakage currents across the parasitic capacitances of the PV array: (**a**) CMV across \(C_{PV1}\); (**b**) leakage current in \(C_{PV1}\); (**c**) CMV across \(C_{PV2}\); (**d**) leakage current in \(C_{PV2}\). Figure 12: The simulation results of the voltage stresses on the switches: (**a**) \(S_{1}\); (**b**) \(S_{2}\); (**c**) \(S_{3}\); (**d**) \(S_{4}\); (**e**) \(S_{5}\). Figure 13: Waveform of the flying capacitor voltage \(C_{FC}\). The isolation is guaranteed by the high impedance of the parasitic capacitance between the PV panel's body and the ground. Therefore, for the DC bus voltage supplied by the PV panels, there are only high-frequency voltage harmonics; thus, the parasitic capacitance impedance is very high, as shown in Equation (40). \[X_{cpv}=\frac{1}{j\omega C_{PV}} \tag{40}\]  
Regarding the voltage harmonics caused by switching the MOSFETs at high frequency, they are eliminated in the proposed topology by clamping the common mode voltage to a constant value, inputting DC bus voltage for \(C_{PV1}\) and the ground for \(C_{PV2}\). For this reason, there is almost no leakage current, as shown in Equation (1).