# SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
## 1 Introduction  
Early planar NAND Flash technology pushed integration density by shrinking cell dimensions while adding more wordlines (WLs). However, as the cell pitch decreased, capacitive coupling between adjacent cells exacerbated program-and-read disturbances, limiting further scaling in the 2D planar architecture [1]. To address these issues, a vertically stacked 3D NAND structure was proposed [2, 3]. This architectural transition to a vertically stacked array significantly improved data storage density, marking a technological breakthrough. In the first stage of 3D NAND Flash development, the cell array was integrated next to the peripheral circuit. Peripheral circuit area remains unchanged despite the advances in NAND array technology. To further improve integration density [4, 5], the cell-over-peripheral (COP) structure was introduced [6, 7, 8, 9, 10, 11], allowing more efficient use of wafer space by placing the cell array above the peripheral circuit. However, unlike in the conventional structure, the channel in the COP structure is not electrically connected to the bulk substrate. As a result, during the erase operation, it is impossible to increase the channel potential by applying a high voltage directly to the substrate. Therefore, the gate induced drain leakage (GIDL) erase method, which utilizes band-to-band tunneling (BTBT) of electrons from the valence band into the conduction band at the drain junctionto generate holes in the channel and raise the channel potential, is employed in the COP structure [7, 12].  
However, since this hole-accumulation mechanism relies on hole generation to raise the channel potential, it requires a longer time than the bulk erase method. Moreover, as the number of WLs increases, the channel capacitance increases proportionally, further prolonging the time needed for the same hole-induced potential change and degrading overall erase throughput. Such prolonged erase time not only degrades the write performance but also raises power consumption.  
Previous studies have attempted to solve this issue either by integrating undoped Si around the bitline (BL) PAD or by employing SiGe material in order to enhance BTBT and the hole generation rate [13, 14]. Additionally, dynamic voltage scheduling based on machine learning has been proposed to generalize fixed-time erase profiles [15]. To further boost the erase speed, we propose a structure with SiGe surrounding the BL PAD in this work. SiGe has a narrower bandgap than Si, resulting in an increased BTBT rate and a significantly higher hole generation rate that accelerates erase speed while minimizing the reduction in read on-current after programming. We used Sentaurus TCAD simulation tool from Synopsys and modeled a single 96-WL 3D NAND string based on the COP structure and verified the effectiveness of this approach. Furthermore, we developed a quantitative model for the electrical characteristics such as BTBT rate and GIDL current by analyzing the voltage across the SiGe layer, the resulting electric field, and the channel potential with varying \(\mathrm{ts_{SiGe}}\), Ge composition ratio, and the voltage difference between BL PAD and GIDL transistor (GIDL TR). We also evaluated the reduction in read on-current by varying the program voltage, erase voltage, Ge composition ratio, and SiGe thickness (\(\mathrm{ts_{SiGe}}\)). As a result, the SiGe-surrounded BL PAD approach improved erase speed while minimizing the reduction in read on-current.