## 3 Circuit Design
### Simulation Analysis  
The principle of the NDPA is to add the current on the drain ATLAS step-by-step, but the offset of the current phase will bring about inefficiency. Figure 12a shows the variation of the output current of each stage of the drain. It can be seen that both the amplitude and phase of the current have changed, and the ideal situation is that the currents at all levels are superimposed in phase. Figure 12b shows the change of current at the drain output under different frequencies. It can be seen that the amplitude and phase of the output current are inconsistent at different frequencies. In the frequency range of 3 GHz-9 GHz, the amplitude difference of the current is small, but the phase difference is up to 90\({}^{\circ}\). When the frequency is 16 GHz, the current amplitude reaches the maximum, but the phase difference between the other frequency points can reach nearly 180\({}^{\circ}\). In the simulation process, adjusting the length and width of the microstrip line can greatly affect the phase, but at the same time change the impedance value calculated in Table 1.  
Figure 11: Actual schematic of a four-stage NDPA.  
Figure 13 shows the small-signal changes when the gate bias voltage changes from \(-0.2\) V to \(-2\) V. When the gate voltage bias is \(-0.2\) V, the drain current is 790 mA. When the gate voltage bias is \(-1.5\) V, the drain current is 335 mA. When the gate voltage is offset at \(-2\) V, the drain current is 154 mA. The small-signal gain decreases gradually with the increase in the gate bias voltage, the return loss S11 changes little with the gate bias voltage, and the return loss S22 fluctuates at high frequencies with the increase in the gate bias voltage.  
\begin{table}
\begin{tabular}{c c c c c} \hline
**GaN NDPA Design** & **FET Number** & \(\mathbf{W_{Q}}\) **(mm)** & \(\mathbf{R_{d,n}}\) **(Ohm)** & \(\mathbf{Z_{0}}\) **(Ohm)** \\ \hline FET Rds (Ohm/mm) = 94 & 1 & 0.5 & 188 & 188 \\ RL (Ohm) = 50 & 2 & 0.32 & 294 & 115 \\ Calculated total FET width (mm) = 1.88 & 3 & 0.32 & 294 & 84 \\ Number of cells = 4 & 4 & 0.32 & 294 & 64 \\ Supply voltage (V) = 28 & & & & \\ \end{tabular}
\end{table}
Table 1: The cell NDPA design.  
Figure 12: Drain current variation: (**a**) Variation of current in each stage of drain with time domain, (**b**) Drain final stage current as a function of frequency.  
Figure 13: Influence of gate bias voltage on small signal.  
There are errors between the capacitance and inductance in the model library and the actual devices. Therefore, the sensitivity analysis and simulation of the key components of the circuit are carried out. Figure 14 shows the sensitive elements in the NDPA circuit. It can be seen from Figure 14 that the value of the gate absorption resistance R and the value of the length of the microstrip line L3 have a great impact on the overall performance of the circuit. Figure 14b shows the Monte Carlo analysis of the length of the microstrip line L3, which is part of the gate artificial transmission line used to connect the first-stage gain unit and the second-stage gain unit. The Monte Carlo simulation is used to sample 2000 points. The median length of L3 is 272 \(\upmu\)m. The actual simulation length is 271 \(\upmu\)m.