# Design of W-Band GaN-on-Silicon Power Amplifier Using Low Impedance Lines
## 2 Design of W-Band Power Amplifier in GaN on Si HEMTs
### Design of W-Band Three-Stage Power Amplifier  
The HEMT with a 100-\(\upmu\)m gate width (four fingers) was selected as a unit transistor for the power amplifier design. It was biased to flow the current (\(I_{\text{DD}}\)) of 45.6 mA at a drain bias voltage (\(V_{\text{DD}}\)) of 10 V. Its optimum load and source impedances were obtained from the load-pull simulation as \(Z_{L,opt}=8.2+\text{j}\,12.0\)\(\Omega\), \(Z_{S,opt}=5.5+\text{j}\,0.7\)\(\Omega\), respectively, at a center frequency (\(f_{0}\)) of 90 GHz, as illustrated in Figure 1. On this condition, the common-source transistor can deliver an output power of 24.8 dBm with a gain of 3.2 dB at 3-dB gain compression point. Two unit transistors were combined in the final stage for higher output power, which theoretically lowers the input and output impedances by half. The impedance matching network can be designed using the tapered lines with continuously varying impedance and using the lines with stepped impedances [14]. In this work, the stepped impedance transformation was adopted for the compact design using microstrip lines which are fabricated on a 100 \(\upmu\)m-thick high-resistivity Si substrate (loss tangent = 0.015). Note that SiC substrates exhibit a few orders of magnitude higher resistivity than Si one [8,15]. Figure 2 shows the simulated characteristics of the microstrip lines as a function of signal metal width at 90 GHz. As expected, characteristic impedance lowers and guide wavelength shortens as the signal width increases. Therefore, the impedance matching networks consisting of low-\(Z_{0}\) lines can result in the small physical length. As shown in Figure 2b, the dielectric loss exceeds the conductor loss for the width \(\geq\) 20 \(\upmu\)m and remains almost constant. The conductor loss continuously reduces as the width increases. As a result, the low-\(Z_{0}\) lines with wide metal width ensures lower total loss. Based on this simulation result, the low-\(Z_{0}\) lines are adopted in this work for the design of low-loss impedance matching networks. Figure 1: Load-pull contours for output power of 100 \(\upmu\)m-wide HEMT at 90 GHz. Figure 2: Simulated characteristics of the microstrip line as a function of signal width at 90 GHz. (**a**) Characteristic impedance \(Z_{0}\) and wavelength \(\lambda_{g}\). (**b**) Attenuation per a wavelength (\(\lambda_{g}\)). Figure 3a shows the schematic of the final stage, consisting of two 100 \(\upmu\)m-wide HEMTs and low-\(Z_{0}\) lines that were used for the impedance transformation. At the output side, a 50 \(\Omega\) termination was transformed to low impedance by \(\text{TL}_{\text{o2}}\) with \(Z_{0}\) of 28 \(\Omega\) and moved to the optimum load impedance (\(Z_{L,opt}\)) by a short \(\text{TL}_{\text{o1}}\) with a relatively high \(Z_{0}\) of 62 \(\Omega\), as illustrated in Figure 3b. The input was matched to a 50 \(\Omega\) by using low-\(Z_{0}\) \(\text{TL}_{\text{i2}}\) (\(Z_{0}\) = 26 \(\Omega\)) and short \(\text{TL}_{\text{i1}}\) (\(Z_{0}\) = 60 \(\Omega\)), as demonstrated in Figure 3c. The widths of \(\text{TL}_{\text{i1}}\) and \(\text{TL}_{\text{ol}}\) lines were determined by considering those of the gate and drain pads of the HEMT. In order to achieve enough gain at W-band, two drive stages are added in front of the final stage as shown in Figure 4a. The first and second stages consist of the unit transistors (100 \(\upmu\)m-wide HEMT), so that the gate width ratio between stages is 1:1:2. Inter-stage and input matching networks are designed using low-impedance lines (around 20 \(\Omega\)) as like output matching network. Considering the limited gain of the transistor at \(f_{0}\), the load of each transistor (\(Z_{L1}\), \(Z_{L2}\), and \(Z_{L3}\)) is matched to the optimum load impedance for each stage to produce high power and fully drive the next stage, as shown in Figure 4b.