# A Tile-Based Multi-Core Hardware Architecture for Lossless Image Compression and Decompression
## 3 High-Efficiency Parallel Processing Architecture
### Four-Stage Pipeline-Based Compression Architecture  
The efficiency of the compression module is further enhanced by implementing pipelining techniques. These techniques are realized through a four-stage pipeline composed of four sequential finite state machines (FSMs), as shown in Figure 6. Each stage is dedicated to a specific task during the compression process.  
In the first stage, the pixel components A, B, C, and D, and the target pixel X, are read sequentially. Each reading operation is completed within one clock cycle. After component C is read, the computation of parameter P is initiated. After component D is read, the computations of parameters G1, G2, and G3 are started.  
During the first clock cycle of the second pipeline stage, the computed results of P, G1, G2, and G3 are latched. Distributing these calculations across multiple clock cycles significantly improves the operating clock frequency. It should be noted that multi-cycle operations must be implemented with strict timing constraints [22]. This approach is considered a key method for enhancing the pipeline performance. The required clock cycles for each operation are indicated in parentheses.  
Figure 6: Four-stage pipeline for compression core.  
Certain operations span multiple pipeline stages. For example, the computations of P, G1, G2, and G3 are not completed at the end of the first stage. Instead, they begin as soon as the necessary data become available.  
During the second clock cycle of the second pipeline stage, a comparison between A and X is performed. If A and X are identical, the pipeline is terminated, and a run-length code is output. Simultaneously, the calculations of parameters mQ and mErrval are initiated. If run-length encoding is output, the computation process is interrupted. Otherwise, it continues without disruption. After four clock cycles, at the fifth clock cycle of the second stage, the results for mQ and mErrval are completed and latched into registers.  
In the first clock cycle of the third pipeline stage, a check is performed to determine whether mErrval exceeds 127. If it does, encoding is skipped, and the pipeline is terminated. If not, the pipeline continues. At the same time, parameter mQ is used as an index to access parameter matrices A and N. After two clock cycles, by the end of the second clock cycle, the A and N matrices are accessed. In the third clock cycle, the indexed parameters are used to calculate parameter k. Meanwhile, updates to matrices A and N are initiated. After two additional clock cycles, at the end of the fourth clock cycle, the value of k is obtained. After three more clock cycles, the updates to matrices A and N are completed.  
In the first clock cycle of the fourth pipeline stage, parameters q and r are calculated. These calculations, which started in the fifth clock cycle of the third stage, are completed after two clock cycles. Using the calculated parameters, the Golomb-Rice-encoded result is generated after three more clock cycles. Finally, in the fifth clock cycle, the encoded result is output.