# A Review of the Optimal Design of Neural Networks Based on FPGA
## 4 Neural Network Optimization Technology Based on FPGA
### Optimization of Data and Its Operations
#### 4.1.1 Fixed-Point Quantitative  
Since the bit width of the number involved in the operation is finite and constant in FPGA calculations, the floating-point decimal number involved in the operation needs to be fixed to limit the bit width of a floating-point decimal to the range of bit width allowed by FPGA. Floating-point decimals mean that the decimal point position is not fixed, and fixed-point decimals mean that the decimal point position is fixed. Fixed-point quantization is the use of finite digits to represent infinite precision numbers, that is, the quantization function maps the full precision numbers (the activation parameters, weight parameters, and even gradient values) to a finite integer space. Fixed-point quantization can greatly reduce the memory space of each parameter and the computational complexity within the acceptable accuracy loss range, so as to achieve neural network acceleration. In 2011, [PERSON] first proposed the linear fixed-point 8-bit quantization technology, which was initially used in X86 CPU, greatly reducing the computational cost, with it then being slowly applied to FPGA [71]. In March 2020, [PERSON] et al. [72] proposed a reconfigurable CNN accelerator with an AXI bus based on advanced RISC  
Figure 6: Neural network optimization technology based on FPGA(fixed-point quantization [71; 72; 73; 74; 75; 76; 77; 78], less computations [79; 80; 81], improve calculation speed [82; 83; 84; 85], Winograd fast convolution algorithm [86; 87; 88; 89; 90; 91], Im2 col convolution optimization algorithm [92; 93; 94; 95; 96; 97], pipelined design [98; 99; 100; 101; 102], Roof-line model [103; 104; 105], ping-pong cache [106; 107; 108; 109], input feature map reuse [110; 111], filter reuse [111; 112], convolutional reuse [110; 111; 111], time reuse or space reuse [111], standardize data access and storage [113; 114; 115]). machine (ARM) + FPGA architecture. The accelerator receives the configuration signal sent by the ARM. The calculation in the reasoning process of different CNN layers is completed by time-sharing, and the data movement of the convolutional layer and pooling layer is reduced by combining convolutional and pooling operations; moreover, the number of access times of off-chip memory is reduced. At the same time, fixed-point quantization is used to convert floating-point numbers into 16-bit dynamic fixed-point format, which improves the computational performance. The peak performance of 289 GOPS is achieved on a Xilinx ZCU102 FPGA. In June of the same year, [PERSON] et al. [73] designed a CNN weight parameter quantization method suitable for FPGA, different from the direct quantization operation in the literature [72]. They transformed the weight parameter into logarithm base 2, which greatly reduced the quantization bit width, improved the quantization efficiency, and reduced the delay. Using a shift operation instead of a convolution multiplication operation saves a large number of computational resources. In December of the same year, [PERSON] et al. [74] first proposed a hardware-friendly quantization method named Sum-of-Power-of-2 (SP2), and on the basis of this method proposed a mixed scheme quantization (MSQ) combining SP2 and fixed-point quantization methods. By combining these two schemes, a better match with the weight distribution is achieved, accomplishing the effect of maintaining or even improving the accuracy. In 2021, consistent with [PERSON]'s view of whole-integer quantization [75], [PERSON] et al. [76] proposed an effective quantization method that was based on hardware implementation, a learnable parameter soft clipping fully integer quantization (LSFQ). Different from previous studies that only quantified weight parameters, input and output data, etc., their study quantified the entire neural network as integers and automatically optimized the quantized parameters in order to minimize losses through backpropagation. Then, the batch norm layer and convolution layer were fused to further quantify the deviation and quantization step.