## 2 Evaluation Methods  
### Test Pattern for Noise Evaluation  
The test structure is constructed using 0.22 \(\upmu\)m, 1-poly 2-metal standard CMOS technology and includes n-MOSFETs of various gate sizes [35; 36; 37; 38] as shown in Table 1. The measured MOSFETs are arrayed in 1024 rows and 1776 columns (total number of MOSFETs:  
Figure 2: (a) Variation in the number of electrons as a function of the number of signal electrons. (b) Logic error rate as a function of the number of signal electrons. 1217856) in a chip at 5 \(\upmu\)m intervals. The size of the MOSFETs, and their number, and location in a chip are shown in Table 1. The test chip has an area of 5.5 mm \(\times\) 14 mm. The gate insulator is formed by pyrogenic oxidation and is 5.8 nm thick. A schematic block diagram of a test pattern is shown in Figure 3a[35; 37; 39; 40]. This is composed of MOSFETs measured in arrayed unit cells, vertical and horizontal shift registers for addressing measured MOSFETs, MOSFETs located on each column for current control of measured MOSFET, analog memories for storing the source voltage of the measured MOSFETs within one line, and a source follower circuit for amplifying the output signal. The drain (V\({}_{\text{D}}\)) and gate (V\({}_{\text{G}}\)) voltage in measured MOSFETs and the gate voltage applied to current source MOSFETs (V\({}_{\text{REF}}\)) are supplied from the external voltage source simultaneously. V\({}_{\text{DD}}\) and V\({}_{\text{SS}}\) are the supply voltages in the peripheral circuits and ground voltage, respectively. The measured MOSFET and current source transistor construct a source follower circuit using a select transistor. This test structure uses simple peripheral circuits. Therefore, it can be used to evaluate various MOSFETs with varying gate lengths, gate widths, gate insulator films, thicknesses, and other characteristics. Figure 3b shows the circuit schematic of a unit cell and current source transistor in Figure 1, which is the principle of this measurement. A unit cell is constructed with a measured MOSFET and a select transistor. When the current source transistor operates at a saturation region, IREF is independent of the voltage between the source and drain in the current source transistor (V\({}_{\text{out}}\)). When the gate bias of the select transistor (\(\Phi_{\text{x}}\)) is applied from a vertical shift register, IREF flows into the measured MOSFET. The output voltage (V\({}_{\text{out}}\)) is indicated as follows. \[\text{V}_{\text{gs}}=\text{V}_{\text{G}}-\text{V}_{\text{out}}-\text{IREF}. \text{R}_{\text{select}}\approx\text{V}_{\text{G}}-\text{V}_{\text{out}} \tag{10}\]  
where R\({}_{\text{select}}\) is the channel resistance of the select switch transistor. The select transistor must be operated in the linear region to have sufficient high channel conductivity compared with the measured MOSFET, and then, IREF.R\({}_{\text{select}}\) can be neglected. The output signal can be obtained as a source voltage for each measured MOSFET by shift register scanning, and then 1.2 million MOSFETs can be measured within approximately 0.7 s. The electrical characteristics of the measured MOSFETs can be observed as the V\({}_{\text{gs}}\) included in the output voltage V\({}_{\text{out}}\) (Figure 3b). In this frame measurement mode, each MOSFET can be measured every 0.7 s. This test pattern has another measurement mode, which can measure a specific MOSFET every 1 \(\upmu\)s.