## 7 Experimental Results  
To investigate the efficiency of proposed method, we use standard benchmarks from the library [11]. The library includes 48 benchmarks taken from the design practice. The benchmarks are rather simple, but they are very often used by different studies to compare new and known results [26]. The benchmarks are represented in KISS2 format. The characteristics of benchmarks are shown in Table 7.  
We used our CAD tool K2F [26] to translate KISS2 -based files into VHDL-based FSM models. Next, the Active-HDL environment was used to synthesize and simulate FSMs. To get FSM circuits, we used Xilinx CAD tool Vivado [27]. The FPGA chip XC7 VX690 TFFG1761-2 by Vertex-7 [28] was used as a target platform. The chip includes LUTs with 6 inputs and EMBs with configurations from \(\langle 15,1\rangle\) till \(\langle 9,64\rangle\). We presume that only a single EMB is available to implement an FSM circuit. As follows from Table 7, the condition (7) takes place for 33 benchmark FSMs (it is around 68% from all benchmarks). Therefore, it is necessary only a single EMB to implement an FSM circuit for these benchmarks. We mark this situation by the sign \"+\" in the column \"EMB\" of Table 7. Also, we show in this column pairs \(\langle S_{A},t_{F}\rangle\) corresponding to the configuration required to implement the circuit with a single EMB. The further research was conducted for these 15 benchmarks. Three discussed methods (\(U_{1}\), \(U_{3}\) and \(U_{4}\)) were taken to compare with our approach (\(U_{5}\)). The results are shown in Table 8 (the number of LUTs in FSM circuits), Table 9 (the operating frequency) and Table 10 (the consumed energy). To design FSM \(U_{1}\), a single EMB was used to implement a part of FSM circuit. We do not know which part of a circuit was implemented as an EMB. It is up to Vivado and cannot be directly specified by a designer. Tables 8-10 are organized in the same order. The rows are marked by the names of benchmarks, the columns by design methods. The rows \"Total\" include results of summation for values from corresponding columns. The summarized characteristics of \(U_{5}\)-based FSMs are taken as 100%. The rows \"Percentage\" show the percentage of summarized characteristics respectively to \(U_{5}\)-based benchmarks. To design all circuits, we use the mode AUTO of Vivado. As follows from Table 8, the \(U_{5}\)-based FSMs require fewer LUTs than their counterparts based on other FSM models. There is the following economy: (1) 23% regarding \(U_{1}\); (2) 4% regarding \(U_{3}\); (3) 45% regarding \(U_{4}\). Therefore, for these benchmarks the \(U_{4}\)-based FSMs require the largest number of LUTs. It is connected with the fact that the condition (20) is violated for all considered \(U_{4}\)-based benchmarks. It results in multi-level circuits implementing functions (17) and (18). \begin{table}
\begin{tabular}{c c c c c c} \hline \hline \(K(a_{m})\) & \(X\) & \(Z\) & \(V\) & \(\Phi_{E}\) & \(q\) \\ \hline \(T_{1}T_{2}T_{3}T_{4}\) & \(x_{1}x_{2}x_{3}x_{4}x_{5}x_{6}x_{7}\) & \(z_{1}z_{2}z_{3}\) & \(v_{1}v_{2}\) & \(D_{2}D_{4}\) & \\ \hline
0000 & 0000000 & 000 & 01 & 01 & 1 \\ \hline
0000 & 0000001 & 000 & 01 & 01 & 2 \\ \hline
0000 & 0000010 & 000 & 01 & 01 & 3 \\ \hline
0000 & 0000011 & 000 & 01 & 01 & 4 \\ \hline
0000 & 0000100 & 000 & 01 & 01 & 5 \\ \hline
0000 & 0000101 & 000 & 01 & 01 & 6 \\ \hline
0000 & 0000110 & 000 & 01 & 01 & 7 \\ \hline
0000 & 0000111 & 000 & 01 & 01 & 8 \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Part of table of EMB of Mealy FSM \(U_{5}(S_{1})\)