## 1 Introduction
A simpler approach was proposed in [29], wherein a code density test was used to calibrate the delay cell, and the conversion output bit was adjusted to improve differential non-linearity (DNL) and integral nonlinearity (INL) values. Nonetheless, that nonlinearity correction was still processed in the same manner as an off-line program-based correction. In [30], the auto-calibration circuit was implemented in a single FPGA; however, the calibration was only run when the FPGA was started. This underlines the importance of developing a straightforward system that can be used to implement run-time corrections to resist environmental effects. In [31], the authors presented a dual-phase tapped delay line with on-the-fly calibration, implemented on a 40-nm FPGA. The results demonstrated that the characteristics of the delay cell tend to change at different temperatures. During a temperature shift from 10-50 \({}^{\circ}\)C, their TDC with on-the-fly calibration maintained a 12.8-ps root-mean-squared (RMS) standard uncertainty [31]. Several works have presented delay cells that are sensitive to environmental changes, especially temperature effects [13; 14; 16; 19; 23; 24; 30; 31]. Moreover, a comparison is listed in Table 1, which presents the performance of the proposed DDL-TDC compared with existing works. \begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**Method**} & \multirow{2}{*}{**Structure**} & \multirow{2}{*}{**FPGA**} & \multicolumn{1}{c}{**Dynamic**} & **RMS** & **LSB** & **DNL** & **INL** & **Calibration** \\  & & & **Range** & **(ps)** & **(ps)** & **(_LSB_)** & **(_LSB_)** & **Method** \\ \hline
[13; 14] & VDL & pASIC (0.65 \(\upmu\)m) & 43 s & 129 & 200 & \([-0.47,0.44]\) & \([-0.2,1.28]\) & Off-line \\
[16] & TDL & Virtex-5 (65 nm) & 50 ns & 24.2 & 17 & \([-1.00,3.55]\) & \([-2.99,2.58]\) & Off-line \\
[23] & TDL & UltraScal (20 nm) & 2 ns \({}^{*}\) & 4.2 & 3.29 & — & \([-\,,.2]\) & Off-line \\
[25] & TDL & Virtex-5 (65 nm) & 42 s & 20 & 2.5 & — & — & Off-line \\
[28] & TDL & Virtex-5 (65 nm) & 6 ns \({}^{*}\) & 28.9 & 50 & \([-0.47,0.62]\) & \([-0.87,0.68]\) & Off-line \\
[29] & TDL & Virtex-5 (65 nm) & 6 ns \({}^{*}\) & – & 60 & \([-0.54,0.24]\) & \([-0.66,0.65]\) & Off-line \\
[30] & TDL & Virtex-5 (65 nm) & 6 ns \({}^{*}\) & – & 46.9 & \(-0.68,1.04]\) & \([-4.27,2.27]\) & Real-time \({}^{*}\) \\
[31] & TDL & Virtex-6 (40 nm) & 1.6 ns \({}^{*}\) & 12.8 & 10 & \([-1.00,1.91]\) & \([-2.20,3.93]\) & Real-time \\ This Work & TDL & Virtex-5 (65 nm) & 6 ns \({}^{*}\) & 32 & 46.9 & \([-0.64,0.92]\) & \([-7.12,4.18]\) & Real-time \\ \hline \hline \end{tabular}  
* VDL: Vernerideraly line; TDL: tapped delay line; FPGA: Field-Programmable-Gate-Array; RMS: root-mean-squared; LSB: least significant bit; DNL: differential non-linearity; INL: integral nonlinearity.
* Only calibrate at the start of the TDC. \({}^{*}\) The dynamic range for the fine time counter.  
\end{table} 
Table 1: Comparison with FPGA-based TDCs. LSB, least significant bit. This study proposes a novel architecture that employs two TDLs for an FPGA-based TDC, referred to as a dual delay line (DDL) TDC. This architecture can be implemented within the calibration circuit of an FPGA chip to enable calibration operations in real time. A finite state machine (FSM) is used to manage both the calibration delay line and the conversion delay line, which allows (1) nonuniform delay cells to be calibrated and (2) time differences to be converted based on data held in calibration mapping memory. Experimental results demonstrated the superiority of the proposed DDL-TDC over conventional TDL-TDCs in terms of time linearity and maximum INL and DNL values, despite variations in temperature. This makes the proposed DDL-TDC highly robust for the measurement of time differences in a broad range of external environments. The remainder of this paper is organized as follows. The proposed FPGA-based DDL-TDC is outlined in Section 2. Details concerning the TDL-TDC, FPGA platforms, and DNL calibration circuits are presented in Section 2.