# Soft Error-Tolerant and Highly Stable Low-Power SRAM for Satellite Applications
## 2 Proposed RHSP16T Cell
### Soft-Error Recovery Analysis  
This subsection explains the characteristics of the proposed cell. A node is considered sensitive when it is affected by SEUs [3]. Generally, PMOS and NMOS transistors are known to induce positive and negative transient pulses, respectively [16]. For instance, in the case of PMOS, positive transient pulses can occur during transitions from '0' to '1' or from '1' to '1'. However, if the datum stored at the node is '1', the node retains its state as '1', even if a positive transient pulse is induced. Therefore, for PMOS, only the  
Figure 2: The layout of the proposed RHSP16T cell. positive transient pulse during the transition from '0' to '1' needs to be considered. In contrast, in the case of NMOS, negative transient pulses can occur during transitions from '1' to '0' or from '0' to '0'. However, if the datum stored at the node is '0', the node retains its state as '0', even if a negative transient pulse is induced. Thus, for NMOS, only the negative transient pulse during the transition from '0' to '0' needs to be considered. In summary, nodes storing '1' and surrounded by PMOS transistors and nodes storing '0' and surrounded by NMOS transistors can be regarded as insensitive because only positive transient pulses and negative transient pulses, respectively, can occur in these nodes. Given the initial state of '1' for the proposed 16T cell, the storage node QB starts with a value of '0' and is surrounded exclusively by NMOS transistors. Hence, the only possible transient state when an SEU occurs is '0'\(\rightarrow\)'0'. Similarly, the internal node S1 has an initial value of '1' and is surrounded only by PMOS transistors, resulting in the possible transient state of '1'\(\rightarrow\)'1' during an SEU. Therefore, for the assumed initial state, nodes QB and S1 can be considered insensitive, while Q and S0 are sensitive nodes. Waveforms for soft-error recovery and the fundamental hold/read/write operations of the proposed RHSP16T cell are shown in Figure 3.  
(1) SEU at node Q: When an SEU occurs at node Q, the state of Q changes from '1' to '0'. This transition turns off transistor N4 and activates transistors P4 and P7. As a result, transistors P2 and N3 will remain off, which leads to nodes QB and S0 entering a high-impedance state. In the high-impedance state, they are disconnected from both the pull-up and pull-down paths, typically meaning their state remains unaffected [3]. Therefore, nodes QB and S0 will retain their initial state of '0'. Since QB and S0 maintain their initial state, transistor N7 will stay off while transistor P6 will remain on. This setup allows node S1 to be pulled up to VDD through the path 'S1-P6-VDD', maintaining its initial state of '1'. With nodes QB, S0, and S1 remaining stable in their initial states, node  
Figure 3: Comprehensive waveforms for soft-error recovery and the fundamental hold/read/write operations of the proposed RHSP16T cell. Q, affected by the SEU, can be restored to its initial state of '1' by being pulled up to VDD through the path 'Q-N5-P5-VDD'. (2) SEU at node S0: When an SEU flips S0 from '0' to '1', it causes transistor N3 to turn on and transistor P6 to turn off. However, since transistors P7 and N7 remain off, node S1 will enter a high-impedance state, allowing it to maintain its initial value of '1'. As node S1 holds its initial state, transistor N5 remains on, which allows node Q to be pulled up to VDD through the path 'Q-N5-P5-VDD', thus retaining its initial state of '1'. For node QB, although the activation of transistor N3 will occur due to the flip of S0, the initial state of node Q will keep transistor P4 off, disconnecting QB from the pull-up path. Therefore, node QB will maintain its initial state of '0' as it is pulled down to GND through the path 'QB-N4-GND'. Since nodes Q, QB, and S1 are not directly affected by the SEU and retain their initial states, node S0, impacted by the SEU, can be restored to its initial state of '0' by being pulled down to GND through the path 'S0-P3-N2-GND'.