## 3 Study of the Communication System
### Experimental Setup
The digital white noise here emulates the averaged real noises in the wireless transmission channel which allows us to perform series of uniformed noise impact experimental measurements required for BER analysis. For AWGN generation, a model provided by MathWorks, \"HDL Implementation of AWGN Generator\" [26], was used with slight modifications (such as data bus width adjustments and changing complex output into real). It provides AWGN output for various SNR input values relative to 1 W (0 dBW) signal power with 0.1 dB step. Real SNR for the experimental data is corrected in accordance with the average power of the input FM-ACSK signal (\(-\)12.1112642 dBW) and its bandwidth (1.72 MHz) relative to the Nyquist frequency (25 MHz). SNR is controlled in real time using onboard switches and buttons, which allow us to select one of the 127 pre-mapped SNR states, or turn off the noise addition to the signal. Usage of 14-bit signed fixed point data bus with 12 fractional bits on both input and output of AWGN Controller implies limitation on SNR values that are too low, as the noise overflows the numeric range that this format can represent; thus, such low values were not used in experimental tests. BER controller unit processes received data bits and counts bit errors. It is identical to the transmitter's 16-bit LFSR pseudorandom sequence module, as well as two simple Linear Shift Registers (LSRs): 16-bit LSR that takes input from LFSR output and 32-bit LSR that takes input from FM-ACSK receiver output (see Figure 12). When received data sequence, uploaded to 32-bit LSR, exactly matches known pre-loaded 32-bit sequence key in the 16-bit LFSR and 16-bit LSR taken together, BER controller's state switches from \"INITIAL\" to \"LOCKED\". It indicates this event by lighting up an LED on the development board, and enables the remaining two shift registers, after which LFSR begins to continuously  
Figure 11: Simplified diagram of FM-ACSK communication system FPGA prototype overall experimental setup. produce the next values of the pseudorandom sequence. From this moment, two counters are activated: one counts bit errors, while another counts the amount of received bits. Values of these counters are later used for BER value estimation. Bit error fact is determined by comparing internally generated pseudorandom sequence bit values with received bit values. The BER controller module also has a \"soft\" reset signal input, attached to an onboard button key (separately from global FPGA \"hard\" reset signal), which can be used to clear counters and reset BER controller to the \"INITIAL\" state. It is notable that this controller will only recognize received 32-bit key sequence as valid if no bit detection errors occurred during the reception of key bits, which makes the locking hard to achieve at lower SNRs. If any bit errors occurred during the first key reception attempt, locking with higher probability may happen on one of the next attempts, as the whole pseudorandom bit sequence is cyclic and repeats after \(2^{16}\)\(-\)\(1\) = 65,535 values, which takes 65,535 \(\times\) Tb/Fs = 65,535 \(\times\) 8192/(50 \(\times\) 10\({}^{6}\)) = 10.737 s on FPGA. This cycle time being relatively short is one of the reasons for choosing LFSR to be 16 bits long. However, the key length of 32 bits was selected mainly to reduce probability of random noise input decoding as a valid key. For 16-bit key, such probability (assuming noise input generates statistically equal number of zeros and ones) is (\(1\)\(-\)\(0.5\))\({}^{16}\) = 1.526 \(\times\) 10\({}^{-5}\), but for 32-bit key, it is (\(1\)\(-\)\(0.5\))\({}^{32}\) = 2.328 \(\times\) 10\({}^{-10}\). Another reason for choosing the 32-bit key over the 16-bit one is the key correlation statistics with the whole pseudorandom sequence. For the 16-bit keys, all 16 bits fully correlate with the pseudo-random sequence only once (as it should be), but 15 of 16 key bits will correlate 16 times, and 14 of 16 key bits will correlate 120 times.