# 25-34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver
## 2 Design of the Single-Pole, Double-Throw (SPDT) Switch  
Figure 2 shows the block diagram of the SPDT, which is composed of two switch cores, isolation enhancement (IE) inductors, \(L_{DS}\) to cancel out the parasitic capacitances of the switch cores, three impedance matching circuits for the RX, TX, and ANT ports, and a switch selector. Two types of switch cores were designed: The first switch core employs cross-biasing (CB) control with a single positive supply (\(V_{DD}\)) and ground voltage (0 V). The gate voltage is defined as \(V_{C}\), and the drain and source voltage is defined as \(\overline{V_{C}}\), as shown in Figure 3a. Since \(\overline{V_{C}}\) varies according to the state of the switch controls \(\mathbb{S}_{1}\) and \(\mathbb{S}_{0}\), direct current (DC)-blocking capacitors, \(C_{B}\), are added to the drain and source of the transistor. The other switch core uses dual supply biasing (DSB) control with positive and negative supply voltages (\(V_{DD}\), \(-V_{NN}\)), as shown in Figure 3b. These supply voltages control only the gate voltage, \(V_{C}\), while the drain and source are grounded, i.e., \(V_{S,D}\) = 0 V. The negative supply voltage is generated by an internal negative voltage generator (NVG). Figure 1: Block diagram of the beamforming transceiver. BB: baseband; LO: local oscillator; PS: phase shifters; PA: power amplifier; LNA: low-noise amplifier; SPDT: single-pole, double-throw switch. The CB technique is to control gate and drain/source voltages simultaneously, by reversing their sign, to turn the switch on or off. The gate to drain/source voltage, \(V_{GD,S}\) becomes \(V_{DD}\) in the on state, and \(-V_{DD}\) in the off state. This negative \(V_{GD,S}\) can increase the TX-RX isolation, because the parasitic channel capacitances are reduced, in comparison to a normal biasing (NB) where \(V_{GD,S}=0\) V in the off state, due to the fixed drain and source voltage, i.e., \(V_{D,S}=0\) V. With the DSB technique, the drain and source voltages are fixed to 0 V, as with the NB technique. However, by applying \(V_{DD}\) in the on state and \(-V_{NN}\) in the off state, a negative \(V_{GD,S}\) is applied, as in the CB technique. Thus, high TX-RX isolation is achieved. Since the DC-voltages of the drain and source are fixed to 0 V, no DC-blocking capacitors are required. All the deep-N-well (DNW) nodes are tied to \(V_{DD}\), and the substrate node is connected to 0 V. The lowest voltage is good in terms of the power linearity [18]. Thus, the body biases of the CB switch are set to 0 V, and the body biases for the DSB switch are set to \(-V_{NN}\). The substrate resistance of the CMOS process is as small as a few ohms. The noise and interference between transistors occur through the substrate, resulting in a decrease in signal-to-noise ratio (SNR). To reduce this effect, the P-type body of the transistor is separated to an N-type silicon layer, which is called deep-N-well (DNW), as shown in Figure 4. The substrate of the transistor can be modeled as a P-N-P diode with a triple-well structure. In addition, the junction of the drain/source and the body can also be modeled as a diode. In Figures 3 and 4, \(\mathrm{J_{DB}}\) and \(\mathrm{J_{SB}}\) are the junction diodes between the drain to body, and source to body, respectively. \(\mathrm{J_{B-DNW}}\) is the junction diode between the body and DNW, and \(\mathrm{J_{DNW-SUB}}\) is the junction diode between the DNW and chip substrate, respectively. If the voltage applied to the P-type silicon of the diode is higher than the voltage applied to the N-type silicon, it is conducted. However, in the opposite case, a current does not flow through the diode. It can be modeled as a reverse biased diode and a parallel parasitic capacitor. In Figures 3 and 4,  
Figure 3: Schematics of the switch cores with (**a**) cross-biasing (CB) control and (**b**) a dual-supply biasing (DSB) control. Figure 2: Block diagram of the proposed SPDT switch. ANT: antenna; RX: receiver; TX: transmitter; SW: switch.