# Thermal Mapping of Power Semiconductors in H-Bridge Circuit +
## 1 Introduction  
Reliability and lifetime prediction of power converters have been a major research topic in the last few decades, especially for locomotives, high-power drives, electric vehicles, and renewable energy applications [1; 2; 3]. According to an industrial survey presented in [4], power semiconductor failures are a dominant concern for the reliability of power converters. The main failures in power semiconductors are caused by thermo-mechanical fatigue, and thus thermal analysis of the power converter is essential for reliability testing in various applications. Temperature cycling and power cycling are the two most common thermal acceleration approaches used in assessing the reliability of the power device [5]. In temperature cycling, components are periodically moved between cooling and heating chambers, where components are passively heated up. During the power cycling, components are actively heated up by losses produced in the power semiconductor and cooled down with the aid of cooling equipment. For the dc power cycling, a constant dc current for a continuous period of time is considered in a dc circuit, which is simple and easy for monitoring parameters. A specified load current is periodically applied to the insulated gate bipolar transistor (IGBT), and the lower and higher temperature limits are the parameters to be set initially by means of adjusting the loading current, turn-on and turn-off period and cooling system [6; 7]. This is one of the standard testing circuits, which ensures faster changes in temperature due to the higher power losses. However, only the conduction loss is generated in this method, which is inconsistent with the properties of these fast-switching power devices. For the ac power cycling, a Pulse-Width Modulation (PWM) switching sequence is applied for a time until the IGBT rises to the maximum temperature, and the device is switched off until it coolsdown to the minimum temperature [8; 9; 10]. As described in [10], a motor drive test circuit is established, and a short period of overload current is applied to generate the high-temperature variation. Although the failures are accelerated and occur in a low testing duration, the test is not as cost-effective, since the fatigue issues of the motor and other electrical components exist simultaneously. The back-to-back inverter configuration is proposed with an inductor in order to emulate the traction application [11]. With this arrangement, the system current is made to circulate between the two inverters so that each can operate at their full power. Only the conduction and switching losses of the power devices are provided by the dc power supply. Even though the standard dc and ac testing methods can achieve the same thermal stress of the power device, the heating source is different due to the fact that the switching loss only exists in ac power cycling, which may result in various failure mechanisms of the power device. As the ac power cycling mimics realistic conditions of the power devices and emulates various applications by reconfiguring control objectives of the testing and loading legs [12], some research efforts are devoted to the H-bridge testing circuit [13; 14; 15; 16; 17; 18]. In the real application, as the power device is normally selected with around two times the current margin, it makes the power device quite robust and will take years of time before the wear-out aging occurs. In contrast, if the H-bridge circuit is selected, the loading current through the device can be equal or even higher than the maximum loading current, which accelerates device aging much sooner. However, the operation principle of this circuit has not been well described. Moreover, the relationship between the loading condition and the junction temperature of the power semiconductor is not accurately established. In order to fill this research gap, the loss dissipation and thermal stress of the power devices are investigated in detail in this paper.