# A Reconfigurable Framework for Hybrid Quantum-Classical Computing
## 4 Experimental Results
### Training, Testing, and Validation  
The training loop implements a hybrid quantum-classical optimization strategy, iteratively refining quantum circuit parameters to minimize the classification error. For the conducted experiments, a dataset comprising 500 samples was used and pre-processed according to the pipeline described earlier. Each quantum circuit configuration, ranging from eight to fifteen qubits, is trained using a learning rate of 0.01, a batch size of 32, and for a total of two epochs. The circuit initialization involves Hadamard gates, followed by parameterized rotations for encoding the input data. Subsequent quantum layers incorporate parameterized RX, RY, and RZ rotations combined with CNOT gates to facilitate entanglement between neighboring qubits. Quantum circuit simulations during the forward passes are executed using Qiskit's Statevector simulator, while the FPGA processing pipeline handles gradient calculations and parameter updates. For comparison, a baseline implementation of the gradient calculations and parameter updates were performed on the CPU. Performance metrics such as execution time, accuracy, and FPGA-driven speedup were recorded from the two implementations.  
The results in Table 2 demonstrate significant performance gains achieved by integrating FPGA processing for gradient descent and loss calculation with QPU simulations. Columns 2 and 3 in Table 2 represent the timings and accuracy for the baseline implementation on the CPU, while columns 4 and 5 represent the timings and accuracy for the FPGA implementation. As the number of qubits increases, the CPU execution time grows, reaching 3.34 s for 15 qubits, while the FPGA execution time remains consistently low, with a maximum of 0.4 s, as shown in Figure 8. This results in a substantial speedup, increasing from 5.11\(\times\) for eight qubits to 8.35\(\times\) for fifteen qubits, highlighting the efficiency of FPGA acceleration, especially for larger computations, as shown in Figure 9. Additionally, the accuracy of the CPU-only approach declines as the number of qubits increases, dropping from 99% for eight qubits to 76% for fifteen qubits. In contrast, the FPGA system maintainshigher or comparable accuracy, achieving 99% in multiple cases. These findings indicate that FPGA acceleration not only enhances computational speedup but can also improve accuracy in certain scenarios, making it a powerful tool for hybrid computing environments that demand both efficiency and precision.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**No. of Qubits** & **CPU Time (s)** & **CPU Accuracy** & **FPGA Time (s)** & **FPGA Accuracy** & **Speedup** \\ \hline
8 & 1.38 & 99\% & 0.27 & 98\% & 5.11 \\ \hline
9 & 1.53 & 90\% & 0.27 & 95\% & 5.67 \\ \hline
10 & 1.67 & 86\% & 0.30 & 99\% & 5.57 \\ \hline
11 & 1.86 & 98\% & 0.34 & 99\% & 5.47 \\ \hline
12 & 2.03 & 91\% & 0.34 & 93\% & 5.97 \\ \hline
13 & 2.17 & 88\% & 0.36 & 96\% & 6.03 \\ \hline
14 & 3.12 & 78\% & 0.4 & 99\% & 7.8 \\ \hline
15 & 3.34 & 76\% & 0.4 & 96\% & 8.35 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Gradient descent and loss calculation results with CPU vs. FPGA execution times and accuracy.  
Figure 8: Execution times for gradient descent and loss calculation (CPU and FPGA).  
Figure 9: FPGA speedup with regard to CPU.