## 3 Circuit Implementation
### Linearity Enhanced Method  
Figure 6 shows the simplified schematic of power cells and Table 1 shows the power cell transistor size. To ensure the flexibility of power control, the power cells are designed to be reconfigurable and divided into five units. Each cell uses a cascode structure and can be individually biased, which enables dynamic control by the power controller circuit as well as static control. In the common gate-transistors, thick oxide is used for high supply voltage, while thin oxide is used in the common-source transistors to provide high gain. Additionally, a parallel PMOS at the input is added to improve linearity. Figure 4: Simulated power detector output voltage. Figure 5: Simulated output control signal. In general, power amplifiers (PAs) are biased to Class AB for a compromise between linearity and efficiency. In this design, the second stage core devices are divided into five groups that are biased to different voltages. When all the groups are turned on, some groups are biased to Class AB but closer to Class A, while others are biased to Class AB but closer to Class B. The ratio of these two groups is 2:3, which achieves a relatively flat gm over a wider range of input voltage, thus obtaining better linearity at the expense of small signal voltage gain. Figure 7 illustrates the overall linearity, which is greatly improved. Figure 8 shows the simulated comparison of the output power between with- and without-gm linearization. The results show that with the help of gm linearization, the PA has a higher OP1 dB compression point, indicating a higher linearity. \begin{table}
\begin{tabular}{c c} \hline \hline  & **W/L** \\ \hline Common Source & 800 \(\upmu\)m \(\times\) 2/100 n \\ Common Gate & 800 \(\upmu\)m \(\times\) 2/500 n \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Power Cell Transistor Size. Figure 6: Simplified schematic of the power cells. Figure 7: Simulated Gm for Class A and Class B devices, and overall Gm. Additionally, the PA's IMD3 also can be improved by gm linearization. To explain this more clearly, we review the regeneration process of the IMD3 [41]. The drain current(id), the most significant non-linear distortion source, can be expanded in the following Taylor series,  
\[i_{d}=g_{m}V_{gs^{+}}+g_{d}V_{ds}+g_{m2}V_{gs^{2}}^{2}+g_{d2}V_{ds}^{2}+g_{md}V_ {gs}V_{ds}+g_{m3}V_{gs^{+}}^{3}+\cdots\]  
The gterms represent the transconductance, drain conductance, and cross terms. \(R_{L}(\omega_{L})\) assumes the output load impedance at the fundamental frequency. The input signal \(V_{in}\) is given by  
\[V_{in}=A[\cos(\omega_{1}t)+\cos(\omega_{2}t)]\]  
Thus, the IMD3 terms can be derived as  
\[V_{ds}(2\omega_{2}-\omega_{1}) \approx R_{L}(\omega_{L})[\tfrac{3}{4}g_{m3}A^{3}+\tfrac{1}{2}Z_{L }(\omega_{2}-\omega_{1})g_{m2}g_{md}A^{3}+\tfrac{1}{4}Z_{L}(2\omega_{c})g_{m2 }g_{md}A^{3}\] \[V_{ds}(2\omega_{1}-\omega_{2}) \approx R_{L}(\omega_{L})[\tfrac{3}{4}g_{m3}A^{3}+\tfrac{1}{2}Z_{L }(\omega_{1}-\omega_{2})g_{m2}g_{md}A^{3}+\tfrac{1}{4}Z_{L}(2\omega_{c})g_{m2 }g_{md}A^{3}\]  
where \(\omega_{c}=\frac{(\omega_{1}+\omega_{2})}{2}\), \(Z_{L}\) is the frequency-dependent load impedance, and \(Z_{L}=R_{L}(\omega_{L})\) at the fundamental frequency. It can be seen that IMD3 has a great relationship with \(g_{m3}\). Figure 9 shows the simulated \(g_{m3}\) versus bias voltage. Therefore, low \(g_{m3}\) can be realized using a combination of two different bias voltages. Figure 10 shows the comparison of IMD3 between with- and without-gm linearization, indicating better IMD3. Figure 8: Simulated comparison of the output power. However, since the power cells are all biased to class AB, when the input signal is large enough, the device will constantly turn on and off, causing the gate capacitance of NMOS Cgg to change dramatically and resulting in severe AM-AM and AM-PM distortion, thereby deteriorating the overall linearity.