# Research on Clock Synchronization of Data Acquisition Based on NoC
## 5 Clock Synchronization Verification of NoC Data Acquisition  
The data acquisition system operates as follows: Firstly, after the system is powered up and reset, the master-slave clocks are synchronized using Precision Time Protocol (PTP). The offset between the master and slave clocks is calculated, and the local clock of the slave is adjusted by subtracting this offset. Once coarse correction is completed, the offset_shift_finish signal is raised. Subsequently, this signal serves as the trigger for phase detection of the master-slave clocks within the slave node, using DDMTD. The phase difference is determined, and each slave clock's required phase shift is calculated based on the interleaving sampling interval, then applied using Xilinx's MMCM to achieve fine synchronization of the master-slave clocks. Once completed, the phase_shift_flag signal is raised. Finally, the synchronized clocks are used as the sampling clocks for the ADCs, allowing for interleaved sampling across multiple ADCs. The resource network interface receives the collected data from the ADCs, packages it into microchip format, and sends it to the data acquisition router. After handshaking communication between the data acquisition router and the data transmission router, the data are forwarded to the transmission router, and then, sent to the host computer via high-speed transmission interfaces.  
This article utilizes Xilinx's A7 series FPGA chip XC7A200T to implement the system's logic functions, which features 215,360 logic cells, 13,140 Kb of RAM, 10 clock management tiles (CMTs), and 16 high-speed transceivers (GTP) with speeds of up to 6.6 Gbps. Vivado development tools are used for logic design, combined with ModelSim simulation tools to verify the correctness of the logic code. Logic code is employed to simulate the data generated by the ADC chip, hence the overall system simulation is as depicted in Figures 13-15.  
DDMTD is then used to determine the phase relationship between the master and slave clocks, and the phase of the slave clock is shifted by the dynamic phase shift function of the clock phase-locked loop. Once the phase shifts of all slave clocks are completed, the NoC-based TI-ADC will start, as shown in Figure 14.  
In this paper, six sampling channels are interwoven in time, and the ideal interval between adjacent sampling channels at a 250 MHz sampling clock is 0.667 ns. The error in the adjacent sampling interval after clock synchronization is shown in Figure 15. According to the results, the average absolute error in sampling intervals is 7 ps.  
\[T_{interval}=\frac{1}{Nf_{sampling}} \tag{15}\]  
\[T_{average}=\frac{\sum_{i=1}^{n}\left|T_{i}-T_{interval}\right|}{n} \tag{16}\]  
Next, by changing the initial phases of the master and slave clocks, the tests are repeated 10 times. The average absolute errors of the adjacent sampling interval after clock synchronization are shown in Figure 16.  
Figure 14: Clock synchronization function verification.  
Figure 13: PTP verifies synchronization of the slave clock.  
Figure 15: Error analysis of adjacent sampling channels.  
In [15], using a basic WR network structure of one master and one slave, the test synchronization accuracy is not more than 200 ps, and the synchronization accuracy reaches 21 ps. In this paper, the improved White Rabbit protocol is applied to an NoC's clock synchronization for data acquisition, which can also achieve the same clock synchronization accuracy and solve the problem of clock synchronization of TI-ADC. The feasibility of time-interleaved data acquisition using six ADCs with a sampling rate of 250 MHz and a resolution of 8 bits in the NoC system was verified through simulation. Under the architecture of the NoC system designed in this paper, the total sampling rate of data acquisition with the same six sampling points is 1.5 Gbps, far exceeding the 150 Mbps in [7]. The higher the clock synchronization accuracy, the higher the achievable sampling rate.