## 6 Conclusions  
The aim of this paper was to demonstrate the efficiency of the implementation (measured by the number of logic resources used and dynamic power consumption) of the TMR mitigation circuit test environment. A novel element was the introduction of an 'element of randomness' into this environment through the use of the PRBS register in the error injectors. The testing performed revealed a number of observations.  
The first observation is the issue of the synthesis of mitigation circuits. It is clear that the synthesis algorithms are focused on circuit optimisation, which, in extreme cases, can limit the robustness of the circuit to radiation errors (e.g., sharing logic resources). The second observation concerns the number of resources used by the error injector. It can be seen that in this case, it is inefficient to apply mitigation to small circuits. The last observation concerns dynamic power and shows that the implementation of the test environment does not significantly affect its consumption. All these observations lead to the conclusion that it is worthwhile to implement this environment provided that we have sufficient logic resources in the FPGA.  
The efficient synthesis of mitigation circuits has proven to be of great importance. It is becoming necessary to develop algorithms that, on the one hand, provide suitably efficient logic structures and, on the other hand, do not degrade the mitigation properties of circuits. The authors plan to address the problem of mitigation-oriented synthesis in the future.  
Conceptualisation, M.K. and R.C.; methodology, M.K. and R.C.; software, M.K.; formal analysis, M.K. and R.C.; investigation, M.K. and R.C.; resources, M.K. and R.C.; data curation, M.K.; writing--original draft preparation, M.K. and R.C.; writing--review and editing, M.K. and R.C.; visualisation, M.K. and R.C.; supervision, M.K.; funding acquisition, M.K. and R.C. All authors have read and agreed to the published version of the manuscript.  
Figure 12: Summary results of synthesis in Vivado: for combinational circuits, number of LUT blocks (**a**) and dynamic power value (**b**); for sequential circuits, number of LUT blocks (**c**) and dynamic power value (**d**).  
**Funding:** This research was partially supported by European Space Agency (ESA Contract No. 4000132609/20/NL/FE), and by the Polish Ministry of Science and Higher Education funding for statutory activities.  
**Institutional Review Board Statement:** Not applicable.  
**Informed Consent Statement:** Not applicable.  
**Data Availability Statement:** The original contributions presented in the study are included in the article, further inquiries can be directed to the corresponding author.  
**Acknowledgments:** Thank you for the invitation from Academic editor.  
**Conflicts of Interest:** Authors [PERSON] and [PERSON] were employed by the company KP Labs. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.  
**Abbreviations**  
The following abbreviations are used in this manuscript:  
AXI Advanced eXtensible Interface  
AXIS Advanced eXtensible Interface; Stream protocol  
CME Coronal Mass Ejection  
CPLD Complex Programmable Logic Device  
CLB Configurable Logic Block  
ECC Error Checking and Correction  
ESA European Space Agency  
FPGA Field Programmable Gate Arrays  
HDL Hardware Description Language  
LUT Look-up Table  
PAL Programmable Array Block  
PRBS Pseudo-Random Bit Sequence  
SEB Single-event burnout  
SEE Single-Event Effect  
SEFI Single-event function interrupts  
SEGR Single-event gate rupture  
SEL Single-event latch-up  
SET Single-event transient  
SEU Single-event upset  
SRAM Static Random-Access Memory  
TMR Triple modular redundancy