## 6 Conclusions  
This study combined FEM simulations and actual fabrication processes to analyze the impact of unnecessary interconnect sections on current conduction in a metal line-via-metal line structure. Simulation results revealed that current density was primarily concentrated in approximately 20% of the interconnect height and along the diagonal edges of the via. Based on this, we hypothesized that optimizing the design of interconnects and via would allow for a reduction in unnecessary interconnect length without significantly affecting current conduction performance. To verify these simulation results, Si-based fabrication processes were conducted, designing various interconnect and via structures and measuring resistance values for comparison with simulation results. Experimental findings indicated that when the interconnect width was reduced below a certain threshold, resistance increased sharply due to process limitations. However, up to a certain point, interconnect width reduction had minimal impact on resistance, demonstrating the feasibility of more compact layouts. A comparison between simulation results and experimental data showed an agreement within an error range of 1-3%, confirming the reliability of the resistance calculation formula derived in this study.  
This research suggests that optimizing interconnect and via structures can reduce unnecessary interconnect sections in integrated circuit design, thereby lowering fabrication costs and minimizing area usage. It also implies that a larger margin for misalignment in the patterning process during interconnect fabrication does not significantly impact current conduction. This finding can serve as a basis for establishing practical process limits in advanced semiconductor patterning, where extreme minimization of process constraints may not always be feasible. Additionally, it highlights the effectiveness of using FEM simulations for design optimization prior to experimental validation. Future studies should consider a wider range of process parameters to enhance the reliability of this approach and explore its applicability beyond silicon to other materials and fabrication technologies. By further refining design models for semiconductor process optimization and providing practical design guidelines, this research is expected to contribute to improving the efficiency of high-density semiconductor circuit design.  
Conceptualization, S.E.K. and S.K.H.; methodology, S.E.K. and S.K.H.; software, S.H.O. and T.Y.H.; validation, S.K.H.; formal analysis, S.H.O., T.Y.H., J.K.P. and S.K.H.; writing--original draft preparation, S.H.O.; writing--review and editing, J.K.P. and S.K.H.; visualization, S.H.O. and T.Y.H.; supervision, S.K.H.; project administration, S.K.H. All authors have read and agreed to the published version of the manuscript.  
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (No. RS-2023-00239657 and No. RS-2024-00440244).  
Not applicable.  
The raw data supporting the conclusions of this article will be made available by the authors upon request.  
The interconnect samples were fabricated using Sputtering System (SRN-110), Spin Coater, Aligner System, and Wet Station, S-FAB at Seoul National University of Science and Technology. The EDA tool was supported by the IC Design Education Center (IDEC), Korea.  
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.