## 5 Case Study  
In order to achieve the smart converter design, it is defined for this case study that the main purpose of the circuit to be designed, is to achieve an efficient 24 [V] to 5 [V] conversion, which is a typical conversion rate application. Therefore, a buck converter topology (as the one shown in Figure 2) is selected for the task.  
Nevertheless, by the fact that a more precise model could lead to a better design in this proposed methodology, some of the parasitic elements from the inductor and capacitor are added into the modeling considerations. Thus, the ideal buck converter scheme from Figure 2, can be redrawn as shown in Figure 7; where the added \(R_{L}\) and \(R_{C}\), are the series parasitic elements of the inductance and capacitance, respectively.  
Table 2 summarizes the initial parameters of the case study converter to be optimized. In the case of [2], the converter design was made through an open-loop model, unlike this case study where a closed-loop system is presented. Nevertheless, it is important to highlight that with the proposed methodology any of the parameters can be taken as optimization goals (even more than one of the parameters).  
However, this optimization example enables the suitability of converters with fixed controllers, for different operating parameters. In other words, this case study takes as inspiration a typical issue in mass production elements, where a certain inductor is out of stock, and this methodology enables to find another inductance that could work even better, than the temporarily unavailable inductor. Additionally, this type of case study could enable the improvement of existing designs. Hence, the closed-loop system follows the blocks diagram shown in Figure 8, where a cascade scheme is presented for the inductance current (\(i_{L}\)) and the output voltage (\(V_{out}\)) parameters.  
\begin{table}
\begin{tabular}{c l l} \hline \hline
**Variable** & **Parameter** & **Value** \\ \hline \(V_{g}\) & Input Voltage & 24 [V] \\ \(f\) & Switching frequency & 100 [kHz] \\ \(L\) & Inductor & 330 [\(\mu\)H] \\ \(R_{L}\) & \(L\) series Resistance & 1.8 [\(\Omega\)] \\ \(C\) & Capacitor & 220 [\(\mu\)F] \\ \(R_{C}\) & \(C\) series Resistance & 40 [m\(\Omega\)] \\ \(R\) & Load resistance & 30–150 [\(\Omega\)] \\ \(P_{out}\) & Output power & 0.167–0.833 [W] \\ \(V_{out}\) & Output voltage & 5 [V] \\ \(i_{out}\) & Output current & 33–167 [mA] \\ \hline \hline \end{tabular}
\end{table}
Table 2: Buck converter initial parameters.  
Figure 7: Buck converter equivalent model with capacitive and inductive parasitic elements.  
In both examples of application (the supercapacitor charger partially designed in [2] and the one presented in this work), the methodology allows selecting an optimal inductance without changing the calibration of the controllers or other circuit elements, which translates into economic benefits and into a viable solution for designers and manufacturers of electronic circuits.  
Then, in Figure 8 can be seen two Proportional Integrative (PI) controllers in cascade, where the first one is tuned to compensate the error from the output voltage, and the second one tuned for the \(i_{L}\) error compensation. In real applications, the output of both controllers has to be converted into the duty cycle, which is latter translated into the control signal for the transistor. Having already described the system to be optimized, the application of the proposed design methodology is presented below.