# Research and Implementation of High-Efficiency and Low-Complexity LDPC Coding Algorithm
## 6 Conclusions  
LDPC codes are highly regarded as linear block codes due to their exceptional coding performance, low decoding complexity, flexible structure, and easy hardware implementation. Consequently, they have become a prominent research topic in the field of channel coding. To address the challenge of high computational complexity in implementing standard encoding algorithms, this study proposes an efficient and low-complexity encoding algorithm through extensive research and analysis of check matrices, building upon the investigation of standard encoding algorithms and recursive iterative encoding algorithms.  
By combining the LLR-BP algorithm with the minimum sum decoding algorithm, we successfully implemented an (1536, 1024) LDPC encoder and decoder with a 2/3 code rate using (6, 2) uniform quantization. The iteration count was set at 8, adhering to the IEEE 802.16e standard. This implementation was tested through software simulation on MATLAB and hardware testing on the Xilinx Zynq7020 FPGA platform. The implementation results obtained from both software simulation and hardware testing demonstrate that when utilizing the minimum sum decoding algorithm in conjunction with BPSK modulation and AWGN channel transmission, the proposed efficient and low-complexity encoding algorithm achieves approximately a 0.25 dB improvement in encoding performance compared to the recursive iterative encoding algorithm. Moreover, it achieves around a 1.25 dB improvement compared to the standard encoding algorithm. These findings further validate the correctness, effectiveness, and feasibility of the proposed algorithm. The experimental results highlight that employing efficient and low-complexity encoding algorithms not only reduces computational complexity and logical delays during the encoder implementation process, but also enhances encoding performance and data transmission reliability. This bears significant theoretical and practical research implications  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Site Type** & **Used** & **Fixed** & **Available** & **Util\%** \\ \hline Slice LUTs * & 36,689 & 0 & 53,200 & 69.00 \\ \hline LUT as Logic & 36,022 & 0 & 53,200 & 68.00 \\ \hline LUT as Memory & 667 & 0 & 17,400 & 4.00 \\ \hline LUT as Distributed RAM & 171 & 0 & & \\ \hline LUT as Shift Register & 496 & 0 & & \\ \hline Slice Registers & 28,536 & 0 & 106,400 & 27.00 \\ \hline Register as Flip Flop & 28,536 & 0 & 106,400 & 27.00 \\ \hline Register as Latch & 0 & 0 & 106,400 & 0.00 \\ \hline F7 Muxes & 2480 & 0 & 26,600 & 9.00 \\ \hline F8 Muxes & 920 & 0 & 13,300 & 7.00 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Coder and decoder resource usage report. * represent The name annotation of logical devices in Xilinx Zynq7020 FPGA hardware resources can be deleted.  
for advancing the widespread application and rapid development of LDPC codes in the realm of digital communication.  
Methodology, X.L., J.G. and Z.L.; Software, Y.X.; Data curation, Y.C. All authors have read and agreed to the published version of the manuscript.  
This research was funded by the National Natural Science Foundation of China under Grant no. 61703060, the National Engineering Research Center for Oil & Gas Drilling Equipment under grant no. 202307, the Sichuan Science and Technology Plan Project (grant nos. 2020 YFS0507, 2021 YFG0361, 2021 YFS0311, 2023 YFS0426).  
The data that support the findings of this study are available from the corresponding author upon reasonable request.  
The authors declare no conflict of interest.