# A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver
###### Abstract  
With the great increases in data transmission rate requirements, analog-to-digital converter (ADC)-based wireline receivers have received more and more attention due to their flexible and powerful equalization capabilities. Considering power consumption, baud-rate Mueller-Muller clock and data recovery (MM-CDR) circuits are widely used in ADC-based wireline receivers since MM-CDR circuits only need one sample signal per unit interval (UI). However, MM-CDR circuits need to set an additional _Vref_ voltage to match the size of the main tap of the channel. If the _Vref_ matching is not appropriate or the signal quality is good as a square wave, MM-CDR circuits cannot accurately lock on to a certain phase and instead drift within a phase range. Therefore, MM-CDR circuits are not as robust and stable as oversampled CDR circuits. In this study, a digital bang-bang clock and data recovery (DBB-CDR) circuit combined with an ADC-based wireline receiver was proposed. The DBB-CDR circuit could eliminate various unstable factors of MM-CDR circuits and achieve fast and robust phase locking without excessively increasing power consumption. A model of the DBB-CDR circuit was combined with an actual 32 GB/s ADC-based wireline receiver, which was implemented in 28 nm CMOS technology to analyze the performance of the DBB-CDR circuit. The simulation results showed that the DBB-CDR circuit could achieve 0.42 Ulpp JTOL@10 MHz, and that the minimum JTOL value was 0.362 Ulpp under a 0.04 UI variance of Gaussian jitter. The area and power consumption of the DBB-CDR circuit were only 64 \(\upmu\)m\({}^{2}\) and 0.02 mW, respectively; and the DBB-CDR circuit could also obtain very stable phase locking and demonstrated a fast frequency offset tracking ability when there was a frequency offset. digital bang-bang phase detector; clock and data recovery; ADC-based wireline receiver 2022113489 10.3390/electronics11213489 10.  
phase detector (MMPD) to determine the best sampling phase of the ADC clocks [6; 7; 8]. The convergence goal of traditional Mueller-Muller clock and data recovery (MM-CDR) circuits is to make the size of the pre-cursor equal to the size of the post-cursor, which requires a reference _Vref_ level to generate the up/down signal. However, MM-CDR circuits face the problem of unstable convergence when the _Vref_ matching is not appropriate, or the signal quality is good as a square wave [9; 10]. [PERSON] et al. [11] proposed a linear model for a Mueller-Muller CDR circuit and used a drift bit width to characterize the influence of the reference _Vref_ level, which showed the phase drift that occurred when the _Vref_ was not set properly through simulations. In order to solve the problem of phase locking not being unique, various structures have been invented. For example, in [12], [PERSON] et al. modified the lock point of an MM-CDR circuit to the unequalized pulse response. In [13], [PERSON] et al. adopted a weight-adjusting sign-sign MM-CDR circuit with a maximum-eye tracking algorithm to make a CDR circuit lock on to the optimal phase that maximized the eye height. However, the power consumption of the additional structure deviated from the original intention of using MM-CDR circuits in ADC-based wireline receivers, which was to reduce power consumption. Therefore, when MM-CDR circuits do not significantly reduce power consumption, the scheme of adopting MM-CDR circuits in ADC-based wireline receivers is not so attractive due to the additional problems that are specific to MMPD, including the requirement for a reasonable _Vref_ under different signal amplitudes and the lack of a linearized MMPD model at the design stage [14]. In this work, we added a partial oversampling system to sample the edges of the signal by interpolating an intermediate phase clock through a time interpolator [15; 16]. This meant that a digital bang-bang phase detector (DBBPD) could be used for phase locking in an ADC-based wireline receiver without excessively increasing its power consumption.