## Results
### Inspection of Sintered Interfaces  
The inspections of sintered interfaces were performed on bare die Si-MOSFETs with a surface of \(2.3\times 2.3\) mm\({}^{2}\) and a TiNiAg backside metallization attached with an in-house developed copper sinter paste to a 1.6 mm thick copper plate with electroless nickel immersion gold (ENIG) surface finish. This thermomechanical set-up was selected to highlight the thermal characteristic of the sintered interface without any thermal low-conductive material, e.g., dielectrics overlapping. Three sinter pastes based on etched brass flakes with different percentages of remaining Zn (weight percentage: 0.7, 3.0, and 6.4) were inspected. All pastes were sintered with the same process parameters. The pastes were stencil-printed with a 75 \(\upmu\)m stencil and predried for 5 min at 120 \({}^{\circ}\)C in air. Afterward, the MOSFETs were placed and sintered for 5 min under 10 MPa bonding pressure for 5 min under nitrogen atmosphere. A detailed description of pastes and process parameters can be found in [51]. A sample with SAC305 solder paste was used as reference. The electrical connection for TTA was realized by an FR4-PCB adapter mounted on the copper sheet with a central opening for the MOSFET. Top contacts of the MOSFET were connected with Al wire bonds to the adapter PCB holding the probing pads for the ATIM. This set-up can be seen in Figure 7. TTA measurements were performed with heating in the saturation region (\(P_{Heat}\) = 10 W) and using \(V_{th}\) as TSP (\(P_{Sense}\) = 0.1 W) for \(t_{Heat}\) = \(t_{Sense}\) = 10 s with the equipment described in [42]. X-ray images and SAM images with a 100 MHz transducer were from top and were taken before wire bonding. Figure 7: Sintered bare die MOSFET on ENIG metallized copper plate with FR4 adapter PCB holding the probing pads for ATIM and Al wire bonds to the MOSFET top contacts. The results of the NDTs for the sintered interconnects are summarized in Figure 8 with X-ray inspection in (X1) to (X3) for qualification of the sintered interconnect being impossible. Even the die edges were hardly visible despite the marking of the upper right and lower left corners with red arrows. The absorption of the copper sheet overlapped the signal of the interconnect and silicon die. In SAM images (S1) to (S3) instead, the die outline was clearly visible, and differences between the interconnects and inhomogeneities inside single interconnects were also observable. The color level correlated with the porosity of the sintered interconnect, whereby darker areas were less porous than brighter ones and bright white areas could be interpreted as local delaminations. Considering that,  
Figure 8: Comparison of NDTs on three sintered copper pastes. (**X1**) to (**X3**) show X-ray images including red arrows to mark the die outline, (**S1**) to (**S3**) show SAM images with a 100 MHz transducer, (**Z**) shows the \(Z_{th}(t)\), and (**B**) shows the normalized logarithmic derivative plot, both including the measurement of an identical sample soldered with SAC305 paste. In (**Z**), increases in \(Z_{th}(t)\) between 1 ms and 10 ms of 0.78 K/W for paste 1, 0.54 K/W for paste 2, 0.89 K/W for paste 3, and 0.68 K/W for SAC305 were measured. A normalization interval from 100 μs to 400 μs was used in (**B**), and peak changes of 0.112 for paste 1, \(-\)0.202 for paste 2, and 0.191 for paste 3 compared to SAC305 were measured. paste 1 was the poorest, while pastes 2 and 3 showed comparable sintering. However, an inference from SAM to the thermal performance was not possible as revealed by the TTA. The \(Z_{th}(t)\) curves for the three pastes and a SAC305 reference sample are plotted in (Z), and the waveforms could be separated into four time intervals referring to the four material layers. The first interval until approximately 1 ms could be assigned to the silicon of the die, and the curves overlapped within.