## 4 Conclusions  
We presented a new silicon qubit device design consisting of a linear array of electrostatically-defined quantum dots, each of them hosting one electron spin qubit. The QDs are confined along a trapezoidal silicon nano-ridge with wet-chemically-etched [111] facets for reduced potential disorder. We perform electrostatic simulation on the device design and demonstrate the required technology modules, which are adapted from the well-developed industry-compatible processes and thus promise scalable multi-qubit device fabrication. According to the electrostatic simulations, we can generate a translationally-symmetric array of QD with tunable tunnel barriers in our device and in principle with an arbitrary length. Using a split-gate array as the top-gate structure, a linear double-QD array or alternatively a linear QD array with adjacent a single electron transistor can be formed. The perpendicular valley states are sufficiently split off (>1 meV) from the mixed \(\pm k_{z}\) valley states due to confinement and the anisotropic electron mass. Thus, the <110> lattice orientation of our silicon nano-ridge does not impose complications on the valley-orbital states for the qubit. The fabrication of the nano-ridge is based on selective anisotropic wet-etching using TMAH, resulting in atomically-flat [111] sidewalls with \(\text{RMS}=0.3992\,\text{nm}\) and dry oxidation at a temperature above the viscous flow point. Thus, the high-quality, confining Si/SiO\({}_{2}\) interface is intrinsically protected and comparable to industrial standards. After deposition of two TiN side-gates, chemical-mechanical polishing enables the fabrication of a linear array of metal gates by a SiO\({}_{2}\) spacer (10 nm in width) process. We achieve a 50-nm gate pitch, already very close to the simulation requirement of 45 nm. Electrical defect characterization of the CVD deposited SiO\({}_{2}\) on the {111} silicon facet shows an interface defect density of \(D_{\text{lt}}=(5.6\pm 0.5)\cdot 10^{11}\,\text{V}^{-1}\text{cm}^{-2}\) and \(D_{\text{lt}}=(2\pm 1)\cdot 10^{10}\,\text{V}^{-1}\text{cm}^{-2}\) before and after thermal treatment, respectively. The polarity of the dominating  
Figure 5: Fabrication steps of the self-aligned spacer process as the basis of a high-density gate structure. (**a**) Schematic of the self-aligned spacer process. Top to bottom: structured resist (red) on the layer-stack including the SiO\({}_{2}\) hard mask (blue), the \(a\)Si sacrificial layer (dark grey), and the Al\({}_{2}\)O\({}_{3}\) etch stop layer (green); anisotropic dry-etching; conformal SiO\({}_{2}\) deposition; anisotropic dry back-etching; free-standing oxide spacer. (**b**) Cross-section and top-view scanning electron micrograph of the free-standing SiO\({}_{2}\) spacer with a width of 15 nm on a (75: 5) nm pitch. The spacer height is 45 nm. (**c**) Scanning electron micrograph of top-viewed 10 nm free-standing SiO\({}_{2}\) spacer with a 50 nm pitch. Metallic gates between the spacers are not shown here, but voltage labels are added for clarity (cf. Figure 1). The final gate structure is used for top-ridge localization. Ohmic contacts to the electron reservoirs at the ends of the silicon nano-ridge are indicated by crossed squares. defects is changed by the treatment. The defect density observed is similar to our thermally-grown SiO\({}_{2}\) on the {001} facet. In the future, our proposed multi-qubit device can be operated in two ways, both significant for future scalable quantum computing architectures with quantum error correction: (1) A long linear array of physical qubits with next-neighbor two-qubit gates is sufficient to define a logical, thus quantum error-corrected qubit [32]. Such a linear chain can be realized with our device concept. (2) Looking toward the future, a 2D grid of silicon nano-ridges with high-density gate arrays is within reach.