# An Automatic Detection Method for Cutting Path of Chips in Wafer
## 4 Discussion  
To verify the accuracy and stability of the template matching algorithm used in the paper, we compare it with SAD and NCC matching algorithms, evaluate the number of chips matched, matching deviation, and running time, and verify the adaptability, accuracy, and real-time of the template matching algorithm. The images in Section 3.1 are used as experimental samples. When the deviation exceeds 10 pixels, the area where the interlayer is located cannot be guaranteed due to variations in the shape of the chip, resulting in cutting tracks with deviations in position and angle. The Sum of Absolute Differences (\(SAD\)) traverses the entire target image and calculates the absolute difference between the sub-image and the template image. The smaller the absolute difference, the more similar it is. \[SAD(i,j)=\sum_{s=1}^{M}\sum_{t=1}^{N}\lvert S(i+s-1,j+t-1)-T(s,t)\rvert \tag{23}\]  
Figure 12: Comparison of fitting error between LSM and RANSAC algorithms for four categories of wafer images, where LSM is Least Squares Method. where, \(S\) is the target image and \(T\) is the template image. The Normalized Cross Correlation (\(NCC\)) is similar to the SAD in that it uses the gray level of the target image and template image to calculate the matching degree by the normalized correlation measure. \[NCC(i,j)=\frac{\sum_{s=1}^{M}\sum_{t=1}^{N}\left|S^{ij}(s,t)-E\left(S^{i,j} \right)\left|\cdot\right|T(s,t)-E(T)\right|}{\sqrt{\sum_{s=1}^{M}\sum_{t=1}^{N} \left[S^{i,j}(s,t)-E\left(S^{i,j}\right)\right]^{2}\cdot\sum_{s=1}^{M}\sum_{t=1 }^{N}\left[T(s,t)-E(T)\right]^{2}}} \tag{24}\]  
where \(E(S^{i,j})\) and \(E(T)\) represent the average gray value of the search area and template at \((i,j)\), respectively. To ensure the accuracy of the street location, when column \(j\) in the wafer image locates only one chip, it is considered that this column does not match the chip because the deviation of the cut path determined by only one chip is large. The adaptability of the algorithm is determined by processing the number of chips matched in different wafer images and the matching accuracy rate. The more chips are located, the better the adaptability of the method. The definition of accuracy is the same as that in Section 3.1. The difference between the maximum and minimum value in the \(x\)-direction coordinate position of each chip column is obtained, and then the mean value of the difference in each column of an image is calculated as the positioning error of the image. The smaller the average difference, the more accurate the positioning is. Real-time is defined as the average processing time for each wafer image in different categories. Table 6 shows the comparison of the number of SAD, NCC, and proposed method matching chips with the correct rate, deviation in the X direction, and processing time. If too few chips are matched, there will not be enough chips on either side of the street to locate the cut path. Table 6 shows that the matching accuracy of the proposed method is the highest, the matching results are all correct, and the number of chip regions matched in the wafer images of Cat.2, Cat.3, and Cat.4 are the largest. Although the SAD matches the largest number of chips in the image of Cat.2, the accuracy is less than 90%, and as the number of matches between this method and SAD is less than 1, the NCC method has the worst effect. In terms of accuracy, when using the proposed method to process images of Cat1 and Ca2, the deviation in the X direction is the smallest. Among the image processing results of Cat3 and Cat4, the deviation using the SAD is the smallest, but the number of chips matched by the SAD is also less than that of the proposed method. In terms of real-time, the running time of the proposed method is stable within 0.7 s, while the speed of processing the image of Cat.4 is slightly slower and stable at 1.1 s. In the experiments in Section 3.1, the fitting accuracy of Cat.4 is the best. The processing time of SAD and NCC algorithms is 44.5 s and 195 s, respectively.