## 5 Experimental Results
### High-Data and Multi-Level Modulated Traffic  
Considering the application of the fast optical switch PIC in DCNs deployed with advanced optical interconnect solutions, the capability of handling the high data-rate and multi-level modulated traffic is a necessity. The potential impact on the signal integrity and OSNR degradation when given lower input power, therefore, should be well addressed. To assess the performance of the fast optical switch PIC in switching the high-capacity and multi-level modulated traffic, the experimental setup shown in Figure 12 is employed. Three types of traffic are generated and tested, namely the 40 Gb/s NRZ-OOK, 20 Gb/s PAM4, and data-rate adaptive DMT. The four WDM channels are de-correlated, amplified, and polarization-controlled before reaching the fast optical switch PIC chip. Module 1, as one of the four identical modules, has been selected for the switching performance assessment. The bias current for the booster SOA and gate SOA are adjusted by an FPGA-based switch controller. The switching of the packetized 40 Gb/s NRZ-OOK (PRBS 211-1) traffic is first analyzed. The power of each channel launched into the WDM OXC is \(-\)4 dBm and the driving current for the booster SOA and gate SOA are 100 mA and 60 mA, respectively. At the output, switched traffic is amplified and sent to the BER tester (BERT). The BER curves, as well as eye diagrams for Channel 1 with a single channel and WDM input applied are shown in Figure 13a. The back-to-back (B2B) curve is also included for reference. Error-free operation with a 0.5 dB power penalty at a BER of 1 \(\times\) 10\({}^{-9}\) has been measured for single channel case. When four WDM channels are fed into the switch, the result indicates slight performance degradation with a penalty of around 1 dB which is mainly due to the noise introduced by the SOAs. The power penalty measured at BER of 1 \(\times\) 10\({}^{-9}\) with different input optical power is plotted in Figure 13b. The bias current for the booster and gate SOAs are varied to equalize the output power of the chip. For single channel input, 14 dB dynamic range is achieved with less than 1.5 power dB penalty. WDM input would cause an expense of 1 dB extra penalty. A smaller dynamic range of 10 dB is obtained for the WDM input case. The required bias current for the booster SOA and gate SOA is also illustrated in Figure 13b. Higher input power would require less driving current for both SOAs to achieve the equal  
Figure 12: Experimental setup for the performance assessment of NRZ-OOK traffic. As promising interconnect solutions, PAM4 and DMT can effectively boost the link capacity, and the switching performances have been analyzed for the fast optical switch PIC. The WDM channels are modulated with the PAM4 and DMT traffic generated by the 24 GSa/s arbitrary waveform generator. At the switch output, the traffic is received by a real-time 50 GSa/s digital phosphor oscilloscope (DPO) for offline DSP. The BER curves and the eye diagrams of the switched 20 Gb/s PAM4 traffic at Channel 1 are shown in Figure 14a. A power penalty of 0.4 dB and 1 dB at BER of 1 \(\times\) 10\({}^{-3}\) has been observed for the single channel and WDM input, respectively. The optical power dynamic range guaranteeing a BER \(<\) 1 \(\times\) 10\({}^{-3}\) is then studied. The power penalty when varying the input power and the corresponding bias current of both SOAs for equalized output are depicted in Figure 14b. Both cases achieve \(>\)10 dB dynamic range within a 2 dB power penalty. Similar to the NRZ-OOK traffic, lower input power is limited by the OSNR degradation where the noise is more dominant. A larger penalty is also found for higher input power due to the increased sensitivity to saturation, as confirmed by the eye diagrams in Figure 14b. The situation without the output EDFA is also investigated for the single channel input case, and the dynamic range result is presented in Figure 14b. A similar trend with a smaller power penalty has been observed compared to the presence of EDFA.