# Parallel Eclipse-Aware Routing on FPGA for SpaceWire-Based OBC in LEO Satellite Networks
## 4 Experimental Results  
### Experimental Setups  
This experiment verifies satellite network routing using FPGA-accelerated KSP and EAR algorithms. Figure 5 presents the overall test architecture, and Figure 6 shows the real equipment. The testbed comprises two PCs, a single FPGA board, and two SpaceWire Brick MK4 units--hereafter MK4#1 and MK4#2. The host PC programs the FPGA over JTAG; the FPGA then executes the KSP and EAR kernels and returns the best route to the PC. Using this result, the PC remotely updates the routing table of MK4#2 across the SpaceWire network. MK4#1 and MK4#2 were controlled from the PC through the SpaceWire API.  
Figure 4: Schematically illustrated pipelined KSP algorithm.  
Figure 3: KSP and EAR Algorithms Running in PS and PL area.  
Figure 5: Structure for experimental environments.  
In Figure 5 the two MK4 routers are interconnected with a SpaceWire cable. The Brick MK4 integrates a multi-channel USB 3.0 interface that conveys data, power, and control signals between the host PC and the router. Through this interface, Channel 0 serves as a dedicated control link for reading and writing the routing table and link parameters, while Channels 1 and 2 provide independent data paths for SpaceWire packets, thereby preventing contention during multi-link experiments. At the core sits a non-blocking SpaceWire router capable of path and logical addressing at up to 300 Mbit/s per link. Router configuration and status monitoring are accessed via a dedicated config port, and external connectivity is supplied by SpaceWire ports 1 and 2, which physically interconnect MK4#1 and MK4#2 through a SpaceWire cable that forms the actual data path between the two devices.  
Figure 6 is a photograph of the laboratory setup used for the experiment. The two PCs are interconnected via SpaceWire equipment to the MK4 routers. The PC on the left is linked to the FPGA; after receiving the computation results from the FPGA, it remotely updates the routing tables and thus corresponds to the upper-side PC in Figure 5. The PC on the right, which checks whether the routing table has been correctly modified, serves as the lower-side PC in Figure 5.  
The FPGA used in this experiment was UltraScale+\({}^{\text{TM}}\) MPSoC ZCU104. Because a central contribution of this work is an FPGA implementation that operates in concert with real SpaceWire hardware, a detailed description of the experimental platform is essential to demonstrate both the practicality and reproducibility of our approach. Since PS and PL are installed and we have enough resources for the current experimental setup, pipelining in PL was possible. The PC connected to the remote device MK4#2 verified the accuracy of the routing table's modification with the SpaceWire GUI. In this experiment, the performance of the PC was not an important factor in the experimental results, so the specifications of both PCs were omitted.  
Table 1 summarizes the key specifications of the FPGA used in this experiment. The Zynq UltraScale+\({}^{\text{TM}}\) MPSoC ZCU104 board is built around the Xilinx Zynq UltraScale+ MPSoC (ZU7 EV) and offers four Cortex A53, two Cortex R5, Mali 400 MP2 GPUs with clocks up to 600 MHz, 2 GB DDR4, and a variety of high-speed I/O (PCIe, USB 3.0, SATA, etc.). This makes it an optimal environment for embedded FPGA acceleration and PS-PL collaboration and is suitable for KSP and EAR algorithm acceleration assessments such as large-scale graph  
Figure 6: Configured real experimental environment.  
search. In this experiment, we evaluated the performance of the KSP and EAR algorithms based on the FPGA using resources from the UltraScale+TM MPSoC ZCU104.