## 4 Experimental Verification
### Testing Results and Analysis
The method in [2] is a typical voltage-type droop scheme, whose core expression is  
Figure 14:2  
where \(u_{\text{ref},k}\), \(u_{\text{ok}}\), and \(i_{\text{ok}}\) are the reference voltage, output voltage, and output current of the \(k\)-th unit, respectively. In [10], the current-type droop method is denoted as  
Figure 14:3  
where \(m_{0}\) and \(m_{1}\) are the initial droop coefficients, which must be properly chosen to prevent obvious voltage deviations. In [2], \(n\) was set as 8 in case the power of ESU#1 exceeded its allowable upper limit. A small \(m_{0}\) helps to reduce the deviation of \(u_{\text{dc}}\), and it is \(1\times 10^{-5}\) here. In [10], \(i_{\text{sutu}}\) was 33 A, and \(n\) was 50. A large \(m_{1}\) leads to a lower voltage drop of \(u_{\text{dc}}\), and it was set to \(1\times 10^{9}\). If \(m_{1}\) is larger than \(1\times 10^{9}\), the system will be unstable. The related waveforms are presented in Figure 14:4 Affected by the mismatched power losses and line resistances in real circuits, the ESU with the highest SoC does not deliver the highest current in the primary stage. Based on Equations (38) and (39), \(u_{\text{dc}}\) gradually declines regardless of whether [2] or [10] is adopted because each SoC level persistently decreases when the discharge continues. The comparative indexes are summarized in Figure 14:5 In contrast with [2] and [10], the results of the proposed strategy in Figure 17a,c display faster balancing speed because the voltage deviation is inexistent; hence, the sum current is always higher than that in the droop methods. Furthermore, a higher sum current leads to a faster mitigation of SoC differences with the same CDRs and circuit parameters. As for equalization precision, the proposed method removes the influence of actual power losses and \(u_{ik}\) decline, so it is more accurate. In [2] and [10], the SoC in real time is based on approximate estimation. However, the actual SoC during discharge is always lower than its approximate value used in microprocessor programs because ESUs must deliver higher currents to make up for power losses. Furthermore, the mismatched power losses of each unit enlarge the final SoC deviations between the highest and lowest SoC values. The corresponding results are shown in Figure 14:6 \begin{table}
\begin{tabular}{l c c} \hline \hline
**Balancing Scheme** & **Balancing Duration** & **Final SoC Deviation** \\ \hline [2] & over 6000 s (Figure 22c) & around 0.9\% (Figure 22e) \\ [10] & over 2300 s (Figure 22d) & around 0.3\% (Figure 22f) \\ proposed & 1450 s (Figure 17a) & around 0.1\% (Figure 17c) \\ \hline \hline \end{tabular}
\end{table} 
Table 6: Experimental performance comparisons of different methods. \begin{table}
\begin{tabular}{l c c c c c c} \hline \hline \multirow{2}{*}{**Case**} & \multicolumn{3}{c}{**Parallel Application**} & \multicolumn{3}{c}{**Series Application**} \\ \cline{2-7}  & **Theoretical** & **Actual** & **Deviation** & **Theoretical** & **Actual** & **Deviation** \\ \hline Normal operation & 1700 s & 1450 s & 14.7\% & 2400 s & 2200 s & 8.3\% \\ Load change & 2050 s & 1800 s & 12.2\% & 2600 s & 2550 s & 1.9\% \\ Battery degradation & 1560 s & 1500 s & 3.8\% & 2620 s & 2550 s & 2.7\% \\ Sudden termination & 1600 s & 1400 s & 12.5\% & 2350 s & 2250 s & 4.3\% \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Theoretical and experimental comparisons of balancing time using the proposed strategy.