# Logic Synthesis Strategy Oriented to Low Power Optimization
## 5 Experimental Results  
In order to test the effectiveness of the solutions obtained using the PowerDekBDD algorithm, a number of experiments were performed. The PowerDekBDD algorithm is implemented in the tool of the same name. A popular set of benchmarks [43] was used for the experiments. Since Equation (6) does not take into account the sharing of logic resources between individual functions of the team, it was decided to consider each function separately and then sum the obtained results. In the first series of experiments, it was decided to compare PowerDekBDD with other academic tools. Since PowerDekBDD is an extension of the DekBDD algorithm, it is crucial to compare both algorithms. Additionally, it was decided to compare with the leading synthesis tool ABC [27]. The work [44] discusses the appropriate scripts for the ABC system: \"Baseline\" as the basic one, and \"PowerMap\" and \"PowerDC\" as the scripts aimed at reducing power consumption. The comparisons between the tools were made, taking into account the necessary number of LUTs in the obtained \"LUTs\" solution (assumed k = 5) and the number of logic levels, \"Levels,\" obtained. Of course, additional information has also been added: in the case of the DekBDD and PowerDekBDD tools, the value of the achieved switching activity, \"SW,\" for each benchmark, while in the case of the ABC tool, the value of \"Power\" was given, which, as stated in [44], is calculated on the basis of \"SW.\" According to the authors, the calculation methods of \"Power\" and \"SW\" in both tools are slightly different, and it is difficult to make a direct comparison between them. In order to maintain the reliability of the results, the authors provide the \"Power\" value for ABC, but at the same time emphasize that the purpose of compiling these results is not to compare them directly. The described list of results is presented in Table 1.  
The last rows of Table 1 contain the sum value and the geometric sum. The values of the respective sums are summarized in the graphs in Figure 6.  
Analyzing the graph in Figure 6a, it can be observed that the solutions obtained with the PowerDekBDD tool are the most effective in terms of the number of LUTs. The obtained improvement over DekBDD is about 2%. Taking into account Figure 6b, it can be observed that the total number of logic levels for PowerDekBDD is slightly greater than for DekBDD. However, both solutions are much worse than the solutions obtained for ABC. Figure 6c shows the comparison in terms of SW. In the case of PowerDekBDD, this parameter was reduced by over 5% compared with DekBDD. Unfortunately, it is impossible to reliably compare the PowerDekBDD method with the ABC system because the methodology of SW determination in both systems is slightly different; therefore, this issue will not be further developed. \begin{table}
\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline \multirow{2}{*}{**Svp1**} & \multirow{2}{*}{**PowerDekBDD**} & \multicolumn{3}{c|}{**dekBDD**} & \multicolumn{3}{c|}{**PowerDekBDD**} & \multicolumn{3}{c|}{**ABC Baseline**} & \multicolumn{3}{c|}{**ABC PowerMap**} & \multicolumn{3}{c|}{**ABC PowerD**} \\ \cline{3-14}  &  
Summarizing the comparison of academic systems, it can be stated that it was possible to reduce the number of blocks, but it is difficult to draw any conclusions as to the reduction in dynamic power dissipation (SW reduction), which is the main subject of this paper. In this situation, it was decided to conduct a second series of experiments, this time using a commercial tool from Xilinx-Vivado [45]. The next steps of the synthesis in the Vivado system were performed with the default settings. The series 7 FPGA (Artix-7) was selected as the target device. The relevant results included in this paper were taken from the reports generated in this tool after the implementation process. In the PowerDekBDD system, synthesized HDL (Verilog) descriptions of the function after decomposition were generated.