## 4 System Implementation and Simulation Results
### Efficiency Analysis
For the first scenario, where the dead times \(T_{dR}\) (for the rising edge) and \(T_{dF}\) (for the falling edge) are adjusted, the dead time values are calculated using Equations (12) and (13) based on the analysis in [50]. \[T_{dR}\geq(T_{PdR1}-T_{PdR2})+(T_{d,off,M1}-T_{d,on,M2}) \tag{12}\]  
\[T_{dF}\leq(T_{PdF1}-T_{PdF2})+(T_{d,on,M1}-T_{d,off,M2}) \tag{13}\]  
These inequalities incorporate the propagation delays and the turn-on and turn-off delays obtained from Figure 6 to calculate the dead times as a function of operating temperature. These inequalities were derived based on the graph in \[P_{DC-DC} =P_{Cond.}+P_{Sw.} \tag{9}\]0 When these inequalities are evaluated using the simulated data, and an engineering factor that allows to fulfill the inequalities, Figure 13 is generated, showing the required dead time values for each temperature point. In the second scenario, where the dead times are kept fixed across the entire temperature range, the worst-case scenarios are selected. Specifically, \(T_{dR}\) is set to its maximum value at 295 \({}^{\circ}\)C, which is 129 ns, while \(T_{dF}\) is set to its minimum value at 295 \({}^{\circ}\)C, which is 21 ns. Finally, in the third scenario, \(T_{dR}\) is fixed at its maximum value at 295 \({}^{\circ}\)C, and \(T_{dF}\) is set as its symmetric counterpart, with \(T_{dF}=-T_{dR}\). \[P_{DC-DC} =P_{Cond.}+P_{Sw.} \tag{9}\]1 Operation point \(I_{o}=300\) mA; **(a)** efficiency versus output voltage **(left)**, output power versus voltage **(middle)**, gate driver losses versus voltage **(right)**. **(b)** Losses versus voltage of \(M_{2}\) **(left)**, and \(M_{1}\) **(right)**. Based on the results obtained from the three scenarios, it is evident that adjusting the dead times yields the best converter performance, achieving efficiencies of 84.83% at 25 \({}^{\circ}\)C and 89.63% at 295 \({}^{\circ}\)C. In second place is the case with fixed asymmetric dead times, which achieves efficiencies of 84.2% at 25 \({}^{\circ}\)C and 88.18% at 295 \({}^{\circ}\)C. Lastly, the scenario with symmetric dead times results in efficiencies of 83.4% at 25 \({}^{\circ}\)C and 86.45% at 295 \({}^{\circ}\)C. The difference in performance between these experiments can be primarily attributed to the losses caused by \(M_{2}\), where the body diode conduction losses are minimized when the dead times are adjusted. Additionally, it can be observed that in all three experiments, there is an increase in efficiency at higher temperatures. This is mainly due to a reduction in losses in \(M_{1}\), which can be explained by a decrease in its on-resistance. According to (2), this resistance decreases with lower threshold voltage \(V_{th}\) values and stable hole mobility, conditions that are typically met at higher temperatures for PMOS devices in this technology [32, 33, 34]. In Table 6, this work is compared to state-of-the-art high-temperature DC-DC converters reported in the literature. In [51], a monolithic GaN buck DC-DC converter for temperatures up to 250 \({}^{\circ}\)C has been experimentally characterized, showing a large power density and overshoot/oscillation suppression due to reduced parasitics. Nevertheless, the power and efficiency of the system are not provided for comparison. In [52], on the other hand, a high-temperature buck DC-DC converter implemented using Si CMOS is discussed. Although the output power is higher than in our case, the intrinsic temperature limitations for silicon restrict the achievable temperature range. Finally, in [53], a comparative study among three discrete implementations of a non-isolated DC-DC buck converter is done. WBG implementations (using SiC and GaN devices) are highlighted for their low switching power losses and high switching frequencies.