## 3 Design of Serial Bus Network System
### Design of Characteristic Impedance and Termination of Serial Bus  
After connecting three unit network systems together, the length of the bus line becomes 2.4 m. A long bus line means a long returning time of reflected signals from the terminals back to the LSI's I/O cell that drives the bus. Since the LSI has the collision avoidance function, the LSIs at some positions on a long bus line (around the middle part) with low characteristic impedance may never send normal data packets.  
Figure 10 shows a simulated waveform of the rising edge of a logic 1 signal recorded at the TP nearest to the bus pin of the middle sensor platform LSI (No. 24 LSI) that sends this signal. A lower bus line characteristic impedance results in a lower value of the \"Low voltage stage\". A longer bus line results in a longer lasting time of the \"Low voltage stage\". In the case shown in Figure 10, the bus line characteristic impedance is adjusted to a low value (35.5 \(\Omega\) at 1 MHz calculated by ADS). This low characteristic impedance makes the bus logic level judged by the LSI's I/O cell different from the logic level that the LSI sent on the bus. Therefore, the LSI will regard this situation as data collision and stop sending the data packet. This can happen to each logic signal sent by this LSI, and it will never send a normal data packet. To avoid this, the bus line characteristic impedance needs to be increased to lift the \"Low voltage stage\" over the low to high threshold voltage value of the I/O cell of the LSI. As for the falling edge, the high characteristic impedance of the bus line works in a similar way.  
When the LSI drives the bus, its I/O cell's equivalent inner resistance is around 20 \(\Omega\), which causes a certain fraction of the voltage drop. In addition, the typical capacitance of the bus pin of the LSI is 2.83 pF. This bus pin capacitance decreases the equivalent characteristic impedance of the bus line. Therefore, the characteristic impedance of the microstrip bus line was tuned to 127.6 \(\Omega\) at 1 MHz and 112.2 \(\Omega\) at 1 GHz based on Finite Element Method (FEM) simulation (FEMTET from Murata Software Co., Ltd., Tokyo, Japan).  
Figure 9: Photograph of network system with 48 sensor platform LSIs.  
A nearly matched terminal resistance (\(110\,\Omega\)) is better in terms of signal reflection at the ends of the serial bus. However, a low terminal resistance leads to a large bus driving current, which results in a large vibration of the bus driving current when an LSI sends a data packet. This makes the 3.3 V power at the site of the LSI that sends data packets unstable, when many LSIs (e.g., more than 16) are connected to the same long (around 1 m) 3.3 V power line. The unstable 3.3 V power can lead to an abnormal behavior of the LSI. On the other hand, a large terminal resistance (\(10\,\mathrm{k}\Omega\)) leads to a low bus driving current, which results in a low vibration of the bus driving current when an LSI sends a data packet. This helps to stabilize the 3.3 V power at the site of the LSI that sends data packets.  
Therefore, we considered two cases of termination: \(110\,\Omega\) (nearly matched) and \(10\,\mathrm{k}\Omega\) terminations. Simulation was done for each case. If the number of connected LSIs is relatively small, or the number of LSIs triggered at the same time is small (i.e., event-driven mode), \(110\,\Omega\) may be a better choice for high speed communication because there is no severe bus signal fluctuation. In this study, however, we investigated one of the worst cases, i.e., all LSIs were triggered at the same time. Thus, we used \(10\,\mathrm{k}\Omega\) resistors as terminals. The terminal mismatch leads to the vibration of the bus signal. However, because of the high bus characteristic impedance, the bus signal vibrates over or under the threshold value of the LSI's I/O cell. Thus, we think the high terminal resistance does not have negative impact on the communication performance under \(1\,\mathrm{MHz}\) data transmission speed.