# High-Performance QC-LDPC Code Co-Processing Approach and VLSI Architecture for Wi-Fi 6
## 3 The Co-Processing Schemes and Architectures  
### The Strategy and Architecture of Pre-Processing  
The preprocessor's architecture, as shown in Figure 3, consists of the input cache: Input Buffer (IB), the Block Splicing (BS), the output cache: Output Buffer (OB), and the global controller: Global Control (GC). The external module gives LDPC-related parameters (usually provided by the baseband frame parsing module, which is not discussed in this paper) and LLRs information. The preprocessor first stores the LLRs information in the IB. The highest modulation, the maximum number of antenna streams _Nss_, and the quantization of the bit width \(Q\) determine the bit width size of the IB, and the bit width sizes in various configurations are shown in Table 2. Suppose the maximum modulation supported by the system is 256 QAM, and the maximum number of antenna streams is two, taking the dual-stream Quadrature Phase Shift Keying (QPSK) as an example. In that case, the input data format is shown in Figure 4. Where in the effective bit widths _dins1\(1\), _dins1\(2\), _dins2\(1\), and _dins2\(2\) represent the soft information of the 1 st bit, the 2 nd bit in antenna 1, the 1 st bit, the 2 nd bit in the antenna 2, respectively. The number of effective bits may be less than the maximum bit widths to maintain pattern compatibility, and the remaining bits can be filled with zero. If the OB is not whole and the IB is not empty, the preprocessor starts taking data from IB and stitching fields. Since the QC-LDPC code is a linear block grouping code, the output data format of the pre-processing module is continuous output by block. Furthermore, considering the compatibility of the length of the codewords, the output bit width is unified to the maximum bit width, 81 \(\times\) Q. However, because the bit width size of the IB is fixed, field stitching and block stitching are mixed, the control is highly complex, and it is not easy to ensure complete coverage of all possible scenarios. Based on this, this paper proposes a structure in which field splicing and block splicing are separated, the top-level control state machine is only for field splicing, and the BS completes the block splicing. Taking a codeword in a frame as an example, the critical points of field stitching are as follows. DBs: Firstly, the length of SBs for the current codeword is needed. Using the total number of SBs \(N_{slstr}\) and \(N_{CW}\), the quotient and the remainder of the SBs are obtained by division. If the ordinal number of the current codeword is less than or equal to the rest, the size of SBs is the quotient plus one, and vice versa, is equal to the quotient. The actual length of DBs can be obtained by subtracting the size of SBs from the SIF length. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Nss** & **BPSK** & **QPSK** & **16 QAM** & **64 QAM** & **256 QAM** & **1024 QAM** \\ \hline
1 & Q & Q & 2 \(\times\) Q & 4 \(\times\) Q & 6 \(\times\) Q & 8 \(\times\) Q \\
2 & 2 \(\times\) Q & 2 \(\times\) Q & 4 \(\times\) Q & 8 \(\times\) Q & 12 \(\times\) Q & 16 \(\times\) Q \\ \(\cdots\) & \(\cdots\) & \(\cdots\) & \(\cdots\) & \(\cdots\) & \(\cdots\) & \(\cdots\) \\
8 & 8 \(\times\) Q & 8 \(\times\) Q & 16 \(\times\) Q & 32 \(\times\) Q & 48 \(\times\) Q & 64 \(\times\) Q \\ \hline \hline \end{tabular}
\end{table} 
Table 2: The bit width of the input buffer. Figure 4: The data format of the input buffer. Figure 3: Preprocessor Architecture. The output data of the IB of the last codeword may have a residue connected to the end of the PBs or the RBs. If PUBs are not zero, the residual number is written to the DBs of the current codeword before the remaining length of the DBs is taken from IB, as shown in case 1 in Figure 5. If the RBs are not zero, the RBs in the IB output data needs to be discarded.