# A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis
## 3 TSV Reliability
### Thermal Management
(1) TSV Resistor  
The skinning effect emerges as a prominent factor influencing the parasitic resistance of through-silicon vias (TSVs) at high frequencies. In the direct current (DC) scenario, the current passing through the TSV is uniformly distributed across its entire cross-section. However, as the frequency of the signal traversing the TSV escalates, the current density no longer remains uniform and exhibits an exponential decrease with increasing distance from the TSV's surface (i.e., its sidewalls). Consequently, the skinning effect prompts the majority of the current to flow near the surface, leading to a reduction in the effective cross-sectional area of the TSV and an associated increase in its effective resistance. The depth at which the current density diminishes by a factor of 1/e with respect to the current density at the conductor surface is defined as the skinning depth. (2) TSV Inductor  
The concept of inductance is grounded in the formation of a loop created by the regions of current inflow and outflow. However, identifying the precise current return path within intricate integrated circuits, such as passive devices, like capacitors, presents a challenge. Typically, the current return path in integrated circuits is concentrated within the power distribution network (PDN) or in adjacent conductors. As integrated circuits grow increasingly complex, signal transmission no longer adheres to a single fixed return path; instead, several, or even a multitude of wires, may collectively serve as the return path. Three primary factors exert significant influence on TSV inductance. Firstly, the skinning effect impacts inductance, followed by the proximity effect, and lastly, the redistribution of multiple return paths. In instances where multiple return paths exist, the total loop inductance of the TSV encompasses the summation of partial loop inductances and their corresponding return paths. (3) TSV Capacitor  
The capacitance of a through-silicon via (TSV) exhibits a higher level of complexity when compared to its resistance and inductance counterparts. This complexity stems from the physical structure of the TSV, which gives rise to a metal oxide semiconductor (MOS) configuration. Consequently, in deriving a comprehensive expression for TSV capacitance, it becomes imperative to account for the MOS effect. Specifically, when a particular voltage is applied to the TSV, a depletion layer capacitance emerges between the insulating layer and the silicon substrate. (4) TSV Conductance  
The conductance of the TSV is composed of two parts, one generated by the insulating layer surrounding the TSV and the other due to the loss of the silicon substrate. The key challenge associated with the long-term structural reliability of TSV technology stems are the different thermal expansion coefficients (CTEs) of Cu (17.5 \(\times\) 10\({}^{-6}\) K\({}^{-1}\)) and Si (2.6 \(\times\) 10\({}^{-6}\) K\({}^{-1}\)), which can lead to thermal stresses in these structures during thermal excursion of microelectronic devices [7; 47]. The presence of large thermal stresses in TSV structures can be particularly detrimental to silicon, which is a brittle material. If the thermal stresses exceed the strength of the silicon, it can lead to cracks and fractures that can compromise the performance and reliability of the IC. Furthermore, the fracture of the Si\(-\)Cu interface can cause delamination, which can also lead to performance and reliability issues. The study by [PERSON] et al. [7] examined the fracture of Si wafers in CF-TSV caused by annealing in the temperature range of 250-550 \({}^{\circ}\)C and natural aging after annealing. They observed the nucleation of microcracks in Si near the Cu column, which propagated at a constant rate during post-annealing room temperature aging, thus, confirming delayed fracture in Si.