## 2 Related Work  
Lots of researchers studied the DPR system based on FPGA performance and effectiveness. Ref. [8] presents methodologies for scheduling periodic hard real-time dynamic task sets on fully and partially reconfigurable FPGA. It assumes that FPGA can be partitioned into a set of homogeneous tiles statically and any tasks can be mapped into this region. Ref. [9] proposes a real-time system manager (RTSM), and verifies in this paper to scheduling tasks on the reconfigurable regions of available processors and FPGA. The RTSM uses a task reuse strategy to minimize reconfiguration overhead, moves tasks between zones to effectively manage FPGA zones, reserves tasks for future reconfiguration and execution, and supports configuration perfecting. Ref. [10] a multiprocessor pipelined memory sensing scheduling method based on genetic algorithm, which uses the efficiency of heuristic method to improve the throughput without reducing the application running time. The task reconfiguration on the reconfiguration region is a time-consuming process. The total running time of the task can be optimized by reducing the configuration delay of the task. Refs. [11; 12; 13] take the technique of perfecting for accomplishing this objective. Some researchers use module reuse to optimize reconfiguration time and power consumption in [14; 15]. Ref. [16] divides software and hardware with the goal of improving FPGA resource utilization. The result of this division has many shortcomings, such as the high complexity of the model and the model based on too many assumptions. The improved algorithm greatly reduces the model complexity, shortens the solving time, and improves the solution results. Ref. [17] exploits A* search algorithm to place hardware tasks in the programmable logic at appropriate times. The model presented in this paper not only optimizes throughput but also takes power consumption as one of the optimization objectives, while it does not partition the area of the reconfiguration region. In [18], the authors propose an Ant Colony Optimization (ACO) approach for mapping, scheduling and placing directed acyclic graph (DAG) on the SoC with a FPGA. It constructs solutions and then searches around the best ones, cutting out non-promising areas of design space, hiding reconfiguration overheads through pre-fetching. Ref. [19] proposes a two-stage task scheduling approach in multi-FPGA systems to optimize task execution efficiency. Ref. [20] proposes an application-specific multi-objective system level design methodology which determine the appropriate number of regions and the mapping and scheduling of tasks to the regions. Ref. [21] presented a design methodology for partitioning the FPGA region under a programming framework FRED. It is accomplished by means of a MILP that is in charge of size of region and which task hardware tasks can be statically allocated to the FPGA. Ref. [22] puts forward a task mapping algorithm for the multi-shape tasks based on an interval list. It improves the shortcoming of traditional task mapping algorithms that wasting a significant portion of FPGA resources. But this article does not consider task scheduling issues. In [23], the author proposes a Mixed-Integer Linear Programming formulation for mapping tasks on the device and scheduling their execution. Even if this method could find the optimal solution, the solving time grows exponentially with the increase of the number of tasks. To overcome high time complexity, the authors propose IS algorithm. In this algorithm, it scheduled k tasks at a time optimally exploiting the MILP model. The value of k can be set according to requirements, so in order to represent the value of k, we abbreviate this algorithm as IS-k. The above researches greatly promote the development of dynamic partial reconfiguration technology, but there is still room for optimization and improvement. This paper proposes a partitioning and scheduling model for DPR system, and designs a solution method based on simulated annealing algorithm to solve the model.