## 3 Results  
### Description of the VHDL Blocks Implemented for the AES Encryption/Decryption Algorithm  
The VDHL block developed for implementing the encryption algorithm is shown in Figure 8 (red box); it accepts the plaintext in input and provides the ciphertext in output, both arranged into 128-bit blocks, via the AXI Stream bus. The source files implementing the encryption block are shown in Figure 9; the first four files are, AES_AXIS_KEY_v1, AES_AXIS_KEY_v1_0_S00_AXIS_inst, AES_AXIS_KEY_v1_0_S01_AXI_inst and AES_AXIS_KEY_v1_0_M00_AXIS_inst, related to the implementation of the communication between blocks, through AXI Bus Stream and AXI Lite; instead, the last two files contain the code for performing the encryption algorithm, namely aes_encoding_block and cipher_key_expansion_block. The portion of the firmware, contained in cipher_key_expansion_block, dealing with the expansion of the key is shown in Figure 10, which performs the necessary operations to obtain the 44 words to make up the 10 sub-keys, used during the encryption rounds. Also, the start of the key expansion routine, whenever a new key is validated by the processor, has been implemented using the expansion_key_start signal; in order to obtain all the 44 words of the expanded key, only 174.5 ns are required. As can be seen, the 44 words, constituting the sub-keys, are obtained by carrying out xor operations between the 32-bit sections of the subkey at the previous round. Figure 8: Complete scheme containing all the blocks implemented, both for the encryption algorithm and for testing it. if round_counter = 0 then  out_valid <= '0';  end if;  ck_current_round(0 to 31) <= ck_precedent_round(0 to 31) xor  (((sbox_encoding_4(to_integer(unsigned(ck_precedent_round(104 to 111)))))) and X^FP00000\") or  ((sbox_encoding_4(to_integer(unsigned(ck_precedent_round(112 to 119)))))) and X^00 FF0000\") or  ((sbox_encoding_4(to_integer(unsigned(ck_precedent_round(120 to 127)))))) and X^000 FF00\") or  ((sbox_encoding_4(to_integer(unsigned(ck_precedent_round(96 to 103))))) and X^00000 FF\")) xor  non(round_counter);  when 2 =>  ck_current_round(32 to 63) <= ck_precedent_round(32 to 63) xor ck_current_round(0 to 31);  when 3 =>  ck_current_round(64 to 95) <= ck_precedent_round(64 to 95) xor ck_current_round(32 to 63);  when 4 =>  ck_current_round(96 to 127) <= ck_precedent_round(96 to 127) xor ck_current_round(64 to 95);  round_counter <= round_counter + 1;  when 5 =>  out_cipher_key <= ck_current_round; ```  
Figure 10: Code section used to generate the 10 subkeys, for encrypting the 128-bit plaintext data packets. Figure 9: Source files used to implement the code performing the encryption process. packets, thus allowing to start the processing of a new packet as soon as the round's processing on the previous ones is completed. Therefore, simultaneous processing on multiple packets is performed, thus allowing better exploitation of the used hardware resources, so reaching higher data throughput. As below reported, the proposed AES implementation takes only a clock period to complete the round's processing, allowing to provide an encrypted data packet for each clock cycle. To test the correct behaviour of the implemented algorithm, a word generator, called Data_Generator (green box in Figure 8), has been included in the tool offered by Vivado IP INTEGRATOR for simulating the presence of the ethernet module, that provides 128-bit data packets at the input of the encryption block, every 42.67 ns, via the AXI Stream bus. Instead, to insert and store the key, an external block called Key_generator (purple box in Figure 8) and a memory block with 4 registers of 32-bit each have been employed, connected via AXI Lite bus, so allowing the user to update the key at any time. A Key_to_write block (orange box in Figure 8) writes the 4 words of the key (32 bits each) in 4 registers, created during the AXI Lite bus implementation phase, asynchronously to the processor, allowing the substitution of the encryption key during the normal operation of the algorithm.