# A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit
## 2 The Proposed Four-Phase All-Digital DLL with De-Skew Circuit Architecture  
The entire DLL system has two input clocks and five output clocks, as shown in Figure 1. The input clock SCLK is the reference clock of the DLL system and originates from the key node in the clock tree of the NAND Flash interface system. The input clock CLKI is the delayed signal of SCLK, which is used as the synchronized clock of the DLL system to control the locking process. The output clocks CLK0, CLK90, CLK180, CLK270 and CLK360 are multiphase clocks based on SCLK that provide important data strobe signals DQS for data transmission and offer synchronized clocks for critical modules of the NAND Flash interface. Figure 1 shows the architecture of the proposed four-phase DLL with a de-skew circuit, which consists of a de-skew circuit, a four-phase circuit, a mirror path and a multiplexer (MUX). The DLL system first works in parallel, which enables both de-skew and four-phase circuits, and then changes to cascade after the four-phase circuit is locked. By making the de-skew and four-phase circuits work in parallel in separate loops until the system is locked, the local power supply network of the DLL system remains stable, thus eliminating the variable phase error caused by mode switching. In addition, the parallel operation helps to reduce the total locking period of the overall circuit. The mirror path replicates the MUX and output buffer on the CLK0 path to produce the mirrored output DCLK0, thus allowing the de-skew circuit to compare phase relationships independently. The MUX is  
Figure 1: The proposed four-phase all-digital DLL with de-skew circuit architecture. used to control the switching of the parallel-cascade configuration. The signal CLKII is an output of the de-skew circuit and also the input clock of the 4P-DCDL in cascaded mode. The four-phase circuit consists of a phase detector, a TDC-based delay line controller, an adaptive controller and a 4P-DCDL, as shown in Figure 2. To improve the frequency range and phase accuracy, the four-phase circuit adopts the configurable 4P-DCDL and the adaptive controller [16]. The configurable 4P-DCDL is configured for different delay ranges according to the configuration signal SET. The adaptive controller generates the signal SET by quantizing the frequency of the input clock. After being enabled, the four-phase circuit first measures the frequency of the input clock through the adaptive controller and generates signal SET to configure the 4P-DCDL for the appropriate delay range. Then, the TDC-based delay line controller controls the 4P-DCDL to generate delay between the input and output clocks to make the latter lag from the former by exactly one clock cycle. Finally, the 4P-DCDL outputs the four-phase signals by dividing the clock cycle equally. Since the adaptive controller needs to reuse the 4P-DCDL, the input clock should go through logic units and buffers before entering the 4P-DCDL, which causes a clock skew (\(t_{skew1}\)) between SCLK and CLK0. Besides the \(t_{skew1}\), there is also a clock skew between SCLK and CLK0 caused by the clock network (\(t_{skew2}\)), as shown in Figure 1.  
The de-skew circuit is embedded in the delay path between SCLK and CLK0 to eliminate the \(t_{skew1}\) and \(t_{skew2}\), as shown in Figure 1. In parallel mode, the de-skew circuit aligns SCLK and CLK0 by aligning SCLK and DCLK0. To achieve the wide frequency range required by the ONFI protocol, the de-skew circuit in this paper is based on HDSC architecture, which can shorten the delay line without affecting the frequency range, instead of the traditional architecture with a long delay line, which means a large area and high power consumption. The de-skew circuit consists of a phase adjuster, a phase detector, a controller and a delay line. The phase adjuster adjusts the phase of the input clock of the delay line to reduce the delay for skew compensation.