## Appendix A \"Anchor\" Proposition 1 Derived from Pelgrom's Transistor  
Mismatch Model  
Proof of Proposition 1.: A paramount insight stemming from Pelgrom et al. [5] is that for any current source on the chip, say \(I_{s}\), (for \(s\) = 0, 1, 2,..., \(S\) = 1), its \"relative variance\" is inversely proportional to the MOS transistor active area (sometimes equivalently restated that \"relative STD\" is inversely proportional to the square root of the MOS transistor active area),  
\[\text{var}^{\text{rel}}\{I_{s}\}\equiv\frac{\sigma_{I_{s}}^{2}}{\left\langle I _{s}\right\rangle^{2}}=\left(\sigma_{I}^{\text{rel}}\right)^{2}\propto\frac{1 }{\text{Area}}\Leftrightarrow\sigma_{I_{s}}^{\text{rel}}\equiv\frac{\sigma_{I_ {s}}}{\left\langle I_{s}\right\rangle}\propto\frac{1}{\sqrt{\text{Area}}} \tag{1}\]  
to first-order (barring higher-order corrections), assuming that all MOS transistors are of equal length and subject to a fixed potential drop. The MOS transistors active areas of the current sources arrays are modeled rectangular, with the current sources of various widths \(W_{s}\), sharing a common length \(L_{s}=L_{0}\) and a common depth. Since \(\text{Area}_{s}=W_{s}\cdot L_{s}=W_{s}\cdot L_{0}\quad\therefore\text{Area}_{s} \propto W_{s}\). It then follows from Pelgrom's model (1) that the relative variance (1) is inversely proportional to the transistor width:  
\[\text{var}^{\text{rel}}\{I_{s}\}\equiv\frac{\text{var}\{I_{s}\}}{\left\langle I _{s}\right\rangle^{2}}=\left(\sigma_{I}^{\text{rel}}\right)^{2}\propto\frac{1 }{\text{Area}}=\frac{1}{W_{s}\cdot L_{s}}\propto\frac{1}{W_{s}} \tag{2}\]  
Equivalently, the relative standard deviation of each current source is inversely proportional to the square root its active area, hence also inversely proportional to the square root of the transistor active region width:  
\[\sigma_{I}^{\text{rel}}\propto\frac{1}{\sqrt{\text{Area}}}\propto\frac{1}{ \sqrt{W_{s}}} \tag{3}\]The higher-order refined current mismatch models which followed Pelgrom et al. seminal work [5], provided refined additive corrections to the dominant term \(\frac{1}{\sqrt{W_{s}}}\), but in this work we assume just the dominant term as described by the transistor models above. Noting that \(L_{s}\) is taken constant, and so is the depth of all active areas constant, it follows that the MOS transistor on-state conductances are proportional to the device widths, \(W_{s}\), (since the conduction of a surface resistor is proportional to its transverse (cross-sectional) area, and given a fixed depth, this area is proportional to the width, \(W_{s}\)). And since all MOS transistor active areas are assumed subject to a common voltage drop, then, by Ohm's law, each mean source current is proportional to the respective source active region conduction, which is turn is proportional to the width, \(W_{s}\); thus, so are mean source currents proportional to the active widths (thus proportional to the respective active areas):  
\[\langle I_{s}\rangle\propto W_{s}\propto A_{s} \tag{10}\]  
To intuitively make this conclusion plausible, note that increasing the transistor width \(n\)-fold, amounts (neglecting boundary effects) to side-wise stacking \(n\) transistors in parallel, evidently yielding an \(n\)-fold increase in current. Our key assertion \(\mathrm{var}I_{s}\propto\langle I_{s}\rangle\) (95) in Proposition 1 (the inverse proportionality of the relative variance and the mean for each current source) then logically stems from \(\mathrm{var}^{\mathrm{rel}}\{I_{s}\}\propto\frac{1}{W_{s}}\) (11) as well as from \(\langle I_{s}\rangle\propto W_{s}\) (10), yielding \(\mathrm{var}^{\mathrm{rel}}\{I_{s}\}\propto\frac{1}{W_{s}}\propto\frac{1}{ \langle I_{s}\rangle}\). To recapitulate, \(\mathrm{var}^{\mathrm{rel}}\{I_{s}\}\propto\frac{1}{\langle I_{s}\rangle}\).