# A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS
## 1 Introduction  
In recent years, the big data industry has been booming. The combination of big data with emerging information technologies such as virtual reality and automatic driving, relying on the analysis and processing of massive data, has accelerated the development of industries such as medical treatment, transportation, and artificial intelligence, and has even changed the mode of economic development. The explosive growth of data volumes requires faster data processing and transmission. The traditional parallel interface improves the transmission speed by increasing the number of channels or increasing the data rate of a single channel. However, with the continuous improvement of the communication speed, serious crosstalk and coupling will occur between multiple closely connected channels. Furthermore, with the increase in transmission distance and communication rate, the synchronization between parallel channels becomes extremely difficult due to the changes in chip PVT (process voltage temperature) and the uncontrollable deviation in packaging, wiring, and plate. The high-speed serial interface (SerDes) only uses a pair of differential lines for signal transmission, which can enhance its anti-interference ability, resist noise, reduce I/O pins, and solve the synchronization problem, so the serial interface replaces the parallel interface, becoming the modern mainstream interface [1; 2; 3; 4; 5; 6]. A SerDes transmitter converts the multichannel low-speed parallel signal into a high-speed serial signal, which passes through transmission media (optical cable or copper wire), and finally converts the high-speed serial signal back into a low-speed parallel signal at the receiver [5; 6; 7]. In the high-speed transmission of data, the NRZ (non return zero) modulation has a high attenuation in high-speed serial port applications above 112 Gb/s. Therefore, the PAM4 modulation has progressively been replacing the NRZ modulation, and its Nyquist frequency is half of that of the NRZ, which better solves the problem of data errors under a 70 dB strong channel attenuation [5; 8; 9; 10; 11; 12; 13]. The University of California, Los Angeles in the United States proposed a new type of transmitter with an FFE delay unit constructed by LC with a speed of 50-64 Gb/s. FFE with an LC structure can improve the bandwidth of key delay chain and driver and uses a 4:1 MUX to save power consumption [14]. The University of California, Berkeley, proposed an NRZ SerDes transceiver with up to 60 Gb/s speed, using adaptive equalization and offset cancellation techniques to cope with harsh channel conditions [15]. Texas A&M University in the United States proposed a SerDes receiver with a speed of up to 10 Gb/s ADC, creatively combined with the traditional DFE circuit to significantly reduce the power consumption of the SerDes circuit [16]. ESilicon proposed a PAM4 receiver with a rate up to 56 Gb/s, which adopted an ADC+DSP architecture. The architecture used an ADC (analog-to-digital converter) to sample and quantize the data and then used a CMOS logic circuit to implement multi-draw balancing and forward error correction in a DSP (digital signal processor), to alleviate bandwidth degradation and linearity constraints in traditional architectures [17]. Compared with the existing references, the transmitter rate was not high, the PAM4/ NRZ modulation was adopted more often, and the study of the duo-binary PAM4 modulation was concentrated in the optical channel [14; 15; 18; 19]. The transmitter designed in this paper is used in the electrical channel with a rate of 112 Gb/s and adopts the duo-binary PAM4 modulation, which has more concentrated energy and higher bandwidth utilization. The high-speed MUX uses precharging transistors to reduce the jitter of the transmitter, and the drive circuit uses a high-precision DAC architecture to improve the linearity. In this context, a high-speed SerDes is studied in depth. A 112 Gb/s SerDes transmitter is designed based on the duo-binary PAM4 modulation technology.