## 3 Proposed QCA Circuits
### Proposed QCA RAM Cell
The proposed multiplexers show remarkable performance improvements compared with existing majority vote gate-based multiplexers [37; 38; 39; 40; 41] and recent cell-interaction-based multiplexers [42]. \(AT^{2}\) reduced from a minimum of 83% to a maximum of 92% compared with the existing majority gate-based circuit. A cost reduction of 69% or more compared with the latest cell-interaction-based circuit was confirmed. \begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Circuit**} & **Cell Count** & \multirow{2}{*}{**Area (nm\({}^{2}\))**} & **Latency** & **AT\({}^{2}\)** & \multirow{2}{*}{**Crossover**} \\  & **(\# of Fixed Inputs)** & & **(Clock Cycle)** & **(Area \(\times\) Latency\({}^{2}\))** & \\ \hline
[37] & 28 (1) & 24,564 & 0.5 & 6141 & Coplanar \\
[38] & 23 (3) & 24,964 & 0.5 & 6241 & Coplanar \\
[39] & 16 (2) & 13,924 & 0.5 & 3481 & Coplanar \\
[40] & 15 (2) & 15,524 & 0.5 & 3881 & Coplanar \\
[41] & 20 (1) & 13,524 & 0.75 & 7607 & Multilayer \\
[42] & 10 (2) & 7644 & 0.5 & 1911 & Coplanar \\ MXC & 11 (2) & 9604 & 0.25 & 600 & Coplanar \\ MXL & 12 (2) & 9604 & 0.25 & 600 & Coplanar \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Comparison of the performance of 2-to-1 multiplexers. Figure 11: Simulation results of proposed 2-to-1 multiplexers: (a) MXC, (b) MXL. Table 5 is a performance table for QCA RAM cells, comparing recently proposed RAM cells. Compared to circuits [21; 22], which separate stored and output values, the proposed circuit reduces the number of cells by 59.77%, the area by 66.6%, and latency by 57.14% and 40%, respectively. In addition, compared to the circuit in [19], which has the highest overall performance, 40.67% of the cell count and 57.14% of the area are reduced, and the \(AT^{2}\) is reduced by 57.14%. For a more objective performance evaluation, the cost function discussed in reference [23; 43] has been applied. \[Cost_{I}=\left(M^{k}+I+C^{l}\right)\times T^{p},\;1\leq k,\;l,\;p \tag{6}\]  
where \(M\) is the number of majority gates, \(I\) is the number of inverters, \(C\) is the number of crossovers, and \(T\) is the delay of the circuit and \(k,l,p\) are the exponential weightings for  
Figure 12: Simulation results of the proposed RAM cells: (**a**) MXCR, (**b**) MXLR. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline \multirow{2}{*}{**Circuit**} & **Cell Count** & \multirow{2}{*}{**Area (\(\mu\)m\({}^{2}\))**} & **Latency** & **AT\({}^{2}\)** & **Cost\({}_{\text{II}}\)** \\  & **(\# of Fixed Inputs)** & & **(Clock Cycle)** & **(Area \(\times\) Latency\({}^{2}\))** & **Cost\({}_{\text{II}}\)** \\ \hline
[16] & 108 (4) & 0.11 & 1.25 & 0.171875 & 669 \\
[17] & 67 (4) & 0.06 & 1.25 & 0.093750 & 754 \\
[18] & 92 (3) & 0.10 & 1.5 & 0.225000 & 2046 \\
[19] & 59 (6) & 0.07 & 0.75 & 0.039375 & 434 \\
[20] & 75 (6) & 0.10 & 1.5 & 0.225000 & 950 \\
[21] & 87 (7) & 0.09 & 1.75 & 0.275625 & 2781 \\
[22] & 87 (5) & 0.09 & 1.25 & 0.140625 & 950 \\
[23] & 71 (4) & 0.06 & 1.25 & 0.093750 & 859 \\
[24] & 94 (4) & 0.08 & 1.25 & 0.125000 & 577 \\ MXCR & 41 (4) & 0.03 & 1.00 & 0.030000 & 298 \\ MXLR & 37 (4) & 0.03 & 0.75 & 0.016875 & 183 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Comparison of the performance of QCA RAM cells. majority gate count, crossover count and delay, respectively. All circuits compared here are coplanar structures so there is no need to consider the number of layers. However, when a 5-input majority gate and a multiplexer using cell interactions were added, we modified the equation to take these into account. The modified equation is shown in Equation (7). \[Cost_{II}=\Big{(}(M_{3}+F_{1}\times M_{5}+F_{2}\times M_{C})^{k}+I+C^{l}\Big{)} \times T^{p} \tag{7}\]  
where \(F_{1}\) and \(F_{2}\) are the ratios of the number of cells of the five-input majority and the cell-interaction-based multiplexer under consideration to the number of cells of the 3-input majority gate, and \(M_{C}\) is the number of cell-interaction-based multiplexer.