## 2 CMOS and MTJ Technologies Operating at Cryogenic Temperatures
### Related Work  
Cryogenic MTJ-based circuit schemes have gained momentum as a promising solution for enabling reliable and energy-efficient operations for future cryogenic memory systems. [PERSON] et al. introduced a 77 K cryogenic 1 Kb STT-MRAM design using MTJ nanopillars for energy-efficiency computing [42]. In [29; 43], a cryogenic STT-MRAM design operating at 77 K that leverages a DMT device with two reference layers was evaluated. This architecture provides improved energy for read and write operations, as compared to the conventional SRAM scheme. In [28], an STT-MRAM operating at 77 K showed performance and energy benefits enabled by a write trimming system. [PERSON] et al. designed an MRAM based on spin-orbit torque (SOT) operating below 10 K [44]. The SOT-MRAM scheme showed improvements in tunnel magnetoresistance and coercive field, leading to improved reliability for cryogenic computing applications. [PERSON] et al. proposed a cryogenic memory array consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, achieving reliable switching between resistance states with low error rates and energy-efficient operations [45]. Overall, MTJ-based computing architectures operating at cryogenic temperatures offer benefits, such as better reliability through higher TMR, low leakage currents, and improved data retention time. Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTI) Devices and Temperature-Dependent Compact Model  
Figure 2 shows the sketches of the perpendicular (a) STT-SMTJ and (b) STT-DMTJ devices considered in this study. Both devices share a core structure built from ferromagnetic layers separated by thin MgO oxide barriers. For the SMTJ, the oxide barrier of thickness (\(t_{\text{OX}}\)) is sandwiched between two CoFeB ferromagnetic layers: the reference layer (RL) and the free layer (FL). The DMTJ exhibits a more complex structure with two oxide barriers (\(t_{\text{OX,T}}\) and \(t_{\text{OX,B}}\)) separating three ferromagnetic layers: a top reference layer (RL\({}_{\text{T}}\)),a free layer (FL), and a bottom reference layer (RL\({}_{\text{B}}\)). The RLs have a fixed magnetization orientation, while the FL has a variable magnetization orientation. Therefore, the two MTJ structures allow for two stable resistive states, depending on the relative magnetization orientation between RL in the case of the SMTJ (or RL\({}_{\text{T}}\) and RL\({}_{\text{B}}\) for the DMTJ)) and FL. Figure 2 also shows the different resistance states of the SMTJ and DMTJ devices. The SMTJ devices exhibit a low resistance state (LRS) when in the parallel (P) state and a high resistance state (HRS) when in the antiparallel (AP) state. The DMTJ resistance can be modeled as two series-connected resistances, one for each oxide barrier. This translates to different LRS and HRS values compared to the SMTJ device. For this work, the LRS and HRS correspond to bit '0' and bit '1', respectively. To write information into the devices, the spin-transfer torque (STT) mechanism [46] was exploited, which uses spin-polarized current to change the magnetization state. For the SMTJ, the switching between P and AP states occurs when a current exceeding the critical switching current (\(I_{Cp}\) or \(I_{CAP}\), with \(I_{Cp}\) larger than \(I_{CAP}\)) is injected in the proper  
Figure 2: (**a**) Single-barrier magnetic tunnel junction (SMTJ) structure; (**b**) double-barrier magnetic tunnel junction (DMTJ) structure. MTJs feature low and high resistance states (LRS and HRS), corresponding to bit ‘0’ and bit ‘1’, respectively. direction. The two reference layers, with antiparallel magnetizations of the DMTJ, lead to more symmetrical switching behavior and lower switching current compared to the SMTJ [30]. We used the analytical macrospin-based Verilog-A compact models to evaluate the behavior and electrical characteristics of SMTJ and DMTJ devices. These models incorporate the cryogenic temperature dependence of key physical parameters using established equations [47; 48; 49].