## 3 Materials and Methods
### Deep Learning
#### 3.3.2 Recurrent Neural Network (RNN)  
RNN is a deep learning architecture [40] employing values from the preceding step in each loop phase to compute sequential data. Its learning outcomes are significantly more comprehensive than other basic neural network methods. The RNN architecture is primarily described as repetitive since it completes the same task for each element of an array, taking into account the previous outputs [41]. A similar architecture manages historical data during calculation and poses the potential to process the input of any length. The prior input form is recorded and merged with the newly acquired input value through iterative processes, establishing a connection between the newly-obtained input with the previous data in the memory. LSTM and BiLSTM refer to the denomination of the specialized versions of the recurrent neural network. As an RNN architecture, LSTM networks have significant benefits over conventional feed-forward neural networks and RNN. A typical LSTM network consists of various memory blocks called cells. Cell state and hidden state are the two forms transferred to the subsequent cell. The cell is responsible for keeping track of values in memory blocks. LSTM is widely used in ordered-or time-series problems [42] since it has the potential to learn long-term dependencies with its transitional memory mechanism. Six separate formulas provided the fundamental equations of an LSTM cell with a forget gate. The term '\(ct\)' stands for the cell state vector in Equation (1). \[c_{t}=\sigma\left(f_{t}\;*C_{t-1}+\;i_{t}\;*\;\widetilde{C}_{t}\right) \tag{1}\]  
where \(C(t)\) stands for the current time step for the memory cell and \(C(t-1)\) denotes the previous time step for the memory cell. However, the term \(\hat{H}\) is a variable indicating the relationship between forget cell and the output cell. The \(i(t)\) is the output of the forget gate and input gate for the time step \(t\). Just as the term \(ot\), \(\widetilde{c}_{t}\) represents the output gate's activation vector, as illustrated in Equation (2). \[\widetilde{c}_{t}=tanh(x_{t}\;U^{s}+h_{t-1}\;W^{s}) \tag{2}\]  
The term '\(it\)' refers to the input or update gate's activation vector in Equation (3). \[it=\sigma(x_{t}\;U^{i}+h_{t-1}\;W^{i}) \tag{3}\]  
Here, the \(Wi\) and \(Uli\) matrices in the calculation of \(\widetilde{c_{t}}^{\prime}\) are the weights used in the memory cell update process, and the term bc is the bias vector. The \(x(t)\) and \(h(t-1)\) denote the input and previous output vectors. the term '\(ft\)' in Equation (4) denotes the forget gate's activation vector. \[\hat{H}=\sigma\left(x_{t}\;U^{i}+h_{t-1}\;W\right) \tag{4}\]  
Here, \(f(t)\) refers to the forget-gate output for the time step \(t\), and the matrices \(Wf\) and \(Uf\) are the weights used in the forget-gate update process. The term \(bf\) is the bias vector. Equation (5) displays the output gate update formula. \[o_{t}=\sigma\left(x_{t}\;U^{o}+h_{t-1}\;W^{o}\right) \tag{5}\]  
The term \(ot\) represents the output gate's activation vector in Equation (4). Here, \(o(t)\) stands for the output gate's outcome for time step \(t\), and the matrices \(Wo\) and \(Uo\) are the weights used in the output gate update process. The term \(bo\) is the bias vector. The output vector \(h(t)\) of the LSTM is calculated by the formula given in the final Equation (6):  
\[h_{t}=\tanh(C_{t}\;)*o_{t} \tag{6}\]  
The term \(ht\) in the final Equation (6) refers to the output vector of the LSTM unit. Here, \(h(t)\) is the output vector for the time step \(t\), and \(C(t)\) is the current time step for the memory cell. The term \(o(t)\) denotes the output gate [42]. The architecture of LSTM is shown in Figure 1.  
The input gate, output gate, and forget gate are the three main mechanisms that regulate the flow of input and output information in the cell. The terms \(i_{t}\), \(o_{t}\), and \(f_{t}\) depicted in Figure 1 refer to the \(Ct\) and \(\widetilde{C}_{t}\) terms for the operational cell memory states of the network.