## 4 Discussion
In Figure 21, the temporal trends of the signals are shown, obtained providing the plaintext data packets (red box) to the encryption/decryption system every 40.86 ns; this data-rate derives from the clock frequency of 220 MHz, corresponding to 4.54 ns clock period, chosen to comply with the 3 Gbit/s throughput required by the specifications of Wireless Connector system, as calculated below in Equation (5). \[\textit{Data}-\textit{Rate}\textit{or}\textit{Throughput}=\frac{128\;\text{bit}} {9\times\textit{clock}\textit{period}}=\frac{128\;\text{bit}}{9\times 4.54\;\text{ ns}}=3.132\;\text{Gbit}/\text{s}. \tag{5}\]  
The encryption of the data packets is performed in 9.5 clock periods (white box); in fact, the encrypted packets are provided at the output of the encryption block on the falling edge of the clock, after exactly 9.5 clock periods and then acquired by the decryption block on the next rising edge. Afterward, the data packet is decrypted in 9.5 clock periods (blue box) and provided at the output of the decryption block after overall 10 clock periods. Therefore, the encryption and decryption operations last 20 clock periods, which are equal to 90.8 ns, considering a system clock frequency of 220 MHz (Figure 21). In Figure 22, the temporal trends related to the behavioral simulations are shown, with the plaintext data packets provided to the system in each clock period (frequency 220 MHz). The s00_axis_tvalid signal is constantly set, indicating to the receiving block that a new data packet is available at the input, providing encrypted packets on each rising edge of the clock, thus allowing a data rate equal to 28.16 Gbit/s (220 MHz + 128 bit = 28.16 Gbit/s). Finally, the post-implementation simulation of the overall system constituted by the cascade of the encryption (red box) and decryption (blue box) blocks has been carried out (Figure 23a). The simulation has been performed by setting the Explore implementation strategy, provided by the Vivado tool. The screenshots of the Project Manager, obtained after the post-implementation simulation, are shown in Figure 23; a positive WNS parameter, equal to 0.056 ns, is obtained (Figure 23b), as well as the hardware utilization of the overall encryption/decryption system is reported in Figure 23c. In particular, the hardware resource utilization was equal to 15% LUTs, 1% FFs, 1% I/O ports, 1% BUFG, as well as a  
Figure 21: Temporal trends related to the behavioral simulations where plaintext data packets are provided every 9 system clock periods at 220 MHz, corresponding to a data rate of 3.123 Gbit/s. 25% area utilization value relative to the IP Clocking Wizard block, used to generate the system clock, was obtained. Besides, the estimation of the total on-chip power (sum of the static FPGA power and design power) of the combined encryption/decryption system has been obtained from the post-implementation simulation, providing plaintext data packets each clock period, which is equal to 1.77 W, with 26.7 \({}^{\circ}\)C chip temperature, ensuring a thermal margin equal to 73.3 \({}^{\circ}\)C (i.e., temperature limit equal to 90 \({}^{\circ}\)C). Figure 23: Block Design including the encryption (red box) and decryption (blue box) blocks connected in cascade (**a**); screenshot of Project Manager, obtained by post-implementation simulation, using a clock frequency of 220 MHz and Explore implementation strategy, showing the positive WNS parameter (green-dashed box) equal to 0.056 ns (**b**) and the hardware usage of the overall system (**c**). Figure 22: Behavioral simulation with the plaintext data packets (red box) acquired by the system on each rising edge of the clock with frequency 220 MHz and a data rate of 28.16 Gbit/s; the encrypted packets (white box) are obtained after 45.40 ns after receiving them and the decrypted ones (blue box) after 90.80 ns.