## 1 Introduction  
Time-to-digital converters (TDCs) are vital components in numerous scientific applications, such as positron emission tomography (PET) [1; 2; 3; 4; 5; 6], time-of-flight (ToF) image sensors [3; 4; 5; 6; 7], and light detection and ranging (LiDAR) [8; 9; 10]. Especially in ToF imaging and LiDAR applications, high-resolution TDCs affect overall performance. Field programmable gate array (FPGA)-based TDC designs have become notably popular thanks to their programmability and the short times required to generate designs [11; 12; 13; 14; 15; 16; 17; 18; 19; 20; 21; 22]. The tapped delay line (TDL) is the simplest FPGA-based structure in TDC designs. Time resolution and linearity are crucial to FPGA-based TDCs; however, the dedicated elements used in FPGAs often result in a lack of uniformity in delay cells, which in turn can undermine time linearity [12]. Therefore, a great deal of research has gone into the development of calibration methods to overcome nonuniform cell delay in FPGA-based TDL-TDCs [13; 14; 15; 16; 17; 18; 19; 20; 21; 22]. Time resolution and time linearity are crucial issues in any FPGA-based TDC design. In 1997, [PERSON] et al. presented a calibration method for an FPGA-based TDC implemented with a QuickLogic pASIC FPGA device. The TDC can reach a time resolution of 200 ps, and the conversion range of this TDC is 43 ns [13; 14]. Dedicated carry lines of an FPGA are used as delay cells to perform time interpolation within the system clock period and to realize fine time measurements [15]. A TDC with calibration implemented in an Altera EP1K50 TC144-1 FPGA has a resolution of 65 ps; a TDC implemented in a Xilinx XC2V4000-6 BF957 FPGA has a resolution of 46.2 ps. The authors also utilized the dedicated resources of FPGA devices to design TDCs on FPGA platforms [16; 17]. Another factor that affects the time linearity in FPGA-based TDC designs is the presence of ultra-wide bins (UWB) when dedicated resources are used in the FPGA device. Thus, because wave union TDCs divide the original bin size, they can deal with UWB effects and improve the time linearity [18; 19; 20; 21]. However, the wave union method is not applicable to high-end FPGAs, in particular the Xilinx UltraScale FPGA that is manufactured with 20-nm process technology. Therefore, the authors proposed a dual-sampling TDL architecture and a bin decimation method for Xilinx UltraScale FPGAs that could make the delay elements as small and uniform as possible, so that the implemented TDCs can achieve high time resolutions beyond the intrinsic cell delay [23; 24]. Recently, selected, divided, or interpolated versions of the delay bin have become more popular to manage the nonuniform delay cells in FPGA-based TDCs, and thus to improve the time resolution and time linearity [22; 23; 24; 25; 26; 27; 28; 29; 30; 31]. Two-stage inner interpolation methods that employ an eight-phase clock and an equivalent time coding delay line within a 28-nm FPGA chip were reported [25]. Although such methods enable high time resolution, the designs are highly complex. Nonetheless, time histogram bin counts have been used to calibrate nonlinearity in TDL-TDC delay bins [26; 27; 28; 29; 30; 31], and two-sample-sums and two-sample-differences of a quantized histogram can be used to minimize the influence of nonlinear quantization on the histogram [26]. Unfortunately, the quantization-and-nonlinearity minimization method depends on a highly complex mathematical analysis [26]. A multi-path delay line can select the most equal cell as a delay bin in an FPGA device to improve its linearity [27]. A merged delay line was also presented to delay the UWB effect [28]. Unfortunately, the methods in [27; 28] must pre-run the code density test to obtain the time information of each bin, then re-design the TDC according to that time information during the calibration. Thus, the process is remarkably time consuming and impractical, especially in real-time systems.