# A Phase Error Correction System for Bioimpedance Measurement Circuits
## 2 Methods
### PECSD Circuit Design  
Figure 4 illustrates the circuit-level implementation of the PECSD, which comprises a Mirrored Enhanced Howland Current Source (MEHCS), a delay block phase synchronizer, a type II phase detector, and a lock-in amplifier.  
Figure 3: Block diagram of the automatic Phase Error Compensated Synchronous Demodulation system (PECSD).  
Figure 4: Main circuit stages of the PECSD bioimpedance measurement system. showing **(a)** MECHS (b)** Type II phase detector, (c) Phase synchroniser and (d) Lock-in Amplifier.  
To implement the phase synchroniser in Figure 4, the current source is driven by U1, a unity gain single to differential op amp that increases common mode rejection and minimises DC offset [26]. The current source consists of U2 and U3 op amp arranged to provide a Mirrored enhanced Howland current source (MEHCS), ensuring true floating load. As such, the output current flowing through the load impedance Zx and sense resistor Resense is:  
\[I_{out}=g_{m}V_{in} \tag{12}\]  
where, \(g_{m}\) is the transconductance of the Howland current source provided by [27].  
\[g_{m}=\frac{R_{4}}{R_{3}*R_{5}} \tag{13}\]  
U4 and U5 are instrumentation amplifiers for measuring the resultant voltages across Resense and Load. In a closed-loop system, Vsense and V\({}_{\text{in}}\) should ideally be in phase and squared through comparators U11 and U12, respectively. The outputs of U11 and U12 are compared in phase using a type II phase detector involving D-type flip flops U13 and U14 and, subsequently, a delay logic gate U15, which offers just enough delay to overcome FETS U19 and U20 dead zones. U16 simultaneously resets U13 and U14 when the Vsense and V\({}_{\text{in}}\) phases are synchronised. The U13 Q1 output activates a positive charge pump; however, when V\({}_{\text{in}}\) leads, the complimentary U14 Q2 output will also activate a negative charge pump when V\({}_{\text{in}}\) lags Vsense. However, only one of these conditions can occur at a time.  
The type II phase detector sends a square pulse to the microcontroller (U6), which detects phase shifts between Vsense and V\({}_{\text{in}}\) and initiates a response to cancel the phase shift between Vsense and V\({}_{\text{in}}\) by delaying V\({}_{\text{in}}\) for an equivalent phase interval. It achieves this by automatically adjusting the wiper of the digital potentiometer of the all-pass filters U7 and U8. The digital potentiometer further stores the wiper's position in its memory once the required phase compensation is achieved. Multiplication is achieved through a lock-in amplifier mechanism comprising U19-U22. The same procedure is performed in the quadrature demodulation cycle.  
Tables 1 and 2 provide a detailed illustration of the raw data and output variables pertaining to a 1 k\(\Omega\) purely resistive load and an RC load consisting of a 1 k\(\Omega\) resistor and 244 pF capacitor, across a frequency range of 1 kHz-300 kHz. These measurements were obtained for an output current (\(I_{out}\)) of 1 mA. Following Equations (10) and (11), it becomes evident that the phase shift compensation between Vsense and the I &Q demodulation signals had minimal impact on the impedance magnitude, as shown in Tables 1 and 2. A significant difference in load impedance phase was noted at higher frequencies before and after phase compensation, as evidenced by the load impedance values before and after phase shift compensation.