# A Self-Powered UHF Passive Tag for Biomedical Temperature Monitoring
## 2 Architecture of Proposed Self-Powered Passive Tag
### Power Management
#### 2.2.3 LDO Voltage Regulator  
The schematic of the implemented LDO voltage regulator and its open-loop small-signal model are presented in Figure 8a,b, respectively. As shown in Figure 8a, the implemented LDO is made up of an error amplifier (\(m_{1},m_{2},m_{ea}\) and \(m_{n_{1}}\)), a pass-element (\(m_{pass}\)), a feedback network (\(m_{3},m_{4}\)), a load capacitor \(C_{L}\), and a compensation capacitor \(C_{M}\). The load current \(I_{L}\) is modeled as an \(R_{L}\) resistor. The implemented LDO uses the \(V_{I_{TC}}\) and \(V_{REF}\) bias voltages to improve its performance against temperature variation. All transistors operate in the subthreshold region.  
Figure 8b presents the open-loop small-signal model of the LDO used to analyze its steady-state performace and transient stability. The open-loop small-signal model in Figure 8b is obtained by breaking the \(v_{loop}\) node connected to the gate of the left \(m_{ea}\) transistor in Figure 8a. After that, a \(v_{i}\) voltage probe is applied  
Figure 8: LDO voltage regulator. (**a**) Schematic circuit. (**b**) Open-loop small-model signal.  
Figure 7: Current and voltage reference. (**a**) Current reference. (**b**) Voltage reference.  
\(m_{ea}\) transistor and the \(v_{loop}(s)/v_{i}(s)\) transfer function is obtained [56]. In Figure 8b, the \(g_{m_{k}}\), \(r_{o_{k}}\), \(C_{gk_{s}}\), \(C_{d_{lb}}\), and \(C_{sb_{k}}\) are the transconductance, channel resistance, gate-drain capacitance, gate-source capacitance, drain-bulk capacitance, and source-bulk capacitance of the \(k-th\) transistor, respectively. Moreover, the following assumptions were done in order to simplify the small-signal model: \(R_{A}=r_{o_{a}}\parallel[(1/g_{m_{2}})+r_{d_{bs_{1}}}]\), \(R_{\mathrm{O}}=r_{o_{p_{p_{p}}}}\parallel[(1/g_{m_{2}})+(1/g_{m_{4}})]\parallel R _{L}\), \(C_{c}=C_{gd_{2}}+C_{dlb_{2}}+C_{gd_{aa}+C_{d_{baa}}}+C_{gg_{p_{p}}}\), and \(C_{i_{\mathrm{ac}}}=C_{gd_{\omega}}+C_{gg_{a}}+C_{dlb_{3}}+C_{gg_{4}}+C_{dlb_{4}}\). In addition, \(g_{m_{k}}r_{o_{k}}\gg 1\), \(C_{\mathrm{C}}>C_{gd_{p_{p}}}\), and \(r_{o_{k}}\gg r_{d_{bs_{1}}}\). The resulting open-loop small-signal model is shown in Equation (25) where the DC open-loop gain \(A_{v}\) is stated by Equation (26).  
\[\frac{v_{loop}}{v_{i}}=A_{v}\cdot\frac{\frac{C_{\mathrm{C}}C_{M}}{g_{m_{2}}g_{ m_{p_{p}}}}g^{2}+\frac{C_{M}}{g_{m_{2}}}g+1}{C_{\mathrm{C}}C_{M}C_{L}r_{d_{ \mathrm{S}}}R_{b}R_{o}s^{3}+C_{\mathrm{C}}(C_{M}+C_{L})R_{b}R_{o}s^{2}+(C_{M} r_{d_{bs_{1}}}g_{m_{p_{p}}}R_{o}+C_{L}R_{o})s+1} \tag{25}\]  
\[A_{v}=-g_{m_{ca}}R_{B}g_{m_{p_{p_{p}}}}R_{o}\frac{R_{4}}{R_{3}+R_{4}} \tag{26}\]  
As the LDO voltage regulator presents transitions between no-load, \(I_{L}=0\), and full-load, \(I_{L}=I_{L_{max}}\), both cases must be analyzed in order to establish the proper stability criteria. For no-load condition, the load current \(I_{L}\) is equal or near to zero amperes causing a maximum open-loop DC gain as the pass-transistor operates in sub-threshold region. This scenario leads to a dominant pole and two split-apart non-dominant poles. The open-loop transfer function, pole locations, and gain-bandwidth product (GBW) are given by Equations (27)-(29), respectively.  
\[FT_{NL}(s)\approx\frac{v_{loop}}{v_{i}}\approx A_{v}\cdot\frac{\frac{C_{ \mathrm{C}}C_{M}}{S_{m_{2}}S_{m_{p_{p}}}}s^{2}+\frac{C_{M}}{S_{m_{2}}}g+1}{C_{ \mathrm{C}}C_{M}C_{L}r_{d_{\mathrm{S}}}R_{b}R_{o}s^{3}+C_{\mathrm{C}}(C_{M}+ C_{L})R_{b}R_{