# Tailorable and Broadband On-Chip Optical Power Splitter
## 1 Introduction  
Recently, photonic integrated circuits have been intensively investigated for applications in quantum photonics [1], optical interconnection [2], photonic computing [3], and optical communications [4]. Integration of multiple photonic components on a photonic chip requires the development of on-chip photonic integrable components, including waveguides, filters, and optical power splitters. An integrated optical power splitter is an important photonic building block that divides optical power into multiple channels, forms interferometer systems, and taps a small portion of signal [5].  
Several approaches have been developed for on-chip power dividers, including Y-junctions [6], directional couplers [7; 8], and multimode interferometers [9; 10]. Conventional Y-junctions typically have a 1-dB insertion loss and a 3-dB splitting ratio due to fabrication imperfections [11; 12]. In the case of directional couplers, the power splitting can be designed by controlling the coupling length and distance between the two waveguides, but the coupling ratio strongly depends on the input wavelengths [8; 13]. Recently, curved directional coupler and its combination with straight directional couplers show small footprints, low loss, and ultra-broadband power splitting, but they need careful design in coupling regions [14; 15]. Multimode interferometers not only have several advantages, such as relatively small size and high fabrication tolerances, but also have drawbacks, such as wavelength dependence and insertion loss [9; 16]. Since the subwavelength grating can engineer refractive index and dispersion properties, a compact, low loss, and ultra-broadband directional couplers are proposed using its design flexibility [17; 18; 19], but the gratings are intrinsically sensitive to fabrication errors. Furthermore, a 3-dB beam splitter that uses adiabatically tapered waveguides was demonstrated [20] having a low insertionloss (\(<\)0.2 dB), a short coupling length (5 \(\upmu\)m), and negligible dependency on the input wavelengths, but it has a fixed power split ratio of 50%. Even if these types of on-chip power splitters meet some of the performance requirements, it is a big challenge that an on-chip optical power splitter satisfies all of compactness, low-insertion loss, wavelength independence, and tailorability of the split ratio.  
These properties are required not only in classical photonic signal processing but also in quantum photonics. For instance, in quantum photonic integrated circuits, asymmetric interferometers are used to generate time-bin entanglement, but a non-3-dB power splitter is needed due to propagation loss in longer path [21]. In addition, controlled-NOT gate was demonstrated using directional couplers with 50:50 and 70:30 ratios [3]. However, as the directional couplers used in these experiments have considerable wavelength dependence, precise control of fabrication is required.  
In this work, we propose a novel scheme of on-chip photonic power splitters that can meet all the required characteristics of tailorability, wideband, compactness, and low insertion loss. The designed structure is based on 1 \(\times\) 2 interleaved tapered waveguides (1 \(\times\) 2 ITW) on a silicon-on-insulator platform, and a power split ratio can be determined by moving laterally one of the output tapered waveguides, lithographically. An insertion loss extracted from computational simulation results is less than 0.3% even if the split ratio changes from 50% to 1%, and wavelength dependence of the split ratio, as well as the insertion loss, is negligible in the wavelength range from 1.5 \(\upmu\)m to 1.6 \(\upmu\)m. This scheme is close to impeccable power splitters and can be the most promising photonic power divider for photonic integrated circuit systems and quantum photonics.