## 3 Proposed DC-GCDRAM Architecture
### Memory Mode  
Figure 4 details the physical and logical organization of compute-in-memory. The whole memory array comprises bilaterally symmetric two 16 kbit storage blocks with row decoders in the middle. The fundamental organization is 4k-word \(\times\) 8-bit. Inside each 16 kbit storage block, the bitline (BL) switches, BL sense amplifiers (BL-SAs), column decoders, and column gates are placed on the bottom of array, while the XNOR-SAs, activation switches and BL precharges are placed on the other side of array. The population counters are placed over the storage blocks, while the computing logics (CMPLGs) and write drivers (WDRs) are placed under the two adjacent blocks. The read-datalines (RDLs) and write-datalines (WDLs), which are shared by two storage blocks, are used to transfer single-ended 8-bit signals between selected columns and CMPLGs or WDRs. Figure 5 depicts the simplified circuitry of a 16 kbit storage array. During the hold, the BL switches are in an off state, and both WBL and RBL are precharged to V\({}_{\text{DD}}\). Every memory access turns on a row and activates the corresponding BL-SA. The latch-type BL-SA in this design makes use of a reference signal (V\({}_{\text{REF}}\)) that is positioned in-between data '0' and data '1' signals. In Figure 6a, we show the simulated waveforms for read operation. After turning off the BL precharges, the read access begins by activating RWL, causing the RBL level to remain stationary or to discharge. Meanwhile, WBLS and RBLS are initially precharged to V\({}_{\text{REF}}\) and V\({}_{\text{DD}}\), respectively, and then floated by raising nSAPRE  
Figure 4: Compute-in-memory organization. (RDL: read-dataline; WDL: write-dataline; CMPLG: computing logic; WDR: write-driver). to V\({}_{\text{DD}}\). Triggering RS and RSB forwards the RBL signal to RBLS. Before sensing the data, the read BL switches are turned off. Then, the BL-SAs are activated by firing SAP and SAN. Afterward, triggering YR and YRB transfers a full-swing RBLS signal to RDL. The latency from RWL to block SA output (BSA\({}_{\text{OUT}}\)) measures 1.5 ns at the 1.0 V supply. Simulated waveforms in Figure 6b illustrate the write operation. After BL-SAs determine the status of accessed cells, an internal write-back operation follows. To store external data on the cells, the new data for selected columns are driven into WBLSs when YW and YWB are triggered. The BL-SAs toggle if the new contents are different from the accessed ones. Next, WBLs are connected to WBLSs by switching WS and WSB. Then, WWL is fired, allowing the external data to be fully written to the selected cells. In Figure 7, we show the data refresh scheme used in this design. Basic refresh circuitry consists of a refresh controller and a 7-bit address counter with an oscillator. The row address buffers switched by internal refresh signals provide either the refresh address (RFA\(<\)0\(>\)\(-\)RA\(<\)6\(>\)) or the normal row address (A\(<\)0\(>\)\(-\)A\(<\)6\(>\)) to the storage array. If an external signal RF is low, the CIM macro is available for memory or two other mode operations. To enter into the auto-refresh, RF is set to high for 0.96 us or over. This blocks the incoming functional command and initiates a series of refresh cycles for all memory rows, corresponding to simple read and write-back with column gate off. The rise in RF activates a refresh demanding signal RFRSH, then the 7-bit counter begins to increase the address of row to be refreshed one by one. A refresh cycle activates two rows (one from each 16 kbit storage block in Figure 4) at the same time, thus 256 bits are restored for each cycle. Right after the last row refresh, RFRSH is finally reset to low. In this design, a refresh time of 100 us or longer achieves a refresh overhead less than 1%. Figure 5: Simplified configuration of a 16 kbit memory array. Figure 6: Simulations for memory operation (\(\mathrm{V_{DD}}\) = 1.0 V, room temperature): (**a**) read-waveforms and (**b**) write-waveforms.