## 4 Hardware Implementation Design  
The proposed algorithm was implemented at hardware level and a respective system level performance evaluation was carried out. The compression module processes input samples on the fly with a latency of 4 clock cycles. As depicted in Figure 3, a small 16 \(\times\) 16 bit _Input Buffer_ stores the incoming 16-bit samples and propagates them to the compression module when instructed by the _Local Controller_. On system power-up the samples are propagated through the differential datapath comprised by a _Subtractor_ and an _Absolute Calculation Unit_. The absolute value of all samples is used to update a metric table with statistical information and is also used to produce the compressed output. This is the initialization phase of the system.  
When a number of samples equal to the defined block size has been collected, the controller enters in calculations' phase and pauses further sample propagation to the rest of the system. The _Huffman Micro-Processor Unit_ calculates and produces the Huffman (S) table, based on the populated metric table, which will be applied on the next block of incoming data. The custom microprocessor functions with encoded operations are designed so as to optimize this phase. The core of the Huffman algorithm is implemented by performing parallel memory accesses on the 33 \(\times\) 9 bits _Tableful Parallel Memory_ and by un-rolling all nested while and for loops to serial operations. A 512 \(\times\) 36 _Instruction Memory_ drives the micro-processor to execute all Real Time Huffman algorithm calculations which leads to a substantial processing latency. The worst-case processing latency due to the iterative nature of the  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Data Set** & **RT-Huffman** & **LEC (s)** & **ALEC** \\ \hline ecgA04 apnea & +18\% & 7.5 & +30\% \\ ecgB05 apnea & +28\% & 6.7 & +35\% \\ ecgEkgMove & +26\% & 16.8 & +35\% \\ ecgUoP & +11\% & 201 & +131\% \\ eegchD0/7070/mit & +14\% & 18.1 & +34\% \\ eegchD141414 mit & +23\% & 17.8 & +38\% \\ eegF4 UoP & +18\% & 191.9 & +144\% \\ eegOZUoP & +10\% & 198.17 & +124\% \\ \hline \hline \end{tabular}
\end{table}
Table 1: Processing delay performance evaluation.  
Figure 2: Compression rate performance evaluation.  
algorithm is calculated to 4175 clock cycles per block of 500 samples. Once the Huffman (S) table has been calculated, the controller resumes propagation of samples through the differential data-path and S is applied to the next block of incoming samples in order to produce the compressed output. When a number of samples equal to the defined block size has been collected, the calculation phase is activated again and so on.  
In Figure 4, the block data flow with respect to compression of the input data block and the calculations of the S table is depicted. It is noted (indicated with the immediate receipt of the data of the 4 th data block following the 3 rd data block) that if the intermediate interval between the last datum of one block and the first datum of the subsequent is smaller than the time required to perform the S table calculations, the Ready For Data (RFD) signal will go low; then excessive data can be stored in an input buffer until the S table calculations are concluded, and then the compression process resumes.