# Interferences of Electromagnetic Pulses on Microcontroller Units
## 3 Experimental Protocol
### Analysis  
As the pressure of the air gap switch of the power source increased, the interference exhibited an increasing trend. This was true for the tests at each position, because as the pressure of the air gap switch increased, the breakdown voltage increased, and the electric field in the TEM cell also increased, thereby enhancing the interference.  
With the increase of the capacitance, the rising edge of the EMP did not change much, but the FWHM of the EMP increased and the interference increased, suggesting that the EMP interference was related to the action time. The longer the action time, the greater the interference. This phenomenon was mainly due to the cumulative effect of interference on the circuit system.  
The significant difference in interference levels between pin 44 and pin 33 is clearly due to the significant difference in input impedance between these two pins--such as inconsistent parasitic capacitance at the pin inlet and parasitic inductance of the internal leads of the pin--resulting in inconsistent wave impedance of the path. Therefore, there are differences in the reflection and refraction of interference electromagnetic waves, but this is entirely due to the design or manufacturing process of the integrated circuits.  
Due to the randomness of the interference, to evaluate the interference on the MCU at different positions, the data in Tables 1-3 were rearranged and summarized into Tables 4-7. C1, C2, and C3 represent different storage capacitors. The data at different FWHMs of the EMP were compared across the same position and the same pressure (i.e., electric field amplitude). For instance, the value in row 5 and column 3 of Table 4 shows that at 2 atm and with the plate at 270\({}^{\circ}\), pin 34 had the maximum interference amplitude under all three FWHMs.  
From Tables 4-7, the maximum and minimum number of interferences at a certain position were used as the evaluation indices. Pin 34 had the most and least interference when the plate was at 270\({}^{\circ}\) and 90\({}^{\circ}\), respectively. Pin 44 had the most and least interference when the plate was at 180\({}^{\circ}\) and 0\({}^{\circ}\), respectively.  
Figure 9 shows X-ray images of the MCU, which reveals that the internal pins of pin 34 and pin 44 differ by 90 degrees. Figure 10 shows that pin 34 was near the power inlet in the TEM cell when the plate was at 90\({}^{\circ}\). At this point, the interference on pin 34 was the lowest. When pin 34 was close to the load--that is, when the MCU was at 270\({}^{\circ}\)--the interference on pin 34 was the highest. The results suggest that EMI is path-dependent and has strong direction selectivity. The direction selectivity is reflected by the specific internal structure of the MCU. Therefore, the interference to the MCU in the test was related to its position.  
For the convenience of analysis, the data were summarized to compare the interference voltages of the three groups. The results, presented in Table 8, show that the higher the FWHM, the greater the interference to the MCU.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Position (\({}^{\circ}\))** & **1 atm** & **2 atm** & **3 atm** & **4 atm** & **Total** \\ \hline
0 & 0 & C1 & C1 & C1 & 3 \\
90 & C1 & 0 & 0 & 0 & 1 \\
180 & C2, C3 & C2 & C2 & C2 & 5 \\
270 & 0 & C3 & C3 & C3 & 3 \\ \hline \hline \end{tabular}
\end{table}
Table 6: The position at which the interference on pin 44 was the highest.  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Position (\({}^{\circ}\))** & **1 atm** & **2 atm** & **3 atm** & **4 atm** & **Total** \\ \hline
0 & C2, C3 & C2 & C2, C3 & C2 & 6 \\
90 & 0 & 0 & 0 & C3 & 1 \\
180 & 0 & C1, C3 & 0 & C1 & 3 \\
270 & C1 & 0 & C1 & 0 & 2 \\ \hline \hline \end{tabular}
\end{table}
Table 7: The position at which the interference on pin 44 was the lowest.  
Figure 9: Left: X-ray image of the MCU. Right: Enlarged view of the pin leads.