# A 5 Gb/s Optoelectronic Receiver IC in 180 nm CMOS for Short-Distance Optical Interconnects
## 4 Conclusions  
We have presented a CMOS-based optoelectronic receiver integrated circuit (CORIC) optimized for short-distance optical interconnect applications. The proposed CORIC adopts a fully differential architecture with cross-coupled active loads, which significantly enhances the dynamic range while maintaining compactness and energy efficiency. Post-layout simulations by utilizing a standard 180 nm CMOS process verify the performance, showing a transimpedance gain of 53.2 dB\(\Omega\), a \(-3\) dB bandwidth of 4.83 GHz, an input sensitivity of \(-25.9\) dBm at a bit error rate (BER) of \(10^{-12}\), a wide dynamic range of 60 dB, and 33.7 mW power consumption from a single 1.8 V supply, hence demonstrating an excellent tradeoff between speed, gain, power, and integration. It is also noteworthy that achieving a 4.83 GHz bandwidth with a standard 180 nm CMOS process is particularly significant owing to the careful circuit-level optimization including cross-coupled loading. The high-frequency performance is further improved by incorporating a 3-bit continuous-time linear equalizer (CTLE) and an \(f_{T}\)-doubler. The CTLE adaptively compensates for the frequency-dependent losses that occur from PCB traces and interconnect parasitics, ensuring signal integrity across the entire bandwidth. The \(f_{T}\)-doubler operates as an output driver that extends the high-frequency response and provides robust differential drive strength for the subsequent digital processing stages. These features jointly contribute to the CORIC's suitability for high-speed optical communication systems, particularly in scenarios requiring strict power budgets and area constraints. Conclusively, the proposed CORIC architecture provides academic contributions in the fields of high-speed analog/mixed-signal designs and exhibits strong industrial potential. The use of standard 180 nm CMOS technology makes the solution highly manufacturable and cost-efficient, especially when compared to advanced node implementations that require higher mask costs and present yield challenges. The low power consumption and small footprint of the design enable its integration into dense multi-channel transceiver modules, such as those used in optical interconnects within data centers, high-performance computing (HPC) systems, and next-generation optical backplanes. In addition, the monolithic integration of avalanche photodiodes (APDs) significantly simplifies the receiver architecture by eliminating the need for external photodiodes, wire bonding, and complex ESD protection networks. This not only reduces the system complexity and the packaging cost, but also improves the noise performance by minimizing the parasitic inductance and the capacitance. Such compact, scalable integration paves the way for single-chip optical front-end modules or full system-on-chip (SoC) optical transceivers, which are highly desirable in today's rapidly evolving data infrastructure. Given the surging demand for energy-efficient, high-speed, and scalable optical I/O solutions, this work offers a viable and forward-looking receiver architecture. The presented CORIC could serve as a foundational building block in the development of future high-bandwidth, low-power optical communication systems for commercial, industrial, and even aerospace applications, where robustness, cost, and integration are of paramount importance. Conceptualization, S.-M.P. ; methodology, Y.S. and S.-M.P. ; validation, Y.S. ; writing--original draft preparation, Y.S. and S.-M.P. ; writing--review and editing, S.-M.P. ; visualization, Y.S. ; supervision, S.-M.P. ; project administration, S.-M.P. ; funding acquisition, S.-M.P. All authors have read and agreed to the published version of the manuscript. This work was supported by the MSIT (Ministry of Science and ICT), Republic of Korea, under the ITRC (Information Technology Research Center) support program (IITP-2025-RS-2020-II201847) supervised by the IITP (Institute for Information and Communications Technology Planning and Evaluation). Not applicable.