# 25-34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver
## 1 Introduction  
The recent explosive growth of mobile traffic has created a demand for increased bandwidths and faster data rates in telecommunication. As a frequency band candidate for fifth-generation (5 G) communication to solve this traffic increase, not only a band below 6 GHz but also Ka-band communication, especially 28 GHz and 39 GHz, has been attracting attention. Also, for terrestrial-satellite backhaul network communication, 17.7-20.2 GHz for downlink and 27.5-30 GHz for uplink are considered in the Ka-band [1; 2; 3]. Due to the short wavelengths corresponding to these frequency bands, compact phased-array antennas can be realized using wafer-scale, on-chip antennas or printed circuit-board antennas, as well as mm-wave, complementary metal oxide semiconductor (CMOS)-integrated circuit technology [4; 5; 6; 7]. Many studies on the development of communication systems using multi-antenna array structures with mm-wave bands have been reported [8; 9; 10; 11; 12]. The front-end of the phased-array transceiver is usually composed of a single-pole, double-throw (SPDT) switch, low-noise amplifier (LNA), power amplifier (PA), and phase shifters (PS).  
The SPDT switch selects the signal path between the antenna (ANT) and receiver (RX), or transmitter (TX), as shown in Figure 1. The time to transmit and receive is divided by the switch, which is called the time-division duplex (TDD) method, in order to share the antenna with the TXand RX. Since the performance of the switch is critical to the noise figure of the RX, and the output power and efficiency of the TX, low insertion loss and high linearity are required. High isolation is also important, to prevent signal leakage from the TX to the RX. In addition to these characteristics, the area of the chip should be minimized, as many components are employed in a phased array antenna. Although there are many advantages associated with CMOS technology, such as low cost and high levels of integration, some challenges remain in implementing SPDT switches in this manner. The main challenge is achieving high isolation in the off state, and low insertion loss in the on state, simultaneously [13; 14; 15]. The \(\pi\)-network has been widely employed at low frequencies, to enhance isolation, through the addition of shunt switches [16; 17; 18; 19; 20]. However, since these shunt switches add additional parasitic capacitances to the signal path, the magnitude of the insertion loss increases, and the operating frequency decreases. Previous works have attempted to reduce parasitic capacitors by using a silicon-on-insulator (SOI) process or by adapting a switch biasing technique. Thus, resonant switch configurations using isolation enhancement (IE) inductors perform better at mm-wave frequencies [21; 22; 23; 24]. Although the size is larger than \(\pi\)-network SPDT, it can be integrated, and the switch performance can be improved in certain mm-wave bands.  
In this paper, two types of the SPDT switches for Ka-band phase-array transceivers are presented, in which the inductors are employed to enhance insertion loss and isolation by cancelling out the parasitic capacitances. The switches employ two different control methods, one using a single supply voltage, and one with dual supply voltages. The design of the mm-wave switch is detailed in Section 2, along with the results of simulations. The results of experiments performed to characterize the SPDTs are described in Section 3. A conclusion, as well as a summary of this paper, is detailed in Section 4.