## 1 Introduction  
As data rates have increased by 1.5 times every year since 2000, high-speed data communications are required in modern broadband applications to address bandwidth demand. Initially, in 2000, radio frequency applications required a bandwidth of 1-2 GHz for optical time-domain reflectometer applications. To meet modern broadband demand, data rates have increased to 25-30 Gbps, which is more than 75% of previous data communications. Increasing bandwidth must meet multiple challenges including channel loss, high-speed operation, area, equalization, and robustness. For data communication power, in particular, consumption is a very important factor in maintaining high performance. There are several previous studies of 28 Gbps or higher data rates [1; 2; 3; 4; 5]. Those use unrolled decision feedback equalizers to meet critical timing margins, but the unrolled CTLE structure increases the power and die's area. To achieve these challenges, one of the key designs is an analog front-end (AFE) cascading transimpedance amplifier with a continuous-time linear equalizer. Historically, TIAs have been mostly developed for the front-ends of the optical receivers (for example, the families of 2.5, 10, 40,... GB/s). However, their usage is not limited to optical applications, although they have been for a long time the major driving force beyond development towards both lower noise and higher speeds. Nevertheless, in recent decades, advanced TIA designs have become increasingly popular for a variety of applications such as physics and radiation detectors of particles, miniaturized magnetic resonance spectroscopy [2], and vision and biological sensors. Different applications have their own requirements for the main parameters of TIA design. For example, high-speed optical communication circuits have pushed the bandwidth of TIAs in multiple GHz ranges from novel designs with lower power consumption to reduced chip area and minimized noise while operating at significant frequency [6]. Obviously, the front-end TIA is the most critical component of the channel influencing both noise sensitivity and the speed of the overall system. At the output of the linear channel, voltage is provided that can be later used by decision circuits. The second most critical component of the analog front-end block is the decision circuit or equalization circuit as shown in Figure 1. Equalization is typically implemented in both the transmitter and the receiver [7]. Before the channel, it is desirable to \"peak\" the transmitted high-frequency content instead of performing all the high-frequency peaking at the receiver side. On the receiver side, high-frequency peaking degrades the receiver input signal-to-noise ratio (SNR), whereas the transmit side does not. Therefore, within the transmitter, equalization is implemented to supply pre-emphasis of the high-frequency vanguard of bit transitions. In the receiver, equalization is implemented to revive the combined transmitter and channel characteristics towards a reference channel that has no or reduced ISI. Obviously, CTLE in a receiver is intended to equalize the combined characteristics of the transmitter and channel and remove the ISI at the received signal sampling points. The RX CTLE is similar to TX FFE CTLE except the input is an analog signal. The RX CTLE is often called a discrete-time linear equalizer [3; 8]. As an FIR filter, designed to subtract ISI effects from adjacent bits. The output of RX CTLE is further sampled to point per data time interval for data detection. The RX CTLE will only cancel ISI at the data detection sample points. Channel losses or insufficient bandwidth are obstacles to achieving higher data rates in data communications. One solution is changing the signal transformation scheme from two-level pulse amplitude modulation (PAM2), also known as non-return-to-zero (NRZ), to four-level pulse amplitude modulation (PAM4), to double the data rate without increasing the bandwidth [9; 10]. However, PAM4 requires greater system linearity.