# Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices
## 3 NAND Flash Memory Reliability
### Retention after Cycling and SILC  
Data retention specifies the maximum period of time that allows a correct retrieval of stored data, and is determined by the faint but nonzero leakage of electrons from the floating gate. Early experimenters ascribed such leakage to electron tunneling through the dielectric and realized that temperature [160] or bias [161] could be used to accelerate the phenomenon, while devising appropriate design criteria [162; 163; 164]. In particular, it was found that a ten-year retention requirement could be satisfied with a minimum tunnel oxide thickness around 3.5-4.5 nm [165; 56], much thinner than the 7-8 nm usually adopted. However, the oxide thickness has barely scaled over the many Flash technology generations, remaining far away from its theoretical limit, because it was soon realized [166; 70; 167] that repeated P/E cycles led to degradation of the tunnel oxide characteristics, enhanced leakage and worse retention. The enhanced oxide leakage at low fields after electrical stress  
Figure 14: \(V_{T}\) distribution of an MLC array in the presence of RTN. Dashed lines represent the reference levels used during read. Figure 15: \(V_{T}\) pdf at the end of the ISPP operation (**left**) and after a successive read operation (**right**). Results are shown for two values of the ISPP step, \(V_{s1}\) and \(V_{s2}>V_{s1}\). is known as _stress-induced leakage current_, or SILC [168; 169]. SILC has been largely studied on capacitors and described in terms of a trap-assisted tunneling (TAT) process through oxide traps [170; 171; 172; 173; 174; 175; 176; 177; 178; 179] (see Figure 17a for a pictorial view of the process), in agreement with experimental evidence [180; 181]. In the realm of non-volatile memories, SILC can lead to charge loss/gain from/to the floating gate after stress and to retention errors. To keep this contribution negligible, the oxide thickness of Flash cells has barely scaled with the technology generations, going from about 10 nm in the first prototype [3] to about 7-8 nm in the latest nodes [182]. However, experimental data [183; 184; 185; 186; 187; 188] have demonstrated that, even if the SILC is reduced, there is a small number of cells that can exhibit a high leakage after stress, in analogy with the statistical behavior of RTN. An example of this effect is reported in Figure 16, where thin-oxide (6.5 nm) NOR Flash arrays were cycled heavily (\(10^{4}\) P/E cycles) before being subjected to positive (left) or negative (right) oxide field to induce a \(V_{T}\) shift [189]: note the distribution tails made up of cells featuring an enhanced leakage with respect to the main part of the distribution, whose shift is due to the intrinsic FN tunnelig current. This enhanced leakage, called _anomalous SILC_, has been also identified as a trap-related phenomenon, because of its low activation energy [188; 189] and fluctuations resulting from capture/emission processes [185; 190]. However, a two-trap assisted tunneling process (2 TAT) has now been invoked to explain the experimental data of individual cells [191; 192], as depicted in Figure 17c. From this view, a picture of the SILC distribution in a Flash array can be built, assuming a statistical distribution of stress-generated oxide defects (Figure 17b): those cells that happen to have two traps close enough to allow significant tunneling will be affected by anomalous SILC [193; 194], while the majority will only experience SILC or the FN tunneling current. Figure 18 shows an example of gate leakage current of two cells affected by anomalous SILC compared with the 2 TAT model predictions (left), and (right) the statistical distribution of SILC at a given control-gate bias for different oxide thicknesses, again compared with results of the statistical model. From there, reliability extrapolations can be performed to estimate the number of failures.