# A Self-Testing Platform with a Foreground Digital Calibration Technique for SAR ADCs
## 2 Proposed Self-Test Platform
### MATLAB Verification  
MATLAB is used to simulate and verify the proposed self-testing platform technique and calibration method and build the behavior model, which includes the 12 bit SAR ADC, RDFT computation, signal generator, and proposed calibration. In addition, a 1% capacitor mismatch, 2 mV DC offset, thermal noise, sampling jitter and switch nonlinearity are adopted in the 12 bit SAR ADC model to demonstrate the proposed calibration. Generally, the backgate effect of the switch transistor is the main source of its resistance nonlinearity. So, the input-dependent switch transistor can be defined as:  
\[R=\frac{1}{\mu C_{\text{ox}}\left(\frac{W}{L}\right)\left[V_{\text{DD}}-V_{ \text{th}}\right]}, \tag{7}\]  
In this work, the parameters of the sampling switch are determined by the virtual process, so the backgate effect value of this switch transistor is:  
\[R_{\text{p}}=\frac{1}{86\times 10^{-6}\left(0.18\right)\left[1.8-\left(-0.5 \right)\right]}\approx 0.911k, \tag{8}\]  
\[R_{\text{n}}=\frac{1}{387\times 0^{-6}\left(0.18\right)\left[1.8-0.5\right]} \approx 0.358k, \tag{9}\]  
It is worthily noted that the body effect problem is not considered in this issue. In this work, the switch model given by using the MATLAB Simulink tool is the transmission gate (pmos and nmos) architectures, and then we further determine the switch nonlinearity error according to the virtual CMOS process parameter. After putting these parameters into Equation (7), we can process the performance analysis of the SAR ADC under the conditions of a 1% capacitor mismatch, 2 mV DC offset, thermal noise, sampling jitter and switch nonlinearity error.  
Figure 4a shows the simulation result. It can be easily observed that the distortion deteriorates the ADC performance in the simulation result with a 5 Hz input frequency at a sampling rate of 126.26 Hz. Furthermore, the third harmonic distortion tone is \(-55.29\) dB without calibration and \(-80.97\) dB with calibration (Figure 4b). The signal-to-noise and distortion (SNDR) can be improved from 48.32 dB to 65.65 dB, while the effective number of bits (ENOB) is improved from 7.73 bits to 10.61 bits. However, the proposed calibration method cannot compensate for the error of the thermal noise, sampling jitter and sampling switch nonlinearity, which generated the harmonic distortion at the output power spectrum, so the ADC such as SNDR and spurious-free dynamic range (SFDR) cannot achieve the ideal ADC performance. Figure 5 shows the time domain result, and it is clear that the signal can be improved when the proposed calibration method is applied.  
Figure 6 shows the simulation result with capacitor mismatch only and analyzes the performance of the ADC before/after calibration. According to the simulation result, the third harmonic distortion tone is \(-65.59\) dB without calibration and \(-90.81\) dB with calibration. The ENOB can be improved from 9.92 bits to 11.11 bits. In addition, Figure 7 shows the simulation result with 2 mV DC offset only and analyzes the performance of the ADC before/after calibration. According to the simulation, the proposed calibration method can reduce the DC offset error and enhance the performance of the ADC.  
Figure 4: Simulation result from the MATLAB tool (**a**) without and (**b**) with calibration. (Total third harmonic distortion, THD3; Spurious-free dynamic range, SFDR).  
Figure 5: Time domain result with/without calibration.  
Figure 6: Simulation result from the MATLAB tool with capacitor mismatch only (**a**) before and (**b**) after calibration.