# The Quanta Image Sensor: Every Photon Counts
## 5 Jot Device
### Jet Device with JFET SF  
It was noticed that although the TPG jot yielded a lower read noise than the PG jot, it actually had higher voltage noise. This effect is believed to be caused by a smaller SF gate area in the TPG jot. As the SF gate capacitance can dominate the total FD capacitance in the PG jot, smaller SF area can provide a higher CG, but also makes the SF more susceptible to the random fluctuation caused by interface traps and leads to increased \(1/f\) noise and RTS. With this tradeoff between gate capacitance (that is, CG) and SF voltage noise, further reduction of read noise becomes challenging. The scatter plot in Figure 10 suggests that further reduction of SF size will not allow us to achieve 0.15 e\(-\) r.m.s. read noise even with CG of 1 mV/e\(-\). Generally, to achieve the ultimate goal of high accuracy photoelectron counting, more innovation is needed for the jot device to reduce noise or increase conversion gain.  
A one-transistor single-electron field effect transistor (SEFET) was proposed as a possibly jot device by earlier work at Samsung [5]. This device used direct collection of photoelectrons in the gate of a junction field effect transistor (JFET) to modulate the current flow of the transistor with CDS performed by resetting the gate back to a fully depleted state. The goals were both small jot size and use of a JFET with high CG and low channel noise to implement low read noise. Only preliminary simulations were performed on the device before the QIS work was abandoned at Samsung.  
A jot device with an in-jot JFET SF has been explored with TCAD to address the dilemma in PG jets [23; 26]. The doping profile of this device is shown in Figure 14. In this device, FD is the n-type doping well located underneath a p-type shallow channel in the JFET SF, and it also functions as the gate of SF. As photoelectrons are transferred from SW to FD, the potential change in FD modulates the depletion region width in the channel, so as to affect the effective channel depth. With the JFET working as a SF, the source (SRC) is biased by a current source and the drain (DRN) connected to ground. Working in saturation mode, the source voltage would follow the gate (FD) voltage. In the PG jot device with a MOSFET SF, FD is connected to the gate of SF through metal wire, and in order to form an Ohmic contact, FD needs to be heavily doped. In this device, since FD is merged with the gate of SF, no metal connection is needed, so the doping concentration of FD can be much lower, which helps reduce the depletion capacitance between FD and substrate. Also, in a MOSFET SF the gate capacitance is relatively large as a result of the extremely thin gate oxide, but in the JFET SF it is replaced by a much smaller junction capacitance between gate and channel. To further reduce the FD node capacitance, a punch-through reset diode is used in this device. Under this mechanism, FD would be reset when a positive pulse is applied on reset drain (RD). Comparing to CIS pixels with punch-through reset [51; 63] taking advantage of the small FWC needed for QIS application, the reset state RD voltage can be much lower (e.g., 2.5 V), and FD would be reset to about 1 V to provide enough FWC. As a result of the reduction in FD capacitance, the JFET jot yields a CG of 1400  
Figure 14: (**a**) 3D doping profile of JFET jot device from TCAD simulation; (**b**) Cross-section doping profiles of JFET SF region.  
according to TCAD simulation. Similar to a conventional JFET, this device gate does not interact with channel on the surface interface, which could lead to reduced \(1/f\) noise and RTS. Other JFET-based readout devices are also under investigation. Generally, the features of high CG and potentially low noise makes this device a promising candidate to achieve the desired 0.15 e\(-\) r.m.s. or less read noise.