## 3 The Proposed SET Hardened LDO Regulator
### Analysis  
A comparison before and after the implementation of the hardened design of \(MN6\)-related circuits is shown in Figure 6.  
The two ends of each resistor \(R_{split}\) are symmetrically connected to \(MN6_{-}(n-1)\), \(MN7_{-}(n-1)\), \(MP4_{-}(n-1)\), \(C1_{-}(n-1)\), and \(MN6_{-}n\), \(MN7_{-}n\), \(MP4_{-}n\), \(C1_{-}n\), and the  
Figure 5: Symmetrical multi-path splitting (SMPS) regulator, with a split factor \(n=2\). Figure 6: (**a**) Unhardened \(MN6\) related circuit; (**b**) symmetrical multi-path splitting (SMPS) circuit-related \(MN6\). electric potentials at both ends are \(V_{G(n-1)}\) and \(V_{Gn}\). In the absence of SET, that is, when direct current (DC) is stabilized, both ends of \(R_{split}\) have the same electric potential because of the completely symmetrical circuit structure, and no current passes through \(R_{split}\). As mentioned above, the number of splits \(n\) must be a power of two. When \(n=2\), the bias voltage of \(MN7\_1\) is provided by \(V_{\text{G1}}\), and the bias voltage of \(MN7\_2\) is provided by \(V_{\text{G2}}\). When the drain of \(MN6\_1\) is affected by a single particle, the voltage fluctuation occurs, and this voltage fluctuation will change the current \(Itail\_1\) of \(MN7\_1\). To analyze the propagation of this fluctuation in the circuit, we give the equivalent circuit of SMPS, as shown in Figure 7a. Note that the small-signal equivalent circuit of the \(MN7\_n\) is not shown in the figure, because the change in the \(MN7\_n\) bias voltage is the main concern. \(R_{eq}\) is the equivalent resistance of \(MP4\_n\) and \(MN6\_n\), and \(C\) is the equivalent capacitance of C1\(\_n\) and each transistor combined. When the drain of \(MN61\) is injected with the same SET model as in Section 2, the current generated by the SET will cause voltage fluctuation \(\Delta V_{G1}\) at \(V_{G1}\). Then, the voltage fluctuation at \(V_{\text{G2}}\), \(\Delta V_{\text{G2}}\) is  
\[\Delta V_{\text{G2}}=\frac{R_{eq}//\frac{1}{sC}}{R_{eq}//\frac{1}{sC}+R_{sp}}= \frac{1}{1+sCR_{sp}+\frac{R_{sp}}{R_{eq}}}\cdot\Delta V_{G1} \tag{9}\]  
\(R_{sp}\) is short for \(R_{split}\). It can be seen that SET-induced voltage fluctuation at \(V_{\text{G2}}\) can be significantly reduced by splitting the transistor and by adding the resistor, reducing the fluctuation of \(I_{tail\_2}\). If the value of \(R_{split}\) is set to be small, the equation can be simplified to  
\[\Delta V_{\text{G2}}=\frac{1}{1+sCR_{sp}}\cdot\Delta V_{G1} \tag{10}\]  
This is the same as the equation in Figure 7b, so we use the simplified circuit shown in Figure 7b in the following analysis. If we split the circuit into four parts (when split factor \(n=4\)), the voltage fluctuation of each stage is gradually reduced. Figure 8 shows the equivalent circuit when \(n=4\). Figure 8: Small-signal-equivalent circuit diagram associated with \(MN6\) in SMPS when split factor \(n=4\). Figure 7: Small-signal equivalent circuit diagram associated with \(MN6\) in SMPS when split factor \(n=2\) (**a**) \(R_{eq}\) presents the equivalent resistance of \(MN6\) and \(MP4\). (**b**) Ignored transistor-equivalent resistance. In Figure 8, with the same voltage fluctuation at \(V_{\text{G1}}\), the voltage fluctuation at \(V_{\text{G2}}\) is  
\[ \begin{split}\Delta V_{\text{G2}}&=\frac{[(R_{sp}+ \frac{1}{s\text{C}})//\frac{1}{s\text{C}}+R_{sp}]//\frac{1}{s\text{C}}}{[(R_{sp} +\frac{1}{s\text{C}})//\frac{1}{s\text{C}}+R_{sp}]//\frac{1}{s\text{C}}+R_{sp} }\cdot\Delta V_{\text{G1}}\\ &=\frac{1+3s\text{C}R_{sp}+(s\text{C})^{2}R_{sp}^{2}}{1+6s\text{C }R_{sp}+5(s\text{C})^{2}R_{sp}^{2}+(s\text{C})^{3}R_{sp}^{3}}\cdot\Delta V_{ \text{G1}}\end{split}  \tag{11}\]  
The voltage change at \(MN6\_3\) is  
\[