# Design of the Converter Prototype for Powering the Hydrogen Electrolyzer
## 3 Constant Current Source Control Algorithm
\[T_{cyk}=N_{pos}\cdot T_{pos}+N_{neg}\cdot T_{neg} \tag{18}\]  
A full-bridge inverter (Q3-Q6, Figure 10) generates the required waveform, enabling bidirectional current flow by switching Q3 and Q6 for positive pulses or Q4 and Q5 for negative pulses. It can also switch to high or low-impedance states [14]. During the \"zero interval\", switching transistors in the left (Q3, Q4) or right (Q5, Q6) branches discharges double-layer capacitance via Q4 and Q6 diodes in positive pulses, complicating control. Q1 and Q2 were added to address this: Q1 closes the current path during the \"zero interval\", and Q2 handles it during the \"active interval\". Switching transistors in the correct order with defined timing is necessary for maintaining a constant conductive path. During the current pulse's rising edge, transistor Q2 is turned on 20 ns ahead of the full bridge part of the inverter, and Q1 is turned off with a 20 ns delay. Similarly, during the current pulse's falling edge, transistor Q1 is turned on 20 ns ahead, and Q2 is turned off with a 20 ns delay. This control method creates a 40 ns time window during which transistors Q1 and Q2 are conductive simultaneously, preventing the conductive path's disappearance on constant current source output [28]. The theoretical scheme of the inverter's transistor switching is shown in Figure 11.  
Figure 10: Principle circuit diagram of the inverter. Figure 5.0 Simplified steady-state equivalent model of the electrolyzer. Considering the component's parameters, the maximum power loss [28] of the transistor if duty converges to 100% is described by Equations (19)-(24). In the inverter, three transistors are turned on simultaneously [20]. The total power loss of the inverter transistors is then 6.44 W [21,22]. Figure 5.1  
Figure 5.2  
Figure 5.3  
Figure 5.4  
Figure 5.5  
Figure 5.6  
The same method used in the buck converter was used to determine the temperature of the transistor junctions in the inverter. According to Equation (25), at a duty cycle close to 100% and an ambient temperature of 25 \({}^{\circ}\)C, the semiconductor junctions heat up to a maximum of 74.3 \({}^{\circ}\)C. The surface temperature simulation results are shown in Figure 5.7  
Figure 5.8  
Figure 5.9 Principle of converter switching. T\({}_{\text{cyk}}\) is the sum of all periods during one working cycle of the inverter, representing a carrier signal in which positive and negative pulses are superponed. \(D_{\text{cyk}}\) is then the duty, which represents the ratio between the time of generation of positive pulses and \(T_{\text{cyk}}\); see Equation (26). Figure 5:0  
Given that the required period depends on the number of pulses, so it can approach times that exceed the maximum possible period when using the \(CLK\) = 120 MHz clock cycle, it is possible to variably set the frequency divider for the time base with the \(CLKDIV_{cyk}\) parameter. If the \(PRD_{cyk}\) value exceeds 216, the division ratio is automatically recalculated. Therefore, the value of the \(PRD_{cyk}\) and \(\zetaMPA_{cyk}\) registers will be as shown in Equations (27)-(29). The carrier signal defines the time when positive or negative pulses are generated. Positive pulses are generated in the case of a positive value, and vice versa. The values for setting the \(PRD_{pos}\) period and the \(\zetaMPA_{pos}\) cycle define the PWM parameters of the positive pulses of the inverter. See Equations (30) and (31). Figure 5:1  
Figure 5:2  
Figure 5:3  
Figure 5:4  
Figure 5:5  
The TRIP zone generates control signals for the \"active\" and \"zero intervals\". If both control signals for the positive and negative pulses are in a low state, then a \"zero interval\" is generated. If any of the signals is in a high state, an \"active interval\" is generated. Figure 13 shows a whole converter control diagram. Figure 5:6 PCB surface temperature simulation of the inverter. All control signals must be brought to a safe state in the event of a fault.