# The Challenges of Advanced CMOS Process from 2D to 3D
## 2 Lithography of Nano-Scaled Transistors
### Challenges in EUV Lithography  
EUV lithography (EUVL) enables to use only a single mask exposure instead of double or quadruple exposure. There are still three issues to deal with this technique: power source, resists and mask infrastructure [14; 15].  
The highest hurdle to implement EUV for mass production is to provide the light source 13.5-nm that enables economical production capacity of the exposure tool. Recent publications show that a power of ~200 W is needed for 125 wafers with 300-mm size per hour. Nowadays, the source issue is considerably mature and several tools are now available from the vendors that provide >80 W at the wafer level but this still is not enough for large scale manufacturing.  
One of the critical technical issues of EUVL is the development of resist material which has high resolution and high sensitivity as well as low line-edge roughness and low outgassing simultaneously [16; 17].  
To improve throughput in high volume manufacturing, the resist sensitivity to the 13.54 nm wavelength radiation of EUV needs to be improved, while the line-width roughness (LWR) specification has to be held to low single-digit nm [18]. With a 250 W source and 25 mJ/cm\({}^{2}\) resist sensitivity an EUV stepper should be able to process ~100 wafer-per-hour (WPH). This allows an affordable use of EUVL which matches with other lithography technologies.  
Though resist line-edge roughness is generally governed by chemical processes (chemical shot noise and acidic diffusion), but the replication of the mask pattern roughness and replicated surface roughness or photon noise will still play a significant role when the pattern dimensions become constantly smaller [19].  
As EUVL continues to move towards high-volume manufacturing, the availability of defect-free reflective mask has been one of the most critical challenges in EUVL [20].  
EUV's patterned masks work in reflective mode. These masks introduce new materials and surfaces that may cause to particle adhesion and cleaning [5], therefore pellicle is needed to protect the mask during use of EUV scanner to avoid the risk of particles adhesion. However, there are still some remained issues for EUV mask with pellicle such as stress from pellicle mounting may cost  
\begin{table}
\begin{tabular}{c c} \hline \hline Metrology & Better overlay measurement \\  & Better alignment measurement \\ \hline \multirow{4}{*}{Wafer} & Reduce wafer warping from previous process steps \\  & Reduce chucking induced wafer distortion \\  & Reduce thermal distortion of wafer from exposure \\  & Correct higher-order overlay errors \\  & Eliminate mask contribution \\ \hline \multirow{4}{*}{Mask} & Reduce pattern placement errors on mask \\  & Reduce mask chucking unflatness in scanners \\ \cline{1-1}  & Reduce pellicle induced mask distortion \\ \cline{1-1}  & Eliminate mask all together \\ \hline \hline \end{tabular}
\end{table}
Table 2: Approaches to improve overlay accuracy.  
overlay error and limit the mask inspection to actinic light in addition to the pellicle absorption which attenuates the precious EUV power.