# The Quanta Image Sensor: Every Photon Counts
## 6 Low-Power and High-Speed Readout Circuits
### Stacked QIS  
A stacked QIS addresses the limited bandwidth problem of the source-follower amplifiers in the pixels or jets. In the stacked QIS approach, more than one substrate or layer could be used to implement the readout circuits. These layers are stacked over each other with bonding interconnections. To readout the jets, the readout and image processing circuits are implemented on the separate substrates.  
A stacked QIS may consist of a billion jets which are organized as an array of M row and N column jets [23]. A cluster of jets is defined as a sub-array of m rows and n columns of jets. Figure 17 shows one example of a simplified schematic of a cluster of jets, their analog readout circuits and chip-level signal or image processing units. In each cluster, the RS switches turn on and off sequentially and only one RS switch is connected to the column bus in a cluster at a time. During the selection of one jet, the reset and signal voltage levels are stored on the correlated double sampling (CDS) unit. A differential CTA amplifies the signals stored in the CDS on the level which is bigger than input referred offset and input referred noise of the ADC. All the clusters function in parallel. ADC can be single-bit or multi-bit, based on the readout structure of the entire image sensor system. After quantization of the signal by the ADC, simple digital processing is done on the digital signal by image processor (IP1) and the output is saved in a memory. The simple digital process can be an adder or a digital convolver. The next ADC output, which is the quantized output of the subsequent jet, is summed or convolved with the value stored in the memory. This process continues until all the jets in the cluster have been readout. At this moment, the value stored in the memory, and all other clusters memories are transferred to a chip-level image processor for further processing. After reading one cluster of jets, the clusters readout is re-done for the next frame. By using this method, the bandwidth of the columns in clusters are wide enough to produce thousands of frames per second while consuming very low-power.  
As an example, in a gigajot, 1000 fps QIS with 16:9 aspect ratio, with cluster size of 32 (m) \(\times\) 32 (n), there are 42,000 columns (N) and 24,000 (M) rows of jets and 984,750 clusters as 750 row and 1313 column.  
In this system there are 984,750 current sources, CDSs, SAs, ADCs, IP1s, 256-bit memories and one chip-level image processor. The sampling rate of the CDS, SA, ADC, IP1 and memory is 1 MSa/s. Considering 2 W as the power budget for entire chip, 0.5 W may be consumed in chip-level image processing and pad frame, and the rest of 1.5 W budget provides almost 1.5 \(\upmu\)W per cluster. Using a more advanced CMOS process such as a 45 nm technology node, charge transfer circuits in the analog domain and sub-threshold regime operation in the digital domain, we estimate it is possible to design the blocks for each cluster to consume less than 1.5 \(\upmu\)W power.  
It should be mentioned that by using a digital kernel and memory, the output data rate can be significantly reduced, although post-readout processing flexibility is reduced. In the above example, if no image processing was implemented on-chip then the output data rate is about 1 Tb/s; whereas by using simple digital kernels in each cluster, the output data rate could be reduced, for example, to about 8 Gb/s. Using a 3 rd stacking layer for chip-level image processing could reduce the output data rate to similar data rates as in conventional cameras.