## 1 Introduction  
Time-to-digital converters (TDCs) are applied to various areas of research such as laser distance meters, high energy physics, and medical application [1; 2; 3; 4; 5]. In positron emission tomography (PET), TDCs are indirectly used to reduce the position of positron emissions [6]. To meet the particle identification requirements of high counting rate and high time resolution in the PET, TDCs must provide high measurement speeds and high measurement precision [7]. For decades, compared with TDCs based on Application Specific Integrated Circuits (ASICs), TDCs based on Field Programmability Gate Arrays (FPGAs) have been developed rapidly due to the advantages of shorter development time and higher flexibility. The common technique in an FPGA-based TDC consists of the coarse counter and the time interpolator [8; 9]. Generally, the coarse counter is obtained by the direct count of a system clock. Recent studies have demonstrated that there are three main methods to implement the time interpolator, such as Vernier delay line (VDL) [10; 11], multiple clock phases (MCPs) [12; 13], and a tapped delay line (TDL) [14; 15; 16]. The VDL-TDC utilizes two similar clock frequencies to measure the time interval. However, it is not suitable for high speed measurements to be used with a long dead time. In 2019, a VDL-TDC achieved 28 ps precision and 602 ns dead time through two ring oscillators [10]. The guideline of the MCP-TDC is that the hit is sampled by N channels of clocks with different phase shifts. Nevertheless, it is hard to obtain a higher resolution because the number of clock phase shifts does not exceed 16. An MCP-TDC structure with 256 channels, 56.2 ps precision, and 4.3 ns dead time was designed in the paper [17]. VDL-TDCs and MCP-TDCs are not suitable for high speed and high precision measurements because of their long dead time and poor precision measurements. The TDL employs the delay elements of the FPGA as a time interpolator. With the advancement of FPGA manufacturing technology, the intrinsic propagation delay becomes smaller and the TDL-TDC becomes the best choice for a high-speed and high-precision time interpolator. The critical issue in the TDL-TDC is the severe bubble errors on the FPGA fabricated with advanced process technology [18]. To solve this problem, one technology that can be used is to reorder the taps according to the static timing analysis (STA) [19]. The real sequence is not consistent with the STA due to the clock slew, thus the bubble problem is not completely solved by reordering the taps. Another improvement is using bin realignment to reorder the taps [20], but it is quite complicated because it requires at least two cycles for the FPGA synthesis. The non-uniformity of delay elements caused by process variation and mismatch in the TDL-TDC is another considerable problem. The scale and linearity of the delay elements in the TDL determine the time precision. The intrinsic propagation delay reflects scale, whereas the differential nonlinearities (DNL) and integral nonlinearities (INL) represent the linearity. The average delay method [21] and the bin-by-bin calibration methodology [22; 23; 24] were proposed to improve linearity. Recent studies have found that the bin-by-bin calibration is the most suitable approach for a TDL-TDC. In 2021, a 26.04 ps precision and 125 M samples/s TDC was design by using bin-by-bin calibration [25]. However, that manuscript did not introduce many details about the calibration, and it was not clear that the bin-by-bin calibration was carried out using software or hardware. Moreover, it was not verified by experiments that the sample rate reached 125 M. To improve the precision and sample rate, the bin-by-bin calibration needs to be online and automatic in the hardware. In this work, the thermometer code with bubble errors is converted to the binary code through the ones-counter encoder, as it could be naturally used for global bubbling error correction.