# Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
## 3 Bit-Cell External Driver Design
### Static Body Biasing Structure and Performance  
The dynamic body biasing circuit, as shown in Figure 10, represents a sophisticated technique employed to regulate the body terminal of a semiconductor device by fixing it to a specific voltage, depending on the operational requirements of the system. This method is particularly useful in modulating the electrical properties of transistors, allowing for optimized performance during different operational modes. In the context of the bit-cell architecture, this circuit is designed to alter the body voltage of the transistor N5 dynamically, based on the intended operation, thus contributing to power efficiency and enhancing the performance of the system.  
Figure 8: Write driver schematic.  
Figure 9: Write driver simulation result.  
The functionality of the dynamic body biasing circuit is governed by the MODE signal, which determines whether the bit-cell is engaged in memory access operations or computational tasks. When the MODE signal is set to 0, the circuit operates in memory mode, enabling the system to perform conventional read and write operations. In this mode, the output signal M of the body biasing circuit is set to a fixed voltage, referred to as Vbias, which is typically 0.6 V. This voltage is applied to the body terminal of transistor N5 within the bit-cell, optimizing its threshold voltage and power consumption for memory access tasks. By lowering the body voltage during memory operations, the dynamic body biasing technique reduces leakage currents and enhances the stability of the memory cell during read and write cycles, ensuring reliable data storage and retrieval. Conversely, when the MODE signal transitions to 1, the system enters computation mode, where the bit-cell is used to perform in-memory computation tasks, such as multiplication and accumulation (MAC) operations. In this mode, the output signal M is set to the supply voltage VDD, which raises the body voltage of transistor N5 to the maximum voltage level. Applying VDD to the body terminal of N5 during computation mode serves to reduce the transistor's threshold voltage, thereby increasing its switching speed and enhancing the overall computational efficiency of the bit-cell.  
This dynamic adjustment of the body voltage depending on the operational mode is crucial for achieving high-performance computations without compromising the energy efficiency of the system. The use of a dynamic body biasing circuit enables fine-grained control over the electrical characteristics of transistor N5, allowing the bit-cell to adapt its behavior to the varying demands of memory and computational operations. This approach not only optimizes the power consumption of the bit-cell but also improves its responsiveness during computational tasks, contributing to the overall performance of the memory array in compute-in-memory (CIM) architectures. The versatility of the dynamic body biasing technique makes it a valuable tool in the design of energy-efficient, high-performance memory systems, particularly in applications such as AI and machine learning, where both memory access and computation are critical.