# Analysis and Optimization of Output Low-Pass Filter
## 5 Experimental Validation of CL Filter Design  
The experimental validation used two CSI prototypes (Table 5) to evaluate the effectiveness of the proposed CL filter design methodology. Prototype 1, using filter configuration FC 4 with open-loop control, showed a total harmonic distortion of 21.2% (Table 6). The comparison shows the difficulty of meeting grid standards without proper harmonic filtering and control. On the other hand, prototype 2 had 7.2% current THD with an optimized CL filter and feedforward control. This substantial THD reduction showed that an improved CL filter design with an efficient control could reduce the THD significantly even though the THD was still slightly higher than 5% Australian Standards limits [11] for the optimized filter. As a result, the performance differences among the prototypes showed the need for optimized filter design and advanced control strategies to meet the grid requirements. Future research will concentrate on integrating advanced closed-loop control to further minimize THD. Table 6 shows the output filter types, parameters, and current THD results for three loading conditions. The first prototype's results are compared to the second prototype. The CL filter arrangement of the first prototype exhibits series damping resistance, similar to FC 4, due to the autotransformer in the experimental setup. Figure 21: The power loss due to damping resistance is analyzed for various total harmonic distortion (THD) values in relation to \(C_{n}\), \(f_{c}\), and \(Q\), specifically under rated output power conditions. \begin{table}
\begin{tabular}{l c c} \hline \hline
**Parameter** & **Prototype 1** & **Prototype 2** \\ \hline Rated maximum input power (\(P_{0}\)) & 82 W & 164 W \\ Input current for \(P_{0}\) (\(I_{0}\)) & 4.5 A & 4.5 A \\ Input voltage (\(V_{CELL}\)) & 17.5 V & 35 V \\ DC link inductance (\(L_{DC}\)) & 82 mH & 192 mH \\ DC link inductance energy storage (\(E\)) & \(\approx\)10 mJ/W & \(\approx\)12 mJ/W \\ DC link inductor resistance (\(R_{LDC}\)) & 1.3 \(\Omega\) & 0.33 \(\Omega\) \\ Filter inductance (\(L_{F}\)) & 0.2–0.3 mH & 2.9 mH \\ Filter capacitance (\(C_{F}\)) & 100–600 \(\mu\)F & 21 \(\mu\)F \\ Filter inductor resistance (\(R_{L}\)) & 0.3 \(\Omega\) & 0.16 \(\Omega\) \\ Filter damping resistance (\(R_{D}\)) & 0.3–0.5 \(\Omega\) & 44.5 \(\Omega\) \\ PWM switching frequency & 4 kHz & 4 kHz \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Specifications of the two CSI prototypes. Figure 22 shows the grid-connected voltage and current waveforms. They were obtained from both simulation and experimental measurements using the optimized CL filter (configuration FC3). The simulation was validated throughout the design process by the close correlation between the simulated and measured waveforms. The low-pass output filter's phase delay caused significant components in the output current around its resonant frequency. The combination of PWM harmonics resulted in a little higher THD than the 5% limit. This can also be seen in Figure 23.  
Figure 23 shows some harmonic distortion present in the output current of the CSI with the optimized CL filter, which used the baseline filter parameters. Open-loop control yielded a total harmonic distortion of 8.1% (see Figure 22), considerably exceeding the grid connection requirement limit of 5% with the pure grid connection. Despite the use of feedforward control, THD was still higher than permitted at 7.2%. This shows that effective harmonic filtering requires a robust closed-loop control strategy. This study focused on the optimization of the CL filter design through the use of a damping resistor. The design technique can be used with several control algorithms, including the PR control described in Section 1. As a result, this CL filter design method tries to reduce total harmonic distortion while additionally reducing losses and ensuring grid compliance.