# Reduced Complexity Sequential Digital Predistortion Technique for 5G Applications
## 2 Sequential Digital Predistortion Using Under-Sampled Feedback Signals
### Proposed Sequential Digital Predistortion  
Two-box based digital predistorters have been widely used for the linearization of wideband power amplifiers exhibiting strong memory effects [9]. In fact, these models typically result in better performance than their single-box counterpart while requiring a lower number of coefficients. In conventional two-box models, the static and the dynamic nonlinearity functions are derived concurrently from a single set of measurements. The flow chart of such process is depicted in Figure 2. First, the input signal is applied to the PA, and the corresponding output signal is acquired. The input and output baseband complex waveforms are then used to perform accurate delay estimation and alignment with a sub-sample delay resolution. This is essential to cancel out the propagation delay between the input and output waveforms, and accurately derive the instantaneous gain of the amplifier. Following this delay estimation and alignment step, the time-aligned input and output waveforms are used to identify the look-up table corresponding to the memoryless predistortion sub-function. Later, and depending on the structure of the two-box network, the signals at the input and output of the remaining predistortion sub-function are generated. This data de-embedding process is then followed by the identification of the memory polynomial predistortion sub-function. This step completes the identification process of the predistortion function. The obtained DPD is then applied to linearize the device under test. Depending on the performance of the synthesized digital predistortion, the update of the predistortion function may be triggered (if the DPD performance does not meet the requirements) or not (if the DPD performance meets the requirements). The proposed S-DPD uses the reverse TNTB structure introduced in [23] along with an enhanced identification approach that allows for the effective use of under-sampled feedback signals. The TNTB predistorter architecture, presented in Figure 3, is made of a memory polynomial function followed by an LUT function. As per the conventional DPD identification process depicted in Figure 2, only one characterization is performed. This characterization, labelled as Characterization #1 in Figure 3, is used to synthesize the two sub-functions of the DPD model by applying the identification process of Figure 2.  
Figure 1: Frequency content of amplifier’s input and output signal for a five-tone input signal and a third order polynomial model: (**a**) input signal; (**b**) output signal. In the proposed approach, two characterization steps are performed. As shown in Figure 3, the first characterization step includes only the power amplifier, and uses the input and output baseband waveforms of the power amplifier to synthesize the LUT predistortion function. During the synthesis of the LUT DPD, accurate delay estimation is used. However, a reduced sampling rate is adopted in the feedback path. In fact, even though such reduction will lead to sub-optimal and slightly inaccurate memoryless DPD sub-function, the resulting residual distortions will be addressed and compensated for during the second characterization step. In this second characterization step, the system to be characterized is made of the LUT DPD as well as the PA (as shown in Figure 3). This system has a mildly nonlinear behavior since the LUT was designed with the objective of reducing the PA distortions. Therefore, reduced sampling rate in the feedback path will not introduce any significant errors since the bandwidth of the signal at the output of the partly linearized system (LUT DPD + PA) is expected to be significantly narrower than that of the PA alone. During the second characterization step, coarse delay estimation and alignment is performed. This implies that the delay resolution will be equal to the sampling period of the signals. This reduces the complexity associated with accurate delay estimation and alignment.