## 2 Device and Methodology  
The devices used in this study are shown in Figure 1. Figure 1a illustrates the structure of the device. The piezoelectric layer is aluminum nitride (AlN) doped with 20% scandium, with a thickness of 1 \(\upmu\)m. Mo electrodes are placed on both sides of the piezoelectric layer, and the bottom structural layer is 4 \(\upmu\)m thick silicon. The diameters of the back cavity of the PMUTs used in this study are 600 \(\upmu\)m and 1000 \(\upmu\)m, respectively. Physical images of the front and back sides of these two sizes are shown in Figure 1b. The diameter of the piezoelectric layer is designed as 78% of the diameter of the back cavity, following previous work [23]. The PMUT fabrication process in this paper follows the standard SOI (silicon-on-insulator) manufacturing process, as shown in Figure 2. The PMUTs designed in this study were manufactured on an 8-inch silicon-on-insulator (SOI) wafer with a 400 nm buried oxide (BOX) layer in the clean room. The piezoelectric stack has a total thickness of 4 \(\upmu\)m, deposited on a low-resistance (100)-oriented Si substrate. Before device fabrication, SOI wafers were sequentially cleaned to remove surface particles, native oxide layers, organic contaminants, and metallic impurities. This process minimizes the impact of particulate contamination on device performance and fabrication. After cleaning, laser marking was performed to label the wafers for subsequent processing steps. In the first step, a 300 nm layer of silicon dioxide (SiO\({}_{2}\)) was deposited using plasma-enhanced chemical vapor deposition (PECVD) at 400 \({}^{\circ}\)C. This layer serves as an insulating dielectric layer to prevent leakage and compensate for thermal stress from subsequent deposition steps. Figure 1: (**a**) Schematic of the device structure. (**b**) Front and back images of two PMUTs with different back cavity sizes. Figure 2: Process flow of the device. (**a**) BOX wafer. (**b**) Thin-film deposition. (**c**) Thin-film etching and metalization. (**d**) Backside etching. Then, an optimized recipe was used to deposit the Mo/Al\({}_{0.8}\)Sc\({}_{0.2}\)N/Mo piezoelectric stack in a single process. Before deposition, the wafer was pretreated in a vacuum under a nitrogen atmosphere at 450 \({}^{\circ}\)C for 5 min, followed by a 7 s physical etch to remove surface impurities and residual moisture. The AlSc\({}_{0.096}\)N layer was used as a seed layer to promote the (002)-oriented growth of the subsequent Al\({}_{0.8}\)Sc\({}_{0.2}\)N layer, reducing surface roughness and ensuring high-quality deposition. The piezoelectric layer was patterned using a 400 nm SiO\({}_{2}\) hard mask deposited via PECVD. The high scandium content in Al\({}_{0.8}\)Sc\({}_{0.2}\)N results in by-products such as ScCl\({}_{3}\) with high sublimation temperatures (\(\sim\)900 \({}^{\circ}\)C ), making dry etching relatively slow. To optimize the etching angle and improve etching selectivity, an inductively coupled plasma (ICP) system (Omega@ etch system from SPTS, Newport, UK) was used. Pre-etching with boron trichloride (BCl\({}_{3}\)) and argon (Ar) was performed to remove surface oxides, improving the main etch process. The process was carefully controlled to stop precisely at the bottom Mo layer, minimizing over-etching and improving yield. PECVD was used to deposit a 200 nm SiO\({}_{2}\) layer, followed by etching to create vias connecting the top and bottom electrodes. Subsequently, a 1 \(\upmu\)m AlCu layer was deposited using physical vapor deposition (PVD) and patterned. The AlCu film was etched in a Cl\({}_{2}\) environment, followed by the immediate removal of dry resist to prevent etching by-products from reacting with moisture to form HCl, which could corrode the interconnection lines. The wafer was thinned to 400 \(\upmu\)m and flipped for back-side processing. Deep reactive ion etching (DRIE) was employed using the Bosch process to fabricate the resonant cavity of the PMUT. To achieve high aspect ratios, the membrane was released in a stepwise etching process.