# High Precision Control System for Micro-LED Displays
## 2 Control System Architecture  
Figure 1 shows the micro-LED display's control structure. The control system consists of the interface control, video processing, image segmentation, image data transmission, control signals generation, correction and memory management. The video decoding module uses the high-definition multimedia interface (HDMI) receiver to produce the RGB data and video timing to be sent to image segmentation. Subsequently, the data are sent to the correction model, which includes gamma correction and brightness correction. The corrected data are input to RAM for memory management. One of these four FPGAs serves as the master, and the remaining three operate as dependents. The master FPGA is responsible for global control and part of the PWM data, while the three dependents generate the PWM data. In order to implement the control of the 24 \(\times\) 46 array, the number of I/O pins of the FPGA needs to be calculated. This process involves adding the number of pins necessary for 10-bit analog voltage signal generation to those required for control signal generation. The number of I/O pins required to generate the 10-bit analog voltage signal can be estimated as follows: m1 = 3 \(\times\) 10 \(\times\) n. Here, n is the number of columns in the micro-LED display's array. We can determine the number of I/O pins by substituting n = 24 into the above equation: m1 = 3 \(\times\) 10 \(\times\) 24 = 720. The control signals consist of CLK1, CLK2, IN, NM and EM. It should be noted that the chip used to generate these signals requires 2 I/O pins. We estimate that the number of I/O pins required to generate the control signals is 10: m2 = 3 \(\times\) 5 = 10. And then the total number of I/O pins can be calculated as follows: m0 = m1 + m2 = 720 + 10 = 730. But as the conventional FPGA do not have a sufficient number of I/O pins, we presented a new architecture to implement the 24 \(\times\) 46 Micro-LED displays. Therefore, we proposed a new architecture to implement 24 \(\times\) 46 Micro-LED displays using an XC7A200T FPGA. The panel is implemented by stitching the video data. Figure 1: The micro-LED displays control structure. A state machine is designed via Verilog programming (Vivado 2019.1) to realize video interception. Each FPGA intercepts a portion of the micro-LED displays area. The CLK1, CLK2, IN, NM, EM, SWEEP and 1-6 columns of PWM data are generated by the master FPGA. Similarly, the 7-12, 13-18 and 19-24 columns of PWM data are generated by the FPGA_2, FPGA_3 and FPGA_4. The 4 FPGA are spliced together in the manner shown in Figure 2.  
Figure 3 shows the timing diagram of the micro-LED, and Table 1 shows the voltage range of these signals [12; 13; 16; 17]. These control signals are generated by the control system. The control signals, namely CLK1, CLK2, IN, NM, EM and comparison SWEEP, are generated by the generation module. The CLK1, CLK2 and IN are outputted to the GOA circuit to generate the scan signals row by row. The NM and EM are the timing control signals used for the TFT. Square wave signals of the desired voltage range are output by controlling the single-pole double-throw (SPDT) switch chip. Figure 4 demonstrates the control of the desired voltage range of the control signals through the SPDT switch. \begin{table}
\begin{tabular}{c c} \hline
**Signal** & **Value (V)** \\ \hline CLK1 & \(-8\)–\(8\) \\ CLK2 & \(-8\)–\(8\) \\ IN & \(-8\)–\(8\) \\ NM & \(-8\)–\(8\) \\ EM & \(-8\)–\(8\) \\ SWEEP & \(0\)–\(9\) \\ DATA & \(0\)–\(8\) \\ \hline \end{tabular}
\end{table} 
Table 1: Design parameters of the control signal. Figure 3: The timing diagram. Figure 2: The control scheme of four FPGAs. Figure 5 shows the pixel circuit with the analog PWM operation [16; 17]. When \(PWM+\Delta SWEEP>VREF\), the micro-LED starts to emit light. Afterwards, \(SWEEP\) will gradually decrease, and if \(PWM+\Delta SWEEP<VREF\), the micro-LED ceases emitting light.