# Solution-Processed CdTe Thin-Film Solar Cells Using ZnSe Nanocrystal as a Buffer Layer
## 3 Results and Discussion
The X-ray photoelectron narrow scan (XPS) of Zn 2p and Se 3d spectra levels are presented in Figure 2d, which implies the formation of the ZnSe composite. The thickness of the ZnSe NC buffer layer and the annealing temperature have great impact on the performance of NC solar cells, as shown in Figure 2e, f. To compare device performance with different thicknesses of ZnSe NC, all the samples are prepared at the same conditions and annealed at 350 \({}^{\circ}\)C with CdCl\({}_{2}\) treatment after five layers of CdTe NC are deposited. We found that the \(J_{\mathrm{sc}}\) increases from 3.58 mA/cm\({}^{2}\) to 10.35 mA/cm\({}^{2}\) when ZnSe thickness increases from 25 nm to 110 nm and decreases to 5.61 mA/cm\({}^{2}\) at 125 nm, which is significantly lower than the thickness among CdTe/CdSe or CdTe/CdS NC solar cells [10; 19]. By contrast, the thickness of the ZnSe NC buffer layer has significant effects on the \(V_{\mathrm{oc}}\), FF (fill factor), and PCE of NC solar cells. The efficiency of the NC device is increased from 0.38% to 1.93% when the thickness of ZnSe is increased from 25 nm to 110 nm. In addition, PCE decreases when ZnSe is thicker than 110 nm. Figure 2: _Cont._  
The best device is obtained when ZnSe is 110 nm with a \(J_{\rm sc}\) of 10.35 mA/cm\({}^{2}\), a \(V_{\rm oc}\) of 0.56 V, a fill factor (FF) of 33.3%, and a PCE of 1.93%. We observed that low series resistance (\(R_{\rm s}\)) is obtained when the ZnSe device has a \(\sim\)110 nm measurement, which shows that a satisfactory diode performance was obtained. Devices with thin or thick ZnSe NCs show low performance, which may be due to inadequate coverage or a higher thickness with a large series resistor. Annealing has a significant effect on the film and junction quality of NC solar cells. Solar cells are probably affected by changes in the film compactness, junction quality, and any defects existing in the ZnSe/CdTe interface. In the previous report, it was found that the annealing temperature has a significant effect on the CdTe/CdSe NC solar cells. In this study, the influence of the annealing temperature on CdTe/ZnSe device performance is investigated. The \(J\)-\(V\) curves of the CdTe solar cells with 110 nm ZnSe annealed at different temperatures are shown in Figure 2f while the detailed parameters are listed in Table 1. The inset of Figure 2e,f show the typical \(J\)-\(V\) curve of one device expressed in logarithmic coordinates. CdTe will grow into a larger size (from several nm to \(\sim\)100 nm) after CdCl\({}_{2}\) annealing, which has been reported in the literature [23]. The formation of larger CdTe grain will reduce grain boundaries and improve carrier collection probability. At a low annealing temperature of 300 \({}^{\circ}\)C, the device performance degrades notably due to the low parallel resistance (\(R_{\rm sh}\)) and the high series resistance (\(R_{\rm s}\)). This can be attributed to the imperfect growth of CdTe NC (the grain size of NC is small compared to NC treated at high temperature) at low temperatures, which leads to a large number of defects in the CdTe NC thin film and an increase in the carrier recombination. We also found that device annealing at a higher temperature of 400 \({}^{\circ}\)C also results in low device performance due to the decreased \(V_{\rm oc}\) and FF. This may be attributed to the enlarged voids and oxidation of CdTe at high temperatures, which is consistent with the previous report [12]. The solar cells with the ZnSe NCs buffer layer annealed at 370 \({}^{\circ}\)C exhibits the best device performance, which includes a \(J_{\rm sc}\) of 11.94 mA/cm\({}^{2}\), a \(V_{\rm oc}\) of 0.63 V, a FF of 40.79%, and a PCE of 3.07%. This PCE value is \(\sim\)36% lower than that of the CdTe/ZnSe thin-film solar cells prepared by vacuum technology [28]. In the case of PbS CQDs solar cells, it was found that smooth and low defects NC thin film can be prepared by using the ligands exchanging strategy [37].