## 1 Introduction
### Simulation Results of Proposed HG-SIQBC
#### Modes of Operation  
For the positive cycle, to obtain a voltage level of 5 \(V_{dc}\), the switches S\({}_{1}\) and S\({}_{3}\) of the H-bridge are kept in the ON state, and the switches S\({}_{5}\)-S\({}_{9}\) are also turned on to produce the positive level of the output voltage. The equivalent circuit for this mode is shown in Figure 17a. Figure 17b shows the equivalent circuit of stage II operation of a multilevel inverter. In this stage, to obtain the voltage level of 4 \(V_{dc}\), the switches S\({}_{1}\) and S\({}_{3}\) of the H-bridge are kept in the ON state, and the switches S\({}_{5}\)-S\({}_{8}\) are also turned ON. Here, the diode connected in an antiparallel manner with S\({}_{9}\) is forward-biased, and the current flows through it. From Figure 17c, a voltage of 3 \(V_{dc}\) is obtained by turning ON the switches S\({}_{1}\) and S\({}_{3}\) of the H-bridge and the switches S\({}_{5}\)-S\({}_{7}\). The current flows through the diodes associated with S\({}_{8}\) and S\({}_{9}\) switches. To obtain the voltage of 2 \(V_{dc}\), the switches S\({}_{1}\) and S\({}_{3}\) of the H-bridge are in the ON state, and the bidirectional switches S\({}_{5}\)-S\({}_{6}\) are also turned ON. The diodes connected in antiparallel with S\({}_{7}\), S\({}_{8}\), and S\({}_{9}\) become forward-biased due to the flow of current passing through it. The equivalent circuit for this mode is shown in Figure 17d. To obtain a positive level voltage \(V_{dc}\), the switches S\({}_{1}\) and S\({}_{3}\) of the H-bridge are in the ON state and the bidirectional switch S\({}_{5}\) is also turned on to produce a positive level of the output voltage. The diodes connected with the switches S\({}_{6}\), S\({}_{7}\), S\({}_{8}\), and S\({}_{9}\) are in conduction mode due to the flow of current through them. The equivalent circuit for this mode is shown in Figure 17e.  
Similarly, the negative cycle operation occurs with S\({}_{2}\) and S\({}_{4}\) in the ON condition. The equivalent circuit for this mode is shown in Figure 18a-e.  
Figure 16: Circuit configuration of proposed multilevel inverter.  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline
**Voltage Levels** & **S\({}_{1}\)** & **S\({}_{2}\)** & **S\({}_{3}\)** & **S\({}_{4}\)** & **S\({}_{5}\)** & **S\({}_{6}\)** & **S\({}_{7}\)** & **S\({}_{8}\)** & **S\({}_{9}\)** \\ \hline
5 \(V_{dc}\) & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 1 \\
4 \(V_{dc}\) & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 0 \\
3 \(V_{dc}\) & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 0 & 0 \\
2 \(V_{dc}\) & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 \\ \(V_{dc}\) & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 \\
0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ \(-V_{dc}\) & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ \(-2\) \(V_{dc}\) & 0 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 \\ \(-3\) \(V_{dc}\) & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 \\ \(-4\) \(V_{dc}\) & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 1 & 0 \\ \(-5\) \(V_{dc}\) & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 1 & 1 \\ \hline \hline \end{tabular}
\end{table}
Table 5: Switching sequence for proposed MLI.  
Figure 17: (**a–e**) Equivalent circuit for different modes during positive cycle of output voltage.  
Figure 18: _Cont_.  
The pulse pattern waveform and the output voltage waveform simulated in MATLAB/SIMULINK are given in Figure 19.  
The pulse pattern for switches S\({}_{1}\)-S\({}_{4}\) is shown on the first four axes of the figure, followed by the pulse patterns of switches S\({}_{5}\)-S\({}_{9}\). The waveform shown on the last axis describes the output voltage of the 11-level inverter.