## 5 Conclusions  
This study presents a detailed analysis of an integrated DC-DC synchronous buck converter using IISB's 2 \(\upmu\)m 4H-SiC CMOS technology, emphasizing the design and performance under various operating conditions, such as different loads, output voltages, and temperature analyses. Regarding the overall operation of the system, it functions as expected for a buck converter, indicating the successful integration of the gate drivers with the power transistors at the design level. In Table 6, some characteristics of the DC-DC synchronous buck converter are presented along with other reported DC-DC buck converters. Examining the efficiency results under varying load conditions, the converter operates within a range of 50 mA to 500 mA total output current, maintaining an efficiency greater than 80%. Additionally, the converter can operate with output voltages between 3.3 V and 12 V, achieving a minimum efficiency of 70% and a maximum of 84.8% at 25 \({}^{\circ}\)C. At high temperatures, the converter improves its efficiency without the need for control adjustments. Moreover, there is potential to increase efficiency at high temperatures by adjusting the dead times, achieving a maximum efficiency of 89.6% at 295 \({}^{\circ}\)C.  
To the best of the authors' knowledge, this work presents the first circuit design exploration focused on power-integrated circuits using the early access 4H-SiC technology provided by Fraunhofer IISB. This contribution opens up new opportunities for future implementations and novel applications in applied sciences, particularly within the context of harsh environment integrated circuits, where the unique properties of this technology can offer significant advantages. Future work will involve integrating a temperature sensor with a look-up table that contains data on gate driver and power switch propagation delays, allowing for a temperature-dependent dead time adjustment system. Additionally, the simulation results will need to be experimentally validated, including characterizing passive component losses and considering manufacturing process errors. Conceptualization, C.A.R. and J.M. ; software, A.M. ([PERSON]), M.S., C.R. and F.T. ; formal analysis, A.M. ([PERSON]) and F.T. ; investigation, A.M. ([PERSON]) and F.T. ; resources, C.A.R., J.M. and M.R. ; writing--original draft preparation, A.M. ([PERSON]) and F.T. ; writing--review and editing, C.A.R., J.M., A.H.W.-V., J.G., M.R., M.M., A.M. ([PERSON]), M.S. and N.C.; visualization, A.M. ([PERSON]) and C.A.R. ; supervision, C.A.R. and J.M. ; project administration, C.A.R. and J.M. ; funding acquisition, A.M. ([PERSON]), C.A.R. and J.M. All authors have read and agreed to the published version of the manuscript. \begin{table}
\begin{tabular}{c c c c c} \hline \hline  & **This Work** & [51] & [52] & [53] \\ \hline Technology & 2 \(\upmu\)m 4H-SiC CMOS & GaN MIS-HFETs & 180 nm Si CMOS & SiC JFET/SiC Diode \\ \hline Integrated & Yes & Yes & Yes & No \\ \hline Temperature [\({}^{\circ}\)C] & [25; 295] & [25; 250] & [\(-\)40, 175] & 150 \\ \hline Efficiency \% & [84.8; 89.6] \({}^{a}\) & - & - & 96 \\ \hline Input voltage/output voltage [V] & 20/3.3–12 & 15–25/2.5–20 & 12–45/5 & 140–240/48 \\ \hline Output current [A] & 0.3 & - & [0, 1] & 5 \\ \hline Switching Frequency [kHz] & 75 & 100 & 200 & 100 \\ \hline \hline \end{tabular} \({}^{a}\) Efficiency @\(V_{e}=12\) V between 25–295 \({}^{\circ}\)C.  
\end{table} 
Table 6: Comparison of the proposed DC-DC synchronous buck converter. **Funding:** This research was funded by AC3E (ANID/BASAL/ AFB240002); ANID + FONDECYT Initiation Research Project 11240947; ANID + FONDECYT Regular Project 1240537; ANID/FONDAP/ 1522A0006; ANID + FONDECYT Postdoctoral Project 3220714; and by the Direccion de Postgrado y Programas, Universidad Tecnica Federico Santa Maria, Valparaiso, under grant PIIC-019/2024. **Institutional Review Board Statement:** Not applicable. **Informed Consent Statement:** Not applicable.