# Thermal Interaction and Cooling of Electronic Device with Chiplet 2.5D Integration
## 1 Introduction  
Moore's Law has driven the electronics industry for over 55 years. However, in recent years, semiconductor processes are nearing their physical constraints. The cost of the monolithic system-on-chip (SoC) is rising as integrated circuit process technology continues to evolve and design complexity increases [1, 2]. Chiplet heterogeneous integration offers a cost-effective alternative to SoC design, with many benefits such as intellectual property (IP) reuse, quick time-to-market, and less risk and cost [3, 4]. The chiplet architecture involves dividing a larger monolithic SoC into smaller chiplets and integrating them into a system [5]. Currently, 2.5D and 3D integration are mainly utilized to package chiplets, and several motivate packaging technologies have been developed. TSMC's Chip-on-Wafer-on-Substrate (CoWoS) is a typical 2.5D package which integrates multiple chips via an interposer [6]. Other 2.5D packages include Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology [7]. In 3D integration, two or more dies are directly stacked vertically by micro-bumps or hybrid bonding technology, such as Intel's Foveros and TSMC's System on Integrated Chip (SoIC) technology [8, 9]. Compared with the 3D integrated chip, the 2.5D integrated chip has lower heat accumulation and multiple chips are stacked side by side on the interposer mounted on the substrate [10]. To improve the computing performance of the heterogeneous integration system, the performance of a single chiplet is improved by laying out more processing units and then integrating multiple chiplets together, which will generate more heat during operation. For example, Intel's newly released GPU chip Ponte Vecchio in 2022 integrates 47 chiplets belonging to five process nodes via EMIB and Foveros packaging technology, with a thermal design power (TDP) of up to 600 W [11], and Intel's SoC-based system Xeon W-3365 chip released in 2022 with a TDP of only 270 W [12]. AMD's Instinct MI300X GPU, released in 2023, has a TDP of up to 750 W and includes 12 chiplets [13]. Based on the performance evolution needs, the TDP of GPUs integrated by chiplets will continually increase in the next five years. The increased TDP strongly influences the functionality and stability of chips and integrated systems, making thermal management critical. Therefore, it is of great significance to develop suitable and efficient cooling technology for high-power chiplets. Common HPC cooling technologies include the following three schemes: jet cooling, spray cooling, and microfluidic cooling. In contrast to other technologies, microchannel cooling stands out for its structural simplicity and cost-effectiveness, while near-chip microfluidic cooling is superior in terms of structural complexity and cost and is suitable for chiplet 2.5D integration [14]. Transistor feature size reduction no longer meets the demands of AI and HPC, and more chiplets must be integrated in a package; the pitch of the chiplets will decrease, and high-density integration will cause considerable thermal interaction between multiple chiplets. For the integration with two or more chiplets, a single value of thermal resistance cannot explain the interactions between chiplets; thermal resistance matrixes are needed. Unfortunately, existing thermal resistance matrixes are not suitable for chiplet heterogeneous integration and only apply to multiple heat sources on a single chip [15]. For multiple heat sources in a monolithic chip, the superposition strategy is a useful tool for predicting temperatures of multiple heat sources and has been applied in the thermal management process. According to the superposition strategy, the temperature distribution caused by multiple chips can be linearly superimposed from temperature profiles with each chip functioning individually [16; 17]. [PERSON] et al. experimentally verified the accuracy of the superposition strategy by fabricating multiple hotspots on one chip [18]. [PERSON] et al.