## 1 Introduction  
With the rapid development of electronic technology, circuit-partitioning algorithms have been widely applied in circuit design to divide large circuits into smaller, more manageable modules, playing a significant role in integrated circuit design, system optimization, and high-performance computing [1, 2, 3]. A well-designed circuit-partitioning algorithm can not only improve the efficiency and reliability of the circuit but also reduce design time and costs. The evaluation of circuit-partitioning algorithms depends primarily on two metrics: the number of cut edges and load balancing. Many heuristic algorithms are commonly used to find approximate solutions [4, 5]. For example, the spectral bisection algorithm [6] achieves high-quality partitioning by computing eigenvectors and eigenvalues, but its high computational complexity limits its feasibility for large-scale systems. The spectral multi-way partitioning algorithm [7] further refines partitioning granularity. The KL algorithm [8, 9] optimizes partitioning by swapping vertices to achieve load balancing. Later, the FM algorithm [10] introduced a single-point movement strategy and a bucket list structure to significantly reduce complexity. The rapid development of machine learning theory has led to the widespread application of intelligent computing methods in the field of circuit partitioning. These intelligent computing methods include genetic algorithms [11, 12, 13, 14, 15], particle swarm optimization algorithms [16, 17], bird flock algorithms [18], and others. [PERSON] [19] proposedan efficient local optimization graph-partitioning method based on genetic algorithms to improve the graph-search capability. [PERSON] and [PERSON] [20] proposed an intelligent partitioning model based on simulated annealing to solve the graph-partitioning problem using adaptive representations and objective functions. [PERSON] [21] proposed a solution to the maximum partitioning problem based on the ant colony algorithm, significantly optimizing the partitioning results for interconnected microgrids. In recent years, multi-level partitioning algorithms [22; 23] have gained widespread attention for their ability to improve computational efficiency when handling large-scale circuits. Some common multi-level partitioning tools include Metis [24] and hMetis [25]. Many researchers have proposed improvements to multilevel partitioning algorithms. [PERSON] and [PERSON] proposed a circuit-clustering method based on edge separability and applied it to multilevel circuit partitioning [26]. [PERSON] and [PERSON] [27] proposed a connectivity-based clustering algorithm and applied it to VLSI circuit partitioning. [PERSON] [13] proposed a coarse partitioning algorithm based on betweenness centrality clustering. [PERSON] proposed the stream-based Metis partitioning method [28; 29] to address computational resource limitations for ultra-large-scale circuits. The complex network-partitioning problem is usually represented using a hypergraph model [30]. Compared to traditional undirected graphs, hypergraphs allow a single edge to connect multiple vertices. To address the partitioning problem of large-scale undirected hypergraphs, many efficient and mature hypergraph-partitioning tools have emerged, such as hmetis, Patoh, and KaHyPar [31; 32; 33]. In addition, some studies [34; 35] have proposed improved methods based on Directed Acyclic Graphs (DAGs) within the framework of multi-level partitioning. [PERSON] et al. [36] proposed a multi-level acyclic partitioning algorithm based on the DAG partitioning model and introduced a direct k-way partitioning method. [PERSON] [37] proposed a local optimization algorithm combining maximum flow-minimum cut and FM strategies to improve the partitioning performance of traditional multi-level partitioning frameworks. In circuit partitioning, graphs offer a simplified representation of circuit components and their connections, making them easier to process and analyze.