# SVPWM Method for Multilevel Indirect Matrix Converter with Eliminate Common Mode Voltage
## 3 Simulation Results and Experimental Results  
Simulations and experiments are carried out in order to verify the proposed method for multilevel IMC control. The simulation process is performed by using PSIM 9.1 software. The parameters of the system including power supply, load, sampling period control for simulation are given in Table 6.  
\begin{table}
\begin{tabular}{c c} \hline Input voltage (\(V_{in}\)) & 100 V \\ Input frequency (\(f_{in}\)) & 50 Hz \\ R load & 20 \(\Omega\) \\ L load & 20 mH \\ Output frequency (\(f_{out}\)) & 40 Hz \\ Sampling period (\(T_{s}\)) & 100 kHz \\ Voltage transfer ratio (\(m\)) & 1.2 \\ \hline \end{tabular}
\end{table}
Table 6: The parameter for simulation and experimental.  
Figure 7: The switching pattern of the multilevel IMC with the proposed SVPWM method.  
In order to confirm the propriety of the proposed topology, theory analysis and simulated results, an experiment for the proposed SVPWM method was built. The experimental parameters are identical to the simulation parameters. Figure 11 shows the block diagram of a multilevel IMC and Figure 12 indicates the photograph of the experimental setup. The system consists of a controller board, power board, sensor board and driver board. The controller board is developed with a high-performance DSP TMS320F28377S, which executes the A/D converter, the generating PWM signals for driver circuit. The sensor board uses the LV-25P of LEM. The power board was implemented by using IGBT SK 60 GM123 for bidirectional switches and IGBT FMG2G50U60 for dual switch in the inverter stage. Table 8 lists the model name, manufacturer and the ratings of the power switches used in the power converter.  
The pulse signals for the rectifier stage according to the input sector are shown in Figure 13. It can be seen that, the switch \(S_{ap1}\), \(S_{ap2}\) are always at ON state in sector 1, they are modulated in sector 2 and 6 and at OFF state in all remain sectors. Figure 14 shows the PWM signals for the rectifier and inverter stages, and the zoom in of these waveforms is shown in Figure 15. From Figure 15, the switch \(S_{ap1}\) of the rectifier stage changes the status from ON to OFF or OFF to ON during the time when the zero vector is applied in the inverter stage (\(S_{A1}\) is OFF state and \(S_{A2}\) is ON state). It means that the soft-switching is achieved in the rectifier stage.  
Figure 11: Block diagram of the multilevel IMC hardware experiment.  
Figure 12: Experimental setup.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Model Name** & **Manufacturer** & **Rated Voltage** & **Rated Current** & **Power Switches in Figure 3** \\ \hline \multirow{2}{*}{SK 60 GM123} & \multirow{2}{*}{Semikron} & \multirow{2}{*}{1200 V} & \multirow{2}{*}{50 A} & \(S_{ap1}\), \(S_{ap1}\), \(S_{ap1}\), \(S_{ap1}\), \(S_{ap1}\), \(S_{ap1}\) \\  & & & \(S_{ap2}\), \(S_{ap2}\), \(S_{ap2}\), \(S_{ap2}\), \(S_{ap2}\), \(S_{ap2}\), \(S_{ap2}\), \(S_{ap2}\) \\ \multirow{2}{*}{FMG 2G 50 US60} & \multirow{2}{*}{Fairchild Semiconductor} & \multirow{2}{*}{600 V} & \multirow{2}{*}{50 A} & \(S_{A2}\), \(S_{A3}\), \(S_{B2}\), \(S_{B3}\), \(S_{C2}\), \(S_{C3}\) \\  & & & \(S_{A1}\), \(S_{A4}\), \(S_{B1}\), \(S_{B4}\), \(S_{C1}\), \(S_{C4}\) \\ \hline \hline \end{tabular}
\end{table}
Table 8: Summary of IGBT Module for the converter.  
Figure 16: Experimental results of input side.  
Figure 17: Experimental results of DC-link voltage.  
Figure 18: Experimental results of load side: line-to-line output voltage, phase output voltage and output current.