# The Quanta Image Sensor: Every Photon Counts
## 5 Jot Device
### High CG Pump-Gate Jet Devices  
Depending on the process feature size and layout design, the overlap capacitance between FD and TG in a CIS pixel can be 0.3 fF or higher, especially in a pixel with a shared readout structure. A pump-gate (PG) technique was developed by our group to eliminate the overlap capacitance between FD and TG without affecting complete charge transfer [13]. A cross-section doping profile of a PG jet device is shown in Figure 9a. A distal FD is formed with no spatial overlap with TG. With different doping concentration in PW, PB and VB regions, two built-in electrostatic potential steps are formed,as shown in Figure 9b. The photoelectrons accumulate in SW during the integration period. During this period, dark current generated directly under TG at the Si-SiO\({}_{2}\) interface, is blocked from flowing to SW by a barrier, and instead dark current flows to FD. As a result of SW being an n-region fully surrounded in 3D by single crystal p-type silicon, dark current is extremely low. For readout, FD is reset and sampled, and then integrated carriers in SW are transferred to the PW region under TG as TG is turned \"on\" by a positive bias, and then transferred to FD in a \"pump\" action when TG is turned \"off\", since a built-in barrier prevents their return to SW. With the transferred charge, FD is sampled a second time for correlated double sampling (CDS). The PG jot device has a FWC of about 200 e\(-\) and can achieve lag-less charge transfer [18].  
A tapered RG technique was developed to reduce the overlap capacitance between FD and RG, which uses STI to shrink the width of reset transistor on the FD end. The use of the tapered RG (aka tapered PG (TPG) jot) significantly increased conversion gain from 250 uV/e\(-\) to over 400 uV/e\(-\) and helped reduce read noise from approximately 0.33-0.45 e\(-\) r.m.s. range to the 0.22-0.35 e\(-\) r.m.s. range as shown in Figure 10. The variation in read noise may be due to fluctuations in the energy levels of traps in the readout transistor, the total number of traps, and other random factors.  
Figure 10: Scatter plot of voltage read noise vs. CG for PG jots and TPG jots. The read noise in e\(-\) r.m.s. levels are shown with dashed lines. Presented in [18].  
Figure 9: (**a**) PG jot cross-section doping profile from TCAD simulation; (**b**) Electrostatic potential curve along charge transfer path AA\({}^{\prime}\). Both are presented in [13].  
The pump-gate technique enables the implementation of shared readout structure (shared PG jot) without adding overlap capacitance due to the distal FD, and the 3D TCAD model of a 4-way shared readout PG jot is depicted in Figure 11. The shared readout jot has a more compact layout design with 1 \(\upmu\)m pitch, but since FD needs to be connected to the SF, more inter-metal parasitic capacitance is added to FD, which yields a mildly lower CG.  
Both PG jot and TPG jot (PG jot with tapered RG) were designed and fabricated in the TSMC BSI 65 nm process. The fabrication followed baseline process with implantation modifications, and no extra mask was required. The TPG jot pitch is 1.4 \(\upmu\)m and has 410 \(\upmu\)V/e\(-\) CG (0.39 fF FD capacitance), the non-shared PG jot pitch is 1.4 \(\upmu\)m and has 250 \(\upmu\)V/e\(-\) CG (0.64f FD capacitance), and the 4-way shared PG jot pitch is 1 \(\upmu\)m and has 230 \(\upmu\)V/e\(-\) CG (0.7 fF FD capacitance). As expected, extremely low SW dark current (0.1 e\(-\)/s at RT) was measured and almost lag-less (<0.1 e\(-\)) charge transfer was achieved. The measured characteristics of jot devices are listed in Table 1.