## 2 Methods
### Photodiodes' Layout  
In order for the photodiodes to be microfabricated in a further step of this work, the photodiodes' layout was also designed, according to the proposed p-n junction geometries. through Europractice, in the United Microelectronics Corporation (UMC), and by using the UMC 1180 MM/RF technology.  
The layout design was performed with CADENCE tools (Version IC6.1.8-64b-500.14), using the UMC 1180 MM/RF technology masks that comprise 6 metal layers [21]. Each type of p-n junction photodiode (n+/p-substrate, n-well/p-substrate and p+/n-well, as shown in Figure 1) has a different layout, as seen in Figure 5.  
To design the n+/p-substrate photodiode layout, a diffusion mask together with the _nplus_ (n+) mask was used, allowing to build the active area of the photodiode (100 \(\upmu\)m \(\times\) 100 \(\upmu\)m), which, in Figure 5a, is represented by the main red square. Then, the p+ ring was implemented around that active area. Finally, as shown in the zoomed figure of the n+/p-substrate photodiode layout, Figure 5a.1, several metal contacts were inserted around the p+ ring and around the active area n+ (represented by small green dots in the  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline
**CMOS Technology** & **CMOS Structure** & **Number of Elements** & **Minimum Quality (a.u.)** & **Average Quality (a.u.)** \\ \hline \multirow{3}{*}{0.18 \(\upmu\)m} & n+/p-substrate & 25,784 & 0.5596 & 0.9027 \\  & n-well/p-substrate & 36,036 & 0.5616 & 0.9153 \\  & p+/n-well & 26,577 & 0.4661 & 0.9133 \\ \hline \multirow{3}{*}{0.35 \(\upmu\)m} & n+/p-substrate & 23,404 & 0.5699 & 0.9106 \\  & n-well/p-substrate & 35,920 & 0.4422 & 0.9145 \\  & p+/n-well & 22,967 & 0.3909 & 0.9147 \\ \hline \multirow{3}{*}{0.7 \(\upmu\)m} & n+/p-substrate & 29,969 & 0.5524 & 0.9039 \\  & n-well/p-substrate & 16,769 & 0.5395 & 0.9335 \\ \cline{1-1}  & p+/n-well & 20,498 & 0.4868 & 0.9188 \\ \hline \hline \end{tabular}
\end{table}
Table 4: Number of mesh elements and quality statistics of the mesh.  
Figure 4: (**a**) View of the 2D mesh applied to the n+/p-substrate photodiode in 0.18 \(\upmu\)m technology and (**b**) zoomed view of the blue square in the left figure where it is possible to observe the meshing of the n+ and p+ doping regions with higher detail.  
figure). The photodiode cathode and anode were fully designed after the addition of the CADENCE predefined _metal1_ layer. Additionally, for the n-well/p-substrate photodiode, an n-well layer was used as active area and for the p+/n-well photodiode, an n-well layer was defined as the substrate, followed by an active area p+ and an n+ ring inserted into that n-well, as previously represented schematically in Figure 1. Three dark photodiodes were also included in the chip, i.e., three structures similar to the ones represented in Figure 1, but with a metal layer on top to experimentally measure the dark current of each p-n junction photodiode. The contacts of the photodiodes, the cathode and the anode, were connected to contact pads through metal, allowing the external access for measurements. Following the design of the layout (as shown in Figure 6), the masks will be sent to a European silicon foundry--IMEC, from the Europractice program--for chip fabrication.  
Figure 5: Top: Layout of the 3 types of photodiodes in 0.18 \(\upmu\)m CMOS technology: (**a**) n+/p-substrate, (**b**) n-well/p-substrate and (**c**) p+/n-well. Bottom: Zoom of the lower right corner of each photodiode layout, allowing the visualization of the contacts (green dots): (**a.1**) n+/p-substrate, (**b.1**) n-well/p-substrate and (**c.1**) p+/n-well.  
Figure 6: Layout of the photodiodes’ area in the chip, ready to be sent to the silicon foundry, with the designed photodiodes included: A—n+/p-substrate, A’—n+/p-substrate covered with metal, B—n-well/p-substrate, B’—n-well/p-substrate covered with metal, C—p+/n-well, C’—p+/n-well covered with metal and D—pad for external connection. The total dimension of the photodetector chip is 0.7 mm \(\times\) 1.1 mm.