## 3 Communication System Design
### Backward Communication Based on S-Bar  
Compared with passive rectifier and full-bridge active rectifier, S-BAR has fewer switching devices and more regulating degrees [32]. For the S-BAR, synchronization signal plays an important role in power regulation. Usually, the phase of resonant current in compensation circuit serves as synchronization signal, which is measured by a current sensor on the secondary side, as shown in Figure 7. To eliminate the noise caused by hard switching and dead time, a low-pass filter (LPF) is used. However, both the current sensor and the LPF will cause phase delay. Therefore, a phase leading correction is required to eliminate the phase delay. In this paper, the BPF and zero-crossing detection are realized through analog circuit, and the phase leading correction is realized through FPGA. There are two reasons for choosing FPGA: (1) The leading phase can be easily adjusted according to the operation frequency. (2) It can be integrated into the modulator on the secondary side, therefore, the hardware cost of SWPIT system can be reduced. Similar to the modulation of forward communication, the data carrier and power carrier are also shared in the backward communication. Then, the phase-shifting angle \(\varphi_{\text{s}}\) is used to regulate output power and equivalent resistance, which is determined by the modulation of bit \"1\" and bit \"0\". The changes of phase-shifting angle during the modulation of bit \"1\" and bit \"0\" is given by  
\[\left\{ \begin{array}{cc}\varphi_{\text{s}}-\Delta\varphi_{\text{s}}\to \varphi_{\text{s}}+\Delta\varphi_{\text{s}}&\text{``1\"}\\ \varphi_{\text{s}}&\text{``0\"}.\end{array} \right. \tag{18}\]  
Figure 6: Key waveforms of full-bridge inverter and modulator during the modulation of bit “1” and bit “0”. Figure 7: Synchronization circuit for semi-bridgeless active rectifier (S-BAR). Figure 8b shows the block diagram of modulation based on DPSK, in which two digital counters with 12 bit data-width are used to record the value of source clock (CLK). The counter 1 and counter 2 account at the rising and falling edges of synchronization signal, respectively. By this way, the positive and negative period of secondary current is measured separately. Meanwhile, the value of \(\varphi_{\text{s}}\) and \(\Delta\varphi_{\text{s}}\) are determined by (18). Once the value of counter is between \(\varphi_{\text{s}}\) and \(\pi-\varphi_{\text{s}}\), the corresponding MOSFET turns OFF. Otherwise, it turns ON. The detailed control strategy for MOSFETs (\(Q_{5}\sim Q_{6}\)) and diodes (\(D_{1}\sim D_{2}\)) is listed in Table 1.  
Obviously, there are two periods when the load obtains energy, otherwise the energy is blocked by MOSFETs. Then, the equivalent resistance seen from S-BAR changes dynamically according to \(\varphi_{\text{s}}\). To further understand the backward communication, the waveforms of the S-BAR and modulator are depicted in Figure 9 during the modulation of bit \"1\" and bit \"0\". According to the phase relation of secondary voltage \(V_{\text{rec}}\) and current \(i_{\text{s}}\), the S-BAR has three working modes, i.e., capacitive, inductive, and resistive modes [33]. To minimize the power losses caused by hard switching, the primary voltage should slightly lead the primary current to realize zero voltage switching (ZVS) [34]. As a result, the S-BAR should be designed in capacitive or resistive mode, and the equivalent impedance \(Z_{\text{e}}\) seen from S-BAR is written as  
\[Z_{\text{e}}=R_{\text{e}}+jX_{\text{e}}. \tag{19}\]