## 3 MOSFET Circuital Model  
The circuital model in Figure 4 represents the MOSFET gate. It is inspired by [38; 39; 40]. The main idea of this circuit is to represent the transients of MOSFET during commutations, taking into consideration only two capacitances, which represent the amount of electric charge between the gate and, respectively, the drain and source. The simplicity of this approach is particularly suitable for the aim of this work, which is the proposal of a tool to easily evaluate the impact of MOSFET behavior in the converter performances. The drain, gate and source of a MOSFET are modeled by, respectively, the left branch, the central branch and the right branch. \(v_{DS}\) is the voltage between MOSFET drain and source; it is modeled as a variable voltage source since its value changes during commutations between V\({}_{\text{DC}}\) and 0 (neglecting the contribution of internal parasitic resistances). \(C_{gd}\) and \(C_{gs}\) are capacitances between, respectively, the drain and gate and the gate and source. They model the amount of charge in the MOSFET junctions, and they are functions of \(v_{DS}\) voltage. V\({}_{\text{GS}}\) is the voltage imposed between gate and source to activate (or deactivate) the MOSFET. Finally, \(R_{g}\) is the gate resistance. Typically, it can be written as \(R_{g}=R_{g(int)}+R_{g(ext)}\). \(R_{g(int)}\) is the intrinsic resistance in the transistor chip: it is the real part of the electric impedance between the gate and source terminals, measured at 1 MHz, with an open drain terminal [41]. \(R_{g(ext)}\) is an external resistance added in the gate drive circuitry to limit the oscillations of voltage and current in the MOSFET during commutations. T\({}_{1}\) and T\({}_{2}\) are ideal switches to consider the ON and OFF states of a MOSFET. When T\({}_{1}\) is closed and T\({}_{2}\) is open, a gate signal is provided and the MOSFET is activated. Conversely, when T\({}_{1}\) is open and T\({}_{2}\) is closed, the MOSFET is deactivated. As can be seen, no parasitic inductances are considered in the circuit to preserve the simplicity of the model. However, according to [42; 43], at very high frequency, the drain series MOSFET inductance could be similar to \(L_{f}\). For this reason, in the next section we will show how to take into account this component in the converter model. The value of these inductances is typically very low, and their neglection make the analysis of the circuit very easy. Indeed, as it will be shown in the next lines, the evaluation of rise and fall times will require the consideration of just one capacitance. The origin of rise and fall times can be understood by observing the qualitative trend of drain-source voltage, GO voltage (with reference to Figure 4) and drain-source current during commutations. They are reported in Figure 5.  
Figure 4: MOSFET equivalent circuital scheme. When a gate signal is provided (T\({}_{1}\) closed, T\({}_{2}\) open), the drain-source voltage starts to decrease after a delay (\(t_{2}\)-\(t_{1}\) in the figure). In this time, the current provided by the gate charges the \(C_{gs}\) capacitance. This is because the nominal value of \(C_{gs}\) is normally higher than the \(C_{gd}\) one, so the current mainly flows in \(C_{gs}\). As consequence, the value of drain-source voltage remains quite constant, and also the values of \(C_{gs}\) and \(C_{gd}\) are constant. When the \(C_{gs}\) capacitance is charged, it imposes the electric potential in the A node in Figure 4; the GO voltage stays constant (it is called a Miller Plateau), the current flows just on \(C_{gd}\) and the \(v_{DS}\) voltage starts to decrease. After the \(t_{3}\) time, the MOSFET is completely closed: \(v_{DS}\) is ideally zero (in Figure 5 it is not zero due to the internal resistance of the MOSFET) and the drain-source current reaches its nominal value.