# An LDPC-RS Concatenation and Decoding Scheme to Lower the Error Floor for FTN Signaling
## 3 LDPC-RS Concatenation Code
### RS Parallel Encoder  
The conventional RS encoder adopts a serial structure that can be treated as a digital circuit. It consists of shifting registers and constant multipliers [26], depicted in Figure 7, whose control, initialization, and reset logic are not depicted here. There are 20 shifting registers and 20 constant multipliers for RS (340, 320) code together with 20 adders (bitwise XOR). After data \(d_{k}\) are serially input, contents of registers are serially shifted out in the sequence of \(R_{19}\), \(R_{18}\), \(\ldots\), \(R_{0}\), which are parity bits, accordingly. For RS (340, 320) code, let the input data be \(\mathbf{d}=\{d_{k}\}\), where \(k=0,1,\ldots,319\) is the index of the clock period in this digital circuit of the encoder, and the generator polynomial is \(g(x)=x^{20}+g_{19}x^{19}+\ldots+g_{1}x+g_{0}\), whose coefficients \([g_{19},\ldots,g_{0}]=[58,257,157,222,388,151,62,280,137,404,286,394,61,399,73, 84,145,293,369,331]\) are constant. Shifting  
Figure 6: Decoding of a (6, 3) trapping set without/with perturbation. Figure 7: Conventional serial RS (340, 320) encoder. register \(R_{n}(k)\) describes the value of register \(n\) at clock period \(k\), where \(n=0,1,\ldots,19\). We formulated the serial encoder as  
\[R_{n}(k+1)=\left\{ \begin{array}{ll}R_{n-1}(k)+&(d_{k}+R_{19}(k))g_{n},n\geq 1, \\ &(d_{k}+R_{19}(k))g_{n},n=0.\end{array} \right. \tag{22}\]  
Furthermore, initial states \(R_{n}(0)=0\) for all registers. After 320 clock periods, all data are input into the encoder, all adders and multipliers are stopped, and 20 registers are shifted out in the sequence of \([R_{19}(320),R_{18}(320),\ldots,R_{0}(320)]\) to constitute the parity part of the RS (340, 320) code. In fact, the calculation performed by this encoder is equivalent to \(x^{20}+R_{19}x^{19}+\cdots+R_{1}x+R_{0}=(((d_{0}g(x)\times x+d_{1}g(x))\times x +\cdots+d_{318}g(x))\times x+d_{319}g(x)\mod g(x)\). \[ \begin{split} R_{5}(k+4)&=R_{4}(k+3)+(d_{k+3}+R_{19} (k+3))g_{5}\\ &=\ldots\\ &=R_{1}(k)+(d_{k+3}+R_{16}(k))g_{5}+(d_{k+2}+R_{17}(k))(g_{4}+g_{19} g_{5})+(d_{k+1}+R_{18}(k))(g_{3}+g_{19}g_{4}+(g_{18}+g_{19}^{2})g_{5})\\ &+(d_{k}+R_{19}(k))(g_{2}+g_{19}g_{3}+(g_{18}+g_{19}^{2})g_{4}+(g_{17 }+2g_{18}g_{19}+g_{19}^{3})g_{5}).\end{split}  \tag{23}\]  
\(R_{n}(k+4)=\)  
\[\left\{ \begin{array}{ll}R_{n-4}(k)+&(d_{k}+R_{19}(k))p_{n}(0)+(d_{k+1}+R_{ 18}(k))p_{n}(1)+(d_{k+2}+R_{17}(k))p_{n}(2)+(d_{k+3}+R_{16}(k))p_{n}(3),n\geq 4, \\ &(d_{k}+R_{19}(k))p_{n}(0)+(d_{k+1}+R_{18}(k))p_{n}(1)+(d_{k+2}+R_{17}(k))p_ {n}(2)+(d_{k+3}+R_{16}(k))p_{n}(3),n=0,1,2,3.\end{array} \right. \tag{24}\]  
The shortcomings of a serial encoder are low throughput and high encoding latency. We accordingly require a new structure to encode in parallel and lower the encoding latency while improving its throughput. Considering a 4-parallel encoder, each clock period during operation should be equivalent to four clock periods in the serial encoder. By carefully observing (22) and Figure 7, we can see that \(R_{n}(k+1)\) is determined by two variable terms \(R_{n-1}(k)\) (except for \(R_{0}\)) and \((d_{k}+R_{19}(k))\). By recursively applying (22), \(R_{n}(k+4)\) is determined by five variable terms: \(R_{n-4}(k)\) (except for \(R_{0},R_{1},R_{2},R_{3}\)), \((d_{k}+R_{19}(k))\), \((d_{k+1}+R_{18}(k))\), \((d_{k+2}+R_{17}(k))\), and \((d_{k+3}+R_{16}(k))\). We take \(R_{5}(k+4)\) for example, as in (23), which is clearly especially complicated to derive and difficult to understand. In order to simplify the derivation, we came up with an easy approach for calculating parallel encoding coefficients, leveraging a conventional serial encoder structure. We came up with a method to use the serial encoder to calculate the parallel encoding coefficients and propose it as Algorithm 2. The details of its derivation are described in the Appendix A. ```
Initialize the serial encoder; set all registers to zero. Input: \"\(1\)\". Run one clock and \(p_{n}(3)\gets R_{n}(1)\). Input: \"\(0\)\". Run one clock and \(p_{n}(2)\gets R_{n}(2)\). Input: \"\(0\)\".