## 4 Discussion  
This study highlights the significant advantages of FPGA-based DL acceleration for practical applications, particularly in resource-constrained and real-time environments. Accuracy, inference latency, and resource utilization are interrelated factors in DL deployment. Improving inference latency often requires optimizations like quantization and parallelism, which can impact accuracy, while resource utilization directly affects the scalability and efficiency of hardware accelerations. In addition, achieving high accuracy may require more computational resources, which in turn affects resource utilization. Hence, achieving a balance between these factors is critical for practical applications. In our work, we maintain high accuracy by leveraging and fine-tuning pretrained models carefully, significantly reducing inference latency through FPGA-specific optimizations such as quantization and parallel processing, and ensuring efficient resource utilization by fully exploiting the computational capabilities of the FPGA without exceeding hardware limits. This balance makes our design particularly suitable for edge AI applications, such as autonomous vehicles and IoT devices, where both low latency and high accuracy are essential.  
While custom implementation methods, such as HDL and HLS, offer unparalleled flexibility and allow for fine-grained hardware optimizations, they come with substantial development time and complexity. In many cases, the incremental performance improvements from custom methods may not justify the added effort, especially when frameworks like Vitis-AI provide streamlined workflows and competitive performance. This trade-off underscores the practicality of using pre-configured frameworks for deploying DL models efficiently.  
As mentioned, one limitation of the TF2 framework in Vitis-AI is its lack of support for BatchNormalization layers, restricting the effective use of certain pretrained models. This limitation can be addressed by employing the PyTorch framework, which supports BatchNormalization and enables compatibility with a broader range of pretrained models to evaluate the generalizability and adaptability of the proposed approach. Transitioning to PyTorch for implementing other architectures, such as EfficientNet, DenseNet, and MobileNet, could enhance the versatility of this approach. Additionally, exploring more complex architectures like Transformer models could enhance the adaptability, efficiency, and relevance of FPGA-based DL acceleration for a wider range of advanced tasks.  
While this study employs CIFAR-10 as a benchmark dataset, we acknowledge its limitations in reflecting the complexity and dynamics of real-world data. Future work will incorporate real-time datasets such as KITTI [26] and Cityscapes [27] to evaluate the models' performance and scalability in more challenging scenarios, including autonomous driving and IoT applications. These datasets will allow us to assess the suitability and efficiency of FPGA acceleration under high computational demands, particularly for high-resolution or sequential data streams. Future work also could involve integrating real-time datasets to assess our approach's suitability for latency-critical scenarios. Utilizing datasets with dynamic classification requirements would provide a more comprehensive evaluation of model scalability for real-world applications.