# A Low Phase Noise Frequency Synthesizer with a Fourth-Order RLC Loop Filter
## 4 Simulation Analysis
### Phase Noise Analysis  
Phase noise is the power per unit bandwidth (\(P_{SSB}\)) to the total signal power (\(P_{S}\)), deviating from the carrier frequency \(f_{m}\) within a specific range. Its unit is dBc/Hz and can be described as follows:  
\[L(f_{m})=\frac{P_{SSB}}{P_{S}} \tag{9}\]  
According to Figure 1, \(\phi_{REF}\), \(\phi_{PFD}\), \(\phi_{LPF}\), \(\phi_{VCO}\), and \(\phi_{N}\) describe the noise introduced by the reference signal, the phase detector, the loop filter, the voltage-controlled oscillator, and the programmable N divider, respectively. Let \(S_{REF}\), \(S_{PFD}\), \(S_{LPF}\), \(S_{VCO}\), and \(S_{N}\) denote the corresponding component's phase noise power spectral density. \(S_{TOT}\) is the total phase noise of the system. The phase noise introduced by the loop filter is negligible. When the loop is locked, and since the system is linear time-invariant [20; 21], the following relation can be obtained by the superposition principle:  
Figure 5: Amplitude-frequency response characteristic curve.  
\begin{table}
\begin{tabular}{c c c} \hline \hline  & **Passive Fourth-Order RC** & **Passive Fourth-Order RLC** \\  & **Filter** & **Filter** \\ \hline zeros & \(-3.4722\times 10^{5}\) & \(-3.4722\times 10^{5}\) \\  & \(-4.2670\times 10^{7}\) & \(-8.1664\times 10^{6}+8.6381\times 10^{6}i\) \\ poles & \(-0.6242\times 10^{7}\) & \(-8.1664\times 10^{6}-8.6381\times 10^{6}i\) \\  & \(-0.0348\times 10^{7}\) & \(-0.3503\times 10^{6}\) \\ \hline \hline \end{tabular}
\end{table}
Table 3: Zero-pole location distributions of the two filters.  
\[S_{\rm TOT}=\Big{(}S_{REF}^{2}+S_{N}^{2}\Big{)}\cdot\bigg{[}\frac{G(s)}{1+G(s)H(s)} \bigg{]}^{2}+S_{\rm FFD}^{2}\cdot\bigg{(}\frac{1}{K_{d}}\bigg{)}^{2}\cdot\bigg{[} \frac{G(s)}{1+G(s)H(s)}\bigg{]}^{2}+S_{\rm VCO}^{2}\cdot\bigg{[}\frac{1}{1+G(s)H (s)}\bigg{]}^{2} \tag{10}\]  
Figure 6 shows the input noise introduced by each part of the loop and the total output phase noise.  
The phase noise introduced by the reference source, the phase detector, and the frequency divider is low-pass. This is the primary factor influencing the total phase noise in the loop bandwidth. Moreover, the phase noise caused by the VCO is high-pass, mainly affecting the out-of-band phase noise [22]. The in-band output signal's phase noise is presented in (11), where \(PN_{\rm SYNTH}\) is the normalized noise ground of the PD, and \(N\) describes the frequency division ratio.  
\[PN=PN_{\rm SYNTH}+10\log f_{PD}+20\log N \tag{11}\]  
From (11), there are three ways to promote the system's total phase noise: increasing the phase detection frequency, reducing the frequency division ratio N, and employing a phase detector with a small noise ground. ADIsimPLL can simulate the output signal's phase noise, loop capture time, and other simulation results. The phase noise simulation results are shown in Figure 7.  
Since the phase noise of the frequency synthesizer focuses on the proximal phase noise, the proximal phase noise is the phase noise in the loop bandwidth. Thus, we mainly analyze the proximal phase noise of both circuits. From Table 4, it can be seen that the proximal phase noise of the passive fourth-order RLC filter is superior to that of the passive fourth-order RC filter. In contrast, the distal phase noise, that is, the phase noise outside the loop bandwidth is inferior.  
\begin{table}
\begin{tabular}{c c c c c} \hline \hline \multirow{2}{*}{**Loop Circuit Type**} & \multicolumn{4}{c}{**Phase Noise (dBc/Hz)**} \\ \cline{2-5}  & **1 KHz** & **10 KHz** & **100 KHz** & **1 MHz** \\ \hline passive fourth-order RC filter & \(-113.3\) & \(-115.5\) & \(-113.4\) & \(-140.7\) \\ passive fourth-order RLC & \(-113.3\) & \(-116.0\) & \(-113.9\) & \(-138.4\) \\ \hline \hline \end{tabular}
\end{table}
Table 4: Phase noise simulation results.  
Figure 6: Single-loop PLL phase noise model.