## 3 Results and Discussion
### Field-Effect ICEO of a Janus micropillar Subjected to a Controllable Gate Voltage
#### 3.3.1 Effect of AC Gate-Voltage Bias on ICEO Mixing- and Pumping-Flow Components
Figure 5: A simulation analysis of the effect of AC gate-voltage offset on the resulting pump \(\mathrm{u_{x}}\) and mixing-flow behavior \(\mathrm{u_{y}}\) orthogonal to each other driven by Janus AC-FFET, in which the metal phase of a Janus micropillar is no longer free from external Ohm contact and is instead subjected to arbitrary AC field-effect flow control, for given values of \(\mathrm{V_{D}}\) = 2 V, f = 200 Hz, and R = 5 \(\upmu\)m. (**A–D**) A surface and streamline plot of ICEO-vortex flow field with both horizontal and transversal symmetric breaking when the Janus pillar is subjected to distinct AC gate voltage supply: (**A**) an apparently negatively-polarized gating-metal phase with \(\mathrm{V_{G}}\) = 0.05 V\(\mathrm{D}\) and \(\beta\) = \(-\)0.9; (**B**) a slightly negatively polarized gating-metal phase with \(\mathrm{V_{G}}\) = 0.45 V\(\mathrm{D}\) and \(\beta\) = \(-\)0.1; (**C**) a slightly positively polarized gating-metal phase with \(\mathrm{V_{G}}\) = 0.55 V\(\mathrm{D}\) and \(\beta\) = 0.1; and (**D**) an apparently positively polarized gating-metal phase with \(\mathrm{V_{G}}\) = 0.95 V\(\mathrm{D}\) and \(\beta\) = 0.9. (**E**) The horizontal pump velocity \(\mathrm{u_{y}}\), transversal mixing velocity \(\mathrm{u_{y}}\), and velocity-component ratio \(\mathrm{u_{y}}/\mathrm{u_{x}}\) as a function of the gate-voltage-offset ratio \(\beta\). (**F**) A quantitative comparison of the magnitude of tangential ICEO slipping and induced zeta potential between the dielectric- and metal-phase surfaces of the Janus micropillar. (**G**) Position-dependent tangential ICEO velocity on the polarizable post surface as a function of the polar angle under varying \(\beta\). (**H**) Position-dependent induced zeta potential on the polarizable pillar surface as a function of the polar angle under varying \(\beta\). With the advent of the new transversal symmetry breaking of ICEO eddies, leading to an effective mixing-flow component \(\upup_{y}\) along the width of the channel, the original pump motion \(\upup_{x}\) induced by the uneven interfacial polarizability of the Janus post remains. As shown in Figure 5E, the sign and value of the gate-voltage-bias ratio \(\beta\) determine the lateral rotating flow component \(\upup_{y}\) through a linear relationship, in which a positive (negative) \(\beta\) corresponds to a positive (negative) \(\upup_{y}\) of the same sign that exactly passes zero for \(\beta=0\). On the other hand, the ICEO's pump behavior \(\upup_{x}\) changes by no more than 20% as the magnitude of \(\beta\) increases from 0 to 0.95. Accordingly, the axial/transversal velocity-component ratio \(\chi=\upup_{y}/\upup_{x}\) rises monotonically with the magnitude of the gate-voltage offset \(\text{abs}(\beta)\) for either sign of \(\beta\) (Figure 5E). This indicates that the induction of \(\upup_{y}\) only appears due to the action of the AC field-effect flow control of the metal phase, and both its orientation (either upward or downward) and magnitude are mainly governed by the biased gate voltage applied to the Janus cylinder, so that \(\upup_{y}\) must vanish under a neutral gate voltage (Figure 3G). This conclusion suggests that this is a very convenient way to achieve separate control over \(\upup_{y}\) and \(\upup_{x}\) by adjusting the gate bias only, because \(\upup_{x}\) is almost insensitive to the specific voltage offset due to its physical origin in the inherent non-uniform material polarizability of the Janus pillar itself. The value of the IZP and the tangential ICEO slipping velocity in the Janus AC-FFET are quantified by a comparison study in Figure 5F. Both the IZP and the electro-osmotic slipping speed in the azimuth direction on the metal-phase surface are always 100-1000 times greater than those at the dielectric-phase/liquid interface. Moreover, an increase in the magnitude of the gate bias can lead to a direct enhancement in IZP and ICEO slipping for either gate-voltage polarity.