# A Low-Latency Fair-Arbiter Architecture for Network-on-Chip Switches
## 5 Conclusions  
In order to ensure that high-performance network-on-chip switches can provide efficient, reliable data exchange capabilities, we focused on improving the performance of the arbiter, mainly in terms of fairness and low latency. The architecture we proposed ensures that all input requests are treated fairly, which designs based on the \"ping-pong\" algorithm cannot do. The FSA has an \(O(log_{4}N)\) critical path delay and is the fastest design, which is exactly what a high-performance switching system needs to be. The most critical feature of our design is that we implemented the search algorithm in layers. We implemented the parallel algorithm for achieving fairness at the leaf node and implemented a high-speed parallel search structure at the upper layer. This will ensure that the FSA will be more scalable in large switching systems. The proposed structure will perform better as the system-on-chip's performance is improved and more nodes are added to it.  
Conceptualization, J.L., Q.X. and F.Y.; methodology, J.L., W.W. and Z.M.; software, J.L. and M.X.; validation, J.L., W.W. and Q.X.; formal analysis, J.L., W.W. and Q.X.; investigation, J.L. and M.X.; data curation, J.L.; writing--original draft preparation, J.L. and W.W.; writing--review and editing, J.L., W.W., Q.X., M.X., F.Y. and Z.M.; visualization, J.L.; supervision, Z.M.; project administration, Z.M. All authors have read and agreed to the published version of the manuscript.  
This research received no external funding.  
Not applicable.  
The data presented in this study are available on request from the corresponding author.  
The authors declare no conflict of interest.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Port** & **PPA [19]** & **SA [21]** & **PRRA [23]** & **IPRRA [23]** & **PLA [25]** & **FSA** \\ \hline \(N=4\) & 7/11 & 8/12 & 7/12 & 7/12 & 10/11 & 6/11 \\ \(N=8\) & 21/23 & 22/28 & 18/24 & 20/24 & 25/23 & 27/24 \\ \(N=16\) & 49/47 & 48/56 & 48/48 & 48/48 & 57/47 & 65/48 \\ \(N=32\) & 104/95 & 106/116 & 96/96 & 93/96 & 127/95 & 122/96 \\ \(N=64\) & 215/191 & 204/232 & 199/192 & 201/192 & 257/191 & 231/192 \\ \(N=128\) & 432/384 & 449/468 & 393/384 & 389/384 & 532/384 & 447/384 \\ \(N=256\) & 883/767 & 836/936 & 859/768 & 839/769 & 1102/767 & 904/768 \\ Avg(LUT) & 100\% & 97\% & 94\% & 93\% & 123\% & 105\% \\ Avg(FF) & 100\% & 122\% & 100\% & 100\% & 100\% & 100\% \\ \hline \hline \end{tabular}
\end{table}
Table 6: FPGA utilization (LUT/FF).  
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Frequency** & **PPA [19]** & **SA [21]** & **PRRA [23]** & **IPRRA [23]** & **PLA [25]** & **FSA** \\ \hline
250 MHz & \begin{tabular}{c} \(256\times 256\) \\ (3.6 ns) \\ \end{tabular} & \begin{tabular}{c} \(256\times 256\) \\ (3.5 ns) \\ \end{tabular} & \begin{tabular}{c} \(256\times 256\) \\ (3.9 ns) \\ \end{tabular} & \begin{tabular}{c} \(256\times 256\) \\ (3.7 ns) \\ \end{tabular} & \
\begin{tabular}{c} \(256\times 256\) \\ (3.7 ns) \\ \end{tabular} &
\begin{tabular}{c} \(256\times 256\) \\ (3.4 ns) \\ \end{tabular} \\
\begin{tabular}{c} \(256\times 256\) \\ (3.1 ns) \\ \end{tabular} \\
400 MHz & \begin{tabular}{c} \(32\times 32\) \\ (2.3 ns) \\ \end{tabular} & \begin{tabular}{c} \(64\times 64\) \\ (2.4 ns) \\ \end{tabular} & \begin{tabular}{c} \(16\times 16\) \\ (2.3 ns) \\ \end{tabular} & \begin{tabular}{c} \(32\times 32\) \\ (2.4 ns) \\ \end{tabular} & \
\begin{tabular}{c} \(16\times 16\) \\ (2.4 ns) \\ \end{tabular} &
\begin{tabular}{c} \(128\times 128\) \\ (2.4 ns) \\ \end{tabular} \\ \hline \hline \end{tabular}
\end{table}
Table 5: Performance and scale of FPGA.