## 6 Findings Overview and Conclusions  
This research introduces a novel hybrid systolic array design specifically optimized for Dickson-basis multiplication in the context of binary extension fields. This advancement is significant for enhancing cryptographic applications that require high levels of efficiency and security. The study leverages a dependency graph to systematically organize multiplication operations, employing sophisticated scheduling and node projection functions. This methodological approach results in a highly efficient multiplier that optimizes computational processes. A key attribute of this design is its reduction in space complexity, transitioning from a quadratic to a linear scale. This reduction is particularly advantageous VLSI applications, where efficient resource utilization is critical for both performance and cost-effectiveness. Performance evaluations utilizing the ASIC CMOS library reveal significant reductions in both area and power consumption. These results illustrate the multiplier's capacity to minimize physical space while achieving lower energy usage, thereby rendering it suitable for energy-sensitive environments. Moreover, key performance metrics such as the power-delay product and area-delay product indicate substantial improvements in overall efficiency when compared to traditional multiplier architectures. The proposed multiplier framework is particularly well-suited for cryptographic protocols deployed in resource-constrained Internet of Things (IoT) devices targeting individuals with disabilities, where optimizing both space and power is essential for effective implementation. Additionally, this design contributes to the functionality of assistive technologies aimed at individuals with disabilities, ensuring reliable and efficient operation. Future work will concentrate on enhancing the design's resistance to side-channel attacks, a significant vulnerability in cryptographic systems. By employing a unidirectional systolic architecture, we aim to simplify modifications and facilitate the  
Figure 10: PDP Evaluation Results.  
Figure 9: ADP Evaluation Results.  
integration of robust error-detection mechanisms, crucial for safeguarding elliptic curve cryptography against such attacks. Additionally, we will investigate the trade-offs associated with increasing the field size in our proposed systolic multiplier, examining its impact on performance, area usage, and power consumption. This thorough analysis will enable us to address both the benefits and challenges of scalability in our future developments.  
Conceptualization, A.I.; methodology, A.I. and F.G.; software, A.I.; validation, A.I.; formal analysis, A.I.; investigation, A.I.; resources, A.I.; data curation, A.I.; writing--original draft preparation, A.I.; writing--review and editing, A.I. and F.G.; visualization, A.I.; supervision, A.I.; project administration, A.I. and F.G.; funding acquisition, A.I. All authors have read and agreed to the published version of the manuscript.  
King Salman Center For Disability Research, Research Group No. KSRG-2024-207.  
Not applicable.  
Data Availability Statement: Data are contained within the article.  
The authors extend their appreciation to the King Salman Center For Disability Research for funding this work through Research Group no KSRG-2024-207.  
The authors declare no conflict of interest.  
The following abbreviations are used in this manuscript:  
\begin{tabular}{l l} IoT & Internet of Things \\ TLS & Transport Layer Security \\ PKI & Public Key Infrastructure \\ PB & Polynomial Basis \\ NB & Normal Basis \\ DB & Dual Basis \\ RB & Redundant Basis \\ PE & Processing Element \\ ADP & Area-Delay Product \\ PDP & Power-Delay Product \\ ASIC & Application Specific Integrated Circuit \\ ECC & Elliptic Curve Cryptography \\ DG & Dependency Graph \\ AOP & All-One Polynomial \\ VLSI & Very Large Scale Integrated Circuit \\ CPD & Critical Path Delay \\ \end{tabular}