## 4 Derivation of the Hybrid Compact Systolic Multiplier
### The Explored Multiplier Layout
This allows for their effective use within each processing element. During this period, control signals \(c_{1}\) and \(c_{0}\) maintain their states (\(c_{1}=1\) and \(c_{0}=0\)), ensuring that all remaining sequential bits of the \(e_{i-1}\) and \(f_{i}\) signals pass through the input ports \(e_{b}\) and \(f_{b}\). 6. At the conclusion of the second \(r\) clock cycles, control signal \(q\) is activated (\(q=1\)) to transfer the intermediate bits of \(h\) to the accumulator (XOR gates and \(D_{h}\) latches) located at the output of each PE, as shown in Figure 3. These bits are added to the previously stored output bits from the first computation phase. The accumulated bits are retained in the \(D_{h}\) latches for subsequent addition to the next output bits produced after the third \(r\) clock cycles, marking the beginning of the third operational phase of the systolic array. 7. After the second \(r\) clock cycles, the systolic array enters the third computation phase. At the first clock cycle of this phase, the latches \(D_{h}\) within each PE are reset to initialize the input bits of \(h_{j}\), for \(j\) ranging from 1 to \(r\), to zero at the inputs of the XOR gates inside each PE, as shown in Figures 4 and 5. Concurrently, control signal \(c\) is activated (\(c=1\)) to facilitate the use of the input signals \(e_{r-j}\), for \(j\) ranging from 1 to \(r\), assigned to input port \(e_{in}\) within each regular PE (PE\({}_{j}\)). Furthermore, during this clock period, control signals \(c_{1}\) and \(c_{0}\) are both activated (\(c_{1}=1\) and \(c_{0}=1\)), allowing the first bits of the \(e_{r-i}\) and \(f_{r-i+1}\) signals, for \(i\) ranging from 1 to \(r\), to pass through the input ports \(e_{c}\) and \(f_{c}\) of the first PE (PE\({}_{1}\)). From the second clock period until the \(r^{th}\) clock period of the third computation phase, control signal \(c\) is deactivated (\(c=0\)), facilitating the sequential passage of the signals \(e_{r-i}\), for \(i\) ranging from 1 to \(r\), through the input port \(e_{s}\), thereby allowing their effective use within each of the regular PEs (PE\({}_{j}\)). During these clock periods, control signals \(c_{1}\) and \(c_{0}\) retain their states (\(c_{1}=1\) and \(c_{0}=1\)), enabling all remaining sequential bits of the \(e_{r-i}\) and \(f_{r-i+1}\) signals, for \(i\) ranging from 1 to \(r\), to traverse the input ports \(e_{c}\) and \(f_{c}\), respectively. This ensures their availability for processing throughout these clock cycles. 9. At the conclusion of the third computation phase, control signal \(q\) is activated (\(q=1\)) to facilitate the transfer of the resulting intermediate bits of \(h\) to the accumulator (XOR gates and \(D_{h}\) latches) located at the output of each PE, as depicted in Figure 3. The obtained bits are added to the output bits previously stored in the \(D_{h}\) latches following the second computation phase. The output bits from the third computation phase will likewise be stored in the \(D_{h}\) latches, culminating in the final computation result of the hybrid systolic multiplier.