# Design of Static Random-Access Memory Cell for Fault Tolerant Digital System
## 2 Background
### Single Event Upset (SEU) and Radiation-Hardening Design Techniques  
In the memory of the digital circuit, SET can change the digital value at the storage nodes, leading to data flipping (0 \(\rightarrow\) 1 or 1 \(\rightarrow\) 0). This logical value change by SET is referred to as single event upset (SEU). In the conventional 6 T SRAM cell shown in Figure 1, the storage nodes Q and QB are not only the drains of access transistors (MX\({}_{1,2}\)) and pull-down transistors (MD\({}_{1,2}\)), which are nMOSFETs, but also are the drains of pull-up transistors (MU\({}_{1,2}\)), which are pMOSFETs. Thus, the Q and QB nodes are exposed to both polarities of SET, 0 \(\rightarrow\) 1 and 1 \(\rightarrow\) 0. For example, when Q = V\({}_{\text{DD}}\) and QB = 0 V, which means that the value of \"1\" is stored, an amount of charge can be collected to result in 1 \(\rightarrow\) 0 SET at Q node. This makes the QB node change from 0 V to V\({}_{\text{DD}}\) accordingly, so the memory cell state is changed into the value of \"0\", which means that the data are flipped erroneously. To enhance the robustness to SEU, there have been several radiation-hardening design techniques.  
First, layout-level techniques can be applied as in [2; 3; 4], such as shallow trench isolation, H-gate, and enclosed annular gate. Through shallow trench isolation, the charge injection node can be isolated from the charge collection node to reduce the possibility of SEU. Through the layout based on the H-gate or annular gate, the leakage current can be efficiently suppressed due to the unique shape of the gate. However, in the present sub-nanotechnology era, these techniques are unlikely to be applicable due to the highly constrained design rules.  
The triple modular redundancy (TMR) is one of the most widely used classical circuit-level radiation-hardened design techniques [5]. In TMR, three copies of memory cells are implemented to hold the identical data during the operation. For read accessing data, a majority voting circuit is employed to decide the final output as the majority data. In this manner, even if one cell stores incorrect data due to SEU, the other two copies keep the correct data, which are unchanged from the initial values. The voting process guarantees that the output data are correct. However, due to the requirement for implementing and operating three copies of hardware, there is a significant amount of area and power overhead.  
At the system level, the most well-known radiation-hardening design technique is the error correction code (ECC) [6; 7; 8; 9; 10; 11]. By writing the multi-bit word data after encoding them to follow a specific pre-determined policy, one or multi-bit error can be detected or corrected by decoding the data at the read-accessing phase. In other words, once some bits of the word are flipped by SEU, the bit sequencing of the word does not follow the pre-determined rule. By analyzing how the word violates the rule, the error bit can be found and corrected. However, applying ECC requires complex encoding and decoding circuits, which incurs a significantly large timing and power overhead.  
One of the most promising approaches to enhance the robustness for SEU, and thus the most widely used method, is to design a new hardened SRAM cell, instead of relying on the conventional 6 T SRAM cell. With this approach, most of the peripheral circuits and systems, and the architecture, are kept unchanged; only the memory cell is replaced with the new radiation-hardened SRAM cell design. Compared to the other approaches, utilizing the new memory cell design is efficient in terms of its practicality and performance. In the following section, various SRAM cell designs for radiation hardening are described in terms of their structure, operation, and key performance characteristics.