# Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM
## 3 Design of an Adaptive Fault Tolerance Mechanism
### Methodology
Figure 3: _Cont._  
\"ECC Encoder\" and \"ECC Decoder\" modules work like this:  
* During a write operation (see Figure 3d), the \"ECC Encoder\" calculates a code from the input data (adding a delay tenc), and both are stored together in the memory. * In a read operation, the encoded data are obtained from the RAM. The \"ECC Decoder\" uses the data part of the memory word read to calculate the corresponding code, and then, the calculated code and the stored code are compared, generating a syndrome vector. This syndrome vector will mark if an erroneous bit(s) is(are) present or not and if error(s) can be corrected or detected. If there are no errors (see Figure 3c, where tdec represents all the delay introduced by the decoder: syndrome generation and data correction), read data can be buffered and delivered to the control unit. If error(s) can be corrected, the output data will be corrected by the decoder and then buffered and delivered; also, the corrected data are re-encoded and written-back in the memory (see Figure 3e). In this case, the memory controller stops the processor during the write-back cycle by setting the \"MEMORY BUSY\" signal (see Figure 2). Comparing the timing diagrams of Plasma and Plasma_ADAPTIVE cores in Figure 3, we can assert how the ECC affects the operating frequency: the delays introduced by the ECC encoder and decoder may enlarge the minimum clock period, hence decreasing the maximum clock frequency. To implement the adaptive version of the memory controller, some considerations must be made first:  
1. Both \"ECC Encoder\" and \"ECC Decoder\" modules must implement the encoders and decoders of at least two different ECCs. When errors are detected, but cannot be corrected, the \"ECC Decoder\" module issues the \"Error Detected\" signal to warn the control unit. This signal is set under distinct circumstances, depending on the error correction and detection capabilities of the ECC used. Figure 3: Timing diagrams of read and write operations in Plasma and Plasma_ADAPTIVE cores. (**a**) Read cycle in Plasma core; (**b**) write cycle in Plasma core; (**c**) fault-free read cycle in Plasma_ADAPTIVE core; (**d**) write cycle in Plasma_ADAPTIVE core; (**e**) faulty read in Plasma_ADAPTIVE core. The system starts operating with the simplest ECC (let us name it ECC1). An _error monitor_ module monitors the occurrence of errors. As the memory degrades, either because the number of upsets increments or because errors in the same location repeatedly appear (manifesting the appearance of an intermittent fault), the _error monitor_ module should be able to detect the new error condition, and it may be necessary to change from current ECC (let us name ECC1) to another ECC (ECCj, j \(\
eq\) i) able to cope with the new error condition. If there are no more ECCs available after detecting a new error condition, the \"Adaptive Memory Controller\" should issue some warning or error signal to the control unit (e.g., see \"MULTIPLE INTERMITTENT ERRORS DETECTED\" in Figure 2). Error conditions are not supposed to improve, but only to get worse. That is, if fault multiplicity increases, it will not decrease back again. Similarly, once a bit has been labeled as \"error-prone\" (i.e., an intermittent fault has been detected in that bit), it will never be unlabeled. If anything, a second (or more) bit could also be labeled as \"error-prone\". To monitor the occurrence of errors, the _error monitor_ module contains a number of counters. From the error syndrome vector, the \"Syndrome Decoder\" indicates which bit(s) has/have failed, incrementing the corresponding counter(s). To count error events, we have based on the \(\alpha\)-count single threshold-based fault identification mechanism proposed by [PERSON] et al. in [8]:  
\[\alpha^{(L)}= \begin{array}{cc}\begin{pmatrix}\alpha^{(L-1)}+1&if\ J^{(L)}=1 \\ \alpha^{(L-1)}-dec&if&\begin{array}{c}J^{(L)}=0\ AND\ \alpha^{(L-1)}-dec>0,\\ 0\leq dec\\ 0&if\ J^{(L)}=0\ AND\ \alpha^{(L-1)}-dec\leq 0\end{array}\end{array}