# A Compact Thevenin Model for a Rectenna and Its Application to an RF Harvester with MPPT
## Appendix A Parallel Circuit Model of the Inductor and Diode  
The use of a matching network leads to sinusoidal voltage and current waveforms at \(f_{\mathrm{o}}\), as mentioned in Section 2. Here, the equivalent circuit model at \(f_{\mathrm{o}}\) is derived from the manufacturer models of the diode ([[https://docs.broadcom.com/docs/AV02-1377](https://docs.broadcom.com/docs/AV02-1377) EN]([https://docs.broadcom.com/docs/AV02-1377](https://docs.broadcom.com/docs/AV02-1377) EN)) and inductor ([[https://www.coilcraft.com/pdfs/spice_0603](https://www.coilcraft.com/pdfs/spice_0603) cs.pdf]([https://www.coilcraft.com/pdfs/spice_0603](https://www.coilcraft.com/pdfs/spice_0603) cs.pdf)) used for the implemented rectenna and reported in Section 4. This model will be used in the left-hand circuit of Figure 3.  
First, the left-hand circuit in Figure 3 shows the equivalent linear circuit model of the diode, connected between node A and the \(V_{\mathrm{o}}\) node at Figure 2, together with the output capacitor \(C_{\mathrm{o}}\), where \(R_{\mathrm{s}}\) is the parasitic resistance, \(C_{\mathrm{j}}\) is the parasitic junction capacitance, and \(R_{\mathrm{j}}\) is the junction resistance. \(R_{\mathrm{j}}\) depends inversely on the bias current and makes only sense for modelling small current variations around a bias current. In our case, the diode current is pulsed and thus the inclusion of \(R_{\mathrm{j}}\) is not appropriate. Instead, a constant voltage drop will be assumed in Section 2 for the analysis of the circuit of Figure 4.  
Using the series-to-parallel equivalent circuit transformation for the left-hand circuit of Figure 11 without \(R_{\rm j}\) and considering \(C_{\rm o}>>C_{\rm j}\), the right-hand circuit results, where:  
\[R_{\rm sp}=R_{\rm s}\frac{R_{\rm s}^{2}C_{\rm j}^{2}\omega_{\rm o}^{2}+1}{R_{\rm s }^{2}C_{\rm j}^{2}\omega_{\rm o}^{2}}, \tag{11}\]  
\[C_{\rm jp}=\frac{C_{\rm j}}{R_{\rm s}^{2}C_{\rm j}^{2}\omega_{\rm o}^{2}+1}. \tag{12}\]  
From the diode datasheet, \(R_{\rm s}\) = 25 \(\Omega\) and \(C_{\rm jo}\) = 0.18 pF (\(C_{\rm jo}\) is \(C_{\rm j}\) at zero bias and will be the assumed value for \(C_{\rm j}\) hereafter). With \(f_{\rm o}\) = 808 MHz, \(R_{\rm sp}\) = 47.9 k\(\Omega\) results from (11) and \(C_{\rm jp}\approx C_{\rm j}\) = 180 fF results from (12). As for the inductor, connected between node A and ground at Figure 2, the left-hand circuit of Figure 12 shows the manufacturer model, where \(R_{\rm v}=k\sqrt{f_{\rm o}}\). Using the series-to-parallel circuit transformation, the circuit in the middle is obtained, where:  
\[L_{\rm mp}=L_{\rm m}\Bigg{[}1+\left(\frac{R_{\rm v}}{\omega_{\rm o}L_{\rm m}} \right)^{2}\Bigg{]}. \tag{13}\]  
\[R_{\rm vp}=R_{\rm v}\Bigg{[}1+\left(\frac{\omega_{\rm o}L_{\rm m}}{R_{\rm v}} \right)^{2}\Bigg{]}, \tag{14}\]  
\[R_{\rm lp}=R_{1}\frac{R_{1}^{2}C_{1}^{2}\omega_{\rm o}^{2}+1}{R_{1}^{2}C_{1}^ {2}\omega_{\rm o}^{2}}, \tag{15}\]  
\[C_{\rm lp}=\frac{C_{\rm l}}{R_{1}^{2}C_{1}^{2}\omega_{\rm o}^{2}+1}. \tag{16}\]  
From the coil datasheet, \(R_{1}\) = 17 \(\Omega\), \(R_{2}\) = 30 m\(\Omega\), \(C_{1}\) = 49 fF, \(L_{\rm m}\) = 27 nH, and \(k\) = 5.75 \(\times\) 10\({}^{-5}\). At 808 MHz, \(R_{\rm v}\) = 1.63 \(\Omega\) and from (13) to (16), \(L_{\rm mp}\approx L_{\rm m}\) = 27 nH, \(R_{\rm vp}\) = 11.5 k\(\Omega\), \(R_{\rm lp}\) = 950 k\(\Omega\), and \(C_{\rm lp}\approx C_{\rm l}\) = 49 fF. Then, neglecting \(R_{2}\), since it is very small, the right-hand circuit of Figure 12 is obtained, where \(R_{\rm Lp}=R_{\rm vp}\|R_{\rm lp}=11.4\) k\(\Omega\). Joining the right-hand circuits in Figures 11 and 12, and considering the parasitic capacitance from node A to ground arising from the layout (\(C_{\rm lay}\)), the circuit in Figure 13 is obtained, where:  
\[R_{\rm p}=R_{\rm sp}\|R_{\rm Lp}=9.21\ {\rm k}\Omega, \tag{17}\]  
\[C_{\rm p}=C_{\rm lp}+C_{\rm lp}+C_{\rm lay}. \tag{18}\]  
Figure 4.0 (**left**) Manufacturer model of the inductor and (**middle** and **right**) equivalent circuits.