## 1 Introduction  
The human life has been simplified and security enhanced by the space industry, which provides various utilities such as satellite communications, military surveillance, guidance, and tracking systems. In the aerospace sector, satellites play a crucial role [1]. The performance of satellite communication and control relies on processors, and improving these processors necessitates the use of more high-performance cores. To support these cores, additional cache memory is required [2], and the primary memory device used for this cache memory is static random access memory (SRAM). Therefore, the performance and reliability of SRAM are vital in the aerospace industry. Space contains radiation and high-energy charged particles [3]. These particles collide with the channel of the MOSFETs that make up SRAM, forming electron-hole pairs. The generated electron-hole pairs drift towards the channel due to the reverse bias formed between the channel and the substrate (or NWell). This results in the generation of an unintended pulse. If such a pulse is applied to a memory cell over a sufficient magnitude and duration, it can flip the stored data value in the cell [3]. Semiconductor devices have become more susceptible to single-event upsets (SEUs) [1]. This is largely due to the emphasis on miniaturization in various semiconductor-based industries, including memory. Consequently, it is critical to enhance SEU resistance for reliable semiconductor designs. Current technologies can also induce single-event multiple-node upsets (SEMNUs). This phenomenon occurs due to charge-sharing, where a single charged particle simultaneously affects multiple nodes. If the affected nodes belong to the same memory cell, it results in an SEU; if they belong to different cells, it leads to an SEMNU [4,5]. Triple modular redundancy (TMR) is frequently used in memory systems to mitigate the effects of SEUs. This approach stores a single bit of data across three separate cells, ensuring data retention through majority voting even if one cell encounters an SEU. However, TMR significantly increases area and power consumption [6,7]. Similarly, error correction code (ECC) provides memory fault tolerance but requires additional circuitry and memory cells for encoders and decoders, introducing considerable area, power, and delay overhead [8,9]. In traditional 6T SRAM, data storage is managed through a latch formed by cross-coupled inverters. An SEU-induced alteration at one storage node is likely to change the value of the opposing node in the feedback loop, effectively reversing the stored bit [10]. Conventional 6T SRAM is highly vulnerable to SEU effects. To combat this, research has focused on modifying SRAM cell architectures [9,11,12,13,14,15,16]. For instance, the QUATRO-10T cell introduced in [11] uses negative feedback to help mitigate SEUs; however, it only provides immunity when storing a logic high. Nodes storing a '0' remain susceptible to upset, resulting in partial immunity and suboptimal read/write performance. An improved write capacity was later offered by the WE-QUATRO cell [12], but it still lacks complete SEU protection at '0'-storing nodes and only minimally enhances read stability. Similarly, the QUCCE12T cell from [9] aims to minimize layout area using refined wiring but fails to adequately restore SEUs at '0' nodes, offering only slight improvements in read stability. Overall, these architectures provide only partial SEU resistance. The DICE cell [13], designed for SEU tolerance, can recover from SEUs across sensitive nodes but neglects SEMNU protection where multiple nodes are simultaneously affected. The RHD12T cell proposed in [14] addresses SEMNU recovery within certain node pairs, though it still cannot withstand SEUs at '0' nodes and has increased leakage power. The RSP14T cell [15] improves SEU immunity and reduces leakage yet still faces high leakage issues. The RHPD14T cell [16] attempts to diminish SEMNU susceptibility with its polar design, enhancing specific node robustness against SEUs.