## 3 Results and Discussion
Figure 3c delineates the transfer characteristics subsequent to the application of a 12 V programming voltage for 10 ms, culminating in a \(\Delta\)V\({}_{\text{th}}\) of 3.2 V. Conversely, administering a \(-\)14 V negative gate pulse for an analogous duration almost restores the Id \(-\) Vg curve to its foundational state, reflective of the device's pristine condition. Moreover, as illustrated in Figure 3d, imposing a \(-\)14 V negative bias pulse on the gate for 10 ms induces a leftward deviation in the device. The subsequent application of a positive 12 V bias pulse for the identical duration remarkably reinstates the device to its original state. This observation is particularly salient as it divulges that the P/E action's duration remains uniform across both voltage polarities, furnishing substantial benefits for MLC applications predicated exclusively on voltage bias modifications [19; 20]. Figure 4 presents an in-depth examination of the memory's data retention properties at both ambient and elevated temperatures (100 \({}^{\circ}\)C), meticulously documenting how the device sustains its charge over extended periods. The investigation into retention characteristics spanned an initial duration of 10\({}^{5}\) s, with findings subsequently projected across a decade to ascertain the extent of charge dissipation following prolonged operational periods of the memory device. The changes in threshold voltage of the device were measured at normal room conditions for different states: unprogrammed (fresh), after programming, and after erasing. The measurements were conducted over a period of 10\({}^{5}\) s. In the case of unaltered devices, the variance in threshold voltage (V\({}_{\text{th}}\)) remained notably insignificant throughout the retention assessment period. Conversely, for units subjected to a 12 V programming pulse for a 10-millisecond interval, a discernible contraction in the storage window was recorded, diminishing to 2.87 V in comparison to the unprogrammed state as the duration of retention progressed. Similarly, when components were subjected to a \(-\)14 V pulse for the same amount of time, the window size decreased to 2.4 V by the end of the 10\({}^{5}\) s evaluation. This decrease is mainly attributed to the discharge of charge from the amorphous indium-gallium-zinc oxide charge storage layer. These findings collectively underscore the flash memory's robust capacity for data preservation and its exemplary retention attributes. When subjected to a high-temperature environment (100 \({}^{\circ}\)C), the storage window significantly decreased due to increased charge migration, which directly corresponds to a reduction in defects within the charge trapping layer. Notwithstanding the incremental diminution of the storage window as retention time extended, the device successfully maintains ample storage capacities of 4.4 V and 3.7 V after a decade (3 \(\times\) 10\({}^{8}\) s) under both ambient and elevated temperature conditions, respectively. These measurements affirm the practicality of deploying such metrics within the realm of non-volatile flash memory solutions, highlighting their suitability and reliability for long-term data storage applications [21]. Figure 5a illustrates a comparison of specimens with different thickness configurations, providing insight into the complex balance needed to optimize memory device functionality by tailoring layer thickness. The engineering of the tunneling layer presents a crucial balance challenge: it needs to be thin enough to allow charge tunneling, but also thick enough to ensure good charge retention. However, excessive thinness undermines this requirement for thickness. Opting for a 5 nm thickness achieves an ideal compromise, ensuring that the tunneling layer remains adequately slender to support efficient charge transit while preserving the structural integrity vital for the device's consistent performance. The development of the blocking layer adds another dimension of complexity.