## 1 Introduction
Secondly, the digital signals are transmitted into the field-programmable gate array (FPGA). Then, the digital signals are buffered in the FPGA. Finally, the reorganization of the signals is completed in the FPGA or computer. There are many mathematical operation modules in the FPGA or computer. Additionally, these mathematical operation modules can be used for digital calibration methods. Therefore, it is of practical significance to study digital calibration methods to reduce the accuracy requirements of analog circuits. In the continuous-time wide-sense stationary (WSS) signal, the offset can be estimated using the mean, and the gain can be estimated using the standard deviation. The estimation of time skew and bandwidth mismatch can be divided into three strategies: (a) reference ADC [9]; (b) autocorrelation of the signal [13]; (c) fractional delay filter. There are the following three disadvantages to the strategy of reference ADC: (1) additional reference  
Figure 1: Conceptual graph of an \(M\)-channel time-interleaved analog-to-digital conversion system. ADC significantly increases power consumption and hardware overhead [23]. (2) The reference channel will generate additional spurs by changing the input impedance of the TI-ADC [24]. (3) alternating the reference ADC with a single comparator can result in a slow convergence [25]. These disadvantages do not exist in the all-digital calibration strategies of autocorrelation of the signal or fractional delay filter. However, there is high computational complexity, a limitation in the first sub-ADC bandwidth, and slow operational speed for all-digital calibration strategies, which adopt autocorrelation of the signal or fractional delay filter. A digital calibration technique for timing skew is proposed in the reference [26]. However, this technique cannot deal with the gain mismatch. In this paper, a new parameter vector is proposed to correct gain, time skew, and bandwidth mismatch simultaneously. Firstly, compared with the techniques calibrating time skew by the Taylor series [10; 13], the proposed approach enables a wide range of time skew mismatch compensation. Secondly, the proposed parameter vector has a smaller number of filter taps than the derivative filter [10; 13] or Hilbert filter [27]. Therefore, fewer computing resources are used to correct the input signal after obtaining the proposed parameter vector. Then, ref. [16] limits its application to the TI-ADCs with specific channel numbers to ensure there are Hadamard transforms for the given channel number. However, the proposed algorithm is not limited by the number of channels. Finally, the proposed parameter vector is estimated with the bandpass fractional delay filter and least squares (LS) algorithm. Based on the bandpass fractional delay filter, the proposed technique can work for ultra-high frequency signals. Additionally, there are matrix inversions in the LS algorithm. The implementation of matrix inversion within FPGA is complex. Therefore, solving a system of linear equations is used to replace matrix inversions. The structure of this paper has the following parts: Section 2 describes the TI-ADCs model, the characteristics of offset, gain, time skew, and bandwidth mismatch, and the correction of these mismatches. Section 3 explains how to apply the LS algorithm to estimate gain, time skew, and bandwidth mismatch. Section 4 explains the bandpass fractional delay filter and the alternative method of the matrix inversion and validates the proposed technique by showing results from simulation and measurement. In the end, Section 5 concludes this article.