## 3 Design of a Memory-Efficient Lightweight Object-Detection Model
### Design of a Lightweight Backbone Network Based on FasterNet  
PConv, by processing only a subset of feature channels, significantly reduces memory requirements compared to DSC. Consequently, The FasterNet backbone is integrated with PConv for efficient feature extraction. Figure 5 illustrates the structure of the FasterNet backbone used in the model, comprising four groups of FasterNet modules. Each feature map initially passes through either an embedded layer (with a 4 \(\times\) 4 kernel and a stride of 4) or a merging layer (with a 2 \(\times\) 2 kernel and a stride of 2) before entering the FasterNet modules, facilitating downsampling and channel expansion. In the implementation, each FasterNet module comprises a 3 \(\times\) 3 PConv with padding of 1 and a stride of 1, reducing the input dimension to a quarter. This is followed by two pointwise convolutions, each with a 1 \(\times\) 1 kernel and stride, which modulate the dimensions of the output from the PConv to ensure comprehensive integration and extraction of features. After the first pointwise convolution, the output is processed through a batch normalization (BN) layer followed by a ReLU activation function. The arrangement of FasterNet modules varies across the groups: one module in the first group, two in the second, eight in the third, and two in the fourth. The feature maps generated by the second, third, and fourth groups are then directed to a multi-scale feature-fusion module. Originally, the FasterNet series included variants like FasterNet-T0/T1/T2 and FasterNet-S/M/L, differing primarily in the number of modules per group and the dimensions of features processed. The configuration of these dimensions, \(c_{1}\), \(c_{2}\), \(c_{3}\), and \(c_{4}\), is critical in determining the parameter count and computational cost. For instance, FasterNet-T0 features dimensions of 40, 80, 160, and 320, with a parameter count of 3.9 M and a computational cost of 0.34 GFLOPs. However, in the context of ultra-lightweight models, these parameters are relatively high, with leading models like FastestDet exhibiting parameter counts as low as 0.24 M.  
To address this short coming, the FasterNet structure is refined to create FasterNet-16, a more streamlined model tailored for embedded devices that enhances feature-extraction  
Figure 4: Detailed structure of PConv. capabilities without the heavy computational load. Each FasterNet module in FasterNet-16 integrates a \(3\times 3\)PConv, two \(1\times 1\) pointwise convolutions, and residual connections to improve feature integration and system resilience. Each FasterNet module not only includes PConv and pointwise convolutions but also introduces residual connections. Residual connections effectively mitigate the vanishing gradient problem in deep networks, promote feature reuse, and improve training efficiency and performance. As shown in Figure 5, the number of FasterNet modules in each group varies: the first group uses one module, the second group uses two, the third group uses eight, and the fourth group uses two. Ultimately, the multi-scale feature maps extracted by these modules are fed into the multi-scale feature-fusion module for feature fusion. The detailed structure of FasterNet-16 backbone is shown in Table 1. In Table 1, \"Conv_k_c_s\" denotes a standard convolution with kernel size \(k\), output channel count \(c\), and stride \(s\). \"PConv_k_c_s_r\" represents a partial convolution with an additional parameter \(r\), indicating the proportion of channels that undergo partial convolution, refining the computational efficiency. \(H\times W\) represents the dimensions of the input feature map, while \(b_{i}\) indicates the number of modules in each FasterNet group.