## 2 Design and Implementation
### RF Power Harvesting Design-II  
This subsection investigates the power harvesting method from the wireless radio frequency (RF) wideband of operations. It is well known that RF wireless power harvesting holds vast potential for replacing batteries or increasing life spans. Therefore, this research work introduces a CMOS based RF power harvesting circuit; the schematic is shown in Figure 5a. The architecture of CMOS IC consists of power harvesting stages, storage capacitors, and filtering network. The corresponding noise power is achieved at the output when frequency bands are considered in division stages and they are varied at the input of power harvester circuit stages. Finally, smooth and regulated DC output powers are obtained at the output of T-shape filtering network ranging from mW to Watt. An efficient rectifier, on-chip capacitor, and robust power are essential for RF power harvesting system. In order to avoid the junction and oxide breakdown of the transistors in previous metal oxide semiconductor (MOS) technologies, we employ the new rectifier scheme as shown in Figure 5a. Figure 5: _Cont._  
To enhance the rectifier sensitivity, using CMOS process provides a lower threshold operation for the diodes that are realized using P-type metal oxide semiconductor (PMOS) transistors, where the body terminal tied to the source in order to eliminate the body effect. The considered threshold voltage operation of the PMOS transistor in forward bias can be expressed as in (1) [25]. \[\mathrm{V_{thp}}=\mathrm{V_{thdp}}-\gamma\big{(}\sqrt{|2\varnothing_{\mathrm{F}}- \mathrm{V_{sb}}|}\big{)}-\sqrt{|2\varnothing_{\mathrm{F}}|} \tag{1}\]  
where \(\mathrm{V_{thdp}}\) is zero threshold voltage when substrate voltage (\(\mathrm{V_{sb}}\)) is zero,\(\gamma\) is the body effect coefficient, and \(2\varnothing_{\mathrm{F}}\) is the surface potential. The considered drain current operation for PMOS transistors for calculating power at each stage can be expressed as in (2). \[\mathrm{I_{ds}}=\mathrm{I_{B}}\Big{(}\frac{\mathrm{W}}{\mathrm{L}}\Big{)} \bigg{(}e^{(\frac{\mathrm{V_{d}}}{\mathrm{I_{ds}}})}-e^{(-\frac{(n-1)\mathrm{V _{d}}}{\mathrm{n\varnothing_{\mathrm{t}}}})}\bigg{)} \tag{2}\]  
where \(\mathrm{V_{d}}\) is drain voltage \(\mathrm{I_{ds}}\) is the current through channel of the transistor with its negative direction from drain to source, \(\mathrm{W}\) is the channel width, \(\mathrm{L}\) is the channel length, \(\varnothing_{\mathrm{t}}\) is the thermal voltage and equals to 26 mV at room temperature and \(\mathrm{n}\) is the slope factor, respectively. The proposed schematic consists of stacked power harvesting stages because it avoids additional DC power losses and provides a power combining technique. Here, it is noted that the reason for choosing a two stage stacked techniques is to maintain a design trade-off between output power and impedance matching. In power harvesting circuit, each stage consists of four diode-connected transistors named as M1 to M4 and M1\({}^{\prime}\) to M4\({}^{\prime}\), respectively. The coupling capacitors C1 to C4 pass the RF signals that correspond to each stage to provide an unregulated DC signals. The T-network employed for filter operation corresponds to unregulated DC signals and obtains the regulated output DC power ranging from milliWatt to Watt. A schematic of power harvesting circuit is analyzed and implemented using commercial CMOS process design kit on Advanced Design RF Simulator (ADS), which can be seen in Figure 5a. While the microchip photograph of the power harvester circuit along with on-chip antenna in single platform IC is shown in Figure 5b where on-chip filtering network takes only 12% area of the whole chip. The chip fabrication is done by using commercial 65 nm Samsung CMOS process. The fabrication of metal-insulator-metal layer is employed for the passive components. The area of the on-chip antenna and power harvesting IC are calculated as \(1.4\times 2.3\) mm\({}^{2}\).