## 3 The Design Process for an Aging Sensor with Multiple Points of Frequency Detection  
Figure 3 presents the proposed flow of aging sensor detection. The aging sensor detector has two main inputs, which are the clock (_Clk_) and voltage (_Vi_); the clock skew effect is negligible [51; 52]. This detection circuit will produce seven ranges of phase point detection ranging from 0\({}^{\circ}\)/360\({}^{\circ}\) to 300\({}^{\circ}\) with a 50\({}^{\circ}\) resolution. Phase point detection is a technique that segregates the detection process of the delay signal into several types of frequency detections. Each detection process ranging from 0 to 49\({}^{\circ}\) represents level 0, while the phase detection range of 50-99\({}^{\circ}\) represents level 50, and so forth. The total delay time for level 0 was from 0 s to 1.39 ns, and level 50 was from 1.39 ns to 2.78 ns. Therefore, the detection process was applicable only if the frequency of _Vi_ was less than the frequency of the _Clk_ such that it produced a successful detection. The _Clk_ was synchronized to the clock of the FPGA circuit using a clock generator that provided a stable clock for the entire system. The input signal originated from an external clock, and the output produced was a synchronous clock called _clk_cntrl_, which triggered the _Clock Delay_ and circuit under test (CUT) modules. The _Clk_ may originate from the various FPGA manufacturers with different intellectual properties (IPs). The Xilinx FPGA used in this work has a reset input and locked outputs that are used for initialization purposes. There is also an indicator called a clocking wizard (CW) signal that is fully stable. The Xilinx FPGA board provides an IP that requires 69 clock cycles to stabilize the clock. For the proposed aging sensor circuit, the programmer requires the CW to conduct a frequency synthesis and phase alignment to manipulate the frequency and duty cycles of the synchronized clock. Based on this CW specification, two clock inputs served as the primary and secondary clocks, respectively, ranging from 10 MHz to 700 MHz. The maximum outputs produced were seven clock outputs with frequencies ranging from 5 to 700 MHz and phase degrees between 0 and 360\({}^{\circ}\). The CW initial setup provides the desired and actual frequency for input and output frequency configurations [53]. This initial setup is essential for the accuracy of the design for the multiple-point phase degrees chosen. For the 40 nm Virtex-6 FPGA board, the maximum output capabilities of the CWs can produce up to seven different frequencies [53]. However, the CW configurations for other FPGA manufacturers have varying limitations and settings. The CW can be rearranged in series  
Figure 3: The schematic diagram for an aging sensor detector. or parallel or a combination of series and parallel for better phase-detection ranges to cater to this matter. For the proposed aging sensor, the duty cycles were set to 50%. Therefore, only a single clock with the same frequency is used for the input and output of this clock generator circuit. The clock delay module uses a separate CW to generate seven different output phase delays sequentially. It used _clk_cnttrl_ as the input and _clk_x_ at the output, where \(x\) represents the phase shift frequencies. The phase shift frequencies were set to \(0^{\circ}/360^{\circ}\), \(50^{\circ}\), \(100^{\circ}\), \(150^{\circ}\), \(200^{\circ}\), \(250^{\circ}\), and \(300^{\circ}\). All shifting in the phases acts after the _clk_cnttrl_ signal. The CUT and the clock delay modules subsequently feed their respective signal into the comparator module. The comparator module consequently obtain the correct correlation between the signals it received from the CUT module with the phase shift frequencies fed from the clock delay module. Each correlated phase shift frequency corresponds to a particular range of the remaining lifetime. The CUT module consists of a _Vi_ input, a clocking input (_clk_cnttrl_), and an output (Q\({}_{\text{d}}\)).