## 2 Proposed SST Circuit, Specifications and Control Layout
### Control Layout of the SST-Voltage Source Inverter  
Three phase two level voltage source inverters (VSIs), consisting of two power electronic switches in each leg, have penetrated in the industry as they provide various speed control demands of induction motor drives. A two level VSI has six active states and two null states. Various PWM techniques are proposed in [33; 34] to reduce the VSI output waveform distortions at a given switching frequency. The most popular one is the space vector PWM as it provides low output current ripple and provides maximum utilization of the DC -link voltages [35; 36]. It provides 15% higher ac voltage, lower current and voltage harmonics distortions as compared to conventional PWM [37]. This is the reason that SVPWM as a modulation technique is employed in this research. The active states divide the space vector plane into six sectors of equal magnitude as shown in Figure 4. Switching states for all eight (six active and two null) vectors are shown in Table 2.  
Using SVPWM, desired three phase voltages are provided by the voltage vector controlled in the d-q rotating frame as shown in Figure 4, whose rotation is sampled in every sub-cycle \(T_{s}\). Figure 5 shows the component of the reference voltage vector of magnitude \(V_{\textit{ref}}\) along the \(\alpha\) and \(\beta\)-axis in sector \begin{table}
\begin{tabular}{c c c c} \hline \hline  & **Nominal Voltage** & **Specifications** & **Impedance** \\ \hline Ac grid & 11 kV & 200 kVA & \(R=1\,\Omega\,L=100\) mH \\ DC -link & 20 kV & & \\ DC -capacitor & 20 kV & Single 880 μF & \\ \hline \hline \end{tabular}
\end{table} 
Table 1: VSC specifications for SST. Figure 4: Vector representation of the SVPWM signal. I whereas, \(T_{1}\), \(T_{2}\) and \(T_{x}\) are dwell times for which the active voltage vector \(V_{1}\), active voltage vector \(V_{2}\) and null vectors are applied in a sub-cycle \(T_{s}\), such that the following relation is always satisfied. \[T_{S}\,=\,T_{1}\,+\,T_{2}+\,T_{Z}. \tag{16}\]  
Consequently, the applied gating sequence of sector I is depicted in Figure 6.  
Volt-second balance equations along the \(\alpha\)-axis and \(\beta\)-axis are given as:  
\[V_{ref}\times T_{S}\times\cos(\alpha)\,=\,\frac{2}{3}\,V_{dc}\Big{\{}T_{1}\,+ \,T_{2}\times\cos(\frac{\pi}{3})\Big{\}}. \tag{17}\]  
\[V_{ref}\times T_{S}\times\sin(\alpha)\,=\,\frac{2}{3}\,V_{dc}\times T_{2}\times \sin(\frac{\pi}{3}). \tag{18}\] \begin{table}
\begin{tabular}{c c c c c c} \hline \hline \multirow{2}{*}{**Vector**} & \multirow{2}{*}{**Sector \& Vector Combination**} & \multicolumn{3}{c}{**Line to Line Voltage**} & \multirow{2}{*}{**State**} \\ \cline{3-3} \cline{5-6}  & & & \(V_{ab}\) & \(V_{bc}\) & \(V_{ca}\) \\ \hline \(V_{0}\) (000) & & & 0 & 0 & Zero \\ \(V_{1}\) (100) & I & \(V_{0}\), \(V_{1}\), \(V_{2}\), \(V_{7}\) & \(+V_{4}\) & 0 & \(-V_{d}\) & Active \\ \(V_{2}\) (110) & II & \(V_{7}\), \(V_{2}\), \(V_{3}\), \(V_{0}\) & 0 & \(+V_{d}\) & \(-V_{d}\) & Active \\ \(V_{3}\) (010) & III & \(V_{0}\), \(V_{3}\), \(V_{4}\), \(V_{7}\) & \(-V_{d}\) & \(+V_{d}\) & 0 & Active \\ \(V_{4}\) (011) & IV & \(V_{7}\), \(V_{4}\), \(V_{5}\), \(V_{0}\) & \(-V_{d}\) & 0 & \(+V_{d}\) & Active \\ \(V_{5}\) (001) & V & \(V_{0}\), \(V_{5}\), \(V_{6}\), \(V_{7}\) & 0 & \(-V_{d}\) & \(+V_{d}\) & Active \\ \(V_{6}\) (101) & VI & \(V_{7}\), \(V_{6}\), \(V_{1}\), \(V_{0}\) & \(+V_{d}\) & \(-V_{d}\) & 0 & Active \\ \(V_{7}\) (111) & & & 0 & 0 & 0 & Zero \\ \hline \hline \end{tabular}
\end{table} 
Table 2: Space vectors state and the switching sequence. Figure 5: Vector representation of the SVM signal in sector 1. Figure 6: Gating sequence for the switches.