## 3 Future CONERSTONE Platforms
### Pick-and-Place of Light Sources onto SOI  
Although there are a variety of different technologies to integrate III-V active devices on SOI chips, these can be broadly classed into three main groups, namely heteroepitaxial growth, wafer or die bonding and flip-chip integration [152]. Heteroepitaxial growth of III-V semiconductor layers on a Si substrate would provide the ideal route for large scale industrial manufacturing of PICs; however, current technology in this area lacks the required reliability and performance. In fact the large lattice constant mismatch between silicon and III-V materials such as GaAs and InP, and the formation of antiphase domains at the III-V/silicon interface pose major technological challenges that affect the quality of the epitaxial layers [153]. In the wafer or die bonding approach, most commonly called heterogeneous integration, pieces of III-V material are bonded onto a patterned Si wafer followed by substrate removal and then processed using standard lithography tools [154; 155]. The two most exploited bonding techniques are covalent molecular direct bonding and adhesive bonding using polymers, each with its own advantages and limitations [156]. Wafer bonding allows for very high accuracy lithographic alignment of the III-V devices as it employs the same registration markers used for the SOI chip fabrication; however, this requires running fully processed silicon PIC wafers through an III-V foundry. An alternative  
Figure 18: The integrated Si photonics receiver. (**a**) Circuit diagram of the balanced PD integrated with a CMOS transimpedance amplifier (TIA), (**b**) microscope image of the Si photonics receiver, (**c**) measured results at 40 Gb/s OOK and (**d**) measured results at 64 Gb/s PAM-4 (reprinted from [151], The Optical Society, 2020). approach that circumvents this limitation is transfer printing, in which fully fabricated III-V membrane devices are directly transferred and bonded onto the SOI chip [157]. Transfer printing retains the advantages of a full post-fabrication process at the expense, however, of a more complicated III-V fabrication processing that require the release of the III/V membranes from the native substrate, usually achieved through selective wet etching of a sacrificial layer [158]. Additionally, transfer printing does not provide a good heat flow when only Van der Waals forces are used for the bonding. In fact, efficient heat dissipation is a prime requirement of any heterogeneous integration technique as it directly impacts the reliability, lifetime and performance of the III-V active devices. This issue can be mitigated by using a metal, e.g., gold, as a bonding layer [159] or by bonding the membrane directly on the Si substrate after removal of the SiO\({}_{2}\) BOX layer [160; 161]. The use of thin III-V membranes in the wafer bonding and transfer printing approaches is ideal to implement vertical mode coupling via efficient adiabatic mode coupling between III/V and SOI waveguides or to design hybrid coupled modes [162; 163; 164; 165]. Although wafer bonding technology has substantially progressed in the last decade, hybrid integration by flip-chip bonding III-V active devices onto SOI chips is still the industry standard for the manufacturing of PICs in large markets such as telecoms and data centers [166; 167; 168]. In this approach, prefabricated III-V active devices are picked and placed onto silicon photonic chips usually with microgrippers [169; 170] and attached to the host substrate via metal-to-metal flip-chip bonding. Crucially, because integration by flip-chip bonding is a post-fabrication technique it allows to independently optimize and prescreen devices fabricated in different foundries, which adds substantial design flexibility, reduces packaging cost and improves device yield. One major requirement of flip-chip integration is an accurate and robust alignment process to minimize the insertion losses that arise by any misalignment between the III/V active devices and the SOI waveguides.