## 5 Experimental Results
### Performance Analyses of Hardware Processing  
During the experiment, the \"Key Stream Generator\" first utilized the micro-processor to execute the RC4 algorithm, which was designed in pure software using the C language. Measurement of experimental data revealed that the initialization of the S-Box memory content took approximately 618 \(\upmu\)s. Subsequently, generating ten thousand 8-bit key stream blocks required about 30,597 \(\upmu\)s. As shown in the experimental results in Figure 11, in comparison, the \"Key Stream Generator\" designed in Verilog language took approximately 25.78 \(\upmu\)s from reset to generating the first key stream block. This time is mainly used for initializing the content of the S-Box memory.dis  
Figure 10: SG-DMA execution flow from the interrupt configuration to performance calculation.  
Figure 9: Design components of SG-DMA.  
The operating frequency of the FPGA development board used in this system is 50 MHz (i.e., 20 ns per clock cycle), indicating that the \"Key Stream Generator\" requires a startup time of 1289 clock cycles (=25.78 \(\upmu\)s/(20 ns/cycle)). Figure 12a shows that, utilizing the \"HW Generator\", the initialization of the S-Box memory content only requires 4.19% (25.78 \(\upmu\)s/616 \(\upmu\)s) of the time needed by \"Pure \(\upmu\)P\" processing when that computation is performed by the micro-processor alone.  
After the system startup, as shown in Figure 12b in the solid blue box (a zoomed-in portion of key stream block generation from the previous Figure 11), a key stream block can be generated every 5 clock cycles of 100 ns (=20 ns \(\times\) 5 = 100 ns = 100,000 ps), at the shortest. Accordantly, to generate ten thousand key stream blocks, it would take 50,000 clock cycles or an operating time of 1000 \(\upmu\)s (100 ns \(\times\) 10,000). Figure 13a evaluates the real system performance for generating ten thousand key blocks by \"Pure \(\upmu\)P\" and \"HW Generator\", respectively. It illustrates that the \"HW Generator\" consumes only 3.27% (1000/30,597) of the time required by \"Pure \(\upmu\)P\" processing.  
This sub-section illustrates the performance enhancement achieved through hardware processing of the \"Key Stream Generator\", yet the key blocks generated by it could be repeated. The reuse of key blocks raises the risk of encrypted data being compromised, as discussed in the conventional cipher methods in Sections 3.1 and 3.2. The significant contribution of this paper lies in achieving theoretical un-breakability, as proven by [PERSON] [16], through the proposed OTP\({}^{3}\) secure mechanism, which requires non-repeating key blocks for data encryption. However, the non-repeating check is computationally intensive in the proposed OTP\({}^{3}\) secure mechanism, as detailed in Sections 3.3 and 3.4. Accordingly, the subsequent subsection will present experimental results to address this issue.  
Figure 11: Initialization of S-Box memory and starting key stream generation for activating a hardware stream generator.  
Figure 12: (**a**) Performance comparison depicted in percentage on the y-axis of pure software (Pure \(\upmu\)P) processing and hardware key stream generator (HW Generator) on the x-axis for S-Box memory initialization. (**b**) Consecutive generation of multiple key stream blocks after activating the HW Generator.