# An 8 kb RRAM-Based Nonvolatile SRAM with Pre-Decoding and Fast Storage/Restoration Time
## 2 RRAM-Based nvSRAM Structure and Memory Cell
### Memory Cell Design  
The memory cell of nvSRAM is mainly composed of SRAM and nonvolatile cells. The improved 8T2R nvSRAM memory cell proposed in this paper is shown in Figure 2. A pair of 1T1R RRAM are added to the traditional 6T SRAM storage nodes. While maintaining the traditional functions of SRAM, the data storage and data restoration functions are realized by controlling the memory cells of the RRAM. Different from the previous research, in the 1T1R structure, one end of the NMOS transistor is connected to the storage node, and the other end is connected to the lower electrode of the RRAM [22; 23; 24; 25; 26]. The gate of the transistor is controlled by the new signal RWL, and the upper electrode of two RRAMs is controlled by RBL and RBLB, respectively. Since bipolar RRAM is used, when the RRAM performs set and reset operations, different voltages are applied to the upper and lower electrodes of the RRAM to control the change in resistance. The upper electrode of the RRAM is introduced into independent control signals, and the resistance value of the RRAM is controlled through a driving circuit and power control circuit. Only when the RWL signal is turned on can the data of the SRAM and RRAM be transmitted, so that the static power consumption is zero when the NVM is not working. Under normal circumstances, nvSRAM performs read and write operations. Only when the voltage of the SRAM drops to a certain value, will the system switch to the data storage mode, and the data are stored in RRAM. The voltage required during this period is provided by the outside system. When the voltage of the SRAM is restored, the data restoration operation starts to restore the data in RRAM to the storage node of the SRAM. The Memory cell truth table is shown in Table 1.  
Figure 2: (a) 8T2R nvSRAM memory cell, (b) 128 \(\times\) 64 array. The principle of data storage operation is shown in Figure 3. When Q = 0, QB = 1, the supply voltage of nvSRAM is VD, WL and RWL are low, and nvSRAM maintains the data retention mode of SRAM at this time. Through turning off MN3 and MN4, the two bit lines free the data of the storage node from the interference of the BL and BLB signals. Meanwhile, RRAM1 and RRAM2 on both sides are in the state of high resistance and low resistance, respectively. When the system power supply fails, the nvSRAM enters the data storage mode. At this time, the voltage VD is switched to RVD, which is controlled by an independent power control circuit and is greater than VD. When the power supply rises, the voltage of storage node QB will rise to RVD with the change in power supply, while the voltage of Q is still 0. Both RBL and RBLB are connected to the read-write drive circuit of the RRAM. When the signal Store is valid and the signal Program is high, the voltage of RBL and RBLB becomes RVD through the control of the write drive circuit. When decoded by the address decoding control circuit, the RWL is high, making MN5 and MN6 turn on. Then, the upper electrode of RRAM1 is RVD, and its lower electrode is connected to storage node Q through the drain of MN5. While the voltage of storage node Q is 0, RRAM1 performs a set operation. This changes the resistance value of RRAM1 from high to low and completes the operation of writing 0. The upper electrode of RRAM 2 is also RVD, and its lower electrode is connected to storage node QB through the drain of MN6. Therefore, the voltage of storage node QB is RVD, which makes the voltage difference between the upper and lower electrodes of RRAM2 small, so RRAM2 maintains the current resistance value. Similarly, when signal Store is valid and signal Program is low, the voltage of RBL and RBLB becomes low through the control of the write drive circuit. After decoding by the address decoding control circuit, the RWL is high, which makes MN5 and MN6 on. At this time, the upper electrode of RRAM2 is low, and the lower electrode is connected to storage node Q through the drain of MN6. The voltage of storage node Q rises to RVD with the rise in the power supply voltage.