## 1 Introduction  
Over recent years, the evolution of amorphous indium-gallium-zinc oxide (a-IGZO)-based thin film transistors (TFTs), integrating the technology of non-volatile charge trap memory (CTM), has captivated the interest of both academic researchers and industrial practitioners [1]. The main reason for this interest lies in their unique characteristics, such as their ability to achieve high electron mobility, which allows for fast data manipulation; their capacity for optical transparency, which enables the development of transparent electronic devices; and their ability to be manufactured at low temperatures. This adaptability is particularly important for merging with pliable substrates and for the diminution of fabrication expenses. Among the most prominent features of these devices is their exceptional efficiency in programming, marked by considerable variations in threshold voltage (\(\Delta\)Vth), a fundamental requirement for the dependable archiving and retrieval of data within memory frameworks. Extensive research has been conducted to enhance the functionality and efficiency of non-volatile memories by exploring different materials suitable for the charge trap layer, which are different from those used in the tunneling or barrier layers [2; 3]. Predominantly, silicon nitride has been selected as the trapping layer [4] owing to its superior capabilities in charge trapping, whereas the construction of tunnel and barrier layers has involved a variety of metal oxides or nitride insulating materials [5]. Opting for distinct materials for each specific layer has facilitated the optimization of individual layer properties, thereby enhancing the cumulative performance of the device. However, the use of multiple materials in this approach presents certain challenges, including discrepancies at interfaces and an increase in the complexity of the manufacturing process [6; 7]. Despite these challenges, the implementation of such stratified structures has demonstrably optimized manufacturing workflows within the sector, encouraging broader acceptance of sophisticated memory technologies. On the other hand, the uniform arrangement of blocking, trapping, and tunneling layers in memory devices has historically been overlooked, mainly because it was believed that a uniform composition might not effectively promote charge trapping [8], which is crucial for the efficient functioning of memory devices. Contrary to this presumption [9], the present study introduces a novel memory device that leverages a uniform oxide stacking methodology, realized through the meticulous calibration of production parameters. Specifically, this device employs uniform HfZrO across the charge trap, blocking, and tunneling layers, facilitating the establishment of multilevel storage mechanisms within the device [10]. HfZrO is highly advantageous due to its deep trap energy levels, making it an excellent alternative to Si\({}_{3}\)N\({}_{4}\). It offers improved properties compared to traditional SiO\({}_{2}\) tunneling layers [11; 12] because of its energy band offsets and compatibility with low-temperature processing methods. The production of the blocking and tunneling layers is executed using high-temperature sputtering techniques, whereas the trapping layer is synthesized through a low-temperature procedure, ensuring the structural compatibility of the device with an extensive array of substrates [13; 14]. Our examination of program/erase (P/E) dynamics showcases a substantial memory window exceeding 4.3 V, delineating the states of full erasure and programming, indicative of the data storage capacity. Furthermore, the device exhibits remarkable data retention, preserving data integrity beyond 10\({}^{5}\) s, and displays durable endurance characteristics, indispensable for prolonged reliability. Additionally, operating within a low programming voltage threshold, with operational voltages remaining below 14 V, delineates this device as a power-efficient option for memory storage applications.