# Reducing LUT Count for FPGA-Based Mealy FSMs
## 6 Experimental Results
Let us point out that the model  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Benchmark** & **Auto** & **One-Hot** & **JEDI** & **DEMAIN** & **Our Approach** & **Category** \\ \hline bbara & 193.39 & 193.39 & 212.21 & 198.46 & 183.32 & 1 \\ bbsse & 157.06 & 169.12 & 182.34 & 178.91 & 159.24 & 1 \\ bbtas & 204.16 & 204.16 & 206.12 & 208.32 & 194.43 & 0 \\ beecount & 166.61 & 166.61 & 187.32 & 184.21 & 156.72 & 1 \\ cse & 146.43 & 163.64 & 178.12 & 174.19 & 153.24 & 1 \\ dk14 & 191.64 & 172.65 & 193.85 & 187.32 & 162.78 & 1 \\ dk15 & 192.53 & 185.36 & 194.87 & 188.54 & 175.42 & 1 \\ dk16 & 169.72 & 174.79 & 197.13 & 189.83 & 164.16 & 1 \\ dk17 & 199.28 & 167 & 199.39 & 172.19 & 147.22 & 0 \\ dk27 & 206.02 & 201.9 & 204.18 & 205.10 & 181.73 & 0 \\ dk512 & 196.27 & 196.27 & 199.75 & 197.49 & 175.63 & 0 \\ donfile & 184.03 & 184.00 & 203.65 & 194.83 & 174.28 & 1 \\ ex1 & 150.94 & 139.76 & 176.87 & 186.14 & 164.32 & 2 \\ ex2 & 198.57 & 198.57 & 200.14 & 199.75 & 188.95 & 1 \\ ex3 & 194.86 & 194.86 & 195.76 & 193.43 & 174.44 & 0 \\ ex4 & 180.96 & 177.71 & 192.83 & 178.14 & 168.39 & 1 \\ ex5 & 180.25 & 180.25 & 181.16 & 181.76 & 162.56 & 0 \\ ex6 & 169.57 & 163.80 & 176.59 & 174.12 & 156.42 & 1 \\ ex7 & 200.04 & 200.84 & 200.6 & 200.32 & 191.43 & 1 \\ keyb & 156.45 & 143.47 & 168.43 & 157.16 & 136.49 & 1 \\ kirkman & 141.38 & 154 & 156.68 & 143.76 & 155.36 & 2 \\ lion & 202.43 & 204 & 202.35 & 201.32 & 185.74 & 0 \\ lion9 & 205.3 & 185.22 & 206.38 & 205.86 & 167.28 & 0 \\ mark1 & 162.39 & 162.39 & 176.18 & 169.65 & 153.48 & 1 \\ mc & 196.66 & 195.47 & 196.87 & 192.53 & 178.02 & 0 \\ modulo12 & 207 & 207 & 207.13 & 207.37 & 189.7 & 0 \\ opus & 166.2 & 166.2 & 178.32 & 168.79 & 157.42 & 1 \\ planet & 132.71 & 132.71 & 187.14 & 185.73 & 174.68 & 2 \\ planet1 & 132.71 & 132.71 & 187.14 & 185.73 & 173.29 & 2 \\ pma & 146.18 & 146.18 & 169.83 & 153.57 & 156.12 & 2 \\ s1 & 146.41 & 135.85 & 157.16 & 149.17 & 145.32 & 2 \\ s1488 & 138.5 & 131.94 & 157.18 & 153.12 & 141.27 & 2 \\ s1494 & 149.39 & 145.75 & 164.34 & 159.42 & 155.63 & 2 \\ s1a & 153.37 & 176.4 & 169.17 & 158.12 & 166.36 & 2 \\ s208 & 174.34 & 176.46 & 178.76 & 172.87 & 166.42 & 2 \\ s27 & 198.73 & 191.5 & 199.13 & 198.43 & 185.15 & 1 \\ s386 & 168.15 & 173.46 & 179.15 & 169.21 & 164.65 & 1 \\ s420 & 173.88 & 176.46 & 177.25 & 172.87 & 186.35 & 4 \\ s510 & 177.65 & 177.65 & 198.32 & 183.18 &\(U_{1}\) is used for designs with Auto, One-hot, JEDI and DEMAIN. Furthermore, for better visualization, summary data are presented in the Figures 7-9. As follows from Table 5 and Figure 7, the \(U_{4}\)--based FSMs required fewer LUTs than it is for other investigated methods. There is the following economy: (1) 35.65% regarding Auto; (2) 59.27% regarding One-hot; (3) 12.04% regarding JEDI-based FSMs and (4) 21.20% regarding DEMAIN-based FSMs. The higher is the category, the greater is the gain in LUTs. For trivial and simple FSMs, the better results are produced by either JEDI or DEMAIN. The gain are becoming more and more noticeable, starting from the average FSMs. As follows from Table 6 and Figure 8, the \(U_{4}\)--based FSMs have a lower operating frequency than it is for other investigated methods. There is the following loss: (1) 2.65% regarding Auto; (2) 1.82% regarding One-hot; (3) 10.13% regarding JEDI-based FSMs and (4) 6.87% regarding DEMAIN-based FSMs. However, starting from big FSMs, the losses are getting smaller. It is connected with the fact that \(U_{4}\)--based FSMs always have three levels of logic and more regular system of interconnections. Figure 8: Experimental results (the operating frequency—total percentage). Figure 7: Experimental results (the number of LUTs—total percentage). The main goal of the proposed approach is to reduce the LUT count in circuits of FPGA-based Mealy FSMs. As follows from Table 5, the degree of reduction in the number of LUTs depends on the category of an FSM.