# Thermomechanical Stresses in Silicon Chips for
## 4 Discussion
\begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Temperature** & **Maximum** & **Minimum** & **Average** & **Maximum** & **Unit for Shift** \\
[\({}^{\circ}\)C] & **Value** & **Value** & **Value** & **Variation** & **and Stress** \\ \hline \multirow{3}{*}{\(-\)50} & 521.13 \(\pm\) 0.05 & 521.02 \(\pm\) 0.05 & 521.07 \(\pm\) 0.05 & 0.11 \(\pm\) 0.1 & [cm\({}^{-1}\)] \\  & 27 \(\pm\) 20 & \(-\)28 \(\pm\) 20 & \(\phantom{-}\)0 \(\pm\) 1 & 5 \(\pm\) 40 & [MPa] \\  & 518.84 \(\pm\) 0.05 & 518.63 \(\pm\) 0.05 & 518.77 \(\pm\) 0.05 & 0.21 \(\pm\) 0.1 & [cm\({}^{-1}\)] \\  & 71 \(\pm\) 20 & \(-\)36 \(\pm\) 20 & \(\phantom{-}\)0 \(\phantom{-}\)0 \(\pm\) 2 & 107 \(\pm\) 40 & [MPa] \\  & 515.49 \(\pm\) 0.02 & 515.26 \(\pm\) 0.02 & 515.36 \(\pm\) 0.02 & 0.23 \(\pm\) 0.04 & [cm\({}^{-1}\)] \\  & 52 \(\pm\) 20 & \(-\)63 \(\pm\) 20 & \(\phantom{-}\)0 \(\phantom{-}\)0 \(\pm\) 2 & 115 \(\pm\) 40 & [MPa] \\ \hline \hline \end{tabular}
\end{table} 
Table 4: Raman shift [cm\({}^{-1}\)] and stress values [MPa] obtained for the Si\({}_{\text{-}}\)Unmounted sample. \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Temperature** & **Maximum** & **Minimum** & **Average** & **Maximum** & **Unit for Shift** \\
[\({}^{\circ}\)C] & **Value** & **Value** & **Value** & **Variation** & **and Stress** \\ \hline \multirow{3}{*}{\(-\)50} & 521.13 \(\pm\) 0.05 & 521.02 \(\pm\) 0.05 & 521.07 \(\pm\) 0.05 & 0.11 \(\pm\) 0.1 & [cm\({}^{-1}\)] \\  & 27 \(\pm\) 20 & \(-\)28 \(\pm\) 20 & \(\phantom{-}\)0 \(\phantom{-}\)1 \(\phantom{-}\) & 5 \(\pm\) 40 & [MPa] \\  & 518.84 \(\pm\) 0.05 & 518.63 \(\pm\) 0.05 & 518.77 \(\pm\) 0.05 & 0.21 \(\pm\) 0.1 & [cm\({}^{-1}\)] \\  & 71 \(\pm\) 20 & \(-\)36 \(\pm\) 20 & \(\phantom{-}\)0 \(\phantom{-}\)0 \(\pm\) 2 & 107 \(\pm\) 40 & [MPa] \\  & 515.49 \(\pm\) 0.02 & 515.26 \(\pm\) 0.02 & 515.36 \(\pm\) 0.02 & 0.23 \(\pm\) 0.04 & [cm\({}^{-1}\)] \\  & 52 \(\pm\) 20 & \(-\)63 \(\pm\) 20 & \(\phantom{-}\)0 \(\phantom{-}\)0 \(\pm\) 2 & 115 \(\pm\) 40 & [MPa] \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Raman shift [cm\({}^{-1}\)] and stress values [MPa] obtained for the A\({}_{\text{-}}\)AuSn_p sample. of the same order of magnitude as the calculated errors. This fact agrees with expectations: since the unmounted samples are used as zero-stress reference materials, low-stress values around zero are expected. These values represent the starting point for calculating the stress of the other samples developed during the assembly steps. The A_AuSn_p sample (Table 5) shows higher stress variations on the whole surface at \(-50\)\({}^{\circ}\)C and at room temperature, while the A_AuSn sample (Table 6) shows the highest variations at all temperatures. In A_AuSn_p, the peak positions change slightly from point to point on the diagonal, giving asymmetric stress distributions and presenting a region of compressive stress on a side area of the chip. At room temperature, the highest variation in Raman shift on the entire surface is 0.30 cm\({}^{-1}\), which is only slightly higher than that of the unmounted sample. This value corresponds to a variation in stress of 171 MPa. The situation is different with sample A_AuSn: the Raman shift and stress variations over the surface at room temperature are higher than in the other cases: they reach values of 1.88 cm\({}^{-1}\) and 775 MPa, respectively. The stress distribution developed along a diagonal clearly shows the predominance of tensile stresses, higher (in absolute value) in the center of the chip. It increases (in absolute value) with decreasing temperature, particularly in the central area. The A_AuSn sample displays only tensile stresses (negative values); meanwhile, the A_AuSn_p shows compressive stresses (positive values) at 180 \({}^{\circ}\)C and tensile stresses at \(-50\)\({}^{\circ}\)C and at room temperature. Further measurements to check the interconnections have revealed that the assembling process was not sufficiently efficient under the pressure of 5 N, because the Si chip was not well soldered to the substrate.