## 3 Results and Discussion  
As presented in Section 1, the integration of a buried aluminum gate with an ALD Al\({}_{2}\)O\({}_{3}\) dielectric presents the challenge of etch compatibility when accessing the buried Al gate electrode. Although Al\({}_{2}\)O\({}_{3}\) can be etched in a fluorine-based chemistry, with very high selectivity to Al, this etch is slow and requires nonstandard lithography, such as the use of a hard mask or a thicker photoresist. A selective method to etch the Al\({}_{2}\)O\({}_{3}\) gate over the buried Al gate electrode using standard lithography has been developed and is shown in Figure 3. The proposed method includes a thin etch-stop TEOS layer between the Al and the Al\({}_{2}\)O\({}_{3}\). This TEOS layer is 45 nm thick and deposited after the Al gate has been patterned. After deposition, the TEOS is patterned and etched in a fluorine-based dry chemistry as to only remain over the gate electrode contact locations away from the active channel area of the GFET, as shown in Figure 1. A 15 nm Al\({}_{2}\)O\({}_{3}\) gate dielectric is then deposited via ALD and remains on the entire wafer. The graphene is then transferred and patterned, and the metal contacts are deposited and patterned, as described in Section 2. Finally, the contacts must also be patterned and etched to access the Al bottom gate. This is accomplished via a two-step etch process as shown in Figure 3a,b. The contact vias are patterned using conventional lithography with a 1 \(\upmu\)m AZ-MiR 701 positive photoresist. The Al\({}_{2}\)O\({}_{3}\) is then etched in the Plasmatherm ICP Etcher with 30 sccm of \(\mathrm{BCl_{3}}\) for 23 s under a chamber pressure of 4 mTorr and 500 W of ICP source along with a 50 W RF bias where the high-selectivity to TEOS makes this layer act as an etch stop, as shown in Figure 3a. This \(\mathrm{BCl_{3}}\) etch has an etch rate of 40 nm/min and allows the process to complete with the photoresist still remaining for the next step. The etch-stop TEOS layer is removed in the Trion Phantom III with 60 sccm of \(\mathrm{CF_{4}}\), 70 sccm of \(\mathrm{CHF_{3}}\), and 6 sccm of \(\mathrm{O_{2}}\) for 60 s under 130 mTorr chamber pressure and 200 W of RF power as shown in Figure 3b, thereby exposing the Al gate contact. Figure 2: Block diagram description of a double PMMA assisted transfer process of graphene. Moreover, the proposed process may also be applicable to other etch materials for similar device structures to this work. Other published studies have demonstrated the use of other high-k atomic layer deposited materials such as HfO\({}_{2}\) and TiO\({}_{2}\)[29; 60] for graphene or 2D material-based devices. While most high-k ALD dielectric materials can be etched with chlorine-based gas chemistries, the proposed etch process provides great value with minimum process optimization, and it can be easily adapted for a wide variety of device structures. A schematic top view of the tested GFETs is shown in Figure 4a indicating the gate length (L\({}_{\text{gate}}\)), width (W\({}_{\text{channel}}\)), and source/drain-to-gate gap (Gaps\({}_{\text{\text{\text{\text{\text{\text{\  
Figure 5 shows the SEM pictures and the related Raman spectra at different locations of three different devices on three separate die areas. These devices correspond to devices with low current (\(\sim\)200 uA, Dirac point at 6.2 V), identified as Device 1, (Figure 5a,b), medium current (\(\sim\)310 uA, Dirac point at 5.8 V), identified as Device 2 (Figure 5c,d), and high current (379 uA, Dirac point at 6.0 V), identified as Device 3 (Figure 5e,f), with current levels at a V\({}_{\text{GS}}=-10\) V and V\({}_{\text{DS}}=1\) V. The SEM of Device 1 in Figure 5a shows that the source and drain are connected with graphene, and approximately 50% of its width is missing. Device 2 and Device 3 illustrate a relatively continuous graphene connection in the SEM image across the channel when compared to Device 1.