# PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA
## 3 Proposed P4-Programmable Parser
### Software Overview
#### 3.1.2 P4 Compiled JSON File
The results are summarized in Table 2, showing the throughput improvements achieved by increasing the number of modified base blocks. Figure 6: Overlay Block. ### Pipeline Optimization

As seen in Section 3.3, the overlay design has limitations due to the complex critical path caused by the selection process for the output of each parallel search. This complexity limits the maximum frequency for larger bus sizes. We propose a pipeline approach suitable for larger bus sizes to achieve better throughput for large bus sizes. The longest path in our graph can be parsed in a maximum of two clock cycles with a bus size of 512 bits and one clock cycle with a bus size of 1024 bits. Consequently, there will be no need for memory to store packets. We propose a pipeline parser and a bus selector unit. The bus selector either parallelizes the 1024-bit input into sixteen chunks of 64-bit data or, in a more complex manner, forwards the eight chunks of 512-bit input into the correct half of the pipeline. The bus selector is a critical component in this design. It splits the 1024-bit input into sixteen parallel chunks of 64 bits each or divides the 512-bit input into eight parallel chunks, forwarding them into the correct half of the pipeline. This selective forwarding ensures that data is distributed evenly and processed efficiently across the pipeline stages. The pipeline's parser unit is a simplified base block version (Figure 7). Since the block is replicated along the pipeline, the first two multiplexers of the Prism Controller can be omitted. The clock controls these multiplexers, but in our pipeline approach, each stage is associated with a specific clock cycle. This simplification makes the base block even more streamlined, reducing the clock frequency. Since block \(i\) depends on \(i-1\), the bitmap of the latter is forwarded to the former, creating a streaming pipeline that accepts a packet per clock cycle. As explained in the previous section, the Prism Controller consists of three multiplexers, two of which are controlled by the clock number. If the same base block is put \begin{table}
\begin{tabular}{c c c c c c c} \hline  & \multicolumn{3}{c}{**Performance**} & \multicolumn{3}{c}{**Resources**} \\ \hline
**Data Bus** & **Parameter** & **Frequency** & **TP** & **Max Latency** & **LUTs** & **FFs** & **Total Logic** \\
**[bits]** & **x** & **[MHz]** & **[Gb/s]** & **[cycles]** & **LUTs** & **FFs** & **Logic** \\ \hline
64 & 1 & 237.69 & 15.20 & 9 & 1028 & 1873 & 2901 \\
128 & 2 & 193.38 & 24.80 & 5 & 3613 & 1938 & 5551 \\
192 & 3 & 165.00 & 31.71 & 4 & 6841 & 2012 & 8853 \\
256 & 4 & 145.51 & 37.20 & 3 & 8782 & 2066 & 10,848 \\
320 & 5 & 97.50 & 31.21 & 2 & 17,427 & 2147 & 19,574 \\
512 & 8 & 69.00 & 35.32 & 2 & 21,143 & 2311 & 23,454 \\
1024 & 16 & 62.90 & 64.42 & 1 & 21,492 & 2880 & 24,372 \\ \hline \end{tabular}
\end{table} 
Table 2: Results overlay block with different bus sizes. Figure 7: Parser Pipeline Block. in a pipeline fashion, these two multiplexers can be eliminated since each stage in the pipeline is dedicated to a particular clock number. The generated bitmap is forwarded for comparison to the next pipeline stage, simplifying the base block even further than the overlay design that includes only one multiplexer for control. This simplification also improves the performance frequency, enabling higher throughput for larger bus sizes. By unrolling the two multiplexers controlled by the clock, the pipeline design eliminates the need for complex control logic at each stage. Each pipeline stage processes its specific data portion in parallel, and the results are forwarded to the next stage in real-time. This design allows for continuous data flow and high throughput, removing the need for intermediate storage. The improved frequency and reduced complexity make this pipeline design suitable for handling larger bus sizes and achieving higher overall performance. The results are summarized in Table 3, showing the throughput improvements achieved by this approach. Adopting a pipeline design offers several advantages.