## 3 Proposed Method
### Failure Probability of the Matrix of Test Vectors  
The process of interconnect test of the integrated circuit system by boundary scan technique is injecting MTV (matrix of test vectors) and reading MRV (matrix of response vectors), by comparing the difference between them to carry out the fault diagnosis process. A schematic of the structure of the boundary scan test is shown in Figure 3. This architecture is proposed by IEEE1149.1 standard, which is based on JTAG (Joint Test Action Group) interface and BSC (Boundary Scan Cell) [32]. The TDI and TDO ports of the JTAG interface of the chip under test are connected in the form of daisy chain. During each test, the test vectors move into the boundary scan test unit through the TDI serial of each chip, motivating the corresponding pins. After the excitation, the response vectors are displaced from the TDO port of the chip. The whole testing process is controlled by TCK and TMS signals in the form of a bus. The elements of MTV are logical values of 0 or 1. The rows of the matrix which are called STV (Sequential Test Vector) represent the logical values that are applied to the same network in multiple boundary scan test cycles. The columns of the matrix which are called PTV (Parallel Test Vector) represent vectors composed of logical values that are loaded onto each network during a boundary scan test cycle. MTV is as follows. \[ \begin{array}{cccc}a_{11}&a_{12}&\cdots&a_{1m}\\ a_{21}&a_{22}&\cdots&a_{2m}\\ \vdots&\vdots&\ddots&\vdots\\ a_{n1}&a_{n2}&\cdots&a_{nm}\end{array}  \tag{11}\]  
The number of MTV's rows(\(n\)) is equal to the number of networks under test. The number of MTV's rows(\(m\)) is called compactness index, which needs to satisfy the following requirements. \[m\geq log_{2}(n+2) \tag{12}\]  
The rows of MRV are called SRV (Sequential Response Vector). Each SRV is a collection of logical values received on a network in the circuit under test. The columns of MRV are called PRV (Parallel Response Vector). Each SRV is a collection of logical values received from a network in one cycle of the boundary scan test. When short-circuit faults occur between networks, the SRVs received from the fault networks are presented as a result of wired-AND of STVs (wired-AND and wired-OR are dual models. There is only one situation in the same circuit, so this paper only discusses wired-AND here). By observing which networks SRV is the result of corresponding STVs wired-AND, testers can judge which networks have a short-circuit fault. Figure 3: The structure of the boundary scan test. On this basis, the definition of the short-circuit fault diagnosis through the SRV network with the phenomenon of misjudgment and confusion is as follows. Misjudgment: When an STV injected into one network is the same as the result of wired-AND of STVs injected into another group of networks. It is not possible to judge whether there is a short-circuit failure between this network and this set of networks. At this point, a misjudgment has occurred on the MTV. As an example, shown in Figure 4, the result of wired-AND of the STV injected into net1 and net2 is the same as the STV injected into net3, when a short-circuit fault occurs between net1 and net2, testers cannot determine whether net3 has a short-circuit fault with them (as shown by the red dotted line), so the misjudgment occurred. Confusion: When the result of wired-AND of a group STVs is the same as the result of wired-AND of another group STVs (There is no overlap between them). It is not possible to judge whether there is a short-circuit failure between these two groups of networks. At this point, a confusion has occurred on the MTV. As an example, shown in Figure 5, the result of wired-AND of the STV injected into net1, net2, and net4 is the same as the result of wired-AND of STV injected into net3 and net5, when a short-circuit fault occurs between net1, net2, and net4, and a short-circuit fault occurs between net3 and net5.