## 5 Findings and Analysis
### Implementation Insights and Results
A notable characteristic of the new architecture is its slightly increased delay when compared to various reference designs as illustrated in Figure 8. This increase in delay primarily results from a modest rise in latency and an elevated Critical Path Delay (CPD) within the new layout. The CPD defines the longest delay path in the multiplier circuit and is essential for overall performance as it directly influences the speed of operation execution. Nonetheless, it is crucial to highlight that despite this moderate increase in delay, the new architecture maintains a level of computational effectiveness that is comparable to existing options in terms of time complexity. This indicates that the design can still execute tasks efficiently even in light of the increased delay. Such efficiency renders the new architecture particularly suitable for a wide array of practical applications in real-time IoT scenarios that assist individuals with disabilities. In these vital contexts, achieving a balance among performance, resource efficiency, and design considerations is imperative for success.Thus, while the delay may be somewhat increased, the overall effectiveness and adaptability of this architecture position it as a strong candidate for tackling the security challenges in resource-constrained IoT edge nodes designed for individuals with disabilities. Its design specifically addresses the need for safe and reliable technological solutions that cater to the unique vulnerabilities of this community. The analysis presented in Table 3 and illustrated in Figures 9 and 10 indicates that the suggested hybrid systolic multiplier arrangement offers substantial benefits regarding the ADP and PDP. These two performance metrics are critical as they encapsulate the compromises among area, delay, and power consumption, which are essential considerations in modern circuit design. Remarkably, the new architecture achieves ADP reductions ranging from 99.5% to 99.9% when compared to existing designs, signifying a considerable enhancement in overall efficiency and improved resource utilization, thereby allowing for more compact circuit implementations. Moreover, the advancements noted in PDP are particularly noteworthy, with decreases ranging from 92.8% to 98.8%. Such results highlight the significant energy efficiency improvements of the proposed architecture, which can lead to lower operational costs and reduced heat generation during function. Consequently, this hybrid systolic multiplier emerges as an excellent option for deployment in limited-resource IoT applications tailored for individuals with disabilities, in which optimizing resource efficiency is crucial for ensuring functionality and accessibility in these vital technologies. The analysis indicates that the offered multiplier architecture successfully integrates substantial space and power savings while maintaining a delay that comparable to that of alternative designs, which is crucial for maintaining competitive performance. This equilibrium is vital for ensuring effective computation and quick response times in critical applications, where even minor delays can significantly impact functionality. Additionally, the design achieves significant reductions in both the ADP and PDP, which reflect enhanced overall performance and efficiency in practical scenarios. These improved metrics not only signify effective resource management but also highlight increased power efficiency, thereby reducing operational costs and minimizing heat generation. Consequently, this design is particularly well-suited for resource-constrained IoT devices specifically tailored for individuals with disabilities, where optimized performance and prolonged battery life are essential to meet their unique requirements and enhance their overall user experience. The constructed hybrid systolic multiplier presents a compelling solution for efficient cryptographic implementations in resource-constrained IoT devices, maximizing space and energy efficiency while delivering robust performance.