# Application of Surge Arrester in Limiting Voltage Stress at Direct Current Breaker
## 5 Experimental and Simulation Results
Figure 10: Simulated voltages and currents during fault disruption using the proposed hybrid DCCB with surge arrester (Figure 1b); (**a**) Voltages under 260 V supply, (**b**) Currents under 280 V supply; (**c**) Voltages under 500 V supply; (**d**) Currents under 500 V supply; Currents graphs are inverted for clarity. As shown in Figure 12, the surge-arrester voltage, initially at 14 kV, drops to 9.4 kV when the fault starts. When the downstream current reaches 20 kA, the trip signal is issued and SW2 followed by SW1 operations occur. At this time, due to the voltage rise in the capacitors and the conduction of the redirecting diodes, the surge-arrester voltage reaches its blocking voltage of 15 kV and upstream current flows into the surge arrester, leading the surge-arrester voltage to rise to 18 kV based on its characteristic curve. This, in turn, harnesses the capacitor (switch) voltages (at 23.2 kV). A low-cost breaker downstream isolates the downstream circuit upon reaching the downstream current zero-crossing. The downstream current zero-crossing is reached in 3 ms. In contrast, in the absence of the surge arrester, the upstream current is forced to move downstream, excessively charge the bypassing capacitors, and cause a high overvoltage (52.8 kV). The high C1 voltage turns on D2 and pushes a reverse upstream current back into  
Figure 11: Case 5: Distribution line. Figure 12: Simulation results for the breaker at one-third of the line, with the fault at the end of the line: (**a**) Voltages (**b**) 421 currents. the source through the upstream inductance (29 kA peak reverse current). This potentially damaging current passes through the upstream inductance, C1, D2, and the source. Thus, an oscillatory behavior of upstream current is possible but can be prevented by using an additional (low-cost) breaker at the upstream branch. Nonetheless, the peak voltage at the DCCB input terminals reaches a very high voltage (53.8 kV). When the breaker is placed at two-third of the distance from the source with the fault location at the end of the line, the proposed breaker has a larger value of upstream impedance (2.22 mH and 22 m\(\Omega\)). Figure 13 compares the current and voltage waveforms with and without the surge arrester in this case. The capacitor (switch) voltages are clamped at 22.8 kV under the surge-arrester 18 kV blocking voltage. The downstream current zero-crossing is reached in 1.7 ms. Note that, in this case, the upstream current takes a longer time to decay. In contrast, the absence of the surge arrester causes a high overvoltage of 76 kV and an upstream peak reverse current of 22 kA. The surge arrester's ability to consistently regulate voltage under different fault conditions, as demonstrated in this case, is essential for maintaining the overall performance of the proposed circuit breaker. This is especially crucial in scenarios with longer power lines or inductive loads where voltage spikes can be particularly harmful. Overall, the hardware and simulation results illustrate the effectiveness of the modified hybrid DC breaker equipped with a surge arrester. The simple structure of the proposed DC breaker, where no bulky inductors are utilized in the DCCB, makes it an effective protective device in low- and medium-voltage DC circuits. Figure 13: Simulation results for breaker at two-thirds of the line, with the fault at the end of the line: (**a**) Voltages (**b**) currents.