## 4 Results  
To determine the optimal operating conditions for the 4-bit parity generator and checker to achieve acceptable performance, we have utilized the QF metric. Figure 4 illustrates the simulation results for both even and odd parity generation employing CR-SOAs-MZIs at a data rate of 120 Gb/s with RZ data pulses. These findings are in accordance with the truth table displayed on the left-hand side of Figure 3, confirming the accurate generation of the 4-bit parity sequence by the proposed scheme. The obtained QFs for the even and odd parity generators are 32.72 and 12.35, respectively. Figure 4: 4-bit parity generation using CR-SOAs-MZIs at 120 Gb/s. (**a**) Data A, (**b**) data B, (**c**) data C, (**d**) data D, (**e**) even parity generation (Pe), (**f**) Pe eye diagram with QF = 32.72, (**g**) odd parity generation (Po), and (**h**) Po eye diagram with QF = 12.35. Figure 5 depicts the results, labeled as Ce and Co, obtained from even and odd parity checking utilizing CR-SOAs-MZIs with 120 Gb/s RZ data pulses. In case of errors in the received data identified by the parity checker, the check bit output is set to '1' to signify incorrect data reception. Conversely, if the received data is accurate, the output of the parity checkers should be '0'. The QF values for the even and odd parity checkers are recorded as 35.13 and 15.76, respectively. In summary, the parity processor demonstrates effective execution of its intended operations on 4-bit binary words with both logical correctness and satisfactory quality when employing CR-SOAs at 120 Gb/s. The experimental setup and results for parity generation/checking utilizing conventional SOAs with 10 Gb/s RZ data pulses are detailed in [3]. In the context of CR-SOAs, the transition duration from the carrier reservoir (CR) to the active region (AR), denoted by \(\tau_{\text{t}}\), holds significant importance. Thus, it is essential to explore its impact on the performance of the all-optical parity process, as demonstrated in Figure 6 for both 4-bit even (Pe) and odd (Po) parity generations. A shorter \(\tau_{\text{t}}\) signifies a faster recovery of the device following excitation. This swift recovery empowers the CR-SOA to promptly respond to incoming signals, thereby enhancing signal processing efficiency. Consequently, CR-SOAs with a shorter \(\tau_{\text{t}}\) achieve a higher QF, indicative of superior signal quality. Figure 5: 4-bit parity checking using CR-SOAs-MZIs at 120 Gb/s. (**a**) even parity checking (Ce), (**b**) Ce eye diagram with QF = 35.13, (**c**) odd parity checking (Co), and (**d**) Co eye diagram with QF = 15.76. Figure 7 provides insights into the relationship between the injection bias current (I) and the QF for 4-bit parity generation utilizing CR-SOA-based MZIs operating at 120 Gb/s. As this parameter is increased, more carriers are injected into the CR layer, expediting the recovery process and replenishment of the AR layer following depletion by input pulses. Consequently, the observed increase in the QF suggests enhanced signal quality with higher I. By optimizing the injection bias current, researchers can improve the efficiency and accuracy of logic operations performed using CR-SOA-based MZIs. However, the analysis is limited to a maximum of 500 mA. The primary reason for this limitation is the practical constraints and trade-offs associated with higher injection currents. Increasing the injection bias current beyond 500 mA introduces significant thermal effects that can negatively impact the performance and reliability of the CR-SOAs. Higher currents lead to increased heat generation, which can cause thermal saturation, adversely affecting the gain dynamics and carrier lifetime within the SOAs. Additionally, excessive injection currents can accelerate device degradation, reducing the operational lifespan of the amplifier [25]. Therefore, 500 mA represents a balance between achieving improved QF and maintaining the thermal stability and longevity of the device.