## 7 Conclusions  
Depth estimation algorithms are used in various fields, such as in research and automation. This paper proposes a plenoptic based approach which works on a single recording of a raw image from the light-field camera. From the timing point of view, high computation tasks and large resulting execution time are the biggest challenges of such algorithms. The existing solution is to use a GPU based system with high computation power to comply with the computation requirements. However, this solution is expensive from power consumption perspective and therefore cannot be used in power limited applications, such as a mobile application. This paper proposes a modified single recording plenoptic camera based depth estimation algorithm. Moreover, it presents a FPGA based hardware design in order to optimize the performance of the algorithm by employing inherited parallelization. FPGA based hardware exploits both temporal and spatial parallelization in the targeted algorithm. The performance bottleneck is mainly caused by the presence of recursive operations and large memory access time. Optimization of memory accesses and managing the resources is a complex and an iterative process. The presented hardware design is realized and compared with the low-power mobile GPU solution. The results have shown a considerable improvement in the performance with respect to execution time. It leads to the conclusion that the presented FPGA hardware design is faster and consumes less power as compare to both PC-system and mobile GPU based solutions.  
Conceptualization, F.B. and T.G.; methodology, F.B. and T.G.; software, F.B.; validation, F.B.; formal analysis, F.B. and T.G.; investigation, F.B.; resources, F.B.; data curation, F.B.; writing--original draft preparation, F.B.; writing--review and editing, F.B. and T.G.; visualization, F.B. and T.G.; supervision, T.G.; project administration, T.G.; funding acquisition, T.G. All authors have read and agreed to the published version of the manuscript.  
This work is financed by the Baden-Wurttemberg Stiftung gGmbH, Germany.  
Not applicable.  
The authors declare no conflict of interest.  
The following abbreviations are used in this manuscript:  
\begin{tabular}{l l l l} ACP & \multicolumn{1}{c}{Accelerator Coherency Port} \\ APU & \multicolumn{1}{c}{Application Processor Unit} \\ ASIC & \multicolumn{1}{c}{Application-specific Integrated Circuit} \\ BPR & \multicolumn{1}{c}{Percentage of Bad Pixels} \\ BRAM & \multicolumn{1}{c}{Block RAM} \\ CPU & \multicolumn{1}{c}{Central Processing Unit} \\ CT & \multicolumn{1}{c}{Census Transform} \\ DOF & \multicolumn{1}{c}{Depth of Field} \\ FF & \multicolumn{1}{c}{Flip-flop} \\ GPU & \multicolumn{1}{c}{Graphics Processing Unit} \\ \end{tabular}  
\begin{table}
\begin{tabular}{l c c c c} \hline \hline  & **Exec. Time per** & **Throughput in** & \multicolumn{1}{c}{**Power in W**} & \multicolumn{1}{c}{**Performance in**} \\  & **Frame** & **fps** & **fps/W** \\ \hline PC-System & 88 ms & 11 & 85.1 & 0.13 \\ Mobile GPU & 34 ms & 29 & 13.4 & 2.19 \\ FPGA MPSoC & 27 ms & 37 & 7.1 & 5.21 \\ \hline \hline \end{tabular}
\end{table}
Table 5: PC-system, mobile GPU and FPGA comparison.