# Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks
## 5 Comparative Analysis
### Gate-Level Hiding  
To better analyze the values presented in Table 1, they are depicted in Figures 14 and 15, showing the area vs. delay and the area-delay product (ADP) vs. security metrics. To clarify the clustered values, zoom-in view is also shown. \begin{table}
\begin{tabular}{c c c c c c c c} \hline \hline
**Logic Style** & **Data Reference** & **Based on** & **Area** & **Frequency** & **Power** & **Security** & **Special P\&R** \\ \hline CMOS & NA\({}^{1}\) & STD & 1 & 1 & 1 & 1 & NO \\ \hline DRSL [78] & [78; 79] & FC/STD\({}^{2}\) & 2-7.5 & 0.50 & \(>\)CMOS & \(>\)MDPL \({}^{3}\) & NO \\ \hline iMDPL [76] & [80] & STD & 18–19 & 0.2–0.3 & \(>\)MDPL & 90–120 & NO \\ \hline MASKED-AND [71] & [10] & STD & 3.86 & 0.56 & NA & \(>\)CMOS \({}^{4}\) & NO \\ \hline Masked-SABL [81] & [81] & FC & 1.19 \(\times\) SABL & 0.88 \(\times\) SABL & \(=\)SABL & 3 \(\times\) SABL & YES \\ \hline MDPL [11] & [11;76; 83] & STD & 4–5 & 0.5–0.6 & 17.43 & 1.69 & NO \\ \hline RSL [10] & [10] & FC/STD\({}^{2}\) & 2.02 & 0.68 & NA & \(>\)MASKED-AND \({}^{4}\) & NO \\ \hline \hline \end{tabular}  
* NA = not available. \({}^{2}\) Full-custom (FC) for RSL and based on standard gates (STD) in FPGA implementations RSLUT. \({}^{3}\) CMOS \(<\) MDPL \(<\) WDDL \(<\) DRSL. \({}^{4}\) CMOS \(<\) MASKED-AND \(<\) WDDL \(<\) RSL.  
\end{table} 
Table 2: Gate-level masking performance and security normalized values with respect to CMOS logic style. Figure 14: Area vs. delay of gate-level hiding countermeasures. Figure 15: ADP vs. security of gate-level hiding countermeasures. From Figure 14, it can be clearly seen that the 26 most cost-effective proposals are located in the bottom left corner. The potential selection for low area and with a low performance impact should be kept within these zoomed squares. These values show that all the hiding techniques require extra hardware compared to CMOS, with GliFred and GliFred-P being the fastest ones. It can also be seen that CML-based and SABL-based solutions have a linear growth between area and speed, with TSPL being the one with the best area-performance ratio. As seen below, this solution also presents an interesting security level. Regarding the security level, Figure 15 depicts the distribution of these solutions according to their security levels _vs_ ADP values, with the upper-left corner ones suggesting the best security cost trade-off. It is clear that the lack of quantified values for the security level does not facilitate a fair comparison. Often the only information provided by the authors is \"this proposal is more secure than that proposal\". To fairly assess each solution in terms of their relative security, the following relation was used, based on the comparisons presented on each state-of-the-art paper:  
* In [36], DyCML \(<\) SABL \(<\) 3 sDDL. * In [31], WDDL \(<\) DPL_noEE \(<\) AWDDL. * In [14], CRSABL \(<\) SABL. * In [46], DyCML \(<\) DDCVSL \(<\) LSCML. * In [39], DyCML \(<\) SABL \(<\) DDPL. * In [47], DyCML \(<\) IFLSCML \(<\) LSCML \(<\) DDSLL. * In [9], DDCVSL \(<\) DyCML \(<\) SABL. * In [51], DPL_noEE \(<\) BCDL \(<\) AWDDL. * In [38], WDDL \(<\) TSPL \(<\) TDPL. Notice that in [9] and [46], the DyCML and DDCVSL proposals have contradictory results, but it is important to notice that both have security levels within the same order of magnitude. The zoomed areas contain specific values for the security level in terms of order of magnitude above CMOS. These specific solutions can be considered acceptable. The best security results are clearly achieved by the SecLib and DDPL solutions. However, these require further validation, other than their authors. While SecLib presents a partially higher security level, it does so with a significantly higher area-performance cost. With identical results between each other, BCDL, SDMLp, TSPL, HDRL, and SABL show consistent security-performance figures. Combining all the figures, BCDL, SDMLp, TSPL, HDRL, and SABL are the most promising proposals, but it should be kept in mind that all of them have inherent difficulties.