## 1 Introduction  
The automotive industry's requirements are becoming increasingly complex and sophisticated with the development of novel security systems, comfort features, and new designs. To deal with these requirements, more data processing capacity is needed to support technologies like Autonomous Driving and Assistance Systems (ADAS) [1], as well as safety-critical systems that are part of safer vehicles. Electronic Control Units (ECUs), complex networks of computers and processing units, are found in most vehicles and exchange information continuously. These units have become increasingly complex in both hardware and software, with Volvo cars requiring around 100 million lines of code derived from approximately 100,000 functional requirements [2]. Automotive manufacturers have started utilizing off-the-shelf multicore microcontrollers, commonly referred to as Multiprocessor System-on-a-Chip (MPSoC), in ECUs to keep up with this trend. These controllers implement new functions, parallel processing, and increased performance, making it easier to implement safety requirements such as those from ISO 26262 [3]. Despite these advancements, significant challenges remain in efficiently managing inter-core communication and maintaining the predictability of data flow in multicore systems. Traditional software designed for single-core systems incorporates communication methods to exchange data between tasks in preemptive and non-preemptive setups. However, when there are multiple cores in a microcontroller, different parts of the software need to be distributed and executed by parallel cores [4]. This situation presents new challenges for event chains, as tasks can be distributed across different cores, making it difficult to maintain the predictability of data flow without implementing contention mechanisms. Several studies have proposed solutions for inter-core communication in embedded systems, yet many solutions are tailored to specific industries like avionics and automotive applications, where time is of the essence, particularly in safety-related use cases. According to these needs, it is hypothesized that the development of a communication model between cores, along with a synchronization mechanism in heterogeneous systems, will contribute to reducing latency caused by the overlap of operations. This paper proposes a solution that merges the predictability of LET, applied to inter-task communication, with the composability of time-controlled buffers using a TDMA scheme for inter-core communication. This approach ensures consistent latency and temporal determinism in core-to-core communication [5]. The benefit of this approach is that it reduces the need to bind applications to specific cores, facilitating the creation of less dependent event chains. Moreover, by setting temporal intervals for data transfer between cores, deterministic data flows can be modeled. This methodology's portability is crucial, as it is not tied to specific hardware implementations, allowing its use across various platforms. However, scheduling mechanisms and peripheral resources, such as DMA, are outside the scope of this work and represent areas of interest for future research. The main contributions of this work are as follows:  
* We propose a solution that merges the predictability of Logical Execution Time (LET) applied to inter-task communication with the composability of time-controlled buffers. * We utilize a TDMA scheme for inter-core communication to ensure consistent latency and temporal determinism in core-to-core communication. * Our proposal reduces the need to bind applications to specific cores, facilitating the creation of less dependent event chains. This work is structured as follows. Section 2 presents the related works. Section 3 presents the communication strategies in multicore systems, beginning with a discussion on explicit communication and its problems, such as variable latency and lack of determinism.