# An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder
## 1 Introduction  
[PERSON] first introduced the Low-Density Parity-Check (LDPC) codes as a family of linear Forward Error Correction (FEC) codes in his doctoral thesis in 1962 [1]. LDPC codes were known as near-Shannon limits error correction codes in practice [2]. Since their rediscovery in the middle of the 1990s [3], they have received much attention in both academia and industry. LDPC codes have a lot of advantages such as excellent coding gain, very low error floor, inherently parallelizable decoding schemes, and various optimum decoding architectures. Several industry standards, including WLAN (802.11 ay) [4], WiMAX (802.16e) [5], WiFi 6 [6], DVB-S2 [7], and 10 GbaseT (802.3 an) [8] systems, have actually adopted them. Moreover, they have been selected for the enhanced Mobile Broadband (eMBB) in the 5 th generation (5G) mobile communications by 3 GPP (3 rd Generation Partnership Project) [9; 10]. LDPC codes have a variety of desirable characteristics that make them particularly appealing for implementation. The LDPC decoding algorithm may be performed using low-complexity computations, resulting in comparatively acceptable processing hardware design and implementation costs. LDPC codes can be effectively decoded with the iterative Message-Passing (MP) algorithm. This decoding technique is the standard Belief-Propagation (BP) algorithm [11], which is also called the Sum-Product (SP) [12]. Although the BP algorithm provides excellent decoding performance, its implementation complexity is very high. Therefore, the Min-Sum (MS) algorithm [13] was proposed to reduce the processing of exchanged messages by applying computational approximations. The computations of the MS algorithm required only addition and comparison operations. The MS algorithm carried out the low-cost hardware implementation at the cost of significant error correction performancedegradation. In an effort to improve this performance loss, numerous approaches have been presented in the state-of-the-art, including some well-known algorithms such as the Offset Min-Sum (OMS) and the Normalized Min-Sum (NMS) [14; 15]. Moreover, several enhancements have been further proposed in the literature, such as the Improved Offset Min-Sum (IOMS) algorithm [16], the Second Minimum Approximation Min-Sum algorithm (SMA-MSA) [17], the Simplified 2-Dimensional Scaled (S2 DS) algorithm [18], the Hybrid Offset Min-Sum (HOMS), and the Variable Offset Min-Sum (VOMS) algorithms [19]. Although the design of individual processing units is relatively basic, the design of a whole LDPC decoder is influenced by a complicated interaction between a number of system properties. These include processing delay, decoding performance, processing throughput, bandwidth efficiency, power consumption, and flexibility. In the case of an area-efficient decoder design, one of the main difficulties is an increase in decoding algorithm complexity, which results in more hardware and memory resource consumption. Many designs have been proposed in recent years to reduce hardware resources. For instance, the authors in [20] proposed a layered decoder architecture that included several single-port memory bank structures. Once a pipeline conflict occurs, the A-Posteriori (AP) update is postponed. The conflicted check node messages contribute to the AP only when a new non-conflicted update happens. In the case that the base graph matrix is dense, which means that it has a high percentage of non-negative values relative to the total number of entries, this postponement of the AP updates might dramatically lower the performance of the layered scheduling. The authors in [21] proposed an LDPC decoder architecture without any stall cycles caused by memory access pipeline conflicts or check node degree change. The design was performed as a hybrid decoding schedule. This means it generally operates as layered scheduling and only shifts to flooded scheduling when a pipeline conflict occurs. The resulting LDPC decoder obtains better hardware efficiency.