# FPGA-Based Manchester Decoder for IEEE 802.15.7 Visible Light Communications
## 5 Experiments and Results  
### Resources and Timings  
The algorithm described so far was coded in VHDL [41] and implemented in a VLC research system realized in-house [30]. The system includes a 10M50 DAF486C6 FPGA from Intel (Santa Clara, CA, USA) together with all the electronics for transmitting and receiving VLC data. The system is managed through a MATLAB(r) user interface that runs on a host PC. A framework present in the FPGA supports the user in the implementation of new applications, like the one here proposed. More details about the VLC system and its use can be found in [30; 42].  
The resources employed by the proposed decoder once integrated in the FPGA are listed in Table 7. The receiver requires about 7% of Advanced Logic Modules (ALMs), 3.5% of the Digital Signal Processors (DSPs) and 1.3% of the memory available in the target FPGA. The logic that requires most of the resources is the NIOSII soft processor. However, it should be noted that the processor can be used for other tasks as well.  
The receiver was compiled with a target clock of 100 MHz, and the compilation software confirmed the timing closure with a large margin.  
Before proceeding to the field experiments, we checked with the on-board emulator that the timings of the system tasks were consistent. Every bit in air lasts for \(T_{b}\), which corresponds to 1000 clock cycles when the clock is 100 MHz. Thus, every bit must be processed in 1000 clock cycles at most on average. Thanks to the 5-bit capacity of the input circular buffer, a few bits every now and again can take more time, as long as the 1000 cycles limit is maintained on average.  
\begin{table}
\begin{tabular}{c c c c} \hline
**Entity** & **ALM** & **DSP (18 \(\times\) 18)** & **Memory (bit)** \\ \hline Circular Buffer & 143 & 0 & 8192 \\ I/Q Demodulator & 172 & 2 & 3072 \\ Phase Calc. & 686 & 0 & 0 \\ NIOSII Processor & 2133 & 3 & 10,762 \\ Interconnect & 321 & 0 & 0 \\ \hline TOT & 3455 & 5 & 22,026 \\ \hline \end{tabular}
\end{table}
Table 7: FPGA resources required by receiver.  
Figure 12: Comparison of BERs measured by a receiver working with ideal mathematic (IM, dashed curves) and real mathematic (RM, continuous curves). Tests are performed with SNR from 0 to \(-25\) dB and \(Z_{\%}\) of 6%, 10%, and 20%.  
Figure 13 shows the timing of the processing, checked in the FPGA working in real time. As long as a bit is present in the circular buffer, the NIOSII commands the start of the I/Q demodulation, which terminates in 100 clock cycles: a cycle per sample. At this time, I and Q are present in the accumulators and ready for the phase calculation, which occurs in 20 cycles. The NIOSII gets the phase, makes the decision on the bit, and calculates the phase correction for reading the next bit. This info is set in the circular buffer that in the meantime continued to store input samples. Now the NIOSII waits for the next 100 samples from the new offset to be ready in the buffer, and the processing starts again. On average the processor has about 650 cycles free every 1000, that can be used for managing the data packaging, searching for the data preambles, CRC checking, etc. The \(\upmu\)C is apparently unloaded; however, its calculation power would never be enough to support the calculation of the phase in real time, which, for this reason, is performed by the specialized hardware described in the previous parts of this work.  
Finally, we note that the latency of the processing is very low, less than \(T_{b}\).