# A Survey of Analog-to-Digital Converters for Operation under Radiation Environments
## 4 Data Analysis
### Technologies  
Bipolar, CB (complementary-bipolar), LC\({}^{2}\)MOS (linear compatible CMOS), BiCMOS (bipolar-CMOS) and pure CMOS processes [75; 76; 77] are found among the _selection_ (cf. column 'Tech.' in Table 1). Particularly, MOS processes have characteristic lengths of 0.35 \(\upmu\)m, 250 nm, 180 nm, 130 nm, 90 nm, 65 nm and 32 nm, being 0.35 \(\upmu\)m and 180 nm the two more recurrent (with at least ten and eleven specimens, respectively). Both 0.35 \(\upmu\)m and 180 nm MOS nodes are usually accompanied with other process options--BJTs (bipolar juntion transistors), additional thicker gate oxide, etc.--that allow to integrate in a monolithic solution a wide voltage range analog front-end together with the ADC.  
The organization contributing the most to the _selection_ is Texas Instruments (with 22 specimens). BiCom3 and CMOS9 are its most recurrent technologies within the _selection_ (with at least six and seven specimens, respectively); both are briefly described below.  
BiCom3 is a CB SiGe BiCMOS triple-metal technology on SOI [78]. It includes 5V NPN and PNP SiGe BJTs and isolated 3.3 V 0.35 \(\upmu\)m CMOS devices. It offers several process options for faster BJTs (3X and 3Y options for 25 and 33 GHz, respectively), for high voltage applications (3 XHV option, up to 36 V) and without SOI (3 XL bulk option); however, only BiCom3 (basic) and BiCom3X options can be found within the _selection_. The technology can be considered latch-up free and ELDRS immune (enhanced low dose rate sensitivity), and has been tested up to 150 krad(Si) of TID (ADS5424-SP) and up to \(6.08\times 10^{11}\) neutrons/cm\({}^{2}\) of DDD (DD dose) (ADS5400-SP).  
CMOS9 is a DGO (dual gate oxide) CMOS process using STI (shallow trench isolation) for inter-device isolation [23]. It provides 1.8 V and 3.3 V CMOS devices with, respectively, 180 nm and <400 nm minimum gate lengths, and 5 nm and <10 nm gate oxide thicknesses. The process is originally from National Semiconductor, derived from the TSMC's 180 nm process (Taiwan Semiconductor Manufacturing Company). The technology can be considered ELDRS immune and has been tested up to 300 krad(Si) at LDR and HDR of TID (ADC08D1000).  
Special mention is deserved by the 32 nm CMOS SOI technology by IBM used to implement the best \(\text{FOM}_{TID}\) and \(\text{FOM}_{SET}\) specimen: the Boeing-1 pipelined ADC [50]. Combined with on-chip calibration, the technology has shown practically no variation up to 1 Mrad(Si) of TID for this application. In addition to analog-to-digital conversion, the technology was also proven suitable for other high-speed applications (such as SerDes, PLL and DRAM) in heavy-ions environments.  
Radiation hardening in ADC applications can be achieved with multiple technologies; several options are combined to achieve a versatile and power efficient design. RHBD (radiation hardening by design) techniques at physical level (additional contact rings, smart device distribution, etc.) and certain technology options (buried layers, trenches, etc.) are used to enhance radiation performance. The smallest MOS node (32 nm) used up to now for radenv-ADCs seems, not only the most suitable for a SoC solution, but also the most power + radiation efficient when combined with calibration; however, greater nodes (0.35 \(\upmu\)m and 180 nm, including other technology options) offer the possibility to integrate a wide voltage range analog front-end without neglecting the power + radiation efficiency. In any case, we shall remark that the SOI feature is always present in the best performing specimens of the _selection_.