## 6 Results and Comparison
### Throughput Results  
The throughput of the proposed architectures is recorded for various system configurations. Table 3 presents the measured throughput for 2 \(\times\) 2 and 4 \(\times\) 4 MIMO considering block and fast fading channels at the maximum operating clock frequency. For FPGA implementation, in the case of block channel fading, 115.8 mega symbolsper second for 2 \(\times\) 2 MIMO and 62.4 mega symbols per second for 4 \(\times\) 4 MIMO throughputs are achieved for the FPGA implementation at an operating frequency of 202.67 MHz. In the case of fast fading, the throughput is reduced. At the same operating frequency, throughputs of 6.4 mega symbols per second and 4.7 mega symbols per second are achieved for 2 \(\times\) 2 and 4 \(\times\) 4 MIMO, respectively.  
Furthermore, Table 3 shows the throughput of the ASIC implementation of the designed NASC-based equalizer architecture. Using the ST 65-nm CMOS technology, with the CORE65 GPHVTlibrary at the nominal case operating conditions (1 V; 25 \({}^{\circ}\)C), the architecture can achieve a maximum throughput of 302.3 mega symbols per second in the case of MIMO 2 \(\times\) 2 transmission over the block fading channel. Note that higher throughput can be achieved by using newer technologies, such as 28-nm technology and beyond. In fact, the throughput in bits per second depends on the adopted constellation. For the 16-QAM and 64-QAM modulation schemes, the designed NASC-based processor dedicated for MIMO equalization can achieve 1.2 giga bits per second and 1.8 giga bits per second, respectively. Recall that the most recent LTE-Advanced standard [4] imposes a throughput of 1 giga bit per second for the down-link and 500 mega bits per second for the up-link. Hence, for the current achieved throughput, the receiver implementing the designed application-specific processor can satisfy the requirements of throughput imposed by the LTE-Advanced standard for both constellations in the down-link and up-link.  
\begin{table}
\begin{tabular}{l c c} \hline \hline
**Logic Utilization and Timing** & **Equalizer** & **Demapper** \\ \hline
**Operating conditions** & nominal case (1 V; 25 \({}^{\circ}\)C) \\ \hline
**Area** & 0.126 mm\({}^{2}\) & 0.048 mm\({}^{2}\) \\ \hline
**Maximum operating frequency** & 529 MHz & 520 MHz \\ \hline \hline \end{tabular}
\end{table}
Table 2: Application-specific integrated circuit (ASIC) synthesis results of the proposed NASC-based equalizer and demapper architectures targeting 65-nm STCMOS technology.  
\begin{table}
\begin{tabular}{c c c c} \hline \hline \multirow{2}{*}{**Implementation**} & \multirow{2}{*}{**Fading Type**} & \multicolumn{2}{c}{**Throughput (Mega Symbols per Second)**} \\ \cline{3-4}  & & \(\mathbf{2\times 2\) MIMO SM} & \(\mathbf{4\times 4\) MIMO SM} \\ \hline \multirow{2}{*}{FPGA @202.67 MHz} & Block fading & 115.8 & 62.4 \\ \cline{2-4}  & Fast fading & 6.4 & 4.7 \\ \hline \multirow{2}{*}{ASIC @ 529 MHz} & Block fading & 302.3 & 162.8 \\ \cline{2-4}  & Fast fading & 16.8 & 12.2 \\ \hline \hline \end{tabular}
\end{table}
Table 3: Throughput of the proposed NASC-based equalizer architecture. SM, spatially-multiplexed.  
On the other hand, Table 4 summarizes the achieved throughput of the proposed demapper design for different modulation schemes. For the FPGA implementation, the demapper architecture enables a maximum throughput of 234.6 mega LLRs per second adopting the 16-QAM modulation scheme when operating at a clock frequency of 293.242 MHz. In addition, Table 4 shows the throughput of the ASIC implementation of the designed NISTC-based demapper architecture. Using the ST 65-nm CMOS technology, with the CORE65 GPHVT library at nominal case operating conditions (1 V; 25 \({}^{\circ}\)C), the architecture can achieve a maximum throughput of 416 mega LLRs per second in the case of the 16-QAM modulation and 347 mega LLRs per second in the case of the 64-QAM modulation.