## 4 Experimental Verification
### Testing Results and Analysis
Figure 18: Experimental curves using different \(i_{\text{satur}}\) in series applications: (**a**) voltage when \(i_{\text{satur}}\) is 33 A, (**b**) voltage when \(i_{\text{satur}}\) is 24 A, (**c**) currents when \(i_{\text{satur}}\) is 33 A, (**d**) currents when \(i_{\text{satur}}\) is 24 A, (**e**) SoC when \(i_{\text{satur}}\) is 33 A, and (**f**) SoC when \(i_{\text{satur}}\) is 24 A. Moreover, the slave ESU#2 suddenly stopped working on validating the feasibility of the proposed strategy when the number of slave units was reduced. Figure 20 depicts the entire process when the duty cycle of PCU#2 is disabled in series and parallel applications. Then, \(SoC_{1}\) and \(SoC_{3}\) could still be allowed to move towards each other by setting the corresponding variables of \(SoC_{2}\) in the communication network as zero. Finally, equal SoC levels and balanced currents were still achieved between the remaining ESUs. The \(SoC_{2}\) linearly decreases in series applications because the load current flows through ESU#2. However, \(SoC_{2}\) remains unchanged in parallel applications because \(D_{2}\) is turned off as a result of inverse voltage. After this point, \(i_{2}\) becomes zero. The experimental results almost agree with the theoretical analysis, which proves the effectiveness of the proposed strategy. Figure 19: Experimental curves using different saturation styles in series applications: (**a**) currents under load change with fixed saturation, (**b**) currents under load change with variable saturation, (**c**) SoC under load change with fixed saturation, and (**d**) SoC under load change with variable saturation. Figure 20: Experimental curves when ESU#2 has ceased functioning: (**a**) currents in parallel applications, (**b**) currents in series applications, (**c**) SoC in parallel applications, and (**d**) SoC in series applications. Another two old batteries were used to carry out balancing control for the degradation condition. With the help of a battery tester, the actual levels of capacity reduction were obtained by measuring the internal resistance. The experimental waveforms of battery degradation are given in Figure 21. After the SoC levels had balanced, three currents were gradually increased to keep \(u_{\text{dc}}\) stable because the battery voltages decreased as a result of SoC decline. At the same time, it was satisfied that \(i_{1}/Q_{1}\approx i_{2}/Q_{2}\approx i_{3}/Q_{3}\) after SoC errors were removed under the two kinds of applications. In other words, the ratio of steady current versus its own capacity was constant. With the proposed strategy, current sharing is realized when the battery capacities are match, so the balancing result with matched battery capacities can be seen as a special case of mismatched results. The theoretical and actual balancing times required to achieve SoC consistency under different cases are collected in Figure 14:0 To obtain the ideal curves, \(u_{k}\) was assumed to be constant at 12 V to power the load in Section 3.4. Compared with the ideal time, the actual time was reduced. In the actual experiment, the battery voltages decreased and internal resistances increased during a long discharge, so \(d_{k}\) increases to keep \(u_{\text{dc}}\) unchanged and hence \(i_{k}\) gradually increased. With the same CDRs and circuit parameters, the higher the sum current, the shorter the duration required to eliminate SoC differences. In fact, this phenomenon contributes to the reduced balancing time. Figure 14:1 Experimental curves under battery degradation: (**a**) voltage in parallel applications, (**b**) voltage in series applications, (**c**) currents in parallel applications, (**d**) currents in series applications, (**e**) SoC in parallel applications, and (**f**) SoC in series applications. To show the performance differences, experiments using the droop methods in reference [2] and [10] were further executed.