## 2 Circuit Design  
The main concern in LNA design is the achievement of the lowest _NF_ possible because it is critical for the overall _NF_ of the system. In this work, the LNA is divided into two fully differential CS stages with source degeneration, as shown in Figure 1. All the values of the passive components used in the circuit are described in Table 1. The advantage of using a CS topology with inductive degeneration is the possibility of simultaneously achieving impedance matching for minimum _NF_ and maximum gain (\(G_{max}\)) [15]. This topology is widely used in applications with very low _NF_. In comparison to CS amplifiers, the common gate (CG) topology is frequently used in wideband applications, because of its potential to achieve a higher gain. However, the _NF_ obtained is usually higher in comparison with CS amplifiers. On the other hand, a higher gain can be obtained with a cascode architecture as well, but at the expense of higher power consumption, since the supply voltage cannot be reduced due to the presence of two transistors in the same branch. Transistors M1 and M2 in Figure 1 are the core of the first stage, and are biased with the DC voltage \(V_{G}\). Transistors M3 and M4 are the core of the second stage, and they are sized and biased exactly as M1 and M2. The degeneration inductances \(L_{s}\) are used to improve the noise and IRL of both stages. The input matching network of the circuit is efficiently implemented by the input transformer T1, which is characterized by the coupling factor \(k_{1}\), primary inductance \(L_{p1}\), and secondary inductance \(L_{s1}\). The same applies to transformers T2 (\(k_{2}\), \(L_{p2}\), \(L_{s2}\) ) and T3 (\(k_{3}\), \(L_{p3}\), \(L_{s3}\) ). Transformer T1 performs three tasks simultaneously: translation from SE to differential mode, impedance matching, and efficient DC biasing of transistors M1 and M2 through the center tap connection of the secondary. In the same way, transformer T3 has the same task at the output node, but it converts the differential mode signal into SE mode in order to facilitate the measurement procedure of the amplifier. Transformer T2 is used to couple stages 1 and 2 and is also efficiently used to bias the drains of M1 and M2, and the gates of M3 and M4 at the same time, while performing interstage impedance matching. An integrated transformer occupies the same space as a single inductor but performs three tasks simultaneously, therefore, we are able to save a significant amount of area. Finally, capacitors \(C_{m}\) of 195 fF are used at the gates of M3 and M4 to improve impedance matching without significantly compromising the performance and area of the resulting circuit. To perform device sizing, we inspect the most relevant performance metrics (i.e., the minimum \(NF\) and \(G_{max}\)) in relation to the current density \(J_{DS}\) for a number of device geometries. As depicted in Figure 2, for a device geometry of 60 \(\upmu\)m with 120 fingers (0.5 \(\upmu\)m per finger), a minimum \(NF\) of 1.17 dB is obtained when the device is biased with a \(J_{DS}\) of 0.1286 mA/\(\upmu\)m. Thus, a drain current \(I_{DS}\) of 0.1286 mA/\(\upmu\)m x 60 \(\upmu\)m = 7.71 mA is required. To achieve this current density, a gate voltage \(V_{G}\) of 0.38 V is employed. Therefore, we choose this size and biasing conditions for the CS transistors M1 and M2. Once the device is biased with a DC drain current of 7.71 mA, the resulting optimum source impedance \(S_{opt}\) required at the gate of M1 and M2 is calculated to achieve the minimum \(NF\). In a conventional design, a complex input matching network would be needed to match the \(S_{opt}\) to the 50 Ohms of the input antenna, but thanks to the differential approach, we are able to efficiently use transformers for this task.