# Doherty Power Amplifier Design via Differential Combining
## 2 Proposed Combiner  
In [11], a differential combiner was proposed to address the transistors' output capacitance by summing the currents from each transistor at a specific chosen frequency. While this method is highly effective at relatively high frequencies, its application becomes less appropriate for frequencies outside this range, limiting its versatility. Thus, the main disadvantage of the work in [11] is its limitation when implemented at relatively low frequencies. The load of one of the transistors is frequency-dependent, which significantly impacts the transistor's load impedances at low frequencies. In this context, the remaining imaginary part in the work shown in [11] affects the desired load modulation expected in DPAs. In contrast, this new combiner theoretically has the ability to eliminate that frequency dependence at the design frequency, allowing it to be used even at relatively low frequencies. The approach presented in this paper builds on and complements this work by enabling compensation across a broader spectrum, theoretically allowing for application at any chosen frequency. This enhancement significantly expands design flexibility and adaptability, making it suitable for a wide range of frequency applications. In this work, we introduce a new differential combiner that effectively compensates for these capacitances at any chosen frequency, thereby addressing the limitations of the previous design. This is achieved by adding a capacitor with a value of \(2C_{OUT}\) exactly at the midpoint of the \(\lambda/4\) transmission line proposed in [11]. This innovative approach allows for precise capacitance cancellation, independent of the operating frequency, thereby broadening the combiner's applicability to a wider range of designs, including those with varying frequency requirements. The proposed combiner is depicted in Figure 1a, where \(C_{OUT}\) represents the output capacitance of the transistor used. The simple yet effective addition of this capacitor ensures that the combiner can be employed in various high-frequency applications. \begin{table}
\begin{tabular}{c c c c c c} \hline \hline
**Ref** & **[8]** & **[9]** & **[10]** & **[11]** & **This Work (Sim.)** \\ \hline
**BW (GHz)** & 24–28 & 24–28 & 28 & 27.5–29.5 & **30–34** \\ \hline
**PAE\({}_{\text{64D}}\)** (\%) & 14–32 & 18.1–30.1 & 31 & 21–24 & **14–28** \\ \hline
**PAE\({}_{\text{sat}}\)** (\%) & 23–41 & 27.8–36.8 & 42 & 24–34 & **24–37** \\ \hline
**P\({}_{\text{OUT}}\)** (dBm) & 34–36 & 35.4–36 & 26.5 & 32–33 & **36.5–37** \\ \hline
**S. Gain** (dB) & 11–13 & 8–11 & 11.8 & 8–12 & **11–14** \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Comparison with state-of-the-art MMIC DPAs. Furthermore, the proposed combiner structure offers additional benefits when the network is loaded with a resistor \(R\), as illustrated in Figure 1. Under these conditions, the load seen at each transistor's current reference plane becomes \(2R\). This characteristic makes the combiner particularly advantageous for use with transistors that require high load impedance, which is a common scenario in millimeter-wave (mmW) applications. This feature not only simplifies the design process for such systems, but also enhances performance by ensuring that the load impedance is optimally matched to the transistors' requirements. To validate the functionality of the proposed combiner, we refer to the equivalent circuit presented in Figure 1b. The chosen frequency is called \(f\) and \(\omega=2\pi f\). Using the ABCD matrix formulation for each network element, the following relationship is obtained for the drain voltages and currents of each device, here represented by \(V_{1}\), \(V_{2}\), \(I_{1}\) and \(I_{2}\):  
\[ \begin{bmatrix}V_{1}\\ I_{1}\end{bmatrix} =