# Automatic Configurable Hardware Code Generation for Software-Defined Radios+
## 8 Experimental Results
### A Case Study
**MIMO-OFDM RX (IEEE 802.11a)**: The MIMO-OFDM RX system is illustrated in Figure 11f and the blocks for each of the four receive paths operate in the same way as the corresponding blocks for IEEE 802.11a standard receiver in Figure 11b. The only exception is the newly added parallel-to-serial (**P/S**) block which serializes the four parallel 48-sample data streams to a single stream of 192 samples. On each port of the four input ports, the _P/S_ consumes the data samples with the access pattern \([(10000)^{48}]\) (i.e., one data sample is consumed every fifth cycle starting from the first cycle) and it uses pattern \([(01111)^{48}]\) on its output port (i.e., produces four samples every five cycles). 7. **GSM DDC**: The GSM DDC as shown in Figure 11 accepts a high sample-rate (69.33 MSPS) bandpass signal from the source block which produces one sample every five cycles using pattern \([00001]\). The data produced by the numerically controlled oscillator (**NCO**) with pattern \([00001]\) is mixed with a bandpass data to produce a low sample-rate (270.83 KSPS) data stream. Please note that the mixing process is performed by a digital mixer block with the input access pattern \([10]\) and the output access pattern \([01]\). The cascaded integrator comb (**CIC**) block performs a decimation of factor 256 by receiving the 256 samples with pattern \([(1)^{256}]\) (i.e., consumes 256 samples at the rate of one data sample on every cycle of \(ET=256\)) and produces one sample every 256 cycles using pattern \([(0)^{255}1]\). The rest of the blocks use pattern \([1]\) for both input and output ports. Lastly, the compensation of the CIC signal is performed by a compensating FIR filter (**CFIR**) which is followed by a programmable FIR filter (**PFIR**) that finalizes the filtering process. 8. **FM DDC**: The FM DDC in Figure 11h accepts the high sample-rate (81.92 MSPS) bandpass signal and produces a low sample-rate (160 KSPS) signal. The decimation factor of 512 is facilitated by the two _CIC_ filters (_CIC1_ = input pattern \([(1)^{128}]\) and output pattern \([(0)^{127}1]\), and _CIC2_ = input pattern \([(1)^{4}]\) and output pattern \([(0)^{3}1]\)) with respective decimation factors of 128 and 4. Each _CIC_ filter is followed by a compensating filter (i.e., _CFIR1_ and _CFIR2_ respectively) which improves the corresponding _CIC_ output signal. Each of the eight SDR applications is associated with ten design variants (range: _V1-V10_) which are generated under ten throughput constraints which are 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90% and 100% of the maximum throughput for each application as shown in Table 3. For each application, the throughput is relative to a sink actor where the maximum throughput \(\tau_{max}\) is determined as described in Section 3.2. The results of different throughput constraints may be similar, in which case the _All_ column (range: _T1-T8_) of Table 3 is used to to group all the design variants for each application. We have represented the throughput to be measured in samples per cycle (SPC). SPC can clearly be translated into the more standard samples per second (SPS) units by multiplying the value by the clock frequency. However, we chose to use SPC as this is a more FPGA independent measure - for instance, an FPGA that can support a higher clock rate will correspondingly achieve a higher throughput. A real example is using the maximum throughput value of IEEE 802.11a TX which is 0.007752 SPC together with D/A converter (i.e., 16-bit I/Q sink actor) driven by the FPGA at the clock speed that meets standard transmission data rate of 54 Mbps. By choosing the D/A clock speed of 218 MHz, the practical data rate can be computed as 0.007752 \(SPC\)\(\times\) 218 MHz \(\times\) (2\(\times\)16-bit I/Q sample) = 54.078 Mbps that equals the standard data rate.