# Architecture and Process Integration Overview of 3D NAND Flash Technologies
## 4 Conclusions  
Currently, the demand for NAND flash memory continues to grow. It has various applications, such as in solid-state drives, and it is widely used in mobile devices requiring data storage. Over time, the planar flash array has evolved into a 3D integrated architecture to increase memory capacity and overcome scaling issues. With over 10 years of development, there has been a significant reduction in the cost per bit of 3D NAND flash. As the number of stack layers increases, a high aspect-ratio etching technology is required for hole formation, considering the fact that it is hard to reduce the hole critical dimension due to gate dielectric stacks, and there is a problem with peripheral circuits and WL thickness. Several efforts have been made to solve these issues, including etching technology with an extremely high aspect-ratio and a so-called four-dimensional NAND flash technology with peripheral circuit under a flash cell array. In addition, program methods have been proposed to reduce the cost per bit of flash instead of stacking layers and conducted to obtain the distribution margin of \(V_{\text{T}}\) for quadruple level cell (QLC) implementation [20; 46; 47; 48; 49]. Starting with the BiCS structure, we have reviewed various kinds of 3D NAND flash structures by classifying and comparing their structures and fabrication methods. Depending on the channel direction and gate formation, their fabrication methods and consequential electrical characteristics significantly differ, and vertical NAND structures with a charge trapping layer have been commercialized, thanks to their easy integration method and high stackablity. In addition, it is believed that etching technology with a high aspect-ratio and programming scheme for accurate multi-level operations should be further improved for the bit cost scaling of 3D NAND flash technologies. However, it is expected that there would be a physical limitation to increase the number of stack layers infinitely, even assuming excellent hole etching technology, and it is necessary to investigate how to solve this through structural changes or emerging memories. Various emerging memories, including resistive random access memory (RRAM) [50; 51; 52; 53; 54; 55; 56; 57; 58; 59] and phase-change random access memory (PCRAM) [60; 61; 62; 63; 64; 65; 66; 67], have been widely investigated for faster speed and lower operating voltage, but the reliability is still considered one of the most important factors to be solved for the competition with mainstream memories. The 3D integration of emerging memory devices should also be investigated to replace 3D NAND flash, and it can be inspired by  
Figure 19: Process flow of STAR NAND flash [43], Copyright IEEE, 2012.  
the architectures and fabrication methods of 3D NAND flash technologies. In addition, we believe that it is important to investigate memory computing applications, including neuromorphic systems and processing-in-memory using flash technology, in order to expand the function and capability of 3D NAND flash beyond data storage [68; 69; 70; 71; 72; 73; 74; 75; 76; 77].  
Investigation, G.H.L., S.H., and J.Y.; writing--original draft preparation, G.H.L.; writing--review and editing, H.K.; supervision, H.K.; funding acquisition, H.K., G.H.L., and S.H. equally contributed to this work. All authors have read and agreed to the published version of the manuscript.  
This study was supported in part by the National Research Foundation (NRF), funded by the Korean Government under grant nos. 2019M3F3A1A03079821 and 2020M3F3A2A01081656, in part by the Brain Korea 21 Four Program, and in part by the INHA UNIVERSITY Research Grant.  
Not applicable.  
Informed Consent Statement: Informed consent was obtained from all subjects involved in the study.  
The data presented in this study are available on request from the corresponding author.  
The authors declare no conflict of interest.