# Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions
## 3 Materials and Methods
### Resource Distribution and Reconfigurable Partition in Xilinx FPGAs  
Xilinx FPGAs support module-based partial reconfiguration under a name of Dynamic Function Exchange (DFX). At the top level of hierarchy, any Partially Reconfigurable design is divided into a number of reconfigurable partitions and a static part. Each partition needs to be assigned to a partition block (PBlock)--a PR compatible sector of the FPGA fabric. At the top level, all partitions are treated as black-boxes; any reconfigurable module with compatible interface can be implemented within the partition, provided that PBlock resources are satisfactory for module requirements.  
Modern Xilinx FPGA architectures use highly heterogeneous resources. For the purpose of PBlock construction analysis, only reconfigurable logic resources are of relevance, other resources (including communication transceivers, input-output buffers, PCIe controllers, XADC converters, etc.) will be omitted. Xilinx FPGAs use coarse Block RAMs and DSPs alongside two variants of fine-grained LUT-based Configurable Logic Blocks--with (CLBM) and without (CLBL) additional distributed RAM and shift registers. The internal structure of each Xilinx FPGA device is highly connected to the construction of its clock tree. The fabric is divided into clock regions corresponding to horizontal clock routing channels branching from a centrally located vertical clock spine or multiple vertical spines in the case of UltraScale devices. Resources are grouped by type and distributed unevenly in columns perpendicular to clock region rows (Figure 1). In general, resources of a single type fill an entire span of a column within a single clock region--occaional occurrences of non-reconfigurable resources and empty spaces in the FPGA fabric prevent some columns from being uniform across multiple clock rows. In both Xilinx 7-Series and UltraScales, routing resources used by the components are placed alongside either side of the logic alternately, in separate interconnection block columns (INT). Despite being uneven, the distribution is very regular with observable repetitiveness of identical patterns (Figure 1).  
The smallest unit of configuration memory that can be independently reprogrammed is defined as a configuration frame. It contains configuration data for all components in a clock-region wide section of a single logic column and the routing corresponding switchboxes. Configurations of individual components reside at fixed-offset positions, based on their relative vertical location within the span of the clock region. A partition block can cover area corresponding to multiple configuration frames tiled horizontally (within a clock region) and vertically (across multiple regions), but only rectangular shapes are allowed. Furthermore, enlarging the partition area increases time required to reprogram it. Theoretically, reconfiguration of a single frame is allowed, but as partial reconfiguration flow in Xilinx Vivado tools does not allow separating adjacent interconnection tiles (back-to-back violation) [46], it is only feasible at specific locations.