## 4 Measurement Results  
The LNA chip draws 7.9 mA dc core current from the 1.8 V supply voltage. The S parameters of the designed gain and input return loss are depicted in Figures 9 and 10. The measured power gains at 2.5/3.5/5.2 GHz were 12.3/15.3/13.1 dB, and the input return losses were more than 10 dB among the three operating frequencies. The noise figure was measured using Agilent N8975A noise figure analyzer with Agilent 346C noise source. The simulated and measured noise figures at the same bias condition are depicted in Figure 11. The measured noise figures at 2.5/3.5/5.2 GHz were 2.3/2.2/2.6 dB. The relation between the input third-order intercept point (IIP3) and the 1-dB compression points (P\({}_{\rm 1 dB}\)) is shown as [24].  
\[\rm IIP_{3}=P_{\rm 1 dB}+9.6\;dB \tag{12}\]  
The measured P\({}_{\rm 1 dB}\) are \(-15/-16/-17\) dBm at 2.5/3.5/5.2 GHz, as shown in Figure 12, therefore, IIP3 could be calculated as \(-5.4/-6.4/-7.4\) dBm.  
Figure 10: Measured and simulated S-parameters (\(S_{22}\) and \(S_{12}\)) of the proposed LNA.  
Figure 9: Measured and simulated S-parameters (S21 and S11) of the proposed LNA.  
The measurement results of the proposed LNA are summarized with recently published information in Table 1.  
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline
**Ref.** & **Technology** & **Freq. (GHz)** & **Gmax (dB)** & **NFmin (dB)** & **IIP3 (dBm)** & **Power Consumption** & **FOM 5** & **Area (mm2)** \\ \hline \multirow{3}{*}{[26]} & \multirow{3}{*}{0.18-\(\mu\)m} & 2.4 & 14.4 & 3.3 & \(-\)7.12 & \multirow{3}{*}{7.2} & \multirow{3}{*}{1.66} & \multirow{3}{*}{0.63} \\  & & 3.5 & 13 & 3.8 & \(-\)6.2 & & & \\  & & 5.2 1 & 10 & 4.3 & \(-\)4.34 & & & \\  & & 2.4 & 22.1 & 2.8 & \(-\)18.2 & & & \\
[27] & 0.13-\(\mu\)m & 3.4 & 22.6 & 2.2 & \(-\)15.3 & 4.6 & 6.01 & 0.49 \\  & & 5.4 1 & 24.8 & 3.1 & \(-\)20.4 & & & \\  & & 2.8 2 & 16.1 & 2.4 & \(-\)4 & & & \\
[28] & 0.13-\(\mu\)m & 3.3 & 14.2 & 3.0 & \(-\)2 & 6.4 & 9.61 & 0.44 \\  & & 5.65 & 14.9 & 4.8 & \(-\)4.2 & & & \\  & & 2.4 & & & \(-\)12 & & & \\
[29] & 0.13-\(\mu\)m & 3.5 & 15 & 2.7 & \(-\)13.5 & - 6 & -6 & -6 \\  & & 5.2 & & & \(-\)13 & & & \\
[30] & 0.18-\(\mu\)m & 2.4-11 & 14.8 & 4.1 & \(-\)11.5 & 3.4 & 1.72 & 1.1 4  & 2.3 & 2.7 3 & \(-\)3.2 3 & 13.1 & 26 & 0.34 \\  & & 2.5 & 12.3 & 2.3 & \(-\)5.4 & & & \\ This work & 0.18-\(\mu\)m & 3.5 & 15.3 & 2.2 & \(-\)6.4 & 14.2 & 2.9 & 0.52 \\  & & 5.2 & 13.1 & 2.7 & \(-\)7.4 & & & \\ \hline \hline \end{tabular}  
* \({}^{1}\) 5 GHz band provides less than 800 MHz. \({}^{2}\) 2 GHz band lacks for time-division long-term evolution (TD-LTE) Band 40. \({}^{3}\) Simulation result. \({}^{4}\) Chip area is the largest in Table 1. \({}^{5}\) Only the best result for all operating bands is shown. \({}^{6}\) Full TRX design. IIP\({}_{3}\): input third-order intercept point; FOM: figure of merit.  
\end{table}
Table 1: Performance summary of the published CMOS LNAs.  
Figure 11: Measured and simulated noise figures of the proposed LNA.  
Figure 12: The linearity (\(P_{1 dB}\)) of the proposed LNA.  
For performance comparison, the figure of merit (FOM) is defined by [31]:  
\[\text{FOM}=\frac{\text{Gain(abs)}\times\text{IIP3(mW)}\times\text{fc(GHz)}}{( \text{NF}-1)(\text{abs})\times\text{Powerconsumption(mW)}} \tag{13}\]  
Comparing the performance among the three operating frequencies, in terms of power gain, noise figure, and cost, the proposed switched triple-band LNA is the only one that can cover the whole target bands and provide the lowest NF\({}_{\text{min}}\) with adequate power gain among 2-, 3-, and 5-GHz frequencies. The measured power consumption of the proposed design is slightly large due to the additional buffer amplifier stage for testing purposes. In this study, the circuit simulation was performed using Agilent's Advanced Design System (ADS) software with a TSMC design kit. In addition, the LNA is fabricated in an inexpensive 0.18-\(\upmu\)m CMOS process with a smaller chip-size, therefore, it has an advantage in terms of lower manufacturing cost.