## 4 Study Cases and Analysis Results  
In order to evaluate the proposed design methodology, four study cases were selected with the initial specifications listed in Table 7. These cases show different design starting points and they involve the optimization of at least one circuit variable. In the first study case, the design goal is to find the maximum output power for a given \(V_{DD}\) and \(R_{L}\). This example could be useful in wireless power transfer applications, where the power amplifier load could be fixed into the PA design as a specification for maintaining the high efficiency of the inductive link while using an adaptive impedance matching network between the output of the amplifier and link [1; 19]. The second case requires the maximum load resistance while using \(D=0.5\). This design approach could be useful in VLSI applicationsm where the MOSFET driver is integrated, since, by setting \(D\) = 0.5, its layout complexity is reduced and consequently the overall chip size too [16]. Furthermore, maximizing the load value decreases the power dissipation in the parasitic elements of the output load network because the current delivered to the load under the same output power is decreased [19]. The design goal of the third study case is to find the maximum \(C_{p}\) value for a given \(P_{out}\), \(R_{L}\), \(f_{o}\), and \(Q_{L}\). The \(C_{p}\) maximization improves the useful life of the semiconductor device and reduces the cost of the amplifier; this feature is relevant for several Class-E applications. Finally, the fourth study case looks for the higher \(R_{L}\) value with a limited RMS current through the switch. This design approach with a limited value of the switch RMS current could be used when the switch has size constraints, because the consumed power of the switch is directly related to this RMS value. Furthermore, the \(R_{L}\) maximization could be used in order to reduce the losses in the quasi-tuned LC circuit, as we discussed before. In each case, the unknown circuit values were found applying the proposed methodology by using the software Maple(tm), the obtained solutions are listed in Table 8. Additionally, the validation of the design solutions was made by circuit simulations in OrCAD PSpice (tm)Designer software. In all simulations were used ideal components and a voltage-controlled switch with zero falls and rise commutation times, off-resistance of 300 M\(\Omega\), and on-resistance of 10 m\(\Omega\). \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Specification** & **Case 1** & **Case 2** & **Case 3** & **Case 4** \\ \hline \(D\) & 0.4 & 0.5 & nv & nv \\ \(q\) & nv & nv & nv & nv \\ \(f_{o}\) [MHz] & 0.5 & 1 & 10 & 4 \\ \(Q_{L}\) & nv & nv & 30 & 32 \\ \(V_{DD}\) [V] & 12 & nv & nv & 6 \\ \(P_{in}\) [W] & nv & 1 & 8 & 6 \\ \(P_{out}\) [W] & nv & 1 & 8 & 6 \\ \(\eta\) & 1 & 1 & 1 & 1 \\ \(R_{L}\) [\(\Omega\)] & 3.3 & nv & 2.4 & nv \\ \(L_{o}\) [uH] & nv & 33 & nv & nv \\ \(C_{e}\) [nF] & 22 & nv & nv & nv \\ \(C_{SH}\) [nF] & nv & 22.6 & nv & nv \\ maximize & \(P_{out}\) & \(R_{L}\) & \(C_{p}\) & \(R_{L}\) \\ \(I_{RMS_{SW}}\) & nv & nv & nv & \(<\)2A \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Design specifications. In study case 1, it is required the maximum output power for a given \(V_{DD}\) and \(R_{L}\), the specified duty cycle is 0.4, and the \(q\) value is undefined. The mathematical expressions of the unknown circuit values were obtained following the process that is described in the diagram of Figure 10. According to the \(P_{out}\) search space plotted in Figure 11a, the maximum output power for \(D=0.4\) is achieved at \(q=1.244\). Therefore, the unknown circuit components were calculated and listed in Table 8 using \(q=1.244\). Finally, the design solution was verified by simulation. The simulated \(P_{out}\) was 50.82 W, and the waveforms of the output power and average output power are shown in Figure 11b.