## 1 Introduction  
Single Event Upsets (SEU) have increasingly become a reliability concern for storage cells, such as Flip-Flops (FF), within Integrated Circuit designs (IC) [1]. While common in space, SEU occurrences on the ground have also been documented [2]. Electronic systems operating in environments with elevated radiation levels, such as space or high altitudes, should be hardened to limit the effects caused by ionized particle strikes [3]. When an ionized particle with sufficient energy strikes a sensitive region of a storage cell, it can cause the contents of the cell to become flipped. As feature sizes of transistors continue to scale down, the likelihood of SEUs within complex designs is expected to increase due to the smaller amount of deposited charge needed to cause an upset [4, 5]. Over the years, various techniques have been used to harden storage cells. These techniques may be performed at the schematic level of the cell or in the physical layout. One such design that has proved to be effective at preventing SEUs is the Dual Interlocked Cell (DICE). This design provides single-node upset immunity due to the interlocking of four back-to-back inverters [6]. However, at sub-micron bulk technology nodes, such as at 65 nm, 40 nm, or 28 nm nodes, the Soft Error Rate (SER) performance of the cell becomes less effective. This is because at these scales, the spacing between adjacent transistors is small enough that deposited charge clouds from ion strikes can often affect more than one transistor at a time. This charge-sharing phenomenon renders the DICE cell to be ineffective at preventing SEUs [2; 7]. While it is possible to reduce the charge sharing effect in bulk technologies through a smart layout design, as shown in [8], these alterations can come with increased area and performance penalties, as well as increasingly complex metal layer routing. Furthermore, it is not yet definitive if these layout changes can still make DICE effective at bulk nodes smaller than 28 nm. As such, the use of the Fully Depleted Silicon on Insulator (FD SOI) technology is attractive for DICE cells due to the limited charge sharing between adjacent transistors. Transistors developed with the FD SOI technology are fabricated on a small silicon island on top of a thinly Buried Oxide (BOX) layer, as shown in Figure 1. This provides various advantages over similar bulk technology nodes, but most notably, charge sharing between adjacent transistors is greatly reduced since each transistor is electrically isolated due to the BOX layer. Additionally, the amount of deposited charge from an ionized particle strike is decreased because of the small silicon island [9]. As a result, flip-flop designs using DICE latches have once again become an effective way to reduce SEUs within IC designs. However, when using nano-scale technologies, such as in the case of 22 nm nodes, the spacing between adjacent transistors may be small enough that the isolation provided by the BOX layer is no longer sufficient to completely prevent charge sharing [10]. Other techniques, such as guard-gate stacking, may be needed to further harden the DICE latch [10]. Additionally, the 22 nm FD SOI technology node allows for a new layout construct known as Continuous Active Diffusion (CnRx) [11]. This construct aims to remove the channel strain on PFETs by replacing any PFET active diffusion breaks with a special type of layout structure to produce an uninterrupted diffusion region. It is not yet fully known how this new construct will affect the soft error rates of hardened cells, such as DICE. From 28 nm node data, a conventional master-slave FF using back-to-back inverter latches in the FD SOI technology can potentially rival the SER performance of a hardened DICE design at a similarly sized bulk technology node [12; 13].