## 4 Results and Discussion
\begin{table}
\begin{tabular}{c c c c c c c c c} \hline \hline \multirow{2}{*}{**Design**} & \multirow{2}{*}{\begin{tabular}{c} **Datapath** \\ **(Bits)** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **No. of** \\ **LEs** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **No. of** \\ **Clock** \\ **Cycles** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Max. Freq.** \\ **(MHz)** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **Power** \\ **(mW)** \\ \end{tabular} } & \multirow{2}{*}{\begin{tabular}{c} **LE** \\ **Reduction** \\ **Rate (\%)** \\ \end{tabular} } & \multirow{2}{*}{\
\begin{tabular}{c} **Power** \\ **Resolution** \\ **Rate (\%)** \\ \end{tabular} } & \multirow{2}{*}{
\begin{tabular}{c} **FPCA** \\ **Device** \\ \end{tabular} } \\ \hline
**AE** & 100 & 1030 & 140 & 140.39 & 99.30 & 13.52 & 24.19 & \\
**LED** & 64 & 365 & 32 & 208.72 & 89.38 & & & Cyclone II \\
**PHOTON** & 100 & 826 & 108 & 321.44 & 41.60 & & & \\ \hline
**AE** & 100 & 1017 & 140 & 184.77 & 89.73 & 13.67 & 39.03 & \\
**LED** & 64 & 357 & 32 & 271.96 & 82.19 & & & Cyclone III \\
**PHOTON** & 100 & 821 & 108 & 338.75/250.0 & 64.99 & & & \\ \hline
**AE** & 100 & 1018 & 140 & 150.51 & 157.97 & 13.73 & 46.04 & Cyclone III \\
**LED** & 64 & 357 & 32 & 231.21 & 150.45 & & & LS \\
**PHOTON** & 100 & 823 & 108 & 336.36/250.0 & 142.21 & & & Cyclone IV \\ \hline
**AE** & 100 & 1024 & 140 & 176.87 & 147.38 & 13.58 & 33.06 & \\
**LED** & 64 & 357 & 32 & 254.19 & 120.52 & & & Cyclone IV \\
**PHOTON** & 100 & 828 & 108 & 361.53/250.00 & 99.65 & & & \\ \hline
**AE** & 100 & 1020 & 140 & 164.31 & 217.51 & 13.56 & 19.65 & \\
**LED** & 64 & 357 & 32 & 265.46 & 173.61 & & & Cyclone IV \\
**PHOTON** & 100 & 823 & 108 & 368.32/250.0 & 97.10 & & & GX \\ \hline \hline \end{tabular}
\end{table} 
Table 3: Synthesis and simulation results of authenticated encryption, LED, and PHOTON. AE runs at a frequency within the range of the single design of the LED. Table 3 illustrates the operating frequency of the single architecture, as well as the composite architecture. The operating frequency of the proposed AE is slightly lower than the frequency of both LED and PHOTON. This is because this design completes a full permutation round in a single cycle, as well as sharing more than a single operation in one cycle. Therefore, the cycle count is the same as the total number of permutation rounds of LED and PHOTON. The proposed AE scheme is efficient in terms of power consumption and area reduction. For the same number of permutation rounds, the utilization of logic resources is proportional to the power consumption. Sharing the common resources between LED and PHOTON and reducing the utilization of logic resources will result in a reduction in the power consumption. This includes the tradeoffs of security, cost, and architecture design. In this work, we aimed to optimize the architecture to reduce the logic resources, thus reducing the cost and power consumption. The available previous work related to targeted cryptographic primitives aims for a single-architecture design. Moreover, these architecture designs are mostly synthesized on Xilinx FPGA devices. Therefore, a proposed authenticated encryption architecture synthesized on Altera FPGA devices is compared with our single LED and PHOTON architecture designs. The LED and PHOTON architectures were individually designed and synthesized on several FPGA platforms. The cyclone family was used for synthesis and simulation. The results show similar resource utilization levels for all cyclone devices, as shown in Table 3. For the LED block cipher, the resource utilization was approximately 365 LE, whereas the PHOTON hash function utilizes 826 LE. The total logic utilization for both LED and PHOTON, when synthesized individually, is 1191 LE. However, the proposed architecture of LED-PHOTON authenticated encryption utilizes about 1030 LE for Altera Cyclone devices. This results in a reduction in the utilization of logic resources by approximately 14% in comparison with individual architectures.