# Vibration Suppression of Collaborative Robot Servo with Dual Encoders
## 6 BiSS Data Acquisition  
First, this paper needs to sample data from two encoders. This paper uses an absolute photoelectric encoder to research. The BiSS protocol is an open synchronous serial communication protocol that is freely available. The communication speed can reach up to 10 Megabits per second (Mbps), which is more than five times faster than some other commonly used serial communication protocols of the same type.  
The DSP sends a read signal via the serial peripheral interface (SPI) bus, and with the two SPI peripheral modules of the DSP, it can sample data from two encoders simultaneously. Upon receiving the read signal from the DSP, the encoder synchronously returns the data to the SPI bus. The DSP parses the returned data signal and extracts the encoder's single-turn value, alarm value, and other relevant information. As shown in Figure 5, D1 is the data transmitted from encoder1 to DSP, C1 is the clock signal sent from DSP to encoder1, D2 is the data transmitted from encoder2 to DSP, C2 is the clock signal sent from DSP to encoder2, D1+ and D1\(-\) are the differential signals transmitted from encoder1 to DSP1, and C1+ and C1\(-\) are the differential signals transmitted from DSP to encoder1. D2+ and D2\(-\) are differential signals transmitted from encoder1 to DSP1, while C2+ and C2\(-\) are differential signals transmitted from DSP to encoder1. DSP can convert differential signals into single-ended signals or vice versa through the SN65 HVD77D transmission chip. The BiSS encoder employs a cyclic redundancy check (CRC) to ensure the accuracy of data received by the DSP. If the CRC checksum calculated by the DSP is equal to the checksum sent by the encoder, then the received encoder data are accurate. Otherwise, encoder data that have not passed the verification are considered incorrect. In the design phase, it is recommended that the number of encoder check errors be displayed for operators to analyze. The schematic design was further optimized to enhance signal integrity and improve noise immunity. This was achieved through a strategic signal conversion approach: initially converting single-ended signals to differential signals and subsequently reconverting them back to single-ended signals at the receiving end. This configuration ensures that the extended transmission path utilizes differential signaling, thereby significantly improving the system's immunity to electromagnetic interference (EMI) and common-mode noise. The differential signaling implementation during the critical transmission phase provides inherent noise rejection capabilities, while the single-ended conversion at both ends maintains compatibility with standard interface requirements.  
In this paper, the PWM modulation frequency is 10 kHz, the control period is 100 us, and the sampling period is also 100 us. The clock frequency is 2.5 M, the clock cycle is 0.4 us, and it takes about 12.8 us to sample data from one encoder. The time to sample two encoders is 25.6 us. The time left for other processes is 74.4 us, which is enough. However, if the sampling frequency is further increased and the sampling time is reduced, it is still beneficial.