# A 4.1 GHz-9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer
## 2 Materials and Methods
### Circuit Design of MMD
#### 2.2.2 Program Counter and Swallow Counter  
A program counter and swallow counter has a similar structure. The structure of counter P and counter S is shown in Figure 6. A six-bit counter is used as counter P, while counter S is four-bit. Both counter P and counter S are down counters. Take counter S as an example. The output of the DFF divider chain can be regarded as a code. The code is reset to 0000 as the reset bit is active. The code state will change to \(1111\) when the next clock edge come. The code will minus one as the following clock edge come, until the code change to \(\overline{\text{C}_{3}\text{C}_{2}\text{C}_{1}\text{C}_{0}}\), the counter stops counting. As the first state of code is 0000, the counter counts S + 1 rather than S until it stops. Figure 4: (**a**) Block diagram of the2/3 prescaler; (**b**) Block diagram of 4/5 prescaler. Figure 5: Simulation result of the input sensitivity curves of the prescaler. Counter P has the similar principle of counter S. As the codes turn to \(\overline{C_{5}C_{4}C_{3}C_{2}C_{1}C_{0}}\) from 000000, the reset bit reset the counter and the codes turn to 000000. However, each stage has a time delay. Due to the time delay, wrong state may occur when the code turns. For example, when the codes turn from 000000 to 111111, there are five temporary states 000001, 000011, 000111, 001111, 011111 occur. These code states may cause wrong result of the reset signal, which will cause error count. In order to avoid the wrong state, a DFF is added before the output as shown in Figure 6b. And the DFF has another effect as a retiming block [22]. It performs duty-cycle equalization function of the reset signal. Because of the adding of the retiming DFF, the counter counts P + 3 rather than P.  
In the meanwhile, the time delay between each stage of DFF will accumulate. If the accumulated time delay of the DFF divider chain is larger than the clock period, error state will appear. Therefore, for those counters with several DFFs, the time delay of each DFF should be considered in the design, and the working frequency of DFF should be in the range of the frequency of the input signal. For a counter with a six DFF-stage chain, the input signal of the first DFF is the output of the N/N + 1 prescaler, which has a frequency of \(f_{\rm dm\_out}\). The input signal frequency of the last stage of the divider-chain is \(f_{\rm dm\_out}/32\). This means that the design of divider should both consider the high working frequency condition and low working frequency condition. DFF based on transmission gate is a conventional structure and it is widely used as a divider. The circuit of such DFF is shown in Figure 7a. The DFF based on transmission gate has a good low working frequency performance, but the time delay of such DFF is large and it cannot work at a high frequency. Therefore, a TSPC DFF is used in the counter. It has a smaller time delay, and it can work at a higher frequency than the conventional structure, which satisfies the demand of high operating frequency. The circuit is shown in Figure 7b. Figure 6: (**a**) Block diagram of counter S; (**b**) Block diagram of counter P.  
The conventional DFF, based on transmission gate and TSPC DFF, are designed and simulated. As the input signal is 1 GHz pulse signal, the time delay of two DFF in \(-\)40, 50 and 125 \({}^{\circ}\)C is simulated. The result is shown in the Table 1 and Figure 8. It can be seen from the Table 1 and Figure 8 that the time delay of rising edge of the TSPC is much smaller than the conventional DFF, and the time delay of the falling edge is also smaller when the TSPC is used.