## 4 Emerging Lightweight Security Approaches
### Symmetric Encryption--Lightweight AES Approaches
#### 4.1.1 Lightweight AES for FPGA  
AES transformations can be done in hardware or software. When it is implemented in hardware, it typically uses field programmable array (FPGA) integrated circuits. An example of lightweight AES implementation in FPGA is presented in [76], whose main objective was to reduce the latency of the AES transformations by reducing the number of clock cycles of AES transformations. The AES transformations include substitution and permutation transformations. Each round of encryption consists of four AES transformations, in the order shown in Figure 7. In each round, a unique key is used. These round keys are obtained through key expansion based upon the first cipher key [43]. Before the first round begins, the AddRoundKey transformation is performed between the 16-byte block (which is a four-by-four-byte matrix) and the cipher key. Then, all four transformations are performed in the following order: SubBytes, ShiftRows, MixColumns, and AddRoundKey. Each round has four transformations, except for the final round, which consists of only the last three transformations. \begin{table}
\begin{tabular}{c c c c c c c} \hline \hline \multicolumn{3}{c}{**Block Cipher Primitives**} & \multicolumn{3}{c}{**High Performance**} & \multicolumn{2}{c}{**Implementation**} \\ \hline \multicolumn{3}{c}{**Small Block**} & **Small Key** & **Simple Round** & **Key Schedule** & **Custom CPU** & **Crypto Array** & **Software** & **Hardware** \\ \hline LightAES for & & & & & & & \(\checkmark\) & \(\checkmark\) \\ FPGA [76] & & & & & & & \(\checkmark\) \\ \hline LPADA [77] & & & & & & & \(\checkmark\) \\ \hline LAES [78] & & & \(\checkmark\) & & & & & \(\checkmark\) \\ \hline ALE [79] & & & \(\checkmark\) & & & & & \(\checkmark\) \\ \hline Masked AES [80] & & & & \(\checkmark\) & & & & \(\checkmark\) \\ \hline AES-64 [81] & \(\checkmark\) & \(\checkmark\) & & & & & \(\checkmark\) \\ \hline ISA [82] & & & & & \(\checkmark\) & & \(\checkmark\) & \(\checkmark\) \\ \hline Quark [83] & & & & & & \(\checkmark\) & & \(\checkmark\) \\ \hline ECC & & & & & & & \(\checkmark\) & \\ WaterMark [84] & & & & & & & \(\checkmark\) & \\ \hline ECIOT [85] & & \(\checkmark\) & \(\checkmark\) & & & & \(\checkmark\) & \\ \hline ECC & & & & & & & \(\checkmark\) \\ Accel. [86] & & & & & & & \(\checkmark\) \\ \hline \hline \end{tabular}
\end{table} 
Table 7: Emerging lightweight approaches for IoT that are based on AES and ECC encryption. The authors in [76] programmed the SubBytes transformation to be done in a parallel manner. Because SubBytes operates independently on each byte of the four-by-four state matrix using a substitution table called S-Box, they propose to substitute multiple bytes in the matrix in parallel. Moreover, the S-Box can either be stored in the device's memory or be generated based on equations explained in the Federal Information Processing Standard (FIPS) 197 AES standard [43]. In the work proposed in [76], the S-Box is pre-calculated and used as a look-up table to substitute multiple bytes at the same time. A second parallel operation that they propose is the MixColumns transformation, which performs linear transformations on each column of the state matrix. In the MixColumns transformation, each column of the state matrix is a vector that is multiplied by a fixed four-by-four matrix, resulting in a new column in the state matrix. The authors explain that the multiplications on each column can be done in parallel. Another design choice proposed in [76] was to calculate the round key at every round, instead of calculating the complete key schedule prior to the encryption and storing all keys in memory. This is mainly to save memory storage. These techniques mainly address the lightweight primitives of hardware improvements at the FPGA level for low-resource devices, to reduce delays and save memory space. The parallel operations of SubBytes and MixColumns transformations can be considered a type of system performance primitive, as crypto-array operations.