# Development and Testing of an Active Noise Control System for Urban Road Traffic Noise
## 3 Development of the Active Noise Control Prototype System
### System Software Development  
Upon finalizing the hardware selection, a software system is needed to drive the hardware platform and achieve functionalities such as audio signal transmission and algorithm execution.  
(1) FPGA Development Tools and Language  
This study used the Vivado 2018.3 software for development. Vivado is one of the primary development tools for FPGAs, supporting various data input methods, integrated synthesizers, and simulators. It can complete the full development process from new project design input to generating bitstream for FPGA download. The development process utilized Verilog HDL, a hardware description language that supports hardware development, verification, synthesis, and testing functions. The related active noise control algorithms can be implemented using Verilog HDL. Notably, compared to hardware filters, FPGA multi-stage adaptive filters implemented via software demonstrate greater flexibility and stability.  
(2) Audio Data Interaction and Processing  
The audio data interaction between the WM8731 audio decoding chip and the FPGA main chip is achieved via two serial pins, ADCDAT and DACDAT, necessitating data parallelization. As shown in Figure 7, the data transmission and processing of noise signals include the following steps.  
Initially, the FPGA development board configures the WM8731 audio chip's sampling rate, data format, and conversion initiation functions using the I2C configuration module, setting the sampling rate at 48 KHz, and data length for conversion at 16 bits. Next, the WM8731 chip employs the ADC conversion module to transform the analog signal collected by the sensor into a digital signal, inputting this into the FPGA's serial-to-parallel conversion module. This module then transforms the input serial digital signal into parallel  
\begin{table}
\begin{tabular}{p{85.4 pt} p{113.8 pt} p{113.8 pt} p{113.8 pt} p{113.8 pt}} \hline \hline
**Hardware** & **Model** & **Manufacturer** & **Specifications** & **Function** \\ \hline FPGA Development Board & AX7020 & Alinx Electronic Technology (Shanghai, China) Co., Ltd. & 85,000 logic units, 220 multipliers & Code debugging and system control \\ \hline Audio Module & WM8731 & Cirrus Logic Inc. (Austin, TX, USA) & Sample rate: 8–96 KHz, data length: 16–32 bit & Audio decoding, analog-to-digital conversion \\ \hline Reference Sensor & Microphone & Shenzhen Huayun Ziyuan Electronics Co., Ltd. (Shenzhen, China) & Frequency response range: 20 Hz-20 kHz, 3.5 mm audio jack, unidirectional & Noise acquisition \\ \hline Active Loudspeaker & SM-1800 & Feixinyuan Audio Company. (Beijing, China) & Frequency response range: 20 Hz-20 kHz & Secondary source of in the cancellation area \\ \hline \hline \end{tabular}
\end{table}
Table 1: The hardware description of active noise control prototype system.  
Figure 7: Noise signal data transmission and processing.  
16-bit data and inputs it into the data reorganization module. After undergoing de-zeroing and redundancy removal in this module, the data are input into the ANC algorithm module.  
The ANC algorithm module employs the Least Mean Squares (LMS) algorithm, a commonly used adaptive filtering algorithm suitable for processing signals with unknown attributes. The calculated secondary source signal is sent to the parallel-to-serial conversion module, which transforms the parallel data back into serial data and sends it to the WM8731 chip to complete the digital-to-analog conversion. Finally, the active speaker emits the secondary source audio, completing the active noise control.  
(3) Control Program and Debugging  
In the overall system, FLASH is primarily used for control program storage, while the JTAG interface is used for program debugging and burning. These two elements jointly ensure the system's stable operation and effective debugging.