# High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA
## 3 The ASMD-FSMD Technique  
The development of digital devices using the ASMD-FSMD technique consists of constructing the ASMD chart of device behavior and creating Verilog code in the form of the FSMD [14]. The ASMD chart consists of ASMD blocks (Figure 4). Every ASMD block represents the FSMD's behavior within a single state over one clock cycle. The ASMD block includes one state box (rectangle). Also, it may have several decision boxes (rhombuses) and conditional output boxes (ovals). The rhombuses may both precede ovals and follow ovals. The ASMD block has only one input, which is the input to the state box, and may have one or more outputs. The inputs and outputs of boxes are connected by arcs. Feedback loops are prohibited inside an ASMD block. Algorithm loops and wait states in the ASMD chart are implemented using external feedback (concerning the ASMD block). Figure 3: The control device of the sequential multipliers c and d in the form of Mealy’s FSM. For the Moore FSMD, the operations performed in some states are written inside the state box. In the Mealy FSMD, the actions associated with transitions are noted within the conditional output boxes. Logical expressions are placed inside the decision boxes, with the decision block outputs being represented as either zero or one, indicating transitions based on whether the logical expression evaluates to false or true. Any operations written into either rectangles or ovals can be used if they are admissible in the Verilog HDL. The same is true for the logical expressions written down in rhombuses. The ASMD chart is a composition of connected ASMD blocks. Each output of any ASMD box can be connected to only one input of another box, i.e., branching of the algorithm is possible only in the decision boxes. The Verilog code of the design is built directly from the ASMD chart created before. The ASMD-FSMD technique can be represented as the following Algorithm (Figure 5):  
1. The FSMD states are determined. 2. The ASMD block is constructed for each FSMD state. 1. Within the ASMD decision boxes, logical expressions are placed, and their values are evaluated in this state. 2. In a Moore FSMD, the actions that are executed on the register content within this state are listed within the state box. 3. In the Mealy FSMD, the operations carried out on the content of the registers during these transitions are placed in the conditional output box. 3. ASMD blocks are linked to one another following the device's operational algorithm. Each ASMD block's output may be connected to only one input of the same or a different ASMD block. 4. When needed, the ASMD is adjusted to enhance the device's performance or area. For instance, through analysis of the algorithm loops, the ASMD is altered to reduce the number of states within the loop. 5. The FSMD Verilog code is developed directly from the ASMD chart. Variables in the Verilog code are equivalent to the device registers. Logical statements in the **if** conditions align with those in the ASMD conditional boxes. Actions depicted in ASMD blocks are presented as procedural blocks enclosed between begin...end. For Moore FSMD, the operations conducted in the respective ASMD block are specified in the state box, and subsequent states are determined by ASMD transitions. In the case  
Figure 4: The ASMD block. of Mealy FSMD, every action performed in the associated ASMD block is presented in an algorithmic description format. * The FSMD is implemented using a suitable design tool. * End. The primary distinction from traditional methods lies in combining two digital system description techniques within a single algorithm. An FSM described using ASMD is referred  
Figure 5: The ASMD-FSMD algorithm. to as a state machine with a datapath (FSMD). The ASMD-based FSMD design methodology is called the ASMD-FSMD technique. Unlike traditional designs, the FSMD is not explicitly divided into a control unit (FSM) and a datapath. Instead, it more closely aligns with a behavioral or algorithmic representation of the device's operation.