## 2 Materials and Methods
To achieve this, adjacent transistors that would otherwise be separated by dummy polysilicon are replaced with special T-shaped or L-shaped structures, as shown in Figure 5. These special structures tie dummy polysilicon to their respective VSS or VDD lines and allow the active diffusion layer to be made continuous. Early results showed that the CnRx construct can offer 30% performance benefits over traditional Single Diffusion Break (SDB) or Double Diffusion Break (DDB) designs [11]. Additionally, due to simplified masks for fabrication purposes, CnRx can also provide increases in cell density. The proposed DICE FF design in this work making use of the CnRx construct used the same interleaving layout technique that was previously described. To provide the  
Figure 4: (**a**) Simplified traditional DICE latch layout, (**b**) simplified DICE latch layout using transistor interleaving. Figure 5: (**a**) Design using double diffusion breaks for the active region of the PFETS, (**b**) design using the CnRx construct to keep the PFET diffusion continuous. Note the inclusion of the T-shape structure that allows the polysilicon to be tied to the respective VDD voltage. best possible comparison between the other designs and the CnRx DICE FF, no changes were made to either the schematic or the layout of the design other than the use of the special T-shaped and L-shaped structures to make the active diffusion layer of the PMOS transistors continuous. The guard-gate technique can be used in latch designs to help mitigate soft errors. In the guard-gate hardening technique, two input signals are compared such that the circuitry will be able to operate as normal if they are the same; in contrast, if the inputs differ, the guard gate causes the output of the circuitry to remain the same. Shown in Figure 6 is the guard gate DICE latch presented in this work. The effectiveness of transistor stacking has been proven in the 28 nm FD SOI technology node due to the isolation between transistors, and the guard gate technique takes advantage of this due to its inherent stacking structure [16]. The guard gate structure is very similar to that of a stacked transistor structure, the key differentiator between guard gating and transistor stacking being that in transistor stacking, the two series transistors share the same input. In the guard gate DICE latch, their inputs are connected to two separate nodes storing the same data. For example, if node A\({}_{1}\) currently stores a '0', then the adjacent nodes A\({}_{3}\) and A\({}_{2}\) will store a '1', thus keeping off the two PMOS transistors of the first inverter. This helps prevent a SET pulse from affecting the two series transistors simultaneously, since a pulse on one node will only affect a single transistor of a stacked inverter. The 22 nm FD SOI node is expected to follow the same SER improvement trends as the 28 nm FD SOI node when it comes to guard gating and transistor stacking. However, if both series transistors in a stacked structure are struck simultaneously by a particle with a steep incidence angle causing current pulses in both transistors, then the benefits of transistors stacking are lost. In the guard gate DICE FF design, the minimum distance between two sensitive nodes was 0.42 \(\upmu\)m.  
The three DICE FF designs, the standard interleaved DICE, CnRx DICE, and the Guard Gate DICE were fabricated on a 22 nm FD SOI test chip alongside the reference FF. The FF designs were placed into shift register chains containing 11,700 serially connected FFs and were clocked using the reverse clocking scheme. This clocking was used to help alleviate any potential issues with hold time violations or clock skew in the chains during testing. Figure 7 shows the block diagram for an implemented chain in the test chip. The nominal core voltage for this technology is 0.8 V, and the I/O voltage used was 1.8 V.  
Figure 6: Guard gate DICE latch schematic. To monitor for SEUs, a test system consisting of power supplies, a FPGA board, and a microcontroller was used.