## 1 Introduction  
Micro and nanoscale structures have improved the performance of many electronic devices such as solar cells [1; 2], light emitting diodes [3], detectors [4], and batteries [5]. Patterning the surface of planar silicon with micropillars results in broadband antireflection [6; 7; 8], enhanced light trapping [9; 10] and high carrier collection efficiency by separating the path for light absorption and carrier collection using a core-shell p-n junction and increasing the junction area [11]. At the same time, the large junction area and surface area on the pillar arrays compared to traditional planar junction silicon solar cells makes it challenging to fabricate high performance devices due to an increase in surface defects. This makes the choice of the micropillar fabrication technique very critical since it has an impact on the quality of the surface of the pillars. Micropillars can be formed using a bottom-up approach such as the metal-catalyzed Vapor-Liquid-Solid (VLS) technique or using top-down approaches such as Metal Assisted Chemical Etching (MACE) and Reactive Ion Etching (RIE), which are the most commonly used [12; 13]. Over the past few years, RIE has been used extensively for surface texturing of silicon, mainly due to its relative ease in controlling process parameters which means that good reliability and reproducibility can be obtained [14]. In the RIE process a silicon substrate is put in contact with a noble metal mask (gold or silver). The substrate is placed on a high frequency driven and dc-biased electrode [15]. After ignition of the plasma, a capacitive coupled electrode acquires a negative charge because the electron mobility is much greater than that of the ions. Glow-discharge plasma is used to generate the gas-phase etching environment, which consists of positive and negative ions, electrons, radicals, and neutrals from a feed gas (CF4). The material on the electrode is thus exposed to energetic bombardment by positive ions. At the same time chemical reactions between radicals and neutralsand the material being etched (silicon) occur at the surface and produce either volatile species or their precursors. Also, positive ions are accelerated across the plasma sheath and remove material by sputtering. The combination of the chemical activity of reactive species and sputtering can result in much higher material erosion rates in the vertical than in the lateral direction which forms the sharp edges of the pillars [16]. MACE is a wet etching technique that produces high aspect ratio semiconductor micro- and nanostructures. This technique has been used in photonic, photovoltaic, and diffusion membrane applications [17]. To fabricate micro- or nano-features using this application, metal particles or films are deposited at the silicon surface prior to chemical etching to enhance silicon dissolution. This step can be done using different techniques such as sputtering, thermal evaporation, electrochemical deposition, or electroless deposition in HF solutions [18]. Wet etching of most semiconductors occurs isotropically. This usually results in the loss of lateral resolution defined by the used mask. One of the exceptions is the use of crystal dependent wet etch. For example, the etch rate of Si (111) in KOH solution can be over two orders of magnitude slower than Si (110); therefore a Si (110) surface can be etched to produce deep trenches with (111) sidewalls [18]. Both RIE and MACE etching methods result in surface damage that affects the carrier lifetimes. Surface damage has been mitigated using various surface passivation methods that either etch away the damaged surface using material such as KOH or passivate the surface using material such as Al\({}_{2}\)O\({}_{3}\)[19], SiO\({}_{2}\)[20], or SiN [21] to passivate dangling bonds. The effect of the above approaches varies in nature and the intent of this paper is to quantify the surface damage and investigate the best passivation method that provides the highest carrier lifetime.