# Power Consumption Modeling of Discontinuous Reception for Cellular Machine Type Communications
## 6 Simulation Setup and Results Analysis
### Analytical Model Results Validation
Furthermore, Figure 6(b) shows that the wake-up latency \(d\) significantly increases for the larger values of the long cycle timer. For instance, when the long cycle timer value is raised to 2560 ms, the wake-up latency increases by 76%. Figure 8 shows the influence of distinct values of Tail time \(T_{tail}\), which is usually set by operators. It is the trade-off between the device power consumption and packet delay performance. We used \(T_{tail}\) values ranging from 0 s to 30 s in this work, according to Reference [30]. Results in Figure 7(a) show that the power-saving factor is approximately reduced by 45% when the value of \(T_{tail}\) is increased from 0 to 30 s. Similarly, the wake-up Latency also reduces for the increasing values of \(T_{tail}\), as given in Figure 7(b). For instance, when the value of \(T_{tail}\) is raised to 30 s, the wake-up latency is reduced by around 44%. This means that higher values of tail time improve the delay performances. Since a device also consumes significant power within the period of \(T_{tail}\), its value should be kept very low in order to reduce its power consumption. Figure 6: Performance analysis of the DRX mechanism for different values of \(T_{ON}\). Other parameter settings include \(\frac{1}{\lambda}=60\) s, \(T_{I}=20\) ms, \(T_{SC}=0.64\) s, \(T_{LC}=1.28\) s, \(T_{RC}=260\) ms, and \(T_{tail}=11.576\) s.  
Figure 9 depicts the influence of the short cycle timer on the performance metrics, such as the power-saving factor \(P_{S}\) and wake-up latency. Figure 8(a) shows that the \(P_{S}\) factor slightly increases for the larger values of \(T_{SC}\). However, the wake-up Latency decreases for the increasing values of \(T_{SC}\), as depicted in Figure 8(b). This is due to the fact that the device is more likely to be in the short cycle before moving to the long cycle for the increasing values of \(T_{SC}\). As a result, the wake-up latency decreases for the larger values of \(T_{SC}\). Similarly, Figure 10 shows the impact of the number of short cycles on the power-saving factor and wake-up latency. Figure 9(a) shows that the \(P_{S}\) factor decreases when the number of short cycles is increased. This is due to the fact that the device is less likely to go to the long cycle due to the greater number of short cycles. However, this improves the wake-up latency of the device when the number of short cycles is increased. Therefore, Figure 9(b) shows that the wake-up Latency reduces for the greater number of short cycles, such as 16. Figure 8: Performance analysis of the DRX mechanism for different values \(T_{tail}\). Other parameter settings include \(\frac{1}{\lambda}=60\) s, \(T_{I}=20\) ms, \(T_{ON}=40\) ms, \(T_{SC}=0.64\) s, \(T_{LC}=1.28\) s, \(T_{RC}=260\) ms.  
Figure 9: Performance analysis of the DRX mechanism for different values of \(T_{SC}\). Other parameter settings include \(\frac{1}{\lambda}=60\) s, \(T_{I}=20\) ms, \(T_{ON}=40\) ms, \(N_{SC}=16\), \(T_{LC}=1.28\) s, \(T_{RC}=260\) ms, and \(T_{tail}=11.576\) s.  
From the aforementioned results, we found that the packet inter-arrival time has the highest impact on the power-saving factor as \(P_{S}\) increases approximately by 79%. Furthermore, other DRX parameters such as the long cycle timer \(T_{LC}\) and the tail time \(T_{tail}\) also influence the \(P_{S}\) factor significantly. Similarly, the wake-up latency is mainly influenced by the packet inter=arrival time and \(T_{LC}\). Therefore, the wake-up Latency is increased by 83% and 76% when the values of packet inter=arrival time and the long cycle timer \(T_{LC}\) are increased to 3600 s and 2560 ms, respectively. Furthermore, the tail time \(T_{tail}\) affects the wake-up latency more than the on duration timer and short cycle timer.