# A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers
## 4 Test Results  
Figure 8 shows the pre-equalization test platform. The pre-equalization test platform iwas built using the laboratory's bit error tester, adjustable CTLE receiver chip, and FPGA. The NRZ data of 56 Gb/s is sent by the bit error tester, respectively, through the 50 cm and 85 cm long backplane channels, and input to the receiver chip. The external FPGA controls the adaptive algorithm to self-adjust the CTLE's degradation resistance Rs and DFE tap coefficient. As shown in Figures 9 and 10, after stabilization, the output control signals dlev are 23 and 16, respectively, and the controlled resistance values are 350 \(\Omega\) and 700 \(\Omega\), respectively.The tap coefficients of the DFE are 10 and \(-7\), respectively. Figure 11 is the test result displayed by the oscilloscope. After adjustment, you can see the obvious Doubinary signal. Channel reshaping is complete.  
Figure 8: Pre-equalization test platform.  
Figure 7: 1-tap pre-judgment DFE.  
Figure 10: dlev values.  
Figure 9: S12 parameters for channels.  
On the cadence IC software platform, the circuit was built as shown in Figure 1, the analog part adopts TSMC 28 nm technology, the DSP is generated by Verilog, and the extracted actual channel parameters are used as channel parameters for further verification. The pre-equalization results are consistent with the test results, and the second step adjustment results are as follows; Figure 12 shows the LMS algorithm for DFE and FFE coefficients at 112 Gb/s \(-\)35 dB. Due to the pre-equalization process, after the algorithm is started, the tap coefficient of FFE can be stabilized within 6 us, while the convergence speed of DFE equalization is slow and stable within 10 us. After the AMS simulation, the DSP output result is redrawn to the eye diagram. The result is shown in Figure 13. It is obvious that six open eyes can be seen, and the bit error rate of the system is 3e-9.  
Table 1 summarizes the performance of the DSP and compares it with the DSPs of other PAM4/DB-PAM4 receivers operating above 112 Gb/s. The two-step equalization method greatly reduces the equalization intensity; compared with other structures of DSP, the system has fewer taps at 112 G high-speed data and has obvious advantages in bit error rate and hardware overhead. In the 28 nm CMOS process, it can achieve performance similar to that of the advanced process. Compared with the literature [12], with the same technology, the design of digital DSP is more convenient to transplant, and the processing capability in high-loss channels is stronger. The adaptive adjustment algorithm makes the receiver more adaptable to the channel. Figure 14 shows the system layout of the digital DSP part.  
Figure 11: Eye diagram after pre-equalization.  
Figure 12: (**a**) FFE coefficients. (**b**) DFE coefficient.  
Figure 14: System layout of the DSP part.  
\begin{table}
\begin{tabular}{l c c c c c} \hline \hline
**References** & [6] & [13] & [14] & [12] & **This Work** \\ \hline Data Format & PAM4/DB-PAM4 & PAM4 & PAM4 & PAM4 & DB-PAM4 \\ Data rate(Gbps) & 112/116 & 112 & 112 & 112 & 112 \\ Technology & 7 nm & 10 nm & 7 nm & 28 nm & 28 nm \\ Rx DSP \# Taps FFE/DFE & [24-8]/1 & 16/1 & 31/1 & analog 4/0 & 16/1 \\ Max IL(dB) @112 Gb/s & \(-\)45 dB & \(-\)35 dB & \(-\)37.5 dB & \(-\)20.8 dB & \(-\)35 dB \\
112 Gb/s BER & 1.8e-10/2.8e-9 & 1e-6 & 1e-8 & 1e-11 & 3e-9 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Performance comparison.  
Figure 13: The eye diagram in 112 Gb/s \(-\)35 dB.