## 3 Typical NIST Design Methodology  
The NISTC design approach offers an open source tool set [19] that can be used either as a free C-to-RTL(i.e., C to Verilog) synthesis tool or as a tool to design embedded custom processors. To design a custom processor dedicated to a specific application, the designer should specify first a datapath and a C code, which describes the target application. The formal ADL of the tool set, which is called generic netlist representation (GNR), captures the structural details of the datapath [20; 21]. GNR describes the datapath as a netlist of components and assigns different attributes to each component. The component type can be a basic RTL component or a module, which is a hierarchical component composed of components described by another GNR module with their connections. The datapath of a NIST architecture can have several instances of each component type. A component instance should have  
Figure 5: (**a**) Minimum finder operational unit; (**b**) subtractor used in the subtraction operation of the minimum pair.  
a unique name and a type name that refers to a component description in the library. The datapath description also includes netlist connections.  
The NISTC compiler is then provided by the high-level description of the application and the GNR description of the datapath. The compiler maps the C code directly on the devised datapath and generates a finite state machine (FSM), which specifies the behavior of the datapath in each clock cycle. Then, the compiler runs netlist-constrained resource scheduling and binding techniques and later uses the FSM to generate the stream of control signals.  
Corresponding to each control signal of each component in the datapath, a field is added to the control words. The NISTC compiler produces \"0\", \"1\" or \"don't care\" values for the bits of the control words. A \"don't care\" value (denoted by \"X\") indicates that the corresponding unit is inactive at a given cycle, and its control signal can be assigned to \"0\" or \"1\" without affecting execution behavior. The structural information of the datapath is also processed (validated and completed) and then translated automatically by the tool set RTL generator into a synthesizable RTL design described in hardware description language (HDL)that is used later for simulation and synthesis.  
After simulation, synthesis and placement and routing (PAR), the accurate timing, power and area information can be extracted and used for further datapath and/or application refinement. The NISTC tool set generic design flow is shown in Figure 6. The flow enables the designer to iteratively refine and improve the results. The designer can initially start with a certain description of the application and use a specific datapath in order to execute the application and generate initial results. Later, the designer can modify iteratively the chosen application and/or the datapath and then utilize the NISTC tool set to generate new results. In each iteration, the designer can concentrate separately on one quality metric, such as implementation area, clock frequency, parallelism, power consumption, etc. Finally, the designer can choose from multiple studies the design that best fits with his or her desired requirements.