# A Manycore Vision Processor for Real-Time Smart Cameras +
## 5 Results and Analysis
### Performance Evaluation
The authors of [20] build a method to program heterogeneous MPSoCs using the Xilinx SDSoC framework. It implements an edge detection algorithm in multiple scenarios: software only, HW/SW with static and runtime task mapping/scheduling. The authors of [12] uses a 2D mesh NoC-based 16 RISC core processor to implement different image processing tasks for its parallel programming model called threaded MPI. The authors of [19] develop a high-level synthesis tool to facilitate time-to-market heterogeneous MPSoCs design, using an MPI-based programming model and Vivado tools for HLS and TCL scripting. Figure 11: Execution time for multiple algorithms with acquisition and visualization scheme. Table 5 compares our best timing performance MPSoC with related architectures for the Harris corner detector application [4]. We show in the table two results: the simulated one, with 400 tiles, and the implemented one (limited by the FPGA size), with 81 tiles. The authors of [29] utilize a Jetson (ARM and GPU) similar to this work, with a GPU instead of using programmable logic. The authors of [30] implement HCD on a ASIC SIMD architecture. The authors of [12] use an NoC-based MPSoC with 16 RISC cores assisted by an external ARM CPU. The authors of [31] build the application in a processor array using VIIW PEs and point-to-point communication, building a tightly-coupled processor array. The authors of [32; 33; 34; 35] implement pipelined HCD architectures in FPGA. The motion estimation was implemented only in the ARM processor. Its performance is independent of the manycore's performance, for the same input image. The center of mass computation and the motion estimation resulted in an average performance of only 1.43 ms. In general, non-programmable pipelined FPGA architectures have better results but lack flexibility. However, other device types can also achieve similar performance, in terms of frames per second, for ICs that can run at higher frequencies but consume more power. It is important to emphasize that this work explored the platform physical limits in the Zynq ZCU104 board and still can reduce HCD execution time for larger FPGAs. Moreover, our solution brings full flexibility with a performance close to non-programmable architectures. Reference [12] is also an NoC-based MPSoC with RISC processors, and the most similar implementation to our architecture in Table 5.  
The main goal of our architecture is to provide a feasible processing system for real-time IP/CV applications. A very popular architecture with similar utilization is a GPU, for example, the NVidia Jetson family [29]. Despite not being similar in the microarchitecture characteristics, we can compare our work to GPUs, considering the huge number of processing cores. We divided the comparison with GPUs into two parts: the first one with a soft GPU, and the second one with a commercial GPU. Our manycore was implemented as an overlay architecture, so it should be fair to compare it with an overlay GPU. In [6], the authors provide the FGPU, a general-purpose GPU optimized for FPGAs. The FGPU architecture is composed of several computing units \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Reference** & **Architecture** & **Cycles/Pixel** & **Application Agnostic?** \\ \hline
[20] 2019 * & MPSoC-FPGA & 1.06 & no \\ Our (impl.) & MPSoC-FPGA & 1.52 & yes \\
[12] 2015 & MPSoC-ASIC & 2.67 & yes \\
[19] 2019 & MPSoC-FPGA & 64.13 & yes \\ \hline \hline \end{tabular}  
* Includes the initial image transfer time.  
\end{table} 
Table 4: Comparison of implementations of Sobel edge detector.