# An Uplink Channel Estimator Using a Dedicated Instruction Set for 5G Small Cells
## 4 Design and Acceleration of Instruction Set
### Instrumentation Set Design and Acceleration Opportunities  
#### 4.3.1 Micromanipulation Decomposition and SIMD Data Parallel Instructions  
For the LS module, first of all, we can make full use of the feature that an SIMD instruction in VLIW architecture can take multiple data for instruction optimization. In order to facilitate the discussion, we first discuss the micromanipulation decomposition corresponding to pseudo code with a small degree of parallelism. Setting the parameters as described in Section 4.2, we obtain Equations (8)-(11). \[H_{i\parallel 1}=(Z1^{*}R2+Z2^{*}R1)/(2^{*}R1^{*}R2) \tag{8}\]\[H_{i2j1} =(Z1^{*}R2-Z2^{*}R1)/(2^{*}R1^{*}R2) \tag{9}\] \[H_{i1j2} =(Z3^{*}R2+Z4^{*}R1)/(2^{*}R1^{*}R2)\] (10) \[H_{i2j2} =(Z3^{*}R2-Z4^{*}R1)/(2^{*}R1^{*}R2) \tag{11}\]  
For Equations (8)-(11), the microoperations we need to carry out are as follows:  
1. calculate B = 2*R1*R2;//2 clock acceleration:clock1 times clock2 shift; including operand forwarding;
2. calculate C1 = Z1*R2 + Z2*R1, C2 = Z1*R2 - Z2*R1;
3. calculate OOX = 1/B;//numerator and denominator of real number in clock1, reciprocal by LUT in clock2, reciprocal in clock3 using multiplication; including operand forwarding;
4. calculate C3 = Z3*R2 + Z4*R1, C4 = Z3*R2 - Z4*R1;//including operand forwarding;
5. NOP //C3 & C4 need two execution cycles, inserted NOP are for result waiting;
6. calculate \(H_{i1j1}\) = C1*OOX, \(H_{i2j1}\) = C2*OOX, \(H_{i1j2}\) = C3*OOX, \(H_{i2j2}\) = C4*OOX. In normal DSP architecture, MAC-like instructions need two execution cycles, and results are not available right after the first execution cycle. Results from other instructions are available at the end of the single execution cycle thanks to the register forwarding technique. In order to eliminate the NOP inserted in step 5, we need to parallel calculate the unrelated subcarrier data in the instruction pipeline. After a plurality of subcarriers are calculated respectively in step 4, the next step in the pipeline can be calculated without inserting the NOP. Taking the Wiener filter interpolation module in the frequency domain as an example, in order to implement Equation (3) and (4), the microoperations that need to be carried out in the loop are as follows:  
1. calculate RPP = RPP++\(\beta\)/SNR*IN;//autocorrelation matrix RPP add SNR diagonal matrix;
2. calculate the reciprocal ad-bc of the determinant of RPP': [a b; c d] //including operand forwarding;
3. calculate the cofactor of RPP':[d -b;-c a];
4. calculate OOY = 1/(ad-bc)//reciprocal of real numbers; including operand forwarding;
5. calculate the inverse matrix iRPP' = OOY*[d -b;-c a];//including operand forwarding;
6. calculate W = RHP*iRPP;;//including operand forwarding;
7. calculate Hj,Uhalf[2, 4] = W1n*Hls2(i-1)[2, 4] + W2n*Hls2i[2, 4];//8 H values of non-pilot points are obtained by interpolation;
8. calculate Hj,Lhalf[2, 4] = W1n*Hls2i-1[2, 4] + W2n*Hls2i + 1[2, 4];//The other 8 H values of non-pilot points are obtained by interpolation. The above work is to decompose the algorithm module into microoperations according to pseudo code. After obtaining the micromanipulations, we need to carry out instruction subcarrier parallelism and data parallelism according to the SIMD capability of the processor. In this paper, subcarrier parallelism is to execute multisubcarrier data in parallel at the same step by an SIMD instruction. Data parallelism refers to the simultaneous processing of multidata or multisteps of data independence computation in a subcarrier by an SIMD instruction. Traditional general vector processors can only perform simple subcarrier parallel computing. The VP used in this paper can support data parallel SIMD instructions because of the use of special data channels.