## 2 Platform Architecture
### Particle Waveform Data FPGA Forward Inference Module  
The particle waveform data FPGA forward inference module is the key link for realizing the real-time identification of particle waveforms, which must have the following characteristics in order to meet task requirements: reconfigurable, portable, flexible configuration, and reasonable resource consumption and extrapolation time. Combined with the obtained fixed-point weights and bias parameters of each CNN layer, the construction process of the FPGA forward inference module for particle waveform data is shown in Figure 4.  
Figure 4: Forward inference architecture construction flowchart. To ensure the correctness of the forward inference of the FPGA-based CNN architecture, the parameters obtained from training using the Pytorch (1.0.0) architecture need to be exported and generated as fixed-point input into the FPGA to verify the correctness of the parameters; given the complexity of verification using FPGA (1.0.0), a set of forward inference models is reconstructed based on MATLAB with the function of importing and exporting the parameters, the pooling layer of the convolutional layer and the fully connected layer calculation, and the calculation results of the output layer for each type of category and final classification results. Finally, the results of the Pytorch calculations and MATLAB calculations are compared to verify the correctness of the exported parameters. Fixed-point quantization is not only a necessary step when migrating digital models from software environments to hardware implementations, especially when employing field-programmable gate arrays (FPGAs), but also provides multiple advantages [22; 23; 24]. Firstly, FPGAs have a limited number of logic cells, and fixed-point quantization helps reduce the logic resources required, enabling more compact hardware designs. Secondly, fixed-point algorithms simplify the hardware implementation of the algorithms compared to floating-point algorithms, reducing processing delays and improving the speed and efficiency of data processing. Furthermore, fixed-point algorithms are usually more energy efficient than floating-point algorithms, which is especially important for power-sensitive application areas. Through quantization, a balance between accuracy and hardware resources can be found, allowing complex algorithms to be implemented on FPGAs, which is crucial for many resource-constrained embedded systems and high-performance computing applications. The convolutional kernel, bias, and input data in this architecture are quantized using a 16-bit fixed-point quantization strategy to improve the inference speed and reduce the resource footprint. FPGA forward inference module construction at this stage typically uses platforms such as high-level synthesis language (HLS) or VITIS AI to automatically generate the model architecture into deployable hardware bitstreams using compilers and optimizers [25; 26]. This approach, despite its many advantages, is not fully applicable to satellite-borne devices. Firstly, the transparency and maintainability of the code in onboard applications are of high priority, and the code facilitates error detection, system validation, and anti-irradiation designs. Secondly, onboard resources tend to be more constrained in terms of power consumption compared to ground-based devices, which require fine optimization and the finetuning of the design at the RTL level. In addition, onboard equipment often has customized functional requirements, and designing these devices at the RTL level can better organically combine different parts in order to improve operational efficiency. Finally, it is crucial to note that most SOC or AI chips at this stage do not have anti-irradiation capabilities and thus cannot meet the requirements for in-orbit operation. Therefore, the RTL-level development of the FPGA forward inference CNN module is adopted in this architecture.