# Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications
## 5 Conclusions  
There are three main phase noise sources in all-digital frequency synthesisers: noise of reference signal, TDC and DCO. Noise induced by DCO has two components: quantisation noise and oscillator's noise. Noise induced by TDC and DCO's noise have separate dominance ranges--noise induced by TDC dominates at low frequency offsets from the carrier (in-band) and noise induced by DCO dominates at high frequency offsets from the carrier (out-of-band). Therefore, requirements of phase noise performance for frequency synthesisers can be transformed into the requirements for TDC and DCO. The structure of the all-digital frequency synthesiser for wireless transceivers for IoT and IoV applications, suitable for implementation in nanometric and submicron CMOS technologies, has to be made of TDC whose resolution has to be lower than 12 ps to ensure a lower than \(-90\) dBc/Hz in-band phase noise when the frequency of the DCO's signal is 6 GHz; DCO whose frequency tuning range is at least 1 GHz and its out-of-band phase noise is lower than \(-120\) dBc/Hz; and digital filter which enables to change the type and order of frequency synthesiser to be able to precisely control the bandwidth of the synthesiser. A wide tuning range is achieved by using multicore DCO, which is made of multiple LC tank DCO cores, decoupling stages, differential to single ended converter, tri-state buffers and frequency dividers. Such a structure is scalable and different number of cores can be used to satisfy operating frequency and tuning range requirements. However, the penalty of adding more cores is a rapidly increasing area of silicon. With partial case in 0.18 \(\upmu\)m CMOS technology, when only two DCO cores are used, the tuning range is 4.3-5.4 GHz and the phase noise is \(-116.4\) dBc/Hz and \(-134\) dBc/Hz at respectively 1 MHz and 10 MHz offset from the 5.44 GHz carrier. High resolution of TDC is achieved by using 2D Vernier TDC based on gated ring oscillators, which can measure time interval, with a lower delay than inverters. The main blocks of this TDCs are two gated ring oscillators, which are used as infinite delay lines, lap and edge counters of both oscillators, matrix of arbiters, control block and output decoder. Close to 1 ps resolution of such TDC can be achieved when it is synthesised in 65 nm and 0.13 \(\upmu\)m CMOS technologies. Digital filters made of a proportional and integral gain parts and additional IIR filters should be used in multiband synthesisers for IoT and IoV applications. If four stages of IIR filter are used, such a filter allows us to set a synthesiser to type-I or type-II and change its order from first to sixth. The proposed structure with presented blocks of frequency synthesiser allows us to achieve a synthesiser's in-band phase noise of lower than \(-100\) dBc/Hz, an out-of-band phase noise equal to \(-134.0\) dBc/Hz, allows us to set a synthesiser to type-I or type-II, and to change its order from first to sixth. All authors contributed to the present paper with the same effort in finding available literature resources, conducting both simulations and measurements, as well as writing the paper. This research was funded by the Research Council of Lithuania grant number DOTSUT-235, No. 01.2.2-LMT-K-718-01-0054 as a part of \"Design and Research of Internet of Things (IoT) Framework Model and