## 3 Study of the Communication System
### Experimental Setup
These partial correlations are additional risk factors of false-positive key locking event probability, if the few non-correlated bits were to be flipped due to the noise impact on the transmission. The 32-bit keys have exactly 0 partial correlations with 31, 30, 29, and 28 key bits, with only 14 partial correlations with 27 of 32 bits, thus greatly reducing probability of this possible error. This is not critical for BER counting purposes, but it will enhance the security of the transmission with key-coded packets that will be used in future design. At the BER-to-DMA module, simple data bus is bridged for Avalon Streaming interface [27] and passed to the DMA Write Master IP core module with the goal of sending the obtained bit count and bit error values to the SDRAM memory. Further data processing is performed by the Altera IP cores and the HPS modules which ensure interconnection in accordance with the defined settings and internal design of SoC. Finally, obtained BER data are retrieved, processed, and displayed on PC monitor by a simple custom program (written in C), running on Linux. Figure 12: BER controller schematic with main signals, omitting reset and clock. Comparing processing speed between Matlab Simulink simulation and FPGA prototype of FM-ACSC communication system, it takes about 10 h to simulate transmission of 20,000 data bits on an average PC, while on FPGA, it takes exactly 3.2768 s. That makes FPGA prototype transmission speed about 11,000 times faster, which gives a significant advantage for BER estimation on relatively high SNR values and allows us to improve the overall BER precision by significantly increasing the number of transmitted bits per SNR point. The data rate on the FPGA is constant as it is defined by the used system clock speed of 50 MHz and the chosen symbol length of 8192 samples, resulting in 6.1 kbps. Figure 13 shows FPGA resource usage summary for all main FM-ACSK modules in the form of Quartus Prime 20.1 software report. For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all its sub-entities in the hierarchy. Most resource-consuming modules are FIR filters (inside of the FM demodulator, and after it), because their performance quality correlates with the number of filter taps used in the design. Higher precision of the filtering increases the system's immunity to the channel noise, but this effect has minimal impact on the BER analysis, where SNR considers only noise that is within unfiltered signal band. Block memory is used in two application scenarios--delay lines (e.g., accumulator) and signal generation (e.g., AWGN). Using the DSP blocks is necessary when multiplication of two variable signals is required, which happens mainly in filters. Fortunately, despite the limited number of DSP blocks, Quartus can effectively reuse the same processing blocks multiple times, which is defined during late stages of compilation. Overall, resource usage would scale relatively to the chosen bit widths of data buses. This number varies within modules, but the base value at the transmitter is 14 bits, but at the receiver it is raised to 17 bits. The 14-bit bus width is chosen for compatibility with the 14-bit ADC and DAC units used in the prototype, which limits the precision of chaotic signals but is sufficient for communication system application tests. Figure 13: Resource usage summary by main modules in FPGA design of FM-ACSK prototype.