## 4 Multiple-User UWB System
With this modulation scheme, the data rate will be decreased as it takes 4 time slots to transmit 1 bit of information. However, at the cost of reduced data rate per channel, the number of particular channels used has been increased (12) to achieve simultaneous data transmission. This scheme employs 4 composite MHPs, each transmitting 12 bits of data in each time slot (e.g., symbol 1(\(S_{1}\))) which is a vast improvement over typical cases where it would take 12 time slots for transmitting individual bits of data from 12 channels. Hence, it can be said that there is a trade-off between the data rate and the number of channels. At the receiver end, there is a correlator block which is responsible for decoding the composite signals based on a set threshold value. It is followed by the logic block which matches the pattern and decides if binary 1 or 0 was transmitted from each channel. The receiver architecture with 4 orthogonal pulses is shown in Figure 4. The composite pulses are received in the order as they were transmitted. These composite pulses are sent to the correlator blocks to decode the composition of the pulses. After decoding, the decoded information is sent to the template matching block to decide if the particular channel has transmitted any information bits. Finally, the output from the template matching block is passed to the respective channels for further processing. There are 4 correlator blocks \begin{table}
\begin{tabular}{c c c c c} \hline \hline
**Channel** & **First Bit** & **Second Bit** & **Third Bit** & **Fourth Bit** & **Pattern Sequence** \\ \hline
1 & \(MHP_{0}\) & \(MHP_{1}\) & \(MHP_{2}\) & \(MHP_{3}\) & \(MHP\): 0, 1, 2, 3 \\
2 & \(MHP_{0}\) & \(MHP_{0}\) & \(MHP_{1}\) & \(MHP_{3}\) & \(MHP\): 0, 0, 1, 3 \\
4 & \(MHP_{0}\) & \(MHP_{3}\) & \(MHP_{2}\) & \(MHP_{3}\) & \(MHP\): 0, 3, 2, 3 \\
5 & \(MHP_{0}\) & \(MHP_{0}\) & \(MHP_{0}\) & \(MHP_{3}\) & \(MHP\): 0, 0, 3 \\
6 & \(MHP_{0}\) & \(MHP_{0}\) & \(MHP_{2}\) & \(MHP_{0}\) & \(MHP\): 0, 0, 2, 0 \\
7 & \(MHP_{0}\) & \(MHP_{0}\) & \(MHP_{2}\) & \(MHP_{1}\) & \(MHP\): 0, 0, 2, 1 \\
8 & \(MHP_{0}\) & \(MHP_{0}\) & \(MHP_{2}\) & \(MHP_{2}\) & \(MHP\): 0, 0, 2, 2 \\
9 & \(MHP_{0}\) & \(MHP_{0}\) & \(MHP_{3}\) & \(MHP_{3}\) & \(MHP\): 0, 0, 3, 3 \\
10 & \(MHP_{1}\) & \(MHP_{0}\) & \(MHP_{2}\) & \(MHP_{3}\) & \(MHP\): 1, 0, 2, 3 \\
11 & \(MHP_{2}\) & \(MHP_{0}\) & \(MHP_{2}\) & \(MHP_{3}\) & \(MHP\): 2, 0, 2, 3 \\
12 & \(MHP_{3}\) & \(MHP_{0}\) & \(MHP_{2}\) & \(MHP_{3}\) & \(MHP\): 3, 0, 2, 3 \\ \hline \hline \end{tabular}
\end{table} 
Table 13: Template pattern for 12 channels using 4 orthogonal pulses. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Channel** & **First Bit** & **Second Bit** & **Third Bit** & **Pattern Sequence** \\ \hline
1 & \(MHP_{0}\) & \(MHP_{1}\) & \(MHP_{2}\) & \(MHP\): 0, 1 \\
2 & \(MHP_{0}\) & \(MHP_{1}\) & \(MHP_{1}\) & \(MHP\): 0, 1, 1 \\
3 & \(MHP_{0}\) & \(MHP_{2}\) & \(MHP_{0}\) & \(MHP\): 0, 2, 0 \\
4 & \(MHP_{0}\) & \(MHP_{0}\) & \(MHP_{0}\) & \(MHP\): 0, 0, 0 \\
5 & \(MHP_{1}\) & \(MHP_{1}\) & \(MHP_{0}\) & \(MHP\): 1, 1, 0 \\
6 & \(MHP_{2}\) & \(MHP_{1}\) & \(MHP_{0}\) & \(MHP\): 2, 1, 0 \\ \hline \hline \end{tabular}
\end{table} 
Table 11: Template pattern for 2 channels using 2 orthogonal pulses. which are responsible for decoding the received pulses. Depending upon the power requirement and system complexity, the receiver architecture can be employed with either 4 correlator blocks or a single correlator block instead to decode the composite pulses in a sequential order. Doing so will enable the system to leverage the trade-off between speed and complexity of the system.