## 5 Communication Protocol Design
### PHY Layer Description
#### 5.1.4 Receiver Design  
As the DS-CDMA receiver is of significantly higher complexity than the transmitter, it is implemented in GNU Radio and run on a high-performance desktop computer connected to a USRP N210 radio front-end. The block diagram of the receiver associated with one particular PN code sequence is shown in Figure 7. Note that in a multi-node setup with four unique PN code sequences, the synchronizer, despreader and differential encoder blocks are replicated four times.  
The chip filter is an RRC filter with the same parameters as the pulse shaping filter in the transmitter. Together, the transmit and receive chip filters perform matched filtering to minimize the inter-symbol interference. The filtered samples are fed to the synchronizer block to detect the frame and obtain symbol and frame synchronization. The synchronizer block comprises a PN-matched filter, with coefficients corresponding to the first segment of the spreading sequence and a noise-adaptive peak detector. The PN-matched filter calculates the correlation value at each sample, which gives the shortest acquisition time at the expense of significant computational requirement. (Note that such rapid acquisition is essential in sensor networks, where the packed lengths tend to be short.) According to Equations (1) and (2), the PN-matched filter (correlator) output exhibits peaks when the corresponding PN spread  
\begin{table}
\begin{tabular}{l c} \hline \hline
**Component** & **Logic Utilization** \\ \hline DSSS transmitter & 1,624 (14.1\%) \\ Chip filter & 3,272 (28.4\%) \\ \hline
**Total** & **4,896 (42.5\%)** \\ \hline \hline \end{tabular}
\end{table}
Table 3: FPGA logic resource utilization of the DSSS transmit path.  
Figure 7: Simplified block diagram of the DS-CDMA receiver implemented on the USRP N210 and GNU Radio platform.  
synchronization pattern is found, but remains insensitive for patterns spread by other PN sequences, see Figure 8. The adaptive threshold logic determines the peak indexes and sets the time base for the despreader block to reconstruct the PHY payload from the spread packet.  
Figure 8: The output of the PN-matched filter in the synchronizer, showing distinct pulses at the start of five spread packet frames and insensitivity to noise and other ongoing network traffic.  
Figure 9: The amplitude (blue) and phase (red) of the integrate and dump block output for an inaccurately (**left**) and an accurately (**right**) synchronized packet.  
The despreader block is essentially a serial correlator, where the PN generator realizes a \(2^{11}-1\) long m-sequence through a linear-feedback shift register. The PN generator is reset and triggered by the synchronizer block to properly time the onset of the integrate-and-dump block, performing:  
\[I_{k}(\tau)=\int\limits_{k\,N_{p}T_{c}}^{(k+1)\,N_{p}T_{c}}r(t-\tau)\cdot\mathrm{ PN}_{i}(t)\,dt\qquad 0\leq k<K \tag{3}\]  
where \(I_{k}(\tau)\) is the integrator output for the \(k^{\mathrm{th}}\) payload symbol, \(N_{p}\) is the spreading factor, \(T_{c}\) is the chip period, \(r(t)\) is the complex chip-filtered signal, \(\mathrm{PN}_{i}(t)\) is the despreading PN sequence of the \(i^{th}\) receiver, \(\tau\) is the assumed onset of the first payload symbol and \(K\) is the number of payload symbols. Figure 9 shows that the phase of the integrator output is noise-like when inaccurately synchronized. However, in the case of accurate synchronization, its amplitude steadily builds up and its phase remains stable, allowing for proper non-coherent demodulation in the differential decoder.