# A Mayfly-Based Approach for CMOS Inverter Design with Symmetrical Switching
## 5 Results

Table 3: Lower and upper bounds for the eight design sets of Case III [25; 26; 27; 28; 29; 30; 32]. Figure 4: MA results for the seventh design set of Case I.  
Figure 5: Plot of \(C_{\rm L}\) with iterations for the seventh design set of Case I.  
Figure 6: Plot of (W/L) with iterations for the seventh design set of Case I.  
Figure 7: Plot of \(t_{\rm f}\) with iterations for the seventh design set of Case I. The MA is stochastic by its nature. Therefore, different simulation runs will give different design results. The MA has been run 50 times for the best design set of all the case studies and the resulting CF values have been utilized for the box and whisker plots. Figure 8 shows the box and whisker plot for the seventh design set of the MA; the green square represents the maximum value, the purple star represents upper whisker, the blue triangle represents median value, the red diamond represents the lower whisker, and the orange circle represents the minimum value. The median value of the CF is found to be equal to \(5.95\times 10^{-20}\), the maximum value is \(9.98\times 10^{-20}\), and the minimum value is \(2.75\times 10^{-20}\), the lower whisker is \(4.32594\times 10^{-20}\) and the upper whisker is \(7.8561\times 10^{-20}\). Table 5 shows the simulation results for each design set in case studies I. Spice simulation results show that the MA method is very accurate with small variations due to MOSFET junction capacitance. The fall time for the seventh design set of Case I using Spice simulation is shown in Figure 9. As shown in Figure 9, using the values obtained using the MA, an optimum value of the fall time equal to \(4.1925571\) ns is achieved. For Case II, the optimal CMOS inverter design with symmetrical operation (fall time equals rise time) is found using the MA for the eight different design sets in Table 2. The MA gives the optimal design parameters needed to minimize the cost function in 15. Table 6 gives the optimal design parameters needed for the CMOS inverter with a symmetrical operation for the eight design sets of Case II. It is apparent that in Table 6 the symmetry in the fall time and rise time has been achieved. Figure 8: Box and whisker plot of the MA for the seventh design set of Case I. \begin{table}
\begin{tabular}{c c c c} \hline \hline
**Set Number** & **C\({}_{\text{L}}\) (pF)** & **W/L** & **T\({}_{\text{f}}\) (ns)** \\ \hline
1.0 & 0.6610313 & 3.3 & 2.5000779 \\ \hline
2.0 & 0.6817429 & 2.3 & 2.8601715 \\ \hline
3.0 & 0.6 & 2.8 & 2.6132502 \\ \hline
4.0 & 0.7064141 & 2.5 & 3.2513576 \\ \hline
5.0 & 0.8389162 & 3.9 & 2.7435698 \\ \hline
6.0 & 0.7272609 & 2.5 & 3.4637568 \\ \hline
7.0 & 0.7122034 & 1.9 & 4.1925571 \\ \hline
8.0 & 0.8179995 & 2.4 & 4.0108611 \\ \hline \hline \end{tabular}
\end{table} 
Table 5: Spice results for Case I. In Figure 10, a plot of the objective function convergence with MA iteration for the fourth design set is shown; the objective function converges after 160 iterations. Figures 10-12 show the convergence plots of the inverter design parameters, CL, (W/L)n, and (W/L)p, for the same design set. In Figure 11, convergence is achieved after the 25 th iteration with an optimum value of 0.6085469 pF for the load capacitance. Figure 12 shows the convergence of the NMOS transistor aspect ratio for the fourth set which is equal to 2.4734372. On the other hand, the optimum value for PMOS aspect ratio is equal to 13.206141, as shown in Figure 13.