# Architecture and Process Integration Overview of 3D NAND Flash Technologies
## 3 Fabrication Methods of 3D NAND Flash
Gate electrodes and isolating films (nitride) are sequentially deposited on a Si mesa. Subsequently, an active region is formed, and the CMP process is conducted immediately without the VRAT undercut process, leading each WL to be exposed on the same plane. Subsequently, gate dielectric layers and a poly-Si layer as the channel materials are deposited, and each vertical string is separated by lithography and etching [5]. The direction of WL and BL for the VG NAND structure is changed in a channel-stacked structure for simple WL interconnection, as shown in Figure 17. An n\({}^{+}\) poly-Si BL is formed first, then n\({}^{+}\) poly-Si WLs are formed on the top of it in a crossing direction. Subsequently, p-type poly-Si multi-active layers are deposited, and n-type ion implantation is performed to form an SSL layer. After the deposition of an interlayer dielectric between the multi-active layers, an ONO stack is deposited over the active regions, and the gate is formed vertically. Thanks to the buried BLs and WLs formed at the early stage of the process flow, the interconnection to them can be easily accomplished [6]. Figure 16: Process flow of (**a**) VRAT [35], Copyright IEEE, 2008, and (**b**) a VSAT structure [5], Copyright IEEE, 2009. The DC-SF NAND flash structure utilizes a surrounding floating gate as a charge storage layer instead of a CTL, as shown in Figure 18a. Oxide and poly-Si layers are deposited first. Subsequently, a hole etch is done for channel region, and the oxide layer is recessed to form FG regions, respectively. The IPD and FG layers are deposited in order as a blocking oxide and charge storage layer, respectively, and each FG is isolated by wet etching. Lastly, a tunnel oxide and poly-Si layers are deposited in the hole channel [8]. Thanks to the FG structure, the DC-SF boasts better retention characteristics than other 3D SONOS flash architectures; however, the use of the DC-SF poly-Si gate causes several issues, including a high gate resistance, the IPD damage during the FG separation process, field confinement due to the horn-shaped FG, and GIDL during erasing due to the floating channel. In order to ease them, the MCGL process is demonstrated as shown in Figure 18b. First, oxide and nitride layers are deposited on n\({}^{+}\)/p-Si substrate. Subsequently, a channel hole is etched, and FGs for individual flash cells are formed at the recessed region after isotropic oxide etching. Then, a tunnel oxide is deposited, and a hole is etched on the Si substrate for channel contact. The poly-Si layer is filled in the channel hole and directly connected to the substrate. Following this, the nitride is removed, and the gate stack, including a high-k IPD film and a tungsten metal gate, is deposited on the FG. In this structure, the tungsten metal gate gives a low WL resistance compared to a poly-Si gate, and the bulk erase operation becomes possible thanks to the direct connection between the substrate and the poly-Si channel [11]. Figure 17: Process flow of a VG NAND structure [6], Copyright IEEE, 2009. The STAR NAND flash has a unique feature of single crystalline Si nanowire channels, and its fabrications method is described in Figure 19. Initially, Si/SiGe layers are epitaxially grown, and an active region is formed by using oxide/poly-Si/oxide layers as an etching hard mask. Subsequently, n-type and p-type ions are implanted in the left BL region and the right body region, respectively. Then, an additional oxide layer is deposited and etched as a buttress to prevent the collapse of long Si channels during the selective SiGe layer etch. After the selective SiGe etching is carried out, an oxide layer is re-deposited to fill the gap between the Si channels. Oxide patterning for the WL region is followed by isotropic etching of oxide to expose the Si channels and make a gate stack. The width of the buttress oxide (B) should be greater than the width of the oxide (A) of the channel region to be removed so that the buttress oxide can remain with the reduced width (B\(\rightarrow\)C).