# Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits--A Review
## 3 Methods of Reducing Power Consumption in CMOS Integrated Circuits
Unfortunately, it results in a technology-imposed utilization wall: only a fraction of an FPGA chip can be used at full speed within a power budget. 4. It is known that information and telecommunications technology contribute around 3% to the overall carbon footprint [65]. Thus, to contribute to the green computing, it is necessary to diminish the power consumption of digital systems. All these factors should be taken into account in the process of FPGA-based FSMs' design. To achieve this, it is necessary to have efficient methods for reducing the power consumption represented by (9)-(10). How can it be done? As follows from (9), the static power is determined by technology. It is shown in [66] that the value of \(P_{st}\) increases drastically with CMOS scaling. The higher the FPGA chip density is, the higher the value of \(P_{st}\) is. Obviously, within a certain technology, the static power consumption of VLSI-based FSM circuit could be decreased by reducing the chip area occupied by an FSM circuit. Thus, it is necessary to reduce the quantity of internal occupied resources (IORs) used by an FSM circuit. It means that it is necessary to improve methods of IOR optimization used in VLSI-based FSM design. The analysis of (10) shows that the value of \(P_{dyn}\) can be reduced by reducing the value of \(C_{par}\). This can be achieved simply by improving the semiconductor technology. Next, the reducing supply voltage \(V_{dd}\) significantly diminishes the value of \(P_{dyn}\), but it diminishes the possible operating frequency of an FSM circuit. Reducing the value of \(f_{op}\) also leads to a decrease in \(P_{dyn}\). But very often, there is a deadline for producing FSM outputs \(y_{n}\in Y\). For example, it is very important for real-time embedded systems [14; 67; 68]. An FSM is a part of some digital system including various operational blocks. The lower the operating frequency, the more time is required by a system to fulfill a specific task. The system's consumed energy depends on the time of system operation. It means that reducing the \(f_{op}\) of an FSM can increase the overall power consumption of a digital system. To control the values of \(V_{dd}\) and \(f_{op}\), various methods of dynamic voltage and frequency scaling (DVFS) can be used [3]. Also, it can be done using low-power modes. These methods belong to a group of power mode management (PMM) sometimes named dynamic power management (DPM) [69]. Thus, only a parameter whose value can be changed due to the synthesis strategy represents a switching activity. To minimize the value of \(\alpha\), various methods of state assignment can be used [70]. We discuss them a bit later. The analysis of the literature allows us to classify the known RPC methods. This classification is shown in Figure 3.  
We have divided RPC methods into two groups. The coarse-grained methods (CGMs) are the same for any block of a digital system. The fine-grained methods (FGMs) take into account specifics of a particular block. As a rule, all these methods assume the presence of some additional block providing the RPC (Figure 4). The system's RPC block executes rules of DVFS accepted in a particular digital system. It could be either the voltage scaling or clock frequency scaling or both. For example, the value of \(V_{dd}\) can be reduced for any operational or sequential block such as FSM. Also, either \(V_{dd}\) or _Clock_ could be cut off a particular block. The system's RPC can replace the \(GND\) voltage by some other voltage to reduce the values of leakage currents. Obviously, if either \(V_{dd}=0\) or \(f_{op}=0\), then \(P_{dyn}=0\). This follows from (10). From (9), diminishing the value of \(I_{leak}\) leads to reducing the value of \(P_{\text{sf}}\). This is a positive effect of DVFS. But this approach also has two negative effects [69]. Firstly, to implement the system's RPC block, it is necessary to use some IORs. Thus, this block requires an additional chip area. Also, the block consumes some power and adds to the system's latency time.