# A Review of Advanced CMOS RF Power Amplifier Architecture Trends for Low Power 5G Wireless Networks
## Advanced RF PA Architectures
### Envelope Tracking RF PA (ET/EER PA)
But in many cases, the use of a linear regulator in parallel with the highly efficient switched converter improves the bandwidth very much by means of a small efficiency penalization [22]. \begin{table}
\begin{tabular}{l l l} \hline \hline \multicolumn{1}{c}{**Regulator Type**} & \multicolumn{2}{c}{**Parameter/Comments**} \\ \hline \multirow{4}{*}{Classic linear regulator} & \(\bullet\) & Wideband (tens of megahertz); \\  & \(\bullet\) & Output voltage ripple can be neglected (mV range); \\  & \(\bullet\) & Small system efficiency at low input signal levels (\textless{}50\%); \\  & \(\bullet\) & Regulator efficiency: \textless{}60\%; \\ \hline \multirow{4}{*}{Switching regulator} & \(\bullet\) & Bandwidth is a fraction (several percent points) of switching frequency; \\  & \(\bullet\) & Large output voltage ripple (tens of mV range); \\  & \(\bullet\) & Large efficiency at low input signal levels (\textgreater{}70\%); \\  & \(\bullet\) & Regulator efficiency: \textgreater{}90\%; \\ \hline \multirow{4}{*}{Parallel combined linear and switching regulator} & \(\bullet\) & Switching regulator provides average power; \\  & \(\bullet\) & LDO supplies the residual power and acts as an active filter; \\  & \(\bullet\) & Regulator efficiency: 70–90\%; \\ \hline \multirow{4}{*}{Series combined linear and switching regulator} & \(\bullet\) & Medium output voltage ripple. Larger than that of the linear, but smaller than that of switching. At high switching regulator frequencies (when the wireless signal has a wide bandwidth) voltage ripples increase (due to the reduction of LDO PSRR); \\  & \(\bullet\) & Regulator efficiency: 60–80\% (higher than that of classic linear regulator); \\ \hline \multirow{4}{*}{Adaptive PA bias} & \(\bullet\) & No bandwidth restrictions; \\  & \(\bullet\) & No undesired output ripples; \\  & \(\bullet\) & Overall efficiency can be increased at lower input power levels up to 5\%; \\ \hline \multirow{4}{*}{Adaptive (multimode) PA supply} & \(\bullet\) & Requires high current low loss switches to connect different supply rails to the RF choke and a smoothing LFP to reduce noise; \\  & \(\bullet\) & No bandwidth restrictions; \\  & \(\bullet\) & Output voltage ripple is present during RF choke supply rail change leading to challenges in maintaining fluent switching transition; \\  & \(\bullet\) & Multimode regulator efficiency can reach 97\%; \\  & \(\bullet\) & Overall efficiency can be increased by 5–6\%. \\ \hline \hline \end{tabular}
\end{table} 
Table 1: Envelope tracking (ET) regulator architecture type comparison. ET/EER architecture advantages:  
1. Various envelope detection methods. Envelope detection can be implemented in the analog domain alongside ET/EER or using a digital signal processor (DSP) alongside a polar PA architecture;
2. High PAE improvement possibilities. Utilizing ET/EER architecture can lead to an overall PAE improvement by up to 20% compared to that of the traditional PA;
3. A choice of different architecture variations. Linear, switching and their combinations as well as adaptive biasing techniques are at the disposal of the designer;
4. Linearization possible but difficult as the nonlinearities of other system components such as the regulator have to be accounted for. ET/EER architecture disadvantages:  
1. High synchronization precision between the PA and the regulator requirements. The regulator and the RF path have to be phase matched as the supply voltage must follow the envelope for maximum efficiency;
2. Additional noise in the supply rail due to a switching regulator;
3. Narrow bandwidth. Bandwidth primarily restricted by the regulator therefore is not suitable for multi-standard solutions and is not reported to be higher than 40 MHz;
4. Complex implementation. The architecture requires high power regulators with precise controls;
5. No possibility of full integration in a single application-specific integrated circuit (ASIC). The main reason is the large high current inductor present at the output of the switching regulator.