## 4 Hardware Design
### Design Analysis  
To estimate the complexity of the design, we have estimated the area and power consumption of the main blocks as detailed in Table 3.  
As it can be seen, the QR decomposition block consumes the largest area of the design. This is because for \(8\times 8\) decomposition 26 processing elements and 8 delay units were used. As mentioned previously, the decision was made to simplify the design by converting the inputs from complex to real. However, if QR decomposition for \(4\times 4\) matrix would be used, this could save up around 25% of the area consumed by the QR block. Unfortunately, this optimization in the QR block would lead to more area overhead in other parts of the design including the matrix multiplication and inverting blocks as well as normal embedded multipliers used in other blocks. As a result, it has been concluded that \(8\times 8\) QR decomposition is necessary and this cost of area is actually the best option. Other modules that take up a significant area in the design are the K-best and ELR blocks. Then concerning the power, the QR block consumes the most power due its size and complexity. Additionally, the ELR and K-best blocks consume a reasonable chunk of the power due to similar reasons. However, it is noticeable that the'scale and shift' and the'shift and scale' blocks consume power at the same level as the ELR and  
\begin{table}
\begin{tabular}{c c c c} \hline \hline
**Block** & **Area (\(\mathbf{\mu m^{2}}\))** & **Dynamic Power** & **Leakage Power** \\ \hline QR Decomposition & 1526.958 & 16.1716 mW & 1.9799 W \\ \hline Complex to Real & 6.112 & 2.7862 uW & 14.5767 mW \\ \hline Matrix Transpose & 4.479 & 5.8194 uW & 11.7656 mW \\ \hline Matrix Inverse & 39.675 & 638.8223 uW & 63.3990 mW \\ \hline Matrix Multiplication & 28.458 & 634.2357 uW & 48.2523 mW \\ \hline ELR & 146.725 & 1.1203 mW & 272.7617 mW \\ \hline K-Best & 55.702 & 634.9234 uW & 114.3604 mW \\ \hline Scale and Shift & 3.171 & 550.4507 uW & 6.0161 mW \\ \hline Shift and Scale & 23.867 & 1.0652 mW & 35.0875 mW \\ \hline Select Minimum & 0.354 & 60.7517 uW & 367.1118 uW \\ \hline Real to Complex & 0.552 & 748.5910 nW & 1.4709 uW \\ \hline \hline \end{tabular}
\end{table}
Table 3: Area and Power Analysis for Proposed Decoder using 32 nm CMOS Technology at 100 MHz.  
K-best blocks. This is due to the use of many multipliers and shifters in order to carry out the desired operations in those blocks.  
Finally, Area and power costs are estimated for both the proposed detector and for a conventional K-Best design [17], where we summarise the overall results in Table 4. In Table 4, we have included the attainable BER achieved at a SNR=30 dB, while we have shown previously that the ELR-aided detector requires lower SNR to attain any BER compared to the detector dispensing with ELR. Hence, the results in Table 4 can be extended to any SNR to show that at any SNR the ELR-aided detector attains a lower BER. This can be extended as follows: given a target BER, the ELR-aided detector will require lower SNR to attain the target BER and hence a lower transmit power compare with the detector not using the ELR. The results indicates that the proposed design incurs 20% more area and consumes 18% more power compared to the conventional design dispensing with ELR, but this may be a small price to pay given the significant increase in the BER performance described in Section 3.