# Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications
## 3 Results  
The performance results for the flexible convolver are presented in this section. The proposed method was validated by implementing different representative convolution layer configurations of state-of-the-art CNNs. For its hardware implementation, the convolution filters' coefficients were generated in Matlab using random numbers. Subsequently, these coefficients were converted to their 8-bit fixed-point representation in the decimal part since this represents a trustworthy standard for its implementation in FPGAs [50]. Arbitrary images with pixel values normalized to the range [0,1] were used as convolver input data. The convolver output data were compared with those obtained through software processing (Matlab) to validate correctness. It should be noted that the employed validation method is a convolver performance evaluation taking into account processing time, number of operations per second, and power consumption. Nonetheless, the proposed method does not lose generality to be applied to different convolution layer configurations; the system, in fact, is intended to be applied to configurations (config) such as those shown in Table 1.  
The achievable processing time by the proposed architecture is defined by Equation (5), where \(T\) is the period of the clock signal and \(C_{conv}\) is the required clock cycles to perform either a shift in the PLB or a multiply-accumulate operation in the SA. Due to the nature of the processing, \(nn=1\), thus operation parallelism is not exploited. Instead, hardware resources (multipliers) are intended for filter and data parallelism. In addition, the intra-output parallelism (\(n_{fi}\)) was set to the minimum value. Figure 5: Flexible SA block diagram for convolution with filter sizes of \(3\times 3\) and \(5\times 5\). \[Pt=T\times C_{conv}\times[((w^{2}+n_{fo}+nv)\times\frac{(N_{out})^{2}}{nv}+nv) \times\frac{K}{n_{fo}}\times\frac{CH}{n_{fi}}] \tag{5}\]  
It should be noted that Equation (5) only considers the processing time for convolutions on valid masks. Additionally, the time needed to shift data in the PLB (dead time) in order to generate valid masks must be considered. The number of cycles required by design to generate a not valid mask is defined as:  
\[Lat_{buffer}=\underbrace{N_{in}^{(l)}\times(w-1)+w}_{\text{initial latency}}+ \underbrace{((N_{in}^{(l)})^{2}-(N_{out}^{(l)})^{2})}_{\text{invalid mask latency}} \tag{6}\]  
The initial latency represents the necessary clock cycles to generate a valid mask from the first value read from the input memory. The invalid mask latency is produced by the parameter \(S\); thus, the greater the value of \(S\), the greater the dead time. Table 2 shows the processing time calculated with Equations (5) and (6) for the convolutional layers configurations shown in Table 1. Additionally, the processing time for the convolutional layers of CNNs taken as test cases in previous studies [22] is shown. These are one-, two-, and three-convolution layers of naive CNNs trained for classification tasks under the MNIST [51] dataset. Information regarding the processing time of a modified CNN Alexnet has also been included. It has the characteristic of operating with input image dimensions of \(67\times 67\times 3\) and being trained with the CALTECH101 dataset [52]. For each CNN, the processing time required to process all the convolution layers is shown. Note that overall time processing corresponds, in fact, to all the layers of the convnets, not only to those shown in the table. This provides an estimation of the attainable processing time for each CNN. The fourth column reports the processing time obtained in hardware. The difference in time is due to overhead processing that is related to the control logic.