# Real-Time Simulator for Dynamic Systems on FPGA
## 2 Related Work
The results indicate that the proposed HIL methodology provides a practical and cost-efficient verification of controller performance, accelerating development and reducing risks associated with designing new PFC converters. Additionally, ref. [34] presents a high-performance and cost-effective FPGA-based motor drive emulator. The emulator is designed to replicate the dynamic behavior of permanent magnet synchronous machines (PMSMs), including the voltage source inverter and control strategy, using a digital description in Verilog. The study explores two design methods, parallel and sequential, to optimize FPGA resource usage, resulting in a solution that accurately emulates motor behavior while saving resources and costs. The results show that the emulator is efficient for many applications, from developing new control strategies to early fault detection and maintaining the portability and flexibility of FPGA platforms. Furthermore, ref. [25] presents a universal equivalent model for real-time CPU/FPGA co-simulation applied to hybrid cascaded multilevel converters. The study focuses on creating a model that can be used for simulating complex power converters, combining CPU processing with the parallelism capabilities of FPGAs. The proposed model was validated through real-time simulations, demonstrating its effectiveness in improving the accuracy and efficiency of co-simulation systems, particularly in power electronics applications that require high temporal resolution and computational performance. The research presented in [35] provides an overview of interface algorithms, communication signals, and delay management in real-time co-simulation of distributed power systems. The study addresses the challenges of maintaining stability and accuracy in geographically distributed simulations, where communication latency between simulators can compromise results. The authors review various interface techniques and discuss methods to mitigate the effects of communication delays, ensuring that distributed simulators remain synchronized and stable, thereby improving the fidelity of simulations in complex power systems. Complementing this discussion, ref. [24] address the automatic transformation of SIMULINK models into FPGA-in-the-Loop (FiL) systems for real-time simulation, identifying the main challenges in the C-to-HDL code synthesis process and proposing a detailed roadmap to overcome them. The research demonstrates, step by step, how to convert SIMULINK models into FiL systems using tools like Vitis HLS and Vivado, validating the resulting FiL system to ensure its real-time functionality. This approach offers a practical solution for engineers seeking to automate the design process of FiL systems, facilitating the development of digital twins and other high-performance industrial applications. Table 1 compares the proposed methodology with recent studies on real-time simulations using FPGAs and other platforms. The criteria selected for comparison include the platform used, the simulation methods employed, the precision achieved, the cost, the flexibility and applicability, the real-time efficiency, and the type of dynamic system simulated. These criteria were chosen because they are the most relevant for evaluating the performance and innovation of the proposed methods. Table 1 shows that besides offering simulation precision and reduced cost, the approach presented in this paper stands out for its flexibility and applicability to a wide range of dynamic systems. Compared to the studies analyzed, the proposed methodology achieves comparable or superior precision, providing a versatile platform that can be applied in different contexts, from electrical to mechanical systems. This reflects the contributions of this work to the field, offering an efficient solution for real-time simulations adaptable to various needs and applications. The studies presented above are individually focused, in that they are aimed at specific energy or automotive applications.