# PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA
## 3 Proposed P4-Programmable Parser
### Software Overview
#### 3.1.2 P4 Compiled JSON File
Consequently, each bit in the enable vector has two corresponding bits in the select vector. ```
Input: J: The compiled P4 JSON file, B: The desired bus size, S: The desired multiplexers size Output:MemCode: Memory configuration code
1 Initialization:
2\(G\leftarrow\) Create an empty DAG
3\(ProtocolBitmap\leftarrow\) Create an empty array
4\(ProtocolMask\leftarrow\) Create an empty array
5\(Matchvalues\leftarrow\) Create an empty array
6\(NextState\leftarrow\) Create an empty array
7\(MaxSelect\leftarrow\) Create an empty array
8\(EnableSignals\leftarrow\) Create an empty array
9\(NextStateBitmap\leftarrow\) Create an empty array
10\(MemCode\leftarrow\) Create an empty array
11\(HeaderInfo\leftarrow\) parseJSON(J)
12 foreach\(parseObj\) in \(J.get('parsers')\)do
13\(header\leftarrow\) parseObj.name
14\(G.\)addNode(header)
15\(G.\)addData(HeaderInfo.get(header))
16 foreach\(transition\) in \(parseObj.get('transitions')\)do
17\(G.\)addEdge(G.currentNode, transition.nextState, transition.value)
18\(paths\leftarrow\) DFS(\(G\))
19\(reducedPaths\leftarrow\) removeUnosedPaths(\(paths\))
20 foreach\(path\) in \(reducedPaths\)do
21 foreach\(header\) in \(path\)do
22\(ProtocolBitmap.\)append(getProtocolBitmap(header, HeaderInfo.get(header)))
23\(ProtocolMask.\)append(getProtocolMask(header, HeaderInfo.get(header)))
24\(Matchvalues.\)append(getMatchvalues(header, HeaderInfo.get(header)))
25\(NextState.\)append(getNextState(header, HeaderInfo.get(header)))
26\(MUXSelect.\)append(getMultiplexerSelect(header, HeaderInfo.get(header), B, S))
27\(EnableSignals.\)append(getEnableSignals(header, HeaderInfo.get(header), B, S))
28\(NextStateBitmap.\)append(getNextStateBitmap(header, HeaderInfo.get(header)))
29\(MemCode\leftarrow\) createMemContent(ProtocolBitmap, ProtocolMask, Matchvalues, NextState, MuxSelect, EnableSignals, NextStateBitmap, B) return\(MemCode\)
```

**Algorithm 1**Configuration and control extraction algorithm. A key feature of the software component is its ability to support dynamic adaptability. It can handle real-time updates to P4 configurations, enabling the hardware to adapt to new parsing requirements on the fly. This adaptability is achieved through efficient data transfer mechanisms and a flexible hardware design. ### Hardware Design Overview

The core of the packet parser presented in this study is conceptualized as a DAG, where each node symbolizes a protocol, and the edges denote transitions between protocols. It functions as an abstract state machine (ASM), systematically evaluating state transitions at each node within the parser. The states that link the initial state to the terminal state in the ASM delineate the set of protocols supported by the P4 parsing graph. This design introduces a _base block_ capable of reuse to accommodate larger bus sizes and higher data throughputs. The base design architecture is a streaming packet parser that operates without needing packet storage, explicitly tailored for 64-bit bus sizes. This bus size is strategically chosen to comply with byte-aligned network protocols and ensure reliable header key alignment, thereby preventing any header key from being split across two incoming data chunks. This careful balance in bus size selection avoids the complications of an overly intricate design while preventing excessive demands on software computations and hardware resources. This approach results in a highly flexible and scalable hardware design that can efficiently handle current demands and adapt to future network protocol developments. Base Block Architecture and Microarchitecture

The base block, shown in Figure 3, is designed to support a 64-bit bus size with a maximum possible clock frequency to handle a data throughput of more than 10 Gbps efficiently. This throughput is commonly used in high-speed networks and ensures the design can meet industry-standard performance requirements while consuming a minimal area footprint. Table 1 compares the proposed design with previous programmable packet parsers using the same bus size.