## 4 Results and Discussion
The datapath width and the number of cycles for LED, PHOTON, and the AE are the same for all FPGA devices. However, the performance of the individual implementation of LED, PHOTON, and AE varies from one FPGA device to another. The individual design of LED achieves 208.72 MHz to 265.46 MHz, and PHOTON achieves 321.44 MHz to 368.32 MHz, depending on the type of FPGA device. When LED and PHOTON are merged without sharing the logic resources, the maximum frequency of PHOTON is cut off at the lower frequency of the LED. On the other hand, the proposed authenticated encryption achieves 140.39 MHz to 176.87 MHz for the same FPGA devices as the single designs. The proposed AE has a slightly lower maximum allowable frequency in comparison to the individual designs of LED and PHOTON. However, the degradation in performance is quite reasonable compared to the reduction in logic resource usage that is accomplished. As the logic area utilization is mostly proportional to the power consumption, the reduction in the logic resources also improves the power consumption. For the individual designs of LED and PHOTON, the total power consumption for both ranges from 130.98 mW to 292.66 mW, whereas the power consumption of the proposed architecture ranges from 89.73 mW to 217.51 mW, depending on the FPGA device of the Cyclone family. Therefore, the power consumption was reduced by a minimum of 19.65% and a maximum of 46.04% based on the FPGA device, as shown in Table 3.  
A comparison of the related work with the proposed work is provided in Table 4. The work detailed in [33] implemented an authenticated encryption on Stratix 4 FPGA and other devices from the Virtex family with the goal of reducing the logic area and achieving high speeds. They used an AES block cipher with an offset two-round (OTR) method, comprising an authenticated encryption. The authors were able to reduce the logic area by almost half compared to the original design. However, since they had to keep the speed in gigabits, the architecture still utilizes a large area compared to the proposed lightweight authenticated encryption. [PERSON] et al. [40] introduced CiliPadi lightweight authenticated encryption, and the first design was submitted to the first round of the US NIST project. Their design was implemented on the Virtex 6 Xilinx FPGA device. They achieved higher frequencies compared to our work and the benchmarked work, but their most lightweight design (CiliPadi-Mild) still consumes more logic resources, even in comparison to their benchmarked proposals [42; 43]. The authors of [21] aimed to design an authenticated encryption architecture and reuse the datapath functions by integrating an LED block cipher with the PHOTON hash function. They performed design space exploration for the LED and PHOTON resources and reported their results in logic slices. They were able to achieve an 8.6% reduction in logic resource utilization. The authors of [10] constructed an authenticated encryption by composing a PRESENT block cipher and a SPONGENT hash function with the goal of reusing the common datapath blocks. The design of the SPONGENT architecture was inherited from the sponge construction with the permutation function instantiated from the PRESENT block cipher. The authors of [10] reported their results in Gate Equivalent (GE) and were able to reduce the logic resources by 27% compared to the individual architectures of both primitives. However, the performance of their composite authenticated encryption was degraded. There are always tradeoffs between security, cost, and architecture design, where improving one of them can result in compromising one or both of the others. The architecture design in this paper was optimized to reduce the utilization of logic resources. Nevertheless, the performance results are still quite acceptable.