## 4 Simulations and Measurements  
The circuit was simulated by Advanced Design System (ADS) and Virtuoso System Design Platform. In addition, Ansys HFSS simulates all passive structures. The chip was fabricated in 130 nm SiGe BiCMOS process, offered by STMicroelectronics. High -peed HBT (heterojunction bipolar transistor) in process library was adopted for Q1 and Q2 in Figure 9a, and Q3 in Figure 10. NMOS transistor in process library was adopted for M1 in Figure 10. The specific dimensions are shown in Table 1. The SiGe BiCMOS process provided four thin metal layers and two thick metal layers. All capacitors were MOM (metal-oxide-metal) capacitors, using metal layers to form finger structures. All resistors were poly resistors offered by process library. Other passive components, such as inductors, transformers, etc., were designed by thick metal layers, and simulated by Ansys HFSS. Figure 14 presents the microphotographs of the proposed high-linearity and wide IF bandwidth down-conversion active mixer's chip with a size of 0.69 mm \(\times\) 0.69 mm including all pads, using a 130 nm SiGe BiCMOS process. The DC pads were bonded out, VDD were 1.6 V, the total current were 12.4 mA, and the total DC power consumption were 19.8 mW. The measurement results show that the circuit is not sensitive to bias changes. Figure 14: Chip photograph of the proposed mixer with a chip size of 0.69 \(\times\) 0.69 mm\({}^{2}\) including pads. Figure 13: The impedance changes with R1 and R2 at the IF. Except for the IF port, all measurements, including S-parameters, conversion gain, linearity, and isolation, were performed using on-chip probing. The instruments connection is shown in Figure 15a; the RF and LO ports are connected through GSG probes, and the IF output port is connected to the PCB board through bonding wires and then to the SMA interface through the transmission lines for testing, as shown in Figure 15b; the loss of transmission line has been calibrated. A four-channel vector network analyzer with a working frequency up to 67 GHz was used for the three-port measurement of the mixer, and a spectrum analyzer for noise measurement. A 100 kHz to 50 GHz pre-amplifier was used for linearity measurements to amplify the input RF signal because the design has an ultra-high IP1 dB. In order to obtain general performance, a room temperature of 27 \({}^{\circ}\)C was set for measurement [24]. The simulation and measurement results of the reflection coefficient of the RF port are shown in Figure 16a. The result indicates that the S\({}_{11}\) is less than \(-10\) dB in the required operating frequency band of 24-30 GHz, and the bandwidth is much larger than needed. Similarly, Figure 16b shows the simulation and measurement results of the reflection coefficient of the LO port. In the range of 16\(\sim\)24 GHz, the S\({}_{22}\) is less than \(-10\) dB. Due to the application requirements of ultra-wideband for the IF port, a Marchand balun is used to achieve an IF range of 3\(\sim\)11 GHz; as shown in Figure 16c, in the entire IF band, the S\({}_{33}\) is less than \(-5\) dB. The results show that the return loss of each port is within an acceptable range, which meets the general system requirements. Figure 16d features the measured conversion gain versus local oscillator power at the LO frequency of 20 GHz, the RF frequency of 27 GHz, and the IF frequency of 7 GHz. The reason for choosing this group of frequencies is because they are in the center of the operating frequency band and are representative. When the LO power increases to a certain level, the CG no longer has an obvious enhancement, and the LO has reached the optimal driving state. In order to obtain the best conversion gain and linearity performance, we chose a fixed local oscillator power of +2 dBm to complete all measurements. Figure 15: (**a**) Block diagrams of measurement setups, and (**b**) micrograph of the PCB board for bonding. Table 2 illustrates the measured conversion gain versus RF frequency.