# Reliability Prediction of Mixed-Signal Module Based on Multi-Stress Field Failure Mechanisms
## 6 Reliability Prediction of the Communication Module Under the Mission Profile
### Key Component Performance Degradation Reliability Prediction  
Based on the results of the mixed-signal multi-stress field simulation under the spacecraft mission profile, the reliability prediction of key components is carried out by constructing a Physics of Failure model to consider performance degradation. The analysis focuses on the FPGA and SRAM. Since the degradation and failure processes of these two components are similar, this section mainly considers the reliability prediction of the FPGA with regard to the impact of NBTI (Negative Bias Temperature Instability). In the reliability prediction of the FPGA, the primary consideration is the impact of NBTI effects. Under the influence of NBTI, the threshold voltage of the PMOS in the FPGA gradually increases over time. On the one hand, the delay of the gate circuit increases as the threshold voltage increases. For the FPGA, an increase in delay can lead to timing issues during operation, causing the communication module to malfunction. On the other hand, as the threshold voltage increases, the PMOS in the FPGA becomes more difficult to turn on. If the threshold voltage exceeds the gate voltage of the PMOS, it will prevent the PMOS from turning on, which can also prevent the communication module from functioning properly. To simulate the impact of FPGA delay degradation, the communication module simulation test circuit model shown in Figure 11 is used. The simulation results are used to identify the primary failure mode of the FPGA. The simulation time is controlled to adjust the rate of change in the FPGA's delay, ensuring that the threshold voltage remains lower than the gate voltage during the simulation process. The simulation results are shown in Figure 20. From the figure, it can be observed that the telemetry data returned by the FPGA contain the expected data, indicating that the communication module continues to operate normally at this stage. It is assumed that the failure of the PMOS is the primary cause of FPGA failure. The analysis focuses on PMOS failure due to the increase in the threshold voltage. The gate voltage of the FPGA can be considered equal to the core voltage of the FPGA, which is 1.2 V. Therefore, 1.2 V is set as the failure threshold for the threshold voltage. Based on this threshold, the lifetime and reliability of the PMOS are calculated using the NBTI failure physical model. To analyze the long-term degradation process of the threshold voltage, the long-term NBTI degradation model from the multi-stress field Physics of Failure model is used. The specific model is as follows:  
\[\Delta V_{\text{th}}=\Bigg{(}\frac{\sqrt{K_{\text{e}}^{2}\pi T_{\text{clk}  
Based on the reference [37], Table 5 summarizes the parameters used in the spacecraft's long-term NBTI degradation model. Based on the long-term NBTI degradation model, to calculate the threshold voltage degradation curve, it is necessary to obtain the gate voltage \(V_{\text{gs}}\), initial threshold voltage \(V\)th, and temperature \(T\) for the PMOS. The gate voltage is assumed to be 1.2 V, the initial threshold voltage is assumed to be 0.45 V, and the temperature \(T\) is approximated as the FPGA chip temperature, which is 26.7643 \({}^{\circ}\)C. Additionally, from the FPGA signal activity statistics in Section 4.2, it is determined that \(\alpha\cdot T_{\text{clk}}\) is approximately 0.14, and \((1-\alpha)\cdot T_{\text{clk}}\) has an average value of approximately 0.78. Once all the parameters are determined, the long-term NBTI model is solved for calculation. Since the gate oxide thickness \(t_{\text{ox}}\) of the PMOS may fluctuate in practice, it is assumed to follow a normal distribution, \(t_{\text{ox}}\)-N(2.6,0.05). According to the FPGA resource usage in Table 2, the FPGA design uses 2458 basic logic units. It is estimated that each basic logic unit contains approximately 50 PMOS transistors, which means the FPGA design uses about 122,900 PMOS transistors. The next step is to calculate the threshold voltage degradation of these PMOS transistors.