# A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits
## 4 Effect of Process, Voltage and Temperature (PVT) in SDD and HDD Testing  
The first major challenge in detecting SDDs and HDDs is testing them in the presence of delay variation due to PVT. It is difficult to differentiate whether the delay is due to the defect or it is due to the process variations, crosstalk, etc. The chip must not be declared defective if the delay is due to process variation. Various works are available in the literature addressing this issue. In [18], the delay due to SDD is differentiated from the delay due to process variation by comparing the delay difference between the inter-correlated paths. If the delay of one path changes and that of the correlated path does not change, it can be concluded that the delay is due to the small delay fault. The inter-path correlation is estimated using process variations, spatial correlation, and structural correlation. But the disadvantage of this method is that it focuses mainly on critical paths. The studies in [19; 20]  
Figure 5: (**a**) Delay of each path of the circuit through fault site X and the observation time T1 and T2 for detecting the small delay; (**b**) Delay of the path through the fault site X and the observation time T1 to detect the hidden delay.  
are commonly referenced for the characterization of detectable delay defects as one with a probability of detection of at least 50% in the presence of process variability. Here the path delay is regarded as a gaussian distribution with a mean \(\mu\) and variance \(\sigma\). It is mentioned that the delay defect in the presence of process variation is detectable if the added delay due to the defect is beyond the 3\(\sigma\) of the fault-free path delay distribution. This concludes the smallest delay defect size that can be detected in the presence of process variation. In [21], the effect of crosstalk and process variation is studied to detect SDDs and HDDs in the presence of these effects. The crosstalk analysis using HSPICE shows that the transition speeds up in the presence of crosstalk when the neighbouring paths have a transition in the same direction and slows down when the transition is in the opposite direction. The process variation effects are studied by using Monte Carlo simulation and modeling. Here the path delay is considered as a gaussian delay distribution. These effects are considered for pattern selection for SDD testing, which is discussed in detail in the Section 6.2. Still, this is more time-consuming and complex because of the Monte Carlo simulation for different process variations and the extraction of coupling capacitance from the layout. Also, the effect of temperature must be considered during the SDD detection because the increase in temperature increases the propagation delay in MOSFET circuit and decreases in FinFET circuits [22]. Hence during the pattern generation, this effect must be addressed. Moreover, the supply voltage variations at the power supply node can be caused due to the excessive switching activity caused by the patterns. This, in turn, affects the delay in the paths of the circuit. Hence this effect of the patterns must also be considered [23]. Addressing all the above mentioned problems during the testing of SDDs and HDDs is essential as this affects the testing accuracy.