# DFT-Low-Latency Bit-Slice Design of Discrete Fourier Transform
## 8 Discussions and Conclusions  
Hardware solutions of DFT approaches are useful for real-time and high-speed processing applications. Theoretical concepts equal to DFT software procedures are the basis of HW designs, but implementations differ in the approach. SW procedures are described using standard programming languages and generally have a serial organization fashion. Instead, HW implementations of DFT are usually conceived to develop operating tasks with some degree of parallelism and by adopting a pipeline methodology. In this paper, a novel, dedicated implementation of the DFT calculation chain is proposed. Input sequence samples are split into bit slices, and each bit slice is Fourier transformed, independently. A simplification in the computational complexity is achieved because only complex sums are required instead of complex multiplies. The method was first developed in the Matlab(r) environment for debugging purpose, and then the hardware implementation was validated on an FPGA device. The authors designed the conceived system using an algorithm-to-hardware compiler tool chain and characterized the hardware using the DE2-115 development board by Terasic. The main contributions of our paper are:  
* Processes on different DFT slices can be carried out in parallel by different circuits with equal hardware structure;
* The implemented architecture is free of multipliers, and the DFT composition of BFT slices can be accomplished by left-bit shifts of the obtained results;
* The DFT of each bit slice introduces some approximations due to the twiddle factor precision: stated \(L\), the number of bits used to describe twiddle factors, and \(b\), the number of bits of the input sequence. The output Fourier-transformed coefficient can be described, at most, by \(L+N+b-1\) bits, with \(N\) being the number of sample points and, consequently, the number of sums needed to compute the BFT coefficient; the \(b\) bits are more used to sum the bit slices after proper power of two shifts to compute the \(X_{k}\) Fourier coefficients. * Full precision can be accomplished in the DFT computation if no approximation is carried out at each computation step. The number of bits describing the DFT coefficients can be \(L+N+b-1\), after the recomposition of BFT slices into the DFT. In this case, the final approximation in DFT computation is limited by the number of bits used to describe the twiddle factors and a possible final truncation of the output coefficients;
* A simplification step can be implemented in each DFT slice due to the symmetry inherently present on twiddle factors;
* The algorithm needs \(N\) complex sums for the final DFT composition from BFTs and \(b\cdot N^{2}\) complex sums for the computation of all the \(b\) BFT slices in the worst case (that is when no complexity-reduction step is carried out). If bits are assumed equal in probability of occurrence, \(N\cdot(bN+1)/2\) sums are necessary to obtain the DFT because only terms corresponding to ones are summed up. This value may decrease if complexity reduction occurs;
* A high-accuracy solution was designed. A SQNR above 109 dB is obtained, if compared with the MATLAB double-precision floating-point calculations for a pure sinusoid, and above 120 dB for a low-pass signal. * A very low latency implementation of the 1024 points DFT calculation: a two-clock step value is obtained with a clock of \(1 ns\). * The proposed architecture occupies only a small percentage of the total area of the Cyclone IV FPGA (about 1%). It follows that a higher parallelism could be implemented by replicating processing blocks to reduce the latency. **Author Contributions:** Conceptualization, C.G. ; methodology, C.G. ; software, A.G.; validation, A.G., M.R. and C.G. ; formal analysis, C.G., M.R. and A.G.; investigation, M.R. ; data curation, M.R. ; writing--original draft preparation, C.G. ; writing--review and editing, M.R. ; supervision, C.G. and M.R. ; funding acquisition, C.G. All authors have read and agreed to the published version of the manuscript.