## 4 Adopted Design Flow
### FPGA Implementation Level  
At the FPGA implementation level, Xilinx ISE tool suite is used to implement the designed architectures. For each architecture design, the HDL generated by NISTC tool set describing the \(EquaNisc/DemaNlSC\) module is imported into a new Xilinx ISE project. Furthermore, the simple architecture of the control unit, which is required to load the control words from control memory to the functional module, is provided in HDL. The Xilinx project is assumed to integrate the functional module (\(EquaNisc/DemaNlSC\)), the control unit and the input memory blocks. The only missing elements, at this level, are the synthesizable memories. IP synchronous block memories of suitable parameters (type, depth, width) are generated by means of the Xilinx Core Generator. Block memories are chosen to be utilized in this prototype not to impose additional logic utilization rather than that occupied by the actual architecture in the final synthesis. Block memories are implemented in dedicated blocks in the FPGA. Adequate interface modules are constructed in order to realize the connection between memories and the architecture modules. The used memories are initialized by memory-content files. A fixed-point software reference model is used to generate automatically the contents of input memory blocks. Concerning control memory (_CMem_), the _CWs_ generated by the compiler are utilized. The NISTC tool set imposes a basic NISTC architecture with supplementary hardware resources, such as the interrupt unit, data memory and combinational logic devices. Thus, the generated control words include extra control bits. In addition to control words related to the desired functions, the NISTC compiler would generate control words that are responsible for the startup addressing, jump and call/return operations of C functions. These control words and the extra control signals do not impact the desired functional operation and form an additional overhead in terms of memory size. In our work, neither the added control words nor the control signals of the additional resources are taken into account. Only the sequence of control signals, which are related to the real functionality of the architecture, are extracted from the generated memory file and imported to control memory _CMem_. With this complete model, sufficient simulations are conducted in order to confirm the proper functionality of the architecture for various system configurations. The simulations are performed to cover separate case studies with multitude characteristics concerning antenna dimensions, channel fading types, modulation schemes and mapping styles. Running simulations enables detecting the state of all internal signals and inspecting the flow of input and output data at each time slot. Figure 11 presents the simulation window of the equalizer architecture using Xilinx ISE. The simulation window shows the output signals of the equalizer architecture for \(2\times 2\) block fading mode. For this mode, the estimates relative to two successive symbol vectors (\(\hat{\mathbf{x}}\) and \(\bar{\mathbf{x}}\)) are generated concurrently. The figure shows the real and imaginary parts of the estimate symbols \(\vec{x_{0}}\), \(\vec{x_{1}}\), \(\vec{x_{0}}\) and \(\vec{x_{1}}\) relative to the input symbols \(\hat{x}_{0}\), \(\hat{x}_{1}\), \(\hat{x}_{0}\) and \(\vec{x}_{1}\). In addition, the figure shows signals, such as \"_FrameDone_\" and \"_SymbolOutReady_\", which indicate respectively that the whole frame is processed and that estimated symbols are ready at the output. Logic synthesis is conducted targeting a Xilinx Virtex-7 FPGA. The simulation and synthesis results (logic utilization, frequency and critical path) may imply feedback in NISTC modeling to further refine or modify the datapath and/or C code application. Iterative refinement can be exploited to concentrate separately on one design metric (frequency, flexibility, parallelism, implantation area, etc.) and then finally choose among several designs the one that meets the design requirements.