## 1 Introduction  
With the advancement of the integrated circuit industry, semiconductor manufacturing processes have become increasingly complex. Chip production involves hundreds of types of processing equipment and numerous processing steps. Variations in the manufacturing process and environment can lead to defects, resulting in significant uncertainties in production yield, directly impacting a company's costs and profits. Consequently, it is imperative to reduce process defects, decrease losses in semiconductor manufacturing, and enhance production efficiency and economic benefits. A wafer is a fundamental unit in integrated circuit manufacturing. After the manufacturing process, testing equipment evaluates the functionality of each die (chip) on the wafer. Hundreds of dies on a wafer are tested using chip probing. Furthermore, the die with a passing testing result will be packaged as a final chip. Figure 1 presents the relationship between wafer, die, and chip. Wafer bin maps (WBMs) represent the test results of the wafer based on the pass or fail (bin) values of each die. Multiple defective dies form spatial patterns as defect patterns. We refer to such instances where multiple defective dies are spatially aggregated, forming spatial patterns as wafer defects. Each defect pattern is associated with a failure or anomaly in a specific segment of the production line. Thus, WBM defect classification can provide critical information for the improvement of manufacturing processes and yield [1]. Figure 2 presents examples of several wafer bin maps with specific defect patterns. Black dots represent failed dies and white dots represent passing dies. In most semiconductor manufacturing enterprises, WBM defect classification primarily relies on human expertise. Manual labeling is time-consuming and can be subject to variations due to the subjective judgments of different engineers [2]. Therefore, investigating methods for automatic defect classification is of paramount importance. In this regard, researchers have proposed numerous automatic defect classification approaches over the past two decades, including statistic learning-based methods [3; 4; 5] and machine-learning-based methods [6; 7; 8; 9; 10; 11; 12]. In recent years, defect classification algorithms based on deep learning have been gradually proposed and developed because they improved image classification performance. [PERSON] [13] employed convolutional neural networks (CNNs) for WBM defect classification. [PERSON] [14] developed an automatic defect classification (ADC) method based on deep learning, capable of automatically classifying different wafer surface damage types. The proposed method could accurately identify the GFA classes that were not encountered during model training by comparing the CNN features of the unseen classes. [PERSON] [15] proposed an ensemble convolutional neural network (ECNN) framework for WBM defect classification, adopting a weighted majority function to assign higher weights to the base classifiers with superior predictive performance. Furthermore, [PERSON] [16] suggested using CNNs to classify mixed-type GFA in WBMs in an individual classification model framework for each GFA. However, training deep learning classification methods requires a large amount of labeled data, which meets the conflict that manual labeling is time-consuming and inconsistent. Moreover, in practice, there exists a vast amount of unlabeled WBMs that have not been utilized. Therefore, making good use of the large number of unlabeled WBMs and reducing the reliance on labeled data is one of the pressing issues that need to be addressed. Several methods have been proposed for utilizing unlabeled WBMs, such as semisupervised learning. [PERSON] and [PERSON] [17] proposed to adopt a ladder network and the semisupervised variational autoencoder to classify WBMs. Active learning and pseudo-labeling are also utilized to accelerate learning. Recently, self-supervised learning has been proposed as an effective unsupervised learning branch.