## 3 Experimental Setup and Characterization  
The experimental setup adopted for the tests, conducted in the hemi-anechoic chamber at the Engineering Department of the University of Ferrara, is reported in Figures 6 and 7. An omnidirectional noise source is placed outside the cabin, about 1 m away from it. The reference microphone, which measures the signal of the noise source in the feed-forward systems, has two possible locations: in front of the cabin, as shown in Figure 6a, or inside the cabin, as shown in Figure 7.  
For the feedback system, this microphone is not exploited, because the reference signals are modeled starting from the error signals. The error microphones, which define the zone of quiet, are allocated at the entrance to the ear canals of a binaural dummy torso  
Figure 6: Experimental setup: (**a**) outside the cabin, (**b**) inside the cabin, with reference microphone placed outside. Figure 7: Experimental setup inside the cabin with the reference microphone placed inside. for acoustic testing, to take into account the diffraction effect due to the presence of the head. Two control loudspeakers with a cut-off frequency of 100 Hz, endowed with an amplifier and a 5.25'' driver, are positioned on a shelf mounted behind the seat, at the same height as the error microphones. The type of error microphones is 1/2'' B&K 4100, while for the reference, 1/2'' PCB 377B02 has been used. The whole system is driven by a National Instruments real-time target (cRio 9063) with an FPGA (field programmable gate array), sampling input and output signals with a frequency of 6400 Hz. The sensed data are processed in a deterministic way by means of the previously described algorithms, with a timing for the operations defined by the 40 MHz on-board clock. The tested algorithms are implemented on the hardware through LabVIEW, by compiling the codes directly on the FPGA to have a processing system working in an autonomous way with respect to the PC monitoring the experiments. During the compilation, the operations contained in the algorithms (i.e., the convolutions, sums, and subtractions as described in Section 2) are assigned to circuits able to work in parallel to optimize the processing time. All the arrays used for the storage of signals and filters are implemented on blocks of memory (BRAM), instead of look-up tables (LUT RAM), which would consume the more limited resources that the FPGA uses for the logical operations and employ a fixed-point data type to optimize the usage of resources with respect to floating-point data. The generic scheme of the operations executed in the workflow is depicted in Figure 8. Firstly, all the arrays used for the storage of signals and filters are initialized to zero, while the length of the filters and the step size (for the algorithms with a fixed parameter) are updated from the external PC, which works as a simple interface. Secondly, the coefficients of the secondary paths are uploaded (considering the previously defined filter length), and the FPGA prepares itself to wait for \"ANC On\" command. At this point, the system works in a loop by processing the acquired data with the adaptive algorithm and generating the anti-noise signals in real time. When the \"stop\" command is sent to the FPGA, the loop is interrupted, and the stored data are transmitted to the external PC for the post-processing and the saving of the data. The studied configurations with the respective algorithms are indicated in the following:  
* Feed-forward configuration,
* Filtered-X least mean squares (FF_FXLMS), as in Section 2.1;
* Filtered-X least mean squares with normalized step size (FF_FXNLMS), as in Section 2.2;
* Filtered-U recursive least mean squares (FF_FURLMS), as in Section 2.3;
* Feedback configuration,
* Filtered-X least mean squares (FB_FXLMS), as in Section 2.4. Figure 8: Generic scheme of the workflow implemented on the hardware.