## 3 Our MDCIM Work  
### Algorithm and Architecture of FP64 Computation  
In the process of FP64 MAC operations, the power consumption and latency of multipliers are much higher than that of adders. In traditional FP64 multiplication, the 52-bit mantissa multiplier includes \(52\times 52\) AND gates, 52 registers of 52 bits each to store column results, and 51 full adders for shift accumulation, with their bit width increasing from 54 bits to 104 bits. Since the number of AND gates in the multiplier cannot be reduced, and the full adder has the highest bit width and is the part with the largest area overhead, we consider reducing the bit width of the shift adder to decrease the area overhead of the entire multiplier. Segmenting the two high bit-width multiplicands is an effective way to reduce the bit width of the multiplier, and we can decrease the area overhead required for a single MAC unit by increasing the number of computations. As shown in Figure 5, the 52-bit mantissa is divided into 4 sets of 13b inputs, e.g., \(a_{0}\sim a_{3}\) and \(x_{0}\sim x_{3}\), and then they multiply each other to obtain 16 sets of 26-bit partial products: \(a_{0}x_{0}\sim a_{3}x_{3}\). In this process, the number of AND gates and registers remains unchanged (\(13\times 13\times 4\times 4=52\times 52\)), but due to the reduction in input bit width, the bit width of the full adder is greatly reduced, with the largest full adder bit width being 26 bits. Then, we accumulate these partial products. It can be seen from Figure 5 that there are partial products with the same shift, and we first accumulate them. For instance, \(p_{3}\) is the sum of \(a_{3}x_{0}\), \(a_{2}x_{1}\), \(a_{1}x_{2}\), and \(a_{0}x_{3}\). Since it is same-position accumulation, we only need thirteen 26-bit full adders, then use eight sets of 26-bit registers to store the results. Ultimately, we obtain seven sets of 26-bit partial sums: \(p_{0}\sim p_{6}\) and a set of 15-bit partial sum with carry: \(p_{7}\). These partial sums can be rearranged into two groups of high bit-width numbers based on the parity of the base, and then, through a 106-bit full adder, the 52-bit mantissa product result is obtained. This method of mantissa segmentation can greatly reduce the area overhead of high bit-width multipliers. Under the same process node, the transistor count of the segmented mantissa  
Figure 4: Significands need to be normalized and rounded at the end during FP64 MAC operations. multiplier is 0.74\(\times\) that of the traditional multiplier, and it can also achieve a reduction in power consumption. We proposed the **MDCIM** macro by mapping mantissa segment multiplication to digital circuits. Since the algorithm involves a large number of independent MAC operations, we constructed a pipeline multiplication array as the overall architecture. As shown in Figure 6, the macro consists of 16 sets of MAC units, 3 sets of adders, and multilayer latches. A MAC unit group including a 13-bit MRAM cell, a 13-bit multiplier, a carry-save adder (CSA), and a full adder (FA). Figure 5: Divide the significands and multiply each part separately. Figure 6: A pipeline multiplier and accumulator array for multiplication of segmented mantissa. The red numbers indicate MAC units. As shown in Figure 6, the MAC unit performs preliminary MAC operation between the segmented \(m_{a}\) and \(m_{x}\). The MRAM cell is used to save the segmented mantissa \(m_{x}\), i.e., \(x_{0}\), \(x_{1}\), \(x_{2}\), and \(x_{3}\). The multiplier multiplies two segmented mantissa, e.g., \(a_{0}\) and \(x_{0}\). The CSA is a three-input and two-output adder. The first input to CSA is the 26-bit partial product, e.g., \(a_{0}x_{0}\), from the multiplier while the second input is the carry from the low-order MAC unit, and the final input is the sum of the same position of MAC units. Taking MAC unit 3 as an example, inputs of its CSA are \(a_{2}x_{1}\), carry from unit 2, and sum from unit 1. The CSA will output the \(sum_{mid}\) and \(carry_{mid}\) of 26 bits, which have overlapping bits.