# Secure ECDSA SRAM-PUF Based on Universal Single/Double Scalar Multiplication Architecture
## 4 Hardware Architecture
### The Architecture of ECDSA
The extension method must use the same approach as the extension of \(x_{p}Z\) stored in the ROM; otherwise, the same value cannot be obtained after the expansion of \(X\) and \(x_{p}Z\), preventing completion of the signature verification due to failure to satisfy Equation (1). Based on the data dependency introduced by Equations (A9) and (A10), we proposed the timing schedule for ECSM and ECDSM with one two-stage multiplier and one square unit as shown in Figure 4(a),b. \"REG\" represents a register in this clock cycle buffering the current intermediate value. The timing schedule for ECSM is based on the Montgomery ladder Algorithm A4. With one two-stage multiplier, we proposed a compact six-clock-cycle (6 CC) timing schedule, as shown in Figure 4(a). The multiplier is always busy, leaving no idle clock cycle. Based on this compact schedule, it consumes 6 CCs for each loop. Note that the figure illustrates the calculation process over seven clock cycles, where the seventh is also the next iteration's first cycle. The timing schedule for ECDSM follows a similar pattern. In this timing schedule, the modular multiplication operations of PD, \(Z_{2}=X_{2}^{2}Z_{2}^{2}\) and \(X_{2}=bZ_{2}^{4}+X_{2}^{4}\), locate at clock cycles 3-4 and clock cycles 5-6, while other multiplication operations belong to PA. The squares are arranged as close to the related multiplication as possible to avoid wasting registers for holding internal values. The timing schedule for ECDSM follows the proposed Algorithm A4. Each loop involves two PAs and one PD, resulting in 10 multiplication operations per loop. Based on this design philosophy, we introduce a compact ECDSM timing schedule utilizing a two-stage multiplier and a square unit, as illustrated in Figure 4(b). Ten CCs are required to execute two PAs and one PD in each loop. The values of \(i\) and \(k\) are determined by the proposed flag signal generation Algorithm 4 during precomputation. After precomputation, modular multiplications of PD are scheduled at clock cycles 3-4 and 8-9, enabling the first PA in ECDSM to advance by one clock cycle. Meanwhile, the second PA remains idle during clock cycles 8-9 to wait for the results of \(X_{3}Z_{k}\); thus, another multiplication of PD is scheduled at clock cycles 8-9 to ensure an utterly compact timing schedule without any wasted clock cycles. The two-stage multiplier employs the Karatsuba-Ofman algorithm, with carefully inserted pipeline stages to alleviate critical paths. Two squaring units are directly cascaded, requiring one clock cycle for square and quartic powering operations. During ECDSM computation, the DAC generator precomputes chain parameters based on scalars \(k\) and \(l\). Additionally, a finite-state machine governs the operational modes of the architecture. The register bank includes extra registers for storing internal values during ECSM and ECDSM operations. Each register is connected to a multiplexer to regulate the datapath. Control signals from these multiplexers are consolidated into instructions executed at every clock cycle.