## 1 Introduction  
Data switching networks are facing increasing difficulties in handling the exponential growth of traffic [1]. The scaling up of traditional network-on-chip capacity is severely limited by overheating problems [2]. Silicon photonics is believed to be a potential solution to improve the performance of interconnects and computing systems, specifically allowing larger bandwidth and lower power consumption. Data switching networks can thus benefit from several advantages of Si-technology such as large-area wafers, CMOS-compatibility, large-scale dimension device integration, high-level integration process and device density, heterogeneous integration such as electro-optic modulators and germanium photodetectors, low-cost, high volume, and compactness. Planar photonic switches have been largely fabricated on Silicon platforms, based on thermo-optic (TO) or/and electro-optic (EO) phase shifters. The first ones have a micro-second switching transient time, which matches the requirements of telecommunication network nodes and inter-data center connections. In contrast, the second ones have a nano-second switching transient, which fits the requirements of CPU/CPU and CPU/memory interconnections as well as intra-data center connections [3]. Mach-Zehnder interferometer (MZI) is a critical building block for scalable silicon photonic systems, whether in optical switching or in other applications like optical sensing [4]. The non-resonant interference mechanism for such devices is suitable for spectral broadband operation and temperature-insensitive switching. Many promising achievements have been performed, \(32\times 32\) electro-optic (EO) and \(64\times 64\) thermo-optic (TO) Mach-Zehnder-based switches were fabricated by CAS [5]. To the best of our knowledge, this is the largest scale realized for these types of switches. A \(4\times 4\) EO + TO Mach-Zehnder-based switch monolithically integrated in a CMOS logic process was demonstrated for the first time by IBM [6]. However, the scalability of switches is still limited mainly by the optical path loss and cumulative crosstalk [7]. An appropriate choice of architecture, which impacts strongly on the overall performance of the switch, can reduce these limitations [8]. In several publications, the comparison of architectures takes into account only the effect of MZIs [3; 9] or is mainly based on the calculation of the total insertion loss, without considering any crosstalk [10]. These approaches may not be sufficient to estimate which architecture matrix is the most appropriate for a given technology. In this paper, and for the first time to our knowledge, the two basic performance parameters--optical crosstalk and insertion loss--of both MZIs and waveguide crossings, are considered in one single metric to select the most suitable architecture. Then, after defining the signal-to-crosstalk ratio expression, we show that this metric can be used as a tool for architecture evaluation and comparison. This paper is organized as follows. In the next section, the performance of the switch fabric building blocks is defined. In the third section, we describe four architectures very popular in literature. In the fourth section, we introduce our analytical model of SCR, and we detail the calculus necessary to apply it to the four architectures. This is followed, in the fifth section, by a comparison between architectures, using the proposed SCR metric, when scaling up the numbers of inputs/outputs. The last section presents our Si-based \(2\times 2\) MZI and waveguide crossing characterization results. Then, we conclude.