# A Novel Top-Down Fabrication Process for Vertically-Stacked Silicon-Nanowire Array
## 1 Introduction  
Silicon nanowires are widely used for sensing applications due to their outstanding mechanical, electrical, and optical properties. Accordingly, research is currently being conducted on the physical properties of silicon nanowires, as well as on their manufacturing methods and applications [1; 2; 3; 4; 5]. Indeed, technology is being developed to use silicon nanowires as sensing elements, with further research being conducted in terms of possible integration with complementary metal-oxide-semiconductor (CMOS) circuits [6; 7]. In the case of silicon nanowires, the physical and chemical properties are largely dependent on the surface-to-volume ratio and the quantum-size effect, which are atypical compared with conventional macroscale materials [8]. Since the surface-to-volume ratio is enormous in the nanoscale dimension, sensing apparatuses that consist of nanostructures exhibit ultrasensitive properties for surface changes. This possibility has resulted in many methods of fabricating silicon nanowire-based biosensing platforms, all of which provide label-free and highly responsive sensing in real time [9; 10; 11; 12; 13]. Thus, a sensor platform with highly-sensitive silicon nanowires is a viable alternative; moreover, it can facilitate the combination of multiple functions within a single sensor using the same structure of silicon-nanowire building blocks [14]. The major challenge for sensor applications of silicon nanowires is to introduce silicon-nanowire arrays to a specific layout location with reproducible and controllable dimensions. However, the bottom-up fabrication method of silicon nanowires using the metallic-catalyst growth method has difficulties with respect to the exact positioning of nanowires. In addition, due to the randomly oriented growth and inconsistent distribution of the required dimensions, the control of structural parameters is also an issue that needs to be resolved [15]. In addition, many researchers have reported nanostructure fabrication using metal-assisted chemical etching processes [16; 17; 18]. This is a method to fabricate nanostructures of vertically-aligned structures by patterning metal on the substrate. This makes it possible to fabricate well-aligned vertical nanostructures according to patterned metals, but for fabrication of laterally-aligned silicon-nanowire arrays, the aligned structures can be deformed during substrate transfer [19], or the separation of nanostructures from the substrate can be difficult [20]. The Si/SiGe epitaxy method has also been reported to fabricate the nanowire [21]. The epitaxial method allows for very tight control of the film thickness; however, the stacked epitaxial layers require careful control on the film stress to obtain reproducible electrical characteristics. Among the alternative fabrication approaches, the most promising technique is based on the top-down fabrication of silicon nanowires on a silicon-on-insulator (SOI) substrate. For sensors using silicon nanowires as a sensing structure, the sensor characteristics are determined according to the dimensions of the nanowires, which must to be controllable within the tunable range of electronics. In previous studies, a method of fabricating silicon nanowires by defining a pattern width by e-beam lithography (EBL) on an SOI wafer with a thin top layer has been reported [4]. In addition, silicon nanowires can be fabricated by defining microscale patterns using conventional ultraviolet (UV) lithography and then narrowing the pattern width through wet oxidation processes [5; 6; 22]. As a result of our previous work, we reported on the fabrication of silicon nanowires using (100)- and (111)-single crystalline silicon, as shown in Figure 1. The authors fabricated junctionless FETs and photodetectors using silicon nanowires fabricated from top-down methods. The results of the previously reported papers confirm that the number of silicon nanowires affects the sensor characteristics rather than the morphology of individual nanowires [22].