# Technology Mapping of FSM Oriented to LUT-Based FPGA
## 6 Results  
In order to prove the effectiveness of the presented methods of carrying out FSM, a series of experiments were conducted. The experiments were conducted on the set of benchmarks [53] described in the format kiss2. In most cases, FSM states were represented in a symbolic form. In the process of coding, next words of natural binary code were ascribed to separate states. The most basic way of state assignment was chosen as the essence of the method, shown in the paper, based on minimization of the number of LUTs that is possible for each coding of a state. After having ascribed the codes of states, it was possible to describe combinational blocks FSM in the format pla. It made it possible to conduct a logic synthesis of FSM using the description of a transition function (\(\delta\)) and description of an output function (\(\lambda\)). It was also real to carry out synthesis using the proposed method in which the description of the whole combinational block FSM was used, i.e., the simultaneous description of a transition and output function (\(\delta+\lambda\)). The results of technology mapping of the analyzed FSM into FPGA were accurately examined. The essence of technology mapping is based on appropriately conducting a decomposition process. In the process of decomposition, an author's tool DECOMP [49] was used as well as ABC [35], which has been one of the best academic tools so far and was created at the University of California, Berkeley. The ABC system is a flexible tool that may carry out many stages of logic synthesis directed at both combinational logic as well as sequential ones. The essence of its flexibility lies in carrying out appropriate strategies of a synthesis launching with the usage of scripts. The script (&get; &st; &synch2; &if -K 4; &ps;) was used in experiments and helped to direct technology mapping at LUTs that have four inputs. It was decided to conduct experiments for blocks that have low number of inputs as the number of inputs in the presented benchmarks is also low, very often. Analyzing the function, which has a low number of variables and too high a number of inputs in a LUT, leads to the situation in which decomposition may turn out to be unnecessary. It may hinder showing the efficiency of the ideas presented in the paper. The results obtained for ABC are presented in Tables 1 and 2. Table 1 includes the results for benchmarks describing FSMs that have maximum 9 inner states. Table 2 includes the results for benchmarks describing bigger FSMs. \begin{table}
\begin{tabular}{c c c c c c c c c c c c} \hline \hline  & & & & & \multicolumn{3}{c}{**Separate**} & \multicolumn{3}{c}{**Shared**} & \multicolumn{3}{c}{**Separate im.-**} \\  & & & & & \multicolumn{3}{c}{**Implementation**} & & \multicolumn{3}{c}{**Implementation**} & \multicolumn{3}{c}{**Shared im. **} \\ \hline \multicolumn{8}{c}{**Benchmarks**} \\ \hline
**Name** & **In** & **Out** & **P** & **States** & **Blocks** & **Levels** & **Blocks** & **Levels** & **Blocks** & **Levels** & **Blocks** & **Levels** \\ \hline Bbtas & 2 & 2 & 24 & 6 & 4 & 2 & 2 & 1 & 6 & 2 & 0 & 0 \\ Beecount & 3 & 4 & 28 & 7 & 10 & 3 & 12 & 2 & 22 & 3 & 0 & 0 \\ dk14 & 3 & 5 & 56 & 7 & 20 & 3 & 20 & 3 & 39 & 3 & 1 & 0 \\ dk15 & 3 & 5 & 32 & 4 & 6 & 2 & 14 & 2 & 20 & 3 & 0 & \(-1\) \\ dk17 & 2 & 3 & 32 & 8 & 33 & 4 & 22 & 4 & 54 The obtained results are presented in Tables 1 and 2. The first five columns describe separate benchmarks: name, the number of inputs, the number of outputs, the number of transitions (\(p\)), and the number of states. In the next columns, the number of blocks (Blocks) and the number of levels in a critical path (levels) were given. The results are shown only for these two cases. In the first case (separate implementation), the synthesis process was based on separately carrying out a transition (\(\delta\)) and an output function (\(\lambda\)). In the second case (shared implementation), the whole combinational block, described in the form \(\delta+\lambda\), was subjected to synthesis.