# Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing
## 3 Results and Discussion
### Binarized Neural Networks Applications
Thus, we also consider an alternative approach in which the number of computing steps scales linearly with the number of input bits, reducing the number of computing steps when more than 9 bits are compared (see 2-SIMPLYOpt.WideWords in Figure 11 and Supplementary Figure S6). The same two approaches can be optimized with the 3-SIMPLY operation (see 3-SIMPLYOnlyXNOROpt. and 3-SIMPLYOpt.) providing a considerable reduction in the number of computing steps (see Supplementary Figures S7 and S8). While the use of the 4-SIMPLY operation enables additional step savings (see 4-SIMPLYOpt. in Figure 11 and Supplementary Figure S9), n-SIMPLY with larger n values would not provide any additional step reduction. Thus, some applications, such as the BNN inference, can largely benefit from a limited increase in n-SIMPLY operation parallelism. In fact, most of the step reduction for a 1-bit FA, the bitwise XNOR operation, the popcounting operation, and the activation function are achieved by using only up to the 4-SIMPLY operation. Further increasing the parallelism of the n-SIMPLY operation would not provide relevant additional energy savings while causing a reduction in the available RM, thus potentially reducing the circuit reliability, and increasing the instruction set complexity. To benchmark the latency improvement brought by the n-SIMPLY operation when performing an inference task, we consider the results of the 2-SIMPLY implementation of a BNN reported in [30], which consists of a single fully connected hidden layer with 1000 neurons performing a handwritten digit recognition task, achieving an accuracy of 91.4%. The use of n-SIMPLY reduces the number of computing steps from 190,657 to 135,539, therefore resulting in a remarkable 29% latency reduction leading to a 542 \(\upmu\)s inference time at 0.5 GHz, which further highlights the advantages of the SIMPLY architecture as a solution for ultra-low power devices for edge computing applications. Additionally, unlike conventional IMPLY architectures, SIMPLY is not constrained to employ bipolar RRAM devices [18] and can use unipolar RRAM devices as well as other memory technologies such as phase change memories (PCM) [53], ferroelectric FETs  
Figure 11: Analysis of the comparator implementation for increasing n of the n-SIMPLY operation and number of compared bits. Both the total number of computing steps and the percentage of saved computing steps are reported in (**a**,**b**), respectively. The use of optimized sequences for the 3-SIMPLY (i.e., 3-SIMPLYOpt.) and 4-SIMPLY (i.e., 4-SIMPLYOpt.) operations considerably reduces the number of computing steps. (FeFETs) [54], ferroelectric tunnel junctions (FTJs) [54], and virtually any 2- or 3-terminal non-volatile memory. Therefore, device/circuit co-design strategies can be implemented easily to further improve performance. For instance, memory technologies with ultra-low power consumption like FeFETs and FTJs [54] may be targeted to improve power consumption. Further, devices with higher endurance than most RRAM technologies, such as PCM [54] and STT-MRAM [53], could be evaluated on the SIMPLY architecture.