All-Analytic Statistical Modeling of Constellations in (Optical) Transmission Systems Driven by High-Speed Electronic Digital to Analog Converters Part I: DAC Mismatch Statistics, Metrics, Symmetries, Error Vector Magnitude  
performance. The eDAC random impairments are assumed to be induced by the stochastic mismatch errors of the transistors implementing the current sources. Our applicative interest is in particular in optical communication interconnects based on MZMs driven by ultra-high-speed eDACs [1]. However, the results are meaningful for electrical (wireless, wireline) electrical communication at large as we elucidate here the impact of eDAC nonlinearity metrics on error vector magnitude (EVM). The analytic-statistical eDAC foundations developed in this paper will enable, in our planned sequel publication (Part II), developing an analytic model the nonlinear propagation of the eDAC current mismatch impairment statistics via the MZM nonlinear sine-shaped TC, as well as modeling optical DACs (oDAC). Random device variations are identified as a key factor limiting the performance of high-resolution CMOS current steering D/A converters used as drivers in ultra-high-speed electronic and optical Tx-s. For high-end ultra-high-speed energy-efficient applications, current-steering eDACs are the drivers of choice [2]. In eDACs, the transistor mismatch of current sources is often the predominant error determining the nonlinearity of the static eDAC transfer characteristic. This paper provides in-depth analytic statistical treatment of electronic mismatch in eDACs, albeit not at the device level but at the sub-system level. The stochastic effect of \"devices mismatch\" (the inevitable variability in identically designed devices) is the most fundamental of the eDAC impairments, irreducible (for any given device structure) by technological advances, in fact becoming progressively worse along Moore's law evolutionary path, as the CMOS technology node is reduced. Despite a formidable amount of research having addressed device-level mismatch, e.g., [3; 4], knowledge is still insufficient on the propagation of random contributions from the stochastic mismatch sources on the eDAC chip via the Tx, channel and Rx sub-systems, collectively affecting the attainable precision of the Tx output, as well as the signal detected in the Rx at the far end of the link. In historical terms, Pelgrom et al. [5] pioneered rigorous device-level modeling of the mismatch impairment of CMOS transistors. Some 16 years later, he insightfully commented on the significance of mismatch statistical analysis, providing the following perspective [6]: \"As dimensions shrink, the granularity of the silicon device will play a more and more dominant role... It seems inevitable that we are now entering an era where statistical design is the rule not the exception... We will see many more papers exploring the statistical behavior of the devices and their interaction with technology\". Our paper may well be one of those contemplated by Pelgrom in 2005, with some distinctions: granted, numerous papers have been published ever since on the impact of mismatch modeled by Monte Carlo simulation. However, to the best of our knowledge, far fewer papers [7; 8; 9] approached the statistical problem in an all-analytic mindset. Moreover, our paper is differentiated by its particular (optical) communication orientation, analytically tracing the mismatch statistics of the eDAC current source devices all the way along the chain of subsystems in the (optical) transmission link to obtain communication performance figures of merit such as EVM (in the current paper Part I), SER and BER (in the upcoming Part II), of direct interest to optical or wireless communication engineers designing eDAC drivers into their transmitters.