# A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits
## 10 Test Quality Metrics for SDDs and HDDs
### Weighted Slack Percentage (\(WeSper\))  
To overcome the disadvantages of the previously mentioned metrics, the \(WeSper\) metric is introduced [84]. It is calculated by the ratio of slacks as given in Equation (8). The total \(WeSper\) factor is calculated using Equation (7). The test pattern that maximizes this factor effectively detects SDD or HDD. The best test path is the longest path through the fault site in all other metrics. But here, the best-activated path is the one that maximizes the factor. The factor uses a new term called the confidence level (\(CL\)) multiplier. The \(CL\) multiplier equation acts as a weighting factor to denote whether the factor chosen is good or bad for the test. The  
Figure 13: Delay defect distribution [82].  
equation must penalize the undesirable aspects of the test and reward the desirable aspects of the test. The factors that affect the SDD testing include patterns that create hazards in the endpoints, over testing the design during FAST, etc. In [43], the use of this factor for FAST is discussed. This metric is the aptest metric for FAST. Over testing must be penalized when the test detects defects of a size less than the smallest possible defect size that fails the circuit during at-speed operation. The below mentioned equation gives the \(CL\) factor to penalize over testing. Also, this metric is sensitive to the delay variations due to the PVT, as mentioned in [85]. When the exact delay defect distribution is available for the particular process and technology, the \(CL\) multiplier can penalize the pattern that detects the defect sizes that are not important. But the major demerit of the metric is that the \(CL\) equations for other factors that affect SDD testing are not mentioned. It has to be found by the test engineers, and experiments must be performed based on the requirements.  
\[WeSPer=\frac{1}{N}\sum_{i=1}^{N}f_{i}\times 100\% \tag{7}\]  
\[f_{i}=\frac{T_{sys}-PD_{LT_{i}}}{T_{test}-PD_{BA_{i}}}CL\quad for\quad T_{test }>PD_{BA_{i}} \tag{8}\]  
\[CL=\begin{cases}1&\text{if}\quad\frac{T_{sys}-PD_{LT_{i}}}{T_{test}-PD_{BA_{i} }}<1\\ \frac{T_{sys}-PD_{LT_{i}}}{T_{test}-PD_{BA_{i}}}&\text{if}\quad\frac{T_{sys}- PD_{LT_{i}}}{T_{test}-PD_{BA_{i}}}>1\end{cases}\]  
In Figure 14, it is clearly illustrated that the \(SDDCdpm\) values are higher than the \(WeSPer\) factor, which shows that during FAST, the \(SDDCdpm\) metric assigns a perfect grade for over testing patterns and test clock, which is a pessimism. But \(WeSPer\) addresses this issue and can be used as a quality metric when reliability defects are of no interest for detection. Figure 15 shows that the \(WeSPer\) value increases when the test detects the SDD similar to the ideal test model, i.e., when the test detects the exact SDD size. The graph plot shows that the value is higher during the at-speed test. The flow diagram for \(WeSPer\) based pattern generation is shown in Figure 16.  
Figure 14: Comparison of \(SDDCdpm\) and \(WeSPer\) for FAST [84].  
Figure 16: Flow diagram for \(WeSPer\) based pattern generation for SDDs and HDDs [43].  
Figure 15: Comparison of \(WeSPer\) percentage for Slow, At-speed and Fast test clocks for three different benchmark circuits [84].