## 1 Introduction
The presence of these defects disrupts the pathways necessary for effective charge transport, thus reducing the device's overall performance. In another study by [PERSON] et al., it showed that during thermal annealing, cracks primarily form due to the inelastic stress associated with side chains in the TIPS pentacene [49]. These cracks act as sites for moisture and oxygen trapping, leading to increased off-current and a reduction in the overall stability and mobility of the transistor device. Annealing at optimal temperatures can mitigate crack formation, enhancing the crystallinity of the TIPS pentacene film and improving the transistor electrical performance and stability over time. Grain boundary: boundaries in the crystal domains are crucial in influencing the electrical properties and various other properties of polycrystalline thin films [50; 51]. [PERSON] et al. discovered the impact of grain boundaries on mobility and many other parameters, including on/off ratio, threshold voltage, and hysteresis in transfer characteristics of TIPS pentacene thin film transistors, employing both experimental methods and simulations [52]. An apparatus was designed and fabricated to control solution casting, enabling the production of TIPS pentacene thin film transistors with more managed microstructure and defect density variations. Hysteresis in electrical characteristics was found to be directly linked with grain width in the active layers. Additionally, TIPS pentacene crystals with larger grain width typically formed long needle-like shapes, while those with smaller domain sizes tended to have a more equiaxed geometry, leading to a marked increase in effective mobility in larger grains. For devices based on casting from toluene solution, the mobility for grain widths smaller than a certain threshold was generally lower, whereas the mobility for films with larger grain widths was typically higher. Mobility variation: these morphological issues lead to significant mobility variations in TIPS pentacene thin films [53; 54]. Dendritic crystals, which are characterized by misorientation, can disrupt charge transport due to their random alignment and result in anisotropic pathways [55; 56]. The poor coverage of TIPS pentacene films on the substrate, evidenced by incomplete regions, creates areas lacking active material, which further restricts electrical performance and leads to substantial mobility fluctuations. Additionally, thermal cracks induced by stress during film formation or post-deposition annealing introduce structural discontinuities, compromise the film integrity, and disrupt charge transport. These cracks pose a risk of device failure and significantly lower overall performance [57; 58; 59]. The variations in grain width and crystal geometry also play a critical role, with larger grain widths associated with enhanced mobility. [PERSON] et al. devised a deposition system to investigate the relationship between the crystal long axis direction and charge transport [60]. By fabricating devices with TIPS pentacene crystals oriented at different angles within the channel, ranging from 0\({}^{\circ}\) to 90\({}^{\circ}\), they found significant differences in hole mobility: 0.004 cm\({}^{2}\)/Vs at 0\({}^{\circ}\) compared to 0.04 cm\({}^{2}\)/Vs at 90\({}^{\circ}\), indicating a tenfold variation due to crystal orientation. Additionally, crystal misorientation, coupled with factors like large grain boundaries and low areal coverage, can lead to substantial variability in charge carrier mobilities. For example, it was reported in another work the combined effect of crystal anisotropy, varied grain width and coverage corresponds to a wide range of measured mobilities, spanning from 1.6 \(\times\) 10\({}^{-1}\) cm\({}^{2}\)/Vs to 3.1 \(\times\) 10\({}^{-6}\) cm\({}^{2}\)/Vs [61]. In this section, we have discussed the importance of understanding the morphological characteristics of organic semiconductors to improve their performance in organic electronic applications.