# A Wideband Hybrid Envelope Tracking Supply Modulator with Slew-Rate-Enhanced Linear Amplifier
## 3 Experimental Results  
The proposed HETSM chip was fabricated on a 180 nm CMOS process, of which the die size was 1.98 mm \(\times\) 0.9 mm, as depicted in Figure 14. The chip was operating under a 6.5 V power supply, with an off-chip inductor of 4.7 \(\upmu\)H.  
\begin{table}
\begin{tabular}{c c c} \hline \hline
**Design** & \
\begin{tabular}{c} **Conventional LA** \\ **(Without SRE)** \\ \end{tabular} &
\begin{tabular}{c} **The Proposed LA** \\ **(With SRE)** \\ \end{tabular} \\ \hline UGB (MHz) & 48.2 & 226.6 \\ \hline Phase Margin (\({}^{\circ}\)) & 91.2 & 56.6 \\ \hline DC Gain (dB) & 105.6 & 111.2 \\ \hline Slew Rate (\(V\)/\(\upmu\)s) & \(-\)178.5/+122.2 & \(-\)1907/+2320 \\ \hline Quiescent Current (mA) & 16.2 & 24 \\ \hline \hline \end{tabular}
\end{table}
Table 1: Simulation results of the proposed LA and the conventional LA.  
Figure 14: The micrograph of the proposed HETSM.  
\begin{table}
\begin{tabular}{c c c c c c c} \hline \hline
**Process** & **Temperature (\({}^{\circ}\)C)** & **DC Gain (dB)** & **Phase Margin (\({}^{\circ}\))** & **UGB (MHz)** & \begin{tabular}{c} **Quiescent** \\ **Current (mA)** \\ \end{tabular} & \
\begin{tabular}{c} **Positive Slew** \\ **Rate (V/us)** \\ \end{tabular} &
\begin{tabular}{c} **Negative Slew** \\ **Rate (V/us)** \\ \end{tabular} \\ \hline \multirow{3}{*}{ff lib} & \(-\)40 & 117 & 62 & 209.7 & 20.1 & 4311 & \(-\)3246 \\ \cline{2-7}  & 25 & 108.8 & 61.3 & 216.9 & 26.2 & 3513 & \(-\)3738 \\ \cline{2-7}  & 85 & 96.9 & 6  
Figure 15 shows the measured waveforms for a 100 MHz signal, with a 16 QAM modulation and an 8.49 dB PAPR. The external clock frequency was set to 20 MHz. The input envelope signal, output signal, and switching node voltage are shown in the figure. The HETSM amplified the amplitude of the input signal by a factor of 2, with an output signal delay of 7.5 ns.  
Figure 16 illustrates the measured step response waveform of the proposed LA with the SRE circuit. A 100 pF capacitor was connected to the output of LA as a capacitive load. The rise time slew rate was measured at 1239 V/ us, while the fall time slew rate was measured at \(-\)1857 V/ us.  
Figure 16: Measured step responses of the proposed LA with the SRE circuit: (**a**) fall condition and (**b**) rise condition.  
Figure 15: The measured transient response of the ET modulator to the 100 MHz envelope signal.  
Figure 17 presents the measured efficiency of the HETSM chip with a 5 \(\Omega\) load paralleled with a 100 pF capacitor. For the 100 MHz, 16 QAM, and 8.49 dB PAPR signal, the peak efficiency reached 87.4%. When the output power was small, the ratio of these intrinsic losses to the output power was relatively large. According to Equation (3), the efficiency was relatively small under low-power conditions for the large value of the aforementioned ratio, as shown in Figure 17.  
Figure 18 shows the measured error between the output voltage and the ideal output voltage when tracking the 100 MHz, 16 QAM envelope signal. The tracking error was less than 3%.  
The comparison of the proposed HETSM with prior works is shown in Table 3. Our work showed the highest slew rate of LA and adapted the 100 MHz wideband signal tracking. Also, it achieved 87.4% efficiency, which is comparable to prior works. The  
Figure 17: Measured efficiency of the HETSM chip with the 100 MHz envelope signal.  
Figure 18: Measured tracking error between the output and the ideal output voltage with the 100 MHz envelope signal.  
proposed HETSM provided a maximum voltage of 6 V, which can accommodate GaAs PA applications.