# Improvement of Power Converters Performance by an Efficient Use of Dead Time Compensation Technique
## 3 Proposed Dead Time Compensation Technique
### Dead-Time Compensation for PWM Inverter  
The design of a three-phase voltage-based inverter is given in Figure 3 where 'n' and 'o' indicate dc link and induction motor neutral points respectively and IGBTs paired with diodes work as switches. As an example, the effect of dead time and forward voltage drops have been examined in phase A leg. The phase A leg contains four different current paths as demonstrated in Figure 3. The forward voltage drop of IGBT is represented as '\(u_{ce}\)' and that of the anti-diode as '\(u_{d}\)'. From Figure 4, phase A current \(i_{a}\) is represented by the dashed line in Figure 4. It is established from Figure 4a,b that when current flows from the inverter to load, \(i_{a}>0\) and from Figure 4c,d it is evident that \(i_{a}<0\) for opposite current direction reverses. Figure 4: Analysis of different current flow paths of phase A. (**a**) When i_a>0 from D1 (**b**) When i_a>0 from D2 (**c**) When i_a<0 from D1 (**d**) When i_a<0 from D2 (**d**) When i_a<0 from D2 (**d**)  
Figure 3: Two-level inverter-motor system [21]. Since the delay in the on-off of IGBTs for this study is extremely small in comparison to the dead time, it is considered negligible. In the beginning, the dead time setting is analyzed. The delays between turn on and off of power electronic devices (IGBTs) are considered negligible in this study as they are very small in comparison to the dead time. One switching cycle of sinusoidal pulse width modulation (SPWM) contains two stages of dead time in which power electronic devices remain in the OFF state. Hence, the load current is forced to pass through anti-parallel diodes D1 or D2 (depending on the direction). Current flows through D2 when \(i_{a}\) is positive during phase A and is interconnected to the negative terminal as evident from Figure 4b. If \(i_{a}\) is negative, current flows through D1 with phase A connection setting shown in Figure 4c. Forward voltage drop occurs when the switching devices pass load current. When the current is positive, the voltage output at phase A is marginally less than the respective DC linkage voltage. In such instances, the IGBT S1 passes current from the positive linkage or D2 passes current from the negative linkage. Similarly, for negative \(i_{a}\), the voltage output at phase A is marginally greater in comparison to the DC linkage voltage. In this case, positive linkage gets current via D1, and negative linkage via S2. The various permutations of currents flow, and voltage waveforms at different instances are given in Table 1.  
As seen from Table 1 the error voltage is the largest for the time range \(t_{8}-t_{8}\) where \(i_{a}\) is negative. These analyses for phase A leg can also be applied to three-phase legs. The gate signals and voltage waveforms of phase A as per the pulse generation rule of SPWM are given in Figure 5. It depicts the gate input and dead time incorporated gate input signals for top and bottom switching devices (\(u+g\), \(u-g\)), voltage output (\(u_{ideal}\)), real output voltage incorporating dead time (\(u_{real}\)), with both dead time and forward voltage drop (\(u_{real2}\)). Accordingly, the corresponding dead time error is given as the difference between \(u_{ideal}\) and \(u_{ideal2}\). Similarly, \(V_{dc}\), \(T_{s}\), and \(T_{d}\) indicate the DC linkage voltage, switching period, and dead time respectively. It is evident from the left side of Figure 4 that for negative \(i_{a}\) ideal PWM voltage is greater than the actual PWM voltage. In other words, the ideal voltage output will exceed the actual voltage output. The actual o/p voltage will be slightly less when the forward voltage drop is applied. The voltage varies between \(\frac{V_{dc}}{2}-u_{ce}\) and \(-\frac{V_{dc}}{2}-u_{d}\) when the load current is applied to positive and negative terminal respectively. It is evident from Figure 5 that the deviation from ideal behavior is a function of dead time.