# High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing
## 3 Method
### Line Buffer Access Pattern and Control Instruction
#### 3.3.2 Control Code Generation  
To perform the buffer store and load with the proposed access pattern, D-SWIM adopts customized instructions along with hardware logic to control the LBs. The BRAM control signals inside each LB are given by the instruction codes and decode logic, and the line-rolling behavior (store block/load block) is controlled by the hardware logic. The instruction codes for a specific image size were generated and loaded into the Instruction Memory before run-time. The instruction-based control method has two key benefits: firstly, it saves hardware logic for control signal generation; and secondly, the content in the Instruction Memory can be rapidly switched for processing differently sized images. Note that each instruction manages the buffer behavior over multiple cycles corresponding to one image line. As Table 2 listed, the customized instruction is composed of five sections, and each of them is translated into specific BRAM control signals by the control logic. Because an arbitrary number of remainder pixels (\(N_{remain}\)) may exist ahead of the first block of a line (line-initial block), we set section \(\mathtt{MEM_{start}}\) to give the BRAM index from which to store the line-initial block. Furthermore, since the block access may not be aligned to the BRAM boundary, the offset position inside a BRAM is given by section \(\mathtt{MEM_{offset}}\). In the D-SWIM design, we constrained \(N_{blk}\) to be an integer multiple of the BRAM width (\(N_{blk}/(W_{bran}/8)\in\mathbb{Z}\)). Thus, all pixel blocks in one image line have the same offset inside a BRAM, which is given by \(\mathtt{MEM_{offset}}\). This constraint leads to a regular storage pattern and reduces the hardware logic usage for control signal generation. Section \(\mathtt{REMAIN}\) gives the value of \(N_{remain}\), which represents the number of pixels in the last block of a line that overflows into the successive line, and they are duplicated and stored in the next LB. Section \(\mathtt{CYCLE}\) gives the number of blocks in the line, which indicates the cycle number of the control period for the current instruction code. In addition, \(\mathtt{CYCLE}\) determines the interval period of fetching a new instruction. The periodic access pattern of continuous image lines presented in Equation (3) enables instruction reuse. For instance, \(P_{line}\) is 4 in Figure 7a; thus, only four instructions are needed. To reuse the instruction periodically, section \(\mathtt{RETURN}\) gives the flag to reset the instruction-fetch address and restart a new period of the access pattern. The periodic reuse of control code saves the instruction memory and reduces time delay caused by instruction reloading while switching the image size. Theoretically, the maximum possible number of instruction is \(N_{blk}\). Figure 7: (**a**) shows an example of the block storage pattern with parameters \(N_{line}=44\), \(N_{blk}=16\), and \(H=3\). (**b**) shows the buffer instruction list for achieving the access pattern in (a). Algorithm 1 gives the instruction generation flow in D-SWIM's SW-tool. Each iteration of the program calculates five sections and then assembles the instruction to binary codes. The iteration continues till \(N_{remain}\)(value of REMAIN section) gets to zero. In the last instruction of the list, RETURN is set to 1, that leads to re-execution of the entire instruction list. For instance, Figure 7b gives the instruction code for each image line in Figure 7a, which is generated by Algorithm 1. For Line0, the line-initial block starts from BRAM0 without pixel offset. Thus, MEMstart and MEMoffset are 0. It takes 3 blocks to fulfill the Line0, and the last block contains 4 pixels belonging to the following Line1. Thus REMAIN and CYCLE is equal to 4 and 3, respectively. Algorithm 1 starts with an initial state that all variables are set to 0, and input parameters \(N_{line}\), \(N_{blk}\), and \(W_{bran}\) are set to 44, 16, and 64, respectively.