## 4 Experimental Results and Verification
### Phase Noise Measurement  
Figure 10 presents the absolute phase noise measurements for a frequency synthesis chain consisting of a 10 MHz OCXO, a 200 MHz OCXO, and a DRO. The phase noise measurements were conducted using the R&S FSWP26. As discussed in Section 3, PLL1 and PLL2 were set with bandwidths of 150 Hz and 300 kHz, respectively. Figure 10a illustrates the absolute phase noises of the 10 MHz OCXO, which are measured at \(-123.8\) dBc/Hz, \(-137.5\) dBc/Hz, \(-158.5\) dBc/Hz, and \(-165.5\) dBc/Hz at 1 Hz, 10 Hz, 1 kHz, and 10 kHz offset frequencies, respectively. The output clock of the 200 MHz OCXO in its free-running state was measured at a power level of approximately +26 dBm, using a signal passed through a directional coupler and amplifier. The absolute phase noises at 1 Hz, 10 Hz, 1 kHz, and 10 kHz offsets were recorded as \(-56.5\) dBc/Hz, \(-93.2\) dBc/Hz, \(-145.3\) dBc/Hz, and \(-163.6\) dBc/Hz, respectively (see Figure 10c). While PLL1 was locked, the absolute phase noises of the 200 MHz OCXO signal were observed to be \(-97.5\) dBc/Hz, \(-110.1\) dBc/Hz, \(-145.0\) dBc/Hz, and \(-163.8\) dBc/Hz at 1 Hz, 10 Hz, 1 kHz, and 10 kHz offset frequencies, respectively (see Figure 10b). Comparing Figure 10c and Figure 10b, it is evident that the phase noise performance exhibits an improvement of approximately 40 dB around the 1 Hz offset frequency at a carrier frequency of 200 MHz. In PLL1, a narrow-loop bandwidth of around 150 Hz was employed to suppress higher offset frequency phase noise while ensuring low phase noise performance for PLL2. As a result, PLL2 can operate with a moderate loop bandwidth of 300 kHz.  
Figure 10: Absolute phase noise measurement. (**a**) 10 MHz OCXO, (**b**) 200 MHz phase locked to 10 MHz, (**c**) 200 MHz OCXO free running, (**d**) 9.192 GHz phase locked to 10 MHz, (**e**) free-running DRO.  
Figure 9: Comparison of phase step response measurements. \(\tau_{1}\) is maintained at \(2\times 10^{-4}\) s. The subfigures are labeled as follows: (**a**) \(k_{p1}=2\); (**b**) \(k_{p1}=8/3\); (**c**) \(k_{p1}=10/3\); (**d**) \(k_{p1}=4\); The simulation results are depicted using dotted lines, and the measurement results are denoted by solid lines.  
The selection of the loop bandwidth for PLL2 aims to combine the superior high-offset frequency phase noise characteristics of the DRO with the favorable low-offset frequency phase noise of the 200 MHz OCXO. When the DRO operates in a free-running state as depicted in Figure 10e, the phase noises are recorded as \(-66.2\) dBc/Hz and \(-88.3\) dBc/Hz at 1 kHz and 10 kHz offsets, respectively. Figure 10d illustrates the phase noises at 9.192 GHz when the frequency synthesis chain is locked, which are measured as \(-63.7\) dBc/Hz, \(-75.7\) dBc/Hz, \(-107.1\) dBc/Hz, and \(-122.5\) dBc/Hz at 1 Hz, 10 Hz, 1 kHz, and 10 kHz offset frequencies, respectively. Our absolute phase noise performance has an advantage, especially at the frequency offset of 1 Hz. However, for the phase noise of the frequency synthesizer, it should be evaluated based on the actual deterioration degree, using the reference source as a benchmark. Notably, from Figure 10e, it can be observed that the phase noises at 1 Hz and 10 Hz offsets, with a carrier frequency of 9.192 GHz, are only 0.8 dB and 2.5 dB worse than the 20 logN rule derived from the 10 MHz reference source. Consequently, the frequency synthesizer demonstrates favorable phase noise performance at low offset frequencies below 150 Hz.  
In Figure 10d, the phase noise plot exhibits two inflection points around the offset frequencies corresponding to the two loop bandwidths. By appropriately increasing the loop bandwidths of both PLLs, a significant improvement in the phase noise performance can be achieved for offset frequencies lower than the bandwidths. However, a higher loop bandwidth results in more accumulated noise. Therefore, both loop bandwidths in the frequency synthesizer should be selected appropriately.