## 4 Light Sources  
The tight electro-optical integration concept of the switch matrix, as depicted in Figure 2, greatly profits from a monolithic co-integration of the light sources. Though external light sources might be feasible, a direct co-integration provides a much simplified and leaner assembly. Light is generated at the position in the matrix where it is required, in the unit cell depicted in Figure 5. For the co-integration of the light source and the gain material, we explored a novel approach that goes beyond today's established III-V on silicon photonics concepts [23]. We embed the III-V layer in between the front- and back-end of the line of the silicon stack while the laser feedback structures are integrated into the silicon waveguide layer [24]. This will enable a monolithic co-integration of passive and active photonic functions together with electrical (Bi)CMOS circuits. Several requirements need to be fulfilled to establish a truly CMOS embedded III-V on silicon technology. First, the materials involved must be CMOS compatible. We, therefore, established gold-free electrical contacts to the gain medium [25]. The additional processes related to the integration of the laser must be CMOS compatible. This is especially challenging with respect to the temperature, which should not exceed 600 \({}^{\circ}\)C for more than 2 min [26]. This led to our choice to integrate the III-V layer by bonding. Furthermore, the CMOS embedded laser concept puts hard boundary conditions on the geometry. As the III-V gain layer is integrated on top of the first dielectric layer in the back-end-of-the-line stack, its thickness should not exceed  
Figure 12: (**a**) The experimental testbed developed to interface with the L3 MATRIX technology. (**b–e**) The experimental channel response of (**b**) input #1 and (**c**) input #2 of the 2 \(\times\) 6 Echelle grating, followed by the response of (**d**) input #1 and (**e**) input #2 of the 2 \(\times\) 4 configurations, respectively. The layout of the Echelle grating is shown in (**f**), where the diffractive grating is visible on the right side of the free space area. The sharp spikes reduce spurious reflections and so help to minimize the crosstalk. (**g,h**) Optical micrographs of the L3 MATRIX Echelle gratings; inset of (**g**) shows an SEM image of the region indicated by the green rectangle. about 200 nm. This has severe consequences for the electrical pumping scheme of the lasers, as indicated in Figure 13.  
Figure 13a shows a vertical current injection scheme. As the III-V stack has a thickness of only 200 nm, the top electrical contacts are moved to the edge of the mesa to avoid absorption of the optical mode. With this structure, we could demonstrate optically and electrically pumped lasers. The latter work only at low temperatures of 100 K. As indicated  
Figure 13: (**a**) The vertical current injection scheme for thin III–V layers integrated on silicon. (**b**) The vertical scheme leads to some recombination of the carriers at the edges of the mesa and insufficient overlap with the optical mode. (**c**) Lateral current injection scheme. In (**d**), we show the high-level process flow for realizing the III–V on silicon lasers. The silicon chip with the passive photonic structures is planarized by chemical mechanical polishing. Then, the InP wafer with the gain quantum-well stack is bonded to the silicon wafer. The InP wafer is removed, the III–V gain sections are etched, and finally, the electrical contacts are applied. by the arrows, a challenge emerges to sustain confinement of the optical mode and the carriers in the center of the structure, which is essential for efficient pumping and high gain [24]. As a result, carriers tend to recombine at the edge of the mesa, thus leading to insufficient gain, which suppresses room temperature (RT) lasing (Figure 13b). Oxidation of the aluminum-containing layers in the quantum well stack, a method successfully applied for vertical cavity surface-emitting lasers, appears to be not reproducible.