Repository: veryl-lang/veryl (Rust)

Issue:
Emit let declaration into single line
let declaration are emitted by variable declaration and assign declaration into two lines.
When there are many continuous let declarations, it may be hard to see.

* Veryl

```systemverilog
let a: logic = 1;
let b: logic = 1;
let c: logic = 1;
```

* Generated SV

```systemverilog
logic a;
always_comb a = 1;
logic b;
always_comb b = 1;
logic c;
always_comb c = 1;
```

The following format seems to be better.

```systemverilog
logic a; always_comb a = 1;
logic b; always_comb b = 1;
logic c; always_comb c = 1;
```


Discussion:

Patch:
diff --git a/crates/emitter/src/emitter.rs b/crates/emitter/src/emitter.rs
index c34ddc8fc..ba1417629 100644
--- a/crates/emitter/src/emitter.rs
+++ b/crates/emitter/src/emitter.rs
@@ -2477,7 +2477,7 @@ impl VerylWalker for Emitter {
         }
         self.align_finish(align_kind::ARRAY);
         self.str(";");
-        self.newline();
+        self.space(1);
         if is_tri {
             self.str("assign");
         } else {


Test patch:
diff --git a/crates/emitter/src/tests.rs b/crates/emitter/src/tests.rs
index 02cf219a0..0b4f7a853 100644
--- a/crates/emitter/src/tests.rs
+++ b/crates/emitter/src/tests.rs
@@ -62,10 +62,8 @@ module ModuleB (
         .rst_high_rst_rst_high (rst_high_rst_rst_high)
     );
 
-    logic _a;
-    always_comb _a = clk_pos_clk_clk_pos;
-    logic _b;
-    always_comb _b = rst_high_rst_rst_high;
+    logic _a; always_comb _a = clk_pos_clk_clk_pos;
+    logic _b; always_comb _b = rst_high_rst_rst_high;
 
     logic _c;
     always_ff @ (posedge clk_pos_clk_clk_pos, posedge rst_high_rst_rst_high) begin
@@ -143,10 +141,8 @@ module ModuleB (
         .rst_low_rst_rst_low (rst_low_rst_rst_low)
     );
 
-    logic _a;
-    always_comb _a = clk_neg_clk_clk_neg;
-    logic _b;
-    always_comb _b = rst_low_rst_rst_low;
+    logic _a; always_comb _a = clk_neg_clk_clk_neg;
+    logic _b; always_comb _b = rst_low_rst_rst_low;
 
     logic _c;
     always_ff @ (negedge clk_neg_clk_clk_neg) begin
@@ -252,8 +248,7 @@ fn expand_case_statement() {
     localparam bit y = 1;
 
     logic a;
-    logic x;
-    always_comb x = 1;
+    logic x; always_comb x = 1;
 
     always_comb begin
         case (1'b1)
@@ -342,8 +337,7 @@ fn expand_case_expression() {
 "#;
 
     let expect = r#"module ModuleA;
-    logic a;
-    always_comb a = 1;
+    logic a; always_comb a = 1;
     logic b;
 
     always_comb b = (((a) ==? (1)) ? (
@@ -397,14 +391,10 @@ fn async_reset_cast() {
     logic b;
     logic c;
 
-    logic d;
-    always_comb d = a;
-    logic e;
-    always_comb e = ~a;
-    logic f;
-    always_comb f = b;
-    logic g;
-    always_comb g = ~c;
+    logic d; always_comb d = a;
+    logic e; always_comb e = ~a;
+    logic f; always_comb f = b;
+    logic g; always_comb g = ~c;
 endmodule
 //# sourceMappingURL=test.sv.map
 "#;
@@ -442,14 +432,10 @@ fn sync_reset_cast() {
     logic b;
     logic c;
 
-    logic d;
-    always_comb d = ~a;
-    logic e;
-    always_comb e = a;
-    logic f;
-    always_comb f = ~b;
-    logic g;
-    always_comb g = c;
+    logic d; always_comb d = ~a;
+    logic e; always_comb e = a;
+    logic f; always_comb f = ~b;
+    logic g; always_comb g = c;
 endmodule
 //# sourceMappingURL=test.sv.map
 "#;
@@ -555,8 +541,7 @@ fn emit_cond_type() {
     input logic i_clk,
     input logic i_rst
 );
-    logic x;
-    always_comb x = 1;
+    logic x; always_comb x = 1;
     logic a;
     logic b;
     logic c;
diff --git a/testcases/map/testcases/sv/02_builtin_type.sv.map b/testcases/map/testcases/sv/02_builtin_type.sv.map
index 3fbe44c49..c07859d13 100644
--- a/testcases/map/testcases/sv/02_builtin_type.sv.map
+++ b/testcases/map/testcases/sv/02_builtin_type.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"02_builtin_type.sv.map","sources":["../../../veryl/02_builtin_type.veryl"],"names":["","module","Module02",";","int unsigned","_a","=","1","longint unsigned","_aa","int signed","_b","longint signed","_bb","shortreal","_c","real","_cc","logic","_d","[","10","]","_dd","][","_ddd","bit","_e","_ee","_eee","_f","2","'{",",","}","_ff","_fff","_ffff","_fffff","_ffffff","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;;IAEHC,iBAALC;mBAASC,EAAEC,CAACJ;IACPK,iBAALC;oBAASH,EAAEC,CAACJ;;;IAGPO,eAALC;mBAASL,EAAEC,CAACJ;IACPS,eAALC;oBAASP,EAAEC,CAACJ;;;IAGPW,UAALC;mBAAST,EAAEC,CAACJ;IACPa,UAALC;oBAASX,EAAEC,CAACJ;;;IAGNe,uBAANC;mBAAoBb,EAAEC,CAACJ;IACjBe,MAAKE,CAACC,MAAEC,UAAdC;oBAAoBjB,EAAEC,CAACJ;IACjBe,MAAKE,CAACC,MAAEG,EAAEH,MAAEC,EAAlBG;qBAAoBnB,EAAEC,CAACJ;;;IAGjBuB,qBAANC;mBAAkBrB,EAAEC,CAACJ;IACfuB,IAAGN,CAACC,MAAEC,UAAZM;oBAAkBtB,EAAEC,CAACJ;IACfuB,IAAGN,CAACC,MAAEG,EAAEH,MAAEC,EAAhBO;qBAAkBvB,EAAEC,CAACJ;;;IAGZC,iBAAT0B,QAAaV,GAACW,GAACT;mBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBK,iBAAT2B,QAAaf,GAACW,GAACT;oBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBO,iBAAT0B,QAAahB,GAACW,GAACT;qBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBS,iBAATyB,QAAajB,GAACW,GAACT;sBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBW,iBAATwB,QAAalB,GAACW,GAACT;uBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBa,iBAATuB,QAAanB,GAACW,GAACT;wBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;AAClCqC"}
\ No newline at end of file
+{"version":3,"file":"02_builtin_type.sv.map","sources":["../../../veryl/02_builtin_type.veryl"],"names":["","module","Module02",";","int unsigned","_a","=","1","longint unsigned","_aa","int signed","_b","longint signed","_bb","shortreal","_c","real","_cc","logic","_d","[","10","]","_dd","][","_ddd","bit","_e","_ee","_eee","_f","2","'{",",","}","_ff","_fff","_ffff","_fffff","_ffffff","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;;IAEHC,iBAALC,oBAASC,EAAEC,CAACJ;IACPK,iBAALC,qBAASH,EAAEC,CAACJ;;;IAGPO,eAALC,oBAASL,EAAEC,CAACJ;IACPS,eAALC,qBAASP,EAAEC,CAACJ;;;IAGPW,UAALC,oBAAST,EAAEC,CAACJ;IACPa,UAALC,qBAASX,EAAEC,CAACJ;;;IAGNe,uBAANC,qBAAoBb,EAAEC,CAACJ;IACjBe,MAAKE,CAACC,MAAEC,UAAdC,sBAAoBjB,EAAEC,CAACJ;IACjBe,MAAKE,CAACC,MAAEG,EAAEH,MAAEC,EAAlBG,uBAAoBnB,EAAEC,CAACJ;;;IAGjBuB,qBAANC,qBAAkBrB,EAAEC,CAACJ;IACfuB,IAAGN,CAACC,MAAEC,UAAZM,sBAAkBtB,EAAEC,CAACJ;IACfuB,IAAGN,CAACC,MAAEG,EAAEH,MAAEC,EAAhBO,uBAAkBvB,EAAEC,CAACJ;;;IAGZC,iBAAT0B,QAAaV,GAACW,GAACT,kBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBK,iBAAT2B,QAAaf,GAACW,GAACT,mBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBO,iBAAT0B,QAAahB,GAACW,GAACT,oBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBS,iBAATyB,QAAajB,GAACW,GAACT,qBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBW,iBAATwB,QAAalB,GAACW,GAACT,sBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;IACjBa,iBAATuB,QAAanB,GAACW,GAACT,uBAAEhB,EAAE0B,EAAEzB,CAAC0B,EAAE1B,CAAC2B,CAAC/B;AAClCqC"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/03_operator.sv.map b/testcases/map/testcases/sv/03_operator.sv.map
index 2ccefe5a1..94488c341 100644
--- a/testcases/map/testcases/sv/03_operator.sv.map
+++ b/testcases/map/testcases/sv/03_operator.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"03_operator.sv.map","sources":["../../../veryl/03_operator.veryl"],"names":["","module","Module03",";","logic","_a","=","+","1","_aa","-","_b","!","_bb","~","_c","&","_cc","|","_ccc","^","_cccc","~&","_ccccc","~|","_cccccc","~^","_ccccccc","^~","_d","**","_dd","*","_ddd","/","_dddd","%","_ddddd","_dddddd","_e","<<","_ee",">>","_eee","<<<","_eeee",">>>","_f","_ff","<=","_fff","_ffff",">=","_fffff","==","_ffffff","!=","_fffffff","===","_ffffffff","!==","_fffffffff","==?","_ffffffffff","!=?","_g","_gg","_ggg","_gggg","_ggggg","_h","&&","_hh","||","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;;IAEHC,MAALC;mBAAWC,EAAEC,CAACC,CAACL;IACVC,MAALK;oBAAWH,EAAEI,CAACF,CAACL;;;IAGVC,MAALO;mBAAWL,EAAEM,CAACJ,CAACL;IACVC,MAALS;oBAAWP,EAAEQ,CAACN,CAACL;;;IAGLC,MAAVW;mBAAgBT,EAAEU,CAACR,CAACL;IACVC,MAAVa;oBAAgBX,EAAEY,CAACV,CAACL;IACVC,MAAVe;qBAAgBb,EAAEc,CAACZ,CAACL;IACVC,MAAViB;sBAAgBf,EAAEgB,EAAEd,CAACL;IACXC,MAAVmB;uBAAgBjB,EAAEkB,EAAEhB,CAACL;IACXC,MAAVqB;wBAAgBnB,EAAEoB,EAAElB,CAACL;IACXC,MAAVuB;yBAAgBrB,EAAEsB,EAAEpB,CAACL;;;IAGZC,MAATyB;mBAAevB,EAAEE,EAAEsB,GAAGtB,CAACL;IACdC,MAAT2B;oBAAezB,EAAEE,EAAEwB,EAAExB,CAACL;IACbC,MAAT6B;qBAAe3B,EAAEE,EAAE0B,EAAE1B,CAACL;IACbC,MAAT+B;sBAAe7B,EAAEE,EAAE4B,EAAE5B,CAACL;IACbC,MAATiC;uBAAe/B,EAAEE,EAAED,EAAEC,CAACL;IACbC,MAATkC;wBAAehC,EAAEE,EAAEE,EAAEF,CAACL;;;IAGfC,MAAPmC;mBAAajC,EAAEE,EAAEgC,GAAGhC,CAACL;IACdC,MAAPqC;oBAAanC,EAAEE,EAAEkC,GAAGlC,CAACL;IACdC,MAAPuC;qBAAarC,EAAEE,EAAEoC,IAAIpC,CAACL;IACfC,MAAPyC;sBAAavC,EAAEE,EAAEsC,IAAItC,CAACL;;;IAGTC,MAAb2C;mBAAmBzC,EAAEE,IAAKA,CAACL;IACdC,MAAb4C;oBAAmB1C,EAAEE,EAAEyC,GAAGzC,CAACL;IACdC,MAAb8C;qBAAmB5C,EAAEE,IAAKA,CAACL;IACdC,MAAb+C;sBAAmB7C,EAAEE,EAAE4C,GAAG5C,CAACL;IACdC,MAAbiD;uBAAmB/C,EAAEE,EAAE8C,GAAG9C,CAACL;IACdC,MAAbmD;wBAAmBjD,EAAEE,EAAEgD,GAAGhD,CAACL;IACdC,MAAbqD;yBAAmBnD,EAAEE,EAAEkD,IAAIlD,CAACL;IACfC,MAAbuD;0BAAmBrD,EAAEE,EAAEoD,IAAIpD,CAACL;IACfC,MAAbyD;2BAAmBvD,EAAEE,EAAEsD,IAAItD,CAACL;IACfC,MAAb2D;4BAAmBzD,EAAEE,EAAEwD,IAAIxD,CAACL;;;IAGpBC,MAAR6D;mBAAc3D,EAAEE,EAAEQ,EAAER,CAACL;IACbC,MAAR8D;oBAAc5D,EAAEE,EAAEY,EAAEZ,CAACL;IACbC,MAAR+D;qBAAc7D,EAAEE,EAAEkB,GAAGlB,CAACL;IACdC,MAARgE;sBAAc9D,EAAEE,EAAEoB,GAAGpB,CAACL;IACdC,MAARiE;uBAAc/D,EAAEE,EAAEU,EAAEV,CAACL;;;IAGhBC,MAALkE;mBAAWhE,EAAEE,EAAE+D,GAAG/D,CAACL;IACdC,MAALoE;oBAAWlE,EAAEE,EAAEiE,GAAGjE,CAACL;AAC3BuE"}
\ No newline at end of file
+{"version":3,"file":"03_operator.sv.map","sources":["../../../veryl/03_operator.veryl"],"names":["","module","Module03",";","logic","_a","=","+","1","_aa","-","_b","!","_bb","~","_c","&","_cc","|","_ccc","^","_cccc","~&","_ccccc","~|","_cccccc","~^","_ccccccc","^~","_d","**","_dd","*","_ddd","/","_dddd","%","_ddddd","_dddddd","_e","<<","_ee",">>","_eee","<<<","_eeee",">>>","_f","_ff","<=","_fff","_ffff",">=","_fffff","==","_ffffff","!=","_fffffff","===","_ffffffff","!==","_fffffffff","==?","_ffffffffff","!=?","_g","_gg","_ggg","_gggg","_ggggg","_h","&&","_hh","||","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;;IAEHC,MAALC,oBAAWC,EAAEC,CAACC,CAACL;IACVC,MAALK,qBAAWH,EAAEI,CAACF,CAACL;;;IAGVC,MAALO,oBAAWL,EAAEM,CAACJ,CAACL;IACVC,MAALS,qBAAWP,EAAEQ,CAACN,CAACL;;;IAGLC,MAAVW,yBAAgBT,EAAEU,CAACR,CAACL;IACVC,MAAVa,0BAAgBX,EAAEY,CAACV,CAACL;IACVC,MAAVe,2BAAgBb,EAAEc,CAACZ,CAACL;IACVC,MAAViB,4BAAgBf,EAAEgB,EAAEd,CAACL;IACXC,MAAVmB,6BAAgBjB,EAAEkB,EAAEhB,CAACL;IACXC,MAAVqB,8BAAgBnB,EAAEoB,EAAElB,CAACL;IACXC,MAAVuB,+BAAgBrB,EAAEsB,EAAEpB,CAACL;;;IAGZC,MAATyB,wBAAevB,EAAEE,EAAEsB,GAAGtB,CAACL;IACdC,MAAT2B,yBAAezB,EAAEE,EAAEwB,EAAExB,CAACL;IACbC,MAAT6B,0BAAe3B,EAAEE,EAAE0B,EAAE1B,CAACL;IACbC,MAAT+B,2BAAe7B,EAAEE,EAAE4B,EAAE5B,CAACL;IACbC,MAATiC,4BAAe/B,EAAEE,EAAED,EAAEC,CAACL;IACbC,MAATkC,6BAAehC,EAAEE,EAAEE,EAAEF,CAACL;;;IAGfC,MAAPmC,sBAAajC,EAAEE,EAAEgC,GAAGhC,CAACL;IACdC,MAAPqC,uBAAanC,EAAEE,EAAEkC,GAAGlC,CAACL;IACdC,MAAPuC,wBAAarC,EAAEE,EAAEoC,IAAIpC,CAACL;IACfC,MAAPyC,yBAAavC,EAAEE,EAAEsC,IAAItC,CAACL;;;IAGTC,MAAb2C,4BAAmBzC,EAAEE,IAAKA,CAACL;IACdC,MAAb4C,6BAAmB1C,EAAEE,EAAEyC,GAAGzC,CAACL;IACdC,MAAb8C,8BAAmB5C,EAAEE,IAAKA,CAACL;IACdC,MAAb+C,+BAAmB7C,EAAEE,EAAE4C,GAAG5C,CAACL;IACdC,MAAbiD,gCAAmB/C,EAAEE,EAAE8C,GAAG9C,CAACL;IACdC,MAAbmD,iCAAmBjD,EAAEE,EAAEgD,GAAGhD,CAACL;IACdC,MAAbqD,kCAAmBnD,EAAEE,EAAEkD,IAAIlD,CAACL;IACfC,MAAbuD,mCAAmBrD,EAAEE,EAAEoD,IAAIpD,CAACL;IACfC,MAAbyD,oCAAmBvD,EAAEE,EAAEsD,IAAItD,CAACL;IACfC,MAAb2D,qCAAmBzD,EAAEE,EAAEwD,IAAIxD,CAACL;;;IAGpBC,MAAR6D,uBAAc3D,EAAEE,EAAEQ,EAAER,CAACL;IACbC,MAAR8D,wBAAc5D,EAAEE,EAAEY,EAAEZ,CAACL;IACbC,MAAR+D,yBAAc7D,EAAEE,EAAEkB,GAAGlB,CAACL;IACdC,MAARgE,0BAAc9D,EAAEE,EAAEoB,GAAGpB,CAACL;IACdC,MAARiE,2BAAc/D,EAAEE,EAAEU,EAAEV,CAACL;;;IAGhBC,MAALkE,oBAAWhE,EAAEE,EAAE+D,GAAG/D,CAACL;IACdC,MAALoE,qBAAWlE,EAAEE,EAAEiE,GAAGjE,CAACL;AAC3BuE"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/04_module.sv.map b/testcases/map/testcases/sv/04_module.sv.map
index aca2e2ecb..9f44e64a2 100644
--- a/testcases/map/testcases/sv/04_module.sv.map
+++ b/testcases/map/testcases/sv/04_module.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"04_module.sv.map","sources":["../../../veryl/04_module.veryl"],"names":["","module","Module04","#","(","parameter","int unsigned","a","=","1",",","localparam","aa","type","aaa","logic","[","10","]",")","input","b","output","bb","inout","tri","bbb","interface","bbbb","veryl_testcase_Interface04.d","bbbbb",";","c","longint unsigned","cc","_d","_dd","bit","][","_ddd","always_comb","0","assign","endmodule","Interface04","modport","d","endinterface"],"mappings":"AAAAA;AACAC,sBAAOC,SAASC,CAACC;;IAEbC,WAAWC,aAALC,IAAUC,EAAEC,cAASC;IAC3BC,WAAWL,aAALM,IAAUJ,EAAEC,cAASC;IAC3BC,WAAWE,aAALC,IAAUN,EAAEO,MAAKC,CAACC,MAAEC,CAAClB;AAC/BmB,EAAEf;;IAESgB,OAAOL,UAASC,CAACC,MAAEC,EAA1BG,KAA2BX;IACpBY,OAAOP,UAASC,CAACC,MAAEC,EAA1BK,KAA2Bb;IACpBc,OAAOC,IAAIV,MAAKC,CAACC,MAAEC,EAA1BQ,KAA2BhB;IACpBiB,UAAPC,KAAgBlB;IACDmB,6BAAfC,KAA6B9B;AACjCmB,CAAEY;;IAEEpB,WAAUL,iBAAJ0B,GAAQxB,EAAEC,CAACsB;IACjBpB,WAAUsB,iBAAJC,GAAQ1B,EAAEC,CAACsB;;;IAGPhB,uBAANoB;mBAAoB3B,EAAEC,CAACsB;IACjBhB,MAAKC,CAACC,MAAEC,UAAdkB;oBAAoB5B,EAAEC,CAACsB;IACjBM,MAAKrB,CAACC,MAAEqB,EAAErB,MAAEC,EAAlBqB;qBAAoB/B,EAAEC,CAACsB;;IAE3BS,YAAOjB,IAAIf,EAAEiC,CAACV;IACdW,OAAOhB,IAAIlB,EAAEiC,CAACV;AAClBY;;AAEAhB,yBAAUiB,WAAYb;IACXhB,MAAHiB,CAAQD;;IAEZc,QAAQC,EAAE1C;QACHgB,MAAHY,CAAQhC;IACZmB;AACJ4B"}
\ No newline at end of file
+{"version":3,"file":"04_module.sv.map","sources":["../../../veryl/04_module.veryl"],"names":["","module","Module04","#","(","parameter","int unsigned","a","=","1",",","localparam","aa","type","aaa","logic","[","10","]",")","input","b","output","bb","inout","tri","bbb","interface","bbbb","veryl_testcase_Interface04.d","bbbbb",";","c","longint unsigned","cc","_d","_dd","bit","][","_ddd","always_comb","0","assign","endmodule","Interface04","modport","d","endinterface"],"mappings":"AAAAA;AACAC,sBAAOC,SAASC,CAACC;;IAEbC,WAAWC,aAALC,IAAUC,EAAEC,cAASC;IAC3BC,WAAWL,aAALM,IAAUJ,EAAEC,cAASC;IAC3BC,WAAWE,aAALC,IAAUN,EAAEO,MAAKC,CAACC,MAAEC,CAAClB;AAC/BmB,EAAEf;;IAESgB,OAAOL,UAASC,CAACC,MAAEC,EAA1BG,KAA2BX;IACpBY,OAAOP,UAASC,CAACC,MAAEC,EAA1BK,KAA2Bb;IACpBc,OAAOC,IAAIV,MAAKC,CAACC,MAAEC,EAA1BQ,KAA2BhB;IACpBiB,UAAPC,KAAgBlB;IACDmB,6BAAfC,KAA6B9B;AACjCmB,CAAEY;;IAEEpB,WAAUL,iBAAJ0B,GAAQxB,EAAEC,CAACsB;IACjBpB,WAAUsB,iBAAJC,GAAQ1B,EAAEC,CAACsB;;;IAGPhB,uBAANoB,qBAAoB3B,EAAEC,CAACsB;IACjBhB,MAAKC,CAACC,MAAEC,UAAdkB,sBAAoB5B,EAAEC,CAACsB;IACjBM,MAAKrB,CAACC,MAAEqB,EAAErB,MAAEC,EAAlBqB,uBAAoB/B,EAAEC,CAACsB;;IAE3BS,YAAOjB,IAAIf,EAAEiC,CAACV;IACdW,OAAOhB,IAAIlB,EAAEiC,CAACV;AAClBY;;AAEAhB,yBAAUiB,WAAYb;IACXhB,MAAHiB,CAAQD;;IAEZc,QAAQC,EAAE1C;QACHgB,MAAHY,CAAQhC;IACZmB;AACJ4B"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/06_function.sv.map b/testcases/map/testcases/sv/06_function.sv.map
index 1d3580977..53821fd6c 100644
--- a/testcases/map/testcases/sv/06_function.sv.map
+++ b/testcases/map/testcases/sv/06_function.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"06_function.sv.map","sources":["../../../veryl/06_function.veryl"],"names":["","module","Module06",";","localparam","int unsigned","ParamX","=","1","function","logic","[","]","FuncA","(","input","a",",","output","b","ref","c",")","d","+","/","return","2","endfunction","FuncC","e","f","always_comb","initial","begin","end","$clog2","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAAcC,aAARC,OAAYC,EAAEC,CAACL;;;IAGrBM,mBAIKC,MAAKC,CAACL,UAAMM,EAJRC,KAAMC;QACRC,OAAOL,MAAKC,CAACL,UAAMM,EAAtBI,CAAuBC;QACpBC,OAAOR,MAAKC,CAACL,UAAMM,EAAtBO,CAAuBF;QACpBG,OAAOV,MAAKC,CAACL,UAAMM,EAAtBS,CAAuBrB;IAC3BsB,EAAEtB,CAAiBA;QACRK,aAAHkB;UAAOhB,EAAEC,CAACL;QACdgB,EAAEZ,EAAES,EAAEQ,EAAEhB,EAAEgB,EAAED,CAACpB;QACbkB,EAAEd,EAAES,EAAES,EAAEjB,CAACL;QACTuB,OAAOV,EAAEQ,EAAEG,CAACxB;IAChByB;;;IAGAnB,wBAASoB,KAAMf;QACRC,MAAML,MAAKC,CAACL,UAAMM,EAArBI,CAAsBC;QACnBG,MAAMV,MAAKC,CAACL,UAAMM,EAArBS,CAAsBrB;IAC1BsB,GAAEtB;QACEqB,EAAEd,EAAES,EAAES,EAAEjB,CAACL;IACbyB;;IAEOlB,MAAKC,CAACL,UAAMM,EAAfI;kBAAiBT,EAAEC,CAACL;IACjBO,MAAKC,CAACL,UAAMM,EAAfO,CAAgBhB;IACbO,MAAKC,CAACL,UAAMM,EAAfS,CAAgBlB;IACbO,MAAKC,CAACL,UAAMM,EAAfW,CAAgBpB;IACbO,MAAKC,CAACL,UAAMM,EAAfkB,CAAgB3B;IACbO,MAAKC,CAACL,UAAMM,EAAfmB,CAAgB5B;;;IAGpB6B,YAAOT,EAAEhB,EAAEM,KAAKC,CAACE,CAACC,EAAEE,CAACF,EAAEI,CAACC,CAACnB;;;IAGzB8B,QAAQC;QACJL,KAAKf,CAACE,CAACC,EAAEa,CAACR,CAACnB;IACfgC;;;IAGAH,YAAOD,EAAExB,EAAE6B,MAAMtB,CAACE,CAACM,CAACnB;AACxBkC"}
\ No newline at end of file
+{"version":3,"file":"06_function.sv.map","sources":["../../../veryl/06_function.veryl"],"names":["","module","Module06",";","localparam","int unsigned","ParamX","=","1","function","logic","[","]","FuncA","(","input","a",",","output","b","ref","c",")","d","+","/","return","2","endfunction","FuncC","e","f","always_comb","initial","begin","end","$clog2","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAAcC,aAARC,OAAYC,EAAEC,CAACL;;;IAGrBM,mBAIKC,MAAKC,CAACL,UAAMM,EAJRC,KAAMC;QACRC,OAAOL,MAAKC,CAACL,UAAMM,EAAtBI,CAAuBC;QACpBC,OAAOR,MAAKC,CAACL,UAAMM,EAAtBO,CAAuBF;QACpBG,OAAOV,MAAKC,CAACL,UAAMM,EAAtBS,CAAuBrB;IAC3BsB,EAAEtB,CAAiBA;QACRK,aAAHkB;UAAOhB,EAAEC,CAACL;QACdgB,EAAEZ,EAAES,EAAEQ,EAAEhB,EAAEgB,EAAED,CAACpB;QACbkB,EAAEd,EAAES,EAAES,EAAEjB,CAACL;QACTuB,OAAOV,EAAEQ,EAAEG,CAACxB;IAChByB;;;IAGAnB,wBAASoB,KAAMf;QACRC,MAAML,MAAKC,CAACL,UAAMM,EAArBI,CAAsBC;QACnBG,MAAMV,MAAKC,CAACL,UAAMM,EAArBS,CAAsBrB;IAC1BsB,GAAEtB;QACEqB,EAAEd,EAAES,EAAES,EAAEjB,CAACL;IACbyB;;IAEOlB,MAAKC,CAACL,UAAMM,EAAfI,iBAAiBT,EAAEC,CAACL;IACjBO,MAAKC,CAACL,UAAMM,EAAfO,CAAgBhB;IACbO,MAAKC,CAACL,UAAMM,EAAfS,CAAgBlB;IACbO,MAAKC,CAACL,UAAMM,EAAfW,CAAgBpB;IACbO,MAAKC,CAACL,UAAMM,EAAfkB,CAAgB3B;IACbO,MAAKC,CAACL,UAAMM,EAAfmB,CAAgB5B;;;IAGpB6B,YAAOT,EAAEhB,EAAEM,KAAKC,CAACE,CAACC,EAAEE,CAACF,EAAEI,CAACC,CAACnB;;;IAGzB8B,QAAQC;QACJL,KAAKf,CAACE,CAACC,EAAEa,CAACR,CAACnB;IACfgC;;;IAGAH,YAAOD,EAAExB,EAAE6B,MAAMtB,CAACE,CAACM,CAACnB;AACxBkC"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/07_statement.sv.map b/testcases/map/testcases/sv/07_statement.sv.map
index 8e0bc03cd..1ae659cf7 100644
--- a/testcases/map/testcases/sv/07_statement.sv.map
+++ b/testcases/map/testcases/sv/07_statement.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"07_statement.sv.map","sources":["../../../veryl/07_statement.veryl"],"names":["","module","Module07",";","logic","a","aa","clk","=","1","always_comb","begin","+=","-=","*=","/=","%=","&=","|=","^=","<<=",">>=","<<<=",">>>=","if","end","else","for","int unsigned","i","0","10","+","2","==","break","j","&&","always_ff","(",")","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACHC,MAALC,GAAUF;IACLC,MAALE,GAAUH;IACLC,MAALG;oBAAWC,EAAEC,CAACN;;IAElBO,YAAYC;;QAERN,EAAEG,KAAKC,CAACN;QACRE,EAAEO,KAAKH,CAACN;QACRE,EAAEQ,KAAKJ,CAACN;QACRE,EAAES,KAAKL,CAACN;QACRE,EAAEU,KAAKN,CAACN;QACRE,EAAEW,KAAKP,CAACN;QACRE,EAAEY,KAAKR,CAACN;QACRE,EAAEa,KAAKT,CAACN;QACRE,EAAEc,KAAKV,CAACN;QACRE,EAAEe,KAAKX,CAACN;QACRE,EAAEgB,KAAKZ,CAACN;QACRE,EAAEiB,KAAKb,CAACN;QACRE,EAAEkB,KAAKd,CAACN;;;QAGRqB,IAAGnB,GAAEM;YACDN,GAAGG,EAAEC,CAACN;YACNG,GAAGE,EAAEC,CAACN;QACVsB,IAAEC,KAAKF,IAAGnB,GAAEM;YACRN,GAAGG,EAAEC,CAACN;YACNG,GAAGE,EAAEC,CAACN;QACVsB,IAAEC,KAAKf;YACHN,GAAGG,EAAEC,CAACN;YACNG,GAAGE,EAAEC,CAACN;QACVsB;;;QAGAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,KAAgBlB;YAChBN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;QACdsB;;;QAGAE,KAAOC,aAAHC,IAAUC,GAAVD,KAAcE,IAAdF,KAAiBlB;YACjBN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;QACdsB;;;QAGAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,EAAqBjB,GAAGqB,GAAEtB;YAC1BN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;QACdsB;QACAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,EAAqBf,GAAGmB,GAAEtB;YAC1BN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;QACdsB;;;QAGAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,KAAgBlB;YAChBN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;YACVqB,IAAGK,EAAEK,GAAGJ,GAAEnB;gBACNwB,KAAKhC;YACTsB;QACJA;;QAEAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,KAAgBlB;YAChBgB,KAAOC,aAAHQ,IAAUN,GAAVM,IAAaL,IAAbK,KAAgBzB;gBAChBN,GAAGG,EAAEqB,CAAC1B;gBACNG,GAAGE,EAAEqB,EAAEG,EAAEI,CAACjC;gBACVqB,IAAGK,EAAEK,GAAGJ,EAAEO,GAAGD,EAAEF,GAAGJ,GAAEnB;oBAChBwB,KAAKhC;gBACTsB;YACJA;QACJA;IACJA;;IAEAa,YAAUC,SAAChC,GAAGiC,EAAE7B;QACZN,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,MAAOI,EAACN;QACRE,GAAEG,EAAFH,MAAOI,EAACN;QACRE,GAAEG,EAAFH,OAAOI,EAACN;QACRE,GAAEG,EAAFH,OAAOI,EAACN;IACZsB;AACJgB"}
\ No newline at end of file
+{"version":3,"file":"07_statement.sv.map","sources":["../../../veryl/07_statement.veryl"],"names":["","module","Module07",";","logic","a","aa","clk","=","1","always_comb","begin","+=","-=","*=","/=","%=","&=","|=","^=","<<=",">>=","<<<=",">>>=","if","end","else","for","int unsigned","i","0","10","+","2","==","break","j","&&","always_ff","(",")","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACHC,MAALC,GAAUF;IACLC,MAALE,GAAUH;IACLC,MAALG,qBAAWC,EAAEC,CAACN;;IAElBO,YAAYC;;QAERN,EAAEG,KAAKC,CAACN;QACRE,EAAEO,KAAKH,CAACN;QACRE,EAAEQ,KAAKJ,CAACN;QACRE,EAAES,KAAKL,CAACN;QACRE,EAAEU,KAAKN,CAACN;QACRE,EAAEW,KAAKP,CAACN;QACRE,EAAEY,KAAKR,CAACN;QACRE,EAAEa,KAAKT,CAACN;QACRE,EAAEc,KAAKV,CAACN;QACRE,EAAEe,KAAKX,CAACN;QACRE,EAAEgB,KAAKZ,CAACN;QACRE,EAAEiB,KAAKb,CAACN;QACRE,EAAEkB,KAAKd,CAACN;;;QAGRqB,IAAGnB,GAAEM;YACDN,GAAGG,EAAEC,CAACN;YACNG,GAAGE,EAAEC,CAACN;QACVsB,IAAEC,KAAKF,IAAGnB,GAAEM;YACRN,GAAGG,EAAEC,CAACN;YACNG,GAAGE,EAAEC,CAACN;QACVsB,IAAEC,KAAKf;YACHN,GAAGG,EAAEC,CAACN;YACNG,GAAGE,EAAEC,CAACN;QACVsB;;;QAGAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,KAAgBlB;YAChBN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;QACdsB;;;QAGAE,KAAOC,aAAHC,IAAUC,GAAVD,KAAcE,IAAdF,KAAiBlB;YACjBN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;QACdsB;;;QAGAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,EAAqBjB,GAAGqB,GAAEtB;YAC1BN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;QACdsB;QACAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,EAAqBf,GAAGmB,GAAEtB;YAC1BN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;QACdsB;;;QAGAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,KAAgBlB;YAChBN,GAAGG,EAAEqB,CAAC1B;YACNG,GAAGE,EAAEqB,EAAEG,EAAEvB,CAACN;YACVqB,IAAGK,EAAEK,GAAGJ,GAAEnB;gBACNwB,KAAKhC;YACTsB;QACJA;;QAEAE,KAAOC,aAAHC,IAAUC,GAAVD,IAAaE,IAAbF,KAAgBlB;YAChBgB,KAAOC,aAAHQ,IAAUN,GAAVM,IAAaL,IAAbK,KAAgBzB;gBAChBN,GAAGG,EAAEqB,CAAC1B;gBACNG,GAAGE,EAAEqB,EAAEG,EAAEI,CAACjC;gBACVqB,IAAGK,EAAEK,GAAGJ,EAAEO,GAAGD,EAAEF,GAAGJ,GAAEnB;oBAChBwB,KAAKhC;gBACTsB;YACJA;QACJA;IACJA;;IAEAa,YAAUC,SAAChC,GAAGiC,EAAE7B;QACZN,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,KAAOI,EAACN;QACRE,GAAEG,EAAFH,MAAOI,EAACN;QACRE,GAAEG,EAAFH,MAAOI,EAACN;QACRE,GAAEG,EAAFH,OAAOI,EAACN;QACRE,GAAEG,EAAFH,OAAOI,EAACN;IACZsB;AACJgB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/08_generate_declaration.sv.map b/testcases/map/testcases/sv/08_generate_declaration.sv.map
index 5c4402a33..c2791642b 100644
--- a/testcases/map/testcases/sv/08_generate_declaration.sv.map
+++ b/testcases/map/testcases/sv/08_generate_declaration.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"08_generate_declaration.sv.map","sources":["../../../veryl/08_generate_declaration.veryl"],"names":["","module","Module08",";","localparam","int unsigned","a","=","1","b","logic","i_clk","if","==","begin",":","label","always_ff","(",")","end","else","label1","for","i","0","10","label2","+=","2","label3","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAAaC,aAAPC,MAAaC,EAAEC,CAACL;IACtBC,WAAaC,aAAPI,MAAaF,EAAEC,CAACL;IACXO,aAAPC;sBAAaJ,EAAEC,CAACL;;;IAGpBS,IAAGN,EAAEO,GAAGL,GAASM,MAAPC,CAACC;QACAN,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEC,CAACL;QACTiB;IACJA,IAAEC,KAAKT,IAAGH,EAAEI,GAAGL,eAAER;QACNU,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEC,CAACL;QACTiB;IACJA,IAAEC,KAAKT,IAAGH,EAAEI,GAAGL,SAAEO,CAACO,MAAOtB;QACdU,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEC,CAACL;QACTiB;IACJA,IAAEC,iBAAKrB;QACIU,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEC,CAACL;QACTiB;IACJA;;;IAGAG,YAAIC,IAAKC,GAALD,IAAQE,IAARF,KAAmBV,MAARC,CAACY;QACLjB,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEiB,CAACrB;QACTiB;IACJA;;;IAGAG,YAAIC,IAAKC,GAALD,IAAQE,IAARF,EAAgBI,GAAGC,GAAUf,MAARC,CAACe;QACfpB,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEiB,CAACrB;QACTiB;IACJA;AACJW"}
\ No newline at end of file
+{"version":3,"file":"08_generate_declaration.sv.map","sources":["../../../veryl/08_generate_declaration.veryl"],"names":["","module","Module08",";","localparam","int unsigned","a","=","1","b","logic","i_clk","if","==","begin",":","label","always_ff","(",")","end","else","label1","for","i","0","10","label2","+=","2","label3","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAAaC,aAAPC,MAAaC,EAAEC,CAACL;IACtBC,WAAaC,aAAPI,MAAaF,EAAEC,CAACL;IACXO,aAAPC,yBAAaJ,EAAEC,CAACL;;;IAGpBS,IAAGN,EAAEO,GAAGL,GAASM,MAAPC,CAACC;QACAN,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEC,CAACL;QACTiB;IACJA,IAAEC,KAAKT,IAAGH,EAAEI,GAAGL,eAAER;QACNU,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEC,CAACL;QACTiB;IACJA,IAAEC,KAAKT,IAAGH,EAAEI,GAAGL,SAAEO,CAACO,MAAOtB;QACdU,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEC,CAACL;QACTiB;IACJA,IAAEC,iBAAKrB;QACIU,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEC,CAACL;QACTiB;IACJA;;;IAGAG,YAAIC,IAAKC,GAALD,IAAQE,IAARF,KAAmBV,MAARC,CAACY;QACLjB,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEiB,CAACrB;QACTiB;IACJA;;;IAGAG,YAAIC,IAAKC,GAALD,IAAQE,IAARF,EAAgBI,GAAGC,GAAUf,MAARC,CAACe;QACfpB,MAAHJ,CAAQH;QACZc,YAAUC,SAACP,KAAKQ,EAAEL;YACdR,GAAEC,EAAEiB,CAACrB;QACTiB;IACJA;AACJW"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/11_let.sv.map b/testcases/map/testcases/sv/11_let.sv.map
index 5a8be32d4..283edbfcf 100644
--- a/testcases/map/testcases/sv/11_let.sv.map
+++ b/testcases/map/testcases/sv/11_let.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"11_let.sv.map","sources":["../../../veryl/11_let.veryl"],"names":["","module","Module11",";","logic","b","[","10","]","bb","bit","][","_bbb","=","1","_c","always_comb","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;;IAEFC,uBAANC,IAAmBF;IACbC,MAAKE,CAACC,MAAEC,UAAdC,IAAmBN;IACbO,MAAKJ,CAACC,MAAEI,EAAEJ,MAAEC,EAAlBI;qBAAoBC,EAAEC,CAACX;;;IAGnBC,MAAKE,CAACC,MAAEC,EAAZO;mBAAcF,EAAEC,CAACX;;;IAGrBa,YAAOX,GAAGQ,EAAEC,CAACX;IACba,YAAOP,GAAGI,EAAEC,CAACX;AACjBc"}
\ No newline at end of file
+{"version":3,"file":"11_let.sv.map","sources":["../../../veryl/11_let.veryl"],"names":["","module","Module11",";","logic","b","[","10","]","bb","bit","][","_bbb","=","1","_c","always_comb","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;;IAEFC,uBAANC,IAAmBF;IACbC,MAAKE,CAACC,MAAEC,UAAdC,IAAmBN;IACbO,MAAKJ,CAACC,MAAEI,EAAEJ,MAAEC,EAAlBI,uBAAoBC,EAAEC,CAACX;;;IAGnBC,MAAKE,CAACC,MAAEC,EAAZO,mBAAcF,EAAEC,CAACX;;;IAGrBa,YAAOX,GAAGQ,EAAEC,CAACX;IACba,YAAOP,GAAGI,EAAEC,CAACX;AACjBc"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/12_always.sv.map b/testcases/map/testcases/sv/12_always.sv.map
index 44d80a76f..7c035f7bd 100644
--- a/testcases/map/testcases/sv/12_always.sv.map
+++ b/testcases/map/testcases/sv/12_always.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"12_always.sv.map","sources":["../../../veryl/12_always.veryl"],"names":["","module","Module12_1","(","input","logic","i_clk",",","i_rst_n",")",";","a","b","c","always_ff","begin","if","=","0","end","else","~","endmodule","Module12_2","i_clk_p","i_clk_n","i_rst_ah","i_rst_al","i_rst_sh","i_rst_sl","aa","1","[","10","]","1'b0","5",":","d","for","i","g","e","int unsigned","always_comb","10'b0",".","10'b01z","+","16'hffff","*","3","/","4"],"mappings":"AAAAA,AAAAC,sBAAOC,WAAWC;IACPC,MAAMC,MAAbC,OAAkBC;IACXH,MAAMC,MAAbG,OAAkBR;AACtBS,CAAEC;IACSL,MAAHM,CAAQD;IACLL,MAAHO,CAAQF;IACLL,MAAHQ,CAAQH;;IAEZI,YAAUX,SAACG,sBAAKG,EAAEM;QACdC,cAASD;YACLF,GAAEI,EAAEC,CAACR;QACTS,IAAEC,KAAKL;YACHF,GAAEI,EAAEI,CAACV,CAACD;QACVS;IACJA;;IAEAL,6CAAUC;QACNC,cAASD;YACLJ,GAAEM,EAAEC,CAACR;QACTS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEI,CAACV,CAACD;QACVS;IACJA;;IAEAL,4BAAUC;QACNH,GAAEK,EAAEN,CAACD;IACTS;AACJG;;AAEArB,sBAAOsB,WAAWpB;IACJC,MAASC,MAAnBC,QAAmCC;IACzBH,MAASC,MAAnBmB,QAAmCjB;IACzBH,MAASC,MAAnBoB,QAAmClB;IACzBH,MAASC,MAAnBG,QAAmCD;IACzBH,MAASC,MAAnBqB,QAAmCnB;IACzBH,MAASC,MAAnBsB,QAAmCpB;IACzBH,MAASC,MAAnBuB,QAAmCrB;IACzBH,MAASC,MAAnBwB,QAAmC7B;AACvCS,CAAEC;IACUL,eAAJM,EAAaD;IACTL,eAAJyB,EAAapB;IACTL,eAAJO;kBAAcK,EAAEc,CAACrB;IACbL,MAAK2B,CAACC,MAAEC,EAAZrB;kBAAcI,EAAEc,CAACrB;;;IAGrBI,YAAUX,SAACG,KAAKC,UAAEC,OAAKC,EAAEM;QACrBC,cAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKJ,IAAGL,GAAEI;YACRJ,GAAEM,EAAEL,CAACoB,CAACd,CAACgB,CAACxB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;;;IAGAL,YAAUX,SAACG,KAAKG,EAAEM;QACdC,IAAGL,GAAEI;YACDJ,GAAEM,EAAEL,CAACF;QACTS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;;;IAGAL,YAAUX,SAACqB,OAAOjB,UAAEmB,QAAQjB,EAAEM;QAC1BC,cAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;IACAL,YAAUX,SAACsB,OAAOlB,UAAEoB,QAAQlB,EAAEM;QAC1BC,eAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;IACAL,YAAUX,SAACqB,OAAiBf,EAAEM;QAC1BC,cAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;IACAL,YAAUX,SAACsB,OAAiBhB,EAAEM;QAC1BC,eAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;;;IAGOd,MAAK2B,CAACC,MAAEC,EAAXI,CAAY5B;IAChB6B,YAAIC,IAAKtB,GAALsB,IAAQP,IAARO,KAAczB,MAAHsB,CAACI;QACZ3B,YAAUX,SAACG,KAAKC,UAAEC,OAAKC,EAAEM;YACrBC,cAASD;gBACLuB,CAACN,CAACQ,CAACN,GAAEjB,EAAEuB,CAAC9B;YACZS;QACJA;IACJA;;;IAGOd,MAAK2B,CAACC,MAAEC,EAAXQ,CAAYhC;IAChBI,YAAUX,SAACG,KAAKC,UAAEC,OAAKC,EAAEM;QACrBC,cAASD;YACLwB,KAAOI,aAAHH,IAAUtB,GAAVsB,IAAaP,IAAbO,KAAgBzB;gBAChB2B,CAACV,CAACQ,CAACN,GAAEjB,EAAEuB,CAAC9B;YACZS;QACJA;IACJA;;;IAGAyB,YAAY7B;QACRJ,KAAKM,EAAEgB,EAAEvB;QACToB,KAAKb,EAAE4B,KAAKnC;QACZoB,EAAEgB,CAACnC,EAAEM,EAAE8B,OAAOrC;;QAEdC,GAAGM,EAAEgB,GAAGe,EAAEf,EAAEvB;QACZoB,GAAGb,EAAEgB,GAAGe,EAAEC,SAASC,EAAE/C,CAACgD,EAAEC,EAAEC,CAAC5C,CAACC;IAChCS;AACJG"}
\ No newline at end of file
+{"version":3,"file":"12_always.sv.map","sources":["../../../veryl/12_always.veryl"],"names":["","module","Module12_1","(","input","logic","i_clk",",","i_rst_n",")",";","a","b","c","always_ff","begin","if","=","0","end","else","~","endmodule","Module12_2","i_clk_p","i_clk_n","i_rst_ah","i_rst_al","i_rst_sh","i_rst_sl","aa","1","[","10","]","1'b0","5",":","d","for","i","g","e","int unsigned","always_comb","10'b0",".","10'b01z","+","16'hffff","*","3","/","4"],"mappings":"AAAAA,AAAAC,sBAAOC,WAAWC;IACPC,MAAMC,MAAbC,OAAkBC;IACXH,MAAMC,MAAbG,OAAkBR;AACtBS,CAAEC;IACSL,MAAHM,CAAQD;IACLL,MAAHO,CAAQF;IACLL,MAAHQ,CAAQH;;IAEZI,YAAUX,SAACG,sBAAKG,EAAEM;QACdC,cAASD;YACLF,GAAEI,EAAEC,CAACR;QACTS,IAAEC,KAAKL;YACHF,GAAEI,EAAEI,CAACV,CAACD;QACVS;IACJA;;IAEAL,6CAAUC;QACNC,cAASD;YACLJ,GAAEM,EAAEC,CAACR;QACTS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEI,CAACV,CAACD;QACVS;IACJA;;IAEAL,4BAAUC;QACNH,GAAEK,EAAEN,CAACD;IACTS;AACJG;;AAEArB,sBAAOsB,WAAWpB;IACJC,MAASC,MAAnBC,QAAmCC;IACzBH,MAASC,MAAnBmB,QAAmCjB;IACzBH,MAASC,MAAnBoB,QAAmClB;IACzBH,MAASC,MAAnBG,QAAmCD;IACzBH,MAASC,MAAnBqB,QAAmCnB;IACzBH,MAASC,MAAnBsB,QAAmCpB;IACzBH,MAASC,MAAnBuB,QAAmCrB;IACzBH,MAASC,MAAnBwB,QAAmC7B;AACvCS,CAAEC;IACUL,eAAJM,EAAaD;IACTL,eAAJyB,EAAapB;IACTL,eAAJO,kBAAcK,EAAEc,CAACrB;IACbL,MAAK2B,CAACC,MAAEC,EAAZrB,kBAAcI,EAAEc,CAACrB;;;IAGrBI,YAAUX,SAACG,KAAKC,UAAEC,OAAKC,EAAEM;QACrBC,cAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKJ,IAAGL,GAAEI;YACRJ,GAAEM,EAAEL,CAACoB,CAACd,CAACgB,CAACxB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;;;IAGAL,YAAUX,SAACG,KAAKG,EAAEM;QACdC,IAAGL,GAAEI;YACDJ,GAAEM,EAAEL,CAACF;QACTS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;;;IAGAL,YAAUX,SAACqB,OAAOjB,UAAEmB,QAAQjB,EAAEM;QAC1BC,cAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;IACAL,YAAUX,SAACsB,OAAOlB,UAAEoB,QAAQlB,EAAEM;QAC1BC,eAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;IACAL,YAAUX,SAACqB,OAAiBf,EAAEM;QAC1BC,cAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;IACAL,YAAUX,SAACsB,OAAiBhB,EAAEM;QAC1BC,eAASD;YACLJ,GAAEM,EAAEkB,IAAIzB;QACZS,IAAEC,KAAKL;YACHJ,GAAEM,EAAEJ,CAACmB,CAACI,CAACC,CAACnB,CAACgB,CAACxB;QACdS;IACJA;;;IAGOd,MAAK2B,CAACC,MAAEC,EAAXI,CAAY5B;IAChB6B,YAAIC,IAAKtB,GAALsB,IAAQP,IAARO,KAAczB,MAAHsB,CAACI;QACZ3B,YAAUX,SAACG,KAAKC,UAAEC,OAAKC,EAAEM;YACrBC,cAASD;gBACLuB,CAACN,CAACQ,CAACN,GAAEjB,EAAEuB,CAAC9B;YACZS;QACJA;IACJA;;;IAGOd,MAAK2B,CAACC,MAAEC,EAAXQ,CAAYhC;IAChBI,YAAUX,SAACG,KAAKC,UAAEC,OAAKC,EAAEM;QACrBC,cAASD;YACLwB,KAAOI,aAAHH,IAAUtB,GAAVsB,IAAaP,IAAbO,KAAgBzB;gBAChB2B,CAACV,CAACQ,CAACN,GAAEjB,EAAEuB,CAAC9B;YACZS;QACJA;IACJA;;;IAGAyB,YAAY7B;QACRJ,KAAKM,EAAEgB,EAAEvB;QACToB,KAAKb,EAAE4B,KAAKnC;QACZoB,EAAEgB,CAACnC,EAAEM,EAAE8B,OAAOrC;;QAEdC,GAAGM,EAAEgB,GAAGe,EAAEf,EAAEvB;QACZoB,GAAGb,EAAEgB,GAAGe,EAAEC,SAASC,EAAE/C,CAACgD,EAAEC,EAAEC,CAAC5C,CAACC;IAChCS;AACJG"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/13_range_operator.sv.map b/testcases/map/testcases/sv/13_range_operator.sv.map
index 52b25992a..a8d054224 100644
--- a/testcases/map/testcases/sv/13_range_operator.sv.map
+++ b/testcases/map/testcases/sv/13_range_operator.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"13_range_operator.sv.map","sources":["../../../veryl/13_range_operator.veryl"],"names":["","module","Module13",";","logic","a","b","c","d","e","[","10","]","X","=","1","always_comb","0",":","+:","2","-:","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,eAAHC,CAAYF;IACTC,eAAHE,CAAYH;IACTC,eAAHG,CAAYJ;IACTC,eAAHI,CAAYL;IACTC,eAAHK,CAAYN;IACTC,MAAKM,CAACC,MAAEC,EAAXC;kBAAaC,EAAEC,CAACZ;;;IAGpBa,YAAOX,EAAES,EAAED,CAACH,CAACO,CAACL,CAACT;;;IAGfa,YAAOV,EAAEQ,EAAED,CAACH,CAACK,CAACG,CAACD,CAACL,CAACT;;;IAGjBa,YAAOT,EAAEO,EAAED,CAACH,CAACK,CAACI,EAAEC,CAACR,CAACT;IAClBa,YAAOR,EAAEM,EAAED,CAACH,CAACK,CAACM,EAAED,CAACR,CAACT;;;IAGlBa,YAAOP,EAAEK,EAAED,CAACH,CAACK,GAAOK,KAAAA,EAACR,CAACT;AAC1BmB"}
\ No newline at end of file
+{"version":3,"file":"13_range_operator.sv.map","sources":["../../../veryl/13_range_operator.veryl"],"names":["","module","Module13",";","logic","a","b","c","d","e","[","10","]","X","=","1","always_comb","0",":","+:","2","-:","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,eAAHC,CAAYF;IACTC,eAAHE,CAAYH;IACTC,eAAHG,CAAYJ;IACTC,eAAHI,CAAYL;IACTC,eAAHK,CAAYN;IACTC,MAAKM,CAACC,MAAEC,EAAXC,iBAAaC,EAAEC,CAACZ;;;IAGpBa,YAAOX,EAAES,EAAED,CAACH,CAACO,CAACL,CAACT;;;IAGfa,YAAOV,EAAEQ,EAAED,CAACH,CAACK,CAACG,CAACD,CAACL,CAACT;;;IAGjBa,YAAOT,EAAEO,EAAED,CAACH,CAACK,CAACI,EAAEC,CAACR,CAACT;IAClBa,YAAOR,EAAEM,EAAED,CAACH,CAACK,CAACM,EAAED,CAACR,CAACT;;;IAGlBa,YAAOP,EAAEK,EAAED,CAACH,CAACK,GAAOK,KAAAA,EAACR,CAACT;AAC1BmB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/14_inst.sv.map b/testcases/map/testcases/sv/14_inst.sv.map
index 90d9b1661..4dd84d02a 100644
--- a/testcases/map/testcases/sv/14_inst.sv.map
+++ b/testcases/map/testcases/sv/14_inst.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"14_inst.sv.map","sources":["../../../veryl/14_inst.veryl"],"names":["","module","Module14",";","localparam","int unsigned","X","=","1","logic","a","aa","bbb","veryl_testcase_Module14B","x","veryl_testcase_Module14C","#","(",",","Y","10",")","xx","bb","bbbb","veryl_testcase_InterfaceA","y","b","yy","xxx","yyy","[","]","endmodule","Module14B","Module14C","parameter","input","32","interface","InterfaceA","endinterface"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAASC,aAAHC,EAAOC,EAAEC,CAACL;;IAEPM,MAALC;kBAAWH,EAAEC,CAACL;IACTM,MAALE;mBAAWJ,EAAEC,CAACL;IACTM,MAALG;oBAAWL,EAAEC,CAACL;;;IAGlBH,AAAQa,yBAAHC,IAAYX;;;IAGjBH,AAASe,yBAAUC,CAACC;SAChBX,GAAAA,GAAKY;SACLC,GAACnB,AAAEoB,GAAEpB;IACTqB,EAHKC,GAGHL;SACEP,MAAAA,IAASQ;SACTK,MAAIvB,AAAEW,IAAGO;SACTM,MAAIxB,AAAEY,IAAGZ;IACbqB,CAAClB;;;IAGDH,AAAQyB,0BAAHC,IAAavB;;;IAGlBH,AAAUyB,0BAAWT,CAACC,EAACP,GAAAA,EAACQ,GAAES,GAAC3B,AAAEoB,GAAEpB,AAACqB,EAA3BO,MAA4BzB;IACjCH,AAAUyB,0BAAWT,CAACC,EAACP,GAAAA,EAACQ,GAAES,GAAC3B,AAAEoB,GAAEpB,AAACqB,EAA3BQ,MAA4B1B;;;IAGjCH,AAAUyB,0BAALK,IAAgBC,GAACX,IAAEY,IAAC7B;AAC7B8B;;AAEAhC,sBAAOiC,SAAU/B;AAAC8B;;AAElBhC,sBAAOkC,UAAUnB,CAACC;IACdmB,UAAS/B,aAAHC,EAAOC,EAAEC,CAACU;IAChBkB,UAAS/B,aAAHc,EAAOZ,EAAEC,CAACR;AACpBqB,EAAEJ;IACQoB,MAAM5B,MAAKsB,CAACO,MAAEN,EAApBtB,IAAqBQ;IACfmB,MAAM5B,MAAKsB,CAACO,MAAEN,EAApBT,IAAqBL;IACfmB,MAAM5B,MAAKsB,CAACO,MAAEN,EAApBR,IAAqBxB;AACzBqB,CAAElB;AAAC8B;;AAEHM,yBAAUC,WAAWxB,CAACC;IAClBmB,UAAS/B,aAAHK,EAAOH,EAAEC,CAACU;IAChBkB,UAAS/B,aAAHsB,EAAOpB,EAAEC,CAACR;AACpBqB,CAAElB;AAACsC"}
\ No newline at end of file
+{"version":3,"file":"14_inst.sv.map","sources":["../../../veryl/14_inst.veryl"],"names":["","module","Module14",";","localparam","int unsigned","X","=","1","logic","a","aa","bbb","veryl_testcase_Module14B","x","veryl_testcase_Module14C","#","(",",","Y","10",")","xx","bb","bbbb","veryl_testcase_InterfaceA","y","b","yy","xxx","yyy","[","]","endmodule","Module14B","Module14C","parameter","input","32","interface","InterfaceA","endinterface"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAASC,aAAHC,EAAOC,EAAEC,CAACL;;IAEPM,MAALC,mBAAWH,EAAEC,CAACL;IACTM,MAALE,oBAAWJ,EAAEC,CAACL;IACTM,MAALG,qBAAWL,EAAEC,CAACL;;;IAGlBH,AAAQa,yBAAHC,IAAYX;;;IAGjBH,AAASe,yBAAUC,CAACC;SAChBX,GAAAA,GAAKY;SACLC,GAACnB,AAAEoB,GAAEpB;IACTqB,EAHKC,GAGHL;SACEP,MAAAA,IAASQ;SACTK,MAAIvB,AAAEW,IAAGO;SACTM,MAAIxB,AAAEY,IAAGZ;IACbqB,CAAClB;;;IAGDH,AAAQyB,0BAAHC,IAAavB;;;IAGlBH,AAAUyB,0BAAWT,CAACC,EAACP,GAAAA,EAACQ,GAAES,GAAC3B,AAAEoB,GAAEpB,AAACqB,EAA3BO,MAA4BzB;IACjCH,AAAUyB,0BAAWT,CAACC,EAACP,GAAAA,EAACQ,GAAES,GAAC3B,AAAEoB,GAAEpB,AAACqB,EAA3BQ,MAA4B1B;;;IAGjCH,AAAUyB,0BAALK,IAAgBC,GAACX,IAAEY,IAAC7B;AAC7B8B;;AAEAhC,sBAAOiC,SAAU/B;AAAC8B;;AAElBhC,sBAAOkC,UAAUnB,CAACC;IACdmB,UAAS/B,aAAHC,EAAOC,EAAEC,CAACU;IAChBkB,UAAS/B,aAAHc,EAAOZ,EAAEC,CAACR;AACpBqB,EAAEJ;IACQoB,MAAM5B,MAAKsB,CAACO,MAAEN,EAApBtB,IAAqBQ;IACfmB,MAAM5B,MAAKsB,CAACO,MAAEN,EAApBT,IAAqBL;IACfmB,MAAM5B,MAAKsB,CAACO,MAAEN,EAApBR,IAAqBxB;AACzBqB,CAAElB;AAAC8B;;AAEHM,yBAAUC,WAAWxB,CAACC;IAClBmB,UAAS/B,aAAHK,EAAOH,EAAEC,CAACU;IAChBkB,UAAS/B,aAAHsB,EAAOpB,EAAEC,CAACR;AACpBqB,CAAElB;AAACsC"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/15_named_block.sv.map b/testcases/map/testcases/sv/15_named_block.sv.map
index 8819e5a1a..01cc6dca4 100644
--- a/testcases/map/testcases/sv/15_named_block.sv.map
+++ b/testcases/map/testcases/sv/15_named_block.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"15_named_block.sv.map","sources":["../../../veryl/15_named_block.veryl"],"names":["","module","Module15",";","logic","_a","=","1","if (1) begin",":","label","end","label1","for","i","0","10","begin","label2","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACJC,MAAJC;mBAAUC,EAAEC,CAACJ;;IAEVK,aAAPC,CAACC;QACWN,MAAJC;uBAAUC,EAAEC,CAACJ;IACrBQ;;IAEQH,aAARC,CAACG;QACWR,MAAJC;uBAAUC,EAAEC,CAACJ;IACrBQ;;IAEAE,YAAIC,IAAKC,GAALD,IAAQE,IAARF,KAAmBG,MAARR,CAACS;QACLV,aAAPC,CAACC;YACWN,MAAJC;2BAAUC,EAAEC,CAACJ;QACrBQ;IACJA;AACJQ"}
\ No newline at end of file
+{"version":3,"file":"15_named_block.sv.map","sources":["../../../veryl/15_named_block.veryl"],"names":["","module","Module15",";","logic","_a","=","1","if (1) begin",":","label","end","label1","for","i","0","10","begin","label2","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACJC,MAAJC,mBAAUC,EAAEC,CAACJ;;IAEVK,aAAPC,CAACC;QACWN,MAAJC,mBAAUC,EAAEC,CAACJ;IACrBQ;;IAEQH,aAARC,CAACG;QACWR,MAAJC,mBAAUC,EAAEC,CAACJ;IACrBQ;;IAEAE,YAAIC,IAAKC,GAALD,IAAQE,IAARF,KAAmBG,MAARR,CAACS;QACLV,aAAPC,CAACC;YACWN,MAAJC,mBAAUC,EAAEC,CAACJ;QACrBQ;IACJA;AACJQ"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/16_case_switch.sv.map b/testcases/map/testcases/sv/16_case_switch.sv.map
index 7d23e5465..3a9638bbf 100644
--- a/testcases/map/testcases/sv/16_case_switch.sv.map
+++ b/testcases/map/testcases/sv/16_case_switch.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"16_case_switch.sv.map","sources":["../../../veryl/16_case_switch.veryl"],"names":["","module","Module16",";","localparam","bit","y","=","1","logic","a","b","x","[","3","]","z","always_comb","begin","case",") inside","0",":","2","end",",","4","5","7","-","default","endcase","(1'b1)","==","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAASC,IAAHC,EAAOC,EAAEC,CAACL;;IAETM,cAAHC,CAAWP;IACRM,cAAHE,CAAWR;IACRM,cAAHG;kBAAYL,EAAEC,CAACL;IACZM,MAAKI,CAACC,KAACC,EAAVC;kBAAYT,EAAEC,CAACL;;IAEnBc,YAAYC;QACRC,MAAKP,CAAEQ;YACHC,CAACC,EAAEZ,EAAEH,EAAEC,CAACL;YACRK,CAACc,EAAEZ,EAAEH,EAAEC,CAACL;YACRoB,CAACD,EAAEJ;mBACIR,EAAEH,EAAEC,CAACL;mBACLO,EAAEH,EAAEC,CAACL;mBACLO,EAAEH,EAAEC,CAACL;eACTqB;YACHV,CAACW,EAAEC,IAAIJ,EAAEZ,EAAEH,EAAEC,CAACL;aACdwB,EAAIC,IAAGN,EAAEZ,EAAEH,EAAEC,CAACL;YACdG,EAAEuB,EAAErB,GAAGc,EAAEZ,EAAEH,EAAEC,CAACL;YACd2B,OAAOR,EAAEZ,EAAEH,EAAEC,CAACL;QAClB4B;IACJP;;IAEAP,YAAYC;QACRC,KAAOa;YACHhB,EAAEiB,GAAGZ,CAACC,EAAEX,EAAEJ,EAAEC,CAACL;YACba,EAAEiB,GAAGzB,CAACc,EAAEX,EAAEJ,EAAEC,CAACL;YACba,EAAEiB,GAAGV,CAACD,EAAEJ;wBACIP,EAAEJ,EAAEC,CAACL;wBACLQ,EAAEJ,EAAEC,CAACL;wBACLQ,EAAEJ,EAAEC,CAACL;oBACTqB;YACRR,EAAEiB,GAAGnB,CAACW,EAAET,EAAEiB,GAAGP,CAACJ,EAAEX,EAAEJ,EAAEC,CAACL;YACrB2B,cAAcR,EAAEX,EAAEJ,EAAEC,CAACL;QACzB4B;IACJP;AACJU"}
\ No newline at end of file
+{"version":3,"file":"16_case_switch.sv.map","sources":["../../../veryl/16_case_switch.veryl"],"names":["","module","Module16",";","localparam","bit","y","=","1","logic","a","b","x","[","3","]","z","always_comb","begin","case",") inside","0",":","2","end",",","4","5","7","-","default","endcase","(1'b1)","==","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAASC,IAAHC,EAAOC,EAAEC,CAACL;;IAETM,cAAHC,CAAWP;IACRM,cAAHE,CAAWR;IACRM,cAAHG,iBAAYL,EAAEC,CAACL;IACZM,MAAKI,CAACC,KAACC,EAAVC,iBAAYT,EAAEC,CAACL;;IAEnBc,YAAYC;QACRC,MAAKP,CAAEQ;YACHC,CAACC,EAAEZ,EAAEH,EAAEC,CAACL;YACRK,CAACc,EAAEZ,EAAEH,EAAEC,CAACL;YACRoB,CAACD,EAAEJ;mBACIR,EAAEH,EAAEC,CAACL;mBACLO,EAAEH,EAAEC,CAACL;mBACLO,EAAEH,EAAEC,CAACL;eACTqB;YACHV,CAACW,EAAEC,IAAIJ,EAAEZ,EAAEH,EAAEC,CAACL;aACdwB,EAAIC,IAAGN,EAAEZ,EAAEH,EAAEC,CAACL;YACdG,EAAEuB,EAAErB,GAAGc,EAAEZ,EAAEH,EAAEC,CAACL;YACd2B,OAAOR,EAAEZ,EAAEH,EAAEC,CAACL;QAClB4B;IACJP;;IAEAP,YAAYC;QACRC,KAAOa;YACHhB,EAAEiB,GAAGZ,CAACC,EAAEX,EAAEJ,EAAEC,CAACL;YACba,EAAEiB,GAAGzB,CAACc,EAAEX,EAAEJ,EAAEC,CAACL;YACba,EAAEiB,GAAGV,CAACD,EAAEJ;wBACIP,EAAEJ,EAAEC,CAACL;wBACLQ,EAAEJ,EAAEC,CAACL;wBACLQ,EAAEJ,EAAEC,CAACL;oBACTqB;YACRR,EAAEiB,GAAGnB,CAACW,EAAET,EAAEiB,GAAGP,CAACJ,EAAEX,EAAEJ,EAAEC,CAACL;YACrB2B,cAAcR,EAAEX,EAAEJ,EAAEC,CAACL;QACzB4B;IACJP;AACJU"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/18_concatenation.sv.map b/testcases/map/testcases/sv/18_concatenation.sv.map
index 53d0f557c..ffebc4c8d 100644
--- a/testcases/map/testcases/sv/18_concatenation.sv.map
+++ b/testcases/map/testcases/sv/18_concatenation.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"18_concatenation.sv.map","sources":["../../../veryl/18_concatenation.veryl"],"names":["","module","Module18",";","logic","[","20","]","a","b","c","=","1","always_comb","{","10",":","0",",","}","4","_d","8","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,MAAKC,CAACC,MAAEC,EAAXC,CAAYL;IACTC,eAAHK,CAAYN;IACTC,eAAHM;kBAAaC,EAAEC,CAACT;;IAEpBU,YAAOL,EAAEG,EAAEG,CAACN,CAACH,CAACU,EAAEC,CAACC,CAACV,CAACW,EAAER,CAAES,CAAChB;IACxBU,YAAOJ,EAAEE,EAAEG,EAAgBC,GAAfP,CAACH,CAACU,EAAEC,CAACC,CAACV,GAAWW,GAAWE,EAATV,GAAUS,CAAChB;;;IAGlCC,MAAJiB;mBAAUV,EAAEG;SACHQ,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ;IAC5BS,CAAChB;AACLoB"}
\ No newline at end of file
+{"version":3,"file":"18_concatenation.sv.map","sources":["../../../veryl/18_concatenation.veryl"],"names":["","module","Module18",";","logic","[","20","]","a","b","c","=","1","always_comb","{","10",":","0",",","}","4","_d","8","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,MAAKC,CAACC,MAAEC,EAAXC,CAAYL;IACTC,eAAHK,CAAYN;IACTC,eAAHM,iBAAaC,EAAEC,CAACT;;IAEpBU,YAAOL,EAAEG,EAAEG,CAACN,CAACH,CAACU,EAAEC,CAACC,CAACV,CAACW,EAAER,CAAES,CAAChB;IACxBU,YAAOJ,EAAEE,EAAEG,EAAgBC,GAAfP,CAACH,CAACU,EAAEC,CAACC,CAACV,GAAWW,GAAWE,EAATV,GAAUS,CAAChB;;;IAGlCC,MAAJiB,mBAAUV,EAAEG;SACHQ,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ,GAAUQ;SACzBI,EAATd,GAAUU,GAAWI,EAATb,GAAUS,GAAWI,EAATZ;IAC5BS,CAAChB;AACLoB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/20_if_case_switch_expression.sv.map b/testcases/map/testcases/sv/20_if_case_switch_expression.sv.map
index 64ef180bc..371a1d98b 100644
--- a/testcases/map/testcases/sv/20_if_case_switch_expression.sv.map
+++ b/testcases/map/testcases/sv/20_if_case_switch_expression.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"20_if_case_switch_expression.sv.map","sources":["../../../veryl/20_if_case_switch_expression.veryl"],"names":["","module","Module20",";","logic","a","b","c","x","=","1","y","always_comb","((",") ? (",")",":","(","2","))","0","3","4","5","7","(((","==","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,MAAHC,CAAQF;IACLC,MAAHE,CAAQH;IACLC,MAAHG,CAAQJ;IACLC,MAAHI;kBAASC,EAAEC,CAACP;IACTC,MAAHO;kBAASF,EAAEC,CAACP;;IAEhBS,YAAOP,EAAEI,EAAEI,EAAGL,CAAEM;QACZJ;IACJK,EAAEC,EAAKC;QACHJ,EAAGF,CAAEG;YACDJ;QACJK,EAAEC,EAAKC;YACHC;QACJC;IACJA,EAAChB;;IAEDS,YAAON,EAAEG,EAAEI,GAAKR,QACZK;QAASU;UADGf,QAEZa;QAASR;IAACK,MAFEV,QAGZgB;QAASH;IAARH,MAHWV,QAGTiB;QAAMJ;IAACH,MAHEV,YAIZkB,EAAIC;QAAKH;IAACN;QACDO;IACbH,EAAChB;;IAEDS,YAAOL,EAAEE,EAAEgB,GACPpB,EAAEqB,GAAGhB;QAAWU;UAChBf,EAAEqB,GAAGR;QAAWR;IAACK,MACjBV,EAAEqB,GAAGL;QAAWH;IAAVH,MAAEV,EAAEqB,GAAGJ;QAAGJ;IAACH;QACDM;IACpBF,EAAChB;AACLwB"}
\ No newline at end of file
+{"version":3,"file":"20_if_case_switch_expression.sv.map","sources":["../../../veryl/20_if_case_switch_expression.veryl"],"names":["","module","Module20",";","logic","a","b","c","x","=","1","y","always_comb","((",") ? (",")",":","(","2","))","0","3","4","5","7","(((","==","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,MAAHC,CAAQF;IACLC,MAAHE,CAAQH;IACLC,MAAHG,CAAQJ;IACLC,MAAHI,iBAASC,EAAEC,CAACP;IACTC,MAAHO,iBAASF,EAAEC,CAACP;;IAEhBS,YAAOP,EAAEI,EAAEI,EAAGL,CAAEM;QACZJ;IACJK,EAAEC,EAAKC;QACHJ,EAAGF,CAAEG;YACDJ;QACJK,EAAEC,EAAKC;YACHC;QACJC;IACJA,EAAChB;;IAEDS,YAAON,EAAEG,EAAEI,GAAKR,QACZK;QAASU;UADGf,QAEZa;QAASR;IAACK,MAFEV,QAGZgB;QAASH;IAARH,MAHWV,QAGTiB;QAAMJ;IAACH,MAHEV,YAIZkB,EAAIC;QAAKH;IAACN;QACDO;IACbH,EAAChB;;IAEDS,YAAOL,EAAEE,EAAEgB,GACPpB,EAAEqB,GAAGhB;QAAWU;UAChBf,EAAEqB,GAAGR;QAAWR;IAACK,MACjBV,EAAEqB,GAAGL;QAAWH;IAAVH,MAAEV,EAAEqB,GAAGJ;QAAGJ;IAACH;QACDM;IACpBF,EAAChB;AACLwB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/21_cast.sv.map b/testcases/map/testcases/sv/21_cast.sv.map
index 010b10eca..044254343 100644
--- a/testcases/map/testcases/sv/21_cast.sv.map
+++ b/testcases/map/testcases/sv/21_cast.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"21_cast.sv.map","sources":["../../../veryl/21_cast.veryl"],"names":["","module","Module21",";","logic","a","[","2","]","b","c","=","1","typedef enum","{","EnumA_A",",","EnumA_B","EnumA","EnumB_C","EnumB_D","EnumB","localparam","type","EnumC","int unsigned","EnumD","always_comb","(",")","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,cAAHC,CAAWF;IACRC,MAAKE,CAACC,KAACC,EAAVC,CAAWN;IACRC,cAAHM;kBAAYC,EAAEC,CAACT;;IAEnBU,aAAYT,MAAMU;QACdC,OAACC;QACDC,OAACjB;MAFAkB,MAGLlB;;IAEAa,aAAYT,MAAMU;QACdK,OAACH;QACDI,OAACpB;MAFAqB,MAGLrB;;IAEAsB,WAAaC,KAAPC,MAAYb,EAAEU,KAAKlB;;IAEzBmB,WAAaG,aAAPC,MAAWf,EAAEC,CAACT;;IAEpBwB,YAAOtB,EAAEM,EAAwCe,OAAtCE,CAA4BJ,OAA3BI,CAAiBP,OAAhBO,CAAMV,OAALR,EAAUmB,EAAUA,EAAUA,EAAU1B;IACtDwB,YAAOlB,EAAEE,EAAOJ,GAALG,EAAMP;AACrB2B"}
\ No newline at end of file
+{"version":3,"file":"21_cast.sv.map","sources":["../../../veryl/21_cast.veryl"],"names":["","module","Module21",";","logic","a","[","2","]","b","c","=","1","typedef enum","{","EnumA_A",",","EnumA_B","EnumA","EnumB_C","EnumB_D","EnumB","localparam","type","EnumC","int unsigned","EnumD","always_comb","(",")","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,cAAHC,CAAWF;IACRC,MAAKE,CAACC,KAACC,EAAVC,CAAWN;IACRC,cAAHM,iBAAYC,EAAEC,CAACT;;IAEnBU,aAAYT,MAAMU;QACdC,OAACC;QACDC,OAACjB;MAFAkB,MAGLlB;;IAEAa,aAAYT,MAAMU;QACdK,OAACH;QACDI,OAACpB;MAFAqB,MAGLrB;;IAEAsB,WAAaC,KAAPC,MAAYb,EAAEU,KAAKlB;;IAEzBmB,WAAaG,aAAPC,MAAWf,EAAEC,CAACT;;IAEpBwB,YAAOtB,EAAEM,EAAwCe,OAAtCE,CAA4BJ,OAA3BI,CAAiBP,OAAhBO,CAAMV,OAALR,EAAUmB,EAAUA,EAAUA,EAAU1B;IACtDwB,YAAOlB,EAAEE,EAAOJ,GAALG,EAAMP;AACrB2B"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/22_type_modifier.sv.map b/testcases/map/testcases/sv/22_type_modifier.sv.map
index 0dea356e3..63faa1ede 100644
--- a/testcases/map/testcases/sv/22_type_modifier.sv.map
+++ b/testcases/map/testcases/sv/22_type_modifier.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"22_type_modifier.sv.map","sources":["../../../veryl/22_type_modifier.veryl"],"names":["","module","Module22",";","logic","[","10","]","_a","=","1","tri","_b","_c","_d","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACGC,iBAASC,CAACC,MAAEC,EAAvBC;mBAAyBC,EAAEC,CAACP;IACxBQ,IAAWP,aAAKC,CAACC,MAAEC,EAAvBK;cAAyBH,EAAEC,CAACP;IACjBQ,IAAIP,aAAKC,CAACC,MAAEC,EAAvBM;cAAyBJ,EAAEC,CAACP;IACxBC,iBAAgBC,CAACC,MAAEC,EAAvBO;mBAAyBL,EAAEC,CAACP;AACpCY"}
\ No newline at end of file
+{"version":3,"file":"22_type_modifier.sv.map","sources":["../../../veryl/22_type_modifier.veryl"],"names":["","module","Module22",";","logic","[","10","]","_a","=","1","tri","_b","_c","_d","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACGC,iBAASC,CAACC,MAAEC,EAAvBC,mBAAyBC,EAAEC,CAACP;IACxBQ,IAAWP,aAAKC,CAACC,MAAEC,EAAvBK,cAAyBH,EAAEC,CAACP;IACjBQ,IAAIP,aAAKC,CAACC,MAAEC,EAAvBM,cAAyBJ,EAAEC,CAACP;IACxBC,iBAAgBC,CAACC,MAAEC,EAAvBO,mBAAyBL,EAAEC,CAACP;AACpCY"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/23_ifdef.sv.map b/testcases/map/testcases/sv/23_ifdef.sv.map
index a85b38c16..8e45fa6a6 100644
--- a/testcases/map/testcases/sv/23_ifdef.sv.map
+++ b/testcases/map/testcases/sv/23_ifdef.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"23_ifdef.sv.map","sources":["../../../veryl/23_ifdef.veryl"],"names":["","module","Module23","#","(","ifdef","DEFINE_A","DEFINE_B","DEFINE_C","DEFINE_D","parameter","int unsigned","ParamA","=","1",",","ParamB","ParamC",")","input","logic","port_a","port_b","port_c",";","[","10","]","_a","_b","_c","_d","always_comb","begin","0","end","endmodule","Module23_A","ifndef","Module23_B","Module23_C"],"mappings":"AAAAA,AAAAC,sBAAOC,SAASC,CAACC;KACXC,MAAMC;KACND,MAAME;KACNF,MAAMG;KACNH,MAAMI;IACRC,UAAcC,aAARC,OAAYC,EAAEC;IAACC;;;;IACrBL,UAAcC,aAARK,OAAYH,EAAEC,CAACC;KACnBV,MAAMC;;IAEJI,UAAcC,aAARM,OAAYJ,EAAEC,CAACd;UACxBA;AACLkB,EAAEd;KACIC,MAAMC;IACAa,MAAMC,MAAdC;IAAmBN;IACXI,MAAMC,MAAdE,MAAmBP;;KAEjBV,MAAMC;;IAEIa,MAAMC,MAAdG,MAAmBvB;UACtBA;AACLkB,CAAEM;KACInB,MAAMC;KACND,MAAME;IACAa,MAAKK,CAACC,MAAEC,EAAZC;mBAAcf,EAAEC,CAACU;;;;KAEnBnB,MAAMC;IAEIc,MAAKK,CAACC,MAAEC,EAAZE;mBAAchB,EAAEC,CAACU;IACbJ,MAAKK,CAACC,MAAEC,EAAZG;mBAAcjB,EAAEC,CAACU;;;IAGjBJ,MAAJW,EAASP;IACbQ,YAAYC;SACN5B,MAAMI;QAEJsB,GAAGlB,EAAEqB,CAACV;;;IAEdW;AACJC;;CAEE/B,MAAMC;AACRL,sBAAOoC,UAAWb;AAACY;;;CAEjBE,OAAOhC;AAELL,sBAAOsC,UAAWf;AAACY;AACnBnC,sBAAOuC,UAAWhB;AAACY"}
\ No newline at end of file
+{"version":3,"file":"23_ifdef.sv.map","sources":["../../../veryl/23_ifdef.veryl"],"names":["","module","Module23","#","(","ifdef","DEFINE_A","DEFINE_B","DEFINE_C","DEFINE_D","parameter","int unsigned","ParamA","=","1",",","ParamB","ParamC",")","input","logic","port_a","port_b","port_c",";","[","10","]","_a","_b","_c","_d","always_comb","begin","0","end","endmodule","Module23_A","ifndef","Module23_B","Module23_C"],"mappings":"AAAAA,AAAAC,sBAAOC,SAASC,CAACC;KACXC,MAAMC;KACND,MAAME;KACNF,MAAMG;KACNH,MAAMI;IACRC,UAAcC,aAARC,OAAYC,EAAEC;IAACC;;;;IACrBL,UAAcC,aAARK,OAAYH,EAAEC,CAACC;KACnBV,MAAMC;;IAEJI,UAAcC,aAARM,OAAYJ,EAAEC,CAACd;UACxBA;AACLkB,EAAEd;KACIC,MAAMC;IACAa,MAAMC,MAAdC;IAAmBN;IACXI,MAAMC,MAAdE,MAAmBP;;KAEjBV,MAAMC;;IAEIa,MAAMC,MAAdG,MAAmBvB;UACtBA;AACLkB,CAAEM;KACInB,MAAMC;KACND,MAAME;IACAa,MAAKK,CAACC,MAAEC,EAAZC,mBAAcf,EAAEC,CAACU;;;;KAEnBnB,MAAMC;IAEIc,MAAKK,CAACC,MAAEC,EAAZE,mBAAchB,EAAEC,CAACU;IACbJ,MAAKK,CAACC,MAAEC,EAAZG,mBAAcjB,EAAEC,CAACU;;;IAGjBJ,MAAJW,EAASP;IACbQ,YAAYC;SACN5B,MAAMI;QAEJsB,GAAGlB,EAAEqB,CAACV;;;IAEdW;AACJC;;CAEE/B,MAAMC;AACRL,sBAAOoC,UAAWb;AAACY;;;CAEjBE,OAAOhC;AAELL,sBAAOsC,UAAWf;AAACY;AACnBnC,sBAAOuC,UAAWhB;AAACY"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/24_sv_attribute.sv.map b/testcases/map/testcases/sv/24_sv_attribute.sv.map
index cbe917a0f..6ba22c37a 100644
--- a/testcases/map/testcases/sv/24_sv_attribute.sv.map
+++ b/testcases/map/testcases/sv/24_sv_attribute.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"24_sv_attribute.sv.map","sources":["../../../veryl/24_sv_attribute.veryl"],"names":["","module","Module24",";","ram_style=\"block\"","logic","_a","=","1","mark_debug=\"true\"","_b","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;OACPC;IACGC,MAAJC;mBAAUC,EAAEC,CAACL;OACZM;IACGJ,MAAJK;mBAAUH,EAAEC,CAACL;AACrBQ"}
\ No newline at end of file
+{"version":3,"file":"24_sv_attribute.sv.map","sources":["../../../veryl/24_sv_attribute.veryl"],"names":["","module","Module24",";","ram_style=\"block\"","logic","_a","=","1","mark_debug=\"true\"","_b","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;OACPC;IACGC,MAAJC,mBAAUC,EAAEC,CAACL;OACZM;IACGJ,MAAJK,mBAAUH,EAAEC,CAACL;AACrBQ"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/26_array.sv.map b/testcases/map/testcases/sv/26_array.sv.map
index d4099e7fc..d5581c22d 100644
--- a/testcases/map/testcases/sv/26_array.sv.map
+++ b/testcases/map/testcases/sv/26_array.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"26_array.sv.map","sources":["../../../veryl/26_array.veryl"],"names":["","module","Module26",";","logic","[","10","]","_a","=","1","][","_b","_c","2","'{",",","}","_d","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACJC,MAAKC,CAACC,MAAEC,UAAZC;mBAAyBC,EAAEC,CAACP;IACxBC,MAAKC,CAACC,MAAEK,EAAEL,MAAEC,EAAhBK;mBAAyBH,EAAEC,CAACP;IACxBC,MAAKC,CAACC,MAAEK,EAAEL,MAAEC,EAAhBM,GAAkBR,GAACS,GAACP;mBAAKE,EAAEM,EAAEL,CAACM,EAAEN,CAACO,CAACd;IAC9BC,MAAKC,CAACC,MAAEK,EAAEL,MAAEC,EAAhBW,GAAkBb,GAACS,GAACH,IAAEG,GAACP;mBAAEE,EAAEM,EAAEA,EAAEL,CAACM,EAAEN,CAACO,CAACD,EAAED,EAAEL,CAACM,EAAEN,CAACO,CAACA,CAACd;AACtDgB"}
\ No newline at end of file
+{"version":3,"file":"26_array.sv.map","sources":["../../../veryl/26_array.veryl"],"names":["","module","Module26",";","logic","[","10","]","_a","=","1","][","_b","_c","2","'{",",","}","_d","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACJC,MAAKC,CAACC,MAAEC,UAAZC,kCAAyBC,EAAEC,CAACP;IACxBC,MAAKC,CAACC,MAAEK,EAAEL,MAAEC,EAAhBK,kCAAyBH,EAAEC,CAACP;IACxBC,MAAKC,CAACC,MAAEK,EAAEL,MAAEC,EAAhBM,GAAkBR,GAACS,GAACP,yBAAKE,EAAEM,EAAEL,CAACM,EAAEN,CAACO,CAACd;IAC9BC,MAAKC,CAACC,MAAEK,EAAEL,MAAEC,EAAhBW,GAAkBb,GAACS,GAACH,IAAEG,GAACP,kBAAEE,EAAEM,EAAEA,EAAEL,CAACM,EAAEN,CAACO,CAACD,EAAED,EAAEL,CAACM,EAAEN,CAACO,CAACA,CAACd;AACtDgB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/27_string.sv.map b/testcases/map/testcases/sv/27_string.sv.map
index 6e8b27533..4c093c39b 100644
--- a/testcases/map/testcases/sv/27_string.sv.map
+++ b/testcases/map/testcases/sv/27_string.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"27_string.sv.map","sources":["../../../veryl/27_string.veryl"],"names":["","module","Module27",";","localparam","string","a","=","\"aaa\"","_b","\"bbb\"","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAASC,OAAHC,EAAUC,EAAEC,KAAKL;;IAEfE,OAAJI;mBAAWF,EAAEG,KAAKP;AAC1BQ"}
\ No newline at end of file
+{"version":3,"file":"27_string.sv.map","sources":["../../../veryl/27_string.veryl"],"names":["","module","Module27",";","localparam","string","a","=","\"aaa\"","_b","\"bbb\"","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAASC,OAAHC,EAAUC,EAAEC,KAAKL;;IAEfE,OAAJI,mBAAWF,EAAEG,KAAKP;AAC1BQ"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/28_msblsb.sv.map b/testcases/map/testcases/sv/28_msblsb.sv.map
index 07d335a4b..cc0bbcb9c 100644
--- a/testcases/map/testcases/sv/28_msblsb.sv.map
+++ b/testcases/map/testcases/sv/28_msblsb.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"28_msblsb.sv.map","sources":["../../../veryl/28_msblsb.veryl"],"names":["","module","Module28A","(","input","logic","[","30","][","40","]","c",")",";","localparam","int unsigned","WIDTH0","=","10","WIDTH1","20","a","1","+","b","_x","($size(a, 1) - 1)","($size(a, 2) - 1)",":","0","_y","($size(b, 1) - 1)","-","3","($size(b, 2) - 1)","5","_z","($size(c, 1) - 1)","($size(c, 2) - 1)","endmodule","package","typedef struct packed","{","veryl_testcase_Package28B::B","StructA","endpackage","Package28B","B","2","Package28C","W","N","bit","C","ModuleB","veryl_testcase___Package28A__Package28B_B::StructA","always_comb",".","_w","($bits(a) - 1)","($size(a.a, 1) - 1)","veryl_testcase_Package28C::C","($size(veryl_testcase_Package28C::C, 1) - 1)","($size(veryl_testcase_Package28C::C, 2) - 1)"],"mappings":"AAAAA,AAAAC,sBAAOC,UAAUC;IACVC,MAAMC,MAAKC,CAACC,MAAEC,EAAEC,MAAEC,EAArBC,CAAsBX;AAC1BY,CAAEC;IACEC,WAAcC,aAARC,OAAYC,EAAEC,EAAEL;IACtBC,WAAcC,aAARI,OAAYF,EAAEG,EAAEP;;IAEfR,MAAKC,CAACY,MAAEV,EAAEY,MAAEV,eAAfW;kBAA8BJ,EAAEK,CAACT;IAC9BR,MAAKC,CAACU,OAAOO,EAAEL,MAAEV,EAAEW,UAAMT,EAA5Bc;kBAA8BP,EAAEK,CAACT;;IAE7BR,MAAJoB;mBAAUR,EAAEI,CAACf,CAACoB,iBAAGhB,CAACJ,CAACqB,iBAAGC,CAACC,EAAIN,EAAED,CAACZ,CAACG;IAC3BR,MAAJyB;mBAAUb,EAAEO,CAAClB,CAACyB,kBAAIC,EAAEC,CAACvB,CAACJ,CAAC4B,kBAAIX,EAAEY,CAACP,CAACC,CAAGnB,CAACG;IAC/BR,MAAJ+B;mBAAUnB,EAAEN,CAACL,CAAC+B,iBAAG3B,CAACJ,CAACgC,iBAAG5B,CAACG;AAC/B0B;;AAEAC,iDAA+B3B;IAC3B4B,sBAAeC;QACRrC,MAAKC,CAACqC,gCAACjC,EAAVW,CAAWR;MADR+B,QAEP5C;AACJ6C;;AAEAL,uBAAQM,UAAWjC;IACfC,WAASC,aAAHgC,EAAO9B,EAAE+B,CAACnC;AACpBgC;;AAEAL,uBAAQS,UAAWpC;IACfC,WAASC,4BAAHmC,EAAajC,EAAE+B,CAACnC;IACtBC,WAASC,4BAAHoC,EAAalC,EAAEgB,CAACpB;IACtBC,WAASsC,aAAG9C,CAAC6C,KAAC3C,EAAE0C,KAACxC,EAAX2C,EAAapC,EAAEY,CAAChB;AAC1BgC;;AAEA5C,sBAAOqD,OAAQzC;IACF0C,mDAALlC,GAAyCR;IAC7C2C,YAAOnC,CAACoC,CAACpC,EAAEJ,EAAEY,CAAChB;;IAENR,MAAJqD;mBAAUzC,EAAEI,CAACf,CAACqD,cAAGjD,CAACG;IACdR,MAAJoB;mBAAUR,EAAEI,CAACoC,CAACpC,CAACf,CAACsD,mBAAGlD,CAACG;IAChBR,MAAJyB;mBAAUb,EAAE4C,4BAAavD,CAACwD,4CAAGpD,CAACG;IAC1BR,MAAJ+B;mBAAUnB,EAAE4C,4BAAavD,CAACuB,CAACnB,CAACJ,CAACyD,4CAAGrD,CAACG;AACzC0B"}
\ No newline at end of file
+{"version":3,"file":"28_msblsb.sv.map","sources":["../../../veryl/28_msblsb.veryl"],"names":["","module","Module28A","(","input","logic","[","30","][","40","]","c",")",";","localparam","int unsigned","WIDTH0","=","10","WIDTH1","20","a","1","+","b","_x","($size(a, 1) - 1)","($size(a, 2) - 1)",":","0","_y","($size(b, 1) - 1)","-","3","($size(b, 2) - 1)","5","_z","($size(c, 1) - 1)","($size(c, 2) - 1)","endmodule","package","typedef struct packed","{","veryl_testcase_Package28B::B","StructA","endpackage","Package28B","B","2","Package28C","W","N","bit","C","ModuleB","veryl_testcase___Package28A__Package28B_B::StructA","always_comb",".","_w","($bits(a) - 1)","($size(a.a, 1) - 1)","veryl_testcase_Package28C::C","($size(veryl_testcase_Package28C::C, 1) - 1)","($size(veryl_testcase_Package28C::C, 2) - 1)"],"mappings":"AAAAA,AAAAC,sBAAOC,UAAUC;IACVC,MAAMC,MAAKC,CAACC,MAAEC,EAAEC,MAAEC,EAArBC,CAAsBX;AAC1BY,CAAEC;IACEC,WAAcC,aAARC,OAAYC,EAAEC,EAAEL;IACtBC,WAAcC,aAARI,OAAYF,EAAEG,EAAEP;;IAEfR,MAAKC,CAACY,MAAEV,EAAEY,MAAEV,eAAfW,iBAA8BJ,EAAEK,CAACT;IAC9BR,MAAKC,CAACU,OAAOO,EAAEL,MAAEV,EAAEW,UAAMT,EAA5Bc,iBAA8BP,EAAEK,CAACT;;IAE7BR,MAAJoB,mBAAUR,EAAEI,CAACf,CAACoB,iBAAGhB,CAACJ,CAACqB,iBAAGC,CAACC,EAAIN,EAAED,CAACZ,CAACG;IAC3BR,MAAJyB,mBAAUb,EAAEO,CAAClB,CAACyB,kBAAIC,EAAEC,CAACvB,CAACJ,CAAC4B,kBAAIX,EAAEY,CAACP,CAACC,CAAGnB,CAACG;IAC/BR,MAAJ+B,mBAAUnB,EAAEN,CAACL,CAAC+B,iBAAG3B,CAACJ,CAACgC,iBAAG5B,CAACG;AAC/B0B;;AAEAC,iDAA+B3B;IAC3B4B,sBAAeC;QACRrC,MAAKC,CAACqC,gCAACjC,EAAVW,CAAWR;MADR+B,QAEP5C;AACJ6C;;AAEAL,uBAAQM,UAAWjC;IACfC,WAASC,aAAHgC,EAAO9B,EAAE+B,CAACnC;AACpBgC;;AAEAL,uBAAQS,UAAWpC;IACfC,WAASC,4BAAHmC,EAAajC,EAAE+B,CAACnC;IACtBC,WAASC,4BAAHoC,EAAalC,EAAEgB,CAACpB;IACtBC,WAASsC,aAAG9C,CAAC6C,KAAC3C,EAAE0C,KAACxC,EAAX2C,EAAapC,EAAEY,CAAChB;AAC1BgC;;AAEA5C,sBAAOqD,OAAQzC;IACF0C,mDAALlC,GAAyCR;IAC7C2C,YAAOnC,CAACoC,CAACpC,EAAEJ,EAAEY,CAAChB;;IAENR,MAAJqD,mBAAUzC,EAAEI,CAACf,CAACqD,cAAGjD,CAACG;IACdR,MAAJoB,mBAAUR,EAAEI,CAACoC,CAACpC,CAACf,CAACsD,mBAAGlD,CAACG;IAChBR,MAAJyB,mBAAUb,EAAE4C,4BAAavD,CAACwD,4CAAGpD,CAACG;IAC1BR,MAAJ+B,mBAAUnB,EAAE4C,4BAAavD,CAACuB,CAACnB,CAACJ,CAACyD,4CAAGrD,CAACG;AACzC0B"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/29_allow.sv.map b/testcases/map/testcases/sv/29_allow.sv.map
index 1ca6539dd..007f121dc 100644
--- a/testcases/map/testcases/sv/29_allow.sv.map
+++ b/testcases/map/testcases/sv/29_allow.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"29_allow.sv.map","sources":["../../../veryl/29_allow.veryl"],"names":["","module","Module29","(","input","logic","clk",",","rst_n",")",";","a","b","c","=","1","always_ff","begin","if","0","end","else","veryl_testcase_Module29A","u0","endmodule","Module29A"],"mappings":"AAAAA,AAAAC,sBAAOC,SAASC;IACPC,MAAMC,MAAXC,KAAgBC;IACXH,MAAMC,MAAXG,KAAgBR;AACpBS,CAAEC;IACSL,MAAHM,CAAQD;IACLL,MAAHO,CAAQF;;IAELL,MAAHQ;kBAASC,EAAEC,CAACL;;IAGhBM,YAAUb,SAACG,GAAGC,UAAEC,KAAGC,EAAEQ;QACjBC,YAASD;YACLN,GAAEG,EAAEK,CAACT;QACTU,IAAEC,KAAKJ;YACHN,GAAEG,EAAEK,CAACT;YACLE,GAAEE,EAAEK,CAACT;QACTU;IACJA;;IAGApB,AAASsB,yBAAJC,KAAab;AACtBc;;AAEAvB,sBAAOwB,UAAUtB;IACRC,MAAMC,MAAXC,KAAgBC;IACXH,MAAMC,MAAXG,KAAgBR;AACpBS,CAAEC;AAACc"}
\ No newline at end of file
+{"version":3,"file":"29_allow.sv.map","sources":["../../../veryl/29_allow.veryl"],"names":["","module","Module29","(","input","logic","clk",",","rst_n",")",";","a","b","c","=","1","always_ff","begin","if","0","end","else","veryl_testcase_Module29A","u0","endmodule","Module29A"],"mappings":"AAAAA,AAAAC,sBAAOC,SAASC;IACPC,MAAMC,MAAXC,KAAgBC;IACXH,MAAMC,MAAXG,KAAgBR;AACpBS,CAAEC;IACSL,MAAHM,CAAQD;IACLL,MAAHO,CAAQF;;IAELL,MAAHQ,iBAASC,EAAEC,CAACL;;IAGhBM,YAAUb,SAACG,GAAGC,UAAEC,KAAGC,EAAEQ;QACjBC,YAASD;YACLN,GAAEG,EAAEK,CAACT;QACTU,IAAEC,KAAKJ;YACHN,GAAEG,EAAEK,CAACT;YACLE,GAAEE,EAAEK,CAACT;QACTU;IACJA;;IAGApB,AAASsB,yBAAJC,KAAab;AACtBc;;AAEAvB,sBAAOwB,UAAUtB;IACRC,MAAMC,MAAXC,KAAgBC;IACXH,MAAMC,MAAXG,KAAgBR;AACpBS,CAAEC;AAACc"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/34_width_all_set.sv.map b/testcases/map/testcases/sv/34_width_all_set.sv.map
index 0c6c26ed9..dbac50c67 100644
--- a/testcases/map/testcases/sv/34_width_all_set.sv.map
+++ b/testcases/map/testcases/sv/34_width_all_set.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"34_width_all_set.sv.map","sources":["../../../veryl/34_width_all_set.veryl"],"names":["","module","Module34",";","logic","[","32","]","_a0","=","'0","_a1","'1","_a2","'x","_a3","'z","_a4","10'b0000000000","_a5","10'b1111111111","_a6","10'bxxxxxxxxxx","_a7","10'bzzzzzzzzzz","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACHC,MAAKC,CAACC,MAAEC,EAAbC;oBAAeC,EAAEC,EAAEP;IACdC,MAAKC,CAACC,MAAEC,EAAbI;oBAAeF,EAAEG,EAAET;IACdC,MAAKC,CAACC,MAAEC,EAAbM;oBAAeJ,EAAEK,EAAEX;IACdC,MAAKC,CAACC,MAAEC,EAAbQ;oBAAeN,EAAEO,EAAEb;IACdC,MAAKC,CAACC,MAAEC,EAAbU;oBAAeR,EAAES,cAAIf;IAChBC,MAAKC,CAACC,MAAEC,EAAbY;oBAAeV,EAAEW,cAAIjB;IAChBC,MAAKC,CAACC,MAAEC,EAAbc;oBAAeZ,EAAEa,cAAInB;IAChBC,MAAKC,CAACC,MAAEC,EAAbgB;oBAAed,EAAEe,cAAIrB;AAC7BsB"}
\ No newline at end of file
+{"version":3,"file":"34_width_all_set.sv.map","sources":["../../../veryl/34_width_all_set.veryl"],"names":["","module","Module34",";","logic","[","32","]","_a0","=","'0","_a1","'1","_a2","'x","_a3","'z","_a4","10'b0000000000","_a5","10'b1111111111","_a6","10'bxxxxxxxxxx","_a7","10'bzzzzzzzzzz","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACHC,MAAKC,CAACC,MAAEC,EAAbC,qBAAeC,EAAEC,EAAEP;IACdC,MAAKC,CAACC,MAAEC,EAAbI,qBAAeF,EAAEG,EAAET;IACdC,MAAKC,CAACC,MAAEC,EAAbM,qBAAeJ,EAAEK,EAAEX;IACdC,MAAKC,CAACC,MAAEC,EAAbQ,qBAAeN,EAAEO,EAAEb;IACdC,MAAKC,CAACC,MAAEC,EAAbU,qBAAeR,EAAES,cAAIf;IAChBC,MAAKC,CAACC,MAAEC,EAAbY,qBAAeV,EAAEW,cAAIjB;IAChBC,MAAKC,CAACC,MAAEC,EAAbc,qBAAeZ,EAAEa,cAAInB;IAChBC,MAAKC,CAACC,MAAEC,EAAbgB,qBAAed,EAAEe,cAAIrB;AAC7BsB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/35_unconnected_port.sv.map b/testcases/map/testcases/sv/35_unconnected_port.sv.map
index 1d343e818..74bc482a0 100644
--- a/testcases/map/testcases/sv/35_unconnected_port.sv.map
+++ b/testcases/map/testcases/sv/35_unconnected_port.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"35_unconnected_port.sv.map","sources":["../../../veryl/35_unconnected_port.veryl"],"names":["","module","Module35",";","logic","aa","=","1","veryl_testcase_Module35B","xx","(",",","bb","bbbb",")","endmodule","Module35B","input","[","32","]","output","always_comb","begin","0","end"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACJC,MAAJC;mBAAUC,EAAEC,CAACJ;;IAEjBH,AAASQ,yBAAJC,GAAcC;SACfL,MAAAA,GAAOM;SACPC,MAAIZ,AAAEA,GAACW;SACPE,MAAIb,AAAEA,GAACA;IACXc,CAACX;AACLY;;AAEAd,sBAAOe,UAAUN;IACPO,OAAOb,MAAKc,CAACC,MAAEC,EAArBf,IAAsBM;IAChBU,OAAOjB,MAAKc,CAACC,MAAEC,EAArBR,IAAsBD;IAChBU,OAAOjB,MAAKc,CAACC,MAAEC,EAArBP,IAAsBb;AAC1Bc,CAAEX;IACEmB,YAAYC;QACRX,KAAKN,EAAEkB,CAACrB;QACRU,KAAKP,EAAEkB,CAACrB;IACZsB;AACJV"}
\ No newline at end of file
+{"version":3,"file":"35_unconnected_port.sv.map","sources":["../../../veryl/35_unconnected_port.veryl"],"names":["","module","Module35",";","logic","aa","=","1","veryl_testcase_Module35B","xx","(",",","bb","bbbb",")","endmodule","Module35B","input","[","32","]","output","always_comb","begin","0","end"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACJC,MAAJC,mBAAUC,EAAEC,CAACJ;;IAEjBH,AAASQ,yBAAJC,GAAcC;SACfL,MAAAA,GAAOM;SACPC,MAAIZ,AAAEA,GAACW;SACPE,MAAIb,AAAEA,GAACA;IACXc,CAACX;AACLY;;AAEAd,sBAAOe,UAAUN;IACPO,OAAOb,MAAKc,CAACC,MAAEC,EAArBf,IAAsBM;IAChBU,OAAOjB,MAAKc,CAACC,MAAEC,EAArBR,IAAsBD;IAChBU,OAAOjB,MAAKc,CAACC,MAAEC,EAArBP,IAAsBb;AAC1Bc,CAAEX;IACEmB,YAAYC;QACRX,KAAKN,EAAEkB,CAACrB;QACRU,KAAKP,EAAEkB,CAACrB;IACZsB;AACJV"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/37_package_ref.sv.map b/testcases/map/testcases/sv/37_package_ref.sv.map
index 2ce91da70..9c45ad27f 100644
--- a/testcases/map/testcases/sv/37_package_ref.sv.map
+++ b/testcases/map/testcases/sv/37_package_ref.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"37_package_ref.sv.map","sources":["../../../veryl/37_package_ref.veryl"],"names":["","package","Package37",";","localparam","int unsigned","A","=","1","typedef enum","logic","{","B_C","B","function","X","return","0","endfunction","endpackage","module","Module37","_a","veryl_testcase_Package37::A","_b","veryl_testcase_Package37::B_C","_c","veryl_testcase_Package37::X","(",")","endmodule"],"mappings":"AAAAA,AAAAC,uBAAQC,SAAUC;IACdC,WAASC,aAAHC,EAAOC,EAAEC,CAACL;;IAEhBM,aAAQC,MAAMC;QACVC,GAACZ;MADAa,EAELb;;IAEAc,mBAAcT,aAALU,CAAEf,CAAOA;QACdgB,OAAOC,CAACd;IACZe;AACJC;;AAEAC,sBAAOC,QAASlB;IACJE,aAAJiB;mBAAQf,EAAEgB,2BAAYpB;IAClBE,aAAJmB;mBAAQjB,EAAEkB,6BAAetB;IACrBE,aAAJqB;mBAAQnB,EAAEoB,2BAAYC,CAACC,CAAC1B;AAChC2B"}
\ No newline at end of file
+{"version":3,"file":"37_package_ref.sv.map","sources":["../../../veryl/37_package_ref.veryl"],"names":["","package","Package37",";","localparam","int unsigned","A","=","1","typedef enum","logic","{","B_C","B","function","X","return","0","endfunction","endpackage","module","Module37","_a","veryl_testcase_Package37::A","_b","veryl_testcase_Package37::B_C","_c","veryl_testcase_Package37::X","(",")","endmodule"],"mappings":"AAAAA,AAAAC,uBAAQC,SAAUC;IACdC,WAASC,aAAHC,EAAOC,EAAEC,CAACL;;IAEhBM,aAAQC,MAAMC;QACVC,GAACZ;MADAa,EAELb;;IAEAc,mBAAcT,aAALU,CAAEf,CAAOA;QACdgB,OAAOC,CAACd;IACZe;AACJC;;AAEAC,sBAAOC,QAASlB;IACJE,aAAJiB,mBAAQf,EAAEgB,2BAAYpB;IAClBE,aAAJmB,mBAAQjB,EAAEkB,6BAAetB;IACrBE,aAAJqB,mBAAQnB,EAAEoB,2BAAYC,CAACC,CAAC1B;AAChC2B"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/45_var_let_in_always.sv.map b/testcases/map/testcases/sv/45_var_let_in_always.sv.map
index 7534c1b50..f8291f8ac 100644
--- a/testcases/map/testcases/sv/45_var_let_in_always.sv.map
+++ b/testcases/map/testcases/sv/45_var_let_in_always.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"45_var_let_in_always.sv.map","sources":["../../../veryl/45_var_let_in_always.veryl"],"names":["","module","Module45",";","logic","a","=","1","[","10","]","b","c","always_ff","(",")","begin","x","*","end","always_comb","y","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,eAAHC;kBAAaC,EAAEC,CAACJ;IACbC,MAAKI,CAACC,MAAEC,EAAXC,CAAYR;IACTC,MAAKI,CAACC,MAAEC,EAAXE,CAAYT;;IAEhBU,YAAUC,SAACT,CAACU,EAAEC;QACHZ,MAAKI,CAACC,MAAEC,EAAXO,CAAYd;QAChBc,EAAEX,GAAEC,CAACJ;QACLQ,GAAEL,EAAEW,EAAEC,EAAEX,CAACJ;IACbgB;;IAEAC,YAAYJ;QACDZ,MAAKI,CAACC,MAAEC,EAAXW;UAAaf,EAAEC,CAACJ;QACpBS,EAAEN,EAAEe,EAAEH,EAAEX,CAACJ;IACbgB;AACJG"}
\ No newline at end of file
+{"version":3,"file":"45_var_let_in_always.sv.map","sources":["../../../veryl/45_var_let_in_always.veryl"],"names":["","module","Module45",";","logic","a","=","1","[","10","]","b","c","always_ff","(",")","begin","x","*","end","always_comb","y","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,eAAHC,iBAAaC,EAAEC,CAACJ;IACbC,MAAKI,CAACC,MAAEC,EAAXC,CAAYR;IACTC,MAAKI,CAACC,MAAEC,EAAXE,CAAYT;;IAEhBU,YAAUC,SAACT,CAACU,EAAEC;QACHZ,MAAKI,CAACC,MAAEC,EAAXO,CAAYd;QAChBc,EAAEX,GAAEC,CAACJ;QACLQ,GAAEL,EAAEW,EAAEC,EAAEX,CAACJ;IACbgB;;IAEAC,YAAYJ;QACDZ,MAAKI,CAACC,MAAEC,EAAXW;UAAaf,EAAEC,CAACJ;QACpBS,EAAEN,EAAEe,EAAEH,EAAEX,CAACJ;IACbgB;AACJG"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/46_var_let_anywhere.sv.map b/testcases/map/testcases/sv/46_var_let_anywhere.sv.map
index b3393af02..b5bcd9a55 100644
--- a/testcases/map/testcases/sv/46_var_let_anywhere.sv.map
+++ b/testcases/map/testcases/sv/46_var_let_anywhere.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"46_var_let_anywhere.sv.map","sources":["../../../veryl/46_var_let_anywhere.veryl"],"names":["","module","Module46",";","logic","a","=","1","[","10","]","b","c","d","e","always_ff","(",")","begin","x","*","end","always_comb","y","function","FuncA","input",",","output","ref","int unsigned","/","+","return","2","endfunction","FuncB","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,eAAHC;kBAAaC,EAAEC,CAACJ;IACbC,MAAKI,CAACC,MAAEC,EAAXC,CAAYR;IACTC,MAAKI,CAACC,MAAEC,EAAXE,CAAYT;IACTC,MAAKI,CAACC,MAAEC,EAAXG,CAAYV;IACTC,MAAKI,CAACC,MAAEC,EAAXI,CAAYX;;IAEhBY,YAAUC,SAACX,CAACY,EAAEC;QAEHd,MAAKI,CAACC,MAAEC,EAAXS,CAAYhB;QADhBU,GAAEP,EAAEC,CAACJ;;QAELgB,EAAEb,GAAEC,CAACJ;QACLQ,GAAEL,EAAEa,EAAEC,EAAEb,CAACJ;IACbkB;;IAEAC,YAAYJ;QAEDd,MAAKI,CAACC,MAAEC,EAAXa;QADJT,EAAER,EAAEC,CAACJ;UACYG,EAAEC,CAACJ;QACpBS,EAAEN,EAAEiB,EAAEH,EAAEb,CAACJ;IACbkB;;IAEAG,mBAIKpB,MAAKI,CAACC,MAAEC,EAJJe,KAAMT;QACRU,OAAOtB,MAAKI,CAACC,MAAEC,EAAlBL,CAAmBsB;QAChBC,OAAOxB,MAAKI,CAACC,MAAEC,EAAlBC,CAAmBgB;QAChBE,OAAOzB,MAAKI,CAACC,MAAEC,EAAlBE,CAAmBZ;IACvBiB,EAAEjB,CAAaA;QAEJ8B,aAAHjB,CAAMV;QADVS,EAAEN,EAAED,EAAE0B,EAAExB,CAACJ;;QAETU,EAAEP,EAAEC,CAACJ;QACLQ,EAAEL,EAAED,EAAE2B,EAAEzB,EAAEyB,EAAEnB,CAACV;QACb8B,OAAO5B,EAAE2B,EAAEE,CAAC/B;IAChBgC;;IAEAX,mBAIKpB,MAAKI,CAACC,MAAEC,EAJJ0B,KAAMpB;QACRU,OAAOtB,MAAKI,CAACC,MAAEC,EAAlBL,CAAmBsB;QAChBC,OAAOxB,MAAKI,CAACC,MAAEC,EAAlBC,CAAmBgB;QAChBE,OAAOzB,MAAKI,CAACC,MAAEC,EAAlBE,CAAmBZ;IACvBiB,EAAEjB,CAAaA;QAEJ8B,aAAHjB;QADJD,EAAEN,EAAED,EAAE0B,EAAExB,CAACJ;UACEG,EAAEC,CAACJ;QACdQ,EAAEL,EAAED,EAAE2B,EAAEzB,EAAEyB,EAAEnB,CAACV;QACb8B,OAAO5B,EAAE2B,EAAEE,CAAC/B;IAChBgC;AACJE"}
\ No newline at end of file
+{"version":3,"file":"46_var_let_anywhere.sv.map","sources":["../../../veryl/46_var_let_anywhere.veryl"],"names":["","module","Module46",";","logic","a","=","1","[","10","]","b","c","d","e","always_ff","(",")","begin","x","*","end","always_comb","y","function","FuncA","input",",","output","ref","int unsigned","/","+","return","2","endfunction","FuncB","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,eAAHC,iBAAaC,EAAEC,CAACJ;IACbC,MAAKI,CAACC,MAAEC,EAAXC,CAAYR;IACTC,MAAKI,CAACC,MAAEC,EAAXE,CAAYT;IACTC,MAAKI,CAACC,MAAEC,EAAXG,CAAYV;IACTC,MAAKI,CAACC,MAAEC,EAAXI,CAAYX;;IAEhBY,YAAUC,SAACX,CAACY,EAAEC;QAEHd,MAAKI,CAACC,MAAEC,EAAXS,CAAYhB;QADhBU,GAAEP,EAAEC,CAACJ;;QAELgB,EAAEb,GAAEC,CAACJ;QACLQ,GAAEL,EAAEa,EAAEC,EAAEb,CAACJ;IACbkB;;IAEAC,YAAYJ;QAEDd,MAAKI,CAACC,MAAEC,EAAXa;QADJT,EAAER,EAAEC,CAACJ;UACYG,EAAEC,CAACJ;QACpBS,EAAEN,EAAEiB,EAAEH,EAAEb,CAACJ;IACbkB;;IAEAG,mBAIKpB,MAAKI,CAACC,MAAEC,EAJJe,KAAMT;QACRU,OAAOtB,MAAKI,CAACC,MAAEC,EAAlBL,CAAmBsB;QAChBC,OAAOxB,MAAKI,CAACC,MAAEC,EAAlBC,CAAmBgB;QAChBE,OAAOzB,MAAKI,CAACC,MAAEC,EAAlBE,CAAmBZ;IACvBiB,EAAEjB,CAAaA;QAEJ8B,aAAHjB,CAAMV;QADVS,EAAEN,EAAED,EAAE0B,EAAExB,CAACJ;;QAETU,EAAEP,EAAEC,CAACJ;QACLQ,EAAEL,EAAED,EAAE2B,EAAEzB,EAAEyB,EAAEnB,CAACV;QACb8B,OAAO5B,EAAE2B,EAAEE,CAAC/B;IAChBgC;;IAEAX,mBAIKpB,MAAKI,CAACC,MAAEC,EAJJ0B,KAAMpB;QACRU,OAAOtB,MAAKI,CAACC,MAAEC,EAAlBL,CAAmBsB;QAChBC,OAAOxB,MAAKI,CAACC,MAAEC,EAAlBC,CAAmBgB;QAChBE,OAAOzB,MAAKI,CAACC,MAAEC,EAAlBE,CAAmBZ;IACvBiB,EAAEjB,CAAaA;QAEJ8B,aAAHjB;QADJD,EAAEN,EAAED,EAAE0B,EAAExB,CAACJ;UACEG,EAAEC,CAACJ;QACdQ,EAAEL,EAAED,EAAE2B,EAAEzB,EAAEyB,EAAEnB,CAACV;QACb8B,OAAO5B,EAAE2B,EAAEE,CAAC/B;IAChBgC;AACJE"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/50_enum_over_typedef.sv.map b/testcases/map/testcases/sv/50_enum_over_typedef.sv.map
index 0ea7db3bc..f86f30063 100644
--- a/testcases/map/testcases/sv/50_enum_over_typedef.sv.map
+++ b/testcases/map/testcases/sv/50_enum_over_typedef.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"50_enum_over_typedef.sv.map","sources":["../../../veryl/50_enum_over_typedef.veryl"],"names":["","package","Package50",";","typedef enum","logic","[","1","]","{","EnumA_memberA",",","EnumA_memberB","EnumA","endpackage","module","Module50","typedef","veryl_testcase_Package50::EnumA","EnumB","_a","=","veryl_testcase_Package50::EnumA_memberA","_b","veryl_testcase_Package50::EnumA_memberB","endmodule"],"mappings":"AAAAA,AAAAC,uBAAQC,SAAUC;IACdC,aAAYC,MAAKC,CAACC,KAACC,EAAEC;QACjBC,aAAOC;QACPC,aAAOZ;MAFNa,MAGLb;AACJc;;AAEAC,sBAAOC,QAASb;IACZc,QAAaC,gCAARC,KAAwBhB;;IAErBe,gCAAJE;mBAAqBC,EAAEC,uCAAyBnB;IAC5CgB,gCAAJI;mBAAqBF,EAAEG,uCAAcrB;AAC7CsB"}
\ No newline at end of file
+{"version":3,"file":"50_enum_over_typedef.sv.map","sources":["../../../veryl/50_enum_over_typedef.veryl"],"names":["","package","Package50",";","typedef enum","logic","[","1","]","{","EnumA_memberA",",","EnumA_memberB","EnumA","endpackage","module","Module50","typedef","veryl_testcase_Package50::EnumA","EnumB","_a","=","veryl_testcase_Package50::EnumA_memberA","_b","veryl_testcase_Package50::EnumA_memberB","endmodule"],"mappings":"AAAAA,AAAAC,uBAAQC,SAAUC;IACdC,aAAYC,MAAKC,CAACC,KAACC,EAAEC;QACjBC,aAAOC;QACPC,aAAOZ;MAFNa,MAGLb;AACJc;;AAEAC,sBAAOC,QAASb;IACZc,QAAaC,gCAARC,KAAwBhB;;IAErBe,gCAAJE,mBAAqBC,EAAEC,uCAAyBnB;IAC5CgB,gCAAJI,mBAAqBF,EAAEG,uCAAcrB;AAC7CsB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/51_array_literal.sv.map b/testcases/map/testcases/sv/51_array_literal.sv.map
index 1f55d2fbe..57b9f70d7 100644
--- a/testcases/map/testcases/sv/51_array_literal.sv.map
+++ b/testcases/map/testcases/sv/51_array_literal.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"51_array_literal.sv.map","sources":["../../../veryl/51_array_literal.veryl"],"names":["","module","Module51",";","logic","_a","[","2","]","=","'{","1",",","}","_b","_c","default",":","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACJC,MAAJC,GAAUC,GAACC,GAACC;mBAAEC,EAAEC,EAAEC,CAACC,EAAED,CAAEE,CAACV;IACpBC,MAAJU,GAAUR,GAACC,GAACC;mBAAEC,EAAEC,EAAWH,EAATI,EAAUE,CAACV;IACzBC,MAAJW,GAAUT,GAACC,GAACC;mBAAEC,EAAEC,EAAEM,OAAOC,EAAEN,CAACE,CAACV;AACrCe"}
\ No newline at end of file
+{"version":3,"file":"51_array_literal.sv.map","sources":["../../../veryl/51_array_literal.veryl"],"names":["","module","Module51",";","logic","_a","[","2","]","=","'{","1",",","}","_b","_c","default",":","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACJC,MAAJC,GAAUC,GAACC,GAACC,kBAAEC,EAAEC,EAAEC,CAACC,EAAED,CAAEE,CAACV;IACpBC,MAAJU,GAAUR,GAACC,GAACC,kBAAEC,EAAEC,EAAWH,EAATI,EAAUE,CAACV;IACzBC,MAAJW,GAAUT,GAACC,GAACC,kBAAEC,EAAEC,EAAEM,OAAOC,EAAEN,CAACE,CAACV;AACrCe"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/54_generic_function.sv.map b/testcases/map/testcases/sv/54_generic_function.sv.map
index 185467551..0ca12cf46 100644
--- a/testcases/map/testcases/sv/54_generic_function.sv.map
+++ b/testcases/map/testcases/sv/54_generic_function.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"54_generic_function.sv.map","sources":["../../../veryl/54_generic_function.veryl"],"names":["","module","Module54",";","function","logic","[","10","]","(","input","a",")","return","+","1","endfunction","20","_a","=","__FuncA__10","_b","_c","__FuncA__20","_d","2","4","12","_e","__FuncB__10__2","_f","14","_g","__FuncB__10__4","_h","u",".","veryl_testcase_Interface54","_i","__FuncC__u","endmodule","interface","Interface54","endinterface"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,mBAEKC,MAAKC,CAACC,MAACC,aAFeC;QACpBC,MAAML,MAAKC,CAACC,MAACC,EAAhBG,CAAiBX;IACrBY,EAAEZ,CAAYA;QACVa,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;IAJAZ,mBAEKC,MAAKC,CAACW,MAACT,aAFeC;QACpBC,MAAML,MAAKC,CAACW,MAACT,EAAhBG,CAAiBX;IACrBY,EAAEZ,CAAYA;QACVa,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;;IAEQX,MAAKC,CAACC,MAAEC,EAAZU;mBAAcC,EAAEC,WAAWX,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACC,MAAEC,EAAZa;mBAAcF,EAAEC,WAAWX,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACW,MAAET,EAAZc;mBAAcH,EAAEI,WAAWd,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACW,MAAET,EAAZgB;mBAAcL,EAAEI,WAAWd,CAACM,CAACH,CAACT;;IAElCC,mBAEKC,MAAKC,CAACC,GAAEO,EAAEW,KAACjB,gBAFyBC;QAClCC,MAAML,MAAKC,CAACC,GAAEO,EAAEW,KAACjB,EAApBG,CAAqBX;IACzBY,EAAEZ,CAAgBA;QACda,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;IAJAZ,mBAEKC,MAAKC,CAACC,GAAEO,EAAEY,KAAClB,gBAFyBC;QAClCC,MAAML,MAAKC,CAACC,GAAEO,EAAEY,KAAClB,EAApBG,CAAqBX;IACzBY,EAAEZ,CAAgBA;QACda,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;;IAEQX,MAAKC,CAACqB,MAAEnB,EAAZoB;mBAAcT,EAAEU,cAAWpB,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACqB,MAAEnB,EAAZsB;mBAAcX,EAAEU,cAAWpB,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACyB,MAAEvB,EAAZwB;mBAAcb,EAAEc,cAAcxB,CAACM,CAACH,CAACT;IAC7BE,MAAKC,CAACyB,MAAEvB,EAAZ0B;mBAAcf,EAAEc,cAAcxB,CAACM,CAACH,CAACT;;IAErCC,mBAA6CC,gBAANI,CAACG,EAAEZ,CAASA;QAC/Ca,OAAOsB,CAAEC,CAACzB,CAACR;IACfa;;IAEAhB,AAAQqC,2BAAHF,IAAchC;;IAEXE,MAAJiC;mBAAUnB,EAAEoB,UAAU9B,CAACG,CAACT;AAChCqC;;AAEAC,yBAAUC,WAAYvC;IACXE,MAAHM,CAAQR;AAChBwC"}
\ No newline at end of file
+{"version":3,"file":"54_generic_function.sv.map","sources":["../../../veryl/54_generic_function.veryl"],"names":["","module","Module54",";","function","logic","[","10","]","(","input","a",")","return","+","1","endfunction","20","_a","=","__FuncA__10","_b","_c","__FuncA__20","_d","2","4","12","_e","__FuncB__10__2","_f","14","_g","__FuncB__10__4","_h","u",".","veryl_testcase_Interface54","_i","__FuncC__u","endmodule","interface","Interface54","endinterface"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,mBAEKC,MAAKC,CAACC,MAACC,aAFeC;QACpBC,MAAML,MAAKC,CAACC,MAACC,EAAhBG,CAAiBX;IACrBY,EAAEZ,CAAYA;QACVa,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;IAJAZ,mBAEKC,MAAKC,CAACW,MAACT,aAFeC;QACpBC,MAAML,MAAKC,CAACW,MAACT,EAAhBG,CAAiBX;IACrBY,EAAEZ,CAAYA;QACVa,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;;IAEQX,MAAKC,CAACC,MAAEC,EAAZU,mBAAcC,EAAEC,WAAWX,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACC,MAAEC,EAAZa,mBAAcF,EAAEC,WAAWX,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACW,MAAET,EAAZc,mBAAcH,EAAEI,WAAWd,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACW,MAAET,EAAZgB,mBAAcL,EAAEI,WAAWd,CAACM,CAACH,CAACT;;IAElCC,mBAEKC,MAAKC,CAACC,GAAEO,EAAEW,KAACjB,gBAFyBC;QAClCC,MAAML,MAAKC,CAACC,GAAEO,EAAEW,KAACjB,EAApBG,CAAqBX;IACzBY,EAAEZ,CAAgBA;QACda,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;IAJAZ,mBAEKC,MAAKC,CAACC,GAAEO,EAAEY,KAAClB,gBAFyBC;QAClCC,MAAML,MAAKC,CAACC,GAAEO,EAAEY,KAAClB,EAApBG,CAAqBX;IACzBY,EAAEZ,CAAgBA;QACda,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;;IAEQX,MAAKC,CAACqB,MAAEnB,EAAZoB,mBAAcT,EAAEU,cAAWpB,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACqB,MAAEnB,EAAZsB,mBAAcX,EAAEU,cAAWpB,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACyB,MAAEvB,EAAZwB,mBAAcb,EAAEc,cAAcxB,CAACM,CAACH,CAACT;IAC7BE,MAAKC,CAACyB,MAAEvB,EAAZ0B,mBAAcf,EAAEc,cAAcxB,CAACM,CAACH,CAACT;;IAErCC,mBAA6CC,gBAANI,CAACG,EAAEZ,CAASA;QAC/Ca,OAAOsB,CAAEC,CAACzB,CAACR;IACfa;;IAEAhB,AAAQqC,2BAAHF,IAAchC;;IAEXE,MAAJiC,mBAAUnB,EAAEoB,UAAU9B,CAACG,CAACT;AAChCqC;;AAEAC,yBAAUC,WAAYvC;IACXE,MAAHM,CAAQR;AAChBwC"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/55_generic_module.sv.map b/testcases/map/testcases/sv/55_generic_module.sv.map
index 61f514dc1..a3cd9fa96 100644
--- a/testcases/map/testcases/sv/55_generic_module.sv.map
+++ b/testcases/map/testcases/sv/55_generic_module.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"55_generic_module.sv.map","sources":["../../../veryl/55_generic_module.veryl"],"names":["","module","Module55",";","veryl_testcase___Module55A__Module55B","u0","veryl_testcase___Module55A__Module55C","u1","veryl_testcase___Module55E__Module55C","u2","veryl_testcase___Module55E__Module55D","u3","veryl_testcase___Module55F__Module55C","u4","veryl_testcase___Module55F__Module55B","u5","veryl_testcase___Module55H__10","u6","u7","endmodule","veryl_testcase_Module55B","u","veryl_testcase_Module55C","veryl_testcase_Module55D","Module55B","Module55C","Module55D","veryl_testcase___Module55A__Module55D","typedef struct packed","{","logic","[","10","]","value","__StructH__10","_a","=","0"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZH,AAASI,sCAAJC,KAA0BF;IAC/BH,AAASM,sCAAJC,KAA0BJ;IAC/BH,AAASQ,sCAAJC,KAA0BN;IAC/BH,AAASU,sCAAJC,KAA0BR;IAC/BH,AAASY,sCAAJC,KAA0BV;IAC/BH,AAASc,sCAAJC,KAAiBZ;IACtBH,AAASgB,+BAAJC,KAAmBd;IACxBH,AAASgB,+BAAJE,KAAmBf;AAC5BgB;;;AAKIlB,4CAA+BE;IAC/BH,AAAQoB,yBAAHC,IAAIlB;AACbgB;AAFIlB,4CAA+BE;IAC/BH,AAAQsB,yBAAHD,IAAIlB;AACbgB;AAFIlB,4CAA+BE;IAC/BH,AAAQuB,yBAAHF,IAAIlB;AACbgB;;AAEAlB,sBAAOuB,SAAsBrB;AAACgB;;AAE9BlB,sBAAOwB,SAAsBtB;AAACgB;;AAE9BlB,sBAAOyB,SAAsBvB;AAACgB;;AAE9BlB,4CAA+BE;IAC3BH,AAAQM,sCAAHe,IAAiBlB;AAC1BgB;AAFAlB,4CAA+BE;IAC3BH,AAAQ2B,sCAAHN,IAAiBlB;AAC1BgB;;AAEAlB,4CAA2CE;IACvCH,AAAQsB,yBAAHD,IAAIlB;AACbgB;AAFAlB,4CAA2CE;IACvCH,AAAQoB,yBAAHC,IAAIlB;AACbgB;;;AAMAlB,qCAA6BE;IACzByB,sBAA2BC;QAChBC,MAAKC,CAACC,MAACC,EAAdC,KAAe/B;oBACnBH;;IAEQmC,cAAJC;mBAAiBC,EAAEC,CAACnC;AAC5BgB"}
\ No newline at end of file
+{"version":3,"file":"55_generic_module.sv.map","sources":["../../../veryl/55_generic_module.veryl"],"names":["","module","Module55",";","veryl_testcase___Module55A__Module55B","u0","veryl_testcase___Module55A__Module55C","u1","veryl_testcase___Module55E__Module55C","u2","veryl_testcase___Module55E__Module55D","u3","veryl_testcase___Module55F__Module55C","u4","veryl_testcase___Module55F__Module55B","u5","veryl_testcase___Module55H__10","u6","u7","endmodule","veryl_testcase_Module55B","u","veryl_testcase_Module55C","veryl_testcase_Module55D","Module55B","Module55C","Module55D","veryl_testcase___Module55A__Module55D","typedef struct packed","{","logic","[","10","]","value","__StructH__10","_a","=","0"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZH,AAASI,sCAAJC,KAA0BF;IAC/BH,AAASM,sCAAJC,KAA0BJ;IAC/BH,AAASQ,sCAAJC,KAA0BN;IAC/BH,AAASU,sCAAJC,KAA0BR;IAC/BH,AAASY,sCAAJC,KAA0BV;IAC/BH,AAASc,sCAAJC,KAAiBZ;IACtBH,AAASgB,+BAAJC,KAAmBd;IACxBH,AAASgB,+BAAJE,KAAmBf;AAC5BgB;;;AAKIlB,4CAA+BE;IAC/BH,AAAQoB,yBAAHC,IAAIlB;AACbgB;AAFIlB,4CAA+BE;IAC/BH,AAAQsB,yBAAHD,IAAIlB;AACbgB;AAFIlB,4CAA+BE;IAC/BH,AAAQuB,yBAAHF,IAAIlB;AACbgB;;AAEAlB,sBAAOuB,SAAsBrB;AAACgB;;AAE9BlB,sBAAOwB,SAAsBtB;AAACgB;;AAE9BlB,sBAAOyB,SAAsBvB;AAACgB;;AAE9BlB,4CAA+BE;IAC3BH,AAAQM,sCAAHe,IAAiBlB;AAC1BgB;AAFAlB,4CAA+BE;IAC3BH,AAAQ2B,sCAAHN,IAAiBlB;AAC1BgB;;AAEAlB,4CAA2CE;IACvCH,AAAQsB,yBAAHD,IAAIlB;AACbgB;AAFAlB,4CAA2CE;IACvCH,AAAQoB,yBAAHC,IAAIlB;AACbgB;;;AAMAlB,qCAA6BE;IACzByB,sBAA2BC;QAChBC,MAAKC,CAACC,MAACC,EAAdC,KAAe/B;oBACnBH;;IAEQmC,cAAJC,mBAAiBC,EAAEC,CAACnC;AAC5BgB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/56_generic_interface.sv.map b/testcases/map/testcases/sv/56_generic_interface.sv.map
index f72f3a7ad..ef106d869 100644
--- a/testcases/map/testcases/sv/56_generic_interface.sv.map
+++ b/testcases/map/testcases/sv/56_generic_interface.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"56_generic_interface.sv.map","sources":["../../../veryl/56_generic_interface.veryl"],"names":["","package","Package56A",";","localparam","int unsigned","X","=","1","endpackage","Package56B","2","module","Module56","import","veryl_testcase_Package56A::X","veryl_testcase___Interface56A__Package56A_X","u0","veryl_testcase___Interface56A__Package56B_X","u1","veryl_testcase___Interface56B__Package56A_X","u2","u3","veryl_testcase___Interface56B__3","u4","u5","veryl_testcase___Module56Sub__1","u6","logic","_a",".","_b","_c","endmodule","veryl_testcase___Interface56A__1","u","function","f","(",")","endfunction","interface","[","]","endinterface","veryl_testcase_Package56B::X","3"],"mappings":"AAAAA,AAAAC,uBAAQC,UAAWC;IACfC,WAASC,aAAHC,EAAOC,EAAEC,CAACL;AACpBM;;AAEAR,uBAAQS,UAAWP;IACfC,WAASC,aAAHC,EAAOC,EAAEI,CAACR;AACpBM;;AAEAG,sBAAOC,QAASV;IACZW,OAAOC,4BAAaZ;IACpBH,AAASgB,4CAAJC,KAAiCd;IACtCH,AAASkB,4CAAJC,KAAiChB;IACtCH,AAASoB,4CAAJC,KAAiClB;IACtCH,AAASoB,4CAAJE,KAAiCnB;IACtCH,AAASuB,iCAAJC,KAAoBrB;IACzBH,AAASoB,4CAAJK,KAAqBtB;IAC1BH,AAAS0B,gCAAJC,KAAoBxB;;IAEjByB,MAAJC;mBAAUtB,EAAEU,EAAEa,CAACD,EAAE1B;IACbyB,MAAJG;mBAAUxB,EAAEc,EAAES,CAACC,EAAE5B;IACbyB,MAAJI;mBAAUzB,EAAEkB,EAAEK,CAACC,EAAE5B;AACzB8B;;AAEArB,sCAA+BT;IAC3BH,AAAQkC,iCAAHC,IAAoBhC;IACzBiC,wBAASC,CAAEC,CAACC,GAAEvC;IAACwC;AACnBP;;;AAGIQ,qDAAmCtC;IAC3ByB,MAAKc,CAAC3B,gCAAC4B,6BAAXd,EAAY1B;AACpByC;;;AAFIH,qDAAmCtC;IAC3ByB,MAAKc,CAACG,gCAACF,6BAAXd,EAAY1B;AACpByC;;;AAFIH,0CAAmCtC;IAC3ByB,MAAKc,CAAClC,KAACmC,6BAAXd,EAAY1B;AACpByC;;;AAGIH,qDAAuCtC;IAC/ByB,MAAKc,CAAC3B,gCAAC4B,6BAAXZ,EAAY5B;AACpByC;AAFIH,0CAAuCtC;IAC/ByB,MAAKc,CAACI,KAACH,6BAAXZ,EAAY5B;AACpByC"}
\ No newline at end of file
+{"version":3,"file":"56_generic_interface.sv.map","sources":["../../../veryl/56_generic_interface.veryl"],"names":["","package","Package56A",";","localparam","int unsigned","X","=","1","endpackage","Package56B","2","module","Module56","import","veryl_testcase_Package56A::X","veryl_testcase___Interface56A__Package56A_X","u0","veryl_testcase___Interface56A__Package56B_X","u1","veryl_testcase___Interface56B__Package56A_X","u2","u3","veryl_testcase___Interface56B__3","u4","u5","veryl_testcase___Module56Sub__1","u6","logic","_a",".","_b","_c","endmodule","veryl_testcase___Interface56A__1","u","function","f","(",")","endfunction","interface","[","]","endinterface","veryl_testcase_Package56B::X","3"],"mappings":"AAAAA,AAAAC,uBAAQC,UAAWC;IACfC,WAASC,aAAHC,EAAOC,EAAEC,CAACL;AACpBM;;AAEAR,uBAAQS,UAAWP;IACfC,WAASC,aAAHC,EAAOC,EAAEI,CAACR;AACpBM;;AAEAG,sBAAOC,QAASV;IACZW,OAAOC,4BAAaZ;IACpBH,AAASgB,4CAAJC,KAAiCd;IACtCH,AAASkB,4CAAJC,KAAiChB;IACtCH,AAASoB,4CAAJC,KAAiClB;IACtCH,AAASoB,4CAAJE,KAAiCnB;IACtCH,AAASuB,iCAAJC,KAAoBrB;IACzBH,AAASoB,4CAAJK,KAAqBtB;IAC1BH,AAAS0B,gCAAJC,KAAoBxB;;IAEjByB,MAAJC,mBAAUtB,EAAEU,EAAEa,CAACD,EAAE1B;IACbyB,MAAJG,mBAAUxB,EAAEc,EAAES,CAACC,EAAE5B;IACbyB,MAAJI,mBAAUzB,EAAEkB,EAAEK,CAACC,EAAE5B;AACzB8B;;AAEArB,sCAA+BT;IAC3BH,AAAQkC,iCAAHC,IAAoBhC;IACzBiC,wBAASC,CAAEC,CAACC,GAAEvC;IAACwC;AACnBP;;;AAGIQ,qDAAmCtC;IAC3ByB,MAAKc,CAAC3B,gCAAC4B,6BAAXd,EAAY1B;AACpByC;;;AAFIH,qDAAmCtC;IAC3ByB,MAAKc,CAACG,gCAACF,6BAAXd,EAAY1B;AACpByC;;;AAFIH,0CAAmCtC;IAC3ByB,MAAKc,CAAClC,KAACmC,6BAAXd,EAAY1B;AACpByC;;;AAGIH,qDAAuCtC;IAC/ByB,MAAKc,CAAC3B,gCAAC4B,6BAAXZ,EAAY5B;AACpByC;AAFIH,0CAAuCtC;IAC/ByB,MAAKc,CAACI,KAACH,6BAAXZ,EAAY5B;AACpByC"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/62_raw_identifier.sv.map b/testcases/map/testcases/sv/62_raw_identifier.sv.map
index 6ded512d8..1d0821e5a 100644
--- a/testcases/map/testcases/sv/62_raw_identifier.sv.map
+++ b/testcases/map/testcases/sv/62_raw_identifier.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"62_raw_identifier.sv.map","sources":["../../../veryl/62_raw_identifier.veryl"],"names":["","module","Module62",";","logic","clock","reset","in","=","0","out","always_comb","1","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACCC,MAATC,KAAcF;IACLC,MAATE,KAAcH;IACLC,MAATG;mBAAeC,EAAEC,CAACN;IACTC,MAATM,KAAcP;IAClBQ,YAAON,MAAQG,EAAEI,CAACT;IAClBQ,YAAOL,MAAQE,EAAEI,CAACT;IAClBQ,YAAOD,MAAQF,EAAED,EAAIJ;AACzBU"}
\ No newline at end of file
+{"version":3,"file":"62_raw_identifier.sv.map","sources":["../../../veryl/62_raw_identifier.veryl"],"names":["","module","Module62",";","logic","clock","reset","in","=","0","out","always_comb","1","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACCC,MAATC,KAAcF;IACLC,MAATE,KAAcH;IACLC,MAATG,sBAAeC,EAAEC,CAACN;IACTC,MAATM,KAAcP;IAClBQ,YAAON,MAAQG,EAAEI,CAACT;IAClBQ,YAAOL,MAAQE,EAAEI,CAACT;IAClBQ,YAAOD,MAAQF,EAAED,EAAIJ;AACzBU"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/63_prefix_suffix.sv.map b/testcases/map/testcases/sv/63_prefix_suffix.sv.map
index a64d0165f..999c2e420 100644
--- a/testcases/map/testcases/sv/63_prefix_suffix.sv.map
+++ b/testcases/map/testcases/sv/63_prefix_suffix.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"63_prefix_suffix.sv.map","sources":["../../../veryl/63_prefix_suffix.veryl"],"names":["","module","Module63","(","input","logic","i_clk",",","i_rst_n","i_data_a",")",";","veryl_testcase_Module63A","u","a","always_ff","begin","if","=","0","end","else","1","_b","endmodule","Module63A"],"mappings":"AAAAA,AAAAC,sBAAOC,SAASC;IACFC,MAAMC,MAAhBC,QAAqBC;IACXH,MAAMC,MAAhBG,QAAqBD;IACXH,MAAMC,MAAhBI,QAAqBT;AACzBU,CAAEC;IACEX,AAAQY,yBAAHC,EAAaV;SACdG,UAAAA,SAAUC;SACVC,UAAAA,SAAUD;SACVE,UAAAA,SAAUT;IACdU,CAACC;;IAEMN,MAAHS,CAAQH;;IAEZI,6CAAUC;QACNC,cAASD;YACLF,GAAEI,EAAEC,CAACR;QACTS,IAAEC,KAAKL;YACHF,GAAEI,EAAEI,CAACX;QACTS;IACJA;;IAEQf,MAAJkB;mBAAUL,EAAEV,OAAKG;AACzBa;;AAEAvB,sBAAOwB,UAAUtB;IACHC,MAAMC,MAAhBC,QAAqBC;IACXH,MAAMC,MAAhBG,QAAqBD;IACXH,MAAMC,MAAhBI,QAAqBT;AACzBU,CAAEC;AAACa"}
\ No newline at end of file
+{"version":3,"file":"63_prefix_suffix.sv.map","sources":["../../../veryl/63_prefix_suffix.veryl"],"names":["","module","Module63","(","input","logic","i_clk",",","i_rst_n","i_data_a",")",";","veryl_testcase_Module63A","u","a","always_ff","begin","if","=","0","end","else","1","_b","endmodule","Module63A"],"mappings":"AAAAA,AAAAC,sBAAOC,SAASC;IACFC,MAAMC,MAAhBC,QAAqBC;IACXH,MAAMC,MAAhBG,QAAqBD;IACXH,MAAMC,MAAhBI,QAAqBT;AACzBU,CAAEC;IACEX,AAAQY,yBAAHC,EAAaV;SACdG,UAAAA,SAAUC;SACVC,UAAAA,SAAUD;SACVE,UAAAA,SAAUT;IACdU,CAACC;;IAEMN,MAAHS,CAAQH;;IAEZI,6CAAUC;QACNC,cAASD;YACLF,GAAEI,EAAEC,CAACR;QACTS,IAAEC,KAAKL;YACHF,GAAEI,EAAEI,CAACX;QACTS;IACJA;;IAEQf,MAAJkB,mBAAUL,EAAEV,OAAKG;AACzBa;;AAEAvB,sBAAOwB,UAAUtB;IACHC,MAAMC,MAAhBC,QAAqBC;IACXH,MAAMC,MAAhBG,QAAqBD;IACXH,MAAMC,MAAhBI,QAAqBT;AACzBU,CAAEC;AAACa"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/64_cast_to_builtin.sv.map b/testcases/map/testcases/sv/64_cast_to_builtin.sv.map
index 16768b023..0d7d8ba00 100644
--- a/testcases/map/testcases/sv/64_cast_to_builtin.sv.map
+++ b/testcases/map/testcases/sv/64_cast_to_builtin.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"64_cast_to_builtin.sv.map","sources":["../../../veryl/64_cast_to_builtin.veryl"],"names":["","module","Module64",";","int unsigned","a","=","1","_x0","longint unsigned","_x1","int signed","_x2","longint signed","_x3","shortreal","_x4","real","_x5","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,aAAHC;kBAAOC,EAAEC,CAACJ;;IAELC,iBAALI;oBAASF,iBAAED,GAAQF;IACdM,iBAALC;oBAASJ,qBAAED,GAAQF;IACdQ,iBAALC;oBAASN,eAAED,GAAQF;IACdU,iBAALC;oBAASR,mBAAED,GAAQF;IACdY,iBAALC;oBAASV,EAAOS,WAALV,EAAQF;IACdc,iBAALC;oBAASZ,EAAOW,MAALZ,EAAQF;AAC3BgB"}
\ No newline at end of file
+{"version":3,"file":"64_cast_to_builtin.sv.map","sources":["../../../veryl/64_cast_to_builtin.veryl"],"names":["","module","Module64",";","int unsigned","a","=","1","_x0","longint unsigned","_x1","int signed","_x2","longint signed","_x3","shortreal","_x4","real","_x5","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACLC,aAAHC,iBAAOC,EAAEC,CAACJ;;IAELC,iBAALI,qBAASF,iBAAED,GAAQF;IACdM,iBAALC,qBAASJ,qBAAED,GAAQF;IACdQ,iBAALC,qBAASN,eAAED,GAAQF;IACdU,iBAALC,qBAASR,mBAAED,GAAQF;IACdY,iBAALC,qBAASV,EAAOS,WAALV,EAAQF;IACdc,iBAALC,qBAASZ,EAAOW,MAALZ,EAAQF;AAC3BgB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/65_cast_to_clock_reset.sv.map b/testcases/map/testcases/sv/65_cast_to_clock_reset.sv.map
index d4273ae29..fd5cdaa86 100644
--- a/testcases/map/testcases/sv/65_cast_to_clock_reset.sv.map
+++ b/testcases/map/testcases/sv/65_cast_to_clock_reset.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"65_cast_to_clock_reset.sv.map","sources":["../../../veryl/65_cast_to_clock_reset.veryl"],"names":["","module","Module65",";","logic","a","=","1","b_n","c","d","e","f","_x0","_x1","_x2","_x3","_x4","_x5","_x6_n","_x7_n","_x8_n","_x9_n","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACFC,MAANC;kBAAuBC,EAAEC,CAACJ;IACpBC,MAANI;oBAAuBF,EAAEC,CAACJ;IACpBC,MAANK;kBAAuBH,EAAEC,CAACJ;IACpBC,MAANM;kBAAuBJ,EAAEC,CAACJ;IACpBC,MAANO;kBAAuBL,EAAEC,CAACJ;IACpBC,MAANQ;kBAAuBN,EAAEC,CAACJ;;IAElBC,MAARS;oBAAyBP,EAAED,CAAkBF;IACrCC,MAARU;oBAAyBR,EAAED,CAAkBF;IACrCC,MAARW;oBAAyBT,GAAEE,GAAqBL;IACxCC,MAARY;oBAAyBV,EAAEE,GAAoBL;IACvCC,MAARa;oBAAyBX,GAAEE,GAAoBL;IACvCC,MAARc;oBAAyBZ,EAAEE,GAAmBL;IACtCC,MAARe;sBAAyBb,GAAEG,CAAUN;IAC7BC,MAARgB;sBAAyBd,EAAEI,CAAUP;IAC7BC,MAARiB;sBAAyBf,GAAEK,CAAUR;IAC7BC,MAARkB;sBAAyBhB,EAAEM,CAAUT;AAC7CoB"}
\ No newline at end of file
+{"version":3,"file":"65_cast_to_clock_reset.sv.map","sources":["../../../veryl/65_cast_to_clock_reset.veryl"],"names":["","module","Module65",";","logic","a","=","1","b_n","c","d","e","f","_x0","_x1","_x2","_x3","_x4","_x5","_x6_n","_x7_n","_x8_n","_x9_n","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACFC,MAANC,mBAAuBC,EAAEC,CAACJ;IACpBC,MAANI,qBAAuBF,EAAEC,CAACJ;IACpBC,MAANK,mBAAuBH,EAAEC,CAACJ;IACpBC,MAANM,mBAAuBJ,EAAEC,CAACJ;IACpBC,MAANO,mBAAuBL,EAAEC,CAACJ;IACpBC,MAANQ,mBAAuBN,EAAEC,CAACJ;;IAElBC,MAARS,uBAAyBP,EAAED,CAAkBF;IACrCC,MAARU,uBAAyBR,EAAED,CAAkBF;IACrCC,MAARW,uBAAyBT,GAAEE,GAAqBL;IACxCC,MAARY,uBAAyBV,EAAEE,GAAoBL;IACvCC,MAARa,uBAAyBX,GAAEE,GAAoBL;IACvCC,MAARc,uBAAyBZ,EAAEE,GAAmBL;IACtCC,MAARe,yBAAyBb,GAAEG,CAAUN;IAC7BC,MAARgB,yBAAyBd,EAAEI,CAAUP;IAC7BC,MAARiB,yBAAyBf,GAAEK,CAAUR;IAC7BC,MAARkB,yBAAyBhB,EAAEM,CAAUT;AAC7CoB"}
\ No newline at end of file
diff --git a/testcases/map/testcases/sv/72_cond_type.sv.map b/testcases/map/testcases/sv/72_cond_type.sv.map
index b4d6e6955..9be072725 100644
--- a/testcases/map/testcases/sv/72_cond_type.sv.map
+++ b/testcases/map/testcases/sv/72_cond_type.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"72_cond_type.sv.map","sources":["../../../veryl/72_cond_type.veryl"],"names":["","module","Module72","(","input","logic","i_clk",",","i_rst_n",")",";","x","=","1","a","b","c","d","e","f","g","h","i","always_comb","begin","case",") inside","0",":","endcase","end","if","==","always_ff","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,SAASC;IACLC,MAAMC,MAAbC,OAAkBC;IACXH,MAAMC,MAAbG,OAAkBR;AACtBS,CAAEC;IACSL,MAAHM;kBAASC,EAAEC,CAACH;IACTL,MAAHS,CAAQJ;IACLL,MAAHU,CAAQL;IACLL,MAAHW,CAAQN;IACLL,MAAHY,CAAQP;IACLL,MAAHa,CAAQR;IACLL,MAAHc,CAAQT;IACLL,MAAHe,CAAQV;IACLL,MAAHgB,CAAQX;IACLL,MAAHiB,CAAQZ;;IAEZa,YAAYC;;QAERC,MAAKd,CAAEe;YACHC,CAACC,EAAEd,EAAEF,EAAEC,CAACH;mBACPkB,EAAEd,EAAEF,EAAEC,CAACH;QACZmB;;QAEAJ,MAAKd,CAAEe;YACHC,CAACC,EAAEb,EAAEH,EAAEC,CAACH;mBACPkB,EAAEb,EAAEH,EAAEC,CAACH;QACZmB;;QAEAJ,MAAKd,CAAEe;YACHC,CAACC,EAAEZ,EAAEJ,EAAEC,CAACH;mBACPkB,EAAEZ,EAAEJ,EAAEC,CAACH;QACZmB;IACJC;;IAEAP,YAAYC;;QAERO,IAAGpB,EAAEqB,GAAGL,GAAEH;YACNP,EAAEL,EAAEC,CAACH;QACToB,SAAiBN;YACbP,EAAEL,EAAEC,CAACH;QACToB;;QAEAC,IAAGpB,EAAEqB,GAAGL,GAAEH;YACNN,EAAEN,EAAEC,CAACH;QACToB,SAAiBN;YACbN,EAAEN,EAAEC,CAACH;QACToB;;QAEAC,IAAGpB,EAAEqB,GAAGL,GAAEH;YACNL,EAAEP,EAAEC,CAACH;QACToB,SAAiBN;YACbL,EAAEP,EAAEC,CAACH;QACToB;IACJA;;IAEAG,6CAAUT;;QAENO,cAASP;YACLJ,GAAER,EAAEC,CAACH;QACToB,SAAiBN;YACbJ,GAAER,EAAEC,CAACH;QACToB;IACJA;IACAG,6CAAUT;;QAENO,cAASP;YACLH,GAAET,EAAEC,CAACH;QACToB,SAAiBN;YACbH,GAAET,EAAEC,CAACH;QACToB;IACJA;IACAG,6CAAUT;;QAENO,cAASP;YACLF,GAAEV,EAAEC,CAACH;QACToB,SAAiBN;YACbF,GAAEV,EAAEC,CAACH;QACToB;IACJA;AACJI"}
\ No newline at end of file
+{"version":3,"file":"72_cond_type.sv.map","sources":["../../../veryl/72_cond_type.veryl"],"names":["","module","Module72","(","input","logic","i_clk",",","i_rst_n",")",";","x","=","1","a","b","c","d","e","f","g","h","i","always_comb","begin","case",") inside","0",":","endcase","end","if","==","always_ff","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,SAASC;IACLC,MAAMC,MAAbC,OAAkBC;IACXH,MAAMC,MAAbG,OAAkBR;AACtBS,CAAEC;IACSL,MAAHM,iBAASC,EAAEC,CAACH;IACTL,MAAHS,CAAQJ;IACLL,MAAHU,CAAQL;IACLL,MAAHW,CAAQN;IACLL,MAAHY,CAAQP;IACLL,MAAHa,CAAQR;IACLL,MAAHc,CAAQT;IACLL,MAAHe,CAAQV;IACLL,MAAHgB,CAAQX;IACLL,MAAHiB,CAAQZ;;IAEZa,YAAYC;;QAERC,MAAKd,CAAEe;YACHC,CAACC,EAAEd,EAAEF,EAAEC,CAACH;mBACPkB,EAAEd,EAAEF,EAAEC,CAACH;QACZmB;;QAEAJ,MAAKd,CAAEe;YACHC,CAACC,EAAEb,EAAEH,EAAEC,CAACH;mBACPkB,EAAEb,EAAEH,EAAEC,CAACH;QACZmB;;QAEAJ,MAAKd,CAAEe;YACHC,CAACC,EAAEZ,EAAEJ,EAAEC,CAACH;mBACPkB,EAAEZ,EAAEJ,EAAEC,CAACH;QACZmB;IACJC;;IAEAP,YAAYC;;QAERO,IAAGpB,EAAEqB,GAAGL,GAAEH;YACNP,EAAEL,EAAEC,CAACH;QACToB,SAAiBN;YACbP,EAAEL,EAAEC,CAACH;QACToB;;QAEAC,IAAGpB,EAAEqB,GAAGL,GAAEH;YACNN,EAAEN,EAAEC,CAACH;QACToB,SAAiBN;YACbN,EAAEN,EAAEC,CAACH;QACToB;;QAEAC,IAAGpB,EAAEqB,GAAGL,GAAEH;YACNL,EAAEP,EAAEC,CAACH;QACToB,SAAiBN;YACbL,EAAEP,EAAEC,CAACH;QACToB;IACJA;;IAEAG,6CAAUT;;QAENO,cAASP;YACLJ,GAAER,EAAEC,CAACH;QACToB,SAAiBN;YACbJ,GAAER,EAAEC,CAACH;QACToB;IACJA;IACAG,6CAAUT;;QAENO,cAASP;YACLH,GAAET,EAAEC,CAACH;QACToB,SAAiBN;YACbH,GAAET,EAAEC,CAACH;QACToB;IACJA;IACAG,6CAAUT;;QAENO,cAASP;YACLF,GAAEV,EAAEC,CAACH;QACToB,SAAiBN;YACbF,GAAEV,EAAEC,CAACH;QACToB;IACJA;AACJI"}
\ No newline at end of file
diff --git a/testcases/sv/02_builtin_type.sv b/testcases/sv/02_builtin_type.sv
index d4ddd1089..d5e2d9b24 100644
--- a/testcases/sv/02_builtin_type.sv
+++ b/testcases/sv/02_builtin_type.sv
@@ -1,50 +1,32 @@
 module veryl_testcase_Module02;
     // unsigned integer
-    int unsigned     _a ;
-    always_comb _a = 1;
-    longint unsigned _aa;
-    always_comb _aa = 1;
+    int unsigned     _a ; always_comb _a = 1;
+    longint unsigned _aa; always_comb _aa = 1;
 
     // signed integer
-    int signed     _b ;
-    always_comb _b = 1;
-    longint signed _bb;
-    always_comb _bb = 1;
+    int signed     _b ; always_comb _b = 1;
+    longint signed _bb; always_comb _bb = 1;
 
     // floating point
-    shortreal _c ;
-    always_comb _c = 1;
-    real      _cc;
-    always_comb _cc = 1;
+    shortreal _c ; always_comb _c = 1;
+    real      _cc; always_comb _cc = 1;
 
     // 4 state (01xz) type
-    logic                  _d  ;
-    always_comb _d = 1;
-    logic [10-1:0]         _dd ;
-    always_comb _dd = 1;
-    logic [10-1:0][10-1:0] _ddd;
-    always_comb _ddd = 1;
+    logic                  _d  ; always_comb _d = 1;
+    logic [10-1:0]         _dd ; always_comb _dd = 1;
+    logic [10-1:0][10-1:0] _ddd; always_comb _ddd = 1;
 
     // 2 state (01) type
-    bit                  _e  ;
-    always_comb _e = 1;
-    bit [10-1:0]         _ee ;
-    always_comb _ee = 1;
-    bit [10-1:0][10-1:0] _eee;
-    always_comb _eee = 1;
+    bit                  _e  ; always_comb _e = 1;
+    bit [10-1:0]         _ee ; always_comb _ee = 1;
+    bit [10-1:0][10-1:0] _eee; always_comb _eee = 1;
 
     // array
-    int unsigned     _f      [0:2-1];
-    always_comb _f = '{1, 1};
-    longint unsigned _ff     [0:2-1];
-    always_comb _ff = '{1, 1};
-    int signed       _fff    [0:2-1];
-    always_comb _fff = '{1, 1};
-    longint signed   _ffff   [0:2-1];
-    always_comb _ffff = '{1, 1};
-    shortreal        _fffff  [0:2-1];
-    always_comb _fffff = '{1, 1};
-    real             _ffffff [0:2-1];
-    always_comb _ffffff = '{1, 1};
+    int unsigned     _f      [0:2-1]; always_comb _f = '{1, 1};
+    longint unsigned _ff     [0:2-1]; always_comb _ff = '{1, 1};
+    int signed       _fff    [0:2-1]; always_comb _fff = '{1, 1};
+    longint signed   _ffff   [0:2-1]; always_comb _ffff = '{1, 1};
+    shortreal        _fffff  [0:2-1]; always_comb _fffff = '{1, 1};
+    real             _ffffff [0:2-1]; always_comb _ffffff = '{1, 1};
 endmodule
 //# sourceMappingURL=../map/testcases/sv/02_builtin_type.sv.map
diff --git a/testcases/sv/03_operator.sv b/testcases/sv/03_operator.sv
index 491c17b86..9cd236fbd 100644
--- a/testcases/sv/03_operator.sv
+++ b/testcases/sv/03_operator.sv
@@ -1,94 +1,56 @@
 module veryl_testcase_Module03;
     // unary arithmetic
-    logic _a ;
-    always_comb _a = +1;
-    logic _aa;
-    always_comb _aa = -1;
+    logic _a ; always_comb _a = +1;
+    logic _aa; always_comb _aa = -1;
 
     // unary logical
-    logic _b ;
-    always_comb _b = !1;
-    logic _bb;
-    always_comb _bb = ~1;
+    logic _b ; always_comb _b = !1;
+    logic _bb; always_comb _bb = ~1;
 
     // unary reduce
-    logic _c      ;
-    always_comb _c = &1;
-    logic _cc     ;
-    always_comb _cc = |1;
-    logic _ccc    ;
-    always_comb _ccc = ^1;
-    logic _cccc   ;
-    always_comb _cccc = ~&1;
-    logic _ccccc  ;
-    always_comb _ccccc = ~|1;
-    logic _cccccc ;
-    always_comb _cccccc = ~^1;
-    logic _ccccccc;
-    always_comb _ccccccc = ^~1;
+    logic _c      ; always_comb _c = &1;
+    logic _cc     ; always_comb _cc = |1;
+    logic _ccc    ; always_comb _ccc = ^1;
+    logic _cccc   ; always_comb _cccc = ~&1;
+    logic _ccccc  ; always_comb _ccccc = ~|1;
+    logic _cccccc ; always_comb _cccccc = ~^1;
+    logic _ccccccc; always_comb _ccccccc = ^~1;
 
     // binary arithmetic
-    logic _d     ;
-    always_comb _d = 1 ** 1;
-    logic _dd    ;
-    always_comb _dd = 1 * 1;
-    logic _ddd   ;
-    always_comb _ddd = 1 / 1;
-    logic _dddd  ;
-    always_comb _dddd = 1 % 1;
-    logic _ddddd ;
-    always_comb _ddddd = 1 + 1;
-    logic _dddddd;
-    always_comb _dddddd = 1 - 1;
+    logic _d     ; always_comb _d = 1 ** 1;
+    logic _dd    ; always_comb _dd = 1 * 1;
+    logic _ddd   ; always_comb _ddd = 1 / 1;
+    logic _dddd  ; always_comb _dddd = 1 % 1;
+    logic _ddddd ; always_comb _ddddd = 1 + 1;
+    logic _dddddd; always_comb _dddddd = 1 - 1;
 
     // binary shift
-    logic _e   ;
-    always_comb _e = 1 << 1;
-    logic _ee  ;
-    always_comb _ee = 1 >> 1;
-    logic _eee ;
-    always_comb _eee = 1 <<< 1;
-    logic _eeee;
-    always_comb _eeee = 1 >>> 1;
+    logic _e   ; always_comb _e = 1 << 1;
+    logic _ee  ; always_comb _ee = 1 >> 1;
+    logic _eee ; always_comb _eee = 1 <<< 1;
+    logic _eeee; always_comb _eeee = 1 >>> 1;
 
     // binary compare
-    logic _f         ;
-    always_comb _f = 1 < 1;
-    logic _ff        ;
-    always_comb _ff = 1 <= 1;
-    logic _fff       ;
-    always_comb _fff = 1 > 1;
-    logic _ffff      ;
-    always_comb _ffff = 1 >= 1;
-    logic _fffff     ;
-    always_comb _fffff = 1 == 1;
-    logic _ffffff    ;
-    always_comb _ffffff = 1 != 1;
-    logic _fffffff   ;
-    always_comb _fffffff = 1 === 1;
-    logic _ffffffff  ;
-    always_comb _ffffffff = 1 !== 1;
-    logic _fffffffff ;
-    always_comb _fffffffff = 1 ==? 1;
-    logic _ffffffffff;
-    always_comb _ffffffffff = 1 !=? 1;
+    logic _f         ; always_comb _f = 1 < 1;
+    logic _ff        ; always_comb _ff = 1 <= 1;
+    logic _fff       ; always_comb _fff = 1 > 1;
+    logic _ffff      ; always_comb _ffff = 1 >= 1;
+    logic _fffff     ; always_comb _fffff = 1 == 1;
+    logic _ffffff    ; always_comb _ffffff = 1 != 1;
+    logic _fffffff   ; always_comb _fffffff = 1 === 1;
+    logic _ffffffff  ; always_comb _ffffffff = 1 !== 1;
+    logic _fffffffff ; always_comb _fffffffff = 1 ==? 1;
+    logic _ffffffffff; always_comb _ffffffffff = 1 !=? 1;
 
     // binary bitwise
-    logic _g    ;
-    always_comb _g = 1 & 1;
-    logic _gg   ;
-    always_comb _gg = 1 ^ 1;
-    logic _ggg  ;
-    always_comb _ggg = 1 ~^ 1;
-    logic _gggg ;
-    always_comb _gggg = 1 ^~ 1;
-    logic _ggggg;
-    always_comb _ggggg = 1 | 1;
+    logic _g    ; always_comb _g = 1 & 1;
+    logic _gg   ; always_comb _gg = 1 ^ 1;
+    logic _ggg  ; always_comb _ggg = 1 ~^ 1;
+    logic _gggg ; always_comb _gggg = 1 ^~ 1;
+    logic _ggggg; always_comb _ggggg = 1 | 1;
 
     // binary logical
-    logic _h ;
-    always_comb _h = 1 && 1;
-    logic _hh;
-    always_comb _hh = 1 || 1;
+    logic _h ; always_comb _h = 1 && 1;
+    logic _hh; always_comb _hh = 1 || 1;
 endmodule
 //# sourceMappingURL=../map/testcases/sv/03_operator.sv.map
diff --git a/testcases/sv/04_module.sv b/testcases/sv/04_module.sv
index ef67b9102..786195084 100644
--- a/testcases/sv/04_module.sv
+++ b/testcases/sv/04_module.sv
@@ -17,12 +17,9 @@ module veryl_testcase_Module04 #(
     localparam longint unsigned cc = 1;
 
     // variable declaration
-    logic                  _d  ;
-    always_comb _d = 1;
-    logic [10-1:0]         _dd ;
-    always_comb _dd = 1;
-    bit   [10-1:0][10-1:0] _ddd;
-    always_comb _ddd = 1;
+    logic                  _d  ; always_comb _d = 1;
+    logic [10-1:0]         _dd ; always_comb _dd = 1;
+    bit   [10-1:0][10-1:0] _ddd; always_comb _ddd = 1;
 
     always_comb bb  = 0;
     assign bbb = 0;
diff --git a/testcases/sv/06_function.sv b/testcases/sv/06_function.sv
index 580265037..f436232f8 100644
--- a/testcases/sv/06_function.sv
+++ b/testcases/sv/06_function.sv
@@ -22,8 +22,7 @@ module veryl_testcase_Module06;
         c = a / 1;
     endfunction
 
-    logic [ParamX-1:0] a;
-    always_comb a = 1;
+    logic [ParamX-1:0] a; always_comb a = 1;
     logic [ParamX-1:0] b;
     logic [ParamX-1:0] c;
     logic [ParamX-1:0] d;
diff --git a/testcases/sv/07_statement.sv b/testcases/sv/07_statement.sv
index d190b9660..5f536c7ce 100644
--- a/testcases/sv/07_statement.sv
+++ b/testcases/sv/07_statement.sv
@@ -1,8 +1,7 @@
 module veryl_testcase_Module07;
     logic a  ;
     logic aa ;
-    logic clk;
-    always_comb clk = 1;
+    logic clk; always_comb clk = 1;
 
     always_comb begin
         // assignment statement
diff --git a/testcases/sv/08_generate_declaration.sv b/testcases/sv/08_generate_declaration.sv
index 65d7aef89..f4a12aa2f 100644
--- a/testcases/sv/08_generate_declaration.sv
+++ b/testcases/sv/08_generate_declaration.sv
@@ -1,8 +1,7 @@
 module veryl_testcase_Module08;
     localparam int unsigned a     = 1;
     localparam int unsigned b     = 1;
-    logic        i_clk;
-    always_comb i_clk = 1;
+    logic        i_clk; always_comb i_clk = 1;
 
     // if declaration
     if (a == 1) begin :label
diff --git a/testcases/sv/11_let.sv b/testcases/sv/11_let.sv
index c0e663070..abd9d26bb 100644
--- a/testcases/sv/11_let.sv
+++ b/testcases/sv/11_let.sv
@@ -2,12 +2,10 @@ module veryl_testcase_Module11;
     // variable declaration
     logic                  b   ;
     logic [10-1:0]         bb  ;
-    bit   [10-1:0][10-1:0] _bbb;
-    always_comb _bbb = 1;
+    bit   [10-1:0][10-1:0] _bbb; always_comb _bbb = 1;
 
     // variable declaration with assignment
-    logic [10-1:0] _c;
-    always_comb _c = 1;
+    logic [10-1:0] _c; always_comb _c = 1;
 
     // assign declaration
     always_comb b  = 1;
diff --git a/testcases/sv/12_always.sv b/testcases/sv/12_always.sv
index 98b408c9d..8a694095d 100644
--- a/testcases/sv/12_always.sv
+++ b/testcases/sv/12_always.sv
@@ -39,10 +39,8 @@ module veryl_testcase_Module12_2 (
 );
     logic          a ;
     logic          aa;
-    logic          b ;
-    always_comb b = 1;
-    logic [10-1:0] c ;
-    always_comb c = 1;
+    logic          b ; always_comb b = 1;
+    logic [10-1:0] c ; always_comb c = 1;
 
     // always_ff declaration with default polarity
     always_ff @ (posedge i_clk, negedge i_rst_n) begin
diff --git a/testcases/sv/13_range_operator.sv b/testcases/sv/13_range_operator.sv
index 72e955568..e504e2e7e 100644
--- a/testcases/sv/13_range_operator.sv
+++ b/testcases/sv/13_range_operator.sv
@@ -4,8 +4,7 @@ module veryl_testcase_Module13;
     logic          c;
     logic          d;
     logic          e;
-    logic [10-1:0] X;
-    always_comb X = 1;
+    logic [10-1:0] X; always_comb X = 1;
 
     // bit select
     always_comb a = X[0];
diff --git a/testcases/sv/14_inst.sv b/testcases/sv/14_inst.sv
index 8c2c0d720..b6af40a53 100644
--- a/testcases/sv/14_inst.sv
+++ b/testcases/sv/14_inst.sv
@@ -1,12 +1,9 @@
 module veryl_testcase_Module14;
     localparam int unsigned X = 1;
 
-    logic a  ;
-    always_comb a = 1;
-    logic aa ;
-    always_comb aa = 1;
-    logic bbb;
-    always_comb bbb = 1;
+    logic a  ; always_comb a = 1;
+    logic aa ; always_comb aa = 1;
+    logic bbb; always_comb bbb = 1;
 
     // module instantiation
     veryl_testcase_Module14B x ();
diff --git a/testcases/sv/15_named_block.sv b/testcases/sv/15_named_block.sv
index c05c15cd3..c25b39673 100644
--- a/testcases/sv/15_named_block.sv
+++ b/testcases/sv/15_named_block.sv
@@ -1,21 +1,17 @@
 module veryl_testcase_Module15;
-    logic _a;
-    always_comb _a = 1;
+    logic _a; always_comb _a = 1;
 
     if (1) begin :label
-        logic _a;
-        always_comb _a = 1;
+        logic _a; always_comb _a = 1;
     end
 
     if (1) begin :label1
-        logic _a;
-        always_comb _a = 1;
+        logic _a; always_comb _a = 1;
     end
 
     for (genvar i = 0; i < 10; i++) begin :label2
         if (1) begin :label
-            logic _a;
-            always_comb _a = 1;
+            logic _a; always_comb _a = 1;
         end
     end
 endmodule
diff --git a/testcases/sv/16_case_switch.sv b/testcases/sv/16_case_switch.sv
index 08ec4906c..0ae0d6b30 100644
--- a/testcases/sv/16_case_switch.sv
+++ b/testcases/sv/16_case_switch.sv
@@ -3,10 +3,8 @@ module veryl_testcase_Module16;
 
     logic         a;
     logic         b;
-    logic         x;
-    always_comb x = 1;
-    logic [3-1:0] z;
-    always_comb z = 1;
+    logic         x; always_comb x = 1;
+    logic [3-1:0] z; always_comb z = 1;
 
     always_comb begin
         case (x) inside
diff --git a/testcases/sv/18_concatenation.sv b/testcases/sv/18_concatenation.sv
index 6a668b2d8..1a80ae48e 100644
--- a/testcases/sv/18_concatenation.sv
+++ b/testcases/sv/18_concatenation.sv
@@ -1,15 +1,13 @@
 module veryl_testcase_Module18;
     logic [20-1:0] a;
     logic          b;
-    logic          c;
-    always_comb c = 1;
+    logic          c; always_comb c = 1;
 
     always_comb a = {a[10:0], c};
     always_comb b = {{10{a[10:0]}}, {4{c}}};
 
     // multi-line concatenation
-    logic _d;
-    always_comb _d = {
+    logic _d; always_comb _d = {
         {8{a}}, {8{b}}, {8{c}},
         {8{a}}, {8{b}}, {8{c}},
         {8{a}}, {8{b}}, {8{c}},
diff --git a/testcases/sv/20_if_case_switch_expression.sv b/testcases/sv/20_if_case_switch_expression.sv
index e8a9e1220..f4934948a 100644
--- a/testcases/sv/20_if_case_switch_expression.sv
+++ b/testcases/sv/20_if_case_switch_expression.sv
@@ -2,10 +2,8 @@ module veryl_testcase_Module20;
     logic a;
     logic b;
     logic c;
-    logic x;
-    always_comb x = 1;
-    logic y;
-    always_comb y = 1;
+    logic x; always_comb x = 1;
+    logic y; always_comb y = 1;
 
     always_comb a = ((x) ? (
         1
diff --git a/testcases/sv/21_cast.sv b/testcases/sv/21_cast.sv
index 4f5bb7357..7bd736895 100644
--- a/testcases/sv/21_cast.sv
+++ b/testcases/sv/21_cast.sv
@@ -1,8 +1,7 @@
 module veryl_testcase_Module21;
     logic         a;
     logic [2-1:0] b;
-    logic         c;
-    always_comb c = 1;
+    logic         c; always_comb c = 1;
 
     typedef enum logic {
         EnumA_A,
diff --git a/testcases/sv/22_type_modifier.sv b/testcases/sv/22_type_modifier.sv
index c0fc8201a..61b9516ed 100644
--- a/testcases/sv/22_type_modifier.sv
+++ b/testcases/sv/22_type_modifier.sv
@@ -1,11 +1,7 @@
 module veryl_testcase_Module22;
-    logic     signed [10-1:0] _a;
-    always_comb _a = 1;
-    tri logic signed [10-1:0] _b;
-    assign _b = 1;
-    tri logic signed [10-1:0] _c;
-    assign _c = 1;
-    logic            [10-1:0] _d;
-    always_comb _d = 1;
+    logic     signed [10-1:0] _a; always_comb _a = 1;
+    tri logic signed [10-1:0] _b; assign _b = 1;
+    tri logic signed [10-1:0] _c; assign _c = 1;
+    logic            [10-1:0] _d; always_comb _d = 1;
 endmodule
 //# sourceMappingURL=../map/testcases/sv/22_type_modifier.sv.map
diff --git a/testcases/sv/23_ifdef.sv b/testcases/sv/23_ifdef.sv
index b50cebbdd..2780a8434 100644
--- a/testcases/sv/23_ifdef.sv
+++ b/testcases/sv/23_ifdef.sv
@@ -26,16 +26,13 @@ module veryl_testcase_Module23 #(
 );
     `ifdef DEFINE_A
     `ifdef DEFINE_B
-    logic [10-1:0] _a;
-    always_comb _a = 1;
+    logic [10-1:0] _a; always_comb _a = 1;
     `endif
     `endif
 
     `ifdef DEFINE_A
-    logic [10-1:0] _b;
-    always_comb _b = 1;
-    logic [10-1:0] _c;
-    always_comb _c = 1;
+    logic [10-1:0] _b; always_comb _b = 1;
+    logic [10-1:0] _c; always_comb _c = 1;
     `endif
 
     logic _d;
diff --git a/testcases/sv/24_sv_attribute.sv b/testcases/sv/24_sv_attribute.sv
index 5a6011355..59fafa81e 100644
--- a/testcases/sv/24_sv_attribute.sv
+++ b/testcases/sv/24_sv_attribute.sv
@@ -1,9 +1,7 @@
 module veryl_testcase_Module24;
     (* ram_style="block" *)
-    logic _a;
-    always_comb _a = 1;
+    logic _a; always_comb _a = 1;
     (* mark_debug="true" *)
-    logic _b;
-    always_comb _b = 1;
+    logic _b; always_comb _b = 1;
 endmodule
 //# sourceMappingURL=../map/testcases/sv/24_sv_attribute.sv.map
diff --git a/testcases/sv/26_array.sv b/testcases/sv/26_array.sv
index d4091c82a..50b28fc44 100644
--- a/testcases/sv/26_array.sv
+++ b/testcases/sv/26_array.sv
@@ -1,11 +1,7 @@
 module veryl_testcase_Module26;
-    logic [10-1:0]         _a               ;
-    always_comb _a = 1;
-    logic [10-1:0][10-1:0] _b               ;
-    always_comb _b = 1;
-    logic [10-1:0][10-1:0] _c [0:2-1]       ;
-    always_comb _c = '{1, 1};
-    logic [10-1:0][10-1:0] _d [0:2-1][0:2-1];
-    always_comb _d = '{'{1, 1}, '{1, 1}};
+    logic [10-1:0]         _a               ; always_comb _a = 1;
+    logic [10-1:0][10-1:0] _b               ; always_comb _b = 1;
+    logic [10-1:0][10-1:0] _c [0:2-1]       ; always_comb _c = '{1, 1};
+    logic [10-1:0][10-1:0] _d [0:2-1][0:2-1]; always_comb _d = '{'{1, 1}, '{1, 1}};
 endmodule
 //# sourceMappingURL=../map/testcases/sv/26_array.sv.map
diff --git a/testcases/sv/27_string.sv b/testcases/sv/27_string.sv
index 767edba0e..8ec0e2a91 100644
--- a/testcases/sv/27_string.sv
+++ b/testcases/sv/27_string.sv
@@ -1,7 +1,6 @@
 module veryl_testcase_Module27;
     localparam string a = "aaa";
 
-    string _b;
-    always_comb _b = "bbb";
+    string _b; always_comb _b = "bbb";
 endmodule
 //# sourceMappingURL=../map/testcases/sv/27_string.sv.map
diff --git a/testcases/sv/28_msblsb.sv b/testcases/sv/28_msblsb.sv
index ead24f118..4951105b7 100644
--- a/testcases/sv/28_msblsb.sv
+++ b/testcases/sv/28_msblsb.sv
@@ -4,17 +4,12 @@ module veryl_testcase_Module28A (
     localparam int unsigned WIDTH0 = 10;
     localparam int unsigned WIDTH1 = 20;
 
-    logic [10-1:0][20-1:0]              a;
-    always_comb a = 1;
-    logic [WIDTH0 + 10-1:0][WIDTH1-1:0] b;
-    always_comb b = 1;
+    logic [10-1:0][20-1:0]              a; always_comb a = 1;
+    logic [WIDTH0 + 10-1:0][WIDTH1-1:0] b; always_comb b = 1;
 
-    logic _x;
-    always_comb _x = a[($size(a, 1) - 1)][($size(a, 2) - 1):0 + 1];
-    logic _y;
-    always_comb _y = b[($size(b, 1) - 1) - 3][($size(b, 2) - 1) + 5:0];
-    logic _z;
-    always_comb _z = c[($size(c, 1) - 1)][($size(c, 2) - 1)];
+    logic _x; always_comb _x = a[($size(a, 1) - 1)][($size(a, 2) - 1):0 + 1];
+    logic _y; always_comb _y = b[($size(b, 1) - 1) - 3][($size(b, 2) - 1) + 5:0];
+    logic _z; always_comb _z = c[($size(c, 1) - 1)][($size(c, 2) - 1)];
 endmodule
 
 package veryl_testcase___Package28A__Package28B_B;
@@ -37,13 +32,9 @@ module veryl_testcase_ModuleB;
     veryl_testcase___Package28A__Package28B_B::StructA a  ;
     always_comb a.a = 0;
 
-    logic _w;
-    always_comb _w = a[($bits(a) - 1)];
-    logic _x;
-    always_comb _x = a.a[($size(a.a, 1) - 1)];
-    logic _y;
-    always_comb _y = veryl_testcase_Package28C::C[($size(veryl_testcase_Package28C::C, 1) - 1)];
-    logic _z;
-    always_comb _z = veryl_testcase_Package28C::C[0][($size(veryl_testcase_Package28C::C, 2) - 1)];
+    logic _w; always_comb _w = a[($bits(a) - 1)];
+    logic _x; always_comb _x = a.a[($size(a.a, 1) - 1)];
+    logic _y; always_comb _y = veryl_testcase_Package28C::C[($size(veryl_testcase_Package28C::C, 1) - 1)];
+    logic _z; always_comb _z = veryl_testcase_Package28C::C[0][($size(veryl_testcase_Package28C::C, 2) - 1)];
 endmodule
 //# sourceMappingURL=../map/testcases/sv/28_msblsb.sv.map
diff --git a/testcases/sv/29_allow.sv b/testcases/sv/29_allow.sv
index 526b88fc8..969d5079e 100644
--- a/testcases/sv/29_allow.sv
+++ b/testcases/sv/29_allow.sv
@@ -5,8 +5,7 @@ module veryl_testcase_Module29 (
     logic a;
     logic b;
 
-    logic c;
-    always_comb c = 1;
+    logic c; always_comb c = 1;
 
     always_ff @ (posedge clk, negedge rst_n) begin
         if (!rst_n) begin
diff --git a/testcases/sv/34_width_all_set.sv b/testcases/sv/34_width_all_set.sv
index fdb16ee80..2e0f80642 100644
--- a/testcases/sv/34_width_all_set.sv
+++ b/testcases/sv/34_width_all_set.sv
@@ -1,19 +1,11 @@
 module veryl_testcase_Module34;
-    logic [32-1:0] _a0;
-    always_comb _a0 = '0;
-    logic [32-1:0] _a1;
-    always_comb _a1 = '1;
-    logic [32-1:0] _a2;
-    always_comb _a2 = 'x;
-    logic [32-1:0] _a3;
-    always_comb _a3 = 'z;
-    logic [32-1:0] _a4;
-    always_comb _a4 = 10'b0000000000;
-    logic [32-1:0] _a5;
-    always_comb _a5 = 10'b1111111111;
-    logic [32-1:0] _a6;
-    always_comb _a6 = 10'bxxxxxxxxxx;
-    logic [32-1:0] _a7;
-    always_comb _a7 = 10'bzzzzzzzzzz;
+    logic [32-1:0] _a0; always_comb _a0 = '0;
+    logic [32-1:0] _a1; always_comb _a1 = '1;
+    logic [32-1:0] _a2; always_comb _a2 = 'x;
+    logic [32-1:0] _a3; always_comb _a3 = 'z;
+    logic [32-1:0] _a4; always_comb _a4 = 10'b0000000000;
+    logic [32-1:0] _a5; always_comb _a5 = 10'b1111111111;
+    logic [32-1:0] _a6; always_comb _a6 = 10'bxxxxxxxxxx;
+    logic [32-1:0] _a7; always_comb _a7 = 10'bzzzzzzzzzz;
 endmodule
 //# sourceMappingURL=../map/testcases/sv/34_width_all_set.sv.map
diff --git a/testcases/sv/35_unconnected_port.sv b/testcases/sv/35_unconnected_port.sv
index 78d131565..1ea904856 100644
--- a/testcases/sv/35_unconnected_port.sv
+++ b/testcases/sv/35_unconnected_port.sv
@@ -1,6 +1,5 @@
 module veryl_testcase_Module35;
-    logic aa;
-    always_comb aa = 1;
+    logic aa; always_comb aa = 1;
 
     veryl_testcase_Module35B xx (
         .aa   (aa),
diff --git a/testcases/sv/37_package_ref.sv b/testcases/sv/37_package_ref.sv
index 7a5f06e15..d843cfe66 100644
--- a/testcases/sv/37_package_ref.sv
+++ b/testcases/sv/37_package_ref.sv
@@ -11,11 +11,8 @@ package veryl_testcase_Package37;
 endpackage
 
 module veryl_testcase_Module37;
-    int unsigned _a;
-    always_comb _a = veryl_testcase_Package37::A;
-    int unsigned _b;
-    always_comb _b = veryl_testcase_Package37::B_C;
-    int unsigned _c;
-    always_comb _c = veryl_testcase_Package37::X();
+    int unsigned _a; always_comb _a = veryl_testcase_Package37::A;
+    int unsigned _b; always_comb _b = veryl_testcase_Package37::B_C;
+    int unsigned _c; always_comb _c = veryl_testcase_Package37::X();
 endmodule
 //# sourceMappingURL=../map/testcases/sv/37_package_ref.sv.map
diff --git a/testcases/sv/45_var_let_in_always.sv b/testcases/sv/45_var_let_in_always.sv
index b74c503b1..430890963 100644
--- a/testcases/sv/45_var_let_in_always.sv
+++ b/testcases/sv/45_var_let_in_always.sv
@@ -1,6 +1,5 @@
 module veryl_testcase_Module45;
-    logic          a;
-    always_comb a = 1;
+    logic          a; always_comb a = 1;
     logic [10-1:0] b;
     logic [10-1:0] c;
 
diff --git a/testcases/sv/46_var_let_anywhere.sv b/testcases/sv/46_var_let_anywhere.sv
index c4494f33a..0c17546bf 100644
--- a/testcases/sv/46_var_let_anywhere.sv
+++ b/testcases/sv/46_var_let_anywhere.sv
@@ -1,6 +1,5 @@
 module veryl_testcase_Module46;
-    logic          a;
-    always_comb a = 1;
+    logic          a; always_comb a = 1;
     logic [10-1:0] b;
     logic [10-1:0] c;
     logic [10-1:0] d;
diff --git a/testcases/sv/50_enum_over_typedef.sv b/testcases/sv/50_enum_over_typedef.sv
index d52a7b523..b30bbbb2f 100644
--- a/testcases/sv/50_enum_over_typedef.sv
+++ b/testcases/sv/50_enum_over_typedef.sv
@@ -8,9 +8,7 @@ endpackage
 module veryl_testcase_Module50;
     typedef veryl_testcase_Package50::EnumA EnumB;
 
-    veryl_testcase_Package50::EnumA _a;
-    always_comb _a = veryl_testcase_Package50::EnumA_memberA;
-    EnumB                           _b;
-    always_comb _b = veryl_testcase_Package50::EnumA_memberB;
+    veryl_testcase_Package50::EnumA _a; always_comb _a = veryl_testcase_Package50::EnumA_memberA;
+    EnumB                           _b; always_comb _b = veryl_testcase_Package50::EnumA_memberB;
 endmodule
 //# sourceMappingURL=../map/testcases/sv/50_enum_over_typedef.sv.map
diff --git a/testcases/sv/51_array_literal.sv b/testcases/sv/51_array_literal.sv
index 757f41d38..6a44ea622 100644
--- a/testcases/sv/51_array_literal.sv
+++ b/testcases/sv/51_array_literal.sv
@@ -1,9 +1,6 @@
 module veryl_testcase_Module51;
-    logic _a [0:2-1];
-    always_comb _a = '{1, 1};
-    logic _b [0:2-1];
-    always_comb _b = '{2{1}};
-    logic _c [0:2-1];
-    always_comb _c = '{default: 1};
+    logic _a [0:2-1]; always_comb _a = '{1, 1};
+    logic _b [0:2-1]; always_comb _b = '{2{1}};
+    logic _c [0:2-1]; always_comb _c = '{default: 1};
 endmodule
 //# sourceMappingURL=../map/testcases/sv/51_array_literal.sv.map
diff --git a/testcases/sv/54_generic_function.sv b/testcases/sv/54_generic_function.sv
index 56ae48802..9fb8433eb 100644
--- a/testcases/sv/54_generic_function.sv
+++ b/testcases/sv/54_generic_function.sv
@@ -10,14 +10,10 @@ module veryl_testcase_Module54;
         return a + 1;
     endfunction
 
-    logic [10-1:0] _a;
-    always_comb _a = __FuncA__10(1);
-    logic [10-1:0] _b;
-    always_comb _b = __FuncA__10(1);
-    logic [20-1:0] _c;
-    always_comb _c = __FuncA__20(1);
-    logic [20-1:0] _d;
-    always_comb _d = __FuncA__20(1);
+    logic [10-1:0] _a; always_comb _a = __FuncA__10(1);
+    logic [10-1:0] _b; always_comb _b = __FuncA__10(1);
+    logic [20-1:0] _c; always_comb _c = __FuncA__20(1);
+    logic [20-1:0] _d; always_comb _d = __FuncA__20(1);
 
     function automatic logic [10 + 2-1:0] __FuncB__10__2(
         input logic [10 + 2-1:0] a
@@ -30,14 +26,10 @@ module veryl_testcase_Module54;
         return a + 1;
     endfunction
 
-    logic [12-1:0] _e;
-    always_comb _e = __FuncB__10__2(1);
-    logic [12-1:0] _f;
-    always_comb _f = __FuncB__10__2(1);
-    logic [14-1:0] _g;
-    always_comb _g = __FuncB__10__4(1);
-    logic [14-1:0] _h;
-    always_comb _h = __FuncB__10__4(1);
+    logic [12-1:0] _e; always_comb _e = __FuncB__10__2(1);
+    logic [12-1:0] _f; always_comb _f = __FuncB__10__2(1);
+    logic [14-1:0] _g; always_comb _g = __FuncB__10__4(1);
+    logic [14-1:0] _h; always_comb _h = __FuncB__10__4(1);
 
     function automatic logic __FuncC__u() ;
         return u.a;
@@ -45,8 +37,7 @@ module veryl_testcase_Module54;
 
     veryl_testcase_Interface54 u ();
 
-    logic _i;
-    always_comb _i = __FuncC__u();
+    logic _i; always_comb _i = __FuncC__u();
 endmodule
 
 interface veryl_testcase_Interface54;
diff --git a/testcases/sv/55_generic_module.sv b/testcases/sv/55_generic_module.sv
index ca295bb80..2bfe40866 100644
--- a/testcases/sv/55_generic_module.sv
+++ b/testcases/sv/55_generic_module.sv
@@ -49,7 +49,6 @@ module veryl_testcase___Module55H__10;
         logic [10-1:0] value;
     } __StructH__10;
 
-    __StructH__10 _a;
-    always_comb _a = 0;
+    __StructH__10 _a; always_comb _a = 0;
 endmodule
 //# sourceMappingURL=../map/testcases/sv/55_generic_module.sv.map
diff --git a/testcases/sv/56_generic_interface.sv b/testcases/sv/56_generic_interface.sv
index ff6be25e3..8e9e957df 100644
--- a/testcases/sv/56_generic_interface.sv
+++ b/testcases/sv/56_generic_interface.sv
@@ -16,12 +16,9 @@ module veryl_testcase_Module56;
     veryl_testcase___Interface56B__Package56A_X u5 ();
     veryl_testcase___Module56Sub__1 u6 ();
 
-    logic _a;
-    always_comb _a = u0._a;
-    logic _b;
-    always_comb _b = u2._b;
-    logic _c;
-    always_comb _c = u5._b;
+    logic _a; always_comb _a = u0._a;
+    logic _b; always_comb _b = u2._b;
+    logic _c; always_comb _c = u5._b;
 endmodule
 
 module veryl_testcase___Module56Sub__1;
diff --git a/testcases/sv/62_raw_identifier.sv b/testcases/sv/62_raw_identifier.sv
index 026909970..d2bc34c36 100644
--- a/testcases/sv/62_raw_identifier.sv
+++ b/testcases/sv/62_raw_identifier.sv
@@ -1,8 +1,7 @@
 module veryl_testcase_Module62;
     logic clock;
     logic reset;
-    logic in   ;
-    always_comb in = 0;
+    logic in   ; always_comb in = 0;
     logic out  ;
     always_comb clock = 1;
     always_comb reset = 1;
diff --git a/testcases/sv/63_prefix_suffix.sv b/testcases/sv/63_prefix_suffix.sv
index c95206377..9305a6004 100644
--- a/testcases/sv/63_prefix_suffix.sv
+++ b/testcases/sv/63_prefix_suffix.sv
@@ -19,8 +19,7 @@ module veryl_testcase_Module63 (
         end
     end
 
-    logic _b;
-    always_comb _b = i_rst_n;
+    logic _b; always_comb _b = i_rst_n;
 endmodule
 
 module veryl_testcase_Module63A (
diff --git a/testcases/sv/64_cast_to_builtin.sv b/testcases/sv/64_cast_to_builtin.sv
index 1b85d2efe..6d8738080 100644
--- a/testcases/sv/64_cast_to_builtin.sv
+++ b/testcases/sv/64_cast_to_builtin.sv
@@ -1,18 +1,11 @@
 module veryl_testcase_Module64;
-    int unsigned a;
-    always_comb a = 1;
+    int unsigned a; always_comb a = 1;
 
-    int unsigned     _x0;
-    always_comb _x0 = unsigned'(int'(a));
-    longint unsigned _x1;
-    always_comb _x1 = unsigned'(longint'(a));
-    int signed       _x2;
-    always_comb _x2 = signed'(int'(a));
-    longint signed   _x3;
-    always_comb _x3 = signed'(longint'(a));
-    shortreal        _x4;
-    always_comb _x4 = shortreal'(a);
-    real             _x5;
-    always_comb _x5 = real'(a);
+    int unsigned     _x0; always_comb _x0 = unsigned'(int'(a));
+    longint unsigned _x1; always_comb _x1 = unsigned'(longint'(a));
+    int signed       _x2; always_comb _x2 = signed'(int'(a));
+    longint signed   _x3; always_comb _x3 = signed'(longint'(a));
+    shortreal        _x4; always_comb _x4 = shortreal'(a);
+    real             _x5; always_comb _x5 = real'(a);
 endmodule
 //# sourceMappingURL=../map/testcases/sv/64_cast_to_builtin.sv.map
diff --git a/testcases/sv/65_cast_to_clock_reset.sv b/testcases/sv/65_cast_to_clock_reset.sv
index 8ae495df5..e55266c47 100644
--- a/testcases/sv/65_cast_to_clock_reset.sv
+++ b/testcases/sv/65_cast_to_clock_reset.sv
@@ -1,36 +1,20 @@
 module veryl_testcase_Module65;
-    logic a  ;
-    always_comb a = 1;
-    logic b_n;
-    always_comb b_n = 1;
-    logic c  ;
-    always_comb c = 1;
-    logic d  ;
-    always_comb d = 1;
-    logic e  ;
-    always_comb e = 1;
-    logic f  ;
-    always_comb f = 1;
+    logic a  ; always_comb a = 1;
+    logic b_n; always_comb b_n = 1;
+    logic c  ; always_comb c = 1;
+    logic d  ; always_comb d = 1;
+    logic e  ; always_comb e = 1;
+    logic f  ; always_comb f = 1;
 
-    logic _x0  ;
-    always_comb _x0 = a;
-    logic _x1  ;
-    always_comb _x1 = a;
-    logic _x2  ;
-    always_comb _x2 = ~b_n;
-    logic _x3  ;
-    always_comb _x3 = b_n;
-    logic _x4  ;
-    always_comb _x4 = ~b_n;
-    logic _x5  ;
-    always_comb _x5 = b_n;
-    logic _x6_n;
-    always_comb _x6_n = ~c;
-    logic _x7_n;
-    always_comb _x7_n = d;
-    logic _x8_n;
-    always_comb _x8_n = ~e;
-    logic _x9_n;
-    always_comb _x9_n = f;
+    logic _x0  ; always_comb _x0 = a;
+    logic _x1  ; always_comb _x1 = a;
+    logic _x2  ; always_comb _x2 = ~b_n;
+    logic _x3  ; always_comb _x3 = b_n;
+    logic _x4  ; always_comb _x4 = ~b_n;
+    logic _x5  ; always_comb _x5 = b_n;
+    logic _x6_n; always_comb _x6_n = ~c;
+    logic _x7_n; always_comb _x7_n = d;
+    logic _x8_n; always_comb _x8_n = ~e;
+    logic _x9_n; always_comb _x9_n = f;
 endmodule
 //# sourceMappingURL=../map/testcases/sv/65_cast_to_clock_reset.sv.map
diff --git a/testcases/sv/72_cond_type.sv b/testcases/sv/72_cond_type.sv
index 79c580a82..eba48d4c1 100644
--- a/testcases/sv/72_cond_type.sv
+++ b/testcases/sv/72_cond_type.sv
@@ -2,8 +2,7 @@ module veryl_testcase_Module72 (
     input logic i_clk  ,
     input logic i_rst_n
 );
-    logic x;
-    always_comb x = 1;
+    logic x; always_comb x = 1;
     logic a;
     logic b;
     logic c;