Repository: veryl-lang/veryl (Rust)

Issue:
Not add prefix/suffix to hierarchical referenced reset signal
Prefix/suffix is not added to reset signal referenced via hierarchical reference in `always_comb` block.

Veryl
```systemverilog
interface FooIF {
  var rst: reset;
}

module Bar (
  i_rst: input reset
) {
  inst foo_if: FooIF;
  always_comb {
    foo_if.rst = i_rst;
  }
}
```

Generated SV
```systemverilog
interface veryl_testcase_FooIF;
    logic rst_n;
endinterface

module veryl_testcase_Bar (
    input var logic i_rst_n
);
    veryl_testcase_FooIF foo_if ();
    always_comb begin
        foo_if.rst = i_rst_n;
    end
endmodule
```


Discussion:

Patch:
diff --git a/crates/emitter/src/emitter.rs b/crates/emitter/src/emitter.rs
index 4b6a35c2b..d124b3f8f 100644
--- a/crates/emitter/src/emitter.rs
+++ b/crates/emitter/src/emitter.rs
@@ -71,8 +71,9 @@ pub struct Emitter {
     signed: bool,
     default_clock: Option<SymbolId>,
     default_reset: Option<SymbolId>,
-    reset_signal: Option<String>,
-    default_block: Option<Identifier>,
+    reset_signal: Option<VerylToken>,
+    reset_active_low: bool,
+    default_block: Option<VerylToken>,
     enum_width: usize,
     enum_type: Option<ScalarType>,
     emit_enum_implicit_valiant: bool,
@@ -121,6 +122,7 @@ impl Default for Emitter {
             default_clock: None,
             default_reset: None,
             reset_signal: None,
+            reset_active_low: false,
             default_block: None,
             enum_width: 0,
             enum_type: None,
@@ -543,7 +545,7 @@ impl Emitter {
         self.align_finish(align_kind::WIDTH);
     }
 
-    fn emit_identifier(&mut self, arg: &Identifier, namespace: Option<Namespace>) {
+    fn emit_identifier(&mut self, arg: &Identifier, symbol: Option<&Symbol>) {
         let align = !self.align_any()
             && !self.in_attribute
             && attribute_table::is_align(&arg.first(), AlignItem::Identifier);
@@ -551,7 +553,7 @@ impl Emitter {
             self.align_start(align_kind::IDENTIFIER);
         }
 
-        let text = emitting_identifier(arg, namespace).identifier_token;
+        let text = emitting_identifier_token(&arg.identifier_token, symbol);
         self.veryl_token(&text);
         self.push_resolved_identifier(&text.to_string());
 
@@ -815,48 +817,39 @@ impl Emitter {
 
     fn always_ff_implicit_reset_event(&mut self) {
         let symbol = symbol_table::get(self.default_reset.unwrap()).unwrap();
-        let (reset_kind, prefix, suffix) = match symbol.kind {
-            SymbolKind::Port(x) => (x.r#type.kind, x.prefix.clone(), x.suffix.clone()),
-            SymbolKind::Variable(x) => (x.r#type.kind, x.prefix.clone(), x.suffix.clone()),
-            _ => unreachable!(),
-        };
-        let reset_type = match reset_kind {
-            TypeKind::ResetAsyncHigh => ResetType::AsyncHigh,
-            TypeKind::ResetAsyncLow => ResetType::AsyncLow,
-            TypeKind::ResetSyncHigh => ResetType::SyncHigh,
-            TypeKind::ResetSyncLow => ResetType::SyncLow,
-            TypeKind::Reset => self.build_opt.reset_type,
-            _ => unreachable!(),
-        };
+        let reset_type = get_variable_type_kind(&symbol)
+            .map(|x| match x {
+                TypeKind::ResetAsyncHigh => ResetType::AsyncHigh,
+                TypeKind::ResetAsyncLow => ResetType::AsyncLow,
+                TypeKind::ResetSyncHigh => ResetType::SyncHigh,
+                TypeKind::ResetSyncLow => ResetType::SyncLow,
+                TypeKind::Reset => self.build_opt.reset_type,
+                _ => unreachable!(),
+            })
+            .unwrap();
 
-        let token = if prefix.is_some() || suffix.is_some() {
-            VerylToken::new(symbol.token).append(&prefix, &suffix).token
-        } else {
-            symbol.token
-        };
+        let token = emitting_identifier_token(&VerylToken::new(symbol.token), Some(&symbol));
 
-        let prefix_op = match reset_type {
+        match reset_type {
             ResetType::AsyncHigh => {
                 self.str(",");
                 self.space(1);
                 self.str("posedge");
                 self.space(1);
-                self.str(&token.to_string());
-                ""
+                self.duplicated_token(&token);
             }
             ResetType::AsyncLow => {
                 self.str(",");
                 self.space(1);
                 self.str("negedge");
                 self.space(1);
-                self.str(&token.to_string());
-                "!"
+                self.duplicated_token(&token);
             }
-            ResetType::SyncHigh => "",
-            ResetType::SyncLow => "!",
+            _ => {}
         };
 
-        self.reset_signal = Some(format!("{prefix_op}{token}"));
+        self.reset_signal = Some(token);
+        self.reset_active_low = matches!(reset_type, ResetType::AsyncLow | ResetType::SyncLow);
     }
 
     fn always_ff_reset_exist_in_sensitivity_list(&mut self, arg: &AlwaysFfReset) -> bool {
@@ -949,7 +942,10 @@ impl Emitter {
     }
 
     fn emit_generate_named_block(&mut self, arg: &GenerateNamedBlock, prefix: &str) {
-        self.default_block = Some(emitting_identifier(arg.identifier.as_ref(), None));
+        self.default_block = Some(emitting_identifier_token(
+            &arg.identifier.identifier_token,
+            None,
+        ));
         self.token_will_push(&arg.l_brace.l_brace_token.replace(&format!("{prefix}begin")));
         self.space(1);
         self.colon(&arg.colon);
@@ -1311,8 +1307,13 @@ impl Emitter {
     }
 
     fn emit_port_identifier(&mut self, identifier: &Identifier) {
-        let namespace = self.inst_module_namespace.clone();
-        self.emit_identifier(identifier, namespace);
+        let path: SymbolPathNamespace = if let Some(namespace) = &self.inst_module_namespace {
+            SymbolPathNamespace(identifier.into(), namespace.clone())
+        } else {
+            identifier.into()
+        };
+        let symbol = symbol_table::resolve(path).map(|x| x.found).ok();
+        self.emit_identifier(identifier, symbol.as_ref());
     }
 
     fn emit_inst_unconnected_port(
@@ -2171,7 +2172,8 @@ impl VerylWalker for Emitter {
 
     /// Semantic action for non-terminal 'Identifier'
     fn identifier(&mut self, arg: &Identifier) {
-        self.emit_identifier(arg, None);
+        let symbol = symbol_table::resolve(arg).map(|x| x.found).ok();
+        self.emit_identifier(arg, symbol.as_ref());
     }
 
     /// Semantic action for non-terminal 'Number'
@@ -2192,15 +2194,6 @@ impl VerylWalker for Emitter {
     /// Semantic action for non-terminal 'HierarchicalIdentifier'
     fn hierarchical_identifier(&mut self, arg: &HierarchicalIdentifier) {
         let list_len = &arg.hierarchical_identifier_list0.len();
-        let (prefix, suffix) = if let Ok(found) = symbol_table::resolve(arg) {
-            match &found.found.kind {
-                SymbolKind::Port(x) => (x.prefix.clone(), x.suffix.clone()),
-                SymbolKind::Variable(x) => (x.prefix.clone(), x.suffix.clone()),
-                _ => (None, None),
-            }
-        } else {
-            unreachable!()
-        };
         let array_size = if self.build_opt.flatten_array_interface
             && !arg.hierarchical_identifier_list.is_empty()
         {
@@ -2210,11 +2203,8 @@ impl VerylWalker for Emitter {
         };
 
         if *list_len == 0 {
-            self.identifier(&identifier_with_prefix_suffix(
-                &arg.identifier,
-                &prefix,
-                &suffix,
-            ));
+            let symbol = symbol_table::resolve(arg).map(|x| x.found).ok();
+            self.emit_identifier(&arg.identifier, symbol.as_ref());
         } else {
             self.identifier(&arg.identifier);
         }
@@ -2235,11 +2225,8 @@ impl VerylWalker for Emitter {
         for (i, x) in arg.hierarchical_identifier_list0.iter().enumerate() {
             self.dot(&x.dot);
             if (i + 1) == *list_len {
-                self.identifier(&identifier_with_prefix_suffix(
-                    &x.identifier,
-                    &prefix,
-                    &suffix,
-                ));
+                let symbol = symbol_table::resolve(arg).map(|x| x.found).ok();
+                self.emit_identifier(&x.identifier, symbol.as_ref());
             } else {
                 self.identifier(&x.identifier);
             }
@@ -2342,7 +2329,12 @@ impl VerylWalker for Emitter {
             if i > 0 || expanded_modport.is_none() {
                 self.dot(&x.dot);
                 self.push_resolved_identifier(".");
-                self.identifier(&x.identifier);
+                if (i + 1) < arg.expression_identifier_list0.len() {
+                    self.identifier(&x.identifier);
+                } else {
+                    let symbol = symbol_table::resolve(arg).map(|x| x.found).ok();
+                    self.emit_identifier(&x.identifier, symbol.as_ref());
+                }
             }
 
             for x in &x.expression_identifier_list0_list {
@@ -3159,7 +3151,7 @@ impl VerylWalker for Emitter {
         //self.str(";");
         //self.newline();
         self.align_start(align_kind::IDENTIFIER);
-        self.identifier(&emitting_identifier(arg.identifier.as_ref(), None));
+        self.identifier(&arg.identifier);
         self.align_finish(align_kind::IDENTIFIER);
         self.space(1);
         self.equ(&arg.equ);
@@ -3308,8 +3300,10 @@ impl VerylWalker for Emitter {
         );
         self.space(1);
         self.str("(");
-        let reset_signal = self.reset_signal.clone().unwrap();
-        self.str(&reset_signal);
+        if self.reset_active_low {
+            self.str("!");
+        }
+        self.duplicated_token(&self.reset_signal.clone().unwrap());
         self.str(")");
         self.space(1);
         self.statement_block(&arg.statement_block);
@@ -3569,7 +3563,7 @@ impl VerylWalker for Emitter {
             self.str("always_comb");
         }
         self.space(1);
-        self.identifier(&emitting_identifier(arg.identifier.as_ref(), None));
+        self.identifier(&arg.identifier);
         self.space(1);
         self.equ(&arg.equ);
         self.space(1);
@@ -3687,26 +3681,15 @@ impl VerylWalker for Emitter {
 
     /// Semantic action for non-terminal 'AlwaysFfClock'
     fn always_ff_clock(&mut self, arg: &AlwaysFfClock) {
-        if let Ok(found) = symbol_table::resolve(arg.hierarchical_identifier.as_ref()) {
-            let clock = match found.found.kind {
-                SymbolKind::Port(x) => x.r#type.kind,
-                SymbolKind::Variable(x) => x.r#type.kind,
-                SymbolKind::ModportVariableMember(x) => {
-                    let symbol = symbol_table::get(x.variable).unwrap();
-                    if let SymbolKind::Variable(x) = symbol.kind {
-                        x.r#type.kind
-                    } else {
-                        unreachable!();
-                    }
-                }
-                _ => unreachable!(),
-            };
-            let clock_type = match clock {
-                TypeKind::ClockPosedge => ClockType::PosEdge,
-                TypeKind::ClockNegedge => ClockType::NegEdge,
-                TypeKind::Clock => self.build_opt.clock_type,
-                _ => unreachable!(),
-            };
+        if let Ok(symbol) = symbol_table::resolve(arg.hierarchical_identifier.as_ref()) {
+            let clock_type = get_variable_type_kind(&symbol.found)
+                .map(|x| match x {
+                    TypeKind::ClockPosedge => ClockType::PosEdge,
+                    TypeKind::ClockNegedge => ClockType::NegEdge,
+                    TypeKind::Clock => self.build_opt.clock_type,
+                    _ => unreachable!(),
+                })
+                .unwrap();
 
             match clock_type {
                 ClockType::PosEdge => self.str("posedge"),
@@ -3722,51 +3705,41 @@ impl VerylWalker for Emitter {
     /// Semantic action for non-terminal 'AlwaysFfReset'
     fn always_ff_reset(&mut self, arg: &AlwaysFfReset) {
         if let Ok(found) = symbol_table::resolve(arg.hierarchical_identifier.as_ref()) {
-            let (reset_kind, prefix, suffix) = match found.found.kind {
-                SymbolKind::Port(x) => (x.r#type.kind, x.prefix.clone(), x.suffix.clone()),
-                SymbolKind::Variable(x) => (x.r#type.kind, x.prefix.clone(), x.suffix.clone()),
-                SymbolKind::ModportVariableMember(x) => {
-                    let symbol = symbol_table::get(x.variable).unwrap();
-                    if let SymbolKind::Variable(x) = symbol.kind {
-                        (x.r#type.kind, x.prefix.clone(), x.suffix.clone())
-                    } else {
-                        unreachable!();
-                    }
-                }
-                _ => unreachable!(),
-            };
-            let reset_type = match reset_kind {
-                TypeKind::ResetAsyncHigh => ResetType::AsyncHigh,
-                TypeKind::ResetAsyncLow => ResetType::AsyncLow,
-                TypeKind::ResetSyncHigh => ResetType::SyncHigh,
-                TypeKind::ResetSyncLow => ResetType::SyncLow,
-                TypeKind::Reset => self.build_opt.reset_type,
-                _ => unreachable!(),
-            };
-            let prefix_op = match reset_type {
+            let reset_type = get_variable_type_kind(&found.found)
+                .map(|x| match x {
+                    TypeKind::ResetAsyncHigh => ResetType::AsyncHigh,
+                    TypeKind::ResetAsyncLow => ResetType::AsyncLow,
+                    TypeKind::ResetSyncHigh => ResetType::SyncHigh,
+                    TypeKind::ResetSyncLow => ResetType::SyncLow,
+                    TypeKind::Reset => self.build_opt.reset_type,
+                    _ => unreachable!(),
+                })
+                .unwrap();
+
+            match reset_type {
                 ResetType::AsyncHigh => {
                     self.str("posedge");
                     self.space(1);
                     self.hierarchical_identifier(&arg.hierarchical_identifier);
-                    ""
                 }
                 ResetType::AsyncLow => {
                     self.str("negedge");
                     self.space(1);
                     self.hierarchical_identifier(&arg.hierarchical_identifier);
-                    "!"
                 }
-                ResetType::SyncHigh => "",
-                ResetType::SyncLow => "!",
+                _ => {}
             };
 
             let mut stringifier = Stringifier::new();
-            stringifier.hierarchical_identifier_with_prefix_suffix(
-                &arg.hierarchical_identifier,
-                &prefix,
-                &suffix,
-            );
-            self.reset_signal = Some(format!("{}{}", prefix_op, stringifier.as_str()));
+            stringifier.hierarchical_identifier(&arg.hierarchical_identifier);
+            let token = arg
+                .hierarchical_identifier
+                .identifier
+                .identifier_token
+                .replace(stringifier.as_str());
+
+            self.reset_signal = Some(emitting_identifier_token(&token, Some(&found.found)));
+            self.reset_active_low = matches!(reset_type, ResetType::AsyncLow | ResetType::SyncLow);
         } else {
             unreachable!()
         }
@@ -4157,11 +4130,12 @@ impl VerylWalker for Emitter {
             unreachable!();
         };
 
-        self.identifier(&identifier_with_prefix_suffix(
-            &arg.identifier,
+        let token = identifier_token_with_prefix_suffix(
+            &arg.identifier.identifier_token,
             &Some(format!("{prefix}_")),
             &None,
-        ));
+        );
+        self.veryl_token(&token);
         if let Some(ref x) = arg.enum_item_opt {
             self.space(1);
             self.equ(&x.equ);
@@ -5189,8 +5163,7 @@ impl VerylWalker for Emitter {
         } else {
             self.space(1);
             self.str(":");
-            let name = self.default_block.clone().unwrap();
-            self.identifier(&name);
+            self.veryl_token(&self.default_block.clone().unwrap());
         }
         self.token_will_push(&arg.l_brace.l_brace_token.replace(""));
         for (i, x) in arg.generate_optional_named_block_list.iter().enumerate() {
@@ -5730,39 +5703,50 @@ pub fn symbol_string(
     ret.replace("$std_", "__std_")
 }
 
-pub fn identifier_with_prefix_suffix(
-    identifier: &Identifier,
+fn get_variable_type_kind(symbol: &Symbol) -> Option<TypeKind> {
+    match &symbol.kind {
+        SymbolKind::Port(x) => Some(x.r#type.kind.clone()),
+        SymbolKind::Variable(x) => Some(x.r#type.kind.clone()),
+        SymbolKind::ModportVariableMember(x) => {
+            let symbol = symbol_table::get(x.variable).unwrap();
+            get_variable_type_kind(&symbol)
+        }
+        _ => None,
+    }
+}
+
+fn get_variable_prefix_suffix(symbol: &Symbol) -> (Option<String>, Option<String>) {
+    match &symbol.kind {
+        SymbolKind::Port(x) => (x.prefix.clone(), x.suffix.clone()),
+        SymbolKind::Variable(x) => (x.prefix.clone(), x.suffix.clone()),
+        SymbolKind::ModportVariableMember(x) => {
+            let symbol = symbol_table::get(x.variable).unwrap();
+            get_variable_prefix_suffix(&symbol)
+        }
+        _ => (None, None),
+    }
+}
+
+fn identifier_token_with_prefix_suffix(
+    token: &VerylToken,
     prefix: &Option<String>,
     suffix: &Option<String>,
-) -> Identifier {
-    let token = if prefix.is_some() || suffix.is_some() {
-        let token = &identifier.identifier_token.strip_prefix("r#");
+) -> VerylToken {
+    if prefix.is_some() || suffix.is_some() {
+        let token = token.strip_prefix("r#");
         token.append(prefix, suffix)
     } else {
-        identifier.identifier_token.strip_prefix("r#")
-    };
-    Identifier {
-        identifier_token: token,
+        token.strip_prefix("r#")
     }
 }
 
-pub fn emitting_identifier(arg: &Identifier, namespace: Option<Namespace>) -> Identifier {
-    let path_namespace = if let Some(x) = namespace {
-        SymbolPathNamespace(arg.into(), x)
-    } else {
-        arg.into()
-    };
-
-    let (prefix, suffix) = if let Ok(found) = symbol_table::resolve(path_namespace) {
-        match &found.found.kind {
-            SymbolKind::Port(x) => (x.prefix.clone(), x.suffix.clone()),
-            SymbolKind::Variable(x) => (x.prefix.clone(), x.suffix.clone()),
-            _ => (None, None),
-        }
+fn emitting_identifier_token(token: &VerylToken, symbol: Option<&Symbol>) -> VerylToken {
+    let (prefix, suffix) = if let Some(symbol) = symbol {
+        get_variable_prefix_suffix(symbol)
     } else {
         (None, None)
     };
-    identifier_with_prefix_suffix(arg, &prefix, &suffix)
+    identifier_token_with_prefix_suffix(token, &prefix, &suffix)
 }
 
 pub fn resolve_generic_path(


Test patch:
diff --git a/crates/emitter/src/tests.rs b/crates/emitter/src/tests.rs
index 225950279..1db4dcfc4 100644
--- a/crates/emitter/src/tests.rs
+++ b/crates/emitter/src/tests.rs
@@ -233,6 +233,56 @@ endmodule
     assert_eq!(ret, expect);
 }
 
+#[test]
+fn hierarchical_referenced_clock_reset_signals() {
+    let code = r#"interface FooIF {
+    var clk: clock;
+    var rst: reset;
+}
+module ModuleA (
+    i_clk: input clock,
+    i_rst: input reset,
+) {
+    inst foo_if: FooIF;
+    always_comb {
+        foo_if.clk = i_clk;
+        foo_if.rst = i_rst;
+    }
+}
+"#;
+
+    let expect = r#"interface prj_FooIF;
+    logic clk_p;
+    logic rst_x;
+endinterface
+module prj_ModuleA (
+    input var logic i_clk_p,
+    input var logic i_rst_x
+);
+    prj_FooIF foo_if ();
+    always_comb begin
+        foo_if.clk_p = i_clk_p;
+        foo_if.rst_x = i_rst_x;
+    end
+endmodule
+//# sourceMappingURL=test.sv.map
+"#;
+
+    let mut metadata: Metadata =
+        toml::from_str(&Metadata::create_default_toml("prj").unwrap()).unwrap();
+    metadata.build.clock_posedge_suffix = Some("_p".to_string());
+    metadata.build.reset_low_suffix = Some("_x".to_string());
+
+    let ret = if cfg!(windows) {
+        emit(&metadata, code).replace("\r\n", "\n")
+    } else {
+        emit(&metadata, code)
+    };
+
+    println!("ret\n{}exp\n{}", ret, expect);
+    assert_eq!(ret, expect);
+}
+
 #[test]
 fn omit_project_prefix() {
     let code = r#"module ModuleA {
diff --git a/testcases/map/10_various_line_comment.sv.map b/testcases/map/10_various_line_comment.sv.map
index 9f9ae4721..d2571cd43 100644
--- a/testcases/map/10_various_line_comment.sv.map
+++ b/testcases/map/10_various_line_comment.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"10_various_line_comment.sv.map","sources":["../veryl/10_various_line_comment.veryl"],"names":["","module","veryl_testcase_Module10","(","input","logic","i_clk",",","i_rst_n","i_up","i_down","output","[","8","]","o_count",")",";","count","2","up_down","always_comb","=","begin","<<","1","|","end","always_ff","if","0","else","==","2'b10","+","2'b01","-","endmodule"],"mappings":"AAAAA,AAAAC;CACCC;CACAC;;IAGIC;SACAC;KAHDC;IAIAC;IACOH,UAAMC,MAAbG,OAAkBD;IACXH,UAAMC,MAAbI,OAAkBF;;IAETH,WAAOC,cAAhBK,OAAwBH;IACfI,WAAON,MAAKO,CAACC,KAACC,EAAvBC,OAAwBf;AAC5BgB,CAAEC;;IAEIZ;KACFO;IACAC;QACAC;KAJII;IAKJD;IACaZ,MAAKO,CAACO,KAACL,EAAhBM,OAAiBH;;IAErBI,YAAON,QAAQO,EAAEJ,KAAKD;;IAEtBI;KACCE;QACGH,QAAQE;SACPnB,CAACM;SACDe;SACAC,CAACT;SACDU,EAAEhB,MAAMO;IACbU;;IAEAC;OACCzB,SAACG;IACFC;aACCC;IACDQ;KACCO;QACGM;oBACCN;YACGL,OAAMI,EAAEQ,CAACb;QACbU;SACCI;SACAF;UACAT;SACAY;SACAC,OAAMV;YACHL,OAAMI,EAAEJ;aACPgB,EAAET;YACHR;QACJU;SACCI;SACAF;UACAT,QAAQY,GAAGG,OAAMZ;YACdL;cACCI,EAAEJ,MAAMkB;aACRX,CAACR;QACNU;IACJA;AACJU"}
\ No newline at end of file
+{"version":3,"file":"10_various_line_comment.sv.map","sources":["../veryl/10_various_line_comment.veryl"],"names":["","module","veryl_testcase_Module10","(","input","logic","i_clk",",","i_rst_n","i_up","i_down","output","[","8","]","o_count",")",";","count","2","up_down","always_comb","=","begin","<<","1","|","end","always_ff","if","0","else","==","2'b10","+","2'b01","-","endmodule"],"mappings":"AAAAA,AAAAC;CACCC;CACAC;;IAGIC;SACAC;KAHDC;IAIAC;IACOH,UAAMC,MAAbG,OAAkBD;IACXH,UAAMC,MAAbI,OAAkBF;;IAETH,WAAOC,cAAhBK,OAAwBH;IACfI,WAAON,MAAKO,CAACC,KAACC,EAAvBC,OAAwBf;AAC5BgB,CAAEC;;IAEIZ;KACFO;IACAC;QACAC;KAJII;IAKJD;IACaZ,MAAKO,CAACO,KAACL,EAAhBM,OAAiBH;;IAErBI,YAAON,QAAQO,EAAEJ,KAAKD;;IAEtBI;KACCE;QACGH,QAAQE;SACPnB,CAACM;SACDe;SACAC,CAACT;SACDU,EAAEhB,MAAMO;IACbU;;IAEAC;OACCzB,SAACG;IACFC;aACCC;IACDQ;KACCO;QACGM;WAHHrB,SAIIe;YACGL,OAAMI,EAAEQ,CAACb;QACbU;SACCI;SACAF;UACAT;SACAY;SACAC,OAAMV;YACHL,OAAMI,EAAEJ;aACPgB,EAAET;YACHR;QACJU;SACCI;SACAF;UACAT,QAAQY,GAAGG,OAAMZ;YACdL;cACCI,EAAEJ,MAAMkB;aACRX,CAACR;QACNU;IACJA;AACJU"}
\ No newline at end of file
diff --git a/testcases/map/12_always.sv.map b/testcases/map/12_always.sv.map
index d5f10d716..2aeb9d698 100644
--- a/testcases/map/12_always.sv.map
+++ b/testcases/map/12_always.sv.map
@@ -1,1 +1,1 @@
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diff --git a/testcases/map/29_allow.sv.map b/testcases/map/29_allow.sv.map
index 12dd9a5fc..e249a3a76 100644
--- a/testcases/map/29_allow.sv.map
+++ b/testcases/map/29_allow.sv.map
@@ -1,1 +1,1 @@
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diff --git a/testcases/map/63_prefix_suffix.sv.map b/testcases/map/63_prefix_suffix.sv.map
index 2365044d4..047116f11 100644
--- a/testcases/map/63_prefix_suffix.sv.map
+++ b/testcases/map/63_prefix_suffix.sv.map
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diff --git a/testcases/map/72_cond_type.sv.map b/testcases/map/72_cond_type.sv.map
index 2de904e39..d5203f6fa 100644
--- a/testcases/map/72_cond_type.sv.map
+++ b/testcases/map/72_cond_type.sv.map
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+{"version":3,"file":"72_cond_type.sv.map","sources":["../veryl/72_cond_type.veryl"],"names":["","module","veryl_testcase_Module72","(","input","logic","i_clk",",","i_rst_n",")",";","x","=","1","a","b","c","d","e","f","g","h","i","always_comb","begin","case",") inside","0",":","endcase","end","if","==","always_ff","endmodule"],"mappings":"AAAAA,AAAAC,OAAOC,wBAASC;IACLC,UAAMC,MAAbC,OAAkBC;IACXH,UAAMC,MAAbG,OAAkBR;AACtBS,CAAEC;IACSL,MAAHM,eAAAA,EAASC,EAAEC,CAACH;IACTL,MAAHS,CAAQJ;IACLL,MAAHU,CAAQL;IACLL,MAAHW,CAAQN;IACLL,MAAHY,CAAQP;IACLL,MAAHa,CAAQR;IACLL,MAAHc,CAAQT;IACLL,MAAHe,CAAQV;IACLL,MAAHgB,CAAQX;IACLL,MAAHiB,CAAQZ;;IAEZa,YAAYC;;QAERC,MAAKd,CAAEe;YACHC,CAACC,EAAEd,EAAEF,EAAEC,CAACH;mBACPkB,EAAEd,EAAEF,EAAEC,CAACH;QACZmB;;QAEAJ,MAAKd,CAAEe;YACHC,CAACC,EAAEb,EAAEH,EAAEC,CAACH;mBACPkB,EAAEb,EAAEH,EAAEC,CAACH;QACZmB;;QAEAJ,MAAKd,CAAEe;YACHC,CAACC,EAAEZ,EAAEJ,EAAEC,CAACH;mBACPkB,EAAEZ,EAAEJ,EAAEC,CAACH;QACZmB;IACJC;;IAEAP,YAAYC;;QAERO,IAAGpB,EAAEqB,GAAGL,GAAEH;YACNP,EAAEL,EAAEC,CAACH;QACToB,SAAiBN;YACbP,EAAEL,EAAEC,CAACH;QACToB;;QAEAC,IAAGpB,EAAEqB,GAAGL,GAAEH;YACNN,EAAEN,EAAEC,CAACH;QACToB,SAAiBN;YACbN,EAAEN,EAAEC,CAACH;QACToB;;QAEAC,IAAGpB,EAAEqB,GAAGL,GAAEH;YACNL,EAAEP,EAAEC,CAACH;QACToB,SAAiBN;YACbL,EAAEP,EAAEC,CAACH;QACToB;IACJA;;IAEAG,oCApDAzB,SAoDUgB;;QAENO,KAtDJvB,SAsDagB;YACLJ,GAAER,EAAEC,CAACH;QACToB,SAAiBN;YACbJ,GAAER,EAAEC,CAACH;QACToB;IACJA;IACAG,oCA5DAzB,SA4DUgB;;QAENO,KA9DJvB,SA8DagB;YACLH,GAAET,EAAEC,CAACH;QACToB,SAAiBN;YACbH,GAAET,EAAEC,CAACH;QACToB;IACJA;IACAG,oCApEAzB,SAoEUgB;;QAENO,KAtEJvB,SAsEagB;YACLF,GAAEV,EAAEC,CAACH;QACToB,SAAiBN;YACbF,GAAEV,EAAEC,CAACH;QACToB;IACJA;AACJI"}
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diff --git a/testcases/map/77_default_clock_reset.sv.map b/testcases/map/77_default_clock_reset.sv.map
index 92ea1fee1..ee56a4ffa 100644
--- a/testcases/map/77_default_clock_reset.sv.map
+++ b/testcases/map/77_default_clock_reset.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"77_default_clock_reset.sv.map","sources":["../veryl/77_default_clock_reset.veryl"],"names":["","module","veryl_testcase_Module77","(","input","logic","i_clk_a",",","i_rst_a_n","i_clk_b","i_rst_b_n","i_d","output","o_d",")",";","always_ff","begin","if","=","0","end","else","endmodule"],"mappings":"AAAAA,AAAAC,OAAOC,wBAASC;IACHC,WAAUJ,AAAQK,MAA3BC,SAAgCC;IACvBH,WAAUJ,AAAQK,MAA3BG,SAAgCD;IACvBH,WAAUC,MAAnBI,SAAgCF;IACvBH,WAAUC,MAAnBK,SAAgCH;IACvBH,WAAUC,MAAnBM,SAAgCJ;IACvBK,WAAUP,MAAnBQ,SAAgCb;AACpCc,CAAEC;IACEC,iDAAUC;QACNC,gBAASD;YACLJ,KAAIM,EAAEC,CAACL;QACXM,IAAEC,KAAKL;YACHJ,KAAIM,EAAER,GAAGI;QACbM;IACJA;AACJE"}
\ No newline at end of file
+{"version":3,"file":"77_default_clock_reset.sv.map","sources":["../veryl/77_default_clock_reset.veryl"],"names":["","module","veryl_testcase_Module77","(","input","logic","i_clk_a",",","i_rst_a_n","i_clk_b","i_rst_b_n","i_d","output","o_d",")",";","always_ff","begin","if","=","0","end","else","endmodule"],"mappings":"AAAAA,AAAAC,OAAOC,wBAASC;IACHC,WAAUJ,AAAQK,MAA3BC,SAAgCC;IACvBH,WAAUJ,AAAQK,MAA3BG,SAAgCD;IACvBH,WAAUC,MAAnBI,SAAgCF;IACvBH,WAAUC,MAAnBK,SAAgCH;IACvBH,WAAUC,MAAnBM,SAAgCJ;IACvBK,WAAUP,MAAnBQ,SAAgCb;AACpCc,CAAEC;IACEC,sCANAR,WAMUS;QACNC,KAPJV,WAOaS;YACLJ,KAAIM,EAAEC,CAACL;QACXM,IAAEC,KAAKL;YACHJ,KAAIM,EAAER,GAAGI;QACbM;IACJA;AACJE"}
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diff --git a/testcases/map/78_interface_with_clock_reset.sv.map b/testcases/map/78_interface_with_clock_reset.sv.map
index 21ed38af3..fb775f161 100644
--- a/testcases/map/78_interface_with_clock_reset.sv.map
+++ b/testcases/map/78_interface_with_clock_reset.sv.map
@@ -1,1 +1,1 @@
-{"version":3,"file":"78_interface_with_clock_reset.sv.map","sources":["../veryl/78_interface_with_clock_reset.veryl"],"names":["","interface","veryl_testcase_Interface78",";","logic","clk","rst_n","modport","slave","(","input",",","rst",")","endinterface","module","veryl_testcase_Module78","veryl_testcase_Interface78.slave","intf","x","always_ff",".","begin","if","=","0","end","else","1","endmodule"],"mappings":"AAAAA,AAAAC,UAAUC,0BAAYC;IACTC,MAALC,KAAUF;IACLC,MAALE,KAAUH;;IAEdI,QAAQC,MAAMC;QACLC,MAALL,GAAUM;QACLD,MAALE,GAAUZ;IACda;AACJC;;AAEAC,OAAOC,wBAASP;IACEQ,iCAAdC,IAAgClB;AACpCa,CAAEV;IACSC,MAAHe,CAAQhB;;IAEZiB,YAAUX,SAACS,IAAIG,CAAChB,GAAGM,UAAEO,IAAIG,CAACT,GAAGC,EAAES;QAC3BC,iBAASD;YACLH,GAAEK,EAAEC,CAACtB;QACTuB,IAAEC,KAAKL;YACHH,GAAEK,EAAFL,KAAKS,EAACzB;QACVuB;IACJA;AACJG"}
\ No newline at end of file
+{"version":3,"file":"78_interface_with_clock_reset.sv.map","sources":["../veryl/78_interface_with_clock_reset.veryl"],"names":["","interface","veryl_testcase_Interface78",";","logic","clk","rst_n","modport","slave","(","input",",",")","endinterface","module","veryl_testcase_Module78","veryl_testcase_Interface78.slave","intf","x","always_ff",".","begin","if","intf.rst_n","=","0","end","else","1","endmodule"],"mappings":"AAAAA,AAAAC,UAAUC,0BAAYC;IACTC,MAALC,KAAUF;IACLC,MAALE,KAAUH;;IAEdI,QAAQC,MAAMC;QACLC,MAALL,KAAUM;QACLD,MAALJ,KAAUN;IACdY;AACJC;;AAEAC,OAAOC,wBAASN;IACEO,iCAAdC,IAAgCjB;AACpCY,CAAET;IACSC,MAAHc,CAAQf;;IAEZgB,YAAUV,SAACQ,IAAIG,CAACf,GAAGM,UAAEM,IAAIG,CAACd,KAAGM,EAAES;QAC3BC,KADiBC,YACRF;YACLH,GAAEM,EAAEC,CAACtB;QACTuB,IAAEC,KAAKN;YACHH,GAAEM,EAAFN,KAAKU,EAACzB;QACVuB;IACJA;AACJG"}
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diff --git a/testcases/sv/78_interface_with_clock_reset.sv b/testcases/sv/78_interface_with_clock_reset.sv
index 7082dd926..9945f6020 100644
--- a/testcases/sv/78_interface_with_clock_reset.sv
+++ b/testcases/sv/78_interface_with_clock_reset.sv
@@ -3,8 +3,8 @@ interface veryl_testcase_Interface78;
     logic rst_n;
 
     modport slave (
-        input clk,
-        input rst
+        input clk  ,
+        input rst_n
     );
 endinterface
 
@@ -13,7 +13,7 @@ module veryl_testcase_Module78 (
 );
     logic x;
 
-    always_ff @ (posedge intf.clk, negedge intf.rst) begin
+    always_ff @ (posedge intf.clk, negedge intf.rst_n) begin
         if (!intf.rst_n) begin
             x <= 0;
         end else begin