Repository: zephyrproject-rtos/zephyr (C)

Issue:
tests: tests/drivers/dma/loop_transfer: mimxrt595_evk/mimxrt595s/cm33: failed: Timeout
**Describe the bug**
below case are failed
drivers.dma.loop_transfer.dma_m2m_loop.tst_dma0_m2m_loop_repeated_start_stop

test is failed on v4.1.0-5871-gea2990702f67 on mimxrt595_evk/mimxrt595s/cm33
testcase path is tests/drivers/dma/loop_transfer

git bisect found this issue is introduced by

eeaf860dfabfc90ccba92db229cb46241139c5be is the first bad commit
```
commit eeaf860dfabfc90ccba92db229cb46241139c5be
Author: Vit Stanicek <vit.stanicek@nxp.com>
Date:   Tue Jun 18 12:28:24 2024 +0200

    dma_mcux_lpc: add host directions, DMA driver ctx, getter func

    Add support for HOST_TO_MEMORY, MEMORY_TO_HOST directions (aliases of
    MEMORY_TO_MEMORY). Implement dma_mcux_lpc_get_attribute function. Fix
    missing DMA driver context.

    Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>

 drivers/dma/dma_mcux_lpc.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
```

see logs for details

**To Reproduce**
1. 
```
scripts/twister -p mimxrt595_evk/mimxrt595s/cm33  -T tests/drivers/dma/loop_transfer
```
or
```
# west twister -p mimxrt595_evk/mimxrt595s/cm33 -T tests/drivers/dma/loop_transfer --sub-test tests/drivers/dma/loop_transfer
```
2. See error

```
Timeout
```

**Expected behavior**
test pass

**Impact**


**Logs and console output**

```
*** Booting Zephyr OS build v4.1.0-5871-gea2990702f67 ***
Running TESTSUITE dma_m2m_loop
===================================================================
START - test_tst_dma0_m2m_loop
DMA memory to memory transfer started
Preparing DMA Controller: dma-controller@104000
Starting the transfer on channel 0 and waiting for 1 second
Each RX buffer should contain the full TX buffer string.
RX data Loop 0
RX data Loop 1
RX data Loop 2
RX data Loop 3
Finished DMA: dma-controller@104000
 PASS - test_tst_dma0_m2m_loop in 0.281 seconds
===================================================================
START - test_tst_dma0_m2m_loop_repeated_start_stop
DMA memory to memory transfer started
Preparing DMA Controller
Starting the transfer on channel 1 and waiting for 1 second
E: ***** BUS FAULT *****
E:   Precise data bus error
E:   BFAR Address: 0x3ff5007
E: r0/a1:  0x3018bf80  r1/a2:  0x3018bf80  r2/a3:  0x30189d9f
E: r3/a4:  0x03ff5003 r12/ip:  0x3018c8e8 r14/lr:  0x1800796f
E:  xpsr:  0x81000000
E: Faulting instruction address (r15/pc): 0x1800a42e
E: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0
E: Current thread: 0x3018bf80 (!P050)
E: Halting system


```

**Environment (please complete the following information):**
 - OS: (e.g. Linux ): posix
 - Toolchain (e.g Zephyr SDK): zephyr
 - Commit SHA or Version used: v4.1.0-5871-gea2990702f67
     


Discussion: ![Image](https://github.com/user-attachments/assets/46ab91c9-148a-4180-b751-931c04d9fed1)

the thread address has no alignment

![Image](https://github.com/user-attachments/assets/7b8fb8d9-5145-4859-91af-cef2ea5f842c)



Fix (patch):
diff --git a/drivers/dma/dma_mcux_lpc.c b/drivers/dma/dma_mcux_lpc.c
index 2375c4d30c318..aec9147ffa482 100644
--- a/drivers/dma/dma_mcux_lpc.c
+++ b/drivers/dma/dma_mcux_lpc.c
@@ -33,6 +33,7 @@ struct dma_mcux_lpc_config {
 	uint32_t otrig_base_address;
 	uint32_t itrig_base_address;
 	uint8_t num_of_channels;
+	uint8_t num_of_allocated_channels;
 	uint8_t num_of_otrigs;
 	void (*irq_config_func)(const struct device *dev);
 };
@@ -482,6 +483,12 @@ static int dma_mcux_lpc_configure(const struct device *dev, uint32_t channel,
 
 	/* If needed, allocate a slot to store dma channel data */
 	if (dma_data->channel_index[channel] == -1) {
+		/* Not enough items in channel data array */
+		if (dma_data->num_channels_used >= dev_config->num_of_allocated_channels) {
+			LOG_ERR("No free DMA channels available");
+			return -ENOMEM;
+		}
+
 		dma_data->channel_index[channel] = dma_data->num_channels_used;
 		dma_data->num_channels_used++;
 		/* Get the slot number that has the dma channel data */
@@ -944,6 +951,7 @@ static DEVICE_API(dma, dma_mcux_lpc_api) = {
 static const struct dma_mcux_lpc_config dma_##n##_config = {		\
 	.base = (DMA_Type *)DT_INST_REG_ADDR(n),			\
 	.num_of_channels = DT_INST_PROP(n, dma_channels),		\
+	.num_of_allocated_channels = DMA_MCUX_LPC_NUM_USED_CHANNELS(n),	\
 	.num_of_otrigs = DT_INST_PROP_OR(n, nxp_dma_num_of_otrigs, 0),			\
 	.otrig_base_address = DT_INST_PROP_OR(n, nxp_dma_otrig_base_address, 0x0),	\
 	.itrig_base_address = DT_INST_PROP_OR(n, nxp_dma_itrig_base_address, 0x0),	\