Original: From the time that the processor 's instruction decoder has figured out that it has encountered a conditional branch instruction to the time that the deciding register value can be read out , the pipeline needs to be stalled for several cycles , or if it 's not and the branch is taken , the pipeline needs to be flushed .
Simplified: The from time that the processor 's instruction decoder has found that it has encountered a conditional branch instruction to the time that the deciding jumping register value can be read out , the pipeline might be stalled for several cycles .