msdsl (pypi): Library for generating synthesizable mixed-signal models for FPGA emulation
Keywords: analog|mixed-signal|mixed signal|behavioral|real number model|real number models|rnm|rnms|model|models|generator|verilog|system-verilog|system verilog|synthesizable|emulation|fpga|ams|analog-circuits|python|real-number-modeling|simulation|synthesis