다음은 ARM 홀딩스와 서드파티가 설계한 ARM 계열 명령어 집합 기반 마이크로아키텍처 목록이다. 케일 또한 ARM 기반 프로세서의 벤더 요약을 제공한다. ==ARM 코어== === ARM 설계 === ARM 계열 ARM 아키텍처 ARM 코어 기능 캐시 (I D), MMU 일반 MIPS MHz 참조 ARM1 ARMv1 ARM1 최초 구현 없음 ARM2 ARMv2 ARM2 ARMv2 added the MUL (multiply) instruction 없음 MIPS MHz0.33 드라이스톤/MHz ARMv2a ARM250 Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions 없음, MEMC1a MIPS 12 MHz ARM3 ARMv2a ARM3 First integrated memory cache KB unified 12 MIPS 25 MHz0.50 DMIPS/MHz ARM6 ARMv3 ARM60 ARMv3 first to support 32-bit memory address space (previously 26-bit).ARMv3M first added long multiply instructions (32x32=64). 없음 10 MIPS 12 MHz ARM600 As ARM60, cache and coprocessor bus (for FPA10 floating-point unit) KB unified 28 MIPS 33 MHz ARM610 As ARM60, cache, no coprocessor bus KB unified 17 MIPS 20 MHz0.65 DMIPS/MHz ARM7 ARMv3 ARM700 KB unified 40 MHz ARM710 As ARM700, no coprocessor bus KB unified 40 MHz ARM710a As ARM710 KB unified 40 MHz0.68 DMIPS/MHz ARM7T ARMv4T ARM7TDMI(-S) 3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing 없음 15 MIPS 16.8 MHz63 DMIPS 70 MHz ARM710T As ARM7TDMI, cache KB unified, MMU 36 MIPS 40 MHz ARM720T As ARM7TDMI, cache KB unified, MMU with FCSE (Fast Context Switch Extension) 60 MIPS 59.8 MHz ARM740T As ARM7TDMI, cache MPU ARM7EJ ARMv5TEJ ARM7EJ-S 5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructions 없음 ARM8 ARMv4 ARM810 5-stage pipeline, static branch prediction, memory KB unified, MMU 84 MIPS 72 MHz1.16 DMIPS/MHz ARM9T ARMv4T ARM9TDMI 5-stage pipeline, Thumb 없음 ARM920T As ARM9TDMI, cache 16 KB 16 KB, MMU with FCSE (Fast Context Switch Extension) 200 MIPS 180 MHz ARM922T As ARM9TDMI, caches KB KB, MMU ARM940T As ARM9TDMI, caches KB KB, MPU ARM9E ARMv5TE ARM946E-S Thumb, enhanced DSP instructions, caches Variable, tightly coupled memories, MPU ARM966E-S Thumb, enhanced DSP instructions No cache, TCMs ARM968E-S As ARM966E-S No cache, TCMs ARMv5TEJ ARM926EJ-S Thumb, Jazelle DBX, enhanced DSP instructions Variable, TCMs, MMU 220 MIPS 200 MHz ARMv5TE ARM996HS Clockless processor, as ARM966E-S No caches, TCMs, MPU ARM10E ARMv5TE ARM1020E 6-stage pipeline, Thumb, enhanced DSP instructions, (VFP) 32 KB 32 KB, MMU ARM1022E As ARM1020E 16 KB 16 KB, MMU ARMv5TEJ ARM1026EJ-S Thumb, Jazelle DBX, enhanced DSP instructions, (VFP) Variable, MMU or MPU ARM11 ARMv6 ARM1136J(F)-S 8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory access Variable, MMU 740 532–665 MHz (i.MX31 SoC), 400–528 MHz ARMv6T2 ARM1156T2(F)-S 9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructions Variable, MPU ARMv6Z ARM1176JZ(F)-S As ARM1136EJ(F)-S Variable, MMU ARM 아키텍처 965 DMIPS 772 MHz, up to 2,600 DMIPS with four processors ARMv6K ARM11MPCore As ARM1136EJ(F)-S, 1–4 core SMP Variable, MMU SecurCore ARMv6-M SC000 0.9 DMIPS/MHz ARMv4T SC100 ARMv7-M SC300 1.25 DMIPS/MHz Cortex-M ARMv6-M Cortex-M0 Microcontroller profile, most Thumb some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory Optional cache, no TCM, no MPU 0.84 DMIPS/MHz Cortex-M0+ Microcontroller profile, most Thumb some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory Optional cache, no TCM, optional MPU with regions 0.93 DMIPS/MHz Cortex-M1 Microcontroller profile, most Thumb some Thumb-2, hardware multiply instruction (optional small), OS option adds SVC banked stack pointer, optional system timer, no bit-banding memory Optional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU 136 DMIPS 170 MHz, (0.8 DMIPS/MHz FPGA-dependent) ARMv7-M Cortex-M3 Microcontroller profile, Thumb Thumb-2, hardware multiply and divide instructions, optional bit-banding memory Optional cache, no TCM, optional MPU with regions 1.25 DMIPS/MHz ARMv7E-M Cortex-M4 Microcontroller profile, Thumb Thumb-2 DSP optional VFPv4-SP FPU, hardware multiply and divide instructions, optional bit-banding memory Optional cache, no TCM, optional MPU with regions 1.25 DMIPS/MHz (1.27 w/FPU) Cortex-M7 Microcontroller profile, Thumb Thumb-2 DSP optional VFPv5 single and double precision FPU, hardware multiply and divide instructions 0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with or 16 regions 2.14 DMIPS/MHz ARMv8-M Cortex-M23 Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZone Optional cache, no TCM, optional MPU with 16 regions 0.99 DMIPS/MHz Cortex-M33 Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor Optional cache, no TCM, optional MPU with 16 regions 1.50 DMIPS/MHz Cortex-M35P Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor Built-in cache (with option 2–16 KB), I-cache, no TCM, optional MPU with 16 regions 1.50 DMIPS/MHz Cortex-R ARMv7-R Cortex-R4 Real-time profile, Thumb Thumb-2 DSP optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity ECC for internal buses cache TCM, 8-stage pipeline dual-core running lockstep with fault logic 0–64 KB 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 8/12 regions 1.67 DMIPS/MHz Cortex-R5 Real-time profile, Thumb Thumb-2 DSP optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity ECC for internal buses cache TCM, 8-stage pipeline dual-core running lock-step with fault logic optional as independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP) 0–64 KB 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions 1.67 DMIPS/MHz Cortex-R7 Real-time profile, Thumb Thumb-2 DSP optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity ECC for internal buses cache TCM, 11-stage pipeline dual-core running lock-step with fault logic out-of-order execution dynamic register renaming optional as independent cores, low-latency peripheral port (LLPP), ACP 0–64 KB 0–64 KB, of 0–128 KB TCM, opt. MPU with 16 regions 2.50 DMIPS/MHz Cortex-R8 TBD TBD 2.50 DMIPS/MHz ARMv8-R Cortex-R52 TBD TBD 2.16 DMIPS/MHz Cortex-A(32비트) ARMv7-A Cortex-A5 Application profile, ARM Thumb Thumb-2 DSP SIMD Optional VFPv4-D16 FPU Optional NEON Jazelle RCT and DBX, 1–4 cores optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 4−64 KB 4−64 KB L1, MMU TrustZone 1.57 DMIPS/MHz per core Cortex-A7 Application profile, ARM Thumb Thumb-2 DSP VFPv4 FPU NEON Jazelle RCT and DBX Hardware virtualization, in-order execution, 슈퍼스칼라, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design 8−64 KB 8−64 KB L1, 0–1 MB L2, MMU TrustZone 1.9 DMIPS/MHz per core Cortex-A8 Application profile, ARM Thumb Thumb-2 VFPv3 FPU NEON Jazelle RCT and DAC, 13-stage 슈퍼스칼라 pipeline 16–32 KB 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU TrustZone Up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than GHz) Cortex-A9 Application profile, ARM Thumb Thumb-2 DSP Optional VFPv3 FPU Optional NEON Jazelle RCT and DBX, out-of-order speculative issue 슈퍼스칼라, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 16–64 KB 16–64 KB L1, 0–8 MB L2 opt. parity, MMU TrustZone 2.5 DMIPS/MHz per core, 10,000 DMIPS GHz on Performance Optimized TSMC 40G (dual-core) Cortex-A12 Application profile, ARM Thumb-2 DSP VFPv4 FPU NEON Hardware virtualization, out-of-order speculative issue 슈퍼스칼라, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 32−64 KB 3.0 DMIPS/MHz per core Cortex-A15 Application profile, ARM Thumb Thumb-2 DSP VFPv4 FPU NEON integer divide fused MAC Jazelle RCT hardware virtualization, out-of-order speculative issue 슈퍼스칼라, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline 32 KB w/parity 32 KB w/ECC L1, 0–4 MB L2, L2 has ECC, MMU TrustZone At least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation) Cortex-A17 Application profile, ARM Thumb Thumb-2 DSP VFPv4 FPU NEON integer divide fused MAC Jazelle RCT hardware virtualization, out-of-order speculative issue 슈퍼스칼라, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP 32 KB L1, 256 KB–8 MB L2 w/optional ECC 2.8 DMIPS/MHz ARMv8-A Cortex-A32 Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline 8–64 KB w/optional parity 8−64 KB w/optional ECC L1 per core, 128 KB–1 MB L2 w/optional ECC shared Cortex-A(64비트) ARMv8-A ARM 아키텍처 Application profile, AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline 8−64 KB w/parity 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses Cortex-A35 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline 8−64 KB w/parity 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses 1.78 DMIPS/MHz Cortex-A53 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline 8−64 KB w/parity 8−64 KB w/ECC L1 per core, 128 KB–2 MB L2 shared, 40-bit physical addresses 2.3 DMIPS/MHz Cortex-A57 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline 48 KB w/DED parity 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses 4.1–4.5 DMIPS/MHz Cortex-A72 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width superscalar, deeply out-of-order pipeline 48 KB w/DED parity 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses 4.7 DMIPS/MHz Cortex-A73 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width superscalar, deeply out-of-order pipeline 64 KB 32−64 KB L1 per core, 256 KB–8 MB L2 shared w/ optional ECC, 44-bit physical addresses 4.8 DMIPS/MHz ARMv8.2-A Cortex-A55 Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline 16−64 KB 16−64 KB L1, 256 KB L2 per core, MB L3 shared Arm Cortex-A65AE Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, out-of-order pipeline, SMT 64 64 KB L1, 256 KB L2 per core, MB L3 shared Cortex-A75 Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline 64 64 KB L1, 512 KB L2 per core, MB L3 shared Cortex-A76 Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way issue, 13 stage pipeline, deeply out-of-order pipeline 64 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared Cortex-A77 Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 6-width instruction fetch, 12-way issue, 13 stage pipeline, deeply out-of-order pipeline 1.5K L0 MOPs cache, 64 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared Neoverse Neoverse N1 Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way dispatch/issue, 13 stage pipeline, deeply out-of-order pipeline 64 64 KB L1, 512−1024 KB L2 per core, 2−128 MB L3 shared, 128 MB system level cache Neoverse E1 Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, 10 stage pipeline, out-of-order pipeline, SMT 32−64 KB 32−64 KB L1, 256 KB L2 per core, MB L3 shared ARM 계열 ARM 아키텍처 ARM 코어 기능 캐시 (I D), MMU 일반 MIPS MHz 참조 As Dhrystone is synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads use with caution. === 서드 파티 설계 === 코어 계열 명령어 집합 마이크로아키텍처 기능 캐시 (I D), MMU 일반 MIPS MHz ARMv4 SA-110 5-stage pipeline 16 KB 16 KB, MMU 100–233 MHz1.0 DMIPS/MHz SA-1100 derivative of the SA-110 16 KB KB, MMU Faraday(Faraday Technology) ARMv4 FA510 6-stage pipeline Up to 32 KB 32 KB cache, MPU 1.26 DMIPS/MHz 100–200 MHz FA526 Up to 32 KB 32 KB cache, MMU 1.26 MIPS/MHz 166–300 MHz FA626 8-stage pipeline 32 KB 32 KB cache, MMU 1.35 DMIPS/MHz 500 MHz ARMv5TE FA606TE 5-stage pipeline No cache, no MMU 1.22 DMIPS/MHz200 MHz FA626TE 8-stage pipeline 32 KB 32 KB cache, MMU 1.43 MIPS/MHz800 MHz FMP626TE 8-stage pipeline, SMP 1.43 MIPS/MHz500 MHz FA726TE 13 stage pipeline, dual issue 2.4 DMIPS/MHz1000 MHz XScale(인텔 Marvell) ARMv5TE XScale 7-stage pipeline, Thumb, enhanced DSP instructions 32 KB 32 KB, MMU 133–400 MHz Bulverde Wireless MMX, wireless 스피드스텝 added 32 KB 32 KB, MMU 312–624 MHz Monahans Wireless MMX2 added 32 KB 32 KB L1, optional L2 cache up to 512 KB, MMU Up to 1.25 GHz Sheeva(Marvell) ARMv5 Feroceon 5–8 stage pipeline, single-issue 16 KB 16 KB, MMU 600–2000 MHz Jolteon 5–8 stage pipeline, dual-issue 32 KB 32 KB, MMU PJ1 (Mohawk) 5–8 stage pipeline, single-issue, Wireless MMX2 32 KB 32 KB, MMU 1.46 DMIPS/MHz1.06 GHz ARMv6 ARMv7-A PJ4 6–9 stage pipeline, dual-issue, Wireless MMX2, SMP 32 KB 32 KB, MMU 2.41 DMIPS/MHz1.6 GHz Snapdragon(퀄컴) ARMv7-A Scorpion or cores. ARM Thumb Thumb-2 DSP SIMD VFPv3 FPU NEON (128-bit wide) 256 KB L2 per core 2.1 DMIPS/MHz per core Krait 1, 2, or cores. ARM Thumb Thumb-2 DSP SIMD VFPv4 FPU NEON (128-bit wide) KB KB L0, 16 KB 16 KB L1, 512 KB L2 per core 3.3 DMIPS/MHz per core ARMv8-A Kryo cores. Up to 2.2 GHz (6.3 DMIPS/MHz) Ax(Apple) ARMv7-A Swift cores. ARM Thumb Thumb-2 DSP SIMD VFPv4 FPU NEON L1: 32 KB 32 KB, L2: MB 3.5 DMIPS/MHz per core ARMv8-A Cyclone cores. ARM Thumb Thumb-2 DSP SIMD VFPv4 FPU NEON ARM 아키텍처 AArch64. Out-of-order, superscalar. L1: 64 KB 64 KB, L2: MB, L3: MB 1.3 or 1.4 GHz ARMv8-A Typhoon or cores. ARM Thumb Thumb-2 DSP SIMD VFPv4 FPU NEON ARM 아키텍처 AArch64 L1: 64 KB 64 KB, L2: MB or MB, L3: MB 1.4 or 1.5 GHz ARMv8-A Twister cores. ARM Thumb Thumb-2 DSP SIMD VFPv4 FPU NEON ARM 아키텍처 AArch64 L1: 64 KB 64 KB, L2: MB, L3: MB or MB 1.85 or 2.26 GHz ARMv8.1-A Hurricane and Zephyr Hurricane: or cores. AArch64, 6-decode, 6-issue, 9-wide, superscalar, or cores. AArch64. L1: 64 KB 64 KB, L2: MB or MB, L3: MB or MB 2.34 or 2.38 GHz ARMv8.2-A Monsoon and Mistral Monsoon: cores. AArch64, 7-decode, ?-issue, 11-wide, superscalar, cores. AArch64, out-of-order, superscalar. Based on Swift. L1I: 128 KB, L1D: 64 KB, L2: MB, L3: MB 2.39 GHz ARMv8.3-A Vortex and Tempest Vortex: or cores. AArch64, 7-decode, ?-issue, 11-wide, superscalar, cores. AArch64, 3-decode, out-of-order, superscalar. Based on Swift. L1: 128 KB 128 KB, L2: MB, L3: MB 2.5 GHz ARMv8.4-A Lightning and Thunder Lightning: cores. AArch64, 7-decode, ?-issue, 11-wide, superscalar, cores. AArch64, out-of-order, superscalar. L1: 128 KB 128 KB, L2: MB, L3: 16 MB 2.66 GHz X-Gene(Applied Micro) ARMv8-A X-Gene 64-bit, quad issue, SMP, 64 cores Cache, MMU, virtualization GHz (4.2 DMIPS/MHz per core) Denver(엔비디아) ARMv8-A Denver cores. AArch64, 7-wide 슈퍼스칼라, in-order, dynamic code optimization, 128 MB optimization cache,Denver1: 28nm, Denver2:16nm 128 KB I-cache 64 KB D-cache Up to 2.5 GHz Carmel(엔비디아) ARMv8(t.b.d.) Carmel cores. AArch64, 10-wide 슈퍼스칼라, in-order, dynamic code optimization, MB optimization safety, dual execution, parity ECC KB I-cache KB D-cache Up to GHz ARMv8-A ThunderX 64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips) Up to 2.2 GHz K12(어드밴스트 마이크로 디바이시스) ARMv8-A K12 삼성 엑시노스(삼성그룹) ARMv8-A M1/M2 ("Mongoose") cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order 64 KB I-cache 32 KB D-cache, L2: 16-way shared MB 5.1 DMIPS/MHz (2.6 GHz) ARMv8-A M3 ("Meerkat") cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order 64 KB I-cache 32 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared MB ARMv8.2-A M4 ("Cheetah") cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order 64 KB I-cache 32 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared MB == ARM 코어 타임라인 == 다음의 표는 발표 연도별 코어를 나열한다. ARM7 이전 코어는 표에 포함되어 있지 않다. 연도 클래식 코어 Cortex 코어 Neoverse 코어 ARM7 ARM8 ARM9 ARM10 ARM11 마이크로컨트롤러 실시간 애플리케이션(32비트) 애플리케이션(64비트) 애플리케이션(64비트) 1993 ARM700 1994 1995 ARM710a 1996 ARM810 1997 1998 ARM9TDMIARM940T 1999 2000 ARM1020T 2001 2002 ARM1026EJ-S ARM1136J(F)-S 2003 ARM968E-S 2004 Cortex-M3 2005 ARM11MPCore Cortex-A8 2006 ARM996HS 2007 Cortex-M1 Cortex-A9 2008 2009 Cortex-M0 Cortex-A5 2010 Cortex-M4(F) Cortex-A15 2011 Cortex-A7 2012 Cortex-M0+ 2013 Cortex-A12 2014 Cortex-M7(F) Cortex-A17 2015 2016 Cortex-A32 Cortex-A73 2017 2018 Cortex-M35P(F) 2019 Cortex-A77 Neoverse E1Neoverse N1 2020 Cortex-M55(F) Cortex-A78 Cortex-X1 == 같이 보기 == ARM 아키텍처 == 각주 == 분류:마이크로프로세서 목록 분류:ARM 코어