Theorem: BVExpr.bitblast.blastVar.go_eq_eval_getLsb (LeanSAT/Reflect/BVExpr/BitBlast/Lemmas/Var.lean)

State before:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
⊢ ∀ (idx : Nat) (hidx1 : idx < w),
    curr ≤ idx →
      ⟦{ aig := (go w aig curr s a hcurr).aig, ref := (go w aig curr s a hcurr).stream.getRef idx hidx1 },
          assign.toAIGAssignment⟧ =
        (eval assign (var a)).getLsb idx
Tactic:
intro idx hidx1 hidx2
State after:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
⊢ ⟦{ aig := (go w aig curr s a hcurr).aig, ref := (go w aig curr s a hcurr).stream.getRef idx hidx1 },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx

State before:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
⊢ ⟦{ aig := (go w aig curr s a hcurr).aig, ref := (go w aig curr s a hcurr).stream.getRef idx hidx1 },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx
Tactic:
generalize hgo : go w aig curr s a hcurr = res
State after:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hgo : go w aig curr s a hcurr = res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx

State before:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hgo : go w aig curr s a hcurr = res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
unfold go at hgo
State after:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hgo :
  (if hidx : curr < w then
      let res := aig.mkAtomCached (BVBit.mk a ⟨curr, hidx⟩);
      let aig_1 := res.aig;
      let bitRef := res.ref;
      let s := s.cast ⋯;
      let s := s.pushRef bitRef;
      go w aig_1 (curr + 1) s a ⋯
    else
      let_fun hidx := ⋯;
      { aig := aig, stream := hidx ▸ s }) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx

State before:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hgo :
  (if hidx : curr < w then
      let res := aig.mkAtomCached (BVBit.mk a ⟨curr, hidx⟩);
      let aig_1 := res.aig;
      let bitRef := res.ref;
      let s := s.cast ⋯;
      let s := s.pushRef bitRef;
      go w aig_1 (curr + 1) s a ⋯
    else
      let_fun hidx := ⋯;
      { aig := aig, stream := hidx ▸ s }) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
split at hgo
State after:
case isTrue
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
h✝ : curr < w
hgo :
  (let res := aig.mkAtomCached (BVBit.mk a ⟨curr, h✝⟩);
    let aig_1 := res.aig;
    let bitRef := res.ref;
    let s := s.cast ⋯;
    let s := s.pushRef bitRef;
    go w aig_1 (curr + 1) s a ⋯) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx

case isFalse
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
h✝ : ¬curr < w
hgo :
  (let_fun hidx := ⋯;
    { aig := aig, stream := hidx ▸ s }) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx

State before:
case isTrue
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
h✝ : curr < w
hgo :
  (let res := aig.mkAtomCached (BVBit.mk a ⟨curr, h✝⟩);
    let aig_1 := res.aig;
    let bitRef := res.ref;
    let s := s.cast ⋯;
    let s := s.pushRef bitRef;
    go w aig_1 (curr + 1) s a ⋯) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx

case isFalse
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
h✝ : ¬curr < w
hgo :
  (let_fun hidx := ⋯;
    { aig := aig, stream := hidx ▸ s }) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
. next hlt =>
  dsimp at hgo
  cases Nat.eq_or_lt_of_le hidx2 with
  | inl heq =>
    rw [← hgo]
    rw [go_getRef]
    rw [AIG.RefStream.getRef_push_ref_eq']
    . rw [← heq]
      rw [go_denote_mem_prefix]
      . simp [hlt]
      . simp [Ref.hgate]
    . rw [heq]
  | inr =>
    rw [← hgo]
    dsimp
    rw [go_eq_eval_getLsb]
    . simp
    . omega
State after:
case isFalse
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
h✝ : ¬curr < w
hgo :
  (let_fun hidx := ⋯;
    { aig := aig, stream := hidx ▸ s }) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx

State before:
case isFalse
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
h✝ : ¬curr < w
hgo :
  (let_fun hidx := ⋯;
    { aig := aig, stream := hidx ▸ s }) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
. omega
State after:
no goals

State before:
case isTrue
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
h✝ : curr < w
hgo :
  (let res := aig.mkAtomCached (BVBit.mk a ⟨curr, h✝⟩);
    let aig_1 := res.aig;
    let bitRef := res.ref;
    let s := s.cast ⋯;
    let s := s.pushRef bitRef;
    go w aig_1 (curr + 1) s a ⋯) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
next hlt =>
dsimp at hgo
cases Nat.eq_or_lt_of_le hidx2 with
| inl heq =>
  rw [← hgo]
  rw [go_getRef]
  rw [AIG.RefStream.getRef_push_ref_eq']
  . rw [← heq]
    rw [go_denote_mem_prefix]
    . simp [hlt]
    . simp [Ref.hgate]
  . rw [heq]
| inr =>
  rw [← hgo]
  dsimp
  rw [go_eq_eval_getLsb]
  . simp
  . omega
State after:
no goals

State before:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  (let res := aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩);
    let aig_1 := res.aig;
    let bitRef := res.ref;
    let s := s.cast ⋯;
    let s := s.pushRef bitRef;
    go w aig_1 (curr + 1) s a ⋯) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
dsimp at hgo
State after:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx

State before:
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
cases Nat.eq_or_lt_of_le hidx2 with
| inl heq =>
  rw [← hgo]
  rw [go_getRef]
  rw [AIG.RefStream.getRef_push_ref_eq']
  . rw [← heq]
    rw [go_denote_mem_prefix]
    . simp [hlt]
    . simp [Ref.hgate]
  . rw [heq]
| inr =>
  rw [← hgo]
  dsimp
  rw [go_eq_eval_getLsb]
  . simp
  . omega
State after:
no goals

State before:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
rw [← hgo]
State after:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
                  ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).stream.getRef
            idx hidx1 },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx

State before:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
                  ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).stream.getRef
            idx hidx1 },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx
Tactic:
rw [go_getRef]
State after:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref := (((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref).getRef idx ?inl.hidx).cast ⋯ },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx

case inl.hidx
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ idx < curr + 1

State before:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref := (((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref).getRef idx ?inl.hidx).cast ⋯ },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx

case inl.hidx
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ idx < curr + 1
Tactic:
rw [AIG.RefStream.getRef_push_ref_eq']
State after:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯ },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx

case inl.hidx
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ idx = curr

State before:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯ },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx

case inl.hidx
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ idx = curr
Tactic:
. rw [← heq]
  rw [go_denote_mem_prefix]
  . simp [hlt]
  . simp [Ref.hgate]
State after:
case inl.hidx
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ idx = curr

State before:
case inl.hidx
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ idx = curr
Tactic:
. rw [heq]
State after:
no goals

State before:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯ },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx
Tactic:
rw [← heq]
State after:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯ },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb curr

State before:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯ },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb curr
Tactic:
rw [go_denote_mem_prefix]
State after:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{ aig := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig,
        ref := { gate := ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate, hgate := ?inl.hstart } },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb curr

case inl.hstart
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate <
    (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig.decls.size

State before:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{ aig := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig,
        ref := { gate := ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate, hgate := ?inl.hstart } },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb curr

case inl.hstart
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate <
    (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig.decls.size
Tactic:
. simp [hlt]
State after:
case inl.hstart
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate <
    (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig.decls.size

State before:
case inl.hstart
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate <
    (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig.decls.size
Tactic:
. simp [Ref.hgate]
State after:
no goals

State before:
case inl
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ⟦{ aig := (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig,
        ref := { gate := ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate, hgate := ?inl.hstart } },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb curr
Tactic:
simp [hlt]
State after:
no goals

State before:
case inl.hstart
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ ((aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref.cast ⋯).gate <
    (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig.decls.size
Tactic:
simp [Ref.hgate]
State after:
no goals

State before:
case inl.hidx
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
heq : curr = idx
⊢ idx = curr
Tactic:
rw [heq]
State after:
no goals

State before:
case inr
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
rw [← hgo]
State after:
case inr
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
                  ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).stream.getRef
            idx hidx1 },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx

State before:
case inr
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
                  ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).stream.getRef
            idx hidx1 },
      assign.toAIGAssignment⟧ =
    (eval assign (var a)).getLsb idx
Tactic:
dsimp
State after:
case inr
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
                  ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).stream.getRef
            idx hidx1 },
      assign.toAIGAssignment⟧ =
    (BitVec.truncate w (assign.getD a).bv).getLsb idx

State before:
case inr
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ ⟦{
        aig :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
              ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).aig,
        ref :=
          (go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
                  ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯).stream.getRef
            idx hidx1 },
      assign.toAIGAssignment⟧ =
    (BitVec.truncate w (assign.getD a).bv).getLsb idx
Tactic:
rw [go_eq_eval_getLsb]
State after:
case inr
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ (eval assign (var a)).getLsb idx = (BitVec.truncate w (assign.getD a).bv).getLsb idx

case inr.a
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ curr + 1 ≤ idx

State before:
case inr
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ (eval assign (var a)).getLsb idx = (BitVec.truncate w (assign.getD a).bv).getLsb idx

case inr.a
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ curr + 1 ≤ idx
Tactic:
. simp
State after:
case inr.a
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ curr + 1 ≤ idx

State before:
case inr.a
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ curr + 1 ≤ idx
Tactic:
. omega
State after:
no goals

State before:
case inr
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ (eval assign (var a)).getLsb idx = (BitVec.truncate w (assign.getD a).bv).getLsb idx
Tactic:
simp
State after:
no goals

State before:
case inr.a
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
hlt : curr < w
hgo :
  go w (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).aig (curr + 1)
      ((s.cast ⋯).pushRef (aig.mkAtomCached (BVBit.mk a ⟨curr, hlt⟩)).ref) a ⋯ =
    res
h✝ : curr < idx
⊢ curr + 1 ≤ idx
Tactic:
omega
State after:
no goals

State before:
case isFalse
w : Nat
aig : AIG BVBit
a : Nat
assign : Assignment
curr : Nat
hcurr : curr ≤ w
s : aig.RefStream curr
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry BVBit w
h✝ : ¬curr < w
hgo :
  (let_fun hidx := ⋯;
    { aig := aig, stream := hidx ▸ s }) =
    res
⊢ ⟦{ aig := res.aig, ref := res.stream.getRef idx hidx1 }, assign.toAIGAssignment⟧ = (eval assign (var a)).getLsb idx
Tactic:
omega
State after:
no goals