Theorem: AIG.mkAndCached_decl_eq (LeanSAT/AIG/CachedGatesLemmas.lean)

State before:
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
idx : Nat
aig : AIG α
input : aig.BinaryInput
h : idx < aig.decls.size
h2 : idx < (aig.mkAndCached input).aig.decls.size
⊢ (aig.mkAndCached input).aig.decls[idx] = aig.decls[idx]
Tactic:
simp only [mkAndCached]
State after:
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
idx : Nat
aig : AIG α
input : aig.BinaryInput
h : idx < aig.decls.size
h2 : idx < (aig.mkAndCached input).aig.decls.size
⊢ (aig.mkGateCached (input.asGateInput false false)).aig.decls[idx] = aig.decls[idx]

State before:
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
idx : Nat
aig : AIG α
input : aig.BinaryInput
h : idx < aig.decls.size
h2 : idx < (aig.mkAndCached input).aig.decls.size
⊢ (aig.mkGateCached (input.asGateInput false false)).aig.decls[idx] = aig.decls[idx]
Tactic:
rw [AIG.LawfulOperator.decl_eq (f := mkGateCached)]
State after:
no goals