Theorem: Prod.Lex.mk_fst_mono_lt_iff (Etch/Verification/Misc.lean)

State before:
m : Type u → Type v
inst✝² : Monad m
α : Type u_1
β : Type u_2
r₁ : α → α → Prop
r₂ : β → β → Prop
inst✝¹ : Preorder α
inst✝ : Preorder β
x : α
y₁ y₂ : β
⊢ (x, y₁) < (x, y₂) ↔ y₁ < y₂
Tactic:
simp [lt_iff']
State after:
no goals