Theorem: Etch.Verification.Stream.min_toOrder_le (Etch/StreamFusion/Proofs/StreamMul.lean)

State before:
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q)) ≤ toOrder (mul a b) q
Tactic:
rw [Prod.Lex.le_iff'']
State after:
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ (min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).1 ≤ (toOrder (mul a b) q).1 ∧
    ((min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).1 = (toOrder (mul a b) q).1 →
      (min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).2 ≤ (toOrder (mul a b) q).2)

State before:
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ (min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).1 ≤ (toOrder (mul a b) q).1 ∧
    ((min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).1 = (toOrder (mul a b) q).1 →
      (min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).2 ≤ (toOrder (mul a b) q).2)
Tactic:
simp only [Monotone.map_min (@Prod.Lex.fst_mono ι Bool _ _)]
State after:
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ min (toOrder a (mul.valid.fst q)).1 (toOrder b (mul.valid.snd q)).1 ≤ (toOrder (mul a b) q).1 ∧
    (min (toOrder a (mul.valid.fst q)).1 (toOrder b (mul.valid.snd q)).1 = (toOrder (mul a b) q).1 →
      (min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).2 ≤ (toOrder (mul a b) q).2)

State before:
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ min (toOrder a (mul.valid.fst q)).1 (toOrder b (mul.valid.snd q)).1 ≤ (toOrder (mul a b) q).1 ∧
    (min (toOrder a (mul.valid.fst q)).1 (toOrder b (mul.valid.snd q)).1 = (toOrder (mul a b) q).1 →
      (min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).2 ≤ (toOrder (mul a b) q).2)
Tactic:
constructor
State after:
case left
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ min (toOrder a (mul.valid.fst q)).1 (toOrder b (mul.valid.snd q)).1 ≤ (toOrder (mul a b) q).1

case right
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ min (toOrder a (mul.valid.fst q)).1 (toOrder b (mul.valid.snd q)).1 = (toOrder (mul a b) q).1 →
    (min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).2 ≤ (toOrder (mul a b) q).2

State before:
case left
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ min (toOrder a (mul.valid.fst q)).1 (toOrder b (mul.valid.snd q)).1 ≤ (toOrder (mul a b) q).1
Tactic:
exact min_le_max
State after:
no goals

State before:
case right
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ min (toOrder a (mul.valid.fst q)).1 (toOrder b (mul.valid.snd q)).1 = (toOrder (mul a b) q).1 →
    (min (toOrder a (mul.valid.fst q)) (toOrder b (mul.valid.snd q))).2 ≤ (toOrder (mul a b) q).2
Tactic:
simp only [toOrder]
State after:
case right
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ min (a.index (mul.valid.fst q)) (b.index (mul.valid.snd q)) = (mul a b).index q →
    (min (a.index (mul.valid.fst q), a.ready (mul.valid.fst q))
          (b.index (mul.valid.snd q), b.ready (mul.valid.snd q))).2 ≤
      (mul a b).ready q

State before:
case right
ι : Type
inst✝¹ : LinearOrder ι
α : Type u
inst✝ : Mul α
a b : Stream ι α
q : { p // mul.valid a b p = true }
⊢ min (a.index (mul.valid.fst q)) (b.index (mul.valid.snd q)) = (mul a b).index q →
    (min (a.index (mul.valid.fst q), a.ready (mul.valid.fst q))
          (b.index (mul.valid.snd q), b.ready (mul.valid.snd q))).2 ≤
      (mul a b).ready q
Tactic:
aesop
State after:
no goals