Title: FlashMoE: Fast Distributed MoE in a Single Kernel
Venue: NeurIPS 2025
Accepted: yes
Keywords: Distributed Machine Learning

Kernel Fusion

Mixture-of-Experts
Abstract: The computational sparsity of Mixture-of-Experts (MoE) models enables sub-linear growth in compute cost as model size increases, thus offering a scalable path to training massive neural networks. However, existing implementations suffer from low GPU utilization, significant latency overhead, and a fundamental inability to leverage task locality, primarily due to CPU-managed scheduling, host-initiated communication, and frequent kernel launches. To overcome these limitations, we develop FlashMoE, a fully GPU-resident MoE operator that fuses expert computation and inter-GPU communication into a single persistent GPU kernel. FlashMoE enables fine-grained pipelining of dispatch, compute, and combine phases, eliminating launch overheads and reducing idle gaps. Unlike existing work, FlashMoE obviates bulk-synchronous collectives for one-sided, device-initiated, inter-GPU (R)DMA transfers, thus unlocking payload efficiency, where we eliminate bloated or redundant network payloads in sparsely activated layers. When evaluated on an 8-H100 GPU node with MoE models having up to 128 experts and 16K token sequences, FlashMoE achieves up to 9× higher GPU utilization, 6× lower latency, 5.7× higher throughput, and 4× better overlap efficiency compared to state-of-the-art baselines—despite using FP32 while baselines use FP16. FlashMoE shows that principled GPU kernel-hardware co-design is key to unlocking the performance ceiling of large-scale distributed ML. We provide code at https://github.com/osayamenja/FlashMoE.

FlashMoE: Fast Distributed MoE in a Single Kernel

Abstract

The computational sparsity of Mixture-of-Experts (MoE) models enables sublinear growth in compute cost as model size increases, thus offering a scalable path to training massive neural networks. However, existing implementations suffer from low GPU utilization, significant latency overhead, and a fundamental inability to leverage task locality, primarily due to CPU-managed scheduling, host-initiated communication, and frequent kernel launches. To overcome these limitations, we develop FlashMoE, a fully GPU-resident MoE operator that fuses expert computation and inter-GPU communication into a single persistent GPU kernel. FlashMoE enables fine-grained pipelining of dispatch, compute, and combine phases, eliminating launch overheads and reducing idle gaps. Unlike existing work, FlashMoE obviates bulk-synchronous collectives for one-sided, device-initiated, inter-GPU (R)DMA transfers, thus unlocking payload efficiency, where we eliminate bloated or redundant network payloads in sparsely activated layers. When evaluated on an 8-H100 GPU node with MoE models having up to 128 experts and 16K token sequences, FlashMoE achieves up to 9 × higher GPU utilization, 6 × lower latency, 5.7 × higher throughput, and 4 × better overlap efficiency compared to state-of-the-art baselines-despite using FP32 while baselines use FP16. FlashMoE shows that principled GPU kernel-hardware co-design is key to unlocking the performance ceiling of large-scale distributed ML. We provide code at https://github.com/osayamenja/FlashMoE .

FlashMoE

Comet

FasterMoE

0

20

40

60

80

100

Average SM Util (%)

93.17%

42.31%

9.67%

59.11%

13.55%

Forward Pass |

E

=64 |

k

=2 | 2 A100s |

is better

(a) GPU SM Utilization

2

4

8

# of H100s

0

5

10

15

20

25

Runtime (ms)

3.3

3.4

3.7

10.3

12.6

21.3

4.2

16.6

18.9

4.4

9.0

18.9

Forward Latency | T = 8K |

E

=32 |

k

=2 |

is better

FlashMoE

FasterMoE

Megatron-TE

4K

8K

16K

Number of Tokens

0

10

20

30

40

Runtime (ms)

2.1

3.7

7.0

10.3

21.3

45.3

9.9

18.9

36.9

10.0

18.9

36.9

Forward Latency |

E

=32 |

k

=2 | 8 H100s |

is better

FlashMoE

FasterMoE

Megatron-TE

(b) Scaling Tokens

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128

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is better

FlashMoE

FasterMoE

Megatron-TE

(c) Weak Scaling across GPUs

Rachee Singh

Cornell University rs2293@cornell.edu

1 Introduction

State-of-the-art large language models (LLMs) [1-5] have adopted the Mixture-ofExperts (MoE) architecture for its computational efficiency and strong performance across a range of tasks. The traditional Transformer block consists of a self-attention module followed by a dense feed-forward network (FFN) [6]. In contrast, MoE architectures replace this single FFN (Figure 2(a)) with many identically sized FFNs, known as experts (Figure 2(b)). A trainable neural network, known as a gate function, sparsely activates these experts by dynamically routing input tokens to the experts selected at runtime. This increase in model parameters due to more FFNs improves model quality without the corresponding increase in computational cost.

Communication overheads in MoE. As MoE

model sizes grow, GPU memory constraints prevent hosting all experts on a single device. The standard practice is to distribute experts across multiple GPUs using expert parallelism (EP), which requires token routing via many-to-many communication primitives like AlltoAll [1, 4, 3, 7] (Figure 2(c)). Another round of AlltoAll communication restores the permuted tokens processed by experts to their original order in the sequence. AlltoAll communication is challenging to optimize on GPU networks and is highly sensitive to straggler delays - a phenomenon where a single straggler GPU delays all others from making progress [8]. These communication operations can account for 68% of the total runtime [9, 10], causing GPUs to remain idle (Figure 3, top left).

Kernel launch overheads in MoE. To mitigate these communication bottlenecks, recent work pipelines computation with communication kernels (Figure 3, left middle). However, the effectiveness of these solutions is limited by the overhead of launching many kernels from the CPU. Specifically, existing implementations [11-14] launch a large number of kernels per a single layer pass (see Table 1). Frequent kernel launches negatively affect performance by: (1) creating non-deterministic kernel start times across GPUs, exacerbating straggler issues; (2) introducing unnecessary synchronization points, causing GPUs to wait on peers or the CPU before proceeding; and (3) incurring repeated global memory round trips at kernel boundaries. Although CUDA graphs [15] can partially mitigate the first issue in static workloads, they are incompatible with MoE's dynamic expert routing patterns. Addressing the remaining issues requires novel solutions, which we provide in this work through complete kernel fusion and asynchronous device-initiated communication.

Attn

CPU

GPU

NIC

Gate

A2A (Dispatch)

E

A2A (Combine)

Attn

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GPU

NIC

Gate

Attn

CPU

GPU

NIC

Gate

E

Kernel launch

GPU kernel execution

Remote communication

A2A (Dispatch)

A2A (Combine)

E

E

E

Ours: FlashMoE

Single Kernel

Some Overlap

No Overlap

Time (milliseconds)

Gate

Expert

A2A

Expert

Expert

A2A

Scale

5

10

15

Baseline

MoE

FlashMoE

Our Contributions: distributed MoE in a single kernel. To overcome these fundamental inefficiencies in state-of-the-art MoE models, we develop FlashMoE a megakernel that integrates

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All-to-All (Combine)

(a) Transformer

(b) MoE

(c) Distributed MoE

all MoE computation and communication tasks into a single persistent GPU kernel i.e., a kernel that remains active for the entirety of the MoE operator (Figure 3 bottom left). Instead of multiple kernel launches coordinated by the CPU, FlashMoE requires launching only one kernel, significantly reducing the involvement of the CPU. Within the fused kernel, FlashMoE implements a reactive programming model to achieve fine-grained parallelism and loosely coupled, non-blocking execution among tens of thousands of GPU threads.

In-kernel Block scheduling and Tile paral-

lelism. FlashMoE implements tile-level parallelism , meaning it partitions input token matrices into smaller, independent units called tiles , which are processed by blocks but managed (scheduled and constructed) by warps. We specialize every thread block, except one, as processors to perform compute. In addition, we designate a dedicated Operating System (OS) block (4 warps) to perform administrative tasks of (1) scheduling computational work to processors ( scheduler ), and (2) decoding computational tasks from messages received from other GPUs ( subscriber ). This design allows FlashMoE to dynamically assign tasks to GPU blocks based on readiness , ensuring that no GPU SM remains idle throughout the lifetime of the MoE

Table 1: We report number of GPU operations launched by MoE implementations by profiling with Nsight Systems [17]. We count operations in a single MoE layer (Gate → Dispatch → Expert → Combine) on 2 A100 GPUs, where each GPU has 32 experts. FlashMoE is the first to fully fuse the distributed MoE layer into a single GPU kernel.

operator. FlashMoE selects tile dimensions to maximize GPU arithmetic intensity while benefitting from a high-degree of parallelism.

Asynchronous and payload-efficient communication. By redesigning the MoE operator from the ground up, FlashMoE resolves fundamental inefficiencies inherent in the conventional MoE execution pipeline. One notable inefficiency is token padding during communication. To simplify programming complexity and due to symmetry constraints of collective communication APIs, existing implementations have to zero-pad token payloads to match predefined buffer sizes. This occurs when tokens are asymmetrically routed to experts, resulting in GPUs receiving much less than the expected capacity. However, these null payloads waste communication bandwidth, bloat data transfer latency and may lead to unnecessary computations on null matrices in some implementations. FlashMoE introduces payload-efficient communication by sending non-padded tokens only to GPUs with actively selected experts, conserving both communication and computational resources.

Technical challenges. Realizing the single-kernel design of FlashMoE required solving several technical challenges to achieve high performance: (1) lightweight computational dependency management; (2) navigating optimal SM occupancy configurations; (3) implementing in-device BLAS operations; (4) minimizing inter- and intra-device synchronization overheads; (5) implementing transfer-awareness by leveraging DMA over Unified Virtual Addressing (UVA) when available. In addressing these challenges, FlashMoE's design presents a radical departure from traditional synchronous AlltoAll collectives, where GPUs exhibit significant idle time during layer execution. For device-initiated communication, FlashMoE uses NVSHMEM [18] to establish a global address space across all GPUs for Direct Memory Access (DMA) communication. For in-device BLAS, FlashMoE develops custom high-performance GEMM operations via CUTLASS [19].

Results. Our evaluations show that FlashMoE achieves 6 × latency speedup, 9 × higher GPU utilization, 4 × better weak scaling efficiency and 5.7 × increased throughput compared to state-ofthe-art implementations. We project these performance gains becoming even better in multi-node scenarios, where inter-node communication occurs using lower bandwidth inter-node links ( e.g., RDMA, Infiniband).

2 Motivation

Synchronous Communication. AlltoAll or AllGather communication as currently used in MoE frameworks is a synchronous collective operation, whose completion requires the participation of all involved GPUs. Here, disparities in processing speeds or kernel scheduling among GPUs induce

Comet

FasterMoE

0

20

40

60

80

100

Average SM Util (%)

42.31%

9.67%

59.11%

13.55%

Forward Pass |

E

=64 |

k

=2 | 2 A100s |

is better

FlashMoE

(a) GPU SM Utilization across baselines

(b) Kernel Launch overhead (CUDA API row)

a straggler effect detrimental (Figure 13) to (1) the collective operation's performance and (2) E2E performance, as stalled GPUs cannot proceed to downstream dependent or independent tasks until the collective terminates. We expound on this problem in §A.

Kernel Launch Overhead. We compare the kernel launch overheads between FlashMoE and existing baselines. Table 1 shows the number of kernel launches during a single forward pass: FlashMoE launches exactly one persistent kernel, while the baselines launch up to 550 short-lived kernels to perform the same computation. Figure 4 provides a visual comparison using CUDA API traces captured by NSight Systems, illustrating the difference between FlashMoE and DeepEP. DeepEP exhibits many small CUDA API calls, with frequent stalls between individual operators, leading to increased GPU idle time (Figure 4a). In contrast, FlashMoE maintains high GPU utilization by avoiding launch overhead and synchronization gaps-achieving 93.17 %GPUutilization compared to 14% for DeepEP. See §4 for experimental results and §B for a discussion of related work.

3 Fused MoE Kernel Design

Modern distributed MoE systems suffer from two limitations: (1) frequent many-to-many ( AlltoAll or AllGather ) collectives on the critical path, and (2) significant overhead from repeated kernel launches. We address these in FlashMoE, a fully fused MoE operator implemented as a single persistent GPU kernel. Unlike previous approaches [12, 1, 11, 13, 20, 10, 2125], FlashMoE is the first solution to implement a completely fused Distributed MoE kernel , eliminating kernel launch overhead entirely by requiring only a single kernel launch (see Table 1).

Actor-based model. The design of FlashMoE is based on the actor model of concurrent computation [26-28]. Weimplement this model by specializ-

Block n-1

FusedGate

Packet Encode and Dispatch

Subscriber

Block n-2

Block 1

Block 0

...

...

Warp

Processor

1

Processor

0

Processor

n-1

...

Scheduler

warp 0

warp 1 warp 2 warp 3

OS

Decoded Tasks

Remote

Packets

Send Tile to

GPU x

Send Tile

to GPU y

Send Tile

to GPU z

Schedule Task

t

to Processor

p

ing GPU thread blocks and warps into three distinct actor roles: (1) Processor (§F.1), (2) Subscriber (§F.3), and (3) Scheduler (§F.2). The Processor performs compute (GEMMs and element-wise operations) and tile communication. We use CUTLASS [19] as the underlying infrastructure for high-performance BLAS routines and NVSHMEM for kernel-initiated communication [18]. The Subscriber and Scheduler perform administrative functions. Specifically, the Scheduler assigns computational tasks to available thread blocks. Our key innovation is making the Scheduler both multithreaded , enabling high scheduling throughput, and work-conserving , ensuring consistently high GPU SM utilization. On the other hand, the Subscriber decodes tile packets from peer GPUs to task

Algorithm 1: FlashMoE Distributed MoE Fused Kernel

Figure 6: DMoE Functional Dependencies Expressed as a Chain of Actor Interactions . We denote S b , S h , and P as the Subscriber, Scheduler and Processor actors, respectively. For any actor a ∈ { S b , S h , P } , a i identifies an actor on GPU i . We define D j i as the operator, where GPU j dispatches packets of tiles to GPU i . This diagram expresses task dependencies at the granularity of a tile, namely GEMM 0 , GEMM 1 , combine and communication produce an output tile. Notifications occur as signals propagated through shared memory (subscriber ↔ scheduler) or global memory (scheduler ↔ processor or inter-GPU communication). Note one-sided inter-GPU transfers (packet or single tile) are coupled with a signal to notify S j b on the receiving GPU j of the message's delivery.

descriptors (§3.1). Of the N thread blocks on a GPU, we specialize N -1 to adopt the Processor role. We specialize the last block as the Operating System (OS). Within this block, we specialize three warps for the Subscriber role and one warp for the Scheduler role. This split of thread blocks across actors is intentional: our goal is to use few resources for administrative tasks while reserving bulk of the resources for performing MoE computation tasks. Figure 5 summarizes the FlashMoE architecture and its constituent actors, while Algorithm 1 gives a very close translation of the system in code. Note that A ∈ R S × H is the input token matrix; O ∈ R S × H the output matrix; and X ∈ R E × H × D is a 3-D tensor of expert weights, where E denotes the number of local experts for the executing GPU, H is the embedding dimension, D is the FFN intermediate dimension and S is the sequence length. T ϕ ∈ ( N × R ) E × C is a routing table data structure, where T ϕ ( e, c ) = ( i, w ) indicates that token i at slot c dispatches to expert e . w is the combine weight (Equation 2) and C is expert capacity. The tuple structure of T ϕ is an implementation detail. G ϕ ∈ R S × E captures the affinity scores produced by the gate (Equation 3). Inter-actor interactions in FlashMoE. FlashMoE decomposes MoE computation and communication at the granularity of a tile, a statically sized partition of a tensor, to achieve parallel execution and efficient overlap of tasks. Each tile maps to a discrete unit of work encapsulated by a task descriptor . The Subscriber decodes these task descriptors from the remote tile packets it receives. Concurrently, the Scheduler receives notifications about available tasks and dispatches them for execution to Processor actors that perform computations defined by these tasks, namely the feed-forward network (FFN) and expert-combine operations. Figure 6 show the chain of actor interactions, demonstrating how FlashMoE enforces DMoE functional dependencies.

Determining tile dimensions in FlashMoE. Selecting appropriate tile dimensions in FlashMoE is crucial to ensure efficient GPU utilization. An undersized tile underutilizes the GPU, while excessively large tiles create register pressure, causing performance-degrading register spills to local memory. After careful parameter sweeps, we choose tile dimensions of (128, 64). Our key insights are: increasing tile width significantly raises the register usage per thread, potentially triggering costly spills; increasing tile height without adjusting thread count increases workload per thread, harming performance. Raising the thread count per block beyond our fixed value of 128 threads reduces the

number of concurrent blocks, negatively affecting SM occupancy. Larger thread-block sizes also increase overhead from intra-block synchronization ( __syncthreads() barriers), further degrading performance. Thus, our chosen tile dimensions balance register usage, shared-memory constraints, and GPU occupancy to deliver optimal performance.

3.1 Task Abstraction for Computation

Computational operators. The FFN operator is a standard position-wise feed-forward network widely used in Transformer architectures [6], composed of two linear transformations separated by a nonlinear activation ϕ (e.g., GELU or ReLU):

Here, W 1 and W 2 represent learnable weight matrices, and b 1 and b 2 are biases. The expert-combine operation, used in architectures like GShard [29] and DeepSeek [1], merges outputs from multiple experts by computing a weighted combination based on their affinity scores:

In these equations, i ∈ 0 , S -1 represents an input token index, e = E i,k identifies the k -th expert selected for token i , and g i,e is the affinity score indicating how relevant expert e is for token i .

Unified task abstraction. We unify the FFN and combine operations under a common abstraction called a task . Tasks provide a uniform interface for communicating tile-level work among Subscribers, Schedulers, and Processors. Formally, a task descriptor t ∈ T is defined as a tuple:

where M is a set of metadata ( e.g., device ID, tile index), ⋆ is a binary tensor operation (specifically, matrix multiplication · or Hadamard product ⊙ ), and ϕ is an element-wise activation function (e.g., ReLU or identity).

We define a task t operating on input tensors A , B , D , producing output tensor C , as follows:

The operator ⋆ t (instantiated from ⋆ ) may behave differently depending on the task metadata M , and the result of A⋆ t B is accumulated into D . We provide an example of task metadata in §E.

In practice, we implement each task defined by Equation 4 as a single fused __device__ decorated function which the Processor (Algorithm 2) invokes at runtime. Fusion for t entails applying ϕ and the succeeding addition operation to registers storing the results of the binary operator ⋆ t . To illustrate its flexibility, we show how the FFN and expert-combine operations can be expressed using this task framework. Note that we omit the matrix multiplication symbol ( · ) for simplicity. Also, ϕ 1 can be any activation function, while ϕ 2 is the identity function. The FFN is expressed as:

Whereas, the expert-combine operation is formalized as:

3.2 Symmetric Tensor Layout for Inter-GPU Communication

Within a single GPU device, the actors in FlashMoE communicate through the GPU's memory subsystem. Specifically, the Scheduler and Subscriber actors exchange data via fast shared memory,

Exper t Par allel Gr oup

B0

B1

B0

B1

R0

R1

P0

P1

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E1

P0

E2

E3

P1

E0

E1

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E1

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P1 View

P1 R1 B1 E2

P0 R1 B0 E2

P0 R0 B1 E2

2.)

P0

stages the outgoing

message to

P1

before

remote transfer

3.)

P1

receives

4.)

P1

processes

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6.)

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receives

Start

1.)

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intends

to Dispatch

to

E2

on

P1

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4.)

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receives

Start

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P1

3.)

P1

processes

(a) Layout across 2 Expert-parallel Processes .

(b) State machine for DMA (top) and RDMA (bottom) communication.

while other actor pairs communicate through global memory. For communication across multiple devices, FlashMoE uses device-initiated communication , leveraging the one-sided PGAS (Partitioned Global Address Space) programming model [30]. However, achieving scalable and correct one-sided memory accesses in PGAS without costly synchronization is a known challenge [1, 31]. We address this challenge with a provably correct and scalable solution: a symmetric tensor layout L , supporting fully non-blocking memory accesses. We define L as:

where: P is the expert parallel world size, R identifies communication rounds ( i.e., two rounds, one for token dispatch and one for combine), B is number of staging buffers, E is the number of local experts, C is the upscaled expert capacity (§3.2.1) and H is the token embedding dimension. Our core insight to enable non-blocking communication is temporal buffering . Specifically, we overprovision memory for the underlying token matrix by at least 2 · r times, where r is the number of communication rounds in the dependency graph, and the factor of 2 accounts for separate buffers for incoming and outgoing data within each communication round. For MoE models, we have 2 · r = 4 . This modest increase in memory usage eliminates the need for synchronization during one-sided data transfers. Figure 7b illustrates how cells within this symmetric tensor layout are indexed and used for Direct Memory Access (DMA) and Remote DMA (RDMA) operations. As Theorem 3.1 reinforces, this indexing scheme over L is the underlying mechanism that allows for fully non-blocking accesses eliding synchronization because all accesses are write conflict-free . See§ C for the proof.

Theorem 3.1. The symmetric tensor layout L is write-write conflict-free.

To construct L , we start from the original token buffer T ∈ R S × H , where S is the sequence length and H is the token embedding dimension. We first reorganize the sequence dimension S into three sub-dimensions representing the expert capacity ( C ), local expert slots ( E ), and the expert parallel world size ( W ), st:

In the typical case of uniform expert distribution (illustrated in Figure 7a), we have S ′ = S and E ′ = E W , where E W is the total number of experts in the model. Thus, the size of the token buffer is Size ( T ) = S ′ · H . In Figure 7a, each cell labeled E i (with i ∈ { 0 , . . . , 3 } ) is a matrix of size ( C, H ) . Extending prior work [29, 12], we introduce additional temporal dimensions R (communication rounds) and B (staging buffers). Each communication round has two fixed staging slots: one for outgoing tokens and another for incoming tokens. Each slot, indexed by dimension P , forms a tensor of shape ( S ′ , H ) . Therefore, the tensor size Size ( L ) is generally at least four times the original token buffer size, becoming exactly four times larger in the case of uniform expert distribution. Empirically, we find Size ( L ) ≈ 4 · Size ( T ) , contributing memory overhead ≤ 2 % of memory capacity for inference of popular models. We present a thorough breakdown in §D.

3.2.1 In-place Padding for Payload Efficiency

Due to the dynamic and uneven distribution of tokens in MoE dispatch [32], GPUs commonly receive fewer tokens than their predefined expert capacity. Current MoE frameworks [11] typically pad these buffers with null tokens before computation, unnecessarily increasing communication payloads and degrading performance. In contrast, we propose in-place padding , performing padding directly within the local symmetric tensor buffers and thus eliminating excess network communication.

As we show in Figure 7a as a reference, each cell E i is sized according to the expert capacity C . We further align this capacity to ensure divisibility by the tile block size bM = 128 , guaranteeing safe and aligned memory reads by Processor threads consuming remote tokens. This in-place padding strategy slightly increases the memory footprint of L , as described below:

4 Evaluation

We implement (§G) and evaluate FlashMoE across five metrics: Forward Latency (§ 4.1), GPU Utilization (§ 4.2), Overlap Efficiency (§ 4.4), Throughput (§ 4.3), and Expert Scalability (§ 4.5). We run experiments on a server with 8 NVIDIA H100 80G GPUs interconnected via NVLink, 125 GBof RAM, and 20 vCPUs. We used PyTorch 2.6.0, CUDA 12.8, and Ubuntu 22.04. All experiments use MoE transformer models configured with 16 attention heads, an embedding dimension of 2048, and an FFN intermediate size of 2048. We apply Distributed Data Parallelism (DDP) and Expert Parallelism for all experiments. We execute only the forward pass over a single MoE layer and measure the average runtime of 32 passes after 32 warmup passes. We use top-2 routing with a capacity factor of 1.0. We compare FlashMoE against several state-of-the-art MoE systems: (1) Comet [12], (2) FasterMoE [14], (3) Megatron-CUTLASS [13], and (4) Megatron-TE : MegatronLM with Transformer Engine [33]. Comet relies on cudaMemcpyPeerAsync [34], while FasterMoE and Megatron-LM use NCCL exclusively for communication.

Desiderata. We observe Comet exhibiting anomalously bad performance values at 8 GPUs, so we exclude their results from evaluations at 8 GPUs and only include for results at ≤ 4 GPUs. We evaluate FlashMoE using FP32 precision whereas all baselines use FP16. We do so because (1) of incomplete fp16 tuning (§H) and (2) no baseline supports FP32. Note, this precision discrepancy disadvantages FlashMoE by doubling its communication volume and computational workload.

4.1 Forward Latency

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E

=32 |

k

=2 | 4 H100s |

is better

FlashMoE

Comet

FasterMoE

Megatron-TE

(a) 4 H100s

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18.9

36.9

Forward Latency |

E

=32 |

k

=2 | 8 H100s |

is better

FlashMoE

FasterMoE

Megatron-TE

(b) 8 H100s

We first measure the forward latency of FlashMoE across different sequence lengths on both 4 and 8 GPU setups (Figure 8). FlashMoE consistently outperforms all baselines, with especially notable improvements at longer sequence lengths. On 4 GPUs, it achieves up to 4.6 x speedup over Megatron-TE at 16K tokens, and 2.6 x over FasterMoE. The gains are even more pronounced at 8 GPUs where FlashMoE maintains low latency, exhibiting up to 6.4 x speedup over baselines that degrade steeply due to increasing communication costs as token buffers increase proportionally.

4.2 GPU Utilization

To quantify GPU efficiency, we measure Streaming Multiprocessor (SM) utilization during the forward pass (Figure 9). FlashMoE achieves 93.17% average SM utilization, over 9 x higher than FasterMoE (9.67%), 6.8 x higher than DeepEP+Megatron-LM (13.55%) 4 x higher than Megatron-TE (59.11%), and 2.2 x higher than Comet (42.31%). This improvement stems from our fully fused kernel architecture and finegrained pipelining of compute and communication tasks. By eliminating idle gaps due to kernel launches and enabling in-kernel task scheduling, FlashMoE ensures SMs remain busy with productive work throughout execution.

4.3 Throughput

As shown in Figure 10, FlashMoE scales linearly with GPU count, reaching 17.7 MTokens/s at 8 GPUs. This is over 5.7 x higher than FasterMoE and 4.9 x higher than Megatron-TE and Megatron-CUTLASS. Notably, these results are achieved despite FlashMoEoperating entirely in FP32, while baselines use FP16 . This indicates that FlashMoE 's design eliminates throughput bottlenecks not by exploiting lower precision, but by maximizing hardware utilization and eliminating host-driven inefficiencies.

FlashMoE

Comet

FasterMoE

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20

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Average SM Util (%)

93.17%

42.31%

9.67%

59.11%

13.55%

Forward Pass |

E

=64 |

k

=2 | 2 A100s |

is better

2

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4.90

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17.70

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3.68

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3.60

Forward Pass | T = 8K |

E

=32 |

k

=2 |

is better

FlashMoE

FasterMoE

Megatron-TE

# of H100s

4.4 Overlap Efficiency

2

4

8

# of H100s

0

5

10

15

20

25

Runtime (ms)

3.3

3.4

3.7

10.3

12.6

21.3

4.2

16.6

18.9

4.4

9.0

18.9

Forward Latency | T = 8K |

E

=32 |

k

=2 |

is better

FlashMoE

FasterMoE

Megatron-TE

2

4

8

# of H100s

0

20

40

60

80

100

100

97

90

100

82

48

100

26

22

100

49

24

Forward | T = 8K |

E

=32 |

k

=2 |

is better

Flash

FM

M-C

M-TE

(a) Latency as Number of GPUs increases.

(b) Weak scaling efficiency

We evaluate the extent to which FlashMoE overlaps communication and computation by measuring weak scaling efficiency as the number of GPUs increases (Figure 11b). We note that most baselines fail to execute at a single GPU, hence why we use 2 GPUs as the reference point. We observe that Megatron-CUTLASS and Megatron-TE degrade significantly, with overlap efficiency dropping below 50% at ≥ 4 GPUs. FlashMoE gives up to 3.88 x and 4 x higher efficiency at 4 and 8 GPUs, respectively. Figure 11a further illuminates this efficiency, as FlashMoE shows stable forward latency growth. These results corroborate that FlashMoE's actor-based design and asynchronous data movement achieve near-ideal overlap.

4.5 Expert Scalability

8

16

32

64

128

Number of Experts

0

5

10

15

20

25

30

35

Runtime (ms)

Forward Latency |

T

=16

K

|

k

=2 | 4 H100s |

is better

FlashMoE

Comet

FasterMoE

Megatron-TE

(a) 4 H100s

8

16

32

64

128

Number of Experts

0

10

20

30

40

50

60

Runtime (ms)

Forward Latency |

T

=16

K

|

k

=2 | 8 H100s |

is better

FlashMoE

FasterMoE

Megatron-TE

(b) 8 H100s

We analyze how FlashMoE scales with increasing number of experts at fixed sequence length (T = 16K). Note that for the discussed plots, the number of experts on the x-axis is the total number across all GPUs . Each GPU gets 1/8th of this value. As seen in Figure 12, FlashMoE maintains low, uniform latency, as desired, even as the number of experts grows from 8 to 128. In contrast, baselines exhibit superlinear latency increases due to increased kernel launch overheads. FlashMoE outperforms these baselines by up to 4 X at 4 H100s and 6.6 X at 8 H100s, both at 128 experts. FlashMoE 's payload-efficient communication and scheduler-driven in-kernel dispatching allow it to sustain expert parallelism without incurring the communication and orchestration penalties seen in other systems. These results reinforce FlashMoE 's scalability for ultra-sparse MoE configurations.

5 Limitations and Future Work

Engineering complexity. Fully fused, persistent kernels demand deep GPU + distributed-systems expertise; future work may investigate compiler/DSL abstractions to lower this barrier.

FP16 inefficiency. Our FP16 path is suboptimal (§H) due to insufficient tuning. We anticipate addressing this gap with autotuned GEMM operators like cuBLASDx [35] or CUTLASS builders.

Training support. This work targets inference; enabling training will require fusing backward computation and gradient communication with new bookkeeping and task descriptors.

6 Conclusion

We introduce FlashMoE, the first work to fuse the entire Distributed MoE operator into a single persistent GPU kernel that unifies computation, communication, and scheduling via actor-style concurrency, warp specialization, and async (R)DMA. We address two dominant bottlenecks in prior systems-CPU-managed synchronous communication and fragmented multi-kernel execution. Empirically, FlashMoE achieves up to 6× speedup, 9× higher GPU utilization, and 5.7× throughput for distributed MoE. Looking ahead, we see a shift from CPU orchestration to fully autonomous, GPU-native pipelines-extending this fusion approach to training and beyond.

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A Supplementary Motivation

B

B

GPU 1

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Gate

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combine

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(4)

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C

In Figure 14, we present empirical cumulative and raw distributions of AlltoAll kernel runtime from distributed training of a 1.3B GPT-3 MoE model across 32 A100 and 8 V100 GPUs. We use this result to motivate the severity and prevalence of straggler effects. In Figure 14b, we observe P95 communication performance degradation of 1.32X when compared to the mean actual kernel time. This performance reduction is rather tame as the underlying hardware is a supercomputer well-tuned against 'software jitter' [36]. However, we observe a more severe p95 performance loss of 11X in a single-node Virtual Machine (VM). In line with prior HPC works [37, 38], we argue that obviating the inherent barrier in this synchronous collective communication would allow GPUs to repurpose this observed idle time for downstream computation as depicted in Figure 13.

B Related Work

Computation-Communication Overlap and Kernel Fusion. To reduce the communication overheads of synchronization in distributed DNN training, many research efforts have been focused on increasing the overlap of computation and communication. For generic Transformer-based models without MoE layers, many works [39-47] have provided insights and techniques to partition and schedule computation and communication operations, aimed at finer-grained overlapping. To address the challenges posed by AlltoAll communication and expert parallelism in MoE training, Tutel [48]

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= 0.28ms

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GPT-3 MoE 32x1.3B All-to-All Straggler Effect: 8x4 A100

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avg actual =  1.99ms

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GPT-3 MoE 8x350M All-to-All Straggler Effect: 1x8 V100

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GPT-3 MoE 8x350M All-to-All Straggler Effect: 1x8 V100

(d) Raw Distribution

and FasterMoE [14] overlap AlltoAll with expert computation. Lancet [49] additionally enables both non-MoE computation in forward pass and weight gradient computation in backward pass to be overlapped with AlltoAll . Despite overlapping, the performance of these approaches is limited in practice due to blocking synchronous collective communication with barriers. In contrast, FlashMoE fundamentally eliminates these inefficiencies with asynchronous, device-initiated data transfers overlapped with tiled computation all within a single kernel . FlashMoE further differentiates itself from SOTA works like COMET [12] and DeepEP [1], which also use this form of kernel-initiated communication but at a coarse-grained granularity and without complete kernel fusion.

C Proof of Theorem 3.1

We begin with two necessary definitions vital to the proof.

Definition C.1. Define a write as w ( p s , p t , i ) , where p s is the source process and i is an ordered tuple indicating the index coordinates for L residing on the target process p t . A write-write conflict occurs when there exist at least two distinct, un-synchronized, concurrent writes w 1 ( p s 1 , p t 1 , i 1 ) and w 2 ( p s 2 , p t 2 , i 2 ) , such that p t 1 = p t 2 and index coordinates i 1 = i 2 but p s 1 = p s 2

̸

Definition C.2. For any source process p s , a valid index coordinate i = ( p ∗ , r, b, e, c ) satisfies the following:

For inter-device writes, it must hold that p ∗ = p s and b = 1 . Note this also applies to self-looping writes w ( p t , p t , i ) .

For any write w ( p s , p t , i ) , if b = 0 , then p s = p t . This rule describes intra-device staging writes.

We restate Theorem 3.1 and outline its proof below.

Theorem C.1. The symmetric tensor layout L is write-write conflict-free.

Proof. As is the case for typical physical implementations, assume that each index coordinate i maps to a distinct memory segment in L . Next, we show by contradiction that no write-write conflicts can exist when accessing L using valid i . For simplicity, we only include the index coordinates when describing a write. Assume that there exist at least two writes w 1 ( p s 1 , p t 1 , i 1 ) , w 2 ( p s 2 , p t 2 , i 2 ) with p t 1 = p t 2 and valid destination coordinates i 1 , i 2 , where i 1 = i 2 lexicographically and both are unpacked below.

Note that intra-process writes always have distinct c j coordinates, where j ∈ { 0 , C -1 } . For inter-process transfers, we have two cases.

Case 1: p s 1 = p s 2

̸

Here, w 1 and w 2 are identical operations. This contradicts the definition of a conflict, which requires that p s 1 = p s 2 . In practice, such repeat writes never even occur.

̸

Case 2: p s 1 = p s 2

̸

To ensure validity for i 1 and i 2 , it is the case that p 1 = p s 1 and p 2 = p s 2 . However, this implies that i 1 = i 2 yielding a contradiction as desired.

D Memory Overhead

We measure the GPU memory required for the symmetric tensor L and runtime bookkeeping state of FlashMoE. The memory overhead primarily depends on the tile size, expert capacity ( EC ), and the number of experts ( E ). Table 3 summarizes the memory overhead across recent MoE models [50-55] during inference, showing that FlashMoE maintains a modest and predictable memory footprint. In particular, the symmetric tensor ( ST ) accounts for at most 2.15% additional memory relative to the total inference memory requirements.

E Task Implementation

F Actors

F.1 Processor

F.2 Scheduler

Algorithm 3: Scheduler Actor : executed by one warp

F.3 Subscriber

G Implementation

H FP16 Memory Throughput

2.81 M Inst

2.08MReg

40.29 KB

2.54 K Req

2.54 K Reg

3.46 GB

L2Cache

160.59 MB

532.13MB

203.34 MB

8000

51.47 M Inst

11.00 G8

1.00 B

2 C

53.66 M Inst

52.51 M Req

0.00

1,15 M Req

MemoryChart

721.40 K Req

2.75 M Inst

1.97 M Req

108.67KB

6.91 KReqg

6.82 K Req

6.58 G8

258.01MB

H

3.58GB

2.88 GB

106.00 MB

51.47 M Inst

Store Shared

L2C

28.46 M Inst

27.25 M Req

Roao

1.22 M Ret

Peer reviews:
{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper introduces FlashDMoE, a novel distributed MoE operator that fuses computation and communication into a single persistent GPU kernel. The work is motivated by the growing inefficiencies in conventional MoE models where distributed experts incur high communication overheads due to frequent kernel launches and synchronous communication operations. The paper addresses the challenges by employing device-initiated asynchronous communication, fine-grained tile-level parallelism, and an actor-based scheduling model, resulting in significant speedups (up to 15×) over existing state-of-the-art MoE implementations.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths:\n\n1. The approach introduces a single persistent GPU kernel that fuses all computation and communication tasks. It successfully eliminates repeated kernel launch overhead and reduces idle time on GPUs. It achieves higher GPU utilization and demonstrably faster execution compared to multiple short-lived kernel launches in existing systems.\n\n2. The proposed method leverages device-initiated asynchronous communication to mitigate the straggler problem. It efficiently routes only active tokens to the GPUs hosting the relevant experts. It minimizes excessive data transfer by implementing payload-efficient communication.\n\n3. The design employs fine-grained tile-level parallelism and an actor-based concurrency model. It effectively partitions the workload into small, independent tasks that can be dynamically scheduled across GPU warps. It optimizes the balance between computation and administrative tasks for better overall performance.\n\n4. The experimental evaluations demonstrate strong performance improvements across multiple dimensions. It shows substantial speedups when scaling tokens, experts, and GPUs compared to existing MoE implementations. It substantiates the claims with detailed profiling and comparative analyses.\n\n\nWeaknesses:\n\n\n1. The current implementation targets FP32 precision exclusively. It does not explore or support lower-precision arithmetic such as FP16 or mixed precision, which are common in modern deep learning deployments. This limitation may impact its applicability and performance in production-scale environments where lower precision is preferred.\n\n2. While optimizing the efficiency of MoE at the CUDA level is helpful and practical, from the system perspective, the contribution of kernel fusion is relatively weak. A simple kernel fusion is trivial and might be not enough for NeurIPS.\n\nQUESTIONS:\nSee weaknesses.\n\nLIMITATIONS:\nYes.", "TITLE": "Official Review", "RECOMMENDATION": 3, "REVIEWER_CONFIDENCE": 4, "CLARITY": 3, "IMPACT": 2, "ORIGINALITY": 3, "DATE": "2025-06-01"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper introduces FlashDMoE, a system designed to accelerate the execution of distributed Mixture-of-Experts (MoE) layers in large language models. \n\nThe work identifies two bottlenecks in existing MoE implementations: communication and kernel launch overheads.   \n\nTo solve these problems, the authors propose FlashDMoE, an MoE operator architected as a single persistent GPU kernel. Instead of relying on the CPU to launch a sequence of kernels, FlashDMoE launches a monolithic kernel that remains active throughout the entire MoE operation, managing all internal tasks directly on the GPU to eliminate kernel launch overhead by design, reducing the number of required GPU operations from hundreds to one.   \n\nThe core mechanisms of FlashDMoE are threefold:\n\n1. Actor-Based Concurrency\n2. Asynchronous, Device-Initiated Communication\n3. Payload-Efficient Data Transfer\n\nThe authors present a comprehensive evaluation of multi-GPU servers equipped with NVIDIA H100s. The results demonstrate that FlashDMoE achieves speedups ranging from 1.2x to 15x over state-of-the-art baselines. Furthermore, the system achieves over 90% Streaming Multiprocessor (SM) utilization, showcasing its effectiveness at eliminating GPU idle time.\n\nSTRENGTHS AND WEAKNESSES:\nStrength:\n\n1. The idea is intuitive and addresses bottlenecks in traditional LLM kernels.\n2. The experiments show good latency hiding and resource utilization results.\n\nWeakness\n\n1. While the idea of a monolithic kernel is new, the core techniques are not. The idea of integrating communication and computation tasks within fused GPU kernels and thread block specialization is well-studied and are in one of the baselines, Comet, that the authors compare with. Other than pushing the idea to a single kernel, which comes with its drawbacks of less flexibility, it is not clear what the additional challenges are.\n\n2. It's not clear how the additional activation buffer would affect per-device batch size in a larger-scale scenario. If this extra memory requirement causes higher GPU requirements, then a more detailed analysis of the efficiency-memory tradeoff is needed.\n\n3. FP32 is a suboptimal setup for both inference and training. \n\n4. It's not clear how much additional effort is required to support more diverse expert routing algorithms.\n\nMinor typos:\n\n1. Extra comma in line 43.\n2. Incomplete/fragmented sentence in line 138.\n3. Duplicated sentence in line 205.\n\nQUESTIONS:\nPlease see above.\n\nLIMITATIONS:\nYes.", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 4, "CLARITY": 4, "IMPACT": 4, "ORIGINALITY": 3, "DATE": "2025-06-22"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nAlthough MoE models are efficient because they only activate a few experts at a time, spreading experts across many GPUs causes heavy communication and frequent GPU launches, especially due to ALLTOALL operations. To solve this, FlashDMoE combines all computing and communication steps into one long-running GPU kernel, removing the need for CPU control.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths:\n* It achieves significant speedups, with 1.2X-15X speedup over state-of-the-art MoE implementations in evaluations on multiple ML servers each with 8 NVIDIA H100 GPUs, and 3−10× improvement in forward pass latency on a single node with 8 NVlink-ed H100 GPUs compared to existing MoE systems.\n* It eliminates repeated kernel launches, launching only one persistent kernel during a single forward pass, while baselines launch up to 550 short-lived kernels, thus reducing kernel launch overheads significantly.\n* It mitigates the impact of communication stragglers through fine-grained, tile-level parallelism within the kernel, addressing the long-tail latency issue of synchronous ALLTOALL communication.\n* It improves payload efficiency by introducing in-place padding and symmetric tensor layouts, transmitting only active tokens, and reducing unnecessary data transfers, which leads to better runtime performance.\n\nWeaknesses:\n* FlashDMoE is currently only evaluated on a single node with 8 GPUs connected via NVLink. Its performance on multi-node systems, especially over slower interconnects like InfiniBand, is not yet tested.\n* To enable non-blocking communication, FlashDMoE over-provisions memory using a 4× symmetric tensor layout, which increases memory consumption compared to some other MoE implementations.\n* The system is benchmarked on synthetic workloads and toy MoE layers, without integration into full-scale production models like LLaMA or GPT. Thus, the practical benefit of end-to-end training/inference remains to be validated.\n\nQUESTIONS:\nHave you trained an MoE model to compare the stability, throughput, and loss of FlashDMoE and Megatron during actual training?\n\nLIMITATIONS:\nyes", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 2, "CLARITY": 3, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-02"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper proposed FlashDMoE, a fully fused MoE operator that runs as a single GPU kernel. It integrates all compute and communication tasks directly on the GPU, bypassing the need for multiple kernel launches and improving GPU utilization. The innovative of this paper include 1. replacing hundreds of short-lived GPU kernels with one long-lived kernel; 2. breaking work into tiles processed in parallel across GPU threads; 3. communicating only with GPUs hosting selected experts. The experiment result shows it achieves 1.2× to 15× faster performance compared to SOTA method like DeepEP, Megatron-LM, FasterMoE, and Comet.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths:\n1. Novel Single-Kernel Design: FlashDMoE introduces a unified, persistent GPU kernel that eliminates host-side kernel launch overhead.\n2. Deep Systems Innovation: The paper presents a well-engineered actor-based GPU execution model with tile-level parallelism and efficient memory management.\n3. Substantial Performance Gains: The approach achieves 1.2× to 15× speedup over existing MoE systems and significantly improves GPU utilization.\n\nWeaknesses:\n1. Lack of Open Source and Flexibility: The code is not open-sourced, and adapting the implementation to new MoE architectures or shapes may be complex.\n2. Limited Evaluation Scope: All experiments are conducted on a single-node, 8-GPU system, with no multi-node benchmarks.\n3. Missing Baseline Comparisons: The paper does not compare against other recent expert-parallel fusion methods, such as [Optimizing Distributed ML Communication with Fused Computation-Collective Operations](https://arxiv.org/html/2305.06942v2).\n\nQUESTIONS:\n1. How difficult would it be to adapt FlashDMoE to support other MoE routing strategies, such as top-k routing with dynamic capacity?\n2. How easily can FlashDMoE be integrated into popular frameworks like Transformers or PyTorch?\n3. Do you plan to open-source the implementation? If so, will it include utilities for configuring different model shape and architecture?\n\nLIMITATIONS:\nPlease refer to weakness and questions.", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 3, "CLARITY": 2, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-03"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper introduces FlashDMoE, a novel system for executing the Mixture-of-Experts (MoE) layer in distributed deep learning environments. The authors identify two critical performance bottlenecks in existing MoE implementations: (1) high communication overhead and straggler sensitivity from synchronous \"ALLTOALL\" collectives, and (2) significant latency from the host CPU launching hundreds of individual GPU kernels.\n\nTo address these issues, the authors propose a paradigm shift: fusing the entire MoE operator—including gating, expert computation, and inter-GPU communication—into a single, persistent GPU kernel. This design eliminates kernel launch overhead and enables fine-grained, asynchronous execution. The core technical contributions are:\n\n1. An actor-based concurrency model within the kernel, where GPU warps are specialized into roles (Processor, Scheduler, Subscriber) to manage tasks.\n2. A device-initiated asynchronous communication protocol built on a novel symmetric tensor layout. This layout overprovisions memory to create a partitioned global address space (PGAS), enabling non-blocking data transfers without synchronization penalties.\n\nPayload-efficient communication via \"in-place padding\", which avoids transmitting zero-padded tokens across the network.\n\nThe authors evaluate FlashDMoE on an 8x H100 GPU server, demonstrating significant forward-pass latency speedups of 1.2x to 15x over state-of-the-art systems like DeepEP, Comet, and Megatron-LM.\n\nSTRENGTHS AND WEAKNESSES:\nS1. The concept of a fully fused, single-kernel MoE operator is a radical and elegant departure from conventional approaches. It fundamentally rethinks the execution model to eliminate well-known bottlenecks at their source, rather than merely optimizing around them. If this approach proves generalizable, it could influence the design of other complex communication-intensive operators in deep learning.\n\nS2. The experimental results are compelling. Achieving speedups of up to 15x and maintaining over 90% SM utilization is a testament to the effectiveness of the design. The system's ability to maintain near-constant latency when scaling the number of tokens (Figure 10a) is particularly noteworthy and highlights the success of the computation-communication overlap.\n\nS3. The symmetric tensor layout is a intuitive and insightful solution to the challenge of asynchronous, one-sided communication. Trading a predictable amount of memory for the complete removal of synchronization barriers is a powerful and well-justified engineering decision. The actor model provides a clean abstraction for managing the complex interactions within the fused kernel.\n\nS4. The authors conduct a comprehensive evaluation against multiple strong baselines. The experiments are well-designed to isolate performance across different scaling dimensions (tokens, experts, GPUs). The inclusion of micro-benchmarks that analyze GPU utilization (Fig 12a) and payload efficiency (Fig 12b) provides clear evidence for why the system is faster, strengthening the paper's claims.\n\nW1.The primary concern is the 4x memory overhead required for the token buffer to enable the symmetric tensor layout. The authors describe this as \"modest,\" but for models with very large sequence lengths or on memory-constrained hardware, this could be a prohibitive cost. The paper would benefit from a more detailed analysis of this trade-off, perhaps identifying the point at which this memory cost outweighs the performance benefits.\n\nW2. The claims of the paper are based entirely on a single-node, multi-GPU setup with high-bandwidth NVLink interconnect. The most challenging ALLTOALL bottlenecks and straggler effects often manifest in multi-node clusters connected over lower-bandwidth networks like InfiniBand. Without multi-node results, the paper's claims about scalability and straggler mitigation remain partially unsubstantiated. This is the most significant gap in the current evaluation.\n\nW3. The implementation is restricted to FP32 precision. Modern LLM inference and training workflows heavily rely on lower-precision formats (FP16, BF16, FP8) for performance and memory efficiency. This limitation currently makes FlashDMoE impractical for many state-of-the-art models.\n\nW4. The system is a highly specialized, low-level implementation (6,800+ lines of CUDA/C++). This presents a potential barrier to adoption and maintenance compared to solutions built on standard, well-documented libraries like NCCL. While not a flaw in the research, it's a practical consideration worth acknowledging.\n\nQUESTIONS:\nQ1. How sensitive is the performance of the symmetric tensor layout to the number of communication rounds ($\\tau$)? The paper states $2\\cdot\\tau$=4 for MoE, but how would the design and its memory overhead adapt to more complex computational graphs with more communication steps?\n\nQ2. The actor model dedicates one warp to the Scheduler role. Have you observed this scheduler becoming a bottleneck in any configuration, particularly with a very high number of experts or small tile sizes, leading to a high rate of task dispatching?\n\nQ3. The evaluation focuses exclusively on the forward pass for inference. Have you considered the implications of this design for the backward pass in a training scenario? Or, you can modify the architecture in a training-free manner? How would the actor model and communication scheme handle the additional complexities of gradient computation and accumulation?\n\nLIMITATIONS:\nN/A", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 3, "CLARITY": 3, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-03"}