Title: SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning
Venue: NeurIPS 2025
Accepted: yes
Keywords: RTL Optimization

Neuron-Symbolic

Electronic Design Automation
Abstract: Optimizing Register Transfer Level (RTL) code is crucial for improving the efficiency and performance of digital circuits in the early stages of synthesis. Manual rewriting, guided by synthesis feedback, can yield high-quality results but is time-consuming and error-prone. Most existing compiler-based approaches have difficulty handling complex design constraints. Large Language Model (LLM)-based methods have emerged as a promising alternative to address these challenges. However, LLM-based approaches often face difficulties in ensuring alignment between the generated code and the provided prompts. This paper introduces SymRTLO, a neuron-symbolic framework that integrates LLMs with symbolic reasoning for the efficient and effective optimization of RTL code. Our method incorporates a retrieval-augmented system of optimization rules and Abstract Syntax Tree (AST)-based templates, enabling LLM-based rewriting that maintains syntactic correctness while minimizing undesired circuit behaviors. A symbolic module is proposed for analyzing and optimizing finite state machine (FSM) logic, allowing fine-grained state merging and partial specification handling beyond the scope of pattern-based compilers. Furthermore, a fast verification pipeline, combining formal equivalence checks with test-driven validation, further reduces the complexity of verification. Experiments on the RTL-Rewriter benchmark with Synopsys Design Compiler and Yosys show that SymRTLO improves power, performance, and area (PPA) by up to 43.9%, 62.5%, and 51.1%, respectively, compared to the state-of-the-art methods. We will release the code as open source upon the paper's acceptance.

SymRTLO : Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning

Abstract

Optimizing Register Transfer Level (RTL) code is crucial for improving the efficiency and performance of digital circuits in the early stages of synthesis. Manual rewriting, guided by synthesis feedback, can yield high-quality results but is time-consuming and error-prone. Most existing compiler-based approaches have difficulty handling complex design constraints. Large Language Model (LLM)-based methods have emerged as a promising alternative to address these challenges. However, LLM-based approaches often face difficulties in ensuring alignment between the generated code and the provided prompts. This paper introduces SymRTLO, a neuron-symbolic framework that integrates LLMs with symbolic reasoning for the efficient and effective optimization of RTL code. Our method incorporates a retrieval-augmented system of optimization rules and Abstract Syntax Tree (AST)-based templates, enabling LLM-based rewriting that maintains syntactic correctness while minimizing undesired circuit behaviors. A symbolic module is proposed for analyzing and optimizing finite state machine (FSM) logic, allowing fine-grained state merging and partial specification handling beyond the scope of pattern-based compilers. Furthermore, an efficient verification pipeline, combining formal equivalence checks with test-driven validation, further reduces the complexity of verification. Experiments on the RTL-Rewriter benchmark with Synopsys Design Compiler and Yosys show that SymRTLO improves power, performance, and area (PPA) by up to 43.9%, 62.5%, and 51.1%, respectively, compared to the state-of-the-art methods. Our code is available at https://github.com/NellyW8/SymRTLO

1 Introduction

Register Transfer Level (RTL) optimization is a cornerstone of modern circuit design flows, serving as the foundation for achieving optimal Power, Performance, and Area (PPA). As the earliest phase in the hardware design lifecycle, RTL development provides engineers with the most significant degree of flexibility to explore design patterns, make architectural trade-offs, and influence the overall design quality [8]. Engineers use hardware description languages (HDLs) like Verilog to describe circuit functionality. At this stage, decisions made have far-reaching implications, as the quality of the RTL implementation directly impacts subsequent stages, including synthesis, placement, and routing [40]. A well-optimized RTL not only ensures better design outcomes but also prevents suboptimal designs from propagating through the flow, leading to significant inefficiencies and costly iterations [13, 49].

Despite its importance, RTL optimization remains a challenging and labor-intensive task. Engineers must iteratively refine their designs through multiple rounds of synthesis and layout feedback to ensure functionality and meet stringent PPA targets. This process becomes increasingly cumbersome as design complexity grows, with synthesis times scaling disproportionately, often taking hours or even days for a single iteration [13]. Consequently, designers frequently face numerous synthesis cycles to evaluate trade-offs and reach acceptable results. While modern electronic design automation (EDA) tools provide compiler-based methods to aid optimization, these approaches are inherently limited [46]. They rely heavily on predefined heuristics, making them ill-suited for adapting to unconventional design patterns, complex constraints, or dynamic optimization scenarios. As a result, the RTL optimization process demands significant expertise and effort.

Recent advances in artificial intelligence, particularly the advent of large language models (LLMs), have introduced a new paradigm for automating and optimizing RTL code [23, 25, 5, 1, 37, 15, 46, 14, 42, 41, 16, 26]. Leveraging the powerful generative capabilities of LLMs, researchers have demonstrated their potential to rewrite and optimize Verilog code automatically [46]. However, existing LLM-based approaches face critical challenges that limit their effectiveness. First, these models often fail to align their generated outputs with specified optimization objectives. The inherent limitations in logical reasoning within LLMs can lead to deviations from intended transformations, resulting in suboptimal or incorrect outputs. Second, despite their potential for automating code generation, current methods still heavily rely on traditional synthesis feedback loops for optimization. This reliance results in the inefficiencies of the synthesis process, failing to address the core issue of long design cycles.

Our Proposed Framework. To address the critical challenges in RTL optimization, we introduce SymRTLO , the first neuron-symbolic system that seamlessly integrates LLMs with symbolic reasoning to optimize RTL code. SymRTLO significantly reduces the reliance on repeated synthesis tool invocations and enhances the alignment of LLM-generated results with intended optimization rules.

Designing such a system introduces significant challenges, which we address through the integration of carefully designed modules. The first challenge lies in the generalization of optimization rules. Traditionally, optimization patterns are scattered across code samples, books, and informal notes, making it difficult for compiler-based methods to formalize or apply them effectively. SymRTLO tackles this by employing an LLM-based rule extraction system, combined with a retrieval-augmented generation (RAG) mechanism and a search engine. This ensures that optimization rules are not only generalized but also efficiently retrievable from a robust library built from diverse sources.

Another critical challenge is the alignment of LLM-generated RTL code with the intended transformations, as LLMs often struggle to produce outputs that strictly adhere to the specified optimization objective, leading to unreliable and unexplainable results. To ensure alignment, SymRTLO employs Abstract Syntax Tree (AST)-based templates, which guide the LLM to generate code that satisfies syntactic and semantic correctness. For complex control flows or edge cases that exceed the capabilities of AST templates, the framework utilizes a symbolic generation module, designed to handle such scenarios dynamically while maintaining optimization quality.

In addition to alignment, conflicts often arise when different design patterns are required to meet distinct PPA goals. To address this, SymRTLO introduces a goal-oriented approach, where each optimization rule is explicitly tied to its intended objective. This enables selective application based on user-defined optimization goals, efficiently balancing these conflicts to deliver optimized designs without disproportionately compromising PPA metrics.

Verification in traditional RTL workflows demands significant manual effort for test case development. To address this, SymRTLO integrates an automated test case generator, streamlining verification while ensuring functional correctness.

Our key contributions are summarized as follows:

LLM Symbolic Optimization: SymRTLO , the first framework to combine LLM-based rewriting with symbolic reasoning for RTL optimization.

Data Path and Control Path Optimization: SymRTLO addresses critical challenges in both traditional EDA compilers and purely LLM-based approaches, particularly by aligning generated code with FSM and data path algorithms, balancing conflicting optimization rules, and improving explainability.

PPA Improvements: SymRTLO demonstrates its efficacy on industrial-scale and benchmark circuits, surpassing manual coding, classical compiler flows ( e.g., Synopsys DC Compiler), and state-of-the-art LLM-based methods, achieving up to 43.9%, 62.5%, and 51.1% improvements in power, delay, and area.

2 Background and Motivation

LLMs have emerged as powerful tools for RTL design automation, with various approaches being developed since 2023. As summarized in Table 1, these approaches fall into three primary categories: RTL code generation [23, 25, 5, 1], debugging [37, 15], and optimization [46]. This growing body of research demonstrates the significant potential of LLMs to improve the efficiency and effectiveness of EDA workflows. However, RTL code optimization has always been a significant challenge in RTL design, even for human experts, as it has the greatest impact on the performance of downstream tasks.

Challenges in RTL Code Optimization with LLMs. Aligning generated code with intended optimization goals is a major challenge in LLM-based RTL optimization. Due to inherent randomness, LLMs often produce incomplete, incorrect, or suboptimal results. For example, RTLRewriter [46] employs retrieval-augmented prompts and iterative synthesis-feedback loops to enhance functional correctness but still struggles with fundamental misalignment between generated code and optimization objectives. Additionally, the need for multiple synthesis rounds significantly increases optimization time as design complexity increases, limiting the scalability of current LLM-based methods for large industrial-scale designs.

Current Approaches: Underutilization of Knowledge and Manual Verification.

Traditional RTL design optimization relies on established patterns such as subexpression elimination [31, 9], dead code elimination [20, 17], strength reduction [10], algebraic simplification [3, 4], Mux reduction [6, 43], and memory sharing [21, 27]. While these techniques are effective, these optimizations typically operate at the gatelevel netlist, making the relationship between optimized output and original RTL code less transparent. Additionally, optimization patterns from design manuals and codebases remain underutilized due to the lack of a centralized repository, forcing engineers to rely on their expertise rather than automated tools. Furthermore, verification

Table 1: Comparative analysis of LLM-based methods for RTL design. ✔ indicates the presence of the feature, ✘ indicates absence of the feature, and -indicates nonapplicable.

requires the creation of test benches and test cases manually, making the RTL design flow both time-consuming and error-prone.

Optimization Conflicts and Limited Compiler Capabilities. Existing compiler-based methods face additional challenges, particularly in managing optimization goal conflicts and handling complex patterns. For instance, optimizing for one metric, such as delay, often conflicts with another, such as power consumption. Striking the right balance between these competing objectives is crucial, especially as trade-offs between power and delay directly impact overall system performance. As shown in Table 2, each optimization method has its own specific goal, which often clashes with others. Compiler-based methods also lack the flexibility to adapt to such conflicts, limiting their effectiveness in optimizing designs with diverse and competing constraints.

Advancing LLM-based RTL Optimization with Neuron-Symbolic Integration. Recent research has shown a growing trend toward combining symbolic reasoning with LLM [45, 39, 7, 12, 11],

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bringing new inspirations for more efficient and reliable LLM-based RTL code optimization with better prompt-code alignment. These integrated approaches have seen broad application across various fields, from automated theorem proof and knowledge representation to robotics and medical diagnostics, demonstrating how the combination of pattern recognition and generative capabilities of LLM with the interpretability and logical rigor of symbolic systems can significantly improve the alignment between LLM output and the given prompt.

Motivation Experiments. To highlight the limitations of current LLM-based RTL optimization, we conduct an experiment using state-of-the-art commercial LLM, GPT-O1, to optimize an 11-state FSM design. The goal was to minimize and merge unnecessary states to enhance PPA metrics. GPT-O1 receives a detailed state reduction algorithm to guide the optimization process. We compare its results with an optimized design that directly applied the state reduction algorithm. As shown in Table 3, GPT-O1 struggles to align its outputs with the algorithm, resulting in an under-optimized FSM with little state reduction and degradation in PPA. Although GPT-O1 achieves some state reduction, it fails to consider switching activity minimization and efficient state encoding, resulting in poor code choices that increase Hamming distances between frequently transitioning states and generate more complex combinational logic [48]. In contrast, algorithm-driven optimization achieves significantly better results, highlighting current LLM limitations in complex RTL optimization tasks.

3 Methodology

SymRTLO takes a Verilog RTL module as input and optimizes it for specific design goals, such as low power, high performance, or reduced area. As illustrated in Figure 1, the workflow begins by entering the RTL code and the user-specified optimization goal ( 1 ) into the LLM Dispatcher ( 2 ). This dispatcher analyzes the input circuit and determines the appropriate optimization path: either proceeding solely with Data Flow Optimization (§3.2) or incorporating Control Flow Optimization (§3.3) as well, depending on the characteristics of the design. For Data Flow Optimization, a search engine with a retrieval-augmented module extracts optimization rules and constructs AST-based templates. For Control Flow Optimization, an LLM-driven symbolic system generator performs FSM-specific transformations. Finally, the Final Optimization Module (§3.4) integrates both paths and incorporates a verification system to ensure the functional correctness of the optimized design.

3.1 LLMDispatcher

The LLM Dispatcher ( 2 ) receives the input RTL code and the specified optimization goal ( e.g., low power) ( 1 ) before any optimization begins. It first summarizes the code and generates potential optimization suggestions. These suggestions are then passed to the Retrieval-Augmented Generation (RAG) system to identify the relevant optimization rules. Additionally, the Dispatcher evaluates the presence of a Finite State Machine (FSM) in the original code to determine whether control flow optimization is necessary.

3.2 Data Flow Optimization

Data Flow represents the process by which information is propagated, processed, and optimized within an RTL design. Effective data flow optimizations improve system efficiency by simplifying computations, reducing redundancy, and enhancing PPA metrics. Common techniques include sub-

expression elimination, constant folding, and resource sharing. The proposed Data Flow Optimization Module addresses three key challenges: (1) generalizing diverse optimization patterns into accurate, reusable rules; (2) aligning LLM-generated optimizations with functional and logical requirements; and (3) resolving conflicts between optimization goals inherent in distinct design patterns.

Optimization Rule Search Engine Optimization knowledge is often scattered across books, lecture notes, codebases, and design manuals, with no generalized repository to serve as a unified knowledge base. Furthermore, optimization patterns frequently conflict due to divergent goals, for example, power reduction versus performance improvement. To tackle these challenges, we developed a retrieval-augmented generation (RAG) system equipped with an optimization goal-based rule extraction module.

Optimization Library. The RAG system aggregates raw RTL optimization data from sources such as lecture notes, manuals, and example designs [38, 35, 32, 30] into a comprehensive knowledge base ( 3 ). LLMs then summarize and structure these data into an optimization library ( 4 ). Each rule is abstracted to include its description, applicable optimization goals ( e.g., area, power, or timing), and its category ( e.g., data flow, FSM, MUX, memory, or clock gating). A similarity engine identifies overlaps with existing entries, prompting merges or exclusive labels to ensure the scalability of the rule library. To align optimization goals with generated outputs, the rules specify detailed instructions for constructing AST templates, enabling precise application of optimization patterns. Rules with clearly defined requirements include template-writing guidelines, while more abstract rules are stored as descriptive text and used directly as optimization prompts. See Appendix C for an example RAG.

Enforcing Rule Alignment and Resolving Conflicts To improve the structure and alignment of optimization rules, the LLM Dispatcher ( 1 ) provides both a summary of the input RTL code and suggestions for potential optimizations. These inputs are passed to the search engine along with user-specified optimization goals, performing a similarity search to identify the most relevant rules from the RAG system.

Given the potential for conflicts between optimization goals, it is critical to prevent the inclusion of conflicting rules while ensuring no critical optimizations are overlooked. To achieve this balance, we employ the elbow method to analyze the similarity scores between the query and the candidate rules. This approach identifies a natural cutoff point where adding more rules no longer yields significant benefits. Let the similarity scores between the query and candidate rules be ordered as: s 1 ≥ s 2 ≥ · · · ≥ s M , where s i denotes the similarity score for i -th rule, ordered from highest to lowest, and M is the total number of candidates.

The optimal cutoff index i ∗ is determined by maximizing the difference between consecutive similarity scores: i ∗ = arg max 1 ≤ i<M , ( s i -s i +1 ) .

Rules with similarity scores above the threshold τ elbow are selected for application. The similarity between the query embedding ( e query) and the rule embedding ( e rule) is computed as shown below:

This method ensures that only the most relevant rules are selected, striking an optimal balance between comprehensiveness and precision. The output of the search engine contains two components: rules with detailed template-writing instructions ( 7 ) and abstract rules described only by their optimization properties ( 6 ).

AST Template Building To ensure that LLM-generated RTL code aligns with functional and logical optimization goals, we enforce rules using AST-based symbolic systems, which have been proven to be effective in hardware debugging [37]. Compared to LLM-generated symbolic systems, AST-based templates offer several advantages: (1) parsing Verilog into an AST ensures accurate and structured design representations; (2) limiting each template to a single optimization goal maintains conciseness, facilitating correct generation and application by LLMs; and (3) the modular approach allows selection of templates to balance conflicting optimization patterns, enhancing flexibility.

For rules that include template-writing instructions, we prompt the LLM to generate an AST-based template that serves as a general optimization framework ( 8 ). Let A denote the set of all AST

nodes in the Verilog design, and let the matching condition: Φ : A → { true , false } , determine whether a node qualifies for optimization. The process begins by identifying the Target Node Type , such as Always , Instance , Assign or Module Instantiation . For each node of the specified type, we apply Φ to decide whether it requires rewriting. Once the target nodes are identified, the Transformation Rule is applied as follows: τ : { a ∈ A | Φ( a ) = true } -→ A , where τ replaces the matched node with an optimized AST subtree ( e.g., merging nested if-else statements, folding constants, or simplifying expressions; code example see Appendix B). To ensure functional correctness, the transformed design undergoes an equivalence check using LLM-generated testbenches. If the template passes verification, it is stored in the RAG system as reusable content.

As shown in Figure 2, the RTL design is initially interpreted as an AST representation. The RAG system provides the LLM with multiple template options. Due to the varying optimization goals and scenarios, the system avoids relying on a fixed sequence of templates. Instead, the LLM determines which templates to apply and in what order, tailoring the optimization process to the design's specific requirements. To further prevent conflicts between templates or failures in the symbolic system, we introduce a feedback loop . This loop allows the LLM to re-select templates and adjust its strategy based on prior failures, ensuring robustness and adaptability.

3.3 Control Flow Optimization

Control Flow, unlike Data Flow's focus on how information is processed and propagated, defines the execution paths and sequencing of operations in RTL designs through finite-state machines (FSMs) that capture states, transitions, and outputs. These FSMs are tightly coupled with design constraints ( i.e., partial specifications, clock gating, and reset logic), making generic symbolic systems fragile or incomplete. Addressing these challenges requires deeper semantic analysis beyond simple pattern matching or generic AST templates. To enhance alignment between optimized code and the FSM minimization algorithm, we propose a Control Flow Optimization module utilizing an LLM-based symbolic system. An FSM can be formally represented as: M = ( Q, Σ , δ, q 0 , F ) , where Q is the finite set of states, Σ is the input alphabet, δ : Q × Σ → Q is the transition function, q 0 ∈ Q is the initial state, and F ⊆ Q is the set of accepting states.

For a partially specified FSM M p , the transition function is extended to handle non-deterministic transitions: δ p : Q × Σ → 2 Q , where 2 Q represents the power set of Q .

Classical minimization algorithms ( e.g., Hopcroft's [18] or Moore's [28]) are effective for completely specified FSMs but are limited by real-world complexities. Practical RTL designs often integrate control logic with data path constraints, and undefined states and transitions make FSM minimization an NP-complete problem with a general complexity of O (2 | Q | ) . A single pre-built AST script cannot efficiently handle all such incomplete specifications. Let ϕ : Q × D → B represent the data path constraints, where D is the data path state space and B is the boolean domain. Pure FSM-focused AST-based optimization scripts can overlook these data path side effects, failing to capture deeper control semantics.

Inspired by [19], we propose leveraging LLMs to transform each circuit into a symbolic representation focused solely on FSM components, i.e., isolating states, transitions, and relevant outputs, as illustrated in Figure 3. Instead of relying on a one-size-fits-all script, we prompt the LLM to dynamically generate a specialized minimization script tailored to the specific FSM structure and constraints. We show an example workflow in Appendix A.

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3.4 Verification and Final Optimization

To address the challenges of manual verification and unreliable automated methods, we introduce an automated verification module that integrates functionality testing and formal equivalence checking. After AST-based optimization and the LLM-assisted symbolic system generate initial results, the LLM combines extracted rules, template-optimized code, and symbolic outputs to produce the final optimized RTL design ( 11 ). Verification is essential to ensure correctness, as LLM-generated rewrites may introduce unintended behavioral deviations. We employ a two-step verification pipeline: (1) the LLM generates test benches to validate basic functional correctness, acting as a rapid filter to reject invalid rewrites early; and (2) for designs that pass initial tests, we perform formal equivalence checking to formally confirm functional equivalence to the original design. For combinational logic and straightforward synchronous sequential circuits, we apply standard Boolean Satisfiability Problem (SAT)-based equivalence checking. While more complex designs like asynchronous resets, CDC paths, or retimed logic, we employ advanced sequential equivalence checking with robust state matching and transformation-tolerant verification techniques.

4 Experiments

4.1 Experimental Setup

Baseline We compare SymRTLO with several state-of-the-art LLM and open source RTL optimization frameworks. The LLM baselines include GPT-O1, GPT-4o, GPT-4 [29], GPT-3.5[47], and GPT-4o-mini. Additionally, we include two specialized open-source LLM-based tools: Verigen [36] and RTL-Coder-Deepseek [25]. For a comprehensive evaluation, we analyze SymRTLO performance using circuits from the RTLRewriter Benchmark. Although the RTLRewriter environment is reproducible using Yosys [44] for wires and cells analysis, the exact test case they use is not provided. Moreover, comparing PPA results is even more challenging due to its reliance on Yosys + ABC [2]with unknown libraries. To demonstrate SymRTLO 's capabilities, we subject it to a broader evaluation scope, selecting examples that are diverse in size and functionality, while including cases reported in RTLRewriter's benchmark for direct comparison.

Implementations The SymRTLO framework takes GPT-4o as its primary LLM for optimization strategy selection, symbolic system generation, and iterative HDL synthesis, leveraging its robust inference, low inference cost, and coding capabilities. While the framework is model-agnostic by design, alternatives like GPT-3.5 and GPT-O1 were excluded after preliminary tests showed poor results-GPT-3.5 lacked sufficient coding capability, and GPT-O1 incurred high latency and API costs, reducing overall efficiency. Pyverilog [34] is used for AST extraction and code reconstruction.

To efficiently retrieve relevant transformation templates and knowledge, we integrate OpenAI's text embedding-3-small, which excels in embedding-based retrieval tasks. For hardware compilation and validation, we use a combination of open-source and commercial tools. Yosys measures wires and cells, while Synopsys DC Compiler 2019 [33], paired with the Synopsys Standard Cell (SSC) library, performs PPA analysis. GPT-4o generates test benches for functional coverage. Yosys + ABC serves as the logical equivalence checker, while Synopsys Formality for sequential equivalence checking. For a fair comparison with standard compiler workflows, we apply typical Synopsys DC Compiler optimizations, using medium mapping effort and incremental mapping to reflect common practices.

Evaluation Metrics First, to evaluate generation quality and functional correctness, we use the pass@k metric commonly employed in code generation tasks. This metric captures the probability that at least one valid solution exists within the top k generations: pass@k = 1 N ∑ N i =0 (1 -C k n i -c i C k n i ) , where N is the number of problems, n i and c i represent the total and correct samples for the i -th problem, respectively. Second, to test the performance of the synthesis results, we use the best results of the 10 valid generations of each model and our method. This sampling maintains token budget fairness, as SymRTLO with GPT-4o averages 7,728 tokens across all circuits, while the base GPT-4o model uses approximately 775 tokens per generation-a 10× difference.

For smaller benchmarks, we evaluate optimization results using Wires and Cells metrics, which reflect low-level physical characteristics of circuits. These metrics provide granular insights into routing complexity (wires) and logical component count (cells), offering a precise evaluation for isolated modules or blocks. For larger designs, we focus on PPA metrics to capture high-level efficiency and real-world applicability. These metrics offer a holistic view of resource usage and performance for complex designs, where low-level metrics like Wires and Cells become impractical.

4.2 Functional Correctness Analysis

To demonstrate that our method reduces synthesis time and improves functional correctness, Table 4 presents the evaluation results. SymRTLO achieves near-perfect first-attempt pass rates, ensuring valid, optimized RTL code with maintained functional equivalence. This significantly outperforms stateof-the-art language models, particularly given the complexity of RTL optimization tasks and the necessity of maintaining functional equivalence. SymRTLO

reduces synthesis iterations, minimizing redundant computations throughout the optimization process.

4.3 Circuit Optimization Performance

To demonstrate SymRTLO 's effectiveness in resolving cross-rule conflicts and achieving optimization objectives, we conduct an experiment presented in Figure 4. Given the limited benchmarks available for LLM-driven RTL design, we analyze our framework on RTLRewriter's benchmark, which primarily emphasizes area optimization, leaving minimal room for improvements in power and delay. To align with this limitation, we put area opti-

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mization as our primary goal. Despite these constraints, SymRTLO achieves substantial improvements, averaging 40.96% in power, 17.02% in delay, and 38.05% in area, while maintaining a balanced optimization across all three metrics, highlighting its versatility and robustness.

We present a comprehensive analysis of SymRTLO capabilities using 11 short-benchmark examples from RTLRewriter focusing on Wires and Cells optimization, along with 10 complex FSM and algorithm examples from both short and long benchmarks. This representative selection demonstrates SymRTLO 's scalability and effectiveness across diverse functional domains but also aligns with circuits reported in RTLRewriter's paper, enabling direct comparison with state-of-the-art results.

Smaller benchmarks requiring only 1-2 optimization patterns provide ideal test cases for LLM output alignment . Table 5 shows that SymRTLO consistently outperforms baseline implementations across various test cases. With wire and cell ratios of 0.63 and 0.67 respectively, it surpasses the state-of-theart values of 0.69 and 0.77. While models like GPT-4 excel in certain cases, they lack consistency across diverse optimization tasks.

In FSM PPA experiments, SymRTLO significantly outperforms existing approaches, particularly in relation to RTLRewriter, the state-of-the-art solution, achieving an improvement of up to 50.59%, 12.65%, 53.09% in power, time, and area, respectively. As shown in Table 6, it effectively aligns the FSM state reduction algorithm with optimized code, minimizing all FSM states and achieving the best overall PPA results. This demonstrates that the LLM-generated symbolic system is both stable and aligned with intended optimization goals.

To evaluate the effectiveness of generalized rules and AST templates in balancing conflicting rules, we conduct algorithm case PPA experiments involving complex Data Path and Control Path scenarios. As shown in Table 7, SymRTLO applies AST templates, optimized rules, and minimized FSM states, achieving 30.34%, 21.37%, and 20.01% improvements in PPA over GPT-4o, our base model, on average. Note that RTLRewriter's results are unavailable for comparison for these cases.

We test SymRTLO with Synopsys DC optimization workflows with medium mapping effort, incremental mapping for both FSM and Algorithm cases, as shown in Table 6 and Table 7, demonstrating further balanced optimization alongside compiler optimization processes, achieving overall improvements of 36.2% in power and 35.66% in area, with only an 8.3% increase in time as a trade-off. Even under more stringent compiler optimization settings of flattened mode with high mapping effort, SymRTLO still delivers overall improvements of 27.7% in area, 35.8% in power, and 0.5% in delay.

4.4 Ablation Studies

To assess the effectiveness of individual components in SymRTLO , we conduct ablation studies by systematically removing one component at a time from the complete SymRTLO framework. In the first setting, disabling the AST-based template generation ('Remove Template-Based Opt') forced the model to rely solely on abstract rule descriptions without structural guidance. In the second, removing the FSM symbolic optimization module ('Remove Symbolic Reasoning') limited the framework to dataflow-only optimization.

In the third, turning off the goal-based rule filtering ('Remove Goal-Based Search') allowed all retrieved rules to be applied regardless of potential conflicts. For each configuration, we measured average PPA improvements across all benchmarks relative to the original designs. Figure 5 summarizes these results, showing that all three components contribute significantly to SymRTLO 's overall performance. Removing any one of them results in substantial losses in optimization effectiveness, further emphasizing the necessity of their integration. By con-

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trast, GPT-4o alone achieves minimal improvements, underscoring the advantages of SymRTLO 's tailored framework.

5 Discussion

It is important to clarify that SymRTLO operates as a pre-synthesis optimizer that complements rather than replaces traditional synthesis tools. RTL logic synthesis (e.g., Synopsys Design Compiler) takes RTL hardware descriptions and converts them to optimized gate-level netlists through optimizations including Boolean logic simplification, constant propagation, technology mapping, gate sizing, and retiming. While synthesis tools can perform local optimizations and limited resource sharing, they generally preserve the fundamental RTL architecture and control flow structure-operating within the constraints of the original RTL specification.

In contrast, SymRTLO performs source-level code optimization that modifies the RTL before synthesis, enabling algorithmic transformations, architectural restructuring, dataflow modifications, FSM redesign, and pipeline adjustments that fundamentally alter the hardware implementation. By optimizing at the RTL source level, SymRTLO can explore a broader design space and make architectural decisions that are beyond the scope of gate-level synthesis tools, typically yielding larger PPA improvements than synthesis optimizations alone.

6 Limitations

While SymRTLO demonstrates significant improvements in RTL optimization, the framework's performance is fundamentally dependent on the underlying capabilities of the base LLM, which may limit its effectiveness on novel or highly specialized circuit patterns not well-represented in its training data. The optimization rule library, though comprehensive, requires ongoing maintenance and expansion to keep pace with evolving hardware design practices and emerging optimization techniques. Since final PPA evaluation relies on synthesis tools like Synopsys DC Compiler and Yosys, results may vary across different tool versions or technology libraries. Additionally, while the symbolic reasoning module effectively handles FSM optimization, the approach may face scalability challenges when applied to extremely large state machines or circuits with highly complex control flows that exceed current computational bounds for formal analysis.

7 Conclusion

We present SymRTLO , a neuron-symbolic framework that integrates LLM-based code rewriting and symbolic reasoning to optimize both data flow and control flow in RTL designs. SymRTLO generalizes optimization rules, aligns generated code with intended transformations, resolves conflicting optimization goals, and ensures reliable automated verification. By combining retrieval-augmented guidance with symbolic systems, SymRTLO automates complex structural rewrites while maintaining functional correctness. Extensive evaluations on industrial-scale designs demonstrate significant PPA gains over state-of-the-art solutions.

References

Jason Blocklove, Siddharth Garg, Ramesh Karri, and Hammond Pearce. Chip-chat: Challenges and opportunities in conversational hardware design. In 5th ACM/IEEE Workshop on Machine Learning for CAD, MLCAD . IEEE, 2023.

R. Brayton and A. Mishchenko. ABC: An academic industrial-strength verification tool. In Computer Aided Verification: 22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010. Proceedings 22 , pages 24-40. Springer, 2010.

Bruno Buchberger and Rüdiger Loos. Algebraic simplification. In Computer algebra: symbolic and algebraic computation , pages 11-43. Springer, 1982.

Jacques Carette. Understanding expression simplification. In Proceedings of the 2004 international symposium on Symbolic and algebraic computation , pages 72-79, 2004.

Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, and Xiaowei Li. Chipgpt: How far are we from natural language hardware design. abs/2305.14019, 2023.

Deming Chen and Jason Cong. Register binding and port assignment for multiplexer optimization. In Proceedings of the 2004 Asia and South Pacific Design Automation Conference , ASP-DAC '04, page 68-73. IEEE Press, 2004.

Sihan Chen, Zhuangzhuang Qian, Wingchun Siu, Xingcan Hu, Jiaqi Li, Shawn Li, Yuehan Qin, Tiankai Yang, Zhuo Xiao, Wanghao Ye, Yichi Zhang, Yushun Dong, and Yue Zhao. Pyod 2: A python library for outlier detection with llm-powered model selection. arXiv , 2412.12154, December 2024.

Pong P Chu. RTL hardware design using VHDL: coding for efficiency, portability, and scalability . John Wiley & Sons, 2006.

John Cocke. Global common subexpression elimination. In Proceedings of a symposium on Compiler Optimization , pages 20-24. ACM, 1970.

Keith D Cooper, L Taylor Simpson, and Christopher A Vick. Operator strength reduction. ACM Transactions on Programming Languages and Systems (TOPLAS) , 23(5):603-625, 2001.

Revathy Venkataramanan Deepa Tilwani and Amit P. Sheth. Neurosymbolic ai approach to attribution in large language models. arXiv , 2410.03726, September 2024. Paper under review.

Stefano Teso Diego Calanzone and Antonio Vergari. Logically consistent language models via neuro-symbolic integration. arXiv , 2409.13724, September 2024.

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, and Zhiyao Xie. Masterrtl: A pre-synthesis ppa estimation framework for any rtl design. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD) , pages 1-9, 2023.

Weimin Fu, Yiting Wang, Zelin Lu, Xiaolong Guo, and Gang Qu. Hada: Leveraging multisource data to train large language models for hardware security assertion generation. In 2025 ACM/IEEE 7th Symposium on Machine Learning for CAD (MLCAD) , pages 1-7, 2025.

Weimin Fu, Kaichen Yang, Raj Gautam Dutta, Xiaolong Guo, and Gang Qu. Llm4sechw: Leveraging domain-specific large language model for hardware debugging. In 2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST) , pages 1-6, 2023.

Ping Guo, Yiting Wang, Wanghao Ye, Yexiao He, Ziyao Wang, Xiaopeng Dai, Ang Li, and Qingfu Zhang. Evoverilog: Large langugage model assisted evolution of verilog code, 2025.

Rajiv Gupta, DA Benson, and Jesse Zhixi Fang. Path profile guided partial dead code elimination using predication. In Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques , pages 102-113. IEEE, 1997.

John E Hopcroft and Jeffrey D Ullman. Formal languages and their relation to automata . Addison-Wesley Longman Publishing Co., Inc., 1969.

Yi Hu, Haotong Yang, Zhouchen Lin, and Muhan Zhang. Code prompting: a neural symbolic method for complex reasoning in large language models, 2023.

Jens Knoop, Oliver Rüthing, and Bernhard Steffen. Partial dead code elimination. ACM Sigplan Notices , 29(6):147-158, 1994.

Charles Eric LaForest and J. Gregory Steffan. Efficient multi-ported memories for fpgas. In Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '10) , pages 41-50, Monterey, CA, USA, 2010. ACM.

P. Langley. Crafting papers on machine learning. In Pat Langley, editor, Proceedings of the 17th International Conference on Machine Learning (ICML 2000) , pages 1207-1216, Stanford, CA, 2000. Morgan Kaufmann.

Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, and Haoxing Ren. Chipnemo: Domain-adapted llms for chip design. CoRR , abs/2311.00176, 2023.

Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, and Haoxing Ren. Invited paper: Verilogeval: Evaluating large language models for verilog code generation. In IEEE/ACM International Conference on Computer Aided Design, ICCAD . IEEE, 2023.

Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, and Zhiyao Xie. Rtlcoder: Fully open-source and efficient llm-assisted rtl code generation technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2024.

Yiyi Lu, Hoi Ian Au, Junyao Zhang, Jingyu Pan, Yiting Wang, Ang Li, Jianyi Zhang, and Yiran Chen. Autoeda: Enabling eda flow automation through microservice-based llm agents, 2025.

Jiacheng Ma, Gefei Zuo, Kevin Loughlin, Xiaohe Cheng, Yanqiang Liu, Abel Mulugeta Eneyew, Zhengwei Qi, and Baris Kasikci. A hypervisor for shared-memory fpga platforms. In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems , pages 827-844, 2020.

Edward F Moore et al. Gedanken-experiments on sequential machines. Automata studies , 34:129-153, 1956.

OpenAI, Josh Achiam, Steven Adler, Sandhini Agarwal, , and many others. Gpt-4 technical report. arXiv , 2303.08774, March 2023.

Samir Palnitkar. Verilog HDL: a guide to digital design and synthesis , volume 1. Prentice Hall Professional, 2003.

R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, and Daniela Duracková. A new algorithm for elimination of common subexpressions. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , 18:58 - 68, 02 1999.

Jim Schultz. Optimizing the rtl design flow with real-time ppa analysis. Synopsys Silicon to Systems Blog , N/A, March 2023. Blog Post. URL: https://www.synopsys.com/blogs/silicon-tosystems/optimizing-rtl-design-flow-real-time-ppa-analysis/ (Accessed January 26, 2025).

Synopsys. Dc ultra for synthesis and test. https://www.synopsys.com/ implementation-and-signoff/rtl-synthesis-test/dc-ultra.html .

Shinya Takamaeda-Yamazaki. Pyverilog: A python-based hardware design processing toolkit for verilog hdl. In Applied Reconfigurable Computing , volume 9040 of Lecture Notes in Computer Science , pages 451-460. Springer International Publishing, Apr 2015.

Vaibbhav Taraate. Digital logic design using verilog . Springer, 2022.

Shailja Thakur, Baleegh Ahmad, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Ramesh Karri, and Siddharth Garg. Verigen: A large language model for verilog code generation. ACM Trans. Design Autom. Electr. Syst. , 2024.

Yunda Tsai, Mingjie Liu, and Haoxing Ren. Rtlfixer: Automatically fixing RTL syntax errors with large language model. In Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC . ACM, 2024.

Frank Vahid. Digital design with rtl design, vhdl, and verilog (2nd edition). John Wiley & Sons Inc , 2, January 2010. ISBN-13: 978-0470531082, 575 pages.

Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Sixu Li, Youbin Kim, Ananda Samajdar, Yingyan Celine Lin, Mohamed Ibrahim, Jan M. Rabaey, Tushar Krishna, and Arijit Raychowdhury. Towards efficient neuro-symbolic ai: From workload characterization to hardware architecture. arXiv , 2409.13153, September 2024. Published in IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI), 2024.

Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Tim Cheng. Electronic design automation: synthesis, verification, and test . Morgan Kaufmann, 2009.

Yiting Wang, Guoheng Sun, Wanghao Ye, Gang Qu, and Ang Li. Verireason: Reinforcement learning with testbench feedback for reasoning-enhanced verilog generation, 2025.

Yiting Wang, Wanghao Ye, Yexiao He, Yiran Chen, Gang Qu, and Ang Li. Mcp4eda: Llmpowered model context protocol rtl-to-gdsii automation with backend aware synthesis optimization, 2025.

Zicheng Wang, Hailong You, Jie Wang, Meihua Liu, Yu Su, and Yong Zhang. Optimization of multiplexer combination in rtl logic synthesis. In Proceedings of the 2023 International Symposium of Electronics Design Automation (ISEDA) , page N/A. IEEE, May 2023.

Clifford Wolf, Johann Glaser, and Johannes Kepler. Yosys-a free verilog synthesis suite. In Proceedings of the Forum on Specification and Design Languages (FDL) , 2013. Yosys is the first open-source Verilog synthesis suite supporting a wide range of synthesizable Verilog features.

Sen Yang, Xin Li, Leyang Cui, Lidong Bing, and Wai Lam. Neuro-symbolic integration brings causal and reliable reasoning proofs. arXiv , 2311.09802, November 2023. Code available at this URL.

Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Chen Ran, Lei Chen, Mingxuan Yuan, Hong Xu, and Bei Yu. Rtlrewriter: Methodologies for large models aided rtl code optimization, 09 2024.

Junjie Ye, Xuanting Chen, Nuo Xu, Can Zu, Zekai Shao, Shichun Liu, Yuhan Cui, Zeyang Zhou, Chao Gong, Yang Shen, Jie Zhou, Siming Chen, Tao Gui, Qi Zhang, and Xuanjing Huang. A comprehensive capability analysis of gpt-3 and gpt-3.5 series models, 2023.

Lin Yuan, Gang Qu, Tiziano Villa, and Alberto Sangiovanni-Vincentelli. Fsm re-engineering and its application in low power state encoding. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference , ASP-DAC '05, page 254-259, New York, NY, USA, 2005. Association for Computing Machinery.

Haifeng Zhou, Zhenghui Lin, and Wei Cao. Research on vhdl rtl synthesis system. In Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002 , pages 99-103, 2002.

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A FSM Symbolic System

The following section demonstrates an example FSM in verilog. First the verilog is transformed to Symbolic Representation, then the Symbolic system applied minimization algorithm to optimize the FSM.

B AST Template

The following section demonstrate how applying AST templates transforms the code and apply optimization patterns.

C RAG Example

Peer reviews:
{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper presents SymRTLO, a neuro-symbolic framework that combines large language models (LLMs) with symbolic reasoning for optimizing Register Transfer Level (RTL) code. The key contributions include: (1) a retrieval-augmented system for extracting and applying optimization rules, (2) an AST-based template approach to maintain syntactic correctness, and (3) a symbolic module for finite state machine (FSM) optimization. The authors demonstrate improvements in power, performance, and area (PPA) over state-of-the-art methods, including both traditional compiler-based tools and LLM-driven approaches. The framework aims to reduce reliance on iterative synthesis feedback while improving alignment between optimization goals and generated RTL code.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths:\n- Integrating LLM into compilation is a promising direction to explore.\n- Introduced various new technologies into an old problem, e.g. LLM, RAG, symbolic reasoning etc.\n\nWeaknesses:\n- Many optimizations presented (e.g., dead code elimination, subexpression removal) are standard in existing EDA tools. The paper does not sufficiently justify why LLMs are needed for tasks that deterministic algorithms already solve reliably.\n- The RAG-based rule extraction (Appendix C) includes trivial optimizations (e.g., \"zero multiplication elimination\") that do not clearly benefit from LLM involvement. A stronger case should be made for where LLMs provide unique value beyond traditional methods.\n- The paper overlooks the reliability risks of introducing generative models into compilation. The paper claims a \"fast verification pipeline,\" but testbench generation is a long-standing complex problem that is not solvable in a paragraph of a NeurIPS paper. The current approach (LLM-generated test cases + equivalence checking) seems amateurish.\n\nQUESTIONS:\n- Can the authors clarify where LLMs provide unique advantages over traditional symbolic methods?\n- The completeness of LLM-generated testbenches (e.g., branch/state coverage)?\n- How false positives/negatives in equivalence checking are mitigated?\n- The RAG examples (Appendix C) include simplistic rules. Are there more complex, LLM-specific optimizations that traditional tools cannot easily replicate?\n- The paper acknowledges LLM reliability issues but relies on post-hoc verification. Are there safeguards during code generation (e.g., constrained decoding, symbolic grounding)?\n\nLIMITATIONS:\nyes", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 3, "CLARITY": 2, "IMPACT": 3, "ORIGINALITY": 2, "DATE": "2025-06-27"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper proposes SymRTLO, a neuro-symbolic framework integrating LLMs with symbolic reasoning for RTL code optimization. SymRTLO incorporates RAG-based system and AST-based templates, enabling LLM-based RTL optimization with an FSM-specific symbolic module. A fast verification pipeline is introduced to accelerate formal equivalence checks and test-driven validation. Experimental results show that compared with Synopsys DC and Yosys, SymRTLO achieves significant PPA improvements with up to 62.5% delay reduction.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths:\n1. Related work will be open-sourced upon acceptance, providing the community with an effective approach for RTL optimization using novel LLM- and RAG-based methods.\n2. Experimental results demonstrate improvements in power, performance, and area (PPA) by up to 43.9%, 62.5%, and 51.1% respectively, which shows significant performance gains.\n3. The idea of using RAG and AST to optimize RTL code is simple yet effective. It's happy to see the authors experimentally validate this approach.\n4. Integrating LLMs and FSMs for formal verification seems an interesting idea.\n\nWeaknesses:\n1. The checklist mentions limitations, but these are not actually covered in the paper or supplementary materials. The authors are encouraged to provide further discussion on these limitations.\n2. In experimental results such as Table 5, SymRTLO appears to exhibit no significant improvements over RTLrewriter. Moreover, this paper does not mention other LLM-based RTL generators, including RTL++ and similar approaches.\n3. The RAG-based rule extraction (Sec 3.2) lacks implementation details. What are the specific rules for pipelining? How are conflicting rules (e.g., pipelining vs. resource sharing in Table 2) resolved beyond similarity scores? I noticed the example in Sec App.C but I think it is not clear enough.\n4. No comparison with commercial tools (e.g. Cadence JasperGold) for formal verification efficiency.\n5. Minor formatting issues:​​ The spacing between figures, tables, and paragraphs appears insufficient, which may impact readability.\n\nQUESTIONS:\n1. Could you provide further discussion on limitations of SymRTLO?\n2. Could you provide additional experimental evidence demonstrating SymRTLO's superiority over existing LLM-based RTL generators, including RTLrewriter and RTL++?\n3. Could you provide further explanation on the implementation details of the RAG-based rule, such as pipelining?\n4. The $O(2^{|Q|})$ time complexity for FSMs seems high. Could you provide further discussion on the algorithm's scalability and complexity?\n5. Could you provide further comparison on SymRTLO with recent commercial tools, including Cadence JasperGold and Synopsys DC NXT or newer DC releases rather than DC 2019?\n6. The checklist mentions that this paper have the full set of assumptions and a complete proof. Could you explicitly locate all critical assumptions and proofs in the manuscript? Otherwise, the checklist statements should be revised accordingly.\n\nIf the authors address my concerns, I may raise my score accordingly.\n\nLIMITATIONS:\nAs mentioned before, the checklist mentions limitations, but these are not actually covered in the paper or supplementary materials. I think this paper has no potential negative societal impact.", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 4, "CLARITY": 2, "IMPACT": 2, "ORIGINALITY": 3, "DATE": "2025-06-27"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper presents SymRTLO, a neuron-symbolic framework for RTL code optimization. Specifically, SymRTLO uses a RAG mechanism with search engines to retrieve the optimization rules and employs AST-based templates for syntactic and semantic correctness guarantees. Experimental results show SymRTLO can achieve good PPA improvements on several benchmarks.\n\nSTRENGTHS AND WEAKNESSES:\n- Strength\n  - A comprehensive framework for RTL code optimization that combines LLM code generation and formal methods as symbolic complements.\n- Weakness\n  - The benchmark used in the experiment seems small. It is unclear how SymRTLO performs on large designs.\n  - No reasoning models (e.g., GPT-o4-mini, Gemini-2.5-Pro) are compared in the experiment. Such experiments would be instrumental in understanding how the state-of-the-art LLMs perform and whether this neuron-symbolic approach is indeed necessary.\n  - Several settings require additional clarification (as per the questions listed below).\n\nQUESTIONS:\n1. Table 2: How does SymRTLO resolve optimization conflicts? Why are compiler-based methods unable to adapt to such conflicts? Compilers always have tunable knobs for users to constrain the maximum hardware resources and the target objective.  How does SymRTLO or the LLM guarantee that these specified goals are met?\n2. Figure 1: What are the sources of the \"books, code, and manuals\"? Given the statement in L62, \"SymRTLO combined with a retrieval-augmented generation (RAG) mechanism and a search engine,\" how do these sources differ from the search-engine method? What is the criterion for deciding when to use RAG versus a search engine?\n3. Page 5: What if the query rules are not included in the candidate set?\n4. Page 5: \"$\\tau$ replaces the matched node with an optimized AST subtree\" Why is a node instead of a subgraph replaced with a subtree? For instance, in constant folding optimization, a series of arithmetic operations might be represented by multiple nodes.\n5. Page 6: How to combine dataflow and control flow optimization? Are they totally separate processes? It seems there is no interactive process for dataflow and control flow in Figure 1.\n6. Table 4: Pass@k only shows the final success rate, but how many attempts do LLMs require to obtain valid solutions?\n7. Figure 3: How is the correctness of the Verilog translation to symbolic representation guaranteed? Is this verification only performed in the final step of the process?\n8. Table 5: The benchmarks used seem pretty small in terms of wires and cells. Are there results available for larger benchmarks with more kernels?\n9. Table 6: What are the reasoning models' performance? It is highly recommended to include experimental results for models like GPT-4o-mini to provide a clear baseline for state-of-the-art models and quantify SymRTLO's benefits.\n10. Table 6: Please clarify whether \"Original\" in Table 6 refers to the RTLRewriter's result. Clearly define the baseline when discussing \"improvement\" in the table. How are the numerical values in the text (50.59%, 12.65%, 53.09%) derived, and how do they correspond to the numbers presented in the table?\n\nLIMITATIONS:\nSee above.", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 5, "CLARITY": 2, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-02"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThe authors propose an effective and efficient RTL code optimization framework, as SymRTLO, which integrates a LLM with a neuron- inspired symbolic reasoning module. The framework targets both data path and control path optimization, addressing limitations in traditional EDA compilers as well as purely LLM-based approaches. By leveraging RAG and AST-based templates, and alignment with FSM and data path algorithms, the approach introduces a novel and structured methodology. The proposed framework achieves significant improvements in PPAD metrics when benchmarked against SOTA methods.\n\nSTRENGTHS AND WEAKNESSES:\nStrength:\n1. The authors provide a thorough discussion of the existing challenges in RTL code optimization, addressing limitations in both traditional compilers and recent LLM-based approaches. This comprehensive background helps a broader audience understand the motivation behind the research and the rationale for the proposed methodology. Multi-variate optimization is a fundamental challenge in complex frameworks such as chip design flows, and the authors effectively articulate and formulate this challenge in the context of identifying an optimal solution.\n2. Again, methodology is clearly explained with substantial detail, using step identifiers (1,2,3...) as illustrated in Figure 1. to describe the proposed architecture. Sub-sections such as data flow optimization, control flow optimization,  AST template construction, rule alignment and conflict resolution are thoroughly detailed and well-articulated.\n3. Finally, experimental details and validation are well discussed and justified.\n\nLimitations:\nI have minor suggestions\n1. Ablation study representation w.r.t Figure 5 appears ambiguous, while the authors' intent is understandable, this section requires revisions (rewriting) for greater clarity. It is not clearly conveyed (..to me both in text and in figure) what the authors wanted to explain as \"We then analyze the impact of each removal across test cases, measuring the resulting overall PPA improvements compared to the base\"  . A more precise and correctly written explanation will be appreciated.\n2.  Please provide and discuss the limitation or breaking point of the proposed framework. Though author mentioned a separate section on this discussion, did not practically notice it. is this right? Can you please highlight if I missed anything?\n3. some typos can be noticed. like \"line number 205..........and the a rule embedding...\"\n\nQUESTIONS:\nQ1. How well does proposed approach generalize across ASIC and FPGA designs?\nQ2. Are the learned optimization rules transferrable across domains like DSP, control logic etc.?\nQ3. How do you handle edge cases where rule learning (knowledge) fails or contradicts hardware constraints?\n\nLIMITATIONS:\nThe authors mentioned an intention to discuss the limitations, but this is missing from the current version of the manuscript (best of my knowledge). The points raised under weaknesses and questions should help improving the technical merit of the manuscript.", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 5, "CLARITY": 3, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-16"}