Title: FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design
Venue: NeurIPS 2025
Accepted: yes
Keywords: Graph Neural Networks

Gradient-Based Reasoning

Analog and mm-Wave Circuit Design

Layout-Aware Optimization

Design Automation

Physics-Informed Machine Learning
Abstract: Designing analog circuits from performance specifications is a complex, multi-stage process encompassing topology selection, parameter inference, and layout feasibility. We introduce FALCON, a unified machine learning framework that enables fully automated, specification-driven analog circuit synthesis through topology selection and layout-constrained optimization. Given a target performance, FALCON first selects an appropriate circuit topology using a performance-driven classifier guided by human design heuristics. Next, it employs a custom, edge-centric graph neural network trained to map circuit topology and parameters to performance, enabling gradient-based parameter inference through the learned forward model. This inference is guided by a differentiable layout cost, derived from analytical equations capturing parasitic and frequency-dependent effects, and constrained by design rules. We train and evaluate FALCON on a large-scale custom dataset of 1M analog mm-wave circuits, generated and simulated using Cadence Spectre across 20 expert-designed topologies. Through this evaluation, FALCON demonstrates >99\% accuracy in topology inference, <10\% relative error in performance prediction, and efficient layout-aware design that completes in under 1 second per instance. Together, these results position FALCON as a practical and extensible foundation model for end-to-end analog circuit design automation.

FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design

Abstract

Designing analog circuits from performance specifications is a complex, multi-stage process encompassing topology selection, parameter inference, and layout feasibility. We introduce FALCON, a unified machine learning framework that enables fully automated, specification-driven analog circuit synthesis through topology selection and layout-constrained optimization. Given a target performance, FALCON first selects an appropriate circuit topology using a performance-driven classifier guided by human design heuristics. Next, it employs a custom, edge-centric graph neural network trained to map circuit topology and parameters to performance, enabling gradient-based parameter inference through the learned forward model. This inference is guided by a differentiable layout cost, derived from analytical equations capturing parasitic and frequency-dependent effects, and constrained by design rules. We train and evaluate FALCON on a large-scale custom dataset of 1M analog mm-wave circuits, generated and simulated using Cadence Spectre across 20 expert-designed topologies. Through this evaluation, FALCON demonstrates >99% accuracy in topology inference, <10% relative error in performance prediction, and efficient layout-aware design that completes in under 1 second per instance. Together, these results position FALCON as a practical and extensible foundation model for end-to-end analog circuit design automation. Our code and dataset are publicly available at https://github.com/AsalMehradfar/FALCON .

1 Introduction

Analog radio frequency (RF) and millimeter-wave (mm-wave) circuits are essential to modern electronics, powering critical applications in signal processing [1], wireless communication [2], sensing [3], radar [4], and wireless power transfer systems [5]. Despite their importance, the design of analog circuits remains largely manual, iterative, and dependent on expert heuristics [6-8]. This inefficiency stems from several challenges: a vast and continuous design space that is difficult to explore systematically; tightly coupled performance metrics (e.g. gain, noise, bandwidth, and power) that create complex trade-offs; and physical and layout-dependent interactions that complicate design decisions. As demand grows for customized, high-performance analog blocks, this slow, expert-driven design cycle has become a critical bottleneck. While machine learning (ML) has revolutionized digital design automation, analog and RF circuits still lack scalable frameworks for automating the full pipeline from specification to layout.

While recent ML approaches have made progress in analog circuit design, they typically target isolated sub-tasks such as topology generation or component sizing [9, 10] at the schematic level, without addressing the full synthesis pipeline. Many efforts assume fixed topologies [11-14], limiting adaptability to new specifications or circuit families. Optimization strategies often rely on black-box methods that do not scale well to large, continuous design spaces [15]. Some methods predict

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performance metrics directly from netlists [16], but do not support inverse design, i.e., generating circuit parameters from target specifications. Furthermore, layout awareness is typically handled as a separate post-processing step [17], missing the opportunity to guide optimization with layout constraints. Finally, many available benchmarks are built on symbolic or synthetic simulations [18], lacking the fidelity and realism of the process of commercial grade design flows. As a result, current ML pipelines do not allow fully generalizable, layout-aware, and end-to-end analog circuit design.

We propose FALCON (Fully Automated Layout-Constrained analOg circuit desigN), a scalable and modular machine learning framework for end-to-end analog and RF circuit design. Built on a dataset of over one million Cadence-simulated circuits, FALCON comprises three core components (Figure 1): (1) a lightweight multilayer perceptron (MLP) selects the most appropriate topology given a target performance specification; (2) a generalizable graph neural network (GNN) maps circuit topology and element-level parameters to performance metrics, operating on a native graph representation derived from Cadence netlists; and (3) gradient-based optimization over the forward GNN model recovers design parameters that meet the target specification, guided by a differentiable layout-aware loss that encodes parasitic effects and physical constraints. Notably, the GNN model in FALCON generalizes effectively to unseen topologies, enabling inverse design across diverse circuit families, even in low-data regimes, with optional fine-tuning for improved accuracy. By integrating layout modeling directly into the optimization process, FALCON unifies schematic and physical considerations within a single differentiable learning framework.

Our main contributions are as follows:

We construct a large-scale analog/RF circuit dataset comprising over one million Cadencesimulated datapoints across 20 expert-designed topologies and five circuit types.

We introduce a native netlist-to-graph representation that preserves both structural and parametric fidelity, enabling accurate learning over physical circuit topologies.

We design a generalizable GNN capable of accurate performance prediction and parameter inference across both seen and unseen topologies, with optional fine-tuning.

We develop a modular ML framework for end-to-end inverse design, incorporating performance-driven topology selection and layout-aware gradient-based optimization, with a differentiable loss that enforces area constraints, design-rule compliance, and frequencydependent modeling of passive components.

We show that FALCON enables fast, reliable inverse design under layout and physical constraints, generating high-quality circuits in under one second per instance on CPU.

2 Related Work

While recent ML-based approaches have advanced analog and RF circuit design, they typically target isolated stages of the design flow-such as topology generation, parameter sizing, or schematic-level performance prediction-without supporting unified, end-to-end synthesis. FALCON bridges this gap by jointly addressing aforementioned stages within a single framework.

Topology generation methods aim to select or synthesize candidate circuit structures [9, 19, 20], often using discrete optimization or generative models to explore the circuit graph space. However, these approaches typically target low-frequency or simplified designs [9] and may produce physically invalid or non-manufacturable topologies. In contrast, FALCON leverages a curated set of netlists, ensuring manufacturable validity and eliminating the need to rediscover fundamental circuit structures.

Parameter sizing and performance prediction have been explored through various learning paradigms. Reinforcement learning [10, 21] and Bayesian optimization [15, 22] optimize parameters via trial-and-error, often requiring large simulation budgets. Supervised learning methods [23, 24, 11] regress parameter values from performance targets under fixed topologies. Graph-based models [16] incorporate topology-aware representations to predict performance metrics from netlists. However, these approaches focus on forward prediction or black-box sizing and do not support inverse design across varied topologies. In contrast, FALCON unifies forward modeling and parameter inference in a single differentiable architecture that generalizes to unseen netlists.

Layout-aware sizing and parasitic modeling have been explored to mitigate schematic-to-layout mismatch. Parasitic-aware methods [25] integrate pre-trained parasitic estimators into Bayesian optimization loops for fixed schematics. While effective for estimation, these approaches rely on time-consuming black-box search and lack inverse design capabilities. Other methods, such as ALIGN [26] and LayoutCopilot [27], generate layouts from fully sized netlists using ML-based constraint extraction or scripted interactions, but assume fixed parameters and do not support cooptimization or differentiable inverse design. In contrast, FALCON embeds layout objectives directly into the learning loss, enabling joint optimization of sizing and layout without relying on external parasitic models. For mm-wave circuits, our layout-aware loss captures frequency-sensitive constraints via simplified models that implicitly reflect DRC rules, EM coupling, and performancecritical factors such as quality factor and self-resonance frequency.

Datasets for analog design are often limited to symbolic SPICE simulations or small-scale testbeds that do not reflect real-world design flows. AnalogGym [18] and AutoCkt [13] rely on synthetic circuits and symbolic simulators, lacking the process fidelity, noise characteristics, and layoutdependent behavior of foundry-calibrated flows. In contrast, FALCON is trained on a large-scale dataset constructed from over one million Cadence-simulated circuits across 20 topologies and five circuit categories, offering a substantially more realistic foundation for ML-driven analog design.

To the best of our knowledge, FALCON is the first framework to unify topology selection, parameter inference, and layout-aware optimization in a single end-to-end pipeline, validated at scale using industrial-grade Cadence simulations for mm-wave analog circuits. A qualitative comparison with representative prior work is provided in Appendix A.

3 A Large-Scale Dataset and Inverse Design Problem Formulation

3.1 Dataset Overview

We construct a large-scale dataset of analog and RF circuits simulated using industry-grade Cadence tools [28] with a 45nm CMOS process design kit (PDK). The dataset spans five widely used mm-wave circuit types for wireless applications [29, 30]: low-noise amplifiers (LNAs) [31-34], mixers [35-38], power amplifiers (PAs) [39-43], voltage amplifiers (V As) [44-48], and voltage-controlled oscillators (VCOs) [49-53]. Each circuit type is instantiated in four distinct topologies, resulting in a total of 20 expert-designed architectures.

For each topology, expert-designed schematics were implemented in Cadence Virtuoso, and key design parameters were manually identified based on their functional relevance. Parameter ranges were specified by domain experts and systematically swept using Cadence ADE XL, enabling parallelized Spectre simulations across the design space. For each configuration, performance metrics-such as gain, bandwidth, and oscillation frequency-were extracted and recorded. Each datapoint therefore includes the full parameter vector, the corresponding Cadence netlist, and the simulated performance metrics. The resulting dataset comprises over one million datapoints, capturing a wide range of circuit behaviors and design trade-offs across diverse topologies. This large-scale, high-fidelity dataset forms the foundation for training and evaluating our inverse design pipeline. Detailed metric definitions and per-topology parameter ranges appear in Appendix B.

3.2 Graph-Based Circuit Representation

To enable flexible and topology-agnostic learning, we represent each analog circuit as a graph extracted from its corresponding Cadence netlist. Nodes correspond to voltage nets (i.e., electrical connection points), and edges represent circuit elements such as transistors, resistors, capacitors, or sources. Multi-terminal devices-such as transistors and baluns-are decomposed into multiple

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edges, and multiple components may connect the same node pair, resulting in heterogeneous, multi-edged graphs that preserve structural and functional diversity.

Recent works such as DICE [54] have explored transistor-level circuit-to-graph conversions for self-supervised learning, highlighting the challenges of faithfully capturing device structure and connectivity. In contrast, our approach maintains a native representation aligned with foundrycompatible netlists. Rather than flattening or reinterpreting device abstractions, we preserve symbolic parameters, multi-edge connections, and device-specific edge decomposition directly from the schematic source, enabling scalable learning across diverse analog circuit families.

To support learning over such structured graphs, each edge is annotated with a rich set of attributes: (i) a categorical device type , specifying the component and connected terminal pair (e.g., NMOS drain-gate, resistor); (ii) numeric attributes , such as channel length or port resistance, fixed by the schematic; (iii) parametric attributes , defined symbolically in the netlist (e.g., W1 , R3 ) and resolved numerically during preprocessing; (iv) one-hot categorical features , such as source type (DC, AC, or none); and (v) computational attributes , such as diffusion areas ( Ad , As ) derived from sizing. This rule-based graph construction generalizes across circuit families without task-specific customization. Graphs in the FALCON dataset range from 4-40 nodes and 7-70 edges, reflecting the variability of practical analog designs. Figure 2 shows two representative graph examples from our dataset-IFVCO and ClassBPA.

3.3 Inverse Design Problem Definition

In analog and RF circuit design, the traditional modeling process involves selecting a topology T and parameter vector x , then evaluating circuit behavior via simulation to obtain performance metrics y = f ( T, x ) . This forward workflow depends heavily on designer intuition, manual tuning, and exhaustive parameter sweeps. Engineers typically simulate many candidate ( T, x ) pairs and select the one that best satisfies the target specification-a slow, costly, and unguided process.

In contrast, our goal is to perform inverse design : given a target performance specification y target , we aim to directly infer a topology and parameter configuration ( T, x ) such that f ( T, x ) ≈ y target , without enumerating the full design space. This inverse problem is ill-posed and the search space is constrained by both device-level rules and layout-aware objectives.

Formally, the task is to find the optimal topology T ∗ ∈ T and the optimal parameters x ∗ ∈ R p such that f ( T ∗ , x ∗ ) ≈ y target where f : T × R p → R d the true performance function implemented by expensive Cadence simulations. In practice, f is nonlinear and non-invertible, making direct inversion intractable. FALCON addresses this challenge through a modular, three-stage pipeline:

Stage 1: Topology Selection. We frame topology selection as a classification problem over a curated set of K candidate topologies { T 1 , . . . , T K } . Given a target specification y target, a lightweight MLP selects the topology T ∗ ∈ T most likely to satisfy it, reducing the need for exhaustive search.

Stage 2: Performance Prediction. Given a topology T and parameter vector x , we train a GNN f θ to predict the corresponding performance ˆ y = f θ ( T, x ) . This model emulates the forward behavior of the simulator f , learning a continuous approximation of circuit performance across both seen and unseen topologies. By capturing the topology-conditioned mapping from parameters to performance, f θ serves as a differentiable surrogate that enables gradient-based inference in the next stage.

Stage 3: Layout-Aware Gradient Reasoning. Given y target and a selected topology T ∗ , we infer a parameter vector x ∗ by minimizing a loss over the learned forward model f θ . Specifically, we solve:

where L perf measures prediction error, and L layout encodes differentiable layout-related constraints such as estimated area and soft design-rule penalties. Optimization is performed via gradient descent, allowing layout constraints to guide the search through a physically realistic parameter space.

4 Stage 1: Performance-Driven Topology Selection

Task Setup. We formulate topology selection as a supervised classification task over a fixed library of 20 expert-designed circuit topologies T = { T 1 , T 2 , . . . , T 20 } . Rather than generating netlists from scratch-which often leads to invalid or impractical circuits-we select from a vetted set of designer-verified topologies. This ensures that all candidates are functionally correct, layout-feasible, and manufacturable. While expanding the topology set requires retraining, our lightweight MLP classifier enables rapid updates, making the approach scalable. This formulation also aligns with practical design workflows, where quickly identifying a viable initial topology is critical.

Each datapoint is represented by a 16-dimensional performance vector of key analog/RF metrics 1 . We normalize features using z-scores computed from the training set. Missing metrics (e.g., oscillation frequency for amplifiers) are imputed with zeros, yielding zero-centered, fixed-length vectors that retain task-relevant variation. Dataset splits are stratified to preserve class balance across training, validation, and test sets. We assume each target vector is realizable by at least one topology in T , though the library can be extended with new designs.

Model Architecture and Training. We train a 5-layer MLP with hidden size 256 and ReLU activations for this problem. The model takes the normalized performance vector y target ∈ R 16 as input and outputs a probability distribution over 20 candidate topologies. The predicted topology is selected as T ∗ = arg max T k ∈T MLP ( y target ) k . We train the model using a cross-entropy loss and the Adam optimizer [55], with a batch size of 256. An overview of this process is shown in Figure 3.

(a) t-SNE of performance vectors

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(c) Per-class accuracy across circuit topologies

Evaluation. We begin by assessing the quality of the input representation used for topology classification. Normalized performance vectors encode rich semantic information about circuit behavior. To validate this, we project them into a two-dimensional t-SNE space [56] (Figure 4(a)). The resulting clusters align closely with topology labels, indicating that performance specifications reflect underlying schematic structure and are effective inputs for supervised classification.

We assess classification performance using accuracy, balanced accuracy, macro precision, macro recall, macro F1, and micro F1 scores on the test set. As summarized in Table 1, the classifier achieves an overall accuracy of 99.57%, with macro F1 of 99.30% and balanced accuracy of 99.33%, demonstrating strong generalization across all 20 circuit topologies. Micro F1 (identical to accuracy in the multiclass setting) reaches 99.57%, while macro metrics-averaged equally across classes-highlight robustness to class imbalance. Seed-averaged results with 95% confidence intervals are provided in Appendix C. These trends are reinforced by the per-class accuracy plot in Figure 4(c), where most topologies reach 100% accuracy.

The confusion matrix in Figure 4(b) visualizes only the misclassified instances, as most classes achieve perfect accuracy. The few observed errors are primarily concentrated among the two voltage amplifier topologies-common-gate (CGVA) and common-source (CSVA). These circuits operate near the gain-bandwidth limit of the transistor, and when the main amplifier transistor size is held constant, performance metrics such as power consumption, gain, and bandwidth can converge across these architectures. This occasional overlap in the performance space introduces ambiguity in classification for a small subset of instances. For other circuit categories, no significant confusion is expected or observed. These results validate our hypothesis that performance vectors contain sufficient semantic structure for accurate, scalable topology classification.

5 Stage 2: Generalizable Forward Modeling for Performance Prediction

Task Setup. The goal of Stage 2 is to learn a differentiable approximation of the circuit simulator that maps a topology T and parameter vector x to a performance prediction ˆ y = f θ ( T, x ) , where ˆ y ∈ R 16 . Unlike black-box simulators, this learned forward model enables efficient performance estimation and supports gradient-based parameter inference in Stage 3. The model is trained to generalize across circuit families and can be reused on unseen topologies with minimal fine-tuning.

Each datapoint consists of a graph-structured Cadence netlist annotated with resolved parameter values and the corresponding performance metrics. We frame the learning task as a supervised regression problem. Since not all performance metrics apply to every topology (e.g., oscillation frequency is undefined for amplifiers), we train the model using a masked mean squared error loss:

where m i = 1 if the i -th metric is defined for the current sample, and 0 otherwise.

Model Architecture and Training. Each circuit is represented as an undirected multiedge graph with voltage nets as nodes and circuit components as edges. All circuit parameters-both fixed and sweepable-are assigned to edges, along with categorical device types and one-hot encoded indicators. For each edge e , these attributes are concatenated to form a unified feature vector x e . The feature set is consistent within each component type but varies across types (e.g., NMOS vs. inductor), reflecting the structure defined in Section 3.2.

To account for component heterogeneity, we apply type-specific MLP encoders ϕ ( t e ) enc to the raw features x e of each edge e , producing edge embeddings z e = ϕ ( t e ) enc ( x e ) , where t e denotes the component type of edge e . Node features are initialized as scalar dummy values and mapped to a hidden dimension via a shared linear layer. We then apply a 4-layer edge-centric message-passing GNN with residual connections. At each layer ℓ , every node u receives messages from all incident edges e ∈ E u , where E u denotes the set of edges connected to u . Messages are computed using a shared function ϕ MSG, which takes the hidden state of the neighboring node src ( e ) and the associated edge embedding. Node states are then updated via a learnable function ϕ UPD, followed by a residual connection and nonlinearity:

where z e ∈ R d is the learned embedding of edge e , and h ( ℓ ) src ( e ) ∈ R d is the hidden state of the node at the other end of edge e from u at layer ℓ . The update function ϕ UPD is a shared linear transformation applied to all nodes. After L = 4 GNN layers, node embeddings are aggregated using global mean pooling to obtain a fixed-size graph representation:

where V is the set of all nodes in the graph. The resulting vector is then passed through a fully connected MLP ( output_mlp ) to predict the 16-dimensional performance vector ˆ y ∈ R 16 . An overview of this GNN-based forward prediction pipeline is shown in Figure 5.

To stabilize training, physical parameters are rescaled by their expected units (e.g. resistance by 10 3 ), and performance targets are normalized to z-scores using training statistics. We train the model using the Adam optimizer (learning rate 10 -3 , batch size 256) and a ReduceLROnPlateau scheduler. Xavier uniform initialization is used for all layers, and early stopping is based on validation loss. We adopt the same splits as in Section 4 for consistency in evaluation.

Evaluation. We evaluate the accuracy of the GNN forward model f θ on a test set drawn from 19 of the 20 topologies. One topology-RVCO-is entirely excluded from training, validation, and test splits to assess generalization to unseen architectures. Prediction quality is measured using standard regression metrics: coefficient of determination (R 2 ), root mean squared error (RMSE), and mean absolute error (MAE), computed independently for each of the 16 performance metrics. We also report the mean relative error per metric , computed as the average across all test samples where each metric is defined. As summarized in Table 2, the model achieves high accuracy across all dimensions, with an average R 2 of 0.972.

To evaluate end-to-end prediction accuracy at the sample level, we compute the mean relative error per instance , defined as the average relative error across all valid (non-masked) performance metrics for each test sample. Figure 6 shows the distribution of this quantity across the test set (trimmed at the 95th percentile to reduce the impact of outliers). The distribution is sharply concentrated, indicating that most predictions closely match their corresponding target vectors. Without percentile trimming, the overall mean relative error across the full test set is 9.09% . Seed-averaged results with 95% confidence intervals are provided in Appendix C.

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Generalizing to Unseen Topologies via Fine-Tuning. To assess the generalization ability of our pretrained GNN, we evaluate it on the held-out RVCO topology, which was entirely excluded from the Stage 2 training, validation, and test splits. Notably, the RVCO training partition used here matches that of the Stage 1 experiments (Section 4), enabling consistent cross-stage evaluation.

We fine-tune the GNN by freezing all encoder and message-passing layers and updating only the final output head ( output_mlp ). Fine-tuning is performed on the RVCO training set, which contains approximately 30,000 instances, and completes in under 30 minutes on a MacBook CPU.

Even in the zero-shot setting-where the model has never seen RVCO topologies-the pretrained GNN achieves a nontrivial mean relative error of 30.4%, highlighting its strong cross-topology generalization. Fine-tuning reduces this error to just 0.9% , demonstrating that the structural and parametric priors learned during pretraining are highly transferable. Table 3 reports detailed performance across five key metrics of RVCO, confirming that the pretrained GNN can be rapidly adapted to novel circuit families with minimal supervision.

6 Stage 3: Layout-Aware Parameter Inference via Gradient Reasoning

Task Setup. Given a target performance vector y target and a selected topology T ∗ , the goal of Stage 3 is to recover a parameter vector x ∗ that minimizes a total loss combining performance error and layout-aware penalties, using the learned forward model f θ from Stage 2. This formulation enables instance-wise inverse design without requiring circuit-level simulation.

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To initialize optimization, we perturb domain-specific scale factors (e.g., 10 -12 for capacitors) to sample a plausible starting point x 0 . Parameters are iteratively updated via gradient descent, guided by both functional and physical objectives. Topology-specific constants are held fixed, and parameter values are clipped to remain within valid domain bounds throughout the process.

Loss Function. The total loss follows the structure defined in Eqn 1, jointly minimizing performance mismatch and layout cost:

where L perf is the masked mean squared error (see Eqn 2) between predicted and target performance vectors, and L layout is a normalized area penalty derived from analytical layout equations. To prioritize functionality, layout loss is softly gated by a sigmoid function:

where σ ( · ) denotes the sigmoid function, and γ , τ are fixed scalars controlling the sharpness and center of the gating. This gating attenuates layout penalties when performance error exceeds a threshold τ , encouraging the model to first achieve functionality before optimizing for layout compactness.

We set τ = 0 . 05 , γ = 50 , and normalize layout area by 1 mm 2 to stabilize gradients. The layout weight λ area = 0 . 02 is chosen empirically to balance performance accuracy and physical realism without dominating the loss. This gated formulation supports manufacturable parameter recovery and reflects the broader paradigm of physics-informed learning [57]. Further discussion on user-defined objectives is provided in Appendix D.

Differentiable Layout Modeling. In mm-wave analog design, layout is not a downstream concern but a critical determinant of circuit performance-particularly for passive components. Substrate coupling, proximity effects, and DRC-imposed geometries directly affect key metrics such as resonance frequency, quality factor, and impedance matching. To incorporate these effects, we introduce a differentiable layout model that computes total physical area analytically from circuit parameters. This enables layout constraints to directly guide parameter optimization during inverse design. By minimizing the layout area in distributed mm-wave circuits [58], unwanted signal loss [59] is reduced, the self-resonance frequency of passives can increase [60], and phase and amplitude mismatches across signal paths [61] can be reduced.

The layout model is deterministic and non-learned. It estimates area contributions from passive components-capacitors, inductors, and resistors-as these dominate total area and exhibit layoutsensitive behavior. Active devices (e.g., MOSFETs) are excluded since their geometries are fixed by the PDK and are negligible [62]. For a given parameter vector x , the total layout loss is computed as: L layout ( x ) = ∑ e ∈E passive A e ( x ) , where E passive is the set of passive elements, and A e ( x ) is the area of the created layout for the passive component based on analytical physics-based equations. The area of element e is estimated based on its 2D dimensions (e.g., A = W · L for resistors and capacitors). This area is normalized and used as a differentiable penalty in the optimization objective (see Eqn 3). Further implementation details are provided in Appendix E.

Gradient Reasoning Procedure. Starting from the initialized parameter vector x 0 , we iteratively update parameters via gradient reasoning. At each step, the frozen forward model f θ predicts the performance ˆ y = f θ ( T, x ) , and the total loss L total is evaluated. Gradients are backpropagated with respect to x , and updates are applied using the Adam optimizer. Optimization proceeds for a fixed number of steps, with early stopping triggered if the loss fails to improve over a predefined window.

(a) Designed DohPA schematic

(b) Layout of designed DohPA

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Cg

Rb

C1

L1

L2

Two NMOS

Transistors

To handle varying circuit difficulty and initialization quality, we employ an adaptive learning rate strategy. Each instance begins with a moderate learning rate ( 10 -6 ), refined during optimization via a ReduceLROnPlateau scheduler. If the solution fails to meet thresholds on performance error or layout area, optimization restarts with a more exploratory learning rate. This adjustment balances exploration and fine-tuning, enabling rapid convergence to physically valid solutions, typically within milliseconds to under one second per instance. An overview is shown in Figure 7.

Evaluation. We evaluate Stage 3 on 9,500 test instances (500 per topology) using our gradient-based optimization pipeline. A design is considered converged if it meets both: (i) a predicted mean relative error below 10%, and (ii) a layout area under a topology-specific bound-1 mm 2 for most circuits and 1.5 mm 2 for DLNA, DohPA, and ClassBPA. The 10% error threshold reflects the forward model's ∼ 9% average prediction error (Section 5). A design is deemed successful if its final Cadencesimulated performance deviates from the target by less than 20%, confirming real-world viability. Our method achieves a success rate of 78.5% and a mean relative error of 17.7% across converged designs, with average inference time under 1 second on a MacBook CPU. Notably, success rate is coupled with the convergence threshold: tighter error bounds yield higher accuracy but require more iterations-critical for large-scale design tasks.

To illustrate the effectiveness of our pipeline, Figure 8 shows a representative result for the DohPA topology: the synthesized schematic is shown on the left, and the corresponding layout is on the right. These results confirm that the recovered parameters are both functionally accurate and physically realizable. Together, they demonstrate that FALCON enables layout-aware inverse design within a single differentiable pipeline-a capability not supported by existing analog design frameworks.

7 Conclusion and Future Work

We presented FALCON, a modular framework for end-to-end analog and RF circuit design that unifies topology selection, performance prediction, and layout-aware parameter optimization. Trained on over one million Cadence-simulated mm-wave circuits, FALCON combines a lightweight MLP, a generalizable GNN, and differentiable gradient reasoning to synthesize circuits from specification to layout-constrained parameters. FALCON achieves >99% topology selection accuracy, <10% prediction error, and efficient inverse design-all within sub-second inference. In addition, the GNN forward model generalizes to unseen topologies with minimal fine-tuning, supporting broad practical deployment. Further discussion of training and inference efficiency, as well as practical limitations, is provided in Appendix F.

In future work, we aim to expand the topology library and support hierarchical macroblocks for scalable design beyond the cell level. We also plan to extend the dataset to cover multiple operating frequencies, enabling validation across diverse bands, and to enhance the layout-aware optimization with learned parasitic models, EM-informed constraints, and electromigration considerations for more accurate post-layout estimation. Finally, integrating reinforcement learning or diffusion-based models for generative topology synthesis represents a promising step toward general-purpose analog design automation.

Acknowledgments and Disclosure of Funding

We thank Andrea Villasenor and Tanqin He for their assistance with circuit data generation. We also thank Mohammad Shahab Sepehri for his insightful discussions and thoughtful feedback during the development of this work.

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A Qualitative Comparison with Prior Work

To contextualize FALCON within the broader landscape of analog circuit design automation, we provide a qualitative comparison against representative prior works in Table 4. This comparison spans key capabilities including topology selection, parameter inference, performance prediction, layout awareness, and simulator fidelity. We additionally assess reproducibility via dataset and code availability, and introduce a new axisRF/mm-wave support-to highlight methods evaluated on high-frequency circuit blocks such as LNAs, mixers, and VCOs. Compared to existing approaches, FALCON is the only framework that unifies all these dimensions while maintaining foundry-grade fidelity and open-source accessibility. Definitions for each comparison axis are provided in Table 5.

B Dataset Details and Performance Metric Definitions

During dataset generation, each simulated circuit instance is annotated with a set of performance metrics that capture its functional characteristics. All simulations are performed at a fixed frequency of 30 GHz, ensuring consistency across circuit types and relevance to mm-wave design. A total of 16 metrics are defined across all circuits-spanning gain, efficiency, impedance matching, noise, and frequency-domain behavior-though the specific metrics used vary by topology. For example, phase noise is only applicable to oscillators. An overview of all performance metrics is provided in Table 6.

B.1 Low-Noise Amplifiers (LNAs)

Low-noise amplifiers (LNAs) are critical components in receiver front-ends, responsible for amplifying weak antenna signals while introducing minimal additional noise. Their performance directly influences downstream blocks such as mixers and analog-to-digital converters (ADCs), ultimately determining system-level fidelity [31]. To capture the architectural diversity of practical radio-frequency (RF) designs, we include four widely used LNA topologies in this study-common-source LNA (CSLNA), common-gate LNA (CGLNA), cascode LNA (CLNA), and differential LNA (DLNA)-as shown in Figure 9.

The CSLNA is valued for its simplicity and favorable gain-noise trade-off, especially when paired with inductive source degeneration [30]. The CGLNA, often used in ultra-wideband systems, enables broadband input matching but typically suffers from a higher noise figure [32]. The CLNA improves gain-bandwidth product and reverse isolation, making it ideal for high-frequency, high-linearity applications [33]. The DLNA exploits circuit symmetry to enhance linearity and reject common-mode noise, and is commonly found in high-performance RF front-end designs [34]. The design parameters and performance metrics associated with these topologies are summarized in Table 7.

(a) CSLNA

(b) CGLNA

(c) CLNA

(d) DLNA

VoD

VoD

Voo

VoD

Ld

M

0

C1

C1

C

北

oVout

H—oVout

VoutO

C2

WN2

W

VinoH

WN

WN

C

Lg

北

VinoH

C2

L9

WN1

Vin+oH

C2

000

WN1

WN1

Lg

HIoVin-

C2

C1

V

gs

B.2 Mixers

Mixers are fundamental nonlinear components in RF systems, responsible for frequency translation by combining two input signals to produce outputs at the sum and difference of their frequencies. This functionality is essential for transferring signals across frequency domains and is widely used in both transmission and reception paths [35]. To capture diverse mixer architectures, we implement four representative topologies in this work-double-balanced active mixer (DBAMixer), double-balanced passive mixer (DBPMixer), single-balanced active mixer (SBAMixer), and single-balanced passive mixer (SBPMixer)-as shown in Figure 10.

The DBAMixer integrates amplification and differential switching to achieve conversion gain and high port-to-port isolation. Despite its elevated power consumption and design complexity, it is well suited for systems requiring robust performance over varying conditions [36]. The DBPMixer features a fully differential structure that suppresses signal leakage and improves isolation, at the cost of signal loss and a strong local oscillator drive requirement [37]. The SBAMixer includes an amplification stage preceding the switching core to enhance signal strength and reduce noise, offering a balanced performance trade-off with increased power consumption and limited spurious rejection [30]. The SBPMixer employs a minimalist switching structure to perform frequency translation without active gain, enabling low power operation in applications with relaxed performance demands [38]. The parameters and performance metrics for these mixer topologies are listed in Table 8.

(a) DBAMixer

(b) DBPMixer

(c) SBAMixer

(d) SBPMixer

VoD

VLO+

C

R

R

C

VoD

VLO+

OVIF+

ViF.O

VRF+O

WN

W

R

OVIF+VIF.O

R

R

C

VLO+O

WN2

VLO-

WN2

VLO+

VIF+

D

VLO+O

WN2

WN2

OVLO-

WN

VIF+

"T

R

VRFO

VIF.

VRF+O

WN1

WN1

WN

VRF.O

WN

R

VRF

C

WN1

w

R

H

VLO+

C

ltail

VLO-

C

Dataset Type

Topology (Code)

# of Samples

Parameter

Sweep Range

Performance Metrics (Unit)

Mixer

DBAMixer (4)

42k

C

[1-10] pF

DCP (W)

CGain (dB)

NF (dB)

VSwg (V)

R

[1-10] k

Ω

WN1

[10-30] µm

WN2

[5-25] µm

DBPMixer (5)

42k

C

[100-500] fF

R

[100-600]

Ω

WN

[10-30] µm

SBAMixer (6)

52k

C

[1-15] pF

R

[0.7-2.1] k

Ω

WN1

[10-30] µm

WN2

[10-20] µm

Itail

[3-10] mA

SBPMixer (7)

44k

C

[1-30] pF

R

[1-30] k

Ω

WN

[5-29.5] µm

B.3 Power Amplifiers (PAs)

Power amplifiers (PAs) are the most power-intensive components in radio-frequency (RF) systems and serve as the final interface between transceiver electronics and the antenna. Given their widespread use and the stringent demands of modern communication standards, PA design requires careful trade-offs across key performance metrics [39]. Based on the transistor operating mode, PAs are typically grouped into several canonical classes [40]. In this work, we implement four representative topologies-Class-B PA (ClassBPA), Class-E PA (ClassEPA), Doherty PA (DohPA), and differential PA (DPA)-as shown in Figure 11.

The ClassBPA employs complementary transistors to deliver high gain with moderate efficiency, making it suitable for linear amplification scenarios [41]. The ClassEPA uses a single transistor configured as a switch, paired with a matching network. By minimizing the overlap between drain voltage and current, this topology enables high-efficiency operation and improved robustness to component variation [30]. The DohPA combines main and peaking amplifiers using symmetric two-stack transistors, maintaining consistent gain and efficiency under varying power levels [42]. The DPA features a two-stage cascode structure designed to maximize gain and linearity, offering a favorable trade-off between output power and power consumption [43]. For this topology, we replace the transformer with a T-equivalent network to simplify modeling and training of the graph neural network. Parameter sweeps and performance metrics for these PAs are listed in Table 9.

(a) ClassBPA

(b) ClassEPA

(c) DohPA

(d) DPA

VDD

VDD

VDD

VDD

Vb2

Vb2

R

000

W

W

C2

L2

F

000—oVout

WN1

WN2

V

000

OVout

C

C

WN

C

C2

000

Vb

Vb1

Vb1

Vb1

Vb2

WN1

000

WN1

VDD

Vb4

WN

WN2

L

g Los

WN1

WN1

WN

WN2

Lis

1

Lm

Vin-O

oVout

Vb1

Vb2

EquivalentModel ofTransformers

B.4 Voltage Amplifiers (VAs)

Voltage amplifiers (VAs) are fundamental components in analog circuit design, responsible for increasing signal amplitude while preserving waveform integrity. Effective VA design requires balancing key performance metrics tailored to both RF and baseband operating conditions [44]. In this work, we implement four widely used VA topologies-common-source VA (CSVA), commongate VA (CGVA), cascode VA (CVA), and source follower VA (SFVA)-as shown in Figure 12.

The CSVA remains the most widely adopted configuration due to its structural simplicity and high voltage gain. It is frequently used as the first gain stage in various analog systems [45]. The CGV A is suitable for applications requiring low input impedance and wide bandwidth, such as impedance transformation or broadband input matching [46]. The CVA, which cascades a common-source stage with a common-gate transistor, improves the gain-bandwidth product and enhances stability, making it ideal for applications demanding wide dynamic range and robust gain control [47]. The SFV A, also known as a common-drain amplifier, provides near-unity voltage gain and low output impedance, making it well suited for interstage buffering, load driving, and impedance bridging [48]. Parameter ranges and performance specifications for these V A topologies are listed in Table 10.

(a) CSVA

(b) CGVA

(c) CVA

(d) SFVA

VDD

R

oVout

Vb

WN2

WN1

Vb

WN3

VDD

VoD

R

R

Vouto

oVout

C

Vgate

WN

WN1

WN2

VDD

Vgate

WN1

oVout

Vb

WN2

B.5 Voltage-Controlled Oscillators (VCOs)

Voltage-controlled oscillators (VCOs) are essential building blocks in analog and RF systems, responsible for generating periodic waveforms with frequencies modulated by a control voltage. These circuits rely on amplification, feedback, and resonance to sustain stable oscillations. Owing to their wide tuning range, low power consumption, and ease of integration, VCOs are broadly used in systems such as phase-locked loops (PLLs), frequency synthesizers, and clock recovery circuits [49]. In this work, we implement four representative VCO topologies-inductive-feedback VCO (IFVCO), cross-coupled VCO (CCVCO), Colpitts VCO (ColVCO), and ring VCO (RVCO)-as shown in Figure 13.

The IFVCO employs an NMOS differential pair with an inductor-based feedback path to sustain oscillations. This topology provides favorable noise performance and compact layout, making it well suited for low-voltage, low-power designs [50]. The CCVCO achieves negative resistance through cross-coupling, enabling low phase noise and high integration density, and is widely adopted in frequency synthesizers and PLLs [51]. The ColVCO uses an LC tank and capacitive feedback to achieve high frequency stability and low phase noise, making it ideal for precision RF communication and instrumentation [52]. The RVCO consists of cascaded delay stages forming a feedback loop, offering low power consumption, wide tuning range, and minimal area footprint, though at the cost of higher phase noise. It is commonly used in on-chip clock generation and low-power sensor applications [53]. Design parameters and performance metrics for these VCO topologies are presented in Table 11.

(a) IFVCO

(b) CCVCO

(c) ColVCO

(d) RVCO

VoD

VoD

C

out

Vout

Vcont

WN

L2

00

L2

NN

Vcont

Wvar

Wvar

WN

oVout

WN

WN

WN

WN

WN

C2

C2

C

tail

Vcont

Wvar

Wvar

Vcont

VcontO

C Robustness Across Random Seeds

To evaluate the robustness of our models to random initialization and data shuffling, we repeated experiments using five distinct random seeds: {42, 123, 777, 2023, 3407}. Reporting across multiple seeds is important for ensuring that observed results are not artifacts of a specific initialization or training trajectory, but rather reflect the stable behavior of the method. For each metric, we compute the mean and 95% confidence interval across seeds, reporting results in the form µ ± ∆ .

For the MLP topology selection model, results are highly stable across random seeds. The accuracy reaches 99 . 57 ± 0 . 01% with balanced accuracy at 99 . 34 ± 0 . 02% , while both macro and micro F1 scores exceed 99 . 3% with confidence intervals no larger than ± 0 . 02 . These narrow intervals indicate that the MLP's performance is effectively invariant to random initialization, underscoring its robustness and reliability in the topology selection stage of the pipeline (Section 4).

For the GNN-based forward performance prediction model, the overall mean relative error across all metrics is 9 . 14 ± 0 . 38% (95% CI). Individual performance predictions, including DC power consumption, gain, bandwidth, and oscillation frequency, exhibit narrow confidence intervals-for example, noise figure achieves 4 . 48 ± 0 . 07% error and oscillation frequency 0 . 65 ± 0 . 03% . These results indicate that the GNN achieves consistently accurate predictions across diverse circuit characteristics. The tight confidence intervals further demonstrate that the model's performance is robust to random initialization, underscoring its reliability as a generalizable forward predictor within the pipeline (Section 5). The full seed-dependent results for both models are provided in Tables 12 and 13.

D User-Defined Loss Functions for Gradient Reasoning

Stage 3 of FALCON employs gradient reasoning with the forward GNN fixed, enabling the optimization objective to be redefined without retraining or fine-tuning the predictive model. This design allows users to flexibly adapt the loss function to capture specific trade-offs or constraints. We illustrate this flexibility with two examples.

Weighted Performance Loss. Rather than treating all performance metrics equally, users can specify weights α i for each target metric:

where larger α i prioritize certain specifications (e.g., gain or noise figure). Here, m i = 1 if the i -th metric is defined for the current sample, and 0 otherwise.

Interval-Constrained Performance Loss. Users may also define acceptable ranges for metrics rather than fixed targets. Given optional lower and/or upper bounds y lower i , y upper i , the interval penalty is:

where the indicator ✶ {·} indicates whether the corresponding bound is specified. This formulation naturally handles the cases where only an upper bound, only a lower bound, or both bounds are provided. As above, m i = 1 if the i -th metric is defined for the current sample, and 0 otherwise.

General Extensibility. More generally, the total loss in Eqn. 3 can be replaced with any user-defined formulation, allowing both L perf and L layout to be substituted with customized objectives. Additional physical constraints, multi-objective trade-offs, or alternative layout penalties can be incorporated with only a few lines of code. This extensibility underscores the flexibility of FALCON and enables the framework to adapt to diverse design objectives.

E Layout Design and DRC Compliance

E.1 Design Rule Enforcement in 45 nm CMOS

We implemented FALCON using a 45 nm CMOS technology node, applying rigorous Design Rule Checking (DRC) at both the cell and full-chip layout levels. At the cell level, our parameterized layout generators enforced foundry-specific constraints, including minimum feature width and

length, contact and via spacing, and metal enclosure rules. At the circuit level, we incorporated physical verification to mitigate interconnect coupling, IR drop, and layout-dependent parasitic mismatches-factors that are especially critical in high-frequency and precision analog design.

DRC plays a vital role in ensuring that layouts comply with process design rules defined by the semiconductor foundry. Adhering to these rules ensures not only physical manufacturability but also electrical reliability . Violations may lead to fabrication failures, including yield degradation, electrical shorts or opens, electromigration-induced issues, and parasitic mismatches. Moreover, DRC compliance is essential for compatibility with downstream fabrication steps such as photomask generation, optical lithography, and chemical-mechanical planarization (CMP), safeguarding the yield and fidelity of the final IC.

Circuit-Level Layout Guidelines. We enforced several topology-aware layout constraints during full-circuit integration to preserve signal integrity and robustness:

Inductor-to-inductor spacing: ≥ 35.0 µ m to mitigate mutual inductive coupling and magnetic interference.

Guardring placement: Sensitive analog blocks are enclosed by N-well or deep N-well guardrings with spacing ≥ 5.0 µ mto suppress substrate noise coupling.

Differential pair symmetry: Differential signal paths are layout-matched to ensure ∆ L < 0 . 5 µ m, minimizing mismatch and preserving phase balance.

DRC Constraints and Layer Definitions. Table 14 summarizes the DRC constraints applied to key analog components across relevant process layers. Table 15 provides the abbreviations used for metal, contact, and via layers in the 45 nm CMOS process.

W

(b) Resistor layout

L

Dout

Din

M

E.2 MIMCapacitor Capacitance Model

The total capacitance C N of a metal-insulator-metal (MIM) capacitor is modeled as:

where L and W are the layout length and width in µ m, C a is the area capacitance density, and C p is the fringing field contribution per unit length. This model includes both area and perimeter contributions to more accurately reflect layout-dependent capacitance in IC design (see Figure 14(a)).

1. Area Capacitance Term: C a · L · W

Physical Concept: This term represents the primary (parallel-plate) capacitance formed between the overlapping top and bottom metal layers. It arises from the uniform electric field across the dielectric.

Layer Physics Explanation:

L · W corresponds to the overlap area of the plates.

C a = 0 . 335 fF /µ m 2 is the area capacitance density, derived from:

-Dielectric permittivity ε of the insulating material.

-Dielectric thickness d , with C ∝ ε/d .

2. Perimeter (Fringing) Capacitance Term: C p · 2 · ( L + W )

Physical Concept: This term models fringing fields at the plate edges, contributing additional capacitance-particularly relevant in small geometries.

Layer Physics Explanation:

2 · ( L + W ) is the physical perimeter of the capacitor.

C p = 0 . 11 fF /µ maccounts for the fringing field contribution per unit length.

Summary: This composite model enables accurate estimation of MIM capacitance by capturing both parallel-plate and fringing effects. The constants C a and C p are typically calibrated using process-specific measurements or electromagnetic simulations.

For a fixed capacitor length L = 20 µ mand width W ∈ [6 . 05 , 150 . 0] µ m, the layout-aware capacitance is approximated by:

The corresponding bounding area is estimated from the component's geometric envelope:

E.3 N + Silicided Polysilicon Resistor Model

The resistance of a layout-defined resistor implemented using the ndslires layer is modeled as:

Physical Concept: This structure uses heavily doped N + polysilicon overlaid with a silicide layer to reduce resistance. Current flows laterally through the poly-silicide film (see Figure 14(b)), and resistance is shaped by the aspect ratio of the layout as well as process-dependent corrections.

Layer Physics Explanation:

R s = 17 . 6 Ω / □ (ohm per square) is the sheet resistance of the silicided poly layer.

W = 5 . 0 µ m is the drawn width; ∆ W = 0 . 048 µ m accounts for process-induced width bias.

L is the drawn resistor length.

R end = 1Ω models terminal resistance due to contact diffusion and current crowding.

δ = 0 . 917 Ω accounts for residual layout-dependent parasitics.

Summary: The empirical layout relation used in parameterized generation is:

This model is valid for L ∈ [0 . 4 , 5 . 0] µ mwith fixed width W = 5 . 0 µ m. The estimated layout area based on bounding box dimensions is:

E.4 Octagon Spiral Inductor Model

Physical Concept: Accurate modeling and layout optimization of planar spiral inductors are critical in analog circuit design. Inductor performance is highly sensitive to parasitic elements, achievable quality factor ( Q ), and layout constraints imposed by process design rules. To support accurate performance prediction and inform layout choices, we adopt a modified power-law model that expresses inductance as a function of key geometric parameters. The model is validated against empirical measurements and shows strong agreement with classical analytical formulations.

Numerous classical formulations relate inductance to geometric factors such as the number of turns, average diameter, trace width, and inter-turn spacing. Among these, the compact closed-form expressions in RF Microelectronics textbook [30] are widely adopted for their balance of simplicity and accuracy. Building on this foundation, we adopt a reparameterized monomial model that better fits our empirical measurement data:

Layer Physics Explanation:

D out = 2( R + W 2 ) is the outer diameter,

D in = 2( R -W 2 ) is the inner diameter,

D avg = ( D out + D in ) / 2 = 2 R is the average diameter,

R is the radius in µ m ,

W is the trace width in µ m ,

S is the spacing in µ m .

This expression is calibrated using measured data from a series of one-turn inductors fabricated with varying radius ( R ), while keeping the trace width fixed at W = 10 µ m and spacing at S = 0 . 0 µ m . Table 16 summarizes the measured inductance values used for model fitting.

Summary: With W and S fixed, inductance simplifies to:

The bounding area is estimated by:

Table 16: Measured inductance for one-turn inductors with fixed W = 10 µ m and S = 0 . 0 µ m

The performance of on-chip inductors is fundamentally influenced by layout-dependent factors such as trace width, metal thickness, and inter-turn spacing. Increasing the trace width ( W ind) reduces series resistance by enlarging the conductor's cross-sectional area, thereby improving the quality factor, Q = ωL/R series. However, wider traces also increase parasitic capacitance to adjacent turns and the substrate, which lowers the self-resonance frequency.

Metal thickness ( H ind) also plays a crucial role in minimizing ohmic losses. At high frequencies, current is confined near the conductor surface due to the skin effect. For copper at 25 GHz , the skin depth δ is approximately 0 . 41 µ m ; thus, using a metal layer thicker than 4 δ (i.e., 1 . 6 µ m ) ensures efficient current flow. However, increasing thickness beyond this threshold yields diminishing returns in Q due to saturation in current penetration.

Turn-to-turn spacing ( S ) affects both inductance and quality factor ( Q ). Tighter spacing enhances magnetic coupling, thereby increasing inductance density. However, it also intensifies capacitive coupling and dielectric losses-particularly in modern CMOS processes with highk inter-metal dielectrics-which can degrade Q . Conversely, excessive spacing reduces inductance without providing a proportionate benefit in loss reduction. As a result, one-turn spiral inductors are commonly favored in RF design due to their low series resistance, minimized parasitics, and improved modeling predictability.

These insights guided our design choices for layout-aware inductor implementation. To balance the competing demands of Q optimization, parasitic control, and DRC compliance, we implemented inductors using Metal 3 and set W = 10 µ m as the default trace width. This width offers a lowresistance path that enhances Q while maintaining manageable parasitic capacitance and sufficient pitch for lithographic reliability. Metal 3 was selected for its favorable trade-off between thickness and routing density-it is thick enough to mitigate skin-effect losses at high frequencies while offering sufficient flexibility for compact layout integration.

The implemented spiral inductor geometry is shown in Figure 14(c). Table 17 summarizes the DRC-compliant tuning ranges, estimated layout areas, and decomposition strategies for single-cell passive components in our layout library.

E.5 Layout Examples of Synthesized Circuits

To illustrate the correspondence between schematic and layout representations, we present three synthesized circuits: DBAMixer, IFVCO, and DLNA, shown in Figures 15, 16, and 17, respectively.

(b) Layout of designed DBAMixer

VoD

C:

R 7.23 kQ

7.23kQR

C

Lmax

15pF

15pF

OVIF+

ViF.O

WN2

WN2

VLO+O

22.3 μm

22.3 μm

OVLO+

Wmax

VLO-

VRF+O

WN1

WN1

OVRF-

C

R

R

18.7 μm

18.7 μm

Routing

Wn2

Wn2

Capacitor

Resistor

Transistors

SixNMOS

Wn1

Wn1

(a) Designed DBAMixer schematic

(a) Designed IFVCO schematic

(b) Layout of designed IFVCO

Lmax

L1

L1

Wvar

TwoNMOS

Varactors

Routing

888

2888

888928

C2

C1

C2

Wmax

Inductor

Capacitor

Wn

L2

NMOs Transistor

350pH

L1

350pH

out

Wvar

509 pH

509pH

Wvar

9.94μm

L2

00

L2

9.94 μm

Vcont

WN

WN

Vcont

5.03μm

5.03μm

C2

C2

300fF

3

700fF

C1

L3

300fF

(a) Designed DLNA schematic

(b) Layout of designed DLNA

Lmax

Rb

R

Wn3

VoD

Ld

Ld

Rd

Ru

Rg

Rd

Rd

Rb

Rb

112 pH

5

112 pH

NMOS Transistor

oVoutO

WN3

WN2

200fF

C

C

200fF

WN2

WN3

12.4 μm

12.4 μm

1

Rg

Wn2

Wmax

Wn1

WN1

WN1

HoVin

C2

Lg

4.97 μm

4.97 μm

Lg

C2

Two NMOS

100 fF

600 pH

600 pH 100fF

Transistors

Ls

Routing

100 pH

100 pH

Inductor

Capacitor

Resistor

67

In the IFVCO example, the inductor labeled L 3 functions as an RF choke and is excluded from the on-chip layout due to its large area requirement. Instead, it is intended for off-chip implementation at the PCB level and connected to the die via wire bonding. This external connection is indicated by the yellow pad in Figure 16(b), which serves as the wire-bonding interface.

Since the current stage of system lacks automated routing, all interconnects in the layout were manually drawn to ensure accurate correspondence with the schematic connectivity. These examples demonstrate that synthesized circuit parameters can be successfully translated into DRC-compliant, physically realizable layouts, bridging the gap between high-level optimization and tapeout-ready design.

F Practical Considerations and Limitations

F.1 Training and Inference Efficiency

Although our codebase supports GPU acceleration, all experiments in this work-excluding initial dataset generation-were conducted entirely on a MacBook CPU. This highlights the efficiency and accessibility of the FALCON pipeline, which can be executed on modest hardware without specialized infrastructure. Our MLP and GNN models contain 207k and 1.4M trainable parameters, respectively, with memory footprints of just 831 KB and 5.6 MB.

In Stage 1, the MLP classifier trains in approximately 30 minutes with a batch size of 256 and performs inference in the order of milliseconds per batch. Stage 2's GNN model takes around 3 days to train on the full dataset using the same batch size and hardware. Fine-tuning on an unseen topology (e.g., RVCO) using ∼ 30,000 samples completes in under 30 minutes.

In Stage 3, the pretrained GNN is used without retraining to perform layout-constrained parameter inference via gradient-based optimization. Inference is conducted one instance at a time (batch size 1), with typical runtimes under 1 second per circuit. Runtime varies based on the convergence threshold and circuit complexity but remains below 2-3 seconds in the worst case across the full test set.

A solution is considered successful if the predicted performance meets the target within a specified relative error threshold. While tighter thresholds (e.g., 5%) improve accuracy, they require more optimization steps-particularly over large datasets. As a result, both success rate and inference time in Stage 3 are directly influenced by this tolerance, which can be tuned based on design fidelity requirements.

F.2 Limitations

This work focuses on a representative set of 20 curated analog topologies spanning five circuit families. Consequently, the topology selection stage is limited to suggesting only among the designs present in the training set and cannot synthesize novel circuits. A natural future direction is to either extend the training library to a broader set of topologies or replace the classifier with a generative model capable of directly proposing new netlists conditioned on input specifications. In contrast, the GNN-based forward modeling stage is designed to operate on arbitrary circuit graphs and has already demonstrated strong generalization to unseen architectures (e.g., RVCO), indicating that no modification to this stage is required to support novel circuits.

Beyond topology considerations, the dataset is constructed at a fixed operating frequency of 30 GHz, which ensures consistency across circuit families but constrains frequency generalization. Although the framework can, in principle, extend to other operating points-for example, the voltage amplifier topologies already demonstrate scalability across varying gain-bandwidth trade-offs-systematic validation across diverse frequency bands is beyond the scope of this work. Extending the dataset to cover multiple operating frequencies, or incorporating frequency as an explicit conditioning variable during training, represents an important direction for broadening applicability.

Finally, the differentiable layout model in FALCON captures parasitic effects through analytical approximations of passive components, which is effective for guiding parameter optimization within the learning framework. However, this approach does not fully replace electromagnetic (EM) simulations or post-layout verification, and electromigration constraints are not explicitly incorporated. Incorporating learned parasitic estimators, EM-informed models, and reliability constraints, therefore, remains an important extension toward bridging schematic-level optimization and silicon-proven robustness. In addition, all interconnect routing in the current flow is performed manually to ensure precise control over parasitic management and DRC compliance. While this provides accuracy for the studied designs, it limits scalability for more complex circuits, motivating future integration with automated analog routing tools.

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Answer: [NA]

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Peer reviews:
{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThe paper proposes a unified framework for synthesis of Analog designs. It is aimed at addressing the inverse problem that is given a target specification, design a circuit that meets the spec. The approach involves three steps: a) Topology selection: For a given target performance, choose an optimal topology amongst a fixed set of 20 topologies using a trained MLP classifier b) Performance prediction: For a given topology and parameters, predict the circuit performance using a learned GNN based forward model. c) Parameter inference: Given the target spec and topology, use gradient descent over the learned forward model to find the optimal parameters that meet the requirement.\n\nSTRENGTHS AND WEAKNESSES:\n**Strengths:**  \tThe paper is well-structured and clearly written. It addresses the challenging problem of automating Analog design from specifications. The approach combines topology selection with parameter inference while maintaining structural fidelity. The inclusion of early layout-aware optimization adds value.\n\n**Weakness:**      The paper lacks comparison with existing ML/non-ML based techniques, making it difficult to assess relative performance, efficiency and generalizability against prior approaches.  \n\nThe method uses fixed specification targets and a limited set of topologies, which reduces flexibility and scalability. It is also unclear how practical the approach would be for experienced analog designer, given the lack of support for guiding trade-offs or incorporating domain expertise.\n\nQUESTIONS:\n( I am willing to re-consider scores if some of the following are addressed, especially comparison with prior art)\n\n\n1. It would be helpful if the method could handle specification ranges instead of fixed targets, since that’s how design specs are usually defined in practice.\n2. Allowing designers to indicate which specs matter more—or where trade-offs are acceptable—could make the tool more usable in real design workflows. One way to achieve this would be to use weighted inputs\n3. The paper would benefit immensely from comparison with existing work. While no complete framework exists for direct comparison, each component (topology selection, performance prediction, parameter inference) should be compared against relevant existing methods referenced in the supplementary material (Table 3).\n4.  The paper would benefit from ablation studies on layout cost to access its impact, multi-start to evaluate sensitivity local minima, and a study on parameter initialization to understand its effect on design quality.\n5.  In addition to mean error statistics, it would also be interesting to see the maximum error stats for all three steps.\n\n*Minor:*\n1. Confusion matrix in Fig.3(b) is not complete. Can be added to supplementary material.                                  \t   \t\n2. It would be good to include the discussion on limitations in practical considerations/generalization of this approach in the main paper rather than supplementary.\n\nLIMITATIONS:\nYes", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 4, "CLARITY": 4, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-01"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis work introduces a fully automated framework, FALCON, for designing analog circuits with the aid of machine learning. While various ML-based approaches have been proposed for analog circuit design, they typically focus on isolated steps of the design process—such as topology generation, parameter sizing, or schematic-level performance evaluation. \nWith three core components—a lightweight MLP that selects circuit topology, a GNN that maps topology to performance metrics, and gradient-based optimization of the design parameters—FALCON enables full automation of the entire design process. \nFinally, through training and evaluation leveraging a dataset of one million analog mm-wave circuits, FALCON demonstrates strong performance in topology inference, performance prediction, and efficient layout-aware design.\n\nSTRENGTHS AND WEAKNESSES:\n**Strengths**\n\n- FALCON is an end-to-end, scalable and modular ML framework for designing analog and RF circuits. \nUnlike other prior works, FALCON provides full automation on the entire process. \n\n- To the best of the reviewer's understanding, this paper  utilizes a dataset constructed by the authors themselves, which in itself is a commendable contribution.\n\n- The paper is clearly written and well organized, which makes the high-level idea easy to understand. This clarity is a notable strength of the paper.\n\n\n**Weaknesses**\n\n- This reviewer has a few questions and minor concerns but couldn’t find any significant weaknesses.\n\nQUESTIONS:\n- **Q1.** This reviewer does think that one unified framework is a meaningful contribution. However, this reviewer is curious about what differences there would be compared to simply concatenating the known approaches for each step. What would be the benefit of a unified framework over using established methods for each procedure individually? Are there aspects that are qualitatively more challenging when developing a unified framework, as opposed to just applying known approaches?\n\n- **Q2.** Table 1 shows that the classification task for topology selection can be performed with a high score, even using a simple MLP. The scores seem notably high, and this reviewer is curious whether there is any risk of overfitting. To the best of this reviewer's understanding, the evaluation is performed on pre-labeled data. However, the ultimate goal of topology selection is to build a proper circuit that fits a specific purpose, not merely to classify pre-labeled data. What is the justification for assuming that a high classification score will lead to good topology selection for new tasks? Or is there a procedure to adjust the topology in a later step? Also, it seems the classification is limited to 20 topologies. This reviewer is curious whether these 20 topologies are general enough to support the design of a wide range of new circuits.\n\n\n- **Q3.** The focus of the framework suggested in this paper seems to be analog/RF circuits, but this reviewer feels the overall structure is flexible enough to handle circuits for different tasks. For example, there is a line of work on designing electrical circuits to solve convex optimization problems or to design new convex optimization algorithms. However, if we want to consider circuits for different tasks, I believe the concrete components of the framework would need to change. For example, the topology classification based on an analog/RF circuit dataset should be replaced with another component. Still, it seems possible to retain the idea of updating parameters with gradient descent by modifying the loss function. Do you think the structure of your framework can be adapted to design circuits for different tasks, with appropriate replacements of the components? Or do you think the required changes would be almost equivalent to developing an entirely new framework? Since this question may be outside the scope of your research, the reviewer would appreciate any high-level thoughts the authors are willing to share, if any.\n\nLIMITATIONS:\nYes.", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 1, "CLARITY": 4, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-01"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper presents an ML framework for automating analogue circuit design. The framework consists of: (1) topology selector module, (2) forward GNN mapper that evaluates the performance of a topology-parameter pair, and (3) differentiable layout-constrained optimisation of circuit parameters. The framework is evaluated on a 1 million dataset of millimetre-wave circuits to demonstrate successful end-to-end analogue circuit design.\n\nSTRENGTHS AND WEAKNESSES:\n### Strengths:\n- Advancing the state-of-the-art of automated analogue circuit design is important and timely\n- Releasing a dataset to support further ML-based analogue design research is useful\n- Appendices A to E do a good job at supplementing the core treatment for better understanding in this specialised field of research \n### Weaknesses:\n- From an analogue/RF design standpoint, the work lacks in detail, especially when it presents the results achieved by the Circuit Designer\n- In the Evaluation section, the authors present the results of 9500 test instances (nearly 80% success rate and 17.7% relative error); however, these metrics are highly dependent on the circuit specifications fed into the algorithm. This is a key limitation, as the paper doesn’t explore how performance varies with more challenging or non-standard specs.\n- Appendix F.2 touches on the limitations of the work, but further discussion of limitations needs to be added. See below.\n\nQUESTIONS:\n- In Section 3.3 line 165, is the term “reasoning” for describing the optimisation of Eq. (1) the best term to use?\n- In Section 4, line 184, regarding the 5-layer MLP, is it possible to ablate this?\n- For Figure 3(a), can you provide expanded commentary on the t-SNE visualisation. For instance, could you speculate as to what the strands in the pastel purple cluster (north-most) may mean from a circuit topology standpoint?\n- In Section 5, paragraph “Evaluation” (right after line 237), can you repeat evaluation 19 times so that the held-out topology (1 out of 19) is swept across all available topologies? This will help us understand if RVCO is particularly easy (or difficult) to generalise for.\n\nLIMITATIONS:\nNo. This reviewer suggests considering the following additional limitations: \n- The topologies are characterized @30GHz, but this is not sufficient. The topology choice can vary massively depending on the frequency and therefore a design at 2.5GHz is likely to require a different topology, respect to a design at 30GHz\n- The analysis of the parasitics is approximate. The authors admit that the next step is the addition of EM modelling to improve accuracy of the parasitic. Simulating a 30GHz RF block without an adequate EM model of the interconnects is unreliable, in this reviewer’s opinion a waste of time. I am also unclear on how the accuracy is calculated. Does it compare the results of the model vs. inaccurate non-EM extracted Spectre sims? If so, the correspondence with real silicon results is likely to be rather weak\n- For high-power devices (especially PAs), electromigration must be considered. Especially in advanced nodes, this often drives the transistors and interconnect sizing. Ignoring this can lead to underestimation of the parasitics.", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 3, "CLARITY": 3, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-03"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper introduces a new, single, and scalable machine learning framework for the entire end-to-end analog circuit design flow, including such tasks as topology selection, parameter inference, and layout-aware optimization. Analog and RF design flows conventionally tend to be manual, iterative, and strongly reliant on designer heuristics. FALCON addresses these limitations by formulating circuit synthesis as an inverse problem: given a target performance specification, the framework learns both the circuit topology and parameter configuration to meet the target. \nThe system operates in three stages. In the first stage, it demonstrates the performance-directed topology selection by using a light multilayer perceptron. Secondly, it illustrates the performance prediction by a graph neural network that has been trained on Cadence-simulated circuit graphs. Eventually, this stage emphasizes the gradient-based optimization layout-driven with differentiable constraints to parasitic and physical layout rules. Overall, one of the key contributions is to bring layout goals directly into the optimization loop so that schematic and layout concerns can be represented jointly.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths：\n1. The authors present and publicly release an exceptionally large, high-fidelity dataset of over one million Cadence Spectre simulations spanning 20 expert-designed mm-wave analog/RF topologies. Such an industrial-scale, process-calibrated dataset is exceedingly rare in the academic literature. \n2. FALCON integrates three distinct components—performance-driven topology selection, a graph-neural-network forward model, and a differentiable layout cost—into one seamless, differentiable pipeline. This modular design is among the first to jointly handle inverse circuit design and layout constraints in a unified framework. By embedding parasitic effects and soft design-rule penalties directly into the gradient-based optimization via a differentiable layout loss, the method ensures that the inferred parameters meet both electrical performance targets and physical manufacturability requirements, filling a gap left by traditional “simulate-then-layout” or post-hoc layout workflows.\n3. FALCON demonstrates few-shot generalization by maintaining high accuracy on an entirely unseen topology, indicating its potential for rapid adaptation to new circuit families with minimal additional data. Furthermore, all sub-modules rely on lightweight MLPs or edge-centric GNNs, and the final inversion stage runs in milliseconds to seconds without invoking time-consuming circuit simulators. This real-time performance aligns with the stringent requirements of practical automated design toolchains, highlighting the framework’s clear path to industrial deployment.\n\nWeaknesses：\n1. FALCON assumes a “fixed but extensible” library of expert-designed circuit topologies, which means it cannot autonomously discover or generate novel structures. In contrast to purely generative topology search methods, its capacity for true topological innovation is bounded by the existing template set. This reliance may limit FALCON’s ability to propose entirely new architectures beyond human-curated designs.\n2. The differentiable layout cost in FALCON is based solely on simple two-dimensional area calculations for passive components, omitting more complex parasitic couplings, electromagnetic interactions, and multilayer interconnect effects. In high-precision mm-wave designs, these richer physical phenomena can dominate performance, so a purely area-based surrogate may underestimate post-layout discrepancies, potentially widening the gap between predicted and actual behavior.\n3. All quantitative results in the paper derive from a single training run with fixed random seeds and there is no reporting of standard deviations, confidence intervals, or other measures of variability across multiple trials. For complex models trained on large-scale data, stability and sensitivity to initialization can materially affect conclusions. The absence of statistical significance metrics makes it difficult to assess the robustness of the reported performance gains.\n4. While FALCON covers five key mm-wave circuit type, its evaluation is confined to the mm-wave frequency band. The framework’s generality and performance in lower-frequency analog circuits, mixed-signal systems, or digital-analog co-design scenarios remain untested. This restriction may hinder broader adoption in electronic design automation, where diverse frequency domains and mixed-signal workflows are commonplace.\n\nQUESTIONS:\nQuestion 1: Can you incorporate or evaluate a richer parasitic/EM-aware surrogate (e.g., a simple analytic coupling model or pre-trained EM estimator) in your differentiable layout loss? Your current area-only proxy may underestimate critical mm-wave effects, risking larger errors in post-layout verification. The paper can include a small ablation comparing pure area loss vs. an EM-informed loss on a subset of topologies.\nQuestion 2: Have you measured variability across multiple training runs? Reporting only single-run metrics makes it hard to assess stability, especially for large GNNs. Your team should provide mean±std for key metrics (topology accuracy, forward RMSE, inversion error) over several runs.\nQuestion 3: Have you tested applying FALCON to lower-frequency analog or mixed-signal blocks? Broader applicability would greatly enhance the framework’s impact in EDA. At minimum, discuss the modifications needed or outline a small pilot on one low-frequency topology.\nQuestion 4: Given the high training cost, can you provide a “light” version (e.g., subset of 100k samples) or share pretrained weights to lower the barrier for replication? Accessibility to smaller labs/companies is critical for adoption and follow-up research. Your team can release a trimmed dataset + pretrained model checkpoint for at least one topology family.\n\nLIMITATIONS:\nNo. Suggestions for Improvement: The paper would benefit from an explicit “Limitations” section that summarizes key boundaries of FALCON’s applicability such as its reliance on a fixed topology library, simplified layout surrogate, and exclusive focus on mm-wave blocks so that readers immediately grasp where the approach may fall short.", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 3, "CLARITY": 3, "IMPACT": 3, "ORIGINALITY": 2, "DATE": "2025-07-04"}