Title: MIHC: Multi-View Interpretable Hypergraph Neural Networks with Information Bottleneck for Chip Congestion Prediction
Venue: NeurIPS 2025
Accepted: yes
Keywords: Electronic Design Automation

Hypergraph Neural Networks

Interpretable Machine Learning

Information Bottleneck

Multi-view Learning

Chip Congestion Prediction
Abstract: With AI advancement and increasing circuit complexity, efficient chip design through Electronic Design Automation (EDA) is critical. Fast and accurate congestion prediction in chip layout and routing can significantly enhance automated design performance. Existing congestion modeling methods are limited by **(i)** ineffective processing and fusion of multi-view circuit data information, and **(ii)** insufficient reliability and interpretability in the prediction process. To address these challenges, We propose **M**ulti-view **I**nterpretable **H**ypergraph for **C**hip (**MIHC**), a trustworthy 'multi-view hypergraph neural network'-based framework that **(i)** processes both graph and image information in unified hypergraph representations, capturing topological and geometric circuit data, and **(ii)** implements a novel subgraph Information Bottleneck mechanism identifying critical congestion-correlated regions to guide predictions. This represents the first attempt to incorporate such interpretability into congestion prediction through informative graph reasoning. Experiments show our model reduces NMAE by 16.67% and 8.57% in cell-based and grid-based predictions on ISPD2015, and 5.26% and 2.44% on CircuitNet-N28, respectively, compared to state-of-the-art methods. Rigorous cross-design generalization experiments further validate our method’s capability to handle entirely unseen circuit designs.

MIHC: Multi-View Interpretable Hypergraph Neural Networks with Information Bottleneck for Chip Congestion Prediction

Abstract

With the advancement of artificial intelligence (AI) and increasing integrated circuit (IC) design complexity, efficient chip design through electronic design automation (EDA) has become critical. Fast and accurate congestion prediction in chip layout and routing can significantly enhance automated design performance. Existing congestion modeling methods are limited by (i) ineffective processing and fusion of multi-view circuit data information, and (ii) insufficient reliability and interpretability in the prediction process. To address these challenges, we propose the M ulti-view I nterpretable H ypergraph for C hip ( MIHC ), a trustworthy multi-view hypergraph neural network framework that (i) processes both graph and image information in unified hypergraph representations, capturing topological and geometric circuit data; (ii) implements a novel subgraph Information Bottleneck mechanism, identifying critical congestion-correlated regions to guide predictions. This work is the first attempt to incorporate such interpretability into congestion prediction through informative graph reasoning. Experiments show that the MIHC method reduces NMAE by 16.67% and 8.57% in cell-based and grid-based predictions on ISPD2015, and 5.26% and 2.44% on CircuitNet-N28, respectively, compared to state-of-the-art methods. Rigorous cross-design generalization experiments further validate our method's capability to handle entirely unseen circuit designs.

1 Introduction

Advances in artificial intelligence (AI) and cyber-physical systems (CPS) [23] require a continuous and increasing demand for computational power supported by integrated circuits (ICs). This necessitates rapid, accurate IC design through electronic design automation (EDA)[12]. Efficient quality assessment of generated circuits is crucial to the design process [9], with circuit congestion prediction being particularly vital as it directly impacts reliability, performance, and manufacturability.

Circuit congestion occurs when routing resources are exceeded by wires attempting to traverse the same physical region [4]. This issue arises when cells (i.e., electronic components) that are logically connected by nets (i.e., connecting wires) are physically placed far apart or when many nets must share limited routing space. These situations commonly result from the mismatch between circuit connectivity requirements and physical layout constraints [10]. Therefore, accurate congestion

prediction requires comprehensive analysis of both the logical relationships between cells and nets and their geometric distribution in the physical layout [4, 20, 27].

Given this dual nature of congestion formation, circuit congestion prediction primarily involves two types of data: netlist and layout . Netlist captures logical connections between cells and nets, representing topological information naturally modeled as graphs. Layout data divides the placement area into grids containing circuit features like cell and net density, encoding geometric information in an image-like format. Effective congestion prediction requires processing and fusion of both complementary information types, as congestion patterns are determined by both connection topology and component geometric distribution.

Traditional congestion prediction approaches use rule-based systems [18] and statistical models [16], but struggle with modern circuit complexity [15]. Deep learning (DL) methods have emerged with superior performance, divided into single-view and multi-view approaches. Single-view methods include DE-HNN [14], which transforms circuit connections into hypergraphs using HGNNs [7] to capture topological information, and GAN-based approaches [26] that process grid-based features as images. However, these single-view approaches inevitably miss valuable information from the complementary perspective.

In an attempt to process both views simultaneously, CircuitGNN [24] incorporates layout information into netlist-based hypergraphs by adding position-aware edges, while Lay-Net[28] introduces specialized HGNN modules into Swin-Transformer-based layout processing. However, these methods tend to favor one view while incorporating the other as supplementary information, leading to insufficient fusion of topological and geometric information. Moreover, existing deep learning approaches operate as black boxes, lacking interpretability and trustworthiness crucial for circuit design validation[9, 12].

To address these limitations, we propose the M ulti-view I nterpretable H ypergraph for C hip (MIHC) framework, a trustworthy multi-view hypergraph neural network-based model featuring symmetrical architecture that fuses netlist and layout data through net-based bridging. Specifically, we construct cell-based and grid-based hypergraphs from respective data sources, with hyperedges in both hypergraphs built through nets, enabling balanced fusion of topological and geometric information. Furthermore, we incorporate a novel subgraph information bottleneck (IB) [17] mechanism that identifies critical congestion-correlated regions, guiding focused prediction while revealing areas needing optimization. This enhances accuracy through targeted information processing while providing interpretability by revealing critical local structures causing congestions. Such insights are particularly important since congestion typically emerges from interactions between neighboring components rather than isolated elements, offering designers actionable guidance for targeted optimization.

Contributions. The main contributions of this paper are summarized as follows: (1) Multi-View Representation Learning: We propose a novel balanced multi-view HGNN that effectively fuses netlist and layout information through net-based bridging, enabling comprehensive learning of both topological and geometric features for congestion prediction. (2) Interpretable Bottleneck Subgraph: We develop a subgraph IB mechanism that identifies critical regions highly related to congestion, providing interpretability for circuit optimization while improving prediction accuracy through focused learning. (3) Superior Prediction Performance: Comprehensive experiments on the ISPD2015 and CircuitNet-N28 datasets, including rigorous cross-design generalization evaluations, demonstrate that our model reduces NMAE by 16.67% and 8.57% in cell-based and grid-based predictions on ISPD2015, and 5.26% and 2.44% on CircuitNet-N28, respectively, compared to state-of-the-art methods. The evaluation results verify the effectiveness of our multi-view learning strategy and interpretable bottleneck mechanism.

2 Related Work

2.1 Deep Learning for Congestion Prediction

Congestion prediction involves processing two types of data: netlist data that can be naturally modeled as graphs, and layout data that can be represented in an image format. Based on how these data types are processed, existing DL approaches can be categorized into single-view and multi-view methods.

Single-View Methods. These approaches focus on processing either netlist or layout data exclusively. For netlist-based methods, CongestionNet[9] and Cross-Graph[5] model the netlists as homogeneous graphs and employ GNNs for congestion prediction, while DE-HNN[14] leverages HGNNs to capture

high-order relationships in circuit netlists. For layout-based methods, RouteNet[22] treats grid-based layout data as images and utilizes CNNs to generate congestion maps; CircuitFormer[29] regards the grids of a layout as a point cloud and uses Point Transformer to process each grid. However, these single-view approaches inevitably miss valuable information from the other perspective.

Multi-View Methods. Recent efforts attempt to incorporate both the netlist and layout information. Netlist-centric approaches like the CircuitGNN[24], LHNN[20], and HybridNet[27] construct hypergraphs from netlists and incorporate layout information through position-aware edges or nodes. Layout-centric methods such as Lay-Net[28], DFM-Net[6], and PGNN[1] primarily process gridbased layout data using vision models like U-Net while integrating the netlist information through specialized GNN or HGNN modules. However, these methods tend to favor one data type, often leading to suboptimal and insufficient fusion of topological and geometric information. In contrast, our proposed MIHC model processes both data types by constructing cell-based and grid-based hypergraphs, achieving balanced fusion through net-based bridging.

2.2 Interpretation Methods For Graph

In chip congestion prediction, interpretability has received little attention despite being crucial for identifying key performance-enhancing components and transforming black-box approaches into semi-transparent ones that users find more accessible. Since chip congestion prediction naturally involves graph-structured data with complex interactions, we examine graph domain interpretability methods. Existing approaches are primarily post-hoc, such as GNNExplainer [25] and PGExplainer [13], which provide node/edge-level explanations through learned masks but rely on post-hoc strategies for supervised tasks. Recent progress includes self-interpretable methods like SIGNET [11], which generates inherent interpretations during graph anomaly detection. Inspired by these approaches, our MIHC integrates Information Bottleneck [17] to achieve interpretability in chip congestion prediction-representing, to our knowledge, the first interpretability work in this domain.

3 Preliminaries

3.1 Problem Formulation

The circuit congestion prediction task aims to estimate the potential congestion levels in a complex circuit design based on its layout and netlist information during early design stages. Congestion can be quantified as the ratio of overflow demand to available routing tracks in IC backend design [3], where overflow represents excess routing requirements beyond provided resources.

Formally, each circuit data is represented as multi-view data comprising grid-based and cell-based information. The grid-based view models circuit layout as a structured grid P ∈ R M × N × K , where M,N ∈ N + are grid dimensions and K ∈ N + is the number of features per grid cell. The cell-based view represents the circuit at a finer granularity level based on the netlist information, where each cell corresponds to an individual circuit component with specific features. The cell-based view represents the circuit netlist as a hypergraph G = ( V, E ) , where V is the set of nodes (cells) and E is the set of hyperedges (nets connecting multiple cells). Given grid-based representation P and cell-based hypergraph G , our goal is to simultaneously predict a grid congestion map C G ∈ R M × N and a cell congestion graph C C ∈ R | V | , where C G [ i, j ] ∈ R + and C C [ k ] ∈ R + quantify congestion levels at grid ( i, j ) and cell k , respectively. The notations used in the manuscript are presented in Appendix B.

The predictive model f , parameterized by θ , is defined as follows:

with the supervised objective to minimize the mean squared error:

3.2 Information Bottleneck

The Information Bottleneck (IB) formalism [17] addresses a fundamental challenge in representation learning by extracting the minimal yet sufficient features from high-dimensional data. For example, it

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inspired new hierarchical perception methods for multimodal learning [21]. Given an input variable X and target variable Y , IB seeks an intermediate representation T that optimally balances data compression and target information preservation, formulated as:

where I ( T ; X ) and I ( T ; Y ) denote mutual information, and β ∗ ∈ R + controls the compressionrelevance trade-off. This formulation enables the identification of critical features driving model predictions while minimizing redundancy, making IB particularly valuable for model interpretability and subgraph analysis in networks [11].

4 Method

In this section, we introduce the proposed MIHC framework (see Figure 1) which consists of four parts: (a) The Process Module converts raw multi-view data, including cell-based netlist graph and grid-based layout image, into hypergraphs for further processing. (b) The Interpretable Subgraph Module introduces a novel subgraph Information Bottleneck (IB) mechanism to identify critical bottleneck subgraphs highly related to circuit congestion and guide the model to focus on these regions during prediction. (c) The Multi-View Representation Learning Module integrates both graph and image data into unified hypergraph representations, capturing topological and geometric features of circuit data. (d) The Prediction Module computes the prediction in both cell and grid views.

4.1 Process Module

Given the dual nature of the data, the Process Module converts raw multi-view data, including both cell-based netlist graph and grid-based layout image, into hypergraphs for subsequent processing.

Hypergraph Construction from Cell-based Netlist Graph. We construct a cell-based hypergraph H C = ( V C , E C ) , where V C represents circuit cells and E C represents hyperedges based on net

connections. Each node v C ∈ V C is initialized with feature X C v derived from circuit netlist characteristics. This hypergraph primarily captures topological relationships among circuit components.

Hypergraph Construction from Grid-based Layout Image. We construct a grid-based hypergraph H G = ( V G , E G ) , where V G represents local layout image regions with feature representation X G v containing each region's component density, and E G represents hyperedges connecting these regions. The formation of grid-based hyperedges e G ∈ E G is guided by spatial proximity and net connections. Hyperedges are established among nodes corresponding to spatially adjacent regions to preserve the geometric information. More importantly, nodes within the same net are grouped into hyperedges to capture high-order geometric information. Both cell-based hyperedges E C and grid-based hyperedges E G , though from different hypergraphs, are built on identical net connections-critical for fusing topological and geometric information in subsequent multi-view representation learning.

4.2 Interpretable Subgraph Module

The interpretable subgraph module is designed to identify critical parts in the circuit hypergraph and guide the model to assign more attention to these parts.

Multi-View Information Bottleneck. We develop a Multi-View Information Bottleneck (MVIB) approach combining information from both cell-based netlist and grid-based layout data. After extracting hypergraphs H C and H G , IB learns bottleneck subgraphs for each view. Taking H C as an example, the objective is to learn a bottleneck subgraph H C S by optimizing the following objective:

where β C controls compression-relevance trade-off. A similar formulation applies for H G S .

Bottleneck Subgraph Extractor. Inspired by [11], we adopt a single extractor design for both hypergraph views. The extractor processes hypergraph H C using a Hypergraph Neural Network to obtain node probabilities, modeled as p θ ( H C S | H C ) = ∏ v ∈ V C p θ ( v ∈ V C S | H C ) . The HNN outputs probability vector p ∈ [0 , 1] | V C | , enabling bottleneck subgraph extraction:

where M C is the incidence matrix of H C , X C represents the node features, and ⊙ denotes the row-wise production. The bottleneck subgraph for the grid-based view H G S can then be extracted using the mapped probability vector in the same form as Eq. (5).

Node probabilities map between views through spatial relationships. For each node v G in H G , its probability is p ∗ [ v G ] = max v C ∈N ( v G ) p [ v C ] , where N ( v G ) denotes cell nodes associated with grid node v G . This single-extractor design ensures bottleneck subgraph consistency across views while reducing complexity. The extracted subgraphs H C S and H G S preserve the most informative structures for congestion prediction, guided by the information bottleneck objective in Eq. (7).

Bottleneck Subgraph Augmentation. After extracting the bottleneck subgraphs, we leverage bottleneck subgraphs to enhance feature representations through dynamic reweighting:

where W C , W G are learnable weights, σ is the sigmoid function, and || represents concatenation. This mechanism enhances features based on bottleneck structure relevance, while residual connections ensure stable gradient flow and preserve structural information.

Multi-View Information Bottleneck Loss. The information bottleneck loss regularizes bottleneck subgraph embeddings. The objective is reformulated as:

where p θ and p γ refer to bottleneck subgraph extractors, D SKL denotes symmetrized KL divergence, and β controls the trade-off between terms. Derivations from Eq. (4) Eq.(7) are in Appendix A.

4.3 Multi-View Representation Learning Module

Given the multi-view data available, we propose a Multi-View Heterogeneous Graph Neural Network (MV-HGNN) that processes and integrates cell-based and grid-based hypergraph representations through a two-step message passing mechanism.

Node-to-Hyperedge Message Passing. For both cell-based and grid-based hypergraphs, we first aggregate node features within each hyperedge separately:

where h C e , h G e are intermediate hyperedge embeddings, V C ( e ) , V G ( e ) denote nodes in respective hyperedges, and W C v , W G v can transform features into a common semantic space.

The net-based hyperedge embedding is then obtained by first concatenating these intermediate embeddings followed by a non-linear transformation:

where h N e represents the actual net-based hyperedge embedding that captures both topological and geometric information.

Hyperedge-to-Node Message Passing. The second step updates node embeddings by aggregating information from different sources. For cell-based nodes:

where ˆ h C v , ˆ h N v are intermediate embeddings from respective hyperedges, E C ( v ) , E N ( v ) denote hyperedge sets containing node v . The final cell-based node embedding is obtained through concatenation and non-linear transformation:

For grid-based nodes, we similarly aggregate information from spatially adjacent nodes and use the previously computed net-based hyperedge information: ˆ h G v = ∑ u ∈N G ( v ) W G u h G u , where N G ( v ) represents spatially adjacent grid nodes. The final grid-based embedding:

After L message passing layers, final node embeddings serve two purposes: downstream congestion prediction and generating subgraph embeddings for contrastive learning. The subgraph embeddings are derived from previously identified bottleneck subgraphs:

This symmetric design facilitates effective congestion prediction for both views while maintaining the inherent characteristics of each representation.

Contrastive Loss. To enhance and align the interaction between cell-based and grid-based information, we employ contrastive learning. The contrastive loss is defined as:

where h C S i , h G S i form positive pairs from the same input, h G S j represents negative samples, sim ( a, b ) denotes cosine similarity, and τ controls similarity distribution sharpness.

4.4 Prediction Module

Unlike previous methods that can only produce predictions in either the cell view or the grid view at once, our method's prediction module can output predictions in both scenarios simultaneously.

Prediction. In the prediction, we obtain both h C v , the cell-based node embedding, and h G v , the grid-based node embedding. Therefore, we use two MLPs, f C and f G , to map the two embeddings to the node congestion prediction results for both views: ˆ y C v = f C ( h C v ) , ˆ y G v = f G ( h G v ) , where ˆ y C v and ˆ y G v represent the predicted node congestion values for the cell and grid views, respectively.

Total Loss. The overall loss combines contrastive (refer to Eq.(14)), supervised (refer to Eq.(2)), and information bottleneck losses (refer to Eq.(7)) to optimize the model.

Time Complexity. The overall complexity is O (( | V C | × | E C | + | V G | × | E G | ) × D × L ) , where | V C | and | V G | represent the number of cell and grid nodes, | E C | and | E G | represent their respective hyperedges, D is the hidden dimension, and L is the number of layers.

5 Experiments

In this section, we evaluate MIHC through comprehensive experiments designed to address four key research questions:

RQ1: How does MIHC's circuit congestion prediction accuracy compare to state-of-the-art methods?

RQ2: What is the MIHC's interpretability performance?

RQ3: What is the impact of MIHC's core design components on its overall performance?

RQ4: How sensitive is MIHC's performance to parameter variations?

5.1 Experimental Setup

Datasets. For chip congestion prediction, we evaluate our method on two public datasets: ISPD2015 [2] and CircuitNet-N28 [3]. ISPD2015 is divided into two variants: ISPD2015-Balanced (ISPD2015B), which excludes extremely large superblue circuits, and ISPD2015-Full (ISPD2015-F), which includes them, allowing us to assess our model's performance on data imbalance challenges. CircuitNetN28 contains over 10,000 samples (compared to ISPD2015's approximately 500), providing a more comprehensive test of our model's generalizability across diverse circuit designs.

To rigorously evaluate generalization capability, we employ two data partitioning strategies: (1) Placement-level split, where different placement solutions from the same design appear in both training and test sets, and (2) Design-level split, where training and test sets contain completely different circuit designs with no overlap. The placement-level split follows our standard 7:3 train-test ratio, while the design-level split involves bidirectional evaluation (A → B and B → A) on carefully partitioned design groups. Detailed partitioning strategies are presented in Appendix C.5.

For explainable GAD task, we use MNIST0 and MNIST1 datasets [11].

Baselines. There are two aspects of prediction tasks: cell-based prediction and grid-based prediction. To comprehensively evaluate our model, we first employ several classical graph learning models as

baselines: GCN [8], GAT [19], and HGNN [7]. Furthermore, we compare with specialized circuitoriented models: CircuitGNN [24] and LHNN [20], which are capable of handling both cell-based and grid-based predictions; DE-HNN [14], which focuses exclusively on cell-based prediction; and RouteNet [22], CircuitFormer [29] and Lay-Net [28], which specifically target grid-based prediction. To illustrate the usefulness of the model interpretability module, we chose GCN + GNNExplainer [25], GAT + GNNExplainer and SIGNET [11] as baselines.

Evaluation Metrics. For chip congestion prediction, similar to [24], we employ both regression-based metrics (NMAE and NRMS) to measure prediction accuracy and ranking-based metrics (Pearson, Spearman, and Kendall correlations) to assess prediction quality; while in interpretability module test, since the downstream task is a classification task, ACC, Precision, Recall, F1, and AUC are used to measure the accuracy of the classification.

Further details about datasets and our experiment settings are presented in Appendix C.

5.2 Chip Congestion Prediction Results (RQ1)

We present comprehensive evaluation results under both placement-level and design-level settings. The placement-level results are shown in Table 1 and design-level results are presented in Table 2, both with the best in bold and the second best underlined (More details in Appendix D.1). Given that our data encompasses both cell and grid views, we assess the validity and rationality of our model across these dual views by comparing prediction accuracy against their respective state-of-the-art (SOTA) counterparts.

5.2.1 Placement-level Results

As shown in Table 1, for ISPD2015-B, MIHC outperforms the SOTA method DE-HNN with 9.37% reduction in NMAE and 6.51% improvement in Pearson correlation at the cell level, and surpasses Lay-Net with 3.23% reduction in NMAE and 1.20% improvement in Pearson correlation at the grid level. On the more challenging ISPD2015-F with extremely large circuits, MIHC achieves even more significant gains: 16.67% reduction in NMAE and 12.21% improvement in Pearson correlation compared to DE-HNN at the cell level, and 8.57% reduction in NMAE and 3.93% improvement in Pearson correlation over Lay-Net at the grid level. These results demonstrate MIHC's robustness when handling imbalanced data distributions. The CircuitNet-N28 results, based on over 10,000 diverse samples, further confirm MIHC's generalizability with 5.26% NMAE reduction and 3.60% Pearson improvement compared to DE-HNN at the cell level, and 2.44% NMAE reduction and 1.64% Pearson improvement over Lay-Net at the grid level. This consistent performance across a substantially larger dataset validates our method's universal applicability for congestion prediction in real-world VLSI design environments.

5.2.2 Design-level Results

To rigorously evaluate generalization to entirely unseen circuit designs, we conduct additional experiments following the design-level split setting (detailed setup in Appendix C.5), where training and test sets contain completely different circuit designs with no overlap. As shown in Table 2, this setting presents significantly more challenging conditions with substantial performance degradation across all methods. Despite these challenges, MIHC maintains superior performance over baselines in the vast majority of metrics. For ISPD2015-B, MIHC outperforms DE-HNN with 7.55% reduction in cell-based NMAE and 5.68% improvement in Pearson correlation in the B → A experiments, while achieving 5.87% Pearson improvement in grid-based prediction over Lay-Net. For ISPD2015-F, MIHC achieves 6.35% cell-based NMAE reduction and 7.53% Pearson improvement in the A → B direction. These results provide strong evidence that our method achieves genuine generalization capability rather than simply memorizing design-specific characteristics, offering a realistic evaluation for real-world deployment scenarios.

5.3 Explainability Results (RQ2)

To validate the effectiveness of our model's explainability module, we examine its capability to identify important structures in chip congestion prediction scenarios. As demonstrated in Figure 2, our bottleneck subgraph successfully captures critical congestion regions, and MIHC achieves

Gound Truth

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Our Bottleneck

predictions that closely match the ground truth patterns, underscoring its superior interpretability. Additionally, the bottleneck subgraph heat map indicates that our IB bottleneck subgraph can be extracted to reveal regions relevant to the final prediction results. While node-level predictions identify congestion points, our Information Bottleneck identifies the critical local structures that cause these anomalies, revealing the structural patterns that contribute to surrounding node congestion rather than just detecting generic anomalies. This is particularly important in circuit design where congestion typically emerges from interactions between neighboring components rather than isolated elements. Due to the lack of publicly available datasets for interpretability in the EDA domain, we also briefly evaluated our model on the MNIST 0/1 dataset, where it demonstrated strong consistency across various metrics in Table 16. In comparison, baseline methods showed significant limitations: GAT+GNNExplainer suffered from low precision while SIGNET failed to capture comprehensive node relationships. These results, combined with the visual evidence from chip congestion heatmaps, confirm that MIHC not only delivers superior prediction accuracy but also provides meaningful explainability for practical VLSI design applications.

5.4 Ablation Study(RQ3)

In ablation studies, we conducted two sets of experiments on ISPD2015-B to evaluate: the contribution of different model modules (Table 3) and the impact of different loss functions (Table 4).

The ablation results of model modules in Table 3 reveal several important findings. First, removing the Multi-View Representation Learning Module (w/o MV-HGNN) results in performance similar to the basic HGNN but significantly worse than the Full Model, demonstrating the crucial role of multi-view information fusion. Second, excluding the Interpretable Subgraph Module (w/o ISM) yields better results than basic HGNN but still underperforms compared to the Full Model, with substantial decreases in correlation metrics (13.3% lower Pearson for cell-based results). Finally, the Full Model achieves optimal performance across all metrics by effectively combining ISM for critical information filtering with MV-HGNN for multi-view integration, showing impressive improvements over the baseline HGNN (19.1% Pearson improvement for cell-based results).

The comprehensive ablation results in Table 4 systematically demonstrate the effectiveness evaluation of different loss functions. The experimental results show that using both Cell and Grid Supervised loss consistently achieves better performance (NMAE=0.031 for cell-based, 0.033 for grid-based)

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compared to single-view supervision (Cell-Sup only: 0.033, 0.037; Grid-Sup only: 0.035, 0.034), thus validating the fundamental importance of multi-view information fusion by using multi-view loss. Furthermore, through detailed comparative analysis, the removal of IB loss (w/o IB Loss) leads to substantial performance degradation (Pearson correlation decreases by 4.21% for cell-based results), confirming its crucial role in guiding the model to extract essential subgraph components.

5.5 Parameters Sensitivity(RQ4)

We conduct a comprehensive hyperparameter analysis of MIHC on ISPD2015-B, specifically examining the impact of Multi-View HGNN layer number (ranging from 1 to 6) and hidden dimensions (varying from 32 to 256) on model performance. As illustrated in Figure 3, MIHC demonstrates robust stability across different hyperparameter configurations. However, notable performance degradation occurs in two specific configurations: when the model is configured with a single Multi-View HGNN layer or when the hidden dimension is set to 32. These significant performance drops can be attributed to insufficient model capacity, as either a single layer or a small hidden dimension proves inadequate for learning the complex hierarchical features and relationships inherent in the data.

6 Conclusion

This paper presents MIHC, a novel interpretable hypergraph neural network for circuit congestion prediction. Through its balanced multi-view hypergraph architecture with net-based bridging, MIHC achieves effective fusion of netlist and layout information, providing a comprehensive understanding of circuit characteristics. The incorporation of a subgraph Information Bottleneck mechanism further enhances the model by identifying critical subgraphs correlated with congestion patterns and leveraging this selective information to improve prediction accuracy. Our comprehensive experiments demonstrate MIHC's superior performance compared to existing methods, achieving significant improvements in both cell-based and grid-based prediction tasks. This synergistic combination of balanced multi-view information fusion and interpretable bottleneck analysis represents a meaningful advancement in trustworthy Electronic Design Automation, establishing a foundation for future interpretable machine learning approaches in integrated circuit design.

Limitations. While MIHC achieves significant performance improvements, there remain areas for enhancement. The Information Bottleneck mechanism, though effective for interpretability, introduces computational complexity that could be optimized with more efficient algorithms. Additionally, our comparative analysis between ISPD2015-B and ISPD2015-F indicates that performance on imbalanced datasets, while still superior to baselines, presents opportunities for improvement-a challenge shared across current congestion prediction approaches. Future work will address these aspects while maintaining MIHC's interpretability and prediction accuracy advantages.

Broader impacts. Our interpretable hypergraph model enhances EDA performance with limited impact. There is a minimal possibility that without proper validation, over-reliance risks erroneous decisions in chip design.

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A Muti-View Information Bottleneck Loss Computation

As shown in Eq (4), we can wirte the objective of the cell-based hypergraphs H C to a loss function as follows:

where β C is the trade-off parameter for L C , and we aim to minimize Eq (16) during the training. Similarily, the objective of the grid-based hypergraphs H G can be wirtten to a loss function as follows:

where β G is the trade-off parameter for L G .

Then, we compute the average loss of L C and L G , which helps us to optimize both H C S and H G S :

For term I ( H C ; H C S | H G ) , we can derive his upper bound. The conditional mutual information I θ ( H C ; H C S | H G ) is defined as:

where the Kullback-Leibler (KL) divergence is given by:

Substituting the definition of KL divergence into the conditional mutual information:

Then, we derive the upper bound of I θ ( H C ; H C S | H G ) :

I θ ( H C ; H C S | H G ) = E H C , H G ∼ p ( H C ,H G ) E H S ∼ p θ ( H C S | H C ) [ log p θ ( H C S = H S | H C = H C ) p θ ( H C S = H S | H G = H G ) ] = E H C , H G ∼ p ( H C ,H G ) E H S ∼ p θ ( H C S | H C ) [ p θ ( H C S = H S | H C = H C ) p γ ( H G S = H S | H G = H G ) · p γ ( H G S = H S | H G = H G ) p θ ( H C S = H S | H G = H G ) ] = D KL ( p θ ( H C S | H C ) ∥ p γ ( H G S | H G ) ) -D KL ( p θ ( H C S | H G ) ∥ p γ ( H G S | H G ) ) ≤ D KL ( p θ ( H C S | H C ) ∥ p γ ( H G S | H G ) ) . Similarly, we can get the upper bound for I ( H G ; H G S | H C )) :

Therefore, the upper bound for the first term is:

where D SKL ( · ) denotes the symmetrized Kullback-Leibler (SKL) divergence.

Then, look at the I ( H G ; H C S ) in the second term. According to the symmetry of mutual information, i.e., I ( X ; Y ) = I ( Y ; X ) , and the chain rule of mutual information, i.e., I ( X ; Y, Z ) = I ( X ; Y ) + I ( X ; Z | Y ) , we can have:

Since the conditional mutual information is always non-negative, we can infer:

Therefore, we can get the lower bound of I ( H G ; H C S ) as:

Similarly, for I ( H C ; H G S ) , we can get,

Therefore, the second term gets the upper bound:

Therefore, the combination loss has an upper bound:

By scaling both terms with β = 2 β C β G β C + β G and re-parameterizing the objective, we derive a tractable loss function for the MVIB framework:

where p θ ( H C S | H C ) and p γ ( H G S | H G ) represent the bottleneck subgraph extractors for H C and H G parameterized by θ and γ respectively, and D SKL ( · ) denotes the symmetrized Kullback-Leibler (SKL) divergence. The hyperparameter β controls the trade-off between the two terms.

B Mathematical Notations

Tables 5 and 6 summarize the mathematical notations used throughout the MIHC framework. Table 5 covers the fundamental problem formulation and basic Information Bottleneck concepts, while Table 6 details the components specific to multi-view representation learning and bottleneck mechanisms. Together, these notations describe the dual hypergraph structures that enable balanced fusion of topological and geometric circuit information for interpretable congestion prediction.

C Experimental Details

C.1 Code Availability.

Our code is available in this link: https://github.com/hping666/MIHC .

C.2 Hypergraph Construction Details

As shown in Figure 1(a) of our paper, we construct hypergraphs from circuit data through a specific process. In the layout example of Figure 1(a), we have 10 circuit components (cells), each represented as a node in the cell-based hypergraph. The layout is simultaneously divided into 9 grid cells, with each grid cell becoming a node in the grid-based hypergraph. The circuit nets connecting multiple circuit components are modeled as hyperedges in both representations. For the cell-based hypergraph, cells connected by the same net form a hyperedge. As illustrated in Figure 1(c) in the top-left diagram, blue cells 2, 5, 6, and 7 are connected by the same net, thus forming one hyperedge in the cell-based hypergraph.

For the grid-based hypergraph, grid cells traversed by the same net are connected via a hyperedge. Additionally, spatially adjacent grid cells are also connected through hyperedges to preserve geometric proximity information. As shown in Figure 1(c) in the bottom-left diagram, green grid cells 1, 4, 5, and 6 are traversed by the same net, thus forming one hyperedge in the grid-based hypergraph. Simultaneously, adjacent grid cells like 1-2, 2-3, 4-5, etc., would form their own hyperedges based on spatial adjacency.

C.3 ISPD-2015 Benchmark Dataset

The ISPD-2015 benchmark consists of 20 industrial designs from various applications, with circuit sizes ranging from 29K to 1.3M cells, as shown in Table 7. These designs include both standard cells and macro blocks, presenting realistic challenges in placement and routing congestion prediction. Each design in the dataset includes:

Circuit netlist information with both standard cells and macro blocks

Placement solutions generated using Cadence Innovus v17.1 with varying parameters

Ground truth congestion maps derived from global routing solutions

The dataset provides several key features for congestion prediction:

RUDY (Rectangular Uniform wire DensitY): Models the routing demand within bounding boxes of nets

PinRUDY: Represents pin density distribution in grid cells

MacroRegion: Binary indicators for regions covered by macro cells

Horizontal/Vertical MacroMargin: Measures distances between margins of adjacent macros

For experimentation purposes, 533 different placement solutions were generated for each design using Innovus with varying parameters, resulting in a comprehensive dataset for training and evaluating congestion prediction models. The dataset divides the circuit layout into an M × N grid, with each grid cell represented as a pixel containing multiple feature channels. The routing overflow ground truth is provided in both horizontal and vertical directions.

C.4 CircuitNet-N28 Benchmark Dataset

The CircuitNet-N28 is a comprehensive open-source dataset specifically designed for machine learning applications in VLSI CAD, particularly for cross-stage prediction tasks. It contains 10242

layout samples extracted from versatile runs of commercial design tools based on six open-source RISC-V designs in a 28nm technology node, as shown in Table 8.

Circuit data is generated from six RISC-V designs (RISCY, RISCY-FPU, zero-riscy, and their variants)

Layouts are generated using commercial tools (Cadence Innovus v20.10) with diverse parameter settings

Ground truth labels include congestion, DRC violations, and IR drop information

The dataset provides several key features for prediction tasks:

Macro Region: Regions covered by macros which are fixed during placement

Cell Density: Cell distribution in each tile

RUDY & Pin RUDY: Routing demand estimation for nets and pin density

Pin Configuration: High-resolution representation of pin and routing blockage patterns

Congestion: Overflow of routing demand in each tile

CircuitNet-N28 introduces significant diversity through various design parameters, including five core utilization settings (70%-90%), three macro placement strategies, eight power mesh combinations, and different filler insertion approaches. This results in 240 combinations of settings for each netlist, creating a dataset with substantial variation that better reflects real-world design scenarios. The tile size for all feature maps is 1.5 µ m×1.5 µ m, aligning with the global routing cell size in commercial tools.

C.5 Data Split Strategies

We employ two distinct data partitioning strategies to comprehensively evaluate our model's performance and generalization capability: placement-level split and design-level split.

C.5.1 Placement-level Split

The placement-level split follows a standard design-level partitioning strategy where all designs appear in both training and testing sets, but with different placement solutions. As shown in Table 7, the ISPD2015 dataset contains 20 circuit designs, each with multiple placement solutions generated using different synthesis and placement parameters. For each design, we divide its corresponding placements into training and testing sets with a 7:3 ratio. This results in:

ISPD2015-F : 374 training samples and 159 testing samples (all 20 designs including superblue series, 533 total placements)

ISPD2015-B : 269 training samples and 114 testing samples (15 designs excluding superblue series, 383 total placements)

For CircuitNet-N28 (Table 8), we follow a similar approach across its 10,242 samples from six RISC-V designs, resulting in 7,170 training samples and 3,072 testing samples, maintaining the 7:3 ratio. This approach ensures all designs appear in both training and testing sets, allowing for comprehensive evaluation of model performance on known design types.

C.5.2 Design-level Split for Generalization Evaluation

To rigorously evaluate our model's generalization capability to entirely unseen circuit designs, we conduct additional experiments following the design-level split setting. Unlike the placement-level split, this setting ensures training and test sets contain completely different circuit designs with no overlap between design families, providing a more stringent evaluation that better reflects real-world scenarios where models must generalize to new designs during deployment.

ISPD2015-B Design Partitioning For ISPD2015-B containing 15 designs, we partition them into two groups ensuring designs with the same prefix remain together:

Group A (8 designs): des_perf_1, des_perf_a, des_perf_b, fft_1, fft_2, fft_a, fft_b, edit_dist_a

Group B (7 designs): matrix_mult_1, matrix_mult_2, matrix_mult_a, matrix_mult_b, matrix_mult_c, pci_bridge32_a, pci_bridge32_b

ISPD2015-F Design Partitioning For ISPD2015-F containing 20 designs, we use a 10 vs 10 split:

Group A (10 designs): des_perf series (3 designs: des_perf_1, des_perf_a, des_perf_b), fft series (4 designs: fft_1, fft_2, fft_a, fft_b), edit_dist_a, superblue12, superblue16_a

Group B (10 designs): matrix_mult series (5 designs: matrix_mult_1, ma-trix_mult_2, matrix_mult_a, matrix_mult_b, matrix_mult_c), pci_bridge32 series (2 designs: pci_bridge32_a, pci_bridge32_b), superblue11_a, superblue14, superblue19

This partitioning strategy ensures that:

Designs with the same prefix (indicating functional similarity) remain in the same group, preventing information leakage between functionally related circuits

Both groups contain a mix of different design families and sizes

The evaluation captures the model's true capability to handle entirely unseen circuit architectures

Bidirectional Evaluation We conduct bidirectional evaluation to provide comprehensive assessment:

A → B : Train on all placement solutions from Group A designs, test on all placement solutions from Group B designs

B → A : Train on all placement solutions from Group B designs, test on all placement solutions from Group A designs

This bidirectional approach ensures our evaluation is not biased by the specific choice of training/testing groups and provides robust evidence of generalization performance across different design families.

C.6 Evaluation Metrics Details

This study employs a variety of evaluation metrics to assess the performance of the proposed model, including NMAE, NRMS, Pearson correlation, Spearman correlation, Kendall's tau for chip congestion prediction and Accuracy (ACC) for graph anomaly detection. Below are the definitions and mathematical formulations of each metric:

Normalized Mean Absolute Error (NMAE): NMAE measures the average absolute difference between predicted and true values, normalized by the range of the true values. It is defined as:

where y i is the true value, ˆ y i is the predicted value, and max( y ) and min( y ) represent the maximum and minimum values of the true data, respectively. A lower NMAE indicates better predictive accuracy.

Normalized Root Mean Square Error (NRMS): NRMS quantifies the deviation between the predicted and actual values, normalized by the range of the true values. It is computed as:

This metric penalizes larger errors more heavily, making it useful for evaluating prediction accuracy.

Pearson Correlation Coefficient (Pearson): The Pearson correlation coefficient measures the linear relationship between the predicted and true values, with values ranging from -1 (perfect negative correlation) to 1 (perfect positive correlation). It is given by:

where ¯ y and ¯ ˆ y represent the mean of the true and predicted values, respectively.

Spearman Rank Correlation (Spearman): Spearman's rank correlation coefficient assesses the monotonic relationship between the true and predicted values by considering their ranks. It is calculated as:

where d i is the difference in ranks for each pair of corresponding values, and n is the number of data points.

Kendall's Tau (Kendall): Kendall's tau is another measure of rank correlation, specifically focusing on the concordance and discordance between pairs of predictions. It is defined as:

where C is the number of concordant pairs, D is the number of discordant pairs, and n is the number of data points.

C.7 Parameter Setting

In this section, we present the key implementation details of our model. The detailed parameter settings are listed in Table 9.

The key parameters include:

Hidden Dimension : The dimension of node embeddings in both cell-based and grid-based views.

# MV-HGNN Layers : Number of Multi-View Heterogeneous Graph Neural Network layers.

# MLP Layers : Number of layers in the prediction module MLPs.

IB Weight β : The trade-off parameter in Information Bottleneck loss.

Temperature τ : Temperature parameter in contrastive learning.

# Attention Heads : Number of attention heads in message passing.

The model is trained using the Adam optimizer with a learning rate of 1e-4. We apply dropout with rate 0.1 to prevent overfitting. The batch size is set to 32 for training efficiency.

C.8 Time Consumption and Memory Usage

C.8.1 Time Consumption

Our experiments on one NVIDIA A100 80GB GPU show practical performance across circuit scales. Small circuits ( 30K cells/nets) require only 0.3 seconds for inference and 0.9 seconds per training iteration, while very large circuits (1.3M cells/nets) take 1.6 seconds for inference and 5.0 seconds per training iteration. These measurements confirm that despite the model's sophistication, its computational demands remain manageable for real-world industrial applications, with reasonable inference times even for the largest circuits.

C.8.2 Memory Usage

Our model's memory footprint scales efficiently with circuit size. Small circuits ( 30K cells/nets) consume approximately 3GB of GPU memory, while even the largest circuits (1.3M cells/nets) require 22GB during training, well within the 80GB capacity of modern A100 GPUs, ensuring our approach remains practical for industrial-scale designs.

D Result Supplement

D.1 Chip Congestion Prediction Results

D.2 Expalination Results

Due to the lack of publicly available, interpretable datasets in the EDA domain, we use the commonly adopted MNIST 0/1 dataset to demonstrate the explainability of our proposed MIHC. To validate the effectiveness of the explainability module in our model, we conduct explainability testing experiments on these datasets to test our model's capability in identifying important nodes in the graph through node-level explainability testing. The results of these tests are presented in Table 16. Our proposed method demonstrates strong consistency across both datasets, exhibiting high performance across various evaluation metrics. This suggests that our approach provides reliable and coherent explanations across different types of data, indicating that the model's interpretability is robust and can generalize well. The consistent high scores in all the key metrics underscore the model's ability to

Table 16: Node explanation test on MNIST0 and MNIST1. The best in bold and the second underlined.

offer actionable and meaningful insights for decision-making in practical applications. In comparison, baseline methods show significant limitations. GAT+GNNE suffers from low precision despite high recall, while SIGNET achieves high precision but fails to capture comprehensive node relationships, leading to low recall scores. The core principle of explainability-identifying the most important part of the graph-remains the same across both MNIST and chip congestion scenarios.

Furthermore, to demonstrate MIHC's explainability under realistic congestion scenarios, we present a chip congestion heatmap in Figure 2. This visualization highlights the model's capability to accurately localize critical regions on the chip. As clearly shown, MIHC achieves the closest match to the ground truth, underscoring its superior interpretability.

D.3 Hyper-parameter Sensitivity

Detailed results of hyper-parameter sensitivity are shown in Table 17 and Table 18.

Peer reviews:
comments: SUMMARY:
This work proposes MIHC, a new way of integrating both cell-based and grid-based circuit features to enhance congestion prediction. It also considers interpretability using an information bottleneck mechanism. The authors provide comprehensive experiments on a wide range of test cases. The tests on both ISPD2015 and CircuitNet are convincing.

STRENGTHS AND WEAKNESSES:
Strengths:
- This paper gives a comprehensive and clear comparing analysis of the existing literatures. Chip congestion prediction is a vital problem in EDA community and worth investigating.
- The interpretable subgraph module for feature fusion is intuitive. The idea of adopting nets to connect not only graph nodes, but also grid cells is an interesting and reasonable design.
- The experimental results provide a large amount of baselines and superior performance.
- I like the part C.8 since it provides detailed runtime and memory use and all those statistics. That helps readers understand the computation resource immediately and can quickly assess whether this technique is applicable to their own designs and own device.

Weaknesses:
- Could you please detail the runtime comparison with other baseline methods?

QUESTIONS:
- Is there any chance that your method could provide a method for chip congestion optimization? Like congestion-driven placement?

LIMITATIONS:
Yes
TITLE: Official Review
CLARITY: 4
IMPACT: 3
ORIGINALITY: 4
DATE: 2025-06-27

comments: SUMMARY:
This paper proposes a multi-view hypergraph neural network framework for chip congestion prediction. This framework processes both graph and image information in hypergraph representations to fuse multi-view circuit data information. This framework also implements a subgraph Information Bottleneck mechanism to identify critical congestion-correlated regions. Experiments show this framework achieves great improvement on ISPD2025 and CircuitNet-N28.

STRENGTHS AND WEAKNESSES:
**Strengths**
﻿
1. MIHC naturally and effectively fuses the cell-based and grid-based information.

2. Chip congestion prediction results (RQ1) show this framework achieves great improvement on ISPD2015-B and CircuitNet-N28.

**Weaknesses**
1. The illustration of MIHC’s interpretability performance(RQ2) is not clear.

QUESTIONS:
1. In equation (9),  $h_e^C$ and $h_e^G$ are concatenated. Does this mean cell-based and grid-based hypergraphs share the same topological structure (Because equation (9) concatenates the embedding of the same edge from two hypergraphs)? If not, how do you construct cell-based and grid-based hypergraphs to achieve this?

LIMITATIONS:
1. The Information Bottleneck mechanism introduces computational complexity.
﻿
2. Performance on imbalanced datasets (ISPD2025-F) is worse than on balanced datasets (ISPD2025-B).
TITLE: Official Review
CLARITY: 3
IMPACT: 3
ORIGINALITY: 3
DATE: 2025-07-04

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper proposes a dual hyper graph approach to congestion prediction for chip design. Congestion prediction is an important problem because during the chip design process, when wiring congestion occurs, it can require a lot of disruptive changes to the design. If it can be predicted, it can be avoided earlier in the design process and therefore save a lot of time and money while improving the quality of results. However, predicting congestion is difficult, and although many prior works have made progress on this problem, it remains challenging. This paper proposes improving the congestion prediction model by using both a netlist hypergraph as well as a layout hypergraph in order to simultaneously understand the circuit as well as the proposed layout, combining them with an information bottleneck in order to better analyze the design. The proposed approach yields impressive results on standard academic benchmarks and also provides interpretability so that engineers can analyze the design and understand how congestion arises.\n\nSTRENGTHS AND WEAKNESSES:\nThe empirical results seem strong, and the high-level components seem reasonable. The paper is also clearly written.\n\nThe biggest weakness in my mind has to do with generalization. I wasn't clear whether the paper trains a single model and tries to generalize across all designs, or whether there were separate models trained for different designs. I had questions about the training/test split from the datasets the authors created, because generally it's easier for a model to make predictions about a design if very closely related circuits are in the training set. And in this case it appears the authors split up designs so that pieces of each design were both in the training set and the test set. \nAdditionally there are quite a few components to the model and it does seem a little complex. However, that is often the case in chip design methods. \nFinally I'd like to see more about training cost and frequency.\n\nQUESTIONS:\nWhy is it ok to include subsets of the same designs in both training and test sets? \"This approach ensures all designs appear in both training and testing sets, allowing for comprehensive evaluation of model generalization capability.\" - I'm concerned this reduces the ability to comprehensively evaluate model generation.\n\nHow often do you train a new model and how much compute does it take?\n\nLIMITATIONS:\nyes", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 3, "CLARITY": 3, "IMPACT": 3, "ORIGINALITY": 2, "DATE": "2025-07-08"}