Title: Multiplication-Free Parallelizable Spiking Neurons with Efficient Spatio-Temporal Dynamics
Venue: NeurIPS 2025
Accepted: yes
Keywords: Spiking Neural Network

SNN

deep learning

spiking neuron

neuromorphic computing
Abstract: Spiking Neural Networks (SNNs) are distinguished from Artificial Neural Networks (ANNs) for their complex neuronal dynamics and sparse binary activations (spikes) inspired by the biological neural system. Traditional neuron models use iterative step-by-step dynamics, resulting in serial computation and slow training speed of SNNs. Recently, parallelizable spiking neuron models have been proposed to fully utilize the massive parallel computing ability of graphics processing units to accelerate the training of SNNs. However, existing parallelizable spiking neuron models involve dense floating operations and can only achieve high long-term dependencies learning ability with a large order at the cost of huge computational and memory costs. To solve the dilemma of performance and costs, we propose the mul-free channel-wise Parallel Spiking Neuron, which is hardware-friendly and suitable for SNNs’ resource-restricted application scenarios. The proposed neuron imports the channel-wise convolution to enhance the learning ability, induces the sawtooth dilations to reduce the neuron order, and employs the bit-shift operation to avoid multiplications. The algorithm for the design and implementation of acceleration methods is discussed extensively. Our methods are validated in neuromorphic Spiking Heidelberg Digits voices, sequential CIFAR images, and neuromorphic DVS-Lip vision datasets, achieving superior performance over SOTA spiking neurons. Training speed results demonstrate the effectiveness of our acceleration methods, providing a practical reference for future research. Our code is available at Github.

Multiplication-Free Parallelizable Spiking Neurons with Efficient Spatio-Temporal Dynamics

Abstract

Spiking Neural Networks (SNNs) are distinguished from Artificial Neural Networks (ANNs) for their complex neuronal dynamics and sparse binary activations (spikes) inspired by the biological neural system. Traditional neuron models use iterative step-by-step dynamics, resulting in serial computation and slow training speed of SNNs. Recently, parallelizable spiking neuron models have been proposed to fully utilize the massive parallel computing ability of graphics processing units to accelerate the training of SNNs. However, existing parallelizable spiking neuron models involve dense floating operations and can only achieve high long-term dependencies learning ability with a large order at the cost of huge computational and memory costs. To solve the dilemma of performance and costs, we propose the mul-free channel-wise Parallel Spiking Neuron, which is hardware-friendly and suitable for SNNs' resource-restricted application scenarios. The proposed neuron imports the channel-wise convolution to enhance the learning ability, induces the sawtooth dilations to reduce the neuron order, and employs the bit-shift operation to avoid multiplications. The algorithm for the design and implementation of acceleration methods is discussed extensively. Our methods are validated in neuromorphic Spiking Heidelberg Digits voices, sequential CIFAR images, and neuromorphic DVS-Lip vision datasets, achieving superior performance over SOTA spiking neurons. Training speed results demonstrate the effectiveness of our acceleration methods, providing a practical reference for future research. Our code is available at Github.

1 Introduction

Inspired by the biological neural system, Spiking Neural Networks (SNNs) are regarded as the third-generation neural network models [1]. By emulating neuronal dynamics and spike-based communication characteristics in the brain [2], SNNs effectively capture temporal information and achieve event-driven efficient computation, providing a novel paradigm for building the spike-based machine intelligence [3].

Spiking neurons are the key component that distinguishes SNNs from Artificial Neural Networks (ANNs) [4]. They integrate input currents from synapses to membrane potentials by complex neuronal

dynamics and fire spikes when the membrane potentials cross the threshold. These proceedings are generally described by several discrete-time difference equations [5, 6] in a formulation similar to the Recurrent Neural Networks. The discrete threshold-triggered firing mechanism induces the nondifferentiable problem and restricts the application of gradient descent methods. Recently, this problem has been resolved to a considerable degree by the surrogate gradient methods [7, 8, 9].

Deep SNNs [10, 11, 12] commonly use stateless synapses, i.e., the weights are shared across time-steps and outputs only depend on the inputs at the same time-step, to extract spatial features. Consequently, dynamic spiking neurons play a critical role in SNNs in extracting temporal features, and this has attracted many research interests. Most of the previous research focuses on increasing the neuron model complexity with learnable parameters [5, 13] or adaptive dynamics [14], which strengthens the model capacity but brings extra computation costs, making it unfriendly for resourcerestricted neuromorphic hardware. Another issue is that traditional spiking neuron models run in a serial step-by-step mode, limiting the utilization of the powerful parallel computing capabilities of Graphics Processing Units (GPUs) and resulting in a slower training speed for SNNs compared to ANNs. Recently, parallelizable spiking neuron models [15, 16, 17, 18] have been proposed that overwhelm traditional serial models in running speed, showing a promising solution to accelerate the training of SNNs.

One of the most attractive characteristics of SNNs is that the multiply-accumulate (MAC) operations between binary spikes and synaptic weights can be superseded by accumulate (AC) operations during inference in neuromorphic chips [19]. However, in previous designs of spiking neurons, the computational costs of the neuronal dynamics have not been paid much attention. For instance, the Complementary Leaky Integrated-and-Fire (CLIF) neuron [14] introduces the computationally expensive sigmoid exponentiation, the Parallel Spiking Neuron (PSN), and the masked PSN [15] rely on the dense floating-point matrix multiplication. Compared to PSN and masked PSN, sliding PSN [15] only requires convolutional operations and demonstrates superior performance in handling time series with variable lengths. However, according to the study by [15], sliding PSN only achieves comparable performance to PSN when using a large convolutional kernel size, denoted as the order of the neuron, which significantly increases computational cost and memory usage. Moreover, these neurons still rely on massive multiply-accumulate (MAC) operations between floating-point neuronal weights and input currents.

In this article, we focus on designing a new variant of parallelizable spiking neuron models with hardware-friendly dynamics, low computation cost, and high long-term dependency learning ability. We propose an enhanced neuronal architecture named Multiplication-Free Channel-wise Parallel Spiking Neurons (mul-free channel-wise PSN), whose neuronal dynamics are shown in Figure 1, and validate its performance with state-of-the-art (SOTA) accuracy on temporal datasets. Our contributions are as follows.

1) To enhance the temporal information-capturing ability, we derive the sliding PSN by applying the channel-wise separable convolutions. To solve the dilemma of large temporal receptive fields and computational costs, we use dilated convolution. Compared to sliding PSN, our improvement does not introduce any additional floating point operations (FLOPs) and significantly reduces the inference memory.

2) To avoid the costly multiplication operations, we replace them with bit-shift operations, which are hardware-friendly for resource-restricted neuromorphic chips. The theoretical energy cost and area for hardware implementation with 8-bit integers (INT8) precision under 45nm CMOS is reduced 8 × , from 0.2 pJ and 282 µm 2 to 0.024 pJ and 34 µm 2 [20], respectively.

3) We discuss the implementations of SNNs with mul-free channel-wise PSN on GPUs for efficient training. We propose an autoselect algorithm to choose the fastest implementations, which is practical for future research about accelerating parallelizable spiking neurons.

4) We achieve superior performance over other SOTA spiking neurons on various temporal tasks, validating the superior capability of the proposed methods in learning long-term dependencies.

2 Related Work

Hardware-friendly Network Design. To deploy neural network models to edge devices such as mobile phones and Field Programmable Gate Arrays with limited energy, memory, and computational

Input

𝑿 ∈ ℝ 𝑇×𝐶

Neuronal Weight

𝑾∈ℤ 𝐶×𝑘

Hidden State

𝑯 ∈ ℝ 𝑇×𝐶

𝑋[4]

𝑋[3]

𝑋[2]

𝑋[1]

𝑋[0]

𝑘 = 2

𝑑 = 2

+3

-2

-5

+1

+1

-4

𝐶

𝑇

<<1

>>2

<<1

>>1

<<

𝑆[3]

Output Spike

𝑺 ∈ {0,1} 𝑇×𝐶

Threshold

𝑽𝑡ℎ

∈ ℝ 𝐶

෍

Shift

Sum

Subtract

Heaviside

-

𝑘

𝐶

ability, a promising solution is hardware-friendly network design. Various methodologies have been proposed. Network quantization [21] quantizes the original weights and activations to low bits. Typical models in 8-bit integers require 4 × less memory consumption and achieve up to 4 × faster computation than models in 32-bit floating-point. Network pruning [22] prunes synapses and neurons to reduce the size of the model. Classic pruning methods can achieve 4 × compression ratio for ResNet-18 on ImageNet with about 5% accuracy drop [23]. Knowledge distillation [24] employs a large teacher network to supervise the learning of a small student network, and the student network can obtain a competitive or even higher performance than the teacher network. Apart from the above universal methods, SNNs [1, 25] achieve extreme power efficiency by asynchronous event-driven computation in tailored neuromorphic chips. For instance, Intel Loihi [26] consumes 48 × energy efficiency than CPUs in solving the LASSO optimization problem; Tsinghua Tianjic [19] achieves up to 10 4 times power efficiency over the Titan-Xp GPU when classifying the NMNIST dataset [27].

Spiking Neuron Models. The improvement of spiking neuron models provides a general method to upgrade SNNs, which attracts much interest in the research community. The Parametric Leaky Integrated-and-Fire (PLIF) spiking neuron [5] parameterizes the membrane time constant τ m by a sigmoid function and can learn τ m by gradient descent during training, showing better accuracy and lower latency than the traditional Leaky Integrated-and-Fire (LIF) neuron with fixed τ m . The Gated LIF (GLIF) neuron [13] assembles the learnable gate units to fuse different bio-features in the neuronal behaviors of membrane leakage, integration accumulation, and reset, achieving impressive performance by these rich neuronal patterns. The Complementary LIF (CLIF) neuron [28] introduces the complementary membrane potential into the LIF neuron, effectively capturing and maintaining information related to membrane potential decay. However, the sigmoid used in its neuronal dynamics cannot be removed during inference, which is costly for neuromorphic chips. The Parallel Spiking Neuron (PSN) family [15] and the Stochastic Parallelizable Spiking Neuron (Stochastic PSN) [16] are the first parallelizable spiking neuron models. These two models convert the iterative neuronal dynamics to a non-iterative formulation by removing the neuronal reset. Extending from PSN, several variants are proposed. The Parallel Multi-compartment Spiking Neuron (PMSN) [29] introduces multiple interacting substructures to enhance the learning ability over diverse timescales. The Parallel Spiking Unit (PSU) [30] adds a fully-connected layer with sigmoid activations inside the neuron to approximate the neuronal reset. These methods obtain performance gains over PSN in certain datasets, but increase the complexity of neuron models and slow down training speeds.

3 Preliminary

3.1 Traditional Spiking Neurons

In general, spiking neurons can be described by three discrete-time difference equations [5]:

Eq.(1) illustrates the neuronal charging process, where X [ t ] is the input current at time-step t , extracted from the original spike input via a synapse layer (e.g., convolutional neural network or multi-layer perceptron). H [ t ] and V [ t ] are the membrane potentials before charging and after resetting

at time-step t , and f is the charging equation specified for different spiking neurons. In Eq.(2), Θ( x ) is the Heaviside step function, defined as Θ( x ) = 1 for x ≥ 0 and Θ( x ) = 0 for x < 0 . When H [ t ] exceeds the threshold V th , spiking neurons will fire spikes, and the membrane potential is reset as in Eq.(3). There are mainly two types of reset methods: hard reset will force the V [ t ] to V reset , while soft reset will subtract V th from V [ t ] .

3.2 Parallel Spiking Neuron

Fang et al. [15] found that for commonly used spiking neurons with a linear sub-threshold dynamic Eq.(1), such as the Integrate-and-Fire (IF) neuron and the LIF neuron, the neuronal dynamics could be expressed in a non-iterative form after removing the reset equation Eq.(3):

where W [ t ][ i ] is determined by Eq.(1). For example, W [ t ][ i ] = τ m -1 (1 -τ m -1 ) t -i · Θ( t -i ) for the LIF neuron whose neuronal charging equation is:

Fang et al. [15] extended Eq.(4) by setting W [ t ][ i ] as a learnable parameter, and proposed the PSN with the following neuronal dynamics:

where T is the sequence length. For simplicity, we ignore the batch dimension. The PSN does not involve iteration over time-steps. The core computation of the PSN is the matrix multiplication, which is highly optimized on GPUs and can be computed in parallel. Modified from the PSN, the sliding PSN is proposed by [15] with hidden states generating from the last k inputs by a shared weight W ∈ R k across time-steps, whose neuronal dynamics are as follows:

where X [ j ] = 0 for any j < 0 and k is the order of the neuron. The sliding PSN can process input sequences with variable lengths, and the number of its parameters is decoupled with T . It can output H [ t ] at the time-step t , while the PSN can only generate outputs after receiving the whole input sequence, making it more suitable for temporal tasks.

4 Methods

4.1 Channel-wise and Dilated Convolution

In PSN and sliding PSN, the weights of the neurons are shared across all channels. However, the visualization of feature maps from an SNN conducted by [5] implies that the difference between channels is huge, e.g., one channel extracts the edges and another channel extracts the background at all time-steps (refer to Figure S4 in [5] for more details). This coarse design concept of sharing weights across channels may fail to capture the subtle disparity of features in channels. To solve this issue, we extend the weights to channel-wise.

𝑙 = 0

𝑙 = 1

𝑙 = 2

𝑙 = 3

𝑇

𝑇

(a) Fixed dilations

(b) Sawtooth dilations

To capture long-term dependency, the sliding PSN must use a large order k , resulting in a significant rise in computational cost and memory usage. We overcome this issue through the dilated convolution

log 2 𝑥

round(𝑥)

2 𝑥

sign(𝑥)

𝒬(𝑥)

𝑾

𝑾𝑞

3

2

1

0

1

2

3

0

.

8

1

.

0

1

.

2

1

.

4

Q

′

(

x

)

Q

(

x

)

-

4

-

2

0

2

4

(a) The workflow of power-of-2 quantizer.

-

-

-

(b) Using Straight-Through Estimator (STE) to redefine round ′ ( x ) will cause a discrete gradient Q ′ ( x ) .

[31], where the convolution no longer processes consecutive inputs ( ..., X [ t -2] , X [ t -1] , X [ t ]) , but instead ( ..., X [ t -2 d ] , X [ t -d ] , X [ t ]) , with d > 1 as the dilation rate.

Specifically, denote the input sequence as X ∈ R T × C , where T is the sequence length and C is the number of channels. We propose the channel-wise PSN with the following neuronal charging equation:

where W ∈ R C × k is the learnable weight, k is the order of the neuron and d ∈ N + is the dilation rate. The channel-wise PSN has identical FLOPs to the sliding PSN, and the latter can be regarded as a simplified case with setting W [0][ i ] = W [1][ i ] = ... = W [ C -1][ i ] and d = 1 in Eq.(10).

Additionally, when using multiple layers of dilated convolutions, setting the same dilation rate will lead to the grid effect. An approach to solving this issue is to assign the dilation rate using a sawtooth wave-like heuristic [32]. Specifically, when constructing SNNs with channel-wise PSNs, we start by initializing with d 0 = 1 for the first spiking neuron layer, where the superscript represents the spiking neuron layer index. Then we update d l as:

This approach ensures that after stacking multiple layers, the convolution in the time domain could effectively incorporate inputs from all time-steps. Figure 2 shows how the temporal receptive field increases with depths with (a) fixed dilations d = 1 in the sliding PSN and (b) sawtooth dilations in the channel-wise PSN. The order is k = 2 in both cases. It can be found that, with increasing depths, both neurons achieve larger temporal receptive fields. However, the sliding PSN can only capture the last 4 time-steps with 3 layers, while the channel-wise PSN can capture the last 7 time-steps.

4.2 Multiplication-Free Neuronal Dynamics

To future reduce the internal computation costs of spiking neurons, we introduce the bit-shift operation to supersede multiplication, which has been successfully employed in quantized neural networks [33, 34]. In this way, the entire network can perform inference without any multiplication operations. For multiplication of IEEE 754-defined FP32/FP16 values x with powers of 2 (denoted as w ), the operation can be converted to a lower-bit integer addition to the floating-point exponent bits [35]. For integers x multiplied by w , it can be achieved by the bit-shift operation, as shown in Eq.(12).

where << is the left bit-shift operation. In particular, when log 2 ( w ) < 0 , left shifting an negative number log 2 ( w ) of bits is actually right shifting >> | log 2 ( w ) | . To employ the bit-shift operation, we quantize W in Eq.(10) to W q , whose elements are the power of 2 , by an quantizing function Q :

where sign( x ) is the sign function and returns the sign ( 1 or -1 ) of the input x ; round( x ) is the rounding-to-nearest function. Figure 3a shows the workflow of Eq.(13).

Remarkably, the gradient of round( x ) is zero almost everywhere, and other operations in Eq.(13) are differentiable. The standard practice is to employ the Straight-Through Estimator [36] to redefine its gradient as 1:

Then the gradient of Eq.(13) is:

However, Eq.(15) is still unstable because round( x ) causes jump points and it oscillates around 0, shown in Figure 3b, which may cause the collapse. To avoid the numerical instability caused by Eq.(15), we redefine Q ′ ( x ) as a whole Straight-Through Estimator, rather than using Eq.(14) solely:

The neuron model is called mul-free channel-wise PSN when using W q in Eq.(13), and the complete neuronal dynamics is as follows, which is illustrated in Figure 1:

where V th ∈ R C is the learnable channel-wise threshold, and log 2 ( W q ) ∈ Z C × k is quantized from W by Eq.(13). Note that log 2 ( W q ) is solved beforehand and there are no log and multiplication operations during inference. Table 1 presents an analysis of the parameter and operation costs of various neurons, evaluated under T time-steps, k order and C channels.

4.3 Training Acceleration

The motivation for proposing parallelizable spiking neuron models is to solve the slow training speed of SNNs on GPUs caused by the step-by-step iterations of traditional serial neuron models. Efficient implementation of mul-free channel-wise PSN, a typical 1-D convolution described in Eq.(17), requires elaborate consideration. To tackle this, we explore the implementations under two SNN data layouts: time-first and time-last. The time-first layout ( T, N, C, ... ) , widely adopted in SNN frameworks like SpikingJelly [6], accelerates stateless layers by fusing the T (time-steps) and N (batch size) dimensions, while C denotes the channel dimension and " ... " represents any additional dimensions. In comparison, the time-last layout ( N,C,..., T ) arranges T as the last dimension.

A vanilla implementation of Eq.(17) leverages PyTorch's 1-D Convolution ( Conv1d ), which requires the shape of inputs as ( N,C,T ) . However, for both time-first and time-last layout, it is unavoidable to perform reshape operations ( T, N, C, ... ) ⇌ ( N ∗ , C, T ) and ( N,C,..., T ) ⇌ ( N ∗ , C, T ) before and after the Conv1d to satisfy the shape requirement of Conv1d , where N ∗ represents the fusion of any additional dimensions in " ... " into the N dimension. Note that physical memory is 1-D, meaning that data in nonadjacent dimensions is also stored nonadjacent in physical memory. These reshape operations involve nonadjacent dimensions and require costly memory reading/writing (R/W) operations to create a new contiguous tensor in physical memory. Figure 4 illustrates examples of reshape operations with or without memory R/W.

To address the overhead caused by costly nonadjacent reshape operations in the neuron layer, we have developed several acceleration methods. For the time-first layout ( T, N, C, ... ) , we propose two methods. One is a custom CUDA kernel that directly performs convolutions along the T dimension. Another leverages PyTorch's vectorizing map function (Vmap) to parallelize computations over the C dimension, followed by matrix multiplication (MM) to process other dimensions. For the time-last layout ( N,C,..., T ) , in addition to the custom CUDA kernel or Vamp + MM approach as in the time-first layout, we propose two additional methods. One uses the 2-D convolution to implement the 1-D convolution with the weight and stride as 1 to handle " ... " dimension. Another applies Vmap to vectorize the C dimension and employs Conv1d to handle other dimensions. Furthermore, we also

Memory R/W

Layout

shape =

𝑇, 𝑁, 𝐶

= (3,2,4)

𝑁

𝑇

𝐶

shape =

𝑁, 𝐶, 𝑇

= (2,4,3)

𝐶

𝑁

𝑇

shape =

𝑇𝑁,𝐶

= (6,4)

𝐶

𝑇𝑁

Layout

Layout

Physical Memory

Reshape Without Memory R/W

Reshape With Memory R/W

nonadjacent reshapes

adjacent reshapes

slow speed

fast speed

memory R/W

mapping between physical

memory and layout

elaborate on acceleration strategies for stateless layers in the time-last layout. Details for accelerating neuron and stateless layers are provided in Appendix A and B, respectively.

The choice of acceleration methods for neuron layers affects the data layout, which subsequently influences the performance of stateless layers. Moreover, the acceleration effect is dependent on input shapes and GPUs, making the process of selecting acceleration methods inherently empirical. To eliminate the need for manual selection, we design an autoselect acceleration algorithm, as shown in Algorithm 1. At the start of SNN training, the input sequence's shape is determined. Then the algorithm will run a benchmark over data layouts and acceleration methods, selecting the configuration with the highest execution speed. In Algorithm 1, each t l,i is evaluated through 2 m +1 repeated executions, with the average execution time of the last m iterations serving as the measured runtime for the corresponding acceleration method. As the autoselect method is invoked only once during the entire training phase, its impact on overall train time is negligible.

Algorithm 1 Autoselect acceleration algorithm

Require: An SNN stacked with L layers { M 0 , M 1 , ..., M L -1 } . The layer M l has n l optional acceleration methods. The input sequence X 0 .

1: for Ω ← {time-first, time-last}

2: Reshape X 0 to Ω

3: t Ω = 0

4: for l ← 0 , 1 , ...L -1

6: Record the current time T 0

5: for i ← 0 , 1 , ..., n l -1

7: Execute the forward propagation Y l = M l ( X l )

8: Record the current time T 1

9: Randomize a tensor Z l with the same shape as Y l

10: Record the current time T 2

12: Record the current time T 3

11: Execute the backward propagation M ′ l ( Z l )

13: t l,i = T 1 -T 0 + T 3 -T 2

15: t Ω ← t Ω +min( t l,i )

14: Choose the faster method a Ω ,l = argmin i ( t l,i )

Outputs: The layout Ω ∗ = argmin Ω ( t Ω ) and the acceleration method a Ω ∗ ,l for M l

5 Experiments

In this section, we evaluate the mul-free channel-wise PSN on various kinds of datasets. We conduct the ablation experiments on the order k and demonstrate that the sawtooth dilations can compensate for the long-term dependencies learning ability. Finally, we provide a training speed comparison to validate the efficiency of the autoselect algorithm.

5.1 Learning Long-Term Dependencies

We evaluate the long-term dependencies learning ability of mul-free channel-wise PSN in three widely used classification tasks, including the Spiking Heidelberg Digits (SHD) spoken digit dataset

[37], the sequential CIFAR dataset, and the high spatial-temporal resolution automatic lip-reading DVS-Lip dataset [38]. These datasets cover the types of voices, images, and neuromorphic events.

Comparison between our method and previous SOTA SNN methods on the SHD dataset is shown in Table 2. Specifically, we replace the LIF neurons in the SNN-delay architecture [39] with our neurons. With sawtooth dilations and order k = 2 , we achieve a test accuracy of 95 . 50 ± 0 . 36% under three seeds ( 0 , 1 , 2 ).

Sequential image classification tasks have been commonly benchmarks to evaluate spiking neurons by [40, 15, 29]. In these tasks, images are fed into the model column by column, and the number of time-step is equal to the width of the images. We also conduct experiments on sequential CIFAR10 and CIFAR100 datasets. To ensure fairness, we fully employ the network architecture and hyperparameters as [15], only replacing the spiking neurons with ours. The results are shown in Table 3, where the data for PMSN is sourced from [29], maintaining the same architecture as well, while the data for other neurons is sourced from [15]. On the sequential CIFAR10 dataset, our mul-free channel-wise PSN outperforms PSN by 2 . 72% and PMSN by 0 . 2% . Additionally, on the sequential CIFAR100 dataset, it surpasses PSN by 4% and PMSN by 0 . 13% . Notably, the order of our neurons here we report is 16, while the order of sliding PSN and masked PSN is 32, 2 × than ours.

Furthermore, we demonstrate the capability of mul-free channel-wise PSN in processing complex neuromorphic DVS-Lip dataset, which comprises 100 classes and consists of 19871 samples, each containing approximately 10 4 events with a spatial resolution of 128 × 128 . Half of the words in the dataset are visually similar pairs in the LRW dataset [41] (e.g., "America" and "American"). The training and testing sets are derived from different speakers, posing a challenge for the model to exhibit robust generalization capabilities with respect to speaker characteristics.

Currently, the SOTA accuracy of 75.3% on the DVS-Lip dataset is achieved by [42] using a Spiking ResNet-18 with the channel-wise PLIF neurons fronted, a SpikGRU2+ backend, and events are integrated into 90 frames ( T = 90 ). In our experiments, we introduce several modifications to the frontend. We replace the PLIF neurons with our neurons and remove spiking neurons from the pooling layers, referring to this architecture as Modified Spiking ResNet-18. As Table 4 shows, our method achieves 70.9% accuracy and is only second to [42] with SpikGRU2+ backend. It is worth noting that SpikGRU2+ is bi-directional with two groups of separate hidden states, employs sigmoid gates with floating activations, and outputs ternary spikes ( -1 , 1 , 0 ), which is not a pure SNN module and might be difficult to deploy to neuromorphic chips. The accuracy we report here is based on the neuron order k = 2 and sawtooth dilations, indicating that our method can effectively capture rich historical information with a small order even when handling tasks involving long-time sequences.

17.8654

23.0475

27.4735

44.1847

88.1255

28.238

42.1026

493.0139

623.137

881.8755

44.0952

771.6241

887.3643

1119.7214

1379.3742

1413.3727

1696.0142

15.0693

25.3319

45.8241

84.9146

181.0693

24.6782

45.5955

77.6099

231.6537

46.4084

78.2273

193.8566

1

10

100

1,000

2

4

8

16

32

training duration (

𝑠

/epoch)

PSN/Sliding PSN

𝑘 = 2

)

𝑘 = 4

)

𝑘 = 8

)

Autoselect (

𝑘 = 8

)

Autoselect (

𝑘 = 2

)

Autoselect (

𝑘 = 4

)

the number of time-steps

𝑇

5.2 Ablation Study

To validate that our neurons can effectively approximate the effect of a larger receptive field with a smaller order k through sawtooth dilations, we conduct ablation experiments on the sequential CIFAR100 and pixel CIFAR10 classification tasks.

Figure 5 (a) illustrates the accuracy curves of mul-free channel-wise PSN and other neurons on the sequential CIFAR100 dataset, with the highest accuracy marked by a red ★ . When the order is 2, the accu-

(a) Sequential CIFAR100

(b) Pixel CIFAR10

order

order

accuracy

accuracy

racy of our neuron already significantly surpasses the whole PSN family. Furthermore, when the order increases to 3 or more, the accuracy remains roughly around 66%. It is evident that our neuron is more robust than the sliding PSN, as it does not exhibit the issue of fluctuating accuracy while increasing order.

To evaluate the effectiveness of sawtooth dilations, we conduct an ablation study on the pixel CIFAR10 classification task. In this task, images are flattened into one-dimensional vectors as time series inputs to the network. Thus, the number of time-step is T = 1024 . We adopt the same network structure as [29]. Figure 5 (b) illustrates the accuracy curves with/without sawtooth dilations. It can be observed that the accuracy with sawtooth dilations is consistently higher than that without. Additionally, when the order k is small, which is a practical case for deployment, the accuracy of our neuron with sawtooth dilations is much higher. These results validate that the sawtooth dilations compensate for the effect of large receptive fields when using a small k .

5.3 Training Acceleration

We compare the training speed of PSN and the mul-free channel-wise PSN implemented by the autoselect Algorithm 1. The vanilla implementation, using reshape and Conv1d operations for neuron layers and time batch dimension fusion for stateless layers, is also compared. The experiments are carried out on a Debian GNU/Linux 11(bullseye) server with an Intel(R) Xeon(R) Platinum 8336C CPU, an Nvidia A100-SXM4-80GB GPU and 32GB RAM. Following the original PSN [15] settings, we use the batch size of 128 on the CIFAR dataset.

The training duration ( s /epoch) of different neurons under different order k on CIFAR100 is shown in Figure 6. Note that both PSN and sliding PSN are implemented by matrix multiplication in GPUs [15], their speeds are identical and decoupled with k . The results show that our autoselect algorithm greatly improves the efficiency of mul-free channel-wise PSN and achieves a much faster training speed than the vanilla implementation. When T ≤ 4 , our method is comparable to PSN/sliding PSN. In this case, the matrix is nearly stripped in PSN/sliding PSN because T is much less than other dimensions, causing inefficient matrix multiplications. When T continuously increases, our method is slower, which is caused by the fact that the quantization induces additional overhead, and memory R/W caused by Vmap operations for processing inputs/outputs in our SNNs is slower than

the dimension fusion. Nonetheless, the speed gaps are not significant. The autoselect algorithm itself introduces only negligible time overhead, contributing 1 . 17% , 0 . 39% , 0 . 27% for T = 2 , 8 , 32 , respectively. Further results for different batch sizes and GPUs can be found in Appendix G.

5.4 Inference Memory Analysis

Both our approach and sliding PSN require storing an input sequence whose length is proportional to the neuron order k . According to [15], sliding PSN typically needs a large k to maintain stable performance on long-term dependencies. In contrast, our method can achieve more stable and better performance with a much smaller k , as shown in Fig. 5. By substantially reducing the required neuron order, our approach shortens the length of the stored input sequence and significantly lowers memory consumption during inference. As demonstrated in Table 5, this leads to a substantial reduction in memory overhead for storing input sequences, making our solution more suitable for deployment on resource-constrained devices.

5.5 Inference Energy Estimation

Assume implemented on the 45 nm CMOS technology, where a 32-bit floating-point (FP32) multiplication (MUL) and addition (ADD) operation consumes 3 . 7 pJ and 0 . 9 pJ, respectively [44]. In comparison, for the shift operation of a 32-bit fixed-point (FIX32) and a power-of-two number, it requires only 0 . 13 pJ [44]. For the multiplication of a FP32 number with a power-of-two number, it can be performed by one single lower-bit integer addition, which is also energy efficient [35]. Here we use the FIX32 shift energy as an approximation. Based on the sequential CIFAR100 models (see Appendix D), we estimate the average computational energy of PSN and our method for processing a single CIFAR100 image, as shown in Table 6. Our method achieves nearly 9 × lower energy consumption compared to PSN, demonstrating a significant advantage in hardware efficiency. Notably, our energy estimation considers the cost of neuronal layers, whereas most previous studies only account for synaptic layers. Moreover, we observe that for PSN, the energy consumption of the neuronal layer is significantly higher than that of the synaptic layer, which is mainly due to the dense floating-point matrix multiplications involved. Details of the energy estimation procedure can be found in Appendix F.

6 Conclusion

In this paper, we introduce a novel parallelizable spiking neuron model named mul-free channelwise PSN, which employs the channel-wise convolutions to process the input sequences, avoids the large neuron order by sawtooth dilations, and gets rid of floating multiplications by efficient bit-shift operations. The considerations of accelerating the training of SNNs with the proposed neuron models are also discussed in detail. Experimental results demonstrate that mul-free channel-wise PSN achieves significant performance improvements in temporal classification tasks, showcasing its superior capability to capture long-term dependencies. Our methods solve the dilemma of performance and computational costs of spiking neuron models, and our acceleration methods will benefit future research as a practical reference.

Acknowledgments and Disclosure of Funding

This work is supported by National Science and Technology Innovation 2030 Major Project (No. 2025ZD0215501), Guangdong S&T Programme 2024B0101010003 and National Natural Science Foundation of China (62236009).

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Appendix

A Acceleration Details of Spiking Neuron Layer

A.1 Acceleration Methods

Based on the aforementioned background, we design the following accelerating implementations as candidates:

Time-last + Vmap + Conv1d : this method uses the vectorizing map function ( Vmap ) in PyTorch to vectorize Conv1d to process the input sequence with the ( N,C, ∗ , T ) layout over the " ∗ " dimension. The reshape operations ( N,C,..., T ) ⇌ ( N,C, ∗ , T ) are nearly cost-free because the reshaped dimensions are adjacent physically.

Time-last + Conv2d : this method is similar to the implementation (1), but processes the input sequence with the ( N,C, ∗ , T ) by Conv2d and sets the weight and stride in the " ∗ " dimension as 1, rather than by Vmap .

Time-first/last + Vmap + MM : this method uses Vmap to vectorize matrix multiplication ( MM ) to process inputs over channels ( c in Eq.(17)). Refer to Appendix A.2 for more details about how the weights for MM are generated.

Time-first/last + Custom CUDA Kernel : this method avoids reshape operations and can be used for any memory layout. However, the convolutions in PyTorch are highly optimized, i.e., implemented by the official NVIDIA CUDA Deep Neural Network (cuDNN) library, which might be much faster than custom implementations. Refer to Appendix A.3 for more details.

Note that if the spiking neuron layer implementations adopt the time-last layout, the stateless layers should also use the same layout. Otherwise, reshape operations between time-first and time-last layouts will cause great latency. Correspondingly, the time batch dimension fusion method to accelerate stateless layers in SpikingJelly cannot be applied. In Appendix B, we fully discuss the acceleration method of the stateless layer for the time-last layout.

A.2 Details of Time-first/last + Vmap + MM

In Eq.(17), weight of the standard 1D convolution W q is shaped as [ C, k ] . The standard 1D convolution operation could be implemented by matrix multiplication and vectorizing map. When the input sequence X ∈ R T × N arrives, where the sequence length T is known, for the time-first data layout, the weight matrix A ∈ R C × T × T can be generated as:

where [:] means the slice operation.

Similarly, for the time-last data layout, the weight matrix A ∈ R C × T × T can be generated as:

Applying the vectorizing map to the input sequence and the weight matrix across the channel dimension, the membrane potential H can be calculated through the matrix multiplication operation over channels in parallel:

A.3 Details of Time-first/last + Custom CUDA Kernel

Suppose X is the input sequence, H is the hidden states, and δ H is the gradient with respect to H , obtained by automatic differentiation in PyTorch, all of them are shaped as ( T, N, C, H, W ) or

( N,H,W,C,T ) . Suppose W and b are the weight and bias of the convolution, shaped as [ C, k ] and [ C ] , respectively.

The process of forward propagation can be represented as:

where pad represents padding k -1 zeros on the left of X over the time dimension T , and ⋆ denotes the convolution operation on the T dimension of X using W .

The process of backward propagation can be represented as:

where flip ( W ) represents flip W left and right along the k dimension.

Beyond PyTorch (cuDNN), a custom CUDA implementation for two data layouts is also considered. To avoid the reshape and incident memory copying, we design CUDA kernels by OpenAI Triton for processing both data layouts directly. Specifically, we manually implement the Eqs.(22)-(25) using the Triton framework. We design a custom autograd function, where the aforementioned kernel functions are called in the forward and backward methods. Note that the convolution operation in Eq.(23) is consistent with that in Eq.(22), so the triton kernel function remains the same. Taking the time-first layout as an example, Eq.(22) and (24) could be implemented as Algorithms 2 and 3, respectively.

Algorithm 2 Triton forward kernel

Input: The input sequence pointer X ptr , weight matrix pointer W ptr , the output sequence pointer H ptr , point to the first address of tensors, shaped ad [ T + k -1 , N, C, H, W ] , [ C, k ] and [ T, N, C, H, W ] , respectively.

1: Utilize the triton autotune method to determine the BLOCK_SIZE_NHW ( BN ) and BLOCK_SIZE_C ( BC )

2: Calculate the offset X offset , W offset and H offset of each thread, shaped as [ BN,BC,T,k ] , [1 , BC, 1 , k ] and [ BN,BC,T ] , respectively

3: Load values of X ptr + X offset and W ptr + W offset from memory to SRAM tensors X and W

4: Utilizing the broadcasting mechanism, perform the element-wise multiplication of X and W

5: Sum the output H along the k dimension

6: Store the values of H to H ptr + H offset address

Algorithm 3 Triton grad of weight kernel

Input: The grad of output pointer O ptr , the input sequence pointer X ptr , the grad of weight pointer W ptr , point to the first address of tensors, shaped ad [ T, N, C, H, W ] , [ T + k -1 , N, C, H, W ] and [ C, k ] , respectively.

1: Utilize the triton autotune method to determine the BLOCK_SIZE_NHW ( BN ) and BLOCK_SIZE_C ( BC )

2: Calculate the offset O offset , X offset and W offset of each thread, shaped as [ BN,BC,T, 1] , [ BN,BC,T,k ] and [ BC,k ] , respectively

3: Load values of O ptr + O offset and X ptr + X offset from memory to SRAM tensors O and X

4: Utilizing the broadcasting mechanism, perform the element-wise multiplication of O and X

5: Sum the grad of weight W along the T and k dimensions

6: Atomic add the values of W to W ptr + W offset address

B Acceleration Details of Stateless Layer

Stateless layers include the convolutional, batch normalization, pooling, and linear layers. When using the time-first data layout, the stateless layers can be accelerated by fusing the time dimension and the

batch dimension in SpikingJelly. More specifically, the data layout changes as ( T, N, ∗ ) ⇌ ( TN, ∗ ) before and after processing of the stateless layers. Then GPUs regard the time-step dimension as the batch dimension, leading to fully parallel computing over time-steps. It is worth noting that the dimension fusion is nearly no cost because the time and batch dimensions are physically adjacent in memory. The reshape operation only changes the view of tensors and does not involve memory copying.

When using the time-last layout, the dimension fusion method of SpikingJelly cannot be applied except for the batch normalization layer, which only requires that the channel dimension be the 1-th dimension. Both layouts can be satisfied by a reshape without additional memory R/W. For the convolutional and pooling layer, we introduce two new methods: the vectorizing map provided in PyTorch and the high-dimension convolution/pooling that has been used in the Lava framework, a software framework for neuromorphic computing.

The vectorizing map vectorizes the stateless layers to process the input sequence with the ( N,..., T ) layout over the last dimension T , then the computation over time-steps is in parallel. This method actually implies a reshape operation ( N,..., T ) ⇌ ( T, N, ... ) when splitting and concatenating the sequence. The high-dimension convolution/pooling uses the ( n +1) -D convolution/pooling to implement the n -D convolution/pooling with a weight of 1 and a stride of 1 in the additional dimension. This method is also in parallel, while the main drawback is that the high-dimension convolution/pooling is complex and not as efficient as the dimension fusion method [6].

C Neuron Quantization

To reduce the internal covariate shift along the temporal and batch dimensions, and increase the numerical stability of the model, we use batch normalization to implement the learnable threshold V th . Eq.(18) could be rewrite as:

where γ ∈ R C and β ∈ R C are the learnable weight, initialized as 1 and -1 . µ B ∈ R C and σ 2 B ∈ R C are the mean and variance of the input over the dimension C . Specifically, at train time, they are the mean and biased variance of the input sequence; at inference time, they are the moving average of the mean and unbiased variance of the input sequence on the training stage, which means µ B and σ 2 B are invariant during inference.

Since our quantization goal is to use the efficient bit-shift operation to replace the multiplication, the convolution layer and the batch normalization layer could be fused to reduce computation during inference, so we need to quantize the fused weights during training. The formula for the fusion of convolution and batch normalization can be represented as follows:

Thus, W in Eq.(13) is actually W f in Eq.(27). To implement the quantization of fused weight, during the training stage, input sequence X is first passed to the convolutional layer, resulting in the intermediate variable T to update the µ B and σ 2 B in Eq.(27) and Eq.(28). Then, we use W f as W in Eq.(13) and b f as V th in Eq.(18), perform the convolution operation on the input X twice. After the training is completed, µ B and σ 2 B is fixed, so we could directly use the quantized W f and b f as the weight and bias of the convolution layer, performing the convolution operation only once.

D Network Structure

Table 7 illustrates the details of the network structure for different datasets. c128k3s1 represents convolution layer with output channels = 128 , kernel size = 3 and stride = 1 , BN is the batch normalization. SN is the mul-free channel-wise PSN, APk2s2 is the avg-pooling layer with kernel

size = 2 and stride = 2 , FC256 represents the fully connected layer with output feature = 256 . RB128 is the residual block with output channels = 128 , Dcls256 is the dilated convolution with learnable spacings with output channels = 256 , DP is the dropout layer. LIF(Vth=1e9) represents a LIF spiking neuron the threshold = 1 e 9 , and the membrane potential is the output, which could be thought of the moving average of the input current. 3D_c64k577s122p233 represents the 3D convolution layer with output channels = 64 , kernel size = (5 , 7 , 7) , stride = (1 , 2 , 2) and padding = (2 , 3 , 3) . AAPk1 is the adaptive avg-pooling layer with output feature = 1 . Stateful FC 100 is an FC layer with stateful synapses.

E Setting of Experiments

The main hyper-parameters for different datasets are shown in Table 8. Other training options are listed as follows.

Sequential CIFAR The data augmentation techniques include random mixup with p = 1 and α = 0 . 2 , random cutmix with p = 1 and α = 1 , random choice between the two mix methods with p = 0 . 5 , random horizontal flip with p = 0 . 5 , trivial augmentation, normalization, random erasing with p = 0 . 1 , and label smoothing with the amount 0 . 1 [15]. The number of channels is 128 . The surrogate function is the arctan surrogate function σ ( x ) = α 2(1+( π 2 αx ) 2 ) with α = 2 .

Pixel CIFAR All parameters and experimental settings are the same as Sequential CIFAR.

SHD Augmentation methods include spatio jitter with var 0 . 55 , uniform noise with number n = 35 , drop event with p = 0 . 05 , drop event chunk with p = 0 . 3 and max drop chunk length l = 0 . 02 . The surrogate function is also the arctan surrogate function with α = 5 .

DVS-Lip The data augmentation techniques include center cropped size = 96 × 96 , then random cropped size = 88 × 88 , random horizontal flip with p = 0 . 5 , 2D spatial mask with mask num = 4 and maximum length = 20 , random choice between zoom in and zoom out with p = 0 . 5 and max scale = 26 , temporal mask with mask num = 6 and maximum length = 18 [42]. The surrogate function is σ ( x ) = 1 1+ αx 2 with α = 10 .

F Details of the Energy Estimation

By combining the neuron operation counts in Table 1 with the corresponding per-operation energy consumption, the theoretical neuronal energy consumption can be estimated, as shown in Table 9.

·

×

·

×

·

When the neuron order k reaches its maximum value T , the maximum theoretical energy consumption of our neuron is 0 . 515 T 2 +1 . 415 T , which is approximately 9 × lower than that of PSN for large T . This result clearly demonstrates the superior energy efficiency of our approach in hardwareconstrained scenarios.

Further, we use the sequential CIFAR100 Network structure (see Appendix D for more details) to evaluate the energy consumption on a single CIFAR100 Image. Following [11], we use Eq.(29) to calculate the energy of synaptic layers, where FL 1 SNNConv is the FLOPs of the first layer to encode static RGB images into spike-form, N is the number of convolutional layers, and M is the number of fully connected layers. fr in Eq.(30) is the firing rate of the input spike sequence of every synaptic layer, and here is the average value of the trained network across the entire test dataset. Assume the MAC and AC operations are implemented on the 45nm hardware, E MAC = 4 . 6 pJ and E AC = 0 . 9 pJ . Following the experimental setup specified in Table 3, the neuron order k of our neuron is 16 . Detailed energy analysis is shown in Table 6, where the FLOPs and SOPs of the synaptic layers refer to the FL 1 SNN Conv and ( ∑ N n =2 SOP n SNN Conv + ∑ M m =1 SOP m SNN FC ) in the Eq.(29), respectively.

G Experimental Results

Table 10 presents the original data depicted in Figure 5, illustrating the performance of mul-free channel-wise PSN across varying orders and datasets.

In addition, we report extra results on the H20 GPU and the A100 GPU with different batch sizes in Tab.11. The results and conclusions are consistent with using the A100 GPU and batch size 128. Notably, the training duration of our neuron is with the quantization operation, i.e., perform the convolution operation twice, so it is inherently slower than PSN on the training stage.

For the training speed across different neuron implementations (PSN, vanilla, and autoselect), each method is trained for two epochs, and the training durations of the second epoch are set as the results. In this way, the results have accounted for statistical validity and warm-up of GPUs and eliminated the influence of model loading and other initialization processes. Hence, the reported speed is the speed at the steady state .

Training

Test

accuracy

accuracy

In Figure 3b, we mention that the gradient of Eq.(15) has jump points, which is detrimental to the network. On the sequence CIFAR dataset, we find that the network is still able to learn quite well. However, on the DVS-Lip dataset, as shown in Figure 7, using the original ste gradient causes the network to crash, resulting in the training and testing accuracy suddenly dropping to 1% . The reason is that the gradients appear to be the Not a Number (NaN) values.

H Limitations

Although we have designed multiple acceleration methods that significantly improve the training speed of the vanilla mul-free channel-wise PSN, its training speed is still slightly slower than that of PSN. This is mainly due to the additional overhead induced by quantization, and the memory read/write operations caused by Vmap during input/output processing in our SNNs being slower compared to dimension fusion. Nonetheless, the speed gap is not significant.

NeurIPS Paper Checklist

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Question: Does the paper report error bars suitably and correctly defined or other appropriate information about the statistical significance of the experiments?

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Justification: The effectiveness of the autoselect algorithm is evaluated based on the average runtime of multiple executions of each acceleration strategy. The paper reports the results averaged over different random seeds for the SHD dataset and uses the baseline methods' random seed settings for other datasets to ensure fairness and reproducibility.

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Peer reviews:
{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper introduces a novel multiplication-free, channel-wise Parallel Spiking Neuron (PSN) model to improve the training efficiency of Spiking Neural Networks (SNNs), particularly in resource-constrained neuromorphic applications. Unlike conventional spiking neuron models that rely on serial iterative updates or costly high-order approximations, the proposed neuron model offers hardware-friendly acceleration by eliminating multiplications and enabling channel-level parallelism. The method is evaluated on neuromorphic audio (Spiking Heidelberg Digits), vision (DVS-Lip), and sequential image (CIFAR) datasets, achieving competitive or superior accuracy and demonstrating significant training speedups over prior SOTA neurons.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths:\n\n1. Important Problem Area:\nThe work targets a key bottleneck in neuromorphic computing—efficient training of SNNs—by addressing both latency and resource usage, which are crucial in embedded or real-time SNN deployment.\n\n2. Hardware-Friendly Design:\nThe design eliminates multiplication operations, aligning well with the constraints of edge neuromorphic hardware and making it more suitable for low-power, high-efficiency environments.\n\nWeaknesses:\n\n1. Unclear Practical Impact of GPU Speedup:\nThe reported training speedups on a high-end A100 GPU may not convincingly reflect practical gains, especially given that CIFAR training is already fast on such hardware. Since the main selling point is hardware efficiency, evaluations on actual neuromorphic processors (e.g., Loihi, SpiNNaker) or low-resource edge devices would provide more meaningful insights.\n\n2. Lack of Benchmark Diversity at Scale:\nThe paper does not include results on larger-scale datasets such as ImageNet. Demonstrating effectiveness at scale would further validate the method’s generalizability and robustness.\n\nQUESTIONS:\n1. What is the speedup of this new training method on embedded or low-end GPUs?\n\n2. What is the accuracy of this new training method on other datasets such as imagenet?\n\nLIMITATIONS:\nyes", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 3, "CLARITY": 3, "IMPACT": 2, "ORIGINALITY": 2, "DATE": "2025-06-20"}

comments: SUMMARY:
This paper proposes a novel spiking neuron model called the mul-free channel-wise Parallel Spiking Neuron, designed to improve the training speed and efficiency of SNNs while maintaining strong long-term dependency modeling.
Key innovations include the use of channel-wise convolution to improve representational capacity, sawtooth dilations to reduce model order (and thus complexity), and bit-shift operations to eliminate costly multiplications.
Experiments show superior performance compared to existing state-of-the-art spiking neurons, along with demonstrated improvements in training speed.

STRENGTHS AND WEAKNESSES:
## Strengths
1. I think it is important for the model to be explicitly designed to leverage GPU parallelism, addressing one of the long-standing challenges in SNN training.
2. Experiments are conducted on multiple benchmark datasets, showing broad applicability and state-of-the-art results.
3. The theory of the proposed method is complete.

## Weaknesses
I want to know:
1. Is the bit-shift replacement of multiplication universally applicable? Or does it introduce constraints on precision or dynamic range in practice, like FP-16, or other precisions?
2. How does the proposed model balance sparsity with dense operations like channel-wise convolution? 
3. Has the proposed method been evaluated on real neuromorphic hardware (e.g., Loihi)? If not, how were the energy and latency benefits estimated?

QUESTIONS:
Please refer to the weaknesses.

LIMITATIONS:
Yes.
TITLE: Official Review
CLARITY: 3
IMPACT: 3
ORIGINALITY: 3
DATE: 2025-06-30

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper redesigns the core neuron architecture of SNNs by combining per-channel separable convolution, zig-zag dilated convolution, and replacing multiplications with shift operations—augmented by an automated benchmarking system to select the optimal implementation - thereby achieving a multiplier-free design that efficiently captures long-range dependencies while remaining hardware-friendly. Experiments on SHD, sequential CIFAR, and DVS-Lip tasks reach or approach state-of-the-art performance, and training speed rivals that of traditional matrix multiplication.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths: \nThe manuscript is well-written, logically rigorous, and clearly presented. This work makes a significant contribution to the field of parallel SNN neurons by avoiding expensive multiplications to accelerate and reduce the energy consumption of SNN computations, while also achieving competitively strong algorithmic performance.\n\nWeaknesses: \nEven though I think this paper is excellent, the method lacks evaluation on more advanced architectures such as Spikformer.\n\nQUESTIONS:\n1.\tBy replacing all weights with power-of-two shifts, you remove multipliers—but real weights can be any real number. Have you quantified how much representational capacity you lose, especially for small or negative weights?\n2.\tHow much memory do operations like reshape, depthwise + pointwise convolutions, and dilation actually consume in large models or with long sequences? The paper only reports training speed, but I believe training memory usage is what most researchers care about.\n3.\tDepth-wise + pointwise separation slashes parameters, but it also forces each channel’s temporal filter to be independent before mixing. Could that break important cross-channel correlations in the input spike train? \n4.\tIn the Introduction, the authors claim that the method achieves significant energy savings, but the paper provides no analysis or experiments on energy consumption, nor is any such content found in the supplementary materials.\n5.\tWhile accelerating training is certainly important, for deployable methods acceleration during inference is even more critical. Have the authors evaluated whether this method’s inference speed offers sufficient advantages over PSN-based or sliding-PSN models with comparable parameter counts\n\nLIMITATIONS:\nYes.", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 3, "CLARITY": 4, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-02"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nTraditional neuron models involve iterative step-by-step dynamics (implemented like RNN) which slow down computation. For some popular neuronal dynamics (like IF and LIF), one can express these dynamics in a way that allows for parallel computation as noted by Fang et al. [15]; in particular one can calculate how the membrane potential evolves over time without the resetting mechanism as in eq. (6) and calculate the binary spikes as in eq. (7) with learnable thresholds whose dimension is T (the number of time steps). The sliding PSN proposed by [15] uses shared weights of size k which convolve over the input sequence, allowing this model to use fewer weight parameters and handle variable length sequences (and not just T). This work builds on the sliding PSN of [15] by making the following changes: 1) first, this work uses a dilated convolution processing non-consecutive inputs and sets the dilation rates using a sawtooth wave-like heuristic (eq. (11)) and 2) replace multiplication with bit-shift operations and 3) quantize the the weights W. The authors also propose an autoselect algorithm (Algorithm 1) to choose amongst different acceleration options, which depend on data input shapes and GPUs. Finally, the authors apply these changes to SOTA SNN models for experimental validation, using the same architecture and hyperparameters as in [38] and [15] and benchmarking the results on a few datasets including SHD, (sequential) CIFAR10, CIFAR100, and DVS-Lip.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths:\n- The experiments seem to show SOTA performance on a few benchmarks (namely SHD, CIFAR10, CIFAR100). \n- The method appears to be practical and (relatively) simple, which seems like it would be useful to many practitioners if the code/implementation were to be integrated into existing libraries.\n\nWeaknesses:\n- I feel that a lot of the ideas in this paper are not necessarily very “new” but pieces together many existing (known) techniques and put them together on top of the existing sliding PSN model/framework\n- The justification for using the straight-through estimator for Q’(W) (and not considering any other methods) was a bit weak, especially considering the previous point. (STE is very simple to use is a first option to try.) Other methods for dealing with discontinuous and almost zero everywhere gradients exist, such as through using smooth surrogates. \n- The improvements in test accuracy seem material but mild, and the uncertainty/error bars are not always reported for the authors’ work (I understand it may not always be available in other works, but having a sense of how tight the error bars are would help interpret some of the results), such as in Table 3 and 4.\n- There doesn’t seem to be any indication that the code will be released publicly, which I think if done would strengthen the paper.\n\nQUESTIONS:\nIn Figure 6, when comparing to PSN/Sliding PSN it is explained that this work is slower for T > 4. In the introduction, it is explained that the purpose of this work is to address the computational and memory limitations of sliding PSN. Could the authors perhaps comment more on these tradeoffs?\n\nLIMITATIONS:\nyes", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 1, "CLARITY": 3, "IMPACT": 3, "ORIGINALITY": 2, "DATE": "2025-07-17"}