Title: High-Performance Arithmetic Circuit Optimization via Differentiable Architecture Search
Venue: NeurIPS 2025
Accepted: yes
Keywords: Arithmetic Circuit Optimization

AI for Electronic Design Automation

Differentiable Architecture Search
Abstract: Arithmetic circuit optimization remains a fundamental challenge in modern integrated circuit design. Recent advances have cast this problem within the Learning to Optimize (L2O) paradigm, where intelligent agents autonomously explore high-performance design spaces with encouraging results. However, existing approaches predominantly target coarse-grained architectural configurations, while the crucial interconnect optimization stage is often relegated to oversimplified proxy models or a heuristic approach. This disconnect undermines design quality, leading to suboptimal solutions in the circuit topology search space. To bridge this gap, we present **Arith-DAS**, a **D**ifferentiable **A**rchitecture **S**earch framework for **Arith**metic circuits. To the best of our knowledge, **Arith-DAS** is the first to formulate interconnect optimization within arithmetic circuits as a differentiable edge prediction problem over a multi-relational directed acyclic graph, enabling fine-grained, proxy-free optimization at the interconnection level. We evaluate **Arith-DAS** on a suite of representative arithmetic circuits, including multipliers and multiply-accumulate units. Experiments show substantial improvements over state-of-the-art L2O and conventional methods, achieving up to $\textbf{27.05}$% gain in hypervolume of area-delay Pareto front, a standard metric for evaluating multi-objective optimization performance. Moreover, integrating our optimized arithmetic units into large-scale AI accelerators yields up to $\textbf{6.59}$% delay reduction, demonstrating both scalability and real-world applicability.


Peer reviews:
{"IS_META_REVIEW": false, "comments": "SUMMARY:\nArithmetic circuit design is the basis of modern hardware platforms. A lot of works have aimed to design better arithmetic circuits, and they have focused on coarse-grained designs (compressor allocation in compressor tree). In the meantime, those works have relied on heuristics to design fine-grained parts. \n\nThis work proposes to optimize compressor interconnections, which is a fine-grained design of arithmetic circuits. It denotes compressor interconnection architecture as a graph, regarding compressors as nodes and connections between any two compressors as edges. By doing so, compressor interconnection becomes a link prediction problem that can be solved differentially with GNN and graph attention.\n\nHowever, there is a critical barrier to optimizing compressor interconnections with GNN. The search space of compressor interconnections is discrete, thus it is not suitable for solving the problem with neural networks. To resolve this issue, this work relaxes the discrete search space into continuous search space by denoting edges as softmax-based soft labels, instead of hard labels.\n\nWith the above proposals, the paper achieves Pareto-dominance results than other prior works.\n\nSTRENGTHS AND WEAKNESSES:\nStrengths\n- It is noticeable that propose to design arithmetic circuits differentiably based on GNN.\n- This work optimizes arithmetic circuit design by focusing on interconnections, which haven’t been addressed.\n- Search space relaxation tailored loss function for the problem leads to achieving state-of-the-art results for designing arithmetic circuits.\n- The paper supports the claim well with mathematic formulas.\n\nWeaknesses\n- It seems that the paper’s Compressor Tree design, which previous L2O works have aimed, is highly rooted in the previous work (MUTE).\n- If so, it would be better to demonstrate the effectiveness of the proposed interconnection design by integrating the proposal with other prior works.\n\nQUESTIONS:\nIt seems that the compressor tree search part is based on MUTE. However, in the experiments in the appendix, the area of the circuits designed by the proposal is smaller than that of MUTE. Is there any difference between the two methods while searching compressor trees, or does it come from the stochasticity of the evolution-based method?\n\nLIMITATIONS:\nYes", "TITLE": "Official Review", "RECOMMENDATION": 4, "REVIEWER_CONFIDENCE": 2, "CLARITY": 2, "IMPACT": 3, "ORIGINALITY": 2, "DATE": "2025-06-30"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper aims to enhance the Arithmetic Circuit optimization via a differentiable architecture search framework. To do so, the author first model the combinational logic circuits as directed acyclic graphs (DAGs), in which partial products and compressors are modeled as nodes, and logical dependencies are modeled as directed edges. To capture this asymmetry, they represent the compressor tree as a multi-relational graph, where each edge type corresponds to a specific input port of the target node.  Then, the paper proposes a method called **ARITH-DAS**,encoding structural information via a multi-relational graph neural network and modeling interconnect prediction through graph attention, it enables end-to-end, gradient-based optimization directly guided by post-synthesis performance metrics. ARITH-DAS can also perform a proxy-free PPO-like training to optimize the interconnect structure with respect to post-synthesis performance metrics. The experiments shows ARITH-DAS's effectiveness and superiority when comparing it to other heuristic and ML-based baselines in area-delay trade-offs.\n\nSTRENGTHS AND WEAKNESSES:\n# Strengths\n1. The research questions are very practical.\n2. The paper is able to illustrate the concept of arithmetic circuit to readers who are not familiar with this topic\n3. The proposed method is effective and the ablation study also states the importance of each proposed module.\n\n\n# Weakness\n1. Some details of ARITH-DAS are not fully explained. For example, in lines 168-181, the author mentions \\mathbb{s} as the matrix of allocation of a compressor tree without demonstrating the role of \\mathbb{s} in terms of DAG setup or rest of the method implementation.\n2.  There is one paper: Reinforcement Learning for Combinatorial Optimization [1] which might be associate this submission, and the author may also include it as one reference.\n\n[1] Darvariu, Victor-Alexandru, Stephen Hailes, and Mirco Musolesi. \"Graph reinforcement learning for combinatorial optimization: A survey and unifying perspective.\" arXiv preprint arXiv:2404.06492 (2024).\n\nQUESTIONS:\nSee weaknesses.\n\nLIMITATIONS:\nYes", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 2, "CLARITY": 3, "IMPACT": 4, "ORIGINALITY": 3, "DATE": "2025-07-05"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper introduces a differentiable architecture search framework for arithmetic circuit optimization, which is set to overcome the existing limitations such as the under-explored design space of interconnection and the misaligned/oversimplified proxy objective, where both challenges are illustrated by case studies with randomized interconnect experiments. The empirical results show that the proposed ARITH-DAS framework can achieve 27.05% gain in hypervolume and 6.59% delay reduction in large-scale designs.\n\nSTRENGTHS AND WEAKNESSES:\n- This paper presents a comprehensive differentiable architecture search framework for arithmetic circuits, especially for the multipliers and multiply-accumulate units since they account for major computations. \n\n- The paper is well written with easy-to-follow flows and illustrative figures to show the major contributions. \n\n- The final results show a decent improvement of hypervolume on a suite of selected circuits, as well as significant delay reduction on large-scale designs. \n\nHowever, I do spot certain weaknesses of the work and raise a few questions as follows:\n\n- The authors mention in line 68, “The entire framework is trained in a proxy-free manner.” However, it seems that this applies to the post-synthesis alignment only. \n- The major evaluation metric is hypervolume (HV), and the authors showcase a significant improvement on Pareto frontiers when compared to other baselines. However, with the large-scale computing circuits, the results are limited to the delay reduction only. What is the main reason that area (or more generally, Pareto frontiers) are not shown here?\n- In the ablation study, it looks like neglecting certain key modules will not affect the improvements in general. Can the authors add the runtime difference when these key modules are not considered, since the current total runtime is not outperforming certain baselines? \n- Certain typos are found. For example, line 116 should be “Misaligned”.\n\nQUESTIONS:\nN/A\n\nLIMITATIONS:\nThe proposed work is \"proxy-free\" in the sense of synthesis results. What about plugging into the full design flow? It looks like the proxy-gap is limited to a certain degree.", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 4, "CLARITY": 3, "IMPACT": 3, "ORIGINALITY": 3, "DATE": "2025-07-06"}