Title: NeuralFuse: Learning to Recover the Accuracy of Access-Limited Neural Network Inference in Low-Voltage Regimes
Venue: NeurIPS 2024
Accepted: yes
Keywords: machine learning

energy efficient inference

bit error resilience
Abstract: Deep neural networks (DNNs) have become ubiquitous in machine learning, but their energy consumption remains problematically high. An effective strategy for reducing such consumption is supply-voltage reduction, but if done too aggressively, it can lead to accuracy degradation. This is due to random bit-flips in static random access memory (SRAM), where model parameters are stored. To address this challenge, we have developed NeuralFuse, a novel add-on module that handles the energy-accuracy tradeoff in low-voltage regimes by learning input transformations and using them to generate error-resistant data representations, thereby protecting DNN accuracy in both nominal and low-voltage scenarios. As well as being easy to implement, NeuralFuse can be readily applied to DNNs with limited access, such cloud-based APIs that are accessed remotely or non-configurable hardware. Our experimental results demonstrate that, at a 1% bit-error rate, NeuralFuse can reduce SRAM access energy by up to 24% while recovering accuracy by up to 57%. To the best of our knowledge, this is the first approach to addressing low-voltage-induced bit errors that requires no model retraining.

NeuralFuse: Learning to Recover the Accuracy of Access-Limited Neural Network Inference in Low-Voltage Regimes

Abstract

Deep neural networks (DNNs) have become ubiquitous in machine learning, but their energy consumption remains problematically high. An effective strategy for reducing such consumption is supply-voltage reduction, but if done too aggressively, it can lead to accuracy degradation. This is due to random bit-flips in static random access memory (SRAM), where model parameters are stored. To address this challenge, we have developed NeuralFuse, a novel add-on module that handles the energy-accuracy tradeoff in low-voltage regimes by learning input transformations and using them to generate error-resistant data representations, thereby protecting DNNaccuracy in both nominal and low-voltage scenarios. As well as being easy to implement, NeuralFuse can be readily applied to DNNs with limited access, such cloud-based APIs that are accessed remotely or non-configurable hardware. Our experimental results demonstrate that, at a 1% bit-error rate, NeuralFuse can reduce SRAMaccess energy by up to 24% while recovering accuracy by up to 57%. To the best of our knowledge, this is the first approach to addressing low-voltage-induced bit errors that requires no model retraining.

1 Introduction

Energy-efficient computing is of primary importance to the effective deployment of deep neural networks (DNNs), particularly in edge devices and in on-chip AI systems. Increasing DNN computation's energy efficiency and lowering its carbon footprint require iterative efforts from both chip designers and algorithm developers. Processors with specialized hardware accelerators for AI computing, capable of providing orders of magnitude better performance and energy efficiency for AI computation, are now ubiquitous. However, alongside reduced precision/quantization and architectural optimizations, endowing such systems with the capacity for low-voltage operation is a powerful lever for reducing their power consumption.

The computer engineering literature contains ample evidence of the effects of undervolting and low-voltage operation on accelerator memories that store weights and activations during computation. Aggressive scaling-down of static random access memory's (SRAM's) supply voltage to below the rated value saves power, thanks to the quadratic dependence of dynamic power on voltage. Crucially,

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however, it also leads to an exponential increase in bit failures. Memory bit flips cause errors in the stored weight and activation values [Chandramoorthy et al., 2019, Ganapathy et al., 2017], leading to catastrophic accuracy loss.

A recent wave of research has proposed numerous techniques for allowing low-voltage operation of DNN accelerators while preserving their accuracy. Most of these have been either hardware-based error-mitigation techniques or error-aware robust training of DNN models. On-chip error mitigation methods have significant performance and power overheads [Chandramoorthy et al., 2019, Reagen et al., 2016]. On the other hand, some have proposed to generate models that are robust to bit errors via a specific learning algorithm [Kim et al., 2018, Koppula et al., 2019, Stutz et al., 2021], thereby eliminating the need for on-chip error mitigation. However, error-aware robust training to find the optimal set of robust parameters for each model is time- and energy-intensive and may not be possible in all access-limited settings.

In this paper, therefore, we propose a novel model-agnostic approach: NeuralFuse . This proof-ofconcept machine-learning module offers trainable input transformation parameterized by a relatively small DNN; and, by enhancing input's robustness, it mitigates bit errors caused by very low-voltage operation, thus serving the wider goal of more accurate inferencing. The pipeline of NeuralFuse is illustrated in Figure 1. To protect the deployed models from making wrong predictions under low-power conditions, NeuralFuse accepts scenarios under access-limited neural networks (e.g., non-configurable hardware or cloud-based APIs). Specifically, we consider two access-limited scenarios that are common in the real world: 1) relaxed access , in which 'black box' model details are unknown, but backpropagation through those models is possible; and 2) restricted access , in which the model details are unknown and backpropagation is disallowed. To enable it to deal with relaxed access, we trained NeuralFuse via backpropagation, and for restricted-access cases, we trained it on a white-box surrogate model. To the best of our knowledge, this is the first study that leverages a learning-based method to address random bit errors as a means of recovering accuracy in low-voltage and access-limited settings.

We summarize our main contributions as follows:

We propose NeuralFuse , a novel learning-based input-transformation module aimed at enhancing the accuracy of DNNs that are subject to random bit errors caused by very low voltage operation. NeuralFuse is model-agnostic, i.e., operates on a plug-and-play basis at the data-input stage and does not require any re-training of deployed DNN models.

We explore two practical limited-access scenarios for neural-network inference: relaxed access and restricted access. In the former setting, we use gradient-based methods for module training. In the latter one, we use a white-box surrogate model for training, which is highly transferable to other types of DNN architecture.

We report the results of an extensive program of experiments with various combinations of DNN models (ResNet18, ResNet50, VGG11, VGG16, and VGG19), datasets (CIFAR-10, CIFAR-100,

GTSRB, and ImageNet-10), and NeuralFuse implementations of different architectures and sizes. These show that NeuralFuse can consistently increase the perturbed accuracy (accuracy evaluated under random bit errors in weights) by up to 57% , while simultaneously saving up to 24% of the energy normally required for SRAM access, based on our realistic characterization of bit-cell failures for a given memory array in a low-voltage regime inducing a 0 . 5% / 1% bit-error rate.

We demonstrate NeuralFuse's transferability (i.e., adaptability to unseen base models), versatility (i.e., ability to recover low-precision quantization loss), and competitiveness (i.e., state-of-the-art performance) in various scenarios, establishing it as a promising proof-of-concept for energyefficient, resilient DNN inference.

2 Related Work and Background

Software-based Energy-saving Strategies. Various recent studies have proposed software-based methods of reducing computing's energy consumption. For instance, quantization techniques have been reported to reduce the precision required for storing model weights, and thus to decrease total memory storage [Gong et al., 2014, Rastegari et al., 2016, Wu et al., 2016]. On the other hand, Yang et al. [2017] - who proposed energy-aware pruning on each layer and fine-tuning of weights to maximize final accuracy - suggested several ways to reduce DNNs' energy consumption. For example, they devised the ECC framework, which compresses DNN models to meet a given energy constraint [Yang et al., 2019a], and a method of compressing such models via joint pruning and quantization [Yang et al., 2020]. It is also feasible, during DNN training, to treat energy constraints as an optimization problem and thereby reduce energy consumption while maximizing training accuracy [Yang et al., 2019b]. However, unlike ours, all these methods imply changing either model architectures or model weights.

Hardware-based Energy-saving Strategies. Prior studies have also explored ways of improving energy efficiency via specially designed hardware. Several of them have focused on the undervolting of DNN accelerators and proposed methods to maintain accuracy in the presence of bit errors. For instance, Reagen et al. [2016] proposed an SRAM fault-mitigation technique that rounds faulty weights to zero to avoid degradation of prediction accuracy. Srinivasan et al. [2016] recommended storing sensitive MSBs (most significant bits) in robust SRAM cells to preserve accuracy. Chandramoorthy et al. [2019] proposed dynamic supply-voltage boosting to improve the resilience of memory-access operations; and the learning-based approach proposed by Stutz et al. [2021] aims to find models that are robust to bit errors. The latter paper discusses several techniques for improving such robustness, notably quantization, weight-clipping, random bit-error training, and adversarial bit-error training. Its authors concluded from their experiments that a combination of quantization, weight-clipping, and adversarial bit-error training will yield excellent performance. However, they also admitted that the relevant training process was sensitive to hyperparameter settings, and hence, it might come with a challenging training procedure.

However, we suggest that all the methods mentioned above are difficult to implement and/or unsuitable for use in real-world access-limited settings. For example, the weights of DNN models packed on embedded systems may not be configurable or updatable, making model retraining (e.g., Stutz et al. [2021]) non-viable in that scenario. Moreover, DNN training is already a tedious and time-consuming task, so adding error-aware training to it may further increase its complexity and, in particular, make hyperparameter searches more challenging. Özdenizci and Legenstein [2022] also reported that error-aware training was ineffective for large DNNs with millions of bits. NeuralFuse obviates the need for model retraining via an add-on trainable input-transformation function parameterized by a relatively small secondary DNN.

SRAM Bit Errors in DNNs. Low voltage-induced memory bit-cell failures can cause bit-flips from 0 to 1 and vice versa. In practice, SRAM bit errors increase exponentially when the supply voltage is scaled below V min , i.e., the minimum voltage required to avoid them. This phenomenon has been studied extensively in the prior literature, including work by Chandramoorthy et al. [2019] and Ganapathy et al. [2017]. The specific increases in bit errors as voltage scales down, in the case of an SRAM array of 512 × 64 bits with a 14nm technology node, is illustrated in Figure 2. The corresponding dynamic energy per SRAM read access, measured at each voltage at a constant frequency, is shown on the right-hand side of the figure. In this example, accessing the SRAM at

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0.83 V min leads to a 1% bit-error rate, and at the same time, dynamic energy per access is reduced by approximately 30% . This can lead to DNNs making inaccurate inferences, particularly when bit-flips occur at the MSBs. However, improving robustness to bit errors can allow us to lower V min and exploit the resulting energy savings.

It has been observed that bit-cell failures for a given memory array are randomly distributed and independent of each other. That is, the spatial distribution of bit-flips can be assumed to be random, as it generally differs from one array to another, within as well as between chips. Below, following Chandramoorthy et al. [2019], we model bit errors in a memory array of a given size by generating a random distribution of such errors with equal likelihood of 0-to-1 and 1-to-0 bit-flipping. More specifically, we assume that the model weights are quantized to 8-bit precision (i.e., from 32-bit floats to 8-bit integers), and generate perturbed models by injecting our randomly distributed bit errors into the two's complement representation of weights. For more implementation details, please refer to Section 4.1.

3 NeuralFuse: Framework and Algorithms

3.1 Error-Resistant Input Transformation

As illustrated in Figure 1, we propose a novel trainable input-transformation module, NeuralFuse, parametrized by a relatively small DNN, to mitigate the accuracy-energy tradeoff for model inference and thus overcome the drawback of performance degradation in low-voltage regimes. A specially designed loss function and training scheme are used to derive NeuralFuse and apply it to the input data such that the transformed inputs will become robust to low voltage-induced bit errors.

Consider the input x sampled from the data distribution X and a set of models M p with p % random bit errors on weights (i.e., perturbed models). When it is not manifesting any bit errors (i.e., at normal-voltage settings), the perturbed model operates as a nominal deterministic one, denoted by M 0 . NeuralFuse aims to ensure that a model M p ∈ M p can make correct inferences on the transformed inputs while also delivering consistent results in its M 0 state. To adapt to various data characteristics, NeuralFuse - designated as F in Eq. (1), below - is designed to be input-aware. This characteristic can be formally defined as

where G ( x ) is a 'generator' (i.e., an input-transformation function) that can generate a perturbation based on input x . As transformed by NeuralFuse, i.e., as F ( x ) , that input is passed to the deployed model ( M 0 or M p ) for final inference. Without loss of generality, we assume the transformed input lies within a scaled input range F ( · ) ∈ [ -1 , 1] d , where d is the (flattened) dimension of x .

3.2 Training Objective and Optimizer

To train our generator G ( · ) , which ought to be able to ensure the correctness of both the perturbed model M p and the clean model M 0 , we parameterized it with a neural network and apply our training objective function

where W G is the set of trainable parameters for G ; y is the ground-truth label of x ; P M denotes the likelihood of y as computed by a model M being given a transformed input F ( x ; W G ) ; M p is the distribution of the perturbed models inherited from the clean model M 0 , under a p % random bit-error rate; and λ is a hyperparameter that balances the importance of the nominal and perturbed models.

The training objective function can be readily converted to a loss function ( L ) that evaluates crossentropy between the ground-truth label y and the prediction P M ( y |F ( x ; W G ) . That is, the total loss function can be calculated as

In particular, optimizing the loss function requires evaluation of the impact of the loss term L M p on randomly perturbed models. Our training process is inspired by expectation over transformation (EOT) attacks [Athalye et al., 2018], which aim to produce robust adversarial examples that are simultaneously adversarial over the entire transformation distribution. Based on that idea, we propose a new optimizer for solving Eq. (3), which we call expectation over perturbed models (EOPM). EOPM-trained generators can generate error-resistant input transformations and mitigate inherent bit errors. However, it would be computationally impossible to enumerate all possible perturbed models with random bit errors, and the number of realizations for perturbed models is constrained by the memory size of the GPUs used for training. In practice, therefore, we only use N perturbed models per iteration to calculate empirical average loss, i.e.,

where N is the number of perturbed models { M p 1 , · · · , M p N } that are simulated to calculate the loss caused by random bit errors. Therefore, the gradient used to update the generator can be calculated as follows:

Through our implementation, we found that stable performance could be delivered when N = 10 , and that there was little to be gained by using a larger value. The results of our ablation study for different values of N can be found in Appendix E.

3.3 Training Algorithm

Algorithm 1 in Appendix A summarizes NeuralFuse's training steps. Briefly, this involves splitting the training data X into B mini-batches for training the generator in each epoch. For each mini-batch, we first feed these data into F ( · ) to obtain the transformed inputs. Also, we simulate N perturbed models using a p % random bit-error rate, denoted by M p 1 , · · · , M p N , from M p . Then, the transformed inputs are fed into those N perturbed models as well as into the clean model M 0 , and their respective losses and gradients are calculated. Finally, NeuralFuse parameters W G are updated based on the gradient obtained by EOPM.

4 Experiments

4.1 Experiment Setups

Datasets. We evaluate NeuralFuse on four different datasets: CIFAR-10 [Krizhevsky and Hinton, 2009], CIFAR-100 [Krizhevsky and Hinton, 2009], the German Traffic Sign Recognition Benchmark (GTSRB) [Stallkamp et al., 2012], and ImageNet-10 [Deng et al., 2009]. CIFAR-10 consists of 10 classes, with 50,000 training images and 10,000 testing images in total. Similarly, CIFAR-100 consists of 100 classes, with 500 training images and 100 testing images in each. The GTSRB contains 43 classes with a total of 39,209 training images and 12,630 testing images. Similar to CIFAR-10 and CIFAR-100, we resize GTSRB into 32 × 32 × 3 in our experiment. For ImageNet-10, we chose the same ten categories as Huang et al. [2022], in which there are 13,000 training images and 500 test images cropped into 224 × 224 × 3. Due to space limitations, our CIFAR-100 results are presented in Appendices F and G.

Base Models. We selected several common architectures for our base models: ResNet18, ResNet50 [He et al., 2016], VGG11, VGG16, and VGG19 [Simonyan and Zisserman, 2015]. To replicate the deployment of models on chips, all our based models were given quantization-aware training that followed Stutz et al. [2021].

NeuralFuse Generators. The architecture of the NeuralFuse generator ( G ) ) is based on an encoderdecoder structure. We designed and compared three types of generators, namely convolution-based, deconvolution-based, and UNet-based. We also considered large(L)/small(S) network sizes for each type. Further details can be found below and in Appendix B.

Convolution-based (Conv). Conv uses convolution with MaxPool layers for its encoder and convolution with UpSample layers for its decoder. This architecture has previously been shown to be efficient and effective at generating input-aware backdoor triggers [Nguyen and Tran, 2020].

Deconvolution-based (DeConv). DeConv uses convolution with MaxPool layers for its encoder and deconvolution layers for its decoder. We expected this modification both to enhance its performance and to reduce its energy consumption.

UNet-based (UNet). UNet uses convolution with MaxPool layers for its encoder, and deconvolution layers for its decoder. UNet is known for its robust performance in image segmentation [Ronneberger et al., 2015].

Energy-consumption Calculation. The energy consumption reported in Figure 1 is based on the product of the total number of SRAM memory accesses in a systolic array-based convolution neural network (CNN) accelerator and the dynamic energy per read access at a given voltage. Research by Chen et al. [2016] previously showed that energy consumption by SRAM buffers and arrays accounts for a high proportion of total system energy consumption. We assume that there are no bit errors on NeuralFuse, given its status as an add-on data preprocessing module whose functions could also be performed by a general-purpose core. In this work we assume it is implemented on the accelerator equipped with dynamic voltage scaling and therefore NeuralFuse computation is performed at nominal error-free voltage. We report a reduction in overall weight-memory energy consumption (i.e., NeuralFuse + Base Model under a p % bit-error rate) with respect to the unprotected base model in the regular-voltage mode (i.e., 0% bit-error rate and without NeuralFuse).

To quantify memory accesses, we used the SCALE-SIM simulator [Samajdar et al., 2020], and our chosen configuration simulated an output-stationary dataflow and a 32 × 32 systolic array with 256KB of weight memory. We collected data on the dynamic energy per read access of the SRAM both at V min and at the voltage corresponding to a 1% bit-error rate ( V ber ≈ 0 . 83 V min ) from Cadence ADE Spectre simulations, both at the same clock frequency.

Relaxed and Restricted Access Settings. In the first of our experiments' two scenarios, relaxed access, the base-model information was not entirely transparent, but allowed us to obtain gradients from the black-box model through backpropagation. Therefore, this scenario allowed direct training of NeuralFuse with the base model using EOPM. In the restricted-access scenario, on the other hand, only the inference function was allowed for the base model, and we therefore trained NeuralFuse using a white-box surrogate base model and then transfering the generator to the access-restricted model.

Computing Resources. Our experiments were performed using eight Nvidia Tesla V100 GPUs and implemented with PyTorch. NeuralFuse was found to generally take 150 epochs to converge, and its training time was similar to that of the base model it incorporated. On both the CIFAR-10 and CIFAR-100 datasets, average training times were 17 hours (ResNet18), 50 hours (ResNet50), 9 hours (VGG11), 13 hours (VGG16), and 15 hours (VGG19). For GTSRB, the average training times were 9 hours (ResNet18), 27 hours (ResNet50), 5 hours (VGG11), 7 hours (VGG16), and 8 hours (VGG19); and for ImageNet-10, the average training times were 32 hours (ResNet18), 54 hours (ResNet50), 50 hours (VGG11), 90 hours (VGG16), and 102 hours (VGG19).

4.2 Performance Evaluation, Relaxed-access Scenario

Our experimental results pertaining to the relaxed-access scenario are shown in Figure 3. The biterror rate (BER) due to low voltage was 1% in the cases of CIFAR-10 and GTSRB, and 0 . 5% for ImageNet-10. The BER of ImageNet-10 was lower than that of the other two because, being pretrained, it has more parameters than either of them. For each experiment, we sampled and evaluated N = 10 perturbed models (independent from training), and below, we report the means and standard deviations of their respective accuracies. Below, clean accuracy (CA) refers to a model's accuracy measured at nominal voltage, and perturbed accuracy (PA) to its accuracy measured at low voltage.

In the cases of CIFAR-10 and the GTSRB, we observed that large generators like ConvL and UNetL recovered PA considerably, i.e., in the range of 41% to 63% on ResNet18, VGG11, VGG16,

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37

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and VGG19. ResNet50's recovery percentage was slightly worse than those of the other base models, but it nevertheless attained up to 51% recovery on the GTSRB. On the other hand, the recovery percentages achieved when we used small generators like DeConvS were worse than those of their larger counterparts. This could be explained by larger-sized networks' better ability to learn error-resistant generators (though perhaps at the cost of higher energy consumption). In the case of ImageNet-10, using larger generators also yielded better PA performance recovery, further demonstrating NeuralFuse's ability to work well with large input sizes and varied datasets.

4.3 Performance Evaluation, Restricted-access Scenario (Transferability)

The experimental results of our restricted-access scenario are shown in Table 1. We adopted ResNet18 and VGG19 as our white-box surrogate source models for training the generators under a 1 . 5% biterror rate. We chose ConvL and UNetL as our generators because they performed best out of the six we tested (see Figure 3).

From Table 1, we can see that transferring from a larger BER such as 1 . 5% can endow a smaller one (e.g., 1% ) with strong resilience. The table also makes it clear that using VGG19 as a surrogate model with UNet-based generators like UNetL can yield better recovery performance than other model/generator combinations. On the other hand, we observed in some cases that if we transferred between source and target models of the same type (but with different BERs for training and testing), performance results could exceed those we had obtained during the original relaxed-access scenario. For instance, when we transferred VGG19 with UNetL under a 1 . 5% BER to VGG19 or VGG11 under a 0 . 5% BER, the resulting accuracies were 85 . 86% (as against 84 . 99% for original VGG19) and 84 . 81% (as against 82 . 42% for original VGG11). We conjecture that generators trained on relatively large BERs can cover the error patterns of smaller BERs, and even help improve the latter's generalization. These findings indicate the considerable promise of access-limited base models in low-voltage settings to recover accuracy.

4.4 Energy/Accuracy Tradeoff

We report total dynamic energy consumption as the total number of SRAM-access events multiplied by the dynamic energy of a single such event. Specifically, we used SCALE-SIM to calculate total

Note . SM: source model, used for training generators; TM: target model, used for testing generators; BER: the bit-error rate of the target model; CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

weight-memory access (TWMA), specifics of which can be found in Appendix C's Table 6. In Table 2, below, we report the percentages of energy saved (ES) at voltages that yield a 1% bit-error rate for various base-model and generator combinations. The formula for computing ES is

where NV denotes nominal voltage regime, and LV , a low-voltage one.

Our results indicate that when ResNet18 is utilized as a base model, NeuralFuse can recover model accuracy by 20 -49% while reducing energy use by 19 -29% . In Appendix C, we provide more results on the tradeoff between energy and accuracy of different NeuralFuse and base-model combinations. Overall, it would appear that using NeuralFuse can effectively restore model accuracy when SRAM encounters low-voltage-induced random bit errors.

Runtime and Latency. On the other hand, runtime and its corresponding energy consumption may also affect overall energy savings. For instance, previous research has shown that multiply-andaccumulate (MAC) operations account for more than 99% of all operations in state-of-the-art CNNs, dominating processing runtime and energy consumption alike Yang et al. [2017]. Therefore, we also report the results of our MAC-based energy-consumption estimation in Appendix C, and of our latency analysis in Appendix D. Here, it should also be noted that an additional latency overhead is an inevitable tradeoff for reducing energy consumption in our scenarios. Although neither runtime nor latency is a major focus of this paper, future researchers could usefully design a lighter-weight version of the NeuralFuse module, or apply model-compression techniques to it, to reduce these two factors.

4.5 Model Size and NeuralFuse Efficiency

To arrive at a full performance characterization of NeuralFuse, we analyzed the relationship between the final recovery achieved by each base model in combination with generators of varying parameter counts. For this purpose, we defined efficiency ratio as the recovery percentage in PA divided by NeuralFuse's parameter count. Table 3 compares the efficiency ratios of all NeuralFuse generators

Original Accuracy

w/o NeuralFuse

NeuralFuse (ConvL)

NeuralFuse (UNetL)

8

7

6

5

4

3

2

Bit Quantization Number

95.5

Accuracy (%)

95

95

95

95

92

67

.5

.5

.4

.4

.6

.7

93

93

93

93

93

92

.4

.3

.3

.3

.3

.0

96

96

96

96

96

95

.2

.2

.2

.2

.1

.7

3

.8

3

.8

3

.8

GTSRB pre-trained ResNet18 (Nominal voltage, No Bit Error)

8

7

6

5

4

3

2

Accuracy (%)

75

69

67

48

24

5

.2

.5

.2

.6

.6

.3

89

89

88

79

52

9

.5

.9

.9

.3

.1

.7

93

94

93

87

62

12

.5

.5

.5

.5

.2

.6

3

.8

3

.8

3

.8

GTSRB pre-trained ResNet18 (Low voltage, 0.5% BER)

Bit Quantization Number

trained on CIFAR-10. Those results show that UNet-based generators had better efficiency per million parameters than either convolution-based or deconvolution-based ones.

4.6 NeuralFuse's Robustness to Reduced-precision Quantization

Lastly, we also explored NeuralFuse's robustness to low-precision quantization on model weights. Uniform quantization is the usual method for quantizing model weights [Gholami et al., 2022]. However, it is possible for it to cause an accuracy drop due to lack of precision. Given our aim of offering protection from bit errors, we hoped to understand whether NeuralFuse could also recover model-accuracy drops caused by this phenomenon. We therefore uniformly quantized the model weights to a lower bit precision and measured the resulting accuracy. Specifically, we applied symmetric uniform quantization to our base models with various numbers of bits to induce precision loss, and defined the quantized weight W q (integer) as W q = ⌊ W s ⌉ , where W denotes the original model weight (full precision), s = max | W | 2 b -1 -1 is the quantization scale parameter, and b is the precision (number of bits) used to quantize the models. Bit errors induced by low voltage operation as previously described, are also applied to low precision weights.

We used the GTSRB pre-trained ResNet18 as our example in an evaluation of two NeuralFuse generators, i.e., ConvL and UNetL trained with 0 . 5% BER, and varied precision b from 8 bits to 2 bits (integer). The results, shown in Figure 4, indicated that when b > 3 bits, NeuralFuse could effectively recover accuracy in both the low-voltage and low-precision scenarios. When b = 3 , while NeuralFuse could still handle the bit-error-free model (Fig. 4 top), it exhibited a limited ability to recover the random bit-error case (Fig. 4 bottom). We find these results encouraging, insofar as NeuralFuse was only trained on random bit errors, yet demonstrated high accuracy in dealing with unseen bit-quantization errors. Further experimental results derived from other base models and datasets can be found in Appendix H.

4.7 Extended Analysis

Here, we would like to highlight some key findings from the additional results in the Appendices. In Appendix E, we compare NeuralFuse against a simple baseline of learning a universal input perturbation. We found that such baseline performed much worse than NeuralFuse at that task, validating the necessity of adopting input-aware transformation if the goal is to learn error-resistant data representations in low-voltage scenarios. In Appendix G, we report that ensemble training of white-box surrogate base models could further improve the transferability of NeuralFuse in restrictedaccess scenarios. Appendices K and L present visualization results of NeuralFuse's data embeddings and transformed inputs. In Appendix J, we show that NeuralFuse can further recover the accuracy of a base model trained with adversarial weight perturbation in a low-voltage setting.

5 Conclusion

In this paper, we have proposed NeuralFuse, the first non-intrusive post hoc module that protects model inference against bit errors induced by low voltage. NeuralFuse is particularly well suited to

practical machine-deployment cases in which access to the base model is limited or relaxed. The design of NeuralFuse includes a novel loss function and a new optimizer, EOPM, that enable it to handle simulated randomness in perturbed models. Our comprehensive experimental results and analysis show that NeuralFuse can recover test accuracy by up to 57% while simultaneously enjoying an up to 24% reduction in memory-access energy requirements. Moreover, NeuralFuse demonstrates high transferability to access-constrained models and high versatility, e.g., robustness to low-precision quantization. In short, NeuralFuse is a notable advancement in mitigating neural-network inference's energy/accuracy tradeoff in low-voltage regimes, and points the way to greener future AI technology. Our future work will include extending this study to other neural-network architectures and modalities, such as transformer-based language models.

Limitations. We acknowledge the challenge of achieving significant power savings without accuracy loss and view NeuralFuse as a foundational, proof-of-concept step toward this goal. Future research could enhance this approach by optimizing the pre-processing module to adapt to specific error characteristics of low-voltage SRAM or by integrating lightweight hardware modifications to further improve the energy-accuracy trade-off.

Broader Impacts. We see no ethical or immediate negative societal consequence of our work, and it holds the potential for positive social impacts, from environmental benefits to improved access to technology and enhanced safety in critical applications.

Acknowledgments and Disclosure of Funding

We thank the anonymous reviewers for their insightful comments and valuable suggestions. The research described in this paper was conducted in the JC STEM Lab of Intelligent Design Automation, which is funded by The Hong Kong Jockey Club Charities Trust in support of Tsung-Yi Ho.

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Appendix

The appendix provides more implementation details for our method, experimental results on more datasets and settings, ablation studies, and qualitative analysis. The appendices cover the following:

Implementation Details: NeuralFuse Training Algorithm (Sec. A), NeuralFuse Generator (Sec. B), Energy/Accuracy Tradeoff (Sec. C), Latency Reports (Sec. D)

Experimental Results: Ablation Studies (Sec. E), Relaxed Access (Sec. F), Restricted Access (Sec. G), Reduced-precision Quantization (Sec. H), Adversarial Training (Sec. I), Adversarial Weight Perturbation (Sec. J)

Qualitative Studies: Data Embeddings Visualization (Sec. K), Transformed Inputs Visualization (Sec. L)

A Training Algorithm of NeuralFuse

Algorithm 1 Training steps for NeuralFuse

Input : Base model M 0 ; Generator G ; Training data samples X ; Distribution of the perturbed models M p ; Number of perturbed models N ; Total training iterations T

Output : Optimized parameters W G for the Generator G

1: for t = 0 , ..., T -1 do

2: for all mini-batches { x , y } B b =1 ∼ X do

3: Create transformed inputs x t = F ( x ) = clip [ -1 , 1] ( x + G ( x ) ) .

4: Sample N perturbed models { M p 1 , ..., M p N } from M p under p % random bit errors.

5: for all M p i ∼ { M p 1 , ..., M p N } do

6: Calculate the loss L p i based on the output of the perturbed model M p i . Then calculate the gradients g p i for W G based on L p i .

7: end for

8: Calculate the loss L 0 based on the output of the clean model M 0 . Then calculate the gradients g 0 for W G based on L 0 .

9: Calculate the final gradient g final using (5) based on g 0 and g p 1 , ..., g p N .

10: Update W G using g final .

11: end for

12: end for

B Implementation Details of NeuralFuse Generator

We consider two main goals in designing the NeuralFuse Generator: 1) efficiency (so the overall energy overhead is decreased) and 2) robustness (so that it can generate robust patterns on the input image and overcome the random bit flipping in subsequent models). Accordingly, we choose to utilize an encode-decoder architecture in implementing the generator. The design of ConvL is inspired by Nguyen and Tran [2020], in which the authors utilize a similar architecture to design an inputaware trigger generator, and have demonstrated its efficiency and effectiveness. Furthermore, we attempted to enhance it by replacing the Upsampling layer with a Deconvolution layer, leading to the creation of DeConvL. The UNetL-based NeuralFuse draws inspiration from Ronneberger et al. [2015], known for its robust performance in image segmentation, and thus, we incorporated it as one of our architectures. Lastly, ConvS, DeConvS, and UNetS are scaled-down versions of the model designed to reduce computational costs and total parameters. The architectures of Convolutional-based and Deconvolutional-based are shown in Table 4, and the architecture of UNet-based generators is in Table 5. For the abbreviation used in the table, ConvBlock means the Convolution block, Conv means a single Convolution layer, DeConvBlock means the Deconvolution block, DeConv means a single Deconvolution layer, and BN means a Batch Normalization layer. We use learning rate = 0 . 001 , λ = 5 , and Adam optimizer. For CIFAR-10, GTSRB, and CIFAR-100, we set batch size b = 25 for each base model. For ImageNet-10, we set b = 64 for ResNet18, ResNet50 and VGG11, and b = 32 for both VGG16 and VGG19.

[Note] #CHs: number of channels .

C NeuralFuse's Energy/Accuracy Tradeoff

SCALE-SIM. SCALE-SIM [Samajdar et al., 2020] is a systolic array-based CNN simulator that can calculate the number of memory accesses and the total time in execution cycles by giving the specific model architecture and accelerator architectural configuration as inputs. In this paper, we use SCALESIM to calculate the weights memory access of 5 based models (ResNet18, ResNet50, VGG11, VGG16, VGG19), and 6 generators (ConvL, ConvS, DeConvL, DeConvS, UNetL, UNetS). While SCALE-SIM supports both Convolutional and Linear layers, it does not yet support Deconvolution layers. Instead, we try to approximate the memory costs of Deconvolution layers by Convolution layers. We change the input and output from Deconvolution into the output and input of the Convolution layers. Besides, we also change the stride into 1 when we approximate it. We also add padding for the convolution layers while generating input files for SCALE-SIM. In this paper, we only consider the energy saving on weights accesses, so we only take the value 'SRAM Filter Reads' from the output of SCALE-SIM as the total weights memory accesses (T.W.M.A.) for further energy calculation.

In Table 6, we report the total weight memory access (T.W.M.A.) using SCALE-SIM. We then showed the energy/accuracy tradeoff between all of the combinations of NeuralFuse and base models under a 1% of bit error rate in Figure 5.

Parameters and MACs Calculation. In addition to T.W.M.A., the number of parameters and MACs (multiply-accumulate operations) are also common metrics in measuring the energy consumption of machine learning models. Yang et al. [2017] have shown that the energy consumption of computation

[Note] T.W.M.A.: total weight memory access .

Comparison under 1%of bit error rate on CIFAR-10

06

VGG11+ConvL

VGG16+ConvL

VGG19+ConvL

VGG11

VGG16

80

ResNet18+ConvL

VGG16+ConvS

VGG11+ConvS

?

VGG19

ResNet18

ResNet50

VGG19+ConvS

ResNet18+ConvS

Perturbed Accuracy(%)

70

ResNet50+ConvS

VGG11+DeConvL

60

VGG19+DeConvL

ResNet18+DeConvL

ResNet50+DeConvL

VGG11+DeConvS

VGG16+DeConvS

VGG19+DeConvS

50

ResNet50+DeConvS

ResNet18+DeConvS

VGG11+UNetL

VGG16+UNetL

VGG19+UNetL

40

ResNet18+UNetL

ResNet50+UNetL

VGG11+UNetS

VGG19+UNetS

VGG16+UNetS

30

ResNet18+UNetS

ResNet50+UNetS

10

15

20

25

30

EnergySavingPercentage(%)

and memory accesses are both proportional to MACs, allowing us to take computation energy consumption into account.

Here, we use the open-source package ptflops [Sovrasov, 2018-2023] to calculate the parameters and MAC values of all the base models and the NeuralFuse generators, in the same units as Bejnordi et al. [2020] used. The results are shown in Table 7. Note that we modified the base model architectures for ImageNet-10, as it has larger input sizes. For example, we use a larger kernel size = 7 instead of 3 in the first Convolution layer in ResNet-based models to enhance the learning abilities. Therefore, the parameters of base models are different between different datasets. For NeuralFuse generators, we utilize the same architectures for implementation (including ImageNet-10). As a result, our proposed NeuralFuse generators are generally smaller than base models, either on total model parameters or MAC values.

MACs-based Energy Consumption. We can then use the MAC values to further approximate the end-to-end energy consumption of the whole model. Assume that all values are stored on SRAM and that a MAC represents single memory access. The corresponding MACs-based energy saving percentage (MAC-ES, %) can be derived from Eq. 7 (c.f. Sec. 4.4), and results can be found in Table 8. We can observe that most combinations can save a large amount of energy, except that VGG11 with two larger NeuralFuse (ConvL and DeConvL) may increase the total energy. These results are consistent with the results reported in Table 2. In addition, we also showed the MACs-based energy/accuracy tradeoff between all of the combinations of NeuralFuse and base models under a 1% of bit error rate in Figure 6.

Comparison under 1%of bit errorrate on CIFAR-10 BasedonMACs

90

VGG11+ConvL

VGG16+ConvL

?

VGG11

VGG19+ConvL

VGG16

80

ResNet18+ConvL

VGG11+ConvS

?

VGG19

ResNet18

VGG16+ConvS

ResNet50

VGG19+ConvS

ResNet18+ConvS

Perturbed Accuracy(%)

70

VGG11+DeConvL

ResNet50+ConvS

VGG19+DeConvL

ResNet18+DeConvL

60

ResNet50+DeConvL

VGG11+DeConvS

VGG16+DeConvS

VGG19+DeConvS

50

ResNet18+DeConvS

ResNet50+DeConvS

VGG11+UNetL

VGG16+UNetL

VGG19+UNetL

40

ResNet50+UNetL

ResNet18+UNetL

VGG11+UNetS

VGG16+UNetS

VGG19+UNetS

30

ResNet18+UNetS

ResNet50+UNetS

-20

-10

0

10

20

30

EnergySavingPercentage(%)

Although using ConvL or DeConvL along with base model VGG11 for CIFAR-10 implies an increase in energy consumption, using other smaller-scale generators, we can still save the overall energy and recover the base model's accuracy. That said, developers can always choose smaller generators (with orders of magnitude fewer MAC operations than the original network) to restore model accuracy, further demonstrating the flexibility of choosing NeuralFuse generators of different sizes.

D Inference Latency of NeuralFuse

In Table 9, we report the latency (batch_size=1, CIFAR-10/ImageNet-10 testing dataset) of utilizing the different NeuralFuse generators with two different base models, ResNet18 and VGG19. While

NeuralFuse contributes some additional latency, we consider this an unavoidable tradeoff necessary to achieve reduced energy consumption within our framework. Although the primary focus of this paper is not on latency, we acknowledge its importance. Future research could explore designing a more lightweight version of the NeuralFuse module or applying model compression techniques to minimize latency. Additionally, we recognize that running NeuralFuse on a general-purpose CPU could lead to different latency and energy consumption figures due to various influencing factors like CPU architecture and manufacturing processes.

E Ablation Studies

Study for N in EOPM. Here, we study the effect of N used in EOPM (Eq. 5). In Figure 7, we report the results for ConvL and ConvS on CIFAR-10 pre-trained ResNet18, under a 1% bit error rate (BER). The results demonstrate that if we apply larger N , the performance increases until convergence. Specifically, for ConvL (Figure 7a), larger N empirically has a smaller standard deviation; this means larger N gives better stability but at the cost of time-consuming training. In contrast, for the small generator ConvS (Figure 7b), we can find that the standard deviation is still large even trained by larger N ; the reason might be that small generators are not as capable of learning representations as larger ones. Therefore, there exists a tradeoff between the stability of the generator performance and the total training time. In our implementation, choosing N = 5 or 10 is a good balance.

(a) Using ConvL

(b) Using ConvS

ResNet18,CIFAR-10,BER=1%

ConvS

70

65

60

8

50

45

40

35

1

5

10

20

50

N

ResNet18,CIFAR-10,BER=1%

100

ConvL

95

90

85

80

75

70

65

10

20

N

Tradeoff Between Clean Accuracy (CA) and Perturbed Accuracy (PA). We conducted an experiment to study the effect of different λ values, which balance the ratio of clean accuracy and perturbed accuracy. In Table 10, the experimental results showed that a smaller λ can preserve clean accuracy, but result in poor perturbed accuracy. On the contrary, larger λ can deliver higher perturbed accuracy, but with more clean accuracy drop. This phenomenon has also been observed in adversarial training [Zhang et al., 2019].

Comparison to Universal Input Perturbation (UIP). Moosavi-Dezfooli et al. [2017] has shown that there exists a universal adversarial perturbation to the input data such that the model will make wrong predictions on a majority of the perturbed images. In our NeuralFuse framework, the universal perturbation is a special case when we set G ( x ) = tanh( UIP ) for any data sample x . The transformed data sample then becomes x t = clip [ -1 , 1] ( x +tanh( UIP ) ) , where x t ∈ [ -1 , 1] d

Note. CA (%): clean accuracy; PA (%): perturbed accuracy; NF: NeuralFuse; and RP: total recover percentage of PA (NF) vs. PA

and UIP is a trainable universal input perturbation that has the same size as the input data. The experimental results with the universal input perturbation are shown in Table 11. We observe that its performance is much worse than our proposed NeuralFuse. This result validates the necessity of adopting input-aware transformation for learning error-resistant data representations in low-voltage scenarios.

Note . BER: the bit-error rate of the base model; CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; UIP: universal input transformation parameter; and RP: total recovery percentage of PA (UIP) vs. PA

F Additional Experimental Results on Relaxed Access Settings

We conducted more experiments on Relaxed Access settings to show that our NeuralFuse can protect the models under different BER The results can be found in Sec. F.1 (CIFAR-10), Sec. F.2 (GTSRB), Sec. F.3 (ImageNet-10), and Sec. F.4 (CIFAR-100). For comparison, we also visualize the experimental results in the figures below each table.

F.1 CIFAR-10

Note . CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

Nominal (w/o NeuralFuse)

Low voltage (w/o NeuralFuse)

Nominal (w/ NeuralFuse)

Low voltage (w/ NeuralFuse)

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

92.6

Accuracy (%)

38

.9

89

88

89

82

86

84

.8

.2

.6

.9

.6

.4

87

59

88

68

84

68

.8

.5

.5

.8

.6

.8

CIFAR-10 pre-trained ResNet18

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

92.6

26

.1

85

85

87

82

86

77

.5

.2

.4

.4

.2

.3

53

34

63

42

75

56

.2

.6

.3

.2

.5

.2

CIFAR-10 pre-trained ResNet50

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

88.4

42

.2

89

84

89

85

87

85

.6

.9

.3

.6

.1

.5

87

66

87

68

83

72

.2

.3

.2

.2

.6

.7

CIFAR-10 pre-trained VGG11

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

90.3

35

.7

90

87

89

86

87

87

.1

.4

.7

.8

.4

.4

86

59

85

66

83

71

.0

.6

.5

.5

.4

.2

CIFAR-10 pre-trained VGG16

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

90.5

36

.0

89

87

86

86

86

86

.8

.3

.3

.5

.3

.3

77

52

78

58

82

66

.7

.7

.4

.2

.1

.4

CIFAR-10 pre-trained VGG19

(a) CIFAR-10,

1%

Bit Error Rate

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

92.6

70

.1

90

91

90

84

89

90

.4

.7

.2

.1

.7

.9

87

78

90

79

86

80

.9

.4

.0

.9

.3

.7

CIFAR-10 pre-trained ResNet18

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

92.6

61

.0

90

90

89

90

89

89

.3

.8

.5

.3

.9

.7

86

73

87

75

83

76

.5

.3

.2

.5

.9

.1

CIFAR-10 pre-trained ResNet50

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

88.4

63

.6

89

88

89

88

88

88

.8

.2

.6

.3

.0

.1

87

74

86

75

82

75

.0

.5

.9

.7

.4

.8

CIFAR-10 pre-trained VGG11

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

90.3

66

.6

90

89

89

90

89

89

.2

.9

.7

.0

.0

.0

88

77

88

78

86

80

.5

.8

.2

.4

.2

.2

CIFAR-10 pre-trained VGG16

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

90.5

64

.2

90

89

90

89

89

89

.4

.6

.4

.7

.1

.2

88

74

88

75

85

77

.1

.5

.5

.2

.0

.1

CIFAR-10 pre-trained VGG19

(b) CIFAR-10,

0

.

5%

Bit Error Rate

F.2 GTSRB

Nominal (w/o NeuralFuse)

Low voltage (w/o NeuralFuse)

Nominal (w/ NeuralFuse)

Low voltage (w/ NeuralFuse)

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

95.5

Accuracy (%)

36

.9

95

94

95

95

96

95

.7

.4

.6

.7

.2

.9

91

68

91

78

93

85

.1

.6

.3

.1

.8

.1

GTSRB pre-trained ResNet18

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

95.0

29

.5

95

94

94

93

94

94

.6

.8

.9

.0

.5

.7

71

50

71

56

80

64

.6

.5

.6

.4

.6

.7

GTSRB pre-trained ResNet50

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

91.9

34

.9

94

91

95

92

92

94

.8

.1

.0

.4

.2

.7

85

62

84

67

83

73

.7

.2

.6

.5

.2

.4

GTSRB pre-trained VGG11

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

95.2

15

.1

96

94

96

93

95

94

.3

.1

.4

.8

.8

.3

72

39

72

50

78

63

.4

.8

.0

.9

.6

.3

GTSRB pre-trained VGG16

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

95.5

36

.6

96

93

95

94

95

94

.0

.8

.4

.5

.4

.6

88

69

87

73

88

80

.3

.0

.2

.1

.2

.6

GTSRB pre-trained VGG19

(a) GTSRB,

1%

Bit Error Rate

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

95.5

75

.2

93

94

95

95

96

95

.4

.8

.4

.8

.2

.5

89

87

93

90

93

91

.5

.7

.4

.1

.5

.4

GTSRB pre-trained ResNet18

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

95.0

74

.0

94

95

94

94

96

95

.6

.4

.7

.6

.5

.9

90

84

91

87

93

90

.6

.5

.6

.4

.7

.6

GTSRB pre-trained ResNet50

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

91.9

64

.9

93

90

93

92

94

94

.9

.9

.6

.3

.8

.6

92

80

91

83

90

88

.6

.5

.9

.1

.6

.9

GTSRB pre-trained VGG11

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

95.2

58

.8

95

94

95

95

96

95

.6

.3

.6

.1

.0

.4

93

82

93

84

92

87

.2

.2

.1

.0

.8

.8

GTSRB pre-trained VGG16

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

95.5

69

.1

95

94

95

95

94

96

.6

.9

.5

.5

.9

.5

93

87

92

88

91

90

.4

.0

.4

.8

.7

.8

GTSRB pre-trained VGG19

(b) GTSRB,

0

.

5%

Bit Error Rate

F.3 ImageNet-10

Note . CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

Nominal (w/o NeuralFuse)

Low voltage (w/o NeuralFuse)

Nominal (w/ NeuralFuse)

Low voltage (w/ NeuralFuse)

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

92.2

Accuracy (%)

72

.3

94

91

94

92

94

93

.0

.8

.0

.8

.0

.2

88

83

89

87

88

86

.0

.6

.2

.5

.1

.4

ImageNet-10 pre-trained ResNet18

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

89.8

39

.4

92

91

93

93

92

92

.2

.8

.0

.2

.2

.4

80

65

79

70

80

73

.0

.0

.4

.9

.5

.6

ImageNet-10 pre-trained ResNet50

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

91.6

47

.8

92

89

91

89

92

86

.0

.4

.0

.0

.4

.2

86

66

86

72

83

73

.1

.4

.0

.5

.0

.5

ImageNet-10 pre-trained VGG11

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

94.6

38

.4

90

90

91

90

90

86

.8

.2

.2

.0

.6

.4

77

60

77

62

81

72

.1

.2

.2

.3

.1

.3

ImageNet-10 pre-trained VGG16

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

92.4

37

.2

91

88

91

88

89

87

.4

.8

.0

.8

.4

.6

75

56

75

64

77

65

.5

.5

.9

.0

.9

.9

ImageNet-10 pre-trained VGG19

F.4 CIFAR-100

As mentioned in the previous section, larger generators like ConvL, DeConvL, and UNetL have better performance than small generators. For CIFAR-100, we find that the gains of utilizing NeuralFuse are less compared to the other datasets. We believe this is because CIFAR-100 is a more challenging dataset (more classes) for the generators to learn to protect the base models. Nevertheless, NeuralFuse can still function to restore some degraded accuracy; these results also demonstrate that our NeuralFuse is applicable to different datasets. In addition, although the recover percentage is less obvious on CIFAR-100 (the more difficult dataset), we can still conclude that our NeuralFuse is applicable to different datasets.

Nominal (w/o NeuralFuse)

Low voltage (w/o NeuralFuse)

Nominal (w/ NeuralFuse)

Low voltage (w/ NeuralFuse)

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

73.7

Accuracy (%)

4

.6

54

49

55

32

50

26

.8

.7

.2

.7

.6

.8

11

4

11

4

14

4

.0

.2

.9

.0

.5

.6

CIFAR-100 pre-trained ResNet18

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

73.5

3

.0

63

65

59

61

39

47

.5

.5

.6

.1

.0

.7

3

3

3

3

5

3

.2

.2

.2

.2

.0

.4

CIFAR-100 pre-trained ResNet50

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

64.8

8

.2

58

56

60

58

51

51

.3

.6

.3

.3

.1

.9

19

10

21

11

22

13

.7

.4

.2

.8

.1

.1

CIFAR-100 pre-trained VGG11

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

67.8

7

.0

51

44

53

23

50

27

.4

.3

.1

.5

.2

.7

19

6

20

4

25

9

.2

.7

.8

.8

.3

.9

CIFAR-100 pre-trained VGG16

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

67.8

10

.6

59

63

60

60

58

59

.4

.7

.1

.9

.7

.1

29

14

29

16

30

18

.2

.4

.6

.1

.2

.0

CIFAR-100 pre-trained VGG19

(a) CIFAR-100,

1%

Bit Error Rate

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

73.7

20

.9

65

70

66

68

66

67

.2

.0

.3

.2

.2

.1

39

24

38

25

40

28

.0

.5

.2

.9

.1

.8

CIFAR-100 pre-trained ResNet18

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

73.5

21

.3

68

71

68

70

66

69

.4

.9

.1

.3

.6

.1

28

23

28

25

36

26

.8

.1

.6

.0

.5

.1

CIFAR-100 pre-trained ResNet50

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

64.8

23

.9

63

62

63

61

61

61

.1

.7

.9

.9

.8

.7

38

27

40

29

37

29

.8

.9

.0

.8

.8

.8

CIFAR-100 pre-trained VGG11

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

67.8

22

.4

61

63

62

62

61

61

.8

.8

.8

.1

.7

.6

41

27

42

29

41

31

.1

.5

.1

.9

.3

.3

CIFAR-100 pre-trained VGG16

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

67.8

34

.0

65

66

65

66

65

66

.6

.6

.7

.5

.5

.3

46

38

46

39

46

40

.5

.3

.9

.0

.9

.1

CIFAR-100 pre-trained VGG19

(b) CIFAR-100,

0

.

5%

Bit Error Rate

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

73.7

31

.4

69

72

69

71

70

70

.4

.1

.2

.6

.3

.9

42

35

42

35

46

38

.9

.1

.9

.8

.3

.3

CIFAR-100 pre-trained ResNet18

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

73.5

35

.7

72

73

71

72

70

72

.0

.0

.7

.8

.8

.6

40

37

41

38

45

39

.8

.4

.7

.9

.3

.6

CIFAR-100 pre-trained ResNet50

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

64.8

31

.3

63

63

64

63

63

63

.9

.9

.0

.5

.5

.8

42

41

42

36

40

35

.4

.8

.8

.1

.9

.7

CIFAR-100 pre-trained VGG11

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

67.8

31

.1

64

66

65

64

64

65

.9

.0

.0

.9

.8

.0

44

36

46

38

46

39

.9

.3

.6

.1

.8

.8

CIFAR-100 pre-trained VGG16

w/o NF

ConvL

ConvS

DeConvS

UNetL

UNetS

67.8

42

.1

66

67

67

67

67

67

.9

.7

.3

.7

.4

.5

49

45

49

45

50

46

.2

.3

.8

.7

.0

.6

CIFAR-100 pre-trained VGG19

(c) CIFAR-100,

0

.

35%

Bit Error Rate

G Additional Experimental Results on Restricted Access Settings (Transferability)

We conduct more experiments with Restricted Access settings to show that our NeuralFuse can be transferred to protect various black-box models. The experimental results are shown in Sec. G.1 (CIFAR-10), Sec. G.2 (GTSRB), and Sec. G.3 (CIFAR-100).

We find that using VGG19 as a white-box surrogate model has better transferability than ResNet18 for all datasets. In addition, we can observe that some NeuralFuse generators have downward applicability if base models have a similar architecture. In other words, if we try to transfer a generator trained on a large BER (e.g., 1%) to a model with a small BER (e.g., 0.5%), the performance will be better than that of a generator trained with the original BER (e.g., 0.5%). For example, in Table 16, we could find that if we use VGG19 as a source model to train the generator ConvL (1%), the generator could deliver better performance (in terms of PA (NF)) when applied to similar base models (e.g., VGG11, VGG16, or VGG19) under a 0.5% BER, compared to using itself as a source model (shown in Table 12). We conjecture that this is because the generators trained on a larger BER can also cover the error patterns of a smaller BER, and thus they have better generalizability across smaller B.E.Rs.

To further improve the transferability to cross-architecture target models, we also conduct an experiment in Sec. G.4 to show that using ensemble-based training can help the generator to achieve this feature.

G.1 CIFAR-10

The results of CIFAR-10 in which NeuralFuse is trained at 1% BER are shown in Table 16.

Note . SM: source model, used for training generators; TM: target model, used for testing generators; BER: the bit-error rate of the target model; CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

G.2 GTSRB

In Tables 17 and 18, we show the results on GTSRB in which NeuralFuse is trained at 1.5% and 1% BER, respectively.

Note . SM: source model, used for training generators; TM: target model, used for testing generators; BER: the bit-error rate of the target model; CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

Note . SM: source model, used for training generators; TM: target model, used for testing generators; BER: the bit-error rate of the target model; CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

G.3 CIFAR-100

In Tables 19 and 20, we show results on CIFAR-100 with NeuralFuse trained at 1% and 0.5% BER, respectively.

G.4 Generator Ensembling

To improve the transferability performance on cross-architecture cases (e.g., using ResNet-based models as surrogate models to train NeuralFuse and then transfer NeuralFuse to VGG-based target models), we try to adopt ensemble surrogate models to train our NeuralFuse. The experimental results are shown in Table 21. We use the same experimental settings mentioned in Table 1 but change one source model (e.g., ResNet18 or VGG19) into two (ResNet18 with VGG19) for training. The results show that the overall performance is better than the results shown in Table 1, which means ensemble-based training can easily solve the performance degradation on cross-architecture target models.

Note . SM: source model, used for training generators; TM: target model, used for testing generators; BER: the bit-error rate of the target model; CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

H NeuralFuse on Reduced-precision Quantization and Random Bit Errors

As mentioned in Sec. 4.6, we explore the robustness of NeuralFuse to low-precision quantization of model weights and consider the case of random bit errors. Here, we demonstrate that NeuralFuse can recover not only the accuracy drop due to reduced precision, but also the drop caused by low-voltageinduced bit errors (0.5% BER) under low precision. We selected two NeuralFuse generators (ConvL and UNetL) for our experiments, and these generators were trained with the corresponding base models (ResNet18 and VGG19) at 1% BER (CIFAR-10, GTSRB) and 0.5% BER (ImageNet-10). The experimental results are shown as follows: CIFAR-10 (Sec. H.1), GTSRB (Sec. H.2), and ImageNet-10 (Sec. H.3). Similarly, for ease of comparison, we visualize the experimental results in the figures below each table. Our results show that NeuralFuse can consistently perform well in low-precision regimes as well as recover the low-voltage-induced accuracy drop.

H.1 CIFAR-10

Note . CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

Original Accuracy

w/o NeuralFuse

NeuralFuse (ConvL)

NeuralFuse (UNetL)

8

7

6

5

4

3

2

Bit Quantization Number

92.6

Accuracy (%)

92

92

92

92

91

84

.6

.5

.6

.4

.8

.8

90

90

90

90

90

89

.4

.4

.4

.4

.0

.9

89

89

89

89

89

88

.7

.6

.7

.7

.7

.9

10

.010

.010

.0

CIFAR-10 pre-trained ResNet18 (Nominal voltage, No Bit Error)

(a) Base Model: ResNet18, no bit error.

8

7

6

5

4

3

2

Bit Quantization Number

Accuracy (%)

70

68

68

52

26

11

.1

.8

.4

.7

.3

.3

87

87

87

78

40

11

.9

.5

.0

.8

.0

.6

88

85

84

77

42

12

.1

.2

.9

.4

.4

.6

10

.010

.010

.0

CIFAR-10 pre-trained ResNet18 (Low voltage, 0.5% BER)

(b) Base Model: ResNet18, 0.5% B.E.R.

8

7

6

5

4

3

2

Bit Quantization Number

90.5

Accuracy (%)

90

90

90

90

87

78

.5

.3

.1

.2

.5

.3

90

90

90

90

90

89

.4

.3

.4

.3

.1

.4

89

89

89

88

88

87

.1

.1

.2

.9

.6

.3

10

.010

.010

.0

CIFAR-10 pre-trained VGG19 (Nominal voltage, No Bit Error)

(c) Base Model: VGG19, no bit error.

8

7

6

5

4

3

2

Bit Quantization Number

Accuracy (%)

64

66

59

37

14

10

.2

.5

.8

.7

.7

.5

88

88

85

60

19

10

.1

.0

.5

.1

.5

.4

85

84

82

60

19

10

.0

.7

.0

.2

.8

.9

10

.010

.010

.0

CIFAR-10 pre-trained VGG19 (Low voltage, 0.5% BER)

(d) Base Model: VGG19, 0.5% B.E.R.

H.2 GTSRB

Original Accuracy

w/o NeuralFuse

NeuralFuse (ConvL)

NeuralFuse (UNetL)

8

7

6

5

4

3

2

Bit Quantization Number

95.5

Accuracy (%)

95

95

95

95

92

67

.5

.5

.4

.4

.6

.7

93

93

93

93

93

92

.4

.3

.3

.3

.3

.0

96

96

96

96

96

95

.2

.2

.2

.2

.1

.7

3

.8

3

.8

3

.8

GTSRB pre-trained ResNet18 (Nominal voltage, No Bit Error)

(a) Base Model: ResNet18, no bit error.

8

7

6

5

4

3

2

Bit Quantization Number

Accuracy (%)

75

69

67

48

24

5

.2

.5

.2

.6

.6

.3

89

89

88

79

52

9

.5

.9

.9

.3

.1

.7

93

94

93

87

62

12

.5

.5

.5

.5

.2

.6

3

.8

3

.8

3

.8

GTSRB pre-trained ResNet18 (Low voltage, 0.5% BER)

(b) Base Model: ResNet18, 0.5% B.E.R.

8

7

6

5

4

3

2

Bit Quantization Number

95.5

Accuracy (%)

95

95

95

95

92

60

.5

.6

.3

.2

.0

.0

95

95

95

95

95

91

.6

.6

.6

.5

.1

.0

94

94

95

94

94

90

.9

.9

.0

.7

.3

.8

5

.9

5

.9

5

.9

GTSRB pre-trained VGG19 (Nominal voltage, No Bit Error)

8

7

6

5

4

3

2

Bit Quantization Number

Accuracy (%)

69

66

64

48

18

2

.1

.1

.2

.2

.2

.0

93

90

91

80

37

1

.4

.4

.3

.2

.1

.8

91

90

89

77

39

1

.7

.0

.6

.6

.0

.8

3

.8

3

.8

3

.8

GTSRB pre-trained VGG19 (Low voltage, 0.5% BER)

(c) Base Model: VGG19, no bit error.

(d) Base Model: VGG19, 0.5% B.E.R.

H.3 ImageNet-10

Note . CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

Original Accuracy

w/o NeuralFuse

NeuralFuse (ConvL)

NeuralFuse (UNetL)

8

7

6

5

4

3

2

Bit Quantization Number

92.2

Accuracy (%)

92

92

92

91

91

85

.2

.4

.4

.0

.4

.2

94

94

94

94

93

89

.0

.2

.2

.2

.8

.2

94

93

93

94

92

89

.0

.6

.6

.0

.6

.4

10

.010

.010

.0

ImageNet-10 pre-trained ResNet18 (Nominal voltage, No Bit Error)

(a) Base Model: ResNet18, no bit error.

8

7

6

5

4

3

2

Bit Quantization Number

Accuracy (%)

72

70

68

60

47

28

.3

.6

.9

.9

.4

.8

88

86

85

82

68

44

.0

.7

.1

.5

.6

.1

88

87

86

83

68

42

.1

.8

.4

.2

.7

.7

10

.010

.010

.0

ImageNet-10 pre-trained ResNet18 (Low voltage, 0.5% BER)

(b) Base Model: ResNet18, 0.5% B.E.R.

8

7

6

5

4

3

2

Bit Quantization Number

92.4

Accuracy (%)

92

92

92

92

89

46

.4

.0

.4

.0

.4

.8

91

91

91

91

90

83

.4

.2

.0

.6

.8

.2

89

89

89

89

89

84

.4

.4

.4

.0

.6

.2

10

.010

.010

.0

ImageNet-10 pre-trained VGG19 (Nominal voltage, No Bit Error)

(c) Base Model: VGG19, no bit error.

8

7

6

5

4

3

2

Bit Quantization Number

Accuracy (%)

37

27

27

15

12

9

.2

.3

.9

.1

.2

.9

75

59

59

23

14

10

.5

.3

.7

.1

.0

.4

77

65

64

27

14

9

.9

.4

.9

.9

.6

.9

10

.010

.010

.0

ImageNet-10 pre-trained VGG19 (Low voltage, 0.5% BER)

(d) Base Model: VGG19, 0.5% B.E.R.

I Additional Experiments on Adversarial Training

Adversarial training is a common strategy to derive a robust neural network against certain perturbations. By training the generator using adversarial training proposed in Stutz et al. [2021], we report its performance against low voltage-induced bit errors. We use ConvL as the generator and ResNet18 as the base model, trained on CIFAR-10. Furthermore, we explore different K flip bits as the perturbation on weights of the base model during adversarial training, and then for evaluation, the trained-generator will be applied against 1% of bit errors rate on the base model. The results are shown in Table 25. After careful tuning of hyperparameters, we find that we are not able to obtain satisfactory recovery when adopting adversarial training. Empirically, we argue that adversarial training may not be suitable for training generator-based methods.

J Additional Experiments on Robust Model Trained with Adversarial Weight Perturbation with NeuralFuse

Previously, Wu et al. [2020] proposed that one could obtain a more robust model via adversarial weight perturbation. To seek whether such models could also be robust to random bit errors, we

Note . CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: Neural- Fuse; and RP: total recovery percentage of PA (NF) vs. PA

conducted an experiment on CIFAR-10 with the proposed adversarially trained PreAct ResNet18. The experimental results are shown in Table 26. We find that the average perturbed accuracy is 23% and 63.2% for PreAct ResNet18 under 1% and 0.5% BER, respectively. This result is lower than 38.9% and 70.1% from ResNet18 in Table 12, indicating their poor generalization ability against random bit errors. Nevertheless, when equipped NeuralFuse on the perturbed model, we could still witness a significant recover percentage under both 1% and 0.5% BER This result further demonstrates that NeuralFuse could be adapted to various models (i.e., trained in different learning algorithms).

Note . BER: the bit-error rate of the base model; CA ( % ): clean accuracy; PA ( % ): perturbed accuracy; NF: NeuralFuse; and RP: total recovery percentage of PA (NF) vs. PA

K Data Embeddings Visualization

To further understand how our proposed NeuralFuse works, we visualize the output distribution from the final linear layer of the base models and project the results onto the 2D space using t-SNE [van der Maaten and Hinton, 2008]. Figure 15 shows the output distribution from ResNet18 (trained on CIFAR-10) under a 1% bit error rate. We chose two generators that have similar architecture: ConvL and ConvS, for this experiment. We can observe that: (a) The output distribution of the clean model without NeuralFuse can be grouped into 10 classes denoted by different colors. (b) The output distribution of the perturbed model under a 1% bit error rate without NeuralFuse shows mixed representations and therefore degraded accuracy. (c) The output distribution of the clean model with ConvL shows that applying NeuralFuse will not hurt the prediction of the clean model too much (i.e., it retains high accuracy in the regular voltage setting). (d) The output distribution of the perturbed model with ConvL shows high separability (and therefore high perturbed accuracy) as opposed to (b). (e)/(f) shows the output distribution of the clean/perturbed model with ConvS. For both (e) and (f),

we can see nosier clustering when compared to (c) and (d), which means the degraded performance of ConvS compared to ConvL. The visualization validates that NeuralFuse can help retain good data representations under random bit errors and that larger generators in NeuralFuse have better performance than smaller ones.

(a)

(b)

(c)

(d)

(e)

(f)

Clean modelwithout NeuralFuse.Accuracy=92.6%

Perturbed model without NeuralFuse. Accuracy=35.41%

Clean modelwithNeuralFuse.Accuracy=89.78%

CleanmodelwithNeuralFuse.

.Accuracy=88.24%

L Qualitative Analysis of Transformed Inputs

In this section, we conduct a qualitative study to visualize the images transformed by NeuralFuse and present some properties and observations of these images. We utilize six different architectures of NeuralFuse generators trained with ResNet18 under a 1% bit error rate.

Figure 16 (a) showcases several images from the truck class in CIFAR-10. Notably, images of the same class, when transformed by the same NeuralFuse, exhibit similar patterns, such as circles symbolizing the wheels of the trucks.

In Figures 16 (b) and 16 (c), we observe analogous phenomena in the GTSRB and CIFAR-100 datasets. Transformed images of the same class using the same generator consistently display patterns. On GTSRB, NeuralFuse-generated patterns highlight the sign's shape with a green background, even if the original images have a dark background and are under different lighting conditions. These results further underscore the efficacy and efficiency of NeuralFuse.

Figure 17 presents more images from different classes in (a) CIFAR-10, (b) GTSRB, and (c) CIFAR100. The transformed images exhibit distinct patterns for each class, suggesting that NeuralFuse effectively transforms images into class-specific patterns, making associated features robust to random bit errors and easily recognizable by the base model in low-voltage settings.

Clean

ConvL

ConvS

DeConvS

UNetL

UNetS

(a)

Truck

class in CIFAR-10.

(b)

No Passing

sign in GTSRB.

(c)

Apple

class in CIFAR-100.

Ahhi

Clean

ConvL

ConvS

DeConvS

UNetL

UNetS

(a) 10 classes sampled from CIFAR-10

(b) 10 traffic signs sampled from GTSRB

Clean

ConvL

ConvS

DeConvS

UNetL

UNetS

30

50

80

30

[50

30

50

00

39

50

301

30

(c) 20 classes sampled from CIFAR-100

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Peer reviews:
comments: SUMMARY:
The paper proposes a method to handle the errors when reducing the voltage of SRAM to reduce the power consumption. The method is based on preprocessing the input data into error-resilient forms. Experiments show a tradeoff with a reduction of 24% of power and 2-3% accuracy loss in CIFAR10-ResNet settings.

STRENGTHS:
1. The reduction of SRAM power is appreciated to lower the cost.
2. The training method to recovered accuracy at 1% weight bit errors is also important.

WEAKNESSES:
1. Reduction of voltage of SRAM requires hardware access and will cause more errors than the ideal uniform bit flipping errors. I think tolerating 1% error is useful and interesting, but the motivation might be from more than lowering the SRAM voltages.

2. I did not catch what if the weights in the generator (preprocessing) of the image has bit errors or not. Is it? If the generator network is assumed error free, then it seems not consistent with the overall system configuration.

3. By reducing the power by 30%, the accuracy loss of CIFAR10 dataset is 2-3%. The worth of the tradeoff is debatable. What if I use a 30% smaller network and use full power of SRAM? In the experiment, clearly ResNet50 and ResNet18 has the same clean accuracy, but ResNet18 is 3 times smaller. So one could easily achieve 3x power reduction by using ResNet18 instead of ResNet50. More rigorous experiment setup needs to be considered to validate the motivation of the paper: Why one would make tradeoffs by reducing SRAM's voltage to suffer bit-errors rather than using a smaller network? This is my major concern.

QUESTIONS:
The questions are listed in the "weakness"

LIMITATIONS:
n/a
TITLE: Official Review
SOUNDNESS_CORRECTNESS: 3
DATE: 2024-07-11

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper presents NeuralFuse, a module that produces error-resistant data representations by learning input transformations in order to solve the accuracy loss of deep neural networks (DNNs) brought on by low-voltage-induced bit errors in SRAM, allowing DNNs to continue operating accurately even at low voltage without the need for model retraining. NeuralFuse was tested on multiple models and datasets, and it showed that it could recover accuracy by reasonable margin and save SRAM access energy. It supports two scenarios: restricted access, which trains using a white-box surrogate model, and relaxed access, which permits backpropagation. NeuralFuse exhibits robustness against low-precision quantization and is transferrable and adaptable. The authors argue that this development may be helpful for edge devices and on-chip AI.\n\nSTRENGTHS:\n1.\tThe proposed NeuralFuse operates as an add-on module, meaning it can be integrated with existing DNNs without requiring modifications of the base models. This non-intrusive approach makes it applicable to various models and scenarios, including those with limited access to model internals like cloud APIs\n2.\tThe results demonstrate high robustness to low-voltage-induced bit errors and low-precision quantization. It shows reasonable performance recovery across different datasets and architectures and its high transferability and adaptability to unseen models \n3.\tExperimentation shows that during low-voltage operation, it can recover performance drop due to bit error with energy efficiency as fringe benefit\n\nWEAKNESSES:\n1.\tAuthors assume that NeuralFuse module itself is bit error free due to low voltage of SRAM, claiming that its function can be performed by general purpose core operating in nominal voltage. However, in that case, the latency of running this module will be order of magnitude higher during inference time, and the total power consumption might even be higher than base model. If instead it is run on SRAM, then it itself should be vulnerable to bit error, whose analysis is not done. From the writing, it may be assumed that the energy and latency calculation in Appendix C and D is done assuming the proposed module is in SRAM, which will change drastically if we assume that Neuralfuse operation is performed by CPU.\n2.\tIt is seen from Figure 3 and Table-1 that in bigger models (e.g: ResNet-50), the standard deviation of performance is very high for different random test bit error patterns and furthermore, the smaller the generator architecture, the worse the performance in general. So, to scale up the performance, bigger generators might be needed, which in turn will be harder to optimize and more resource consuming.\n3.\tThe authors claim that their approach has advantage over previous methods because it does not retrain base model, however, the training of generator itself has been shown to be equally hard and time-consuming, which may scale up for bigger base models or generators, so the advantage here is not very apparent.\n4.\tIf the base model is running in nominal voltage, then there should not be any bit error and in that case, the added NeuralFuse module will only increase latency and power loss with performance decrease added to it due to transformation of input to base model. So, it is only logical to adopt an adaptive approach where this module is only applicable when the SRAM voltage goes below minimum required voltage\n\nQUESTIONS:\nRefer to the weakness section.\n\nLIMITATIONS:\nI have raised some concerns in the weaknesses section. Those are some possible limitations of this work. The authors may work on these points to overcome the limitation of their work.", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 3, "SOUNDNESS_CORRECTNESS": 2, "DATE": "2024-07-12"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThe paper presents NeuralFuse, a novel approach to address the accuracy degradation of deep neural networks (DNNs) in low-voltage regimes. The core idea is to learn an input transformation module that can generate error-resistant data representations, thereby protecting DNN accuracy even when bit errors occur due to voltage scaling. The proposed method is model-agnostic and doesn't require retraining of the deployed DNNs, making it suitable for access-limited scenarios like cloud-based APIs or non-configurable hardware. Experimental results demonstrate that NeuralFuse can significantly recover accuracy while achieving energy savings.\n\nSTRENGTHS:\n1. Novelty and Practicality: The paper introduces a new perspective on mitigating the impact of bit errors in low-voltage DNN inference by focusing on input transformation. This approach is model-agnostic and doesn't necessitate retraining, making it practical for real-world scenarios where model access is limited.\n\n2. Effectiveness: The experimental results across various datasets, DNN models, and NeuralFuse implementations showcase the effectiveness of the proposed method in recovering accuracy and achieving energy savings. The paper also demonstrates the versatility of NeuralFuse in handling low-precision quantization and adversarial weight perturbation.\n\n3. Thorough Evaluation: The paper provides a comprehensive evaluation of NeuralFuse, including ablation studies, comparisons with baselines, and qualitative analysis, which strengthens the validity of the claims.\n\nWEAKNESSES:\n1. Limited Evaluation on Complex Models and Tasks: The evaluation of NeuralFuse is primarily focused on image classification tasks using CNN-based models. It would be beneficial to assess its performance on more complex tasks, such as object detection or natural language processing, and with different types of neural networks, such as Transformers or RNNs, to ensure its broader applicability.\n\n2. Lack of Comparison with Post-Training Quantization: The paper demonstrates the effectiveness of NeuralFuse in recovering accuracy loss due to quantization. However, it would be valuable to compare its performance with post-training quantization techniques that also aim to reduce model size and energy consumption without retraining.\n\n3. Applicability to Dynamic Voltage Scaling: The paper assumes a fixed low-voltage setting during inference. It would be valuable to explore the applicability of NeuralFuse in scenarios with dynamic voltage scaling, where the voltage might change during inference based on the workload or energy constraints.\n\n4. Impact of NeuralFuse on Interpretability: Does the input transformation introduced by NeuralFuse affect the interpretability of the base model? It would be interesting to analyze how NeuralFuse impacts the ability to explain the model's decisions.\n\nQUESTIONS:\n1. Potential for Hardware Acceleration of NeuralFuse: The NeuralFuse module itself might introduce computational overhead. Could NeuralFuse be implemented or accelerated in hardware to minimize its impact on inference latency and energy consumption?\n\n2. Limited Exploration of the Impact on Latency: While the paper acknowledges the latency overhead introduced by NeuralFuse, a more detailed analysis of its impact on real-time applications would be beneficial. It would be valuable to quantify the latency overhead for different NeuralFuse architectures and base models.\n\n3. Assumption of Random Bit Errors: The paper assumes a random distribution of bit errors. However, in practice, bit errors might exhibit spatial or temporal correlations. It's worth investigating the robustness of NeuralFuse to different bit error patterns.\n\nLIMITATIONS:\n1. Potential for Adversarial Attacks on NeuralFuse: The paper doesn't discuss the potential for adversarial attacks specifically targeting the NeuralFuse module. It's worth investigating whether the input transformations introduced by NeuralFuse could be exploited to craft adversarial examples that bypass the error resistance mechanism.", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 4, "SOUNDNESS_CORRECTNESS": 2, "DATE": "2024-07-12"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThe authors train an input pre-processing module which aims to counteract the effects of random bit errors induced by low-voltage SRAM operation. They demonstrate the ability to avoid most accuracy drops on a handful of CNNs while operating in a 0.5-1% error regime.\n\nDisclosure: I have reviewed this paper in the past. I stand by much of my previous review, as the paper has not changed substantially.\n\nSTRENGTHS:\nThe paper takes a rather unique approach to trying to counteract bit errors. Instead of fixing the model or the hardware (both of which have been studied extensively, as the authors admit), they pre-transform the input to avoid stepping in areas of the input space which are vulnerable to random bit errors in the model weights.\n\nThe paper is clearly scoped. The authors avoid some common pitfalls with energy cost savings (e.g., they account for the costs of their own technique), and the explanation of end-to-end considerations was probably necessary for readers not used the HW energy measurement. Overall, I felt that the authors did a solid job of balancing practicality (don't want to get too far into SRAM design tweaks) and depth (the energy simulation setup seems like a very reasonable configuration).\n\nThe authors' actual learned model is fairly simplistic. Perhaps others might see this as a weakness, but as I see it, the benefit of this paper is in following the authors' perspective flip to its logical conclusion. If further work wants to attempt something more sophisticated for $\\mathcal{G}(x)$, great. Better surrogates for transfer? Sure. Plenty of room to follow-on later, if someone wants.\n\nUltimately, I see this work as a \"perspective paper\". The energy savings are not anything to write home about, but the approach is qualitatively different, and that makes it valuable. It's healthy to have a method that attacks the problem from a different angle, even if it doesn't quite stack up to state of the art. By analogy, it's worth exploring a very early automobile even if a horse can outrun it---maybe there's more down this road, maybe not. But the authors have at least shown that you can do *something* here, and the explanation and foundation they've provided is stable enough to build on.\n\nWEAKNESSES:\nThe authors' approach is not competitive with most existing HW techniques addressing low-voltage operation. This is less bad than it sounds. NeuralFuse bolts a model on to the front of an existing not-optimized-for-robustness model and tries to make the best of things. If one can add low-voltage-aware hardware modifications or low-voltage-aware models, one should. This doesn't make NeuralFuse a bad idea, but it probably does mean that HW, SW, and model builders should be trying to avoid the scenarios where NeuralFuse would be useful. This ultimately limits the practical utility of the approach.\n\nI was a bit underwhelmed by the actual reported energy/accuracy values achieved. One of the elephants in the room that the authors skirt around is the zero accuracy degradation scenario. In order for a real-world operator to accept any kind of accuracy degradation, the power savings must be *enormous*, usually measured in factors (i.e. a 5x or 10x reduction for a 1% error loss would be reasonable). In order to get good power savings, you really want to be aggressive lowering the voltage, but BER skyrockets with even small adjustments. So this is kind of the name of the game in low-voltage fault tolerance: it's a lot easier to get energy savings by allowing accuracy drop. But the test that usually separates wheat from the chaff is when you dial that down to zero measurable accuracy drop. You can always say \"well there's a trade-off a user can adjust\", but in this case, the \"trade-off\" is dominated by one end of the spectrum, and if there's not a lot of savings in that area, then it kind of condemns the approach.\n\nQUESTIONS:\nFeel free to address the zero accuracy degradation scenario above. (I'll note that there are plenty of other papers from the HW community that do solve this problem without accuracy loss, so while I accept that the authors' approach is different---and valuably so, I'm not willing to accept an argument that it's an unreasonably high bar. Just harder.)\n\nLIMITATIONS:\nAddressed above. No societal concerns.", "TITLE": "Official Review", "RECOMMENDATION": 7, "REVIEWER_CONFIDENCE": 4, "SOUNDNESS_CORRECTNESS": 4, "DATE": "2024-07-12"}