Title: Macro Placement by Wire-Mask-Guided Black-Box Optimization
Venue: NeurIPS 2023
Accepted: yes
Keywords: Black Box Optimization

Macro Placement

Electronic Design Automation

Reinforcement Learning

Application
Abstract: The development of very large-scale integration (VLSI) technology has posed new challenges for electronic design automation (EDA) techniques in chip floorplanning. During this process, macro placement is an important subproblem, which tries to determine the positions of all macros with the aim of minimizing half-perimeter wirelength (HPWL) and avoiding overlapping. Previous methods include packing-based, analytical and reinforcement learning methods. In this paper, we propose a new black-box optimization (BBO) framework (called WireMask-BBO) for macro placement, by using a wire-mask-guided greedy procedure for objective evaluation. Equipped with different BBO algorithms, WireMask-BBO empirically achieves significant improvements over previous methods, i.e., achieves significantly shorter HPWL by using much less time. Furthermore, it can fine-tune existing placements by treating them as initial solutions, which can bring up to 50% improvement in HPWL. WireMask-BBO has the potential to significantly improve the quality and efficiency of chip floorplanning, which makes it appealing to researchers and practitioners in EDA and will also promote the application of BBO. Our code is available at https://github.com/lamda-bbo/WireMask-BBO.

Macro Placement by Wire-Mask-Guided Black-Box Optimization

Abstract

The development of very large-scale integration (VLSI) technology has posed new challenges for electronic design automation (EDA) techniques in chip floorplanning. During this process, macro placement is an important subproblem, which tries to determine the positions of all macros with the aim of minimizing half-perimeter wirelength (HPWL) and avoiding overlapping. Previous methods include packingbased, analytical and reinforcement learning methods. In this paper, we propose a new black-box optimization (BBO) framework (called WireMask-BBO) for macro placement, by using a wire-mask-guided greedy procedure for objective evaluation. Equipped with different BBO algorithms, WireMask-BBO empirically achieves significant improvements over previous methods, i.e., achieves significantly shorter HPWL by using much less time. Furthermore, it can fine-tune existing placements by treating them as initial solutions, which can bring up to 50% improvement in HPWL. WireMask-BBO has the potential to significantly improve the quality and efficiency of chip floorplanning, which makes it appealing to researchers and practitioners in EDA and will also promote the application of BBO. Our code is available at https://github.com/lamda-bbo/WireMask-BBO .

1 Introduction

EDA techniques have been widely employed to assist engineers in designing chips [30, 31], while the rapid advancement of VLSI technology has led to an exponential growth in chip scale, posing significant challenges. Particularly, for the important chip floorplanning stage in EDA, which strives to optimize power, performance, and area metrics while adhering to constraints such as congestion and density [45], the number of cells to be placed on the chip canvas increases rapidly and their routing relationships also become more complex, requiring innovative and efficient methods.

During the floorplanning placement stage, the position of each cell on the chip canvas is established. A modern chip typically comprises thousands of macros (i.e., individual building blocks such as memories) and millions of standard cells (i.e., smaller basic components like logic gates). The designer provides a netlist, which outlines the design requirements and serves as a large-scale hypergraph containing numerous hyper-edges (also called nets) that represent the routing relationships among macros and standard cells. Traditionally, the placement problem is divided into two successive stages [4]: macro placement, which is usually addressed by heuristic or learning methods [42, 44], and standard cell placement, which is usually addressed by analytical solvers [13, 28]. After placing all the cells (including macros and standard cells), a routing stage is performed. The general flow of chip floorplanning and routing is illustrated in Figure 1. In this work, we concentrate on macro placement due to its greater impact on placement quality: Macros are often larger and more crucial for achieving optimal placement [4, 47].

Canvas

Macros

Macro

Placement

Placement

Earlier methods often formulate macro placement as a rectangular packing problem, where solutions are represented by sequence pair (SP) [33], B ∗ -tree [11], corner block list (CBL) [19] or other data structures [34, 27], and solve it by simulated annealing (SA) [1, 18, 24, 40]. This kind of method suffers from the poor scalability due to the quadratic complexity of decoding a genotype solution to a phenotype placement. Analytical methods [12, 13, 28, 29] place macros and standard cells simultaneously, and relax the task to a mathematical programming problem, which can be solved efficiently. However, they cannot guarantee the non-overlapping between cells, which is a hard constraint of cell placement. More recently, by dividing the chip canvas into discrete grids and formulating the task of placing macros onto grids step by step as a Markov decision process (MDP), reinforcement learning (RL) methods have been applied, showing promising performance [14, 15, 26, 32]. But their fast convergence (after only a few hundred evaluations) observed in experiments may imply that the huge search space of placement is still underexplored, and further improvement is expected. A detailed review of these existing methods is provided in Section 2.

In this paper, we propose a new BBO framework for macro placement. To allow better exploration, a solution is directly represented by the coordinates of all macros on the chip canvas. HPWL is used as the minimization objective function. The key of our framework is that in order to improve efficiency, we use an elaborate evaluation procedure, which greedily improves a solution (with the goal of minimizing HPWL while avoiding overlapping) before evaluation. Concretely, using the wire mask [26] to record the increment of HPWL by moving a macro to each candidate grid on the chip canvas, the macros in the solution are sequentially adjusted to the nearest best grid. This framework is briefly called WireMask-BBO, which can use any BBO algorithm to solve the resulting problem.

Experimental results on multiple popular benchmarks demonstrate that WireMask-BBO, when equipped with different BBO algorithms such as random search (RS), Bayesian optimization (BO), and evolutionary algorithms (EA), significantly outperforms the compared representative methods, including traditional BBO methods based on packing formulation, analytical methods, and RL methods. Especially, WireMask-EA (i.e., WireMask-BBO equipped with EA) generates the highest-quality placement in 6 out of 7 different chip benchmarks, and surpasses the state-of-the-art MaskPlace [26] in 8 minutes on average. Besides, as an optimization-based method, WireMask-BBO can fine-tune any existing placement, regardless of how it was generated. That is, WireMask-BBO can be combined with any existing macro placement method as post-processing. Our experiments show that such fine-tuning can lead to an improvement of up to 50% in the objective HPWL.

Our main contribution is introducing the general framework WireMask-BBO, while not developing new BBO algorithms. In fact, our experiments show that even employing simple BBO techniques has led to superior performance over previous methods. We will open-source WireMask-BBO and use it as an optimization benchmark to encourage the invention of more efficient BBO algorithms for solving macro placement problems, as well as broaden the application scenario of BBO.

2 Background

In this section, we introduce the macro placement problem, and the existing methods which can be generally categorized into packing-based, analytical, and grid-based RL methods.

2.1 Macro Placement

The input for a macro placement problem constitutes a netlist H = ( V, E ) , where V denotes the information (i.e., height and width) about all cells designated for placement on the chip, and E is a hyper-graph comprised of hyper-edges e i ∈ E , which encompasses multiple cells (including both macros and standard cells) and signifies their interconnectivity during the routing phase. A macro placement solution consists of the positions of all macros { v i } k i =1 with the coordinates of each macro v i ∈ V on the chip canvas expressed as ( x i , y i ) , where k denotes the total number of marcros. To facilitate a comprehensive understanding of the macro placement problem, we present several key metrics for evaluating placement outcomes.

HPWL is the predominant metric for gauging placement quality, as it offers a precise estimation of the wirelength necessary for routing [9, 22, 38]. A shorter wirelength decreases delay and power consumption, enhancing overall performance [36]. To calculate HPWL of a macro placement solution s , each hyper-edge e j ∈ E corresponds to a rectangle area characterized by its lower-left endpoint, with coordinates ( min v i ∈ e j x i , min v i ∈ e j y i ), and its upper-right endpoint, with coordinates ( max v i ∈ e j x i , max v i ∈ e j y i ). That is, the rectangle is the smallest one bounding all cells within e j . Let w j = max v i ∈ e j x i -min v i ∈ e j x i and h j = max v i ∈ e j y i -min v i ∈ e j y i denote the width and height of the rectangle, respectively. Then,

Congestion serves as a vital metric in determining the routability of a given placement, exerting a direct influence on the manufacturing process. A widely-adopted approach for approximating congestion is rectangular uniform wire density (RUDY) [41]. The congestion of a grid on the canvas can be represented as the cumulative impact of all hyper-edge rectangle areas encompassing the grid. By selecting the top 10% congested grids (denoted as G ∗ ) and computing the mean of their congestion, the RUDY value of a macro placement solution is calculated as 1 | G ∗ | ∑ g i ∈ G ∗ ∑ e j ∈ E ( g i ) w j + h j w j · h j , where | G ∗ | is the size of G ∗ , E ( g i ) denotes the set of hyper-edges whose rectangle areas cover g i , and ( w j + h j ) / ( w j · h j ) measures the impact of the rectangle area of hyper-edge e j .

Density measures the overlap degree between cells by employing an electrostatic analogy [29]. It is often treated as a penalty to diminish overlap, yielding a more uniform distribution of cells across the chip area [4, 13, 28, 29]. Further discussion will not be provided here, as our formulation ensures non-overlapping, which is a hard constraint of macro placement.

Area denotes the area of the minimum bounding rectangle that encloses all the macros. It was prevalent when the focus was on tightly packing macros and minimizing the area they occupied [10, 42]. However, when considering fixed-area chips as in [15, 26, 28, 32] and our work, the placement of cells optimized is to reduce wirelength and congestion rather than minimize the area.

2.2 Packing-based Methods

As the focus was once on minimizing the bounding area of given macros, which can lead to a higher chip area utilization ratio [31], the packing formulation emerged as a natural and straightforward approach for the macro placement problem. Each macro, represented as a rectangle, has to be packed within a specified chip canvas, with the objective being to optimize the weighted sum of the area metric and HPWL metric. Several solution representation methods have been proposed, such as SP [33], B ∗ -tree [11], CBL [19], etc. These genotype solutions will be mapped to concrete macro placement (phenotype) solutions for evaluation. SA is often employed [1, 18, 24, 40] to solve such BBO problems by perturbing the genotype to generate new offspring solutions and evaluating the corresponding phenotype to determine whether to accept the perturbation.

To handle both macros and standard cells, a divide-and-conquer idea is introduced [39, 43]. The standard cells are first clustered into blocks using either the logical hierarchy or min-cut-based partitioning algorithms [23, 37]. Placement is then performed on the mix of macro blocks and clustered standard cell blocks, often by SA using packing formulation [1, 2]. Finally, the standard cells are re-allocated by detailed placement. While reducing the problem size, clustering standard cells into rectangular blocks may cut some connections and hinder finding an optimal solution.

Recently, RL has been introduced to decide which perturbation operator should be selected and which macro should be perturbed by SA [46]. Moreover, [5] formulates the CBL establishment as a

(a) SP-SA [33]: HPWL = 1 . 22 × 10 7 Congestion = 1.07

MDP and constructs a CBL genotype step by step. These advancements continue to grapple with the drawbacks of packing, such as poor scalability, which cannot be solved fundamentally because the drawbacks come from the quadratic complexity of mapping from genotype to phenotype [33]. Besides, at least one edge of each macro under the packing setting must be attached to another macro or the canvas's edge, making the placement quite congested, as visualized in Figure 2(a). Note that the congested macro placement will limit the space for subsequent standard cell placement, and lead to the bad performance of full placement, which will be shown in Table 3.

2.3 Analytical Methods

Analytical methods [12, 13, 28, 29] place macros and standard cells simultaneously, and relax the full placement task to a mathematical programming problem, which can be solved efficiently. For example, DREAMPlace [28], a state-of-the-art and highly efficient analytical placement method, recasts the full placement task as min WA ( s , H ) + λ · Density ( s , H ) , where WA represents the smooth weighted-average wirelength (originally proposed by [20]) for approximating HPWL, Density denotes a differentiable density metric for penalizing overlapping, and λ is a trade-off factor. This problem is then solved numerically using classical mathematical optimization techniques (e.g., gradient descent), to rapidly generate high-quality full placement. Figure 2(b) shows a macro placement generated by DREAMPlace, which is better than that generated by packing in Figure 2(a). However, analytical methods cannot guarantee the non-overlapping between cells. Even employing macro placement legalization techniques, numerous overlaps may persist [4].

2.4 Grid-based RL Methods

As the number of macros increases, packing-based methods encounter scalability challenges, while analytical methods may produce overlapping placements that are impractical for manufacturing [4]. To meet the demands of modern chip design and fully leverage RL, the Graph placement published in Nature [32] divides the chip canvas into discrete grids, with each macro assigned discrete coordinates of grids, and formulates the placement problem as a MDP, wherein the agent decides the placement of the next macro at each step. Notably, no reward is given until the final step, when all macros are placed. The ultimate reward is the weighted sum of HPWL and congestion. Compared with packing-based methods, the grid-based design eliminates edge attachment and provides room for standard cell placement while offering improved scalability. The length of the MDP grows linearly with the number of macros, as opposed to the quadratic complexity of packing formulation [33]. DeepPR [15] integrates convolutional and graph neural networks during the embedding stage, and introduces an intrinsic reward to promote exploration. However, DeepPR brings overlaps. Though PRNet [14] incorporates the overlap area into the reward function as a penalty, the non-overlapping issue still exists as observed in their experiments.

A key limitation of the above-mentioned methods is the absence of extrinsic rewards until the final step, leading to sub-optimal performance for a long MDP with over one thousand steps. To

address this issue, MaskPlace [26] introduces a dense reward RL pipeline, incorporating a view mask for gathering global information, a position mask to ensure non-overlapping, and a wire mask to evaluate the placement of the current macro. Notably, the wire mask offers an immediate reward, calculated as the increase in HPWL after placing the current macro. These three masks are processed by a convolutional neural network and serve as input features for both the value and policy networks. MaskPlace can generate high-quality non-overlapping placement results in an affordable time. Figure 2(c) gives a placement example, which is better than that generated by packing and analytical methods as shown in Figures 2(a) and 2(b). From the experiments in [26], we can also observe that MaskPlace converges after only a few hundred evaluations, implying that the huge search space of placement may be still underexplored. The experimental results in Section 4 will confirm this conjecture, showing that our proposed framework will bring significant improvement.

3 Proposed Framework WireMask-BBO

This section is devoted to our proposed WireMask-BBO, where Section 3.1 introduces the problem formulation and Section 3.2 is concerned with optimization methods to solve the resulting problem.

3.1 Wire-Mask-Guided Problem Formulation

Solution representation. To allow better exploration, a macro placement solution s is directly represented by the coordinates of all macros { v i } k i =1 , i.e., s = ( x 1 , y 1 , . . . , x k , y k ) , where ( x i , y i ) denotes the coordinates of the macro v i on the chip canvas. For example, there are three macros A, B and C for the placement task in Figure 3, and thus a solution s is represented by ( x 1 , y 1 , x 2 , y 2 , x 3 , y 3 ) .

Objective evaluation. The metric HPWL in Eq. (1) is used as the objective function to be minimized. But if optimizing in the solution space directly, it is difficult to efficiently find a solution that has a small HPWL value and satisfies the non-overlapping constraint. To improve the efficiency, a greedy improvement strategy is applied to a solution before evaluating it.

As in [32], the chip canvas is first divided into discrete grids. In the process of improving a solution greedily, each macro is moved to a grid by letting the macro's bottom-left corner situate at the bottom-left corner of the grid. The order of adjusting the position of a macro v i is determined by the area of all the cells connected with v i , i.e., all the cells in the hyper-edges containing v i . Note that each hyper-edge contains a set of connected cells. The positions of all macros will be adjusted sequentially in the decreasing order of their corresponding computed areas, because a macro with a larger computed area implies connecting with more large cells and thus is intuitively more important.

Let v ∗ 1 , . . . , v ∗ k denote the ordered macros. Assume that the positions of v ∗ 1 , . . . , v ∗ i -1 have been adjusted. When considering v ∗ i , a wire mask W i introduced in [26] is first computed, which records the increase of HPWL by placing v ∗ i to each candidate grid, given v ∗ 1 , . . . , v ∗ i -1 already adjusted. Note that those grids that will lead to overlap or exceeding the canvas boundary after placing v ∗ i are excluded. Then, v ∗ i is moved to the grid with the least increment of HPWL. If such a grid is not unique, v ∗ i is moved to the nearest one among them. This is actually a greedy step that moves v ∗ i to the grid with the least increment on HPWL given the placement of v ∗ 1 , . . . , v ∗ i -1 . This process is repeated until the positions of all the macros have been adjusted. The HPWL of the resulting solution with all the adjusted macros is treated as the objective value of the original solution. Thus, a solution and its improved version in objective evaluation can be viewed as the genotype and phenotype representation of a macro placement. The detailed process of objective evalution is presented in Algorithm 1.

Figure 3 gives an example illustration of objective evaluation. For the input netlist H = ( V, E ) , V contains three macros A, B and C, and the hyper-graph E contains two hyper-edges: one encompasses macros A and B, and the other encompasses A and C. Each hyper-edge signifies the interconnectivity of the macros contained by it. The chip canvas is partitioned into 5 × 5 grids. Assume that the width and height of each grid is both 1. The solution to be evaluated (as shown in Figure 3(a)) consists of the positions of macros A, B and C. According to the hyper-graph E , we know that during the routing phase, macro A is connected with B and C, while macro B and C are both connected with only A. Thus, the corresponding areas computed in line 1 of Algorithm 1 are decreasingly ordered as A, B and C, which is just the order in line 2 to adjust the positions of macros sequentially.

When trying to adjust the position of macro A, a wire mask is first computed as in line 5 of Algorithm 1, which is shown in Figure 3(b), where the number in each grid is the increment of HPWL

Algorithm 1 Objective evaluation of WireMask-BBO

Input : solution s , netlist H = ( V, E ) , and number m of partitions Output : improved solution s ′ , and the corresponding objective (i.e., HPWL) value Process :

1: For each macro v i ∈ V , compute the area of all the cells connected with it, i.e., ∪ v i ∈ e j ∈ E e j ;

3: Initialize the canvas as m × m grids, and let f = 0 ;

2: Order all macros decreasingly, denoted as v ∗ 1 , . . . , v ∗ k , according to their corresponding areas;

4: for each macro v ∗ i do

5: Generate wire mask W i according to the updated positions of v ∗ 1 , . . . , v ∗ i -1 (see Algorithm 1 in [26]), which records the increment of HPWL by moving v ∗ i to each candidate grid;

6: Q ← the set of grids that has the minimum increment of HPWL (denoted as f i ) in W i ;

8: Update the position of v ∗ i to be that of the grid g ;

7: Select the grid g from Q , which has the smallest Euclidean distance to the macro v ∗ i ;

9: f ← f + f i

10: end for

11: s ′ ← the updated positions of all the macros

12: return s ′ , f

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led by placing macro A in that grid. For example, if placing macro A in the center grid as shown in Figure 3(c), both the two hyper-edges correspond to the smallest rectangle bounding macro A (i.e., the red and black dotted square in Figure 3(c)) for computing HPWL in Eq. (1), and thus the corresponding HPWL is 6, which is the sum of half perimeters of these two rectangles. As the initial HPWL before placing macro A is 0, the increment of HPWL is 6. Note that when adjusting the position of a macro, its bottom-left corner must be situated at the bottom-left corner of a grid, and grids without numbers in the wire mask indicate that the current macro should not be placed there due to overlap or exceeding the canvas boundary. The underlined italic number in the wire mask denotes the least HPWL increment, representing the locally optimal choice, i.e., the set Q in line 6 of Algorithm 1. Then, as shown in lines 7-8 of Algorithm 1, macro A is placed at the local optimal grid, which has the smallest Euclidean distance to it. The coordinate of macro A in the original placement is denoted by the red star in Figure 3(b), and thus it is adjusted to be situated at the grid closest to it, as shown in Figure 3(c).

The positions of macros B and C are adjusted similarly. Figure 3(c) shows the adjusted placement of macro A, and also the wire mask when trying to place macro B. Figure 3(d) shows the adjusted placement of macros A and B, and also the wire mask when trying to place macro C. Figure 3(e) gives the final improved placement after adjusting the positions of all macros. As HPWL is the sum of all hyper-edges' bounding rectangles' half perimeters, these rectangles can be updated each time a macro is placed, as shown by the red and black dotted squares in Figure 3. That is, for any individual macro, it is only necessary to update the bounding rectangles of its associated hyper-edges and compute the increase in their half perimeters. Thus, the calculation of HPWL can be performed incrementally, as in line 9 of Algorithm 1. In Figure 3, the increment of HPWL after placing macros A, B and C is 6, 3 and 2, respectively, leading to the HPWL value 11 of the final improved placement. Note that the red and black dotted bounding rectangles in Figure 3 are shown for illustrative purposes, while the actual HPWL calculation in our experiments is based on pin information.

Therefore, we have formulated macro placement as a black-box optimization problem, where the genotype-phenotype mapping is greedily guided by wire mask. Figures 3(a) and (e) give an example of genotype and phenotype representation. An algorithm for solving this problem will search in the genotype space, where the goodness of a genotype solution is estimated by the objective value of its corresponding phenotype. When an algorithm terminates, the corresponding phenotype of the generated genotype solution will be output as the final macro placement. Note that by the wire-mask-guided mapping process, the phenotype solution is guaranteed to have no overlap, and thus an algorithm can search in the genotype space without considering constraints.

3.2 Black-Box Optimization

The above formulated problem can be solved by any BBO algorithm. In our experiments, we employ three simple ones, random search (RS), Bayesian optimization (BO) [17] and evolutionary algorithm (EA) [7]. RS randomly allocates all macros in a solution and evaluates it, recording the historical best. For BO, we adopt the efficient TuRBO approach [16] to directly optimize the continuous coordinates ( x 1 , y 1 , . . . , x k , y k ) of all macros, resulting in a dimension of 2 k , where k is the number of macros. For EA, we choose the simple (1+1)-EA [6, 49], which maintains only one solution and iteratively improves it by mutation. We design the mutation operator by randomly selecting two macros and exchanging their coordinates in a solution. Our experiments will show that using these three simple BBO algorithms has been sufficient for the superior performance over previous methods. It is expected to design better BBO algorithms for the proposed formulation of macro placement.

By adopting the grid-based discretization and designing the wire-mask-guided greedy genotypephenotype mapping, the proposed framework WireMask-BBO can efficiently generate a nonoverlapping high-quality placement, addressing the poor scalability issue of packing-based methods as well as the overlapping issue of analytical methods. The use of black-box optimization enhances the exploration ability, making WireMask-BBO able to surpass the state-of-the-art RL-based method MaskPlace [26]. Figure 2(d) visualizes a placement generated by WireMask-BBO equipped with EA, which is better than that by SP-SA (a representative packing-based method) [33], DREAMPlace (a representative analytical method) [28] and MaskPlace [26], as shown in Figures 2(a), 2(b) and 2(c).

4 Experiments

We mainly empirically test our method on the ISPD2005 benchmark [35], which was originally proposed as a standard cell placement benchmark with fixed macros. Following conventional practice [15, 14, 26], we modify all macros to be movable for the macro placement problem. The ISPD2005 benchmark contains eight chips, i.e., adaptec1-4 and bigblue1-4 . Note that for the bigblue2 chip, which has over 20,000 macros and 30,000 macro-related hyper-edges, a single objective evaluation by step-by-step placement costs more than an hour. Thus, we do not include this chip in our experiments as [26]. For each chip, the canvas is partitioned into approximately 150 × 150 grids heuristically. The detailed statistics (e.g., the number of macros, partitions, etc.) of the chips are provided in Appendix A.

We compare WireMask-BBO with several representative macro placement methods, including the packing-based SP-SA [33], three analytical methods NTUPlace3 [12], RePlace [13], DREAMPlace [28], and three RL-based methods Graph placement [32], DeepPR [15], MaskPlace [26]. As introduced in Section 3.2, we equip the proposed WireMask-BBO framework with RS, BO and EA,

denoted as WireMask-RS, WireMask-BO and WireMask-EA, respectively. For the employed method TuRBO [16] for BO, we use the common hyper-parameters. For the EA, its initial solution is set as the best among 100 random solutions. All experiments are run on two Intel Xeon Platinum 8171M CPUs, each with 26 cores and 52 threads.

Main results. Table 1 gives the detailed results of running each method using five random seeds. The runtime for each run of WireMask-BBO is set as 1,000 minutes. The results of analytical and RL-based methods are directly from [26]. Note that the analytical method NTUPlace3 is deterministic, and thus has no standard deviation. We compute the rank of each method on each chip as in [21], which are averaged in the last column of Table 1. WireMask-RS, WireMask-BO and WireMask-EA achieve the three highest ranks, disclosing the effectiveness of the proposed general framework WireMask-BBO. Among these three variants, WireMask-EA performs the best, which has the highest rank 1.43 and achieves the smallest HPWL value on 5 out of the 7 chips. RS relies solely on random sampling without leveraging any search history. BO performs well in many low-dimensional tasks (typically when the dimension d ≤ 20 [17]), but suffers from the curse of dimensionality due to the time-consuming cost of updating the Gaussian process surrogate model and optimizing the acquisition function [8]. For example, in our experiments where d (i.e., 2 times the number of macros) is always larger than 1000, EA can sample much more solutions (about 2-7 times as shown in Table 9 of Appendix B) than BO during the 1000-minutes running. Compared with any previous method, WireMask-EA is significantly better on at least 6 out of the 7 chips, by the Wilcoxon rank-sum test with significance level 0.05. It is outperformed by RePlace and DREAMPlace on the chip adaptec4 , implying the suitability of analytical methods for this particular problem.

Running time analysis. As shown in Table 1, any variant of WireMask-BBO always performs better than the state-of-the-art MaskPlace [26], which ranks the highest among the compared previous methods. While [26] did not offer explicit training time details, the authors state a 200-minute convergence time in response to our inquiry. Next, we examine the efficiency of WireMask-BBO when compared with MaskPlace. Taking MaskPlace as the baseline, we plot the curve of HPWL over the wall clock time for WireMask-BBO in Figure 4. Each variant of WireMask-BBO surpasses MaskPlace very quickly. Particularly, WireMask-EA requires only 39, 8, 0.37, 0.62, 0.15, and 3 minutes, respectively, with an average of 8 minutes to surpass MaskPlace across six benchmark chips. This is notably faster than the 200-minute convergence time reported for MaskPlace. We have excluded the bigblue4 chip in Figure 4, because the 1,000-minute search for WireMask-EA only completes its initialization on this large-scale chip. On the chips adaptec3 and adaptec4 , WireMaskEA actually outperforms MaskPlace after only a single greedy placement guided by wire mask, implying that MaskPlace fails to balance exploration and exploitation.

Performance on congestion metric. Aside from HPWL, congestion and density are also vital metrics as introduced in Section 2.1. As our framework WireMask-BBO maintains the non-overlapping property, density constraint does not need to be considered. Here, we evaluate placement congestion and compare it to the results of MaskPlace [26] and SP-SA [33] in Table 2. We normalize the congestion values by setting WireMask-EA's congestion to 1.00. The MaskPlace placements are provided by its authors 2 , while the SP-SA and WireMask-BBO placement results are obtained from a

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WireMask-BO

WireMask-EA

1,000-minute search using the same random seed. The results show that though optimizing HPWL, WireMask-BBO can also achieve smaller congestion. The reason is that the RUDY approximation of congestion is sometimes positively related to the HPWL metric. Given a macro placement solution, the HPWL in Eq. (1) is computed as the sum of the rectangle's half-perimeter of hyper-edge, i.e., ∑ e j ∈ E ( w j + h j ) , where e j denotes a hyper-edge, E denotes the hyper-graph comprised of all hyper-edges, w j and h j denote the width and height of the rectangle corresponding to e j , respectively. The RUDY measures the overall congestion on the canvas, and the congestion of each grid g i on the canvas is calculated by the cumulative impact of all hyper-edges encompassing the grid. Note that a hyper-edge e j will add an impact to each of its covered grids by 1 w j + 1 h j . Then, the overall congestion of all grids is ∑ g i ∑ e j ∈ E ( g i ) 1 w j + 1 h j = ∑ e j ∈ E w j · h j · ( 1 w j + 1 h j ) = ∑ e j ∈ E ( w j + h j ) = HPWL , where E ( g i ) denotes the set of hyper-edges whose corresponding rectangle covers the grid g i . The first equality holds because the number of times of a hyper-edge e j ∈ E enumerated in LHS is equal to the number of grids covered by it, which is w j · h j . Thus, we can observe a positive relation between RUDY and HPWL. Besides our results, Table 4 in MaskPlace [26] and Table 4 in ChiPFormer [25] have also shown that the best HPWL can lead to the best congestion. However, a lower HPWL does not necessarily lead to a lower RUDY, because RUDY only considers the top-10% congested grids as introduced in Section 2.1.

Full placement results. Table 3 shows the results of different methods on the full placement task involving both macros and standard cells. We utilize PRNet [14] and DREAMPlace [28] as baselines, because both of them are designed to handle mixed-size placement tasks. The other five macro placement methods first optimize the macro placement, fix the macro positions, and then employ DREAMPlace to optimize the standard cell placement exclusively. The mean ± std values are derived from DREAMPlace standard cell placement using five different random seeds. The results of PRNet are directly from [14]. Although WireMask-EA achieves the best performance on only one chip, i.e., adaptec4 , it attains the highest average rank. Compared with the mixed-size placement optimization methods PRNet and DREAMPlace, WireMask-EA does not explicitly optimize the full

placement wirelength; thus, its best overall performance confirms the contribution of high-quality macro placement to an overall superior final placement.

Fine-tuning results. In fact, WireMask-BBO can be combined with any existing macro placement method for post-processing. The placement generated by any existing method can be treated as the initial solution of WireMask-BBO and then further improved. Table 4 shows the HPWL results of SP-SA and MaskPlace before and after 1,000 minutes of fine-tuning by WireMask-EA, with the average improvement ratio of 53 . 93% and 17 . 06% , respectively. Compared to Table 1, fine-tuning the placement of MaskPlace leads to the best HPWL value on the two chips adaptec1 and bigblue1 .

Additional results. We propose a post local search procedure to further improve final placement results. We investigate the influence of the two hyper-parameters of WireMask-BBO, i.e., number of partitions in chip canvas discretization, and adjustment order of macros in objective evaluation. For WireMask-EA, the best-performed variant of WireMask-BBO, the influence of different mutation operators is also examined. We compare the number of evaluations of WireMask-BBO methods in 1000 minutes. Furthermore, we test on the ariane RISC-V CPU design benchmark [48], still showing the clear superiority of WireMask-BBO over previous methods. We finally include comparisons with two concurrent advanced methods, i.e., ChiPFormer [25] and AutoDMP [4], and our WireMask-EA still maintains the superior performance. These results are provided in Appendix B.

5 Conclusion

This paper proposes the general framework WireMask-BBO for macro placement, which adopts a wire-mask-guided greedy genotype-phenotype mapping and can be equipped with any BBO algorithm. Extensive experimental results show that WireMask-BBO is clearly superior to previous packingbased, analytical, and RL-based methods. Furthermore, it can be combined with any existing macro placement method to further improve the final placement. Though showing significant potential, WireMask-BBO also has some limitations. First, it can only deal with macro placement, leaving standard cells for analytical placers. Second, its performance is limited for chips with a large number of macros due to the expensive objective evaluation. This, however, can be alleviated by equipping with high-dimensional BBO algorithms [8] or designing specific efficient BBO algorithms for macro placement, which is a very interesting future work. Our method does not have negative social impacts.

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A Experimental Settings

The detailed statistics of benchmarks are in Table 5. Each column in the table represents the following:

#Macros: the number of macros.

#Standard cells: the number of standard cells.

#Hyper-edges: the number of hyper-edges.

#Macro-related Hyper-edges: the number of hyper-edges that are related to Marco, which is used in the objective evaluation process of WireMask-BBO.

Area Utilization Ratio: the proportion of the total area of the chip canvas that is occupied by the macros, calculated by dividing the area of the macros by the total area of the chip canvas. A higher Area Utilization Ratio to some extent indicates a harder placement problem, because we have to maintain the non-overlapping property.

#Partitions: the number of partitions when discretizing the chip canvas into grids.

All columns, except for #Partitions, are predetermined and unalterable in the benchmark. 3 The #Partitions, however, constitutes a crucial hyperparameter, which is determined heuristically based on the heights and widths of the macros and the canvas. To elaborate, in the case where multiple macros of identical size, e.g., 30 × 20 , are present on a given chip, with the canvas size 9000 × 9000 , the value of #Partitions would be set to 300 , thereby resulting in a grid size of 30 × 30 for each grid. The influence of #Partitions is discussed in Table 7 of Appendix B.2.

B Additional Results

B.1 Post local search

As the genotype-phenotype mapping in the objective evaluation of WireMask-BBO is performed greedily, guided by wire mask, we propose a post local search procedure to modify the final generated macro placement, which will probably bring further improvement. For a final generated macro placement, the positions of all macros are sequentially adjusted; the position of each macro is adjusted to the best grid (ties are broken randomly) which reduces the current HPWL value most. Note that when adjusting the position of one macro, all the other macros are fixed, which is different from that in the objective evaluation of WireMask-BBO, which is only based on the positions of those macros that have been adjusted. We have applied this post local search procedure to the final placements generated by SP-SA [33], MaskPlace [26] and WireMask-BBO. The macros are adjusted sequentially according to the order employed by WireMask-BBO (i.e., lines 1-2 in Algorithm 1); this process is performed twice. Note that the adjustment order of macros can be arbitrary when applying this post local search process. The results in Table 6 show that the final placements can be further improved, which is expected because both MaskPlace and WireMask involve (probabilistically) greedy incremental placement guided by wire mask.

B.2 Hyper-parameter analysis

We empirically investigate the influence of the the hyper-parameters of WireMask-EA, i.e., the number of partitions when discretizing the chip canvas into grids, the order of adjusting the positions of macros in objective evaluation, and the mutation operator.

Number of partitions. In our main experiments, the number of partitions is heuristically determined based on detailed macro statistics and varies across different chips, ranging from 108 for adaptec4 to 273 for bigblue4 , as shown in Table 5. The first two rows of Table 7 show the results of WireMask-EA after increasing and decreasing the number of partitions by 100, respectively. The last row gives the results of the default WireMask-EA, achieving the highest average rank.

By increasing the grid partition number, more fine-grained genotype-phenotype mapping guided by wire mask can be achieved, but the computational overhead is also increased. If the grid partition number is too small, the mapping may even not lead to non-overlapping placements, as observed on the chips adaptec2 , adaptec3 and adaptec4 after decreasing the grid partition number by 100 . Thus, a good balance needs to be considered, when determining the grid partition number in practice.

Order of adjusting the positions of macros. In the objective evaluation of WireMask-BBO, the positions of macros are adjusted sequentially, in the decreasing order of the sum of area of each macro's connected cells, as shown in lines 1-2 of Algorithm 1. Here, we also test the random adjustment order and the order only considering the area of each macro itself, the results of which are shown in the first two rows, respectively, of Table 8.

The random order always leads to the worst result, and may even fail to generate non-overlapping placements. Compared with using the order only considering each macro's area, the original WireMask-EA performs significantly better on five chips, and worse on the other two chips. Its best overall performance is expected, because the order considering the sum of area of each macro's connected cells is more closely related to the performance metric HPWL.

Mutation operator. For WireMask-EA, which performs the best among the three variants of WireMask-BBO, we also examine the influence of its mutation operator. We employed the swap mutation operator in our experiments, which randomly selects two macros and interchanges their coordinates. To further investigate, we implement the uniform mutation operator as well, which selects a macro at random and uniformly reallocates it on the chip canvas. Moreover, we combine these two mutation operators, with each being executed with a probability of 1/2. As shown in Figure 5, the utilization of the swap mutation operator alone (i.e., Swap_only) performs better than using the uniform mutation operator alone (i.e., Uniform_only) or their combination (i.e., Mix).

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B.3 Number of evaluations

Table 9 lists the number of evaluations used by WireMask-RS, WireMask-BO and WireMask-EA in Table 1, each of which runs for 1000 minutes. The number of evaluations of RS and EA is rather close, indicating that our EA operator is quite efficient. Besides, BO uses fewer evaluations than RS and EA, owing to the time-consuming cost of updating the Gaussian process model and optimizing the acquisition function.

B.4 Results on the ariane benchmark

We evaluate the performance of our WireMask-BBO framework on another benchmark, the ariane RISC-V CPU design [48], which has been previously studied in works such as [32, 26]. Our evaluation involves a comparison with three analytical methods and three RL methods, and the results are summarized in Table 10. The results of analytical and RL methods are directly from [26]. The analytical methods all fail to generate non-overlapping placement results on ariane , likely due to its high macro area utilization ratio of 0.78, which is the largest among all the benchmarks in Table 5. The overlapping issue is consistent with our discussion presented in Section 2.3. The RL-based methods show significantly worse performance compared to our proposed WireMask-BBO methods. The three different variants of WireMask-BBO are comparable based on the statistical test, with WireMask-EA demonstrating the lowest mean HPWL value.

B.5 Comparison with concurrent works

Recently, ChiPFormer [25] and AutoDMP [4] are proposed as new state-of-the-art methods in macro placement. For a comprehensive comparison, we also conduct experiments with these two concurrent works here.

ChiPFormer. ChiPFormer [25] incorporates an offline learning decision transformer to improve the generalizability. The pre-trained model provides placement results with acceptable quality within minutes, and converges to better results than MaskPlace [26] using fewer evaluations. We have compared our proposed WireMask-EA with ChiPFormer on ten chips, as outlined in Table 11. The experimental results show that our WireMask-EA clearly outperforms ChiPFormer on 9 circuits out of 10, no matter the number of evaluations is 1, 300 or 2k.

AutoDMP. AutoDMP [4] improves the efficient DREAMPlace [28], using Bayesian optimization to explore the configuration space and showing potential in real EDA application. We have included running time comparison between the state-of-the-art method AutoDMP [4] and our proposed WireMask-EA as shown in Figure 6. The results of MaskPlace (3k evaluations) and ChiPFormer (2k evaluations) are ploted by dotted lines in the figure. We can observe that on the two chip benchmarks, adaptec1 and bigblue1 , AutoDMP and WireMask-EA can surpass MaskPlace and ChiPFormer quickly, and WireMask-EA performs the best.

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Peer reviews:
comments: SUMMARY:
This paper proposes a new black-box optimization framework, called WireMask-BBO, for macro placement, which is an important problem in the electronic design automation (EDA) community. By using different black-box optimization algorithms, The experiments show it can achieve improvements (shorter half-perimeter wirelength (HPWL)) over previous methods.

STRENGTHS:
The general framework WireMask-BBO proposed by this paper somewhat provides new angle for macro placement problem. The paper is well-written and it is easy to follow.

WEAKNESSES:
The scalability of the proposed method is doubtful because Bayesian optimization and evolutionary algorithm may not be suitable for large-scale problems.
The experiments are insufficient. The experiments don’t compare with the state-of-the-art macro placement method. The experiments don’t compare the runtime of the proposed method with other methods.

QUESTIONS:
(1)	How about the performance comparison with the state-of-the-art macro placement method in the experiments?
(2)	How about the runtime of the proposed method and compare it with other methods?
(3)	Is it necessary to tune hyperparameters extensively to achieve good results in the experiments?

LIMITATIONS:
Yes
TITLE: Official Review
SOUNDNESS_CORRECTNESS: 2
DATE: 2023-07-05

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper presents a framework using BBO for macro placement in VLSI designs. Any placement solution for a set of macros can be optimized using the wire masks (presented in a prior work using RL) where the optimization goal is to minimize the HPWL of the output. In addition to random inputs, the framework can also be used for further enhancement of any existing solutions.\n\nSTRENGTHS:\nThe work tackles a critical problem in VLSI designs. \n\nThe idea of casting the placement problem to a BBO is interesting and novel.\n\nThis framework can be used to further improve any existing solutions for the macros. This can be used as another step in PnR with reasonable runtime.\n\nOverall, the paper explains the problem, the existing solutions, and the proposed work clearly.\n\nWEAKNESSES:\nThe idea of casting the placement problem to a BBO is interesting and novel. However, as the authors admit in Section 1 that this work does not develop any new BBO algorithm. To the reviewer, the experimental results are not extensive and convincing; this is described in the limitation section. \n\nThe paper also states in the conclusion that it can only place macros but not standard cells without explanation, which limits the application of the proposed work to the actual VLSI problem. On the other hand, this framework can be used to further improve any existing solutions for the macros. This can be used as another step in PnR with reasonable runtime.\n\nQUESTIONS:\nWhy is EA-based framework better than the other two BBO algorithms?\n\nWhy cannot the proposed framework used for standard cell placement? Can't you use a more fine-grained canvas for the problem, where the standard cells are larger than the grid size?\n\nLIMITATIONS:\nThe computational time for the proposed work seems to be high. Therefore, in the experimental section, the paper does not include the complex benchmark that has thousands of macros to be placed. This contradicts with the claim the paper that this approach is scalable.\n\nThe evaluation of the proposed method only uses 5 random seeds. It would be more convincing if the paper includes more experimental data.\n\nThe proposed framework cannot place the standard cells in the design. Therefore, the comparison between this work and the existing methods seems to be unfair.", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 4, "SOUNDNESS_CORRECTNESS": 2, "DATE": "2023-07-06"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThe authors propose a new placement method that is based on the black-box framework. The framework leverages the wire mask-guided information and can achieve significant placement results compared with the state-of-the-art methods.\n\nSTRENGTHS:\n1. The novel method is based on black-box optimization, which has not been implemented on the placement task before. Although many RL methods have been proposed, they are not very efficient enough. Black-box optimization might be a viable direction. \n\n2. The wire mask as the guide for generating phenotype representation is also very novel. It can quickly render a suitable solution based on the initial representation, improving efficiency. \n\n3. The experiments are very comprehensive and solid, showing that the performance of the proposed method can consistently outperform existing methods.\n\n4. The paper writing is well-written and easy to understand.\n\n5. The code is open-source, improving reproducibility.\n\nWEAKNESSES:\n1. The full placement cannot surpass the DREAMPlace, which means the proposed method can only work well in macro placement.\n\n2. The reasons for the improvement in the congestion metric are not clear. The method does not consider the congestion metric in its search process.\n\n3. The recent work [1] based on Maskplace should also be discussed in the related work part.\n\n[1] Lai Y, Liu J, Tang Z, et al. Chipformer: Transferable chip placement via offline decision transformer.\n\nQUESTIONS:\n1. Have you tested the effect of the number of initial states on the final results?\n\n2. Why your method can get better congestion results when you do not consider it in your method.\n\n3. The efficient comparison only provides the clock time. However, the number of search steps is also substantial. Could you provide how many steps you use for each circuit (or how much clock time is consumed to perform a step)?\n\nLIMITATIONS:\nYes.", "TITLE": "Official Review", "RECOMMENDATION": 7, "REVIEWER_CONFIDENCE": 5, "SOUNDNESS_CORRECTNESS": 3, "DATE": "2023-07-10"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper proposes a novel black-box optimization (BBO) framework, namely WireMask-BBO, for macro placement in chip design. Specifically, it devises a post-processing technique that legalizes any searched placement solution while optimizing the half-perimeter wirelength (HPWL). The post-processing technique allows us to perform BBO algorithms to search for solutions with better HPWL. Experiments demonstrate that WireMask-BBO outperforms previous state-of-the-art (SOTA) methods, achieving better HPWL performance in less time.\n\nSTRENGTHS:\n1.\tThis paper explores BBO methods for macro placement, which may provide a new insight for the research community.\n2.\tThe proposed post-processing technique is simple yet effective. It also has a good versatility because it can be combined with other placement methods and BBO methods.\n\nWEAKNESSES:\n1.\tThe propose of the post-processing is purely heuristic. The motivation is unclear and intuitive explanation for the advances is insufficient.\n2.\tThe proposed method only targets on optimizing HPWL, without explicitly considering other important metrics like routing wirelength or congestion. It does not consider cells and routing either. Moreover, the framework can be hardly transferred to tasks with those metrics under consideration, which limits its real application in EDA.\n3.\tBecause introducing BBO-based methods is one of the core contributions of this paper, the authors may want to illustrate the implementation of BBO algorithms for macro placement more detailly.\n4.\tIn Algorithm 1, the macros are ordered decreasingly according to areas, while in Figure 3, the smaller macro-A is considered first.\n5.\tA recent related work [1] is missing.\n[1] Lai Y, Liu J, Tang Z, et al. Chipformer: Transferable chip placement via offline decision transformer. ICML 2023.\n\nQUESTIONS:\n1.\tSince only HPWL is considered as the objective, why does WireMask-BBO also outperforms MaskPlace in congestion?\n2.\tWhat are the results of routing wirelengths?\n3.\tUnder this framework, how to take cell placement or some important yet computationally insufficient metrics into consideration?\n\nLIMITATIONS:\nN/A", "TITLE": "Official Review", "RECOMMENDATION": 6, "REVIEWER_CONFIDENCE": 4, "SOUNDNESS_CORRECTNESS": 3, "DATE": "2023-07-12"}