Title: Neural Modulation for Flash Memory: An Unsupervised Learning Framework for Improved Reliability
Venue: NeurIPS 2023
Accepted: yes
Keywords: WGAN

GAN

Autoencoder

Unsupervised Learning

Generative models

Flash Memory

NAND

Modulation

Reliability

Flash

Communication system
Abstract: Recent years have witnessed a significant increase in the storage density of NAND flash memory, making it a critical component in modern electronic devices. However, with the rise in storage capacity comes an increased likelihood of errors in data storage and retrieval. The growing number of errors poses ongoing challenges for system designers and engineers, in terms of the characterization, modeling, and optimization of NAND-based systems. We present a novel approach for modeling and preventing errors by utilizing the capabilities of generative and unsupervised machine learning methods. As part of our research, we constructed and trained a neural modulator that translates information bits into programming operations on each memory cell in NAND devices. Our modulator, tailored explicitly for flash memory channels, provides a smart writing scheme that reduces programming errors as well as compensates for data degradation over time. Specifically, the modulator is based on an auto-encoder architecture with an additional channel model embedded between the encoder and the decoder. A conditional generative adversarial network (cGAN) was used to construct the channel model. Optimized for the end-of-life work-point, the learned memory system outperforms the prior art by up to 56\% in raw bit error rate (RBER) and extends the lifetime of the flash memory block by up to 25\%.

Neural Modulation for Flash Memory: An Unsupervised Learning Framework for Improved Reliability

Abstract

Recent years have witnessed a significant increase in the storage density of NAND flash memory, making it a critical component in modern electronic devices. However, with the rise in storage capacity comes an increased likelihood of errors in data storage and retrieval. The growing number of errors poses ongoing challenges for system designers and engineers, in terms of the characterization, modeling, and optimization of NAND-based systems. We present a novel approach for modeling and preventing errors by utilizing the capabilities of generative and unsupervised machine learning methods. As part of our research, we constructed and trained a neural modulator that translates information bits into programming operations on each memory cell in NAND devices. Our modulator, tailored explicitly for flash memory channels, provides a smart writing scheme that reduces programming errors as well as compensates for data degradation over time. Specifically, the modulator is based on an auto-encoder architecture with an additional channel model embedded between the encoder and the decoder. A conditional generative adversarial network (cGAN) was used to construct the channel model. Optimized for the end-of-life work-point, the learned memory system outperforms the prior art by up to 56% in raw bit error rate (RBER) and extends the lifetime of the flash memory block by up to 25% .

1 Introduction

The continued scaling of flash memory technology into smaller process nodes, combined with the increased information capacity of each flash cell (i.e, storing more bits per cell), has placed NAND flash memory at the forefront of modern storage technology. Those advances comes at the cost of increased vulnerability to various error mechanisms that can compromise data integrity and system reliability. The endurance of the flash can be measured by the number of program-erase (PE) cycles the cells can undergo, before the error-correction-code (ECC) decoder fails to reconstruct the programmed bits.

Modern flash devices suffer from multiple sources of error, such as write-induced [1], data retention [2, 3] and read-induced [4] errors. The impact of these different mechanisms vary between physical locations in the chip. In addition, the probability of errors to occur on different cells is not independent: The charge stored in a flash memory cell is affected by the state of its neighboring cells (see section 2.1.4), a phenomenon dubbed inter-cell interference (ICI).

To maintain high reliability while pushing for ever-growing storage density, manufactures devote significant resources to comprehensive characterization and optimization of flash systems [5, 6]. Over the years, the industry has developed numerous strategies for mitigating errors, including robust ECC algorithms [7], smart writing schemes [8] and adaptive read methods [9, 10]. However, all above

techniques optimize either the data storage or retrieval operations individually, ignoring their built-in dependencies. Furthermore, they typically neglect the inter-cell correlations between the cells. To that end, we introduce the neural-modulation framework-an end-to-end unsupervised optimization method which is designed to mitigate the complex error patterns of flash memory devices and address the plethora of correlations between their components. By using a learning based approach, we enable (i) state-of-the-art modeling and optimization of the system; and (ii) flexibility and generalization: optimization of a new flash generation can be done in a simple and automatic procedure.

The flash memory stores information in an array of cells, where the information stored in each cell is encoded in its transistor threshold voltage v th . Current writing schemes allocate each cell with a target v th . The targets are optimized to result in a minimal error-rate with an emphasize on the end-of-life workpoint. So far, such prior art modulation methods base the choice of the target voltage solely on the data stored in the cell. This kind of modulation, illustrated in Fig 1, is referred to as a pulse amplitude modulation (PAM). In this work, we propose a novel approach to mitigate the ICI by optimizing the target v th of the memory cells with respect to the data designated to their neighbors. By employing such a scheme, we preemptively counteract the ICI.

We optimize the v th target modulation by performing an end-to-end training of the flash memory system (see Fig 2). Our method is based on the analogy between memory cells and communication channels-both systems receive and transmit data. Consequently, we can follow recent advances in communication research [11, 12, 13]. We use an unsupervised learning method, jointly training the transmitter and receiver of a communication system as an auto-encoder. The channel auto-encoder is trained using a reconstruction loss between the input of the encoder and the output of the decoder (see Fig. 5). In the flash memory domain, we define the transmitter of the system, which we dub the modulator, as the module translating the information bits into v th targets.

The joint optimization of the transmitter and receiver, using standard back-propagation, requires calculating the channel gradient with respect to the transmitted signal (see x in Fig. 5). Since, however, the flash channel is nondifferentiable, we cannot naively implement this technique. To overcome this issue, we train a

Vth targets

(a)

(b)

Vth

conditional generative adversarial network (cGAN) based channel model as proposed in [14]. Recent work by [15] showed that GANs can be useful in modeling the v th distribution of the flash cells by using the data symbols. In this work, the trained channel model learns to produce samples from the v th distribution of a memory cell given the v th targets of the cell and its neighbors. Using the neighbors data, the channel model is able to capture the inter-cell interference statistics, allowing the modulator to counteract this phenomenon.

To reduce the additional programming latency caused by our neural modulator, we develop a novel shared pulses programming scheme. The suggested scheme, which is based on the Incremental Step Pulse Programming (ISPP) scheme [16], achieves accurate programming, without increasing the amount of programming pulses, and with only a minor increase in programming time.

When optimized for the EOL work-point, the learned memory system outperforms the prior art by up to 56% in terms of raw bit error rate (RBER), extending the tested EOL work-point of the chip by 25% in terms of PE cycles. This gain is achieved without increasing the read latency.

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2 Preliminaries

2.1 Flash memory basics

2.1.1 The 3 D NAND flash architecture

The basic unit of a 3 D-NAND Flash Memory is a cell -a semiconductor based charge trap transistor. The cell's information is encoded in its transistor threshold voltage v th , which is a real value v th ∈ [ v min , v max ] . The range [ v min , v max ] is referred to as the dynamic range.

Modern flash devices typically store multiple bits per cell ( BPC ). The dynamical range is divided into 2 BPC segments, each corresponding to a different information bits dubbed symbol . We define a level as the group of cells that hold the same symbol. Flash devices that store 1/2/3/4 BPC are usually referred to as single-level cell ( SLC )/multi-level cell ( MLC )/triple-level cell ( TLC )/quadruple-level cell ( QLC ), respectively.

The flash cells are organized in three dimensional arrays called blocks (see Fig. 3). The three dimensions of the block are the pillar/string axis, the wordline (WL) axis and the bit-line (BL) axis. The two dimensional cross section of the block consisting of the pillar and WL axes is called the string select line (SSL).

2.1.2 The flash memory interface

The two most basic operations on the flash memory device are programming and reading.

Programming the block with information; and more specifically, bringing the v th of each flash cell to the voltage target assigned to the symbol that should be stored in that cell. This operation is done using the ISPP algorithm described in the supplementary material.

Reading the data stored in a WL. This operations is done by segmenting [ v min , v max ] into 2 BPC voltage regions, corresponding to the 2 BPC data symbols.

BL

WL

string/

pillar

2.1.3 Errors in NAND flash memory

Read errors occurs if there is a mismatch between the symbol designated for the cell and its actual threshold voltage. The fraction of bits which were incorrectly assigned by the reading algorithm out of all bits read is called the Bit Error Rate ( BER ).

Errors in flash memory devices can be induced by many factors [1], but for the purpose of this work we will focus only on two of them - programming variation and retention disturb.

The v th of a memory cell after receiving a programming pulse is a stochastic function of the initial cell v th and the pulse magnitude. Therefore, programming a level ℓ in some WL w will result in some distribution of the v th close to the desired target, regardless of the writing algorithm. We define the programming variation as the noise injected by the programming algorithm.

The retention disturb [2, 3] is defined as the v th change during the data storage time, after the programming phase has completed. The retention disturb happens because charge leaks out of the cell over time, thus changing its v th .

The shift in v th due to programming variation and retention disturb varies between WLs and SSLs. Furthermore, it is also a function of the number of PE cycles experienced by the block. Each PE cycle wears down the block cells, making them more vulnerable for disturbs, and therefore increases the BER of the block.

2.1.4 Inter-cell interference in the 3 D-NAND block

The most dominant coupling between cells in a 3 D-NAND, and hence Inter-Cell Interference (ICI), occurs along the pillar axis, and it includes phenomena such as programming interference and lateral migration. The programming interference is the phenomenon at which programming of a flash cell increases the v th of adjacent neighbor cells [1]. The programming interference effect on a flash cell is a stochastic function of the amount and magnitude of the pulses its neighbors experience. Therefore, it is also a function of the v th targets of its neighbors.

The lateral migration [1, 17], which takes place during data retention period, describes charge migration between cells with different v th . Fig 4 illustrates the lateral migration phenomenon measured on a 3 D-NAND chip programmed with QLC data. We measure the v th of each cell immediately after programming the block, and again after an effective retention period of one month at room temperature. 1 The figure

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shows the mean v th change of the cells programmed to data symbol 15 as a function of the symbol of its two adjacent cells. We obtained that low-symbol-neighbors cause higher voltage loss over time.

2.2 Generative adversarial networks

Generative adversarial networks ( GAN s) [19] are a class of generative models consisting of two separate neural networks (NNs), a generator G Θ and discriminator D Ψ . The basic setup of GANs consists of a set of samples { x i } i m =1 ⊂ X drawn from some distribution of interest p , which we wish to produce new samples from. GANs learn the distribution p by fixing a rather simple distribution p Z (Gaussian for example) over a latent space Z and then optimizing the generator function G Θ : Z → X such that the push-forward measure p G := G ⋆ ( p Z ) = p Z ◦ G -1 will be as close as possible to p .

In this work we apply a conditional version of the Wasserstein GAN (WGAN) proposed in [20, 21], which uses the Wasserstein distance as the training loss of the generator. WGANs were proven to enable more stable training and convergence[20].

2.3 End-to-end training of autoencoder-based communication systems

End-to-end training of autoencoder-based communication systems is a relatively new approach [13] for the joint optimization of both the transmitter and the receiver of the system. With this approach, an autoencoder-like architecture is used, where the transmitter acts as the encoder and the receiver as the decoder. Both are represented as NNs with parameters Θ T and Θ R , respectively, which we train jointly using back-propagation. The training uses a reconstruction loss between the symbol s at the input of the transmitter, and the reconstructed symbol ˆ s at the output of the receiver (see Fig 5), where

This reconstruction loss is commonly defined as the categorical Cross-Entropy (CE) between s and ˆ s , where C represents the system channel.

3 End-to-end learning based modulation for the flash memory

The basic program-read flow of the 3 D-NAND flash memory suffers from multiple sources of error, degrading its endurance both in terms of PE cycles, as well as data retention time. To mitigate the effects of those errors we introduce a neural-modulation system, which is inspired by the end-to-end training approach described in Section 2.3. Given some programming scheme, the neural-Modulation system optimizes the v th targets of the 3 D-NAND block. On top of optimizing the v th targets, our system performs pre-distortion of the target of each cell, to counter the ICI phenomenon (see section 2.1.4). For this purpose, the v th target is optimized conditioned on the symbols of its pillar neighbors . This novel approach gives rise to a significant BER reduction, and by that, extend the EOL work-point of the NAND flash block.

3.1 Flash memory as classical communication system

In order to fully describe the end-to-end training approach outlined in the previews section, we first turn to formally define the NAND flash memory as a classical communication system. The three components of a classical communication system are the transmitter, channel and receiver. We adjust their definition to memory devices in the following way:

The transmitter f Θ M , which we dub the modulator , is the component responsible for translating the input symbols s into v th targets for the programming algorithm.

The channel C is the composition of the programming scheme, the data retention process, and the v th read operation. It simulates the disturbs and errors described in Section 2.1.3.

The system receiver f Θ D , which we dub the demodulator , is the component which reconstructs the data symbols ˆ s from the v th readings.

Using this formulation we can adopt the end-to-end learning based approach described in Section 2.3 to learn an optimal modulation for our channel. Bellow we elaborate on the three main components of our system.

3.2 cWGAN as NAND channel model

We model our NAND channel as a cWGAN [21]. Modeling the NAND as a cGAN is essential for training the auto-encoder because it allows differentiating the channel [14]. The generator is trained

to learn the cell's threshold voltage v cell th distribution given its 'context' - the cWGAN condition which includes the following:

The program target of the cell t cell .

The target v th of the two nearest pillar neighbors of the cell T neighbors ∈ R 2 .

The SSL index, ssl ∈ [ N ssls ] and WL index wl ∈ [ N wls ] of the programmed WL.

Including T neighbors in the cell context is crucial for modeling the ICI effects. Consequently, it allows the neural-modulator to adjust the target of each cell according to v th of its neighbors and counteract the ICI. Since different WLs in the block exhibit different reactions both to programming pulses as well as the ICI noise, the SSL and WL indices of the programmed WL are also used to condition our cWGAN. We can therefore formulate the cWGAN objective as learning to produce a sample of v cell th ( v th reads from the NAND) given the conditional density

For full model specification see the supplementary material.

3.3 The neural modulator and demodulator

The next two components of our system are the modulator and the demodulator. The modulator is a function

mapping information symbols s ∈ [ 2 BPC ] to v th targets to be programmed to the NAND, conditioned on the 'context' of the target cell c ∈ C . The context c comprises of the symbols designated to the two neighboring cells along the SSL (one on each side of our given cell), the SSL index and WL index of the target cell C = [ 2 BPC ] × [ 2 BPC ] × [ N ssls ] × [ N wls ] .

The demodulator,

receives a v th read from the channel. It then reconstructs the programmed symbol by learning the log likelihood ratio (LLR) of each symbol s ∈ [ 2 BPC ] given the v th read. Note that the demodulator does not receive any information about the cell's neighbors. This forces our system to exploit the information about the neighbors only at the modulation stage, and thus perform pre-distortion to offset the ICI. In other words, all the information about the neighbors is already encoded by the modulator into its output. This independence of the demodulator from the cell's neighbors also guarantees that our system will not require any changes to be made to the current reading algorithm. As there are physical differences between different sections of the block, we use the SSL and WL indices as input to both the modulator and the demodulator.

The number of layers and other NN parameters of both modulator and demodulator are given in the supplementary material. The output of the modulator is passed through a tanh function, to enforce it to be in the range of ( -1 , 1) . This output is then scaled to the dynamic range of the chip ( v min , v max ) , forcing the modulator to choose only targets that are feasible for programming.

3.4 The training procedure

The Neural-modulation training procedure is divided into two steps. In the first step we train the cWGAN based channel model. The data we use as a train set is a set of v th reads of a single block programmed with given targets T . 2 The critic is utilized solely to train the generator, and is afterwards discarded. The second step includes the joint training of the modulator and demodulator. As a prerequisite, we assume to have the pretrained, frozen channel model (i.e. the generator from the previous step). At each iteration a batch B of samples b ∈ [ 2 BPC ] × C flows through the modulator, generating a program target for each sample. At this point each cell has a corresponding target, but we still require the targets of its neighbor cells as well, to be used as an input for the channel model. We choose the neighbor cells targets according to some constant set of 2 BPC -1 targets that we spread uniformly over the dynamic range [ v min , v max ] (we refer to those targets as the 'default

Train set

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targets'). The targets and neighbor targets then pass through the channel model to sample from the v th distribution of the cells when programming them to those targets. Finally, the demodulator is used to predict the original symbols given the simulated v th and the SSL and WL indices of the cells. As a training loss we use the CE loss between the recovered symbols and the input symbols as described in Section 3. The supplementary material provides the full details of all training parameters.

3.5 Programming the learned targets

The modulator, which translate a block of information symbols into v th targets, is trained upon completion of the second stage. However, the number of target values suggested by the system is significantly larger than the number of data symbols, as it is equal to the number of possible values of the input. As the number of unique targets increases, programming operation latency increases, making it impractical with the conventional programming scheme. Therefore, we propose performing the following two steps:

Quantization of the modulator output, by grouping together close targets to a single target.

Expanding the ISPP program scheme, to enable it to program simultaneouslymultiple, relatively close, targets, using a shared pulses mechanism. The proposed scheme preserves the current number of programming pulses and introduces solely read operations. As per [22], the effect of these read operations on the programming latency is determined to be negligible.

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Using these steps, we are able to program learned targets, while still maintaining a state-ofthe-art programming time. A detailed descrip- tion of both steps is given in the supplementary material.

4 Experiments

One of the main goal of the neural-modulation system is to extend the end-of-life work-point of the chip in terms of PE cycles and data retention time. Therefore, we conduct our experiments at a work-point with high amount of errors, to simulate an EOL scenario.

4.1 GAN channel model experiments

To evaluate the channel model, we first train our cWGAN on a v th read of a single block programmed with 15 linearly spread targets (for QLC modulation) over the dynamic range. We then evaluate the

trained model over a test set which include six blocks. In each test block, we perturb the linearly spread targets { T train i } 15 i =1 by setting T i = T train i + λ i ∆ , where

for ∆ in { 15 , 30 , 45 , 60 , 75 , 90 } . The evaluation itself uses two criteria:

BER: We compare the real and generated BER of each WL in the block.

Histograms: We compare between the histograms generated by our model and those measured on a real chip (i.e. when programming an actual batch of cells to the same target).

The quality of both train and perturbed predicted v th histograms can be seen in Fig. 7. Specifically, we measure a Wasserstein distance of 6 ± 2 mV between the real and generated histograms. For comparison, the average Wasserstein distance between two real blocks in the same chip is 6 mV as well. A detailed description of the distance calculation is given in the supplementary materials. In Fig. 6 we compare the real and predicted BER of a QLC block for different target voltages, i.e., values of ∆ . Again, we see that the BER prediction is very good and has an error margin of up to 5% . This reassures us we can indeed use the trained model to generate targets from the entire v th range (including targets it did not train over).

4.2 Neural-modulation experiments

We train the neural-modulation system as described in Section 3.4. Table 1 summarizes the performance of the model in terms of average block BER at the EOL work-point. We note that not only did the model significantly improve the BER compared to the baseline targets, but it also accurately predicted the BER results via the channel model GAN (see the 'GAN prediction' column of Table 1). Specifically, we pass the modulator targets through the GAN, and use the generated v th distribution to calculate the predicted BER.

Fig. 8 illustrates the pulse amplitude modulation (PAM) constellation the modulator learned for a single QLC WL, compared to the original 16 PAM constellation. The modulator found lower targets for cells with higher symbol neighbors. Such scheme is consistent with the observation discussed in Section 2.1.4, that the charge lose depends on symbols of the cell and its neighbors.

Next, we analyze the model effect as function of the data retention time. We measure the average BER as a result of programming with the default and modulated targets, at different time points during the data retention process. Fig. 9 (a) presents the BER reduction of the modulated targets compared to the default targets. We found that the pre-distortion of the targets helps keeping the BER low over

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longer retention periods. Interestingly, the pre-distortion slightly deteriorate the BER at short times. Since the BER at these time is overall small, there is no real price for using our modulator.

The ultimate purpose of our modulator is to extend the EOL work-point of the NAND block. We would, therefore, like to estimate the change in the number of PE cycles before the the memory device reaches its EOL. The EOL point is determined by a threshold BER value above which the data cannot be reconstructed. This information can be extracted from Fig. 9 (b), where we show the BER after a constant retention time as a function of PE cycles. We found that the modulator extends the number of PE cycles by 25% (notice that the BER is normalized to its EOL value)

5 Conclusions and limitations

In this work, we demonstrated the potential of pre-distorted programming of the flash memory device to mitigate errors caused by ICI. We applied state-of-the-art optimization methods for the programming v th targets by performing end-to-end training of the channel's modulator and demodulator through a pre-trained channel model. To the best of our knowledge, our work is the first to introduce an unsupervised learning based modulation for the flash memory. The importance of our modulator is in reducing the BER for the stored information by 56% compared to conventional writing schemes, and extending the NAND EOL work point by 25% in terms of PE cycles. Currently, our modulator was optimized for a single work-point with a constant read disturb and PE cycles. Future work may generalize the channel model and modulator to overcome this limitation using a dedicated input features. Another drawback is that implementing the modulator in a flash controller requires allocating extra write buffers for the neighbors data. 3

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Peer reviews:
comments: SUMMARY:
A neural modulator is proposed and sufficient results are presented.

STRENGTHS:
Sufficient results are presented.

WEAKNESSES:
No

QUESTIONS:
1. What kind of noise added in the figure 1.
2. Elaborate briefly about the neural modulation comparison with conventional modulation.
3. Explain the experimental setup.

LIMITATIONS:
No
TITLE: Official Review
SOUNDNESS_CORRECTNESS: 2
DATE: 2023-06-17

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThe paper introduces a programming method for 3D NAND flash memory. In 3D NAND, data is stored in the voltage level of cells. A cell can typically store a few bits of information (2,3,4 etc). As device density increases, the data is prone to multiple types of errors. The paper is targets two types of errors, those caused by inter-cell interference, and those caused by charge loss in time (retention error). The authors propose a machine learning scheme, based on an auto-encoder architecture with an additional cGAN (conditional generative adversarial network) between the encoder and the decoder. The auto-encoder model has been proposed before for communication systems. The addition of the cGAN is novel, and it is used to model the channel noise. The cGAN is used in order to overcome the fact that the flash channel is non-differentiable. The goal of the scheme is to predict better voltage thresholds for programming (data writing), by taking into account a more informative context for each cell (the value of its neighbors along the vertical channel dimension, and the position in the block). The new model is trained on data coming from on block of NAND and tested on data from 6 other blocks. Experimental evaluation shows a reduction of bit error rate by 56% and an extension of the program-erase cycles\n\nSTRENGTHS:\nThe topic is good application of modern machine learning tools the a specific problem of data storage in 3D NAND flash memory. The presentation is very clear, and the paper offers a good amount of details and background about all the components of the scheme.\n\nWEAKNESSES:\nThe paper has a very specialized focus, and the techniques that are presented may have limited impact. The experimental assessment is relatively small.\n\nQUESTIONS:\n1. It seems not clear whether any part of the experimental evaluation was performed on a physical device, or it was simulated. Could you please give some details?\n\n2. It seems that when you move to a new block, the SSL would be a new physical location. I'm wondering if it is useful to include this value in the context. In a similar vein, the ICI in 3D NAND is characterized in various sources, for example the one cited below. As we see there, of the two immediate neighbors in the pillar, the one that was programmed before has small ICI, while the one that will be programmed after has high ICI. Similarly, the neighbors along the logical wordline have significant ICI. Would it help to include this information, perhaps in a weighted fashion in your context?\n\nS. K. Park and J. Moon, \"Characterization of Inter-Cell Interference in 3D NAND Flash Memory,\" in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 3, pp. 1183-1192, March 2021, doi: 10.1109/TCSI.2020.3047484.\n\n3. In a 3D NAND there are potentially thousands of blocks. Do you have a proposal for scaling your scheme, how should the training be performed?\n\nLIMITATIONS:\nN/A", "TITLE": "Official Review", "RECOMMENDATION": 7, "REVIEWER_CONFIDENCE": 4, "SOUNDNESS_CORRECTNESS": 3, "DATE": "2023-07-04"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis paper presents a novel approach for improving the reliability of NAND flash memory by utilizing unsupervised learning and neural modulation techniques. The authors constructed and trained a neural modulator that reduces programming errors and compensates for data degradation over time. The proposed framework outperforms prior art by up to 56% in raw bit error rate (RBER) and extends the lifetime of the flash memory block by up to 25%.\n\nSTRENGTHS:\na. Overview:\nThe study proposes a novel approach for modeling and preventing errors in NAND flash memory using generative and unsupervised machine learning methods. The authors utilize a neural modulator that translates information bits into programming operations on each memory cell, reducing programming errors and compensating for data degradation over time. The modulator is based on an auto-encoder architecture with a channel model embedded between the encoder and the decoder. The channel model is constructed using a conditional generative adversarial network (cGAN).\n\nb. Methods:\nThe neural-modulation training procedure consists of two steps. In the first step, a cWGAN based channel model is trained using a set of vth reads of a single block programmed with given targets. The critic is used solely to train the generator and is then discarded. In the second step, the modulator and demodulator are jointly trained. The modulator translates a block of information symbols into vth targets.\n\nc. Experimental results:\nThe trained channel model shows good performance in predicting the bit error rate (BER) and generating accurate histograms. The Wasserstein distance between the real and generated histograms is measured to be 6 ± 2 mV, which is comparable to the average distance between two real blocks in the same chip. The predicted BER has an error margin of up to 5%. The modulator extends the number of program/erase (PE) cycles by 25% before the memory device reaches its end-of-life (EOL) point.\n\nWEAKNESSES:\nThe overhead from programming such models is not adequately discussed\n\nQUESTIONS:\nWhen quantizing the target, how 60 target is decided (in Appendix)? is it the goal to control BER gap within 0.02? Any rationale?\n\nLIMITATIONS:\nThe authors have clearly described the limitations and proposed the next works to tackle.\nNo negative societal impact.", "TITLE": "Official Review", "RECOMMENDATION": 6, "REVIEWER_CONFIDENCE": 4, "SOUNDNESS_CORRECTNESS": 3, "DATE": "2023-07-06"}

comments: SUMMARY:
* This paper introduces a unsupervised learning method using GAN for flash memory.

STRENGTHS:
* The paper is well written and organized, generally easy to follow.
* To the best of my knowledge, this paper is the first to introduce an unsupervised technique to this kind of problem. 
* The core problem is well formatted. The idea of using a cWGAN as channel model looks interesting and intuitive in section 3.
* Experimental results look promising, especially on extending storage life.

WEAKNESSES:
Please see questions

QUESTIONS:
* On Figure 7, it does give a view of generated WL from the generated model, is there quantized way to measure the quality?
* On 3.5, quantization, to what degree to quantize and is there any effect on the overall performance?
* How much resource does it take to run the modulator? Considering it is to be run on flash controllers.

LIMITATIONS:
The authors have discussed the limitation of modulator and channel model.
TITLE: Official Review
SOUNDNESS_CORRECTNESS: 3
DATE: 2023-07-07

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThe authors propose a generative model architecture for compensating for errors in NAND flash memory, with the goal of extending flash memory block lifetime. The architecture consists of a GAN and an autoencoder, where the encoder and decoder represent the memory’s modulator and demodulator respectively. The encoder predicts an optimal $v_{th}$ target for a cell, to which the GAN adds noise simulating errors that occur during writing and storage. The decoder then creates a recovered symbol from the perturbed $v_{th}$ value output by the GAN.\n\nSTRENGTHS:\n-\tMemory lifetime and reliability are very important, and an ML approach to model and counteract memory errors sounds promising. In particular, using a GAN to simulate the errors that occur during storage by taking into account the ICI appears novel and is quite clever. A search returned no prior works on unsupervised ML for flash memory modulation.\n-\tBecause the proposed technique modifies only the writing stage, the reading algorithm does not need to change.\n-\tThe work is well-written and easy to understand, especially in explaining the workings of flash memory.\n-\tThe graphics are useful for summarizing and visualizing the proposed method.\n\nWEAKNESSES:\n-\tThough this appears to be the first unsupervised ML approach to flash memory modulation, no reference is provided to similar prior works on ML and flash memory. A quick search returned several, such as \n   - https://ieeexplore.ieee.org/abstract/document/9205258\n   - https://iopscience.iop.org/article/10.35848/1347-4065/aba5e0/meta?casa_token=JMOIMn_8RJoAAAAA:EoRkZ4ZeYNlOcGh22YIgLcWTwCxmrbKxvvZF6sbHY3Blc7Nj93sAeaxFCbLdE1aaBL-CgyWbkGY\n   - https://ieeexplore.ieee.org/abstract/document/9013031?casa_token=YNITahKT5uEAAAAA:f0HrohD0iLmhUh5PhI_lKSk2GL5rNulHxe3dBhO4nnHo_8iTJdO6mp7uIVi0aFcWrEV9bGBPJA\n-\tThe figure references on lines 315 and 322 (for figures 9a and 9b) appear to be switched.\n-\tThe error bars on figure 9a suggest that the difference in retention time between default and modulated targets is not significant.\n\nQUESTIONS:\n- We customize the $v_th$ target for a given cell, but assume the neighbors use default target values. Would it not be better for the encoder to predict target values for the entire vector of symbols for the WL, then see how the GAN would distort the WL?\n- If the GAN is trained based on a channel model, how realistic does this model have to be? For instance, should we make a new GAN for each class of flash device, for each operating condition such as varying temperatures, etc.?\n- Section 4.1: Why do you perturb like this? What is the range of the targets?\n- In a real-world application, it would be necessary to run the encoder on each write operation. Does this greatly increase writing latency?\n\nLIMITATIONS:\nNo", "TITLE": "Official Review", "RECOMMENDATION": 7, "REVIEWER_CONFIDENCE": 3, "SOUNDNESS_CORRECTNESS": 3, "DATE": "2023-07-25"}