Title: Graph of Circuits with GNN for Exploring the Optimal Design Space
Venue: NeurIPS 2023
Accepted: yes
Keywords: Analog design optimization

Analog synthesis

Graph Neural Networks

EDA

Graph learning

Optimization
Abstract: The design automation of analog circuits poses significant challenges in terms of the large design space, complex interdependencies between circuit specifications, and resource-intensive simulations. To address these challenges, this paper presents an innovative framework called the Graph of Circuits Explorer (GCX). Leveraging graph structure learning along with graph neural networks, GCX enables the creation of a surrogate model that facilitates efficient exploration of the optimal design space within a semi-supervised learning framework which reduces the need for large labelled datasets. The proposed approach comprises three key stages. First, we learn the geometric representation of circuits and enrich it with technology information to create a comprehensive feature vector. Subsequently, integrating feature-based graph learning with few-shot and zero-shot learning  enhances the generalizability in predictions for unseen circuits. Finally, we introduce two algorithms namely, EASCO and ASTROG which upon integration with GCX optimize the available samples to yield the optimal circuit configuration meeting the designer's criteria. The effectiveness of the proposed approach is demonstrated through simulated performance evaluation of various circuits, using derived parameters in 180nm CMOS technology. Furthermore, the generalizability of the approach is extended to higher-order topologies and different technology nodes such as 65nm and 45nm CMOS process nodes.

Graph of Circuits with GNN for Exploring the Optimal Design Space

Abstract

The design automation of analog circuits poses significant challenges in terms of the large design space, complex interdependencies between circuit specifications, and resource-intensive simulations. To address these challenges, this paper presents an innovative framework called the Graph of Circuits Explorer (GCX). Leveraging graph structure learning along with graph neural networks, GCX enables the creation of a surrogate model that facilitates efficient exploration of the optimal design space within a semi-supervised learning framework which reduces the need for large labeled datasets. The proposed approach comprises three key stages. First, we learn the geometric representation of circuits and enrich it with technology information to create a comprehensive feature vector. Subsequently, integrating feature-based graph learning with few-shot and zero-shot learning enhances the generalizability in predictions for unseen circuits. Finally, we introduce two algorithms namely, EASCO and ASTROG which upon integration with GCX optimize the available samples to yield the optimal circuit configuration meeting the designer's criteria. The effectiveness of the proposed approach is demonstrated through simulated performance evaluation of various circuits, using derived parameters in 180 nm CMOS technology. Furthermore, the generalizability of the approach is extended to higher-order topologies and different technology nodes such as 65 nm and 45 nm CMOS process nodes.

1 Introduction

Designing Electronic Design Automation (EDA) tools for analog circuits is challenging as it involves optimizing multiple parameters and their non-linear dependencies. Machine learning models are increasingly being integrated within EDA tools aiming to make this process flexible and suited for analog design across different circuits and technology nodes. Instead of simulation-based global optimization [14], which can be time-consuming for stricter requirements [8], a surrogate-modelassisted optimization approach using less computationally expensive approximation models have been proposed.

Regarding surrogate models, Bayesian optimization and Gaussian process models have been more effective than standard artificial neural networks and radial basis functions. However, Gaussian process modeling is computationally expensive [3], and as circuit complexity increases, inter-sample relations become harder to capture, training time increases and generalization ability is lost. To address these challenges, graph-based models that integrate Graph neural networks (GNNs) [5, 22, 17, 29] have emerged as a powerful technique in high-level synthesis, behavior modeling [9], placement and routing [20, 18, 28, 13], analog and mixed-signal layout exploration [25], making them a plausible choice for graph-based surrogate models. Graphs capture both topological and featurebased information, resulting in faster modeling and optimization of complex systems. Despite their

success, graph-based methods still require improvement in terms of independence from labeled data and generalization ability across different circuit topologies and technology nodes. For optimization algorithms, previous works have employed reinforcement learning [26], and evolutionary algorithms [6]. However, the models or policies that are learned via these methods are highly tailored to the environment or the objective of the optimization and lack reproducibility. Another popular method is the particle swarm intelligence [23] however, it easily falls into local optima in the high dimensional space and suffers from low convergence rate.

This paper introduces a novel and innovative approach to optimize circuit design by leveraging graph representation and graph-based semi-supervised learning. The approach is designed to enhance accuracy and efficiency while reducing the reliance on extensive labeled datasets. To achieve this goal, a semi-supervised learning framework is employed for the graph-based surrogate model. The accuracy of the approach is compared against the benchmark model ParaGraph [22], and its superior performance is demonstrated. Additionally, a new method is introduced to create a comprehensive feature vector that integrates information about various technology nodes and topologies, emphasizing generalizability in zero-shot and few-shot learning frameworks. By integrating these approaches, two new optimization methods on graph-based surrogate models are proposed: Efficient Analog Sizing via Constrained Optimization (EASCO) and Analog Sizing through Real-time Online Graphs (ASTROG). The paper is structured into seven sections, covering graphs, graph-based techniques, optimization strategies, the proposed approach, simulation results, and concluding remarks.

2 Related work

Construction of a graph-based surrogate model starts with circuit representation as graphs and the creation of a labeled graph dataset. The task is formulated as a graph-level regression problem with each graph mapped to its corresponding label vector (performance metric) using Graph Neural Networks (GNNs).

Graph representation for Analog and Mixed-signal circuits A graph is a data structure used to store semantic information with the help of its unique structure formed using nodes and edges. A graph with features is denoted by G = ( V, E, W, X, Y ) where V = { v 1 , v 2 , . . . , v n } is the vertex set, E ⊆ V × V is the edge set and W is the adjacency (weight) matrix. We consider a simple undirected graph without self-loop: W ij > 0 , if ( i, j ) ∈ E and W ij = 0 , if ( i, j ) / ∈ E . Finally, X ∈ R n × d = [ X 1 , X 2 , ..., X n ] T and Y ∈ R n × m = [ Y 1 , Y 2 , ..., Y n ] T are the feature matrix and label matrix respectively, where the row vectors X i ∈ R d and Y i ∈ R m are the feature vector and label vector, respectively associated with one of n nodes of the graph G . The most common approach

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for creating a circuit graph is based on the circuit's topological design. In this approach, circuit components such as resistors, capacitors, and transistors are depicted as nodes, while the circuit wiring (net) is mapped using edge-based information that connects different nodes [22]. This approach results in a heterogeneous graph that is useful for analyzing and developing complex electronic systems. As a result, a graph-level prediction problem [5, 22, 17] arises where we have a set of n graphs denoted by { G 1 , G 2 , . . . , G n } , each with its own set of nodes and edges, a function f which

maps these graphs to corresponding prediction metric ( Y i ), where Y i = f ( G i ) . Let X i be the feature matrix for i th graph where X i ∈ R n × F where n is the number of nodes in a single graph and F is the features of each node. Overall, the problem of graph-level prediction using GNNs involves learning the function f based on graph structure and node features that map the input graphs to the desired prediction metric. Building upon the previously presented method for representing circuits as a graph, [5] proposed a refined approach by explicitly including device terminals as nodes in the graph. This modification results in featureless edges.

While this approach offers a detailed understanding of the interconnection between different circuit components, it suffers from several limitations: (i) As the circuit size increases, the graph becomes densely interconnected, leading to a large number of nodes and edges, making it challenging to comprehend the overall behavior of the circuit. (ii) Creating a large labeled graph dataset is time-consuming and computationally expensive, which hinders effective GNN training. (iii) This framework lacks inter-graph connections, which reduces its reliability. (iv) Since graph regression problems cannot be applied to semi-supervised frameworks, the reliance on labeled datasets is inevitable. (v) Additionally, training and validating over multiple graphs ( n ) with N nodes and E edges when passed through L layer GNN makes the process slow, and the high time-complexity ( O ( n ∗ LN 2 E ) ) and space-complexity ( O ( n ∗ N 2 L ) ) further adds to the computational burden. (vi) Finally, transferring knowledge across different topologies becomes challenging due to varying graph sizes.

3 Proposed Formulation and Background

For our case, consider n number of circuit instances indexed as i = 1 , . . . , n , where X i ∈ R d be the feature vector and Y i ∈ R m the label vector corresponding to i -th circuit. A feature vector X i contains the circuit-level parameters e.g. resistance, capacitance, transistor widths, lengths, junction voltages etc and the corresponding label vector Y i contains performance parameters, including Gain, Bandwidth, Noise, etc . The problem under consideration is:

Given n = l + u circuit instances and their parameters X = ( X l , X u ) along with labels of only l number of circuit instances as Y l , how can we predict the labels of the remaining u number of circuit instances Y u ?

The circuit performance parameters or the labels Y i are generally obtained using expensive SPICE simulation, thus having a large set of labeled data is a luxury. Limited labeled data where l < u is a significant hurdle in learning models for EDA. Graph-based Semi-supervised learning attempts to address this by learning from both labeled as well as unlabeled data.

Consider sets T l = { ( X i , Y i ) } l i =1 ∈ X × Y and T u = { ( X i ) } l + u i = l +1 ∈ X , where X is the domain set and Y is the label set. Suppose the elements of the set T l be sampled from probability distribution P over the ordered pair X ×Y . Samples of the domain set X i ∈ X will follow the marginal distribution P X of P . For the limited labeled data scenario, the goal of a learning algorithm is to estimate conditional distribution P ( Y | X ) using both the labeled and unlabeled data as the training data. To incorporate the additional information of P X obtained because of the unlabeled data by capturing the intrinsic geometry of the marginal distribution through the graph of both unlabeled and labeled data and performing label propagation and feature aggregation over the neighborhood. The guiding principle is that if two data points from the domain set are close in the intrinsic distribution P X then the corresponding conditional distributions should be similar. For the circuit prediction, it means that given two circuit instances with similar features X i ∼ X j then the corresponding label vectors should also be similar Y i ∼ Y j .

To build a learning framework based on the above guiding principle, these are the two main steps i) First use the feature space to obtain a geometric representation such that the samples having similar features are represented closer and connected ii) Build a learning model such that geometric information be leveraged for learning the labels of unknown samples.

3.1 Proposed Framework for Semi-Supervised Learning on Graph of Circuits

We introduce a graph-based semi-supervised learning technique for building a surrogate model (GCX) for analog circuit simulation with limited labels. The proposed framework consists of four main stages: i) Firstly for obtaining feature-aware geometrical representation we construct a graph of circuits using circuit features X = ( X l , X u ) in the form of an adjacency matrix A , where each circuit

i is a node of the graph and the circuit-level parameters, such as resistance, capacitance, transistor widths and lengths, and junction voltages, as its corresponding feature vector X i ∈ R k . ii) Further using the graph adjacency matrix, feature matrix, and available set of circuit performance matrix together, i.e., G ( X,A,Y l ) with the graph neural network pipeline to build a machine learning model, iii) Constructing a comprehensive feature vector that facilitates generalizability(discussed later), iv) predicting the performance parameters Y u corresponding to X ′ u s. Fig 2 illustrates the outline of the proposed framework:

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Algorithm 1 GCX(GNN)

Input:

Feature matrix ( X l , X u ), label matrix ( Y l )

Output:

Optimal design ( X ∗ i )

G ( V, E, W ) ←-Learning Graph of Circuits Using ( X l , X u )

Y u ←-Label prediction of unlabeled circuits using GNN with G ( V, E, W, X l , X u , Y l ) ;

GCX(GNN) ←-G ( V, E, W, X u , X l , Y l ) + GNN; surrogate model

X ∗ i ←-GCX(GNN) + EASCO/ASTROG

Algorithm 1, which we denote by GCX(GNN), summarizes the outline of the proposed framework. The implementation details of each step are discussed subsequently.

This approach allows us to incorporate multiple circuit instances into a single graph while accommodating different technology nodes and topological diversity. We achieve this while maintaining a homogeneous graph with node feature vectors of equal lengths, making the training of GNNs in a semi-supervised framework efficient and cost-effective. Compared to the previous approach that handles circuits as graphs, our approach with N nodes in a graph with E edges when passes through L layer GNN has an overall time complexity of O ( L ∗ N 2 E ) and space complexity of O ( N 2 L ) .

3.2 How to Learn Graph of Circuits to Encode Circuit Similarity

Consider the feature matrix of circuit instances X = [ X 1 , X 2 , . . . , X n ] T where X i is the feature of i th circuit which corresponds to i th node of a graph. In the context of modeling signals or features with graphs, the widely used assumption is that the signal residing on the graph changes smoothly between connected nodes [10]. For example, if two circuit instances X i and X j have similar features then their Euclidean distance ∥ X i -X j ∥ 2 should be smaller but connecting edge weight which quantifies similarity i.e. w ij should be large. The Dirichlet energy (DE) is used for quantifying the smoothness of the graph signals which is defined as:

The lower value of Dirichlet energy indicates a desirable configuration [31, 10]. Smooth graph signal methods are an extremely popular family of approaches for a variety of applications in machine learning and related domains [12, 10]. In order to build a graph of circuits we will use the smoothness

of signals on graph assumption. Nodes connected with stronger weights indicate similar features and performance indices, facilitating knowledge transfer to new circuit instances. Finally, we learn a weighted adjacency matrix W by minimizing the Dirichlet energy combined with other sparsity regularization terms which entails solving the following optimization problem:

where α > 0 and β ≥ 0 controlling the properties of the resultant graph, ∥ w ∥ 2 2 ensures the graph is sparse, while 1 ⊤ log ( Sw ) ensures that every node will have some connections. This problem is a convex optimization problem and efficiently solvable [12, 10].

3.3 Comprehensive feature vector representation for GCX

To streamline GNN training across various technology nodes and topologies, we extend the initial feature vector with one-hot encoded bits, specifically allocated for the technology file and topology. This augmentation generates a new feature vector that facilitates relevant pattern learning by the GNN. This approach significantly reduces computational costs, making it more viable for practical applications. With this trained GNN model, it becomes possible to accurately predict the performance of circuits that are yet to be seen, thereby enhancing circuit design and optimization. Further information about our proposed method is available in Figure 3.

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3.4 Graph Circuit Explorer-Graph Neural Networks: GCX(GNN) surrogate model

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After learning a graph using the feature vector description provided, the graph undergoes label propagation through the GNN architecture. In this process, each node represents a circuit instance and the graph consists of both labeled and unlabeled nodes. During each layer of the GNN, the nodes interact through message passing, and feature aggregation is carried out. The unlabeled circuit instance acquires information from its labeled neighbors in the form of embeddings. The embeddings

are iteratively updated across the L layers of the GNN, ultimately leading to the prediction of a label for the unlabeled circuit instance (node). The formulation for the embedding update can be understood from the equation given below. The process can be understood from Fig:4

h ( k -1) u ∈ R d ( k -1) : Node embeddings of target node u at layer k . W ( k ) self , W ( k ) neigh ∈ R d ( k ) × d ( k -1) :

are the learnable parameters, b ( k ) ∈ R d ( k ) : represents the bias term and σ : represents elementwise non-linearity (e.g., a tanh or ReLU). GCX, the approach of creating a graph of circuits, seamlessly integrates with any GNN architecture, showcasing its flexibility across circuits and architectures. Extensive experiments provide conclusive evidence of its effectiveness.

4 Efficient Analog Sizing via Constrained Optimization (GCX-EASCO)

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Our new algorithm employs a more efficient graph-based surrogate model to obtain optimal circuit parameters. The algorithm uses a static, offline training framework that has been recommended in [15, 16]. The algorithmic flow is described in Fig:5 and the following is the step-by-step overview:

The EASCO algorithm consists of four main components. Firstly, in the data generation phase, n points are uniformly sampled from a d -dimensional feature space such that X i ∈ [ a i , b i ] where a i and b i are the lower bound (LB) and upper bound (UB) for each feature. This creates a dataset (D) such that D ∈ R n × d . Next, a graph is learned (as previously discussed) using all the n sampled points, with a subset of these points simulated under different labeled data settings ( l ), such as 30%, and 50%, by adopting a semi-supervised learning framework. The labeled points, X train ∈ R l × d are used for training, while the rest, X test ∈ R ( n -l ) × d are reserved for testing. In the third component, GNN models [11, 7, 27] are used to make predictions. Lastly, in the constrained optimization component, uniform sampling and integration with label propagation over unlabeled samples offer an overall comprehension of the feature(search) space. With constraints in place, the process returns a subset of the original search space ˆ D ∈ R k × d where k << n . The objective function is optimized using Differential Evolution (DE) algorithm [4] applied to the resulting parameter space, yielding the most optimal parameters.

5 Analog Sizing Through Real-time Online Graphs (GCX-ASTROG)

The previous algorithm efficiently minimized simulations once coarse boundaries were established. However, handling an increasing number of specifications made it challenging to identify these boundaries. To overcome this, we developed an online training version of the algorithm that requires minimal initial data. It utilizes an optimization algorithm, a surrogate model, and an infill sampling criterion [21] to guide the search towards global optima. The algorithm updates iteratively and provides the optimal circuit design parameters upon meeting the stopping criterion. Our adoption of the ranking criterion from [2] ensures consideration of all constraints and enables a precise approach

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to achieving optimal design outcomes. See Fig. 6 for the algorithm flow, and the step-by-step overview is as follows:

Initially, a dataset ( D ) is generated with α samples such that D ∈ R α × d .The initial dataset is created using SPICE simulations within the bounds, denoted as a i and b i for each design metric. Stopping criteria are predefined, and the optimal design is outputted if these criteria are met; otherwise, the process moves to the next step. In step three, all designs in the database are ranked using the adopted infill sampling criterion [2], and the λ best designs are selected. New bounds ˜ X i = [ ˜ a i , ˜ b i ] are obtained based on these designs, where ˜ X i ∈ R λ × d . The Differential Evolution (DE) algorithm [4] is used to optimize the objective function by generating m child solutions from the population within the newly obtained bounds. Next, a graph is learned (with the previously discussed approach) by combining the features of best λ labeled points with the m unlabeled points obtained from the DE algorithm. The obtained graph is passed through the pre-trained GNN models and labels are predicted for the m unlabeled nodes. After the label prediction, the λ + m labeled points are re-ranked using the infill sampling criterion [2]. The optimal design and its corresponding performance metric (label) are then selected from the λ + m labeled points and incorporated into the original database. This process is repeated until the predetermined iteration budget for each circuit is exhausted.

6 Experiments

In this section, we showcase the experimental results of our two proposed algorithms: EASCO and ASTROG. To evaluate the effectiveness of these algorithms, we chose Two-stage OTA with Miller Compensation which is operating mostly in a linear region, and the Ring Oscillator (Three-stage) which is operating mostly in a nonlinear region as our test cases. The Miller Compensated OTA has 11 design variables, while the Ring Oscillator has 6 design variables. The performance evaluation of our algorithms was conducted using multiple metrics, which will be discussed in detail later. Our experimental workflow comprises four stages. We initiate with a comprehensive description of dataset generation using SPICE simulation and subsequently provide an exhaustive analysis of the algorithm's operational efficiency.

6.1 Harnessing EDA tools- SPICE simulator for Dataset generation

We have considered two test cases belonging to different families of circuits: Amplifiers and Oscillators . Design space bounds, Performance metrics and Specifications are carefully considered after designer's recommendation (mentioned subsequently). Features (design space points) X = ( X u , X l ) are generated by uniformly sampling points across the d -dimensional space forming a matrix of size X ∈ R n × d . Since we employ semi-supervised learning we simulate labels corresponding to only l samples where l << n (samples are randomly chosen to avoid bias). The dataset obtained is : ( X l , X u , Y l ) .

Two-stage Miller Compensated OTA : Design parameters ( X i ) are: Reference current ( I ref ), Reference Voltage ( V dd ), Transistor widths and length ( W 1 -8 , L 1 -8 ) , Capacitance ( C c , C L ) and load resistance ( r L ) . Performance metrics ( Y i ) are : Gain, Unity Gain Bandwidth (UGB), Gain Margin (GM), Phase Margin (PM), Noise and Power.

Three-stage Ring Oscillator : Design parameters ( X i ) are: Reference Voltage ( V dd ), Transistor widths and length ( W 1 , 2 , L 1 , 2 ) and Capacitance ( C 1 ). Performance metrics ( Y i ) are: Frequency, rms Jitter, Delay and Power.

6.2 Performance evaluation of GCX surrogate model

To evaluate the efficacy of our proposed approach of learning graph of circuits, we conducted tests by integrating it with various GNN architectures [11, 7, 27]. For each test case we learned a graph with n = 1k nodes and training was performed under different labeled data settings, with l being set to 30% and 50%. We compared the results of our proposed node-level regression approach with benchmark method ParaGraph [22], which is a graph-level regression setting, and ESSAB [2], a novel two-layer neural network for regression. The methods used for comparison do not facilitate semi-supervised learning hence experimental setup was adopted as in mentioned in [22, 2].

We implemented the graph formation technique described in ParaGraph [22] for our selected test cases. We established a graph level regression problem consisting of 15k graphs along with their corresponding label vectors. Additionally, we constructed a GNN architecture as outlined in the paper. However, during experimentation, we observed that the resulting R 2 scores were predominantly negative. Consequently, we opted not to showcase the results for the surrogate model. We attribute this failure to two main factors: (i) The scarcity of node and edge features specific to the circuit under study. The ParaGraph [22] method was initially designed for industrial circuits with longer feature vectors, which might have impacted the performance on our dataset. (ii) The limited number of graphs available for training. Although the training loss initially decreased, it quickly reached saturation, leading to ambiguous predictions. Considering these factors, we believe that a more comprehensive feature set and a larger training dataset would be necessary to achieve more accurate results with the proposed approach.

We utilized the ESSAB surrogate model [2] with a dataset of 1k labeled samples. To ensure consistency in training conditions, we maintained a 50% training-to-testing ratio, similar to our approach.

Our proposed approach, based on the semi-supervised learning framework, outperforms competing methods even when provided with minimal labeled data. We demonstrate the flexibility of our approach by evaluating it on two test cases representing different classes of circuits. Furthermore, we obtain a highly accurate graph-based surrogate model that will be utilized in the subsequent algorithms proposed in this work. Results of our approach are presented in Tables:1,2,3 respectively.

6.3 Comparative analysis between different Optimization strategies

Our approach involves first obtaining a highly accurate surrogate model, which we subsequently employ in two algorithms, as discussed earlier, to determine the optimal parameters for the given design problem. To evaluate the efficacy of our proposed algorithms, we compare them against two benchmark optimization methods - the DE algorithm [24] and the BO-EI algorithm proposed in [1]. To ensure reproducibility, we run each algorithm ten times. We then solve a single objective constrained optimization problem, based on the designer's recommendations, for each circuit, and report the obtained results. We selected the Figure of Merit (FOM) as the objective function to be minimized in our study. To define the FOM, we extensively reviewed the literature [19, 30] and derived a customized expression that aligns with our specific requirements. Further details regarding the formulation of this FOM can be found in the supplementary materials . The FOM expression we developed effectively balances the trade-off between different specifications, enabling us to optimize the input parameters for the given test cases. The best-case results are depicted in blue , while the second-best results are highlighted in black .

ASTROG stands out as the undisputed champion among all competing algorithms. The convergence speed achieved by ASTROG is approximately 8x faster compared to the BO-EI algorithm [1]. The results are as shown in Table:4.

Among the competing algorithms, BO-EI [1] proved to be a formidable rival for our proposed algorithms. Although EASCO maintained its higher rank in terms of reproducibility, ASTROG delivered the second best results. However, the key factor in determining the champion algorithm lies in the speed of convergence towards the optimal value. In this regard, ASTROG's impressive 4x faster convergence clearly establishes it as the ultimate winner. The results are as shown in Table:5. For a comprehensive analysis of the timing results for each algorithm, please refer to the supplementary materials .

6.4 Knowledge Transfer using Zero-shot and Few-shot learning

To broaden the scope of our approach, we incorporated different technology nodes and topologies into our study. We selected a Three-stage ring oscillator as our initial test case and implemented the procedure for creating a comprehensive feature vector. We specifically focused on conducting fewshot (FS) learning experiments using 180 nm technology nodes. We then assessed the generalization of the trained model to 65 nm technology nodes and a five-stage topology. Additionally, we performed zero-shot (ZS) learning experiments using 45 nm technology nodes. This allowed us to evaluate the model's performance without any prior training on the specific technology node.

In our experimental setup, we focused on utilizing a limited number of labeled samples to address the challenge of computational burden associated with generating labeled data. We considered a total of n = 1k labeled samples and evaluated the performance based on the percentage of data ( l ) representing the infusion of technology/topology information for both few-shot and zero-shot learning. Given the constraints on labeled data availability, zero-shot learning was found to be ineffective in achieving satisfactory performance. However, there was some promising progress observed with few-shot learning, which indicates the potential of utilizing a small amount of labeled data to enhance the learning process.

7 Conclusion

Our new method for creating graph of circuits produced a consistent, homogeneous graph that can be used across multiple circuits. This approach lead to an accurate surrogate model with a computationally inexpensive node-level regression problem. By utilizing semi-supervised learning algorithms, we significantly reduced reliance on labeled datasets. The proposed GCX(GNN) surrogate model was further incorporated into EASCO and ASTROG. For the above mentioned test cases these algorithms outperformed the competing state-of-the-art optimization methods and yielded the most optimal design parameters that precisely meets the designer's criteria.

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Peer reviews:
{"IS_META_REVIEW": false, "comments": "SUMMARY:\nAutomatic circuit design and optimization is an active field of research. Many different algorithms have been proposed with different design objectives, e.g., layout optimization, size optimization, and topology generation. Prior works adopted GNNs to represent circuit topologies, but the authors suggest a different approach in this work. After constructing a dataset consisting of sample circuits and their labels, they are mapped as a node in a graph. Then, a GNN model is employed to predict the labels of unlabeled samples. Two different optimization algorithms are proposed, and they exhibited relatively good performance in experiments.\n\nSTRENGTHS:\n- This is a new approach to applying GNNs to circuit design.\n- The method can be applied to a wide range of circuit topologies (in theory).\n- The surrogate model works relatively well in experiments.\n\nWEAKNESSES:\n- Probably the most interesting idea in this work is how to use graphs for circuit optimization. The way of embedding circuits into a node of a graph looks novel. However, the performance of the surrogate model is quite low, as displayed in Tables 1 and 2. It might be slightly better than prior methods, but its accuracy is still too low, so the method is not very practical. Can this really substitute conventional SPICE simulations when optimizing the design? There is no guarantee that this algorithm can produce an equally good circuit compared to SPICE-based approaches.\n- Since the GNN models and optimization algorithms are not entirely new, this work might not see much interest in the machine learning community, especially considering prior works have been mostly published in EDA conferences and journals (e.g., DAC, ICCAD, and TCAD).\n\nQUESTIONS:\n- The optimized two-stage OTAs display good performances in Table 4. However, analog circuits often show totally different behavior in transient simulations. Were all the final designs verified in transient simulations?\n- 2-stage OTA and ring oscillator are very simple circuits. Did the algorithm work well for more complex circuits?\n\nLIMITATIONS:\n- Not a practical substitute for SPICE models\n- Only tested on simple circuits", "TITLE": "Official Review", "RECOMMENDATION": 3, "REVIEWER_CONFIDENCE": 4, "SOUNDNESS_CORRECTNESS": 2, "DATE": "2023-07-05"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\n- This paper propose a GNN based framework, dubbed as Graph of Circuits Explorer (GCX), to optimize circuit design by predicting the performance parameters of the nodes in circuits, e.g., Gain, Bandwidth, Noise, etc.\n- This paper 1) utilizes a semi-supervised learning framework is employed for the graph-based surrogate model, and 2) creates a comprehensive feature vector that integrates information about various technology nodes and topologies, emphasizing generalizability in zero-shot and few-shot learning frameworks.\n- With the proposed techniques, this work can enhance circuit performance prediction accuracy and efficiency while reducing the reliance on extensive labelled datasets.\n- It demonstrated the proposed frameworks's effectiveness via simulation under 180nm CMOS technology, with model generalizability tested on 65nm and 45nm CMOS process nodes.\n\nSTRENGTHS:\n- The presentation of this paper is very solid and clear, both in terms of the text description and the figure illustration.\n- This work conduct comprehensive validation across different GNN model variants, other circuit performance prediction methods, and different ablation settings. The improvements show are consistent.\n\nWEAKNESSES:\n- The contribution and distinction over the inherent characteristics of GNNs can be stressed out more. This paper extensively leverages the GNN's ability of predicting the unknown nodes' results based on their surrounding neighbors. However, this part has been widely researched for in the transductive learning scenario of GNNs and the label propagation in earlier graph processing works. The authors could better stress out these inherent (vanilla) techniques' limitations and what they do to specifically address them.\n- Practical significance of the results' improvements could be supplemented. Although the evaluations consistently generate improvements, it is a little unclear what the technique can enable in the practical EDA tasks while the existing methods can be lacking. Also, the tested metrics' significance in actual applications can be added.\n- Is there any potential limitation of the proposed methods?\n\nQUESTIONS:\nPlease address the comments in the weakness section.\n\nLIMITATIONS:\nThe authors have not yet included the limitations and broader impacts.", "TITLE": "Official Review", "RECOMMENDATION": 7, "REVIEWER_CONFIDENCE": 1, "SOUNDNESS_CORRECTNESS": 3, "DATE": "2023-07-06"}

comments: SUMMARY:
This paper proposes a graph based semi supervised framework that is capable of driving analog design

STRENGTHS:
* The paper is generally well written and organized.
* The figures are nicely drawn to make understanding necessary concept easier.
* The proposed mehtod is well illustrated, the idea of using semi-supervised methods looks interesting and promising.
*  Experimental results are well demonstrated and explained, comparison against existing methods look promising.

WEAKNESSES:
Please see questions.

QUESTIONS:
* on conclusion, from what I understand the result is more optimal than other methods, how to determine that it yields the most optimal parameters?
* For different technologies, does it need separate training or the knowledge is transferrable across technoilogies?

LIMITATIONS:
* The authors discuss some of the limitations in knowledge transfer.
TITLE: Official Review
SOUNDNESS_CORRECTNESS: 3
DATE: 2023-07-07

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThis article proposes a graph-based circuit design framework to help address the issue of label scarcity in circuit design. The paper is well-written, virtually free of errors or inconsistencies. Information is presented accurately and timely, creating a smooth narrative flow between the main paper and supplementary content. However, I do have some queries regarding the specific technical aspects of the paper. I would be immensely grateful if the authors could provide satisfying answers.\n\nSTRENGTHS:\n(1) The technology presented is quite innovative, successfully merging popular Graph Representation Learning with the semi-supervised nature of GNNs and the fundamental characteristics of circuits.\n(2) The writing exhibits smooth logic, with technical details clearly expressed.\n\nWEAKNESSES:\n(1) The citations in this paper primarily focus on circuit design and system-related conferences or journals. I would like to see more analysis related to GNNs, as GNNs typically require deeper layers for larger circuits (components of which should be quite complex). However, an overly deep receptive field might lead to an over-smoothing issue. Is there a chance of over-smoothing occurring when each device is learning within the network?\n\n(2) While this paper presents many circuit-related simulation experiments, it lacks validation in real-world scenarios. To my knowledge, circuit design in practical settings is costly, which may present challenges for the authors in testing on specific circuits. Nevertheless, I am still interested in querying this issue and hope the authors could offer some related thoughts.\n\n(3) The importance of each device in the circuit might vary. In certain situations, some key devices are crucial to the entire circuit. Therefore, I believe the authors' discrete encoding approach may be unsuitable.\n\nQUESTIONS:\n(1) Please include more detailed analysis of the specific GNN networks, especially addressing potential issues such as over-smoothing.\n\n(2) Is it feasible to conduct experiments in real circuits? If so, please include such tests, which could involve smaller, simpler circuits. If not, it would be helpful to clearly explain the reasons for not testing in real-world situations.\n\nLIMITATIONS:\n(1) Please include tests on various GNN frameworks.\n\n(2) Please clarify in the experiment why only simulation results are presented.", "TITLE": "Official Review", "RECOMMENDATION": 6, "REVIEWER_CONFIDENCE": 3, "SOUNDNESS_CORRECTNESS": 3, "DATE": "2023-07-20"}

{"IS_META_REVIEW": false, "comments": "SUMMARY:\nThe design automation of analog circuits poses significant challenges in terms of the large design space, complex interdependencies between circuit specifications, and resource-intensive simulations. To address these challenges, this paper presents an innovative framework called the Graph of Circuits Explorer. GCX enables the creation of a surrogate model that facilitates efficient exploration of the optimal design space within a semi-supervised learning framework which reduces the need for large labelled datasets. The proposed approach comprises three key stages. The effectiveness of the proposed approach is demonstrated through simulated performance evaluation of various circuits, using derived parameters in 180 nm CMOS technology. Furthermore, the generalizability of the approach is extended to higher-order topologies and different technology nodes such as 65 nm and 45 nm CMOS process nodes.\n\nSTRENGTHS:\n- This paper introduces a novel and innovative approach to optimize circuit design by leveraging graph representation and graph-based semi-supervised learning. The approach is designed to enhance accuracy and efficiency while reducing the reliance on extensive labelled datasets. \n- To achieve this goal, a semi-supervised learning framework is employed for the graph-based surrogate model. a new method is introduced to create a comprehensive feature vector that integrates information about various technology nodes and topologies, emphasizing generalizability in zero-shot and few-shot learning frameworks. By integrating these approaches, two new optimization methods on graph-based surrogate models are proposed: Efficient Analog Sizing via Constrained Optimization (EASCO) and Analog Sizing through Real-time Online Graphs (ASTROG).\n\nWEAKNESSES:\n- This paper leverage a GNN,  more experiences about how to extract the feature need to be performed, such as transformer \n- The process of training is not claimed clearly, the paper claims that \"Semi-Supervised Learning on Graph of Circuits\", More details need to be added. such as the process of Semi-Supervised Learning. \n- How to define the node weights of a graph? when training process, does the relation between two nodes is neccessary for training?\n-\"Stopping criteria are predefined, and the optimal design is outputted if these criteria are met; otherwise, the process moves to the next step.\", the definition of \"Stopping criteria\" is not claimed clearly.\n- the details of dataset is not claimed clearly.\n- \"Given the constraints on labelled data availability, zero-shot learning was found to be ineffective in achieving satisfactory performance. However, there was some promising progress observed with few-shot learning, which indicates the potential of utilizing a small amount of labelled data to enhance the learning process.\" more details and analysis need to be provided\n\nQUESTIONS:\nas written in Weaknesses\n\nLIMITATIONS:\nas written in Weaknesses", "TITLE": "Official Review", "RECOMMENDATION": 5, "REVIEWER_CONFIDENCE": 3, "SOUNDNESS_CORRECTNESS": 3, "DATE": "2023-07-29"}