CWE-1422: Exposure of Sensitive Information caused by Incorrect Data Forwarding during Transient Execution

Description:
A processor event or prediction may allow incorrect or stale data to
		  be forwarded to transient operations, potentially exposing data over a
		  covert channel.

Extended Description:
Software may use a variety of techniques to preserve the
			confidentiality of private data that is accessible within the current
			processor context. For example, the memory safety and type safety
			properties of some high-level programming languages help to prevent
			software written in those languages from exposing private data. As a
			second example, software sandboxes may co-locate multiple users'
			software within a single process. The processor's Instruction Set
			Architecture (ISA) may permit one user's software to access another
			user's data (because the software shares the same address space), but
			the sandbox prevents these accesses by using software techniques such
			as bounds checking. 
			
			 If incorrect or stale data can be forwarded (for example, from a
			cache) to transient operations, then the operations'
			microarchitectural side effects may correspond to the data. If an
			attacker can trigger these transient operations and observe their side
			effec

Affected languages: Not Language-Specific
Affected technologies: Not Technology-Specific
Parent weaknesses: CWE-1420, CWE-1420

Consequences:
  - Confidentiality: Read Memory

Detection methods:
  - Automated Static Analysis: A variety of automated static analysis tools can identify
				potentially exploitable code sequences in software. These tools may
				perform the analysis on source code, on binary code, or on an
				
  - Manual Analysis: This weakness can be detected in hardware by manually
				inspecting processor specifications. Features that exhibit this
				weakness may include microarchitectural predictors, access control
				che
  - Automated Analysis: Software vendors can release tools that detect presence of known
				weaknesses on a processor. For example, some of these tools can
				attempt to transiently execute a vulnerable code sequence and d

Mitigations:
  - [Architecture and Design] The hardware designer can attempt to prevent transient
				execution from causing observable discrepancies in specific covert
				channels.
  - [Requirements] Processor designers, system software vendors, or other
				agents may choose to restrict the ability of unprivileged software to
				access to high-resolution timers that are commonly used to monitor
				covert channels.
  - [Requirements] Processor designers may expose instructions or other
				architectural features that allow software to mitigate the effects of
				transient execution, but without disabling predictors. These features
				may also help to limit opportunities for data exposure.
  - [Requirements] Processor designers may expose registers (for example,
				control registers or model-specific registers) that allow privileged
				and/or user software to disable specific predictors or other hardware
				features that can cause confidential data to be exposed during
				transient execution.

Demonstrative examples:
Faulting loads in a victim domain may trigger incorrect transient
				forwarding, which leaves secret-dependent traces in the
				microarchitectural state. Consider this code sequence example from
				[REF-1391].
A processor with this weakness will store the value of untrusted_arg
				(which may be provided by an attacker) to the stack, which is trusted
				memory. Additionally, this store operation will save this value in
				some microarchitectural buffer, for example, the store buffer. 

				 In this code sequence, trusted_ptr is dereferenced while the attacker
				forces a page fault. The faulting load causes the processor to
				mis-speculate by forwarding untrusted_arg as the (transient) load
				result. The processor then uses untrusted_arg for the pointer
				dereference. After the

Some processors try to predict when a store will forward data to a
				subsequent load, even when the address of the store or the load is not
				yet known. For example, on Intel processors this feature is called a
				Fast Store Forwarding Predictor [REF-1392], and on AMD processors the
				feature is called Predictive Store Forwarding [REF-1393]. A
				misprediction can cause incorrect or stale data to be forwarded from a
				store to a load, as illustrated in the following code snippet from
				[REF-1393]:
In this example, assume that the parameter idx can only be 0 or 1, and
				assume that idx_array initially contains all 0s. Observe that the
				assignment to v in line 4 will be array[0], regardless of whether
				idx=0 or idx=1. Now suppose that an attacker repeatedly invokes fn
			

Real-world examples:
  - CVE-2020-0551: A fault, microcode assist, or abort may allow transient
				load operations to forward malicious stale data to dependent
				operations executed by a victim, causing the victim to unintentionally
				
  - CVE-2020-8698: A fast store forwarding predictor may allow store
				operations to forward incorrect data to transient load operations,
				potentially exposing data over a covert channel.