CWE-1247: Improper Protection Against Voltage and Clock Glitches

Description:
The device does not contain or contains incorrectly implemented circuitry or sensors to detect and mitigate voltage and clock glitches and protect sensitive information or software contained on the device.

Extended Description:
A device might support features such as secure boot which are supplemented with hardware and firmware support. This involves establishing a chain of trust, starting with an immutable root of trust by checking the signature of the next stage (culminating with the OS and runtime software) against a golden value before transferring control. The intermediate stages typically set up the system in a secure state by configuring several access control settings. Similarly, security logic for exercising a debug or testing interface may be implemented in hardware, firmware, or both. A device needs to guard against fault attacks such as voltage glitches and clock glitches that an attacker may employ in an attempt to compromise the system.

Affected languages: Not Language-Specific
Affected technologies: ICS/OT, System on Chip, Power Management Hardware, Clock/Counter Hardware, Sensor Hardware
Parent weaknesses: CWE-1384

Consequences:
  - Confidentiality: Gain Privileges or Assume Identity

Detection methods:
  - Manual Analysis: Put the processor in an infinite
			loop, which is then followed by instructions
			that should not ever be executed, since the
			loop is not expected to exit.  After the loop,
			toggle an I/O bit (
  - Dynamic Analysis with Manual Results Interpretation: During the implementation phase where actual hardware is available, specialized hardware tools and apparatus such as ChipWhisperer may be used to check if the platform is indeed susceptible to voltage
  - Architecture or Design Review: Review if the protections against glitching merely transfer the attack target. For example, suppose a critical authentication routine that an attacker would want to bypass is given the protection of m
  - Architecture or Design Review: Many SoCs come equipped with a built-in Dynamic Voltage and Frequency Scaling (DVFS) that can control the voltage and clocks via software alone. However, there have been demonstrated attacks (like Plu

Mitigations:
  - [Architecture and Design] At the circuit-level, using Tunable Replica Circuits (TRCs) or special flip-flops such as Razor flip-flops helps mitigate glitch attacks. Working at the SoC or platform base, level sensors may be implemented to detect glitches. Implementing redundancy in security-sensitive code (e.g., where checks a

Demonstrative examples:
Below is a representative snippet of C code that is part of the secure-boot flow. A signature of the runtime-firmware image is calculated and compared against a golden value. If the signatures match, the bootloader loads runtime firmware. If there is no match, an error halt occurs. If the underlying hardware executing this code does not contain any circuitry or sensors to detect voltage or clock glitches, an attacker might launch a fault-injection attack right when the signature check is happening (at the location marked with the comment), causing a bypass of the signature-checking process.
After bypassing secure boot, an attacker can gain access to system assets to which the attacker should not have access.
... 
            if (signature_matches)  // <-Glitch Here 
            { 
			 
   

Real-world examples:
  - CVE-2019-17391: Lack of anti-glitch protections allows an attacker to launch a physical attack to bypass the secure boot and read protected eFuses.
  - CVE-2021-33478: IP communication firmware allows access to a boot shell via certain impulses