ARCHIVESHISTORIQUES
DELACOMMISSION
COLLECTION RELIEEDES
DOCUMENTS "COM"
COM(81)559
Vol.1981/0171

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fc
COMMISSION OFTHEEUROPEAN COMMUNITIES
COM(81)559 final
Brussels-8October1981
AmendedProposalfora
COUNCILREGULATION (EEC)
concerning Communityactionsinthefieldof
microelectronic technology
(submittedtotheCouncilbytheCommission
pursuanttothesecondparagraphofArticle
149oftheEECTreaty)
COM(81)559 final

AMENDED ,
PROPOSAL FOR ACOUNCIL REGULATION (EEC )
CONCERNING COMMUNITY ACTIONS INTHE FIELD
- > OFMICROELECTRONIC TECHNOLOGY
(PROPOSAL MODIFIED INACCORDANCE WITH ARTICLE 149 ,2ND PARAGRAPH !
OFTHE EEC TREATY
THE COUNCIL OFTHE EUROPEAN .COMMUNITIES ,
Having regard tothe Treaty establishing theEuropean Economic Community ,
and inparticular Article 235 thereof ,
/ · '
Raving regard totheproposal from theCommission ,
Having regard totheOpinion oftheEuropean Parliament (1),
■Having regard totheOpinion oftheEconomic andSocial Committee (2),
Whereas microelectronic technology isessential tothe development and
competitiveness ofCommunity industry asawhole ,atatime when the
„European economy must ,increasingly provide high added value goods and
services ;whereas ,however ,-the scale and nature ofthe effort needed to
, match theeffort ofcompetitors by1985 require aCommunity approach which
must include public financial support for collaborative research and
development byindustry ;whereas the Council Resolution of 1.1September
1979 (3)invites the Commission toexplore methods ofcoordinating
national policies and tosubmit tothe Council specific .projects at
Community level with aview topromoting microelectronic technology ,
( Whereas the aid granted should aim atfurthering abalanced
market and competition situation in 'the Community and taking into
September consideration theprinciples expressed inCounci IRegulation (EEC)No1996 /79of
9ona Community support mechanism inthefield ofdata processing(4 )■,notleast the '
principles of' the ownership of and access toresults ofsupported
projects ,andthereby ^underlining inparticular the importance of .an
adequate dissemination ofgoods and results ofsupported projects ,
HAS ADOPTED THIS REGULATION :.-
(1) ■'
(2)
(3)OJN»C831 ,13.09.1979 ,p.1
(4)OJN"L231 ,13.09.1979 ,p.1
Provision »!«ddrcts :Ru« Loi200 ,8-1049 BrusMts –Tel«phon «7350040/73580 40-
, T«t«x ;"21877COMEU B"COMEUR BruiMll –

ARTICLE 1
Inorder toattain the Community objectives concerning microelectronic
technology ,coordination atCommunity level ofthe activities undertaken ^
inthe Member States inthis domain and implementation ofjoint projects
tosupplement and reinforce these activities shall becarried out under
theconditions set out inthis Regulation .
TITLE 1
Information and Consultation
ARTICLE 2
Asystem for information and consultation concerning initiatives aimed at
promoting the diffusion and the development ofmicroelectronic technology
and its application ishereby established between the Member States and
the Commission .
.ARTICLE 3
1.In order to ensure that the consultations provided for inthis
Regulation are effective ,Member States shall ,independently ,of ,their
obligations under the rules ofcompetition ,supply the Commission
without delay ontheir own initiative ,oratthe Commission 'srequest ,
with sufficient up todate advance information of ascientific ,
economic and financial nature concerning any activities under their
authority both inprogress on ,the date this Regulation enters into
force and contemplated after that date ,adressed to : '
a)the promotion ,ofindustrial research and development onequipment ,"
processes ,instruments and ,techniques ,both hardware and software ^
for use in the design ,industrial manufacture and 'testir\g of
advanced integrated circuits ; _ v
b)the dissemination ofbasic knowledge and training and education of
management and staff specializing inthe design ,utilization and
testing ofadvanced integrated circuits ;
c)the encouragement ofthe establishment within the Community ofan
industry capable ofdesigning andproducing theequipment ,materials
and techniques used inthe manufacture ofadvanced integrated
circuits . • .
They shall also supply .the Commission with anappraisal oftheresults .
ofall these activities .
Information concerning projects which arethesole property ofacompany
shall not becovered bythis Article .
2.The Commission ,inorder tocoordinate the action ofthe Member States
shall ensure that they receive the information concerning activities
referred toinparagraph 1;

3.After consulting the Committee referred toinArticle 6,theCommission
shall specify .the level ofdetail ofthe information tobemade
available byMember States andofthat tobegiven diffusion ,as .well as
procedures and measures for making this information available toMember
States... '
: . TITLE II .
Joint projects
ARTICLE 4 , ' - , . '•
1.The following key research and development projects ,coming directly
within the sectors defined inArticle 3and regarded ,ashaving highest
priority ,shall benefit from Community support under the terms laid down
inArticle 5. - . '
(I)step and repeat onwafer -
(II)electron beam for direct-writing onwafer • ...
(III )plasma etching and déposition r
IV)test ingequi pment ^ .
(V)Computer Aided Design (CAD )for ,Very Large Scale Integration
circuitry ~(VLSI )inthedomains of 1.Architecture 1
2.Language and Data structure
3.Testing
. • . 4.Device .modeling .
2.The technical specifications for the projects specified atpoint 1above
are set out inthe annex . , '. ~
3}. .The Commission ,inconsultation with the .Committee referred ,toin
Article 6,shall update the technical Specifications asmay berequired .
.ARTICLE 4BIS
When allocating -national public support money toprojects related tothe
sectors defined inArticle 3,Member States ,shall give priority ,all
other "conditions being equal ,to those -whose execution involves a
significant participation ,oforganizations from -two ormore .Community
countries . „

TITLEIII
Financingprocedures >'.
ARTICLE5
From1981theEuropeanCommunityshallprovidefinancialsupporttothe
projectsspecifiedinarticle4(l)intheformofagrantofupto50%
ofthecostsoftheirexecution .
Theappropriations necessarytothisend,nowevaluatedatECUSMio52,
shallbeenteredinthebudgetof,theEuropeanCommunity .
Projectseligibleforaidshallmeetthefollowingconditions :
-theirpurposemustbein.linewiththetechnicalspecifications set
outintheAnnexreferredtoinArticle4(2);
-theprojectsmustbecarriedoutwithintheCommunity ;
1. V
Furtnermore : ■
a)forprojectsItoIVof..Article4(1)
/
-theapplicants mustbemanufacturers orinaustrial users
established inthe-Community ;
–asufficient numberoffirmsfromatleasttwoCommunitycountries
nothavingfinanciallinkswiththe,Manufacturer ormanufacturers
takingpart,inthesameprojectmusthaveprovidedevidenceof
theirinterestin-participating intheprojectandcontributing
theirownresources.' This'numbershallbedecidedbythe
Commission ,foreachproject,afterconsultation oftheCommittee
mentioned inarticle6.
b)forproje<?tsfallingunderVofArticle4(1)
\ • • -
–4theapplicants mustbeuniversities ,researchcentres/offirmsestablishedintheCommunity ; "'"
~asufficient numberoffirms -fromatleasttwoCommunitycountries
nothavingfinanciallinkswitheachothermusthaveprovided
evidencecftheirinterestinparticipating intheprojectand
contributing .theirownresources . >
ThisnumbershallbedecidedbytheCommission ,afterconsultation
of\±e/Committeementionedinarticle6.
Or.retheel.igioility oftheprojecthasbeenestablished underthe
rorrssofparagraph 3.a)or.b)/•-allsuitablyqualifiedfirms
t'StabiitilledintheCommunitymaytakepartintheprojectandapplyfor
Li.erelevantfinancial .supportirrespectively oftheirpossible
financiallinkswithotherparticipants inthesameproject.

-5-
5.Applications shallbeaddressedtotheCommission bytheorganisations
concernedinresponsetocallforproposalspublishedintheOfficialJournal
oftheEuropeanCommunities .Theyshallshowevidencethattheyare
justifiedunderthetermsofparagraph3above,andshallprovideany
otherrelevantinformations .TheCommission mayrequestanydocuments
andadditionalinformations requiredforconstituting thedossier.
6.TheCommissionshallacton-applications forwardedtoitwithina
periodofsixmonthsinaccordancewiththeproceduresetoutin
A.rticle8. , -
7.WithoutprejudicetothepowersoftheCourtofAuditorspursuantto
article206a(3)oftheEECTreaty,theCommission maycarryout
investigations onthespotorinquiriesintotheoperationsfinanced,.
1.ACoordinating Committee ,hereinafter calledtheCommittee ,ishereby
setuptocoordinateprojectspromotingmicroelectronic technology .It
shallconsistofrepresentatives oftheMemberStates,whomaybe
iassistedbyexpertsoradvisersdependingonthenatureoftheproject
'underconsideration ,withaCommission ,representative' asChairman.It
willmeetatleasttwiceayear.TITLEIV
Generalprovisions
ARTICLE6
2.TheproceedingsoftheCommitteeshallbeconfidential .
ν ' ι
3.TheCommitteeshalladoptitsownrulesofprocedure .
4.Secretarial servicesfortheCommittee "shallbeprovidedbythe-, .1
:I
Commission .
-ARTICLE7
TheCommission mayconsulttheCommitteeonanymatterfallingwithinthe
scopeofthisRegulationincluding ,butnotlimitedto:
-level,ofdetailofinformation tobedeliveredconcerningnational
activities asspecified ,inarticle3 -
-levelofdetailofinformation tobemadeavailableeitherpublically
ortoMemberStatesGovernmentagencies
procedures andmeasurestomakesuchinformation available
updatingoftechnicalspecifications forprojectspotentiallyeligible
foraid
minimumnumberoffirmsrequiredtomakeaprojecteligibleforaid
-appraisalofapplications andgrantingofaids.

ARTICLE8
1.Wheretheprocedurelaiddowninthisarticleistobefollowed,the
mattershallbereferredtotheCommittee byitsChairman,eitheron
hisowninitiative ,orattherequestoftherepresentative ofaMember
State.
2.WithintheCommittee ,thevotesoftheMemberStatesshallbeweighted
as.providedforinarticle148(2)oftheTreaty.TheChairmanshall
.notvote.
3.TheCommissionrepresentative shallsubmitadraftofthemeasuresto
be•takenaccompanied byanoutlineofthemainelementsofdecision.
TheCommitteeshallgiveitsopiniononthisdraftwithinaperiodto
befixedbytheChairmanhavingregardtotheurgencyofthematter.It
shalladoptitsopinionbyamajorityof45votes.
4.TheCommissionshalladoptdecisions whichshallapplyimmediately .
However,ifthesedecisionsarenotinaccordance withtheOpinionof
theCommittee ,theyshallforthwithbecommunicated bytheCommission
totheCouncil.InthateventtheCommissionshalldeferapplication of
thedecisionswhichithasadoptedfornotmorethantwomonthsfrom
thedateofsuchcommunications .TheCouncil,actingbyqualified
majority ,maytakeadifferentdecisionwithintwomonths.
« ARTICLE9
EachyeartheCommissionshallforwardtotheEuropeanParliament andto
theCouncilareportonthedevelopmentoftheactivitiesintheCommunity
fallingwithinthescopeofthisRegulation .'
ARTICLE10'1
TheCommission ,afterconsulting theCommittee,shalladoptany
supplementary measureswhichmaybenecessaryforimplementation ofthis
Regulation ."
ARTICLE11
ThisRegulationshallenterintoforceon 1981
Itshallapplyuntil 1985.
ThisRegulationshallbebindinginitsentiretyanddirectlyapplicable
inallMemberStates.
DoneatBrussels,
BYTHECOUNCIL
THEPRESIDENT .

■V
. .'TECHNICAL ANNEX TOTHE PROPOSAL
.FOR ACOUNCIL REGULATION (EEC )-
CONCERNING COMMUNITY ACTIONS INTHE FIELD
OFMICROELECTRONIC TECHNOLOGY
Outline technical specification ofprojects and activities for which
financial support ,isbeing proposed under the terms of the draft
regulation : ,
I)STEP AND REPEAT ONWAFER
Direct Optical Stepping Technology
Direct optical stepping machines should beavailable inproduction
with the characteristics listed -below by the end of 1982 ,
preproduction version should bedelivered bytheendof1981.'
-Wafer size supto6inch
-Die size . ... -1„cm
-Minimum line widths 1.25.A monthe-wafer (1.1 ontheresist )
-Automatic registration 'O.lyfm ;
-Throughput 50x4inch wafers perhour at1cm field with "insertion
of5test patterns and auto-registration ateach chip ;addition ofa
,reticle magazine . ' -
Individual times should begiven inthe description ofthe equipment
including the time toinsert test patterns .Registration should be
programmable (per individual ,exposure -per block –per wafer ).
Minimum allowable size ofalignment marks should begiven .
Itisconsidered desirable that machines could besupplied in1983 wit
animproved throughout of50x6inch wafers per hour and improved
resolution of1.0//mminimum line width onwafer .
II)ELECTRON BEAM FOR DIRECT-WRITING ONWAFER ,
Electron Beam Direct Writing' Equipments :\
.E-Beam machines capable ,-of : "-
-Wafer size 6inch
■ .-Throughput " 15to20layers /hr .at1Jim
-Diesize ,. nolimitation
-.-Minimum feature size ■ 0*5yMm
.-Spot size variable - .
-Registration accuracy O.lytfm *
.This equipment should also besuitable for Reticle and Mask making .
Prototype machines meeting all these requirements apart from speed
must beavailable within 1983 .

-2-
III .PLASMA ETCHING
A.Minimum performances ofthe equipment
-Materials tobeetched
*SiO ,doped and undoped '
*Sl3N4 : . %
*polysilicon ,doped andundoped
*silicides and polycides
*aluminium and aluminium alloys
*other metals for contacts and interconnections
*organic polymers for multilevel resists 'and multilevel
metallization .
-Structures tobeetched inproduction
*pitch :(line plus spacing );3/1m '
*minimum linewidth :1-1.5/1m '
*precision :+or-10% oflinewidth for the critical structures
-Selectivity and anisotropy
The selectivity has tobeadequate and foreach layer itshould
bepossible toetch completely anisotropically .
-Throughput
The minimum throughput should be50wafers /hour for theslowest
process .The slowest process will probably be the etching
through 0.8yC (mofthermal SiO^with aselectivity of10:1 over «
Siand with apitch of3/(m.The etching ofother layers e.g. .>
0.4y4m undoped polysilicon over SiO should bemuch faster .
B.Design ofthe equipment y
Weconsider aparallel plate reactor with the following features :
-Design Concept
Most important isthe use ofamodular design concept sothat
the equipment can beoptimally adapted for each application .

Load lock
Undesired species (e.g. water vapor )should beblocked from the
reaction chamber and post-etching effects must beavoided .This
can bereached with avacuum lock containing the cassettes .
Stripping ;ofthe photoresist in the unload-lock should be
considered asanoption . - ,
Electrode and chamber construction
*Individually .driven thermostats for upper and lower electrode
and for the reaction chamber .The range .for temperature
control is15-100°C standard and upto150°C asanoption .
*Electrode distance adjustable between :5-70 mm (batch oriented
system ) .
5-70 mm (single wafer
- \system )
*The electrode assembly must besuited for operation athigh
frequencies (untill 27.12 MHz )e.g ^avoid parasitic ,plasma
anywhere inthe reactor . , -
*Both parallel plasma etching (PE)and reactive ion etching
(RIE )must bepossible inthe system (anode and cathode
.coupling ).
Vacuurn design
*theregion ofinterest isbetween 10mTorr and 10Torr
*Adjustable pumping speed
/ ■•■■■■ . / ■
*Automatic AND •manual pressure control with simple switching
between the two modes .
*Use ofnon-corrosive materials for seals (fittings ,0-rings )
and tubing .- . -
Gas cabinet
Flexible handling of 1to3gasses with' 1to3mass flow
controllers ,preferentially extendable "to5gasses (number of
gasses isanoption ). ' -

-4-
Controls
*The following parameters must becontrollable :
gasline(s )inuse
flowrate
process tirae
time tostabilize i
time tooveretch
R.F *power -
temperature ofboth electrodes
voltage onelectrode
*The electrical signal from "the sensors {pressure sensor ,...)
-must beeasily accessible (e.g. onastandard plug )forprocess
monitonng .
*Atleast one window tolook into the plasma and additional
flange(s )to hook up some analytical tools for process
monitoring should beavailable . *
-Software for autoraatic etching >
* '
*akeyboard and necessary memory for the step bystep command of
the process orthe maintenance sequence
. . I
*aplug-in PROM ,user programmed ,forautomatic etching .
-Wafer handling .
Automatic wafer handling ,cassette tocassette load and unload
without wafer damage orcontamination .
The system should handle wafers of3inch upto150 mmdiameter .
-Maintenance and safety
*Easy dismantling forcleaning andrepair
^Standardisation offlanges ,seals ,plugs ,etc .and spare parts .
IV)TESTING EQUIPMENT '
European testers for integrated circuits should bedeveloped with the
following characteristics :
•-oftheintegral analog /digital type
-ofmodular design ,inorder tobeadaptable toboth development -and
production testing tasks

-5-
-development intwo phases ,asfarasthedigital part isconcerned .
The first step should beatester forclock-rates of10-20 MHz ,the
second step aiming at50-100 MHz .This stepwise development has the
advantage that the technological know-how ,built-up inthe first
phase can beused totackle theproblems that have tobe~ .faced in
the second development round .Moreover ,the high speed 'test
development can thus beadapted tothe developing requirements of
theEuropean IC-industry inthehigh speed bipolar circuits . L
-testing ofdevices' with anincreasing number ofpins (from 64to
128 ) ' " ■ " - :
-substantial parts ofthetestsystem have tobe'"ECL-specific "
'-testing 'ofmemory devices alone has been excluded ,however "on-the - .
chip "memories ,are becoming increasingly important and therefore
their testing has tobecovered .
-one single high level test language concept should besupplied for
thedifferent tester configurations .
V)CADFORVLSI - - - *
1.Architecture ,
The problems tobetackled are the disciplines ofspecification ,
simulation and testing atthe architectural design phase .ajid "the
architectural strategies like error management and structured
logic .The following activities appear toberequired :
-Improvement inknowledge ofcomputer techniques byVLSI designers
'*^through (a)transfer ofknow-how from computer manufacturers (b)
•' better integration ofcomputer science andelectronic engineering
training inuniversities . ■ , . ' '
-research on :
(a)linking ofbehavioural and structural design bydevelopment
!.ofsuitable languages and simulators
(b?synthesis oflogic from RTLdescription
(c)error management including fault-tolerant -aspects ofVLSI
architecture
(d)structured logic including minimisation forPLAs (Programable
Logic Arrays )and automatic programming ofPLAs and ROMs
■(Read Only Memories ) •' •
(e)firmware generation andsimulation aids
Cf)parallel processing machines forsignal processing

Language and Data structure
1»Design Data Management
Conventional graphic ICdesign systems arebased upon abottom up
representation ofthe circuit being designed .This isconsidered
inadequate for coping with the problems ofVLSI design ,and
instead ,aspecification of afile management or design
management system must be formulated ■with respect to the
following purposes :
1)toaid the management ofalarge number offiles representing
alternative representations ofmany modules ofasystem
2)toprotect theintegrity ofadesign involving ateam effort
3)tomanage design modifications
4)toaidre-partitioning ofadesign
5)tomanage theprovision ofdesign documentation
Research projects must beinitiated which will enhance the normal
filing system or operating system to provide the above
facilities .The smallest unit ofdata inatransaction will bea
complete file ,and soconventional databases are not appropriate .
The implementation must becarried out with 'portability inmind .
Astandard language must beused with well defined interfaces to ,
standard filing systems .This project should beajoint project
between IC designers ,CAD tool specialists ,and computer
scientists . ■ ,
2.User Interface
i • ' . ■
.Some design activities are highly interactive and demand a
guaranteed fast response from thecomputer while not demanding a
very powerful computer .Anexample isdesign specification using
graphical techniques .Such activities can besupported onasmall
computer dedicated toasingle user .Other activities are not
primarily interactive ,but dorequire very powerful computing
facilities .An example is simulation .Such activities need
powerful time-shared systems .
Itisimportant that the computers supporting these related
activities should be intirpately connected .Techniques for
controlling tasks split between two ormore computers ,and for
allowing flexible movement ofdata between these tasks ,should be
investigated .General principles applicable toawide range of
hardware should beestablished .

The present trend inhardware design specification istouse text
based language descriptions which are convenient for expressing
the hierarchical structure ,modularity ,and repetitivity which is
inevitable with VLSI .However ,designers still tend tothink in
terms ofdiagrams ,andgraphical aids will continue tobevaluable
inthe design process ..Aproject ought tobe launched to
investigate methods of combining textual and graphical
representations allowing each tobeconverted automatically into
the other ,sothat the most appropriate interface can -befreely
chosen ateach part ofthedesign process .
/Simulation
Software tools for simulation ,test and verification have to .span
the design spectrum from RTL-s down totransistor level .Activity
should bedirected towards the development ofaflexible multi­
level structural description language for NMOS and CMOS VLSI .
Automatic compiler generation into the syntax ofpresently used
single level tools ,and ,more importantly ,directly into thedata
structure ofmixed mode simulators needs investigation .Mixed mode
simulation techniques need considerable attention in /the area of
data structures ,algorithms ,andmodels . 1
Itisstrongly recommended topay special attention toVLSI
network analysis rather than pure simulation inorder toreduce
design time and ensure design correctness .This isacompletely
new research domain which looks entirely feasable based onthe
data structures and algorithms ofpresently existing mixed mode
simulators .
Verification •
Instead of intensive verification of manually performed or
interactive design steps ,the goal should betoautomate asmuch
aspossible (silicon compilation ,standard cell technique ,etc .)
tomake verification unnececessary .Tofind asolid basis for the ■
use orcreation ofsuch tools ,astudy should bqinitiated which
compares thedifferent approaches aswell asdifferent handcrafted
layouts tofind objective criteria forthe fundamental principles
ofefficiency inlayout . . -
The hierarchical design ofVLSI isobvious .The verification
between the different levels ofhierarchy isaproblem but cannot
beavoided .1Inspite ofthe hierarchy ,the complexity and amount
ofdata isenormous and with todays tools leads touneconomic
computer times .Therefore ,further candidates for research and
development are dedicated hardware modules ("e.g. design rule
checkers ,pattern memory plus counters and shift registers ,or
hardware language processors which produce the appropriate data
structures ).

InfluenceofNewComputerArchitectures
Onthebasisoftheassumptionthat!
-softwareisnowexpensiveandshouldbeoptimisedwhilehardware
ischeaperandcanbeusedmorefreely
-inthelastfewyearsalotofhighperformance parallel
processors havebeendevelopedandimplemented
-thearchitecture ofamachineshouldfittheproblemitisto
solve,
investigation inthefollowingtwoareasisproposed :
1.Development ofnewparallelalgorithms andnewdatastructures in
anyCADbranch,toexploitandimplementthemaximumparallelism .
-. ν
2.Studyofnewspecialpurposehardwareprocessortobeinterfaced
withcurrentlyexistingcomputersystemstoimprovepartoftheir
performance byatleastoneorderofmagnitude .

3.Testing :Summary ofrecommendations
The team ontesting recommend toorganize the future work following the
three main areas and the related topics listed below
MAIN AREA OFACTIVITIES
RESEARCH SPECIFICATION n'DEVELOPMENT
• &EVALUATION '
1)TEST DATA GENERATION -
-functional level testing •: ,-v
(methods and strategies ) >* .:
-element level' ATPG * . .
. ,-ATPG forLSIcells , ~ /
regular logic etc . , *
fault types and models
-fault simulation strategies *, "... ,
-nlodular ATPG system '. * • -*
^language for MTPG *
-inteerated ATDG system . *
2)DESIGN FORTESTABILITY ^
-partitioning ' * •. • ' .-'.
–RAMdesign fortestability *■ ,, -
ci-^programmed units *–design fortestability .
ygénéral techniques '*■/
–hardware implemented
self ,testing •'- . '' • '- ■ ..-
–software /firmwar'
self testing , * . ', -
3)DATA ACQr^'-iTION ANDTATA M/v.'AGEMENT
t'y''' '
-DA'S*system ■ ■ .#
•^'fogram development t.ols ' '> ##
*

–lum
4.Device Modeling :Summary ofrecommendations
The present report onDevice Modeling covers three main areas :
Numerical device simula^tion
Ar.alytical models
Table models
For each ofthem ,the main recommendations are summarizea below .
«
1.Numerical device simulation -
The main target ofthis subproject isthat ofstimulating European
research centres and laboratories todevelop advanced device-simulation
packages ,and make them available toEuropean I.C. manufacturers .This
should allow reaching anindependence with respect toAmerican and
Japanese counterparts.' The need for such anactivity stems from the
fact that .,due tothe importance oftwo-,and even three-dimensional 1
effects ,numerical device simulation represents the only predictive
tool whicli can practically beused for *device design .
Itistherefore recommended that atleast 4simulation packages be
developed ,namely :
-2-D MOSFET simulator _ ,
-2-D simulator for bipolar devices 1
-3-D MOSFET simulator
-3-D simulator for bipolar devices
For each ofthem ,detailed specifications have been defined concerning
the ^physical phenomena tobeincorporated inthe program ,thephysical
andgeometrical device structure ,and I/Ographical capabilities .
2.'Analytical models (MOSFET 'sonly ),
Anactivity inthis area isessential for two main reasons :from the
one hand analytical models trading off accuracy and simplicity are
mostly suited for circuit designers inCAD circuit simulation programs ;
onthe other hand ,the functional dependence ofrelevant electrical
parameters ongeometrical and physical device structure ismost easily
identified inanalytical models ,which can ,therefore ,provide some
insight inthe physical phenomena occuring within adevice .
The following analytical models ,should bedeveloped :
SURFACE CHANNEL
KOSFET's(Long channel ,low voltage (level 1)
(Long channel ,high voltage (level 2)
(Short channel ,low voltage (level 3)
(Short channel ,high voltage (level 4)
.BURIED CHANNEL
MOSFET's(Long channel ,(level 1)
(short channel ,(level 2)

Physical model
Again ,detailed specifications are provided for each ofthe above
models .Inaddition tothe development ofthe models ,the problem of
parameter identification should betackled and solved ,especially as
farascharges (orcapacitances )areconcerned .
Table models . - ' '
The need oftable models has been recognized for timing simulation
purposes .Insuch simulators ,,the capacitances are rather poorly
handled ,,being assumed asconstants ;therefore ,theactivity inthis
area should aim atdeveloping tables for .both curents and capacitances .
The most important problem tobesolved isthat ofproviding the
scaling rules ,while maintaining thecomputationel simplicity which is
needed inorder tostrongly reduce the CPU time ,with respect tothat
needed with analytical .models . , ^

COST ESTIMATES
Assuming :-4to5years worklife oftheequipment
-sQto10preproduction units tobedelivered byone single
manufacturer
-aperiod of trials (leased equipment )and interactive
relationship between the manufacturer and the users of18to
24months
including direct costs ofpersonnel involved inthe project
not including :company overheads ,the cost of auxiliary facilities
surrounding the equipment under development (clean room ,up-stream and
down-stream equipments etc.)and thetraining ofpersonnel ..
The following broad figures emerge (inMioECU):
TOTAL GROSS COST OF
THE PROJECTPUBLIC SUPPORT
Project I Wafer Steppers 8 4
Project II Electron Beam 40 20
Project III Plasma 8*4
Project IV Testing 16 8
Project'V C.A.D. 32 16