+++++

( 1 ) OJ NO L 67 , 9 . 3 . 1984 , P . 54 .

COUNCIL DECISION OF 11 FEBRUARY 1985 ADOPTING THE 1985 WORK PROGRAMME FOR THE EUROPEAN STRATEGIC PROGRAMME FOR RESEARCH AND DEVELOPMENT IN INFORMATION TECHNOLOGIES : ESPRIT ( 85/141/EEC )

THE COUNCIL OF THE EUROPEAN COMMUNITIES ,

HAVING REGARD TO THE TREATY ESTABLISHING THE EUROPEAN ECONOMIC COMMUNITY ,

HAVING REGARD TO COUNCIL DECISION 84/130/EEC OF 28 FEBRUARY 1984 CONCERNING A EUROPEAN PROGRAMME FOR RESEARCH AND DEVELOPMENT IN INFORMATION TECHNOLOGIES ( ESPRIT ) ( 1 ) , AND IN PARTICULAR ARTICLE 3 ( 2 ) THEREOF ,

HAVING REGARD TO THE DRAFT WORK PROGRAMME SUBMITTED BY THE COMMISSION ,

WHEREAS , AT TALKS ORGANIZED BY THE COMMISSION , INDUSTRY AND THE ACADEMIC WORLD HAVE GIVEN THEIR OPINIONS ON THE CONTENT OF THE PROJECTS TO BE LAUNCHED AND THEIR PRIORITY ;

WHEREAS THE COMMITTEE REFERRED TO IN ARTICLE 4 OF DECISION 84/130/EEC HAS BEEN CONSULTED ;

WHEREAS THE PROJECTS IDENTIFIED FALL WITHIN THE AREAS DESCRIBED IN THE TECHNICAL ANNEX TO THE DECISION ADOPTING THE ESPRIT PROGRAMME ;

WHEREAS THE ACTUAL NEEDS REGARDING THE COMMUNITY'S CONTRIBUTION TO NEW PROJECTS FALLING BELOW THE THRESHOLD REFERRED TO IN THE THIRD INDENT OF ARTICLE 6 ( 2 ) OF DECISION 84/130/EEC HAVE BEEN CAREFULLY ANALYZED WITH THE RESULT THAT A CERTAIN RANGE OF FLEXIBILITY IS REQUIRED ,

HAS ADOPTED THIS DECISION :

ARTICLE 1

THE ESPRIT WORK PROGRAMME SET OUT IN THE ANNEX HERETO IS HEREBY ADOPTED FOR 1985 .

ARTICLE 2

AS A TARGET FIGURE , 25 % OF THE COMMUNITY'S TOTAL CONTRIBUTION TO NEW PROJECTS MAY BE ALLOCATED TO NEW PROJECTS WHICH FALL BELOW THE THRESHOLD REFERRED TO IN THE THIRD INDENT OF ARTICLE 6 ( 2 ) OF DECISION 84/130/EEC .

ARTICLE 3

THIS DECISION SHALL ENTER INTO FORCE ON 1 JANUARY 1985 .

DONE AT BRUSSELS , 11 FEBRUARY 1985 .

FOR THE COUNCIL

THE PRESIDENT

G . GORIA

ANNEX

ESPRIT 1985 WORKPLAN

CONTENTS

PAGE

0 . INTRODUCTION AND RESOURCES BREAKDOWN 3

1 . SUBPROGRAMME 1 : ADVANCED MICROELECTRONICS 8

R AND D AREAS 1.1 SUBMICRON MOS 9

1.2 SUBMICRON BIPOLAR 11

1.3 COMPUTER AIDED DESIGN ( CAD ) 12

1.4 COMPOUND SEMICONDUCTOR INTEGRATED CIRCUITS 16

1.5 OPTOELECTRONICS 18

1.6 ADVANCED DISPLAY TECHNOLOGIES 19

1.7 ( NUMBER NOT USED ) 20

1.8 GENERAL TYPE B RESEARCH THEMES 20

1.9 PROJECTS IN SUPPORT OF MORE THAN ONE MICROELECTRONIC AREA 21

2 . SUBPROGRAMME 2 : SOFTWARE TECHNOLOGY 23

R AND D AREAS 2.1 THEORIES , METHODS AND TOOLS 26

2.2 MANAGEMENT AND INDUSTRIAL ASPECTS 33

2.3 COMMON ENVIRONMENT 37

2.4 EVALUATION AND DEMONSTRATION PROJECTS 41

3 . SUBPROGRAMME 3 : ADVANCED INFORMATION PROCESSING 42

R AND D AREAS 3.1 KNOWLEDGE ENGINEERING 42

3.2 EXTERNAL INTERFACES 50

3.3 INFORMATION AND KNOWLEDGE STORAGE 53

3.4 COMPUTER ARCHITECTURES 57

3.5 DESIGN AND SYSTEMS ASPECTS 61

3.6 FOCUSING PROJECTS 63

4 . SUBPROGRAMME 4 : OFFICE SYSTEMS 64

R AND D AREAS 4.1 OFFICE SYSTEMS SCIENCE AND HUMAN FACTORS 66

4.2 ADVANCED WORKSTATIONS 69

4.3 COMMUNICATION SYSTEMS 78

4.4 ADVANCED FILING AND RETRIEVAL SYSTEMS 83

4.5 INTEGRATED OFFICE SYSTEM 86

5 . SUBPROGRAMME 5 : COMPUTER INTEGRATED MANUFACTURE 88

R AND D AREAS 5.0 MANUFACTURING COMPANY STRATEGY AND ORGANISATION 88

5.1 INTEGRATED SYSTEM ARCHITECTURE 89

5.2 COMPUTER AIDED DESIGN AND ENGINEERING ( CAD/CAE ) 90

5.3 COMPUTER AIDED MANUFACTURING ( CAM ) 92

5.4 MACHINE CONTROL SYSTEMS 94

5.5 SUBSYSTEMS AND COMPONENTS 97

5.6 CIM SYSTEMS APPLICATIONS 99

INTRODUCTION AND RESOURCES BREAKDOWN

THIS SECTION IS AN INTEGRAL PART OF THE ESPRIT 1985 WORKPLAN AND IS NECESSARY FOR THE PROPER INTERPRETATION OF THE PLAN .

0.1 . BACKGROUND

THE EUROPEAN ECONOMIC COMMUNITY HAS LAUNCHED THE EUROPEAN STRATEGIC PROGRAMME OF RESEARCH AND DEVELOPMENT IN INFORMATION TECHNOLOGY ( ESPRIT ) . THE ESPRIT PROGRAMME IS INTENDED TO PROMOTE PRECOMPETITIVE AND GENERIC RESEARCH AND DEVELOPMENT IN INFORMATION TECHNOLOGY THROUGH COLLABORATIVE PROJECTS WITHIN THE EUROPEAN COMMUNITY WHICH THE COMMUNITY SHALL FINANCE IN PART . A MANAGEMENT PLAN , THE ANNUAL WORKPLAN , HAS BEEN ESTABLISHED WITHIN ESPRIT TO ENHANCE THE CONTROL AND ACCOUNTABILITY OF THE PROGRAMME . UPDATED BY THE COMMISSION IN CONSULTATION WITH THE ESPRIT MANAGEMENT COMMITTEE , EACH YEAR , THE DOCUMENT IS SUBMITTED TO THE COUNCIL FOR APPROVAL .

THIS IS THE SECOND SUCH WORKPLAN AND IT COVERS THE PERIOD 1985-1989 .

0.2 . PURPOSE

THE PURPOSES OF THE ESPRIT 1985 WORKPLAN ARE :

- TO DESCRIBE PROJECT AREAS AND THEIR INTERRELATIONSHIPS , AND INCLUDE DESCRIPTIONS OF CURRENT WORK OF 1984 .

- TO SERVE AS A GUIDELINE TO POTENTIAL PROPOSERS BY INDICATING THE INTENDED SCOPE AND CONTENT OF THE NEW WORK TO BE INITIATED IN 1985 ;

- TO PROVIDE A FRAMEWORK FOR ASSESSMENT AND REVIEW OF PROJECTS UNDER WAY , IN ORDER TO APPRAISE THEIR PROGRESS INDIVIDUALLY AND IN RELATIONSHIP WITH EACH OTHER ;

- TO ACT AS A REFERENCE DOCUMENT FOR CONSIDERATIONS RELATING TO COORDINATING ACTIVITIES UNDER ESPRIT AND UNDER OTHER COMMUNITY AND NATIONAL PROGRAMMES , AND TO SERVE AS A BASIS TO RELATE ESPRIT TO TECHNOLOGICAL PROGRAMMES OUTSIDE THE COMMUNITY .

0.3 . LAYOUT

AFTER THE INTRODUCTORY SECTION , THE DOCUMENT IS SET OUT IN FIVE MAIN SECTIONS CORRESPONDING TO THE MAJOR TECHNICAL SUBPROGRAMMES OF ESPRIT .

THE PARTITIONING OF ESPRIT R AND D INTO FIVE SUBPROGRAMMES IS LARGELY DICTATED BY THE NEED TO BE ABLE TO MANAGE THE TASK FOR THE COMMUNITY . IN PRACTICE , THE TECHNICAL SUBPROGRAMMES ARE INTERRELATED AND THE WORKPLAN INDICATES THE SIGNIFICANT INTERDEPENDENCIES THAT EXIST .

EACH SUBPROGRAMME IS SPLIT INTO A NUMBER OF R AND D AREAS AND THESE ARE FURTHER SUBDIVIDED INTO R AND D TOPICS AND PROJECTS .

EACH R AND D TOPIC IS DISCUSSED IN DETAIL , INDICATING THE ANTICIPATED CONTINUATION OF WORK FROM PREVIOUS YEARS ( IN THIS CASE 1983/84 ) , THE WORK ANTICIPATED TO START IN 1984 AND THE NEW WORK REQUIRED TO BE STARTED IN 1985 AND FURTHER YEARS .

0.4 . THE ESPRIT APPROACH

THE APPROACH OF ESPRIT IS TO CREATE THE TECHNOLOGICAL BASIS WHICH ENABLES THE COMMUNITY TO SEIZE THE OPPORTUNITIES ASSOCIATED WITH NEW INFORMATION TECHNOLOGY , TO FOSTER COOPERATION AND TO PAVE THE WAY TO STANDARDS OF EUROPEAN ORIGIN .

ESPRIT IS THE COMMUNITY PROGRAMME WHICH IS SPECIFICALLY DESIGNED FOR R AND D WHERE COLLABORATION AT THE COMMUNITY LEVEL IS PURPOSEFUL AND WHICH IS PRE-COMPETITIVE . COLLABORATION IS IN ORDER TO ACHIEVE CRITICAL MASS EFFORTS , OR TO BRING TOGETHER THE NECESSARY EXPERTISE OTHERWISE SCATTERED IN THE COMMUNITY , OR TO CREATE THE POTENTIAL TO ENLARGE MARKETS . IN ADDITION BY PROVIDING THE FRAMEWORK FOR CONCURRENT TECHNICAL APPROACHES ESPRIT INVOLVES COLLABORATION BETWEEN COMPANIES AND BETWEEN COMPANIES AND UNIVERSITIES .

ESPRIT'S PRECOMPETITION REQUIREMENT IS FOR AREAS WHERE MARKET OPPORTUNITIES CAN BE SEIZED WITHIN 5-10 YEARS , AND IN DOING SO ESPRIT STANDS BETWEEN BASIC RESEARCH , AND APPLIED INDUSTRIAL RESEARCH AND DEVELOPMENT WORK . THE FORMER IS NOT NORMALLY DETERMINED BY INDUSTRIAL PRIORITIES AND THE LATTER RESPONDS TO SPECIFIC SHORT TERM NEEDS .

IN THE SELECTION AND DEFINITION OF IT AREAS THAT ESPRIT SHOULD ADDRESS , TWO CONSIDERATIONS HAVE BEEN IMPORTANT :

( I ) TO HAVE SUFFICIENT COMMAND OF BASIC TECHNOLOGIES ;

( II ) TO HAVE SYSTEMS CAPABILITIES WHICH ARE ADAPTABLE TO CHANGING MARKET NEEDS THEREBY PERMITTING THE KNOWLEDGE OF MARKETS TO HAVE FURTHER INFLUENCE ON TECHNOLOGY DEVELOPMENT .

FIVE AREAS OR SUBPROGRAMMES ARE OF STRATEGIC IMPORTANCE TO THE COMMUNITY .

SUBPROGRAMME 1 - ADVANCED MICROELECTRONICS

THE MAJOR THRUST IS TO DEVELOP THE TECHNOLOGIES OF SILICON METAL OXIDE AND BIPOLAR DEVICES AND GALLIUM ARSENIDE DEVICES . EACH HAS DIFFERENCE MERITS FOR SPECIFIC APPLICATIONS . ASSOCIATED CAD , CAM AND OTHER MANUFACTURING METHODS ARE ALSO ADDRESSED .

INTERRELATION WITH OTHER SUBPROGRAMMES WILL ENSURE RAPID DEFINITION OF REQUIRED VLSI DEMONSTRATOR CIRCUITS .

SUBPROGRAMME 2 - SOFTWARE TECHNOLOGY

THE SOFTWARE TECHNOLOGY SUBPROGRAMME AIMS AT MAKING AVAILABLE AT COMMUNITY LEVEL EFFICIENT AND COST-EFFECTIVE METHODS FOR THE INDUSTRIAL PRODUCTION OF HIGH-QUALITY SOFTWARE , AND IS INTENDED TO LEAD TO MORE RAPID INTRODUCTION OF NEW PRODUCTS AND A REDUCTION OF LIFE-CYCLE COSTS IN SOFTWARE .

WORK IN THE SUBPROGRAMME ADDRESSES THEORIES , METHODS AND TOOLS TO PUT SOFTWARE PRODUCTION ON A SOUND ENGINEERING BASIS , PROJECT MANAGEMENT AND INDUSTRIAL ASPECTS TO PUT THESE INTO THE BUSINESS AND INDUSTRIAL CONTEXT , A COMMON INTEGRATED SOFTWARE ENGINEERING ENVIRONMENT AND THE DEMONSTRATION OF THE EFFECTIVENESS OF NEW SOFTWARE PRODUCTION METHODS .

SUBPROGRAMME 3 - ADVANCED INFORMATION PROCESSING

THIS SUBPROGRAMME IS SEEKING MEANS FOR IMPROVING THE PERFORMANCE AND EFFICIENCY OF COMPUTING SYSTEMS BY MAKING USE OF ADVANCES IN FOUR KEY AREAS , NAMELY , KNOWLEDGE ENGINEERING , INCLUDING THE DEVELOPMENT OF KNOWLEDGE ACQUISITION , REPRESENTATION AND MANIPULATION TECHNIQUES ; EXTERNAL INTERFACES , DEALING WITH THE RECOGNITION , UNDERSTANDING AND SYNTHESIS OF SIGNALS ; INFORMATION AND KNOWLEDGE STORAGE , THESE ADVANCES ARE THE DEVELOPMENTS IN DATA AND KNOWLEDGE BASES AS WELL AS THE TECHNIQUES OF ACCESS TO THESE BASES , AND DEALS WITH ARCHITECTURAL CHARACTERISTICS AND PHYSICAL PROPERTIES OF ADVANCED STORAGE DEVICES ; COMPUTER ARCHITECTURE , I . E . THE DEVELOPMENT OF NEW COMPUTER ARCHITECTURES AND THEIR ASSOCIATED PROGRAMMING ENVIRONMENTS WHERE PARTICULAR EMPHASIS WILL BE PLACED ON THE USE OF CONCURRENCY .

SUBPROGRAMME 4 - OFFICE SYSTEMS

THE CHALLENGES FACING OFFICE SYSTEMS DEVELOPMENT INCLUDE UNDERSTANDING AND SUPPORTING THE TASKS OF OFFICE WORKERS AND NOT SIMPLY PROVIDING A TECHNOLOGICAL UPDATE OF TRADITIONAL OFFICE FUNCTIONS , ACHIEVING IMPROVEMENTS IN MANSYSTEM INTERFACES THAT ALLOW PRODUCTIVE USE OF OFFICE SYSTEMS BY A WIDE RANGE OF OFFICE WORKERS , AND THE DEVELOPMENT OF SYSTEM ORIENTED APPROACHES TO OFFICE PROBLEMS .

THE SUBPROGRAMME HAS BEEN DIVIDED INTO FIVE AREAS :

OFFICE SYSTEM SCIENCE AND HUMAN FACTORS

ADVANCED WORKSTATIONS

COMMUNICATION SYSTEMS

ADVANCED FILING AND RETRIEVAL SYSTEMS

INTEGRATED OFFICE SYSTEMS .

SUBPROGRAMME 5 - COMPUTER INTEGRATED MANUFACTURE

THE TWO MAIN OBJECTIVES OF THE CIM SUBPROGRAMME ARE : ONE , THE CREATION IN THE COMMUNITY OF AN ENVIRONMENT IN WHICH MULTIVENDOR AUTOMATED MANUFACTURING SYSTEMS CAN BE IMPLEMENTED WITH THE RESULTING INTEGRATED SYSTEM HAVING MINIMUM FUNCTIONAL OVERLAPS AND MAXIMUM CONNECTIVITY , AND TWO , TO SUPPORT INDIVUAL WORK ON SELECTED SUBSYSTEMS , INTERFACES AND TOOLS WHOSE DEVELOPMENT OR REFINEMENT IS SEEN TO BE OF STRATEGIC VALUE TO THE COMMUNITY INDUSTRY , AND WHOSE DESIGN AIMS ARE CONSISTENT WITH THE GENERAL ARCHITECTURE OF THE ENVIRONMENT .

WORK IN THE SUBPROGRAMME RELATES TO THE TOTAL REQUIREMENTS OF MANUFACTURING ACTIVITIES , FROM THE PLANNING AND DESIGN STAGE TO REAL-TIME CONTROL OF PRODUCTION . IT THEN INCLUDES COMPUTER-AIDED DESIGN ( CAD ) , COMPUTER-AIDED ENGINEERING ( CAE ) , COMPUTER-AIDED MANUFACTURING ( CAM ) , FLEXIBLE MACHINING AND ASSEMBLY SYSTEMS , ROBOTICS , TESTING AND QUALITY CONTROL .

0.5 . PROGRAMME EXECUTION AND INFRASTRUCTURE

THE COMMISSION WILL MANAGE AND MONITOR THE EXECUTION OF THE PROGRAMME .

IT WILL SEE THAT THE INFRASTRUCTURE NEEDED FOR PROGRAMME EXECUTION IS SET UP . PART OF THIS INFRASTRUCTURE IS THE INFORMATION EXCHANGE SYSTEM ( IES ) . ANOTHER PART IS THE DISSEMINATION OF RESULTS AND REPORTS AND THE ACQUISITION OF INFORMATION . A THIRD PART IS CONCERNED WITH THE INTERRELATIONSHIP BETWEEN THE R AND D WORK AND STANDARDISATION ACTIVITIES .

THE ESPRIT INFORMATION EXCHANGE SYSTEM ( IES ) SERVES AS A MANAGEMENT TOOL . THE IES IS AN IT BASED DATA COMMUNICATIONS SYSTEM FOR THE EXCHANGE OF INFORMATION BETWEEN SEPARATED PARTICIPANTS IN ESPRIT PROJECTS , THEIR OWN MANAGEMENTS AND POLICY MAKING BODIES , AND THE COMMUNITY AND NATIONAL ADMINISTRATIONS INVOLVED IN PROGRAMME OR PROJECT MANAGEMENT .

A NUMBER OF THE RESEARCH AND DEVELOPMENT PROJECTS IN ESPRIT WILL LAY THE SCIENTIFIC AND TECHNICAL FOUNDATIONS ON WHICH STANDARDISATION ACTIVITIES WILL BE BASED LATER . CONVERSELY , SOME DEMONSTRATIONS OF THE INTERWORKING OF STANDARDS MAY REQUIRE ADDITIONAL WORK ; THIS WORK WILL BE CONSIDERED AS PART OF THE INFRASTRUCTURE . THE WORK TOWARDS STANDARDISATION WILL BE GUIDED BY THE GENERAL IT STANDARDISATION POLICY ESTABLISHED AND NOT DUPLICATE ANY OF THE EXISTING ORGANISATIONS OR ACTIONS .

THE DISSEMINATION OF RESULTS OF AND INFORMATION ACQUISITION FOR ESPRIT IS AN IMPORTANT ELEMENT OF ESPRIT . ITS GOALS WILL BE THE QUICK APPLICATION OF RESEARCH RESULTS FROM ESPRIT IN THE COMMUNITY INDUSTRY AND TO PROVIDE THE BEST BASIS FOR THE PLANNING AND MANAGEMENT OF THE PROGRAMME , AND FOR PROJECT PARTICIPANTS . FOR THIS PURPOSE BOTH CLASSICAL MECHANISMS LIKE PUBLICATIONS OR WORKSHOPS OR CONFERENCES AND NEWER COMMUNICATION METHODS THROUGH ELECTRONIC MEANS , FOR INSTANCE THE IES , WILL BE USED .

0.6 . TELECOMMUNICATIONS

WHEN THE ESPRIT PLANS WERE ORIGINALLY DRAWN UP , IT WAS RECOGNISED THAT TELECOMMUNICATIONS FORMED AN IMPORTANT PART OF INFORMATION TECHNOLOGY . HOWEVER , THE SUBJECT WAS NOT INCLUDED PER SE AT THAT TIME .

IN SEPTEMBER 1983 , THE COMMISSION PREPARED A COMMUNICATION TO COUNCIL , DEMONSTRATING THE INCREASING ECONOMIC IMPORTANCE OF TELECOMMUNICATIONS TO THE ECONOMIC DEVELOPMENT OF THE COMMUNITY , AND PUTTING FORWARD ACTIONS IN THIS FIELD . THE COMMISSION WAS THEN ASKED TO DETAIL PROPOSALS FOR THE SIX LINES OF ACTION SO IDENTIFIED IN THE ACTION PROGRAMME .

THE PROPOSED SECOND LINE OF ACTION RECOGNISES THE KEY ROLE OF COOPERATIVE R AND D , IT CALLS FOR " COOPERATIVE R AND D AND WORKSHARING AT THE PRE-COMPETITIVE STAGE OF THE ESPRIT TYPE " . ACCORDINGLY , THE COMMISSION INITIATED A PLANNING EXERCISE IN TELECOMMUNICATIONS ( PET ) IN CONJUNCTION WITH MAJOR EUROPEAN COMPANIES AND THE NATIONAL PTT LABORATORIES . THE AIM WAS TO ENABLE PROPER ASSESSMENT OF THE ADVANTAGES THAT MIGHT STEM FROM A COMMUNITY APPROACH IN LAYING DOWN THE TECHNICAL GROUND FOR A SIGNIFICANT IMPLEMENTATION OF INTEGRATED BROADBAND COMMUNICATION ( IBC ) BY 1995 IN THE COMMUNITY .

AS A RESULT , A COMMISSION PROPOSAL FOR AN INVENTORY OF R AND D REQUIREMENTS IN TELECOMMUNICATIONS , " R AND D IN ADVANCED COMMUNICATIONS TECHNOLOGIES IN EUROPE ( RACE ) " IS BEING MADE . THE DRAFT RACE WORKPLAN STATES THAT THE WORK UNDERTAKEN WITHIN ESPRIT MUST BE TAKEN INTO ACCOUNT .

0.7 . TYPES OF PROJECT

THROUGHOUT THE ESPRIT 1985 WORKPLAN , A DISTINCTION IS DRAWN BETWEEN TYPE A AND TYPE B PROJECTS . THESE ARE DEFINED AS FOLLOWS :

TYPE A PROJECTS ARE PROJECTS THAT ARE INDIVIDUALLY DESCRIBED IN THE WORKPLAN , WITH SPECIFIED INTERMEDIATE OBJECTIVES . THEY USUALLY REQUIRE LARGE RESOURCES , BOTH HUMAN AND FINANCIAL , AND CONSIDERABLE INFRASTRUCTURE WITH CLEAR AND CONSTANT PERSPECTIVES .

TYPE B PROJECTS ARE COVERED BY " RESEARCH THEMES " WHICH ARE INDICATIVE BUT DO NOT FORM AN EXHAUSTIVE LISTING . THEY USUALLY REQUIRE SMALLER RESOURCES AND ARE NOT AS AMENABLE TO MILESTONE MANAGEMENT AND REVIEW CYCLES AS THE LARGER PROJECTS .

0.8 . CURRENT STATE OF THE PROGRAMME

THIS WORKPLAN SPECIFIES THE WORK THAT WILL BE OPEN TO PROPOSALS IN 1985 . IT ALSO DESCRIBES WORK IN PROGRESS IN 1984 OR LIKELY TO START BEFORE THE 1985 CALL FOR PROPOSALS . THE STEPS LEADING TO THIS WORK WERE AS FOLLOWS :

AN ADVANCE NOTICE FOR PARTICIPATION IN THE MAIN ESPRIT PROGRAMME WAS PUBLISHED ON 30 DECEMBER 1983 . THE COUNCIL OF MINISTERS APPROVED THE PROGRAMME FOR AN INITIAL PERIOD OF FIVE YEARS ON 28 FEBRUARY , 1984 . THE 1984 WORKPLAN WAS PUBLISHED IN THE OFFICIAL JOURNAL OF THE EUROPEAN COMMUNITIES .

A FIRST CALL FOR PROPOSALS FOR THE MAIN PROGRAMME WAS ISSUED ON 21 MARCH 1984 . NEARLY 450 PROPOSALS WERE RECEIVED IN RESPONSE AND WERE EVALUATED DURING MAY AND JUNE 1984 . A SHORTLIST WAS SELECTED IN JULY 1984 FOR DETAILED NEGOTIATIONS AND FINAL APPROVAL . IN ADDITION , MUCH OF THE WORK CARRIED OUT UNDER THE EARLIER PILOT PHASE IS EXPECTED TO COMBINE WITH THE MAIN PROGRAMME . A DIRECT CONSEQUENCE IN THE 1985 WORKPLAN IS THE INCLUSION OF DESCRIPTIONS OF PROJECTS ALREADY UNDERWAY .

A FURTHER CALL FOR PROPOSALS SHOULD BE EXPECTED IN EARLY 1985 AND AT PROPOSAL TIME ABOUT 120 PROJECTS WILL BE UNDERWAY ALREADY .

FOR PARTICIPATION IN THE IES DEVELOPMENT AND SERVICES , A CALL FOR PROPOSALS WAS PUBLISHED ON 14 JULY 1984 AND HAS PRODUCED 25 RESPONSES WHICH HAVE BEEN EVALUATED .

0.9 . WORKPLAN COVERAGE AND INTENDED RESPONSE

THE 1985 WORKPLAN COVERS THE PERIOD 1985-1989 . THIS IS SUFFICIENTLY LONG TO COVER THE DURATION OF THE LONGER PROJECTS . HOWEVER , INFORMATION TECHNOLOGY IS RAPIDLY EVOLVING AND THEREFORE THE R AND D OBJECTIVES MAY WELL HAVE TO BE MODIFIED IN THE COURSE OF YEARLY REVISIONS . ACCORDINGLY , THE INTERMEDIATE OBJECTIVES THAT ARE SET OUT IN THIS WORKPLAN ARE LESS SPECIFIC TOWARDS THE END OF THE PLANNING PERIOD .

SUCH INTERMEDIATE OBJECTIVES ARE , HOWEVER , NECESSARY TO PROVIDE THE FRAMEWORK AND REFERENCE FOR EVALUATION , PROPER MANAGEMENT , AND FURTHER REFINEMENTS . THEY HAVE BEEN INTRODUCED IN THE WORKPLAN AS THE BEST CURRENT ESTIMATE OF HOW THE OVERALL OBJECTIVES OF THE PROJECT MAY BE ACHIEVED . THEY ARE INDICATORS AND CHECKS AGAINST WHICH CONCRETE PROPOSALS FOR PROJECTS WILL BE EXAMINED . INTERMEDIATE OBJECTIVES SHALL , HOWEVER , NOT BE REGARDED AS LEGALLY MANDATORY IN THE SENSE THAT PROPOSALS HAVING PERFECTLY ACCEPTABLE END OBJECTIVES SHOULD NOT HAVE TO BE REJECTED ONLY BECAUSE THEY MAY HAVE BEEN DESIGNED TO REST ON DIFFERENT INTERMEDIATE OBJECTIVES THAN THE ONES PROPOSED HERE .

WITHIN EACH OF THE SEPARATE SUBJECT AREAS OF ESPRIT THERE EXIST PROGRAMMES OF WORK WHICH MAY DEPEND ON SKILLS , TECHNIQUES OR TECHNOLOGIES WHICH ARE BEING DEVELOPED WITHIN ONE OR MORE OF THE OTHER SUBJECT AREAS .

IN INDIVIDUAL CASES THIS MAY LEAD TO SPECIFIC MILESTONES IN ONE AREA REPLACING IDENTIFIED DEMONSTRATORS IN ANOTHER AREA . CONVERSELY DEMONSTRATIONS MIGHT BE REQUESTED OR STARTED AS A SEPARATE ENTITITY IN SUCH CASES .

UNDER EACH R AND D TOPIC , THE WORKPLAN INDICATES WHERE PROPOSALS FOR A-TYPE AND B-TYPE PROJECTS ARE EXPECTED . TO AID THE PRESENTATION , THE DESCRIPTIONS OF CURRENT WORK ARE TYPOGRAPHICALLY DISTINGUISHED . THESE DESCRIPTIONS ARE LOCATED UNDER THE MOST APPROPRIATE HEADING , BUT IT SHOULD BE REALIZED THAT IN SOME CASES PROJECTS FORMULATED IN RESPONSE TO PREVIOUS WORKPLANS OVERLAP THE SUBJECT BOUNDARIES CURRENTLY USED . THERE ARE SOME AREAS FOR WHICH NO NEW PROPOSALS ARE EXPECTED IN 1985 .

THE BEST INFORMATION ON THESE PROJECTS AVAILABLE AT THE TIME OF WRITING HAS BEEN INCORPORATED IN THE 1985 WORKPLAN . HOWEVER , IT SHOULD BE NOTED THAT AT THE TIME THIS WORKPLAN WAS DRAFTED THE COMMISSION HAD NOT YET CONCLUDED FINAL NEGOTIATIONS ON ALL THIS WORK AND SOME MODIFICATIONS MAY PROVE NECESSARY IN SOME CASES .

A-TYPE PROJECTS ARE PART OF AN EXPLICIT PLAN DEEMED NECESSARY FOR THE SUCCESS OF ESPRIT . THIS MEANS THAT IN A GIVEN TOPIC AREA ALL A-TYPE PROJECTS TAKEN TOGETHER MUST ADDRESS THE TOTALITY OF THE GOALS SET FOR THAT AREA IN THE WORKPLAN . THE EVALUATION AND SELECTION PROCESS OF NEW A-TYPE PROPOSALS IS DIRECTED TO ACHIEVE SUCH COVERAGE .

AS B-TYPE PROJECTS ARE COVERED BY RESEARCH THEMES , THE RESPONSE SHALL NOT NECESSARILY BE LIMITED TO THE ITEMS EXPLICITLY MENTIONED . PROPOSALS ADDRESSING ADDITIONAL RELATED TOPICS WILL BE CONSIDERED AS WELL , AND ALSO ( AS A GENERAL RULE ) B-TYPE PROPOSALS IN SUPPORT OF THE WORK DESCRIBED UNDER THE A-TYPE HEADINGS WILL BE CONSIDERED . IN SPITE OF BEING LESS CONSTRAINED BY TOPIC OR RESULT TO BE ACHIEVED , B-TYPE PROPOSALS MUST HAVE , HOWEVER , A STRONG INDUSTRIAL ORIENTATION AND LEAD TO INDUSTRIALLY EXPLOITABLE RESULTS .

AS REGARDS TOPICS OR SUBDIVISIONS THEREOF THAT ARE ALREADY ADDRESSED BY A-TYPE WORK AND FOR WHICH NO NEW A-TYPE WORK IS INVITED THIS YEAR , IT MUST BE NOTED THAT , IF FOR ANY REASON , THE EXISTING WORK SHOULD NOT BE CONTINUED AS EXPECTED , OTHER MAJOR PROPOSALS ADDRESSING THE SAME AREA MAY THEN BE CONSIDERED AGAIN .

A-PROJECTS OR B-THEMES FOR WHICH NO PROPOSALS OR NO SATISFACTORY PROPOSALS ARE RECEIVED , OR AREAS IN WHICH EXISTING WORK IS DISCONTINUED FOR SOME REASON , WILL BE CONSIDERED AGAIN FOR INCLUSION IN THE WORKPLAN FOR THE SUBSEQUENT YEAR .

0.10 . RESOURCES BREAKDOWN

ALLOCATION OF THE BUDGET BETWEEN THE FIVE SUBPROGRAMMES WILL BE A FUNCTION OF THE WORK ENVISAGED IN THE 1985 WORKPLAN AND OF THE FINAL ALLOCATION OF RESOURCES TO THE PROJECTS STARTED IN 1984 . HOWEVER , AS AN INDICATION OF A TOP-DOWN ALLOCATION , THE DESIRED OVERALL BALANCE BETWEEN THE SUBPROGRAMMES CAN BE USED . SINCE THE 1984 PROPOSALS FOR SOFTWARE TECHNOLOGY ( SUBPROGRAMME 2 ) FELL SIGNIFICANTLY SHORT OF EXPECTATIONS , SOME ALLOWANCE IS MADE FOR THIS BY ALLOCATING MORE RESOURCES FOR 1985 .

THE OVERALL WORKPLAN BREAKDOWN OF RESOURCES FOR EACH SUBPROGRAMME IS ALSO SUBJECT TO MODIFICATION IN THE LIGHT OF FURTHER TECHNOLOGICAL EVOLUTION IN THE WORLD . IN PARTICULAR , IN THE LIGHT OF THE INDUSTRY RESPONSE TO CALLS FOR PROPOSALS , IT MUST BE POSSIBLE TO TRANSFER RESOURCES BETWEEN THE VARIOUS SUBPROGRAMMES - AFTER ALL THE PARTITIONING OF ESPRIT INTO FIVE AREAS IS A MANAGEMENT CONVENIENCE AND IS NOT INTRINSIC TO THE NATURE OF THE WORK . IT MUST BE STRESSED THAT ALL SUBPROGRAMMES ARE VERY HEAVILY INTERRELATED .

THE RESULTING APPROXIMATE DISTRIBUTION OF EFFORT TO BE SUPPORTED , IN MAN YEARS EXPENDED EACH OF THE NEXT FIVE YEARS , IS AS FOLLOWS :

SUBPROGRAMME * PROGRAMME YEAR

* 2 * 3 * 4 * 5 * 6

1 . MICROELECTRONICS * 400 * 440 * 430 * 430 * 440

2 . SOFTWARE TECHNOLOGY * 340 * 390 * 400 * 400 * 440

3 . AIP * 370 * 420 * 420 * 420 * 440

4 . OFFICE SYSTEMS * 320 * 360 * 340 * 320 * 360

5 . CIM * 200 * 230 * 230 * 200 * 240

TOTAL * 1 630 * 1 840 * 1 820 * 1 770 * 1 920

SUBPROGRAMME 1

ADVANCED MICROELECTRONICS

1 . THE MAJOR THRUST OF THIS SUBPROGRAMME IS TO DEVELOP THE KEY ENABLING TECHNOLOGIES OF SILICON MOS AND BIPOLAR AND GAAS WITH THE ASSOCIATED CAD . THESE EACH HAVE DIFFERENT MERITS FOR SPECIFIC IT APPLICATIONS ; THESE ARE LISTED IN THE TABLE BELOW .

* SPEED * POWER * DRIVE CAPAB . * COST PER FUNCT . * LEVEL OF INTEGR . * MARKET SIZE

MOS * + + + * + + + + + * + * + + + + + * + + + + + * + + + + +

BIPOLAR * + + + + * + + * + + + + + * + + + * + + + * + + +

GAAS * + + + + + * + + + + * + + * + * + * +

WHEN ASSOCIATED WITH CAD , CAM AND MANUFACTURING METHODS , THESE WILL PRODUCE BY 1988 A SOUNDLY BASED 1 UM INDUSTRIAL CAPABILITY IN A NUMBER OF EUROPEAN SITES , WITH SUBSTANTIAL PROGRESS TOWARDS SUBMICRON CAPABILITY . ALSO IN PLACE WILL BE THE NECESSARY CAD TO DESIGN VLSI CIRCUITS WHICH USE THESE TECHNOLOGIES .

2 . COMMUNICATION WITH THE OTHER SUBPROGRAMMES MUST BE ENHANCED TO ENSURE RAPID DEFINITION OF THE REQUIRED VLSI DEMONSTRATOR CIRCUITS , THEIR DESIGN AND FABRICATION , FUNDED FROM THOSE SUBPROGRAMMES .

3 . THE SUPPLY OF SCIENTIFIC AND ENGINEERING PERSONNEL TRAINED IN THE SPECIFIC SKILLS OF MICROELECTRONIC PROCESS TECHNOLOGY AND DESIGN MUST BE INCREASED .

4 . SUPPORT FOR LONGER RANGE WORK , INCLUDING OPTOELECTRONICS , IS PROVIDED FOR AT A REASONABLE LEVEL .

5 . OVER AND ABOVE THE WORK STARTED AS PART OF THE 1984 WORKPLAN THERE IS A NEED FOR SPECIAL ATTENTION TO CRITICAL AREAS OF TECHNOLOGY AND TECHNIQUES . THESE ARE ADDRESSED IN THE NEW AREA 1.9 AND INCLUDE PACKAGING , DRY ETCHING , RESIST TECHNOLOGY , CONDUCTORS , INSULATORS AND EPITAXY .

IN R AND D AREAS 1.1 AND 1.2 THE MOS AND BIPOLAR PROCESS PROGRAMMES HAVE BEEN RETAINED FOR INFORMATION THOUGH THEY HAVE NOW BEEN ADDRESSED BY THE PROJECTS LISTED . THESE PROGRAMMES WERE STRUCTURED AS LARGE INTEGRAL PROJECTS RATHER THAN SEPARATE 1 UM AND SUBMICRON PROJECTS . THIS HAS BEEN DONE IN THE INTERESTS OF EFFICIENCY , AS EACH LEVEL OF TECHNOLOGY BUILDS ON THE KNOWLEDGE GAINED FROM PRECEDING LEVELS . MANY ASPECTS OF A GIVEN PROCESS REQUIRE CONTINUOUS IMPROVEMENT , E . G . OXIDE QUALITY IN MOS , TO MEET THE DEMANDS OF EACH SUCCESSIVE DEVELOPMENT OF GREATER CIRCUIT COMPLEXITY AND HIGH PERFORMANCE . THIS CONTINUITY OF EFFORT WOULD BE LOST BY HAVING SEPARATE PROJECTS AT 1 UM AND SUBMICRON LEVELS .

A NEW ASPECT OF THE STRATEGY IS THE IDENTIFICATION OF THE NEED FOR MAJOR COHERENT PROJECTS FOCUSSED AS SPECIFIC ASPECTS OF TECHNOLOGY , SUPPORTING THE MAIN PROGRAMMES WHERE RELEVANT . IT IS HIGHLY DESIRABLE THAT EQUIPMENT SUPPLIERS BE INVOLVED . THESE PROJECTS ARE IDENTIFIED IN AREA 1.9 .

THE IMPORTANCE OF CAD FOR VLSI TO THE OVERALL SUCCESS OF ESPRIT CANNOT BE OVER-EMPHASIZED . GIVEN GOOD TECHNOLOGY AND OUTSTANDING CAD , THE HIGHLY INNOVATIVE EUROPEAN INDUSTRY WILL BE ABLE TO COMPETE SUCCESSFULLY IN WORLD MARKETS .

A TOTAL OF SOME 13 CAD PROJECTS , INVOLVING ABOUT 650 MAN-YEARS BETWEEN 1983 AND 1987 , SUPPORTED UNDER THE MICROELECTRONICS REGULATION ( EEC ) 3744/81 AND THE ESPRIT PILOT PHASE ARE ALREADY UNDERWAY . IN ADDITION A NEW PROJECT IS BEING LAUNCHED THIS YEAR ( 1984 ) . THE INTEGRATION OF THE RESULTS OF THIS WORK AND EXTENSION TO COVER THE DESIGN OF SEVERAL MILLION COMPONENT CIRCUITS FOR A WIDE RANGE OF APPLICATIONS IS A MAJOR TASK .

FOLLOWING DETAILED CONSIDERATION OF THE WORK CURRENTLY UNDERWAY , THE NEED FOR A MAJOR THRUST FORWARD IN CAD HAS BEEN IDENTIFIED AND THIS IS INCLUDED IN THE WORKPLAN IN R AND D AREA 1.3 .

THERE ARE FAR MORE ORGANIZATIONS WITH A DIRECT INTEREST AND COMPETENCE IN THE CAD FIELD THAN IS THE CASE WITH VLSI TECHNOLOGY . THE PROJECTS PROPOSED HERE MUST BE PLANNED WITH SUFFICIENT FLEXIBILITY TO DEAL WITH THE COMPLEX TECHNICAL AND ORGANIZATIONAL ISSUES INVOLVED . THE ESPRIT INFORMATION EXCHANGE SYSTEM WILL BE A VALUABLE AID IN THE AREA .

COMPUTER CONTROL OF MANUFACTURING VLSI IS SEEN AS AN ESSENTIAL PART OF THE PROGRAMME , NOT JUST A MEANS OF INCREASING MANUFACTURING EFFICIENCY . THE REDUCTION IN FEATURE SIZE AND LAYER THICKNESS PLACE INCREASING DEMANDS ON PROCESS CONTROL IN A SITUATION WHERE THE FINAL DEVICE PARAMETERS ARE DEPENDENT ON A LARGER NUMBER OF VARIABLES . THE MINIMIZATION OF HUMAN HANDLING AND AN ATTACK ON THE SOURCES OF YIELD LIMITING CONTAMINATION ARE CRITICAL . FOR A GIVEN LEVEL OF CONTAMINATION , YIELD FALLS RAPIDLY AS FEATURE SIZE IS REDUCED . THE SUBMICRON MOS AND BIPOLAR PROJECTS WILL ADDRESS COMPUTER-AIDED MANUFACTURING ASPECTS WHERE APPROPRIATE . THESE COULD ALSO BE ADDRESSED UNDER APPROPRIATE TYPE B PROJECTS .

R AND D AREA 1.1 : SUBMICRON MOS ( TYPE A )

DESCRIPTION

THE REQUIREMENT IS TO DEVELOP ALL THE INDIVIDUAL PROCESS STEPS SUCH AS LITHOGRAPHY , ETCHING , DOPING , ETC . , TO ACHIEVE SUBMICRON FEATURE SIZE IN MOS . THE TARGET IS A PROCESS CAPABLE OF MAKING SEVERAL MILLION COMPONENTS PER CHIP OF LOGIC AND MEMORY . IT IS ENVISAGED THAT BELOW ABOUT 0,7 UM OTHER THAN OPTICAL LITHOGRAPHY TOOLS WILL BE USED . PROCESS AND DEVICE MODELLING WILL BE INCLUDED . TO ACHIEVE THESE GOALS THE CRITICAL TECHNIQUES NEED TO BE DEVELOPED . THESE ARE COMMON TO AREAS 1.1 AND 1.2 AND ARE ADDRESSED IN 1.9 .

PREREQUISITES

- EXPERIENCE WITH STATE-OF-THE-ART PROCESSING ;

- EXPERIENCE ON ADVANCED PROCESS STEPS ;

- AVAILABILITY OF FUNCTIONING COMPUTER AIDED DESIGN/COMPUTER AIDED TEST ( CAD/CAT ) TOOLS ;

PROGRAMME ( - ) AND INTERMEDIATE OBJECTIVES ( * ) :

YEAR 1 :

- CHOICE OF PROCESS ( CMOS OR MIXED C - AND NMOS ) AND OF DESIGN METHODOLOGY ;

- CHOICE OF OPTICAL LITHOGRAPHY EQUIPMENT ;

- ESTABLISHMENT OF PROCESS STEPS .

YEAR 2 :

- OPTIMIZATION OF INDIVIDUAL PROCESS STEPS ;

- ESTABLISHMENT OF PRELIMINARY DESIGN RULES ;

- CHARACTERIZATION OF PROCESS STEPS ;

- START RESEARCH ON NOVEL PROCESS AND STRUCTURES FOR SUBMICRON TECHNOLOGY .

* 18TH MONTH : DESIGN AND EVALUATION OF TEST VEHICLE OF MORE THAN 1 000 TRANSISTORS BASED ON 1 UM DESIGN RULES WITH A PITCH ( METAL PLUS SPACING ) OF 3 UM .

YEAR 3 :

- DEMONSTRATION OF FEASIBILITY WITH A 1 UM FEATURE SIZE , 0,5 MILLION COMPONENTS CIRCUIT . THE TARGET IS A FIGURE OF MERIT OF 50 FEMTO-JOULES AND 1 NS DELAY TIME ;

- EVALUATION OF NOVEL STEPS ( GATE MATERIAL , ISOLATION , INTERCONNECTION ETC . )

- EVALUATION OF EQUIPMENT FOR SUBMICRON PROCESSING .

* 36TH MONTH : FIRST SAMPLES OF DEMONSTRATION CIRCUIT WITH 0,5 MILLION TRANSISTORS , 1 UM DESIGN RULES , WITH DATA ON FIGURE OF MERIT AND DELAY TIME .

YEAR 4 :

- CHOICE OF SUBMICRON LITHOGRAPHY EQUIPMENT ;

- FLOW CHART OF A 0,7 UM PROCESS INCLUDING DESIGN RULES .

* 48TH MONTH : STATISTICAL DATA ON HOMOGENEITY ON A SLICE AND YIELD FOR 1 UM DESIGN RULES ; AND TEST VEHICULE WITH MORE THAN 1 000 TRANSISTORS WITH 0,7 UM DESIGN RULES AND A PITCH OF 2 UM .

YEAR 5 :

- EVALUATION OF THE 0,5 UM PROCESS ;

- DEMONSTRATION OF THE PROCESS FEASIBILITY ;

- DESIGN OF A DEMONSTRATION CIRCUIT WITH MORE THAN 1 000 000 COMPONENTS , A FIGURE OF MERIT OF 50 FEMTO-JOULES AND 1 NS GATE DELAY .

* 60TH MONTH : FIRST SAMPLES OF CIRCUITS WITH MORE THAN 1 000 000 TRANSISTORS , 0,7 UM DESIGN RULES , WITH DATA ON FIGURE OF MERIT AND DELAY TIME .

ACTIVITIES DEPENDENT ON 1.1

VLSI MICROELECTRONICS FOR INFORMATION TECHNOLOGY .

1.1.1 . " SOI MATERIALS AND PROCESSING TOWARDS 3 D INTEGRATION " ( REF . 245 : A/84 )

THE AIM OF THIS COOPERATIVE RESEARCH IS TO STUDY AND DEVELOP NEW SILICON TECHNOLOGIES NECESSARY FOR THREE DIMENSIONAL INTEGRATION . THIS 3 D APPROACH WILL OFFER THE POSSIBILITY OF HIGHER DENSITY INTEGRATION , HIGHER SPEED OF OPERATION AND MULTIFUNCTIONAL SIGNAL PROCESSING . THREE MAIN TECHNOLOGICAL STEPS WILL BE EXPLORED :

A ) THE GROWTH OF SOI ACTIVE LAYERS HAVING ELECTRONIC PROPERTIES NEEDED FOR THE REALISATION OF HIGH QUALITY DEVICES AND CIRCUITS

B ) THE STACKING OF TWO ACTIVE LEVELS IN A WAY THAT AVOIDS ANY DEGRADATION OF ALREADY BUILT DEVICES

C ) THE SINGLE LEVEL SOI PROCESSING FOR THE FABRICATION OF INDIVIDUAL COMPONENTS AND FOR THEIR CONNECTION ; THE DEVELOPMENT OF A COMPLETE PROCESS INCORPORATING TWO ACTIVE LAYERS .

1.1.2 . " SUBMICRON CMOS TECHNOLOGY " ( REF . 554 : A/84 )

THE PROJECT AIMS AT DEVELOPING THE NECESSARY BUILDING BLOCKS FOR A 0.5 UM CMOS PROCESS , PRIMARILY DEDICATED TO THE PRODUCTION OF HIGH SPEED DIGITAL CIRCUITS . IN ORDER TO ALLOW THE PROGRAMME TO PROCEED WITH THE BEST CHANCES OF SUCCESS , TWO MAIN PHASES HAVE BEEN IDENTIFIED AND ORGANISED : THE FIRST REFERS TO AN INTERMEDIATE STEP AT THE 1.0 UM LEVEL ; THE SECOND TO THE FINAL 0.5 UM CMOS FAMILY . AT THE END OF THE PROJECT , THE IC COMPANIES OF THE CONSORTIUM WILL HAVE , IN THEIR PILOT LINES , THE BUILDING BLOCKS OF A CMOS PROCESS CAPABLE OF REALISING IC'S WITH 0.5 UM FEATURES .

1.1.3 . " PHYSICAL-CHEMICAL CHARACTERISATION OF SILICON OXYNITRIDES IN RELATION TO THEIR ELECTRONIC PROPERTIES " ( REF . 369 : B/84 )

THE AIM OF THE PROJECT IS FIRSTLY TO ESTABLISH THE RELATION BETWEEN THE PHYSICO-CHEMICAL AND THE ELECTRICAL PROPERTIES OF SILICON OXYNITRIDE FILM AND SECONDLY THE RELATION BETWEEN THE PHYSICO-CHEMICAL PROPERTIES AND THE GROWTH PARAMETERS . THIS RESEARCH WILL BE CARRIED OUT IN VIEW OF THE LIKELY APPLICATIONS OF SILICON OXYNITRIDES IN I . C . TECHNOLOGY , FOR INSTANCE IN MNOS BASED NON-VOLATILE MEMORIES AND IN SUBMICRON MOS DEVICES .

NO FURTHER A-TYPE PROPOSALS ARE EXPECTED FOR AREA 1.1 .

SPECIFIC B TYPE PROPOSALS ARE SOUGHT IN SUPPORT OF THE ABOVE PROJECTS IN THE AREAS IDENTIFIED IN SECTION 1.9 .

R AND D AREA 1.2 : SUBMICRON BIPOLAR ( TYPE A )

DESCRIPTION

THE OVERALL OBJECTIVE IS TO DEVELOP SPECIFIC BIPOLAR SUBMICRON PROCESS STEPS , LEADING TO A COMPLETE PROCESSING SEQUENCE FOR VERY HIGH PERFORMANCE ICS .

TO REALIZE THIS OBJECTIVE THE FOLLOWING DEVELOPMENTS ARE INCLUDED IN THE PROJECT AREA :

- OVERALL CIRCUIT CONCEPTS WHICH MUST EVOLVE TOGETHER WITH THE TECHNOLOGY ;

- A VERTICAL DEVICE STRUCTURE APPROPRIATE TO SUBMICRON LITHOGRAPHY ;

- A CONVENIENT MULTILAYER INTERCONNECTION TECHNOLOGY ;

- A SUITABLE CONTACT AND MULTILAYER INTERCONNECTION TECHNOLOGY ;

- APPROPRIATE HIGH DISSIPATION , HIGH PIN COUNT , ELECTRICALLY MATCHED LEADS , PACKAGES ;

- PROCESS AND DEVICE MODELLING .

IN ADDITION THE PROJECT AREA SPECIFICALLY DEPENDS ON THE AVAILABILITY OF CRITICAL TECHNIQUES COVERED BY AREA 1.9 .

PREREQUISITES

- EXPERIENCE WITH VLSI AND ADVANCED SILICON PROCESSING ; AVAILABILITY OF CAD/CAT TOOLS .

ACTIVITIES DEPENDENT ON 1.2

FAST VLSI MICROELECTRONICS FOR INFORMATION TECHNOLOGY .

PROGRAMME ( - ) AND INTERMEDIATE OBJECTIVES ( * ) :

YEAR 1 :

- 1 UM TECHNOLOGY : ESTABLISH ACTIVITY ON PROCESS STEPS , CIRCUIT STRUCTURES , MODELLING . EVALUATE AND CHOOSE CRITICAL EQUIPMENT ;

- FIRST CHOICE OF PROCESS AND CIRCUIT STRUCTURES .

* 12TH MONTH : INITIAL PROCESS DESIGN ; EVALUATION AND CHOOSE CRITICAL EQUIPMENT .

YEAR 2 :

- PRELIMINARY OPTIMIZATION OF PROCESS STEPS ;

- DESIGN RULES AT 1 UM ;

- START DESIGN OF DEMONSTRATOR CHIPS ;

- START RESEARCH ON NOVEL PROCESSES AND STRUCTURES FOR SUBMICRON TECHNOLOGY .

* 24TH MONTH : ESTABLISH FINAL DESIGN RULES AT 1 UM .

YEAR 3 :

- DEMONSTRATION OF 1 UM PROCESS FEASIBILITY FOR 10/20 KGATES , 100 PS GATE DELAY CHIPS ;

- START WORK ON MULTILAYER 2 UM PITCH IN ADDITION TO PILOT PROJECT CONTINUATION ;

- CONTINUE RESEARCH ON SUBMICRON TECHNOLOGY ;

- PRELIMINARY DESIGN RULES FOR 0,7 UM STRUCTURES .

* 36TH MONTH : DEMONSTRATE 1 UM 10/20 KGATES , 100 PS GATE DELAY CIRCUITS .

YEAR 4 :

- START DESIGN OF DEMONSTRATOR CHIP AT 0,7 UM ;

- OPTIMIZATION OF SUBMICRON PROCESS STEPS ;

- CHOICE OF CRITICAL EQUIPMENT ;

- YIELD IMPROVEMENT OF 1 UM DEMONSTRATOR .

* 48TH MONTH : ESTABLISH FINAL DESIGN RULES FOR 0,7 UM STRUCTURES .

YEAR 5 :

- DEMONSTRATION OF 0,7 UM PROCESS FEASIBILITY FOR 20/50 KGATES , 50 PS GATE DELAY CHIPS .

* 60TH MONTH : AVAILABILITY OF FIRST SAMPLES OF 20/50 KGATE CIRCUITS IN 0,7 UM PROCESS .

1.2.1 . " SUBMICRON BIPOLAR TECHNOLOGY - I " ( REF . 243 : A/84 )

THE OVERALL OBJECTIVE OF THIS PROGRAMME IS TO DEVELOP SPECIFIC BIPOLAR SUBMICRON PROCESS STEPS LEADING TO COMPLETE PROCESSING SEQUENCES FOR THE MANUFACTURE OF VERY HIGH PERFORMANCE INTEGRATED CIRCUITS . AT THE END OF A FIVE YEAR PERIOD , THE PROCESS FEASIBILITY FOR SUBMICRON STRUCTURES WILL BE DEMONSTRATED ON A LARGE TEST CHIP .

1.2.2 . " SUBMICRON BIPOLAR TECHNOLOGY - II " ( REF . 281 : A/84 )

THE GOAL OF THE PROJECT IS THE DEVELOPMENT OF A BIPOLAR TECHNOLOGY FOR HIGH-SPEED DATA PROCESSING PRODUCTS ( GATE DELAY SMALLER THAN 100 PS , POWER DELAY PRODUCT SMALLER THAN 0,1 PJ , DESIGN RULES SMALLER THAN 1 UM ) . TO REALISE THIS , SPECIFIC PROCESSES FOR COMPONENT ISOLATION , THIN EPI-LAYERS , E-B STRUCTURES , SCHOTTKY DIODES , POLY SI-RESISTORS , MULTILAYER-METALLISATION IN EXCESS OF 4 LAYERS , ADEQUATE PACKAGING AND TESTING TECHNIQUES HAVE TO BE DEVELOPED . THE FEASIBILITY , PERFORMANCE , YIELD AND RELIABILITY WILL BE DEMONSTRATED WITH SPECIFIC TEST VEHICLES ESPECIALLY A GATE ARRAY WITH 10 KGATES/CHIP . THE GATE DELAY OF LESS THAN 100 PS WILL BE GRADUALLY ATTAINED IN THREE STEPS : 200 , 100 , LESS THAN 100 PS .

NO FURTHER A-TYPE PROPOSALS ARE EXPECTED IN AREA 1.2 .

SPECIFIC B TYPE PROPOSALS ARE SOUGHT IN SUPPORT OF THE ABOVE PROJECTS IN THE AREAS IDENTIFIED IN SECTION 1.9 .

R AND D AREA 1.3 : CAD

GLOBAL OBJECTIVES

( A ) TO DEVELOP ADVANCED CAD TECHNIQUES TO MANAGE THE EVER INCREASING CIRCUIT COMPLEXITIES ;

( B ) TO PROVIDE A CAPABILITY FOR COMPLEX VLSI DESIGN WIDELY ACCESSIBLE TO THE EEC IT COMMUNITY .

THE OVERALL AIM IS TO DEVELOP WITHIN A COMMON FRAMEWORK AN INTEGRATED SET OF PORTABLE TOOLS CAPABLE OF HANDLING VLSI CIRCUITS CONTAINING UP TO SEVERAL MILLION COMPONENTS .

THIS SHOULD :

- PROVIDE A FAST RESPONSE , USER FRIENDLY FACILITY THAT IS READILY ADAPTABLE TO CHANGES IN TECHNOLOGY ;

- ALLOW DESIGNERS TO ACHIEVE A RAPID TURNROUND OF VALID AND TESTABLE DESIGNS AND ASSOCIATED TEST INFORMATION ;

- BE EASILY ADAPTABLE TO CHANGES IN TECHNOLOGY ;

- PROVIDE FACILITIES FOR RELIABILITY AND PERFORMANCE OPTIMIZATION OF CIRCUITS ;

- INCLUDE METHODOLOGIES OF CELL-BASED DESIGN AND LIBRARIES OF ADAPTABLE BUILDING BLOCKS ;

- ASSIMILATE RELEVANT RESULTS OF CAD PROJECTS UNDER REGULATION ( EEC ) 3744/81 .

STRATEGY

( A ) A POSITIVE ATTEMPT SHOULD BE MADE TO ENCOURAGE THE EMERGENCE OF AN OVERALL CAD INFRASTRUCTURE SUCH THAT THE MAJORITY OF TOOLS DEVELOPED UNDER EXISTING PROGRAMMES TOGETHER WITH FUTURE TOOLS CAN BE COMBINED TO PROVIDE AN INTEGRATED WIDELY ACCESSIBLE TOOL CAPABILITY .

( B ) AS FAR AS POSSIBLE , COMPLEX DEMONSTRATOR CHIPS WILL BE USED AS A FOCUS FOR EACH STAGE OF THE PROJECT .

( C ) DEVICE AND PROCESS MODELLING IS NOT CONSIDERED AS PART OF THE CAD PROJECTS AND IS INCLUDED IN THE PROJECTS CONCERNED WITH THE DEVELOPMENT OF NEW VLSI PROCESSES ( SEE AREAS 1.1 AND 1.2 ) ; BUT COMPATABILITY WITH CAD IS REQUIRED .

( D ) CARE SHOULD BE TAKEN TO PROMOTE COOPERATIVE DEVELOPMENT BETWEEN UNIVERSITIES , INDUSTRIAL GROUPS AND RESEARCH INSTITUTIONS IN ORDER TO TRANSFER KNOW-HOW AND MAKE CAD AVAILABLE TO A BROADER COMMUNITY .

( E ) CARE WILL BE TAKEN TO INTERFACE WITH , SUPPORT AND EMPLOY THE RESULTS OF OTHER ESPRIT ACTIVITIES .

( F ) THE APPLICATION OF KNOWLEDGE ENGINEERING TECHNIQUES TO CAD SHOULD BE EMPHASISED .

( G ) DEDICATED CAD HARDWARE SHOULD BE INCORPORATED WHERE APPROPRIATE .

MAJOR PROJECTS TO BE LAUNCHED

WORK IS REQUIRED IMMEDIATELY IN FOUR KEY PROJECT AREAS . THE AIM IS TO SIMULTANEOUSLY DEVELOP TOOLS AND TECHNIQUES WHILE PROMOTING SIGNIFICANT MOVEMENTS TOWARDS THE ADOPTION OF A COMMON FRAMEWORK .

A MAJOR DIFFICULTY ARISES OUT OF THE NEED TO INCORPORATE THE RESULTS OF CURRENT EURO PROJECTS WHICH ARE IN MOST CASES DIFFICULT TO QUANTIFY . THE INTEGRATION PROJECT WILL ADRESS THIS ISSUE AND PROVIDE GUIDELINES FOR FUTURE PROJECTS . NEW PROJECTS MUST DEFINE IN ADVANCE THEIR QUANTIFIED GOALS AND LIMITATIONS IN SUFFICIENT DETAIL TO ALLOW THEM TO BE FULLY EVALUATED .

A FIFTH AREA COVERS SMALLER TYPE B PROJECTS OF A SPECULATIVE AND NOVEL NATURE .

MUCH WORK NEEDS TO BE DONE IN THE CAD AREA . OWING TO THE LIMITED RESOURCES AVAILABLE THE FOLLOWING PROJECTS HAVE BEEN CAREFULLY SELECTED AS THOSE MOST LIKELY TO HAVE A LASTING AND LONG TERM IMPACT ON EUROPEAN EFFECTIVENESS .

PREREQUISITES

- KNOWLEDGE OF THE DESIGN PROCESS

- ACCESS TO RESULTS AND TOOLS DEVELOPED IN CAD AND SPECIFICALLY UNDER MICROELECTRONICS REGULATION 3744/81 AND THE ESPRIT PROJECTS

- EXPERIENCE IN ALGORITHMS USED IN VLSI DESIGN

- TECHNOLOGIES AND DEMONSTRATOR CHIPS IN THE ORDER OF 10 MILLION TRANSISTORS

1.3.1 . CAD INTEGRATION PROJECT ( TYPE A )

THE REQUIREMENT IS FOR A WIDE AND REPRESENTATIVE GROUP OF DESIGN AUTOMATION ( DA ) TOOL DEVELOPERS TO MEET AND JOINTLY RECOMMEND THE MECHANISMS AND FRAMEWORK FOR BETTER INTEGRATION AND WIDER ACCESSIBILITY OF EUROPEAN CAD TOOLS .

THE PROJECT WILL PRODUCE REGULAR STUDY REPORTS AND WILL RELATE ITS FINDINGS TO SOME SPECIFIC PROGRAMMING WORK TO SUPPORT INTEGRATION AND LINKING OF EXISTING AND EURO SUPPORTED TOOLS , AND TO DEFINE A FRAMEWORK OF STANDARDS FOR FUTURE WORK .

THE STUDIES MUST TAKE INTO ACCOUNT WORLDWIDE DEVELOPMENT ( EG ELECTRONIC DESIGN INTERCHANGE FORMAT - EDIF ) IN INFORMATION TECHNOLOGY AND DA SYSTEM ARCHITECTURES .

PHASE 1

YEAR 1 :

PROBLEMS OF BRIDGING EXISTING EURO TOOLS , TECHNIQUES FOR INTEGRATION , IMPACT OF NETWORKS AND DISTRIBUTED DATA .

YEAR 2 :

RECOMMEND DATA AND PORTABILITY STANDARDS , IMPACT OF SPECIAL DA H/W ( HARDWARE ) GUIDELINES FOR DEVELOPERS OF DA TOOLS .

MILESTONES :

A ) INTEGRATION OF TOOLS AND SYSTEMS CURRENTLY UNDER DEVELOPMENT INTO A FIRST GENERATION SYSTEM .

B ) DEFINITION OF FRAMEWORK OF STANDARDS FOR FUTURE WORK .

* A MAJOR REVIEW OF ACHIEVEMENTS AND A REASSESSMENT OF THE BALANCE OF THE WORK TO BE MADE AT THIS TIME .

PHASE 2

YEAR 3 AND YEAR 4 :

EXTENSIONS TO INCORPORATE IMPACT OF NEW DEVELOPMENTS IN DA HARDWARE , ARTIFICIAL INTELLIGENCE AND DATABASE TECHNOLOGY .

YEAR 5 :

COMPLETE THE INTEGRATION OF SECOND GENERATION SYSTEM AND REVIEW EXISTING STANDARDS .

MILESTONES :

A ) INTEGRATION OF ADVANCED TOOLS INTO SECOND GENERATION SYSTEM .

B ) REVIEW OF EXISTING STANDARDS WITH UPDATES WHERE APPROPRIATE .

1.3.2 . USER INTERFACE PROJECT ( TYPE A )

THE OBJECTIVE IS TO PROMOTE MORE EFFECTIVE USE AND CONSISTENCY OF CAD TOOLS FROM THE USER POINT OF VIEW . THE WORK WILL BE A COMBINATION OF A WIDE RANGING STUDY AND THE PRACTICAL ADAPTATION OF SOME EXISTING PROGRAMMES .

YEAR 1 :

ENHANCE THE USER INTERFACE ASPECTS IN THE ONGOING CAD SYSTEM PROJECTS ALONG THE WHOLE DESIGN PROCESS :

IMPORTANT CHARACTERISTICS :

- USER FRIENDLINESS

- QUICK RESPONSE TIME

- PORTABILITY

- CONSISTENCY

YEAR 2 :

INVESTIGATE THE LINKS ON COMMUNICATIONS BETWEEN INTELLIGENT WORK STATIONS AND THE CENTRAL COMPUTING UNITS :

- SPEED OF TRANSMISSION

- PROTOCOL OF TRANSMISSION

- PARTITIONING OF DATA AND PROCESSES BETWEEN WORK STATIONS AND COMPUTERS

YEARS 3 AND 4 :

STUDY OF MAN-MACHINE INTERFACE WITH RESPECT TO CAD - NEW INPUT/OUTPUT TECHNIQUES , FOR INSTANCE VOICE INPUT ( AND SEE ALSO OTHER ESPRIT AREAS ) .

1.3.3 . PROBLEMS OF VERY LARGE SCALE INTEGRATION ( TYPE A )

THE TARGET IS TO DEVELOP NEW ALGORITHMS AND ARCHITECTURES APPROPRIATE FOR VLSI CIRCUITS CONTAINING MILLIONS OF TRANSISTORS . THE FIRST STEP IS TO ESTABLISH A FORMAL UNDERSTANDING OF THE LIMITS OF THE EXISTING ALGORITHMS USED TODAY AT DIFFERENT LEVELS OF THE DESIGN PROCESS .

IT IS KNOWN THAT FOR 90 % OF CAD PROBLEMS AN INCREASE IN COMPLEXITY BEYOND A CERTAIN LIMIT REQUIRES NEW SOLUTIONS AND IT IS CERTAIN THAT IN THE FUTURE A LOT OF DIFFERENT APPROACHES MUST BE APPLIED TO THE ALGORITHMS .

THE PARTICIPANTS SHOULD COMBINE JOINT STUDIES AND QUANTIFIED EVALUATION WITH PRACTICAL WORK ON SPECIFIC TOOLS EMPLOYING EXPERT SYSTEMS AND SPECIAL HARDWARE THAT MAY SUPPORT A RANGE OF DA PROBLEMS .

YEAR 1 :

ESTABLISHMENT OF PERFORMANCE EVALUATION CRITERIA ESPECIALLY WITH REGARD TO :

- LAYOUT GENERATION TOOLS

- FLOOR-PLANNING TOOLS

- FUNCTIONAL DESIGN TOOLS

YEAR 2 :

EXPERIMENT WITH EXISTING TOOLS , AI SYSTEMS AND SPECIAL HARDWARE PROVIDING :

- LIMITS IN TIME-SPACE COMPLEXITY

- PATHOLOGICAL CASES

DEFINITION OF A DEMONSTRATOR SYSTEM IN WHICH TO MAKE COOPERATIVE ALGORITHMIC TASKS WITH AI TECHNIQUES AND ANY NECESSARY SPECIAL PURPOSE HARDWARE .

YEARS 3 AND 4 :

IMPLEMENTATION OF THE SYSTEM AND DEMONSTRATION ON A " DIFFICULT " AND LARGE PROBLEM .

1.3.3.1 . " DESCRIPTION LANGUAGE FOR VLSI " ( REF . 42 : A/83 )

THIS PROJECT WILL PRODUCE TWO NEW HIERARCHICAL IC DESIGN DESCRIPTION LANGUAGES FOR DESCRIBING CIRCUIT NETWORKS AND LAYOUTS . THE MAIN AIM IS TO CREATE A VLSI CAD INFRASTRUCTURE THAT AIDS IN DRAMATICALLY IMPROVING DESIGNER PRODUCTIVITY AND THAT ALLOWS FOR FURTHER DEVELOPMENT .

1.3.3.2 . " ADVANCED ALGORITHMS , ARCHITECTURE AND LAYOUT TECHNIQUES FOR VLSI DEDICATED SIGNAL PROCESSING " ( REF . 97 : A/83 )

THIS PROJECT ADDRESSES THE DEVELOPMENT OF CAD TOOLS AND ADVANCED CMOS CIRCUIT DESIGN TECHNIQUES FOR DIGITAL SIGNAL PROCESSING CHIPS FOR BIT-SERIAL AND MIXED BIT-SERIAL-PARALLEL OR PARALLEL ARCHITECTURES .

1.3.3.3 . " HIGH YIELD HIGH RELIABILITY ULTRA-LARGE SCALE INTEGRATION SYSTEM THROUGH RECONFIGURABILITY " ( REF . 244 : B/84 )

HIGHLY RELIABLE ULSI CAN BE ACHIEVED BY INTRODUCING REDUNDANCY INTO A CHIP SO THAT FAULTY CELLS OR ELEMENTS CAN BE TOLERATED . BUT THIS AREA INCREASE MAY LEAD TO A YIELD DECREASE . THE INTRODUCTION OF REDUNDANCY IS PROPOSED WITH THE OBJECTIVES OF YIELD ENHANCEMENT BY MEANS OF END-OF-MANUFACTURING RECONFIGURATION AND THE FAULT TOLERANCE BY MEANS OF ON-LINE RECONFIGURATION . EXPERTISE IN SILICON YIELD ANALYSIS INVOLVING AN UNDERSTANDING OF FAILURE MECHANISMS AND THEIR DISTRIBUTION , ARCHITECTURAL STRATEGIES FOR PARTITIONING , IMPLEMENTING REDUNDANCY AND MAINTAINING TESTABILITY , SILICON DESIGN METHODOLOGIES ENHANCED TO MEET THE ABOVE REQUIREMENTS , AND SPECIFIC MANUFACTURING TECHNIQUES TO SUPPORT THE REQUIRED PHYSICAL RESTRUCTURING AND ADDRESSING THE SPECIAL REQUIREMENTS IN TESTING AND PACKAGING ARE REQUIRED FOR SUCCESSFUL COMPLETION OF THE PROJECT . THE PROJECT WILL TERMINATE IN A DEMONSTRATION CHIP AND THE TECHNOLOGY SUPPORTED WILL BE STATE OF THE ART CMOS WITH ADEQUATE MULTILAYER INTERCONNECTIONS .

ADDITIONAL TYPE A PROPOSALS ARE INVITED .

1.3.4 . HIGH LEVEL DESIGN TOOLS ( TYPE A )

THE REQUIREMENT IS TO DEVELOP A SET OF INTEGRATED DESIGN TOOLS FOR HIGH-LEVEL DESIGN ( SPECIFICATION , SYNTHESIS AND VERIFICATION ) WITH A HIGH DEGREE OF TECHNOLOGY INDEPENDENCE . THESE TARGET DESIGNS ARE OF THE SCALE OF TEN MILLION COMPONENTS PER CHIP WHICH MAY CONTAIN BOTH MEMORY AND LOGIC . THE TOOLS SHOULD ASSIST THE DESIGNER IN PARTITIONING A SYSTEM INTO SUB-SYSTEMS , AND IN ALLOCATING THE FUNCTIONS FOR IMPLEMENTATION IN HARDWARE OR SOFTWARE . IMPLEMENTATION DETAILS SUCH AS TESTABILITY AND LAYOUT MUST BE ADDRESSED . THE PROBLEMS OF MIXED ANALOGUE DIGITAL DESIGNS SHOULD ALSO BE ADDRESSED .

YEAR 1 : DESIGN OVERALL TOOL SET

YEAR 2 : START IMPLEMENTATION OF TOOL SET

YEAR 3 : COMPLETE IMPLEMENTATION OF TOOL SET

YEAR 4 : TEST AND DEMONSTRATE TOOL SET ON MULTIPLE CHIP SUB-SYSTEMS WITH LOGIC , MEMORY AND ANALOGUE FUNCTIONS .

1.3.4.1 . " HIGH LEVEL CAD DESIGN SYSTEMS FOR INTERACTIVE LAYOUT AND DESIGN " ( REF . 10 : A/83 )

THE OBJECTIVE OF THIS PROJECT IS TO DEFINE AND DEMONSTRATE THE CAD SYSTEM FOR THE DESIGN AND LAYOUT OF VLSI INTEGRATED CIRCUITS , FROM THE INITIAL SPECIFICATION TO THE MASKS . CIRCUIT COMPLEXITY UP TO 1 000 000 TRANSISTORS WILL BE ADDRESSED . REDUCED DESIGN TIMES ARE THE OVERALL AIM .

ADDITIONAL TYPE A PROPOSALS ARE INVITED .

1.3.5 . SPECIFIC NOVEL DESIGN TOOLS ( TYPE B )

A NUMBER OF SMALL AND HIGHLY INNOVATIVE PROJECTS WILL BE SUPPORTED . THERE IS A VERY WIDE RANGE OF POSSIBLE TOPICS COVERING THE DESIGN OF LARGE SCALE VLSI CIRCUITS .

IN PARTICULAR , PROJECTS THAT ADDRESS DESIGN PROBLEMS IN THE FOLLOWING AREAS ARE INVITED :

- VERY HIGH SPEED VLSI CIRCUITS ( E . G . 50 PICO SECONDS )

- WAFER SCALE INTEGRATION

- FAULT TOLERANCE FOR HIGH YIELD

- PARALLEL ARCHITECTURES ( E . G . SYSTOLIC ARRAYS )

- SPECIFIC TECHNOLOGIES ( E . G . GAAS )

- SPECIAL PURPOSE HARDWARE FOR CAD .

1.3.6 . DESIGN AND CHARACTERISATION OF CELLS ( TYPE A )

THE OBJECTIVE IS TO PROVIDE CELLS WHICH CAN BE USED TO EVALUATE THE SILICON TECHNOLOGIES AND THE CAD TOOLS DEVELOPED UNDER ESPRIT IN THE CONTEXT OF WORKING CIRCUITS . IT IS NOT INTENDED TO PROVIDE AN EXHAUSTIVE LIBRARY OF CELLS BUT TO DEVELOP A PROVEN METHODOLOGY FOR THE RAPID DESIGN AND CHARACTERISATION OF CELLS . ONE ESSENTIAL INPUT IS DEVICE MODELLING INFORMATION FROM THE PROCESS RESEARCH PROJECTS .

THREE CATEGORIES OF CELLS ARE INCLUDED :

1 . PRIMITIVE CELLS

2 . PARAMETERISED CELLS

3 . FIXED CELLS

TO INCLUDE BOTH ANALOGUE AND DIGITAL FUNCTIONS .

FOR EACH CELL THERE SHOULD BE DESCRIPTIONS AT THE LAYOUT , FUNCTIONAL AND ELECTRICAL LEVEL , WITH COMPLETE INFORMATION FOR SIMULATION AND PARAMETER EXTRACTION . THE INTENTION IS TO PROVIDE A MINIMAL RANGE OF CELLS FOR EACH OF THE TECHNOLOGIES . EACH CELL WILL BE FULLY SIMULATED AND CHARACTERISED .

YEAR 1 :

SELECT PROVISIONAL STANDARDS AND DEVELOP BASIC CELL DESIGN METHODOLOGY .

YEAR 2 :

DEVELOP PRIMITIVE CELL LIBRARY AND TECHNIQUES FOR PARAMETERISATION .

YEAR 3 :

DESIGN PARAMETERISED AND FIXED CELLS .

YEAR 4 :

CHARACTERISATION AND DEMONSTRATION IN REPRESENTATIVE CIRCUITS .

NOTE : DURING THE COURSE OF THE PROJECT APPROPRIATE STANDARDS WILL BE IMPLEMENTED AS SOON AS THEY BECOME AVAILABLE .

R AND D AREA 1.4 : COMPOUND SEMICONDUCTOR INTEGRATED CIRCUITS

DESCRIPTION

INTEGRATED DIGITAL CIRCUITS IN III-V COMPOUND SEMICONDUCTOR MATERIALS OFFER POTENTIAL SPEED AND/OR SPEED POWER PRODUCT ADVANTAGES OVER SILICON CIRCUITS BECAUSE OF HIGHER ELECTRON MOBILITY . TECHNOLOGY COMPLEXITY IS MANY YEARS BEHIND SILICON AND CONSIDERABLE MATERIALS AND PROCESS RESEARCH ARE NECESSARY . BECAUSE OF THE INCREASING MARKET FOR HIGH-SPEED , LOW-POWER CIRCUITS MANY PROBLEMS NEED TO BE TACKLED .

THE TECHNOLOGY ENCOMPASSES GAAS CIRCUITS BASED ON FIELD EFFECT TRANSISTORS ( FET'S ) AS WELL AS GAAS/GAALAS HETEROJUNCTION STRUCTURES USING HIGH ELECTRON MOBILITY TRANSISTORS ( HEMT ) OR THE HETEROJUNCTION BIPOLAR TRANSISTORS ( HJBT'S ) . BASIC RESEARCH IS REQUIRED IN MATERIALS PREPARATION , ION IMPLANTATION , AND IC PROCESS TECHNOLOGIES .

REMARK : THE ACHIEVEMENT OF THE OBJECTIVES OF THIS PROGRAMME NEEDS VERY LARGE RESOURCES WHICH MAY NOT BE AVAILABLE WITHIN THE FRAMEWORK OF ESPRIT . ON THE OTHER HAND THESE OBJECTIVES REPRESENT A MINIMUM TARGET TO REMAIN COMPETITIVE . CONSEQUENTLY COMPLEMENTARY FUNDING MECHANISMS AND/OR LESS AMBITIOUS PROGRAMMES HAVE TO BE ACCEPTED .

PREREQUISITES

- SOURCE OF SUITABLE SUBSTRATE MATERIALS ;

- CAD FACILITIES ;

- SUITABLE LABORATORY AND EXPERIENCED TEAM ;

- CAPABILITY FOR ION IMPLANTATION ;

- AND/OR MOLECULAR BEAM EPITAXY ( MBE ) ;

- AND/OR METAL ORGANIC CHEMICAL VAPOUR DEPOSITION ( MOCVD ) EPITAXIAL GROWTH ;

PROGRAMME ( - ) AND INTERMEDIATE OBJECTIVES ( * ) :

YEAR 1 :

- MAIN EMPHASIS ON DEVELOPMENT OF GAAS IC FABRICATION PROCESS ON 2" WAFERS ARRIVING AT SUBMICRON FEATURES WITH SPECIAL CONCERN FOR REPRODUCIBILITY AND YIELD .

- OPTIMIZE MATERIALS GROWTH AND FABRICATE EXPERIMENTAL HEMT'S AND HJBT'S IN THE GAAS/GAALAS SYSTEM .

* 12TH MONTH : DEMONSTRATE FEASIBILITY OF MESFET BASED CIRCUITS WITH 1 000 GATES AND GATE DELAY ( TPD ) OF LESS THAN 100 PS .

- DEMONSTRATE BASIC HJBT AND/OR HEMT CIRCUITS ( OTHER THAN RING OSCILLATORS ) .

YEAR 2 :

- CONTINUE WORK WITH MAIN EMPHASIS ON GAAS IC FABRICATION PROCESS INVOLVING SUBMICRON FEATURES WITH SPECIAL CONCERN FOR REPRODUCEABILITY AND YIELD . ESTABLISH 3" PROCESS CAPABILITY .

- CONTINUE RESEARCH INTO OPTIMIZATION OF HEMT AND/OR HJBT IC'S ;

* 24TH MONTH : DEMONSTRATE AT LEAST 1 K MEMORY ( LESS THAN 1 NS ACCESS TIME , LESS THAN 500 M W DISSIPATION ) AND/OR EQUIVALENT COMPLEXITY CIRCUITS .

DEMONSTRATE FEASIBILITY OF 100 GATES HEMT AND/OR HJBT CIRCUITS .

YEAR 3 :

- CARRY OUT YIELD AND RELIABILITY IMPROVEMENT EXERCISE ON BASIC GAAS IC PROCESS ;

- IMPROVE BASIC PROCESS STEPS FOR A GAAS/GAALAS IC PROCESS BASED ON THE HEMT OR BIPOLAR TRANSISTOR .

- DETERMINE APPLICABILITY OF HJBT/HEMT FOR DIGITAL IC EG FOR A FAST 8-BIT PROCESSOR ;

* 36TH MONTH : EVALUATE YIELD ON A DEMONSTRATOR CIRCUIT OF 1 K OR EQUIVALENT COMPLEXITY , ON AT LEAST 10 WAFERS .

DEMONSTRATE FEASIBILITY OF 1 K HEMT MEMORY AND/OR COMPARABLE HJBT CIRCUIT .

COMPARISON OF VARIOUS TECHNOLOGIES ( IF POSSIBLE WITH THE SAME CIRCUIT FOR EACH TECHNOLOGY ) . DECISION FOR SELECTING ONE OUT OF THEM .

YEAR 4 :

- IMPROVE AND CONSOLIDATE THE SELECTED PROCESS ;

- FABRICATE EXPERIMENTAL ICS AND IMPROVE YIELD ;

- DEVELOP CIRCUITS FOR FAST 8-BIT PROCESSOR .

* 48TH MONTH : DEMONSTRATE 16 K MEMORY ( OR EQUIVALENT ) IN THE SELECTED TECHNOLOGY .

YEAR 5 :

- INCREASE COMPLEXITY ;

- DESIGN AND FABRICATE OTHER COMPLEX STATE-OF-THE-ART IC'S .

* 60TH MONTH : DEMONSTRATE LARGE CIRCUIT OF 10 TO 20 KGATES COMPLEXITY , GATE DELAY OF LESS THAN 50 PS WITH FIGURE OF MERIT LESS THAN 100 FEMTOJOULES . THIS DEMONSTRATOR COULD BE A 16 KMEMORY WITH AN ACCESS TIME IN THE ORDER OF FEW NANOSECONDS OR IT COULD BE DEFINED DURING YEAR 3 TO FULFILL NEEDS OF OTHER ESPRIT AREAS ( SPECIALLY HIGH SPEED DATA BUS ) OR OF TELECOMMUNICATION INDUSTRY ( SIGNAL PROCESSING CIRCUITS FOR INSTANCE ) .

1.4.1 . " COMPOUND SEMICONDUCTOR MATERIALS AND INTEGRATED CIRCUITS - I " ( REF . 232 : A/84 )

THE OVERALL OBJECTIVE OF THIS PROGRAMME IS TO ESTABLISH GALLIUM ARSENIDE DIGITAL INTEGRATED CIRCUIT TECHNOLOGIES USING THE GAAS MESFET , HIGH ELECTRON MOBILITY TRANSISTORS ( HEMT/TEGFET ) AND HETEROJUNCTION BIPOLAR TRANSISTORS ( HBT ) AS THE ACTIVE CIRCUIT ELEMENTS . THESE CIRCUITS WILL BE CONFIGURED TO ENABLE THE SPEED AND POWER ADVANTAGES OF GAAS OVER SILICON TO BE SUITABLY DEMONSTRATED .

1.4.2 . " COMPOUND SEMICONDUCTOR MATERIALS AND INTEGRATED CIRCUITS - II " ( REF . 522 : A/84 )

THE GENERAL OBJECTIVE OF THE RESEARCH PROGRAMME IS TO DEVELOP ADVANCED ASPECTS OF GAAS DIGITAL INTEGRATED CIRCUIT PROCESS TECHNOLOGY AND ASSOCIATED EXPERTISE TO ENABLE THE FABRICATION OF FAST , HIGH PERFORMANCE DIGITAL CIRCUITS . WHOLE IC FABRICATION IS NOT CONSIDERED TO BE PRE-COMPETITIVE . DEMONSTRATOR DIGITAL IC'S WILL BE DEVELOPED TO EVALUATE THE PERFORMANCE OF THE VARIOUS LOGIC CIRCUIT TECHNOLOGIES .

1.4.3 . " CAD METHODS FOR ANALOG GAAS MONOLITHIC IC'S ( REF . 255 : B/84 )

THE MAJOR EMPHASIS OF THE RESEARCH PROGRAMME IS THE DEVELOPMENT OF A FULL CAD LIBRARY OF THEORETICAL MODELS AND EXPERIMENTAL DATA FOR PASSIVE ELEMENTS AND ACTIVE COMPONENTS REQUIRED FOR THE DESIGN OF GAAS ANALOG IC'S . THE WORK STARTS BY DERIVING PHYSICAL MODELS AND EQUIVALENT CIRCUITS FOR DIFFERENT TYPES OF MESFET AND PASSIVE ELEMENTS BOTH FOR LUMPED AND DISTRIBUTED APPROACHES . THE NEXT STEP IS CAD OF GROUPS OF PASSIVE AND ACTIVE DEVICES FOR THE INTEGRATED IMPLEMENTATION OF ELEMENTARY FUNCTIONS . HERE BESIDES CIRCUIT ANALYSIS , COUPLING BETWEEN ADJACENT ELEMENTS AND THERMAL DISTRIBUTION WILL ALSO BE SIMULATED . IN THE SUCCESSIVE PHASE , ANALOG IC'S DEFINED AS HIGH LEVEL FUNCTIONAL BLOCKS HAVE TO BE CONSIDERED WITH SPECIAL ANALYSIS PROGRAMS . THIS FINAL CAD PROGRAM INCLUDES PACKAGE EFFECT EVALUATION AND ERROR SENSITIVITY ANALYSIS . INTERACTIVE OPTIMISATION WILL BE ORGANISED IN A USER-ORIENTED , TRANSFERABLE PACKAGE . THE PROJECT STARTS WITH C AND X BAND INVESTIGATION TO BE EXTENDED TO 18 GHZ . THE CAD CAPABILITY WILL BE PROOFED WITH DIFFERENT GAAS IC DEMONSTRATORS , INCLUDING SUBMICRON DIMENSION DEVICES .

ADDITIONAL TYPE A AND B PROPOSALS ARE INVITED .

R AND D AREA 1.5 : OPTOELECTRONICS

DESCRIPTION

OPTOELECTRONIC DEVICES WILL BE INCREASINGLY REQUIRED FOR TELECOMS TRANSMISSION , INTRA - AND EXTRA-COMPUTER CONNECTIONS , ULTRA WIDE BAND IMAGE PROCESSING AND SWITCHING . FUTURE GENERATIONS OF MONO-MODE COMMUNICATIONS SYSTEMS MAY USE COHERENT DETECTION AND MULTI-CHANNEL WAVELENGTH MULTIPLEXING AND MAY BE PHASE MODULATED . THIS WILL PROVIDE IMPROVED PERFORMANCE AND BE COMPATIBLE WITH INTEGRATED OPTICAL LOGIC . IT WILL ALLOW PROCESSING , COMBINING AND ROUTING AT VERY HIGH SPEEDS . IN SEMICONDUCTOR FORM IT WILL ALSO BE COMPATIBLE WITH III-V INTEGRATED CIRCUITS PROVIDING A FAST ELECTRICAL INTERFACE .

REMARK : THE ACHIEVEMENT OF THE OBJECTIVES OF THIS PROGRAMME NEEDS VERY LARGE RESOURCES WHICH MAY NOT BE AVAILABLE WITHIN THE FRAMEWORK OF ESPRIT . ON THE OTHER HAND THESE OBJECTIVES REPRESENT A MINIMUM TARGET TO REMAIN COMPETITIVE . CONSEQUENTLY COMPLEMENTARY FUNDING MECHANISMS AND/OR LESS AMBITIOUS PROGRAMMES HAVE TO BE ACCEPTED .

PREREQUISITE

- SOURCE OF SUITABLE SUBSTRATE MATERIALS ;

- SUITABLE LABORATORY AND EXPERIENCED TEAM ;

- CAPABILITY IN EPITAXIAL GROWTH .

THIS PROGRAMME IS NOT AIMED AT OPTICS BASED COMPUTERS BUT RATHER AT PROVIDING COMPONENTS AND SUBSYSTEMS FOR LARGE BIT RATE TRANSMISSIONS . THE TWO APPROACHES ARE :

A ) INTEGRATED ELECTRONIC AND OPTICAL COMPONENTS ON THE SAME CHIP :

PROGRAMME ( - ) AND INTERMEDIATE OBJECTIVES ( * ) :

YEAR 1 :

- OPTIMIZE MATERIALS GROWTH AND LAYER STRUCTURES ;

- INTEGRATE A PHOTODETECTOR WITH A FRONT-END AMPLIFYING COMPONENT ;

- WORK ON LASER DRIVERS IN INP BASED MATERIALS ;

- WORK ON THE DEVELOPMENT OF AN INP BASED IC TECHNOLOGY , COMPATIBLE WITH ITS OPTOELECTRONICS .

* 12TH MONTH : DEMONSTRATE A MONOLITHIC PHOTODETECTOR WITH INTERNAL AMPLIFICATION .

YEAR 2 :

- COMPARE ( BOTH EXPERIMENTALLY AND BY MODELLING ) HYBRID AND MONOLITHIC INTEGRATION FOR RECEIVER MODULE ;

- CONTINUE TO DEVELOP THE INP BASED IC TECHNOLOGY ;

- DEVELOP ISOLATION AND INTERCONNECTION TECHNIQUES ON INP BASED MATERIALS .

* 24TH MONTH : DEMONSTRATE A MONOLITHICALLY INTEGRATED RECEIVER WITH BANDWIDTH GREATER THAN OR EQUAL TO 2.5 GHZ .

YEAR 3 :

- COMPARE HYBRID AND MONOLITHIC INTEGRATION OF TRANSMITTER MODULE ;

- FABRICATE AN INTEGRATED TRANSMITTER .

* 36TH MONTH : DEMONSTRATE AN INTEGRATED TRANSMITTER WITH A BANDWIDTH GREATER THAN 2.5 GHZ .

AFTER YEAR 3 , FURTHER OPTIMISATIONS OF RECEIVER , TRANSMITTER , AND PERHAPS ALSO REPEATERS HAVE TO TAKE INTO ACCOUNT THE PROGRESS AND NEEDS OF THE TELECOMMUNICATIONS INDUSTRY AND OF THE OTHER ESPRIT AREAS .

B ) WAVELENGTH MULTIPLEXING ( WDM ) WITH INTEGRATED OPTICS :

PROGRAMME ( - ) AND INTERMEDIATE OBJECTIVES ( * ) :

YEAR 1 :

- OPTIMIZATION OF EXPITAXIAL GROWTH FOR LASERS , DETECTORS AND WAVEGUIDES ;

- EVALUATE ELECTRON-BEAM AND HOLOGRAPHIC PRODUCED GRATINGS ;

- DEMONSTRATE DISTRIBUTED FEEDBACK ( DFB ) LASER .

* 12TH MONTH : DEMONSTRATION OF DFB LASER WITH THRESHOLD CURRENT LOWER THAN 50 MA ; DEMONSTRATION OF WAVEGUIDE FED PHOTODETECTOR ; LOW LOSS MONOLITHIC WAVEGUIDE ( SMALLER THAN 1 DB/CM ) .

YEAR 2 :

- OPTIMIZE DFB LASER FOR DIRECT MODULATION AT HIGH FREQUENCY ;

- FABRICATE 2 BURIED HETEROSTRUCTURE ( BH ) LASERS AT DIFFERENT WAVELENGTH ON THE SAME CHIP ;

* 24TH MONTH : DEMONSTRATION OF 2.5 GHZ BANDWIDTH MODULATORS IN SEMICONDUCTORS .

YEAR 3 :

- MONOLITHIC INTEGRATION OF 2 DFB LASERS EMITTING AT TWO DIFFERENT WAVELENGTHS :

- OPTIMIZATION OF EXTERNAL MODULATORS ON SEMICONDUCTORS MATERIALS ;

- FABRICATE DEMULTIPLEXING DETECTORS ;

* 36TH MONTH : DEMONSTRATE AN INTEGRATED TRANSMITTER WITH A BANDWIDTH GREATER THAN 2.5 GHZ .

YEAR 4 :

- INTEGRATION OF 2 DFB LASERS TOGETHER WITH AN OPTICAL MULTIPLEXER ;

- IMPROVE DEMULTIPLEXING PHOTODIODE .

* 48TH MONTH : DEMONSTRATE INTEGRATED WDM TRANSMITTER AND RECEIVER MODULES .

AT THIS POINT , SOME INPUTS FROM OTHER ESPRIT AREAS AND TELECOMMUNICATIONS INDUSTRY ARE NEEDED TO IMPLEMENT A DEMONSTRATION LINK AT A SEVERAL GIGABIT RATE .

1.5.1 . " INTEGRATED OPTOELECTRONIC DEVICES FOR VERY HIGH BIT RATE OPTICAL FIBRE TRANSMISSION SYSTEMS " ( REF . 263 : A/84 )

THE GENERAL OBJECTIVE OF THE RESEARCH PROGRAMME IS TO SIGNIFICANTLY INCREASE THE DATA RATE IN INFORMATION TRANSMISSION SYSTEMS , BY THE USE OF HIGH PERFORMANCE DEVICES AND WITH A VARIETY OF MULTIPLEXING TECHNIQUES , MAINLY WITH THE USE OF DIFFERENT WAVELENGTHS . IN THE FIRST THREE YEARS , ACTIVITY WILL BE FOCUSSED ON ACHIEVING AND UTILISING SINGLE MODE DISCRETE FUNCTIONS SUITABLE FOR SUBSEQUENT HYBRID AND MONOLITHIC INTEGRATION . FULL HYBRID INTEGRATION WILL BE WORKED ON IN YEAR THREE AND FOUR . THE WORK ON THESE MATERIALS WILL BE ORIENTED TOWARDS REPRODUCIBLE GROWTH OF HIGH QUALITY , HIGH HOMOGENEITY , LARGE AREA HETEROSTRUCTURES SUITABLE FOR LASERS WITH LOW THRESHOLD CURRENT DENSITY AND WELL CONTROLLED WAVELENGTH , FOR PHOTODETECTORS WITH LOW RESIDUAL DOPING LEVEL AND FOR WAVEGUIDES WITH LOW LOSSES .

1.5.2 . " TECHNOLOGY FOR INP BASED INTEGRATED OPTOELECTRONIC CIRCUITS " ( REF . 546 : A/84 )

THIS PROGRAMME IS AIMED AT THE DEVELOPMENT OF THE TECHNOLOGY NEEDED FOR THE FABRICATION OF THE ELECTRONIC DEVICES IN A FORM WHICH CAN BE INTEGRATED WITH THE OPTICAL DEVICES . A RANGE OF DEVICES WILL BE INVESTIGATED AND COMPARED FOR USE IN A RANGE OF FUNCTIONS . AS A RESULT OF THE IMPORTANCE OF LONGER WAVELENGTH OPERATION ALL THE WORK WILL BE ON INP-BASED SEMICONDUCTOR COMPOUNDS . A VERY IMPORTANT POTENTIAL BENEFIT OF THE PROGRAMME IS THAT THE MATERIALS TO BE STUDIED ARE EXPECTED TO HAVE VERY HIGH PERFORMANCE IN CONVENTIONAL ELECTRONIC CIRCUITS . THUS THE PROGRAMME MAY LEAD TO IMPROVED ELECTRONIC FUNCTIONS AS WELL AS SOPHISTICATED OPTO-ELECTRONIC CIRCUITS .

1.5.3 . " OPTICAL INTERCONNECT FOR VLSI AND HIGH BIT RATE IC'S " ( REF . 380 : B/84 )

THIS SPECULATIVE RESEARCH PROGRAMME IS UNDERTAKEN TO INVESTIGATE THE APPLICATION OF OPTICAL INTERCONNECTION TO REDUCE THE PACKAGE PIN COUNT AND ELECTRO MAGNETIC INTERFERENCE IN VLSI AND HIGH SPEED INTEGRATED CIRCUITS AND IN SUB-ASSEMBLIES CONTAINING THESE COMPONENTS . THE COMPLETE PROGRAMME HAS A FOUR YEAR DURATION . DURING THE FIRST YEAR DESIGN AND STUDY WORK WILL BE UNDERTAKEN . ACTIVITY LEVELS WILL BE HIGHER IN THE SECOND AND THIRD YEARS DURING WHICH THE MAIN EXPERIMENTAL WORK WILL BE UNDERTAKEN . IN THE FINAL YEAR , DEMONSTRATION DEVICES WILL BE COMPLETED , DESIGN AND PERFORMANCE PREDICTIONS FINALISED , AND SPECIFIC APPLICATIONS EXPLORED .

1.5.4 . " MOLECULAR ENGINEERING FOR OPTOELECTRONICS " ( REF . 443 : B/84 )

THE AIM OF THE PROJECT IS THE DEVELOPMENT OF NEW ORGANIC ELECTRO-OPTIC AND NONLINEAR OPTICAL MATERIALS . THERE IS AN INCREASING REQUIREMENT FOR SUCH MATERIALS IN THE RAPIDLY EXPANDING FIELDS OF INTEGRATED OPTICS AND OPTICAL COMMUNICATIONS . THE TARGET OF THE PROJECT IS TO PRODUCE NOVEL MATERIALS FOR THE FABRICATION OF DEVICES UTILISING LINEAR ELECTRO-OPTICAL EFFECTS , SECONDORDER FREQUENCY MIXING EFFECTS AND THIRD-ORDER EFFECTS .

FURTHER A-TYPE ( AND B-TYPE ) PROPOSALS ARE EXPECTED .

R AND D AREA 1.6 : ADVANCED DISPLAY TECHNOLOGIES

IN MANY PRODUCT AREAS EG WORKSTATIONS , ELECTRONIC OFFICE EQUIPMENT ETC . THERE IS A NEED FOR NEW ADVANCED DISPLAY SYSTEMS TO REPLACE AND SUPERSEDE THE CONVENTIONAL CRT . SUCH DISPLAYS WOULD NEED TO BE OF LARGE SIZE ( A4 AND ABOVE ) AND OF MEDIUM TO HIGH DEFINITION . COLOUR CAPABILITY WOULD ALSO BE DESIREABLE/NECESSARY .

MANY APPROACHES ARE CURRENTLY BEING INVESTIGATED . THE PROBLEMS OF MULTIPLEXING , DEFECT MINIMISATION , MATERIALS , ETC . BECOME GREATER WITH INCREASING DISPLAY SIZE AND DEFINITION . A CLEAR IDENTIFICATION OF THE SPECIFIC PROBLEM ISSUES AND A DEFINITION OF THE OPTIMUM TECHNOLOGICAL STRATEGY FOR EUROPE TO MAKE AN IMPACT IN THIS AREA IS REQUIRED . SUCH AN INITIATIVE MUST LINK CLOSELY WITH NATIONAL ACTIVITIES IN THIS AREA .

A TECHNOLOGY DEFINITION PROJECT IN WHICH MAJOR EXISTING COMMUNITY PRACTITIONERS WOULD COMBINE THEIR KNOWLEDGE AND EXPERIENCE IS PROPOSED . THIS PROJECT WOULD BE OF 12 TO 18 MONTHS DURATION AND WOULD PREPARE THE WAY FOR A SIGNIFICANT CO-ORDINATED EUROPEAN APPROACH IN THIS AREA . THE EXPECTED RESULTS IN THIS PROJECT WOULD BE REFLECTED IN A STUDY REPORT TO BE COMPLETED BETWEEN MONTHS 12 AND 14 WHOSE RECOMMENDATIONS WOULD BE SUPPORTED BY ONE OR MORE DEMONSTRATORS TO BE COMPLETED BY MONTH 18 .

1.6.1 . " MATERIALS AND TECHNOLOGIES FOR HIGH MOBILITY TFTS FOR LC DISPLAY BUS DRIVERS " ( REF . 491 : B/84 )

IN CURRENT PRACTICE , THE PERIPHERAL DRIVER CIRCUITS FOR ACTIVE MATRIX LIQUID CRYSTAL DISPLAYS CONSIST OF EXTERNAL IC-CHIPS . THIS PROJECT PROPOSES TO DEVELOP THIN FILM MATERIALS AND TECHNOLOGIES FOR COLUMN - AND LINE-BUS DRIVERS TO REPLACE THE EXTERNAL IC-CHIPS . THE MAIN TASK WILL BE TO DEVELOP A LOW TEMPERATURE DEPOSITION PROCESS FOR THE SEMICONDUCTOR THIN FILM MATERIAL COMPATIBLE WITH THE GLASS SUBSTRATES USED FOR THE LC-DISPLAY . THE MAIN MATERIAL SUGGESTED IS POLYCRYSTALLINE SILICON , DEPOSITED IN A HIGH POWER GLOW DISCHARGE PROCESS . FURTHERMORE ELEMENTARY THIN FILM TRANSISTOR ( TFT ) CIRCUITS SUITABLE FOR BUS DRIVER SHIFT REGISTERS WILL BE DEVELOPED AND INVESTIGATED AND DRIVER PROTOTYPES OF SHORT LENGTH SHALL BE COMBINED WITH LC-MATRIX DISPLAY AND TESTED .

PROPOSALS ARE INVITED IN AREA 1.6 AS OUTLINED ABOVE .

1.7 . - ( NUMBER NOT USED )

R AND D AREA 1.8 : GENERAL TYPE B RESEARCH THEMES

THIS AREA COVERS B-TYPE RESEARCH THEMES NOT ALREADY IDENTIFIED IN THE MICROELECTRONICS AREAS 1.1 TO 1.6 . THESE THEMES MUST OF COURSE BE RELEVANT TO THE OBJECTIVES OF THE MICROELECTRONICS SUBPROGRAMME , AND HAVE A HIGH INTRINSIC VALUE IN THEMSELVES .

NOTE : SINCE THIS RESEARCH AREA IS VERY WIDE RANGING IN ITS SCOPE NO DETAILED PROGRAMME WILL BE GIVEN IN THIS DOCUMENT . IN EACH CASE , HOWEVER , TYPE B PROPOSALS WILL BE EXPECTED TO PROVIDE CLOSELY MEASUREABLE YEARLY TARGETS AGAINST WHICH PROGRESS CAN BE MEASURED .

1.8.1 . " INVESTIGATION OF ALL ASPECTS OF THE INTERCONNECTION OF HIGH PIN COUNT INTEGRATED CIRCUITS " ( REF . 199 - 544 : B/83-84 )

THIS PROJECT HAS THE FOLLOWING AIMS :

1 . THE DEVELOPMENT OF ALTERNATIVE METHODS OF CONNECTING THE INTEGRATED CIRCUIT TO ITS INTERCONNECT MEDIUM .

2 . THE DEVELOPMENT OF LARGE AREA HIGH DENSITY INTERCONNECT USING MULTILAYER POLYMER TECHNIQUES .

3 . THE DEVELOPMENT OF REASONABLY LARGE AREA ULTRA HIGH DENSITY INTERCONNECT BASED UPON A COMBINATION OF THICK FILM DIELECTRICS AND ADDITIVE BASE METAL ELECTROPLATING METHODS .

IT IS THE AIM TO REALISE ALL INTERCONNECT SYSTEMS WITH JUST TWO LAYERS , THEREBY ACHIEVING LOW COST THROUGH REDUCED HANDLING AND INEXPENSIVE MATERIALS . ALL PARTS OF THE PROJECT ARE DESIGNED TO MAKE OPTIMUM USE OF THE PACKAGES BEING DEVELOPED ON THE COMPLEMENTARY PROGRAMME 1.9.1 .

1.8.2 . " PLASMA DEPOSITION TECHNOLOGY FOR MAGNETIC RECORDING THIN FILM MEDIA " ( REF . 334 : B/84 )

THE OBJECTIVE OF THE PROJECT IS TO DEVELOP DEPOSITION TECHNOLOGIES WHICH COMBINE THE SUPERIOR TECHNICAL QUALITIES OF THE THIN FILM MEDIA WITH THE HIGH DEPOSITION RATES REQUIRED FOR INDUSTRIAL PRODUCTION . THE GOAL OF THE PROJECT IS TO INCREASE THE THIN FILM DEPOSITION RATE BY A SIGNIFICANT FACTOR .

ADDITIONAL B-TYPE RESEARCH THEMES ARE INVITED . A NON EXCLUSIVE LIST OF CANDIDATE TOPICS FOR SUCH PROPOSALS INCLUDE :

- ADVANCED PHYSICAL ANALYSIS TECHNIQUES

- SENSORS AND TRANSDUCERS

- NEW TECHNOLOGIES AND TECHNIQUES FOR ADVANCED INFORMATION STORAGE

- NEW INORGANIC AND ORGANIC MATERIALS .

R AND D AREA 1.9 : PROJECTS IN SUPPORT OF MORE THAN ONE MICROELECTRONIC AREA

DESCRIPTION

THIS AREA COVERS ALL THOSE PROJECTS ( A - OR B-TYPE ) WHICH SUPPORT MORE THAN ONE OF THE MAJOR AREA 1.1 TO 1.6 . SUCH PROJECTS CANNOT BE ASSIGNED TO A SPECIFIC AREA BUT , UNLIKE AREA 1.8 , THEY ARE DIRECTLY CONNECTED TO THE MAIN THRUSTS OF THE SUBPROGRAMME .

ALSO THIS AREA REPRESENTS A SIGNIFICANT THRUST TO DEVELOP THE TECHNOLOGIES AND THE TECHNIQUES REQUIRED TO HELP ACHIEVE THE MAJOR GOALS OF THESE AREAS 1.1 TO 1.6 , AND TO LOOK FORWARD BEYOND THE EARLY STAGES OF THESE PROJECTS TO THE SUB-MICRON FINAL GOALS .

1.9.1 . " ADVANCED INTERCONNECT FOR VLSI " ( REF . 14 : B/83 )

THIS PROJECT RELATES TO THE ON-SILICON INTERCONNECT PROBLEM . IT WILL DEAL WITH MULTILAYER AND SUBMICRON GEOMETRIES AND WILL ADDRESS THE RELEVANT MATERIALS TECHNOLOGY AND OTHER RELATED PROBLEMS . RELIABILITY , LIFETEST AND YIELD PROGRAMMES WILL FORM AN INTEGRAL PART OF THE PROJECT . ( OFF-CHIP INTERCONNECT IS THE SUBJECT OF PROJECT 1.8.1 ) .

1.9.2 . " AUTOMATIC DESIGN VALIDATION OF INTEGRATED CIRCUITS USING E-BEAM ( REF . 271 : B/84 )

THE PROJECT SEEKS TO DEVELOP A METHODOLOGY FOR THE AUTOMATIC DESIGN ERRORS DIAGNOSIS OF VLSI DEVICES BASED ON THE OBSERVABILITY FACILITY GIVEN BY AN ELECTRON BEAM SYSTEM , CONNECTION TO THE CAD ENVIRONMENT , PATTERN RECOGNITION TO AUTOMATICALLY POSITION THE E-BEAM , GLOBAL METHODOLOGY , POSSIBLY BASED ON EXPERT SYSTEMS TO DEFINE THE DIAGNOSTIC STRATEGY , NEW HARDWARE CIRCUITRY TO ENHANCE THE EBT PERFORMANCE . THE AREAS OF COMPUTER CONTROL OF THE ELECTRON BEAM SYSTEM , INTERFACING TO CAD SOFTWARE , IDENTIFICATION OF CIRCUIT ELEMENTS , METHODOLOGY FOR DESIGN ERROR DIAGNOSIS , TEST PATTERN GENERATION FOR ELECTRON BEAM DEBUGGING , DESIGN FOR ELECTRON BEAM TESTABILITY , AND ELECTRON BEAM EQUIPMENT DEVELOPMENT , WILL BE ADDRESSED IN ORDER TO ACHIEVE THIS OVERALL OBJECTIVE .

1.9.3 . " ASSESSMENT OF SILICON MBE LAYERS " ( REF . 305 : B/84 )

THIS PROJECT IS DIVIDED INTO THREE PARTS :

1 . GROWTH OF SILICON LAYERS BY MOLECULAR BEAM EPITAXY ( MBE ) .

2 . CONTINUING IN SITU MEASUREMENT OF PROCESS CHARACTERISTICS .

3 . IMPLEMENTING AND DEVELOPING TECHNIQUES FOR THE CHARACTERISATION OF MBE LAYERS . THIS INFORMATION WILL THEN BE USED TO OPTIMISE GROWTH CONDITIONS .

IT IS PLANNED THAT FOUR SPECIFIC DEVELOPMENTAL TASKS BE UNDERTAKEN ON FOUR SPECIFIC TECHNIQUES . THE REMAINDER OF THE PROGRAMME WILL BE CONCERNED WITH THE APPLICATION OF EXISTING TECHNIQUES AND THE INTERPRETATION OF THE TOTALITY OF THE RESULTS SO OBTAINED .

1.9.4 . " SILICON-ON-INSULATOR SYSTEMS COMBINED WITH LOW TEMPERATURE " ( REF . 370 : B/84 )

IN THE PROJECT A NUMBER OF TECHNIQUES WILL BE USED AND COMBINED IN ORDER TO OBTAIN GOOD QUALITY SINGLE CRYSTAL LAYERS WITH THICKNESSES VARYING BETWEEN 0.5 UM AND 50 UM FOR A VARIETY OF APPLICATIONS . THESE RELATE TO BOTH SILICON-ON-INSULATOR ( SOI ) AND TO SOS ( SILICON-ON-SAPPHIRE ) FOR HIGH PERFORMANCE INTEGRATED CIRCUITS , AND ALSO FOR THE PROVISION OF ALTERNATIVES TO THE CURRENTLY USED CUMBERSOME DIELECTRIC ISOLATION ( DI ) PROCESSING .

1.9.5 . " A HIGH PERFORMANCE CMOS BIPOLAR PROCESS FOR VLSI CIRCUITS " ( REF . 412 : A/84 )

THIS PROJECT AIMS AT THE DEVELOPMENT OF A VLSI TECHNOLOGY WHICH COMBINES , ON A SINGLE CHIP , MOS CIRCUITRY OF THE HIGHEST DENSITY PRESENTLY OBTAINABLE , WITH BIPOLAR CIRCUITRY OF SIMILAR DENSITY , BUT BETTER SUITED TO SPECIFIC TASKS , IN PARTICULAR , THE INTERFACING WITH EXTERNAL EQUIPMENT . IN THE PROJECT THE MAIN EFFORT WILL FALL ON THE TECHNOLOGICAL SIDE : DEVELOPMENT OF METHODS WHICH ALLOW BOTH BIPOLAR AND MOS TRANSISTORS TO BE MADE IN COMPATIBLE PROCESS STEPS , AND THIS DOWN TO DIMENSIONS COMPARABLE TO THOSE PRESENTLY OBTAINED IN MOS-ONLY TECHNOLOGY . IN PARALLEL WITH THIS TECHNOLOGICAL WORK DESIGN METHODS HAVE TO BE DEVELOPED FOR THE SPECIFIC TYPE OF CIRCUITRY ENVISAGED , ALONG WITH A STUDY TO DETERMINE , FOR VARIOUS TYPES OF APPLICATION , THE MOST APPROPRIATE DIVISION OF SUBSYSTEMS BETWEEN THE TWO CIRCUIT TECHNOLOGIES .

1.9.6 . " IMPROVEMENT OF YIELD AND PERFORMANCE OF ICS BY DESIGN CENTERING " ( REF . 456 : B/84 )

THIS PROJECT WILL APPLY THE NEW METHOD OF DESIGN CENTERING TO OPTIMISE THE PERFORMANCE OF IC'S . AN ALREADY EXISTING PROGRAM FOR DESIGN CENTERING AND A PROGRAM FOR THE IMPROVEMENT OF THE CIRCUIT PERFORMANCE WILL BE IMPROVED AND ADAPTED IN THE SPECIAL PROBLEMS OCCURING IN THE DESIGN OF VLSI-CIRCUITS . THE PROGRAM-PARTS TO BE DEVELOPED SHOULD INCLUDE SCHEMATIC INPUT , OUTPUT OF RELEVANT RESULTS AND AN IMPROVEMENT OF THE SEARCH STRATEGY IN ORDER TO CUT DOWN CPU-TIME EVENTUALLY BY INCREASING STORAGE REQUIREMENTS . THE PROGRAM SHOULD BE EASY TO HANDLE AND WILL FINALLY BE TESTED WITH VARIOUS IC'S PROVIDED BY THE COMPANIES .

1.9.7 . " SUBSTRATES FOR CMOS VLSI TECHNOLOGY " ( REF . 509 : B/84 )

PART 1 : TO SET UP AN INTRINSIC GETTERING ( IG ) PROCESS FOR WAFERS WITH MEDIUM HIGH OXYGEN CONCENTRATION . THE PROCESS SHOULD BE INDEPENDENT OF THE TYPE , P OR N , OF THE SUBSTRATE AND SHOULD BE ABLE TO PRODUCE :

- A HIGHLY DEFECTIVE BULK REGION

- A DEFECT-FREE DENUDED ZONE

A THICKNESS OF THIS ZONE AROUND 10-20 UM IS IDENTIFIED AS AN OPTIMUM COMPROMISE FOR SEVERAL FACTORS ( LEAKAGE CURRENT , INSENSITIVITY TO LATCH UP AND SOFT ERROR ) .

PART 2 : TO CHARACTERISE EPI WAFERS WITH DIAMETER 4 AND 6 INCHES . THE THICKNESS OF THE EPILAYER SHOULD BE IN THE RANGE 5-10 UM , BOTH FOR P+ AND N+ SUBSTRATES . THIS THICKNESS RANGE IS SUITABLE FOR SUBMICRON CMOS . FINALLY , IG AND EPI PROCESS SHOULD EVENTUALLY MATCH TO HAVE INTRINSICALLY-GETTERED , LOW LEAKAGE EPIWAFERS FOR SUBMICRON CMOS DEVICES INSENSITIVE TO SOFT ERRORS .

1.9.8 . " QUANTUM SEMICONDUCTOR DEVICES " ( REF . 514 : B/84 )

IT IS PLANNED TO

1 . EXPLORE DEVICE STRUCTURES WHERE THE CARRIERS ARE CONTROLLED WITHIN AND BETWEEN LAYERS BY ELECTRIC FIELDS IMPOSED BY IMPLANTED/DIFFUSED REGIONS , OR BY SPECIALLY CONFIGURATED GATE STRUCTURES ( E . G . SUBMICRON PITCH INTERDIGITATED FINGERS ) , AND

2 . SUPPORT THIS PROGRAMME WITH THEORETICAL STUDIES OF BASIC SEMICONDUCTOR PHYSICS AND OF ELECTRONIC AND OPTOELECTRONIC EFFECTS IN NOVEL STRUCTURES .

1.9.9 . " DOPANT PROFILING FOR SUBMICRON STRUCTURES " ( REF . 519 : B/84 )

THE AIM OF THIS PROJECT IS TO REALISE THE CAPABILITIES FOR THE ACCURATE DETERMINATION OF SHALLOW DOPANT PROFILES AS USED IN SUBMICRON DEVICES . TO ACHIEVE THIS THE DEVELOPMENT OF ONE ELECTRICAL TECHNIQUE , I . E . SPREADING RESISTANCE , IS PROPOSED TOGETHER WITH AN INTERCOMPARISON OF THIS TECHNIQUE WITH TWO OTHER NON-ELECTRICAL METHODS , I . E . SECONDARY ION MASS SPECTROMETRY ( SIMS ) AND RUTHERFORD BACK SCATTERING ( RBS ) . THE PRIMARY EMPHASIS OF THE PROJECT WILL BE PUT ON THE DEVELOPMENT AND USE OF THE SPREADING RESISTANCE TECHNIQUE WITH THE OTHER TECHNIQUES BEING USED PRIMARILY FOR COMPARISON . A MAJOR BY-PRODUCT OF THIS APPROACH WILL BE THE DATA ENABLING A BETTER UNDERSTANDING OF DIFFUSION KINETICS TO BE OBTAINED . IN ADDITION THE WORK WILL CONCENTRATE ON PROFILING BORON PHOSPHORUS , ARSENIC AND ANTIMONY AND WILL ALSO INVOLVE THE USE OF AND ASSESSMENT OF NOVEL ANNEALING METHODS SUCH AS STRIP HEATER AND FLASHLAMP ANNEALING .

1.9.10 . " HIGH RESOLUTION PLASMA ETCHING IN SEMICONDUCTOR TECHNOLOGY-FUNDAMENTALS , PROCESSING AND EQUIPMENT " ( REF . 574 : B/84 )

IT IS WIDELY RECOGNISED WITHIN THE ELECTRONICS INDUSTRY THAT PLASMA ETCHING WILL PLAY A VITAL ROLE IN ACHIEVING SUBMICRON TECHNOLOGY BOTH IN SILICON AND III/V SEMICONDUCTOR SYSTEMS . HOWEVER , MUCH REMAINS TO BE DONE TO UNDERSTAND THE COMPLEX CHEMISTRY AND PHYSICS INVOLVED BY APPLYING SUITABLE DIAGNOSTIC METHODS . UNTIL THIS IS ACCOMPLISHED THE FULL POTENTIAL OF PLASMA ETCHING WILL NOT BE REALISED . THE OVERALL PROGRAMME IS NECESSARILY INTERACTIVE AND BRINGS TOGETHER CENTRES OF EXPERTISE IN PLASMA CHEMISTRY AND PHYSICS , INSTRUMENT MANUFACTURERS AND A SUPPLIER OF CHEMICALS TO THE ELECTRONICS INDUSTRY . COLLECTIVELY THEY POSSESS A UNIQUE COMBINATION OF KNOWLEDGE AND FACILITIES WHICH WILL ASSURE SUCCESS IN THIS BROADLY BASED PROGRAMME .

TO ACHIEVE THE PROGRAMME GOALS A SERIES OF SIGNIFICANT PROJECTS IS REQUIRED . IN PARTICULAR TO ACHIEVE PROCESSING AT FEATURE SIZES OF 0.5 UM AND BELOW THE FOLLOWING PROJECT AREAS ARE IDENTIFIED , AND THE DELIVERABLES OF THESE PROPOSALS SHOULD BE ALIGNED WITH THE 1.1 AND 1.2 PROGRAMMES

( A ) 0.5 UM LITHOGRAHY WITH PRODUCTION THROUGHPUT AND ASSOCIATED RESIST DEVELOPMENT WHICH SHOULD BE COMPATIBLE WITH DRY ETCHING PROCESSES

( B ) ANISOTROPIC ETCHING OF WAFERS UP TO 150 UM WITH 0.5 UM FEATURE SIZES ( REACTIVE ION ETCHING -RIE , REACTIVE ION-BEAM ETCHING-RIBE , ETC . )

( C ) PROCESS TECHNIQUES ENABLING REDUNDANCY FOR VERY LARGE AREA INTEGRATED CIRCUITS

( D ) MODELLING OF PROCESSES AND DEVICES INCLUDING EXPERIMENTAL VERIFICATION .

ADDITIONAL PROPOSALS FOR B-TYPE RESEARCH THEMES ARE INVITED . THE FOLLOWING LISTS ARE INDICATIVE OF SUITABLE TOPICS BUT ARE NOT EXCLUSIVE . CANDIDATE SUBJECTS RELATED TO VLSI INCLUDE :

- SEMICONDUCTOR PROCESSING MATERIALS

- RESIST TECHNOLOGY

- PLASMA AND REACTIVE ION PROCESSING

- ION IMPLANTATION

- PHOTO-ASSISTED DEPOSITION TECHNOLOGY

- RAPID THERMAL PROCESSING OF LAYERS ( E-BEAM , LASER , HEAT PULSE , ETC . )

- METALLIZATION : SILICIDE CONDUCTORS , NOVEL MATERIALS , NOVEL PROCESSING METHODS )

- ORGANIC INSULATORS

- HIGH SPEED ON-WAFER TESTING

- ADVANCED PACKAGING TECHNIQUES

- HIGH SPEED , MATERIALS , ETC .

- DEVICE AND PROCESS MODELLING

- AUTOMATED MANUFACTURING AND CONTROL .

CANDIDATE B-TYPE TOPICS SUPPORTING AREAS 1.4 AND 1.5 INCLUDE :

- CRYSTAL GROWTH OF LARGE INP AND GAAS SINGLE CRYSTALS

- MODELLING OPTICAL ELEMENTS

- DEVICE MODELLING FOR GAAS

- SPECIFIC CAD FOR III - V INTEGRATED CIRCUITS

- BASIC TECHNOLOGICAL PROCESSES FOR

- MATERIAL ASSESSMENT

- ION IMPLANTATION AND ANNEAL

- DRY ETCHING TECHNIQUES

- DIELECTRIC AND INSULATORS

- RELIABILITY

- SPECIFIC EQUIPMENT .

IN ADDITION A WIDE RANGING TYPE B PROGRAMME IS TO BE ENCOURAGED , SEEKING TO SUPPORT NEW AND PROMISING TECHNIQUES ACROSS THE WHOLE MICROELECTRONICS AREA AS DEFINED BY THE IDENTIFIED MAJOR PROJECT AREA .

- LITHOGRAPHY ( PHOTO - , ELECTRON - , X-RAY - , LASER - , ION - , ETC . )

- VARIOUS ACTIVE ELEMENTS ON HIGH MOBILITY SEMICONDUCTING MATERIALS

- DEVICE RELIABILITY AND FAILURE MECHANISMS

- NOVEL COMPOUND SEMICONDUCTING MATERIALS , NEW SEMICONDUCTORS AND NOVEL ( EG STACKED ) DEVICES USING THEM

- NEW DISPLAY METHODS ( FOR FLAT PANEL DISPLAYS - SEE SECTION 1.6 ) .

SUBPROGRAMME 2

SOFTWARE TECHNOLOGY

1 . INTRODUCTION

THE 1985 ISSUE OF THE WORKPLAN FOR THE ESPRIT SOFTWARE TECHNOLOGY SUBPROGRAMME IS NOT ONLY AN ADAPTATION OF THE 1984 ISSUE TO CURRENT TECHNOLOGICAL INSIGHTS AND TRENDS . IT ALSO REPRESENTS AN ATTEMPT TO IMPROVE THE WORKPLAN AS AN INSTRUMENT FOR PROJECT EVALUATION AND SELECTION , AND AS THE MAIN TECHNICAL GUIDE TO POTENTIAL PROPOSERS .

2 . OBJECTIVES AND RATIONALE

SOFTWARE TECHNOLOGY IS SEEN AS ONE OF THE MAJOR ENABLING TECHNOLOGIES OF THE IT INDUSTRY . SOFTWARE DEVELOPMENT IS A PART OF THE DESIGN PROCESS OF SYSTEMS AND IS EXPECTED TO ACCOUNT FOR AN INCREASINGLY LARGE PROPORTION OF TOTAL SYSTEM EFFORT . THEREFORE , POSSESSION OF HIGHLY EFFICIENT , COST-EFFECTIVE METHODS FOR THE PRODUCTION OF HIGH QUALITY , RELIABLE SOFTWARE WILL LEAD TO MORE RAPID INTRODUCTION OF NEW PRODUCTS AND THE REDUCTION OF TOTAL LIFE-CYCLE COSTS . EUROPE MUST HAVE FREE ACCESS TO THE BEST METHODS AND TOOLS AND BE AT LEAST EQUAL TO THE REST OF THE WORLD IN THEIR EXPLOITATION .

AT THE PRESENT TIME EUROPE PROBABLY IS ON A PAR TECHNICALLY WITH US AND JAPAN BUT MOST OF ITS EXPERTISE IS IN ISOLATED CENTRES OF EXCELLENCE AND NEEDS COORDINATION AND WIDER DISSEMINATION .

THE OVERALL OBJECTIVE OF THE SOFTWARE TECHNOLOGY SUBPROGRAMME IS TO REACH A STAGE WHERE THE DEVELOPMENT OF INFORMATION SYSTEMS ( I . E . PRODUCTS INCLUDING HARDWARE AND SOFTWARE SOLUTIONS ) WOULD HAVE THE CHARACTERISTICS OF AN INDUSTRIAL DESIGN PROCESS AND , TO A LARGER EXTENT , WOULD BE COMPUTER-ASSISTED . THE INFORMATION SYSTEMS ENVISAGED COVER IN PRINCIPLE THE WHOLE RANGE OF APPLICATION AREAS . SPECIFIC MENTION SHOULD GO TO THE FOLLOWING : DISTRIBUTED SYSTEMS ( E . G . DISTRIBUTED DATABASES ) , AND REALTIME AND EMBEDDED SYSTEMS .

A MAJOR BARRIER TO THE INTRODUCTION OF EXISTING AND FUTURE METHODS IS SEEN TO BE THE LACK OF KNOWLEDGE , BY INDUSTRIAL MIDDLE MANAGEMENT , OF THE BENEFITS TO BE GAINED FROM THESE METHODS AND THE INVESTMENT NEEDED TO INTRODUCE THE METHODS ( STAFF TRAINING , ORGANIZATIONAL CHANGES , ETC . ) . THIS IS FURTHER REINFORCED BY THE NEED TO ADOPT A " MINIMUM-RISK " POLICY FOR NEW INDUSTRIAL PROJECTS .

A NEW CLASS OF PROJECTS HAS THEREFORE BEEN CONSIDERED IN SOFTWARE TECHNOLOGY . THESE WILL INVOLVE THE INDUSTRIAL USE ( NOT THE DEVELOPMENT ) OF CURRENT STATE-OF-THE-ART IN SOFTWARE TECHNOLOGY . THESE PROJECTS CAN START IMMEDIATELY . AN ESSENTIAL PART OF PROJECT PROPOSALS IN THIS CLASS MUST BE ANALYSIS AND DISSEMINATION OF THE EFFECTIVENESS OF THE TECHNOLOGY . THE MAIN ACTIVITY IS TO ASSESS SOFTWARE TECHNOLOGY RATHER THAN TO DEVELOP IT ( I . E . CASE STUDIES IN USAGE ) . SOME PROJECTS OF THIS NATURE HAVE BEEN DESCRIBED UNDER THE R AND D AREAS 2.1 , 2.2 AND 2.3 ; FURTHER PROPOSALS ARE INVITED IN SECTION 2.4 .

3 . DESCRIPTION OF THE SUBPROGRAMME

IN ACCORDANCE WITH THE ACCEPTED DIVISION OF THE SOFTWARE DEVELOPMENT TASK INTO THREE KEY AREAS ( SEE ALSO 1984 WORKPLAN ) , THERE ARE THREE MAIN R AND D AREAS IN THIS SUBPROGRAMME :

THEORIES , METHODS , AND TOOLS ( 2.1 )

THE ACTIVITIES IN THIS AREA ADDRESS THE TRANSITION TO AN ENGINEERING APPROACH TO SYSTEMS AND SOFTWARE . A SCENARIO IS ENVISAGED IN WHICH WELL-FOUNDED SCIENTIFICALLY-BASED METHODS ARE GRADUALLY ADOPTED TO REPLACE AD HOC TECHNIQUES CURRENTLY IN USE . IN ADDITION , THERE WILL BE WORK ON MORE ADVANCED APPROACHES TO INFORMATION SYSTEMS ENGINEERING .

MANAGEMENT AND INDUSTRIAL ASPECTS ( 2.2 )

PROJECTS IN THIS AREA ARE INTENDED TO CONSOLIDATE UNDERSTANDING OF , AND EFFECTIVE MEANS OF SUPPORT FOR , THE MANAGEMENT AND INDUSTRIAL ASPECTS OF SOFTWARE PROJECTS . THESE ASPECTS INCLUDE THE BROADER ISSUES OF THE SOFTWARE PRODUCT LIFE CYCLE AS IT APPEARS IN THE SOFTWARE AND INFORMATION SYSTEMS INDUSTRY . THEY ALSO INCLUDE ISSUES CONCERNED WITH SOFTWARE PROJECT MANAGEMENT .

COMMON ENVIRONMENT ( 2.3 )

PROJECTS IN THIS AREA WILL DEVELOP A COMMON ENVIRONMENT TO BE USED :

- AS A PRIMITIVE SOFTWARE DEVELOPMENT ENVIRONMENT

- AS THE BASIS FOR THE DEVELOPMENT OF A COMPLETE INTEGRATED SOFTWARE ENGINEERING ENVIRONMENT .

OTHER PROJECTS SHOULD PROVIDE THE BASIS FOR THE MORE ADVANCED ENVIRONMENTS OF THE FUTURE .

A FOURTH SECTION OF THE SUBPROGRAMME ADDRESSES THE NEED FOR DEMONSTRATION AND EVALUATION PROJECTS .

THE PROJECTS TO BE EXECUTED UNDER THE ST SUBPROGRAMME ARE INTENDED TO SECURE THE BEST COMPETITIVE POSITION OF THE EUROPEAN IT INDUSTRY BY THE COLLABORATION OF RESEARCH ESTABLISHMENTS , SOFTWARE TOOLMAKERS AND THE INDUSTRIAL USERS .

IN THE OVERALL ACTIVITY CYCLE FOR IMPROVING THE SOFTWARE TECHNOLOGY BASE THREE PHASES CAN BE DISTINGUISHED , EACH TYPE OF COLLABORATOR CONTRIBUTING IN DIFFERENT PROPORTIONS ACCORDING TO THE PHASE , AS FOLLOWS :

* THEORETICAL AND EMPIRICAL RESEARCH

THE AIM OF PROJECTS IN THIS PHASE IS TO PROMOTE A BETTER UNDERSTANDING OF THE NATURE OF THE SOFTWARE PROCESS WITHIN AN ECONOMIC CONTEXT , AND THE UNDERLYING MATHEMATICAL AND COMPUTER-SCIENCE THEORY . THE INDUSTRIAL APPLICABILITY OF THE RESEARCH WILL BE CONFIRMED BY PROTOTYPING AND PILOT APPLICATIONS .

* DEVELOPMENT OF ENABLING TECHNOLOGY

PROJECTS IN THIS PHASE CONCERN THE DEVELOPMENT OF INDUSTRIALLY ACCEPTABLE TECHNOLOGY ( TYPICALLY METHODS AND TOOLS ) WHICH EXPLOIT THE ADVANCED IN THEORETICAL UNDERSTANDING . THIS PHASE REQUIRES THE WIDEST FORM OF COLLABORATION AND THE GREATEST MOBILISATION OF RESOURCES , WHICH IN TURN REQUIRES THE ADOPTION OF A COMMON TOOLS ARCHITECTURE TO ENSURE WIDESPREAD APPLICABILITY AND INTER-WORKING OF TOOLS ACCORDING TO LOCAL REQUIREMENTS .

* INDUSTRIAL APPLICATION

THIS PHASE CONCERNS THE INDUSTRIAL APPLICATION OF THE TECHNOLOGY PRODUCED FROM THE SECOND PHASE . COLLABORATION IN THIS PHASE IS TYPICALLY REQUIRED TO MONITOR THE INTRODUCTION OF THE TECHNOLOGY , THE IMPACT IT HAS ON THE NATURE OF THE SOFTWARE PROCESS , AND THE IMPLICATIONS FOR FUTURE THEORETICAL AND EMPIRICAL WORK . THUS THE CYCLE BEGINS AGAIN .

PROJECTS WITH THE SUBPROGRAMME WILL HAVE CHARACTERISTICS OF ONE OR MORE OF THE PHASES MENTIONED ABOVE AND SHOULD THEREFORE BE ASSESSED ACCORDING TO APPROPRIATE PHASE-ORIENTED CRITERIA , OF WHICH EXAMPLES ARE GIVEN BELOW .

* THEORETICAL AND EMPIRICAL RESEARCH

NOVELTY , ADVANCING STATE OF THE ART , INCREASING UNDERSTANDING OF THE SOFTWARE PROCESS , POTENTIAL IMPACT ON SOFTWARE ECONOMICS , ETC .

* DEVELOPMENT OF ENABLING TECHNOLOGY

INDUSTRIAL ACCEPTABILITY , ACTUAL IMPACT ON SOFTWARE ECONOMICS , INTEROPERABILITY WITH EXISTING INDUSTRIAL PRACTICE , WIDTH OF APPLICABILITY , ADAPTABILITY , CONFORMITY TO STANDARDS , INTEGRABILITY WITH OTHER TOOL DEVELOPMENTS , ETC .

* INDUSTRIAL APPLICATION

IMPACT ON FUTURE RESEARCH , TOOLS STANDARDS , TRAINING , AND OVERALL APPROACH TO CHANGING THE TECHNOLOGY BASE OF THE RELEVANT INDUSTRY SECTOR , GENERALIZABILITY AND DISSEMINATION OF RESULTS , ETC .

IN ORDER TO MAXIMIZE THE INDUSTRIAL ADVANTAGE OF THE DEVELOPMENT AND INTRODUCTION OF TECHNOLOGY , THE ESPRIT SOFTWARE TECHNOLOGY SUBPROGRAMME INCLUDES NOT ONLY THE SPONSORSHIP OF RADICALLY NEW APPROACHES IN THE FORM OF RESEARCH WHICH MAY TAKE SEVERAL YEARS TO MATURE . IT ALSO PROMOTES THE COLLABORATIVE DEVELOPMENT OF INDUSTRIALLY ACCEPTABLE TECHNOLOGY , WHICH EXPLOITS THE EXISTING KNOWLEDGE AS IT MATURES . WITHIN THE CONSTRAINT OF REMAINING PRE-COMPETITIVE , IT ALSO PROMOTES ITS INTRODUCTION INTO INDUSTRY AND ASSESSES ITS IMPACT ON THE INDUSTRIAL USERS .

4 . CURRENT WORK AND NEW PROJECTS FOR 85

THE CURRENTLY ACCEPTED NOTION IS THAT INDUSTRIALISATION OF THE SOFTWARE DEVELOPMENT TASK WILL BE VIA THE INTRODUCTION OF INTEGRATED PROJECT SUPPORT ENVIRONMENTS , I . E . COLLECTIONS OF COMPUTER BASED TOOLS AND METHODS DESIGNED TO WORK TOGETHER AND SUPPORT ALL THE TECHNICAL AND MANAGEMENT ASPECTS OF THE SOFTWARE PROCESS . THE PRESENT ESPRIT WORK PROVIDES A GOOD BASIC COVERAGE OF THE TOOLS AND ENVIRONMENTS BUT REQUIRES FURTHER SUPPORTING PROJECTS TO FILL OUT THE DETAIL AND TO PROVIDE ADDITIONAL COVERAGE OF HIGH-RISK AREAS . IN ADDITION , NEW WORK IS NECESSARY IN THE FOLLOWING FIELDS :

- SYSTEMS PROJECTS ( THE INTEGRATION OF THE HARDWARE AND SOFTWARE DESIGN CYCLES ) .

- ALTERNATIVE AND COMPLEMENTARY METHODS OF SOFTWARE DEVELOPMENT , E . G . PROTOTYPING AND THE APPLICATION OF ARTIFICIAL INTELLIGENCE TECHNIQUES .

- SOFTWARE METHODS AND TOOLS FOR SMALL , HIGHLY CRITICAL SOFTWARE .

- METRICS FOR SOFTWARE AND FOR THE SOFTWARE PRODUCTION PROCESS .

- MAN-MACHINE INTERACTION .

- SOFTWARE ENGINEERING FOR BROAD APPLICATION AREAS SUCH AS CIM AND AIP .

- EVALUATION PROJECTS TO ASSESS THE REAL PROBLEMS AND THE REAL BENEFITS OF INTRODUCING THE NEW TECHNOLOGY .

THE WORKPLAN ALSO CONTAINS WORK ON ADA-RELATED METHODS AND TOOLS , AS WELL AS ON SUITABLE ENVIRONMENTS FOR THE DEVELOPMENT , MAINTENANCE AND EVALUATION OF DISTRIBUTED DATABASES , IN ORDER TO ROUND OUT THE WORK NOW FORESEEN FOR THE EXTENSION OF THE COMMUNITY MULTI-ANNUAL DATA PROCESSING PROGRAMME .

R AND D AREA 2.1 : THEORIES , METHODS AND TOOLS

DESCRIPTION

THE ACTIVITIES IN THIS AREA ADDRESS FIRST OF ALL THE TRANSITION TO AN ENGINEERING APPROACH TO SYSTEMS AND SOFTWARE WITHIN THE FRAMEWORK OF CURRENT LIFE-CYCLE VIEWS . A SCENARIO IS ENVISAGED IN WHICH WELL-FOUNDED SCIENTIFICALLY-BASED METHODS ARE GRADUALLY ADOPTED TO REPLACE AD HOC TECHNIQUES CURRENTLY IN USE .

INDUSTRIAL AND ACADEMIC COLLABORATION IS PARTICULARLY RELEVANT TO THIS AREA , SINCE ACADEMIC RESEARCHERS IN EUROPE HAVE PRODUCED A SIGNIFICANT THEORETICAL BASE WHICH SHOULD PROVIDE THE FOUNDATIONS OF IMPROVED SYSTEMS AND SOFTWARE ENGINEERING METHODS .

ONE OF THESE FOUNDATIONS IS THE WORK IN THE AREA OF FORMAL DESCRIPTION . BECAUSE THEY ADHERE TO WELL-DEFINED MATHEMATICAL PRACTICE , FORMAL DESCRIPTIONS ALLOW THE UNAMBIGUOUS , CONCISE AND CLEAR SPECIFICATION OF A SOFTWARE PRODUCT WITHOUT CONSTRAINING THE IMPLEMENTATION , AND PROVIDE A GOOD BASIS FOR SUCH IMPORTANT CONCERNS AS FUNCTIONAL ANALYSIS , VERIFICATION , SIMULATION , EDUCATION , AUTOMATIC IMPLEMENTATION AND TESTING .

THE EMPHASIS IS ON THE DEVELOPMENT OF IMPROVED METHODS FOR SYSTEM CONSTRUCTION . THESE METHODS MUST THEN BE SUPPORTED BY INTEGRATED SUPPORT TOOLS . IT IS ASSUMED HERE THAT THE OVERALL DEVELOPMENT APPROACH , WHICH THE TOOLS SUPPORT , WILL EMPLOY MULTIPLE LEVELS OF REPRESENTATION WITH INCREMENTAL VERIFICATION AND VALIDATION . WHERE POSSIBLE , TOOLS MAY BE PROVIDED BY RE-WORK OR ENHANCEMENT OF EXISTING SOFTWARE RATHER THAN BY COMPLETELY NEW DEVELOPMENT .

IN THIS CONTEXT IT IS IMPORTANT TO DISTINGUISH SHORT AND LONG TERM CONCERNS :

- IN THE SHORT TERM IT IS IMPORTANT TO WORK TOWARDS UNIFICATION AND INTEGRATION OF THE EXISTING MODELS AND TOOLS IN SOFTWARE PRODUCTION . IN THIS AREA THE EFFORTS WILL HOPEFULLY LOWER THE THRESHOLD WHICH STILL PREVENTS EVEN SOFTWARE ENGINEERS FROM USING THESE TOOLS .

- IN THE LONGER TERM ONE WILL NEED TO STRESS THE VIEW OF THE SYSTEM AS A WHOLE , AND ESPECIALLY UNITE THE CLASSICALLY SEPARATED PROCESSES OF SOFTWARE PRODUCTION AND HARDWARE DEVELOPMENT . THUS PROFIT CAN BE DRAWN FROM THE INCREASED FLEXIBILITY OFFERED BY THE WEAKENED BORDERLINE BETWEEN HARDWARE AND SOFTWARE . ( CONSIDER THE POSSIBILITY OFFERED BY TODAY'S MINICOMPUTERS TO DECIDE , DEPENDING ON THE ACTUAL NEEDS , WHETHER FLOATING POINT ARITHMETIC SHALL BE DONE BY SOFTWARE OR BY HARDWARE ) .

WITH RESPECT TO THE CURRENT PHASE-ORIENTED MODELS OF THE SYSTEM DEVELOPMENT PROCESS , UNIFICATION AND UPGRADING OF TOOLS CORRESPONDING TO INDIVIDUAL PHASES AND THEIR SEQUENCING IS A MORE SHORT-TERM CONCERN , WHEREAS THE POSSIBILITY TO DEFINE NEW PHASES AND/OR A NEW SEQUENCING OF THOSE IS OF MORE LONG-TERM INTEREST .

ALL EFFORTS SHOULD CONTRIBUTE SIGNIFICANTLY TO THE REDUCTION OF LIFE-CYCLE COSTS , PARTICULARLY IN THE AREAS OF TESTING AND MAINTENANCE , THROUGH EARLIER ERROR DETECTION AND REMOVAL , AND THE DEVELOPMENT OF MORE RELIABLE AND HIGHER QUALITY SYSTEMS . THERE IS ALSO A STRONG INTERDEPENDENCE WITH THE MANAGEMENT ACTIVITIES DESCRIBED IN AREA 2.2 . MANAGEMENT METHODS MUST TAKE ACCOUNT OF IMPROVED SYSTEMS AND SOFTWARE DEVELOPMENT METHODS AND , SIMILARLY , SYSTEM DEVELOPMENT METHODS MUST TAKE ACCOUNT OF MANAGEMENT REQUIREMENTS .

THE SUB-AREAS INCLUDED ARE FIRST OF ALL " SYSTEM ORIENTED APPROACHES " ( 2.1.1 ) , WHICH STRESS THE PROBLEMS OF DEVELOPING COMPLETE SYSTEMS ( HARDWARE AND SOFTWARE ) , THEN " IMPROVING CURRENT SOFTWARE DEVELOPMENT APPROACHES " ( 2.1.2 ) , FOLLOWED BY " ADVANCED SOFTWARE DEVELOPMENT APPROACHES " ( 2.1.3 ) , AND FINALLY " QUALITY , RELIABILITY , CONFORMITY TESTING AND DEMONSTRATING " ( 2.1.4 ) .

2.1.1 . SYSTEM ORIENTED APPROACHES

THREE MAIN THEMES HAVE BEEN SELECTED IN THIS AREA :

- HARDWARE/SOFTWARE SYNERGY .

- REQUIREMENTS ENGINEERING .

- DESIGN OF SECURE SYSTEMS .

2.1.1.1 . HARDWARE/SOFTWARE SYNERGY ( TYPE A )

OBJECTIVES

( A ) TO DEVELOP COMMON TECHNIQUES , METHODS AND TOOLS FOR THE WHOLE ( HARDWARE AND SOFTWARE ) SYSTEM DEVELOPMENT PROCESS , E . G . DESIGN LANGUAGES .

( B ) TO DEVELOP AN INTEGRATED APPROACH FOR MODELLING THE OVERALL SYSTEM ( SOFTWARE BEHAVIOUR , HARDWARE PERFORMANCE , SYSTEM UTILIZATION ) . THIS DYNAMIC MODELLING MUST ACHIEVE COST-EFFECTIVENESS AND ADEQUACY OF THE SYSTEM AS A WHOLE , MATCHING HISTORICAL DATA ; SYSTEM CHARACTERISTICS TO BE OBSERVED ARE COMPACTNESS , RESPONSE TIME , REPRODUCIBILITY , ROBUSTNESS , FLEXIBILITY .

( C ) TO ENABLE AUTOMATED TRANSFORMATION OF FORMAL SPECIFICATIONS INTO SILICON/SOFTWARE .

( D ) TO DEVELOP TEST AND EVALUATION STRATEGIES REGARDING THE INCREASED COMPLEXITY OF SUCH SYSTEMS , E . G . CONSIDERING BUGS AND FAILURES AS DECREASING FUNCTIONALITY OVER THE SYSTEM LIFE CYCLE .

RATIONALE/BACKGROUND

THERE IS A NEED FOR AN INTEGRATED APPROACH IN THE DESIGN OF SYSTEMS WITH THE AIM OF BEING ABLE TO REALIZE EACH COMPONENT IN THE BEST SUITED " MATERIAL " . THIS SHOULD LEAD TO GREATER FLEXIBILITY IN DESIGN , AND THE POSSIBILITY OF EASIER TECHNOLOGY UPGRADE DURING PRODUCT LIFE .

TECHNICAL APPROACH

INTEGRATION OF SOFTWARE METHODS AND FORMALISMS WITH THOSE EXISTING IN HARDWARE DESIGN . ANALYSIS OF THE IMPACT OF NON-FUNCTIONAL REQUIREMENTS ON SYSTEM DESIGN METHODS ( TAILORING TO TARGET CHARACTERISTICS ) SUCH AS FAULT TOLERANCE .

INTERMEDIATE OBJECTIVES

YEAR 3 - INITIAL MODELS AND PROTOTYPE TOOLS

YEAR 4 - TEST AND EVALUATION STRATEGIES

YEAR 5 - AUTOMATED TRANSFORMATION OF FORMAL SPECIFICATION

YEAR 6 - DEMONSTRATE TECHNOLOGY DEVELOPED AND SHOW APPLICABILITY TO COMPLETE SYSTEM DESIGN .

INTERDEPENDENCIES

OTHER PROJECTS IN 2.1 , CAD FOR VLSI ( 1.3 ) , COMPUTER ARCHITECTURES ( 3.4 ) .

2.1.1.2 . REQUIREMENTS ENGINEERING ( TYPE A )

OBJECTIVES

TO DEVELOP A FORMAL FRAMEWORK , METHODS AND TOOLS FOR THE CAPTURE AND DESCRIPTION OF SYSTEM REQUIREMENTS .

RATIONALE/BACKGROUND

THIS IS A PROBLEM OF FUNDAMENTAL IMPORTANCE TO ALL IT PRODUCT DEVELOPMENT . FAILURE TO ACHIEVE EFFECTIVE REQUIREMENTS CAPTURE IS AT THE ROOT OF MANY SLIPS IN PROJECT TIMESCALES AND COST OVERRUN .

TECHNICAL APPROACH

INTERACTION WITH THE CLIENT/USER OF THE SYSTEM IS ESSENTIAL TO THIS ISSUE . THEREFORE A VARIETY OF APPROACHES MAY BE REQUIRED LIKE NATURAL LANGUAGE PROCESSING , AUDIO-VISUAL FEEDBACK ( ANIMATION ) , IN ADDITION TO FORMAL METHODS WHICH WOULD BE AT THE CORE OF THE SOLUTION .

INTERMEDIATE OBJECTIVES

YEAR 2 - EXPERIMENT WITH EXISTING SYSTEMS , DRAW UP FORMAL FRAMEWORK

YEAR 3 - INITIAL METHODS AND PROTOTYPE TOOLS

YEAR 5 - PRODUCE DEFINITIVE METHODS AND COMPLETE CORRESPONDING TOOL SUPPORT .

INTERDEPENDENCIES

WITH AIP ( NATURAL LANGUAGE , COGNITIVE PSYCHOLOGY ) .

IN VIEW OF THE WIDE APPLICATION AREA DEPENDENCE , MORE THAN ONE PROJECT IS EXPECTED TO BE LAUNCHED .

2.1.1.3 . PUBLIC-DOMAIN TECHNIQUES FOR SYSTEMS INTEGRITY

OBJECTIVES

TO DEVELOP METHODS AND TECHNIQUES FOR DESIGNING AND IMPLEMENTING SYSTEMS THAT MUST BE SAFEGUARDED FROM STATED INFRINGEMENTS , E . G . BECAUSE THEY DEAL WITH SENSITIVE DATA , OR BECAUSE RESOURCE USAGE MUST BE STRICTLY CONTROLLED FOR ACCOUNTING PURPOSES . AN IMPORTANT REQUIREMENT IS THAT THE METHODS AND TECHNIQUES MUST DEMONSTRABLY PROVIDE THE INTEGRITY PROPERTIES .

THE TECHNIQUES MUST BE CAPABLE OF DEALING WITH A DISTRIBUTED NETWORK OF USERS WITH MULTIPLE LEVELS OF ALLOWED ACCESS .

RATIONALE/BACKGROUND

TECHNIQUES BASED ON NON-PUBLIC , PROPRIETARY METHODS MAY NOT BE SOCIALLY ACCEPTABLE IN MANY AREAS ( PUBLIC TELECOMMUNICATION , MEDICAL , BANKING , . . . ) . ONE OF THE MAIN REASONS WHY THEY MAY BE UNACCEPTABLE IS THE DIFFICULTY OF ASSESSING THE REAL LEVEL OF SECURITY THEY PROVIDE . THEREFORE , THERE IS A NEED FOR TECHNIQUES THAT DO NOT RELY ON THEIR NOT BEING PUBLIC .

TECHNICAL APPROACH

FORMAL METHODS SHOULD BE ADOPTED SO AS TO BE ABLE TO GUARANTEE OR PROVE THE REQUIRED INTEGRITY PROPERTIES OF THE SYSTEM . SPECIFIC CHARACTERISTICS TO BE MEASURED FOR PURPOSES OF DEMONSTRATION WILL HAVE TO BE QUANTIFIED .

INTERDEPENDENCIES

RELATIONS TO SOFTWARE/HARDWARE SYNERGY ( 2.1.1.1 ) AND SOFTWARE QUALITY AND RELIABILITY METRICS ( 2.1.4 ) .

PROPOSALS FOR B-TYPE PROJECTS ARE INVITED , WHICH MAY START IN 1986 .

2.1.1.4 . OTHER B-TYPE RESEARCH THEMES

IN THE AREA OF SYSTEMS ORIENTED APPROACHES A NUMBER OF SMALLER B-TYPE PROJECTS ARE ALSO ENVISAGED IN ADDITION TO THE LARGER A AND B-TYPE PROJECTS MENTIONED ABOVE . AN IMPORTANT ONE COULD BE THE STUDY OF TECHNICAL MEANS FOR EFFECTIVELY SAFEGUARDING THE PROPERTY RIGHTS IN SOFTWARE ( PREVENTION OF SOFTWARE PIRACY ) . OTHERS ARE EXEMPLIFIED BY DESIGN OF SOFTWARE FOR EMBEDDED MICROS , AND METHODS FOR THE DEVELOPMENT OF DISTRIBUTED PROCESSOR SYSTEM .

2.1.2 . IMPROVING CURRENT SOFTWARE DEVELOPMENT APPROACHES

THIS SUB-AREA IS INTENDED TO UNIFY AND IMPROVE METHODS AND TOOLS CORRESPONDING TO EXISTING FORMALISMS , WITH THE AIM OF ENCOURAGING THEIR USE ON A WIDER SCALE . FURTHERMORE , TECHNIQUES AND TOOLS FOR ENHANCING THE EFFICIENT PRODUCTION OF SOFTWARE SHOULD BE DEVELOPED AS A DIRECT AID TO REMOVING THE SO-CALLED APPLICATIONS BACKLOG .

IN RELATION TO THE CURRENT ORIENTATION OF THE EXTENSION TO THE COMMUNITY MULTI-ANNUAL DATA PROCESSING PROGRAMME , ATTENTION IS DRAWN TO THE SUBJECTS OF ADA-RELATED METHODS AND PROGRAMMING TOOLS , AS WELL AS DISTRIBUTED DATABASE TECHNIQUES . WORK ON THESE SUBJECTS WOULD CONTRIBUTE TO ROUNDING OUT THE PURELY DEVELOPMENT ORIENTED WORK THAT CAN BE SUPPORTED UNDER THAT PROGRAMME .

2.1.2.1 . " RIGOROUS APPROACH TO INDUSTRIAL SOFTWARE ENGINEERING ( RAISE ) " ( REF . 315 : A/84 )

THE PROJECT AIMS AT BUILDING A COMPLETE SYSTEMS DEVELOPMENT ENVIRONMENT BASED ON AN ENHANCED VERSION OF THE VDM METHOD . PRESENT SHORTCOMINGS OF VDM WILL BE CORRECTED , A NUMBER OF TOOLS WILL BE BUILT ( FIRST IN PROTOTYPE FORM , THEN IN PRODUCTION QUALITY FORM ) , SEVERAL INDUSTRIAL APPLICATIONS WILL BE UNDERTAKEN , AND TRAINING AND EDUCATIONAL MATERIAL WILL BE PRODUCED .

2.1.2.2 . " PERSONAL WORKSTATION FOR INCREMENTAL GRAPHICAL SPECIFICATION AND FORMAL IMPLEMENTATION OF NON-SEQUENTIAL SYSTEMS ( GRASPIN ) " ( REF . 125 : A/83 )

THE PROJECT AIMS AT A PERSONAL SOFTWARE DEVELOPMENT WORKSTATION FOR INCREMENTAL GRAPHICAL SPECIFICATION AND STEPWISE FORMAL IMPLEMENTATION OF NONSEQUENTIAL SYSTEMS . THE WORKSTATION IS TO COMPRISE A TOOL SET SUPPORTING TECHNIQUES FOR SPECIFICATION AND DOCUMENTATION , TESTING AND VERIFICATION AND CODING SIMULATION . GRASPIN IS BASED ON A WELL ENGINEERED MERGE OF TWO WIDELY ACCEPTED COMPLEMENTARY METHODS : HIGH-LEVEL PETRI-NET SPECIFICATIONS OF CONCURRENT ACTIVITIES AND AXIOMATIC-ALGEBRAIC SPECIFICATIONS OF ABSTRACT DATA TYPES . SIGNIFICANT USE IS TO BE MADE OF GRAPHICS AND OF CONCEPTS SUCH AS FOCUSSING TECHNIQUES , MULTIPLE WINDOWING CONCEPTS , AND SIMULTANEOUS HANDLING OF DIFFERENT CONTEXTS .

2.1.2.3 . COMPONENT-BASED SOFTWARE SYSTEM CONSTRUCTION ( TYPE A )

OBJECTIVES

TO DEVELOP TECHNIQUES AND TOOLS FOR CONSTRUCTING SOFTWARE FROM RE-USABLE SOFTWARE COMPONENTS .

RATIONALE/BACKGROUND

IT IS EXPECTED THAT EFFECTIVE RE-USE OF COMPONENTS WILL LEAD TO DRAMATIC IMPROVEMENTS IN SOFTWARE PRODUCTIVITY FOR APPLICATION SOFTWARE .

TECHNICAL APPROACH

DATABASES AND KNOWLEDGE BASES FOR STORAGE/RETRIEVAL OF COMPONENT DESCRIPTIONS ; THE RETRIEVAL PROCESS HAS TO BE INTEGRATED WITH THE DESIGN CYCLE , AND THIS IS AS YET A MAJOR TOPIC OF R AND D .

INTERMEDIATE OBJECTIVES

YEAR 3 - PRODUCE PROTOTYPE OF DATABASE FOR STORAGE/RETRIEVAL OF COMPONENT DESCRIPTIONS

YEAR 4 , 5 - INCORPORATE RESULTS FROM AIP SUB-PROGRAMME AND FORMAL TECHNIQUES

PRODUCE MORE ADVANCED RETRIEVAL MECHANISM , EXTENDING COMPLEXITY OF COMPONENT DESCRIPTIONS

YEAR 6 - FINAL INTEGRATION OF TECHNIQUES AND RETRIEVAL MECHANISMS .

INTERDEPENDENCIES

PCTE ( 2.3.1.1 ) , SPMMS ( 2.2.1.2 ) , FORMAL SPECIFICATION TECHNIQUES FOR DESCRIBING COMPONENTS , KNOWLEDGE-BASED SYSTEMS .

2.1.2.4 . SOFTWARE PRODUCTION BY SUCCESSIVE PROTOTYPES ( TYPE A )

OBJECTIVES

TO DERIVE METHODS , TECHNIQUES AND TOOLS FOR DEVELOPING SOFTWARE FROM A FIRST PROTOTYPE OF A COMPLETE SYSTEM TO AN IMPLEMENTED PRODUCT BY A SUCCESSION OF INTERMEDIATE " PROTOTYPES " . THE AIM IS FASTER DEVELOPMENT THAN BY " CLASSICAL LIFE-CYCLE APPROACH " .

RATIONALE/BACKGROUND

ONCE A FIRST PROTOTYPE IS AVAILABLE , WHICH SATISFIES ALL THE REQUIREMENTS , IT IS DESIRABLE TO BE ABLE TO SYSTEMATICALLY TRANSFORM IT INTO A REALISTIC PRODUCT .

TECHNICAL APPROACH

POSSIBLY :

- SUCCESSIVE REPLACEMENT OF COMPONENTS BY ONES BETTER SUITING THE PERFORMANCE/RELIABILITY , ETC ;

- TRANSFORMATION TECHNIQUES ;

- SIMULATION TECHNIQUES ;

- NON-IMPERATIVE LANGUAGES .

INTERMEDIATE OBJECTIVES

YEAR 3 - ESTABLISH METHODOLOGY

SELECT MORE PROMISING APPROACHES

YEAR 5 - DEVELOP RELEVANT TOOLS , AND CARRY OUT DEMONSTRATION DESIGNS .

INTERDEPENDENCIES

WITH 2.1.1.2 ( REQUIREMENTS ENGINEERING ) , AND 2.1.2.3 ( COMPONENT-BASED SYSTEM CONSTRUCTION ) .

2.1.2.5 . " PROGRAM DEVELOPMENT BY SPECIFICATION AND TRANSFORMATION " ( REF . 390 : B/84 )

THE OBJECTIVES OF THIS PROJECT ARE TO DEVELOP A STRICT METHODOLOGY FOR PROGRAM DEVELOPMENT BY TRANSFORMATIONS FROM FORMAL SPECIFICATION . THE TRANSFORMATION RULES ARE PROVED CORRECT " ONCE AND FOR ALL " , AND THEIR APPLICATION , SUPPORTED BY SOFTWARE , WOULD GUARANTEE THE DEVELOPMENT OF PROGRAMS CORRECT IN RELATION TO SPECIFICATION . THE USE OF ADA AS A STANDARD LANGUAGE , AND SPECIFICATIONS USING ANNOTATIONS IN ANNA , OR AN ANNA-LIKE LANGUAGE , WILL ENSURE PORTABILITIES BETWEEN APSE'S . IN ORDER TO SUPPORT THE USE OF THESE TOOLS IN A WORKSTATION , A COLLECTION OF ADDITIONAL TOOLS WOULD BE DEVELOPED .

2.1.2.6 . " SOFTWARE ENVIRONMENT FOR THE DESIGN OF OPEN DISTRIBUTED SYSTEMS ( SEDOS ) " ( REF . 410 : B/84 )

THIS THREE YEAR PROJECT IS BASED ON THE FORMAL DESCRIPTION TECHNIQUES CURRENTLY UNDER DEVELOPMENT IN THE FRAMEWORK OF OSI . IT AIMS AT PROVIDING PRAGMATIC AND STABLE FORMAL DESCRIPTION TECHNIQUES , APPLICATIONS OF THESE TECHNIQUES TO STANDARDS , VERIFICATION TECHNIQUES , AND A SET OF ( PROTOTYPE ) TOOLS TO SUPPORT THE SPECIFICATION , VERIFICATION , SIMULATION , IMPLEMENTATION AND TESTING OF OSI PROTOCOLS AND SERVICES IN PARTICULAR AND OPEN DISTRIBUTED SYSTEMS IN GENERAL .

2.1.2.7 . OTHER B-TYPE RESEARCH THEMES

PROPOSALS ARE INVITED IN ORDER TO DEVELOP METHODS , TOOLS AND ENVIRONMENT ASPECTS AROUND EXISTING FORMALISMS , WHICH ARE NOT TACKLED BY THE OTHER EXISTING PROJECTS IN AREA 2.1.2 . THEY SHOULD IN PRINCIPLE USE PCTE ( 2.3.1.1 ) AS AN INFRASTRUCTURE .

B-TYPE PROJECTS UNDER THIS HEADING ARE THOSE INTENDED TO INVESTIGATE AND EXPLOIT SPECIFIC FORMALISMS ; THE FORMALISM ITSELF IS THE CENTRE OF INTEREST . THE WORKPLAN ALSO PROVIDES FOR ALTERNATIVE EMPHASIS IN THE FOLLOWING SECTIONS :

- SECTION 2.2.4 , WHICH CONSIDERS THE MANAGEMENT IMPLICATIONS OF THE USE OF THE FORMALISM ;

- SECTION 2.3.3.1 , WHERE THE AIM IS TO GENERATE AN INTERACTIVE PROGRAMMING ENVIRONMENT FROM A CHARACTERISATION OF THE FORMALISM .

2.1.3 . ADVANCED SOFTWARE DEVELOPMENT APPROACHES

THE OBJECTIVES ARE TO INVESTIGATE THE POSSIBILITY OF INTEGRATING THE RIGOUR OF THE " SOFTWARE ENGINEERING " APPROACH AND THE FLEXIBILITY OF THE EXPERIMENTAL AND " THROWAWAY " STYLE OF SOFTWARE DEVELOPMENT EXEMPLIFIED BY KNOWLEDGE PROCESSING WORK ; ALSO TO PROVIDE FACILITIES FOR RAPID INCORPORATION OF FUTURE DEVELOPMENTS IN DIFFERENT CLASSES OF LANGUAGES .

THERE IS CURRENT WORK UNDER THIS HEADING ( SEE 2.1.3.1 BELOW ) BASED ON FORMAL METHODS ; OTHER PROJECTS COULD BE BASED ON ( I ) THE EXPLOITATION OF EXPERT SYSTEMS APPROACHES OR ( II ) NON-IMPERATIVE LANGUAGES .

2.1.3.1 . " AN INTEGRATED FORMAL APPROACH TO INDUSTRIAL SOFTWARE DEVELOPMENT ( METEOR ) " ( REF . 432 : A/84 )

THE BASIC GOAL OF THIS PROJECT IS THE APPLICATION OF FORMAL METHODS TO THE PROCESS OF DEVELOPING INDUSTRIAL SOFTWARE . THE CURRENT STATE OF THE ART IS NOT YET RIPE FOR STRAIGHTFORWARD INDUSTRIAL EXPLOITATION AND RESEARCH WORK IS NEEDED ON THE INTEGRATION OF FORMAL , YET NOT ENOUGH GENERAL , METHODS INTO A COHERENT AND GENERAL METHOD . IN PARTICULAR THE PROJECT AIMS AT INTEGRATING THE OBJECT-BASED LANGUAGE PARADIGM , THE ALGEBRAIC APPROACH TO SOFTWARE SPECIFICATION , THE RELATIONAL APPROACH AND SO-CALLED FORMAL HEURISTIC . INDUSTRIAL TAKE-UP , ESPECIALLY IN THE AREA OF CONSTRUCTING REALTIME DISTRIBUTED SYSTEMS , IS PROVIDED BY THE PLANNED CONSTRUCTION OF PROTOTYPE ENVIRONMENTS .

2.1.3.2 . " INVESTIGATION OF PERFORMANCE ACHIEVABLE WITH HIGHLY CONCURRENT INTERPRETATIONS OF FUNCTIONAL PROGRAMS " ( REF . 302 : B/84 )

THE PURPOSE OF THE PROJECT IS THE INVESTIGATION OF THE PERFORMA