He is an expert in Semiconductor Design & Test. He received a Best Paper Award at the CPA conference in the United Kingdom for his work on Software Development Methodologies for Real—time Distributed Hardware Systems. He is active in many industry wide activities including Registration Chair, Finance Chair and IEEE Liaison of the Pacific Northwest Test Workshop, Keynote Speaker of the Future of ATE Workshop (FATE) at the International Test Conference, Program Committee Member of the International Test Conference (ITC), SOC Test Topic Chair of the European Test Workshop (ETW), and Cost-of-Test Section Lead of the International Technology Roadmap for Semiconductors (ITRS).