Prof. Asanovic received a bachelor's degree in Electrical and Information Sciences from Cambridge University in 1987 and a doctorate in Computer Science from the University of California, Berkeley, in 1998. At MIT, he leads the SCALE project. From 1987-89 he was at the GEC Hirst Research Center in London where he co-architected the SPACE associative processor containing over 170,000 SIMD processors. At Berkeley, he led the development of the TO vector microprocessor and was an early contributor to the Berkeley IRAM project. He is currently serving as a member of the technical program committees for the International Solid-State Circuits Conference and the International Symposium on Computer Architecture. He is also serving as a DARPA ISAT member.