Document: NUREG-0800
Document ID: 6acfc377-3e1c-4cb9-b2d1-500f564d2f4b
Document Type: srp
Title: Draft Revision 6 – August 2015
Source: NUREG-0800
Source URL: https://www.nrc.gov/docs/ML1515/ML15159B011.pdf
Revision Date: 2023-06
Chapter: 7
Section ID: 7
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previously cited regulatory bases and standards in the design of digital computer systems. This BTP has three objectives: • To verify that system timing requirements calculated from the design basis events and other criteria have been allocated to the digital computer portion of the system as appropriate, and have been satisfied in the digital system design and implementation. BTP 7-21-6 Draft Revision 6 – August 2015 • To make the reviewer aware that more extensive efforts are required to verify certain timing design and implementation techniques, such as interrupts. • To assess the technical basis for concluding that the installed plant systems perform as predicted when enlarged from small-scale or partial-system engineering prototypes used in the design phases. B. BRANCH TECHNICAL POSITION 1. Introduction System architecture needs to be considered in evaluating real-time performance. Digital system architecture affects performance because communication between components of the system takes time, and allocation of functions to various system components affects timing. The architecture may also affect timing because an arrangement of otherwise simple components may have unexpected interactions. Requirements for redundancy and diversity may complicate timing analysis because they result in additional components and interconnections. General guidance on evaluating a system’s architecture is given in SRP BTP 7-14. Specific timing requirements may affect system architecture because it may not be possible to get sufficient computational performance for a specific function or group of functions from a single processor, or the locations where functions are performed may be widely separated. Timing requirements may also increase complexity, either by fragmenting the system into multiple processors or by code tuning, which makes the software product harder to understand, verify, or maintain. The digital instrumentation loop often includes the sensor, transmitter,