Document: NUREG-0800
Document ID: 2dffe24e-cd37-4ffc-9c37-16faf25676b1
Document Type: srp
Title: Appendix 7-A
Source: NUREG-0800
Source URL: https://www.nrc.gov/docs/ML0525/ML052500579.pdf
Revision Date: 2023-06
Chapter: 7
Section ID: 7
CFR Part: 
CFR Title: 

Content:
can be verified as correct and timely, or that a prototype system accurately reflects the performance and correctness expected of the actual plant. Some of the criteria described herein may be met by submissions describing a software development process or verification methods that include real-time concerns. Limiting Response Times Limiting response times should be shown to be consistent with safety requirements, e.g., suppress power oscillations, prevent the fuel design limits from being exceeded, prevent a non-coolable core geometry. Setpoint analyses and limiting response times should also be shown to be consistent. The reviewer should verify that limiting response times are acceptable to the Reactor Systems Branch (SRXB), Electrical Engineering Branch (EELB) and the Plant Systems Branch (SPLB) before accepting their use as a basis for timing requirements. Appendix 7-A Rev. 4 — June 1997 BTP HICB-21-5 Digital Computer Timing Requirements Digital computer timing should be shown to be consistent with the limiting response times and the characteristics of the computer hardware, software, and data communications systems. Computer system timing requirements that should be addressed in a software requirements specification are described in BTP HICB-14. Architecture The level of detail in the architectural description should be sufficient that the Staff can determine the number of message delays and computational delays interposed between the sensor and the actuator. An allocation of time-delays to elements of the system and software architecture should be available. In initial design phases (e.g., at the point of design certification application), an estimated allocation of time-delays to elements of the proposed architecture should be available. Subsequent detailed design should develop refined timing allocations down to unit levels in the software architecture. A design should be feasible with currently known methods and representative equipment. Design timing